ath9k_hw_set_txpowerlimit gets an extra boolean parameter that - if set - causes the rate txpower table and the regulatory limit to be calculated and stored, without changing hardware registers.
Unified · Split
| @@ -873,7 +873,7 @@ static int ar5008_hw_process_ini(struct ath_hw *ah, · 872 unmodified lines | ||
| 873 | 873 | channel->max_antenna_gain * 2, |
| 874 | 874 | channel->max_power * 2, |
| 875 | 875 | min((u32) MAX_RATE_POWER, |
| 876 | − (u32) regulatory->power_limit)); | |
| 876 | + (u32) regulatory->power_limit), false); | |
| 877 | 877 | |
| 878 | 878 | /* Write analog registers */ |
| 879 | 879 | if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { |
| @@ -2131,7 +2131,7 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, · 2130 unmodified lines | ||
| 2131 | 2131 | struct ath9k_channel *chan, u16 cfgCtl, |
| 2132 | 2132 | u8 twiceAntennaReduction, |
| 2133 | 2133 | u8 twiceMaxRegulatoryPower, |
| 2134 | − u8 powerLimit) | |
| 2134 | + u8 powerLimit, bool test) | |
| 2135 | 2135 | { |
| 2136 | 2136 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
| 2137 | 2137 | struct ath_common *common = ath9k_hw_common(ah); |
| @@ -2145,7 +2145,16 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, · 7 unmodified lines | ||
| 2145 | 2145 | twiceMaxRegulatoryPower, |
| 2146 | 2146 | powerLimit); |
| 2147 | 2147 | |
| 2148 | − while (i < ar9300RateSize) { | |
| 2148 | + regulatory->max_power_level = 0; | |
| 2149 | + for (i = 0; i < ar9300RateSize; i++) { | |
| 2150 | + if (targetPowerValT2[i] > regulatory->max_power_level) | |
| 2151 | + regulatory->max_power_level = targetPowerValT2[i]; | |
| 2152 | + } | |
| 2153 | + | |
| 2154 | + if (test) | |
| 2155 | + return; | |
| 2156 | + | |
| 2157 | + for (i = 0; i < ar9300RateSize; i++) { | |
| 2149 | 2158 | ath_print(common, ATH_DBG_EEPROM, |
| 2150 | 2159 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); |
| 2151 | 2160 | i++; |
| @@ -2160,9 +2169,6 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, · 8 unmodified lines | ||
| 2160 | 2169 | i++; |
| 2161 | 2170 | } |
| 2162 | 2171 | |
| 2163 | − /* Write target power array to registers */ | |
| 2164 | − ar9003_hw_tx_power_regwrite(ah, targetPowerValT2); | |
| 2165 | − | |
| 2166 | 2172 | /* |
| 2167 | 2173 | * This is the TX power we send back to driver core, |
| 2168 | 2174 | * and it can use to pass to userspace to display our |
| @@ -2181,8 +2187,10 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, · 12 unmodified lines | ||
| 2181 | 2187 | i = ALL_TARGET_HT20_0_8_16; /* ht20 */ |
| 2182 | 2188 | |
| 2183 | 2189 | ah->txpower_limit = targetPowerValT2[i]; |
| 2184 | − regulatory->max_power_level = ratesArray[i]; | |
| 2190 | + regulatory->max_power_level = targetPowerValT2[i]; | |
| 2185 | 2191 | |
| 2192 | + /* Write target power array to registers */ | |
| 2193 | + ar9003_hw_tx_power_regwrite(ah, targetPowerValT2); | |
| 2186 | 2194 | ar9003_hw_calibration_apply(ah, chan->channel); |
| 2187 | 2195 | } |
| 2188 | 2196 | |
| @@ -614,7 +614,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, · 613 unmodified lines | ||
| 614 | 614 | channel->max_antenna_gain * 2, |
| 615 | 615 | channel->max_power * 2, |
| 616 | 616 | min((u32) MAX_RATE_POWER, |
| 617 | − (u32) regulatory->power_limit)); | |
| 617 | + (u32) regulatory->power_limit), false); | |
| 618 | 618 | |
| 619 | 619 | return 0; |
| 620 | 620 | } |
| @@ -680,7 +680,8 @@ struct eeprom_ops { · 679 unmodified lines | ||
| 680 | 680 | void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); |
| 681 | 681 | void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, |
| 682 | 682 | u16 cfgCtl, u8 twiceAntennaReduction, |
| 683 | − u8 twiceMaxRegulatoryPower, u8 powerLimit); | |
| 683 | + u8 twiceMaxRegulatoryPower, u8 powerLimit, | |
| 684 | + bool test); | |
| 684 | 685 | u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); |
| 685 | 686 | }; |
| 686 | 687 | |
| @@ -726,7 +726,7 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah, · 725 unmodified lines | ||
| 726 | 726 | u16 cfgCtl, |
| 727 | 727 | u8 twiceAntennaReduction, |
| 728 | 728 | u8 twiceMaxRegulatoryPower, |
| 729 | − u8 powerLimit) | |
| 729 | + u8 powerLimit, bool test) | |
| 730 | 730 | { |
| 731 | 731 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
| 732 | 732 | struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; |
| @@ -751,15 +751,20 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah, · 18 unmodified lines | ||
| 751 | 751 | |
| 752 | 752 | ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset); |
| 753 | 753 | |
| 754 | + regulatory->max_power_level = 0; | |
| 754 | 755 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { |
| 755 | 756 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); |
| 756 | 757 | if (ratesArray[i] > AR5416_MAX_RATE_POWER) |
| 757 | 758 | ratesArray[i] = AR5416_MAX_RATE_POWER; |
| 759 | + | |
| 760 | + if (ratesArray[i] > regulatory->max_power_level) | |
| 761 | + regulatory->max_power_level = ratesArray[i]; | |
| 758 | 762 | } |
| 759 | 763 | |
| 764 | + if (test) | |
| 765 | + return; | |
| 760 | 766 | |
| 761 | 767 | /* Update regulatory */ |
| 762 | − | |
| 763 | 768 | i = rate6mb; |
| 764 | 769 | if (IS_CHAN_HT40(chan)) |
| 765 | 770 | i = rateHt40_0; |
| @@ -853,7 +853,7 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah, · 852 unmodified lines | ||
| 853 | 853 | struct ath9k_channel *chan, u16 cfgCtl, |
| 854 | 854 | u8 twiceAntennaReduction, |
| 855 | 855 | u8 twiceMaxRegulatoryPower, |
| 856 | − u8 powerLimit) | |
| 856 | + u8 powerLimit, bool test) | |
| 857 | 857 | { |
| 858 | 858 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
| 859 | 859 | struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; |
| @@ -877,12 +877,26 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah, · 17 unmodified lines | ||
| 877 | 877 | |
| 878 | 878 | ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset); |
| 879 | 879 | |
| 880 | + regulatory->max_power_level = 0; | |
| 880 | 881 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { |
| 881 | 882 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); |
| 882 | 883 | if (ratesArray[i] > AR9287_MAX_RATE_POWER) |
| 883 | 884 | ratesArray[i] = AR9287_MAX_RATE_POWER; |
| 885 | + | |
| 886 | + if (ratesArray[i] > regulatory->max_power_level) | |
| 887 | + regulatory->max_power_level = ratesArray[i]; | |
| 884 | 888 | } |
| 885 | 889 | |
| 890 | + if (test) | |
| 891 | + return; | |
| 892 | + | |
| 893 | + if (IS_CHAN_2GHZ(chan)) | |
| 894 | + i = rate1l; | |
| 895 | + else | |
| 896 | + i = rate6mb; | |
| 897 | + | |
| 898 | + regulatory->max_power_level = ratesArray[i]; | |
| 899 | + | |
| 886 | 900 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 887 | 901 | for (i = 0; i < Ar5416RateSize; i++) |
| 888 | 902 | ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2; |
| @@ -971,17 +985,6 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah, · 82 unmodified lines | ||
| 971 | 985 | | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) |
| 972 | 986 | | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); |
| 973 | 987 | } |
| 974 | − | |
| 975 | − if (IS_CHAN_2GHZ(chan)) | |
| 976 | − i = rate1l; | |
| 977 | − else | |
| 978 | − i = rate6mb; | |
| 979 | − | |
| 980 | − if (AR_SREV_9280_20_OR_LATER(ah)) | |
| 981 | − regulatory->max_power_level = | |
| 982 | − ratesArray[i] + AR9287_PWR_TABLE_OFFSET_DB * 2; | |
| 983 | − else | |
| 984 | − regulatory->max_power_level = ratesArray[i]; | |
| 985 | 988 | } |
| 986 | 989 | |
| 987 | 990 | static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah, |
| @@ -1258,7 +1258,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah, · 1257 unmodified lines | ||
| 1258 | 1258 | u16 cfgCtl, |
| 1259 | 1259 | u8 twiceAntennaReduction, |
| 1260 | 1260 | u8 twiceMaxRegulatoryPower, |
| 1261 | − u8 powerLimit) | |
| 1261 | + u8 powerLimit, bool test) | |
| 1262 | 1262 | { |
| 1263 | 1263 | #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta) |
| 1264 | 1264 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
| @@ -1285,12 +1285,44 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah, · 20 unmodified lines | ||
| 1285 | 1285 | |
| 1286 | 1286 | ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset); |
| 1287 | 1287 | |
| 1288 | + regulatory->max_power_level = 0; | |
| 1288 | 1289 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { |
| 1289 | 1290 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); |
| 1290 | 1291 | if (ratesArray[i] > AR5416_MAX_RATE_POWER) |
| 1291 | 1292 | ratesArray[i] = AR5416_MAX_RATE_POWER; |
| 1293 | + if (ratesArray[i] > regulatory->max_power_level) | |
| 1294 | + regulatory->max_power_level = ratesArray[i]; | |
| 1292 | 1295 | } |
| 1293 | 1296 | |
| 1297 | + if (!test) { | |
| 1298 | + i = rate6mb; | |
| 1299 | + | |
| 1300 | + if (IS_CHAN_HT40(chan)) | |
| 1301 | + i = rateHt40_0; | |
| 1302 | + else if (IS_CHAN_HT20(chan)) | |
| 1303 | + i = rateHt20_0; | |
| 1304 | + | |
| 1305 | + regulatory->max_power_level = ratesArray[i]; | |
| 1306 | + } | |
| 1307 | + | |
| 1308 | + switch(ar5416_get_ntxchains(ah->txchainmask)) { | |
| 1309 | + case 1: | |
| 1310 | + break; | |
| 1311 | + case 2: | |
| 1312 | + regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN; | |
| 1313 | + break; | |
| 1314 | + case 3: | |
| 1315 | + regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; | |
| 1316 | + break; | |
| 1317 | + default: | |
| 1318 | + ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM, | |
| 1319 | + "Invalid chainmask configuration\n"); | |
| 1320 | + break; | |
| 1321 | + } | |
| 1322 | + | |
| 1323 | + if (test) | |
| 1324 | + return; | |
| 1325 | + | |
| 1294 | 1326 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 1295 | 1327 | for (i = 0; i < Ar5416RateSize; i++) { |
| 1296 | 1328 | int8_t pwr_table_offset; |
| @@ -1387,34 +1419,6 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah, · 90 unmodified lines | ||
| 1387 | 1419 | REG_WRITE(ah, AR_PHY_POWER_TX_SUB, |
| 1388 | 1420 | ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6) |
| 1389 | 1421 | | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)); |
| 1390 | − | |
| 1391 | − i = rate6mb; | |
| 1392 | − | |
| 1393 | − if (IS_CHAN_HT40(chan)) | |
| 1394 | − i = rateHt40_0; | |
| 1395 | − else if (IS_CHAN_HT20(chan)) | |
| 1396 | − i = rateHt20_0; | |
| 1397 | − | |
| 1398 | − if (AR_SREV_9280_20_OR_LATER(ah)) | |
| 1399 | − regulatory->max_power_level = | |
| 1400 | − ratesArray[i] + AR5416_PWR_TABLE_OFFSET_DB * 2; | |
| 1401 | − else | |
| 1402 | − regulatory->max_power_level = ratesArray[i]; | |
| 1403 | − | |
| 1404 | − switch(ar5416_get_ntxchains(ah->txchainmask)) { | |
| 1405 | − case 1: | |
| 1406 | − break; | |
| 1407 | − case 2: | |
| 1408 | − regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN; | |
| 1409 | − break; | |
| 1410 | − case 3: | |
| 1411 | − regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; | |
| 1412 | − break; | |
| 1413 | − default: | |
| 1414 | − ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM, | |
| 1415 | − "Invalid chainmask configuration\n"); | |
| 1416 | − break; | |
| 1417 | − } | |
| 1418 | 1422 | } |
| 1419 | 1423 | |
| 1420 | 1424 | static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah, |
| @@ -29,7 +29,7 @@ static void ath_update_txpow(struct ath9k_htc_priv *priv) · 28 unmodified lines | ||
| 29 | 29 | struct ath_hw *ah = priv->ah; |
| 30 | 30 | |
| 31 | 31 | if (priv->curtxpow != priv->txpowlimit) { |
| 32 | − ath9k_hw_set_txpowerlimit(ah, priv->txpowlimit); | |
| 32 | + ath9k_hw_set_txpowerlimit(ah, priv->txpowlimit, false); | |
| 33 | 33 | /* read back in case value is clamped */ |
| 34 | 34 | priv->curtxpow = ath9k_hw_regulatory(ah)->power_limit; |
| 35 | 35 | } |
| @@ -1166,7 +1166,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah, · 1165 unmodified lines | ||
| 1166 | 1166 | channel->max_antenna_gain * 2, |
| 1167 | 1167 | channel->max_power * 2, |
| 1168 | 1168 | min((u32) MAX_RATE_POWER, |
| 1169 | − (u32) regulatory->power_limit)); | |
| 1169 | + (u32) regulatory->power_limit), false); | |
| 1170 | 1170 | |
| 1171 | 1171 | ath9k_hw_rfbus_done(ah); |
| 1172 | 1172 | |
| @@ -2165,7 +2165,7 @@ bool ath9k_hw_disable(struct ath_hw *ah) · 992 unmodified lines | ||
| 2165 | 2165 | } |
| 2166 | 2166 | EXPORT_SYMBOL(ath9k_hw_disable); |
| 2167 | 2167 | |
| 2168 | −void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) | |
| 2168 | +void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) | |
| 2169 | 2169 | { |
| 2170 | 2170 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
| 2171 | 2171 | struct ath9k_channel *chan = ah->curchan; |
| @@ -2178,7 +2178,7 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) · 6 unmodified lines | ||
| 2178 | 2178 | channel->max_antenna_gain * 2, |
| 2179 | 2179 | channel->max_power * 2, |
| 2180 | 2180 | min((u32) MAX_RATE_POWER, |
| 2181 | − (u32) regulatory->power_limit)); | |
| 2181 | + (u32) regulatory->power_limit), test); | |
| 2182 | 2182 | } |
| 2183 | 2183 | EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); |
| 2184 | 2184 | |
| @@ -860,7 +860,7 @@ u32 ath9k_hw_getrxfilter(struct ath_hw *ah); · 859 unmodified lines | ||
| 860 | 860 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); |
| 861 | 861 | bool ath9k_hw_phy_disable(struct ath_hw *ah); |
| 862 | 862 | bool ath9k_hw_disable(struct ath_hw *ah); |
| 863 | −void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit); | |
| 863 | +void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); | |
| 864 | 864 | void ath9k_hw_setopmode(struct ath_hw *ah); |
| 865 | 865 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); |
| 866 | 866 | void ath9k_hw_setbssidmask(struct ath_hw *ah); |
| @@ -23,7 +23,7 @@ static void ath_update_txpow(struct ath_softc *sc) · 22 unmodified lines | ||
| 23 | 23 | struct ath_hw *ah = sc->sc_ah; |
| 24 | 24 | |
| 25 | 25 | if (sc->curtxpow != sc->config.txpowlimit) { |
| 26 | − ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
| 26 | + ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false); | |
| 27 | 27 | /* read back in case value is clamped */ |
| 28 | 28 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; |
| 29 | 29 | } |