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PCI: Decode PCIe 32 GT/s link speed

PCIe r5.0, sec 7.5.3.18, defines a new 32.0 GT/s bit in the Supported Link Speeds Vector of Link Capabilities 2. Decode this new speed. This does not affect the speed of the link, which should be negotiated automatically by the hardware; it only adds decoding when showing the speed to the user. Previously, reading the speed of a link operating at this speed showed "Unknown speed" instead of "32.0 GT/s".

Gustavo Pimentel committed 7 years ago

Commit de76cda1 parent 2d2f4276 files · +13 −2Browse files

Unified · Split

6 files
  1. drivers/pci/pci-sysfs.c +3 −0
  2. drivers/pci/pci.c +3 −1
  3. drivers/pci/probe.c +1 −1
  4. drivers/pci/slot.c +1 −0
  5. include/linux/pci.h +1 −0
  6. include/uapi/linux/pci_regs.h +4 −0
drivers/pci/pci-sysfs.c+3−0
@@ -182,6 +182,9 @@ static ssize_t current_link_speed_show(struct device *dev, · 181 unmodified lines
182 return -EINVAL;182 return -EINVAL;
183 183
184 switch (linkstat & PCI_EXP_LNKSTA_CLS) {184 switch (linkstat & PCI_EXP_LNKSTA_CLS) {
185 case PCI_EXP_LNKSTA_CLS_32_0GB:
186 speed = "32 GT/s";
187 break;
185 case PCI_EXP_LNKSTA_CLS_16_0GB:188 case PCI_EXP_LNKSTA_CLS_16_0GB:
186 speed = "16 GT/s";189 speed = "16 GT/s";
187 break;190 break;
drivers/pci/pci.c+3−1
@@ -5621,7 +5621,9 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) · 5620 unmodified lines
5621 */5621 */
5622 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);5622 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5623 if (lnkcap2) { /* PCIe r3.0-compliant */5623 if (lnkcap2) { /* PCIe r3.0-compliant */
5624 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)5624 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB)
5625 return PCIE_SPEED_32_0GT;
5626 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
5625 return PCIE_SPEED_16_0GT;5627 return PCIE_SPEED_16_0GT;
5626 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)5628 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
5627 return PCIE_SPEED_8_0GT;5629 return PCIE_SPEED_8_0GT;
drivers/pci/probe.c+1−1
@@ -668,7 +668,7 @@ const unsigned char pcie_link_speed[] = { · 667 unmodified lines
668 PCIE_SPEED_5_0GT, /* 2 */668 PCIE_SPEED_5_0GT, /* 2 */
669 PCIE_SPEED_8_0GT, /* 3 */669 PCIE_SPEED_8_0GT, /* 3 */
670 PCIE_SPEED_16_0GT, /* 4 */670 PCIE_SPEED_16_0GT, /* 4 */
671 PCI_SPEED_UNKNOWN, /* 5 */671 PCIE_SPEED_32_0GT, /* 5 */
672 PCI_SPEED_UNKNOWN, /* 6 */672 PCI_SPEED_UNKNOWN, /* 6 */
673 PCI_SPEED_UNKNOWN, /* 7 */673 PCI_SPEED_UNKNOWN, /* 7 */
674 PCI_SPEED_UNKNOWN, /* 8 */674 PCI_SPEED_UNKNOWN, /* 8 */
drivers/pci/slot.c+1−0
@@ -75,6 +75,7 @@ static const char *pci_bus_speed_strings[] = { · 74 unmodified lines
75 "5.0 GT/s PCIe", /* 0x15 */75 "5.0 GT/s PCIe", /* 0x15 */
76 "8.0 GT/s PCIe", /* 0x16 */76 "8.0 GT/s PCIe", /* 0x16 */
77 "16.0 GT/s PCIe", /* 0x17 */77 "16.0 GT/s PCIe", /* 0x17 */
78 "32.0 GT/s PCIe", /* 0x18 */
78};79};
79 80
80static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf)81static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf)
include/linux/pci.h+1−0
@@ -258,6 +258,7 @@ enum pci_bus_speed { · 257 unmodified lines
258 PCIE_SPEED_5_0GT = 0x15,258 PCIE_SPEED_5_0GT = 0x15,
259 PCIE_SPEED_8_0GT = 0x16,259 PCIE_SPEED_8_0GT = 0x16,
260 PCIE_SPEED_16_0GT = 0x17,260 PCIE_SPEED_16_0GT = 0x17,
261 PCIE_SPEED_32_0GT = 0x18,
261 PCI_SPEED_UNKNOWN = 0xff,262 PCI_SPEED_UNKNOWN = 0xff,
262};263};
263 264
include/uapi/linux/pci_regs.h+4−0
@@ -528,6 +528,7 @@ · 527 unmodified lines
528#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */528#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
529#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */529#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
530#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */530#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
531#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
531#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */532#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
532#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */533#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
533#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */534#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
@@ -556,6 +557,7 @@ · 22 unmodified lines
556#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */557#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
557#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */558#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
558#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */559#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
560#define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */
559#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */561#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
560#define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */562#define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */
561#define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */563#define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */
@@ -661,6 +663,7 @@ · 99 unmodified lines
661#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */663#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
662#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */664#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
663#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */665#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
666#define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */
664#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */667#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
665#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */668#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
666#define PCI_EXP_LNKCTL2_TLS 0x000f669#define PCI_EXP_LNKCTL2_TLS 0x000f
@@ -668,6 +671,7 @@ · 1 unmodified line
668#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */671#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
669#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */672#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
670#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */673#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
674#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
671#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */675#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
672#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */676#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
673#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */677#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */