lael-labs/linux

.clang-format+21−4

   - 'bio_for_each_segment_all'
   - 'bio_list_for_each'
   - 'bip_for_each_vec'
+  - 'bitmap_for_each_clear_region'
+  - 'bitmap_for_each_set_region'
   - 'blkg_for_each_descendant_post'
   - 'blkg_for_each_descendant_pre'
   - 'blk_queue_for_each_rl'
   - 'drm_client_for_each_connector_iter'
   - 'drm_client_for_each_modeset'
   - 'drm_connector_for_each_possible_encoder'
+  - 'drm_for_each_bridge_in_chain'
   - 'drm_for_each_connector_iter'
   - 'drm_for_each_crtc'
   - 'drm_for_each_encoder'
   - 'for_each_bio'
   - 'for_each_board_func_rsrc'
   - 'for_each_bvec'
+  - 'for_each_card_auxs'
+  - 'for_each_card_auxs_safe'
   - 'for_each_card_components'
-  - 'for_each_card_links'
+  - 'for_each_card_pre_auxs'
-  - 'for_each_card_links_safe'
   - 'for_each_card_prelinks'
   - 'for_each_card_rtds'
   - 'for_each_card_rtds_safe'
   - 'for_each_dpcm_fe'
   - 'for_each_drhd_unit'
   - 'for_each_dss_dev'
+  - 'for_each_efi_handle'
   - 'for_each_efi_memory_desc'
   - 'for_each_efi_memory_desc_in_map'
   - 'for_each_element'
   - 'for_each_lru'
   - 'for_each_matching_node'
   - 'for_each_matching_node_and_match'
+  - 'for_each_member'
   - 'for_each_memblock'
   - 'for_each_memblock_type'
   - 'for_each_memcg_cache_index'
   - 'for_each_msi_entry'
   - 'for_each_msi_entry_safe'
   - 'for_each_net'
+  - 'for_each_net_continue_reverse'
   - 'for_each_netdev'
   - 'for_each_netdev_continue'
   - 'for_each_netdev_continue_rcu'
+  - 'for_each_netdev_continue_reverse'
   - 'for_each_netdev_feature'
   - 'for_each_netdev_in_bond_rcu'
   - 'for_each_netdev_rcu'
   - 'for_each_reserved_mem_region'
   - 'for_each_rtd_codec_dai'
   - 'for_each_rtd_codec_dai_rollback'
-  - 'for_each_rtdcom'
+  - 'for_each_rtd_components'
-  - 'for_each_rtdcom_safe'
   - 'for_each_set_bit'
   - 'for_each_set_bit_from'
+  - 'for_each_set_clump8'
   - 'for_each_sg'
   - 'for_each_sg_dma_page'
   - 'for_each_sg_page'
   - 'for_each_subelement_id'
   - '__for_each_thread'
   - 'for_each_thread'
+  - 'for_each_wakeup_source'
   - 'for_each_zone'
   - 'for_each_zone_zonelist'
   - 'for_each_zone_zonelist_nodemask'
   - 'list_for_each'
   - 'list_for_each_codec'
   - 'list_for_each_codec_safe'
+  - 'list_for_each_continue'
   - 'list_for_each_entry'
   - 'list_for_each_entry_continue'
   - 'list_for_each_entry_continue_rcu'
   - 'llist_for_each_entry'
   - 'llist_for_each_entry_safe'
   - 'llist_for_each_safe'
+  - 'mci_for_each_dimm'
   - 'media_device_for_each_entity'
   - 'media_device_for_each_intf'
   - 'media_device_for_each_link'
   - 'virtio_device_for_each_vq'
   - 'xa_for_each'
   - 'xa_for_each_marked'
+  - 'xa_for_each_range'
   - 'xa_for_each_start'
   - 'xas_for_each'
   - 'xas_for_each_conflict'
   - 'xas_for_each_marked'
+  - 'xbc_array_for_each_value'
+  - 'xbc_for_each_key_value'
+  - 'xbc_node_for_each_array_value'
+  - 'xbc_node_for_each_child'
+  - 'xbc_node_for_each_key_value'
   - 'zorro_for_each_dev'
 #IncludeBlocks: Preserve # Unknown to clang-format-5.0

CREDITS+5−0

@@ -567,6 +567,11 @@ D: Original author of Amiga FFS filesystem · 566 unmodified lines
567	S: Orlando, Florida	567	S: Orlando, Florida
568	S: USA	568	S: USA
569		569
		570	N: Paul Burton
		571	E: paulburton@kernel.org
		572	W: https://pburton.com
		573	D: MIPS maintainer 2018-2020
		574
570	N: Lennert Buytenhek	575	N: Lennert Buytenhek
571	E: kernel@wantstofly.org	576	E: kernel@wantstofly.org
572	D: Original (2.4) rewrite of the ethernet bridging code	577	D: Original (2.4) rewrite of the ethernet bridging code

Documentation/admin-guide/acpi/fan_performance_states.rst+2−2

@@ -18,7 +18,7 @@ may look as follows:: · 17 unmodified lines
18		18
19	$ ls -l /sys/bus/acpi/devices/INT3404:00/	19	$ ls -l /sys/bus/acpi/devices/INT3404:00/
20	total 0	20	total 0
21	...	21	...
22	-r--r--r-- 1 root root 4096 Dec 13 20:38 state0	22	-r--r--r-- 1 root root 4096 Dec 13 20:38 state0
23	-r--r--r-- 1 root root 4096 Dec 13 20:38 state1	23	-r--r--r-- 1 root root 4096 Dec 13 20:38 state1
24	-r--r--r-- 1 root root 4096 Dec 13 20:38 state10	24	-r--r--r-- 1 root root 4096 Dec 13 20:38 state10
@@ -38,7 +38,7 @@ where each of the "state*" files represents one performance state of the fan · 13 unmodified lines
38	and contains a colon-separated list of 5 integer numbers (fields) with the	38	and contains a colon-separated list of 5 integer numbers (fields) with the
39	following interpretation::	39	following interpretation::
40		40
41	control_percent:trip_point_index:speed_rpm:noise_level_mdb:power_mw	41	control_percent:trip_point_index:speed_rpm:noise_level_mdb:power_mw
42		42
43	* ``control_percent``: The percent value to be used to set the fan speed to a	43	* ``control_percent``: The percent value to be used to set the fan speed to a
44	specific level using the _FSL object (0-100).	44	specific level using the _FSL object (0-100).

Documentation/admin-guide/bootconfig.rst+31−3

@@ -62,6 +62,30 @@ Or more shorter, written as following:: · 61 unmodified lines
62	In both styles, same key words are automatically merged when parsing it	62	In both styles, same key words are automatically merged when parsing it
63	at boot time. So you can append similar trees or key-values.	63	at boot time. So you can append similar trees or key-values.
64		64
		65	Same-key Values
		66	---------------
		67
		68	It is prohibited that two or more values or arrays share a same-key.
		69	For example,::
		70
		71	foo = bar, baz
		72	foo = qux # !ERROR! we can not re-define same key
		73
		74	If you want to append the value to existing key as an array member,
		75	you can use ``+=`` operator. For example::
		76
		77	foo = bar, baz
		78	foo += qux
		79
		80	In this case, the key ``foo`` has ``bar``, ``baz`` and ``qux``.
		81
		82	However, a sub-key and a value can not co-exist under a parent key.
		83	For example, following config is NOT allowed.::
		84
		85	foo = value1
		86	foo.bar = value2 # !ERROR! subkey "bar" and value "value1" can NOT co-exist
		87
		88
65	Comments	89	Comments
66	--------	90	--------
67		91
@@ -102,9 +126,13 @@ Boot Kernel With a Boot Config · 34 unmodified lines
102	==============================	126	==============================
103		127
104	Since the boot configuration file is loaded with initrd, it will be added	128	Since the boot configuration file is loaded with initrd, it will be added
105	to the end of the initrd (initramfs) image file. The Linux kernel decodes	129	to the end of the initrd (initramfs) image file with size, checksum and
106	the last part of the initrd image in memory to get the boot configuration	130	12-byte magic word as below.
107	data.	131
		132	[initrd][bootconfig][size(u32)][checksum(u32)][#BOOTCONFIG\n]
		133
		134	The Linux kernel decodes the last part of the initrd image in memory to
		135	get the boot configuration data.
108	Because of this "piggyback" method, there is no need to change or	136	Because of this "piggyback" method, there is no need to change or
109	update the boot loader and the kernel image itself.	137	update the boot loader and the kernel image itself.
110		138

Documentation/admin-guide/kernel-parameters.txt+4−0

 			dynamic table installation which will install SSDT
 			tables to /sys/firmware/acpi/tables/dynamic.
+	acpi_no_watchdog	[HW,ACPI,WDT]
+			Ignore the ACPI-based watchdog interface (WDAT) and let
+			a native driver control the watchdog device instead.
 	acpi_rsdp=	[ACPI,EFI,KEXEC]
 			Pass the RSDP address to the kernel, mostly used
 			on machines running EFI runtime service to boot the

Documentation/arm64/silicon-errata.rst+2−0

 +----------------+-----------------+-----------------+-----------------------------+
 | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154        |
 +----------------+-----------------+-----------------+-----------------------------+
+| Cavium         | ThunderX GICv3  | #38539          | N/A                         |
++----------------+-----------------+-----------------+-----------------------------+
 | Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456        |
 +----------------+-----------------+-----------------+-----------------------------+
 | Cavium         | ThunderX Core   | #30115          | CAVIUM_ERRATUM_30115        |

Documentation/dev-tools/kunit/usage.rst+1−0

@@ -551,6 +551,7 @@ options to your ``.config``: · 550 unmodified lines
551	Once the kernel is built and installed, a simple	551	Once the kernel is built and installed, a simple
552		552
553	.. code-block:: bash	553	.. code-block:: bash
		554
554	modprobe example-test	555	modprobe example-test
555		556
556	...will run the tests.	557	...will run the tests.

Documentation/devicetree/bindings/arm/arm,scmi.txt+1−1

@@ -102,7 +102,7 @@ Required sub-node properties: · 101 unmodified lines
102	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt	102	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
103	[2] Documentation/devicetree/bindings/power/power-domain.yaml	103	[2] Documentation/devicetree/bindings/power/power-domain.yaml
104	[3] Documentation/devicetree/bindings/thermal/thermal.txt	104	[3] Documentation/devicetree/bindings/thermal/thermal.txt
105	[4] Documentation/devicetree/bindings/sram/sram.txt	105	[4] Documentation/devicetree/bindings/sram/sram.yaml
106	[5] Documentation/devicetree/bindings/reset/reset.txt	106	[5] Documentation/devicetree/bindings/reset/reset.txt
107		107
108	Example:	108	Example:

Documentation/devicetree/bindings/arm/arm,scpi.txt+1−1

@@ -109,7 +109,7 @@ Required properties: · 108 unmodified lines
109	[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html	109	[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
110	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt	110	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
111	[2] Documentation/devicetree/bindings/thermal/thermal.txt	111	[2] Documentation/devicetree/bindings/thermal/thermal.txt
112	[3] Documentation/devicetree/bindings/sram/sram.txt	112	[3] Documentation/devicetree/bindings/sram/sram.yaml
113	[4] Documentation/devicetree/bindings/power/power-domain.yaml	113	[4] Documentation/devicetree/bindings/power/power-domain.yaml
114		114
115	Example:	115	Example:

Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt+1−1

@@ -62,7 +62,7 @@ Timer node: · 61 unmodified lines
62		62
63	Syscon reboot node:	63	Syscon reboot node:
64		64
65	See Documentation/devicetree/bindings/power/reset/syscon-reboot.txt for the	65	See Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml for the
66	detailed list of properties, the two values defined below are specific to the	66	detailed list of properties, the two values defined below are specific to the
67	BCM6328-style timer:	67	BCM6328-style timer:
68		68

Documentation/devicetree/bindings/arm/cpus.yaml+1−1

@@ -216,7 +216,7 @@ properties: · 215 unmodified lines
216	$ref: '/schemas/types.yaml#/definitions/phandle-array'	216	$ref: '/schemas/types.yaml#/definitions/phandle-array'
217	description: \|	217	description: \|
218	List of phandles to idle state nodes supported	218	List of phandles to idle state nodes supported
219	by this cpu (see ./idle-states.txt).	219	by this cpu (see ./idle-states.yaml).
220		220
221	capacity-dmips-mhz:	221	capacity-dmips-mhz:
222	$ref: '/schemas/types.yaml#/definitions/uint32'	222	$ref: '/schemas/types.yaml#/definitions/uint32'

Documentation/devicetree/bindings/arm/fsl.yaml+1−1

@@ -160,7 +160,7 @@ properties: · 159 unmodified lines
160	items:	160	items:
161	- enum:	161	- enum:
162	- armadeus,imx6dl-apf6 # APF6 (Solo) SoM	162	- armadeus,imx6dl-apf6 # APF6 (Solo) SoM
163	- armadeus,imx6dl-apf6dldev # APF6 (Solo) SoM on APF6Dev board	163	- armadeus,imx6dl-apf6dev # APF6 (Solo) SoM on APF6Dev board
164	- eckelmann,imx6dl-ci4x10	164	- eckelmann,imx6dl-ci4x10
165	- emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM	165	- emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM
166	- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base	166	- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base

Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt+1−1

@@ -1,7 +1,7 @@
1	* Hisilicon Hi3519 System Controller Block	1	* Hisilicon Hi3519 System Controller Block
2		2
3	This bindings use the following binding:	3	This bindings use the following binding:
4	Documentation/devicetree/bindings/mfd/syscon.txt	4	Documentation/devicetree/bindings/mfd/syscon.yaml
5		5
6	Required properties:	6	Required properties:
7	- compatible: "hisilicon,hi3519-sysctrl".	7	- compatible: "hisilicon,hi3519-sysctrl".

Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt+1−1

@@ -81,4 +81,4 @@ Example: · 80 unmodified lines
81	};	81	};
82	};	82	};
83		83
84	[1]. Documentation/devicetree/bindings/arm/idle-states.txt	84	[1]. Documentation/devicetree/bindings/arm/idle-states.yaml

Documentation/devicetree/bindings/arm/omap/mpu.txt+1−1

@@ -17,7 +17,7 @@ am335x and am437x only: · 16 unmodified lines
17	- pm-sram: Phandles to ocmcram nodes to be used for power management.	17	- pm-sram: Phandles to ocmcram nodes to be used for power management.
18	First should be type 'protect-exec' for the driver to use to copy	18	First should be type 'protect-exec' for the driver to use to copy
19	and run PM functions, second should be regular pool to be used for	19	and run PM functions, second should be regular pool to be used for
20	data region for code. See Documentation/devicetree/bindings/sram/sram.txt	20	data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
21	for more details.	21	for more details.
22		22
23	Examples:	23	Examples:

Documentation/devicetree/bindings/arm/psci.yaml+17−19

       bindings in [1]) must specify this property.
       [1] Kernel documentation - ARM idle states bindings
-        Documentation/devicetree/bindings/arm/idle-states.txt
+        Documentation/devicetree/bindings/arm/idle-states.yaml
-  "#power-domain-cells":
-    description:
-      The number of cells in a PM domain specifier as per binding in [3].
-      Must be 0 as to represent a single PM domain.
+patternProperties:
+  "^power-domain-":
+    allOf:
+      - $ref: "../power/power-domain.yaml#"
+    type: object
+    description: |
       ARM systems can have multiple cores, sometimes in an hierarchical
       arrangement. This often, but not always, maps directly to the processor
       power topology of the system. Individual nodes in a topology have their
       helps to implement support for OSI mode and OS implementations may choose
       to mandate it.
-      [3] Documentation/devicetree/bindings/power/power_domain.txt
+      [3] Documentation/devicetree/bindings/power/power-domain.yaml
-      [4] Documentation/devicetree/bindings/power/domain-idle-state.txt
+      [4] Documentation/devicetree/bindings/power/domain-idle-state.yaml
-  power-domains:
-    $ref: '/schemas/types.yaml#/definitions/phandle-array'
-    description:
-      List of phandles and PM domain specifiers, as defined by bindings of the
-      PM domain provider.
 required:
   - compatible
       CPU0: cpu@0 {
         device_type = "cpu";
-        compatible = "arm,cortex-a53", "arm,armv8";
+        compatible = "arm,cortex-a53";
         reg = <0x0>;
         enable-method = "psci";
         power-domains = <&CPU_PD0>;
       CPU1: cpu@1 {
         device_type = "cpu";
-        compatible = "arm,cortex-a57", "arm,armv8";
+        compatible = "arm,cortex-a53";
         reg = <0x100>;
         enable-method = "psci";
         power-domains = <&CPU_PD1>;
           exit-latency-us = <10>;
           min-residency-us = <100>;
         };
+      };
+      domain-idle-states {
         CLUSTER_RET: cluster-retention {
           compatible = "domain-idle-state";
       compatible = "arm,psci-1.0";
       method = "smc";
-      CPU_PD0: cpu-pd0 {
+      CPU_PD0: power-domain-cpu0 {
         #power-domain-cells = <0>;
         domain-idle-states = <&CPU_PWRDN>;
         power-domains = <&CLUSTER_PD>;
       };
-      CPU_PD1: cpu-pd1 {
+      CPU_PD1: power-domain-cpu1 {
         #power-domain-cells = <0>;
         domain-idle-states =  <&CPU_PWRDN>;
         power-domains = <&CLUSTER_PD>;
       };
-      CLUSTER_PD: cluster-pd {
+      CLUSTER_PD: power-domain-cluster {
         #power-domain-cells = <0>;
         domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
       };

Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml+1−1

@@ -52,7 +52,7 @@ required: · 51 unmodified lines
52		52
53	examples:	53	examples:
54	- \|	54	- \|
55	mlahb: ahb {	55	mlahb: ahb@38000000 {
56	compatible = "st,mlahb", "simple-bus";	56	compatible = "st,mlahb", "simple-bus";
57	#address-cells = <1>;	57	#address-cells = <1>;
58	#size-cells = <1>;	58	#size-cells = <1>;

Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml+0−1

@@ -70,7 +70,6 @@ examples: · 69 unmodified lines
70	#size-cells = <0>;	70	#size-cells = <0>;
71		71
72	pmic@3e3 {	72	pmic@3e3 {
73	compatible = "...";
74	reg = <0x3e3>;	73	reg = <0x3e3>;
75		74
76	/* ... */	75	/* ... */

Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-osc-clk.yaml+1−1

@@ -40,7 +40,7 @@ additionalProperties: false · 39 unmodified lines
40		40
41	examples:	41	examples:
42	- \|	42	- \|
43	osc24M: clk@01c20050 {	43	osc24M: clk@1c20050 {
44	#clock-cells = <0>;	44	#clock-cells = <0>;
45	compatible = "allwinner,sun4i-a10-osc-clk";	45	compatible = "allwinner,sun4i-a10-osc-clk";
46	reg = <0x01c20050 0x4>;	46	reg = <0x01c20050 0x4>;

Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-gt-clk.yaml+1−1

@@ -41,7 +41,7 @@ additionalProperties: false · 40 unmodified lines
41		41
42	examples:	42	examples:
43	- \|	43	- \|
44	clk@0600005c {	44	clk@600005c {
45	#clock-cells = <0>;	45	#clock-cells = <0>;
46	compatible = "allwinner,sun9i-a80-gt-clk";	46	compatible = "allwinner,sun9i-a80-gt-clk";
47	reg = <0x0600005c 0x4>;	47	reg = <0x0600005c 0x4>;

Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml+1−1

@@ -42,7 +42,7 @@ properties: · 41 unmodified lines
42	be part of GCC and hence the TSENS properties can also be part	42	be part of GCC and hence the TSENS properties can also be part
43	of the GCC/clock-controller node.	43	of the GCC/clock-controller node.
44	For more details on the TSENS properties please refer	44	For more details on the TSENS properties please refer
45	Documentation/devicetree/bindings/thermal/qcom-tsens.txt	45	Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
46		46
47	nvmem-cell-names:	47	nvmem-cell-names:
48	minItems: 1	48	minItems: 1

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tv-encoder.yaml+1−5

         resets = <&tcon_ch0_clk 0>;
         port {
-            #address-cells = <1>;
+            tve0_in_tcon0: endpoint {
-            #size-cells = <0>;
-            tve0_in_tcon0: endpoint@0 {
-                reg = <0>;
                 remote-endpoint = <&tcon0_out_tve0>;
             };
         };

Documentation/devicetree/bindings/display/bridge/anx6345.yaml+2−8

           #size-cells = <0>;
           anx6345_in: port@0 {
-            #address-cells = <1>;
-            #size-cells = <0>;
             reg = <0>;
-            anx6345_in_tcon0: endpoint@0 {
+            anx6345_in_tcon0: endpoint {
-              reg = <0>;
               remote-endpoint = <&tcon0_out_anx6345>;
             };
           };
           anx6345_out: port@1 {
-            #address-cells = <1>;
-            #size-cells = <0>;
             reg = <1>;
-            anx6345_out_panel: endpoint@0 {
+            anx6345_out_panel: endpoint {
-              reg = <0>;
               remote-endpoint = <&panel_in_edp>;
             };
           };

Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml+2−0

@@ -37,6 +37,8 @@ examples: · 36 unmodified lines
37	dsi@ff450000 {	37	dsi@ff450000 {
38	#address-cells = <1>;	38	#address-cells = <1>;
39	#size-cells = <0>;	39	#size-cells = <0>;
		40	reg = <0xff450000 0x1000>;
		41
40	panel@0 {	42	panel@0 {
41	compatible = "leadtek,ltk500hd1829";	43	compatible = "leadtek,ltk500hd1829";
42	reg = <0>;	44	reg = <0>;

Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml+2−0

@@ -37,6 +37,8 @@ examples: · 36 unmodified lines
37	dsi@ff450000 {	37	dsi@ff450000 {
38	#address-cells = <1>;	38	#address-cells = <1>;
39	#size-cells = <0>;	39	#size-cells = <0>;
		40	reg = <0xff450000 0x1000>;
		41
40	panel@0 {	42	panel@0 {
41	compatible = "xinpeng,xpp055c272";	43	compatible = "xinpeng,xpp055c272";
42	reg = <0>;	44	reg = <0>;

Documentation/devicetree/bindings/display/simple-framebuffer.yaml+1−5

       };
     };
-    soc@1c00000 {
+    lcdc0: lcdc { };
-      lcdc0: lcdc@1c0c000 {
-        compatible = "allwinner,sun4i-a10-lcdc";
-      };
-    };
 ...

Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt+1−1

@@ -37,7 +37,7 @@ Optional nodes: · 36 unmodified lines
37	supports a single port with a single endpoint.	37	supports a single port with a single endpoint.
38		38
39	- See also Documentation/devicetree/bindings/display/tilcdc/panel.txt and	39	- See also Documentation/devicetree/bindings/display/tilcdc/panel.txt and
40	Documentation/devicetree/bindings/display/tilcdc/tfp410.txt for connecting	40	Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt for connecting
41	tfp410 DVI encoder or lcd panel to lcdc	41	tfp410 DVI encoder or lcd panel to lcdc
42		42
43	[1] There is an errata about AM335x color wiring. For 16-bit color mode	43	[1] There is an errata about AM335x color wiring. For 16-bit color mode

Documentation/devicetree/bindings/dma/ti/k3-udma.yaml+1−13

@@ -143,7 +143,7 @@ examples: · 142 unmodified lines
143	#size-cells = <2>;	143	#size-cells = <2>;
144	dma-coherent;	144	dma-coherent;
145	dma-ranges;	145	dma-ranges;
146	ranges;	146	ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
147		147
148	ti,sci-dev-id = <118>;	148	ti,sci-dev-id = <118>;
149		149
@@ -169,16 +169,4 @@ examples: · 19 unmodified lines
169	ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */	169	ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
170	};	170	};
171	};	171	};
172
173	mcasp0: mcasp@02B00000 {
174	dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
175	dma-names = "tx", "rx";
176	};
177
178	crypto: crypto@4E00000 {
179	compatible = "ti,sa2ul-crypto";
180
181	dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>;
182	dma-names = "tx", "rx1", "rx2";
183	};
184	};	172	};

Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml+7−7

@@ -84,31 +84,31 @@ examples: · 83 unmodified lines
84	gpu_opp_table: opp_table0 {	84	gpu_opp_table: opp_table0 {
85	compatible = "operating-points-v2";	85	compatible = "operating-points-v2";
86		86
87	opp@533000000 {	87	opp-533000000 {
88	opp-hz = /bits/ 64 <533000000>;	88	opp-hz = /bits/ 64 <533000000>;
89	opp-microvolt = <1250000>;	89	opp-microvolt = <1250000>;
90	};	90	};
91	opp@450000000 {	91	opp-450000000 {
92	opp-hz = /bits/ 64 <450000000>;	92	opp-hz = /bits/ 64 <450000000>;
93	opp-microvolt = <1150000>;	93	opp-microvolt = <1150000>;
94	};	94	};
95	opp@400000000 {	95	opp-400000000 {
96	opp-hz = /bits/ 64 <400000000>;	96	opp-hz = /bits/ 64 <400000000>;
97	opp-microvolt = <1125000>;	97	opp-microvolt = <1125000>;
98	};	98	};
99	opp@350000000 {	99	opp-350000000 {
100	opp-hz = /bits/ 64 <350000000>;	100	opp-hz = /bits/ 64 <350000000>;
101	opp-microvolt = <1075000>;	101	opp-microvolt = <1075000>;
102	};	102	};
103	opp@266000000 {	103	opp-266000000 {
104	opp-hz = /bits/ 64 <266000000>;	104	opp-hz = /bits/ 64 <266000000>;
105	opp-microvolt = <1025000>;	105	opp-microvolt = <1025000>;
106	};	106	};
107	opp@160000000 {	107	opp-160000000 {
108	opp-hz = /bits/ 64 <160000000>;	108	opp-hz = /bits/ 64 <160000000>;
109	opp-microvolt = <925000>;	109	opp-microvolt = <925000>;
110	};	110	};
111	opp@100000000 {	111	opp-100000000 {
112	opp-hz = /bits/ 64 <100000000>;	112	opp-hz = /bits/ 64 <100000000>;
113	opp-microvolt = <912500>;	113	opp-microvolt = <912500>;
114	};	114	};

Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml+7−7

@@ -138,31 +138,31 @@ examples: · 137 unmodified lines
138	gpu_opp_table: opp_table0 {	138	gpu_opp_table: opp_table0 {
139	compatible = "operating-points-v2";	139	compatible = "operating-points-v2";
140		140
141	opp@533000000 {	141	opp-533000000 {
142	opp-hz = /bits/ 64 <533000000>;	142	opp-hz = /bits/ 64 <533000000>;
143	opp-microvolt = <1250000>;	143	opp-microvolt = <1250000>;
144	};	144	};
145	opp@450000000 {	145	opp-450000000 {
146	opp-hz = /bits/ 64 <450000000>;	146	opp-hz = /bits/ 64 <450000000>;
147	opp-microvolt = <1150000>;	147	opp-microvolt = <1150000>;
148	};	148	};
149	opp@400000000 {	149	opp-400000000 {
150	opp-hz = /bits/ 64 <400000000>;	150	opp-hz = /bits/ 64 <400000000>;
151	opp-microvolt = <1125000>;	151	opp-microvolt = <1125000>;
152	};	152	};
153	opp@350000000 {	153	opp-350000000 {
154	opp-hz = /bits/ 64 <350000000>;	154	opp-hz = /bits/ 64 <350000000>;
155	opp-microvolt = <1075000>;	155	opp-microvolt = <1075000>;
156	};	156	};
157	opp@266000000 {	157	opp-266000000 {
158	opp-hz = /bits/ 64 <266000000>;	158	opp-hz = /bits/ 64 <266000000>;
159	opp-microvolt = <1025000>;	159	opp-microvolt = <1025000>;
160	};	160	};
161	opp@160000000 {	161	opp-160000000 {
162	opp-hz = /bits/ 64 <160000000>;	162	opp-hz = /bits/ 64 <160000000>;
163	opp-microvolt = <925000>;	163	opp-microvolt = <925000>;
164	};	164	};
165	opp@100000000 {	165	opp-100000000 {
166	opp-hz = /bits/ 64 <100000000>;	166	opp-hz = /bits/ 64 <100000000>;
167	opp-microvolt = <912500>;	167	opp-microvolt = <912500>;
168	};	168	};

Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml+1−1

@@ -123,7 +123,7 @@ examples: · 122 unmodified lines
123	samsung,syscon-phandle = <&pmu_system_controller>;	123	samsung,syscon-phandle = <&pmu_system_controller>;
124		124
125	/* NTC thermistor is a hwmon device */	125	/* NTC thermistor is a hwmon device */
126	ncp15wb473@0 {	126	ncp15wb473 {
127	compatible = "murata,ncp15wb473";	127	compatible = "murata,ncp15wb473";
128	pullup-uv = <1800000>;	128	pullup-uv = <1800000>;
129	pullup-ohm = <47000>;	129	pullup-ohm = <47000>;

Documentation/devicetree/bindings/input/touchscreen/goodix.yaml+1−1

@@ -62,7 +62,7 @@ required: · 61 unmodified lines
62		62
63	examples:	63	examples:
64	- \|	64	- \|
65	i2c@00000000 {	65	i2c {
66	#address-cells = <1>;	66	#address-cells = <1>;
67	#size-cells = <0>;	67	#size-cells = <0>;
68	gt928@5d {	68	gt928@5d {

Documentation/devicetree/bindings/input/twl4030-pwrbutton.txt+1−1

@@ -1,7 +1,7 @@
1	Texas Instruments TWL family (twl4030) pwrbutton module	1	Texas Instruments TWL family (twl4030) pwrbutton module
2		2
3	This module is part of the TWL4030. For more details about the whole	3	This module is part of the TWL4030. For more details about the whole
4	chip see Documentation/devicetree/bindings/mfd/twl-familly.txt.	4	chip see Documentation/devicetree/bindings/mfd/twl-family.txt.
5		5
6	This module provides a simple power button event via an Interrupt.	6	This module provides a simple power button event via an Interrupt.
7		7

Documentation/devicetree/bindings/leds/common.yaml+1−1

@@ -85,7 +85,7 @@ properties: · 84 unmodified lines
85	# LED will act as a back-light, controlled by the framebuffer system	85	# LED will act as a back-light, controlled by the framebuffer system
86	- backlight	86	- backlight
87	# LED will turn on (but for leds-gpio see "default-state" property in	87	# LED will turn on (but for leds-gpio see "default-state" property in
88	# Documentation/devicetree/bindings/leds/leds-gpio.txt)	88	# Documentation/devicetree/bindings/leds/leds-gpio.yaml)
89	- default-on	89	- default-on
90	# LED "double" flashes at a load average based rate	90	# LED "double" flashes at a load average based rate
91	- heartbeat	91	- heartbeat

Documentation/devicetree/bindings/leds/register-bit-led.txt+1−1

@@ -5,7 +5,7 @@ where single bits in a certain register can turn on/off a · 4 unmodified lines
5	single LED. The register bit LEDs appear as children to the	5	single LED. The register bit LEDs appear as children to the
6	syscon device, with the proper compatible string. For the	6	syscon device, with the proper compatible string. For the
7	syscon bindings see:	7	syscon bindings see:
8	Documentation/devicetree/bindings/mfd/syscon.txt	8	Documentation/devicetree/bindings/mfd/syscon.yaml
9		9
10	Each LED is represented as a sub-node of the syscon device. Each	10	Each LED is represented as a sub-node of the syscon device. Each
11	node's name represents the name of the corresponding LED.	11	node's name represents the name of the corresponding LED.

Documentation/devicetree/bindings/media/ti,cal.yaml+1−1

@@ -177,7 +177,7 @@ examples: · 176 unmodified lines
177	};	177	};
178	};	178	};
179		179
180	i2c5: i2c@4807c000 {	180	i2c {
181	clock-frequency = <400000>;	181	clock-frequency = <400000>;
182	#address-cells = <1>;	182	#address-cells = <1>;
183	#size-cells = <0>;	183	#size-cells = <0>;

Documentation/devicetree/bindings/memory-controllers/ti/emif.txt+1−1

@@ -32,7 +32,7 @@ Required only for "ti,emif-am3352" and "ti,emif-am4372": · 31 unmodified lines
32	- sram : Phandles for generic sram driver nodes,	32	- sram : Phandles for generic sram driver nodes,
33	first should be type 'protect-exec' for the driver to use to copy	33	first should be type 'protect-exec' for the driver to use to copy
34	and run PM functions, second should be regular pool to be used for	34	and run PM functions, second should be regular pool to be used for
35	data region for code. See Documentation/devicetree/bindings/sram/sram.txt	35	data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
36	for more details.	36	for more details.
37		37
38	Optional properties:	38	Optional properties:

Documentation/devicetree/bindings/mfd/max77650.yaml+2−2

@@ -97,14 +97,14 @@ examples: · 96 unmodified lines
97	regulators {	97	regulators {
98	compatible = "maxim,max77650-regulator";	98	compatible = "maxim,max77650-regulator";
99		99
100	max77650_ldo: regulator@0 {	100	max77650_ldo: regulator-ldo {
101	regulator-compatible = "ldo";	101	regulator-compatible = "ldo";
102	regulator-name = "max77650-ldo";	102	regulator-name = "max77650-ldo";
103	regulator-min-microvolt = <1350000>;	103	regulator-min-microvolt = <1350000>;
104	regulator-max-microvolt = <2937500>;	104	regulator-max-microvolt = <2937500>;
105	};	105	};
106		106
107	max77650_sbb0: regulator@1 {	107	max77650_sbb0: regulator-sbb0 {
108	regulator-compatible = "sbb0";	108	regulator-compatible = "sbb0";
109	regulator-name = "max77650-sbb0";	109	regulator-name = "max77650-sbb0";
110	regulator-min-microvolt = <800000>;	110	regulator-min-microvolt = <800000>;

Documentation/devicetree/bindings/mfd/tps65910.txt+2−2

@@ -26,8 +26,8 @@ Required properties: · 25 unmodified lines
26	ldo6, ldo7, ldo8	26	ldo6, ldo7, ldo8
27		27
28	- xxx-supply: Input voltage supply regulator.	28	- xxx-supply: Input voltage supply regulator.
29	These entries are require if regulators are enabled for a device. Missing of these	29	These entries are required if regulators are enabled for a device. Missing these
30	properties can cause the regulator registration fails.	30	properties can cause the regulator registration to fail.
31	If some of input supply is powered through battery or always-on supply then	31	If some of input supply is powered through battery or always-on supply then
32	also it is require to have these parameters with proper node handle of always	32	also it is require to have these parameters with proper node handle of always
33	on power supply.	33	on power supply.

Documentation/devicetree/bindings/mfd/twl-family.txtrenamed from Documentation/devicetree/bindings/mfd/twl-familly.txt+0−0

File renamed without changes.

Documentation/devicetree/bindings/mfd/zii,rave-sp.txt+1−1

@@ -20,7 +20,7 @@ RAVE SP consists of the following sub-devices: · 19 unmodified lines
20	Device Description	20	Device Description
21	------ -----------	21	------ -----------
22	rave-sp-wdt : Watchdog	22	rave-sp-wdt : Watchdog
23	rave-sp-nvmem : Interface to onborad EEPROM	23	rave-sp-nvmem : Interface to onboard EEPROM
24	rave-sp-backlight : Display backlight	24	rave-sp-backlight : Display backlight
25	rave-sp-hwmon : Interface to onboard hardware sensors	25	rave-sp-hwmon : Interface to onboard hardware sensors
26	rave-sp-leds : Interface to onboard LEDs	26	rave-sp-leds : Interface to onboard LEDs

Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt+1−1

@@ -26,7 +26,7 @@ For generic IOMMU bindings, see · 25 unmodified lines
26	Documentation/devicetree/bindings/iommu/iommu.txt.	26	Documentation/devicetree/bindings/iommu/iommu.txt.
27		27
28	For arm-smmu binding, see:	28	For arm-smmu binding, see:
29	Documentation/devicetree/bindings/iommu/arm,smmu.txt.	29	Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
30		30
31	Required properties:	31	Required properties:
32		32

Documentation/devicetree/bindings/mmc/mmc-controller.yaml+1−0

@@ -370,6 +370,7 @@ examples: · 369 unmodified lines
370	mmc3: mmc@1c12000 {	370	mmc3: mmc@1c12000 {
371	#address-cells = <1>;	371	#address-cells = <1>;
372	#size-cells = <0>;	372	#size-cells = <0>;
		373	reg = <0x1c12000 0x200>;
373	pinctrl-names = "default";	374	pinctrl-names = "default";
374	pinctrl-0 = <&mmc3_pins_a>;	375	pinctrl-0 = <&mmc3_pins_a>;
375	vmmc-supply = <&reg_vmmc3>;	376	vmmc-supply = <&reg_vmmc3>;

Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt+1−1

@@ -27,7 +27,7 @@ Required properties of NAND chips: · 26 unmodified lines
27	- reg: shall contain the native Chip Select ids from 0 to max supported by	27	- reg: shall contain the native Chip Select ids from 0 to max supported by
28	the cadence nand flash controller	28	the cadence nand flash controller
29		29
30	See Documentation/devicetree/bindings/mtd/nand.txt for more details on	30	See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
31	generic bindings.	31	generic bindings.
32		32
33	Example:	33	Example:

Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt+1−1

@@ -45,7 +45,7 @@ Optional properties: · 44 unmodified lines
45	switch queue	45	switch queue
46		46
47	- resets: a single phandle and reset identifier pair. See	47	- resets: a single phandle and reset identifier pair. See
48	Documentation/devicetree/binding/reset/reset.txt for details.	48	Documentation/devicetree/bindings/reset/reset.txt for details.
49		49
50	- reset-names: If the "reset" property is specified, this property should have	50	- reset-names: If the "reset" property is specified, this property should have
51	the value "switch" to denote the switch reset line.	51	the value "switch" to denote the switch reset line.

Documentation/devicetree/bindings/net/fsl-fman.txt+7−0

@@ -110,6 +110,13 @@ PROPERTIES · 109 unmodified lines
110	Usage: required	110	Usage: required
111	Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt	111	Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
112		112
		113	- fsl,erratum-a050385
		114	Usage: optional
		115	Value type: boolean
		116	Definition: A boolean property. Indicates the presence of the
		117	erratum A050385 which indicates that DMA transactions that are
		118	split can result in a FMan lock.
		119
113	=============================================================================	120	=============================================================================
114	FMan MURAM Node	121	FMan MURAM Node
115		122

Documentation/devicetree/bindings/nvmem/nvmem.yaml+2−0

@@ -76,6 +76,8 @@ examples: · 75 unmodified lines
76	qfprom: eeprom@700000 {	76	qfprom: eeprom@700000 {
77	#address-cells = <1>;	77	#address-cells = <1>;
78	#size-cells = <1>;	78	#size-cells = <1>;
		79	reg = <0x00700000 0x100000>;
		80
79	wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;	81	wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
80		82
81	/* ... */	83	/* ... */

Documentation/devicetree/bindings/phy/allwinner,sun4i-a10-usb-phy.yaml+1−1

@@ -86,7 +86,7 @@ examples: · 85 unmodified lines
86	#include <dt-bindings/clock/sun4i-a10-ccu.h>	86	#include <dt-bindings/clock/sun4i-a10-ccu.h>
87	#include <dt-bindings/reset/sun4i-a10-ccu.h>	87	#include <dt-bindings/reset/sun4i-a10-ccu.h>
88		88
89	usbphy: phy@01c13400 {	89	usbphy: phy@1c13400 {
90	#phy-cells = <1>;	90	#phy-cells = <1>;
91	compatible = "allwinner,sun4i-a10-usb-phy";	91	compatible = "allwinner,sun4i-a10-usb-phy";
92	reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;	92	reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;

Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml+1−1

@@ -17,7 +17,7 @@ description: \|+ · 16 unmodified lines
17	"aspeed,ast2400-scu", "syscon", "simple-mfd"	17	"aspeed,ast2400-scu", "syscon", "simple-mfd"
18		18
19	Refer to the the bindings described in	19	Refer to the the bindings described in
20	Documentation/devicetree/bindings/mfd/syscon.txt	20	Documentation/devicetree/bindings/mfd/syscon.yaml
21		21
22	properties:	22	properties:
23	compatible:	23	compatible:

Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml+1−1

@@ -18,7 +18,7 @@ description: \|+ · 17 unmodified lines
18	"aspeed,g5-scu", "syscon", "simple-mfd"	18	"aspeed,g5-scu", "syscon", "simple-mfd"
19		19
20	Refer to the the bindings described in	20	Refer to the the bindings described in
21	Documentation/devicetree/bindings/mfd/syscon.txt	21	Documentation/devicetree/bindings/mfd/syscon.yaml
22		22
23	properties:	23	properties:
24	compatible:	24	compatible:

Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml+1−1

@@ -17,7 +17,7 @@ description: \|+ · 16 unmodified lines
17	"aspeed,ast2600-scu", "syscon", "simple-mfd"	17	"aspeed,ast2600-scu", "syscon", "simple-mfd"
18		18
19	Refer to the the bindings described in	19	Refer to the the bindings described in
20	Documentation/devicetree/bindings/mfd/syscon.txt	20	Documentation/devicetree/bindings/mfd/syscon.yaml
21		21
22	properties:	22	properties:
23	compatible:	23	compatible:

Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml+1−1

@@ -248,7 +248,7 @@ examples: · 247 unmodified lines
248	};	248	};
249		249
250	//Example 3 pin groups	250	//Example 3 pin groups
251	pinctrl@60020000 {	251	pinctrl {
252	usart1_pins_a: usart1-0 {	252	usart1_pins_a: usart1-0 {
253	pins1 {	253	pins1 {
254	pinmux = <STM32_PINMUX('A', 9, AF7)>;	254	pinmux = <STM32_PINMUX('A', 9, AF7)>;

Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml+1−1

@@ -18,7 +18,7 @@ description: \|+ · 17 unmodified lines
18	"amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"	18	"amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"
19		19
20	Refer to the the bindings described in	20	Refer to the the bindings described in
21	Documentation/devicetree/bindings/mfd/syscon.txt	21	Documentation/devicetree/bindings/mfd/syscon.yaml
22		22
23	properties:	23	properties:
24	compatible:	24	compatible:

Documentation/devicetree/bindings/power/domain-idle-state.txt+0−33

@@ -1,33 +0,0 @@
1	PM Domain Idle State Node:
2
3	A domain idle state node represents the state parameters that will be used to
4	select the state when there are no active components in the domain.
5
6	The state node has the following parameters -
7
8	- compatible:
9	Usage: Required
10	Value type: <string>
11	Definition: Must be "domain-idle-state".
12
13	- entry-latency-us
14	Usage: Required
15	Value type: <prop-encoded-array>
16	Definition: u32 value representing worst case latency in
17	microseconds required to enter the idle state.
18	The exit-latency-us duration may be guaranteed
19	only after entry-latency-us has passed.
20
21	- exit-latency-us
22	Usage: Required
23	Value type: <prop-encoded-array>
24	Definition: u32 value representing worst case latency
25	in microseconds required to exit the idle state.
26
27	- min-residency-us
28	Usage: Required
29	Value type: <prop-encoded-array>
30	Definition: u32 value representing minimum residency duration
31	in microseconds after which the idle state will yield
32	power benefits after overcoming the overhead in entering
33	i the idle state.

Documentation/devicetree/bindings/power/domain-idle-state.yaml+64−0

@@ -0,0 +1,64 @@
	1	# SPDX-License-Identifier: GPL-2.0
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: PM Domain Idle States binding description
	8
	9	maintainers:
	10	- Ulf Hansson <ulf.hansson@linaro.org>
	11
	12	description:
	13	A domain idle state node represents the state parameters that will be used to
	14	select the state when there are no active components in the PM domain.
	15
	16	properties:
	17	$nodename:
	18	const: domain-idle-states
	19
	20	patternProperties:
	21	"^(cpu\|cluster\|domain)-":
	22	type: object
	23	description:
	24	Each state node represents a domain idle state description.
	25
	26	properties:
	27	compatible:
	28	const: domain-idle-state
	29
	30	entry-latency-us:
	31	description:
	32	The worst case latency in microseconds required to enter the idle
	33	state. Note that, the exit-latency-us duration may be guaranteed only
	34	after the entry-latency-us has passed.
	35
	36	exit-latency-us:
	37	description:
	38	The worst case latency in microseconds required to exit the idle
	39	state.
	40
	41	min-residency-us:
	42	description:
	43	The minimum residency duration in microseconds after which the idle
	44	state will yield power benefits, after overcoming the overhead while
	45	entering the idle state.
	46
	47	required:
	48	- compatible
	49	- entry-latency-us
	50	- exit-latency-us
	51	- min-residency-us
	52
	53	examples:
	54	- \|
	55
	56	domain-idle-states {
	57	domain_retention: domain-retention {
	58	compatible = "domain-idle-state";
	59	entry-latency-us = <20>;
	60	exit-latency-us = <40>;
	61	min-residency-us = <80>;
	62	};
	63	};
	64	...

Documentation/devicetree/bindings/power/power-domain.yaml+11−13

@@ -25,22 +25,20 @@ description: \|+ · 24 unmodified lines
25		25
26	properties:	26	properties:
27	$nodename:	27	$nodename:
28	pattern: "^(power-controller\|power-domain)(@.*)?$"	28	pattern: "^(power-controller\|power-domain)([@-].*)?$"
29		29
30	domain-idle-states:	30	domain-idle-states:
31	$ref: /schemas/types.yaml#/definitions/phandle-array	31	$ref: /schemas/types.yaml#/definitions/phandle-array
32	description:	32	description: \|
33	A phandle of an idle-state that shall be soaked into a generic domain	33	Phandles of idle states that defines the available states for the
34	power state. The idle state definitions are compatible with	34	power-domain provider. The idle state definitions are compatible with the
35	domain-idle-state specified in	35	domain-idle-state bindings, specified in ./domain-idle-state.yaml.
36	Documentation/devicetree/bindings/power/domain-idle-state.txt	36
37	phandles that are not compatible with domain-idle-state will be ignored.	37	Note that, the domain-idle-state property reflects the idle states of this
38	The domain-idle-state property reflects the idle state of this PM domain	38	PM domain and not the idle states of the devices or sub-domains in the PM
39	and not the idle states of the devices or sub-domains in the PM domain.	39	domain. Devices and sub-domains have their own idle states independent of
40	Devices and sub-domains have their own idle-states independent	40	the parent domain's idle states. In the absence of this property, the
41	of the parent domain's idle states. In the absence of this property,	41	domain would be considered as capable of being powered-on or powered-off.
42	the domain would be considered as capable of being powered-on
43	or powered-off.
44		42
45	operating-points-v2:	43	operating-points-v2:
46	$ref: /schemas/types.yaml#/definitions/phandle-array	44	$ref: /schemas/types.yaml#/definitions/phandle-array

Documentation/devicetree/bindings/power/power_domain.txt+1−1

@@ -109,4 +109,4 @@ Example: · 108 unmodified lines
109	required-opps = <&domain1_opp_1>;	109	required-opps = <&domain1_opp_1>;
110	};	110	};
111		111
112	[1]. Documentation/devicetree/bindings/power/domain-idle-state.txt	112	[1]. Documentation/devicetree/bindings/power/domain-idle-state.yaml

Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt+1−1

@@ -161,7 +161,7 @@ The regulator node houses sub-nodes for each regulator within the device. Each · 160 unmodified lines
161	sub-node is identified using the node's name, with valid values listed for each	161	sub-node is identified using the node's name, with valid values listed for each
162	of the PMICs below.	162	of the PMICs below.
163		163
164	pm8005:	164	pm8004:
165	s2, s5	165	s2, s5
166		166
167	pm8005:	167	pm8005:

Documentation/devicetree/bindings/regulator/regulator.yaml+1−1

@@ -191,7 +191,7 @@ patternProperties: · 190 unmodified lines
191		191
192	examples:	192	examples:
193	- \|	193	- \|
194	xyzreg: regulator@0 {	194	xyzreg: regulator {
195	regulator-min-microvolt = <1000000>;	195	regulator-min-microvolt = <1000000>;
196	regulator-max-microvolt = <2500000>;	196	regulator-max-microvolt = <2500000>;
197	regulator-always-on;	197	regulator-always-on;

Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml+5−1

     description: Global reset register offset and bit offset.
     allOf:
       - $ref: /schemas/types.yaml#/definitions/uint32-array
-      - maxItems: 2
+    items:
+      - description: Register offset
+      - description: Register bit offset
+        minimum: 0
+        maximum: 31
   "#reset-cells":
     minimum: 2

Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt+1−1

@@ -3,4 +3,4 @@ STMicroelectronics STM32MP1 Peripheral Reset Controller · 2 unmodified lines
3		3
4	The RCC IP is both a reset and a clock controller.	4	The RCC IP is both a reset and a clock controller.
5		5
6	Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt	6	Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml

Documentation/devicetree/bindings/sound/st,stm32-sai.txt+1−1

@@ -36,7 +36,7 @@ SAI subnodes required properties: · 35 unmodified lines
36	- clock-names: Must contain "sai_ck".	36	- clock-names: Must contain "sai_ck".
37	Must also contain "MCLK", if SAI shares a master clock,	37	Must also contain "MCLK", if SAI shares a master clock,
38	with a SAI set as MCLK clock provider.	38	with a SAI set as MCLK clock provider.
39	- dmas: see Documentation/devicetree/bindings/dma/stm32-dma.txt	39	- dmas: see Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
40	- dma-names: identifier string for each DMA request line	40	- dma-names: identifier string for each DMA request line
41	"tx": if sai sub-block is configured as playback DAI	41	"tx": if sai sub-block is configured as playback DAI
42	"rx": if sai sub-block is configured as capture DAI	42	"rx": if sai sub-block is configured as capture DAI

Documentation/devicetree/bindings/sound/st,stm32-spdifrx.txt+1−1

@@ -10,7 +10,7 @@ Required properties: · 9 unmodified lines
10	- clock-names: must contain "kclk"	10	- clock-names: must contain "kclk"
11	- interrupts: cpu DAI interrupt line	11	- interrupts: cpu DAI interrupt line
12	- dmas: DMA specifiers for audio data DMA and iec control flow DMA	12	- dmas: DMA specifiers for audio data DMA and iec control flow DMA
13	See STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt	13	See STM32 DMA bindings, Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
14	- dma-names: two dmas have to be defined, "rx" and "rx-ctrl"	14	- dma-names: two dmas have to be defined, "rx" and "rx-ctrl"
15		15
16	Optional properties:	16	Optional properties:

Documentation/devicetree/bindings/spi/st,stm32-spi.yaml+1−1

@@ -49,7 +49,7 @@ properties: · 48 unmodified lines
49	dmas:	49	dmas:
50	description: \|	50	description: \|
51	DMA specifiers for tx and rx dma. DMA fifo mode must be used. See	51	DMA specifiers for tx and rx dma. DMA fifo mode must be used. See
52	the STM32 DMA bindings Documentation/devicetree/bindings/dma/stm32-dma.txt.	52	the STM32 DMA bindings Documentation/devicetree/bindings/dma/st,stm32-dma.yaml.
53	items:	53	items:
54	- description: rx DMA channel	54	- description: rx DMA channel
55	- description: tx DMA channel	55	- description: tx DMA channel

Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml+1−1

@@ -125,7 +125,7 @@ examples: · 124 unmodified lines
125	#size-cells = <1>;	125	#size-cells = <1>;
126	ranges;	126	ranges;
127		127
128	sram_a: sram@00000000 {	128	sram_a: sram@0 {
129	compatible = "mmio-sram";	129	compatible = "mmio-sram";
130	reg = <0x00000000 0xc000>;	130	reg = <0x00000000 0xc000>;
131	#address-cells = <1>;	131	#address-cells = <1>;

Documentation/devicetree/bindings/thermal/brcm,avs-ro-thermal.yaml+1−1

@@ -17,7 +17,7 @@ description: \|+ · 16 unmodified lines
17	"brcm,bcm2711-avs-monitor", "syscon", "simple-mfd"	17	"brcm,bcm2711-avs-monitor", "syscon", "simple-mfd"
18		18
19	Refer to the the bindings described in	19	Refer to the the bindings described in
20	Documentation/devicetree/bindings/mfd/syscon.txt	20	Documentation/devicetree/bindings/mfd/syscon.yaml
21		21
22	properties:	22	properties:
23	compatible:	23	compatible:

Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml+1−1

@@ -87,7 +87,7 @@ additionalProperties: false · 86 unmodified lines
87		87
88	examples:	88	examples:
89	- \|	89	- \|
90	timer {	90	timer@1c20c00 {
91	compatible = "allwinner,sun4i-a10-timer";	91	compatible = "allwinner,sun4i-a10-timer";
92	reg = <0x01c20c00 0x400>;	92	reg = <0x01c20c00 0x400>;
93	interrupts = <22>,	93	interrupts = <22>,

Documentation/driver-api/dmaengine/client.rst+10−4

@@ -151,8 +151,8 @@ The details of these operations are: · 150 unmodified lines
151	Note that callbacks will always be invoked from the DMA	151	Note that callbacks will always be invoked from the DMA
152	engines tasklet, never from interrupt context.	152	engines tasklet, never from interrupt context.
153		153
154	Optional: per descriptor metadata	154	Optional: per descriptor metadata
155	---------------------------------	155
156	DMAengine provides two ways for metadata support.	156	DMAengine provides two ways for metadata support.
157		157
158	DESC_METADATA_CLIENT	158	DESC_METADATA_CLIENT
@@ -199,12 +199,15 @@ Optional: per descriptor metadata · 40 unmodified lines
199	DESC_METADATA_CLIENT	199	DESC_METADATA_CLIENT
200		200
201	- DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:	201	- DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
		202
202	1. prepare the descriptor (dmaengine_prep_*)	203	1. prepare the descriptor (dmaengine_prep_*)
203	construct the metadata in the client's buffer	204	construct the metadata in the client's buffer
204	2. use dmaengine_desc_attach_metadata() to attach the buffer to the	205	2. use dmaengine_desc_attach_metadata() to attach the buffer to the
205	descriptor	206	descriptor
206	3. submit the transfer	207	3. submit the transfer
		208
207	- DMA_DEV_TO_MEM:	209	- DMA_DEV_TO_MEM:
		210
208	1. prepare the descriptor (dmaengine_prep_*)	211	1. prepare the descriptor (dmaengine_prep_*)
209	2. use dmaengine_desc_attach_metadata() to attach the buffer to the	212	2. use dmaengine_desc_attach_metadata() to attach the buffer to the
210	descriptor	213	descriptor
@@ -215,6 +218,7 @@ Optional: per descriptor metadata · 4 unmodified lines
215	DESC_METADATA_ENGINE	218	DESC_METADATA_ENGINE
216		219
217	- DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:	220	- DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
		221
218	1. prepare the descriptor (dmaengine_prep_*)	222	1. prepare the descriptor (dmaengine_prep_*)
219	2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the	223	2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the
220	engine's metadata area	224	engine's metadata area
@@ -222,7 +226,9 @@ Optional: per descriptor metadata · 1 unmodified line
222	4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the	226	4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the
223	amount of data the client has placed into the metadata buffer	227	amount of data the client has placed into the metadata buffer
224	5. submit the transfer	228	5. submit the transfer
		229
225	- DMA_DEV_TO_MEM:	230	- DMA_DEV_TO_MEM:
		231
226	1. prepare the descriptor (dmaengine_prep_*)	232	1. prepare the descriptor (dmaengine_prep_*)
227	2. submit the transfer	233	2. submit the transfer
228	3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get	234	3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get
@@ -278,8 +284,8 @@ Optional: per descriptor metadata · 49 unmodified lines
278		284
279	void dma_async_issue_pending(struct dma_chan *chan);	285	void dma_async_issue_pending(struct dma_chan *chan);
280		286
281	Further APIs:	287	Further APIs
282	-------------	288	------------
283		289
284	1. Terminate APIs	290	1. Terminate APIs
285		291

Documentation/filesystems/debugfs.txt+3−3

@@ -164,9 +164,9 @@ file. · 163 unmodified lines
164	void __iomem *base;	164	void __iomem *base;
165	};	165	};
166		166
167	struct dentry debugfs_create_regset32(const char name, umode_t mode,	167	debugfs_create_regset32(const char *name, umode_t mode,
168	struct dentry *parent,	168	struct dentry *parent,
169	struct debugfs_regset32 *regset);	169	struct debugfs_regset32 *regset);
170		170
171	void debugfs_print_regs32(struct seq_file s, struct debugfs_reg32 regs,	171	void debugfs_print_regs32(struct seq_file s, struct debugfs_reg32 regs,
172	int nregs, void __iomem base, char prefix);	172	int nregs, void __iomem base, char prefix);

Documentation/filesystems/porting.rst+8−0

@@ -850,3 +850,11 @@ business doing so. · 849 unmodified lines
850	d_alloc_pseudo() is internal-only; uses outside of alloc_file_pseudo() are	850	d_alloc_pseudo() is internal-only; uses outside of alloc_file_pseudo() are
851	very suspect (and won't work in modules). Such uses are very likely to	851	very suspect (and won't work in modules). Such uses are very likely to
852	be misspelled d_alloc_anon().	852	be misspelled d_alloc_anon().
		853
		854	---
		855
		856	mandatory
		857
		858	[should've been added in 2016] stale comment in finish_open() nonwithstanding,
		859	failure exits in ->atomic_open() instances should NOT fput() the file,
		860	no matter what. Everything is handled by the caller.

Documentation/hwmon/adm1177.rst+1−2

@@ -20,8 +20,7 @@ Usage Notes · 19 unmodified lines
20	-----------	20	-----------
21		21
22	This driver does not auto-detect devices. You will have to instantiate the	22	This driver does not auto-detect devices. You will have to instantiate the
23	devices explicitly. Please see Documentation/i2c/instantiating-devices for	23	devices explicitly. Please see :doc:`/i2c/instantiating-devices` for details.
24	details.
25		24
26		25
27	Sysfs entries	26	Sysfs entries

Documentation/kbuild/kbuild.rst+1−1

@@ -237,7 +237,7 @@ This is solely useful to speed up test compiles. · 236 unmodified lines
237	KBUILD_EXTRA_SYMBOLS	237	KBUILD_EXTRA_SYMBOLS
238	--------------------	238	--------------------
239	For modules that use symbols from other modules.	239	For modules that use symbols from other modules.
240	See more details in modules.txt.	240	See more details in modules.rst.
241		241
242	ALLSOURCE_ARCHS	242	ALLSOURCE_ARCHS
243	---------------	243	---------------

Documentation/kbuild/kconfig-macro-language.rst+1−1

@@ -44,7 +44,7 @@ intermediate:: · 43 unmodified lines
44	def_bool y	44	def_bool y
45		45
46	Then, Kconfig moves onto the evaluation stage to resolve inter-symbol	46	Then, Kconfig moves onto the evaluation stage to resolve inter-symbol
47	dependency as explained in kconfig-language.txt.	47	dependency as explained in kconfig-language.rst.
48		48
49		49
50	Variables	50	Variables

Documentation/kbuild/makefiles.rst+4−7

 	Example::
 		#arch/x86/boot/Makefile
-		subdir- := compressed/
+		subdir- := compressed
 The above assignment instructs kbuild to descend down in the
 directory compressed/ when "make clean" is executed.
 	$(KBUILD_AFLAGS_MODULE) is used to add arch-specific options that
 	are used for assembler.
-	From commandline AFLAGS_MODULE shall be used (see kbuild.txt).
+	From commandline AFLAGS_MODULE shall be used (see kbuild.rst).
     KBUILD_CFLAGS_KERNEL
 	$(CC) options specific for built-in
 	$(KBUILD_CFLAGS_MODULE) is used to add arch-specific options that
 	are used for $(CC).
-	From commandline CFLAGS_MODULE shall be used (see kbuild.txt).
+	From commandline CFLAGS_MODULE shall be used (see kbuild.rst).
     KBUILD_LDFLAGS_MODULE
 	Options for $(LD) when linking modules
 	$(KBUILD_LDFLAGS_MODULE) is used to add arch-specific options
 	used when linking modules. This is often a linker script.
-	From commandline LDFLAGS_MODULE shall be used (see kbuild.txt).
+	From commandline LDFLAGS_MODULE shall be used (see kbuild.rst).
     KBUILD_LDS
 	in arch/$(ARCH)/include/(uapi/)/asm, Kbuild will automatically generate
 	a wrapper of the asm-generic one.
-	The convention is to list one subdir per line and
-	preferably in alphabetic order.
 8 Kbuild Variables
 ==================

Documentation/kbuild/modules.rst+2−2

@@ -470,9 +470,9 @@ build. · 469 unmodified lines
470		470
471	The syntax of the Module.symvers file is::	471	The syntax of the Module.symvers file is::
472		472
473	<CRC> <Symbol> <Namespace> <Module> <Export Type>	473	<CRC> <Symbol> <Module> <Export Type> <Namespace>
474		474
475	0xe1cc2a05 usb_stor_suspend USB_STORAGE drivers/usb/storage/usb-storage EXPORT_SYMBOL_GPL	475	0xe1cc2a05 usb_stor_suspend drivers/usb/storage/usb-storage EXPORT_SYMBOL_GPL USB_STORAGE
476		476
477	The fields are separated by tabs and values may be empty (e.g.	477	The fields are separated by tabs and values may be empty (e.g.
478	if no namespace is defined for an exported symbol).	478	if no namespace is defined for an exported symbol).

Documentation/networking/devlink/devlink-region.rst+0−3

@@ -40,9 +40,6 @@ example usage · 39 unmodified lines
40	# Delete a snapshot using:	40	# Delete a snapshot using:
41	$ devlink region del pci/0000:00:05.0/cr-space snapshot 1	41	$ devlink region del pci/0000:00:05.0/cr-space snapshot 1
42		42
43	# Trigger (request) a snapshot be taken:
44	$ devlink region trigger pci/0000:00:05.0/cr-space
45
46	# Dump a snapshot:	43	# Dump a snapshot:
47	$ devlink region dump pci/0000:00:05.0/fw-health snapshot 1	44	$ devlink region dump pci/0000:00:05.0/fw-health snapshot 1
48	0000000000000000 0014 95dc 0014 9514 0035 1670 0034 db30	45	0000000000000000 0014 95dc 0014 9514 0035 1670 0034 db30

Documentation/networking/net_failover.rst+3−3

@@ -8,9 +8,9 @@ Overview · 7 unmodified lines
8	========	8	========
9		9
10	The net_failover driver provides an automated failover mechanism via APIs	10	The net_failover driver provides an automated failover mechanism via APIs
11	to create and destroy a failover master netdev and mananges a primary and	11	to create and destroy a failover master netdev and manages a primary and
12	standby slave netdevs that get registered via the generic failover	12	standby slave netdevs that get registered via the generic failover
13	infrastructrure.	13	infrastructure.
14		14
15	The failover netdev acts a master device and controls 2 slave devices. The	15	The failover netdev acts a master device and controls 2 slave devices. The
16	original paravirtual interface is registered as 'standby' slave netdev and	16	original paravirtual interface is registered as 'standby' slave netdev and
@@ -29,7 +29,7 @@ virtio-net accelerated datapath: STANDBY mode · 12 unmodified lines
29	=============================================	29	=============================================
30		30
31	net_failover enables hypervisor controlled accelerated datapath to virtio-net	31	net_failover enables hypervisor controlled accelerated datapath to virtio-net
32	enabled VMs in a transparent manner with no/minimal guest userspace chanages.	32	enabled VMs in a transparent manner with no/minimal guest userspace changes.
33		33
34	To support this, the hypervisor needs to enable VIRTIO_NET_F_STANDBY	34	To support this, the hypervisor needs to enable VIRTIO_NET_F_STANDBY
35	feature on the virtio-net interface and assign the same MAC address to both	35	feature on the virtio-net interface and assign the same MAC address to both

Documentation/networking/phy.rst+3−2

@@ -487,8 +487,9 @@ phy_register_fixup_for_id():: · 486 unmodified lines
487	The stubs set one of the two matching criteria, and set the other one to	487	The stubs set one of the two matching criteria, and set the other one to
488	match anything.	488	match anything.
489		489
490	When phy_register_fixup() or \_for_uid()/\_for_id() is called at module,	490	When phy_register_fixup() or \_for_uid()/\_for_id() is called at module load
491	unregister fixup and free allocate memory are required.	491	time, the module needs to unregister the fixup and free allocated memory when
		492	it's unloaded.
492		493
493	Call one of following function before unloading module::	494	Call one of following function before unloading module::
494		495

Documentation/networking/rds.txt+1−1

@@ -159,7 +159,7 @@ Socket Interface · 158 unmodified lines
159	set SO_RDS_TRANSPORT on a socket for which the transport has	159	set SO_RDS_TRANSPORT on a socket for which the transport has
160	been previously attached explicitly (by SO_RDS_TRANSPORT) or	160	been previously attached explicitly (by SO_RDS_TRANSPORT) or
161	implicitly (via bind(2)) will return an error of EOPNOTSUPP.	161	implicitly (via bind(2)) will return an error of EOPNOTSUPP.
162	An attempt to set SO_RDS_TRANSPPORT to RDS_TRANS_NONE will	162	An attempt to set SO_RDS_TRANSPORT to RDS_TRANS_NONE will
163	always return EINVAL.	163	always return EINVAL.
164		164
165	RDMA for RDS	165	RDMA for RDS

Documentation/power/index.rst+0−1

@@ -13,7 +13,6 @@ Power Management · 12 unmodified lines
13	drivers-testing	13	drivers-testing
14	energy-model	14	energy-model
15	freezing-of-tasks	15	freezing-of-tasks
16	interface
17	opp	16	opp
18	pci	17	pci
19	pm_qos_interface	18	pm_qos_interface

Documentation/sphinx/parallel-wrapper.sh+1−1

@@ -30,4 +30,4 @@ if [ -n "$parallel" ] ; then · 29 unmodified lines
30	parallel="-j$parallel"	30	parallel="-j$parallel"
31	fi	31	fi
32		32
33	exec "$sphinx" "$parallel" "$@"	33	exec "$sphinx" $parallel "$@"

Documentation/virt/kvm/api.rst+18−15

@@ -4611,35 +4611,38 @@ unpins the VPA pages and releases all the device pages that are used to · 4610 unmodified lines
4611	track the secure pages by hypervisor.	4611	track the secure pages by hypervisor.
4612		4612
4613	4.122 KVM_S390_NORMAL_RESET	4613	4.122 KVM_S390_NORMAL_RESET
		4614	---------------------------
4614		4615
4615	Capability: KVM_CAP_S390_VCPU_RESETS	4616	:Capability: KVM_CAP_S390_VCPU_RESETS
4616	Architectures: s390	4617	:Architectures: s390
4617	Type: vcpu ioctl	4618	:Type: vcpu ioctl
4618	Parameters: none	4619	:Parameters: none
4619	Returns: 0	4620	:Returns: 0
4620		4621
4621	This ioctl resets VCPU registers and control structures according to	4622	This ioctl resets VCPU registers and control structures according to
4622	the cpu reset definition in the POP (Principles Of Operation).	4623	the cpu reset definition in the POP (Principles Of Operation).
4623		4624
4624	4.123 KVM_S390_INITIAL_RESET	4625	4.123 KVM_S390_INITIAL_RESET
		4626	----------------------------
4625		4627
4626	Capability: none	4628	:Capability: none
4627	Architectures: s390	4629	:Architectures: s390
4628	Type: vcpu ioctl	4630	:Type: vcpu ioctl
4629	Parameters: none	4631	:Parameters: none
4630	Returns: 0	4632	:Returns: 0
4631		4633
4632	This ioctl resets VCPU registers and control structures according to	4634	This ioctl resets VCPU registers and control structures according to
4633	the initial cpu reset definition in the POP. However, the cpu is not	4635	the initial cpu reset definition in the POP. However, the cpu is not
4634	put into ESA mode. This reset is a superset of the normal reset.	4636	put into ESA mode. This reset is a superset of the normal reset.
4635		4637
4636	4.124 KVM_S390_CLEAR_RESET	4638	4.124 KVM_S390_CLEAR_RESET
		4639	--------------------------
4637		4640
4638	Capability: KVM_CAP_S390_VCPU_RESETS	4641	:Capability: KVM_CAP_S390_VCPU_RESETS
4639	Architectures: s390	4642	:Architectures: s390
4640	Type: vcpu ioctl	4643	:Type: vcpu ioctl
4641	Parameters: none	4644	:Parameters: none
4642	Returns: 0	4645	:Returns: 0
4643		4646
4644	This ioctl resets VCPU registers and control structures according to	4647	This ioctl resets VCPU registers and control structures according to
4645	the clear cpu reset definition in the POP. However, the cpu is not put	4648	the clear cpu reset definition in the POP. However, the cpu is not put

Documentation/x86/index.rst+0−1

@@ -19,7 +19,6 @@ x86-specific Documentation · 18 unmodified lines
19	tlb	19	tlb
20	mtrr	20	mtrr
21	pat	21	pat
22	intel_mpx
23	intel-iommu	22	intel-iommu
24	intel_txt	23	intel_txt
25	amd-memory-encryption	24	amd-memory-encryption

MAINTAINERS+16−19

 M:	Yangtao Li <tiny.windzz@gmail.com>
 L:	linux-pm@vger.kernel.org
 S:	Maintained
-F:	Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt
+F:	Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
 F:	drivers/cpufreq/sun50i-cpufreq-nvmem.c
 ALLWINNER CRYPTO DRIVERS
 S:	Maintained
 R:	Enric Balletbo i Serra <enric.balletbo@collabora.com>
 R:	Guenter Roeck <groeck@chromium.org>
-F:	Documentation/devicetree/bindings/sound/google,cros-ec-codec.txt
+F:	Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml
 F:	sound/soc/codecs/cros_ec_codec.*
 CIRRUS LOGIC AUDIO CODEC DRIVERS
 CISCO VIC ETHERNET NIC DRIVER
 M:	Christian Benvenuti <benve@cisco.com>
 M:	Govindarajulu Varadarajan <_govind@gmx.com>
-M:	Parvi Kaustubhi <pkaustub@cisco.com>
 S:	Supported
 F:	drivers/net/ethernet/cisco/enic/
 T:	git git://linuxtv.org/media_tree.git
 S:	Maintained
 F:	drivers/media/platform/sunxi/sun6i-csi/
-F:	Documentation/devicetree/bindings/media/sun6i-csi.txt
+F:	Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
 CW1200 WLAN driver
 M:	Solomon Peachy <pizza@shaftnet.org>
 F:	include/uapi/rdma/cxgb4-abi.h
 CXGB4VF ETHERNET DRIVER (CXGB4VF)
-M:	Casey Leedom <leedom@chelsio.com>
+M:	Vishal Kulkarni <vishal@gmail.com>
 L:	netdev@vger.kernel.org
 W:	http://www.chelsio.com
 S:	Supported
 T:	git git://anongit.freedesktop.org/drm/drm-misc
 S:	Maintained
 F:	drivers/gpu/drm/stm
-F:	Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
+F:	Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml
 DRM DRIVERS FOR TI LCDC
 M:	Jyri Sarha <jsarha@ti.com>
 F:	drivers/scsi/be2iscsi/
 Emulex 10Gbps NIC BE2, BE3-R, Lancer, Skyhawk-R DRIVER (be2net)
-M:	Sathya Perla <sathya.perla@broadcom.com>
 M:	Ajit Khaparde <ajit.khaparde@broadcom.com>
 M:	Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>
 M:	Somnath Kotur <somnath.kotur@broadcom.com>
 M:	"K. Y. Srinivasan" <kys@microsoft.com>
 M:	Haiyang Zhang <haiyangz@microsoft.com>
 M:	Stephen Hemminger <sthemmin@microsoft.com>
-M:	Sasha Levin <sashal@kernel.org>
+M:	Wei Liu <wei.liu@kernel.org>
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git
 L:	linux-hyperv@vger.kernel.org
 S:	Supported
 M:	Andreas Klinger <ak@it-klinger.de>
 L:	linux-iio@vger.kernel.org
 S:	Maintained
-F:	Documentation/devicetree/bindings/iio/proximity/maxbotix,mb1232.txt
+F:	Documentation/devicetree/bindings/iio/proximity/maxbotix,mb1232.yaml
 F:	drivers/iio/proximity/mb1232.c
 MAXIM MAX77650 PMIC MFD DRIVER
 L:	linux-media@vger.kernel.org
 T:	git git://linuxtv.org/media_tree.git
 S:	Supported
-F:	Documentation/devicetree/bindings/media/st,stm32-dcmi.txt
+F:	Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
 F:	drivers/media/platform/stm32/stm32-dcmi.c
 MEDIA DRIVERS FOR NVIDIA TEGRA - VDE
 F:	drivers/usb/image/microtek.*
 MIPS
-M:	Ralf Baechle <ralf@linux-mips.org>
+M:	Thomas Bogendoerfer <tsbogend@alpha.franken.de>
-M:	Paul Burton <paulburton@kernel.org>
 L:	linux-mips@vger.kernel.org
 W:	http://www.linux-mips.org/
-T:	git git://git.linux-mips.org/pub/scm/ralf/linux.git
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git
-Q:	http://patchwork.linux-mips.org/project/linux-mips/list/
+Q:	https://patchwork.kernel.org/project/linux-mips/list/
-S:	Supported
+S:	Maintained
 F:	Documentation/devicetree/bindings/mips/
 F:	Documentation/mips/
 F:	arch/mips/
 L:	linux-pci@vger.kernel.org
 S:	Maintained
 F:	Documentation/devicetree/bindings/pci/cdns,*.txt
-F:	drivers/pci/controller/pcie-cadence*
+F:	drivers/pci/controller/cadence/
 PCI DRIVER FOR FREESCALE LAYERSCAPE
 M:	Minghuan Lian <minghuan.Lian@nxp.com>
 L:	linux-pci@vger.kernel.org
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Supported
-F:	Documentation/devicetree/bindings/pci/pci-thunder-*
 F:	drivers/pci/controller/pci-thunder-*
 PCIE DRIVER FOR HISILICON
 F:	include/linux/reset.h
 F:	include/linux/reset/
 F:	include/linux/reset-controller.h
-K:      \b(?:devm_|of_)?reset_control(?:ler_[a-z]+|_[a-z_]+)?\b
+K:	\b(?:devm_|of_)?reset_control(?:ler_[a-z]+|_[a-z_]+)?\b
 RESTARTABLE SEQUENCES SUPPORT
 M:	Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
 F:	drivers/pwm/pwm-stm32*
 F:	include/linux/*/stm32-*tim*
 F:	Documentation/ABI/testing/*timer-stm32
-F:	Documentation/devicetree/bindings/*/stm32-*timer*
+F:	Documentation/devicetree/bindings/*/*stm32-*timer*
 F:	Documentation/devicetree/bindings/pwm/pwm-stm32*
 STMMAC ETHERNET DRIVER
 R:	Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 S:	Maintained
 F:	drivers/tty/serial/8250/8250_dw.c
+F:	drivers/tty/serial/8250/8250_dwlib.*
+F:	drivers/tty/serial/8250/8250_lpss.c
 SYNOPSYS DESIGNWARE APB GPIO DRIVER
 M:	Hoan Tran <hoan@os.amperecomputing.com>

Makefile+5−3

 VERSION = 5
 PATCHLEVEL = 6
 SUBLEVEL = 0
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc6
 NAME = Kleptomaniac Octopus
 # *DOCUMENTATION*
 #
 # If KBUILD_VERBOSE equals 0 then the above command will be hidden.
 # If KBUILD_VERBOSE equals 1 then the above command is displayed.
+# If KBUILD_VERBOSE equals 2 then give the reason why each target is rebuilt.
 #
 # To put more focus on warnings, be less verbose as default
 # Use 'make V=1' to see the full commands
 %.dtb: include/config/kernel.release scripts_dtc
 	$(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@
-PHONY += dtbs dtbs_install dt_binding_check
+PHONY += dtbs dtbs_install dtbs_check
 dtbs dtbs_check: include/config/kernel.release scripts_dtc
 	$(Q)$(MAKE) $(build)=$(dtstree)
 scripts_dtc: scripts_basic
 	$(Q)$(MAKE) $(build)=scripts/dtc
+PHONY += dt_binding_check
 dt_binding_check: scripts_dtc
 	$(Q)$(MAKE) $(build)=Documentation/devicetree/bindings
 -include $(foreach f,$(existing-targets),$(dir $(f)).$(notdir $(f)).cmd)
-endif # config-targets
+endif # config-build
 endif # mixed-build
 endif # need-sub-make

arch/Kconfig+3−2

 config HAVE_RELIABLE_STACKTRACE
 	bool
 	help
-	  Architecture has a save_stack_trace_tsk_reliable() function which
+	  Architecture has either save_stack_trace_tsk_reliable() or
-	  only returns a stack trace if it can guarantee the trace is reliable.
+	  arch_stack_walk_reliable() function which only returns a stack trace
+	  if it can guarantee the trace is reliable.
 config HAVE_ARCH_HASH
 	bool

arch/arc/Kconfig+2−2

@@ -154,7 +154,7 @@ config ARC_CPU_HS · 153 unmodified lines
154	help	154	help
155	Support for ARC HS38x Cores based on ARCv2 ISA	155	Support for ARC HS38x Cores based on ARCv2 ISA
156	The notable features are:	156	The notable features are:
157	- SMP configurations of upto 4 core with coherency	157	- SMP configurations of up to 4 cores with coherency
158	- Optional L2 Cache and IO-Coherency	158	- Optional L2 Cache and IO-Coherency
159	- Revised Interrupt Architecture (multiple priorites, reg banks,	159	- Revised Interrupt Architecture (multiple priorites, reg banks,
160	auto stack switch, auto regfile save/restore)	160	auto stack switch, auto regfile save/restore)
@@ -192,7 +192,7 @@ config ARC_SMP_HALT_ON_RESET · 31 unmodified lines
192	help	192	help
193	In SMP configuration cores can be configured as Halt-on-reset	193	In SMP configuration cores can be configured as Halt-on-reset
194	or they could all start at same time. For Halt-on-reset, non	194	or they could all start at same time. For Halt-on-reset, non
195	masters are parked until Master kicks them so they can start of	195	masters are parked until Master kicks them so they can start off
196	at designated entry point. For other case, all jump to common	196	at designated entry point. For other case, all jump to common
197	entry point and spin wait for Master's signal.	197	entry point and spin wait for Master's signal.
198		198

arch/arc/configs/nps_defconfig+0−2

 CONFIG_MODULE_FORCE_LOAD=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARC_PLAT_EZNPS=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=4096

arch/arc/configs/nsimosci_defconfig+0−2

 CONFIG_KPROBES=y
 CONFIG_MODULES=y
 # CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci"
 # CONFIG_COMPACTION is not set
 CONFIG_NET=y

arch/arc/configs/nsimosci_hs_defconfig+0−2

 CONFIG_KPROBES=y
 CONFIG_MODULES=y
 # CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
 CONFIG_ISA_ARCV2=y
 CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs"
 # CONFIG_COMPACTION is not set

arch/arc/configs/nsimosci_hs_smp_defconfig+0−2

 CONFIG_KPROBES=y
 CONFIG_MODULES=y
 # CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
 CONFIG_ISA_ARCV2=y
 CONFIG_SMP=y
 # CONFIG_ARC_TIMERS_64BIT is not set

arch/arc/include/asm/fpu.h+2−0

@@ -43,6 +43,8 @@ extern void fpu_init_task(struct pt_regs *regs); · 42 unmodified lines
43		43
44	#endif /* !CONFIG_ISA_ARCOMPACT */	44	#endif /* !CONFIG_ISA_ARCOMPACT */
45		45
		46	struct task_struct;
		47
46	extern void fpu_save_restore(struct task_struct p, struct task_struct n);	48	extern void fpu_save_restore(struct task_struct p, struct task_struct n);
47		49
48	#else /* !CONFIG_ARC_FPU_SAVE_RESTORE */	50	#else /* !CONFIG_ARC_FPU_SAVE_RESTORE */

arch/arc/include/asm/linkage.h+2−0

@@ -29,6 +29,8 @@ · 28 unmodified lines
29	.endm	29	.endm
30		30
31	#define ASM_NL ` /* use '`' to mark new line in macro */	31	#define ASM_NL ` /* use '`' to mark new line in macro */
		32	#define __ALIGN .align 4
		33	#define __ALIGN_STR __stringify(__ALIGN)
32		34
33	/* annotation for data we want in DCCM - if enabled in .config */	35	/* annotation for data we want in DCCM - if enabled in .config */
34	.macro ARCFP_DATA nm	36	.macro ARCFP_DATA nm

arch/arc/kernel/setup.c+1−1

 #include <linux/delay.h>
 #include <linux/root_dev.h>
 #include <linux/clk.h>
-#include <linux/clk-provider.h>
 #include <linux/clocksource.h>
 #include <linux/console.h>
 #include <linux/module.h>
 #include <linux/cpu.h>
+#include <linux/of_clk.h>
 #include <linux/of_fdt.h>
 #include <linux/of.h>
 #include <linux/cache.h>

arch/arc/kernel/troubleshoot.c+12−15

 			if (IS_ERR(nm))
 				nm = "?";
 		}
-		pr_info("    @off 0x%lx in [%s]\n"
+		pr_info("  @off 0x%lx in [%s]  VMA: 0x%08lx to 0x%08lx\n",
-			"    VMA: 0x%08lx to 0x%08lx\n",
 			vma->vm_start < TASK_UNMAPPED_BASE ?
 				address : address - vma->vm_start,
 			nm, vma->vm_start, vma->vm_end);
 	unsigned int vec, cause_code;
 	unsigned long address;
-	pr_info("\n[ECR   ]: 0x%08lx => ", regs->event);
 	/* For Data fault, this is data address not instruction addr */
 	address = current->thread.fault_address;
 	/* For DTLB Miss or ProtV, display the memory involved too */
 	if (vec == ECR_V_DTLB_MISS) {
-		pr_cont("Invalid %s @ 0x%08lx by insn @ 0x%08lx\n",
+		pr_cont("Invalid %s @ 0x%08lx by insn @ %pS\n",
 		       (cause_code == 0x01) ? "Read" :
 		       ((cause_code == 0x02) ? "Write" : "EX"),
-		       address, regs->ret);
+		       address, (void *)regs->ret);
 	} else if (vec == ECR_V_ITLB_MISS) {
 		pr_cont("Insn could not be fetched\n");
 	} else if (vec == ECR_V_MACH_CHK) {
 	show_ecr_verbose(regs);
-	pr_info("[EFA   ]: 0x%08lx\n[BLINK ]: %pS\n[ERET  ]: %pS\n",
-		current->thread.fault_address,
-		(void *)regs->blink, (void *)regs->ret);
 	if (user_mode(regs))
 		show_faulting_vma(regs->ret); /* faulting code, not data */
-	pr_info("[STAT32]: 0x%08lx", regs->status32);
+	pr_info("ECR: 0x%08lx EFA: 0x%08lx ERET: 0x%08lx\n",
+		regs->event, current->thread.fault_address, regs->ret);
+	pr_info("STAT32: 0x%08lx", regs->status32);
 #define STS_BIT(r, bit)	r->status32 & STATUS_##bit##_MASK ? #bit" " : ""
 #ifdef CONFIG_ISA_ARCOMPACT
-	pr_cont(" : %2s%2s%2s%2s%2s%2s%2s\n",
+	pr_cont(" [%2s%2s%2s%2s%2s%2s%2s]",
 			(regs->status32 & STATUS_U_MASK) ? "U " : "K ",
 			STS_BIT(regs, DE), STS_BIT(regs, AE),
 			STS_BIT(regs, A2), STS_BIT(regs, A1),
 			STS_BIT(regs, E2), STS_BIT(regs, E1));
 #else
-	pr_cont(" : %2s%2s%2s%2s\n",
+	pr_cont(" [%2s%2s%2s%2s]",
 			STS_BIT(regs, IE),
 			(regs->status32 & STATUS_U_MASK) ? "U " : "K ",
 			STS_BIT(regs, DE), STS_BIT(regs, AE));
 #endif
-	pr_info("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n",
+	pr_cont("  BTA: 0x%08lx\n", regs->bta);
-		regs->bta, regs->sp, regs->fp);
+	pr_info("BLK: %pS\n SP: 0x%08lx  FP: 0x%08lx\n",
+		(void *)regs->blink, regs->sp, regs->fp);
 	pr_info("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n",
 	       regs->lp_start, regs->lp_end, regs->lp_count);

arch/arm/Makefile+3−1

 ifeq ($(CONFIG_STACKPROTECTOR_PER_TASK),y)
 prepare: stack_protector_prepare
 stack_protector_prepare: prepare0
-	$(eval KBUILD_CFLAGS += \
+	$(eval SSP_PLUGIN_CFLAGS := \
 		-fplugin-arg-arm_ssp_per_task_plugin-tso=$(shell	\
 			awk '{if ($$2 == "THREAD_SZ_ORDER") print $$3;}'\
 				include/generated/asm-offsets.h)	\
 		-fplugin-arg-arm_ssp_per_task_plugin-offset=$(shell	\
 			awk '{if ($$2 == "TI_STACK_CANARY") print $$3;}'\
 				include/generated/asm-offsets.h))
+	$(eval KBUILD_CFLAGS += $(SSP_PLUGIN_CFLAGS))
+	$(eval GCC_PLUGINS_CFLAGS += $(SSP_PLUGIN_CFLAGS))
 endif
 all:	$(notdir $(KBUILD_IMAGE))

arch/arm/boot/compressed/Makefile+2−2

 		$(libfdt) $(libfdt_hdrs) hyp-stub.S
 KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING
-KBUILD_CFLAGS += $(DISABLE_ARM_SSP_PER_TASK_PLUGIN)
 ifeq ($(CONFIG_FUNCTION_TRACER),y)
 ORIG_CFLAGS := $(KBUILD_CFLAGS)
 CFLAGS_fdt_rw.o := $(nossp-flags-y)
 CFLAGS_fdt_wip.o := $(nossp-flags-y)
-ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin -I$(obj)
+ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin \
+	     -I$(obj) $(DISABLE_ARM_SSP_PER_TASK_PLUGIN)
 asflags-y := -DZIMAGE
 # Supply kernel BSS size to the decompressor via a linker symbol.

arch/arm/boot/dts/am437x-idk-evm.dts+2−2

@@ -526,11 +526,11 @@ · 525 unmodified lines
526	* Supply voltage supervisor on board will not allow opp50 so	526	* Supply voltage supervisor on board will not allow opp50 so
527	* disable it and set opp100 as suspend OPP.	527	* disable it and set opp100 as suspend OPP.
528	*/	528	*/
529	opp50@300000000 {	529	opp50-300000000 {
530	status = "disabled";	530	status = "disabled";
531	};	531	};
532		532
533	opp100@600000000 {	533	opp100-600000000 {
534	opp-suspend;	534	opp-suspend;
535	};	535	};
536	};	536	};

arch/arm/boot/dts/bcm2711-rpi-4-b.dts+3−0

 	aliases {
 		ethernet0 = &genet;
+		pcie0 = &pcie0;
 	};
 	leds {
 		pwr {
 			label = "PWR";
 			gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+			default-state = "keep";
+			linux,default-trigger = "default-on";
 		};
 	};

arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts+2−0

 		pwr {
 			label = "PWR";
 			gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+			default-state = "keep";
+			linux,default-trigger = "default-on";
 		};
 	};
 };

arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts+2−0

@@ -27,6 +27,8 @@ · 26 unmodified lines
27	pwr {	27	pwr {
28	label = "PWR";	28	label = "PWR";
29	gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;	29	gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
		30	default-state = "keep";
		31	linux,default-trigger = "default-on";
30	};	32	};
31	};	33	};
32		34

arch/arm/boot/dts/dra7-evm.dts+2−2

@@ -61,10 +61,10 @@ · 60 unmodified lines
61	regulator-max-microvolt = <1800000>;	61	regulator-max-microvolt = <1800000>;
62	};	62	};
63		63
64	evm_3v3: fixedregulator-evm3v3 {	64	vsys_3v3: fixedregulator-vsys3v3 {
65	/* Output of Cntlr A of TPS43351-Q1 on dra7-evm */	65	/* Output of Cntlr A of TPS43351-Q1 on dra7-evm */
66	compatible = "regulator-fixed";	66	compatible = "regulator-fixed";
67	regulator-name = "evm_3v3";	67	regulator-name = "vsys_3v3";
68	regulator-min-microvolt = <3300000>;	68	regulator-min-microvolt = <3300000>;
69	regulator-max-microvolt = <3300000>;	69	regulator-max-microvolt = <3300000>;
70	vin-supply = <&evm_12v0>;	70	vin-supply = <&evm_12v0>;

arch/arm/boot/dts/dra7-l4.dtsi+4−0

 				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;
 				clock-names = "fck";
 				interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+				ti,timer-pwm;
 			};
 		};
 				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
 				clock-names = "fck";
 				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
+				ti,timer-pwm;
 			};
 		};
 				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
 				clock-names = "fck";
 				interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+				ti,timer-pwm;
 			};
 		};
 				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
 				clock-names = "fck";
 				interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+				ti,timer-pwm;
 			};
 		};

arch/arm/boot/dts/dra7.dtsi+2−0

 				device_type = "pci";
 				ranges = <0x81000000 0 0          0x03000 0 0x00010000
 					  0x82000000 0 0x20013000 0x13000 0 0xffed000>;
+				dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
 				bus-range = <0x00 0xff>;
 				#interrupt-cells = <1>;
 				num-lanes = <1>;
 				device_type = "pci";
 				ranges = <0x81000000 0 0          0x03000 0 0x00010000
 					  0x82000000 0 0x30013000 0x13000 0 0xffed000>;
+				dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
 				bus-range = <0x00 0xff>;
 				#interrupt-cells = <1>;
 				num-lanes = <1>;

arch/arm/boot/dts/dra76x.dtsi+5−0

@@ -128,3 +128,8 @@ · 127 unmodified lines
128	&usb4_tm {	128	&usb4_tm {
129	status = "disabled";	129	status = "disabled";
130	};	130	};
		131
		132	&mmc3 {
		133	/* dra76x is not affected by i887 */
		134	max-frequency = <96000000>;
		135	};

arch/arm/boot/dts/dra7xx-clocks.dtsi+2−10

 		clock-div = <1>;
 	};
-	ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
-		ti,bit-shift = <24>;
-		reg = <0x0520>;
-		assigned-clocks = <&ipu1_gfclk_mux>;
-		assigned-clock-parents = <&dpll_core_h22x2_ck>;
-	};
 	dummy_ck: dummy_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 			compatible = "ti,clkctrl";
 			reg = <0x20 0x4>;
 			#clock-cells = <2>;
+			assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
+			assigned-clock-parents = <&dpll_core_h22x2_ck>;
 		};
 		ipu_clkctrl: ipu-clkctrl@50 {

arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts+2−2

@@ -275,7 +275,7 @@ · 274 unmodified lines
275		275
276	/* SRAM on Colibri nEXT_CS0 */	276	/* SRAM on Colibri nEXT_CS0 */
277	sram@0,0 {	277	sram@0,0 {
278	compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";	278	compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
279	reg = <0 0 0x00010000>;	279	reg = <0 0 0x00010000>;
280	#address-cells = <1>;	280	#address-cells = <1>;
281	#size-cells = <1>;	281	#size-cells = <1>;
@@ -286,7 +286,7 @@ · 4 unmodified lines
286		286
287	/* SRAM on Colibri nEXT_CS1 */	287	/* SRAM on Colibri nEXT_CS1 */
288	sram@1,0 {	288	sram@1,0 {
289	compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";	289	compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
290	reg = <1 0 0x00010000>;	290	reg = <1 0 0x00010000>;
291	#address-cells = <1>;	291	#address-cells = <1>;
292	#size-cells = <1>;	292	#size-cells = <1>;

arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi+0−1

@@ -192,7 +192,6 @@ · 191 unmodified lines
192	pinctrl-0 = <&pinctrl_usdhc4>;	192	pinctrl-0 = <&pinctrl_usdhc4>;
193	bus-width = <8>;	193	bus-width = <8>;
194	non-removable;	194	non-removable;
195	vmmc-supply = <&vdd_emmc_1p8>;
196	status = "disabled";	195	status = "disabled";
197	};	196	};
198		197

arch/arm/boot/dts/imx7-colibri.dtsi+0−1

@@ -336,7 +336,6 @@ · 335 unmodified lines
336	assigned-clock-rates = <400000000>;	336	assigned-clock-rates = <400000000>;
337	bus-width = <8>;	337	bus-width = <8>;
338	fsl,tuning-step = <2>;	338	fsl,tuning-step = <2>;
339	max-frequency = <100000000>;
340	vmmc-supply = <&reg_module_3v3>;	339	vmmc-supply = <&reg_module_3v3>;
341	vqmmc-supply = <&reg_DCDC3>;	340	vqmmc-supply = <&reg_DCDC3>;
342	non-removable;	341	non-removable;

arch/arm/boot/dts/imx7d.dtsi+3−3

@@ -44,7 +44,7 @@ · 43 unmodified lines
44	opp-hz = /bits/ 64 <792000000>;	44	opp-hz = /bits/ 64 <792000000>;
45	opp-microvolt = <1000000>;	45	opp-microvolt = <1000000>;
46	clock-latency-ns = <150000>;	46	clock-latency-ns = <150000>;
47	opp-supported-hw = <0xd>, <0xf>;	47	opp-supported-hw = <0xd>, <0x7>;
48	opp-suspend;	48	opp-suspend;
49	};	49	};
50		50
@@ -52,7 +52,7 @@ · 1 unmodified line
52	opp-hz = /bits/ 64 <996000000>;	52	opp-hz = /bits/ 64 <996000000>;
53	opp-microvolt = <1100000>;	53	opp-microvolt = <1100000>;
54	clock-latency-ns = <150000>;	54	clock-latency-ns = <150000>;
55	opp-supported-hw = <0xc>, <0xf>;	55	opp-supported-hw = <0xc>, <0x7>;
56	opp-suspend;	56	opp-suspend;
57	};	57	};
58		58
@@ -60,7 +60,7 @@ · 1 unmodified line
60	opp-hz = /bits/ 64 <1200000000>;	60	opp-hz = /bits/ 64 <1200000000>;
61	opp-microvolt = <1225000>;	61	opp-microvolt = <1225000>;
62	clock-latency-ns = <150000>;	62	clock-latency-ns = <150000>;
63	opp-supported-hw = <0x8>, <0xf>;	63	opp-supported-hw = <0x8>, <0x3>;
64	opp-suspend;	64	opp-suspend;
65	};	65	};
66	};	66	};

arch/arm/boot/dts/ls1021a.dtsi+2−2

@@ -747,7 +747,7 @@ · 746 unmodified lines
747	};	747	};
748		748
749	mdio0: mdio@2d24000 {	749	mdio0: mdio@2d24000 {
750	compatible = "fsl,etsec2-mdio";	750	compatible = "gianfar";
751	device_type = "mdio";	751	device_type = "mdio";
752	#address-cells = <1>;	752	#address-cells = <1>;
753	#size-cells = <0>;	753	#size-cells = <0>;
@@ -756,7 +756,7 @@ · 2 unmodified lines
756	};	756	};
757		757
758	mdio1: mdio@2d64000 {	758	mdio1: mdio@2d64000 {
759	compatible = "fsl,etsec2-mdio";	759	compatible = "gianfar";
760	device_type = "mdio";	760	device_type = "mdio";
761	#address-cells = <1>;	761	#address-cells = <1>;
762	#size-cells = <0>;	762	#size-cells = <0>;

arch/arm/boot/dts/motorola-mapphone-common.dtsi+11−2

 		pwm-names = "enable", "direction";
 		direction-duty-cycle-ns = <10000000>;
 	};
+	backlight: backlight {
+		compatible = "led-backlight";
+		leds = <&backlight_led>;
+		brightness-levels = <31 63 95 127 159 191 223 255>;
+		default-brightness-level = <6>;
+	};
 };
 &dss {
 		vddi-supply = <&lcd_regulator>;
 		reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;	/* gpio101 */
+		backlight = <&backlight>;
 		width-mm = <50>;
 		height-mm = <89>;
 		ramp-up-us = <1024>;
 		ramp-down-us = <8193>;
-		led@0 {
+		backlight_led: led@0 {
 			reg = <0>;
 			led-sources = <2>;
 			ti,led-mode = <0>;
 			label = ":backlight";
-			linux,default-trigger = "backlight";
 		};
 		led@1 {

arch/arm/boot/dts/r8a7779.dtsi+1−1

@@ -377,7 +377,7 @@ · 376 unmodified lines
377	};	377	};
378		378
379	sata: sata@fc600000 {	379	sata: sata@fc600000 {
380	compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";	380	compatible = "renesas,sata-r8a7779";
381	reg = <0xfc600000 0x200000>;	381	reg = <0xfc600000 0x200000>;
382	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;	382	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
383	clocks = <&mstp1_clks R8A7779_CLK_SATA>;	383	clocks = <&mstp1_clks R8A7779_CLK_SATA>;

arch/arm/configs/bcm2835_defconfig+1−0

@@ -178,6 +178,7 @@ CONFIG_SCHED_TRACER=y · 177 unmodified lines
178	CONFIG_STACK_TRACER=y	178	CONFIG_STACK_TRACER=y
179	CONFIG_FUNCTION_PROFILER=y	179	CONFIG_FUNCTION_PROFILER=y
180	CONFIG_TEST_KSTRTOX=y	180	CONFIG_TEST_KSTRTOX=y
		181	CONFIG_DEBUG_FS=y
181	CONFIG_KGDB=y	182	CONFIG_KGDB=y
182	CONFIG_KGDB_KDB=y	183	CONFIG_KGDB_KDB=y
183	CONFIG_STRICT_DEVMEM=y	184	CONFIG_STRICT_DEVMEM=y

arch/arm/configs/omap2plus_defconfig+1−0

@@ -375,6 +375,7 @@ CONFIG_BACKLIGHT_GENERIC=m · 374 unmodified lines
375	CONFIG_BACKLIGHT_PWM=m	375	CONFIG_BACKLIGHT_PWM=m
376	CONFIG_BACKLIGHT_PANDORA=m	376	CONFIG_BACKLIGHT_PANDORA=m
377	CONFIG_BACKLIGHT_GPIO=m	377	CONFIG_BACKLIGHT_GPIO=m
		378	CONFIG_BACKLIGHT_LED=m
378	CONFIG_FRAMEBUFFER_CONSOLE=y	379	CONFIG_FRAMEBUFFER_CONSOLE=y
379	CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y	380	CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
380	CONFIG_LOGO=y	381	CONFIG_LOGO=y

arch/arm/configs/socfpga_defconfig+1−0

@@ -157,6 +157,7 @@ CONFIG_NLS_ISO8859_1=y · 156 unmodified lines
157	CONFIG_PRINTK_TIME=y	157	CONFIG_PRINTK_TIME=y
158	CONFIG_DEBUG_INFO=y	158	CONFIG_DEBUG_INFO=y
159	CONFIG_MAGIC_SYSRQ=y	159	CONFIG_MAGIC_SYSRQ=y
		160	CONFIG_DEBUG_FS=y
160	CONFIG_DETECT_HUNG_TASK=y	161	CONFIG_DETECT_HUNG_TASK=y
161	# CONFIG_SCHED_DEBUG is not set	162	# CONFIG_SCHED_DEBUG is not set
162	CONFIG_FUNCTION_TRACER=y	163	CONFIG_FUNCTION_TRACER=y

arch/arm/include/asm/kvm_host.h+0−3

@@ -392,9 +392,6 @@ static inline void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu) {} · 391 unmodified lines
392	static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}	392	static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}
393	static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}	393	static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}
394		394
395	static inline void kvm_arm_vhe_guest_enter(void) {}
396	static inline void kvm_arm_vhe_guest_exit(void) {}
397
398	#define KVM_BP_HARDEN_UNKNOWN -1	395	#define KVM_BP_HARDEN_UNKNOWN -1
399	#define KVM_BP_HARDEN_WA_NEEDED 0	396	#define KVM_BP_HARDEN_WA_NEEDED 0
400	#define KVM_BP_HARDEN_NOT_REQUIRED 1	397	#define KVM_BP_HARDEN_NOT_REQUIRED 1

arch/arm/kernel/vdso.c+2−0

@@ -94,6 +94,8 @@ static bool __init cntvct_functional(void) · 93 unmodified lines
94	* this.	94	* this.
95	*/	95	*/
96	np = of_find_compatible_node(NULL, NULL, "arm,armv7-timer");	96	np = of_find_compatible_node(NULL, NULL, "arm,armv7-timer");
		97	if (!np)
		98	np = of_find_compatible_node(NULL, NULL, "arm,armv8-timer");
97	if (!np)	99	if (!np)
98	goto out_put;	100	goto out_put;
99		101

arch/arm/lib/copy_from_user.S+1−1

@@ -118,7 +118,7 @@ ENTRY(arm_copy_from_user) · 117 unmodified lines
118		118
119	ENDPROC(arm_copy_from_user)	119	ENDPROC(arm_copy_from_user)
120		120
121	.pushsection .fixup,"ax"	121	.pushsection .text.fixup,"ax"
122	.align 0	122	.align 0
123	copy_abort_preamble	123	copy_abort_preamble
124	ldmfd sp!, {r1, r2, r3}	124	ldmfd sp!, {r1, r2, r3}

arch/arm/mach-imx/Makefile+2−0

@@ -91,6 +91,8 @@ AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a · 90 unmodified lines
91	obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o	91	obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
92	obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o	92	obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o
93	endif	93	endif
		94	AFLAGS_resume-imx6.o :=-Wa,-march=armv7-a
		95	obj-$(CONFIG_SOC_IMX6) += resume-imx6.o
94	obj-$(CONFIG_SOC_IMX6) += pm-imx6.o	96	obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
95		97
96	obj-$(CONFIG_SOC_IMX1) += mach-imx1.o	98	obj-$(CONFIG_SOC_IMX1) += mach-imx1.o

arch/arm/mach-imx/common.h+2−2

 int imx_cpu_kill(unsigned int cpu);
 #ifdef CONFIG_SUSPEND
-void v7_cpu_resume(void);
 void imx53_suspend(void __iomem *ocram_vbase);
 extern const u32 imx53_suspend_sz;
 void imx6_suspend(void __iomem *ocram_vbase);
 #else
-static inline void v7_cpu_resume(void) {}
 static inline void imx53_suspend(void __iomem *ocram_vbase) {}
 static const u32 imx53_suspend_sz;
 static inline void imx6_suspend(void __iomem *ocram_vbase) {}
 #endif
+void v7_cpu_resume(void);
 void imx6_pm_ccm_init(const char *ccm_compat);
 void imx6q_pm_init(void);
 void imx6dl_pm_init(void);

arch/arm/mach-imx/resume-imx6.S+24−0

@@ -0,0 +1,24 @@
	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
	2	/*
	3	* Copyright 2014 Freescale Semiconductor, Inc.
	4	*/
	5
	6	#include <linux/linkage.h>
	7	#include <asm/assembler.h>
	8	#include <asm/asm-offsets.h>
	9	#include <asm/hardware/cache-l2x0.h>
	10	#include "hardware.h"
	11
	12	/*
	13	* The following code must assume it is running from physical address
	14	* where absolute virtual addresses to the data section have to be
	15	* turned into relative ones.
	16	*/
	17
	18	ENTRY(v7_cpu_resume)
	19	bl v7_invalidate_l1
	20	#ifdef CONFIG_CACHE_L2X0
	21	bl l2c310_early_resume
	22	#endif
	23	b cpu_resume
	24	ENDPROC(v7_cpu_resume)

arch/arm/mach-imx/suspend-imx6.S+0−14

@@ -327,17 +327,3 @@ resume: · 326 unmodified lines
327		327
328	ret lr	328	ret lr
329	ENDPROC(imx6_suspend)	329	ENDPROC(imx6_suspend)
330
331	/*
332	* The following code must assume it is running from physical address
333	* where absolute virtual addresses to the data section have to be
334	* turned into relative ones.
335	*/
336
337	ENTRY(v7_cpu_resume)
338	bl v7_invalidate_l1
339	#ifdef CONFIG_CACHE_L2X0
340	bl l2c310_early_resume
341	#endif
342	b cpu_resume
343	ENDPROC(v7_cpu_resume)

arch/arm/mach-meson/Kconfig+0−1

@@ -9,7 +9,6 @@ menuconfig ARCH_MESON · 8 unmodified lines
9	select CACHE_L2X0	9	select CACHE_L2X0
10	select PINCTRL	10	select PINCTRL
11	select PINCTRL_MESON	11	select PINCTRL_MESON
12	select COMMON_CLK
13	select HAVE_ARM_SCU if SMP	12	select HAVE_ARM_SCU if SMP
14	select HAVE_ARM_TWD if SMP	13	select HAVE_ARM_TWD if SMP
15		14

arch/arm/mach-omap2/Makefile+1−1

@@ -16,7 +16,7 @@ hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ · 15 unmodified lines
16	clock-common = clock.o	16	clock-common = clock.o
17	secure-common = omap-smc.o omap-secure.o	17	secure-common = omap-smc.o omap-secure.o
18		18
19	obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common)	19	obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
20	obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)	20	obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
21	obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)	21	obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
22	obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common)	22	obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common)

arch/arm/mach-omap2/io.c+0−2

 	omap_hwmod_init_postsetup();
 	omap_clk_soc_init = omap2420_dt_clk_init;
 	rate_table = omap2420_rate_table;
-	omap_secure_init();
 }
 void __init omap2420_init_late(void)
 	omap_hwmod_init_postsetup();
 	omap_clk_soc_init = omap2430_dt_clk_init;
 	rate_table = omap2430_rate_table;
-	omap_secure_init();
 }
 void __init omap2430_init_late(void)

arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts+1−1

@@ -327,7 +327,7 @@ · 326 unmodified lines
327	#size-cells = <0>;	327	#size-cells = <0>;
328		328
329	bus-width = <4>;	329	bus-width = <4>;
330	max-frequency = <50000000>;	330	max-frequency = <60000000>;
331		331
332	non-removable;	332	non-removable;
333	disable-wp;	333	disable-wp;

arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts+1−0

@@ -593,6 +593,7 @@ · 592 unmodified lines
593	compatible = "brcm,bcm43438-bt";	593	compatible = "brcm,bcm43438-bt";
594	interrupt-parent = <&gpio_intc>;	594	interrupt-parent = <&gpio_intc>;
595	interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;	595	interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
		596	interrupt-names = "host-wakeup";
596	shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;	597	shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
597	max-speed = <2000000>;	598	max-speed = <2000000>;
598	clocks = <&wifi32k>;	599	clocks = <&wifi32k>;

arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi+2−0

@@ -20,6 +20,8 @@ · 19 unmodified lines
20	};	20	};
21		21
22	&fman0 {	22	&fman0 {
		23	fsl,erratum-a050385;
		24
23	/* these aliases provide the FMan ports mapping */	25	/* these aliases provide the FMan ports mapping */
24	enet0: ethernet@e0000 {	26	enet0: ethernet@e0000 {
25	};	27	};

arch/arm64/boot/dts/freescale/imx8qxp-mek.dts+0−5

 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <0>;
 		};
-		ethphy1: ethernet-phy@1 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <1>;
-		};
 	};
 };

arch/arm64/boot/dts/intel/socfpga_agilex.dtsi+3−3

@@ -102,7 +102,7 @@ · 101 unmodified lines
102	};	102	};
103		103
104	gmac0: ethernet@ff800000 {	104	gmac0: ethernet@ff800000 {
105	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";	105	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
106	reg = <0xff800000 0x2000>;	106	reg = <0xff800000 0x2000>;
107	interrupts = <0 90 4>;	107	interrupts = <0 90 4>;
108	interrupt-names = "macirq";	108	interrupt-names = "macirq";
@@ -118,7 +118,7 @@ · 9 unmodified lines
118	};	118	};
119		119
120	gmac1: ethernet@ff802000 {	120	gmac1: ethernet@ff802000 {
121	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";	121	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
122	reg = <0xff802000 0x2000>;	122	reg = <0xff802000 0x2000>;
123	interrupts = <0 91 4>;	123	interrupts = <0 91 4>;
124	interrupt-names = "macirq";	124	interrupt-names = "macirq";
@@ -134,7 +134,7 @@ · 9 unmodified lines
134	};	134	};
135		135
136	gmac2: ethernet@ff804000 {	136	gmac2: ethernet@ff804000 {
137	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";	137	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
138	reg = <0xff804000 0x2000>;	138	reg = <0xff804000 0x2000>;
139	interrupts = <0 92 4>;	139	interrupts = <0 92 4>;
140	interrupt-names = "macirq";	140	interrupt-names = "macirq";

arch/arm64/configs/defconfig+1−1

@@ -773,7 +773,7 @@ CONFIG_ARCH_R8A774A1=y · 772 unmodified lines
773	CONFIG_ARCH_R8A774B1=y	773	CONFIG_ARCH_R8A774B1=y
774	CONFIG_ARCH_R8A774C0=y	774	CONFIG_ARCH_R8A774C0=y
775	CONFIG_ARCH_R8A7795=y	775	CONFIG_ARCH_R8A7795=y
776	CONFIG_ARCH_R8A7796=y	776	CONFIG_ARCH_R8A77960=y
777	CONFIG_ARCH_R8A77961=y	777	CONFIG_ARCH_R8A77961=y
778	CONFIG_ARCH_R8A77965=y	778	CONFIG_ARCH_R8A77965=y
779	CONFIG_ARCH_R8A77970=y	779	CONFIG_ARCH_R8A77970=y

arch/arm64/include/asm/arch_gicv3.h+1−1

@@ -32,7 +32,7 @@ static inline void gic_write_eoir(u32 irq) · 31 unmodified lines
32	isb();	32	isb();
33	}	33	}
34		34
35	static inline void gic_write_dir(u32 irq)	35	static __always_inline void gic_write_dir(u32 irq)
36	{	36	{
37	write_sysreg_s(irq, SYS_ICC_DIR_EL1);	37	write_sysreg_s(irq, SYS_ICC_DIR_EL1);
38	isb();	38	isb();

arch/arm64/include/asm/cache.h+1−1

@@ -69,7 +69,7 @@ static inline int icache_is_aliasing(void) · 68 unmodified lines
69	return test_bit(ICACHEF_ALIASING, &__icache_flags);	69	return test_bit(ICACHEF_ALIASING, &__icache_flags);
70	}	70	}
71		71
72	static inline int icache_is_vpipt(void)	72	static __always_inline int icache_is_vpipt(void)
73	{	73	{
74	return test_bit(ICACHEF_VPIPT, &__icache_flags);	74	return test_bit(ICACHEF_VPIPT, &__icache_flags);
75	}	75	}

arch/arm64/include/asm/cacheflush.h+1−1

@@ -145,7 +145,7 @@ extern void copy_to_user_page(struct vm_area_struct , struct page , · 144 unmodified lines
145	#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1	145	#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
146	extern void flush_dcache_page(struct page *);	146	extern void flush_dcache_page(struct page *);
147		147
148	static inline void __flush_icache_all(void)	148	static __always_inline void __flush_icache_all(void)
149	{	149	{
150	if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))	150	if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))
151	return;	151	return;

arch/arm64/include/asm/cpufeature.h+5−5

arch/arm64/include/asm/io.h+2−2

@@ -34,7 +34,7 @@ static inline void __raw_writew(u16 val, volatile void __iomem *addr) · 33 unmodified lines
34	}	34	}
35		35
36	#define __raw_writel __raw_writel	36	#define __raw_writel __raw_writel
37	static inline void __raw_writel(u32 val, volatile void __iomem *addr)	37	static __always_inline void __raw_writel(u32 val, volatile void __iomem *addr)
38	{	38	{
39	asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));	39	asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
40	}	40	}
@@ -69,7 +69,7 @@ static inline u16 __raw_readw(const volatile void __iomem *addr) · 28 unmodified lines
69	}	69	}
70		70
71	#define __raw_readl __raw_readl	71	#define __raw_readl __raw_readl
72	static inline u32 __raw_readl(const volatile void __iomem *addr)	72	static __always_inline u32 __raw_readl(const volatile void __iomem *addr)
73	{	73	{
74	u32 val;	74	u32 val;
75	asm volatile(ALTERNATIVE("ldr %w0, [%1]",	75	asm volatile(ALTERNATIVE("ldr %w0, [%1]",

arch/arm64/include/asm/kvm_emulate.h+24−24

arch/arm64/include/asm/kvm_host.h+0−32

@@ -626,38 +626,6 @@ static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} · 625 unmodified lines
626	static inline void kvm_clr_pmu_events(u32 clr) {}	626	static inline void kvm_clr_pmu_events(u32 clr) {}
627	#endif	627	#endif
628		628
629	static inline void kvm_arm_vhe_guest_enter(void)
630	{
631	local_daif_mask();
632
633	/*
634	* Having IRQs masked via PMR when entering the guest means the GIC
635	* will not signal the CPU of interrupts of lower priority, and the
636	* only way to get out will be via guest exceptions.
637	* Naturally, we want to avoid this.
638	*
639	* local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a
640	* dsb to ensure the redistributor is forwards EL2 IRQs to the CPU.
641	*/
642	pmr_sync();
643	}
644
645	static inline void kvm_arm_vhe_guest_exit(void)
646	{
647	/*
648	* local_daif_restore() takes care to properly restore PSTATE.DAIF
649	* and the GIC PMR if the host is using IRQ priorities.
650	*/
651	local_daif_restore(DAIF_PROCCTX_NOIRQ);
652
653	/*
654	* When we exit from the guest we change a number of CPU configuration
655	* parameters, such as traps. Make sure these changes take effect
656	* before running the host or additional guests.
657	*/
658	isb();
659	}
660
661	#define KVM_BP_HARDEN_UNKNOWN -1	629	#define KVM_BP_HARDEN_UNKNOWN -1
662	#define KVM_BP_HARDEN_WA_NEEDED 0	630	#define KVM_BP_HARDEN_WA_NEEDED 0
663	#define KVM_BP_HARDEN_NOT_REQUIRED 1	631	#define KVM_BP_HARDEN_NOT_REQUIRED 1

arch/arm64/include/asm/kvm_hyp.h+7−0

@@ -47,6 +47,13 @@ · 46 unmodified lines
47	#define read_sysreg_el2(r) read_sysreg_elx(r, _EL2, _EL1)	47	#define read_sysreg_el2(r) read_sysreg_elx(r, _EL2, _EL1)
48	#define write_sysreg_el2(v,r) write_sysreg_elx(v, r, _EL2, _EL1)	48	#define write_sysreg_el2(v,r) write_sysreg_elx(v, r, _EL2, _EL1)
49		49
		50	/*
		51	* Without an __arch_swab32(), we fall back to ___constant_swab32(), but the
		52	* static inline can allow the compiler to out-of-line this. KVM always wants
		53	* the macro version as its always inlined.
		54	*/
		55	#define __kvm_swab32(x) ___constant_swab32(x)
		56
50	int __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu);	57	int __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu);
51		58
52	void __vgic_v3_save_state(struct kvm_vcpu *vcpu);	59	void __vgic_v3_save_state(struct kvm_vcpu *vcpu);

arch/arm64/include/asm/kvm_mmu.h+2−1

 			__le32 *origptr, __le32 *updptr, int nr_inst);
 void kvm_compute_layout(void);
-static inline unsigned long __kern_hyp_va(unsigned long v)
+static __always_inline unsigned long __kern_hyp_va(unsigned long v)
 {
 	asm volatile(ALTERNATIVE_CB("and %0, %0, #1\n"
 				    "ror %0, %0, #1\n"
 extern void *__kvm_bp_vect_base;
 extern int __kvm_harden_el2_vector_slot;
+/*  This is only called on a VHE system */
 static inline void *kvm_get_hyp_vector(void)
 {
 	struct bp_hardening_data *data = arm64_get_bp_hardening_data();

arch/arm64/include/asm/mmu.h+1−3

  */
 #define ASID(mm)	((mm)->context.id.counter & 0xffff)
-extern bool arm64_use_ng_mappings;
 static inline bool arm64_kernel_unmapped_at_el0(void)
 {
-	return arm64_use_ng_mappings;
+	return cpus_have_const_cap(ARM64_UNMAP_KERNEL_AT_EL0);
 }
 typedef void (*bp_hardening_cb_t)(void);

arch/arm64/include/asm/pgtable-prot.h+4−2

 #include <asm/pgtable-types.h>
+extern bool arm64_use_ng_mappings;
 #define _PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
 #define _PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
-#define PTE_MAYBE_NG		(arm64_kernel_unmapped_at_el0() ? PTE_NG : 0)
+#define PTE_MAYBE_NG		(arm64_use_ng_mappings ? PTE_NG : 0)
-#define PMD_MAYBE_NG		(arm64_kernel_unmapped_at_el0() ? PMD_SECT_NG : 0)
+#define PMD_MAYBE_NG		(arm64_use_ng_mappings ? PMD_SECT_NG : 0)
 #define PROT_DEFAULT		(_PROT_DEFAULT | PTE_MAYBE_NG)
 #define PROT_SECT_DEFAULT	(_PROT_SECT_DEFAULT | PMD_MAYBE_NG)

arch/arm64/include/asm/unistd.h+1−1

 #define __NR_compat_gettimeofday	78
 #define __NR_compat_sigreturn		119
 #define __NR_compat_rt_sigreturn	173
-#define __NR_compat_clock_getres	247
 #define __NR_compat_clock_gettime	263
+#define __NR_compat_clock_getres	264
 #define __NR_compat_clock_gettime64	403
 #define __NR_compat_clock_getres_time64	406

arch/arm64/include/asm/virt.h+1−1

@@ -83,7 +83,7 @@ static inline bool is_kernel_in_hyp_mode(void) · 82 unmodified lines
83	return read_sysreg(CurrentEL) == CurrentEL_EL2;	83	return read_sysreg(CurrentEL) == CurrentEL_EL2;
84	}	84	}
85		85
86	static inline bool has_vhe(void)	86	static __always_inline bool has_vhe(void)
87	{	87	{
88	if (cpus_have_const_cap(ARM64_HAS_VIRT_HOST_EXTN))	88	if (cpus_have_const_cap(ARM64_HAS_VIRT_HOST_EXTN))
89	return true;	89	return true;

arch/arm64/kernel/smp.c+20−5

 }
 #endif
+/*
+ * The number of CPUs online, not counting this CPU (which may not be
+ * fully online and so not counted in num_online_cpus()).
+ */
+static inline unsigned int num_other_online_cpus(void)
+{
+	unsigned int this_cpu_online = cpu_online(smp_processor_id());
+	return num_online_cpus() - this_cpu_online;
+}
 void smp_send_stop(void)
 {
 	unsigned long timeout;
-	if (num_online_cpus() > 1) {
+	if (num_other_online_cpus()) {
 		cpumask_t mask;
 		cpumask_copy(&mask, cpu_online_mask);
 	/* Wait up to one second for other CPUs to stop */
 	timeout = USEC_PER_SEC;
-	while (num_online_cpus() > 1 && timeout--)
+	while (num_other_online_cpus() && timeout--)
 		udelay(1);
-	if (num_online_cpus() > 1)
+	if (num_other_online_cpus())
 		pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
 			cpumask_pr_args(cpu_online_mask));
 	cpus_stopped = 1;
-	if (num_online_cpus() == 1) {
+	/*
+	 * If this cpu is the only one alive at this point in time, online or
+	 * not, there are no stop messages to be sent around, so just back out.
+	 */
+	if (num_other_online_cpus() == 0) {
 		sdei_mask_local_cpu();
 		return;
 	}
 	cpumask_copy(&mask, cpu_online_mask);
 	cpumask_clear_cpu(smp_processor_id(), &mask);
-	atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1);
+	atomic_set(&waiting_for_crash_ipi, num_other_online_cpus());
 	pr_crit("SMP: stopping secondary CPUs\n");
 	smp_cross_call(&mask, IPI_CPU_CRASH_STOP);

arch/arm64/kvm/hyp/switch.c+37−2

@@ -625,7 +625,7 @@ static void __hyp_text __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt) · 624 unmodified lines
625	}	625	}
626		626
627	/* Switch to the guest for VHE systems running in EL2 */	627	/* Switch to the guest for VHE systems running in EL2 */
628	int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)	628	static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
629	{	629	{
630	struct kvm_cpu_context *host_ctxt;	630	struct kvm_cpu_context *host_ctxt;
631	struct kvm_cpu_context *guest_ctxt;	631	struct kvm_cpu_context *guest_ctxt;
@@ -678,7 +678,42 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) · 46 unmodified lines
678		678
679	return exit_code;	679	return exit_code;
680	}	680	}
681	NOKPROBE_SYMBOL(kvm_vcpu_run_vhe);	681	NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe);
		682
		683	int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
		684	{
		685	int ret;
		686
		687	local_daif_mask();
		688
		689	/*
		690	* Having IRQs masked via PMR when entering the guest means the GIC
		691	* will not signal the CPU of interrupts of lower priority, and the
		692	* only way to get out will be via guest exceptions.
		693	* Naturally, we want to avoid this.
		694	*
		695	* local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a
		696	* dsb to ensure the redistributor is forwards EL2 IRQs to the CPU.
		697	*/
		698	pmr_sync();
		699
		700	ret = __kvm_vcpu_run_vhe(vcpu);
		701
		702	/*
		703	* local_daif_restore() takes care to properly restore PSTATE.DAIF
		704	* and the GIC PMR if the host is using IRQ priorities.
		705	*/
		706	local_daif_restore(DAIF_PROCCTX_NOIRQ);
		707
		708	/*
		709	* When we exit from the guest we change a number of CPU configuration
		710	* parameters, such as traps. Make sure these changes take effect
		711	* before running the host or additional guests.
		712	*/
		713	isb();
		714
		715	return ret;
		716	}
682		717
683	/* Switch to the guest for legacy non-VHE systems */	718	/* Switch to the guest for legacy non-VHE systems */
684	int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)	719	int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)

arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c+2−2

@@ -69,14 +69,14 @@ int __hyp_text __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu) · 68 unmodified lines
69	u32 data = vcpu_get_reg(vcpu, rd);	69	u32 data = vcpu_get_reg(vcpu, rd);
70	if (__is_be(vcpu)) {	70	if (__is_be(vcpu)) {
71	/* guest pre-swabbed data, undo this for writel() */	71	/* guest pre-swabbed data, undo this for writel() */
72	data = swab32(data);	72	data = __kvm_swab32(data);
73	}	73	}
74	writel_relaxed(data, addr);	74	writel_relaxed(data, addr);
75	} else {	75	} else {
76	u32 data = readl_relaxed(addr);	76	u32 data = readl_relaxed(addr);
77	if (__is_be(vcpu)) {	77	if (__is_be(vcpu)) {
78	/* guest expects swabbed data */	78	/* guest expects swabbed data */
79	data = swab32(data);	79	data = __kvm_swab32(data);
80	}	80	}
81	vcpu_set_reg(vcpu, rd, data);	81	vcpu_set_reg(vcpu, rd, data);
82	}	82	}

arch/arm64/mm/context.c+15−5

 			CONFIG_CAVIUM_ERRATUM_27456));
 }
-static int asids_init(void)
+static int asids_update_limit(void)
 {
-	asid_bits = get_cpu_asid_bits();
+	unsigned long num_available_asids = NUM_USER_ASIDS;
+	if (arm64_kernel_unmapped_at_el0())
+		num_available_asids /= 2;
 	/*
 	 * Expect allocation after rollover to fail if we don't have at least
 	 * one more ASID than CPUs. ASID #0 is reserved for init_mm.
 	 */
-	WARN_ON(NUM_USER_ASIDS - 1 <= num_possible_cpus());
+	WARN_ON(num_available_asids - 1 <= num_possible_cpus());
+	pr_info("ASID allocator initialised with %lu entries\n",
+		num_available_asids);
+	return 0;
+}
+arch_initcall(asids_update_limit);
+static int asids_init(void)
+{
+	asid_bits = get_cpu_asid_bits();
 	atomic64_set(&asid_generation, ASID_FIRST_VERSION);
 	asid_map = kcalloc(BITS_TO_LONGS(NUM_USER_ASIDS), sizeof(*asid_map),
 			   GFP_KERNEL);
 	 */
 	if (IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0))
 		set_kpti_asid_bits();
-	pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS);
 	return 0;
 }
 early_initcall(asids_init);

arch/mips/boot/dts/ingenic/ci20.dts+28−16

@@ -4,6 +4,8 @@ · 3 unmodified lines
4	#include "jz4780.dtsi"	4	#include "jz4780.dtsi"
5	#include <dt-bindings/clock/ingenic,tcu.h>	5	#include <dt-bindings/clock/ingenic,tcu.h>
6	#include <dt-bindings/gpio/gpio.h>	6	#include <dt-bindings/gpio/gpio.h>
		7	#include <dt-bindings/interrupt-controller/irq.h>
		8	#include <dt-bindings/regulator/active-semi,8865-regulator.h>
7		9
8	/ {	10	/ {
9	compatible = "img,ci20", "ingenic,jz4780";	11	compatible = "img,ci20", "ingenic,jz4780";
@@ -163,63 +165,71 @@ · 153 unmodified lines
163		165
164	regulators {	166	regulators {
165	vddcore: SUDCDC1 {	167	vddcore: SUDCDC1 {
166	regulator-name = "VDDCORE";	168	regulator-name = "DCDC_REG1";
167	regulator-min-microvolt = <1100000>;	169	regulator-min-microvolt = <1100000>;
168	regulator-max-microvolt = <1100000>;	170	regulator-max-microvolt = <1100000>;
169	regulator-always-on;	171	regulator-always-on;
170	};	172	};
171	vddmem: SUDCDC2 {	173	vddmem: SUDCDC2 {
172	regulator-name = "VDDMEM";	174	regulator-name = "DCDC_REG2";
173	regulator-min-microvolt = <1500000>;	175	regulator-min-microvolt = <1500000>;
174	regulator-max-microvolt = <1500000>;	176	regulator-max-microvolt = <1500000>;
175	regulator-always-on;	177	regulator-always-on;
176	};	178	};
177	vcc_33: SUDCDC3 {	179	vcc_33: SUDCDC3 {
178	regulator-name = "VCC33";	180	regulator-name = "DCDC_REG3";
179	regulator-min-microvolt = <3300000>;	181	regulator-min-microvolt = <3300000>;
180	regulator-max-microvolt = <3300000>;	182	regulator-max-microvolt = <3300000>;
181	regulator-always-on;	183	regulator-always-on;
182	};	184	};
183	vcc_50: SUDCDC4 {	185	vcc_50: SUDCDC4 {
184	regulator-name = "VCC50";	186	regulator-name = "SUDCDC_REG4";
185	regulator-min-microvolt = <5000000>;	187	regulator-min-microvolt = <5000000>;
186	regulator-max-microvolt = <5000000>;	188	regulator-max-microvolt = <5000000>;
187	regulator-always-on;	189	regulator-always-on;
188	};	190	};
189	vcc_25: LDO_REG5 {	191	vcc_25: LDO_REG5 {
190	regulator-name = "VCC25";	192	regulator-name = "LDO_REG5";
191	regulator-min-microvolt = <2500000>;	193	regulator-min-microvolt = <2500000>;
192	regulator-max-microvolt = <2500000>;	194	regulator-max-microvolt = <2500000>;
193	regulator-always-on;	195	regulator-always-on;
194	};	196	};
195	wifi_io: LDO_REG6 {	197	wifi_io: LDO_REG6 {
196	regulator-name = "WIFIIO";	198	regulator-name = "LDO_REG6";
197	regulator-min-microvolt = <2500000>;	199	regulator-min-microvolt = <2500000>;
198	regulator-max-microvolt = <2500000>;	200	regulator-max-microvolt = <2500000>;
199	regulator-always-on;	201	regulator-always-on;
200	};	202	};
201	vcc_28: LDO_REG7 {	203	vcc_28: LDO_REG7 {
202	regulator-name = "VCC28";	204	regulator-name = "LDO_REG7";
203	regulator-min-microvolt = <2800000>;	205	regulator-min-microvolt = <2800000>;
204	regulator-max-microvolt = <2800000>;	206	regulator-max-microvolt = <2800000>;
205	regulator-always-on;	207	regulator-always-on;
206	};	208	};
207	vcc_15: LDO_REG8 {	209	vcc_15: LDO_REG8 {
208	regulator-name = "VCC15";	210	regulator-name = "LDO_REG8";
209	regulator-min-microvolt = <1500000>;	211	regulator-min-microvolt = <1500000>;
210	regulator-max-microvolt = <1500000>;	212	regulator-max-microvolt = <1500000>;
211	regulator-always-on;	213	regulator-always-on;
212	};	214	};
213	vcc_18: LDO_REG9 {	215	vrtc_18: LDO_REG9 {
214	regulator-name = "VCC18";	216	regulator-name = "LDO_REG9";
215	regulator-min-microvolt = <1800000>;	217	/* Despite the datasheet stating 3.3V
216	regulator-max-microvolt = <1800000>;	218	* for REG9 and the driver expecting that,
		219	* REG9 outputs 1.8V.
		220	* Likely the CI20 uses a proprietary
		221	* factory programmed chip variant.
		222	* Since this is a simple on/off LDO the
		223	* exact values do not matter.
		224	*/
		225	regulator-min-microvolt = <3300000>;
		226	regulator-max-microvolt = <3300000>;
217	regulator-always-on;	227	regulator-always-on;
218	};	228	};
219	vcc_11: LDO_REG10 {	229	vcc_11: LDO_REG10 {
220	regulator-name = "VCC11";	230	regulator-name = "LDO_REG10";
221	regulator-min-microvolt = <1100000>;	231	regulator-min-microvolt = <1200000>;
222	regulator-max-microvolt = <1100000>;	232	regulator-max-microvolt = <1200000>;
223	regulator-always-on;	233	regulator-always-on;
224	};	234	};
225	};	235	};
@@ -261,7 +271,9 @@ · 35 unmodified lines
261	rtc@51 {	271	rtc@51 {
262	compatible = "nxp,pcf8563";	272	compatible = "nxp,pcf8563";
263	reg = <0x51>;	273	reg = <0x51>;
264	interrupts = <110>;	274
		275	interrupt-parent = <&gpf>;
		276	interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
265	};	277	};
266	};	278	};
267		279

arch/mips/boot/dts/ingenic/jz4740.dtsi+9−8

 // SPDX-License-Identifier: GPL-2.0
 #include <dt-bindings/clock/jz4740-cgu.h>
+#include <dt-bindings/clock/ingenic,tcu.h>
 / {
 	#address-cells = <1>;
 		#clock-cells = <1>;
 	};
-	watchdog: watchdog@10002000 {
-		compatible = "ingenic,jz4740-watchdog";
-		reg = <0x10002000 0x10>;
-		clocks = <&cgu JZ4740_CLK_RTC>;
-		clock-names = "rtc";
-	};
 	tcu: timer@10002000 {
 		compatible = "ingenic,jz4740-tcu", "simple-mfd";
 		reg = <0x10002000 0x1000>;
 		interrupt-parent = <&intc>;
 		interrupts = <23 22 21>;
+		watchdog: watchdog@0 {
+			compatible = "ingenic,jz4740-watchdog";
+			reg = <0x0 0xc>;
+			clocks = <&tcu TCU_CLK_WDT>;
+			clock-names = "wdt";
+		};
 	};
 	rtc_dev: rtc@10003000 {

arch/mips/boot/dts/ingenic/jz4780.dtsi+9−8

 // SPDX-License-Identifier: GPL-2.0
 #include <dt-bindings/clock/jz4780-cgu.h>
+#include <dt-bindings/clock/ingenic,tcu.h>
 #include <dt-bindings/dma/jz4780-dma.h>
 / {
 		interrupt-parent = <&intc>;
 		interrupts = <27 26 25>;
+		watchdog: watchdog@0 {
+			compatible = "ingenic,jz4780-watchdog";
+			reg = <0x0 0xc>;
+			clocks = <&tcu TCU_CLK_WDT>;
+			clock-names = "wdt";
+		};
 	};
 	rtc_dev: rtc@10003000 {
 		status = "disabled";
 	};
-	watchdog: watchdog@10002000 {
-		compatible = "ingenic,jz4780-watchdog";
-		reg = <0x10002000 0x10>;
-		clocks = <&cgu JZ4780_CLK_RTCLK>;
-		clock-names = "rtc";
-	};
 	nemc: nemc@13410000 {
 		compatible = "ingenic,jz4780-nemc";
 		reg = <0x13410000 0x10000>;

arch/mips/boot/dts/ingenic/x1000.dtsi+2−4

 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/ingenic,tcu.h>
 #include <dt-bindings/clock/x1000-cgu.h>
 #include <dt-bindings/dma/x1000-dma.h>
 			compatible = "ingenic,x1000-watchdog", "ingenic,jz4780-watchdog";
 			reg = <0x0 0x10>;
-			clocks = <&cgu X1000_CLK_RTCLK>;
+			clocks = <&tcu TCU_CLK_WDT>;
 			clock-names = "wdt";
 		};
 	};
 	i2c0: i2c-controller@10050000 {
 		compatible = "ingenic,x1000-i2c";
 		reg = <0x10050000 0x1000>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 	i2c1: i2c-controller@10051000 {
 		compatible = "ingenic,x1000-i2c";
 		reg = <0x10051000 0x1000>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 	i2c2: i2c-controller@10052000 {
 		compatible = "ingenic,x1000-i2c";
 		reg = <0x10052000 0x1000>;
 		#address-cells = <1>;
 		#size-cells = <0>;

arch/mips/include/asm/sync.h+3−1

  * effective barrier as noted by commit 6b07d38aaa52 ("MIPS: Octeon: Use
  * optimized memory barrier primitives."). Here we specify that the affected
  * sync instructions should be emitted twice.
+ * Note that this expression is evaluated by the assembler (not the compiler),
+ * and that the assembler evaluates '==' as 0 or -1, not 0 or 1.
  */
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
-# define __SYNC_rpt(type)	(1 + (type == __SYNC_wmb))
+# define __SYNC_rpt(type)	(1 - (type == __SYNC_wmb))
 #else
 # define __SYNC_rpt(type)	1
 #endif

arch/mips/kernel/setup.c+2−1

@@ -605,7 +605,8 @@ static void __init bootcmdline_init(char **cmdline_p) · 604 unmodified lines
605	* If we're configured to take boot arguments from DT, look for those	605	* If we're configured to take boot arguments from DT, look for those
606	* now.	606	* now.
607	*/	607	*/
608	if (IS_ENABLED(CONFIG_MIPS_CMDLINE_FROM_DTB))	608	if (IS_ENABLED(CONFIG_MIPS_CMDLINE_FROM_DTB) \|\|
		609	IS_ENABLED(CONFIG_MIPS_CMDLINE_DTB_EXTEND))
609	of_scan_flat_dt(bootcmdline_scan_chosen, &dt_bootargs);	610	of_scan_flat_dt(bootcmdline_scan_chosen, &dt_bootargs);
610	#endif	611	#endif
611		612

arch/mips/kernel/vpe.c+1−1

@@ -134,7 +134,7 @@ void release_vpe(struct vpe *v) · 133 unmodified lines
134	{	134	{
135	list_del(&v->list);	135	list_del(&v->list);
136	if (v->load_addr)	136	if (v->load_addr)
137	release_progmem(v);	137	release_progmem(v->load_addr);
138	kfree(v);	138	kfree(v);
139	}	139	}
140		140

arch/mips/vdso/Makefile+25−3

 cflags-vdso := $(ccflags-vdso) \
 	$(filter -W%,$(filter-out -Wa$(comma)%,$(KBUILD_CFLAGS))) \
 	-O3 -g -fPIC -fno-strict-aliasing -fno-common -fno-builtin -G 0 \
+	-mrelax-pic-calls $(call cc-option, -mexplicit-relocs) \
 	-fno-stack-protector -fno-jump-tables -DDISABLE_BRANCH_PROFILING \
 	$(call cc-option, -fno-asynchronous-unwind-tables) \
 	$(call cc-option, -fno-stack-protector)
 CFLAGS_REMOVE_vgettimeofday.o = -pg
+DISABLE_VDSO := n
 #
 # For the pre-R6 code in arch/mips/vdso/vdso.h for locating
 # the base address of VDSO, the linker will emit a R_MIPS_PC32
 ifndef CONFIG_CPU_MIPSR6
   ifeq ($(call ld-ifversion, -lt, 225000000, y),y)
     $(warning MIPS VDSO requires binutils >= 2.25)
-    obj-vdso-y := $(filter-out vgettimeofday.o, $(obj-vdso-y))
+    DISABLE_VDSO := y
-    ccflags-vdso += -DDISABLE_MIPS_VDSO
   endif
 endif
+#
+# GCC (at least up to version 9.2) appears to emit function calls that make use
+# of the GOT when targeting microMIPS, which we can't use in the VDSO due to
+# the lack of relocations. As such, we disable the VDSO for microMIPS builds.
+#
+ifdef CONFIG_CPU_MICROMIPS
+  DISABLE_VDSO := y
+endif
+ifeq ($(DISABLE_VDSO),y)
+  obj-vdso-y := $(filter-out vgettimeofday.o, $(obj-vdso-y))
+  ccflags-vdso += -DDISABLE_MIPS_VDSO
+endif
 # VDSO linker flags.
 VDSO_LDFLAGS := \
 	-Wl,-Bsymbolic -Wl,--no-undefined -Wl,-soname=linux-vdso.so.1 \
 UBSAN_SANITIZE := n
 KCOV_INSTRUMENT := n
+# Check that we don't have PIC 'jalr t9' calls left
+quiet_cmd_vdso_mips_check = VDSOCHK $@
+      cmd_vdso_mips_check = if $(OBJDUMP) --disassemble $@ | egrep -h "jalr.*t9" > /dev/null; \
+		       then (echo >&2 "$@: PIC 'jalr t9' calls are not supported"; \
+			     rm -f $@; /bin/false); fi
 #
 # Shared build commands.
 #
 quiet_cmd_vdsold_and_vdso_check = LD      $@
-      cmd_vdsold_and_vdso_check = $(cmd_vdsold); $(cmd_vdso_check)
+      cmd_vdsold_and_vdso_check = $(cmd_vdsold); $(cmd_vdso_check); $(cmd_vdso_mips_check)
 quiet_cmd_vdsold = VDSO    $@
       cmd_vdsold = $(CC) $(c_flags) $(VDSO_LDFLAGS) \

arch/powerpc/kernel/cputable.c+3−1

 		 * oprofile_cpu_type already has a value, then we are
 		 * possibly overriding a real PVR with a logical one,
 		 * and, in that case, keep the current value for
-		 * oprofile_cpu_type.
+		 * oprofile_cpu_type. Futhermore, let's ensure that the
+		 * fix for the PMAO bug is enabled on compatibility mode.
 		 */
 		if (old.oprofile_cpu_type != NULL) {
 			t->oprofile_cpu_type = old.oprofile_cpu_type;
 			t->oprofile_type = old.oprofile_type;
+			t->cpu_features |= old.cpu_features & CPU_FTR_PMAO_BUG;
 		}
 	}

arch/powerpc/kernel/hw_breakpoint.c+7−5

@@ -331,11 +331,13 @@ int hw_breakpoint_handler(struct die_args *args) · 330 unmodified lines
331	}	331	}
332		332
333	info->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ;	333	info->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ;
334	if (!dar_within_range(regs->dar, info))	334	if (IS_ENABLED(CONFIG_PPC_8xx)) {
335	info->type \|= HW_BRK_TYPE_EXTRANEOUS_IRQ;	335	if (!dar_within_range(regs->dar, info))
336		336	info->type \|= HW_BRK_TYPE_EXTRANEOUS_IRQ;
337	if (!IS_ENABLED(CONFIG_PPC_8xx) && !stepping_handler(regs, bp, info))	337	} else {
338	goto out;	338	if (!stepping_handler(regs, bp, info))
		339	goto out;
		340	}
339		341
340	/*	342	/*
341	* As a policy, the callback is invoked in a 'trigger-after-execute'	343	* As a policy, the callback is invoked in a 'trigger-after-execute'

arch/powerpc/kernel/vmlinux.lds.S+6−0

 		*(.branch_lt)
 	}
+#ifdef CONFIG_DEBUG_INFO_BTF
+	.BTF : AT(ADDR(.BTF) - LOAD_OFFSET) {
+		*(.BTF)
+	}
+#endif
 	.opd : AT(ADDR(.opd) - LOAD_OFFSET) {
 		__start_opd = .;
 		KEEP(*(.opd))

arch/powerpc/mm/mem.c+2−0

 	 */
 	if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
 		mb(); /* sync */
+		allow_read_from_user((const void __user *)addr, L1_CACHE_BYTES);
 		icbi((void *)addr);
+		prevent_read_from_user((const void __user *)addr, L1_CACHE_BYTES);
 		mb(); /* sync */
 		isync();
 		return true;

arch/riscv/Kconfig+1−0

@@ -121,6 +121,7 @@ config ARCH_FLATMEM_ENABLE · 120 unmodified lines
121		121
122	config ARCH_SPARSEMEM_ENABLE	122	config ARCH_SPARSEMEM_ENABLE
123	def_bool y	123	def_bool y
		124	depends on MMU
124	select SPARSEMEM_VMEMMAP_ENABLE	125	select SPARSEMEM_VMEMMAP_ENABLE
125		126
126	config ARCH_SELECT_MEMORY_MODEL	127	config ARCH_SELECT_MEMORY_MODEL

arch/riscv/Kconfig.socs+24−0

@@ -10,4 +10,28 @@ config SOC_SIFIVE · 9 unmodified lines
10	help	10	help
11	This enables support for SiFive SoC platform hardware.	11	This enables support for SiFive SoC platform hardware.
12		12
		13	config SOC_VIRT
		14	bool "QEMU Virt Machine"
		15	select VIRTIO_PCI
		16	select VIRTIO_BALLOON
		17	select VIRTIO_MMIO
		18	select VIRTIO_CONSOLE
		19	select VIRTIO_NET
		20	select NET_9P_VIRTIO
		21	select VIRTIO_BLK
		22	select SCSI_VIRTIO
		23	select DRM_VIRTIO_GPU
		24	select HW_RANDOM_VIRTIO
		25	select RPMSG_CHAR
		26	select RPMSG_VIRTIO
		27	select CRYPTO_DEV_VIRTIO
		28	select VIRTIO_INPUT
		29	select POWER_RESET_SYSCON
		30	select POWER_RESET_SYSCON_POWEROFF
		31	select GOLDFISH
		32	select RTC_DRV_GOLDFISH
		33	select SIFIVE_PLIC
		34	help
		35	This enables support for QEMU Virt Machine.
		36
13	endmenu	37	endmenu

arch/riscv/Makefile+4−2

@@ -13,8 +13,10 @@ LDFLAGS_vmlinux := · 12 unmodified lines
13	ifeq ($(CONFIG_DYNAMIC_FTRACE),y)	13	ifeq ($(CONFIG_DYNAMIC_FTRACE),y)
14	LDFLAGS_vmlinux := --no-relax	14	LDFLAGS_vmlinux := --no-relax
15	endif	15	endif
16	KBUILD_AFLAGS_MODULE += -fPIC	16
17	KBUILD_CFLAGS_MODULE += -fPIC	17	ifeq ($(CONFIG_64BIT)$(CONFIG_CMODEL_MEDLOW),yy)
		18	KBUILD_CFLAGS_MODULE += -mcmodel=medany
		19	endif
18		20
19	export BITS	21	export BITS
20	ifeq ($(CONFIG_ARCH_RV64I),y)	22	ifeq ($(CONFIG_ARCH_RV64I),y)

arch/riscv/boot/.gitignore+2−0

@@ -1,2 +1,4 @@
1	Image	1	Image
2	Image.gz	2	Image.gz
		3	loader
		4	loader.lds

arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts+5−0

 /* Copyright (c) 2018-2019 SiFive, Inc */
 #include "fu540-c000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
 #define RTCCLK_FREQ		1000000
 		clock-frequency = <RTCCLK_FREQ>;
 		clock-output-names = "rtcclk";
 	};
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+	};
 };
 &uart0 {

arch/riscv/configs/defconfig+3−14

 CONFIG_EXPERT=y
 CONFIG_BPF_SYSCALL=y
 CONFIG_SOC_SIFIVE=y
+CONFIG_SOC_VIRT=y
 CONFIG_SMP=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_IP_PNP_RARP=y
 CONFIG_NETLINK_DIAG=y
 CONFIG_NET_9P=y
-CONFIG_NET_9P_VIRTIO=y
 CONFIG_PCI=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCI_HOST_GENERIC=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_VIRTIO_BLK=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
-CONFIG_SCSI_VIRTIO=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_NETDEVICES=y
-CONFIG_VIRTIO_NET=y
 CONFIG_MACB=y
 CONFIG_E1000E=y
 CONFIG_R8169=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
 CONFIG_HVC_RISCV_SBI=y
-CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_VIRTIO=y
 CONFIG_SPI=y
 CONFIG_SPI_SIFIVE=y
 # CONFIG_PTP_1588_CLOCK is not set
+CONFIG_POWER_RESET=y
 CONFIG_DRM=y
 CONFIG_DRM_RADEON=y
-CONFIG_DRM_VIRTIO_GPU=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_UAS=y
 CONFIG_MMC=y
 CONFIG_MMC_SPI=y
-CONFIG_VIRTIO_PCI=y
+CONFIG_RTC_CLASS=y
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_INPUT=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_RPMSG_CHAR=y
-CONFIG_RPMSG_VIRTIO=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_9P_FS=y
 CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_DEV_VIRTIO=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_PAGEALLOC=y

arch/riscv/configs/rv32_defconfig+3−15

 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 CONFIG_BPF_SYSCALL=y
+CONFIG_SOC_VIRT=y
 CONFIG_ARCH_RV32I=y
 CONFIG_SMP=y
 CONFIG_MODULES=y
 CONFIG_IP_PNP_RARP=y
 CONFIG_NETLINK_DIAG=y
 CONFIG_NET_9P=y
-CONFIG_NET_9P_VIRTIO=y
 CONFIG_PCI=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCI_HOST_GENERIC=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_VIRTIO_BLK=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
-CONFIG_SCSI_VIRTIO=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_NETDEVICES=y
-CONFIG_VIRTIO_NET=y
 CONFIG_MACB=y
 CONFIG_E1000E=y
 CONFIG_R8169=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
 CONFIG_HVC_RISCV_SBI=y
-CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_VIRTIO=y
 # CONFIG_PTP_1588_CLOCK is not set
+CONFIG_POWER_RESET=y
 CONFIG_DRM=y
 CONFIG_DRM_RADEON=y
-CONFIG_DRM_VIRTIO_GPU=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_UAS=y
-CONFIG_VIRTIO_PCI=y
+CONFIG_RTC_CLASS=y
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_INPUT=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_RPMSG_CHAR=y
-CONFIG_RPMSG_VIRTIO=y
-CONFIG_SIFIVE_PLIC=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_9P_FS=y
 CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_DEV_VIRTIO=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_PAGEALLOC=y

arch/riscv/include/asm/csr.h+12−0

 #define EXC_LOAD_PAGE_FAULT	13
 #define EXC_STORE_PAGE_FAULT	15
+/* PMP configuration */
+#define PMP_R			0x01
+#define PMP_W			0x02
+#define PMP_X			0x04
+#define PMP_A			0x18
+#define PMP_A_TOR		0x08
+#define PMP_A_NA4		0x10
+#define PMP_A_NAPOT		0x18
+#define PMP_L			0x80
 /* symbolic CSR names: */
 #define CSR_CYCLE		0xc00
 #define CSR_TIME		0xc01
 #define CSR_MCAUSE		0x342
 #define CSR_MTVAL		0x343
 #define CSR_MIP			0x344
+#define CSR_PMPCFG0		0x3a0
+#define CSR_PMPADDR0		0x3b0
 #define CSR_MHARTID		0xf14
 #ifdef CONFIG_RISCV_M_MODE

arch/riscv/include/asm/syscall.h+0−7

@@ -28,13 +28,6 @@ static inline int syscall_get_nr(struct task_struct *task, · 27 unmodified lines
28	return regs->a7;	28	return regs->a7;
29	}	29	}
30		30
31	static inline void syscall_set_nr(struct task_struct *task,
32	struct pt_regs *regs,
33	int sysno)
34	{
35	regs->a7 = sysno;
36	}
37
38	static inline void syscall_rollback(struct task_struct *task,	31	static inline void syscall_rollback(struct task_struct *task,
39	struct pt_regs *regs)	32	struct pt_regs *regs)
40	{	33	{

arch/riscv/kernel/entry.S+3−8

 	/* Check to make sure we don't jump to a bogus syscall number. */
 	li t0, __NR_syscalls
 	la s0, sys_ni_syscall
-	/*
-	 * The tracer can change syscall number to valid/invalid value.
-	 * We use syscall_set_nr helper in syscall_trace_enter thus we
-	 * cannot trust the current value in a7 and have to reload from
-	 * the current task pt_regs.
-	 */
-	REG_L a7, PT_A7(sp)
 	/*
 	 * Syscall number held in a7.
 	 * If syscall number is above allowed value, redirect to ni_syscall.
 	 */
 	bge a7, t0, 1f
 	/*
-	 * Check if syscall is rejected by tracer or seccomp, i.e., a7 == -1.
+	 * Check if syscall is rejected by tracer, i.e., a7 == -1.
 	 * If yes, we pretend it was executed.
 	 */
 	li t1, -1
 handle_syscall_trace_enter:
 	move a0, sp
 	call do_syscall_trace_enter
+	move t0, a0
 	REG_L a0, PT_A0(sp)
 	REG_L a1, PT_A1(sp)
 	REG_L a2, PT_A2(sp)
 	REG_L a5, PT_A5(sp)
 	REG_L a6, PT_A6(sp)
 	REG_L a7, PT_A7(sp)
+	bnez t0, ret_from_syscall_rejected
 	j check_syscall_nr
 handle_syscall_trace_exit:
 	move a0, sp

arch/riscv/kernel/head.S+6−0

 	/* Reset all registers except ra, a0, a1 */
 	call reset_regs
+	/* Setup a PMP to permit access to all of memory. */
+	li a0, -1
+	csrw CSR_PMPADDR0, a0
+	li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X)
+	csrw CSR_PMPCFG0, a0
 	/*
 	 * The hartid in a0 is expected later on, and we have no firmware
 	 * to hand it to us.

arch/riscv/kernel/module.c+16−0

@@ -8,6 +8,10 @@ · 7 unmodified lines
8	#include <linux/err.h>	8	#include <linux/err.h>
9	#include <linux/errno.h>	9	#include <linux/errno.h>
10	#include <linux/moduleloader.h>	10	#include <linux/moduleloader.h>
		11	#include <linux/vmalloc.h>
		12	#include <linux/sizes.h>
		13	#include <asm/pgtable.h>
		14	#include <asm/sections.h>
11		15
12	static int apply_r_riscv_32_rela(struct module me, u32 location, Elf_Addr v)	16	static int apply_r_riscv_32_rela(struct module me, u32 location, Elf_Addr v)
13	{	17	{
@@ -386,3 +390,15 @@ int apply_relocate_add(Elf_Shdr sechdrs, const char strtab, · 372 unmodified lines
386		390
387	return 0;	391	return 0;
388	}	392	}
		393
		394	#if defined(CONFIG_MMU) && defined(CONFIG_64BIT)
		395	#define VMALLOC_MODULE_START \
		396	max(PFN_ALIGN((unsigned long)&_end - SZ_2G), VMALLOC_START)
		397	void *module_alloc(unsigned long size)
		398	{
		399	return __vmalloc_node_range(size, 1, VMALLOC_MODULE_START,
		400	VMALLOC_END, GFP_KERNEL,
		401	PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
		402	__builtin_return_address(0));
		403	}
		404	#endif

arch/riscv/kernel/ptrace.c+5−6

  * Allows PTRACE_SYSCALL to work.  These are called from entry.S in
  * {handle,ret_from}_syscall.
  */
-__visible void do_syscall_trace_enter(struct pt_regs *regs)
+__visible int do_syscall_trace_enter(struct pt_regs *regs)
 {
 	if (test_thread_flag(TIF_SYSCALL_TRACE))
 		if (tracehook_report_syscall_entry(regs))
-			syscall_set_nr(current, regs, -1);
+			return -1;
 	/*
 	 * Do the secure computing after ptrace; failures should be fast.
 	 * If this fails we might have return value in a0 from seccomp
 	 * (via SECCOMP_RET_ERRNO/TRACE).
 	 */
-	if (secure_computing() == -1) {
+	if (secure_computing() == -1)
-		syscall_set_nr(current, regs, -1);
+		return -1;
-		return;
-	}
 #ifdef CONFIG_HAVE_SYSCALL_TRACEPOINTS
 	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
 #endif
 	audit_syscall_entry(regs->a7, regs->a0, regs->a1, regs->a2, regs->a3);
+	return 0;
 }
 __visible void do_syscall_trace_exit(struct pt_regs *regs)

arch/riscv/kernel/traps.c+2−2

@@ -156,6 +156,6 @@ void __init trap_init(void) · 155 unmodified lines
156	csr_write(CSR_SCRATCH, 0);	156	csr_write(CSR_SCRATCH, 0);
157	/* Set the exception vector address */	157	/* Set the exception vector address */
158	csr_write(CSR_TVEC, &handle_exception);	158	csr_write(CSR_TVEC, &handle_exception);
159	/* Enable all interrupts */	159	/* Enable interrupts */
160	csr_write(CSR_IE, -1);	160	csr_write(CSR_IE, IE_SIE \| IE_EIE);
161	}	161	}

arch/riscv/mm/init.c+1−1

@@ -131,7 +131,7 @@ void __init setup_bootmem(void) · 130 unmodified lines
131	for_each_memblock(memory, reg) {	131	for_each_memblock(memory, reg) {
132	phys_addr_t end = reg->base + reg->size;	132	phys_addr_t end = reg->base + reg->size;
133		133
134	if (reg->base <= vmlinux_end && vmlinux_end <= end) {	134	if (reg->base <= vmlinux_start && vmlinux_end <= end) {
135	mem_size = min(reg->size, (phys_addr_t)-PAGE_OFFSET);	135	mem_size = min(reg->size, (phys_addr_t)-PAGE_OFFSET);
136		136
137	/*	137	/*

arch/riscv/mm/kasan_init.c+31−22

@@ -19,18 +19,20 @@ asmlinkage void __init kasan_early_init(void) · 18 unmodified lines
19	for (i = 0; i < PTRS_PER_PTE; ++i)	19	for (i = 0; i < PTRS_PER_PTE; ++i)
20	set_pte(kasan_early_shadow_pte + i,	20	set_pte(kasan_early_shadow_pte + i,
21	mk_pte(virt_to_page(kasan_early_shadow_page),	21	mk_pte(virt_to_page(kasan_early_shadow_page),
22	PAGE_KERNEL));	22	PAGE_KERNEL));
23		23
24	for (i = 0; i < PTRS_PER_PMD; ++i)	24	for (i = 0; i < PTRS_PER_PMD; ++i)
25	set_pmd(kasan_early_shadow_pmd + i,	25	set_pmd(kasan_early_shadow_pmd + i,
26	pfn_pmd(PFN_DOWN(__pa((uintptr_t)kasan_early_shadow_pte)),	26	pfn_pmd(PFN_DOWN
27	__pgprot(_PAGE_TABLE)));	27	(__pa((uintptr_t) kasan_early_shadow_pte)),
		28	__pgprot(_PAGE_TABLE)));
28		29
29	for (i = KASAN_SHADOW_START; i < KASAN_SHADOW_END;	30	for (i = KASAN_SHADOW_START; i < KASAN_SHADOW_END;
30	i += PGDIR_SIZE, ++pgd)	31	i += PGDIR_SIZE, ++pgd)
31	set_pgd(pgd,	32	set_pgd(pgd,
32	pfn_pgd(PFN_DOWN(__pa(((uintptr_t)kasan_early_shadow_pmd))),	33	pfn_pgd(PFN_DOWN
33	__pgprot(_PAGE_TABLE)));	34	(__pa(((uintptr_t) kasan_early_shadow_pmd))),
		35	__pgprot(_PAGE_TABLE)));
34		36
35	/* init for swapper_pg_dir */	37	/* init for swapper_pg_dir */
36	pgd = pgd_offset_k(KASAN_SHADOW_START);	38	pgd = pgd_offset_k(KASAN_SHADOW_START);
@@ -38,37 +40,43 @@ asmlinkage void __init kasan_early_init(void) · 1 unmodified line
38	for (i = KASAN_SHADOW_START; i < KASAN_SHADOW_END;	40	for (i = KASAN_SHADOW_START; i < KASAN_SHADOW_END;
39	i += PGDIR_SIZE, ++pgd)	41	i += PGDIR_SIZE, ++pgd)
40	set_pgd(pgd,	42	set_pgd(pgd,
41	pfn_pgd(PFN_DOWN(__pa(((uintptr_t)kasan_early_shadow_pmd))),	43	pfn_pgd(PFN_DOWN
42	__pgprot(_PAGE_TABLE)));	44	(__pa(((uintptr_t) kasan_early_shadow_pmd))),
		45	__pgprot(_PAGE_TABLE)));
43		46
44	flush_tlb_all();	47	flush_tlb_all();
45	}	48	}
46		49
47	static void __init populate(void start, void end)	50	static void __init populate(void start, void end)
48	{	51	{
49	unsigned long i;	52	unsigned long i, offset;
50	unsigned long vaddr = (unsigned long)start & PAGE_MASK;	53	unsigned long vaddr = (unsigned long)start & PAGE_MASK;
51	unsigned long vend = PAGE_ALIGN((unsigned long)end);	54	unsigned long vend = PAGE_ALIGN((unsigned long)end);
52	unsigned long n_pages = (vend - vaddr) / PAGE_SIZE;	55	unsigned long n_pages = (vend - vaddr) / PAGE_SIZE;
		56	unsigned long n_ptes =
		57	((n_pages + PTRS_PER_PTE) & -PTRS_PER_PTE) / PTRS_PER_PTE;
53	unsigned long n_pmds =	58	unsigned long n_pmds =
54	(n_pages % PTRS_PER_PTE) ? n_pages / PTRS_PER_PTE + 1 :	59	((n_ptes + PTRS_PER_PMD) & -PTRS_PER_PMD) / PTRS_PER_PMD;
55	n_pages / PTRS_PER_PTE;	60
		61	pte_t *pte =
		62	memblock_alloc(n_ptes * PTRS_PER_PTE * sizeof(pte_t), PAGE_SIZE);
		63	pmd_t *pmd =
		64	memblock_alloc(n_pmds * PTRS_PER_PMD * sizeof(pmd_t), PAGE_SIZE);
56	pgd_t *pgd = pgd_offset_k(vaddr);	65	pgd_t *pgd = pgd_offset_k(vaddr);
57	pmd_t pmd = memblock_alloc(n_pmds sizeof(pmd_t), PAGE_SIZE);
58	pte_t pte = memblock_alloc(n_pages sizeof(pte_t), PAGE_SIZE);
59		66
60	for (i = 0; i < n_pages; i++) {	67	for (i = 0; i < n_pages; i++) {
61	phys_addr_t phys = memblock_phys_alloc(PAGE_SIZE, PAGE_SIZE);	68	phys_addr_t phys = memblock_phys_alloc(PAGE_SIZE, PAGE_SIZE);
62		69	set_pte(&pte[i], pfn_pte(PHYS_PFN(phys), PAGE_KERNEL));
63	set_pte(pte + i, pfn_pte(PHYS_PFN(phys), PAGE_KERNEL));
64	}	70	}
65		71
66	for (i = 0; i < n_pmds; ++pgd, i += PTRS_PER_PMD)	72	for (i = 0, offset = 0; i < n_ptes; i++, offset += PTRS_PER_PTE)
67	set_pgd(pgd, pfn_pgd(PFN_DOWN(__pa(((uintptr_t)(pmd + i)))),	73	set_pmd(&pmd[i],
		74	pfn_pmd(PFN_DOWN(__pa(&pte[offset])),
68	__pgprot(_PAGE_TABLE)));	75	__pgprot(_PAGE_TABLE)));
69		76
70	for (i = 0; i < n_pages; ++pmd, i += PTRS_PER_PTE)	77	for (i = 0, offset = 0; i < n_pmds; i++, offset += PTRS_PER_PMD)
71	set_pmd(pmd, pfn_pmd(PFN_DOWN(__pa((uintptr_t)(pte + i))),	78	set_pgd(&pgd[i],
		79	pfn_pgd(PFN_DOWN(__pa(&pmd[offset])),
72	__pgprot(_PAGE_TABLE)));	80	__pgprot(_PAGE_TABLE)));
73		81
74	flush_tlb_all();	82	flush_tlb_all();
@@ -81,7 +89,8 @@ void __init kasan_init(void) · 6 unmodified lines
81	unsigned long i;	89	unsigned long i;
82		90
83	kasan_populate_early_shadow((void *)KASAN_SHADOW_START,	91	kasan_populate_early_shadow((void *)KASAN_SHADOW_START,
84	(void )kasan_mem_to_shadow((void )VMALLOC_END));	92	(void )kasan_mem_to_shadow((void )
		93	VMALLOC_END));
85		94
86	for_each_memblock(memory, reg) {	95	for_each_memblock(memory, reg) {
87	void start = (void )__va(reg->base);	96	void start = (void )__va(reg->base);
@@ -90,14 +99,14 @@ void __init kasan_init(void) · 2 unmodified lines
90	if (start >= end)	99	if (start >= end)
91	break;	100	break;
92		101
93	populate(kasan_mem_to_shadow(start),	102	populate(kasan_mem_to_shadow(start), kasan_mem_to_shadow(end));
94	kasan_mem_to_shadow(end));
95	};	103	};
96		104
97	for (i = 0; i < PTRS_PER_PTE; i++)	105	for (i = 0; i < PTRS_PER_PTE; i++)
98	set_pte(&kasan_early_shadow_pte[i],	106	set_pte(&kasan_early_shadow_pte[i],
99	mk_pte(virt_to_page(kasan_early_shadow_page),	107	mk_pte(virt_to_page(kasan_early_shadow_page),
100	__pgprot(_PAGE_PRESENT \| _PAGE_READ \| _PAGE_ACCESSED)));	108	__pgprot(_PAGE_PRESENT \| _PAGE_READ \|
		109	_PAGE_ACCESSED)));
101		110
102	memset(kasan_early_shadow_page, 0, PAGE_SIZE);	111	memset(kasan_early_shadow_page, 0, PAGE_SIZE);
103	init_task.kasan_depth = 0;	112	init_task.kasan_depth = 0;

arch/s390/include/asm/pgtable.h+6−0

 	return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0;
 }
+#define pud_write pud_write
+static inline int pud_write(pud_t pud)
+{
+	return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0;
+}
 static inline int pmd_dirty(pmd_t pmd)
 {
 	return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0;

arch/s390/kvm/kvm-s390.c+17−1

@@ -3268,7 +3268,10 @@ static void kvm_arch_vcpu_ioctl_initial_reset(struct kvm_vcpu *vcpu) · 3267 unmodified lines
3268	/* Initial reset is a superset of the normal reset */	3268	/* Initial reset is a superset of the normal reset */
3269	kvm_arch_vcpu_ioctl_normal_reset(vcpu);	3269	kvm_arch_vcpu_ioctl_normal_reset(vcpu);
3270		3270
3271	/* this equals initial cpu reset in pop, but we don't switch to ESA */	3271	/*
		3272	* This equals initial cpu reset in pop, but we don't switch to ESA.
		3273	* We do not only reset the internal data, but also ...
		3274	*/
3272	vcpu->arch.sie_block->gpsw.mask = 0;	3275	vcpu->arch.sie_block->gpsw.mask = 0;
3273	vcpu->arch.sie_block->gpsw.addr = 0;	3276	vcpu->arch.sie_block->gpsw.addr = 0;
3274	kvm_s390_set_prefix(vcpu, 0);	3277	kvm_s390_set_prefix(vcpu, 0);
@@ -3278,6 +3281,19 @@ static void kvm_arch_vcpu_ioctl_initial_reset(struct kvm_vcpu *vcpu) · 3 unmodified lines
3278	memset(vcpu->arch.sie_block->gcr, 0, sizeof(vcpu->arch.sie_block->gcr));	3281	memset(vcpu->arch.sie_block->gcr, 0, sizeof(vcpu->arch.sie_block->gcr));
3279	vcpu->arch.sie_block->gcr[0] = CR0_INITIAL_MASK;	3282	vcpu->arch.sie_block->gcr[0] = CR0_INITIAL_MASK;
3280	vcpu->arch.sie_block->gcr[14] = CR14_INITIAL_MASK;	3283	vcpu->arch.sie_block->gcr[14] = CR14_INITIAL_MASK;
		3284
		3285	/* ... the data in sync regs */
		3286	memset(vcpu->run->s.regs.crs, 0, sizeof(vcpu->run->s.regs.crs));
		3287	vcpu->run->s.regs.ckc = 0;
		3288	vcpu->run->s.regs.crs[0] = CR0_INITIAL_MASK;
		3289	vcpu->run->s.regs.crs[14] = CR14_INITIAL_MASK;
		3290	vcpu->run->psw_addr = 0;
		3291	vcpu->run->psw_mask = 0;
		3292	vcpu->run->s.regs.todpr = 0;
		3293	vcpu->run->s.regs.cputm = 0;
		3294	vcpu->run->s.regs.ckc = 0;
		3295	vcpu->run->s.regs.pp = 0;
		3296	vcpu->run->s.regs.gbea = 1;
3281	vcpu->run->s.regs.fpc = 0;	3297	vcpu->run->s.regs.fpc = 0;
3282	vcpu->arch.sie_block->gbea = 1;	3298	vcpu->arch.sie_block->gbea = 1;
3283	vcpu->arch.sie_block->pp = 0;	3299	vcpu->arch.sie_block->pp = 0;

arch/s390/pci/pci.c+2−2

@@ -424,7 +424,7 @@ static void zpci_map_resources(struct pci_dev *pdev) · 423 unmodified lines
424		424
425	if (zpci_use_mio(zdev))	425	if (zpci_use_mio(zdev))
426	pdev->resource[i].start =	426	pdev->resource[i].start =
427	(resource_size_t __force) zdev->bars[i].mio_wb;	427	(resource_size_t __force) zdev->bars[i].mio_wt;
428	else	428	else
429	pdev->resource[i].start = (resource_size_t __force)	429	pdev->resource[i].start = (resource_size_t __force)
430	pci_iomap_range_fh(pdev, i, 0, 0);	430	pci_iomap_range_fh(pdev, i, 0, 0);
@@ -531,7 +531,7 @@ static int zpci_setup_bus_resources(struct zpci_dev *zdev, · 100 unmodified lines
531	flags \|= IORESOURCE_MEM_64;	531	flags \|= IORESOURCE_MEM_64;
532		532
533	if (zpci_use_mio(zdev))	533	if (zpci_use_mio(zdev))
534	addr = (unsigned long) zdev->bars[i].mio_wb;	534	addr = (unsigned long) zdev->bars[i].mio_wt;
535	else	535	else
536	addr = ZPCI_ADDR(entry);	536	addr = ZPCI_ADDR(entry);
537	size = 1UL << zdev->bars[i].size;	537	size = 1UL << zdev->bars[i].size;

arch/x86/Makefile+3−2

@@ -194,9 +194,10 @@ avx2_instr :=$(call as-instr,vpbroadcastb %xmm0$(comma)%ymm1,-DCONFIG_AS_AVX2=1) · 193 unmodified lines
194	avx512_instr :=$(call as-instr,vpmovm2b %k1$(comma)%zmm5,-DCONFIG_AS_AVX512=1)	194	avx512_instr :=$(call as-instr,vpmovm2b %k1$(comma)%zmm5,-DCONFIG_AS_AVX512=1)
195	sha1_ni_instr :=$(call as-instr,sha1msg1 %xmm0$(comma)%xmm1,-DCONFIG_AS_SHA1_NI=1)	195	sha1_ni_instr :=$(call as-instr,sha1msg1 %xmm0$(comma)%xmm1,-DCONFIG_AS_SHA1_NI=1)
196	sha256_ni_instr :=$(call as-instr,sha256msg1 %xmm0$(comma)%xmm1,-DCONFIG_AS_SHA256_NI=1)	196	sha256_ni_instr :=$(call as-instr,sha256msg1 %xmm0$(comma)%xmm1,-DCONFIG_AS_SHA256_NI=1)
		197	adx_instr := $(call as-instr,adox %r10$(comma)%r10,-DCONFIG_AS_ADX=1)
197		198
198	KBUILD_AFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr) $(avx2_instr) $(avx512_instr) $(sha1_ni_instr) $(sha256_ni_instr)	199	KBUILD_AFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr) $(avx2_instr) $(avx512_instr) $(sha1_ni_instr) $(sha256_ni_instr) $(adx_instr)
199	KBUILD_CFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr) $(avx2_instr) $(avx512_instr) $(sha1_ni_instr) $(sha256_ni_instr)	200	KBUILD_CFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr) $(avx2_instr) $(avx512_instr) $(sha1_ni_instr) $(sha256_ni_instr) $(adx_instr)
200		201
201	KBUILD_LDFLAGS := -m elf_$(UTS_MACHINE)	202	KBUILD_LDFLAGS := -m elf_$(UTS_MACHINE)
202		203

arch/x86/crypto/Makefile+6−1

@@ -11,6 +11,7 @@ avx2_supported := $(call as-instr,vpgatherdd %ymm0$(comma)(%eax$(comma)%ymm1\ · 10 unmodified lines
11	avx512_supported :=$(call as-instr,vpmovm2b %k1$(comma)%zmm5,yes,no)	11	avx512_supported :=$(call as-instr,vpmovm2b %k1$(comma)%zmm5,yes,no)
12	sha1_ni_supported :=$(call as-instr,sha1msg1 %xmm0$(comma)%xmm1,yes,no)	12	sha1_ni_supported :=$(call as-instr,sha1msg1 %xmm0$(comma)%xmm1,yes,no)
13	sha256_ni_supported :=$(call as-instr,sha256msg1 %xmm0$(comma)%xmm1,yes,no)	13	sha256_ni_supported :=$(call as-instr,sha256msg1 %xmm0$(comma)%xmm1,yes,no)
		14	adx_supported := $(call as-instr,adox %r10$(comma)%r10,yes,no)
14		15
15	obj-$(CONFIG_CRYPTO_GLUE_HELPER_X86) += glue_helper.o	16	obj-$(CONFIG_CRYPTO_GLUE_HELPER_X86) += glue_helper.o
16		17
@@ -39,7 +40,11 @@ obj-$(CONFIG_CRYPTO_AEGIS128_AESNI_SSE2) += aegis128-aesni.o · 22 unmodified lines
39		40
40	obj-$(CONFIG_CRYPTO_NHPOLY1305_SSE2) += nhpoly1305-sse2.o	41	obj-$(CONFIG_CRYPTO_NHPOLY1305_SSE2) += nhpoly1305-sse2.o
41	obj-$(CONFIG_CRYPTO_NHPOLY1305_AVX2) += nhpoly1305-avx2.o	42	obj-$(CONFIG_CRYPTO_NHPOLY1305_AVX2) += nhpoly1305-avx2.o
42	obj-$(CONFIG_CRYPTO_CURVE25519_X86) += curve25519-x86_64.o	43
		44	# These modules require the assembler to support ADX.
		45	ifeq ($(adx_supported),yes)
		46	obj-$(CONFIG_CRYPTO_CURVE25519_X86) += curve25519-x86_64.o
		47	endif
43		48
44	# These modules require assembler to support AVX.	49	# These modules require assembler to support AVX.
45	ifeq ($(avx_supported),yes)	50	ifeq ($(avx_supported),yes)

arch/x86/events/amd/uncore.c+7−10

 	/*
 	 * NB and Last level cache counters (MSRs) are shared across all cores
-	 * that share the same NB / Last level cache. Interrupts can be directed
+	 * that share the same NB / Last level cache.  On family 16h and below,
-	 * to a single target core, however, event counts generated by processes
+	 * Interrupts can be directed to a single target core, however, event
-	 * running on other cores cannot be masked out. So we do not support
+	 * counts generated by processes running on other cores cannot be masked
-	 * sampling and per-thread events.
+	 * out. So we do not support sampling and per-thread events via
+	 * CAP_NO_INTERRUPT, and we do not enable counter overflow interrupts:
 	 */
-	if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
-		return -EINVAL;
-	/* and we do not enable counter overflow interrupts */
 	hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
 	hwc->idx = -1;
 	.start		= amd_uncore_start,
 	.stop		= amd_uncore_stop,
 	.read		= amd_uncore_read,
-	.capabilities	= PERF_PMU_CAP_NO_EXCLUDE,
+	.capabilities	= PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
 };
 static struct pmu amd_llc_pmu = {
 	.start		= amd_uncore_start,
 	.stop		= amd_uncore_stop,
 	.read		= amd_uncore_read,
-	.capabilities	= PERF_PMU_CAP_NO_EXCLUDE,
+	.capabilities	= PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
 };
 static struct amd_uncore *amd_uncore_alloc(unsigned int cpu)

arch/x86/include/asm/io_bitmap.h+8−1

 void io_bitmap_share(struct task_struct *tsk);
 void io_bitmap_exit(void);
-void tss_update_io_bitmap(void);
+void native_tss_update_io_bitmap(void);
+#ifdef CONFIG_PARAVIRT_XXL
+#include <asm/paravirt.h>
+#else
+#define tss_update_io_bitmap native_tss_update_io_bitmap
+#endif
 #else
 static inline void io_bitmap_share(struct task_struct *tsk) { }
 static inline void io_bitmap_exit(void) { }

arch/x86/include/asm/kvm_emulate.h+12−2

 #define X86EMUL_SMM_MASK             (1 << 6)
 #define X86EMUL_SMM_INSIDE_NMI_MASK  (1 << 7)
+/*
+ * fastop functions are declared as taking a never-defined fastop parameter,
+ * so they can't be called from C directly.
+ */
+struct fastop;
+typedef void (*fastop_t)(struct fastop *);
 struct x86_emulate_ctxt {
 	const struct x86_emulate_ops *ops;
 	struct operand src;
 	struct operand src2;
 	struct operand dst;
-	int (*execute)(struct x86_emulate_ctxt *ctxt);
+	union {
+		int (*execute)(struct x86_emulate_ctxt *ctxt);
+		fastop_t fop;
+	};
 	int (*check_perm)(struct x86_emulate_ctxt *ctxt);
 	/*
 	 * The following six fields are cleared together,
 	u64 d;
 	unsigned long _eip;
 	struct operand memop;
-	/* Fields above regs are cleared together. */
 	unsigned long _regs[NR_VCPU_REGS];
 	struct operand *memopp;
 	struct fetch_cache fetch;

arch/x86/include/asm/kvm_host.h+2−1

 	int (*handle_exit)(struct kvm_vcpu *vcpu,
 		enum exit_fastpath_completion exit_fastpath);
 	int (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
+	void (*update_emulated_instruction)(struct kvm_vcpu *vcpu);
 	void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask);
 	u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu);
 	void (*patch_hypercall)(struct kvm_vcpu *vcpu,
 	void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
 	void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu);
 	void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa);
-	void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector);
+	int (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector);
 	int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu);
 	int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
 	int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr);

arch/x86/include/asm/paravirt.h+7−0

@@ -295,6 +295,13 @@ static inline void write_idt_entry(gate_desc dt, int entry, const gate_desc g) · 294 unmodified lines
295	PVOP_VCALL3(cpu.write_idt_entry, dt, entry, g);	295	PVOP_VCALL3(cpu.write_idt_entry, dt, entry, g);
296	}	296	}
297		297
		298	#ifdef CONFIG_X86_IOPL_IOPERM
		299	static inline void tss_update_io_bitmap(void)
		300	{
		301	PVOP_VCALL0(cpu.update_io_bitmap);
		302	}
		303	#endif
		304
298	static inline void paravirt_activate_mm(struct mm_struct *prev,	305	static inline void paravirt_activate_mm(struct mm_struct *prev,
299	struct mm_struct *next)	306	struct mm_struct *next)
300	{	307	{

arch/x86/include/asm/paravirt_types.h+4−0

@@ -140,6 +140,10 @@ struct pv_cpu_ops { · 139 unmodified lines
140		140
141	void (*load_sp0)(unsigned long sp0);	141	void (*load_sp0)(unsigned long sp0);
142		142
		143	#ifdef CONFIG_X86_IOPL_IOPERM
		144	void (*update_io_bitmap)(void);
		145	#endif
		146
143	void (*wbinvd)(void);	147	void (*wbinvd)(void);
144		148
145	/* cpuid emulation, mostly so that caps bits can be disabled */	149	/* cpuid emulation, mostly so that caps bits can be disabled */

arch/x86/include/asm/vmx.h+1−1

@@ -72,7 +72,7 @@ · 71 unmodified lines
72	#define SECONDARY_EXEC_MODE_BASED_EPT_EXEC VMCS_CONTROL_BIT(MODE_BASED_EPT_EXEC)	72	#define SECONDARY_EXEC_MODE_BASED_EPT_EXEC VMCS_CONTROL_BIT(MODE_BASED_EPT_EXEC)
73	#define SECONDARY_EXEC_PT_USE_GPA VMCS_CONTROL_BIT(PT_USE_GPA)	73	#define SECONDARY_EXEC_PT_USE_GPA VMCS_CONTROL_BIT(PT_USE_GPA)
74	#define SECONDARY_EXEC_TSC_SCALING VMCS_CONTROL_BIT(TSC_SCALING)	74	#define SECONDARY_EXEC_TSC_SCALING VMCS_CONTROL_BIT(TSC_SCALING)
75	#define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE 0x04000000	75	#define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE VMCS_CONTROL_BIT(USR_WAIT_PAUSE)
76		76
77	#define PIN_BASED_EXT_INTR_MASK VMCS_CONTROL_BIT(INTR_EXITING)	77	#define PIN_BASED_EXT_INTR_MASK VMCS_CONTROL_BIT(INTR_EXITING)
78	#define PIN_BASED_NMI_EXITING VMCS_CONTROL_BIT(NMI_EXITING)	78	#define PIN_BASED_NMI_EXITING VMCS_CONTROL_BIT(NMI_EXITING)

arch/x86/include/asm/vmxfeatures.h+1−0

@@ -81,6 +81,7 @@ · 80 unmodified lines
81	#define VMX_FEATURE_MODE_BASED_EPT_EXEC ( 232+ 22) / "ept_mode_based_exec" Enable separate EPT EXEC bits for supervisor vs. user */	81	#define VMX_FEATURE_MODE_BASED_EPT_EXEC ( 232+ 22) / "ept_mode_based_exec" Enable separate EPT EXEC bits for supervisor vs. user */
82	#define VMX_FEATURE_PT_USE_GPA ( 232+ 24) / "" Processor Trace logs GPAs */	82	#define VMX_FEATURE_PT_USE_GPA ( 232+ 24) / "" Processor Trace logs GPAs */
83	#define VMX_FEATURE_TSC_SCALING ( 232+ 25) / Scale hardware TSC when read in guest */	83	#define VMX_FEATURE_TSC_SCALING ( 232+ 25) / Scale hardware TSC when read in guest */
		84	#define VMX_FEATURE_USR_WAIT_PAUSE ( 232+ 26) / Enable TPAUSE, UMONITOR, UMWAIT in guest */
84	#define VMX_FEATURE_ENCLV_EXITING ( 232+ 28) / "" VM-Exit on ENCLV (leaf dependent) */	85	#define VMX_FEATURE_ENCLV_EXITING ( 232+ 28) / "" VM-Exit on ENCLV (leaf dependent) */
85		86
86	#endif /* _ASM_X86_VMXFEATURES_H */	87	#endif /* _ASM_X86_VMXFEATURES_H */

arch/x86/include/uapi/asm/kvm.h+1−0

@@ -390,6 +390,7 @@ struct kvm_sync_regs { · 389 unmodified lines
390	#define KVM_STATE_NESTED_GUEST_MODE 0x00000001	390	#define KVM_STATE_NESTED_GUEST_MODE 0x00000001
391	#define KVM_STATE_NESTED_RUN_PENDING 0x00000002	391	#define KVM_STATE_NESTED_RUN_PENDING 0x00000002
392	#define KVM_STATE_NESTED_EVMCS 0x00000004	392	#define KVM_STATE_NESTED_EVMCS 0x00000004
		393	#define KVM_STATE_NESTED_MTF_PENDING 0x00000008
393		394
394	#define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001	395	#define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001
395	#define KVM_STATE_NESTED_SMM_VMXON 0x00000002	396	#define KVM_STATE_NESTED_SMM_VMXON 0x00000002

arch/x86/kernel/apic/vector.c+8−6

 	bool managed = apicd->is_managed;
 	/*
-	 * This should never happen. Managed interrupts are not
+	 * Managed interrupts are usually not migrated away
-	 * migrated except on CPU down, which does not involve the
+	 * from an online CPU, but CPU isolation 'managed_irq'
-	 * cleanup vector. But try to keep the accounting correct
+	 * can make that happen.
-	 * nevertheless.
+	 * 1) Activation does not take the isolation into account
+	 *    to keep the code simple
+	 * 2) Migration away from an isolated CPU can happen when
+	 *    a non-isolated CPU which is in the calculated
+	 *    affinity mask comes online.
 	 */
-	WARN_ON_ONCE(managed);
 	trace_vector_free_moved(apicd->irq, cpu, vector, managed);
 	irq_matrix_free(vector_matrix, cpu, vector, managed);
 	per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;

arch/x86/kernel/cpu/common.c+1−1

@@ -445,7 +445,7 @@ static __always_inline void setup_pku(struct cpuinfo_x86 *c) · 444 unmodified lines
445	* cpuid bit to be set. We need to ensure that we	445	* cpuid bit to be set. We need to ensure that we
446	* update that bit in this CPU's "cpu_info".	446	* update that bit in this CPU's "cpu_info".
447	*/	447	*/
448	get_cpu_cap(c);	448	set_cpu_cap(c, X86_FEATURE_OSPKE);
449	}	449	}
450		450
451	#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS	451	#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS

arch/x86/kernel/cpu/mce/intel.c+5−4

 			return;
 		if ((val & 3UL) == 1UL) {
-			/* PPIN available but disabled: */
+			/* PPIN locked in disabled mode */
 			return;
 		}
-		/* If PPIN is disabled, but not locked, try to enable: */
+		/* If PPIN is disabled, try to enable */
-		if (!(val & 3UL)) {
+		if (!(val & 2UL)) {
 			wrmsrl_safe(MSR_PPIN_CTL,  val | 2UL);
 			rdmsrl_safe(MSR_PPIN_CTL, &val);
 		}
-		if ((val & 3UL) == 2UL)
+		/* Is the enable bit set? */
+		if (val & 2UL)
 			set_cpu_cap(c, X86_FEATURE_INTEL_PPIN);
 	}
 }

arch/x86/kernel/cpu/mce/therm_throt.c+7−2

 {
 	struct thermal_state *state = &per_cpu(thermal_state, cpu);
 	struct device *dev = get_cpu_device(cpu);
+	u32 l;
+	/* Mask the thermal vector before draining evtl. pending work */
+	l = apic_read(APIC_LVTTHMR);
+	apic_write(APIC_LVTTHMR, l | APIC_LVT_MASKED);
-	cancel_delayed_work(&state->package_throttle.therm_work);
+	cancel_delayed_work_sync(&state->package_throttle.therm_work);
-	cancel_delayed_work(&state->core_throttle.therm_work);
+	cancel_delayed_work_sync(&state->core_throttle.therm_work);
 	state->package_throttle.rate_control_active = false;
 	state->core_throttle.rate_control_active = false;

arch/x86/kernel/kvm.c+44−21

@@ -425,7 +425,29 @@ static void __init sev_map_percpu_data(void) · 424 unmodified lines
425	}	425	}
426	}	426	}
427		427
		428	static bool pv_tlb_flush_supported(void)
		429	{
		430	return (kvm_para_has_feature(KVM_FEATURE_PV_TLB_FLUSH) &&
		431	!kvm_para_has_hint(KVM_HINTS_REALTIME) &&
		432	kvm_para_has_feature(KVM_FEATURE_STEAL_TIME));
		433	}
		434
		435	static DEFINE_PER_CPU(cpumask_var_t, __pv_cpu_mask);
		436
428	#ifdef CONFIG_SMP	437	#ifdef CONFIG_SMP
		438
		439	static bool pv_ipi_supported(void)
		440	{
		441	return kvm_para_has_feature(KVM_FEATURE_PV_SEND_IPI);
		442	}
		443
		444	static bool pv_sched_yield_supported(void)
		445	{
		446	return (kvm_para_has_feature(KVM_FEATURE_PV_SCHED_YIELD) &&
		447	!kvm_para_has_hint(KVM_HINTS_REALTIME) &&
		448	kvm_para_has_feature(KVM_FEATURE_STEAL_TIME));
		449	}
		450
429	#define KVM_IPI_CLUSTER_SIZE (2 * BITS_PER_LONG)	451	#define KVM_IPI_CLUSTER_SIZE (2 * BITS_PER_LONG)
430		452
431	static void __send_ipi_mask(const struct cpumask *mask, int vector)	453	static void __send_ipi_mask(const struct cpumask *mask, int vector)
@@ -490,12 +512,12 @@ static void kvm_send_ipi_mask(const struct cpumask *mask, int vector) · 58 unmodified lines
490	static void kvm_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)	512	static void kvm_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
491	{	513	{
492	unsigned int this_cpu = smp_processor_id();	514	unsigned int this_cpu = smp_processor_id();
493	struct cpumask new_mask;	515	struct cpumask *new_mask = this_cpu_cpumask_var_ptr(__pv_cpu_mask);
494	const struct cpumask *local_mask;	516	const struct cpumask *local_mask;
495		517
496	cpumask_copy(&new_mask, mask);	518	cpumask_copy(new_mask, mask);
497	cpumask_clear_cpu(this_cpu, &new_mask);	519	cpumask_clear_cpu(this_cpu, new_mask);
498	local_mask = &new_mask;	520	local_mask = new_mask;
499	__send_ipi_mask(local_mask, vector);	521	__send_ipi_mask(local_mask, vector);
500	}	522	}
501		523
@@ -575,7 +597,6 @@ static void __init kvm_apf_trap_init(void) · 73 unmodified lines
575	update_intr_gate(X86_TRAP_PF, async_page_fault);	597	update_intr_gate(X86_TRAP_PF, async_page_fault);
576	}	598	}
577		599
578	static DEFINE_PER_CPU(cpumask_var_t, __pv_tlb_mask);
579		600
580	static void kvm_flush_tlb_others(const struct cpumask *cpumask,	601	static void kvm_flush_tlb_others(const struct cpumask *cpumask,
581	const struct flush_tlb_info *info)	602	const struct flush_tlb_info *info)
@@ -583,7 +604,7 @@ static void kvm_flush_tlb_others(const struct cpumask *cpumask, · 1 unmodified line
583	u8 state;	604	u8 state;
584	int cpu;	605	int cpu;
585	struct kvm_steal_time *src;	606	struct kvm_steal_time *src;
586	struct cpumask *flushmask = this_cpu_cpumask_var_ptr(__pv_tlb_mask);	607	struct cpumask *flushmask = this_cpu_cpumask_var_ptr(__pv_cpu_mask);
587		608
588	cpumask_copy(flushmask, cpumask);	609	cpumask_copy(flushmask, cpumask);
589	/*	610	/*
@@ -619,11 +640,10 @@ static void __init kvm_guest_init(void) · 29 unmodified lines
619	pv_ops.time.steal_clock = kvm_steal_clock;	640	pv_ops.time.steal_clock = kvm_steal_clock;
620	}	641	}
621		642
622	if (kvm_para_has_feature(KVM_FEATURE_PV_TLB_FLUSH) &&	643	if (pv_tlb_flush_supported()) {
623	!kvm_para_has_hint(KVM_HINTS_REALTIME) &&
624	kvm_para_has_feature(KVM_FEATURE_STEAL_TIME)) {
625	pv_ops.mmu.flush_tlb_others = kvm_flush_tlb_others;	644	pv_ops.mmu.flush_tlb_others = kvm_flush_tlb_others;
626	pv_ops.mmu.tlb_remove_table = tlb_remove_table;	645	pv_ops.mmu.tlb_remove_table = tlb_remove_table;
		646	pr_info("KVM setup pv remote TLB flush\n");
627	}	647	}
628		648
629	if (kvm_para_has_feature(KVM_FEATURE_PV_EOI))	649	if (kvm_para_has_feature(KVM_FEATURE_PV_EOI))
@@ -632,9 +652,7 @@ static void __init kvm_guest_init(void) · 2 unmodified lines
632	#ifdef CONFIG_SMP	652	#ifdef CONFIG_SMP
633	smp_ops.smp_prepare_cpus = kvm_smp_prepare_cpus;	653	smp_ops.smp_prepare_cpus = kvm_smp_prepare_cpus;
634	smp_ops.smp_prepare_boot_cpu = kvm_smp_prepare_boot_cpu;	654	smp_ops.smp_prepare_boot_cpu = kvm_smp_prepare_boot_cpu;
635	if (kvm_para_has_feature(KVM_FEATURE_PV_SCHED_YIELD) &&	655	if (pv_sched_yield_supported()) {
636	!kvm_para_has_hint(KVM_HINTS_REALTIME) &&
637	kvm_para_has_feature(KVM_FEATURE_STEAL_TIME)) {
638	smp_ops.send_call_func_ipi = kvm_smp_send_call_func_ipi;	656	smp_ops.send_call_func_ipi = kvm_smp_send_call_func_ipi;
639	pr_info("KVM setup pv sched yield\n");	657	pr_info("KVM setup pv sched yield\n");
640	}	658	}
@@ -700,7 +718,7 @@ static uint32_t __init kvm_detect(void) · 59 unmodified lines
700	static void __init kvm_apic_init(void)	718	static void __init kvm_apic_init(void)
701	{	719	{
702	#if defined(CONFIG_SMP)	720	#if defined(CONFIG_SMP)
703	if (kvm_para_has_feature(KVM_FEATURE_PV_SEND_IPI))	721	if (pv_ipi_supported())
704	kvm_setup_pv_ipi();	722	kvm_setup_pv_ipi();
705	#endif	723	#endif
706	}	724	}
@@ -732,26 +750,31 @@ static __init int activate_jump_labels(void) · 25 unmodified lines
732	}	750	}
733	arch_initcall(activate_jump_labels);	751	arch_initcall(activate_jump_labels);
734		752
735	static __init int kvm_setup_pv_tlb_flush(void)	753	static __init int kvm_alloc_cpumask(void)
736	{	754	{
737	int cpu;	755	int cpu;
		756	bool alloc = false;
738		757
739	if (!kvm_para_available() \|\| nopv)	758	if (!kvm_para_available() \|\| nopv)
740	return 0;	759	return 0;
741		760
742	if (kvm_para_has_feature(KVM_FEATURE_PV_TLB_FLUSH) &&	761	if (pv_tlb_flush_supported())
743	!kvm_para_has_hint(KVM_HINTS_REALTIME) &&	762	alloc = true;
744	kvm_para_has_feature(KVM_FEATURE_STEAL_TIME)) {	763
		764	#if defined(CONFIG_SMP)
		765	if (pv_ipi_supported())
		766	alloc = true;
		767	#endif
		768
		769	if (alloc)
745	for_each_possible_cpu(cpu) {	770	for_each_possible_cpu(cpu) {
746	zalloc_cpumask_var_node(per_cpu_ptr(&__pv_tlb_mask, cpu),	771	zalloc_cpumask_var_node(per_cpu_ptr(&__pv_cpu_mask, cpu),
747	GFP_KERNEL, cpu_to_node(cpu));	772	GFP_KERNEL, cpu_to_node(cpu));
748	}	773	}
749	pr_info("KVM setup pv remote TLB flush\n");
750	}
751		774
752	return 0;	775	return 0;
753	}	776	}
754	arch_initcall(kvm_setup_pv_tlb_flush);	777	arch_initcall(kvm_alloc_cpumask);
755		778
756	#ifdef CONFIG_PARAVIRT_SPINLOCKS	779	#ifdef CONFIG_PARAVIRT_SPINLOCKS
757		780

arch/x86/kernel/paravirt.c+5−0

 #include <asm/timer.h>
 #include <asm/special_insns.h>
 #include <asm/tlb.h>
+#include <asm/io_bitmap.h>
 /*
  * nop stub, which must not clobber anything *including the stack* to
 	.cpu.iret		= native_iret,
 	.cpu.swapgs		= native_swapgs,
+#ifdef CONFIG_X86_IOPL_IOPERM
+	.cpu.update_io_bitmap	= native_tss_update_io_bitmap,
+#endif
 	.cpu.start_context_switch	= paravirt_nop,
 	.cpu.end_context_switch		= paravirt_nop,

arch/x86/kernel/process.c+1−1

@@ -374,7 +374,7 @@ static void tss_copy_io_bitmap(struct tss_struct tss, struct io_bitmap iobm) · 373 unmodified lines
374	/**	374	/**
375	* tss_update_io_bitmap - Update I/O bitmap before exiting to usermode	375	* tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
376	*/	376	*/
377	void tss_update_io_bitmap(void)	377	void native_tss_update_io_bitmap(void)
378	{	378	{
379	struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);	379	struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
380	struct thread_struct *t = &current->thread;	380	struct thread_struct *t = &current->thread;

arch/x86/kvm/Kconfig+13−0

@@ -59,6 +59,19 @@ config KVM · 58 unmodified lines
59		59
60	If unsure, say N.	60	If unsure, say N.
61		61
		62	config KVM_WERROR
		63	bool "Compile KVM with -Werror"
		64	# KASAN may cause the build to fail due to larger frames
		65	default y if X86_64 && !KASAN
		66	# We use the dependency on !COMPILE_TEST to not be enabled
		67	# blindly in allmodconfig or allyesconfig configurations
		68	depends on (X86_64 && !KASAN) \|\| !COMPILE_TEST
		69	depends on EXPERT
		70	help
		71	Add -Werror to the build flags for KVM.
		72
		73	If in doubt, say "N".
		74
62	config KVM_INTEL	75	config KVM_INTEL
63	tristate "KVM for Intel (and compatible) processors support"	76	tristate "KVM for Intel (and compatible) processors support"
64	depends on KVM && IA32_FEAT_CTL	77	depends on KVM && IA32_FEAT_CTL

arch/x86/kvm/Makefile+1−0

@@ -1,6 +1,7 @@
1	# SPDX-License-Identifier: GPL-2.0	1	# SPDX-License-Identifier: GPL-2.0
2		2
3	ccflags-y += -Iarch/x86/kvm	3	ccflags-y += -Iarch/x86/kvm
		4	ccflags-$(CONFIG_KVM_WERROR) += -Werror
4		5
5	KVM := ../../../virt/kvm	6	KVM := ../../../virt/kvm
6		7

arch/x86/kvm/emulate.c+15−22

@@ -191,25 +191,6 @@ · 190 unmodified lines
191	#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)	191	#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
192	#define FASTOP_SIZE 8	192	#define FASTOP_SIZE 8
193		193
194	/*
195	* fastop functions have a special calling convention:
196	*
197	* dst: rax (in/out)
198	* src: rdx (in/out)
199	* src2: rcx (in)
200	* flags: rflags (in/out)
201	* ex: rsi (in:fastop pointer, out:zero if exception)
202	*
203	* Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
204	* different operand sizes can be reached by calculation, rather than a jump
205	* table (which would be bigger than the code).
206	*
207	* fastop functions are declared as taking a never-defined fastop parameter,
208	* so they can't be called from C directly.
209	*/
210
211	struct fastop;
212
213	struct opcode {	194	struct opcode {
214	u64 flags : 56;	195	u64 flags : 56;
215	u64 intercept : 8;	196	u64 intercept : 8;
@@ -311,8 +292,19 @@ static void invalidate_registers(struct x86_emulate_ctxt *ctxt) · 95 unmodified lines
311	#define ON64(x)	292	#define ON64(x)
312	#endif	293	#endif
313		294
314	typedef void (fastop_t)(struct fastop );	295	/*
315		296	* fastop functions have a special calling convention:
		297	*
		298	* dst: rax (in/out)
		299	* src: rdx (in/out)
		300	* src2: rcx (in)
		301	* flags: rflags (in/out)
		302	* ex: rsi (in:fastop pointer, out:zero if exception)
		303	*
		304	* Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
		305	* different operand sizes can be reached by calculation, rather than a jump
		306	* table (which would be bigger than the code).
		307	*/
316	static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop);	308	static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop);
317		309
318	#define __FOP_FUNC(name) \	310	#define __FOP_FUNC(name) \
@@ -5181,6 +5173,7 @@ int x86_decode_insn(struct x86_emulate_ctxt ctxt, void insn, int insn_len) · 4862 unmodified lines
5181	ctxt->fetch.ptr = ctxt->fetch.data;	5173	ctxt->fetch.ptr = ctxt->fetch.data;
5182	ctxt->fetch.end = ctxt->fetch.data + insn_len;	5174	ctxt->fetch.end = ctxt->fetch.data + insn_len;
5183	ctxt->opcode_len = 1;	5175	ctxt->opcode_len = 1;
		5176	ctxt->intercept = x86_intercept_none;
5184	if (insn_len > 0)	5177	if (insn_len > 0)
5185	memcpy(ctxt->fetch.data, insn, insn_len);	5178	memcpy(ctxt->fetch.data, insn, insn_len);
5186	else {	5179	else {
@@ -5683,7 +5676,7 @@ special_insn: · 496 unmodified lines
5683		5676
5684	if (ctxt->execute) {	5677	if (ctxt->execute) {
5685	if (ctxt->d & Fastop)	5678	if (ctxt->d & Fastop)
5686	rc = fastop(ctxt, (fastop_t)ctxt->execute);	5679	rc = fastop(ctxt, ctxt->fop);
5687	else	5680	else
5688	rc = ctxt->execute(ctxt);	5681	rc = ctxt->execute(ctxt);
5689	if (rc != X86EMUL_CONTINUE)	5682	if (rc != X86EMUL_CONTINUE)

arch/x86/kvm/ioapic.c+5−2

 		if (e->fields.delivery_mode == APIC_DM_FIXED) {
 			struct kvm_lapic_irq irq;
-			irq.shorthand = APIC_DEST_NOSHORT;
 			irq.vector = e->fields.vector;
 			irq.delivery_mode = e->fields.delivery_mode << 8;
-			irq.dest_id = e->fields.dest_id;
 			irq.dest_mode =
 			    kvm_lapic_irq_dest_mode(!!e->fields.dest_mode);
+			irq.level = false;
+			irq.trig_mode = e->fields.trig_mode;
+			irq.shorthand = APIC_DEST_NOSHORT;
+			irq.dest_id = e->fields.dest_id;
+			irq.msi_redir_hint = false;
 			bitmap_zero(&vcpu_bitmap, 16);
 			kvm_bitmap_or_dest_vcpus(ioapic->kvm, &irq,
 						 &vcpu_bitmap);

arch/x86/kvm/irq_comm.c+1−1

@@ -417,7 +417,7 @@ void kvm_scan_ioapic_routes(struct kvm_vcpu *vcpu, · 416 unmodified lines
417		417
418	kvm_set_msi_irq(vcpu->kvm, entry, &irq);	418	kvm_set_msi_irq(vcpu->kvm, entry, &irq);
419		419
420	if (irq.level &&	420	if (irq.trig_mode &&
421	kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,	421	kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
422	irq.dest_id, irq.dest_mode))	422	irq.dest_id, irq.dest_mode))
423	__set_bit(irq.vector, ioapic_handled_vectors);	423	__set_bit(irq.vector, ioapic_handled_vectors);

arch/x86/kvm/lapic.c+4−5

 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 {
 	u8 val;
-	if (pv_eoi_get_user(vcpu, &val) < 0)
+	if (pv_eoi_get_user(vcpu, &val) < 0) {
 		printk(KERN_WARNING "Can't read EOI MSR value: 0x%llx\n",
 			   (unsigned long long)vcpu->arch.pv_eoi.msr_val);
+		return false;
+	}
 	return val & 0x1;
 }
 						       apic->regs + APIC_TMR);
 		}
-		if (vcpu->arch.apicv_active)
+		if (kvm_x86_ops->deliver_posted_interrupt(vcpu, vector)) {
-			kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
-		else {
 			kvm_lapic_set_irr(vector, apic);
 			kvm_make_request(KVM_REQ_EVENT, vcpu);
 			kvm_vcpu_kick(vcpu);
 		}

arch/x86/kvm/mmutrace.h+1−1

@@ -339,7 +339,7 @@ TRACE_EVENT( · 338 unmodified lines
339	/* These depend on page entry type, so compute them now. */	339	/* These depend on page entry type, so compute them now. */
340	__field(bool, r)	340	__field(bool, r)
341	__field(bool, x)	341	__field(bool, x)
342	__field(u8, u)	342	__field(signed char, u)
343	),	343	),
344		344
345	TP_fast_assign(	345	TP_fast_assign(

arch/x86/kvm/svm.c+42−31

 MODULE_AUTHOR("Qumranet");
 MODULE_LICENSE("GPL");
+#ifdef MODULE
 static const struct x86_cpu_id svm_cpu_id[] = {
 	X86_FEATURE_MATCH(X86_FEATURE_SVM),
 	{}
 };
 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
+#endif
 #define IOPM_ALLOC_ORDER 2
 #define MSRPM_ALLOC_ORDER 1
 static int svm_cpu_init(int cpu)
 {
 	struct svm_cpu_data *sd;
-	int r;
 	sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 	if (!sd)
 		return -ENOMEM;
 	sd->cpu = cpu;
-	r = -ENOMEM;
 	sd->save_area = alloc_page(GFP_KERNEL);
 	if (!sd->save_area)
-		goto err_1;
+		goto free_cpu_data;
 	if (svm_sev_enabled()) {
-		r = -ENOMEM;
 		sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
 					      sizeof(void *),
 					      GFP_KERNEL);
 		if (!sd->sev_vmcbs)
-			goto err_1;
+			goto free_save_area;
 	}
 	per_cpu(svm_data, cpu) = sd;
 	return 0;
-err_1:
+free_save_area:
+	__free_page(sd->save_area);
+free_cpu_data:
 	kfree(sd);
-	return r;
+	return -ENOMEM;
 }
 	kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
 }
+static void svm_hardware_teardown(void)
+{
+	int cpu;
+	if (svm_sev_enabled()) {
+		bitmap_free(sev_asid_bitmap);
+		bitmap_free(sev_reclaim_asid_bitmap);
+		sev_flush_asids();
+	}
+	for_each_possible_cpu(cpu)
+		svm_cpu_uninit(cpu);
+	__free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
+	iopm_base = 0;
+}
 static __init int svm_hardware_setup(void)
 {
 	int cpu;
 	return 0;
 err:
-	__free_pages(iopm_pages, IOPM_ALLOC_ORDER);
+	svm_hardware_teardown();
-	iopm_base = 0;
 	return r;
 }
-static __exit void svm_hardware_unsetup(void)
-{
-	int cpu;
-	if (svm_sev_enabled()) {
-		bitmap_free(sev_asid_bitmap);
-		bitmap_free(sev_reclaim_asid_bitmap);
-		sev_flush_asids();
-	}
-	for_each_possible_cpu(cpu)
-		svm_cpu_uninit(cpu);
-	__free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
-	iopm_base = 0;
-}
 static void init_seg(struct vmcb_seg *seg)
 {
 	seg->selector = 0;
 static int avic_init_vcpu(struct vcpu_svm *svm)
 {
 	int ret;
+	struct kvm_vcpu *vcpu = &svm->vcpu;
-	if (!kvm_vcpu_apicv_active(&svm->vcpu))
+	if (!avic || !irqchip_in_kernel(vcpu->kvm))
 		return 0;
 	ret = avic_init_backing_page(&svm->vcpu);
 	struct vmcb *vmcb = svm->vmcb;
 	bool activated = kvm_vcpu_apicv_active(vcpu);
+	if (!avic)
+		return;
 	if (activated) {
 		/**
 		 * During AVIC temporary deactivation, guest could update
 	return;
 }
-static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
+static int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
 {
+	if (!vcpu->arch.apicv_active)
+		return -1;
 	kvm_lapic_set_irr(vec, vcpu->arch.apic);
 	smp_mb__after_atomic();
 		put_cpu();
 	} else
 		kvm_vcpu_wake_up(vcpu);
+	return 0;
 }
 static bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
 	enum exit_fastpath_completion *exit_fastpath)
 {
 	if (!is_guest_mode(vcpu) &&
-		to_svm(vcpu)->vmcb->control.exit_code == EXIT_REASON_MSR_WRITE)
+	    to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
+	    to_svm(vcpu)->vmcb->control.exit_info_1)
 		*exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
 }
 	.cpu_has_kvm_support = has_svm,
 	.disabled_by_bios = is_disabled,
 	.hardware_setup = svm_hardware_setup,
-	.hardware_unsetup = svm_hardware_unsetup,
+	.hardware_unsetup = svm_hardware_teardown,
 	.check_processor_compatibility = svm_check_processor_compat,
 	.hardware_enable = svm_hardware_enable,
 	.hardware_disable = svm_hardware_disable,
 	.run = svm_vcpu_run,
 	.handle_exit = handle_exit,
 	.skip_emulated_instruction = skip_emulated_instruction,
+	.update_emulated_instruction = NULL,
 	.set_interrupt_shadow = svm_set_interrupt_shadow,
 	.get_interrupt_shadow = svm_get_interrupt_shadow,
 	.patch_hypercall = svm_patch_hypercall,

arch/x86/kvm/vmx/capabilities.h+1−0

@@ -12,6 +12,7 @@ extern bool __read_mostly enable_ept; · 11 unmodified lines
12	extern bool __read_mostly enable_unrestricted_guest;	12	extern bool __read_mostly enable_unrestricted_guest;
13	extern bool __read_mostly enable_ept_ad_bits;	13	extern bool __read_mostly enable_ept_ad_bits;
14	extern bool __read_mostly enable_pml;	14	extern bool __read_mostly enable_pml;
		15	extern bool __read_mostly enable_apicv;
15	extern int __read_mostly pt_mode;	16	extern int __read_mostly pt_mode;
16		17
17	#define PT_MODE_SYSTEM 0	18	#define PT_MODE_SYSTEM 0

arch/x86/kvm/vmx/nested.c+69−25

@@ -224,7 +224,7 @@ static inline void nested_release_evmcs(struct kvm_vcpu *vcpu) · 223 unmodified lines
224	return;	224	return;
225		225
226	kvm_vcpu_unmap(vcpu, &vmx->nested.hv_evmcs_map, true);	226	kvm_vcpu_unmap(vcpu, &vmx->nested.hv_evmcs_map, true);
227	vmx->nested.hv_evmcs_vmptr = -1ull;	227	vmx->nested.hv_evmcs_vmptr = 0;
228	vmx->nested.hv_evmcs = NULL;	228	vmx->nested.hv_evmcs = NULL;
229	}	229	}
230		230
@@ -1923,7 +1923,8 @@ static int nested_vmx_handle_enlightened_vmptrld(struct kvm_vcpu *vcpu, · 1692 unmodified lines
1923	if (!nested_enlightened_vmentry(vcpu, &evmcs_gpa))	1923	if (!nested_enlightened_vmentry(vcpu, &evmcs_gpa))
1924	return 1;	1924	return 1;
1925		1925
1926	if (unlikely(evmcs_gpa != vmx->nested.hv_evmcs_vmptr)) {	1926	if (unlikely(!vmx->nested.hv_evmcs \|\|
		1927	evmcs_gpa != vmx->nested.hv_evmcs_vmptr)) {
1927	if (!vmx->nested.hv_evmcs)	1928	if (!vmx->nested.hv_evmcs)
1928	vmx->nested.current_vmptr = -1ull;	1929	vmx->nested.current_vmptr = -1ull;
1929		1930
@@ -3161,10 +3162,10 @@ static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, · 1231 unmodified lines
3161	* or KVM_SET_NESTED_STATE). Otherwise it's called from vmlaunch/vmresume.	3162	* or KVM_SET_NESTED_STATE). Otherwise it's called from vmlaunch/vmresume.
3162	*	3163	*
3163	* Returns:	3164	* Returns:
3164	* NVMX_ENTRY_SUCCESS: Entered VMX non-root mode	3165	* NVMX_VMENTRY_SUCCESS: Entered VMX non-root mode
3165	* NVMX_ENTRY_VMFAIL: Consistency check VMFail	3166	* NVMX_VMENTRY_VMFAIL: Consistency check VMFail
3166	* NVMX_ENTRY_VMEXIT: Consistency check VMExit	3167	* NVMX_VMENTRY_VMEXIT: Consistency check VMExit
3167	* NVMX_ENTRY_KVM_INTERNAL_ERROR: KVM internal error	3168	* NVMX_VMENTRY_KVM_INTERNAL_ERROR: KVM internal error
3168	*/	3169	*/
3169	enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,	3170	enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
3170	bool from_vmentry)	3171	bool from_vmentry)
@@ -3609,8 +3610,15 @@ static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) · 438 unmodified lines
3609	unsigned long exit_qual;	3610	unsigned long exit_qual;
3610	bool block_nested_events =	3611	bool block_nested_events =
3611	vmx->nested.nested_run_pending \|\| kvm_event_needs_reinjection(vcpu);	3612	vmx->nested.nested_run_pending \|\| kvm_event_needs_reinjection(vcpu);
		3613	bool mtf_pending = vmx->nested.mtf_pending;
3612	struct kvm_lapic *apic = vcpu->arch.apic;	3614	struct kvm_lapic *apic = vcpu->arch.apic;
3613		3615
		3616	/*
		3617	* Clear the MTF state. If a higher priority VM-exit is delivered first,
		3618	* this state is discarded.
		3619	*/
		3620	vmx->nested.mtf_pending = false;
		3621
3614	if (lapic_in_kernel(vcpu) &&	3622	if (lapic_in_kernel(vcpu) &&
3615	test_bit(KVM_APIC_INIT, &apic->pending_events)) {	3623	test_bit(KVM_APIC_INIT, &apic->pending_events)) {
3616	if (block_nested_events)	3624	if (block_nested_events)
@@ -3621,8 +3629,28 @@ static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) · 4 unmodified lines
3621	return 0;	3629	return 0;
3622	}	3630	}
3623		3631
		3632	/*
		3633	* Process any exceptions that are not debug traps before MTF.
		3634	*/
		3635	if (vcpu->arch.exception.pending &&
		3636	!vmx_pending_dbg_trap(vcpu) &&
		3637	nested_vmx_check_exception(vcpu, &exit_qual)) {
		3638	if (block_nested_events)
		3639	return -EBUSY;
		3640	nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
		3641	return 0;
		3642	}
		3643
		3644	if (mtf_pending) {
		3645	if (block_nested_events)
		3646	return -EBUSY;
		3647	nested_vmx_update_pending_dbg(vcpu);
		3648	nested_vmx_vmexit(vcpu, EXIT_REASON_MONITOR_TRAP_FLAG, 0, 0);
		3649	return 0;
		3650	}
		3651
3624	if (vcpu->arch.exception.pending &&	3652	if (vcpu->arch.exception.pending &&
3625	nested_vmx_check_exception(vcpu, &exit_qual)) {	3653	nested_vmx_check_exception(vcpu, &exit_qual)) {
3626	if (block_nested_events)	3654	if (block_nested_events)
3627	return -EBUSY;	3655	return -EBUSY;
3628	nested_vmx_inject_exception_vmexit(vcpu, exit_qual);	3656	nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
@@ -5285,24 +5313,17 @@ fail: · 1656 unmodified lines
5285	return 1;	5313	return 1;
5286	}	5314	}
5287		5315
5288		5316	/*
5289	static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,	5317	* Return true if an IO instruction with the specified port and size should cause
5290	struct vmcs12 *vmcs12)	5318	* a VM-exit into L1.
		5319	*/
		5320	bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port,
		5321	int size)
5291	{	5322	{
5292	unsigned long exit_qualification;	5323	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5293	gpa_t bitmap, last_bitmap;	5324	gpa_t bitmap, last_bitmap;
5294	unsigned int port;
5295	int size;
5296	u8 b;	5325	u8 b;
5297		5326
5298	if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5299	return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
5300
5301	exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5302
5303	port = exit_qualification >> 16;
5304	size = (exit_qualification & 7) + 1;
5305
5306	last_bitmap = (gpa_t)-1;	5327	last_bitmap = (gpa_t)-1;
5307	b = -1;	5328	b = -1;
5308		5329
@@ -5329,8 +5350,26 @@ static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, · 20 unmodified lines
5329	return false;	5350	return false;
5330	}	5351	}
5331		5352
		5353	static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
		5354	struct vmcs12 *vmcs12)
		5355	{
		5356	unsigned long exit_qualification;
		5357	unsigned short port;
		5358	int size;
		5359
		5360	if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
		5361	return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
		5362
		5363	exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
		5364
		5365	port = exit_qualification >> 16;
		5366	size = (exit_qualification & 7) + 1;
		5367
		5368	return nested_vmx_check_io_bitmaps(vcpu, port, size);
		5369	}
		5370
5332	/*	5371	/*
5333	* Return 1 if we should exit from L2 to L1 to handle an MSR access access,	5372	* Return 1 if we should exit from L2 to L1 to handle an MSR access,
5334	* rather than handle it ourselves in L0. I.e., check whether L1 expressed	5373	* rather than handle it ourselves in L0. I.e., check whether L1 expressed
5335	* disinterest in the current event (read or write a specific MSR) by using an	5374	* disinterest in the current event (read or write a specific MSR) by using an
5336	* MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.	5375	* MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
@@ -5712,6 +5751,9 @@ static int vmx_get_nested_state(struct kvm_vcpu *vcpu, · 375 unmodified lines
5712		5751
5713	if (vmx->nested.nested_run_pending)	5752	if (vmx->nested.nested_run_pending)
5714	kvm_state.flags \|= KVM_STATE_NESTED_RUN_PENDING;	5753	kvm_state.flags \|= KVM_STATE_NESTED_RUN_PENDING;
		5754
		5755	if (vmx->nested.mtf_pending)
		5756	kvm_state.flags \|= KVM_STATE_NESTED_MTF_PENDING;
5715	}	5757	}
5716	}	5758	}
5717		5759
@@ -5892,6 +5934,9 @@ static int vmx_set_nested_state(struct kvm_vcpu *vcpu, · 174 unmodified lines
5892	vmx->nested.nested_run_pending =	5934	vmx->nested.nested_run_pending =
5893	!!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);	5935	!!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);
5894		5936
		5937	vmx->nested.mtf_pending =
		5938	!!(kvm_state->flags & KVM_STATE_NESTED_MTF_PENDING);
		5939
5895	ret = -EINVAL;	5940	ret = -EINVAL;
5896	if (nested_cpu_has_shadow_vmcs(vmcs12) &&	5941	if (nested_cpu_has_shadow_vmcs(vmcs12) &&
5897	vmcs12->vmcs_link_pointer != -1ull) {	5942	vmcs12->vmcs_link_pointer != -1ull) {
@@ -5949,8 +5994,7 @@ void nested_vmx_set_vmcs_shadowing_bitmap(void) · 51 unmodified lines
5949	* bit in the high half is on if the corresponding bit in the control field	5994	* bit in the high half is on if the corresponding bit in the control field
5950	* may be on. See also vmx_control_verify().	5995	* may be on. See also vmx_control_verify().
5951	*/	5996	*/
5952	void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps,	5997	void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps)
5953	bool apicv)
5954	{	5998	{
5955	/*	5999	/*
5956	* Note that as a general rule, the high half of the MSRs (bits in	6000	* Note that as a general rule, the high half of the MSRs (bits in
@@ -5977,7 +6021,7 @@ void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps, · 20 unmodified lines
5977	PIN_BASED_EXT_INTR_MASK \|	6021	PIN_BASED_EXT_INTR_MASK \|
5978	PIN_BASED_NMI_EXITING \|	6022	PIN_BASED_NMI_EXITING \|
5979	PIN_BASED_VIRTUAL_NMIS \|	6023	PIN_BASED_VIRTUAL_NMIS \|
5980	(apicv ? PIN_BASED_POSTED_INTR : 0);	6024	(enable_apicv ? PIN_BASED_POSTED_INTR : 0);
5981	msrs->pinbased_ctls_high \|=	6025	msrs->pinbased_ctls_high \|=
5982	PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR \|	6026	PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR \|
5983	PIN_BASED_VMX_PREEMPTION_TIMER;	6027	PIN_BASED_VMX_PREEMPTION_TIMER;

arch/x86/kvm/vmx/nested.h+8−2

 };
 void vmx_leave_nested(struct kvm_vcpu *vcpu);
-void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps,
+void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps);
-				bool apicv);
 void nested_vmx_hardware_unsetup(void);
 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *));
 void nested_vmx_set_vmcs_shadowing_bitmap(void);
 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification,
 			u32 vmx_instruction_info, bool wr, int len, gva_t *ret);
 void nested_vmx_pmu_entry_exit_ctls_update(struct kvm_vcpu *vcpu);
+bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port,
+				 int size);
 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 {
 	return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 }
+static inline int nested_cpu_has_mtf(struct vmcs12 *vmcs12)
+{
+	return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
+}
 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
 {
 	return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);

arch/x86/kvm/vmx/vmx.c+141−22

 MODULE_AUTHOR("Qumranet");
 MODULE_LICENSE("GPL");
+#ifdef MODULE
 static const struct x86_cpu_id vmx_cpu_id[] = {
 	X86_FEATURE_MATCH(X86_FEATURE_VMX),
 	{}
 };
 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
+#endif
 bool __read_mostly enable_vpid = 1;
 module_param_named(vpid, enable_vpid, bool, 0444);
 static bool __read_mostly fasteoi = 1;
 module_param(fasteoi, bool, S_IRUGO);
-static bool __read_mostly enable_apicv = 1;
+bool __read_mostly enable_apicv = 1;
 module_param(enable_apicv, bool, S_IRUGO);
 /*
 					   vmx->guest_msrs[i].mask);
 	}
+    	if (vmx->nested.need_vmcs12_to_shadow_sync)
+		nested_sync_vmcs12_to_shadow(vcpu);
 	if (vmx->guest_state_loaded)
 		return;
 	return 1;
 }
+/*
+ * Recognizes a pending MTF VM-exit and records the nested state for later
+ * delivery.
+ */
+static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
+{
+	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
+	struct vcpu_vmx *vmx = to_vmx(vcpu);
+	if (!is_guest_mode(vcpu))
+		return;
+	/*
+	 * Per the SDM, MTF takes priority over debug-trap exceptions besides
+	 * T-bit traps. As instruction emulation is completed (i.e. at the
+	 * instruction boundary), any #DB exception pending delivery must be a
+	 * debug-trap. Record the pending MTF state to be delivered in
+	 * vmx_check_nested_events().
+	 */
+	if (nested_cpu_has_mtf(vmcs12) &&
+	    (!vcpu->arch.exception.pending ||
+	     vcpu->arch.exception.nr == DB_VECTOR))
+		vmx->nested.mtf_pending = true;
+	else
+		vmx->nested.mtf_pending = false;
+}
+static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
+{
+	vmx_update_emulated_instruction(vcpu);
+	return skip_emulated_instruction(vcpu);
+}
 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
 {
 	/*
 	kvm_cpu_vmxoff();
 }
+/*
+ * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
+ * directly instead of going through cpu_has(), to ensure KVM is trapping
+ * ENCLS whenever it's supported in hardware.  It does not matter whether
+ * the host OS supports or has enabled SGX.
+ */
+static bool cpu_has_sgx(void)
+{
+	return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
+}
 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
 				      u32 msr, u32 *result)
 {
 			SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
 			SECONDARY_EXEC_PT_USE_GPA |
 			SECONDARY_EXEC_PT_CONCEAL_VMX |
-			SECONDARY_EXEC_ENABLE_VMFUNC |
+			SECONDARY_EXEC_ENABLE_VMFUNC;
-			SECONDARY_EXEC_ENCLS_EXITING;
+		if (cpu_has_sgx())
+			opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
 		if (adjust_vmx_controls(min2, opt2,
 					MSR_IA32_VMX_PROCBASED_CTLS2,
 					&_cpu_based_2nd_exec_control) < 0)
  * 2. If target vcpu isn't running(root mode), kick it to pick up the
  * interrupt from PIR in next vmentry.
  */
-static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
+static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
 {
 	struct vcpu_vmx *vmx = to_vmx(vcpu);
 	int r;
 	r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
 	if (!r)
-		return;
+		return 0;
+	if (!vcpu->arch.apicv_active)
+		return -1;
 	if (pi_test_and_set_pir(vector, &vmx->pi_desc))
-		return;
+		return 0;
 	/* If a previous notification has sent the IPI, nothing to do.  */
 	if (pi_test_and_set_on(&vmx->pi_desc))
-		return;
+		return 0;
 	if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
 		kvm_vcpu_kick(vcpu);
+	return 0;
 }
 /*
 		vmcs_write32(PLE_WINDOW, vmx->ple_window);
 	}
-	if (vmx->nested.need_vmcs12_to_shadow_sync)
+	/*
-		nested_sync_vmcs12_to_shadow(vcpu);
+	 * We did this in prepare_switch_to_guest, because it needs to
+	 * be within srcu_read_lock.
+	 */
+	WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
 	if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
 		vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
 	if (nested)
 		nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
-					   vmx_capability.ept,
+					   vmx_capability.ept);
-					   kvm_vcpu_apicv_active(vcpu));
 	else
 		memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
 	if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
 		return -EIO;
 	if (nested)
-		nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
+		nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
-					   enable_apicv);
 	if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
 		printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
 				smp_processor_id());
 	to_vmx(vcpu)->req_immediate_exit = true;
 }
+static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
+				  struct x86_instruction_info *info)
+{
+	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
+	unsigned short port;
+	bool intercept;
+	int size;
+	if (info->intercept == x86_intercept_in ||
+	    info->intercept == x86_intercept_ins) {
+		port = info->src_val;
+		size = info->dst_bytes;
+	} else {
+		port = info->dst_val;
+		size = info->src_bytes;
+	}
+	/*
+	 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
+	 * VM-exits depend on the 'unconditional IO exiting' VM-execution
+	 * control.
+	 *
+	 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
+	 */
+	if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
+		intercept = nested_cpu_has(vmcs12,
+					   CPU_BASED_UNCOND_IO_EXITING);
+	else
+		intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
+	/* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
+	return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
+}
 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
 			       struct x86_instruction_info *info,
 			       enum x86_intercept_stage stage)
 	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
+	switch (info->intercept) {
 	/*
 	 * RDPID causes #UD if disabled through secondary execution controls.
 	 * Because it is marked as EmulateOnUD, we need to intercept it here.
 	 */
-	if (info->intercept == x86_intercept_rdtscp &&
+	case x86_intercept_rdtscp:
-	    !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
+		if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
-		ctxt->exception.vector = UD_VECTOR;
+			ctxt->exception.vector = UD_VECTOR;
-		ctxt->exception.error_code_valid = false;
+			ctxt->exception.error_code_valid = false;
-		return X86EMUL_PROPAGATE_FAULT;
+			return X86EMUL_PROPAGATE_FAULT;
-	}
+		}
+		break;
+	case x86_intercept_in:
+	case x86_intercept_ins:
+	case x86_intercept_out:
+	case x86_intercept_outs:
+		return vmx_check_intercept_io(vcpu, info);
+	case x86_intercept_lgdt:
+	case x86_intercept_lidt:
+	case x86_intercept_lldt:
+	case x86_intercept_ltr:
+	case x86_intercept_sgdt:
+	case x86_intercept_sidt:
+	case x86_intercept_sldt:
+	case x86_intercept_str:
+		if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
+			return X86EMUL_CONTINUE;
+		/* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
+		break;
 	/* TODO: check more intercepts... */
-	return X86EMUL_CONTINUE;
+	default:
+		break;
+	}
+	return X86EMUL_UNHANDLEABLE;
 }
 #ifdef CONFIG_X86_64
 	if (nested) {
 		nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
-					   vmx_capability.ept, enable_apicv);
+					   vmx_capability.ept);
 		r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
 		if (r)
 	.run = vmx_vcpu_run,
 	.handle_exit = vmx_handle_exit,
-	.skip_emulated_instruction = skip_emulated_instruction,
+	.skip_emulated_instruction = vmx_skip_emulated_instruction,
+	.update_emulated_instruction = vmx_update_emulated_instruction,
 	.set_interrupt_shadow = vmx_set_interrupt_shadow,
 	.get_interrupt_shadow = vmx_get_interrupt_shadow,
 	.patch_hypercall = vmx_patch_hypercall,

arch/x86/kvm/vmx/vmx.h+3−0

@@ -150,6 +150,9 @@ struct nested_vmx { · 149 unmodified lines
150	/* L2 must run next, and mustn't decide to exit to L1. */	150	/* L2 must run next, and mustn't decide to exit to L1. */
151	bool nested_run_pending;	151	bool nested_run_pending;
152		152
		153	/* Pending MTF VM-exit into L1. */
		154	bool mtf_pending;
		155
153	struct loaded_vmcs vmcs02;	156	struct loaded_vmcs vmcs02;
154		157
155	/*	158	/*

arch/x86/kvm/x86.c+11−7

 			kvm_rip_write(vcpu, ctxt->eip);
 			if (r && ctxt->tf)
 				r = kvm_vcpu_do_singlestep(vcpu);
+			if (kvm_x86_ops->update_emulated_instruction)
+				kvm_x86_ops->update_emulated_instruction(vcpu);
 			__kvm_set_rflags(vcpu, ctxt->eflags);
 		}
 	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
 #ifdef CONFIG_CPU_FREQ
-		struct cpufreq_policy policy;
+		struct cpufreq_policy *policy;
 		int cpu;
-		memset(&policy, 0, sizeof(policy));
 		cpu = get_cpu();
-		cpufreq_get_policy(&policy, cpu);
+		policy = cpufreq_cpu_get(cpu);
-		if (policy.cpuinfo.max_freq)
+		if (policy) {
-			max_tsc_khz = policy.cpuinfo.max_freq;
+			if (policy->cpuinfo.max_freq)
+				max_tsc_khz = policy->cpuinfo.max_freq;
+			cpufreq_cpu_put(policy);
+		}
 		put_cpu();
 #endif
 		cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
 	}
 	if (!ops->cpu_has_kvm_support()) {
-		printk(KERN_ERR "kvm: no hardware support\n");
+		pr_err_ratelimited("kvm: no hardware support\n");
 		r = -EOPNOTSUPP;
 		goto out;
 	}
 	if (ops->disabled_by_bios()) {
-		printk(KERN_ERR "kvm: disabled by bios\n");
+		pr_err_ratelimited("kvm: disabled by bios\n");
 		r = -EOPNOTSUPP;
 		goto out;
 	}

arch/x86/mm/dump_pagetables.c+1−6

 {
 	const struct ptdump_range ptdump_ranges[] = {
 #ifdef CONFIG_X86_64
-#define normalize_addr_shift (64 - (__VIRTUAL_MASK_SHIFT + 1))
-#define normalize_addr(u) ((signed long)((u) << normalize_addr_shift) >> \
-			   normalize_addr_shift)
 	{0, PTRS_PER_PGD * PGD_LEVEL_MULT / 2},
-	{normalize_addr(PTRS_PER_PGD * PGD_LEVEL_MULT / 2), ~0UL},
+	{GUARD_HOLE_END_ADDR, ~0UL},
 #else
 	{0, ~0UL},
 #endif

arch/x86/mm/ioremap.c+18−0

 	return 0;
 }
+/*
+ * The EFI runtime services data area is not covered by walk_mem_res(), but must
+ * be mapped encrypted when SEV is active.
+ */
+static void __ioremap_check_other(resource_size_t addr, struct ioremap_desc *desc)
+{
+	if (!sev_active())
+		return;
+	if (efi_mem_type(addr) == EFI_RUNTIME_SERVICES_DATA)
+		desc->flags |= IORES_MAP_ENCRYPTED;
+}
 static int __ioremap_collect_map_flags(struct resource *res, void *arg)
 {
 	struct ioremap_desc *desc = arg;
  * To avoid multiple resource walks, this function walks resources marked as
  * IORESOURCE_MEM and IORESOURCE_BUSY and looking for system RAM and/or a
  * resource described not as IORES_DESC_NONE (e.g. IORES_DESC_ACPI_TABLES).
+ *
+ * After that, deal with misc other ranges in __ioremap_check_other() which do
+ * not fall into the above category.
  */
 static void __ioremap_check_mem(resource_size_t addr, unsigned long size,
 				struct ioremap_desc *desc)
 	memset(desc, 0, sizeof(struct ioremap_desc));
 	walk_mem_res(start, end, desc, __ioremap_collect_map_flags);
+	__ioremap_check_other(addr, desc);
 }
 /*

arch/x86/platform/efi/efi_64.c+52−99

 static inline phys_addr_t
 virt_to_phys_or_null_size(void *va, unsigned long size)
 {
-	bool bad_size;
+	phys_addr_t pa;
 	if (!va)
 		return 0;
 	if (virt_addr_valid(va))
 		return virt_to_phys(va);
-	/*
+	pa = slow_virt_to_phys(va);
-	 * A fully aligned variable on the stack is guaranteed not to
-	 * cross a page bounary. Try to catch strings on the stack by
-	 * checking that 'size' is a power of two.
-	 */
-	bad_size = size > PAGE_SIZE || !is_power_of_2(size);
-	WARN_ON(!IS_ALIGNED((unsigned long)va, size) || bad_size);
+	/* check if the object crosses a page boundary */
+	if (WARN_ON((pa ^ (pa + size - 1)) & PAGE_MASK))
+		return 0;
-	return slow_virt_to_phys(va);
+	return pa;
 }
 #define virt_to_phys_or_null(addr)				\
 static efi_status_t efi_thunk_get_time(efi_time_t *tm, efi_time_cap_t *tc)
 {
-	efi_status_t status;
+	return EFI_UNSUPPORTED;
-	u32 phys_tm, phys_tc;
-	unsigned long flags;
-	spin_lock(&rtc_lock);
-	spin_lock_irqsave(&efi_runtime_lock, flags);
-	phys_tm = virt_to_phys_or_null(tm);
-	phys_tc = virt_to_phys_or_null(tc);
-	status = efi_thunk(get_time, phys_tm, phys_tc);
-	spin_unlock_irqrestore(&efi_runtime_lock, flags);
-	spin_unlock(&rtc_lock);
-	return status;
 }
 static efi_status_t efi_thunk_set_time(efi_time_t *tm)
 {
-	efi_status_t status;
+	return EFI_UNSUPPORTED;
-	u32 phys_tm;
-	unsigned long flags;
-	spin_lock(&rtc_lock);
-	spin_lock_irqsave(&efi_runtime_lock, flags);
-	phys_tm = virt_to_phys_or_null(tm);
-	status = efi_thunk(set_time, phys_tm);
-	spin_unlock_irqrestore(&efi_runtime_lock, flags);
-	spin_unlock(&rtc_lock);
-	return status;
 }
 static efi_status_t
 efi_thunk_get_wakeup_time(efi_bool_t *enabled, efi_bool_t *pending,
 			  efi_time_t *tm)
 {
-	efi_status_t status;
+	return EFI_UNSUPPORTED;
-	u32 phys_enabled, phys_pending, phys_tm;
-	unsigned long flags;
-	spin_lock(&rtc_lock);
-	spin_lock_irqsave(&efi_runtime_lock, flags);
-	phys_enabled = virt_to_phys_or_null(enabled);
-	phys_pending = virt_to_phys_or_null(pending);
-	phys_tm = virt_to_phys_or_null(tm);
-	status = efi_thunk(get_wakeup_time, phys_enabled,
-			     phys_pending, phys_tm);
-	spin_unlock_irqrestore(&efi_runtime_lock, flags);
-	spin_unlock(&rtc_lock);
-	return status;
 }
 static efi_status_t
 efi_thunk_set_wakeup_time(efi_bool_t enabled, efi_time_t *tm)
 {
-	efi_status_t status;
+	return EFI_UNSUPPORTED;
-	u32 phys_tm;
-	unsigned long flags;
-	spin_lock(&rtc_lock);
-	spin_lock_irqsave(&efi_runtime_lock, flags);
-	phys_tm = virt_to_phys_or_null(tm);
-	status = efi_thunk(set_wakeup_time, enabled, phys_tm);
-	spin_unlock_irqrestore(&efi_runtime_lock, flags);
-	spin_unlock(&rtc_lock);
-	return status;
 }
 static unsigned long efi_name_size(efi_char16_t *name)
 efi_thunk_get_variable(efi_char16_t *name, efi_guid_t *vendor,
 		       u32 *attr, unsigned long *data_size, void *data)
 {
+	u8 buf[24] __aligned(8);
+	efi_guid_t *vnd = PTR_ALIGN((efi_guid_t *)buf, sizeof(*vnd));
 	efi_status_t status;
 	u32 phys_name, phys_vendor, phys_attr;
 	u32 phys_data_size, phys_data;
 	spin_lock_irqsave(&efi_runtime_lock, flags);
+	*vnd = *vendor;
 	phys_data_size = virt_to_phys_or_null(data_size);
-	phys_vendor = virt_to_phys_or_null(vendor);
+	phys_vendor = virt_to_phys_or_null(vnd);
 	phys_name = virt_to_phys_or_null_size(name, efi_name_size(name));
 	phys_attr = virt_to_phys_or_null(attr);
 	phys_data = virt_to_phys_or_null_size(data, *data_size);
-	status = efi_thunk(get_variable, phys_name, phys_vendor,
+	if (!phys_name || (data && !phys_data))
-			   phys_attr, phys_data_size, phys_data);
+		status = EFI_INVALID_PARAMETER;
+	else
+		status = efi_thunk(get_variable, phys_name, phys_vendor,
+				   phys_attr, phys_data_size, phys_data);
 	spin_unlock_irqrestore(&efi_runtime_lock, flags);
 efi_thunk_set_variable(efi_char16_t *name, efi_guid_t *vendor,
 		       u32 attr, unsigned long data_size, void *data)
 {
+	u8 buf[24] __aligned(8);
+	efi_guid_t *vnd = PTR_ALIGN((efi_guid_t *)buf, sizeof(*vnd));
 	u32 phys_name, phys_vendor, phys_data;
 	efi_status_t status;
 	unsigned long flags;
 	spin_lock_irqsave(&efi_runtime_lock, flags);
+	*vnd = *vendor;
 	phys_name = virt_to_phys_or_null_size(name, efi_name_size(name));
-	phys_vendor = virt_to_phys_or_null(vendor);
+	phys_vendor = virt_to_phys_or_null(vnd);
 	phys_data = virt_to_phys_or_null_size(data, data_size);
-	/* If data_size is > sizeof(u32) we've got problems */
+	if (!phys_name || !phys_data)
-	status = efi_thunk(set_variable, phys_name, phys_vendor,
+		status = EFI_INVALID_PARAMETER;
-			   attr, data_size, phys_data);
+	else
+		status = efi_thunk(set_variable, phys_name, phys_vendor,
+				   attr, data_size, phys_data);
 	spin_unlock_irqrestore(&efi_runtime_lock, flags);
 				   u32 attr, unsigned long data_size,
 				   void *data)
 {
+	u8 buf[24] __aligned(8);
+	efi_guid_t *vnd = PTR_ALIGN((efi_guid_t *)buf, sizeof(*vnd));
 	u32 phys_name, phys_vendor, phys_data;
 	efi_status_t status;
 	unsigned long flags;
 	if (!spin_trylock_irqsave(&efi_runtime_lock, flags))
 		return EFI_NOT_READY;
+	*vnd = *vendor;
 	phys_name = virt_to_phys_or_null_size(name, efi_name_size(name));
-	phys_vendor = virt_to_phys_or_null(vendor);
+	phys_vendor = virt_to_phys_or_null(vnd);
 	phys_data = virt_to_phys_or_null_size(data, data_size);
-	/* If data_size is > sizeof(u32) we've got problems */
+	if (!phys_name || !phys_data)
-	status = efi_thunk(set_variable, phys_name, phys_vendor,
+		status = EFI_INVALID_PARAMETER;
-			   attr, data_size, phys_data);
+	else
+		status = efi_thunk(set_variable, phys_name, phys_vendor,
+				   attr, data_size, phys_data);
 	spin_unlock_irqrestore(&efi_runtime_lock, flags);
 			    efi_char16_t *name,
 			    efi_guid_t *vendor)
 {
+	u8 buf[24] __aligned(8);
+	efi_guid_t *vnd = PTR_ALIGN((efi_guid_t *)buf, sizeof(*vnd));
 	efi_status_t status;
 	u32 phys_name_size, phys_name, phys_vendor;
 	unsigned long flags;
 	spin_lock_irqsave(&efi_runtime_lock, flags);
+	*vnd = *vendor;
 	phys_name_size = virt_to_phys_or_null(name_size);
-	phys_vendor = virt_to_phys_or_null(vendor);
+	phys_vendor = virt_to_phys_or_null(vnd);
 	phys_name = virt_to_phys_or_null_size(name, *name_size);
-	status = efi_thunk(get_next_variable, phys_name_size,
+	if (!phys_name)
-			   phys_name, phys_vendor);
+		status = EFI_INVALID_PARAMETER;
+	else
+		status = efi_thunk(get_next_variable, phys_name_size,
+				   phys_name, phys_vendor);
 	spin_unlock_irqrestore(&efi_runtime_lock, flags);
+	*vendor = *vnd;
 	return status;
 }
 static efi_status_t
 efi_thunk_get_next_high_mono_count(u32 *count)
 {
-	efi_status_t status;
+	return EFI_UNSUPPORTED;
-	u32 phys_count;
-	unsigned long flags;
-	spin_lock_irqsave(&efi_runtime_lock, flags);
-	phys_count = virt_to_phys_or_null(count);
-	status = efi_thunk(get_next_high_mono_count, phys_count);
-	spin_unlock_irqrestore(&efi_runtime_lock, flags);
-	return status;
 }
 static void

arch/x86/xen/enlighten_pv.c+25−0

@@ -72,6 +72,9 @@ · 71 unmodified lines
72	#include <asm/mwait.h>	72	#include <asm/mwait.h>
73	#include <asm/pci_x86.h>	73	#include <asm/pci_x86.h>
74	#include <asm/cpu.h>	74	#include <asm/cpu.h>
		75	#ifdef CONFIG_X86_IOPL_IOPERM
		76	#include <asm/io_bitmap.h>
		77	#endif
75		78
76	#ifdef CONFIG_ACPI	79	#ifdef CONFIG_ACPI
77	#include <linux/acpi.h>	80	#include <linux/acpi.h>
@@ -837,6 +840,25 @@ static void xen_load_sp0(unsigned long sp0) · 759 unmodified lines
837	this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);	840	this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
838	}	841	}
839		842
		843	#ifdef CONFIG_X86_IOPL_IOPERM
		844	static void xen_update_io_bitmap(void)
		845	{
		846	struct physdev_set_iobitmap iobitmap;
		847	struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
		848
		849	native_tss_update_io_bitmap();
		850
		851	iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) +
		852	tss->x86_tss.io_bitmap_base;
		853	if (tss->x86_tss.io_bitmap_base == IO_BITMAP_OFFSET_INVALID)
		854	iobitmap.nr_ports = 0;
		855	else
		856	iobitmap.nr_ports = IO_BITMAP_BITS;
		857
		858	HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap);
		859	}
		860	#endif
		861
840	static void xen_io_delay(void)	862	static void xen_io_delay(void)
841	{	863	{
842	}	864	}
@@ -1047,6 +1069,9 @@ static const struct pv_cpu_ops xen_cpu_ops __initconst = { · 204 unmodified lines
1047	.write_idt_entry = xen_write_idt_entry,	1069	.write_idt_entry = xen_write_idt_entry,
1048	.load_sp0 = xen_load_sp0,	1070	.load_sp0 = xen_load_sp0,
1049		1071
		1072	#ifdef CONFIG_X86_IOPL_IOPERM
		1073	.update_io_bitmap = xen_update_io_bitmap,
		1074	#endif
1050	.io_delay = xen_io_delay,	1075	.io_delay = xen_io_delay,
1051		1076
1052	/* Xen takes care of %gs when switching to usermode for us */	1077	/* Xen takes care of %gs when switching to usermode for us */

block/bfq-cgroup.c+5−4

 	 */
 	entity = &bfqg->entity;
 	for_each_entity(entity) {
-		bfqg = container_of(entity, struct bfq_group, entity);
+		struct bfq_group *curr_bfqg = container_of(entity,
-		if (bfqg != bfqd->root_group) {
+						struct bfq_group, entity);
-			parent = bfqg_parent(bfqg);
+		if (curr_bfqg != bfqd->root_group) {
+			parent = bfqg_parent(curr_bfqg);
 			if (!parent)
 				parent = bfqd->root_group;
-			bfq_group_set_parent(bfqg, parent);
+			bfq_group_set_parent(curr_bfqg, parent);
 		}
 	}

block/blk-core.c+0−6

 }
 EXPORT_SYMBOL(kblockd_schedule_work);
-int kblockd_schedule_work_on(int cpu, struct work_struct *work)
-{
-	return queue_work_on(cpu, kblockd_workqueue, work);
-}
-EXPORT_SYMBOL(kblockd_schedule_work_on);
 int kblockd_mod_delayed_work_on(int cpu, struct delayed_work *dwork,
 				unsigned long delay)
 {

block/blk-flush.c+1−1

@@ -412,7 +412,7 @@ void blk_insert_flush(struct request *rq) · 411 unmodified lines
412	*/	412	*/
413	if ((policy & REQ_FSEQ_DATA) &&	413	if ((policy & REQ_FSEQ_DATA) &&
414	!(policy & (REQ_FSEQ_PREFLUSH \| REQ_FSEQ_POSTFLUSH))) {	414	!(policy & (REQ_FSEQ_PREFLUSH \| REQ_FSEQ_POSTFLUSH))) {
415	blk_mq_request_bypass_insert(rq, false);	415	blk_mq_request_bypass_insert(rq, false, false);
416	return;	416	return;
417	}	417	}
418		418

block/blk-iocost.c+1−1

@@ -1318,7 +1318,7 @@ static bool iocg_is_idle(struct ioc_gq *iocg) · 1317 unmodified lines
1318	return false;	1318	return false;
1319		1319
1320	/* is something in flight? */	1320	/* is something in flight? */
1321	if (atomic64_read(&iocg->done_vtime) < atomic64_read(&iocg->vtime))	1321	if (atomic64_read(&iocg->done_vtime) != atomic64_read(&iocg->vtime))
1322	return false;	1322	return false;
1323		1323
1324	return true;	1324	return true;

block/blk-mq-sched.c+37−7

@@ -361,13 +361,19 @@ static bool blk_mq_sched_bypass_insert(struct blk_mq_hw_ctx *hctx, · 360 unmodified lines
361	bool has_sched,	361	bool has_sched,
362	struct request *rq)	362	struct request *rq)
363	{	363	{
364	/* dispatch flush rq directly */	364	/*
365	if (rq->rq_flags & RQF_FLUSH_SEQ) {	365	* dispatch flush and passthrough rq directly
366	spin_lock(&hctx->lock);	366	*
367	list_add(&rq->queuelist, &hctx->dispatch);	367	* passthrough request has to be added to hctx->dispatch directly.
368	spin_unlock(&hctx->lock);	368	* For some reason, device may be in one situation which can't
		369	* handle FS request, so STS_RESOURCE is always returned and the
		370	* FS request will be added to hctx->dispatch. However passthrough
		371	* request may be required at that time for fixing the problem. If
		372	* passthrough request is added to scheduler queue, there isn't any
		373	* chance to dispatch it given we prioritize requests in hctx->dispatch.
		374	*/
		375	if ((rq->rq_flags & RQF_FLUSH_SEQ) \|\| blk_rq_is_passthrough(rq))
369	return true;	376	return true;
370	}
371		377
372	if (has_sched)	378	if (has_sched)
373	rq->rq_flags \|= RQF_SORTED;	379	rq->rq_flags \|= RQF_SORTED;
@@ -391,8 +397,32 @@ void blk_mq_sched_insert_request(struct request *rq, bool at_head, · 17 unmodified lines
391		397
392	WARN_ON(e && (rq->tag != -1));	398	WARN_ON(e && (rq->tag != -1));
393		399
394	if (blk_mq_sched_bypass_insert(hctx, !!e, rq))	400	if (blk_mq_sched_bypass_insert(hctx, !!e, rq)) {
		401	/*
		402	* Firstly normal IO request is inserted to scheduler queue or
		403	* sw queue, meantime we add flush request to dispatch queue(
		404	* hctx->dispatch) directly and there is at most one in-flight
		405	* flush request for each hw queue, so it doesn't matter to add
		406	* flush request to tail or front of the dispatch queue.
		407	*
		408	* Secondly in case of NCQ, flush request belongs to non-NCQ
		409	* command, and queueing it will fail when there is any
		410	* in-flight normal IO request(NCQ command). When adding flush
		411	* rq to the front of hctx->dispatch, it is easier to introduce
		412	* extra time to flush rq's latency because of S_SCHED_RESTART
		413	* compared with adding to the tail of dispatch queue, then
		414	* chance of flush merge is increased, and less flush requests
		415	* will be issued to controller. It is observed that ~10% time
		416	* is saved in blktests block/004 on disk attached to AHCI/NCQ
		417	* drive when adding flush rq to the front of hctx->dispatch.
		418	*
		419	* Simply queue flush rq to the front of hctx->dispatch so that
		420	* intensive flush workloads can benefit in case of NCQ HW.
		421	*/
		422	at_head = (rq->rq_flags & RQF_FLUSH_SEQ) ? true : at_head;
		423	blk_mq_request_bypass_insert(rq, at_head, false);
395	goto run;	424	goto run;
		425	}
396		426
397	if (e && e->type->ops.insert_requests) {	427	if (e && e->type->ops.insert_requests) {
398	LIST_HEAD(list);	428	LIST_HEAD(list);

block/blk-mq-tag.c+2−2

@@ -183,8 +183,8 @@ found_tag: · 182 unmodified lines
183	return tag + tag_offset;	183	return tag + tag_offset;
184	}	184	}
185		185
186	void blk_mq_put_tag(struct blk_mq_hw_ctx hctx, struct blk_mq_tags tags,	186	void blk_mq_put_tag(struct blk_mq_tags tags, struct blk_mq_ctx ctx,
187	struct blk_mq_ctx *ctx, unsigned int tag)	187	unsigned int tag)
188	{	188	{
189	if (!blk_mq_tag_is_reserved(tags, tag)) {	189	if (!blk_mq_tag_is_reserved(tags, tag)) {
190	const int real_tag = tag - tags->nr_reserved_tags;	190	const int real_tag = tag - tags->nr_reserved_tags;

block/blk-mq-tag.h+2−2

@@ -26,8 +26,8 @@ extern struct blk_mq_tags *blk_mq_init_tags(unsigned int nr_tags, unsigned int r · 25 unmodified lines
26	extern void blk_mq_free_tags(struct blk_mq_tags *tags);	26	extern void blk_mq_free_tags(struct blk_mq_tags *tags);
27		27
28	extern unsigned int blk_mq_get_tag(struct blk_mq_alloc_data *data);	28	extern unsigned int blk_mq_get_tag(struct blk_mq_alloc_data *data);
29	extern void blk_mq_put_tag(struct blk_mq_hw_ctx hctx, struct blk_mq_tags tags,	29	extern void blk_mq_put_tag(struct blk_mq_tags tags, struct blk_mq_ctx ctx,
30	struct blk_mq_ctx *ctx, unsigned int tag);	30	unsigned int tag);
31	extern int blk_mq_tag_update_depth(struct blk_mq_hw_ctx *hctx,	31	extern int blk_mq_tag_update_depth(struct blk_mq_hw_ctx *hctx,
32	struct blk_mq_tags **tags,	32	struct blk_mq_tags **tags,
33	unsigned int depth, bool can_grow);	33	unsigned int depth, bool can_grow);

block/blk-mq.c+15−13

 	blk_pm_mark_last_busy(rq);
 	rq->mq_hctx = NULL;
 	if (rq->tag != -1)
-		blk_mq_put_tag(hctx, hctx->tags, ctx, rq->tag);
+		blk_mq_put_tag(hctx->tags, ctx, rq->tag);
 	if (sched_tag != -1)
-		blk_mq_put_tag(hctx, hctx->sched_tags, ctx, sched_tag);
+		blk_mq_put_tag(hctx->sched_tags, ctx, sched_tag);
 	blk_mq_sched_restart(hctx);
 	blk_queue_exit(q);
 }
 		 * merge.
 		 */
 		if (rq->rq_flags & RQF_DONTPREP)
-			blk_mq_request_bypass_insert(rq, false);
+			blk_mq_request_bypass_insert(rq, false, false);
 		else
 			blk_mq_sched_insert_request(rq, true, false, false);
 	}
 			q->mq_ops->commit_rqs(hctx);
 		spin_lock(&hctx->lock);
-		list_splice_init(list, &hctx->dispatch);
+		list_splice_tail_init(list, &hctx->dispatch);
 		spin_unlock(&hctx->lock);
 		/*
  * Should only be used carefully, when the caller knows we want to
  * bypass a potential IO scheduler on the target device.
  */
-void blk_mq_request_bypass_insert(struct request *rq, bool run_queue)
+void blk_mq_request_bypass_insert(struct request *rq, bool at_head,
+				  bool run_queue)
 {
 	struct blk_mq_hw_ctx *hctx = rq->mq_hctx;
 	spin_lock(&hctx->lock);
-	list_add_tail(&rq->queuelist, &hctx->dispatch);
+	if (at_head)
+		list_add(&rq->queuelist, &hctx->dispatch);
+	else
+		list_add_tail(&rq->queuelist, &hctx->dispatch);
 	spin_unlock(&hctx->lock);
 	if (run_queue)
 	if (bypass_insert)
 		return BLK_STS_RESOURCE;
-	blk_mq_request_bypass_insert(rq, run_queue);
+	blk_mq_request_bypass_insert(rq, false, run_queue);
 	return BLK_STS_OK;
 }
 	ret = __blk_mq_try_issue_directly(hctx, rq, cookie, false, true);
 	if (ret == BLK_STS_RESOURCE || ret == BLK_STS_DEV_RESOURCE)
-		blk_mq_request_bypass_insert(rq, true);
+		blk_mq_request_bypass_insert(rq, false, true);
 	else if (ret != BLK_STS_OK)
 		blk_mq_end_request(rq, ret);
 		if (ret != BLK_STS_OK) {
 			if (ret == BLK_STS_RESOURCE ||
 					ret == BLK_STS_DEV_RESOURCE) {
-				blk_mq_request_bypass_insert(rq,
+				blk_mq_request_bypass_insert(rq, false,
 							list_empty(list));
 				break;
 			}
 }
 static unsigned long blk_mq_poll_nsecs(struct request_queue *q,
-				       struct blk_mq_hw_ctx *hctx,
 				       struct request *rq)
 {
 	unsigned long ret = 0;
 }
 static bool blk_mq_poll_hybrid_sleep(struct request_queue *q,
-				     struct blk_mq_hw_ctx *hctx,
 				     struct request *rq)
 {
 	struct hrtimer_sleeper hs;
 	if (q->poll_nsec > 0)
 		nsecs = q->poll_nsec;
 	else
-		nsecs = blk_mq_poll_nsecs(q, hctx, rq);
+		nsecs = blk_mq_poll_nsecs(q, rq);
 	if (!nsecs)
 		return false;
 			return false;
 	}
-	return blk_mq_poll_hybrid_sleep(q, hctx, rq);
+	return blk_mq_poll_hybrid_sleep(q, rq);
 }
 /**

block/blk-mq.h+3−2

  */
 void __blk_mq_insert_request(struct blk_mq_hw_ctx *hctx, struct request *rq,
 				bool at_head);
-void blk_mq_request_bypass_insert(struct request *rq, bool run_queue);
+void blk_mq_request_bypass_insert(struct request *rq, bool at_head,
+				  bool run_queue);
 void blk_mq_insert_requests(struct blk_mq_hw_ctx *hctx, struct blk_mq_ctx *ctx,
 				struct list_head *list);
 static inline void __blk_mq_put_driver_tag(struct blk_mq_hw_ctx *hctx,
 					   struct request *rq)
 {
-	blk_mq_put_tag(hctx, hctx->tags, rq->mq_ctx, rq->tag);
+	blk_mq_put_tag(hctx->tags, rq->mq_ctx, rq->tag);
 	rq->tag = -1;
 	if (rq->rq_flags & RQF_MQ_INFLIGHT) {

block/genhd.c+36−0

@@ -301,6 +301,42 @@ struct hd_struct disk_map_sector_rcu(struct gendisk disk, sector_t sector) · 300 unmodified lines
301	}	301	}
302	EXPORT_SYMBOL_GPL(disk_map_sector_rcu);	302	EXPORT_SYMBOL_GPL(disk_map_sector_rcu);
303		303
		304	/**
		305	* disk_has_partitions
		306	* @disk: gendisk of interest
		307	*
		308	* Walk through the partition table and check if valid partition exists.
		309	*
		310	* CONTEXT:
		311	* Don't care.
		312	*
		313	* RETURNS:
		314	* True if the gendisk has at least one valid non-zero size partition.
		315	* Otherwise false.
		316	*/
		317	bool disk_has_partitions(struct gendisk *disk)
		318	{
		319	struct disk_part_tbl *ptbl;
		320	int i;
		321	bool ret = false;
		322
		323	rcu_read_lock();
		324	ptbl = rcu_dereference(disk->part_tbl);
		325
		326	/* Iterate partitions skipping the whole device at index 0 */
		327	for (i = 1; i < ptbl->len; i++) {
		328	if (rcu_dereference(ptbl->part[i])) {
		329	ret = true;
		330	break;
		331	}
		332	}
		333
		334	rcu_read_unlock();
		335
		336	return ret;
		337	}
		338	EXPORT_SYMBOL_GPL(disk_has_partitions);
		339
304	/*	340	/*
305	* Can be deleted altogether. Later.	341	* Can be deleted altogether. Later.
306	*	342	*

drivers/acpi/acpi_watchdog.c+12−3

 }
 #endif
+static bool acpi_no_watchdog;
 static const struct acpi_table_wdat *acpi_watchdog_get_wdat(void)
 {
 	const struct acpi_table_wdat *wdat = NULL;
 	acpi_status status;
-	if (acpi_disabled)
+	if (acpi_disabled || acpi_no_watchdog)
 		return NULL;
 	status = acpi_get_table(ACPI_SIG_WDAT, 0,
 }
 EXPORT_SYMBOL_GPL(acpi_has_watchdog);
+/* ACPI watchdog can be disabled on boot command line */
+static int __init disable_acpi_watchdog(char *str)
+{
+	acpi_no_watchdog = true;
+	return 1;
+}
+__setup("acpi_no_watchdog", disable_acpi_watchdog);
 void __init acpi_watchdog_init(void)
 {
 	const struct acpi_wdat_entry *entries;
 		gas = &entries[i].register_region;
 		res.start = gas->address;
+		res.end = res.start + ACPI_ACCESS_BYTE_WIDTH(gas->access_width) - 1;
 		if (gas->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
 			res.flags = IORESOURCE_MEM;
-			res.end = res.start + ALIGN(gas->access_width, 4) - 1;
 		} else if (gas->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
 			res.flags = IORESOURCE_IO;
-			res.end = res.start + gas->access_width - 1;
 		} else {
 			pr_warn("Unsupported address space: %u\n",
 				gas->space_id);

drivers/android/binder.c+9−0

 		binder_dev = container_of(filp->private_data,
 					  struct binder_device, miscdev);
 	}
+	refcount_inc(&binder_dev->ref);
 	proc->context = &binder_dev->context;
 	binder_alloc_init(&proc->alloc);
 static void binder_deferred_release(struct binder_proc *proc)
 {
 	struct binder_context *context = proc->context;
+	struct binder_device *device;
 	struct rb_node *n;
 	int threads, nodes, incoming_refs, outgoing_refs, active_transactions;
 		context->binder_context_mgr_node = NULL;
 	}
 	mutex_unlock(&context->context_mgr_node_lock);
+	device = container_of(proc->context, struct binder_device, context);
+	if (refcount_dec_and_test(&device->ref)) {
+		kfree(context->name);
+		kfree(device);
+	}
+	proc->context = NULL;
 	binder_inner_proc_lock(proc);
 	/*
 	 * Make sure proc stays alive after we
 	binder_device->miscdev.minor = MISC_DYNAMIC_MINOR;
 	binder_device->miscdev.name = name;
+	refcount_set(&binder_device->ref, 1);
 	binder_device->context.binder_context_mgr_uid = INVALID_UID;
 	binder_device->context.name = name;
 	mutex_init(&binder_device->context.context_mgr_node_lock);

drivers/android/binder_internal.h+2−0

 #include <linux/list.h>
 #include <linux/miscdevice.h>
 #include <linux/mutex.h>
+#include <linux/refcount.h>
 #include <linux/stddef.h>
 #include <linux/types.h>
 #include <linux/uidgid.h>
 	struct miscdevice miscdev;
 	struct binder_context context;
 	struct inode *binderfs_inode;
+	refcount_t ref;
 };
 /**

drivers/android/binderfs.c+6−2

 	if (!name)
 		goto err;
+	refcount_set(&device->ref, 1);
 	device->binderfs_inode = inode;
 	device->context.binder_context_mgr_uid = INVALID_UID;
 	device->context.name = name;
 	ida_free(&binderfs_minors, device->miscdev.minor);
 	mutex_unlock(&binderfs_minors_mutex);
-	kfree(device->context.name);
+	if (refcount_dec_and_test(&device->ref)) {
-	kfree(device);
+		kfree(device->context.name);
+		kfree(device);
+	}
 }
 /**
 	inode->i_uid = info->root_uid;
 	inode->i_gid = info->root_gid;
+	refcount_set(&device->ref, 1);
 	device->binderfs_inode = inode;
 	device->miscdev.minor = minor;

drivers/atm/nicstar.c+1−1

@@ -91,7 +91,7 @@ · 90 unmodified lines
91	#ifdef GENERAL_DEBUG	91	#ifdef GENERAL_DEBUG
92	#define PRINTK(args...) printk(args)	92	#define PRINTK(args...) printk(args)
93	#else	93	#else
94	#define PRINTK(args...)	94	#define PRINTK(args...) do {} while (0)
95	#endif /* GENERAL_DEBUG */	95	#endif /* GENERAL_DEBUG */
96		96
97	#ifdef EXTRA_DEBUG	97	#ifdef EXTRA_DEBUG

drivers/auxdisplay/Kconfig+8−8

@@ -111,7 +111,7 @@ config CFAG12864B · 110 unmodified lines
111	If unsure, say N.	111	If unsure, say N.
112		112
113	config CFAG12864B_RATE	113	config CFAG12864B_RATE
114	int "Refresh rate (hertz)"	114	int "Refresh rate (hertz)"
115	depends on CFAG12864B	115	depends on CFAG12864B
116	default "20"	116	default "20"
117	---help---	117	---help---
@@ -329,7 +329,7 @@ config PANEL_LCD_PROTO · 211 unmodified lines
329		329
330	config PANEL_LCD_PIN_E	330	config PANEL_LCD_PIN_E
331	depends on PANEL_PROFILE="0" && PANEL_LCD="1" && PANEL_LCD_PROTO="0"	331	depends on PANEL_PROFILE="0" && PANEL_LCD="1" && PANEL_LCD_PROTO="0"
332	int "Parallel port pin number & polarity connected to the LCD E signal (-17...17) "	332	int "Parallel port pin number & polarity connected to the LCD E signal (-17...17) "
333	range -17 17	333	range -17 17
334	default 14	334	default 14
335	---help---	335	---help---
@@ -344,7 +344,7 @@ config PANEL_LCD_PIN_E · 8 unmodified lines
344		344
345	config PANEL_LCD_PIN_RS	345	config PANEL_LCD_PIN_RS
346	depends on PANEL_PROFILE="0" && PANEL_LCD="1" && PANEL_LCD_PROTO="0"	346	depends on PANEL_PROFILE="0" && PANEL_LCD="1" && PANEL_LCD_PROTO="0"
347	int "Parallel port pin number & polarity connected to the LCD RS signal (-17...17) "	347	int "Parallel port pin number & polarity connected to the LCD RS signal (-17...17) "
348	range -17 17	348	range -17 17
349	default 17	349	default 17
350	---help---	350	---help---
@@ -359,7 +359,7 @@ config PANEL_LCD_PIN_RS · 8 unmodified lines
359		359
360	config PANEL_LCD_PIN_RW	360	config PANEL_LCD_PIN_RW
361	depends on PANEL_PROFILE="0" && PANEL_LCD="1" && PANEL_LCD_PROTO="0"	361	depends on PANEL_PROFILE="0" && PANEL_LCD="1" && PANEL_LCD_PROTO="0"
362	int "Parallel port pin number & polarity connected to the LCD RW signal (-17...17) "	362	int "Parallel port pin number & polarity connected to the LCD RW signal (-17...17) "
363	range -17 17	363	range -17 17
364	default 16	364	default 16
365	---help---	365	---help---
@@ -374,7 +374,7 @@ config PANEL_LCD_PIN_RW · 8 unmodified lines
374		374
375	config PANEL_LCD_PIN_SCL	375	config PANEL_LCD_PIN_SCL
376	depends on PANEL_PROFILE="0" && PANEL_LCD="1" && PANEL_LCD_PROTO!="0"	376	depends on PANEL_PROFILE="0" && PANEL_LCD="1" && PANEL_LCD_PROTO!="0"
377	int "Parallel port pin number & polarity connected to the LCD SCL signal (-17...17) "	377	int "Parallel port pin number & polarity connected to the LCD SCL signal (-17...17) "
378	range -17 17	378	range -17 17
379	default 1	379	default 1
380	---help---	380	---help---
@@ -389,7 +389,7 @@ config PANEL_LCD_PIN_SCL · 8 unmodified lines
389		389
390	config PANEL_LCD_PIN_SDA	390	config PANEL_LCD_PIN_SDA
391	depends on PANEL_PROFILE="0" && PANEL_LCD="1" && PANEL_LCD_PROTO!="0"	391	depends on PANEL_PROFILE="0" && PANEL_LCD="1" && PANEL_LCD_PROTO!="0"
392	int "Parallel port pin number & polarity connected to the LCD SDA signal (-17...17) "	392	int "Parallel port pin number & polarity connected to the LCD SDA signal (-17...17) "
393	range -17 17	393	range -17 17
394	default 2	394	default 2
395	---help---	395	---help---
@@ -404,12 +404,12 @@ config PANEL_LCD_PIN_SDA · 8 unmodified lines
404		404
405	config PANEL_LCD_PIN_BL	405	config PANEL_LCD_PIN_BL
406	depends on PANEL_PROFILE="0" && PANEL_LCD="1"	406	depends on PANEL_PROFILE="0" && PANEL_LCD="1"
407	int "Parallel port pin number & polarity connected to the LCD backlight signal (-17...17) "	407	int "Parallel port pin number & polarity connected to the LCD backlight signal (-17...17) "
408	range -17 17	408	range -17 17
409	default 0	409	default 0
410	---help---	410	---help---
411	This describes the number of the parallel port pin to which the LCD 'BL' signal	411	This describes the number of the parallel port pin to which the LCD 'BL' signal
412	has been connected. It can be :	412	has been connected. It can be :
413		413
414	0 : no connection (eg: connected to ground)	414	0 : no connection (eg: connected to ground)
415	1..17 : directly connected to any of these pins on the DB25 plug	415	1..17 : directly connected to any of these pins on the DB25 plug

drivers/auxdisplay/charlcd.c+1−1

@@ -88,7 +88,7 @@ struct charlcd_priv { · 87 unmodified lines
88	int len;	88	int len;
89	} esc_seq;	89	} esc_seq;
90		90
91	unsigned long long drvdata[0];	91	unsigned long long drvdata[];
92	};	92	};
93		93
94	#define charlcd_to_priv(p) container_of(p, struct charlcd_priv, lcd)	94	#define charlcd_to_priv(p) container_of(p, struct charlcd_priv, lcd)

drivers/auxdisplay/img-ascii-lcd.c+1−3

 	const struct of_device_id *match;
 	const struct img_ascii_lcd_config *cfg;
 	struct img_ascii_lcd_ctx *ctx;
-	struct resource *res;
 	int err;
 	match = of_match_device(img_ascii_lcd_matches, &pdev->dev);
 					 &ctx->offset))
 			return -EINVAL;
 	} else {
-		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		ctx->base = devm_platform_ioremap_resource(pdev, 0);
-		ctx->base = devm_ioremap_resource(&pdev->dev, res);
 		if (IS_ERR(ctx->base))
 			return PTR_ERR(ctx->base);
 	}

drivers/base/core.c+20−7

 {
 	struct device_link *link;
+	if (!dev_has_sync_state(dev))
+		return;
 	if (dev->state_synced)
 		return;
 /**
  * device_links_flush_sync_list - Call sync_state() on a list of devices
  * @list: List of devices to call sync_state() on
+ * @dont_lock_dev: Device for which lock is already held by the caller
  *
  * Calls sync_state() on all the devices that have been queued for it. This
- * function is used in conjunction with __device_links_queue_sync_state().
+ * function is used in conjunction with __device_links_queue_sync_state(). The
+ * @dont_lock_dev parameter is useful when this function is called from a
+ * context where a device lock is already held.
  */
-static void device_links_flush_sync_list(struct list_head *list)
+static void device_links_flush_sync_list(struct list_head *list,
+					 struct device *dont_lock_dev)
 {
 	struct device *dev, *tmp;
 	list_for_each_entry_safe(dev, tmp, list, links.defer_sync) {
 		list_del_init(&dev->links.defer_sync);
-		device_lock(dev);
+		if (dev != dont_lock_dev)
+			device_lock(dev);
 		if (dev->bus->sync_state)
 			dev->bus->sync_state(dev);
 		else if (dev->driver && dev->driver->sync_state)
 			dev->driver->sync_state(dev);
-		device_unlock(dev);
+		if (dev != dont_lock_dev)
+			device_unlock(dev);
 		put_device(dev);
 	}
 out:
 	device_links_write_unlock();
-	device_links_flush_sync_list(&sync_list);
+	device_links_flush_sync_list(&sync_list, NULL);
 }
 static int sync_state_resume_initcall(void)
 static void __device_links_supplier_defer_sync(struct device *sup)
 {
-	if (list_empty(&sup->links.defer_sync))
+	if (list_empty(&sup->links.defer_sync) && dev_has_sync_state(sup))
 		list_add_tail(&sup->links.defer_sync, &deferred_sync);
 }
 			driver_deferred_probe_add(link->consumer);
 	}
+	if (defer_sync_state_count)
+		__device_links_supplier_defer_sync(dev);
+	else
+		__device_links_queue_sync_state(dev, &sync_list);
 	list_for_each_entry(link, &dev->links.suppliers, c_node) {
 		if (!(link->flags & DL_FLAG_MANAGED))
 			continue;
 	device_links_write_unlock();
-	device_links_flush_sync_list(&sync_list);
+	device_links_flush_sync_list(&sync_list, dev);
 }
 static void device_link_drop_managed(struct device_link *link)

drivers/base/platform.c+6−19

 {
 	if (!pdev->dev.coherent_dma_mask)
 		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-	if (!pdev->dma_mask)
+	if (!pdev->dev.dma_mask) {
-		pdev->dma_mask = DMA_BIT_MASK(32);
+		pdev->platform_dma_mask = DMA_BIT_MASK(32);
-	if (!pdev->dev.dma_mask)
+		pdev->dev.dma_mask = &pdev->platform_dma_mask;
-		pdev->dev.dma_mask = &pdev->dma_mask;
+	}
 };
 /**
 	pdev->dev.of_node_reused = pdevinfo->of_node_reused;
 	if (pdevinfo->dma_mask) {
-		/*
+		pdev->platform_dma_mask = pdevinfo->dma_mask;
-		 * This memory isn't freed when the device is put,
+		pdev->dev.dma_mask = &pdev->platform_dma_mask;
-		 * I don't have a nice idea for that though.  Conceptually
-		 * dma_mask in struct device should not be a pointer.
-		 * See http://thread.gmane.org/gmane.linux.kernel.pci/9081
-		 */
-		pdev->dev.dma_mask =
-			kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
-		if (!pdev->dev.dma_mask)
-			goto err;
-		kmemleak_ignore(pdev->dev.dma_mask);
-		*pdev->dev.dma_mask = pdevinfo->dma_mask;
 		pdev->dev.coherent_dma_mask = pdevinfo->dma_mask;
 	}
 	if (ret) {
 err:
 		ACPI_COMPANION_SET(&pdev->dev, NULL);
-		kfree(pdev->dev.dma_mask);
 		platform_device_put(pdev);
 		return ERR_PTR(ret);
 	}

drivers/base/swnode.c+7−7

 {
 	struct swnode *swnode = kobj_to_swnode(kobj);
+	if (swnode->parent) {
+		ida_simple_remove(&swnode->parent->child_ids, swnode->id);
+		list_del(&swnode->entry);
+	} else {
+		ida_simple_remove(&swnode_root_ids, swnode->id);
+	}
 	if (swnode->allocated) {
 		property_entries_free(swnode->node->properties);
 		kfree(swnode->node);
 	if (!swnode)
 		return;
-	if (swnode->parent) {
-		ida_simple_remove(&swnode->parent->child_ids, swnode->id);
-		list_del(&swnode->entry);
-	} else {
-		ida_simple_remove(&swnode_root_ids, swnode->id);
-	}
 	kobject_put(&swnode->kobj);
 }
 EXPORT_SYMBOL_GPL(fwnode_remove_software_node);

drivers/block/floppy.c+5−2

 /* selects the fdc and drive, and enables the fdc's input/dma. */
 static void set_fdc(int drive)
 {
+	unsigned int new_fdc = fdc;
 	if (drive >= 0 && drive < N_DRIVE) {
-		fdc = FDC(drive);
+		new_fdc = FDC(drive);
 		current_drive = drive;
 	}
-	if (fdc != 1 && fdc != 0) {
+	if (new_fdc >= N_FDC) {
 		pr_info("bad fdc value\n");
 		return;
 	}
+	fdc = new_fdc;
 	set_dor(fdc, ~0, 8);
 #if N_FDC > 1
 	set_dor(1 - fdc, ~8, 0);

drivers/block/null_blk.h+0−3

 #include <linux/fault-inject.h>
 struct nullb_cmd {
-	struct list_head list;
-	struct llist_node ll_list;
-	struct __call_single_data csd;
 	struct request *rq;
 	struct bio *bio;
 	unsigned int tag;

drivers/block/null_blk_main.c+0−2

@@ -1518,8 +1518,6 @@ static int setup_commands(struct nullb_queue *nq) · 1517 unmodified lines
1518		1518
1519	for (i = 0; i < nq->queue_depth; i++) {	1519	for (i = 0; i < nq->queue_depth; i++) {
1520	cmd = &nq->cmds[i];	1520	cmd = &nq->cmds[i];
1521	INIT_LIST_HEAD(&cmd->list);
1522	cmd->ll_list.next = NULL;
1523	cmd->tag = -1U;	1521	cmd->tag = -1U;
1524	}	1522	}
1525		1523

drivers/block/paride/pcd.c+1−1

@@ -276,7 +276,7 @@ static const struct block_device_operations pcd_bdops = { · 275 unmodified lines
276	.release = pcd_block_release,	276	.release = pcd_block_release,
277	.ioctl = pcd_block_ioctl,	277	.ioctl = pcd_block_ioctl,
278	#ifdef CONFIG_COMPAT	278	#ifdef CONFIG_COMPAT
279	.ioctl = blkdev_compat_ptr_ioctl,	279	.compat_ioctl = blkdev_compat_ptr_ioctl,
280	#endif	280	#endif
281	.check_events = pcd_block_check_events,	281	.check_events = pcd_block_check_events,
282	};	282	};

drivers/block/virtio_blk.c+12−5

 	err = virtblk_add_req(vblk->vqs[qid].vq, vbr, vbr->sg, num);
 	if (err) {
 		virtqueue_kick(vblk->vqs[qid].vq);
-		blk_mq_stop_hw_queue(hctx);
+		/* Don't stop the queue if -ENOMEM: we may have failed to
+		 * bounce the buffer due to global resource outage.
+		 */
+		if (err == -ENOSPC)
+			blk_mq_stop_hw_queue(hctx);
 		spin_unlock_irqrestore(&vblk->vqs[qid].lock, flags);
-		/* Out of mem doesn't actually happen, since we fall back
+		switch (err) {
-		 * to direct descriptors */
+		case -ENOSPC:
-		if (err == -ENOMEM || err == -ENOSPC)
 			return BLK_STS_DEV_RESOURCE;
-		return BLK_STS_IOERR;
+		case -ENOMEM:
+			return BLK_STS_RESOURCE;
+		default:
+			return BLK_STS_IOERR;
+		}
 	}
 	if (bd->last && virtqueue_kick_prepare(vblk->vqs[qid].vq))

drivers/block/xen-blkfront.c+42−38

 	struct blk_mq_tag_set tag_set;
 	struct blkfront_ring_info *rinfo;
 	unsigned int nr_rings;
+	unsigned int rinfo_size;
 	/* Save uncomplete reqs and bios for migration. */
 	struct list_head requests;
 	struct bio_list bio_list;
 static void blkfront_gather_backend_features(struct blkfront_info *info);
 static int negotiate_mq(struct blkfront_info *info);
+#define for_each_rinfo(info, ptr, idx)				\
+	for ((ptr) = (info)->rinfo, (idx) = 0;			\
+	     (idx) < (info)->nr_rings;				\
+	     (idx)++, (ptr) = (void *)(ptr) + (info)->rinfo_size)
+static inline struct blkfront_ring_info *
+get_rinfo(const struct blkfront_info *info, unsigned int i)
+{
+	BUG_ON(i >= info->nr_rings);
+	return (void *)info->rinfo + i * info->rinfo_size;
+}
 static int get_id_from_freelist(struct blkfront_ring_info *rinfo)
 {
 	unsigned long free = rinfo->shadow_free;
 	struct blkfront_info *info = hctx->queue->queuedata;
 	struct blkfront_ring_info *rinfo = NULL;
-	BUG_ON(info->nr_rings <= qid);
+	rinfo = get_rinfo(info, qid);
-	rinfo = &info->rinfo[qid];
 	blk_mq_start_request(qd->rq);
 	spin_lock_irqsave(&rinfo->ring_lock, flags);
 	if (RING_FULL(&rinfo->ring))
 static void xlvbd_release_gendisk(struct blkfront_info *info)
 {
 	unsigned int minor, nr_minors, i;
+	struct blkfront_ring_info *rinfo;
 	if (info->rq == NULL)
 		return;
 	/* No more blkif_request(). */
 	blk_mq_stop_hw_queues(info->rq);
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
-		struct blkfront_ring_info *rinfo = &info->rinfo[i];
 		/* No more gnttab callback work. */
 		gnttab_cancel_free_callback(&rinfo->callback);
 static void blkif_free(struct blkfront_info *info, int suspend)
 {
 	unsigned int i;
+	struct blkfront_ring_info *rinfo;
 	/* Prevent new requests being issued until we fix things up. */
 	info->connected = suspend ?
 	if (info->rq)
 		blk_mq_stop_hw_queues(info->rq);
-	for (i = 0; i < info->nr_rings; i++)
+	for_each_rinfo(info, rinfo, i)
-		blkif_free_ring(&info->rinfo[i]);
+		blkif_free_ring(rinfo);
 	kvfree(info->rinfo);
 	info->rinfo = NULL;
 	int err;
 	unsigned int i, max_page_order;
 	unsigned int ring_page_order;
+	struct blkfront_ring_info *rinfo;
 	if (!info)
 		return -ENODEV;
 	if (err)
 		goto destroy_blkring;
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
-		struct blkfront_ring_info *rinfo = &info->rinfo[i];
 		/* Create shared ring, alloc event channel. */
 		err = setup_blkring(dev, rinfo);
 		if (err)
 	/* We already got the number of queues/rings in _probe */
 	if (info->nr_rings == 1) {
-		err = write_per_ring_nodes(xbt, &info->rinfo[0], dev->nodename);
+		err = write_per_ring_nodes(xbt, info->rinfo, dev->nodename);
 		if (err)
 			goto destroy_blkring;
 	} else {
 			goto abort_transaction;
 		}
-		for (i = 0; i < info->nr_rings; i++) {
+		for_each_rinfo(info, rinfo, i) {
 			memset(path, 0, pathsize);
 			snprintf(path, pathsize, "%s/queue-%u", dev->nodename, i);
-			err = write_per_ring_nodes(xbt, &info->rinfo[i], path);
+			err = write_per_ring_nodes(xbt, rinfo, path);
 			if (err) {
 				kfree(path);
 				goto destroy_blkring;
 		goto destroy_blkring;
 	}
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
 		unsigned int j;
-		struct blkfront_ring_info *rinfo = &info->rinfo[i];
 		for (j = 0; j < BLK_RING_SIZE(info); j++)
 			rinfo->shadow[j].req.u.rw.id = j + 1;
 {
 	unsigned int backend_max_queues;
 	unsigned int i;
+	struct blkfront_ring_info *rinfo;
 	BUG_ON(info->nr_rings);
 	if (!info->nr_rings)
 		info->nr_rings = 1;
-	info->rinfo = kvcalloc(info->nr_rings,
+	info->rinfo_size = struct_size(info->rinfo, shadow,
-			       struct_size(info->rinfo, shadow,
+				       BLK_RING_SIZE(info));
-					   BLK_RING_SIZE(info)),
+	info->rinfo = kvcalloc(info->nr_rings, info->rinfo_size, GFP_KERNEL);
-			       GFP_KERNEL);
 	if (!info->rinfo) {
 		xenbus_dev_fatal(info->xbdev, -ENOMEM, "allocating ring_info structure");
 		info->nr_rings = 0;
 		return -ENOMEM;
 	}
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
-		struct blkfront_ring_info *rinfo;
-		rinfo = &info->rinfo[i];
 		INIT_LIST_HEAD(&rinfo->indirect_pages);
 		INIT_LIST_HEAD(&rinfo->grants);
 		rinfo->dev_info = info;
 	int rc;
 	struct bio *bio;
 	unsigned int segs;
+	struct blkfront_ring_info *rinfo;
 	blkfront_gather_backend_features(info);
 	/* Reset limits changed by blk_mq_update_nr_hw_queues(). */
 	segs = info->max_indirect_segments ? : BLKIF_MAX_SEGMENTS_PER_REQUEST;
 	blk_queue_max_segments(info->rq, segs / GRANTS_PER_PSEG);
-	for (r_index = 0; r_index < info->nr_rings; r_index++) {
+	for_each_rinfo(info, rinfo, r_index) {
-		struct blkfront_ring_info *rinfo = &info->rinfo[r_index];
 		rc = blkfront_setup_indirect(rinfo);
 		if (rc)
 			return rc;
 	/* Now safe for us to use the shared ring */
 	info->connected = BLKIF_STATE_CONNECTED;
-	for (r_index = 0; r_index < info->nr_rings; r_index++) {
+	for_each_rinfo(info, rinfo, r_index) {
-		struct blkfront_ring_info *rinfo;
-		rinfo = &info->rinfo[r_index];
 		/* Kick any other new requests queued since we resumed */
 		kick_pending_request_queues(rinfo);
 	}
 	struct blkfront_info *info = dev_get_drvdata(&dev->dev);
 	int err = 0;
 	unsigned int i, j;
+	struct blkfront_ring_info *rinfo;
 	dev_dbg(&dev->dev, "blkfront_resume: %s\n", dev->nodename);
 	bio_list_init(&info->bio_list);
 	INIT_LIST_HEAD(&info->requests);
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
-		struct blkfront_ring_info *rinfo = &info->rinfo[i];
 		struct bio_list merge_bio;
 		struct blk_shadow *shadow = rinfo->shadow;
 	unsigned int binfo;
 	char *envp[] = { "RESIZE=1", NULL };
 	int err, i;
+	struct blkfront_ring_info *rinfo;
 	switch (info->connected) {
 	case BLKIF_STATE_CONNECTED:
 						    "physical-sector-size",
 						    sector_size);
 	blkfront_gather_backend_features(info);
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
-		err = blkfront_setup_indirect(&info->rinfo[i]);
+		err = blkfront_setup_indirect(rinfo);
 		if (err) {
 			xenbus_dev_fatal(info->xbdev, err, "setup_indirect at %s",
 					 info->xbdev->otherend);
 	/* Kick pending requests. */
 	info->connected = BLKIF_STATE_CONNECTED;
-	for (i = 0; i < info->nr_rings; i++)
+	for_each_rinfo(info, rinfo, i)
-		kick_pending_request_queues(&info->rinfo[i]);
+		kick_pending_request_queues(rinfo);
 	device_add_disk(&info->xbdev->dev, info->gd, NULL);
 {
 	unsigned int i;
 	unsigned long flags;
+	struct blkfront_ring_info *rinfo;
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
-		struct blkfront_ring_info *rinfo = &info->rinfo[i];
 		struct grant *gnt_list_entry, *tmp;
 		spin_lock_irqsave(&rinfo->ring_lock, flags);

drivers/bus/ti-sysc.c+2−2

@@ -1400,7 +1400,7 @@ static void sysc_init_revision_quirks(struct sysc *ddata) · 1399 unmodified lines
1400	}	1400	}
1401		1401
1402	/* 1-wire needs module's internal clocks enabled for reset */	1402	/* 1-wire needs module's internal clocks enabled for reset */
1403	static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata)	1403	static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1404	{	1404	{
1405	int offset = 0x0c; /* HDQ_CTRL_STATUS */	1405	int offset = 0x0c; /* HDQ_CTRL_STATUS */
1406	u16 val;	1406	u16 val;
@@ -1488,7 +1488,7 @@ static void sysc_init_module_quirks(struct sysc *ddata) · 81 unmodified lines
1488	return;	1488	return;
1489		1489
1490	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {	1490	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1491	ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w;	1491	ddata->clk_disable_quirk = sysc_pre_reset_quirk_hdq1w;
1492		1492
1493	return;	1493	return;
1494	}	1494	}

drivers/cdrom/gdrom.c+1−1

@@ -519,7 +519,7 @@ static const struct block_device_operations gdrom_bdops = { · 518 unmodified lines
519	.check_events = gdrom_bdops_check_events,	519	.check_events = gdrom_bdops_check_events,
520	.ioctl = gdrom_bdops_ioctl,	520	.ioctl = gdrom_bdops_ioctl,
521	#ifdef CONFIG_COMPAT	521	#ifdef CONFIG_COMPAT
522	.ioctl = blkdev_compat_ptr_ioctl,	522	.compat_ioctl = blkdev_compat_ptr_ioctl,
523	#endif	523	#endif
524	};	524	};
525		525

drivers/char/ipmi/ipmi_si_platform.c+2−2

@@ -194,7 +194,7 @@ static int platform_ipmi_probe(struct platform_device *pdev) · 193 unmodified lines
194	else	194	else
195	io.slave_addr = slave_addr;	195	io.slave_addr = slave_addr;
196		196
197	io.irq = platform_get_irq(pdev, 0);	197	io.irq = platform_get_irq_optional(pdev, 0);
198	if (io.irq > 0)	198	if (io.irq > 0)
199	io.irq_setup = ipmi_std_irq_setup;	199	io.irq_setup = ipmi_std_irq_setup;
200	else	200	else
@@ -378,7 +378,7 @@ static int acpi_ipmi_probe(struct platform_device *pdev) · 177 unmodified lines
378	io.irq = tmp;	378	io.irq = tmp;
379	io.irq_setup = acpi_gpe_irq_setup;	379	io.irq_setup = acpi_gpe_irq_setup;
380	} else {	380	} else {
381	int irq = platform_get_irq(pdev, 0);	381	int irq = platform_get_irq_optional(pdev, 0);
382		382
383	if (irq > 0) {	383	if (irq > 0) {
384	io.irq = irq;	384	io.irq = irq;

drivers/clk/clk.c+2−2

@@ -4713,7 +4713,7 @@ EXPORT_SYMBOL(of_clk_get_by_name); · 4712 unmodified lines
4713	*	4713	*
4714	* Returns: The number of clocks that are possible parents of this node	4714	* Returns: The number of clocks that are possible parents of this node
4715	*/	4715	*/
4716	unsigned int of_clk_get_parent_count(struct device_node *np)	4716	unsigned int of_clk_get_parent_count(const struct device_node *np)
4717	{	4717	{
4718	int count;	4718	int count;
4719		4719
@@ -4725,7 +4725,7 @@ unsigned int of_clk_get_parent_count(struct device_node *np) · 5 unmodified lines
4725	}	4725	}
4726	EXPORT_SYMBOL_GPL(of_clk_get_parent_count);	4726	EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
4727		4727
4728	const char of_clk_get_parent_name(struct device_node np, int index)	4728	const char of_clk_get_parent_name(const struct device_node np, int index)
4729	{	4729	{
4730	struct of_phandle_args clkspec;	4730	struct of_phandle_args clkspec;
4731	struct property *prop;	4731	struct property *prop;

drivers/clk/qcom/dispcc-sc7180.c+0−19

@@ -592,24 +592,6 @@ static struct clk_branch disp_cc_mdss_rot_clk = { · 591 unmodified lines
592	},	592	},
593	};	593	};
594		594
595	static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
596	.halt_reg = 0x400c,
597	.halt_check = BRANCH_HALT,
598	.clkr = {
599	.enable_reg = 0x400c,
600	.enable_mask = BIT(0),
601	.hw.init = &(struct clk_init_data){
602	.name = "disp_cc_mdss_rscc_ahb_clk",
603	.parent_data = &(const struct clk_parent_data){
604	.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
605	},
606	.num_parents = 1,
607	.flags = CLK_IS_CRITICAL \| CLK_SET_RATE_PARENT,
608	.ops = &clk_branch2_ops,
609	},
610	},
611	};
612
613	static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {	595	static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
614	.halt_reg = 0x4008,	596	.halt_reg = 0x4008,
615	.halt_check = BRANCH_HALT,	597	.halt_check = BRANCH_HALT,
@@ -687,7 +669,6 @@ static struct clk_regmap *disp_cc_sc7180_clocks[] = { · 71 unmodified lines
687	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,	669	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
688	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,	670	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
689	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,	671	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
690	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
691	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,	672	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
692	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,	673	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
693	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,	674	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,

drivers/clk/qcom/videocc-sc7180.c+1−1

@@ -97,7 +97,7 @@ static struct clk_branch video_cc_vcodec0_axi_clk = { · 96 unmodified lines
97		97
98	static struct clk_branch video_cc_vcodec0_core_clk = {	98	static struct clk_branch video_cc_vcodec0_core_clk = {
99	.halt_reg = 0x890,	99	.halt_reg = 0x890,
100	.halt_check = BRANCH_HALT,	100	.halt_check = BRANCH_HALT_VOTED,
101	.clkr = {	101	.clkr = {
102	.enable_reg = 0x890,	102	.enable_reg = 0x890,
103	.enable_mask = BIT(0),	103	.enable_mask = BIT(0),

drivers/cpufreq/cpufreq.c+10−2

 			pol = policy->last_policy;
 		} else if (def_gov) {
 			pol = cpufreq_parse_policy(def_gov->name);
-		} else {
+			/*
-			return -ENODATA;
+			 * In case the default governor is neiter "performance"
+			 * nor "powersave", fall back to the initial policy
+			 * value set by the driver.
+			 */
+			if (pol == CPUFREQ_POLICY_UNKNOWN)
+				pol = policy->policy;
 		}
+		if (pol != CPUFREQ_POLICY_PERFORMANCE &&
+		    pol != CPUFREQ_POLICY_POWERSAVE)
+			return -ENODATA;
 	}
 	return cpufreq_set_policy(policy, gov, pol);

drivers/devfreq/devfreq.c+1−3

 {
 	struct devfreq *devfreq;
 	struct devfreq_governor *governor;
-	static atomic_t devfreq_no = ATOMIC_INIT(-1);
 	int err = 0;
 	if (!dev || !profile || !governor_name) {
 	devfreq->suspend_freq = dev_pm_opp_get_suspend_opp_freq(dev);
 	atomic_set(&devfreq->suspend_count, 0);
-	dev_set_name(&devfreq->dev, "devfreq%d",
+	dev_set_name(&devfreq->dev, "%s", dev_name(dev));
-				atomic_inc_return(&devfreq_no));
 	err = device_register(&devfreq->dev);
 	if (err) {
 		mutex_unlock(&devfreq->lock);

drivers/dma-buf/dma-buf.c+1−0

@@ -108,6 +108,7 @@ static int dma_buf_release(struct inode inode, struct file file) · 107 unmodified lines
108	dma_resv_fini(dmabuf->resv);	108	dma_resv_fini(dmabuf->resv);
109		109
110	module_put(dmabuf->owner);	110	module_put(dmabuf->owner);
		111	kfree(dmabuf->name);
111	kfree(dmabuf);	112	kfree(dmabuf);
112	return 0;	113	return 0;
113	}	114	}

drivers/dma/coh901318.c+0−4

 		return;
 	}
-	spin_lock(&cohc->lock);
 	/*
 	 * When we reach this point, at least one queue item
 	 * should have been moved over from cohc->queue to
 	if (coh901318_queue_start(cohc) == NULL)
 		cohc->busy = 0;
-	spin_unlock(&cohc->lock);
 	/*
 	 * This tasklet will remove items from cohc->active
 	 * and thus terminates them.

drivers/dma/idxd/cdev.c+2−2

 	minor = ida_simple_get(&cdev_ctx->minor_ida, 0, MINORMASK, GFP_KERNEL);
 	if (minor < 0) {
 		rc = minor;
+		kfree(dev);
 		goto ida_err;
 	}
 	rc = device_register(dev);
 	if (rc < 0) {
 		dev_err(&idxd->pdev->dev, "device register failed\n");
-		put_device(dev);
 		goto dev_reg_err;
 	}
 	idxd_cdev->minor = minor;
  dev_reg_err:
 	ida_simple_remove(&cdev_ctx->minor_ida, MINOR(dev->devt));
+	put_device(dev);
  ida_err:
-	kfree(dev);
 	idxd_cdev->dev = NULL;
 	return rc;
 }

drivers/dma/idxd/sysfs.c+23−4

 		rc = idxd_device_config(idxd);
 		if (rc < 0) {
 			spin_unlock_irqrestore(&idxd->dev_lock, flags);
+			module_put(THIS_MODULE);
 			dev_warn(dev, "Device config failed: %d\n", rc);
 			return rc;
 		}
 		rc = idxd_device_enable(idxd);
 		if (rc < 0) {
 			spin_unlock_irqrestore(&idxd->dev_lock, flags);
+			module_put(THIS_MODULE);
 			dev_warn(dev, "Device enable failed: %d\n", rc);
 			return rc;
 		}
 		rc = idxd_register_dma_device(idxd);
 		if (rc < 0) {
 			spin_unlock_irqrestore(&idxd->dev_lock, flags);
+			module_put(THIS_MODULE);
 			dev_dbg(dev, "Failed to register dmaengine device\n");
 			return rc;
 		}
 	if (val > idxd->max_tokens)
 		return -EINVAL;
-	if (val > idxd->nr_tokens)
+	if (val > idxd->nr_tokens + group->tokens_reserved)
 		return -EINVAL;
 	group->tokens_reserved = val;
 	return sprintf(buf, "%u\n", wq->size);
 }
+static int total_claimed_wq_size(struct idxd_device *idxd)
+{
+	int i;
+	int wq_size = 0;
+	for (i = 0; i < idxd->max_wqs; i++) {
+		struct idxd_wq *wq = &idxd->wqs[i];
+		wq_size += wq->size;
+	}
+	return wq_size;
+}
 static ssize_t wq_size_store(struct device *dev,
 			     struct device_attribute *attr, const char *buf,
 			     size_t count)
 	if (wq->state != IDXD_WQ_DISABLED)
 		return -EPERM;
-	if (size > idxd->max_wq_size)
+	if (size + total_claimed_wq_size(idxd) - wq->size > idxd->max_wq_size)
 		return -EINVAL;
 	wq->size = size;
 		return -EPERM;
 	old_type = wq->type;
-	if (sysfs_streq(buf, idxd_wq_type_names[IDXD_WQT_KERNEL]))
+	if (sysfs_streq(buf, idxd_wq_type_names[IDXD_WQT_NONE]))
+		wq->type = IDXD_WQT_NONE;
+	else if (sysfs_streq(buf, idxd_wq_type_names[IDXD_WQT_KERNEL]))
 		wq->type = IDXD_WQT_KERNEL;
 	else if (sysfs_streq(buf, idxd_wq_type_names[IDXD_WQT_USER]))
 		wq->type = IDXD_WQT_USER;
 	else
-		wq->type = IDXD_WQT_NONE;
+		return -EINVAL;
 	/* If we are changing queue type, clear the name */
 	if (wq->type != old_type)

drivers/dma/imx-sdma.c+3−2

 	sdma_channel_synchronize(chan);
-	if (sdmac->event_id0)
+	if (sdmac->event_id0 >= 0)
 		sdma_event_disable(sdmac, sdmac->event_id0);
 	if (sdmac->event_id1)
 		sdma_event_disable(sdmac, sdmac->event_id1);
 	sdmac->event_id0 = 0;
 	sdmac->event_id1 = 0;
+	sdmac->context_loaded = false;
 	sdma_set_channel_priority(sdmac, 0);
 	memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
 	/* Set ENBLn earlier to make sure dma request triggered after that */
-	if (sdmac->event_id0) {
+	if (sdmac->event_id0 >= 0) {
 		if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
 			return -EINVAL;
 		sdma_event_enable(sdmac, sdmac->event_id0);

drivers/dma/tegra20-apb-dma.c+1−5

 	/* Do not allocate if desc are waiting for ack */
 	list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
-		if (async_tx_test_ack(&dma_desc->txd)) {
+		if (async_tx_test_ack(&dma_desc->txd) && !dma_desc->cb_count) {
 			list_del(&dma_desc->node);
 			spin_unlock_irqrestore(&tdc->lock, flags);
 			dma_desc->txd.flags = 0;
 	bool was_busy;
 	spin_lock_irqsave(&tdc->lock, flags);
-	if (list_empty(&tdc->pending_sg_req)) {
-		spin_unlock_irqrestore(&tdc->lock, flags);
-		return 0;
-	}
 	if (!tdc->busy)
 		goto skip_dma_stop;

drivers/dma/ti/k3-udma.c+361−132

@@ -5,6 +5,7 @@ · 4 unmodified lines
5	*/	5	*/
6		6
7	#include <linux/kernel.h>	7	#include <linux/kernel.h>
		8	#include <linux/delay.h>
8	#include <linux/dmaengine.h>	9	#include <linux/dmaengine.h>
9	#include <linux/dma-mapping.h>	10	#include <linux/dma-mapping.h>
10	#include <linux/dmapool.h>	11	#include <linux/dmapool.h>
@@ -96,6 +97,24 @@ struct udma_match_data { · 85 unmodified lines
96	u32 level_start_idx[];	97	u32 level_start_idx[];
97	};	98	};
98		99
		100	struct udma_hwdesc {
		101	size_t cppi5_desc_size;
		102	void *cppi5_desc_vaddr;
		103	dma_addr_t cppi5_desc_paddr;
		104
		105	/* TR descriptor internal pointers */
		106	void *tr_req_base;
		107	struct cppi5_tr_resp_t *tr_resp_base;
		108	};
		109
		110	struct udma_rx_flush {
		111	struct udma_hwdesc hwdescs[2];
		112
		113	size_t buffer_size;
		114	void *buffer_vaddr;
		115	dma_addr_t buffer_paddr;
		116	};
		117
99	struct udma_dev {	118	struct udma_dev {
100	struct dma_device ddev;	119	struct dma_device ddev;
101	struct device *dev;	120	struct device *dev;
@@ -112,6 +131,8 @@ struct udma_dev { · 10 unmodified lines
112	struct list_head desc_to_purge;	131	struct list_head desc_to_purge;
113	spinlock_t lock;	132	spinlock_t lock;
114		133
		134	struct udma_rx_flush rx_flush;
		135
115	int tchan_cnt;	136	int tchan_cnt;
116	int echan_cnt;	137	int echan_cnt;
117	int rchan_cnt;	138	int rchan_cnt;
@@ -130,16 +151,6 @@ struct udma_dev { · 12 unmodified lines
130	u32 psil_base;	151	u32 psil_base;
131	};	152	};
132		153
133	struct udma_hwdesc {
134	size_t cppi5_desc_size;
135	void *cppi5_desc_vaddr;
136	dma_addr_t cppi5_desc_paddr;
137
138	/* TR descriptor internal pointers */
139	void *tr_req_base;
140	struct cppi5_tr_resp_t *tr_resp_base;
141	};
142
143	struct udma_desc {	154	struct udma_desc {
144	struct virt_dma_desc vd;	155	struct virt_dma_desc vd;
145		156
@@ -169,7 +180,7 @@ enum udma_chan_state { · 23 unmodified lines
169		180
170	struct udma_tx_drain {	181	struct udma_tx_drain {
171	struct delayed_work work;	182	struct delayed_work work;
172	unsigned long jiffie;	183	ktime_t tstamp;
173	u32 residue;	184	u32 residue;
174	};	185	};
175		186
@@ -502,7 +513,7 @@ static bool udma_is_chan_paused(struct udma_chan *uc) · 326 unmodified lines
502	{	513	{
503	u32 val, pause_mask;	514	u32 val, pause_mask;
504		515
505	switch (uc->desc->dir) {	516	switch (uc->config.dir) {
506	case DMA_DEV_TO_MEM:	517	case DMA_DEV_TO_MEM:
507	val = udma_rchanrt_read(uc->rchan,	518	val = udma_rchanrt_read(uc->rchan,
508	UDMA_RCHAN_RT_PEER_RT_EN_REG);	519	UDMA_RCHAN_RT_PEER_RT_EN_REG);
@@ -551,12 +562,17 @@ static void udma_sync_for_device(struct udma_chan *uc, int idx) · 42 unmodified lines
551	}	562	}
552	}	563	}
553		564
		565	static inline dma_addr_t udma_get_rx_flush_hwdesc_paddr(struct udma_chan *uc)
		566	{
		567	return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr;
		568	}
		569
554	static int udma_push_to_ring(struct udma_chan *uc, int idx)	570	static int udma_push_to_ring(struct udma_chan *uc, int idx)
555	{	571	{
556	struct udma_desc *d = uc->desc;	572	struct udma_desc *d = uc->desc;
557
558	struct k3_ring *ring = NULL;	573	struct k3_ring *ring = NULL;
559	int ret = -EINVAL;	574	dma_addr_t paddr;
		575	int ret;
560		576
561	switch (uc->config.dir) {	577	switch (uc->config.dir) {
562	case DMA_DEV_TO_MEM:	578	case DMA_DEV_TO_MEM:
@@ -567,21 +583,37 @@ static int udma_push_to_ring(struct udma_chan *uc, int idx) · 4 unmodified lines
567	ring = uc->tchan->t_ring;	583	ring = uc->tchan->t_ring;
568	break;	584	break;
569	default:	585	default:
570	break;	586	return -EINVAL;
571	}	587	}
572		588
573	if (ring) {	589	/* RX flush packet: idx == -1 is only passed in case of DEV_TO_MEM */
574	dma_addr_t desc_addr = udma_curr_cppi5_desc_paddr(d, idx);	590	if (idx == -1) {
		591	paddr = udma_get_rx_flush_hwdesc_paddr(uc);
		592	} else {
		593	paddr = udma_curr_cppi5_desc_paddr(d, idx);
575		594
576	wmb(); /* Ensure that writes are not moved over this point */	595	wmb(); /* Ensure that writes are not moved over this point */
577	udma_sync_for_device(uc, idx);	596	udma_sync_for_device(uc, idx);
578	ret = k3_ringacc_ring_push(ring, &desc_addr);
579	uc->in_ring_cnt++;
580	}	597	}
581		598
		599	ret = k3_ringacc_ring_push(ring, &paddr);
		600	if (!ret)
		601	uc->in_ring_cnt++;
		602
582	return ret;	603	return ret;
583	}	604	}
584		605
		606	static bool udma_desc_is_rx_flush(struct udma_chan *uc, dma_addr_t addr)
		607	{
		608	if (uc->config.dir != DMA_DEV_TO_MEM)
		609	return false;
		610
		611	if (addr == udma_get_rx_flush_hwdesc_paddr(uc))
		612	return true;
		613
		614	return false;
		615	}
		616
585	static int udma_pop_from_ring(struct udma_chan uc, dma_addr_t addr)	617	static int udma_pop_from_ring(struct udma_chan uc, dma_addr_t addr)
586	{	618	{
587	struct k3_ring *ring = NULL;	619	struct k3_ring *ring = NULL;
@@ -610,6 +642,10 @@ static int udma_pop_from_ring(struct udma_chan uc, dma_addr_t addr) · 22 unmodified lines
610	if (cppi5_desc_is_tdcm(*addr))	642	if (cppi5_desc_is_tdcm(*addr))
611	return ret;	643	return ret;
612		644
		645	/* Check for flush descriptor */
		646	if (udma_desc_is_rx_flush(uc, *addr))
		647	return -ENOENT;
		648
613	d = udma_udma_desc_from_paddr(uc, *addr);	649	d = udma_udma_desc_from_paddr(uc, *addr);
614		650
615	if (d)	651	if (d)
@@ -890,6 +926,9 @@ static int udma_stop(struct udma_chan *uc) · 274 unmodified lines
890		926
891	switch (uc->config.dir) {	927	switch (uc->config.dir) {
892	case DMA_DEV_TO_MEM:	928	case DMA_DEV_TO_MEM:
		929	if (!uc->cyclic && !uc->desc)
		930	udma_push_to_ring(uc, -1);
		931
893	udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,	932	udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
894	UDMA_PEER_RT_EN_ENABLE \|	933	UDMA_PEER_RT_EN_ENABLE \|
895	UDMA_PEER_RT_EN_TEARDOWN);	934	UDMA_PEER_RT_EN_TEARDOWN);
@@ -946,9 +985,10 @@ static bool udma_is_desc_really_done(struct udma_chan uc, struct udma_desc d) · 50 unmodified lines
946	peer_bcnt = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);	985	peer_bcnt = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
947	bcnt = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_BCNT_REG);	986	bcnt = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_BCNT_REG);
948		987
		988	/* Transfer is incomplete, store current residue and time stamp */
949	if (peer_bcnt < bcnt) {	989	if (peer_bcnt < bcnt) {
950	uc->tx_drain.residue = bcnt - peer_bcnt;	990	uc->tx_drain.residue = bcnt - peer_bcnt;
951	uc->tx_drain.jiffie = jiffies;	991	uc->tx_drain.tstamp = ktime_get();
952	return false;	992	return false;
953	}	993	}
954		994
@@ -961,35 +1001,59 @@ static void udma_check_tx_completion(struct work_struct *work) · 6 unmodified lines
961	tx_drain.work.work);	1001	tx_drain.work.work);
962	bool desc_done = true;	1002	bool desc_done = true;
963	u32 residue_diff;	1003	u32 residue_diff;
964	unsigned long jiffie_diff, delay;	1004	ktime_t time_diff;
		1005	unsigned long delay;
		1006
		1007	while (1) {
		1008	if (uc->desc) {
		1009	/* Get previous residue and time stamp */
		1010	residue_diff = uc->tx_drain.residue;
		1011	time_diff = uc->tx_drain.tstamp;
		1012	/*
		1013	* Get current residue and time stamp or see if
		1014	* transfer is complete
		1015	*/
		1016	desc_done = udma_is_desc_really_done(uc, uc->desc);
		1017	}
965		1018
966	if (uc->desc) {	1019	if (!desc_done) {
967	residue_diff = uc->tx_drain.residue;	1020	/*
968	jiffie_diff = uc->tx_drain.jiffie;	1021	* Find the time delta and residue delta w.r.t
969	desc_done = udma_is_desc_really_done(uc, uc->desc);	1022	* previous poll
970	}	1023	*/
971		1024	time_diff = ktime_sub(uc->tx_drain.tstamp,
972	if (!desc_done) {	1025	time_diff) + 1;
973	jiffie_diff = uc->tx_drain.jiffie - jiffie_diff;	1026	residue_diff -= uc->tx_drain.residue;
974	residue_diff -= uc->tx_drain.residue;	1027	if (residue_diff) {
975	if (residue_diff) {	1028	/*
976	/* Try to guess when we should check next time */	1029	* Try to guess when we should check
977	residue_diff /= jiffie_diff;	1030	* next time by calculating rate at
978	delay = uc->tx_drain.residue / residue_diff / 3;	1031	* which data is being drained at the
979	if (jiffies_to_msecs(delay) < 5)	1032	* peer device
980	delay = 0;	1033	*/
981	} else {	1034	delay = (time_diff / residue_diff) *
982	/* No progress, check again in 1 second */	1035	uc->tx_drain.residue;
983	delay = HZ;	1036	} else {
		1037	/* No progress, check again in 1 second */
		1038	schedule_delayed_work(&uc->tx_drain.work, HZ);
		1039	break;
		1040	}
		1041
		1042	usleep_range(ktime_to_us(delay),
		1043	ktime_to_us(delay) + 10);
		1044	continue;
984	}	1045	}
985		1046
986	schedule_delayed_work(&uc->tx_drain.work, delay);	1047	if (uc->desc) {
987	} else if (uc->desc) {	1048	struct udma_desc *d = uc->desc;
988	struct udma_desc *d = uc->desc;
989		1049
990	uc->bcnt += d->residue;	1050	uc->bcnt += d->residue;
991	udma_start(uc);	1051	udma_start(uc);
992	vchan_cookie_complete(&d->vd);	1052	vchan_cookie_complete(&d->vd);
		1053	break;
		1054	}
		1055
		1056	break;
993	}	1057	}
994	}	1058	}
995		1059
@@ -1033,29 +1097,27 @@ static irqreturn_t udma_ring_irq_handler(int irq, void *data) · 37 unmodified lines
1033	goto out;	1097	goto out;
1034	}	1098	}
1035		1099
1036	if (uc->cyclic) {	1100	if (d == uc->desc) {
1037	/* push the descriptor back to the ring */	1101	/* active descriptor */
1038	if (d == uc->desc) {	1102	if (uc->cyclic) {
1039	udma_cyclic_packet_elapsed(uc);	1103	udma_cyclic_packet_elapsed(uc);
1040	vchan_cyclic_callback(&d->vd);	1104	vchan_cyclic_callback(&d->vd);
1041	}	1105	} else {
1042	} else {	1106	if (udma_is_desc_really_done(uc, d)) {
1043	bool desc_done = false;
1044
1045	if (d == uc->desc) {
1046	desc_done = udma_is_desc_really_done(uc, d);
1047
1048	if (desc_done) {
1049	uc->bcnt += d->residue;	1107	uc->bcnt += d->residue;
1050	udma_start(uc);	1108	udma_start(uc);
		1109	vchan_cookie_complete(&d->vd);
1051	} else {	1110	} else {
1052	schedule_delayed_work(&uc->tx_drain.work,	1111	schedule_delayed_work(&uc->tx_drain.work,
1053	0);	1112	0);
1054	}	1113	}
1055	}	1114	}
1056		1115	} else {
1057	if (desc_done)	1116	/*
1058	vchan_cookie_complete(&d->vd);	1117	* terminated descriptor, mark the descriptor as
		1118	* completed to update the channel's cookie marker
		1119	*/
		1120	dma_cookie_complete(&d->vd.tx);
1059	}	1121	}
1060	}	1122	}
1061	out:	1123	out:
@@ -1965,36 +2027,81 @@ static struct udma_desc udma_alloc_tr_desc(struct udma_chan uc, · 903 unmodified lines
1965	return d;	2027	return d;
1966	}	2028	}
1967		2029
		2030	/**
		2031	* udma_get_tr_counters - calculate TR counters for a given length
		2032	* @len: Length of the trasnfer
		2033	* @align_to: Preferred alignment
		2034	* @tr0_cnt0: First TR icnt0
		2035	* @tr0_cnt1: First TR icnt1
		2036	* @tr1_cnt0: Second (if used) TR icnt0
		2037	*
		2038	* For len < SZ_64K only one TR is enough, tr1_cnt0 is not updated
		2039	* For len >= SZ_64K two TRs are used in a simple way:
		2040	* First TR: SZ_64K-alignment blocks (tr0_cnt0, tr0_cnt1)
		2041	* Second TR: the remaining length (tr1_cnt0)
		2042	*
		2043	* Returns the number of TRs the length needs (1 or 2)
		2044	* -EINVAL if the length can not be supported
		2045	*/
		2046	static int udma_get_tr_counters(size_t len, unsigned long align_to,
		2047	u16 tr0_cnt0, u16 tr0_cnt1, u16 *tr1_cnt0)
		2048	{
		2049	if (len < SZ_64K) {
		2050	*tr0_cnt0 = len;
		2051	*tr0_cnt1 = 1;
		2052
		2053	return 1;
		2054	}
		2055
		2056	if (align_to > 3)
		2057	align_to = 3;
		2058
		2059	realign:
		2060	*tr0_cnt0 = SZ_64K - BIT(align_to);
		2061	if (len / *tr0_cnt0 >= SZ_64K) {
		2062	if (align_to) {
		2063	align_to--;
		2064	goto realign;
		2065	}
		2066	return -EINVAL;
		2067	}
		2068
		2069	tr0_cnt1 = len / tr0_cnt0;
		2070	tr1_cnt0 = len % tr0_cnt0;
		2071
		2072	return 2;
		2073	}
		2074
1968	static struct udma_desc *	2075	static struct udma_desc *
1969	udma_prep_slave_sg_tr(struct udma_chan uc, struct scatterlist sgl,	2076	udma_prep_slave_sg_tr(struct udma_chan uc, struct scatterlist sgl,
1970	unsigned int sglen, enum dma_transfer_direction dir,	2077	unsigned int sglen, enum dma_transfer_direction dir,
1971	unsigned long tx_flags, void *context)	2078	unsigned long tx_flags, void *context)
1972	{	2079	{
1973	enum dma_slave_buswidth dev_width;
1974	struct scatterlist *sgent;	2080	struct scatterlist *sgent;
1975	struct udma_desc *d;	2081	struct udma_desc *d;
1976	size_t tr_size;
1977	struct cppi5_tr_type1_t *tr_req = NULL;	2082	struct cppi5_tr_type1_t *tr_req = NULL;
		2083	u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
1978	unsigned int i;	2084	unsigned int i;
1979	u32 burst;	2085	size_t tr_size;
		2086	int num_tr = 0;
		2087	int tr_idx = 0;
1980		2088
1981	if (dir == DMA_DEV_TO_MEM) {	2089	if (!is_slave_direction(dir)) {
1982	dev_width = uc->cfg.src_addr_width;	2090	dev_err(uc->ud->dev, "Only slave cyclic is supported\n");
1983	burst = uc->cfg.src_maxburst;
1984	} else if (dir == DMA_MEM_TO_DEV) {
1985	dev_width = uc->cfg.dst_addr_width;
1986	burst = uc->cfg.dst_maxburst;
1987	} else {
1988	dev_err(uc->ud->dev, "%s: bad direction?\n", __func__);
1989	return NULL;	2091	return NULL;
1990	}	2092	}
1991		2093
1992	if (!burst)	2094	/* estimate the number of TRs we will need */
1993	burst = 1;	2095	for_each_sg(sgl, sgent, sglen, i) {
		2096	if (sg_dma_len(sgent) < SZ_64K)
		2097	num_tr++;
		2098	else
		2099	num_tr += 2;
		2100	}
1994		2101
1995	/* Now allocate and setup the descriptor. */	2102	/* Now allocate and setup the descriptor. */
1996	tr_size = sizeof(struct cppi5_tr_type1_t);	2103	tr_size = sizeof(struct cppi5_tr_type1_t);
1997	d = udma_alloc_tr_desc(uc, tr_size, sglen, dir);	2104	d = udma_alloc_tr_desc(uc, tr_size, num_tr, dir);
1998	if (!d)	2105	if (!d)
1999	return NULL;	2106	return NULL;
2000		2107
@@ -2002,19 +2109,46 @@ udma_prep_slave_sg_tr(struct udma_chan uc, struct scatterlist sgl, · 1 unmodified line
2002		2109
2003	tr_req = d->hwdesc[0].tr_req_base;	2110	tr_req = d->hwdesc[0].tr_req_base;
2004	for_each_sg(sgl, sgent, sglen, i) {	2111	for_each_sg(sgl, sgent, sglen, i) {
2005	d->residue += sg_dma_len(sgent);	2112	dma_addr_t sg_addr = sg_dma_address(sgent);
		2113
		2114	num_tr = udma_get_tr_counters(sg_dma_len(sgent), __ffs(sg_addr),
		2115	&tr0_cnt0, &tr0_cnt1, &tr1_cnt0);
		2116	if (num_tr < 0) {
		2117	dev_err(uc->ud->dev, "size %u is not supported\n",
		2118	sg_dma_len(sgent));
		2119	udma_free_hwdesc(uc, d);
		2120	kfree(d);
		2121	return NULL;
		2122	}
2006		2123
2007	cppi5_tr_init(&tr_req[i].flags, CPPI5_TR_TYPE1, false, false,	2124	cppi5_tr_init(&tr_req[i].flags, CPPI5_TR_TYPE1, false, false,
2008	CPPI5_TR_EVENT_SIZE_COMPLETION, 0);	2125	CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
2009	cppi5_tr_csf_set(&tr_req[i].flags, CPPI5_TR_CSF_SUPR_EVT);	2126	cppi5_tr_csf_set(&tr_req[i].flags, CPPI5_TR_CSF_SUPR_EVT);
2010		2127
2011	tr_req[i].addr = sg_dma_address(sgent);	2128	tr_req[tr_idx].addr = sg_addr;
2012	tr_req[i].icnt0 = burst * dev_width;	2129	tr_req[tr_idx].icnt0 = tr0_cnt0;
2013	tr_req[i].dim1 = burst * dev_width;	2130	tr_req[tr_idx].icnt1 = tr0_cnt1;
2014	tr_req[i].icnt1 = sg_dma_len(sgent) / tr_req[i].icnt0;	2131	tr_req[tr_idx].dim1 = tr0_cnt0;
		2132	tr_idx++;
		2133
		2134	if (num_tr == 2) {
		2135	cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1,
		2136	false, false,
		2137	CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
		2138	cppi5_tr_csf_set(&tr_req[tr_idx].flags,
		2139	CPPI5_TR_CSF_SUPR_EVT);
		2140
		2141	tr_req[tr_idx].addr = sg_addr + tr0_cnt1 * tr0_cnt0;
		2142	tr_req[tr_idx].icnt0 = tr1_cnt0;
		2143	tr_req[tr_idx].icnt1 = 1;
		2144	tr_req[tr_idx].dim1 = tr1_cnt0;
		2145	tr_idx++;
		2146	}
		2147
		2148	d->residue += sg_dma_len(sgent);
2015	}	2149	}
2016		2150
2017	cppi5_tr_csf_set(&tr_req[i - 1].flags, CPPI5_TR_CSF_EOP);	2151	cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, CPPI5_TR_CSF_EOP);
2018		2152
2019	return d;	2153	return d;
2020	}	2154	}
@@ -2319,47 +2453,66 @@ udma_prep_dma_cyclic_tr(struct udma_chan *uc, dma_addr_t buf_addr, · 298 unmodified lines
2319	size_t buf_len, size_t period_len,	2453	size_t buf_len, size_t period_len,
2320	enum dma_transfer_direction dir, unsigned long flags)	2454	enum dma_transfer_direction dir, unsigned long flags)
2321	{	2455	{
2322	enum dma_slave_buswidth dev_width;
2323	struct udma_desc *d;	2456	struct udma_desc *d;
2324	size_t tr_size;	2457	size_t tr_size, period_addr;
2325	struct cppi5_tr_type1_t *tr_req;	2458	struct cppi5_tr_type1_t *tr_req;
2326	unsigned int i;
2327	unsigned int periods = buf_len / period_len;	2459	unsigned int periods = buf_len / period_len;
2328	u32 burst;	2460	u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
		2461	unsigned int i;
		2462	int num_tr;
2329		2463
2330	if (dir == DMA_DEV_TO_MEM) {	2464	if (!is_slave_direction(dir)) {
2331	dev_width = uc->cfg.src_addr_width;	2465	dev_err(uc->ud->dev, "Only slave cyclic is supported\n");
2332	burst = uc->cfg.src_maxburst;
2333	} else if (dir == DMA_MEM_TO_DEV) {
2334	dev_width = uc->cfg.dst_addr_width;
2335	burst = uc->cfg.dst_maxburst;
2336	} else {
2337	dev_err(uc->ud->dev, "%s: bad direction?\n", __func__);
2338	return NULL;	2466	return NULL;
2339	}	2467	}
2340		2468
2341	if (!burst)	2469	num_tr = udma_get_tr_counters(period_len, __ffs(buf_addr), &tr0_cnt0,
2342	burst = 1;	2470	&tr0_cnt1, &tr1_cnt0);
		2471	if (num_tr < 0) {
		2472	dev_err(uc->ud->dev, "size %zu is not supported\n",
		2473	period_len);
		2474	return NULL;
		2475	}
2343		2476
2344	/* Now allocate and setup the descriptor. */	2477	/* Now allocate and setup the descriptor. */
2345	tr_size = sizeof(struct cppi5_tr_type1_t);	2478	tr_size = sizeof(struct cppi5_tr_type1_t);
2346	d = udma_alloc_tr_desc(uc, tr_size, periods, dir);	2479	d = udma_alloc_tr_desc(uc, tr_size, periods * num_tr, dir);
2347	if (!d)	2480	if (!d)
2348	return NULL;	2481	return NULL;
2349		2482
2350	tr_req = d->hwdesc[0].tr_req_base;	2483	tr_req = d->hwdesc[0].tr_req_base;
		2484	period_addr = buf_addr;
2351	for (i = 0; i < periods; i++) {	2485	for (i = 0; i < periods; i++) {
2352	cppi5_tr_init(&tr_req[i].flags, CPPI5_TR_TYPE1, false, false,	2486	int tr_idx = i * num_tr;
2353	CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
2354		2487
2355	tr_req[i].addr = buf_addr + period_len * i;	2488	cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,
2356	tr_req[i].icnt0 = dev_width;	2489	false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
2357	tr_req[i].icnt1 = period_len / dev_width;	2490
2358	tr_req[i].dim1 = dev_width;	2491	tr_req[tr_idx].addr = period_addr;
		2492	tr_req[tr_idx].icnt0 = tr0_cnt0;
		2493	tr_req[tr_idx].icnt1 = tr0_cnt1;
		2494	tr_req[tr_idx].dim1 = tr0_cnt0;
		2495
		2496	if (num_tr == 2) {
		2497	cppi5_tr_csf_set(&tr_req[tr_idx].flags,
		2498	CPPI5_TR_CSF_SUPR_EVT);
		2499	tr_idx++;
		2500
		2501	cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1,
		2502	false, false,
		2503	CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
		2504
		2505	tr_req[tr_idx].addr = period_addr + tr0_cnt1 * tr0_cnt0;
		2506	tr_req[tr_idx].icnt0 = tr1_cnt0;
		2507	tr_req[tr_idx].icnt1 = 1;
		2508	tr_req[tr_idx].dim1 = tr1_cnt0;
		2509	}
2359		2510
2360	if (!(flags & DMA_PREP_INTERRUPT))	2511	if (!(flags & DMA_PREP_INTERRUPT))
2361	cppi5_tr_csf_set(&tr_req[i].flags,	2512	cppi5_tr_csf_set(&tr_req[tr_idx].flags,
2362	CPPI5_TR_CSF_SUPR_EVT);	2513	CPPI5_TR_CSF_SUPR_EVT);
		2514
		2515	period_addr += period_len;
2363	}	2516	}
2364		2517
2365	return d;	2518	return d;
@@ -2517,29 +2670,12 @@ udma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, · 151 unmodified lines
2517	return NULL;	2670	return NULL;
2518	}	2671	}
2519		2672
2520	if (len < SZ_64K) {	2673	num_tr = udma_get_tr_counters(len, __ffs(src \| dest), &tr0_cnt0,
2521	num_tr = 1;	2674	&tr0_cnt1, &tr1_cnt0);
2522	tr0_cnt0 = len;	2675	if (num_tr < 0) {
2523	tr0_cnt1 = 1;	2676	dev_err(uc->ud->dev, "size %zu is not supported\n",
2524	} else {	2677	len);
2525	unsigned long align_to = __ffs(src \| dest);	2678	return NULL;
2526
2527	if (align_to > 3)
2528	align_to = 3;
2529	/*
2530	* Keep simple: tr0: SZ_64K-alignment blocks,
2531	* tr1: the remaining
2532	*/
2533	num_tr = 2;
2534	tr0_cnt0 = (SZ_64K - BIT(align_to));
2535	if (len / tr0_cnt0 >= SZ_64K) {
2536	dev_err(uc->ud->dev, "size %zu is not supported\n",
2537	len);
2538	return NULL;
2539	}
2540
2541	tr0_cnt1 = len / tr0_cnt0;
2542	tr1_cnt0 = len % tr0_cnt0;
2543	}	2679	}
2544		2680
2545	d = udma_alloc_tr_desc(uc, tr_size, num_tr, DMA_MEM_TO_MEM);	2681	d = udma_alloc_tr_desc(uc, tr_size, num_tr, DMA_MEM_TO_MEM);
@@ -2631,6 +2767,9 @@ static enum dma_status udma_tx_status(struct dma_chan *chan, · 85 unmodified lines
2631		2767
2632	ret = dma_cookie_status(chan, cookie, txstate);	2768	ret = dma_cookie_status(chan, cookie, txstate);
2633		2769
		2770	if (!udma_is_chan_running(uc))
		2771	ret = DMA_COMPLETE;
		2772
2634	if (ret == DMA_IN_PROGRESS && udma_is_chan_paused(uc))	2773	if (ret == DMA_IN_PROGRESS && udma_is_chan_paused(uc))
2635	ret = DMA_PAUSED;	2774	ret = DMA_PAUSED;
2636		2775
@@ -2697,11 +2836,8 @@ static int udma_pause(struct dma_chan *chan) · 60 unmodified lines
2697	{	2836	{
2698	struct udma_chan *uc = to_udma_chan(chan);	2837	struct udma_chan *uc = to_udma_chan(chan);
2699		2838
2700	if (!uc->desc)
2701	return -EINVAL;
2702
2703	/* pause the channel */	2839	/* pause the channel */
2704	switch (uc->desc->dir) {	2840	switch (uc->config.dir) {
2705	case DMA_DEV_TO_MEM:	2841	case DMA_DEV_TO_MEM:
2706	udma_rchanrt_update_bits(uc->rchan,	2842	udma_rchanrt_update_bits(uc->rchan,
2707	UDMA_RCHAN_RT_PEER_RT_EN_REG,	2843	UDMA_RCHAN_RT_PEER_RT_EN_REG,
@@ -2730,11 +2866,8 @@ static int udma_resume(struct dma_chan *chan) · 22 unmodified lines
2730	{	2866	{
2731	struct udma_chan *uc = to_udma_chan(chan);	2867	struct udma_chan *uc = to_udma_chan(chan);
2732		2868
2733	if (!uc->desc)
2734	return -EINVAL;
2735
2736	/* resume the channel */	2869	/* resume the channel */
2737	switch (uc->desc->dir) {	2870	switch (uc->config.dir) {
2738	case DMA_DEV_TO_MEM:	2871	case DMA_DEV_TO_MEM:
2739	udma_rchanrt_update_bits(uc->rchan,	2872	udma_rchanrt_update_bits(uc->rchan,
2740	UDMA_RCHAN_RT_PEER_RT_EN_REG,	2873	UDMA_RCHAN_RT_PEER_RT_EN_REG,
@@ -3248,6 +3381,98 @@ static int udma_setup_resources(struct udma_dev *ud) · 507 unmodified lines
3248	return ch_count;	3381	return ch_count;
3249	}	3382	}
3250		3383
		3384	static int udma_setup_rx_flush(struct udma_dev *ud)
		3385	{
		3386	struct udma_rx_flush *rx_flush = &ud->rx_flush;
		3387	struct cppi5_desc_hdr_t *tr_desc;
		3388	struct cppi5_tr_type1_t *tr_req;
		3389	struct cppi5_host_desc_t *desc;
		3390	struct device *dev = ud->dev;
		3391	struct udma_hwdesc *hwdesc;
		3392	size_t tr_size;
		3393
		3394	/* Allocate 1K buffer for discarded data on RX channel teardown */
		3395	rx_flush->buffer_size = SZ_1K;
		3396	rx_flush->buffer_vaddr = devm_kzalloc(dev, rx_flush->buffer_size,
		3397	GFP_KERNEL);
		3398	if (!rx_flush->buffer_vaddr)
		3399	return -ENOMEM;
		3400
		3401	rx_flush->buffer_paddr = dma_map_single(dev, rx_flush->buffer_vaddr,
		3402	rx_flush->buffer_size,
		3403	DMA_TO_DEVICE);
		3404	if (dma_mapping_error(dev, rx_flush->buffer_paddr))
		3405	return -ENOMEM;
		3406
		3407	/* Set up descriptor to be used for TR mode */
		3408	hwdesc = &rx_flush->hwdescs[0];
		3409	tr_size = sizeof(struct cppi5_tr_type1_t);
		3410	hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, 1);
		3411	hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size,
		3412	ud->desc_align);
		3413
		3414	hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size,
		3415	GFP_KERNEL);
		3416	if (!hwdesc->cppi5_desc_vaddr)
		3417	return -ENOMEM;
		3418
		3419	hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr,
		3420	hwdesc->cppi5_desc_size,
		3421	DMA_TO_DEVICE);
		3422	if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr))
		3423	return -ENOMEM;
		3424
		3425	/* Start of the TR req records */
		3426	hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size;
		3427	/* Start address of the TR response array */
		3428	hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size;
		3429
		3430	tr_desc = hwdesc->cppi5_desc_vaddr;
		3431	cppi5_trdesc_init(tr_desc, 1, tr_size, 0, 0);
		3432	cppi5_desc_set_pktids(tr_desc, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT);
		3433	cppi5_desc_set_retpolicy(tr_desc, 0, 0);
		3434
		3435	tr_req = hwdesc->tr_req_base;
		3436	cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false,
		3437	CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
		3438	cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT);
		3439
		3440	tr_req->addr = rx_flush->buffer_paddr;
		3441	tr_req->icnt0 = rx_flush->buffer_size;
		3442	tr_req->icnt1 = 1;
		3443
		3444	/* Set up descriptor to be used for packet mode */
		3445	hwdesc = &rx_flush->hwdescs[1];
		3446	hwdesc->cppi5_desc_size = ALIGN(sizeof(struct cppi5_host_desc_t) +
		3447	CPPI5_INFO0_HDESC_EPIB_SIZE +
		3448	CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE,
		3449	ud->desc_align);
		3450
		3451	hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size,
		3452	GFP_KERNEL);
		3453	if (!hwdesc->cppi5_desc_vaddr)
		3454	return -ENOMEM;
		3455
		3456	hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr,
		3457	hwdesc->cppi5_desc_size,
		3458	DMA_TO_DEVICE);
		3459	if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr))
		3460	return -ENOMEM;
		3461
		3462	desc = hwdesc->cppi5_desc_vaddr;
		3463	cppi5_hdesc_init(desc, 0, 0);
		3464	cppi5_desc_set_pktids(&desc->hdr, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT);
		3465	cppi5_desc_set_retpolicy(&desc->hdr, 0, 0);
		3466
		3467	cppi5_hdesc_attach_buf(desc,
		3468	rx_flush->buffer_paddr, rx_flush->buffer_size,
		3469	rx_flush->buffer_paddr, rx_flush->buffer_size);
		3470
		3471	dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr,
		3472	hwdesc->cppi5_desc_size, DMA_TO_DEVICE);
		3473	return 0;
		3474	}
		3475
3251	#define TI_UDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) \| \	3476	#define TI_UDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) \| \
3252	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) \| \	3477	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) \| \
3253	BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) \| \	3478	BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) \| \
@@ -3361,6 +3586,10 @@ static int udma_probe(struct platform_device *pdev) · 107 unmodified lines
3361	if (ud->desc_align < dma_get_cache_alignment())	3586	if (ud->desc_align < dma_get_cache_alignment())
3362	ud->desc_align = dma_get_cache_alignment();	3587	ud->desc_align = dma_get_cache_alignment();
3363		3588
		3589	ret = udma_setup_rx_flush(ud);
		3590	if (ret)
		3591	return ret;
		3592
3364	for (i = 0; i < ud->tchan_cnt; i++) {	3593	for (i = 0; i < ud->tchan_cnt; i++) {
3365	struct udma_tchan *tchan = &ud->tchans[i];	3594	struct udma_tchan *tchan = &ud->tchans[i];
3366		3595

drivers/edac/synopsys_edac.c+7−15

 		pinf = &p->ceinfo;
 		if (!priv->p_data->quirks) {
 			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-				 "DDR ECC error type:%s Row %d Bank %d Col %d ",
+				 "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x",
-				  "CE", pinf->row, pinf->bank, pinf->col);
+				 "CE", pinf->row, pinf->bank, pinf->col,
-			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-				 "Bit Position: %d Data: 0x%08x\n",
 				 pinf->bitpos, pinf->data);
 		} else {
 			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-				 "DDR ECC error type:%s Row %d Bank %d Col %d ",
+				 "DDR ECC error type:%s Row %d Bank %d Col %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0x%08x",
-				  "CE", pinf->row, pinf->bank, pinf->col);
+				 "CE", pinf->row, pinf->bank, pinf->col,
-			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
+				 pinf->bankgrpnr, pinf->blknr,
-				 "BankGroup Number %d Block Number %d ",
-				 pinf->bankgrpnr, pinf->blknr);
-			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-				 "Bit Position: %d Data: 0x%08x\n",
 				 pinf->bitpos, pinf->data);
 		}
 				"UE", pinf->row, pinf->bank, pinf->col);
 		} else {
 			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-				 "DDR ECC error type :%s Row %d Bank %d Col %d ",
+				 "DDR ECC error type :%s Row %d Bank %d Col %d BankGroup Number %d Block Number %d",
-				 "UE", pinf->row, pinf->bank, pinf->col);
+				 "UE", pinf->row, pinf->bank, pinf->col,
-			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-				 "BankGroup Number %d Block Number %d",
 				 pinf->bankgrpnr, pinf->blknr);
 		}

drivers/firmware/efi/efi.c+2−2

@@ -552,7 +552,7 @@ int __init efi_config_parse_tables(void *config_tables, int count, int sz, · 551 unmodified lines
552		552
553	seed = early_memremap(efi.rng_seed, sizeof(*seed));	553	seed = early_memremap(efi.rng_seed, sizeof(*seed));
554	if (seed != NULL) {	554	if (seed != NULL) {
555	size = seed->size;	555	size = READ_ONCE(seed->size);
556	early_memunmap(seed, sizeof(*seed));	556	early_memunmap(seed, sizeof(*seed));
557	} else {	557	} else {
558	pr_err("Could not map UEFI random seed!\n");	558	pr_err("Could not map UEFI random seed!\n");
@@ -562,7 +562,7 @@ int __init efi_config_parse_tables(void *config_tables, int count, int sz, · 3 unmodified lines
562	sizeof(*seed) + size);	562	sizeof(*seed) + size);
563	if (seed != NULL) {	563	if (seed != NULL) {
564	pr_notice("seeding entropy pool\n");	564	pr_notice("seeding entropy pool\n");
565	add_bootloader_randomness(seed->bits, seed->size);	565	add_bootloader_randomness(seed->bits, size);
566	early_memunmap(seed, sizeof(*seed) + size);	566	early_memunmap(seed, sizeof(*seed) + size);
567	} else {	567	} else {
568	pr_err("Could not map UEFI random seed!\n");	568	pr_err("Could not map UEFI random seed!\n");

drivers/firmware/efi/efivars.c+23−9

 efivar_attr_read(struct efivar_entry *entry, char *buf)
 {
 	struct efi_variable *var = &entry->var;
+	unsigned long size = sizeof(var->Data);
 	char *str = buf;
+	int ret;
 	if (!entry || !buf)
 		return -EINVAL;
-	var->DataSize = 1024;
+	ret = efivar_entry_get(entry, &var->Attributes, &size, var->Data);
-	if (efivar_entry_get(entry, &var->Attributes, &var->DataSize, var->Data))
+	var->DataSize = size;
+	if (ret)
 		return -EIO;
 	if (var->Attributes & EFI_VARIABLE_NON_VOLATILE)
 efivar_size_read(struct efivar_entry *entry, char *buf)
 {
 	struct efi_variable *var = &entry->var;
+	unsigned long size = sizeof(var->Data);
 	char *str = buf;
+	int ret;
 	if (!entry || !buf)
 		return -EINVAL;
-	var->DataSize = 1024;
+	ret = efivar_entry_get(entry, &var->Attributes, &size, var->Data);
-	if (efivar_entry_get(entry, &var->Attributes, &var->DataSize, var->Data))
+	var->DataSize = size;
+	if (ret)
 		return -EIO;
 	str += sprintf(str, "0x%lx\n", var->DataSize);
 efivar_data_read(struct efivar_entry *entry, char *buf)
 {
 	struct efi_variable *var = &entry->var;
+	unsigned long size = sizeof(var->Data);
+	int ret;
 	if (!entry || !buf)
 		return -EINVAL;
-	var->DataSize = 1024;
+	ret = efivar_entry_get(entry, &var->Attributes, &size, var->Data);
-	if (efivar_entry_get(entry, &var->Attributes, &var->DataSize, var->Data))
+	var->DataSize = size;
+	if (ret)
 		return -EIO;
 	memcpy(buf, var->Data, var->DataSize);
 	u8 *data;
 	int err;
+	if (!entry || !buf)
+		return -EINVAL;
 	if (in_compat_syscall()) {
 		struct compat_efi_variable *compat;
 {
 	struct efi_variable *var = &entry->var;
 	struct compat_efi_variable *compat;
+	unsigned long datasize = sizeof(var->Data);
 	size_t size;
+	int ret;
 	if (!entry || !buf)
 		return 0;
-	var->DataSize = 1024;
+	ret = efivar_entry_get(entry, &var->Attributes, &datasize, var->Data);
-	if (efivar_entry_get(entry, &entry->var.Attributes,
+	var->DataSize = datasize;
-			     &entry->var.DataSize, entry->var.Data))
+	if (ret)
 		return -EIO;
 	if (in_compat_syscall()) {

drivers/firmware/imx/imx-scu.c+27−0

@@ -29,6 +29,7 @@ struct imx_sc_chan { · 28 unmodified lines
29	struct mbox_client cl;	29	struct mbox_client cl;
30	struct mbox_chan *ch;	30	struct mbox_chan *ch;
31	int idx;	31	int idx;
		32	struct completion tx_done;
32	};	33	};
33		34
34	struct imx_sc_ipc {	35	struct imx_sc_ipc {
@@ -100,6 +101,14 @@ int imx_scu_get_handle(struct imx_sc_ipc **ipc) · 65 unmodified lines
100	}	101	}
101	EXPORT_SYMBOL(imx_scu_get_handle);	102	EXPORT_SYMBOL(imx_scu_get_handle);
102		103
		104	/* Callback called when the word of a message is ack-ed, eg read by SCU */
		105	static void imx_scu_tx_done(struct mbox_client cl, void mssg, int r)
		106	{
		107	struct imx_sc_chan *sc_chan = container_of(cl, struct imx_sc_chan, cl);
		108
		109	complete(&sc_chan->tx_done);
		110	}
		111
103	static void imx_scu_rx_callback(struct mbox_client c, void msg)	112	static void imx_scu_rx_callback(struct mbox_client c, void msg)
104	{	113	{
105	struct imx_sc_chan *sc_chan = container_of(c, struct imx_sc_chan, cl);	114	struct imx_sc_chan *sc_chan = container_of(c, struct imx_sc_chan, cl);
@@ -149,6 +158,19 @@ static int imx_scu_ipc_write(struct imx_sc_ipc sc_ipc, void msg) · 43 unmodified lines
149		158
150	for (i = 0; i < hdr->size; i++) {	159	for (i = 0; i < hdr->size; i++) {
151	sc_chan = &sc_ipc->chans[i % 4];	160	sc_chan = &sc_ipc->chans[i % 4];
		161
		162	/*
		163	* SCU requires that all messages words are written
		164	* sequentially but linux MU driver implements multiple
		165	* independent channels for each register so ordering between
		166	* different channels must be ensured by SCU API interface.
		167	*
		168	* Wait for tx_done before every send to ensure that no
		169	* queueing happens at the mailbox channel level.
		170	*/
		171	wait_for_completion(&sc_chan->tx_done);
		172	reinit_completion(&sc_chan->tx_done);
		173
152	ret = mbox_send_message(sc_chan->ch, &data[i]);	174	ret = mbox_send_message(sc_chan->ch, &data[i]);
153	if (ret < 0)	175	if (ret < 0)
154	return ret;	176	return ret;
@@ -247,6 +269,11 @@ static int imx_scu_probe(struct platform_device *pdev) · 92 unmodified lines
247	cl->knows_txdone = true;	269	cl->knows_txdone = true;
248	cl->rx_callback = imx_scu_rx_callback;	270	cl->rx_callback = imx_scu_rx_callback;
249		271
		272	/* Initial tx_done completion as "done" */
		273	cl->tx_done = imx_scu_tx_done;
		274	init_completion(&sc_chan->tx_done);
		275	complete(&sc_chan->tx_done);
		276
250	sc_chan->sc_ipc = sc_ipc;	277	sc_chan->sc_ipc = sc_ipc;
251	sc_chan->idx = i % 4;	278	sc_chan->idx = i % 4;
252	sc_chan->ch = mbox_request_channel_byname(cl, chan_name);	279	sc_chan->ch = mbox_request_channel_byname(cl, chan_name);

drivers/firmware/imx/misc.c+4−4

@@ -16,7 +16,7 @@ struct imx_sc_msg_req_misc_set_ctrl { · 15 unmodified lines
16	u32 ctrl;	16	u32 ctrl;
17	u32 val;	17	u32 val;
18	u16 resource;	18	u16 resource;
19	} __packed;	19	} __packed __aligned(4);
20		20
21	struct imx_sc_msg_req_cpu_start {	21	struct imx_sc_msg_req_cpu_start {
22	struct imx_sc_rpc_msg hdr;	22	struct imx_sc_rpc_msg hdr;
@@ -24,18 +24,18 @@ struct imx_sc_msg_req_cpu_start { · 1 unmodified line
24	u32 address_lo;	24	u32 address_lo;
25	u16 resource;	25	u16 resource;
26	u8 enable;	26	u8 enable;
27	} __packed;	27	} __packed __aligned(4);
28		28
29	struct imx_sc_msg_req_misc_get_ctrl {	29	struct imx_sc_msg_req_misc_get_ctrl {
30	struct imx_sc_rpc_msg hdr;	30	struct imx_sc_rpc_msg hdr;
31	u32 ctrl;	31	u32 ctrl;
32	u16 resource;	32	u16 resource;
33	} __packed;	33	} __packed __aligned(4);
34		34
35	struct imx_sc_msg_resp_misc_get_ctrl {	35	struct imx_sc_msg_resp_misc_get_ctrl {
36	struct imx_sc_rpc_msg hdr;	36	struct imx_sc_rpc_msg hdr;
37	u32 val;	37	u32 val;
38	} __packed;	38	} __packed __aligned(4);
39		39
40	/*	40	/*
41	* This function sets a miscellaneous control value.	41	* This function sets a miscellaneous control value.

drivers/firmware/imx/scu-pd.c+1−1

@@ -61,7 +61,7 @@ struct imx_sc_msg_req_set_resource_power_mode { · 60 unmodified lines
61	struct imx_sc_rpc_msg hdr;	61	struct imx_sc_rpc_msg hdr;
62	u16 resource;	62	u16 resource;
63	u8 mode;	63	u8 mode;
64	} __packed;	64	} __packed __aligned(4);
65		65
66	#define IMX_SCU_PD_NAME_SIZE 20	66	#define IMX_SCU_PD_NAME_SIZE 20
67	struct imx_sc_pm_domain {	67	struct imx_sc_pm_domain {

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c+3−3

@@ -781,11 +781,11 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file f, char __user buf, · 780 unmodified lines
781	ssize_t result = 0;	781	ssize_t result = 0;
782	uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;	782	uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
783		783
784	if (size & 3 \|\| *pos & 3)	784	if (size > 4096 \|\| size & 3 \|\| *pos & 3)
785	return -EINVAL;	785	return -EINVAL;
786		786
787	/* decode offset */	787	/* decode offset */
788	offset = *pos & GENMASK_ULL(11, 0);	788	offset = (*pos & GENMASK_ULL(11, 0)) >> 2;
789	se = (*pos & GENMASK_ULL(19, 12)) >> 12;	789	se = (*pos & GENMASK_ULL(19, 12)) >> 12;
790	sh = (*pos & GENMASK_ULL(27, 20)) >> 20;	790	sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
791	cu = (*pos & GENMASK_ULL(35, 28)) >> 28;	791	cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
@@ -823,7 +823,7 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file f, char __user buf, · 31 unmodified lines
823	while (size) {	823	while (size) {
824	uint32_t value;	824	uint32_t value;
825		825
826	value = data[offset++];	826	value = data[result >> 2];
827	r = put_user(value, (uint32_t *)buf);	827	r = put_user(value, (uint32_t *)buf);
828	if (r) {	828	if (r) {
829	result = r;	829	result = r;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+4−0

 				if (r)
 					goto out;
+				amdgpu_fbdev_set_suspend(tmp_adev, 0);
 				/* must succeed. */
 				amdgpu_ras_resume(tmp_adev);
 		 */
 		amdgpu_unregister_gpu_instance(tmp_adev);
+		amdgpu_fbdev_set_suspend(adev, 1);
 		/* disable ras on ALL IPs */
 		if (!(in_ras_intr && !use_baco) &&
 		      amdgpu_device_ip_need_full_reset(tmp_adev))

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+1−1

@@ -1389,7 +1389,7 @@ amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, · 1388 unmodified lines
1389		1389
1390	static struct drm_driver kms_driver = {	1390	static struct drm_driver kms_driver = {
1391	.driver_features =	1391	.driver_features =
1392	DRIVER_USE_AGP \| DRIVER_ATOMIC \|	1392	DRIVER_ATOMIC \|
1393	DRIVER_GEM \|	1393	DRIVER_GEM \|
1394	DRIVER_RENDER \| DRIVER_MODESET \| DRIVER_SYNCOBJ \|	1394	DRIVER_RENDER \| DRIVER_MODESET \| DRIVER_SYNCOBJ \|
1395	DRIVER_SYNCOBJ_TIMELINE,	1395	DRIVER_SYNCOBJ_TIMELINE,

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h+1−0

@@ -195,6 +195,7 @@ struct amdgpu_gmc { · 194 unmodified lines
195	uint32_t srbm_soft_reset;	195	uint32_t srbm_soft_reset;
196	bool prt_warning;	196	bool prt_warning;
197	uint64_t stolen_size;	197	uint64_t stolen_size;
		198	uint32_t sdpif_register;
198	/* apertures */	199	/* apertures */
199	u64 shared_aperture_start;	200	u64 shared_aperture_start;
200	u64 shared_aperture_end;	201	u64 shared_aperture_end;

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c+52−46

@@ -52,7 +52,7 @@ · 51 unmodified lines
52	* 1. Primary ring	52	* 1. Primary ring
53	* 2. Async ring	53	* 2. Async ring
54	*/	54	*/
55	#define GFX10_NUM_GFX_RINGS 2	55	#define GFX10_NUM_GFX_RINGS_NV1X 1
56	#define GFX10_MEC_HPD_SIZE 2048	56	#define GFX10_MEC_HPD_SIZE 2048
57		57
58	#define F32_CE_PROGRAM_RAM_SIZE 65536	58	#define F32_CE_PROGRAM_RAM_SIZE 65536
@@ -1304,7 +1304,7 @@ static int gfx_v10_0_sw_init(void *handle) · 1245 unmodified lines
1304	case CHIP_NAVI14:	1304	case CHIP_NAVI14:
1305	case CHIP_NAVI12:	1305	case CHIP_NAVI12:
1306	adev->gfx.me.num_me = 1;	1306	adev->gfx.me.num_me = 1;
1307	adev->gfx.me.num_pipe_per_me = 2;	1307	adev->gfx.me.num_pipe_per_me = 1;
1308	adev->gfx.me.num_queue_per_pipe = 1;	1308	adev->gfx.me.num_queue_per_pipe = 1;
1309	adev->gfx.mec.num_mec = 2;	1309	adev->gfx.mec.num_mec = 2;
1310	adev->gfx.mec.num_pipe_per_mec = 4;	1310	adev->gfx.mec.num_pipe_per_mec = 4;
@@ -2710,18 +2710,20 @@ static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) · 1399 unmodified lines
2710	amdgpu_ring_commit(ring);	2710	amdgpu_ring_commit(ring);
2711		2711
2712	/* submit cs packet to copy state 0 to next available state */	2712	/* submit cs packet to copy state 0 to next available state */
2713	ring = &adev->gfx.gfx_ring[1];	2713	if (adev->gfx.num_gfx_rings > 1) {
2714	r = amdgpu_ring_alloc(ring, 2);	2714	/* maximum supported gfx ring is 2 */
2715	if (r) {	2715	ring = &adev->gfx.gfx_ring[1];
2716	DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);	2716	r = amdgpu_ring_alloc(ring, 2);
2717	return r;	2717	if (r) {
2718	}	2718	DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2719		2719	return r;
2720	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));	2720	}
2721	amdgpu_ring_write(ring, 0);
2722		2721
2723	amdgpu_ring_commit(ring);	2722	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
		2723	amdgpu_ring_write(ring, 0);
2724		2724
		2725	amdgpu_ring_commit(ring);
		2726	}
2725	return 0;	2727	return 0;
2726	}	2728	}
2727		2729
@@ -2818,39 +2820,41 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) · 90 unmodified lines
2818	mutex_unlock(&adev->srbm_mutex);	2820	mutex_unlock(&adev->srbm_mutex);
2819		2821
2820	/* Init gfx ring 1 for pipe 1 */	2822	/* Init gfx ring 1 for pipe 1 */
2821	mutex_lock(&adev->srbm_mutex);	2823	if (adev->gfx.num_gfx_rings > 1) {
2822	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);	2824	mutex_lock(&adev->srbm_mutex);
2823	ring = &adev->gfx.gfx_ring[1];	2825	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2824	rb_bufsz = order_base_2(ring->ring_size / 8);	2826	/* maximum supported gfx ring is 2 */
2825	tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);	2827	ring = &adev->gfx.gfx_ring[1];
2826	tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);	2828	rb_bufsz = order_base_2(ring->ring_size / 8);
2827	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);	2829	tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2828	/* Initialize the ring buffer's write pointers */	2830	tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2829	ring->wptr = 0;	2831	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2830	WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));	2832	/* Initialize the ring buffer's write pointers */
2831	WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));	2833	ring->wptr = 0;
2832	/* Set the wb address wether it's enabled or not */	2834	WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2833	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);	2835	WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2834	WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));	2836	/* Set the wb address wether it's enabled or not */
2835	WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &	2837	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2836	CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);	2838	WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2837	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);	2839	WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2838	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,	2840	CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2839	lower_32_bits(wptr_gpu_addr));	2841	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2840	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,	2842	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2841	upper_32_bits(wptr_gpu_addr));	2843	lower_32_bits(wptr_gpu_addr));
2842		2844	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2843	mdelay(1);	2845	upper_32_bits(wptr_gpu_addr));
2844	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);	2846
2845		2847	mdelay(1);
2846	rb_addr = ring->gpu_addr >> 8;	2848	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2847	WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);	2849
2848	WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));	2850	rb_addr = ring->gpu_addr >> 8;
2849	WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);	2851	WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2850		2852	WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2851	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);	2853	WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2852	mutex_unlock(&adev->srbm_mutex);	2854
2853		2855	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
		2856	mutex_unlock(&adev->srbm_mutex);
		2857	}
2854	/* Switch to pipe 0 */	2858	/* Switch to pipe 0 */
2855	mutex_lock(&adev->srbm_mutex);	2859	mutex_lock(&adev->srbm_mutex);
2856	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);	2860	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
@@ -3513,6 +3517,7 @@ static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) · 656 unmodified lines
3513		3517
3514	/* reset ring buffer */	3518	/* reset ring buffer */
3515	ring->wptr = 0;	3519	ring->wptr = 0;
		3520	atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
3516	amdgpu_ring_clear_ring(ring);	3521	amdgpu_ring_clear_ring(ring);
3517	} else {	3522	} else {
3518	amdgpu_ring_clear_ring(ring);	3523	amdgpu_ring_clear_ring(ring);
@@ -3966,7 +3971,8 @@ static int gfx_v10_0_early_init(void *handle) · 447 unmodified lines
3966	{	3971	{
3967	struct amdgpu_device adev = (struct amdgpu_device )handle;	3972	struct amdgpu_device adev = (struct amdgpu_device )handle;
3968		3973
3969	adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS;	3974	adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
		3975
3970	adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;	3976	adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3971		3977
3972	gfx_v10_0_set_kiq_pm4_funcs(adev);	3978	gfx_v10_0_set_kiq_pm4_funcs(adev);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+1−0

@@ -3663,6 +3663,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) · 3662 unmodified lines
3663		3663
3664	/* reset ring buffer */	3664	/* reset ring buffer */
3665	ring->wptr = 0;	3665	ring->wptr = 0;
		3666	atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
3666	amdgpu_ring_clear_ring(ring);	3667	amdgpu_ring_clear_ring(ring);
3667	} else {	3668	} else {
3668	amdgpu_ring_clear_ring(ring);	3669	amdgpu_ring_clear_ring(ring);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c+36−1

@@ -1271,6 +1271,19 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) · 1270 unmodified lines
1271	}	1271	}
1272	}	1272	}
1273		1273
		1274	/**
		1275	* gmc_v9_0_restore_registers - restores regs
		1276	*
		1277	* @adev: amdgpu_device pointer
		1278	*
		1279	* This restores register values, saved at suspend.
		1280	*/
		1281	static void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
		1282	{
		1283	if (adev->asic_type == CHIP_RAVEN)
		1284	WREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
		1285	}
		1286
1274	/**	1287	/**
1275	* gmc_v9_0_gart_enable - gart enable	1288	* gmc_v9_0_gart_enable - gart enable
1276	*	1289	*
@@ -1376,6 +1389,20 @@ static int gmc_v9_0_hw_init(void *handle) · 99 unmodified lines
1376	return r;	1389	return r;
1377	}	1390	}
1378		1391
		1392	/**
		1393	* gmc_v9_0_save_registers - saves regs
		1394	*
		1395	* @adev: amdgpu_device pointer
		1396	*
		1397	* This saves potential register values that should be
		1398	* restored upon resume
		1399	*/
		1400	static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
		1401	{
		1402	if (adev->asic_type == CHIP_RAVEN)
		1403	adev->gmc.sdpif_register = RREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
		1404	}
		1405
1379	/**	1406	/**
1380	* gmc_v9_0_gart_disable - gart disable	1407	* gmc_v9_0_gart_disable - gart disable
1381	*	1408	*
@@ -1412,9 +1439,16 @@ static int gmc_v9_0_hw_fini(void *handle) · 30 unmodified lines
1412		1439
1413	static int gmc_v9_0_suspend(void *handle)	1440	static int gmc_v9_0_suspend(void *handle)
1414	{	1441	{
		1442	int r;
1415	struct amdgpu_device adev = (struct amdgpu_device )handle;	1443	struct amdgpu_device adev = (struct amdgpu_device )handle;
1416		1444
1417	return gmc_v9_0_hw_fini(adev);	1445	r = gmc_v9_0_hw_fini(adev);
		1446	if (r)
		1447	return r;
		1448
		1449	gmc_v9_0_save_registers(adev);
		1450
		1451	return 0;
1418	}	1452	}
1419		1453
1420	static int gmc_v9_0_resume(void *handle)	1454	static int gmc_v9_0_resume(void *handle)
@@ -1422,6 +1456,7 @@ static int gmc_v9_0_resume(void *handle) · 1 unmodified line
1422	int r;	1456	int r;
1423	struct amdgpu_device adev = (struct amdgpu_device )handle;	1457	struct amdgpu_device adev = (struct amdgpu_device )handle;
1424		1458
		1459	gmc_v9_0_restore_registers(adev);
1425	r = gmc_v9_0_hw_init(adev);	1460	r = gmc_v9_0_hw_init(adev);
1426	if (r)	1461	if (r)
1427	return r;	1462	return r;

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c+1−1

@@ -693,7 +693,7 @@ static int jpeg_v2_0_set_clockgating_state(void *handle, · 692 unmodified lines
693	bool enable = (state == AMD_CG_STATE_GATE);	693	bool enable = (state == AMD_CG_STATE_GATE);
694		694
695	if (enable) {	695	if (enable) {
696	if (jpeg_v2_0_is_idle(handle))	696	if (!jpeg_v2_0_is_idle(handle))
697	return -EBUSY;	697	return -EBUSY;
698	jpeg_v2_0_enable_clock_gating(adev);	698	jpeg_v2_0_enable_clock_gating(adev);
699	} else {	699	} else {

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c+1−1

@@ -477,7 +477,7 @@ static int jpeg_v2_5_set_clockgating_state(void *handle, · 476 unmodified lines
477	continue;	477	continue;
478		478
479	if (enable) {	479	if (enable) {
480	if (jpeg_v2_5_is_idle(handle))	480	if (!jpeg_v2_5_is_idle(handle))
481	return -EBUSY;	481	return -EBUSY;
482	jpeg_v2_5_enable_clock_gating(adev, i);	482	jpeg_v2_5_enable_clock_gating(adev, i);
483	} else {	483	} else {

drivers/gpu/drm/amd/amdgpu/soc15.c+23−2

 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK	0x00010000L
 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK		0x00020000L
 #define mmHDP_MEM_POWER_CTRL_BASE_IDX	0
+/* for Vega20/arcturus regiter offset change */
+#define	mmROM_INDEX_VG20				0x00e4
+#define	mmROM_INDEX_VG20_BASE_IDX			0
+#define	mmROM_DATA_VG20					0x00e5
+#define	mmROM_DATA_VG20_BASE_IDX			0
 /*
  * Indirect registers accessor
  */
 {
 	u32 *dw_ptr;
 	u32 i, length_dw;
+	uint32_t rom_index_offset;
+	uint32_t rom_data_offset;
 	if (bios == NULL)
 		return false;
 	dw_ptr = (u32 *)bios;
 	length_dw = ALIGN(length_bytes, 4) / 4;
+	switch (adev->asic_type) {
+	case CHIP_VEGA20:
+	case CHIP_ARCTURUS:
+		rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20);
+		rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20);
+		break;
+	default:
+		rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
+		rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
+		break;
+	}
 	/* set rom index to 0 */
-	WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
+	WREG32(rom_index_offset, 0);
 	/* read out the rom data */
 	for (i = 0; i < length_dw; i++)
-		dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
+		dw_ptr[i] = RREG32(rom_data_offset);
 	return true;
 }

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c+1−1

@@ -1352,7 +1352,7 @@ static int vcn_v1_0_set_clockgating_state(void *handle, · 1351 unmodified lines
1352		1352
1353	if (enable) {	1353	if (enable) {
1354	/* wait for STATUS to clear */	1354	/* wait for STATUS to clear */
1355	if (vcn_v1_0_is_idle(handle))	1355	if (!vcn_v1_0_is_idle(handle))
1356	return -EBUSY;	1356	return -EBUSY;
1357	vcn_v1_0_enable_clock_gating(adev);	1357	vcn_v1_0_enable_clock_gating(adev);
1358	} else {	1358	} else {

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c+1−1

@@ -1217,7 +1217,7 @@ static int vcn_v2_0_set_clockgating_state(void *handle, · 1216 unmodified lines
1217		1217
1218	if (enable) {	1218	if (enable) {
1219	/* wait for STATUS to clear */	1219	/* wait for STATUS to clear */
1220	if (vcn_v2_0_is_idle(handle))	1220	if (!vcn_v2_0_is_idle(handle))
1221	return -EBUSY;	1221	return -EBUSY;
1222	vcn_v2_0_enable_clock_gating(adev);	1222	vcn_v2_0_enable_clock_gating(adev);
1223	} else {	1223	} else {

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c+1−1

@@ -1672,7 +1672,7 @@ static int vcn_v2_5_set_clockgating_state(void *handle, · 1671 unmodified lines
1672	return 0;	1672	return 0;
1673		1673
1674	if (enable) {	1674	if (enable) {
1675	if (vcn_v2_5_is_idle(handle))	1675	if (!vcn_v2_5_is_idle(handle))
1676	return -EBUSY;	1676	return -EBUSY;
1677	vcn_v2_5_enable_clock_gating(adev);	1677	vcn_v2_5_enable_clock_gating(adev);
1678	} else {	1678	} else {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+84−3

@@ -522,8 +522,9 @@ static void dm_dcn_crtc_high_irq(void *interrupt_params) · 521 unmodified lines
522		522
523	acrtc_state = to_dm_crtc_state(acrtc->base.state);	523	acrtc_state = to_dm_crtc_state(acrtc->base.state);
524		524
525	DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,	525	DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
526	amdgpu_dm_vrr_active(acrtc_state));	526	amdgpu_dm_vrr_active(acrtc_state),
		527	acrtc_state->active_planes);
527		528
528	amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);	529	amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
529	drm_crtc_handle_vblank(&acrtc->base);	530	drm_crtc_handle_vblank(&acrtc->base);
@@ -543,7 +544,18 @@ static void dm_dcn_crtc_high_irq(void *interrupt_params) · 13 unmodified lines
543	&acrtc_state->vrr_params.adjust);	544	&acrtc_state->vrr_params.adjust);
544	}	545	}
545		546
546	if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {	547	/*
		548	* If there aren't any active_planes then DCH HUBP may be clock-gated.
		549	* In that case, pageflip completion interrupts won't fire and pageflip
		550	* completion events won't get delivered. Prevent this by sending
		551	* pending pageflip events from here if a flip is still pending.
		552	*
		553	* If any planes are enabled, use dm_pflip_high_irq() instead, to
		554	* avoid race conditions between flip programming and completion,
		555	* which could cause too early flip completion events.
		556	*/
		557	if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
		558	acrtc_state->active_planes == 0) {
547	if (acrtc->event) {	559	if (acrtc->event) {
548	drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);	560	drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
549	acrtc->event = NULL;	561	acrtc->event = NULL;
@@ -1422,6 +1434,73 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) · 872 unmodified lines
1422	drm_kms_helper_hotplug_event(dev);	1434	drm_kms_helper_hotplug_event(dev);
1423	}	1435	}
1424		1436
		1437	static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
		1438	{
		1439	struct smu_context *smu = &adev->smu;
		1440	int ret = 0;
		1441
		1442	if (!is_support_sw_smu(adev))
		1443	return 0;
		1444
		1445	/* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
		1446	* on window driver dc implementation.
		1447	* For Navi1x, clock settings of dcn watermarks are fixed. the settings
		1448	* should be passed to smu during boot up and resume from s3.
		1449	* boot up: dc calculate dcn watermark clock settings within dc_create,
		1450	* dcn20_resource_construct
		1451	* then call pplib functions below to pass the settings to smu:
		1452	* smu_set_watermarks_for_clock_ranges
		1453	* smu_set_watermarks_table
		1454	* navi10_set_watermarks_table
		1455	* smu_write_watermarks_table
		1456	*
		1457	* For Renoir, clock settings of dcn watermark are also fixed values.
		1458	* dc has implemented different flow for window driver:
		1459	* dc_hardware_init / dc_set_power_state
		1460	* dcn10_init_hw
		1461	* notify_wm_ranges
		1462	* set_wm_ranges
		1463	* -- Linux
		1464	* smu_set_watermarks_for_clock_ranges
		1465	* renoir_set_watermarks_table
		1466	* smu_write_watermarks_table
		1467	*
		1468	* For Linux,
		1469	* dc_hardware_init -> amdgpu_dm_init
		1470	* dc_set_power_state --> dm_resume
		1471	*
		1472	* therefore, this function apply to navi10/12/14 but not Renoir
		1473	* *
		1474	*/
		1475	switch(adev->asic_type) {
		1476	case CHIP_NAVI10:
		1477	case CHIP_NAVI14:
		1478	case CHIP_NAVI12:
		1479	break;
		1480	default:
		1481	return 0;
		1482	}
		1483
		1484	mutex_lock(&smu->mutex);
		1485
		1486	/* pass data to smu controller */
		1487	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
		1488	!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
		1489	ret = smu_write_watermarks_table(smu);
		1490
		1491	if (ret) {
		1492	mutex_unlock(&smu->mutex);
		1493	DRM_ERROR("Failed to update WMTABLE!\n");
		1494	return ret;
		1495	}
		1496	smu->watermarks_bitmap \|= WATERMARKS_LOADED;
		1497	}
		1498
		1499	mutex_unlock(&smu->mutex);
		1500
		1501	return 0;
		1502	}
		1503
1425	/**	1504	/**
1426	* dm_hw_init() - Initialize DC device	1505	* dm_hw_init() - Initialize DC device
1427	* @handle: The base driver device containing the amdgpu_dm device.	1506	* @handle: The base driver device containing the amdgpu_dm device.
@@ -1700,6 +1779,8 @@ static int dm_resume(void *handle) · 272 unmodified lines
1700		1779
1701	amdgpu_dm_irq_resume_late(adev);	1780	amdgpu_dm_irq_resume_late(adev);
1702		1781
		1782	amdgpu_dm_smu_write_watermarks_table(adev);
		1783
1703	return 0;	1784	return 0;
1704	}	1785	}
1705		1786

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+1−0

@@ -451,6 +451,7 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, · 450 unmodified lines
451	aconnector->dc_sink);	451	aconnector->dc_sink);
452	dc_sink_release(aconnector->dc_sink);	452	dc_sink_release(aconnector->dc_sink);
453	aconnector->dc_sink = NULL;	453	aconnector->dc_sink = NULL;
		454	aconnector->dc_link->cur_link_settings.lane_count = 0;
454	}	455	}
455		456
456	drm_connector_unregister(connector);	457	drm_connector_unregister(connector);

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+11−0

@@ -3401,6 +3401,17 @@ static bool retrieve_link_cap(struct dc_link *link) · 3400 unmodified lines
3401	sink_id.ieee_device_id,	3401	sink_id.ieee_device_id,
3402	sizeof(sink_id.ieee_device_id));	3402	sizeof(sink_id.ieee_device_id));
3403		3403
		3404	/* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
		3405	{
		3406	uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
		3407
		3408	if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
		3409	!memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
		3410	sizeof(str_mbp_2017))) {
		3411	link->reported_link_cap.link_rate = 0x0c;
		3412	}
		3413	}
		3414
3404	core_link_read_dpcd(	3415	core_link_read_dpcd(
3405	link,	3416	link,
3406	DP_SINK_HW_REVISION_START,	3417	DP_SINK_HW_REVISION_START,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c+2−2

@@ -840,8 +840,8 @@ static void hubbub1_det_request_size( · 839 unmodified lines
840		840
841	hubbub1_get_blk256_size(&blk256_width, &blk256_height, bpe);	841	hubbub1_get_blk256_size(&blk256_width, &blk256_height, bpe);
842		842
843	swath_bytes_horz_wc = height * blk256_height * bpe;	843	swath_bytes_horz_wc = width * blk256_height * bpe;
844	swath_bytes_vert_wc = width * blk256_width * bpe;	844	swath_bytes_vert_wc = height * blk256_width * bpe;
845		845
846	req128_horz_wc = (2 swath_bytes_horz_wc <= detile_buf_size) ?	846	req128_horz_wc = (2 swath_bytes_horz_wc <= detile_buf_size) ?
847	false : /* full 256B request */	847	false : /* full 256B request */

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c+0−1

@@ -108,7 +108,6 @@ static const struct hwseq_private_funcs dcn20_private_funcs = { · 107 unmodified lines
108	.enable_power_gating_plane = dcn20_enable_power_gating_plane,	108	.enable_power_gating_plane = dcn20_enable_power_gating_plane,
109	.dpp_pg_control = dcn20_dpp_pg_control,	109	.dpp_pg_control = dcn20_dpp_pg_control,
110	.hubp_pg_control = dcn20_hubp_pg_control,	110	.hubp_pg_control = dcn20_hubp_pg_control,
111	.dsc_pg_control = NULL,
112	.update_odm = dcn20_update_odm,	111	.update_odm = dcn20_update_odm,
113	.dsc_pg_control = dcn20_dsc_pg_control,	112	.dsc_pg_control = dcn20_dsc_pg_control,
114	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,	113	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c+114−0

@@ -335,6 +335,117 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { · 334 unmodified lines
335	.use_urgent_burst_bw = 0	335	.use_urgent_burst_bw = 0
336	};	336	};
337		337
		338	struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
		339	.clock_limits = {
		340	{
		341	.state = 0,
		342	.dcfclk_mhz = 560.0,
		343	.fabricclk_mhz = 560.0,
		344	.dispclk_mhz = 513.0,
		345	.dppclk_mhz = 513.0,
		346	.phyclk_mhz = 540.0,
		347	.socclk_mhz = 560.0,
		348	.dscclk_mhz = 171.0,
		349	.dram_speed_mts = 8960.0,
		350	},
		351	{
		352	.state = 1,
		353	.dcfclk_mhz = 694.0,
		354	.fabricclk_mhz = 694.0,
		355	.dispclk_mhz = 642.0,
		356	.dppclk_mhz = 642.0,
		357	.phyclk_mhz = 600.0,
		358	.socclk_mhz = 694.0,
		359	.dscclk_mhz = 214.0,
		360	.dram_speed_mts = 11104.0,
		361	},
		362	{
		363	.state = 2,
		364	.dcfclk_mhz = 875.0,
		365	.fabricclk_mhz = 875.0,
		366	.dispclk_mhz = 734.0,
		367	.dppclk_mhz = 734.0,
		368	.phyclk_mhz = 810.0,
		369	.socclk_mhz = 875.0,
		370	.dscclk_mhz = 245.0,
		371	.dram_speed_mts = 14000.0,
		372	},
		373	{
		374	.state = 3,
		375	.dcfclk_mhz = 1000.0,
		376	.fabricclk_mhz = 1000.0,
		377	.dispclk_mhz = 1100.0,
		378	.dppclk_mhz = 1100.0,
		379	.phyclk_mhz = 810.0,
		380	.socclk_mhz = 1000.0,
		381	.dscclk_mhz = 367.0,
		382	.dram_speed_mts = 16000.0,
		383	},
		384	{
		385	.state = 4,
		386	.dcfclk_mhz = 1200.0,
		387	.fabricclk_mhz = 1200.0,
		388	.dispclk_mhz = 1284.0,
		389	.dppclk_mhz = 1284.0,
		390	.phyclk_mhz = 810.0,
		391	.socclk_mhz = 1200.0,
		392	.dscclk_mhz = 428.0,
		393	.dram_speed_mts = 16000.0,
		394	},
		395	/Extra state, no dispclk ramping/
		396	{
		397	.state = 5,
		398	.dcfclk_mhz = 1200.0,
		399	.fabricclk_mhz = 1200.0,
		400	.dispclk_mhz = 1284.0,
		401	.dppclk_mhz = 1284.0,
		402	.phyclk_mhz = 810.0,
		403	.socclk_mhz = 1200.0,
		404	.dscclk_mhz = 428.0,
		405	.dram_speed_mts = 16000.0,
		406	},
		407	},
		408	.num_states = 5,
		409	.sr_exit_time_us = 8.6,
		410	.sr_enter_plus_exit_time_us = 10.9,
		411	.urgent_latency_us = 4.0,
		412	.urgent_latency_pixel_data_only_us = 4.0,
		413	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
		414	.urgent_latency_vm_data_only_us = 4.0,
		415	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
		416	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
		417	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
		418	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
		419	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
		420	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
		421	.max_avg_sdp_bw_use_normal_percent = 40.0,
		422	.max_avg_dram_bw_use_normal_percent = 40.0,
		423	.writeback_latency_us = 12.0,
		424	.ideal_dram_bw_after_urgent_percent = 40.0,
		425	.max_request_size_bytes = 256,
		426	.dram_channel_width_bytes = 2,
		427	.fabric_datapath_to_dcn_data_return_bytes = 64,
		428	.dcn_downspread_percent = 0.5,
		429	.downspread_percent = 0.38,
		430	.dram_page_open_time_ns = 50.0,
		431	.dram_rw_turnaround_time_ns = 17.5,
		432	.dram_return_buffer_per_channel_bytes = 8192,
		433	.round_trip_ping_latency_dcfclk_cycles = 131,
		434	.urgent_out_of_order_return_per_channel_bytes = 256,
		435	.channel_interleave_bytes = 256,
		436	.num_banks = 8,
		437	.num_chans = 8,
		438	.vmm_page_size_bytes = 4096,
		439	.dram_clock_change_latency_us = 404.0,
		440	.dummy_pstate_latency_us = 5.0,
		441	.writeback_dram_clock_change_latency_us = 23.0,
		442	.return_bus_width_bytes = 64,
		443	.dispclk_dppclk_vco_speed_mhz = 3850,
		444	.xfc_bus_transport_time_us = 20,
		445	.xfc_xbuf_latency_tolerance_us = 4,
		446	.use_urgent_burst_bw = 0
		447	};
		448
338	struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };	449	struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
339		450
340	#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL	451	#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
@@ -3291,6 +3402,9 @@ void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st · 2950 unmodified lines
3291	static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(	3402	static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3292	uint32_t hw_internal_rev)	3403	uint32_t hw_internal_rev)
3293	{	3404	{
		3405	if (ASICREV_IS_NAVI14_M(hw_internal_rev))
		3406	return &dcn2_0_nv14_soc;
		3407
3294	if (ASICREV_IS_NAVI12_P(hw_internal_rev))	3408	if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3295	return &dcn2_0_nv12_soc;	3409	return &dcn2_0_nv12_soc;
3296		3410

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c+0−1

@@ -116,7 +116,6 @@ static const struct hwseq_private_funcs dcn21_private_funcs = { · 115 unmodified lines
116	.enable_power_gating_plane = dcn20_enable_power_gating_plane,	116	.enable_power_gating_plane = dcn20_enable_power_gating_plane,
117	.dpp_pg_control = dcn20_dpp_pg_control,	117	.dpp_pg_control = dcn20_dpp_pg_control,
118	.hubp_pg_control = dcn20_hubp_pg_control,	118	.hubp_pg_control = dcn20_hubp_pg_control,
119	.dsc_pg_control = NULL,
120	.update_odm = dcn20_update_odm,	119	.update_odm = dcn20_update_odm,
121	.dsc_pg_control = dcn20_dsc_pg_control,	120	.dsc_pg_control = dcn20_dsc_pg_control,
122	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,	121	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,

drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h+2−0

@@ -7376,6 +7376,8 @@ · 7375 unmodified lines
7376	#define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e	7376	#define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e
7377	#define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2	7377	#define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2
7378		7378
		7379	#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x395d
		7380	#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2
7379		7381
7380	// addressBlock: dce_dc_fmt4_dispdec	7382	// addressBlock: dce_dc_fmt4_dispdec
7381	// base address: 0x2000	7383	// base address: 0x2000

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c+6−3

@@ -222,7 +222,7 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, · 221 unmodified lines
222	{	222	{
223	int ret = 0;	223	int ret = 0;
224		224
225	if (min <= 0 && max <= 0)	225	if (min < 0 && max < 0)
226	return -EINVAL;	226	return -EINVAL;
227		227
228	if (!smu_clk_dpm_is_enabled(smu, clk_type))	228	if (!smu_clk_dpm_is_enabled(smu, clk_type))
@@ -2006,8 +2006,11 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu, · 1777 unmodified lines
2006	smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&	2006	smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2007	smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {	2007	smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2008	smu_set_watermarks_table(smu, table, clock_ranges);	2008	smu_set_watermarks_table(smu, table, clock_ranges);
2009	smu->watermarks_bitmap \|= WATERMARKS_EXIST;	2009
2010	smu->watermarks_bitmap &= ~WATERMARKS_LOADED;	2010	if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
		2011	smu->watermarks_bitmap \|= WATERMARKS_EXIST;
		2012	smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
		2013	}
2011	}	2014	}
2012		2015
2013	mutex_unlock(&smu->mutex);	2016	mutex_unlock(&smu->mutex);

drivers/gpu/drm/amd/powerplay/navi10_ppt.c+13−9

 {
 	int ret = 0;
-	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
-	    !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
-		ret = smu_write_watermarks_table(smu);
-		if (ret)
-			return ret;
-		smu->watermarks_bitmap |= WATERMARKS_LOADED;
-	}
 	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
 	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 				       *clock_ranges)
 {
 	int i;
+	int ret = 0;
 	Watermarks_t *table = watermarks;
 	if (!table || !clock_ranges)
 				clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
 	}
+	smu->watermarks_bitmap |= WATERMARKS_EXIST;
+	/* pass data to smu controller */
+	if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+		ret = smu_write_watermarks_table(smu);
+		if (ret) {
+			pr_err("Failed to update WMTABLE!");
+			return ret;
+		}
+		smu->watermarks_bitmap |= WATERMARKS_LOADED;
+	}
 	return 0;
 }

drivers/gpu/drm/amd/powerplay/renoir_ppt.c+6−5

 	CLK_MAP(GFXCLK, CLOCK_GFXCLK),
 	CLK_MAP(SCLK,	CLOCK_GFXCLK),
 	CLK_MAP(SOCCLK, CLOCK_SOCCLK),
-	CLK_MAP(UCLK, CLOCK_UMCCLK),
+	CLK_MAP(UCLK, CLOCK_FCLK),
-	CLK_MAP(MCLK, CLOCK_UMCCLK),
+	CLK_MAP(MCLK, CLOCK_FCLK),
 };
 static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = {
 		break;
 	case SMU_MCLK:
 		count = NUM_MEMCLK_DPM_LEVELS;
-		cur_value = metrics.ClockFrequency[CLOCK_UMCCLK];
+		cur_value = metrics.ClockFrequency[CLOCK_FCLK];
 		break;
 	case SMU_DCEFCLK:
 		count = NUM_DCFCLK_DPM_LEVELS;
 				clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
 	}
+	smu->watermarks_bitmap |= WATERMARKS_EXIST;
 	/* pass data to smu controller */
-	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+	if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
-			!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 		ret = smu_write_watermarks_table(smu);
 		if (ret) {
 			pr_err("Failed to update WMTABLE!");

drivers/gpu/drm/amd/powerplay/smu_v11_0.c+5−1

 	struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 	int ret = 0;
-	max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
+	if (!smu->smu_table.max_sustainable_clocks)
+		max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 					 GFP_KERNEL);
+	else
+		max_sustainable_clocks = smu->smu_table.max_sustainable_clocks;
 	smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 	max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;

drivers/gpu/drm/amd/powerplay/smu_v12_0.c+0−3

@@ -458,9 +458,6 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_ · 457 unmodified lines
458	{	458	{
459	int ret = 0;	459	int ret = 0;
460		460
461	if (max < min)
462	return -EINVAL;
463
464	switch (clk_type) {	461	switch (clk_type) {
465	case SMU_GFXCLK:	462	case SMU_GFXCLK:
466	case SMU_SCLK:	463	case SMU_SCLK:

drivers/gpu/drm/arm/display/komeda/komeda_drv.c+2−2

@@ -146,14 +146,14 @@ static const struct of_device_id komeda_of_match[] = { · 145 unmodified lines
146		146
147	MODULE_DEVICE_TABLE(of, komeda_of_match);	147	MODULE_DEVICE_TABLE(of, komeda_of_match);
148		148
149	static int komeda_rt_pm_suspend(struct device *dev)	149	static int __maybe_unused komeda_rt_pm_suspend(struct device *dev)
150	{	150	{
151	struct komeda_drv *mdrv = dev_get_drvdata(dev);	151	struct komeda_drv *mdrv = dev_get_drvdata(dev);
152		152
153	return komeda_dev_suspend(mdrv->mdev);	153	return komeda_dev_suspend(mdrv->mdev);
154	}	154	}
155		155
156	static int komeda_rt_pm_resume(struct device *dev)	156	static int __maybe_unused komeda_rt_pm_resume(struct device *dev)
157	{	157	{
158	struct komeda_drv *mdrv = dev_get_drvdata(dev);	158	struct komeda_drv *mdrv = dev_get_drvdata(dev);
159		159

drivers/gpu/drm/bochs/bochs_hw.c+2−4

 		size = min(size, mem);
 	}
-	if (pci_request_region(pdev, 0, "bochs-drm") != 0) {
+	if (pci_request_region(pdev, 0, "bochs-drm") != 0)
-		DRM_ERROR("Cannot request framebuffer\n");
+		DRM_WARN("Cannot request framebuffer, boot fb still active?\n");
-		return -EBUSY;
-	}
 	bochs->fb_map = ioremap(addr, size);
 	if (bochs->fb_map == NULL) {

drivers/gpu/drm/bridge/analogix/analogix-anx6345.c+1−2

@@ -210,8 +210,7 @@ static int anx6345_dp_link_training(struct anx6345 *anx6345) · 209 unmodified lines
210	if (err)	210	if (err)
211	return err;	211	return err;
212		212
213	dpcd[0] = drm_dp_max_link_rate(anx6345->dpcd);	213	dpcd[0] = dp_bw;
214	dpcd[0] = drm_dp_link_rate_to_bw_code(dpcd[0]);
215	err = regmap_write(anx6345->map[I2C_IDX_DPTX],	214	err = regmap_write(anx6345->map[I2C_IDX_DPTX],
216	SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]);	215	SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]);
217	if (err)	216	if (err)

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c+26−20

 		frame.colorspace = HDMI_COLORSPACE_RGB;
 	/* Set up colorimetry */
-	switch (hdmi->hdmi_data.enc_out_encoding) {
+	if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
-	case V4L2_YCBCR_ENC_601:
+		switch (hdmi->hdmi_data.enc_out_encoding) {
-		if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
+		case V4L2_YCBCR_ENC_601:
-			frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
+			if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
-		else
+				frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
+			else
+				frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
+			frame.extended_colorimetry =
+					HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
+			break;
+		case V4L2_YCBCR_ENC_709:
+			if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
+				frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
+			else
+				frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
+			frame.extended_colorimetry =
+					HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
+			break;
+		default: /* Carries no data */
 			frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
+			frame.extended_colorimetry =
+					HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
+			break;
+		}
+	} else {
+		frame.colorimetry = HDMI_COLORIMETRY_NONE;
 		frame.extended_colorimetry =
-				HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
+			HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
-		break;
-	case V4L2_YCBCR_ENC_709:
-		if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
-			frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
-		else
-			frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
-		frame.extended_colorimetry =
-				HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
-		break;
-	default: /* Carries no data */
-		frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
-		frame.extended_colorimetry =
-				HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
-		break;
 	}
 	frame.scan_mode = HDMI_SCAN_MODE_NONE;

drivers/gpu/drm/drm_dp_mst_topology.c+126−58

@@ -1935,7 +1935,7 @@ static u8 drm_dp_calculate_rad(struct drm_dp_mst_port *port, · 1934 unmodified lines
1935	return parent_lct + 1;	1935	return parent_lct + 1;
1936	}	1936	}
1937		1937
1938	static bool drm_dp_mst_is_dp_mst_end_device(u8 pdt, bool mcs)	1938	static bool drm_dp_mst_is_end_device(u8 pdt, bool mcs)
1939	{	1939	{
1940	switch (pdt) {	1940	switch (pdt) {
1941	case DP_PEER_DEVICE_DP_LEGACY_CONV:	1941	case DP_PEER_DEVICE_DP_LEGACY_CONV:
@@ -1965,13 +1965,13 @@ drm_dp_port_set_pdt(struct drm_dp_mst_port *port, u8 new_pdt, · 23 unmodified lines
1965		1965
1966	/* Teardown the old pdt, if there is one */	1966	/* Teardown the old pdt, if there is one */
1967	if (port->pdt != DP_PEER_DEVICE_NONE) {	1967	if (port->pdt != DP_PEER_DEVICE_NONE) {
1968	if (drm_dp_mst_is_dp_mst_end_device(port->pdt, port->mcs)) {	1968	if (drm_dp_mst_is_end_device(port->pdt, port->mcs)) {
1969	/*	1969	/*
1970	* If the new PDT would also have an i2c bus,	1970	* If the new PDT would also have an i2c bus,
1971	* don't bother with reregistering it	1971	* don't bother with reregistering it
1972	*/	1972	*/
1973	if (new_pdt != DP_PEER_DEVICE_NONE &&	1973	if (new_pdt != DP_PEER_DEVICE_NONE &&
1974	drm_dp_mst_is_dp_mst_end_device(new_pdt, new_mcs)) {	1974	drm_dp_mst_is_end_device(new_pdt, new_mcs)) {
1975	port->pdt = new_pdt;	1975	port->pdt = new_pdt;
1976	port->mcs = new_mcs;	1976	port->mcs = new_mcs;
1977	return 0;	1977	return 0;
@@ -1991,7 +1991,7 @@ drm_dp_port_set_pdt(struct drm_dp_mst_port *port, u8 new_pdt, · 13 unmodified lines
1991	port->mcs = new_mcs;	1991	port->mcs = new_mcs;
1992		1992
1993	if (port->pdt != DP_PEER_DEVICE_NONE) {	1993	if (port->pdt != DP_PEER_DEVICE_NONE) {
1994	if (drm_dp_mst_is_dp_mst_end_device(port->pdt, port->mcs)) {	1994	if (drm_dp_mst_is_end_device(port->pdt, port->mcs)) {
1995	/* add i2c over sideband */	1995	/* add i2c over sideband */
1996	ret = drm_dp_mst_register_i2c_bus(&port->aux);	1996	ret = drm_dp_mst_register_i2c_bus(&port->aux);
1997	} else {	1997	} else {
@@ -2172,7 +2172,7 @@ drm_dp_mst_port_add_connector(struct drm_dp_mst_branch *mstb, · 174 unmodified lines
2172	}	2172	}
2173		2173
2174	if (port->pdt != DP_PEER_DEVICE_NONE &&	2174	if (port->pdt != DP_PEER_DEVICE_NONE &&
2175	drm_dp_mst_is_dp_mst_end_device(port->pdt, port->mcs)) {	2175	drm_dp_mst_is_end_device(port->pdt, port->mcs)) {
2176	port->cached_edid = drm_get_edid(port->connector,	2176	port->cached_edid = drm_get_edid(port->connector,
2177	&port->aux.ddc);	2177	&port->aux.ddc);
2178	drm_connector_set_tile_property(port->connector);	2178	drm_connector_set_tile_property(port->connector);
@@ -2302,14 +2302,18 @@ drm_dp_mst_handle_link_address_port(struct drm_dp_mst_branch *mstb, · 123 unmodified lines
2302	mutex_unlock(&mgr->lock);	2302	mutex_unlock(&mgr->lock);
2303	}	2303	}
2304		2304
2305	if (old_ddps != port->ddps) {	2305	/*
2306	if (port->ddps) {	2306	* Reprobe PBN caps on both hotplug, and when re-probing the link
2307	if (!port->input) {	2307	* for our parent mstb
2308	drm_dp_send_enum_path_resources(mgr, mstb,	2308	*/
2309	port);	2309	if (old_ddps != port->ddps \|\| !created) {
2310	}	2310	if (port->ddps && !port->input) {
		2311	ret = drm_dp_send_enum_path_resources(mgr, mstb,
		2312	port);
		2313	if (ret == 1)
		2314	changed = true;
2311	} else {	2315	} else {
2312	port->available_pbn = 0;	2316	port->full_pbn = 0;
2313	}	2317	}
2314	}	2318	}
2315		2319
@@ -2401,11 +2405,10 @@ drm_dp_mst_handle_conn_stat(struct drm_dp_mst_branch *mstb, · 85 unmodified lines
2401	port->ddps = conn_stat->displayport_device_plug_status;	2405	port->ddps = conn_stat->displayport_device_plug_status;
2402		2406
2403	if (old_ddps != port->ddps) {	2407	if (old_ddps != port->ddps) {
2404	if (port->ddps) {	2408	if (port->ddps && !port->input)
2405	dowork = true;	2409	drm_dp_send_enum_path_resources(mgr, mstb, port);
2406	} else {	2410	else
2407	port->available_pbn = 0;	2411	port->full_pbn = 0;
2408	}
2409	}	2412	}
2410		2413
2411	new_pdt = port->input ? DP_PEER_DEVICE_NONE : conn_stat->peer_device_type;	2414	new_pdt = port->input ? DP_PEER_DEVICE_NONE : conn_stat->peer_device_type;
@@ -2556,13 +2559,6 @@ static int drm_dp_check_and_send_link_address(struct drm_dp_mst_topology_mgr *mg · 144 unmodified lines
2556	if (port->input \|\| !port->ddps)	2559	if (port->input \|\| !port->ddps)
2557	continue;	2560	continue;
2558		2561
2559	if (!port->available_pbn) {
2560	drm_modeset_lock(&mgr->base.lock, NULL);
2561	drm_dp_send_enum_path_resources(mgr, mstb, port);
2562	drm_modeset_unlock(&mgr->base.lock);
2563	changed = true;
2564	}
2565
2566	if (port->mstb)	2562	if (port->mstb)
2567	mstb_child = drm_dp_mst_topology_get_mstb_validated(	2563	mstb_child = drm_dp_mst_topology_get_mstb_validated(
2568	mgr, port->mstb);	2564	mgr, port->mstb);
@@ -2990,6 +2986,7 @@ drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, · 421 unmodified lines
2990		2986
2991	ret = drm_dp_mst_wait_tx_reply(mstb, txmsg);	2987	ret = drm_dp_mst_wait_tx_reply(mstb, txmsg);
2992	if (ret > 0) {	2988	if (ret > 0) {
		2989	ret = 0;
2993	path_res = &txmsg->reply.u.path_resources;	2990	path_res = &txmsg->reply.u.path_resources;
2994		2991
2995	if (txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK) {	2992	if (txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK) {
@@ -3002,14 +2999,22 @@ drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, · 6 unmodified lines
3002	path_res->port_number,	2999	path_res->port_number,
3003	path_res->full_payload_bw_number,	3000	path_res->full_payload_bw_number,
3004	path_res->avail_payload_bw_number);	3001	path_res->avail_payload_bw_number);
3005	port->available_pbn =	3002
3006	path_res->avail_payload_bw_number;	3003	/*
		3004	* If something changed, make sure we send a
		3005	* hotplug
		3006	*/
		3007	if (port->full_pbn != path_res->full_payload_bw_number \|\|
		3008	port->fec_capable != path_res->fec_capable)
		3009	ret = 1;
		3010
		3011	port->full_pbn = path_res->full_payload_bw_number;
3007	port->fec_capable = path_res->fec_capable;	3012	port->fec_capable = path_res->fec_capable;
3008	}	3013	}
3009	}	3014	}
3010		3015
3011	kfree(txmsg);	3016	kfree(txmsg);
3012	return 0;	3017	return ret;
3013	}	3018	}
3014		3019
3015	static struct drm_dp_mst_port drm_dp_get_last_connected_port_to_mstb(struct drm_dp_mst_branch mstb)	3020	static struct drm_dp_mst_port drm_dp_get_last_connected_port_to_mstb(struct drm_dp_mst_branch mstb)
@@ -3596,13 +3601,9 @@ drm_dp_mst_topology_mgr_invalidate_mstb(struct drm_dp_mst_branch *mstb) · 580 unmodified lines
3596	/* The link address will need to be re-sent on resume */	3601	/* The link address will need to be re-sent on resume */
3597	mstb->link_address_sent = false;	3602	mstb->link_address_sent = false;
3598		3603
3599	list_for_each_entry(port, &mstb->ports, next) {	3604	list_for_each_entry(port, &mstb->ports, next)
3600	/* The PBN for each port will also need to be re-probed */
3601	port->available_pbn = 0;
3602
3603	if (port->mstb)	3605	if (port->mstb)
3604	drm_dp_mst_topology_mgr_invalidate_mstb(port->mstb);	3606	drm_dp_mst_topology_mgr_invalidate_mstb(port->mstb);
3605	}
3606	}	3607	}
3607		3608
3608	/**	3609	/**
@@ -4829,41 +4830,102 @@ static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port, · 1220 unmodified lines
4829	return false;	4830	return false;
4830	}	4831	}
4831		4832
4832	static inline	4833	static int
4833	int drm_dp_mst_atomic_check_bw_limit(struct drm_dp_mst_branch *branch,	4834	drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
4834	struct drm_dp_mst_topology_state *mst_state)	4835	struct drm_dp_mst_topology_state *state);
		4836
		4837	static int
		4838	drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
		4839	struct drm_dp_mst_topology_state *state)
4835	{	4840	{
4836	struct drm_dp_mst_port *port;
4837	struct drm_dp_vcpi_allocation *vcpi;	4841	struct drm_dp_vcpi_allocation *vcpi;
4838	int pbn_limit = 0, pbn_used = 0;	4842	struct drm_dp_mst_port *port;
		4843	int pbn_used = 0, ret;
		4844	bool found = false;
4839		4845
4840	list_for_each_entry(port, &branch->ports, next) {	4846	/* Check that we have at least one port in our state that's downstream
4841	if (port->mstb)	4847	* of this branch, otherwise we can skip this branch
4842	if (drm_dp_mst_atomic_check_bw_limit(port->mstb, mst_state))	4848	*/
4843	return -ENOSPC;	4849	list_for_each_entry(vcpi, &state->vcpis, next) {
		4850	if (!vcpi->pbn \|\|
		4851	!drm_dp_mst_port_downstream_of_branch(vcpi->port, mstb))
		4852	continue;
4844		4853
4845	if (port->available_pbn > 0)	4854	found = true;
4846	pbn_limit = port->available_pbn;	4855	break;
4847	}	4856	}
4848	DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch has %d PBN available\n",	4857	if (!found)
4849	branch, pbn_limit);	4858	return 0;
4850		4859
4851	list_for_each_entry(vcpi, &mst_state->vcpis, next) {	4860	if (mstb->port_parent)
4852	if (!vcpi->pbn)	4861	DRM_DEBUG_ATOMIC("[MSTB:%p] [MST PORT:%p] Checking bandwidth limits on [MSTB:%p]\n",
4853	continue;	4862	mstb->port_parent->parent, mstb->port_parent,
		4863	mstb);
		4864	else
		4865	DRM_DEBUG_ATOMIC("[MSTB:%p] Checking bandwidth limits\n",
		4866	mstb);
		4867
		4868	list_for_each_entry(port, &mstb->ports, next) {
		4869	ret = drm_dp_mst_atomic_check_port_bw_limit(port, state);
		4870	if (ret < 0)
		4871	return ret;
4854		4872
4855	if (drm_dp_mst_port_downstream_of_branch(vcpi->port, branch))	4873	pbn_used += ret;
4856	pbn_used += vcpi->pbn;
4857	}	4874	}
4858	DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch used %d PBN\n",
4859	branch, pbn_used);
4860		4875
4861	if (pbn_used > pbn_limit) {	4876	return pbn_used;
4862	DRM_DEBUG_ATOMIC("[MST BRANCH:%p] No available bandwidth\n",	4877	}
4863	branch);	4878
		4879	static int
		4880	drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
		4881	struct drm_dp_mst_topology_state *state)
		4882	{
		4883	struct drm_dp_vcpi_allocation *vcpi;
		4884	int pbn_used = 0;
		4885
		4886	if (port->pdt == DP_PEER_DEVICE_NONE)
		4887	return 0;
		4888
		4889	if (drm_dp_mst_is_end_device(port->pdt, port->mcs)) {
		4890	bool found = false;
		4891
		4892	list_for_each_entry(vcpi, &state->vcpis, next) {
		4893	if (vcpi->port != port)
		4894	continue;
		4895	if (!vcpi->pbn)
		4896	return 0;
		4897
		4898	found = true;
		4899	break;
		4900	}
		4901	if (!found)
		4902	return 0;
		4903
		4904	/* This should never happen, as it means we tried to
		4905	* set a mode before querying the full_pbn
		4906	*/
		4907	if (WARN_ON(!port->full_pbn))
		4908	return -EINVAL;
		4909
		4910	pbn_used = vcpi->pbn;
		4911	} else {
		4912	pbn_used = drm_dp_mst_atomic_check_mstb_bw_limit(port->mstb,
		4913	state);
		4914	if (pbn_used <= 0)
		4915	return pbn_used;
		4916	}
		4917
		4918	if (pbn_used > port->full_pbn) {
		4919	DRM_DEBUG_ATOMIC("[MSTB:%p] [MST PORT:%p] required PBN of %d exceeds port limit of %d\n",
		4920	port->parent, port, pbn_used,
		4921	port->full_pbn);
4864	return -ENOSPC;	4922	return -ENOSPC;
4865	}	4923	}
4866	return 0;	4924
		4925	DRM_DEBUG_ATOMIC("[MSTB:%p] [MST PORT:%p] uses %d out of %d PBN\n",
		4926	port->parent, port, pbn_used, port->full_pbn);
		4927
		4928	return pbn_used;
4867	}	4929	}
4868		4930
4869	static inline int	4931	static inline int
@@ -5061,9 +5123,15 @@ int drm_dp_mst_atomic_check(struct drm_atomic_state *state) · 191 unmodified lines
5061	ret = drm_dp_mst_atomic_check_vcpi_alloc_limit(mgr, mst_state);	5123	ret = drm_dp_mst_atomic_check_vcpi_alloc_limit(mgr, mst_state);
5062	if (ret)	5124	if (ret)
5063	break;	5125	break;
5064	ret = drm_dp_mst_atomic_check_bw_limit(mgr->mst_primary, mst_state);	5126
5065	if (ret)	5127	mutex_lock(&mgr->lock);
		5128	ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
		5129	mst_state);
		5130	mutex_unlock(&mgr->lock);
		5131	if (ret < 0)
5066	break;	5132	break;
		5133	else
		5134	ret = 0;
5067	}	5135	}
5068		5136
5069	return ret;	5137	return ret;

drivers/gpu/drm/drm_gem_shmem_helper.c+11−5

 	if (ret)
 		goto err_zero_use;
-	if (obj->import_attach)
+	if (obj->import_attach) {
 		shmem->vaddr = dma_buf_vmap(obj->import_attach->dmabuf);
-	else
+	} else {
+		pgprot_t prot = PAGE_KERNEL;
+		if (!shmem->map_cached)
+			prot = pgprot_writecombine(prot);
 		shmem->vaddr = vmap(shmem->pages, obj->size >> PAGE_SHIFT,
-				    VM_MAP, pgprot_writecombine(PAGE_KERNEL));
+				    VM_MAP, prot);
+	}
 	if (!shmem->vaddr) {
 		DRM_DEBUG_KMS("Failed to vmap pages\n");
 	}
 	vma->vm_flags |= VM_MIXEDMAP | VM_DONTEXPAND;
-	vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
+	vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
-	vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
+	if (!shmem->map_cached)
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 	vma->vm_ops = &drm_gem_shmem_vm_ops;
 	return 0;

drivers/gpu/drm/drm_lease.c+2−1

 	}
 	DRM_DEBUG_LEASE("Creating lease\n");
+	/* lessee will take the ownership of leases */
 	lessee = drm_lease_create(lessor, &leases);
 	if (IS_ERR(lessee)) {
 		ret = PTR_ERR(lessee);
+		idr_destroy(&leases);
 		goto out_leases;
 	}
 out_leases:
 	put_unused_fd(fd);
-	idr_destroy(&leases);
 	DRM_DEBUG_LEASE("drm_mode_create_lease_ioctl failed: %d\n", ret);
 	return ret;

drivers/gpu/drm/exynos/exynos5433_drm_decon.c+3−2

 struct decon_context {
 	struct device			*dev;
 	struct drm_device		*drm_dev;
+	void				*dma_priv;
 	struct exynos_drm_crtc		*crtc;
 	struct exynos_drm_plane		planes[WINDOWS_NR];
 	struct exynos_drm_plane_config	configs[WINDOWS_NR];
 	decon_clear_channels(ctx->crtc);
-	return exynos_drm_register_dma(drm_dev, dev);
+	return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
 }
 static void decon_unbind(struct device *dev, struct device *master, void *data)
 	decon_atomic_disable(ctx->crtc);
 	/* detach this sub driver from iommu mapping if supported. */
-	exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev);
+	exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
 }
 static const struct component_ops decon_component_ops = {

drivers/gpu/drm/exynos/exynos7_drm_decon.c+3−2

 struct decon_context {
 	struct device			*dev;
 	struct drm_device		*drm_dev;
+	void				*dma_priv;
 	struct exynos_drm_crtc		*crtc;
 	struct exynos_drm_plane		planes[WINDOWS_NR];
 	struct exynos_drm_plane_config	configs[WINDOWS_NR];
 	decon_clear_channels(ctx->crtc);
-	return exynos_drm_register_dma(drm_dev, ctx->dev);
+	return exynos_drm_register_dma(drm_dev, ctx->dev, &ctx->dma_priv);
 }
 static void decon_ctx_remove(struct decon_context *ctx)
 {
 	/* detach this sub driver from iommu mapping if supported. */
-	exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev);
+	exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
 }
 static u32 decon_calc_clkdiv(struct decon_context *ctx,

drivers/gpu/drm/exynos/exynos_drm_dma.c+19−9

  * mapping.
  */
 static int drm_iommu_attach_device(struct drm_device *drm_dev,
-				struct device *subdrv_dev)
+				struct device *subdrv_dev, void **dma_priv)
 {
 	struct exynos_drm_private *priv = drm_dev->dev_private;
 	int ret;
 		return ret;
 	if (IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)) {
-		if (to_dma_iommu_mapping(subdrv_dev))
+		/*
+		 * Keep the original DMA mapping of the sub-device and
+		 * restore it on Exynos DRM detach, otherwise the DMA
+		 * framework considers it as IOMMU-less during the next
+		 * probe (in case of deferred probe or modular build)
+		 */
+		*dma_priv = to_dma_iommu_mapping(subdrv_dev);
+		if (*dma_priv)
 			arm_iommu_detach_device(subdrv_dev);
 		ret = arm_iommu_attach_device(subdrv_dev, priv->mapping);
  * mapping
  */
 static void drm_iommu_detach_device(struct drm_device *drm_dev,
-				struct device *subdrv_dev)
+				    struct device *subdrv_dev, void **dma_priv)
 {
 	struct exynos_drm_private *priv = drm_dev->dev_private;
-	if (IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU))
+	if (IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)) {
 		arm_iommu_detach_device(subdrv_dev);
-	else if (IS_ENABLED(CONFIG_IOMMU_DMA))
+		arm_iommu_attach_device(subdrv_dev, *dma_priv);
+	} else if (IS_ENABLED(CONFIG_IOMMU_DMA))
 		iommu_detach_device(priv->mapping, subdrv_dev);
 	clear_dma_max_seg_size(subdrv_dev);
 }
-int exynos_drm_register_dma(struct drm_device *drm, struct device *dev)
+int exynos_drm_register_dma(struct drm_device *drm, struct device *dev,
+			    void **dma_priv)
 {
 	struct exynos_drm_private *priv = drm->dev_private;
 		priv->mapping = mapping;
 	}
-	return drm_iommu_attach_device(drm, dev);
+	return drm_iommu_attach_device(drm, dev, dma_priv);
 }
-void exynos_drm_unregister_dma(struct drm_device *drm, struct device *dev)
+void exynos_drm_unregister_dma(struct drm_device *drm, struct device *dev,
+			       void **dma_priv)
 {
 	if (IS_ENABLED(CONFIG_EXYNOS_IOMMU))
-		drm_iommu_detach_device(drm, dev);
+		drm_iommu_detach_device(drm, dev, dma_priv);
 }
 void exynos_drm_cleanup_dma(struct drm_device *drm)

drivers/gpu/drm/exynos/exynos_drm_drv.h+4−2

 	return priv->mapping ? true : false;
 }
-int exynos_drm_register_dma(struct drm_device *drm, struct device *dev);
+int exynos_drm_register_dma(struct drm_device *drm, struct device *dev,
-void exynos_drm_unregister_dma(struct drm_device *drm, struct device *dev);
+			    void **dma_priv);
+void exynos_drm_unregister_dma(struct drm_device *drm, struct device *dev,
+			       void **dma_priv);
 void exynos_drm_cleanup_dma(struct drm_device *drm);
 #ifdef CONFIG_DRM_EXYNOS_DPI

drivers/gpu/drm/exynos/exynos_drm_dsi.c+7−5

 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
 				      dsi->supplies);
 	if (ret) {
-		dev_info(dev, "failed to get regulators: %d\n", ret);
+		if (ret != -EPROBE_DEFER)
-		return -EPROBE_DEFER;
+			dev_info(dev, "failed to get regulators: %d\n", ret);
+		return ret;
 	}
 	dsi->clks = devm_kcalloc(dev,
 		dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
 		if (IS_ERR(dsi->clks[i])) {
 			if (strcmp(clk_names[i], "sclk_mipi") == 0) {
-				strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
+				dsi->clks[i] = devm_clk_get(dev,
-				i--;
+							OLD_SCLK_MIPI_CLK_NAME);
-				continue;
+				if (!IS_ERR(dsi->clks[i]))
+					continue;
 			}
 			dev_info(dev, "failed to get the clock: %s\n",

drivers/gpu/drm/exynos/exynos_drm_fimc.c+3−2

 struct fimc_context {
 	struct exynos_drm_ipp ipp;
 	struct drm_device *drm_dev;
+	void		*dma_priv;
 	struct device	*dev;
 	struct exynos_drm_ipp_task	*task;
 	struct exynos_drm_ipp_formats	*formats;
 	ctx->drm_dev = drm_dev;
 	ipp->drm_dev = drm_dev;
-	exynos_drm_register_dma(drm_dev, dev);
+	exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
 	exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
 			DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
 	struct exynos_drm_ipp *ipp = &ctx->ipp;
 	exynos_drm_ipp_unregister(dev, ipp);
-	exynos_drm_unregister_dma(drm_dev, dev);
+	exynos_drm_unregister_dma(drm_dev, dev, &ctx->dma_priv);
 }
 static const struct component_ops fimc_component_ops = {

drivers/gpu/drm/exynos/exynos_drm_fimd.c+3−2

 struct fimd_context {
 	struct device			*dev;
 	struct drm_device		*drm_dev;
+	void				*dma_priv;
 	struct exynos_drm_crtc		*crtc;
 	struct exynos_drm_plane		planes[WINDOWS_NR];
 	struct exynos_drm_plane_config	configs[WINDOWS_NR];
 	if (is_drm_iommu_supported(drm_dev))
 		fimd_clear_channels(ctx->crtc);
-	return exynos_drm_register_dma(drm_dev, dev);
+	return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
 }
 static void fimd_unbind(struct device *dev, struct device *master,
 	fimd_atomic_disable(ctx->crtc);
-	exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev);
+	exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
 	if (ctx->encoder)
 		exynos_dpi_remove(ctx->encoder);

drivers/gpu/drm/exynos/exynos_drm_g2d.c+3−2

 struct g2d_data {
 	struct device			*dev;
+	void				*dma_priv;
 	struct clk			*gate_clk;
 	void __iomem			*regs;
 	int				irq;
 		return ret;
 	}
-	ret = exynos_drm_register_dma(drm_dev, dev);
+	ret = exynos_drm_register_dma(drm_dev, dev, &g2d->dma_priv);
 	if (ret < 0) {
 		dev_err(dev, "failed to enable iommu.\n");
 		g2d_fini_cmdlist(g2d);
 	priv->g2d_dev = NULL;
 	cancel_work_sync(&g2d->runqueue_work);
-	exynos_drm_unregister_dma(g2d->drm_dev, dev);
+	exynos_drm_unregister_dma(g2d->drm_dev, dev, &g2d->dma_priv);
 }
 static const struct component_ops g2d_component_ops = {

drivers/gpu/drm/exynos/exynos_drm_gsc.c+3−2

 struct gsc_context {
 	struct exynos_drm_ipp ipp;
 	struct drm_device *drm_dev;
+	void		*dma_priv;
 	struct device	*dev;
 	struct exynos_drm_ipp_task	*task;
 	struct exynos_drm_ipp_formats	*formats;
 	ctx->drm_dev = drm_dev;
 	ctx->drm_dev = drm_dev;
-	exynos_drm_register_dma(drm_dev, dev);
+	exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
 	exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
 			DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
 	struct exynos_drm_ipp *ipp = &ctx->ipp;
 	exynos_drm_ipp_unregister(dev, ipp);
-	exynos_drm_unregister_dma(drm_dev, dev);
+	exynos_drm_unregister_dma(drm_dev, dev, &ctx->dma_priv);
 }
 static const struct component_ops gsc_component_ops = {

drivers/gpu/drm/exynos/exynos_drm_rotator.c+3−2

 struct rot_context {
 	struct exynos_drm_ipp ipp;
 	struct drm_device *drm_dev;
+	void		*dma_priv;
 	struct device	*dev;
 	void __iomem	*regs;
 	struct clk	*clock;
 	rot->drm_dev = drm_dev;
 	ipp->drm_dev = drm_dev;
-	exynos_drm_register_dma(drm_dev, dev);
+	exynos_drm_register_dma(drm_dev, dev, &rot->dma_priv);
 	exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
 			   DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE,
 	struct exynos_drm_ipp *ipp = &rot->ipp;
 	exynos_drm_ipp_unregister(dev, ipp);
-	exynos_drm_unregister_dma(rot->drm_dev, rot->dev);
+	exynos_drm_unregister_dma(rot->drm_dev, rot->dev, &rot->dma_priv);
 }
 static const struct component_ops rotator_component_ops = {

drivers/gpu/drm/exynos/exynos_drm_scaler.c+4−2

 struct scaler_context {
 	struct exynos_drm_ipp		ipp;
 	struct drm_device		*drm_dev;
+	void				*dma_priv;
 	struct device			*dev;
 	void __iomem			*regs;
 	struct clk			*clock[SCALER_MAX_CLK];
 	scaler->drm_dev = drm_dev;
 	ipp->drm_dev = drm_dev;
-	exynos_drm_register_dma(drm_dev, dev);
+	exynos_drm_register_dma(drm_dev, dev, &scaler->dma_priv);
 	exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
 			DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
 	struct exynos_drm_ipp *ipp = &scaler->ipp;
 	exynos_drm_ipp_unregister(dev, ipp);
-	exynos_drm_unregister_dma(scaler->drm_dev, scaler->dev);
+	exynos_drm_unregister_dma(scaler->drm_dev, scaler->dev,
+				  &scaler->dma_priv);
 }
 static const struct component_ops scaler_component_ops = {

drivers/gpu/drm/exynos/exynos_hdmi.c+12−10

@@ -1805,18 +1805,10 @@ static int hdmi_resources_init(struct hdmi_context *hdata) · 1804 unmodified lines
1805		1805
1806	hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en");	1806	hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en");
1807		1807
1808	if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV) {	1808	if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV)
1809	if (IS_ERR(hdata->reg_hdmi_en))	1809	if (IS_ERR(hdata->reg_hdmi_en))
1810	return PTR_ERR(hdata->reg_hdmi_en);	1810	return PTR_ERR(hdata->reg_hdmi_en);
1811		1811
1812	ret = regulator_enable(hdata->reg_hdmi_en);
1813	if (ret) {
1814	DRM_DEV_ERROR(dev,
1815	"failed to enable hdmi-en regulator\n");
1816	return ret;
1817	}
1818	}
1819
1820	return hdmi_bridge_init(hdata);	1812	return hdmi_bridge_init(hdata);
1821	}	1813	}
1822		1814
@@ -2023,6 +2015,15 @@ static int hdmi_probe(struct platform_device *pdev) · 200 unmodified lines
2023	}	2015	}
2024	}	2016	}
2025		2017
		2018	if (!IS_ERR(hdata->reg_hdmi_en)) {
		2019	ret = regulator_enable(hdata->reg_hdmi_en);
		2020	if (ret) {
		2021	DRM_DEV_ERROR(dev,
		2022	"failed to enable hdmi-en regulator\n");
		2023	goto err_hdmiphy;
		2024	}
		2025	}
		2026
2026	pm_runtime_enable(dev);	2027	pm_runtime_enable(dev);
2027		2028
2028	audio_infoframe = &hdata->audio.infoframe;	2029	audio_infoframe = &hdata->audio.infoframe;
@@ -2047,7 +2048,8 @@ err_unregister_audio: · 18 unmodified lines
2047		2048
2048	err_rpm_disable:	2049	err_rpm_disable:
2049	pm_runtime_disable(dev);	2050	pm_runtime_disable(dev);
2050		2051	if (!IS_ERR(hdata->reg_hdmi_en))
		2052	regulator_disable(hdata->reg_hdmi_en);
2051	err_hdmiphy:	2053	err_hdmiphy:
2052	if (hdata->hdmiphy_port)	2054	if (hdata->hdmiphy_port)
2053	put_device(&hdata->hdmiphy_port->dev);	2055	put_device(&hdata->hdmiphy_port->dev);

drivers/gpu/drm/exynos/exynos_mixer.c+5−2

 	struct platform_device *pdev;
 	struct device		*dev;
 	struct drm_device	*drm_dev;
+	void			*dma_priv;
 	struct exynos_drm_crtc	*crtc;
 	struct exynos_drm_plane	planes[MIXER_WIN_NR];
 	unsigned long		flags;
 		}
 	}
-	return exynos_drm_register_dma(drm_dev, mixer_ctx->dev);
+	return exynos_drm_register_dma(drm_dev, mixer_ctx->dev,
+				       &mixer_ctx->dma_priv);
 }
 static void mixer_ctx_remove(struct mixer_context *mixer_ctx)
 {
-	exynos_drm_unregister_dma(mixer_ctx->drm_dev, mixer_ctx->dev);
+	exynos_drm_unregister_dma(mixer_ctx->drm_dev, mixer_ctx->dev,
+				  &mixer_ctx->dma_priv);
 }
 static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)

drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h+0−1

@@ -83,7 +83,6 @@ · 82 unmodified lines
83	#define VSIZE_OFST 20	83	#define VSIZE_OFST 20
84	#define LDI_INT_EN 0x741C	84	#define LDI_INT_EN 0x741C
85	#define FRAME_END_INT_EN_OFST 1	85	#define FRAME_END_INT_EN_OFST 1
86	#define UNDERFLOW_INT_EN_OFST 2
87	#define LDI_CTRL 0x7420	86	#define LDI_CTRL 0x7420
88	#define BPP_OFST 3	87	#define BPP_OFST 3
89	#define DATA_GATE_EN BIT(2)	88	#define DATA_GATE_EN BIT(2)

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c+0−20

 	struct clk *media_noc_clk;
 	struct clk *ade_pix_clk;
 	struct reset_control *reset;
-	struct work_struct display_reset_wq;
 	bool power_on;
 	int irq;
 	 */
 	ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST,
 			FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND);
-	ade_update_bits(base + LDI_INT_EN, UNDERFLOW_INT_EN_OFST, MASK(1), 1);
 }
 static bool ade_crtc_mode_fixup(struct drm_crtc *crtc,
 			MASK(1), 0);
 }
-static void drm_underflow_wq(struct work_struct *work)
-{
-	struct ade_hw_ctx *ctx = container_of(work, struct ade_hw_ctx,
-					      display_reset_wq);
-	struct drm_device *drm_dev = ctx->crtc->dev;
-	struct drm_atomic_state *state;
-	state = drm_atomic_helper_suspend(drm_dev);
-	drm_atomic_helper_resume(drm_dev, state);
-}
 static irqreturn_t ade_irq_handler(int irq, void *data)
 {
 	struct ade_hw_ctx *ctx = data;
 				MASK(1), 1);
 		drm_crtc_handle_vblank(crtc);
 	}
-	if (status & BIT(UNDERFLOW_INT_EN_OFST)) {
-		ade_update_bits(base + LDI_INT_CLR, UNDERFLOW_INT_EN_OFST,
-				MASK(1), 1);
-		DRM_ERROR("LDI underflow!");
-		schedule_work(&ctx->display_reset_wq);
-	}
 	return IRQ_HANDLED;
 }
 	if (ret)
 		return ERR_PTR(-EIO);
-	INIT_WORK(&ctx->display_reset_wq, drm_underflow_wq);
 	ctx->crtc = crtc;
 	return ctx;

drivers/gpu/drm/i915/Makefile+1−1

@@ -294,7 +294,7 @@ extra-$(CONFIG_DRM_I915_WERROR) += \ · 293 unmodified lines
294	$(shell cd $(srctree)/$(src) && find * -name '*.h')))	294	$(shell cd $(srctree)/$(src) && find * -name '*.h')))
295		295
296	quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@)	296	quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@)
297	cmd_hdrtest = $(CC) $(c_flags) -S -o /dev/null -x c /dev/null -include $<; touch $@	297	cmd_hdrtest = $(CC) $(filter-out $(CFLAGS_GCOV), $(c_flags)) -S -o /dev/null -x c /dev/null -include $<; touch $@
298		298
299	$(obj)/%.hdrtest: $(src)/%.h FORCE	299	$(obj)/%.hdrtest: $(src)/%.h FORCE
300	$(call if_changed_dep,hdrtest)	300	$(call if_changed_dep,hdrtest)

drivers/gpu/drm/i915/display/intel_display_power.c+24−5

 static void icl_mbus_init(struct drm_i915_private *dev_priv)
 {
-	u32 val;
+	u32 mask, val;
-	val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
+	mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
-	      MBUS_ABOX_BT_CREDIT_POOL2(16) |
+		MBUS_ABOX_BT_CREDIT_POOL2_MASK |
-	      MBUS_ABOX_B_CREDIT(1) |
+		MBUS_ABOX_B_CREDIT_MASK |
-	      MBUS_ABOX_BW_CREDIT(1);
+		MBUS_ABOX_BW_CREDIT_MASK;
+	val = I915_READ(MBUS_ABOX_CTL);
+	val &= ~mask;
+	val |= MBUS_ABOX_BT_CREDIT_POOL1(16) |
+		MBUS_ABOX_BT_CREDIT_POOL2(16) |
+		MBUS_ABOX_B_CREDIT(1) |
+		MBUS_ABOX_BW_CREDIT(1);
 	I915_WRITE(MBUS_ABOX_CTL, val);
 }
 		I915_WRITE(BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
 		I915_WRITE(BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
 	} else {
+		u32 val;
 		I915_WRITE(BW_BUDDY1_PAGE_MASK, table[i].page_mask);
 		I915_WRITE(BW_BUDDY2_PAGE_MASK, table[i].page_mask);
+		/* Wa_22010178259:tgl */
+		val = I915_READ(BW_BUDDY1_CTL);
+		val &= ~BW_BUDDY_TLB_REQ_TIMER_MASK;
+		val |= REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8);
+		I915_WRITE(BW_BUDDY1_CTL, val);
+		val = I915_READ(BW_BUDDY2_CTL);
+		val &= ~BW_BUDDY_TLB_REQ_TIMER_MASK;
+		val |= REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8);
+		I915_WRITE(BW_BUDDY2_CTL, val);
 	}
 }

drivers/gpu/drm/i915/display/intel_psr.c+21−4

 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	if (!crtc_state->has_psr)
+	if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp)
 		return;
-	if (WARN_ON(!CAN_PSR(dev_priv)))
+	dev_priv->psr.force_mode_changed = false;
+	if (!crtc_state->has_psr)
 		return;
 	WARN_ON(dev_priv->drrs.dp);
 	if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp)
 		return;
+	dev_priv->psr.force_mode_changed = false;
 	mutex_lock(&dev_priv->psr.lock);
 	enable = crtc_state->has_psr && psr_global_enabled(psr->debug);
 	struct drm_crtc_state *crtc_state;
 	if (!CAN_PSR(dev_priv) || !new_state->crtc ||
-	    dev_priv->psr.initially_probed)
+	    !dev_priv->psr.force_mode_changed)
 		return;
 	intel_connector = to_intel_connector(connector);
 	crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
 						   new_state->crtc);
 	crtc_state->mode_changed = true;
-	dev_priv->psr.initially_probed = true;
+}
+void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv;
+	if (!intel_dp)
+		return;
+	dev_priv = dp_to_i915(intel_dp);
+	if (!CAN_PSR(dev_priv) || intel_dp != dev_priv->psr.dp)
+		return;
+	dev_priv->psr.force_mode_changed = true;
 }

drivers/gpu/drm/i915/display/intel_psr.h+1−0

@@ -40,5 +40,6 @@ bool intel_psr_enabled(struct intel_dp *intel_dp); · 39 unmodified lines
40	void intel_psr_atomic_check(struct drm_connector *connector,	40	void intel_psr_atomic_check(struct drm_connector *connector,
41	struct drm_connector_state *old_state,	41	struct drm_connector_state *old_state,
42	struct drm_connector_state *new_state);	42	struct drm_connector_state *new_state);
		43	void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp);
43		44
44	#endif /* __INTEL_PSR_H__ */	45	#endif /* __INTEL_PSR_H__ */

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c+2−1

@@ -423,7 +423,8 @@ eb_validate_vma(struct i915_execbuffer *eb, · 422 unmodified lines
423	if (unlikely(entry->flags & eb->invalid_flags))	423	if (unlikely(entry->flags & eb->invalid_flags))
424	return -EINVAL;	424	return -EINVAL;
425		425
426	if (unlikely(entry->alignment && !is_power_of_2(entry->alignment)))	426	if (unlikely(entry->alignment &&
		427	!is_power_of_2_u64(entry->alignment)))
427	return -EINVAL;	428	return -EINVAL;
428		429
429	/*	430	/*

drivers/gpu/drm/i915/gem/i915_gem_object.c+1−0

@@ -225,6 +225,7 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915, · 224 unmodified lines
225		225
226	/* But keep the pointer alive for RCU-protected lookups */	226	/* But keep the pointer alive for RCU-protected lookups */
227	call_rcu(&obj->rcu, __i915_gem_free_object_rcu);	227	call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
		228	cond_resched();
228	}	229	}
229	intel_runtime_pm_put(&i915->runtime_pm, wakeref);	230	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
230	}	231	}

drivers/gpu/drm/i915/gem/i915_gem_shrinker.c+1−3

 	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
 		freed = i915_gem_shrink(i915, -1UL, NULL,
 					I915_SHRINK_BOUND |
-					I915_SHRINK_UNBOUND |
+					I915_SHRINK_UNBOUND);
-					I915_SHRINK_ACTIVE);
 	}
 	return freed;
 	freed_pages = 0;
 	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
 		freed_pages += i915_gem_shrink(i915, -1UL, NULL,
-					       I915_SHRINK_ACTIVE |
 					       I915_SHRINK_BOUND |
 					       I915_SHRINK_UNBOUND |
 					       I915_SHRINK_WRITEBACK);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c+1−1

@@ -570,7 +570,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915, · 569 unmodified lines
570		570
571	obj = i915_gem_object_create_internal(i915, size);	571	obj = i915_gem_object_create_internal(i915, size);
572	if (IS_ERR(obj))	572	if (IS_ERR(obj))
573	return PTR_ERR(obj);	573	return false;
574		574
575	mmo = mmap_offset_attach(obj, I915_MMAP_OFFSET_GTT, NULL);	575	mmo = mmap_offset_attach(obj, I915_MMAP_OFFSET_GTT, NULL);
576	i915_gem_object_put(obj);	576	i915_gem_object_put(obj);

drivers/gpu/drm/i915/gt/intel_gt_requests.c+11−3

 			fence = i915_active_fence_get(&tl->last_request);
 			if (fence) {
+				mutex_unlock(&tl->mutex);
 				timeout = dma_fence_wait_timeout(fence,
 								 interruptible,
 								 timeout);
 				dma_fence_put(fence);
+				/* Retirement is best effort */
+				if (!mutex_trylock(&tl->mutex)) {
+					active_count++;
+					goto out_active;
+				}
 			}
 		}
 		if (!retire_requests(tl) || flush_submission(gt))
 			active_count++;
+		mutex_unlock(&tl->mutex);
-		spin_lock(&timelines->lock);
+out_active:	spin_lock(&timelines->lock);
-		/* Resume iteration after dropping lock */
+		/* Resume list iteration after reacquiring spinlock */
 		list_safe_reset_next(tl, tn, link);
 		if (atomic_dec_and_test(&tl->active_count))
 			list_del(&tl->link);
-		mutex_unlock(&tl->mutex);
 		/* Defer the final release to after the spinlock */
 		if (refcount_dec_and_test(&tl->kref.refcount)) {

drivers/gpu/drm/i915/gt/intel_lrc.c+30−51

@@ -1600,17 +1600,6 @@ static void virtual_xfer_breadcrumbs(struct virtual_engine *ve, · 1599 unmodified lines
1600	spin_unlock(&old->breadcrumbs.irq_lock);	1600	spin_unlock(&old->breadcrumbs.irq_lock);
1601	}	1601	}
1602		1602
1603	static struct i915_request *
1604	last_active(const struct intel_engine_execlists *execlists)
1605	{
1606	struct i915_request * const *last = READ_ONCE(execlists->active);
1607
1608	while (last && i915_request_completed(last))
1609	last++;
1610
1611	return *last;
1612	}
1613
1614	#define for_each_waiter(p__, rq__) \	1603	#define for_each_waiter(p__, rq__) \
1615	list_for_each_entry_lockless(p__, \	1604	list_for_each_entry_lockless(p__, \
1616	&(rq__)->sched.waiters_list, \	1605	&(rq__)->sched.waiters_list, \
@@ -1679,11 +1668,9 @@ need_timeslice(struct intel_engine_cs engine, const struct i915_request rq) · 62 unmodified lines
1679	if (!intel_engine_has_timeslices(engine))	1668	if (!intel_engine_has_timeslices(engine))
1680	return false;	1669	return false;
1681		1670
1682	if (list_is_last(&rq->sched.link, &engine->active.requests))	1671	hint = engine->execlists.queue_priority_hint;
1683	return false;	1672	if (!list_is_last(&rq->sched.link, &engine->active.requests))
1684		1673	hint = max(hint, rq_prio(list_next_entry(rq, sched.link)));
1685	hint = max(rq_prio(list_next_entry(rq, sched.link)),
1686	engine->execlists.queue_priority_hint);
1687		1674
1688	return hint >= effective_prio(rq);	1675	return hint >= effective_prio(rq);
1689	}	1676	}
@@ -1725,16 +1712,26 @@ static void set_timeslice(struct intel_engine_cs *engine) · 35 unmodified lines
1725	set_timer_ms(&engine->execlists.timer, active_timeslice(engine));	1712	set_timer_ms(&engine->execlists.timer, active_timeslice(engine));
1726	}	1713	}
1727		1714
		1715	static void start_timeslice(struct intel_engine_cs *engine)
		1716	{
		1717	struct intel_engine_execlists *execlists = &engine->execlists;
		1718
		1719	execlists->switch_priority_hint = execlists->queue_priority_hint;
		1720
		1721	if (timer_pending(&execlists->timer))
		1722	return;
		1723
		1724	set_timer_ms(&execlists->timer, timeslice(engine));
		1725	}
		1726
1728	static void record_preemption(struct intel_engine_execlists *execlists)	1727	static void record_preemption(struct intel_engine_execlists *execlists)
1729	{	1728	{
1730	(void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);	1729	(void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
1731	}	1730	}
1732		1731
1733	static unsigned long active_preempt_timeout(struct intel_engine_cs *engine)	1732	static unsigned long active_preempt_timeout(struct intel_engine_cs *engine,
		1733	const struct i915_request *rq)
1734	{	1734	{
1735	struct i915_request *rq;
1736
1737	rq = last_active(&engine->execlists);
1738	if (!rq)	1735	if (!rq)
1739	return 0;	1736	return 0;
1740		1737
@@ -1745,13 +1742,14 @@ static unsigned long active_preempt_timeout(struct intel_engine_cs *engine) · 4 unmodified lines
1745	return READ_ONCE(engine->props.preempt_timeout_ms);	1742	return READ_ONCE(engine->props.preempt_timeout_ms);
1746	}	1743	}
1747		1744
1748	static void set_preempt_timeout(struct intel_engine_cs *engine)	1745	static void set_preempt_timeout(struct intel_engine_cs *engine,
		1746	const struct i915_request *rq)
1749	{	1747	{
1750	if (!intel_engine_has_preempt_reset(engine))	1748	if (!intel_engine_has_preempt_reset(engine))
1751	return;	1749	return;
1752		1750
1753	set_timer_ms(&engine->execlists.preempt,	1751	set_timer_ms(&engine->execlists.preempt,
1754	active_preempt_timeout(engine));	1752	active_preempt_timeout(engine, rq));
1755	}	1753	}
1756		1754
1757	static inline void clear_ports(struct i915_request **ports, int count)	1755	static inline void clear_ports(struct i915_request **ports, int count)
@@ -1764,6 +1762,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) · 6 unmodified lines
1764	struct intel_engine_execlists * const execlists = &engine->execlists;	1762	struct intel_engine_execlists * const execlists = &engine->execlists;
1765	struct i915_request **port = execlists->pending;	1763	struct i915_request **port = execlists->pending;
1766	struct i915_request ** const last_port = port + execlists->port_mask;	1764	struct i915_request ** const last_port = port + execlists->port_mask;
		1765	struct i915_request * const *active;
1767	struct i915_request *last;	1766	struct i915_request *last;
1768	struct rb_node *rb;	1767	struct rb_node *rb;
1769	bool submit = false;	1768	bool submit = false;
@@ -1818,7 +1817,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine) · 48 unmodified lines
1818	* i.e. we will retrigger preemption following the ack in case	1817	* i.e. we will retrigger preemption following the ack in case
1819	* of trouble.	1818	* of trouble.
1820	*/	1819	*/
1821	last = last_active(execlists);	1820	active = READ_ONCE(execlists->active);
		1821	while ((last = *active) && i915_request_completed(last))
		1822	active++;
		1823
1822	if (last) {	1824	if (last) {
1823	if (need_preempt(engine, last, rb)) {	1825	if (need_preempt(engine, last, rb)) {
1824	ENGINE_TRACE(engine,	1826	ENGINE_TRACE(engine,
@@ -1888,11 +1890,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) · 63 unmodified lines
1888	* Even if ELSP[1] is occupied and not worthy	1890	* Even if ELSP[1] is occupied and not worthy
1889	* of timeslices, our queue might be.	1891	* of timeslices, our queue might be.
1890	*/	1892	*/
1891	if (!execlists->timer.expires &&	1893	start_timeslice(engine);
1892	need_timeslice(engine, last))
1893	set_timer_ms(&execlists->timer,
1894	timeslice(engine));
1895
1896	return;	1894	return;
1897	}	1895	}
1898	}	1896	}
@@ -1927,7 +1925,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) · 28 unmodified lines
1927		1925
1928	if (last && !can_merge_rq(last, rq)) {	1926	if (last && !can_merge_rq(last, rq)) {
1929	spin_unlock(&ve->base.active.lock);	1927	spin_unlock(&ve->base.active.lock);
1930	return; /* leave this for another */	1928	start_timeslice(engine);
		1929	return; /* leave this for another sibling */
1931	}	1930	}
1932		1931
1933	ENGINE_TRACE(engine,	1932	ENGINE_TRACE(engine,
@@ -2103,7 +2102,7 @@ done: · 169 unmodified lines
2103	* Skip if we ended up with exactly the same set of requests,	2102	* Skip if we ended up with exactly the same set of requests,
2104	* e.g. trying to timeslice a pair of ordered contexts	2103	* e.g. trying to timeslice a pair of ordered contexts
2105	*/	2104	*/
2106	if (!memcmp(execlists->active, execlists->pending,	2105	if (!memcmp(active, execlists->pending,
2107	(port - execlists->pending + 1) * sizeof(*port))) {	2106	(port - execlists->pending + 1) * sizeof(*port))) {
2108	do	2107	do
2109	execlists_schedule_out(fetch_and_zero(port));	2108	execlists_schedule_out(fetch_and_zero(port));
@@ -2114,7 +2113,7 @@ done: · 4 unmodified lines
2114	clear_ports(port + 1, last_port - port);	2113	clear_ports(port + 1, last_port - port);
2115		2114
2116	execlists_submit_ports(engine);	2115	execlists_submit_ports(engine);
2117	set_preempt_timeout(engine);	2116	set_preempt_timeout(engine, *active);
2118	} else {	2117	} else {
2119	skip_submit:	2118	skip_submit:
2120	ring_set_paused(engine, 0);	2119	ring_set_paused(engine, 0);
@@ -4001,26 +4000,6 @@ static int gen12_emit_flush_render(struct i915_request *request, · 1880 unmodified lines
4001		4000
4002	*cs++ = preparser_disable(false);	4001	*cs++ = preparser_disable(false);
4003	intel_ring_advance(request, cs);	4002	intel_ring_advance(request, cs);
4004
4005	/*
4006	* Wa_1604544889:tgl
4007	*/
4008	if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) {
4009	flags = 0;
4010	flags \|= PIPE_CONTROL_CS_STALL;
4011	flags \|= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
4012
4013	flags \|= PIPE_CONTROL_STORE_DATA_INDEX;
4014	flags \|= PIPE_CONTROL_QW_WRITE;
4015
4016	cs = intel_ring_begin(request, 6);
4017	if (IS_ERR(cs))
4018	return PTR_ERR(cs);
4019
4020	cs = gen8_emit_pipe_control(cs, flags,
4021	LRC_PPHWSP_SCRATCH_ADDR);
4022	intel_ring_advance(request, cs);
4023	}
4024	}	4003	}
4025		4004
4026	return 0;	4005	return 0;

drivers/gpu/drm/i915/gt/intel_timeline.c+6−2

 static void cacheline_free(struct intel_timeline_cacheline *cl)
 {
+	if (!i915_active_acquire_if_busy(&cl->active)) {
+		__idle_cacheline_free(cl);
+		return;
+	}
 	GEM_BUG_ON(ptr_test_bit(cl->vaddr, CACHELINE_FREE));
 	cl->vaddr = ptr_set_bit(cl->vaddr, CACHELINE_FREE);
-	if (i915_active_is_idle(&cl->active))
+	i915_active_release(&cl->active);
-		__idle_cacheline_free(cl);
 }
 int intel_timeline_init(struct intel_timeline *timeline,

drivers/gpu/drm/i915/gt/intel_workarounds.c+29−15

 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
-	u32 val;
 	/* Wa_1409142259:tgl */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
-	/* Wa_1604555607:tgl */
-	val = intel_uncore_read(engine->uncore, FF_MODE2);
-	val &= ~FF_MODE2_TDS_TIMER_MASK;
-	val |= FF_MODE2_TDS_TIMER_128;
 	/*
-	 * FIXME: FF_MODE2 register is not readable till TGL B0. We can
+	 * Wa_1604555607:gen12 and Wa_1608008084:gen12
-	 * enable verification of WA from the later steppings, which enables
+	 * FF_MODE2 register will return the wrong value when read. The default
-	 * the read of FF_MODE2.
+	 * value for this register is zero for all fields and there are no bit
+	 * masks. So instead of doing a RMW we should just write the TDS timer
+	 * value for Wa_1604555607.
 	 */
-	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
+	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
-	       IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
+	       FF_MODE2_TDS_TIMER_128, 0);
-			    FF_MODE2_TDS_TIMER_MASK);
 }
 static void
 	return ERR_PTR(err);
 }
+static const struct {
+	u32 start;
+	u32 end;
+} mcr_ranges_gen8[] = {
+	{ .start = 0x5500, .end = 0x55ff },
+	{ .start = 0x7000, .end = 0x7fff },
+	{ .start = 0x9400, .end = 0x97ff },
+	{ .start = 0xb000, .end = 0xb3ff },
+	{ .start = 0xe000, .end = 0xe7ff },
+	{},
+};
 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
 {
+	int i;
+	if (INTEL_GEN(i915) < 8)
+		return false;
 	/*
-	 * Registers in this range are affected by the MCR selector
+	 * Registers in these ranges are affected by the MCR selector
 	 * which only controls CPU initiated MMIO. Routing does not
 	 * work for CS access so we cannot verify them on this path.
 	 */
-	if (INTEL_GEN(i915) >= 8 && (offset >= 0xb000 && offset <= 0xb4ff))
+	for (i = 0; mcr_ranges_gen8[i].start; i++)
-		return true;
+		if (offset >= mcr_ranges_gen8[i].start &&
+		    offset <= mcr_ranges_gen8[i].end)
+			return true;
 	return false;
 }

drivers/gpu/drm/i915/gvt/display.c+2−1

@@ -457,7 +457,8 @@ void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) · 456 unmodified lines
457	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;	457	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
458		458
459	/* TODO: add more platforms support */	459	/* TODO: add more platforms support */
460	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv)) {	460	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv) \|\|
		461	IS_COFFEELAKE(dev_priv)) {
461	if (connected) {	462	if (connected) {
462	vgpu_vreg_t(vgpu, SFUSE_STRAP) \|=	463	vgpu_vreg_t(vgpu, SFUSE_STRAP) \|=
463	SFUSE_STRAP_DDID_DETECTED;	464	SFUSE_STRAP_DDID_DETECTED;

drivers/gpu/drm/i915/gvt/dmabuf.c+1−1

 			dmabuf_obj = container_of(pos,
 					struct intel_vgpu_dmabuf_obj, list);
 			if (dmabuf_obj == obj) {
+				list_del(pos);
 				intel_gvt_hypervisor_put_vfio_device(vgpu);
 				idr_remove(&vgpu->object_idr,
 					   dmabuf_obj->dmabuf_id);
 				kfree(dmabuf_obj->info);
 				kfree(dmabuf_obj);
-				list_del(pos);
 				break;
 			}
 		}

drivers/gpu/drm/i915/gvt/opregion.c+2−3

 	/* there's features depending on version! */
 	v->header.version = 155;
 	v->header.header_size = sizeof(v->header);
-	v->header.vbt_size = sizeof(struct vbt) - sizeof(v->header);
+	v->header.vbt_size = sizeof(struct vbt);
 	v->header.bdb_offset = offsetof(struct vbt, bdb_header);
 	strcpy(&v->bdb_header.signature[0], "BIOS_DATA_BLOCK");
 	v->bdb_header.version = 186; /* child_dev_size = 33 */
 	v->bdb_header.header_size = sizeof(v->bdb_header);
-	v->bdb_header.bdb_size = sizeof(struct vbt) - sizeof(struct vbt_header)
+	v->bdb_header.bdb_size = sizeof(struct vbt) - sizeof(struct vbt_header);
-		- sizeof(struct bdb_header);
 	/* general features */
 	v->general_features_header.id = BDB_GENERAL_FEATURES;

drivers/gpu/drm/i915/gvt/vgpu.c+10−4

 {
 	struct intel_gvt *gvt = vgpu->gvt;
-	mutex_lock(&vgpu->vgpu_lock);
 	WARN(vgpu->active, "vGPU is still active!\n");
+	/*
+	 * remove idr first so later clean can judge if need to stop
+	 * service if no active vgpu.
+	 */
+	mutex_lock(&gvt->lock);
+	idr_remove(&gvt->vgpu_idr, vgpu->id);
+	mutex_unlock(&gvt->lock);
+	mutex_lock(&vgpu->vgpu_lock);
 	intel_gvt_debugfs_remove_vgpu(vgpu);
 	intel_vgpu_clean_sched_policy(vgpu);
 	intel_vgpu_clean_submission(vgpu);
 	mutex_unlock(&vgpu->vgpu_lock);
 	mutex_lock(&gvt->lock);
-	idr_remove(&gvt->vgpu_idr, vgpu->id);
 	if (idr_is_empty(&gvt->vgpu_idr))
 		intel_gvt_clean_irq(gvt);
 	intel_gvt_update_vgpu_types(gvt);
 		intel_vgpu_reset_mmio(vgpu, dmlr);
 		populate_pvinfo_page(vgpu);
-		intel_vgpu_reset_display(vgpu);
 		if (dmlr) {
+			intel_vgpu_reset_display(vgpu);
 			intel_vgpu_reset_cfg_space(vgpu);
 			/* only reset the failsafe mode when dmlr reset */
 			vgpu->failsafe = false;

drivers/gpu/drm/i915/i915_drv.c+3−0

 #include "display/intel_hotplug.h"
 #include "display/intel_overlay.h"
 #include "display/intel_pipe_crc.h"
+#include "display/intel_psr.h"
 #include "display/intel_sprite.h"
 #include "display/intel_vga.h"
 	intel_init_ipc(i915);
+	intel_psr_set_force_mode_changed(i915->psr.dp);
 	return 0;
 cleanup_gem:

drivers/gpu/drm/i915/i915_drv.h+1−1

@@ -505,7 +505,7 @@ struct i915_psr { · 504 unmodified lines
505	bool dc3co_enabled;	505	bool dc3co_enabled;
506	u32 dc3co_exit_delay;	506	u32 dc3co_exit_delay;
507	struct delayed_work idle_work;	507	struct delayed_work idle_work;
508	bool initially_probed;	508	bool force_mode_changed;
509	};	509	};
510		510
511	#define QUIRK_LVDS_SSC_DISABLE (1<<1)	511	#define QUIRK_LVDS_SSC_DISABLE (1<<1)

drivers/gpu/drm/i915/i915_pci.c+2−2

@@ -437,7 +437,7 @@ static const struct intel_device_info snb_m_gt2_info = { · 436 unmodified lines
437	.has_rc6 = 1, \	437	.has_rc6 = 1, \
438	.has_rc6p = 1, \	438	.has_rc6p = 1, \
439	.has_rps = true, \	439	.has_rps = true, \
440	.ppgtt_type = INTEL_PPGTT_FULL, \	440	.ppgtt_type = INTEL_PPGTT_ALIASING, \
441	.ppgtt_size = 31, \	441	.ppgtt_size = 31, \
442	IVB_PIPE_OFFSETS, \	442	IVB_PIPE_OFFSETS, \
443	IVB_CURSOR_OFFSETS, \	443	IVB_CURSOR_OFFSETS, \
@@ -494,7 +494,7 @@ static const struct intel_device_info vlv_info = { · 50 unmodified lines
494	.has_rps = true,	494	.has_rps = true,
495	.display.has_gmch = 1,	495	.display.has_gmch = 1,
496	.display.has_hotplug = 1,	496	.display.has_hotplug = 1,
497	.ppgtt_type = INTEL_PPGTT_FULL,	497	.ppgtt_type = INTEL_PPGTT_ALIASING,
498	.ppgtt_size = 31,	498	.ppgtt_size = 31,
499	.has_snoop = true,	499	.has_snoop = true,
500	.has_coherent_ggtt = false,	500	.has_coherent_ggtt = false,

drivers/gpu/drm/i915/i915_perf.c+41−17

 	return i915_vma_get(oa_bo->vma);
 }
-static int emit_oa_config(struct i915_perf_stream *stream,
+static struct i915_request *
-			  struct i915_oa_config *oa_config,
+emit_oa_config(struct i915_perf_stream *stream,
-			  struct intel_context *ce)
+	       struct i915_oa_config *oa_config,
+	       struct intel_context *ce)
 {
 	struct i915_request *rq;
 	struct i915_vma *vma;
 	vma = get_oa_vma(stream, oa_config);
 	if (IS_ERR(vma))
-		return PTR_ERR(vma);
+		return ERR_CAST(vma);
 	err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
 	if (err)
 	err = rq->engine->emit_bb_start(rq,
 					vma->node.start, 0,
 					I915_DISPATCH_SECURE);
+	if (err)
+		goto err_add_request;
+	i915_request_get(rq);
 err_add_request:
 	i915_request_add(rq);
 err_vma_unpin:
 	i915_vma_unpin(vma);
 err_vma_put:
 	i915_vma_put(vma);
-	return err;
+	return err ? ERR_PTR(err) : rq;
 }
 static struct intel_context *oa_context(struct i915_perf_stream *stream)
 	return stream->pinned_ctx ?: stream->engine->kernel_context;
 }
-static int hsw_enable_metric_set(struct i915_perf_stream *stream)
+static struct i915_request *
+hsw_enable_metric_set(struct i915_perf_stream *stream)
 {
 	struct intel_uncore *uncore = stream->uncore;
 	return oa_configure_all_contexts(stream, regs, ARRAY_SIZE(regs));
 }
-static int gen8_enable_metric_set(struct i915_perf_stream *stream)
+static struct i915_request *
+gen8_enable_metric_set(struct i915_perf_stream *stream)
 {
 	struct intel_uncore *uncore = stream->uncore;
 	struct i915_oa_config *oa_config = stream->oa_config;
 	 */
 	ret = lrc_configure_all_contexts(stream, oa_config);
 	if (ret)
-		return ret;
+		return ERR_PTR(ret);
 	return emit_oa_config(stream, oa_config, oa_context(stream));
 }
 			     0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
 }
-static int gen12_enable_metric_set(struct i915_perf_stream *stream)
+static struct i915_request *
+gen12_enable_metric_set(struct i915_perf_stream *stream)
 {
 	struct intel_uncore *uncore = stream->uncore;
 	struct i915_oa_config *oa_config = stream->oa_config;
 	 */
 	ret = gen12_configure_all_contexts(stream, oa_config);
 	if (ret)
-		return ret;
+		return ERR_PTR(ret);
 	/*
 	 * For Gen12, performance counters are context
 	if (stream->ctx) {
 		ret = gen12_configure_oar_context(stream, true);
 		if (ret)
-			return ret;
+			return ERR_PTR(ret);
 	}
 	return emit_oa_config(stream, oa_config, oa_context(stream));
 	.read = i915_oa_read,
 };
+static int i915_perf_stream_enable_sync(struct i915_perf_stream *stream)
+{
+	struct i915_request *rq;
+	rq = stream->perf->ops.enable_metric_set(stream);
+	if (IS_ERR(rq))
+		return PTR_ERR(rq);
+	i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
+	i915_request_put(rq);
+	return 0;
+}
 /**
  * i915_oa_stream_init - validate combined props for OA stream and init
  * @stream: An i915 perf stream
 	stream->ops = &i915_oa_stream_ops;
 	perf->exclusive_stream = stream;
-	ret = perf->ops.enable_metric_set(stream);
+	ret = i915_perf_stream_enable_sync(stream);
 	if (ret) {
 		DRM_DEBUG("Unable to enable metric set\n");
 		goto err_enable;
 		return -EINVAL;
 	if (config != stream->oa_config) {
-		int err;
+		struct i915_request *rq;
 		/*
 		 * If OA is bound to a specific context, emit the
 		 * When set globally, we use a low priority kernel context,
 		 * so it will effectively take effect when idle.
 		 */
-		err = emit_oa_config(stream, config, oa_context(stream));
+		rq = emit_oa_config(stream, config, oa_context(stream));
-		if (err == 0)
+		if (!IS_ERR(rq)) {
 			config = xchg(&stream->oa_config, config);
-		else
+			i915_request_put(rq);
-			ret = err;
+		} else {
+			ret = PTR_ERR(rq);
+		}
 	}
 	i915_oa_config_put(config);

drivers/gpu/drm/i915/i915_perf_types.h+2−1

@@ -339,7 +339,8 @@ struct i915_oa_ops { · 338 unmodified lines
339	* counter reports being sampled. May apply system constraints such as	339	* counter reports being sampled. May apply system constraints such as
340	* disabling EU clock gating as required.	340	* disabling EU clock gating as required.
341	*/	341	*/
342	int (enable_metric_set)(struct i915_perf_stream stream);	342	struct i915_request *
		343	(enable_metric_set)(struct i915_perf_stream stream);
343		344
344	/**	345	/**
345	* @disable_metric_set: Remove system constraints associated with using	346	* @disable_metric_set: Remove system constraints associated with using

drivers/gpu/drm/i915/i915_pmu.c+31−28

 	return sprintf(buf, "config=0x%lx\n", eattr->val);
 }
-static struct attribute_group i915_pmu_events_attr_group = {
-	.name = "events",
-	/* Patch in attrs at runtime. */
-};
 static ssize_t
 i915_pmu_get_attr_cpumask(struct device *dev,
 			  struct device_attribute *attr,
 	.attrs = i915_cpumask_attrs,
 };
-static const struct attribute_group *i915_pmu_attr_groups[] = {
-	&i915_pmu_format_attr_group,
-	&i915_pmu_events_attr_group,
-	&i915_pmu_cpumask_attr_group,
-	NULL
-};
 #define __event(__config, __name, __unit) \
 { \
 	.config = (__config), \
 static void free_event_attributes(struct i915_pmu *pmu)
 {
-	struct attribute **attr_iter = i915_pmu_events_attr_group.attrs;
+	struct attribute **attr_iter = pmu->events_attr_group.attrs;
 	for (; *attr_iter; attr_iter++)
 		kfree((*attr_iter)->name);
-	kfree(i915_pmu_events_attr_group.attrs);
+	kfree(pmu->events_attr_group.attrs);
 	kfree(pmu->i915_attr);
 	kfree(pmu->pmu_attr);
-	i915_pmu_events_attr_group.attrs = NULL;
+	pmu->events_attr_group.attrs = NULL;
 	pmu->i915_attr = NULL;
 	pmu->pmu_attr = NULL;
 }
 static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
 {
-	struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node);
+	struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
 	GEM_BUG_ON(!pmu->base.event_init);
 static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
 {
-	struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node);
+	struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
 	unsigned int target;
 	GEM_BUG_ON(!pmu->base.event_init);
 	return 0;
 }
-static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
 static int i915_pmu_register_cpuhp_state(struct i915_pmu *pmu)
 {
 	enum cpuhp_state slot;
 		return ret;
 	slot = ret;
-	ret = cpuhp_state_add_instance(slot, &pmu->node);
+	ret = cpuhp_state_add_instance(slot, &pmu->cpuhp.node);
 	if (ret) {
 		cpuhp_remove_multi_state(slot);
 		return ret;
 	}
-	cpuhp_slot = slot;
+	pmu->cpuhp.slot = slot;
 	return 0;
 }
 static void i915_pmu_unregister_cpuhp_state(struct i915_pmu *pmu)
 {
-	WARN_ON(cpuhp_slot == CPUHP_INVALID);
+	WARN_ON(pmu->cpuhp.slot == CPUHP_INVALID);
-	WARN_ON(cpuhp_state_remove_instance(cpuhp_slot, &pmu->node));
+	WARN_ON(cpuhp_state_remove_instance(pmu->cpuhp.slot, &pmu->cpuhp.node));
-	cpuhp_remove_multi_state(cpuhp_slot);
+	cpuhp_remove_multi_state(pmu->cpuhp.slot);
+	pmu->cpuhp.slot = CPUHP_INVALID;
 }
 static bool is_igp(struct drm_i915_private *i915)
 void i915_pmu_register(struct drm_i915_private *i915)
 {
 	struct i915_pmu *pmu = &i915->pmu;
+	const struct attribute_group *attr_groups[] = {
+		&i915_pmu_format_attr_group,
+		&pmu->events_attr_group,
+		&i915_pmu_cpumask_attr_group,
+		NULL
+	};
 	int ret = -ENOMEM;
 	if (INTEL_GEN(i915) <= 2) {
 	spin_lock_init(&pmu->lock);
 	hrtimer_init(&pmu->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 	pmu->timer.function = i915_sample;
+	pmu->cpuhp.slot = CPUHP_INVALID;
 	if (!is_igp(i915)) {
 		pmu->name = kasprintf(GFP_KERNEL,
 	if (!pmu->name)
 		goto err;
-	i915_pmu_events_attr_group.attrs = create_event_attributes(pmu);
+	pmu->events_attr_group.name = "events";
-	if (!i915_pmu_events_attr_group.attrs)
+	pmu->events_attr_group.attrs = create_event_attributes(pmu);
+	if (!pmu->events_attr_group.attrs)
 		goto err_name;
-	pmu->base.attr_groups	= i915_pmu_attr_groups;
+	pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
+					GFP_KERNEL);
+	if (!pmu->base.attr_groups)
+		goto err_attr;
 	pmu->base.task_ctx_nr	= perf_invalid_context;
 	pmu->base.event_init	= i915_pmu_event_init;
 	pmu->base.add		= i915_pmu_event_add;
 	ret = perf_pmu_register(&pmu->base, pmu->name, -1);
 	if (ret)
-		goto err_attr;
+		goto err_groups;
 	ret = i915_pmu_register_cpuhp_state(pmu);
 	if (ret)
 err_unreg:
 	perf_pmu_unregister(&pmu->base);
+err_groups:
+	kfree(pmu->base.attr_groups);
 err_attr:
 	pmu->base.event_init = NULL;
 	free_event_attributes(pmu);
 	perf_pmu_unregister(&pmu->base);
 	pmu->base.event_init = NULL;
+	kfree(pmu->base.attr_groups);
 	if (!is_igp(i915))
 		kfree(pmu->name);
 	free_event_attributes(pmu);

drivers/gpu/drm/i915/i915_pmu.h+9−2

 struct i915_pmu {
 	/**
-	 * @node: List node for CPU hotplug handling.
+	 * @cpuhp: Struct used for CPU hotplug handling.
 	 */
-	struct hlist_node node;
+	struct {
+		struct hlist_node node;
+		enum cpuhp_state slot;
+	} cpuhp;
 	/**
 	 * @base: PMU base.
 	 */
 	 * @sleep_last: Last time GT parked for RC6 estimation.
 	 */
 	ktime_t sleep_last;
+	/**
+	 * @events_attr_group: Device events attribute group.
+	 */
+	struct attribute_group events_attr_group;
 	/**
 	 * @i915_attr: Memory block holding device attributes.
 	 */

drivers/gpu/drm/i915/i915_reg.h+1−0

@@ -7757,6 +7757,7 @@ enum { · 7756 unmodified lines
7757	#define BW_BUDDY1_CTL _MMIO(0x45140)	7757	#define BW_BUDDY1_CTL _MMIO(0x45140)
7758	#define BW_BUDDY2_CTL _MMIO(0x45150)	7758	#define BW_BUDDY2_CTL _MMIO(0x45150)
7759	#define BW_BUDDY_DISABLE REG_BIT(31)	7759	#define BW_BUDDY_DISABLE REG_BIT(31)
		7760	#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
7760		7761
7761	#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144)	7762	#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144)
7762	#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154)	7763	#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154)

drivers/gpu/drm/i915/i915_request.c+48−21

@@ -275,7 +275,7 @@ bool i915_request_retire(struct i915_request *rq) · 274 unmodified lines
275	spin_unlock_irq(&rq->lock);	275	spin_unlock_irq(&rq->lock);
276		276
277	remove_from_client(rq);	277	remove_from_client(rq);
278	list_del(&rq->link);	278	list_del_rcu(&rq->link);
279		279
280	intel_context_exit(rq->context);	280	intel_context_exit(rq->context);
281	intel_context_unpin(rq->context);	281	intel_context_unpin(rq->context);
@@ -527,19 +527,31 @@ submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) · 245 unmodified lines
527	return NOTIFY_DONE;	527	return NOTIFY_DONE;
528	}	528	}
529		529
		530	static void irq_semaphore_cb(struct irq_work *wrk)
		531	{
		532	struct i915_request *rq =
		533	container_of(wrk, typeof(*rq), semaphore_work);
		534
		535	i915_schedule_bump_priority(rq, I915_PRIORITY_NOSEMAPHORE);
		536	i915_request_put(rq);
		537	}
		538
530	static int __i915_sw_fence_call	539	static int __i915_sw_fence_call
531	semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)	540	semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
532	{	541	{
533	struct i915_request *request =	542	struct i915_request rq = container_of(fence, typeof(rq), semaphore);
534	container_of(fence, typeof(*request), semaphore);
535		543
536	switch (state) {	544	switch (state) {
537	case FENCE_COMPLETE:	545	case FENCE_COMPLETE:
538	i915_schedule_bump_priority(request, I915_PRIORITY_NOSEMAPHORE);	546	if (!(READ_ONCE(rq->sched.attr.priority) & I915_PRIORITY_NOSEMAPHORE)) {
		547	i915_request_get(rq);
		548	init_irq_work(&rq->semaphore_work, irq_semaphore_cb);
		549	irq_work_queue(&rq->semaphore_work);
		550	}
539	break;	551	break;
540		552
541	case FENCE_FREE:	553	case FENCE_FREE:
542	i915_request_put(request);	554	i915_request_put(rq);
543	break;	555	break;
544	}	556	}
545		557
@@ -721,6 +733,8 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp) · 175 unmodified lines
721	rq->infix = rq->ring->emit; /* end of header; start of user payload */	733	rq->infix = rq->ring->emit; /* end of header; start of user payload */
722		734
723	intel_context_mark_active(ce);	735	intel_context_mark_active(ce);
		736	list_add_tail_rcu(&rq->link, &tl->requests);
		737
724	return rq;	738	return rq;
725		739
726	err_unwind:	740	err_unwind:
@@ -774,16 +788,26 @@ i915_request_await_start(struct i915_request rq, struct i915_request signal) · 47 unmodified lines
774	struct dma_fence *fence;	788	struct dma_fence *fence;
775	int err;	789	int err;
776		790
777	GEM_BUG_ON(i915_request_timeline(rq) ==	791	if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline))
778	rcu_access_pointer(signal->timeline));	792	return 0;
		793
		794	if (i915_request_started(signal))
		795	return 0;
779		796
780	fence = NULL;	797	fence = NULL;
781	rcu_read_lock();	798	rcu_read_lock();
782	spin_lock_irq(&signal->lock);	799	spin_lock_irq(&signal->lock);
783	if (!i915_request_started(signal) &&	800	do {
784	!list_is_first(&signal->link,	801	struct list_head *pos = READ_ONCE(signal->link.prev);
785	&rcu_dereference(signal->timeline)->requests)) {	802	struct i915_request *prev;
786	struct i915_request *prev = list_prev_entry(signal, link);	803
		804	/* Confirm signal has not been retired, the link is valid */
		805	if (unlikely(i915_request_started(signal)))
		806	break;
		807
		808	/* Is signal the earliest request on its timeline? */
		809	if (pos == &rcu_dereference(signal->timeline)->requests)
		810	break;
787		811
788	/*	812	/*
789	* Peek at the request before us in the timeline. That	813	* Peek at the request before us in the timeline. That
@@ -791,20 +815,25 @@ i915_request_await_start(struct i915_request rq, struct i915_request signal) · 1 unmodified line
791	* after acquiring a reference to it, confirm that it is	815	* after acquiring a reference to it, confirm that it is
792	* still part of the signaler's timeline.	816	* still part of the signaler's timeline.
793	*/	817	*/
794	if (i915_request_get_rcu(prev)) {	818	prev = list_entry(pos, typeof(*prev), link);
795	if (list_next_entry(prev, link) == signal)	819	if (!i915_request_get_rcu(prev))
796	fence = &prev->fence;	820	break;
797	else	821
798	i915_request_put(prev);	822	/* After the strong barrier, confirm prev is still attached */
		823	if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
		824	i915_request_put(prev);
		825	break;
799	}	826	}
800	}	827
		828	fence = &prev->fence;
		829	} while (0);
801	spin_unlock_irq(&signal->lock);	830	spin_unlock_irq(&signal->lock);
802	rcu_read_unlock();	831	rcu_read_unlock();
803	if (!fence)	832	if (!fence)
804	return 0;	833	return 0;
805		834
806	err = 0;	835	err = 0;
807	if (intel_timeline_sync_is_later(i915_request_timeline(rq), fence))	836	if (!intel_timeline_sync_is_later(i915_request_timeline(rq), fence))
808	err = i915_sw_fence_await_dma_fence(&rq->submit,	837	err = i915_sw_fence_await_dma_fence(&rq->submit,
809	fence, 0,	838	fence, 0,
810	I915_FENCE_GFP);	839	I915_FENCE_GFP);
@@ -1242,8 +1271,6 @@ __i915_request_add_to_timeline(struct i915_request *rq) · 431 unmodified lines
1242	0);	1271	0);
1243	}	1272	}
1244		1273
1245	list_add_tail(&rq->link, &timeline->requests);
1246
1247	/*	1274	/*
1248	* Make sure that no request gazumped us - if it was allocated after	1275	* Make sure that no request gazumped us - if it was allocated after
1249	* our i915_request_alloc() and called __i915_request_add() before	1276	* our i915_request_alloc() and called __i915_request_add() before
@@ -1303,9 +1330,9 @@ void __i915_request_queue(struct i915_request *rq, · 53 unmodified lines
1303	* decide whether to preempt the entire chain so that it is ready to	1330	* decide whether to preempt the entire chain so that it is ready to
1304	* run at the earliest possible convenience.	1331	* run at the earliest possible convenience.
1305	*/	1332	*/
1306	i915_sw_fence_commit(&rq->semaphore);
1307	if (attr && rq->engine->schedule)	1333	if (attr && rq->engine->schedule)
1308	rq->engine->schedule(rq, attr);	1334	rq->engine->schedule(rq, attr);
		1335	i915_sw_fence_commit(&rq->semaphore);
1309	i915_sw_fence_commit(&rq->submit);	1336	i915_sw_fence_commit(&rq->submit);
1310	}	1337	}
1311		1338

drivers/gpu/drm/i915/i915_request.h+2−0

 #define I915_REQUEST_H
 #include <linux/dma-fence.h>
+#include <linux/irq_work.h>
 #include <linux/lockdep.h>
 #include "gem/i915_gem_context_types.h"
 	};
 	struct list_head execute_cb;
 	struct i915_sw_fence semaphore;
+	struct irq_work semaphore_work;
 	/*
 	 * A list of everyone we wait upon, and everyone who waits upon us.

drivers/gpu/drm/i915/i915_utils.h+5−0

 	__idx;								\
 })
+static inline bool is_power_of_2_u64(u64 n)
+{
+	return (n != 0 && ((n & (n - 1)) == 0));
+}
 static inline void __list_del_many(struct list_head *head,
 				   struct list_head *first)
 {

drivers/gpu/drm/mediatek/mtk_drm_crtc.c+20−10

 	}
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	if (mtk_crtc->cmdq_client) {
+		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
 		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
 		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
 		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
 static int mtk_drm_crtc_init(struct drm_device *drm,
 			     struct mtk_drm_crtc *mtk_crtc,
-			     struct drm_plane *primary,
+			     unsigned int pipe)
-			     struct drm_plane *cursor, unsigned int pipe)
 {
-	int ret;
+	struct drm_plane *primary = NULL;
+	struct drm_plane *cursor = NULL;
+	int i, ret;
+	for (i = 0; i < mtk_crtc->layer_nr; i++) {
+		if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
+			primary = &mtk_crtc->planes[i];
+		else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
+			cursor = &mtk_crtc->planes[i];
+	}
 	ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
 					&mtk_crtc_funcs, NULL);
 }
 static inline
-enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx)
+enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
+					    unsigned int num_planes)
 {
 	if (plane_idx == 0)
 		return DRM_PLANE_TYPE_PRIMARY;
-	else if (plane_idx == 1)
+	else if (plane_idx == (num_planes - 1))
 		return DRM_PLANE_TYPE_CURSOR;
 	else
 		return DRM_PLANE_TYPE_OVERLAY;
 		ret = mtk_plane_init(drm_dev,
 				&mtk_crtc->planes[mtk_crtc->layer_nr],
 				BIT(pipe),
-				mtk_drm_crtc_plane_type(mtk_crtc->layer_nr),
+				mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
+							num_planes),
 				mtk_ddp_comp_supported_rotations(comp));
 		if (ret)
 			return ret;
 			return ret;
 	}
-	ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
+	ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
-				mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] :
-				NULL, pipe);
 	if (ret < 0)
 		return ret;
 			drm_crtc_index(&mtk_crtc->base));
 		mtk_crtc->cmdq_client = NULL;
 	}
-	ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
+	ret = of_property_read_u32_index(priv->mutex_node,
+					 "mediatek,gce-events",
 					 drm_crtc_index(&mtk_crtc->base),
 					 &mtk_crtc->cmdq_event);
 	if (ret)

drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c+1−0

@@ -471,6 +471,7 @@ int mtk_ddp_comp_init(struct device dev, struct device_node node, · 470 unmodified lines
471	/* Only DMA capable components need the LARB property */	471	/* Only DMA capable components need the LARB property */
472	comp->larb_dev = NULL;	472	comp->larb_dev = NULL;
473	if (type != MTK_DISP_OVL &&	473	if (type != MTK_DISP_OVL &&
		474	type != MTK_DISP_OVL_2L &&
474	type != MTK_DISP_RDMA &&	475	type != MTK_DISP_RDMA &&
475	type != MTK_DISP_WDMA)	476	type != MTK_DISP_WDMA)
476	return 0;	477	return 0;

drivers/gpu/drm/mediatek/mtk_drm_plane.c+7−0

 					struct drm_plane_state *state)
 {
 	struct drm_crtc_state *crtc_state;
+	int ret;
 	if (plane != state->crtc->cursor)
 		return -EINVAL;
 	if (!plane->state->fb)
 		return -EINVAL;
+	ret = mtk_drm_crtc_plane_check(state->crtc, plane,
+				       to_mtk_plane_state(state));
+	if (ret)
+		return ret;
 	if (state->state)
 		crtc_state = drm_atomic_get_existing_crtc_state(state->state,
 								state->crtc);
 	plane->state->src_y = new_state->src_y;
 	plane->state->src_h = new_state->src_h;
 	plane->state->src_w = new_state->src_w;
+	swap(plane->state->fb, new_state->fb);
 	state->pending.async_dirty = true;
 	mtk_drm_crtc_async_update(new_state->crtc, plane, new_state);

drivers/gpu/drm/panfrost/panfrost_mmu.c+19−25

@@ -601,33 +601,27 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) · 600 unmodified lines
601	source_id = (fault_status >> 16);	601	source_id = (fault_status >> 16);
602		602
603	/* Page fault only */	603	/* Page fault only */
604	if ((status & mask) == BIT(i)) {	604	ret = -1;
605	WARN_ON(exception_type < 0xC1 \|\| exception_type > 0xC4);	605	if ((status & mask) == BIT(i) && (exception_type & 0xF8) == 0xC0)
606
607	ret = panfrost_mmu_map_fault_addr(pfdev, i, addr);	606	ret = panfrost_mmu_map_fault_addr(pfdev, i, addr);
608	if (!ret) {
609	mmu_write(pfdev, MMU_INT_CLEAR, BIT(i));
610	status &= ~mask;
611	continue;
612	}
613	}
614		607
615	/* terminal fault, print info about the fault */	608	if (ret)
616	dev_err(pfdev->dev,	609	/* terminal fault, print info about the fault */
617	"Unhandled Page fault in AS%d at VA 0x%016llX\n"	610	dev_err(pfdev->dev,
618	"Reason: %s\n"	611	"Unhandled Page fault in AS%d at VA 0x%016llX\n"
619	"raw fault status: 0x%X\n"	612	"Reason: %s\n"
620	"decoded fault status: %s\n"	613	"raw fault status: 0x%X\n"
621	"exception type 0x%X: %s\n"	614	"decoded fault status: %s\n"
622	"access type 0x%X: %s\n"	615	"exception type 0x%X: %s\n"
623	"source id 0x%X\n",	616	"access type 0x%X: %s\n"
624	i, addr,	617	"source id 0x%X\n",
625	"TODO",	618	i, addr,
626	fault_status,	619	"TODO",
627	(fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"),	620	fault_status,
628	exception_type, panfrost_exception_name(pfdev, exception_type),	621	(fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"),
629	access_type, access_type_name(pfdev, fault_status),	622	exception_type, panfrost_exception_name(pfdev, exception_type),
630	source_id);	623	access_type, access_type_name(pfdev, fault_status),
		624	source_id);
631		625
632	mmu_write(pfdev, MMU_INT_CLEAR, mask);	626	mmu_write(pfdev, MMU_INT_CLEAR, mask);
633		627

drivers/gpu/drm/radeon/radeon_drv.c+41−2

@@ -37,6 +37,7 @@ · 36 unmodified lines
37	#include <linux/vga_switcheroo.h>	37	#include <linux/vga_switcheroo.h>
38	#include <linux/mmu_notifier.h>	38	#include <linux/mmu_notifier.h>
39		39
		40	#include <drm/drm_agpsupport.h>
40	#include <drm/drm_crtc_helper.h>	41	#include <drm/drm_crtc_helper.h>
41	#include <drm/drm_drv.h>	42	#include <drm/drm_drv.h>
42	#include <drm/drm_fb_helper.h>	43	#include <drm/drm_fb_helper.h>
@@ -325,6 +326,7 @@ static int radeon_pci_probe(struct pci_dev *pdev, · 282 unmodified lines
325	const struct pci_device_id *ent)	326	const struct pci_device_id *ent)
326	{	327	{
327	unsigned long flags = 0;	328	unsigned long flags = 0;
		329	struct drm_device *dev;
328	int ret;	330	int ret;
329		331
330	if (!ent)	332	if (!ent)
@@ -365,7 +367,44 @@ static int radeon_pci_probe(struct pci_dev *pdev, · 34 unmodified lines
365	if (ret)	367	if (ret)
366	return ret;	368	return ret;
367		369
368	return drm_get_pci_dev(pdev, ent, &kms_driver);	370	dev = drm_dev_alloc(&kms_driver, &pdev->dev);
		371	if (IS_ERR(dev))
		372	return PTR_ERR(dev);
		373
		374	ret = pci_enable_device(pdev);
		375	if (ret)
		376	goto err_free;
		377
		378	dev->pdev = pdev;
		379	#ifdef __alpha__
		380	dev->hose = pdev->sysdata;
		381	#endif
		382
		383	pci_set_drvdata(pdev, dev);
		384
		385	if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP))
		386	dev->agp = drm_agp_init(dev);
		387	if (dev->agp) {
		388	dev->agp->agp_mtrr = arch_phys_wc_add(
		389	dev->agp->agp_info.aper_base,
		390	dev->agp->agp_info.aper_size *
		391	1024 * 1024);
		392	}
		393
		394	ret = drm_dev_register(dev, ent->driver_data);
		395	if (ret)
		396	goto err_agp;
		397
		398	return 0;
		399
		400	err_agp:
		401	if (dev->agp)
		402	arch_phys_wc_del(dev->agp->agp_mtrr);
		403	kfree(dev->agp);
		404	pci_disable_device(pdev);
		405	err_free:
		406	drm_dev_put(dev);
		407	return ret;
369	}	408	}
370		409
371	static void	410	static void
@@ -575,7 +614,7 @@ radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, · 203 unmodified lines
575		614
576	static struct drm_driver kms_driver = {	615	static struct drm_driver kms_driver = {
577	.driver_features =	616	.driver_features =
578	DRIVER_USE_AGP \| DRIVER_GEM \| DRIVER_RENDER,	617	DRIVER_GEM \| DRIVER_RENDER,
579	.load = radeon_driver_load_kms,	618	.load = radeon_driver_load_kms,
580	.open = radeon_driver_open_kms,	619	.open = radeon_driver_open_kms,
581	.postclose = radeon_driver_postclose_kms,	620	.postclose = radeon_driver_postclose_kms,

drivers/gpu/drm/radeon/radeon_kms.c+6−0

 #include <linux/uaccess.h>
 #include <linux/vga_switcheroo.h>
+#include <drm/drm_agpsupport.h>
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_file.h>
 #include <drm/drm_ioctl.h>
 	radeon_modeset_fini(rdev);
 	radeon_device_fini(rdev);
+	if (dev->agp)
+		arch_phys_wc_del(dev->agp->agp_mtrr);
+	kfree(dev->agp);
+	dev->agp = NULL;
 done_free:
 	kfree(rdev);
 	dev->dev_private = NULL;

drivers/gpu/drm/sun4i/sun8i_mixer.c+92−12

@@ -106,48 +106,128 @@ static const struct de2_fmt_info de2_formats[] = { · 105 unmodified lines
106	.rgb = true,	106	.rgb = true,
107	.csc = SUN8I_CSC_MODE_OFF,	107	.csc = SUN8I_CSC_MODE_OFF,
108	},	108	},
		109	{
		110	/* for DE2 VI layer which ignores alpha */
		111	.drm_fmt = DRM_FORMAT_XRGB4444,
		112	.de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
		113	.rgb = true,
		114	.csc = SUN8I_CSC_MODE_OFF,
		115	},
109	{	116	{
110	.drm_fmt = DRM_FORMAT_ABGR4444,	117	.drm_fmt = DRM_FORMAT_ABGR4444,
111	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,	118	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
112	.rgb = true,	119	.rgb = true,
113	.csc = SUN8I_CSC_MODE_OFF,	120	.csc = SUN8I_CSC_MODE_OFF,
114	},	121	},
		122	{
		123	/* for DE2 VI layer which ignores alpha */
		124	.drm_fmt = DRM_FORMAT_XBGR4444,
		125	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
		126	.rgb = true,
		127	.csc = SUN8I_CSC_MODE_OFF,
		128	},
115	{	129	{
116	.drm_fmt = DRM_FORMAT_RGBA4444,	130	.drm_fmt = DRM_FORMAT_RGBA4444,
117	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,	131	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
118	.rgb = true,	132	.rgb = true,
119	.csc = SUN8I_CSC_MODE_OFF,	133	.csc = SUN8I_CSC_MODE_OFF,
120	},	134	},
		135	{
		136	/* for DE2 VI layer which ignores alpha */
		137	.drm_fmt = DRM_FORMAT_RGBX4444,
		138	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
		139	.rgb = true,
		140	.csc = SUN8I_CSC_MODE_OFF,
		141	},
121	{	142	{
122	.drm_fmt = DRM_FORMAT_BGRA4444,	143	.drm_fmt = DRM_FORMAT_BGRA4444,
123	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,	144	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
124	.rgb = true,	145	.rgb = true,
125	.csc = SUN8I_CSC_MODE_OFF,	146	.csc = SUN8I_CSC_MODE_OFF,
126	},	147	},
		148	{
		149	/* for DE2 VI layer which ignores alpha */
		150	.drm_fmt = DRM_FORMAT_BGRX4444,
		151	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
		152	.rgb = true,
		153	.csc = SUN8I_CSC_MODE_OFF,
		154	},
127	{	155	{
128	.drm_fmt = DRM_FORMAT_ARGB1555,	156	.drm_fmt = DRM_FORMAT_ARGB1555,
129	.de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,	157	.de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
130	.rgb = true,	158	.rgb = true,
131	.csc = SUN8I_CSC_MODE_OFF,	159	.csc = SUN8I_CSC_MODE_OFF,
132	},	160	},
		161	{
		162	/* for DE2 VI layer which ignores alpha */
		163	.drm_fmt = DRM_FORMAT_XRGB1555,
		164	.de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
		165	.rgb = true,
		166	.csc = SUN8I_CSC_MODE_OFF,
		167	},
133	{	168	{
134	.drm_fmt = DRM_FORMAT_ABGR1555,	169	.drm_fmt = DRM_FORMAT_ABGR1555,
135	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,	170	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
136	.rgb = true,	171	.rgb = true,
137	.csc = SUN8I_CSC_MODE_OFF,	172	.csc = SUN8I_CSC_MODE_OFF,
138	},	173	},
		174	{
		175	/* for DE2 VI layer which ignores alpha */
		176	.drm_fmt = DRM_FORMAT_XBGR1555,
		177	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
		178	.rgb = true,
		179	.csc = SUN8I_CSC_MODE_OFF,
		180	},
139	{	181	{
140	.drm_fmt = DRM_FORMAT_RGBA5551,	182	.drm_fmt = DRM_FORMAT_RGBA5551,
141	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,	183	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
142	.rgb = true,	184	.rgb = true,
143	.csc = SUN8I_CSC_MODE_OFF,	185	.csc = SUN8I_CSC_MODE_OFF,
144	},	186	},
		187	{
		188	/* for DE2 VI layer which ignores alpha */
		189	.drm_fmt = DRM_FORMAT_RGBX5551,
		190	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
		191	.rgb = true,
		192	.csc = SUN8I_CSC_MODE_OFF,
		193	},
145	{	194	{
146	.drm_fmt = DRM_FORMAT_BGRA5551,	195	.drm_fmt = DRM_FORMAT_BGRA5551,
147	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,	196	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
148	.rgb = true,	197	.rgb = true,
149	.csc = SUN8I_CSC_MODE_OFF,	198	.csc = SUN8I_CSC_MODE_OFF,
150	},	199	},
		200	{
		201	/* for DE2 VI layer which ignores alpha */
		202	.drm_fmt = DRM_FORMAT_BGRX5551,
		203	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
		204	.rgb = true,
		205	.csc = SUN8I_CSC_MODE_OFF,
		206	},
		207	{
		208	.drm_fmt = DRM_FORMAT_ARGB2101010,
		209	.de2_fmt = SUN8I_MIXER_FBFMT_ARGB2101010,
		210	.rgb = true,
		211	.csc = SUN8I_CSC_MODE_OFF,
		212	},
		213	{
		214	.drm_fmt = DRM_FORMAT_ABGR2101010,
		215	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR2101010,
		216	.rgb = true,
		217	.csc = SUN8I_CSC_MODE_OFF,
		218	},
		219	{
		220	.drm_fmt = DRM_FORMAT_RGBA1010102,
		221	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA1010102,
		222	.rgb = true,
		223	.csc = SUN8I_CSC_MODE_OFF,
		224	},
		225	{
		226	.drm_fmt = DRM_FORMAT_BGRA1010102,
		227	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA1010102,
		228	.rgb = true,
		229	.csc = SUN8I_CSC_MODE_OFF,
		230	},
151	{	231	{
152	.drm_fmt = DRM_FORMAT_UYVY,	232	.drm_fmt = DRM_FORMAT_UYVY,
153	.de2_fmt = SUN8I_MIXER_FBFMT_UYVY,	233	.de2_fmt = SUN8I_MIXER_FBFMT_UYVY,
@@ -196,12 +276,6 @@ static const struct de2_fmt_info de2_formats[] = { · 42 unmodified lines
196	.rgb = false,	276	.rgb = false,
197	.csc = SUN8I_CSC_MODE_YUV2RGB,	277	.csc = SUN8I_CSC_MODE_YUV2RGB,
198	},	278	},
199	{
200	.drm_fmt = DRM_FORMAT_YUV444,
201	.de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
202	.rgb = true,
203	.csc = SUN8I_CSC_MODE_YUV2RGB,
204	},
205	{	279	{
206	.drm_fmt = DRM_FORMAT_YUV422,	280	.drm_fmt = DRM_FORMAT_YUV422,
207	.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,	281	.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
@@ -220,12 +294,6 @@ static const struct de2_fmt_info de2_formats[] = { · 12 unmodified lines
220	.rgb = false,	294	.rgb = false,
221	.csc = SUN8I_CSC_MODE_YUV2RGB,	295	.csc = SUN8I_CSC_MODE_YUV2RGB,
222	},	296	},
223	{
224	.drm_fmt = DRM_FORMAT_YVU444,
225	.de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
226	.rgb = true,
227	.csc = SUN8I_CSC_MODE_YVU2RGB,
228	},
229	{	297	{
230	.drm_fmt = DRM_FORMAT_YVU422,	298	.drm_fmt = DRM_FORMAT_YVU422,
231	.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,	299	.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
@@ -244,6 +312,18 @@ static const struct de2_fmt_info de2_formats[] = { · 12 unmodified lines
244	.rgb = false,	312	.rgb = false,
245	.csc = SUN8I_CSC_MODE_YVU2RGB,	313	.csc = SUN8I_CSC_MODE_YVU2RGB,
246	},	314	},
		315	{
		316	.drm_fmt = DRM_FORMAT_P010,
		317	.de2_fmt = SUN8I_MIXER_FBFMT_P010_YUV,
		318	.rgb = false,
		319	.csc = SUN8I_CSC_MODE_YUV2RGB,
		320	},
		321	{
		322	.drm_fmt = DRM_FORMAT_P210,
		323	.de2_fmt = SUN8I_MIXER_FBFMT_P210_YUV,
		324	.rgb = false,
		325	.csc = SUN8I_CSC_MODE_YUV2RGB,
		326	},
247	};	327	};
248		328
249	const struct de2_fmt_info *sun8i_mixer_format_info(u32 format)	329	const struct de2_fmt_info *sun8i_mixer_format_info(u32 format)

drivers/gpu/drm/sun4i/sun8i_mixer.h+11−0

 #define SUN8I_MIXER_FBFMT_ABGR1555	17
 #define SUN8I_MIXER_FBFMT_RGBA5551	18
 #define SUN8I_MIXER_FBFMT_BGRA5551	19
+#define SUN8I_MIXER_FBFMT_ARGB2101010	20
+#define SUN8I_MIXER_FBFMT_ABGR2101010	21
+#define SUN8I_MIXER_FBFMT_RGBA1010102	22
+#define SUN8I_MIXER_FBFMT_BGRA1010102	23
 #define SUN8I_MIXER_FBFMT_YUYV		0
 #define SUN8I_MIXER_FBFMT_UYVY		1
 /* format 12 is semi-planar YUV411 UVUV */
 /* format 13 is semi-planar YUV411 VUVU */
 #define SUN8I_MIXER_FBFMT_YUV411	14
+/* format 15 doesn't exist */
+/* format 16 is P010 YVU */
+#define SUN8I_MIXER_FBFMT_P010_YUV	17
+/* format 18 is P210 YVU */
+#define SUN8I_MIXER_FBFMT_P210_YUV	19
+/* format 20 is packed YVU444 10-bit */
+/* format 21 is packed YUV444 10-bit */
 /*
  * Sub-engines listed bellow are unused for now. The EN registers are here only

drivers/gpu/drm/sun4i/sun8i_vi_layer.c+58−8

 };
 /*
- * While all RGB formats are supported, VI planes don't support
+ * While DE2 VI layer supports same RGB formats as UI layer, alpha
- * alpha blending, so there is no point having formats with alpha
+ * channel is ignored. This structure lists all unique variants
- * channel if their opaque analog exist.
+ * where alpha channel is replaced with "don't care" (X) channel.
  */
 static const u32 sun8i_vi_layer_formats[] = {
+	DRM_FORMAT_BGR565,
+	DRM_FORMAT_BGR888,
+	DRM_FORMAT_BGRX4444,
+	DRM_FORMAT_BGRX5551,
+	DRM_FORMAT_BGRX8888,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_RGB888,
+	DRM_FORMAT_RGBX4444,
+	DRM_FORMAT_RGBX5551,
+	DRM_FORMAT_RGBX8888,
+	DRM_FORMAT_XBGR1555,
+	DRM_FORMAT_XBGR4444,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XRGB1555,
+	DRM_FORMAT_XRGB4444,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_NV16,
+	DRM_FORMAT_NV12,
+	DRM_FORMAT_NV21,
+	DRM_FORMAT_NV61,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_YUV411,
+	DRM_FORMAT_YUV420,
+	DRM_FORMAT_YUV422,
+	DRM_FORMAT_YVU411,
+	DRM_FORMAT_YVU420,
+	DRM_FORMAT_YVU422,
+};
+static const u32 sun8i_vi_layer_de3_formats[] = {
 	DRM_FORMAT_ABGR1555,
+	DRM_FORMAT_ABGR2101010,
 	DRM_FORMAT_ABGR4444,
+	DRM_FORMAT_ABGR8888,
 	DRM_FORMAT_ARGB1555,
+	DRM_FORMAT_ARGB2101010,
 	DRM_FORMAT_ARGB4444,
+	DRM_FORMAT_ARGB8888,
 	DRM_FORMAT_BGR565,
 	DRM_FORMAT_BGR888,
+	DRM_FORMAT_BGRA1010102,
 	DRM_FORMAT_BGRA5551,
 	DRM_FORMAT_BGRA4444,
+	DRM_FORMAT_BGRA8888,
 	DRM_FORMAT_BGRX8888,
 	DRM_FORMAT_RGB565,
 	DRM_FORMAT_RGB888,
+	DRM_FORMAT_RGBA1010102,
 	DRM_FORMAT_RGBA4444,
 	DRM_FORMAT_RGBA5551,
+	DRM_FORMAT_RGBA8888,
 	DRM_FORMAT_RGBX8888,
 	DRM_FORMAT_XBGR8888,
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_NV12,
 	DRM_FORMAT_NV21,
 	DRM_FORMAT_NV61,
+	DRM_FORMAT_P010,
+	DRM_FORMAT_P210,
 	DRM_FORMAT_UYVY,
 	DRM_FORMAT_VYUY,
 	DRM_FORMAT_YUYV,
 	DRM_FORMAT_YUV411,
 	DRM_FORMAT_YUV420,
 	DRM_FORMAT_YUV422,
-	DRM_FORMAT_YUV444,
 	DRM_FORMAT_YVU411,
 	DRM_FORMAT_YVU420,
 	DRM_FORMAT_YVU422,
-	DRM_FORMAT_YVU444,
 };
 struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
 					       int index)
 {
 	u32 supported_encodings, supported_ranges;
+	unsigned int plane_cnt, format_count;
 	struct sun8i_vi_layer *layer;
-	unsigned int plane_cnt;
+	const u32 *formats;
 	int ret;
 	layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
 	if (!layer)
 		return ERR_PTR(-ENOMEM);
+	if (mixer->cfg->is_de3) {
+		formats = sun8i_vi_layer_de3_formats;
+		format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats);
+	} else {
+		formats = sun8i_vi_layer_formats;
+		format_count = ARRAY_SIZE(sun8i_vi_layer_formats);
+	}
 	/* possible crtcs are set later */
 	ret = drm_universal_plane_init(drm, &layer->plane, 0,
 				       &sun8i_vi_layer_funcs,
-				       sun8i_vi_layer_formats,
+				       formats, format_count,
-				       ARRAY_SIZE(sun8i_vi_layer_formats),
 				       NULL, DRM_PLANE_TYPE_OVERLAY, NULL);
 	if (ret) {
 		dev_err(drm->dev, "Couldn't initialize layer\n");

drivers/gpu/drm/ttm/ttm_bo_util.c+1−0

@@ -515,6 +515,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo, · 514 unmodified lines
515	fbo->base.base.resv = &fbo->base.base._resv;	515	fbo->base.base.resv = &fbo->base.base._resv;
516		516
517	dma_resv_init(&fbo->base.base._resv);	517	dma_resv_init(&fbo->base.base._resv);
		518	fbo->base.base.dev = NULL;
518	ret = dma_resv_trylock(&fbo->base.base._resv);	519	ret = dma_resv_trylock(&fbo->base.base._resv);
519	WARN_ON(!ret);	520	WARN_ON(!ret);
520		521

drivers/gpu/drm/virtio/virtgpu_object.c+3−2

 		 * "f91a9dd35715 Fix unlinking resources from hash
 		 * table." (Feb 2019) fixes the bug.
 		 */
-		static int handle;
+		static atomic_t seqno = ATOMIC_INIT(0);
-		handle++;
+		int handle = atomic_inc_return(&seqno);
 		*resid = handle + 1;
 	} else {
 		int handle = ida_alloc(&vgdev->resource_ida, GFP_KERNEL);
 		return NULL;
 	bo->base.base.funcs = &virtio_gpu_gem_funcs;
+	bo->base.map_cached = true;
 	return &bo->base.base;
 }

drivers/hid/hid-alps.c+1−1

@@ -730,7 +730,7 @@ static int alps_input_configured(struct hid_device hdev, struct hid_input hi) · 729 unmodified lines
730	if (data->has_sp) {	730	if (data->has_sp) {
731	input2 = input_allocate_device();	731	input2 = input_allocate_device();
732	if (!input2) {	732	if (!input2) {
733	input_free_device(input2);	733	ret = -ENOMEM;
734	goto exit;	734	goto exit;
735	}	735	}
736		736

drivers/hid/hid-apple.c+2−1

 		unsigned long **bit, int *max)
 {
 	if (usage->hid == (HID_UP_CUSTOM | 0x0003) ||
-			usage->hid == (HID_UP_MSVENDOR | 0x0003)) {
+			usage->hid == (HID_UP_MSVENDOR | 0x0003) ||
+			usage->hid == (HID_UP_HPVENDOR2 | 0x0003)) {
 		/* The fn key on Apple USB keyboards */
 		set_bit(EV_REP, hi->input->evbit);
 		hid_map_usage_clear(hi, usage, bit, max, EV_KEY, KEY_FN);

drivers/hid/hid-bigbenff.c+24−7

 struct bigben_device {
 	struct hid_device *hid;
 	struct hid_report *report;
+	bool removed;
 	u8 led_state;         /* LED1 = 1 .. LED4 = 8 */
 	u8 right_motor_on;    /* right motor off/on 0/1 */
 	u8 left_motor_force;  /* left motor force 0-255 */
 		struct bigben_device, worker);
 	struct hid_field *report_field = bigben->report->field[0];
+	if (bigben->removed)
+		return;
 	if (bigben->work_led) {
 		bigben->work_led = false;
 		report_field->value[0] = 0x01; /* 1 = led message */
 static int hid_bigben_play_effect(struct input_dev *dev, void *data,
 			 struct ff_effect *effect)
 {
-	struct bigben_device *bigben = data;
+	struct hid_device *hid = input_get_drvdata(dev);
+	struct bigben_device *bigben = hid_get_drvdata(hid);
 	u8 right_motor_on;
 	u8 left_motor_force;
+	if (!bigben) {
+		hid_err(hid, "no device data\n");
+		return 0;
+	}
 	if (effect->type != FF_RUMBLE)
 		return 0;
 {
 	struct bigben_device *bigben = hid_get_drvdata(hid);
+	bigben->removed = true;
 	cancel_work_sync(&bigben->worker);
-	hid_hw_close(hid);
 	hid_hw_stop(hid);
 }
 		return -ENOMEM;
 	hid_set_drvdata(hid, bigben);
 	bigben->hid = hid;
+	bigben->removed = false;
 	error = hid_parse(hid);
 	if (error) {
 	INIT_WORK(&bigben->worker, bigben_worker);
-	error = input_ff_create_memless(hidinput->input, bigben,
+	error = input_ff_create_memless(hidinput->input, NULL,
 		hid_bigben_play_effect);
 	if (error)
-		return error;
+		goto error_hw_stop;
 	name_sz = strlen(dev_name(&hid->dev)) + strlen(":red:bigben#") + 1;
 			sizeof(struct led_classdev) + name_sz,
 			GFP_KERNEL
 		);
-		if (!led)
+		if (!led) {
-			return -ENOMEM;
+			error = -ENOMEM;
+			goto error_hw_stop;
+		}
 		name = (void *)(&led[1]);
 		snprintf(name, name_sz,
 			"%s:red:bigben%d",
 		bigben->leds[n] = led;
 		error = devm_led_classdev_register(&hid->dev, led);
 		if (error)
-			return error;
+			goto error_hw_stop;
 	}
 	/* initial state: LED1 is on, no rumble effect */
 	hid_info(hid, "LED and force feedback support for BigBen gamepad\n");
 	return 0;
+error_hw_stop:
+	hid_hw_stop(hid);
+	return error;
 }
 static __u8 *bigben_report_fixup(struct hid_device *hid, __u8 *rdesc,

drivers/hid/hid-core.c+3−1

@@ -1741,7 +1741,9 @@ int hid_report_raw_event(struct hid_device hid, int type, u8 data, u32 size, · 1740 unmodified lines
1741		1741
1742	rsize = ((report->size - 1) >> 3) + 1;	1742	rsize = ((report->size - 1) >> 3) + 1;
1743		1743
1744	if (rsize > HID_MAX_BUFFER_SIZE)	1744	if (report_enum->numbered && rsize >= HID_MAX_BUFFER_SIZE)
		1745	rsize = HID_MAX_BUFFER_SIZE - 1;
		1746	else if (rsize > HID_MAX_BUFFER_SIZE)
1745	rsize = HID_MAX_BUFFER_SIZE;	1747	rsize = HID_MAX_BUFFER_SIZE;
1746		1748
1747	if (csize < rsize) {	1749	if (csize < rsize) {

drivers/hid/hid-google-hammer.c+2−0

 		     USB_VENDOR_ID_GOOGLE, USB_DEVICE_ID_GOOGLE_MAGNEMITE) },
 	{ HID_DEVICE(BUS_USB, HID_GROUP_GENERIC,
 		     USB_VENDOR_ID_GOOGLE, USB_DEVICE_ID_GOOGLE_MASTERBALL) },
+	{ HID_DEVICE(BUS_USB, HID_GROUP_GENERIC,
+		     USB_VENDOR_ID_GOOGLE, USB_DEVICE_ID_GOOGLE_MOONBALL) },
 	{ HID_DEVICE(BUS_USB, HID_GROUP_GENERIC,
 		     USB_VENDOR_ID_GOOGLE, USB_DEVICE_ID_GOOGLE_STAFF) },
 	{ HID_DEVICE(BUS_USB, HID_GROUP_GENERIC,

drivers/hid/hid-hyperv.c+2−4

 		goto cleanup;
 	/* The pointer is not NULL when we resume from hibernation */
-	if (input_device->hid_desc != NULL)
+	kfree(input_device->hid_desc);
-		kfree(input_device->hid_desc);
 	input_device->hid_desc = kmemdup(desc, desc->bLength, GFP_ATOMIC);
 	if (!input_device->hid_desc)
 	}
 	/* The pointer is not NULL when we resume from hibernation */
-	if (input_device->report_desc != NULL)
+	kfree(input_device->report_desc);
-		kfree(input_device->report_desc);
 	input_device->report_desc = kzalloc(input_device->report_desc_size,
 					  GFP_ATOMIC);

drivers/hid/hid-ids.h+2−0

 #define USB_DEVICE_ID_GOOGLE_WHISKERS	0x5030
 #define USB_DEVICE_ID_GOOGLE_MASTERBALL	0x503c
 #define USB_DEVICE_ID_GOOGLE_MAGNEMITE	0x503d
+#define USB_DEVICE_ID_GOOGLE_MOONBALL	0x5044
 #define USB_VENDOR_ID_GOTOP		0x08f2
 #define USB_DEVICE_ID_SUPER_Q2		0x007f
 #define USB_DEVICE_ID_LENOVO_X1_COVER	0x6085
 #define USB_DEVICE_ID_LENOVO_X1_TAB	0x60a3
 #define USB_DEVICE_ID_LENOVO_X1_TAB3	0x60b5
+#define USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_608D	0x608d
 #define USB_VENDOR_ID_LG		0x1fd2
 #define USB_DEVICE_ID_LG_MULTITOUCH	0x0064

drivers/hid/hid-ite.c+3−2

 	{ HID_USB_DEVICE(USB_VENDOR_ID_ITE, USB_DEVICE_ID_ITE8595) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_258A, USB_DEVICE_ID_258A_6A88) },
 	/* ITE8595 USB kbd ctlr, with Synaptics touchpad connected to it. */
-	{ HID_USB_DEVICE(USB_VENDOR_ID_SYNAPTICS,
+	{ HID_DEVICE(BUS_USB, HID_GROUP_GENERIC,
-			 USB_DEVICE_ID_SYNAPTICS_ACER_SWITCH5_012) },
+		     USB_VENDOR_ID_SYNAPTICS,
+		     USB_DEVICE_ID_SYNAPTICS_ACER_SWITCH5_012) },
 	{ }
 };
 MODULE_DEVICE_TABLE(hid, ite_devices);

drivers/hid/hid-logitech-hidpp.c+21−22

@@ -1256,36 +1256,35 @@ static int hidpp20_battery_map_status_voltage(u8 data[3], int *voltage, · 1255 unmodified lines
1256	{	1256	{
1257	int status;	1257	int status;
1258		1258
1259	long charge_sts = (long)data[2];	1259	long flags = (long) data[2];
1260		1260
1261	*level = POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN;	1261	if (flags & 0x80)
1262	switch (data[2] & 0xe0) {	1262	switch (flags & 0x07) {
1263	case 0x00:	1263	case 0:
1264	status = POWER_SUPPLY_STATUS_CHARGING;	1264	status = POWER_SUPPLY_STATUS_CHARGING;
1265	break;	1265	break;
1266	case 0x20:	1266	case 1:
1267	status = POWER_SUPPLY_STATUS_FULL;	1267	status = POWER_SUPPLY_STATUS_FULL;
1268	*level = POWER_SUPPLY_CAPACITY_LEVEL_FULL;	1268	*level = POWER_SUPPLY_CAPACITY_LEVEL_FULL;
1269	break;	1269	break;
1270	case 0x40:	1270	case 2:
		1271	status = POWER_SUPPLY_STATUS_NOT_CHARGING;
		1272	break;
		1273	default:
		1274	status = POWER_SUPPLY_STATUS_UNKNOWN;
		1275	break;
		1276	}
		1277	else
1271	status = POWER_SUPPLY_STATUS_DISCHARGING;	1278	status = POWER_SUPPLY_STATUS_DISCHARGING;
1272	break;
1273	case 0xe0:
1274	status = POWER_SUPPLY_STATUS_NOT_CHARGING;
1275	break;
1276	default:
1277	status = POWER_SUPPLY_STATUS_UNKNOWN;
1278	}
1279		1279
1280	*charge_type = POWER_SUPPLY_CHARGE_TYPE_STANDARD;	1280	*charge_type = POWER_SUPPLY_CHARGE_TYPE_STANDARD;
1281	if (test_bit(3, &charge_sts)) {	1281	if (test_bit(3, &flags)) {
1282	*charge_type = POWER_SUPPLY_CHARGE_TYPE_FAST;	1282	*charge_type = POWER_SUPPLY_CHARGE_TYPE_FAST;
1283	}	1283	}
1284	if (test_bit(4, &charge_sts)) {	1284	if (test_bit(4, &flags)) {
1285	*charge_type = POWER_SUPPLY_CHARGE_TYPE_TRICKLE;	1285	*charge_type = POWER_SUPPLY_CHARGE_TYPE_TRICKLE;
1286	}	1286	}
1287		1287	if (test_bit(5, &flags)) {
1288	if (test_bit(5, &charge_sts)) {
1289	*level = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL;	1288	*level = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL;
1290	}	1289	}
1291		1290

drivers/hid/hid-picolcd_fb.c+2−2

@@ -458,9 +458,9 @@ static ssize_t picolcd_fb_update_rate_show(struct device *dev, · 457 unmodified lines
458	if (ret >= PAGE_SIZE)	458	if (ret >= PAGE_SIZE)
459	break;	459	break;
460	else if (i == fb_update_rate)	460	else if (i == fb_update_rate)
461	ret += snprintf(buf+ret, PAGE_SIZE-ret, "[%u] ", i);	461	ret += scnprintf(buf+ret, PAGE_SIZE-ret, "[%u] ", i);
462	else	462	else
463	ret += snprintf(buf+ret, PAGE_SIZE-ret, "%u ", i);	463	ret += scnprintf(buf+ret, PAGE_SIZE-ret, "%u ", i);
464	if (ret > 0)	464	if (ret > 0)
465	buf[min(ret, (size_t)PAGE_SIZE)-1] = '\n';	465	buf[min(ret, (size_t)PAGE_SIZE)-1] = '\n';
466	return ret;	466	return ret;

drivers/hid/hid-quirks.c+1−0

@@ -103,6 +103,7 @@ static const struct hid_device_id hid_quirks[] = { · 102 unmodified lines
103	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_PENSKETCH_M912), HID_QUIRK_MULTI_INPUT },	103	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_PENSKETCH_M912), HID_QUIRK_MULTI_INPUT },
104	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M406XE), HID_QUIRK_MULTI_INPUT },	104	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M406XE), HID_QUIRK_MULTI_INPUT },
105	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_PIXART_USB_OPTICAL_MOUSE_ID2), HID_QUIRK_ALWAYS_POLL },	105	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_PIXART_USB_OPTICAL_MOUSE_ID2), HID_QUIRK_ALWAYS_POLL },
		106	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_608D), HID_QUIRK_ALWAYS_POLL },
106	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_C007), HID_QUIRK_ALWAYS_POLL },	107	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_C007), HID_QUIRK_ALWAYS_POLL },
107	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_C077), HID_QUIRK_ALWAYS_POLL },	108	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_C077), HID_QUIRK_ALWAYS_POLL },
108	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_KEYBOARD_G710_PLUS), HID_QUIRK_NOGET },	109	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_KEYBOARD_G710_PLUS), HID_QUIRK_NOGET },

drivers/hid/hid-sensor-custom.c+3−3

@@ -313,7 +313,7 @@ static ssize_t show_value(struct device dev, struct device_attribute attr, · 312 unmodified lines
313		313
314	while (i < ret) {	314	while (i < ret) {
315	if (i + attribute->size > ret) {	315	if (i + attribute->size > ret) {
316	len += snprintf(&buf[len],	316	len += scnprintf(&buf[len],
317	PAGE_SIZE - len,	317	PAGE_SIZE - len,
318	"%d ", values[i]);	318	"%d ", values[i]);
319	break;	319	break;
@@ -336,10 +336,10 @@ static ssize_t show_value(struct device dev, struct device_attribute attr, · 16 unmodified lines
336	++i;	336	++i;
337	break;	337	break;
338	}	338	}
339	len += snprintf(&buf[len], PAGE_SIZE - len,	339	len += scnprintf(&buf[len], PAGE_SIZE - len,
340	"%lld ", value);	340	"%lld ", value);
341	}	341	}
342	len += snprintf(&buf[len], PAGE_SIZE - len, "\n");	342	len += scnprintf(&buf[len], PAGE_SIZE - len, "\n");
343		343
344	return len;	344	return len;
345	} else if (input)	345	} else if (input)

drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c+8−0

@@ -341,6 +341,14 @@ static const struct dmi_system_id i2c_hid_dmi_desc_override_table[] = { · 340 unmodified lines
341	},	341	},
342	.driver_data = (void *)&sipodev_desc	342	.driver_data = (void *)&sipodev_desc
343	},	343	},
		344	{
		345	.ident = "Trekstor SURFBOOK E11B",
		346	.matches = {
		347	DMI_EXACT_MATCH(DMI_SYS_VENDOR, "TREKSTOR"),
		348	DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "SURFBOOK E11B"),
		349	},
		350	.driver_data = (void *)&sipodev_desc
		351	},
344	{	352	{
345	.ident = "Direkt-Tek DTLAPY116-2",	353	.ident = "Direkt-Tek DTLAPY116-2",
346	.matches = {	354	.matches = {

drivers/hid/usbhid/hiddev.c+1−1

 	hiddev->exist = 0;
 	if (hiddev->open) {
-		mutex_unlock(&hiddev->existancelock);
 		hid_hw_close(hiddev->hid);
 		wake_up_interruptible(&hiddev->wait);
+		mutex_unlock(&hiddev->existancelock);
 	} else {
 		mutex_unlock(&hiddev->existancelock);
 		kfree(hiddev);

drivers/hwmon/adt7462.c+1−1

@@ -413,7 +413,7 @@ static int ADT7462_REG_VOLT(struct adt7462_data *data, int which) · 412 unmodified lines
413	return 0x95;	413	return 0x95;
414	break;	414	break;
415	}	415	}
416	return -ENODEV;	416	return 0;
417	}	417	}
418		418
419	/* Provide labels for sysfs */	419	/* Provide labels for sysfs */

drivers/hwmon/pmbus/xdpe12284.c+54−0

@@ -18,6 +18,59 @@ · 17 unmodified lines
18	#define XDPE122_AMD_625MV 0x10 /* AMD mode 6.25mV */	18	#define XDPE122_AMD_625MV 0x10 /* AMD mode 6.25mV */
19	#define XDPE122_PAGE_NUM 2	19	#define XDPE122_PAGE_NUM 2
20		20
		21	static int xdpe122_read_word_data(struct i2c_client *client, int page, int reg)
		22	{
		23	const struct pmbus_driver_info *info = pmbus_get_driver_info(client);
		24	long val;
		25	s16 exponent;
		26	s32 mantissa;
		27	int ret;
		28
		29	switch (reg) {
		30	case PMBUS_VOUT_OV_FAULT_LIMIT:
		31	case PMBUS_VOUT_UV_FAULT_LIMIT:
		32	ret = pmbus_read_word_data(client, page, reg);
		33	if (ret < 0)
		34	return ret;
		35
		36	/* Convert register value to LINEAR11 data. */
		37	exponent = ((s16)ret) >> 11;
		38	mantissa = ((s16)((ret & GENMASK(10, 0)) << 5)) >> 5;
		39	val = mantissa * 1000L;
		40	if (exponent >= 0)
		41	val <<= exponent;
		42	else
		43	val >>= -exponent;
		44
		45	/* Convert data to VID register. */
		46	switch (info->vrm_version[page]) {
		47	case vr13:
		48	if (val >= 500)
		49	return 1 + DIV_ROUND_CLOSEST(val - 500, 10);
		50	return 0;
		51	case vr12:
		52	if (val >= 250)
		53	return 1 + DIV_ROUND_CLOSEST(val - 250, 5);
		54	return 0;
		55	case imvp9:
		56	if (val >= 200)
		57	return 1 + DIV_ROUND_CLOSEST(val - 200, 10);
		58	return 0;
		59	case amd625mv:
		60	if (val >= 200 && val <= 1550)
		61	return DIV_ROUND_CLOSEST((1550 - val) * 100,
		62	625);
		63	return 0;
		64	default:
		65	return -EINVAL;
		66	}
		67	default:
		68	return -ENODATA;
		69	}
		70
		71	return 0;
		72	}
		73
21	static int xdpe122_identify(struct i2c_client *client,	74	static int xdpe122_identify(struct i2c_client *client,
22	struct pmbus_driver_info *info)	75	struct pmbus_driver_info *info)
23	{	76	{
@@ -70,6 +123,7 @@ static struct pmbus_driver_info xdpe122_info = { · 46 unmodified lines
70	PMBUS_HAVE_TEMP \| PMBUS_HAVE_STATUS_TEMP \|	123	PMBUS_HAVE_TEMP \| PMBUS_HAVE_STATUS_TEMP \|
71	PMBUS_HAVE_POUT \| PMBUS_HAVE_PIN \| PMBUS_HAVE_STATUS_INPUT,	124	PMBUS_HAVE_POUT \| PMBUS_HAVE_PIN \| PMBUS_HAVE_STATUS_INPUT,
72	.identify = xdpe122_identify,	125	.identify = xdpe122_identify,
		126	.read_word_data = xdpe122_read_word_data,
73	};	127	};
74		128
75	static int xdpe122_probe(struct i2c_client *client,	129	static int xdpe122_probe(struct i2c_client *client,

drivers/hwtracing/intel_th/msu.c+7−6

 	if (old != expect) {
 		ret = -EINVAL;
-		dev_warn_ratelimited(msc_dev(win->msc),
-				     "expected lockout state %d, got %d\n",
-				     expect, old);
 		goto unlock;
 	}
 		/* from intel_th_msc_window_unlock(), don't warn if not locked */
 		if (expect == WIN_LOCKED && old == new)
 			return 0;
+		dev_warn_ratelimited(msc_dev(win->msc),
+				     "expected lockout state %d, got %d\n",
+				     expect, old);
 	}
 	return ret;
 	lockdep_assert_held(&msc->buf_mutex);
 	if (msc->mode > MSC_MODE_MULTI)
-		return -ENOTSUPP;
+		return -EINVAL;
 	if (msc->mode == MSC_MODE_MULTI) {
 		if (msc_win_set_lockout(msc->cur_win, WIN_READY, WIN_INUSE))
 	} else if (msc->mode == MSC_MODE_MULTI) {
 		ret = msc_buffer_multi_alloc(msc, nr_pages, nr_wins);
 	} else {
-		ret = -ENOTSUPP;
+		ret = -EINVAL;
 	}
 	if (!ret) {
 		if (ret >= 0)
 			*ppos = iter->offset;
 	} else {
-		ret = -ENOTSUPP;
+		ret = -EINVAL;
 	}
 put_count:

drivers/hwtracing/intel_th/pci.c+5−0

 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4da6),
 		.driver_data = (kernel_ulong_t)&intel_th_2x,
 	},
+	{
+		/* Elkhart Lake CPU */
+		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4529),
+		.driver_data = (kernel_ulong_t)&intel_th_2x,
+	},
 	{
 		/* Elkhart Lake */
 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4b26),

drivers/hwtracing/stm/p_sys-t.c+3−3

@@ -238,7 +238,7 @@ static struct configfs_attribute *sys_t_policy_attrs[] = { · 237 unmodified lines
238	static inline bool sys_t_need_ts(struct sys_t_output *op)	238	static inline bool sys_t_need_ts(struct sys_t_output *op)
239	{	239	{
240	if (op->node.ts_interval &&	240	if (op->node.ts_interval &&
241	time_after(op->ts_jiffies + op->node.ts_interval, jiffies)) {	241	time_after(jiffies, op->ts_jiffies + op->node.ts_interval)) {
242	op->ts_jiffies = jiffies;	242	op->ts_jiffies = jiffies;
243		243
244	return true;	244	return true;
@@ -250,8 +250,8 @@ static inline bool sys_t_need_ts(struct sys_t_output *op) · 5 unmodified lines
250	static bool sys_t_need_clock_sync(struct sys_t_output *op)	250	static bool sys_t_need_clock_sync(struct sys_t_output *op)
251	{	251	{
252	if (op->node.clocksync_interval &&	252	if (op->node.clocksync_interval &&
253	time_after(op->clocksync_jiffies + op->node.clocksync_interval,	253	time_after(jiffies,
254	jiffies)) {	254	op->clocksync_jiffies + op->node.clocksync_interval)) {
255	op->clocksync_jiffies = jiffies;	255	op->clocksync_jiffies = jiffies;
256		256
257	return true;	257	return true;

drivers/i2c/busses/i2c-altera.c+1−1

@@ -171,7 +171,7 @@ static void altr_i2c_init(struct altr_i2c_dev *idev) · 170 unmodified lines
171	/* SCL Low Time */	171	/* SCL Low Time */
172	writel(t_low, idev->base + ALTR_I2C_SCL_LOW);	172	writel(t_low, idev->base + ALTR_I2C_SCL_LOW);
173	/* SDA Hold Time, 300ns */	173	/* SDA Hold Time, 300ns */
174	writel(div_u64(300 * clk_mhz, 1000), idev->base + ALTR_I2C_SDA_HOLD);	174	writel(3 * clk_mhz / 10, idev->base + ALTR_I2C_SDA_HOLD);
175		175
176	/* Mask all master interrupt bits */	176	/* Mask all master interrupt bits */
177	altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);	177	altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);

drivers/i2c/busses/i2c-designware-pcidrv.c+1−0

@@ -313,6 +313,7 @@ static void i2c_dw_pci_remove(struct pci_dev *pdev) · 312 unmodified lines
313	pm_runtime_get_noresume(&pdev->dev);	313	pm_runtime_get_noresume(&pdev->dev);
314		314
315	i2c_del_adapter(&dev->adapter);	315	i2c_del_adapter(&dev->adapter);
		316	devm_free_irq(&pdev->dev, dev->irq, dev);
316	pci_free_irq_vectors(pdev);	317	pci_free_irq_vectors(pdev);
317	}	318	}
318		319

drivers/i2c/busses/i2c-gpio.c+1−1

@@ -348,7 +348,7 @@ static struct gpio_desc i2c_gpio_get_desc(struct device dev, · 347 unmodified lines
348	if (ret == -ENOENT)	348	if (ret == -ENOENT)
349	retdesc = ERR_PTR(-EPROBE_DEFER);	349	retdesc = ERR_PTR(-EPROBE_DEFER);
350		350
351	if (ret != -EPROBE_DEFER)	351	if (PTR_ERR(retdesc) != -EPROBE_DEFER)
352	dev_err(dev, "error trying to get descriptor: %d\n", ret);	352	dev_err(dev, "error trying to get descriptor: %d\n", ret);
353		353
354	return retdesc;	354	return retdesc;

drivers/i2c/busses/i2c-i801.c+12−33

@@ -132,11 +132,6 @@ · 131 unmodified lines
132	#define TCOBASE 0x050	132	#define TCOBASE 0x050
133	#define TCOCTL 0x054	133	#define TCOCTL 0x054
134		134
135	#define ACPIBASE 0x040
136	#define ACPIBASE_SMI_OFF 0x030
137	#define ACPICTRL 0x044
138	#define ACPICTRL_EN 0x080
139
140	#define SBREG_BAR 0x10	135	#define SBREG_BAR 0x10
141	#define SBREG_SMBCTRL 0xc6000c	136	#define SBREG_SMBCTRL 0xc6000c
142	#define SBREG_SMBCTRL_DNV 0xcf000c	137	#define SBREG_SMBCTRL_DNV 0xcf000c
@@ -1553,7 +1548,7 @@ i801_add_tco_spt(struct i801_priv priv, struct pci_dev pci_dev, · 1410 unmodified lines
1553	pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);	1548	pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1554	spin_unlock(&p2sb_spinlock);	1549	spin_unlock(&p2sb_spinlock);
1555		1550
1556	res = &tco_res[ICH_RES_MEM_OFF];	1551	res = &tco_res[1];
1557	if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)	1552	if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1558	res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;	1553	res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1559	else	1554	else
@@ -1563,7 +1558,7 @@ i801_add_tco_spt(struct i801_priv priv, struct pci_dev pci_dev, · 3 unmodified lines
1563	res->flags = IORESOURCE_MEM;	1558	res->flags = IORESOURCE_MEM;
1564		1559
1565	return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,	1560	return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1566	tco_res, 3, &spt_tco_platform_data,	1561	tco_res, 2, &spt_tco_platform_data,
1567	sizeof(spt_tco_platform_data));	1562	sizeof(spt_tco_platform_data));
1568	}	1563	}
1569		1564
@@ -1576,17 +1571,16 @@ static struct platform_device * · 6 unmodified lines
1576	i801_add_tco_cnl(struct i801_priv priv, struct pci_dev pci_dev,	1571	i801_add_tco_cnl(struct i801_priv priv, struct pci_dev pci_dev,
1577	struct resource *tco_res)	1572	struct resource *tco_res)
1578	{	1573	{
1579	return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,	1574	return platform_device_register_resndata(&pci_dev->dev,
1580	tco_res, 2, &cnl_tco_platform_data,	1575	"iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data,
1581	sizeof(cnl_tco_platform_data));	1576	sizeof(cnl_tco_platform_data));
1582	}	1577	}
1583		1578
1584	static void i801_add_tco(struct i801_priv *priv)	1579	static void i801_add_tco(struct i801_priv *priv)
1585	{	1580	{
1586	u32 base_addr, tco_base, tco_ctl, ctrl_val;
1587	struct pci_dev *pci_dev = priv->pci_dev;	1581	struct pci_dev *pci_dev = priv->pci_dev;
1588	struct resource tco_res[3], *res;	1582	struct resource tco_res[2], *res;
1589	unsigned int devfn;	1583	u32 tco_base, tco_ctl;
1590		1584
1591	/* If we have ACPI based watchdog use that instead */	1585	/* If we have ACPI based watchdog use that instead */
1592	if (acpi_has_watchdog())	1586	if (acpi_has_watchdog())
@@ -1601,30 +1595,15 @@ static void i801_add_tco(struct i801_priv *priv) · 8 unmodified lines
1601	return;	1595	return;
1602		1596
1603	memset(tco_res, 0, sizeof(tco_res));	1597	memset(tco_res, 0, sizeof(tco_res));
1604
1605	res = &tco_res[ICH_RES_IO_TCO];
1606	res->start = tco_base & ~1;
1607	res->end = res->start + 32 - 1;
1608	res->flags = IORESOURCE_IO;
1609
1610	/*	1598	/*
1611	* Power Management registers.	1599	* Always populate the main iTCO IO resource here. The second entry
		1600	* for NO_REBOOT MMIO is filled by the SPT specific function.
1612	*/	1601	*/
1613	devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);	1602	res = &tco_res[0];
1614	pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);	1603	res->start = tco_base & ~1;
1615		1604	res->end = res->start + 32 - 1;
1616	res = &tco_res[ICH_RES_IO_SMI];
1617	res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1618	res->end = res->start + 3;
1619	res->flags = IORESOURCE_IO;	1605	res->flags = IORESOURCE_IO;
1620		1606
1621	/*
1622	* Enable the ACPI I/O space.
1623	*/
1624	pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1625	ctrl_val \|= ACPICTRL_EN;
1626	pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1627
1628	if (priv->features & FEATURE_TCO_CNL)	1607	if (priv->features & FEATURE_TCO_CNL)
1629	priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);	1608	priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1630	else	1609	else

drivers/i2c/busses/i2c-jz4780.c+2−34

@@ -78,25 +78,6 @@ · 77 unmodified lines
78		78
79	#define X1000_I2C_DC_STOP BIT(9)	79	#define X1000_I2C_DC_STOP BIT(9)
80		80
81	static const char * const jz4780_i2c_abrt_src[] = {
82	"ABRT_7B_ADDR_NOACK",
83	"ABRT_10ADDR1_NOACK",
84	"ABRT_10ADDR2_NOACK",
85	"ABRT_XDATA_NOACK",
86	"ABRT_GCALL_NOACK",
87	"ABRT_GCALL_READ",
88	"ABRT_HS_ACKD",
89	"SBYTE_ACKDET",
90	"ABRT_HS_NORSTRT",
91	"SBYTE_NORSTRT",
92	"ABRT_10B_RD_NORSTRT",
93	"ABRT_MASTER_DIS",
94	"ARB_LOST",
95	"SLVFLUSH_TXFIFO",
96	"SLV_ARBLOST",
97	"SLVRD_INTX",
98	};
99
100	#define JZ4780_I2C_INTST_IGC BIT(11)	81	#define JZ4780_I2C_INTST_IGC BIT(11)
101	#define JZ4780_I2C_INTST_ISTT BIT(10)	82	#define JZ4780_I2C_INTST_ISTT BIT(10)
102	#define JZ4780_I2C_INTST_ISTP BIT(9)	83	#define JZ4780_I2C_INTST_ISTP BIT(9)
@@ -576,21 +557,8 @@ done: · 473 unmodified lines
576		557
577	static void jz4780_i2c_txabrt(struct jz4780_i2c *i2c, int src)	558	static void jz4780_i2c_txabrt(struct jz4780_i2c *i2c, int src)
578	{	559	{
579	int i;	560	dev_dbg(&i2c->adap.dev, "txabrt: 0x%08x, cmd: %d, send: %d, recv: %d\n",
580		561	src, i2c->cmd, i2c->cmd_buf[i2c->cmd], i2c->data_buf[i2c->cmd]);
581	dev_err(&i2c->adap.dev, "txabrt: 0x%08x\n", src);
582	dev_err(&i2c->adap.dev, "device addr=%x\n",
583	jz4780_i2c_readw(i2c, JZ4780_I2C_TAR));
584	dev_err(&i2c->adap.dev, "send cmd count:%d %d\n",
585	i2c->cmd, i2c->cmd_buf[i2c->cmd]);
586	dev_err(&i2c->adap.dev, "receive data count:%d %d\n",
587	i2c->cmd, i2c->data_buf[i2c->cmd]);
588
589	for (i = 0; i < 16; i++) {
590	if (src & BIT(i))
591	dev_dbg(&i2c->adap.dev, "I2C TXABRT[%d]=%s\n",
592	i, jz4780_i2c_abrt_src[i]);
593	}
594	}	562	}
595		563
596	static inline int jz4780_i2c_xfer_read(struct jz4780_i2c *i2c,	564	static inline int jz4780_i2c_xfer_read(struct jz4780_i2c *i2c,

drivers/i2c/i2c-core-acpi.c+9−1

 static struct i2c_client *i2c_acpi_find_client_by_adev(struct acpi_device *adev)
 {
 	struct device *dev;
+	struct i2c_client *client;
 	dev = bus_find_device_by_acpi_dev(&i2c_bus_type, adev);
-	return dev ? i2c_verify_client(dev) : NULL;
+	if (!dev)
+		return NULL;
+	client = i2c_verify_client(dev);
+	if (!client)
+		put_device(dev);
+	return client;
 }
 static int i2c_acpi_notify(struct notifier_block *nb, unsigned long value,

drivers/ide/ide-gd.c+1−1

@@ -361,7 +361,7 @@ static const struct block_device_operations ide_gd_ops = { · 360 unmodified lines
361	.release = ide_gd_release,	361	.release = ide_gd_release,
362	.ioctl = ide_gd_ioctl,	362	.ioctl = ide_gd_ioctl,
363	#ifdef CONFIG_COMPAT	363	#ifdef CONFIG_COMPAT
364	.ioctl = ide_gd_compat_ioctl,	364	.compat_ioctl = ide_gd_compat_ioctl,
365	#endif	365	#endif
366	.getgeo = ide_gd_getgeo,	366	.getgeo = ide_gd_getgeo,
367	.check_events = ide_gd_check_events,	367	.check_events = ide_gd_check_events,

drivers/iio/accel/adxl372.c+1−0

@@ -237,6 +237,7 @@ static const struct adxl372_axis_lookup adxl372_axis_lookup_table[] = { · 236 unmodified lines
237	.realbits = 12, \	237	.realbits = 12, \
238	.storagebits = 16, \	238	.storagebits = 16, \
239	.shift = 4, \	239	.shift = 4, \
		240	.endianness = IIO_BE, \
240	}, \	241	}, \
241	}	242	}
242		243

drivers/iio/accel/st_accel_i2c.c+1−1

@@ -110,7 +110,7 @@ MODULE_DEVICE_TABLE(of, st_accel_of_match); · 109 unmodified lines
110		110
111	#ifdef CONFIG_ACPI	111	#ifdef CONFIG_ACPI
112	static const struct acpi_device_id st_accel_acpi_match[] = {	112	static const struct acpi_device_id st_accel_acpi_match[] = {
113	{"SMO8840", (kernel_ulong_t)LNG2DM_ACCEL_DEV_NAME},	113	{"SMO8840", (kernel_ulong_t)LIS2DH12_ACCEL_DEV_NAME},
114	{"SMO8A90", (kernel_ulong_t)LNG2DM_ACCEL_DEV_NAME},	114	{"SMO8A90", (kernel_ulong_t)LNG2DM_ACCEL_DEV_NAME},
115	{ },	115	{ },
116	};	116	};

drivers/iio/adc/at91-sama5d2_adc.c+15−0

@@ -723,6 +723,7 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) · 722 unmodified lines
723		723
724	for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) {	724	for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) {
725	struct iio_chan_spec const *chan = at91_adc_chan_get(indio, bit);	725	struct iio_chan_spec const *chan = at91_adc_chan_get(indio, bit);
		726	u32 cor;
726		727
727	if (!chan)	728	if (!chan)
728	continue;	729	continue;
@@ -731,6 +732,20 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) · 2 unmodified lines
731	chan->type == IIO_PRESSURE)	732	chan->type == IIO_PRESSURE)
732	continue;	733	continue;
733		734
		735	if (state) {
		736	cor = at91_adc_readl(st, AT91_SAMA5D2_COR);
		737
		738	if (chan->differential)
		739	cor \|= (BIT(chan->channel) \|
		740	BIT(chan->channel2)) <<
		741	AT91_SAMA5D2_COR_DIFF_OFFSET;
		742	else
		743	cor &= ~(BIT(chan->channel) <<
		744	AT91_SAMA5D2_COR_DIFF_OFFSET);
		745
		746	at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
		747	}
		748
734	if (state) {	749	if (state) {
735	at91_adc_writel(st, AT91_SAMA5D2_CHER,	750	at91_adc_writel(st, AT91_SAMA5D2_CHER,
736	BIT(chan->channel));	751	BIT(chan->channel));

drivers/iio/adc/stm32-dfsdm-adc.c+10−33

 	}
 }
-static irqreturn_t stm32_dfsdm_adc_trigger_handler(int irq, void *p)
-{
-	struct iio_poll_func *pf = p;
-	struct iio_dev *indio_dev = pf->indio_dev;
-	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
-	int available = stm32_dfsdm_adc_dma_residue(adc);
-	while (available >= indio_dev->scan_bytes) {
-		s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
-		stm32_dfsdm_process_data(adc, buffer);
-		iio_push_to_buffers_with_timestamp(indio_dev, buffer,
-						   pf->timestamp);
-		available -= indio_dev->scan_bytes;
-		adc->bufi += indio_dev->scan_bytes;
-		if (adc->bufi >= adc->buf_sz)
-			adc->bufi = 0;
-	}
-	iio_trigger_notify_done(indio_dev->trig);
-	return IRQ_HANDLED;
-}
 static void stm32_dfsdm_dma_buffer_done(void *data)
 {
 	struct iio_dev *indio_dev = data;
 	int available = stm32_dfsdm_adc_dma_residue(adc);
 	size_t old_pos;
-	if (indio_dev->currentmode & INDIO_BUFFER_TRIGGERED) {
-		iio_trigger_poll_chained(indio_dev->trig);
-		return;
-	}
 	/*
 	 * FIXME: In Kernel interface does not support cyclic DMA buffer,and
 	 * offers only an interface to push data samples per samples.
 			adc->bufi = 0;
 			old_pos = 0;
 		}
-		/* regular iio buffer without trigger */
+		/*
+		 * In DMA mode the trigger services of IIO are not used
+		 * (e.g. no call to iio_trigger_poll).
+		 * Calling irq handler associated to the hardware trigger is not
+		 * relevant as the conversions have already been done. Data
+		 * transfers are performed directly in DMA callback instead.
+		 * This implementation avoids to call trigger irq handler that
+		 * may sleep, in an atomic context (DMA irq handler context).
+		 */
 		if (adc->dev_data->type == DFSDM_IIO)
 			iio_push_to_buffers(indio_dev, buffer);
 	}
 	}
 	ret = iio_triggered_buffer_setup(indio_dev,
-					 &iio_pollfunc_store_time,
+					 &iio_pollfunc_store_time, NULL,
-					 &stm32_dfsdm_adc_trigger_handler,
 					 &stm32_dfsdm_buffer_setup_ops);
 	if (ret) {
 		stm32_dfsdm_dma_release(indio_dev);

drivers/iio/chemical/Kconfig+2−0

 	tristate "SPS30 particulate matter sensor"
 	depends on I2C
 	select CRC8
+	select IIO_BUFFER
+	select IIO_TRIGGERED_BUFFER
 	help
 	  Say Y here to build support for the Sensirion SPS30 particulate
 	  matter sensor.

drivers/iio/light/vcnl4000.c+8−7

@@ -167,16 +167,17 @@ static int vcnl4200_init(struct vcnl4000_data *data) · 166 unmodified lines
167	data->vcnl4200_ps.reg = VCNL4200_PS_DATA;	167	data->vcnl4200_ps.reg = VCNL4200_PS_DATA;
168	switch (id) {	168	switch (id) {
169	case VCNL4200_PROD_ID:	169	case VCNL4200_PROD_ID:
170	/* Integration time is 50ms, but the experiments */	170	/* Default wait time is 50ms, add 20% tolerance. */
171	/* show 54ms in total. */	171	data->vcnl4200_al.sampling_rate = ktime_set(0, 60000 * 1000);
172	data->vcnl4200_al.sampling_rate = ktime_set(0, 54000 * 1000);	172	/* Default wait time is 4.8ms, add 20% tolerance. */
173	data->vcnl4200_ps.sampling_rate = ktime_set(0, 4200 * 1000);	173	data->vcnl4200_ps.sampling_rate = ktime_set(0, 5760 * 1000);
174	data->al_scale = 24000;	174	data->al_scale = 24000;
175	break;	175	break;
176	case VCNL4040_PROD_ID:	176	case VCNL4040_PROD_ID:
177	/* Integration time is 80ms, add 10ms. */	177	/* Default wait time is 80ms, add 20% tolerance. */
178	data->vcnl4200_al.sampling_rate = ktime_set(0, 100000 * 1000);	178	data->vcnl4200_al.sampling_rate = ktime_set(0, 96000 * 1000);
179	data->vcnl4200_ps.sampling_rate = ktime_set(0, 100000 * 1000);	179	/* Default wait time is 5ms, add 20% tolerance. */
		180	data->vcnl4200_ps.sampling_rate = ktime_set(0, 6000 * 1000);
180	data->al_scale = 120000;	181	data->al_scale = 120000;
181	break;	182	break;
182	}	183	}

drivers/iio/magnetometer/ak8974.c+1−1

@@ -564,7 +564,7 @@ static int ak8974_read_raw(struct iio_dev *indio_dev, · 563 unmodified lines
564	* We read all axes and discard all but one, for optimized	564	* We read all axes and discard all but one, for optimized
565	* reading, use the triggered buffer.	565	* reading, use the triggered buffer.
566	*/	566	*/
567	*val = le16_to_cpu(hw_values[chan->address]);	567	*val = (s16)le16_to_cpu(hw_values[chan->address]);
568		568
569	ret = IIO_VAL_INT;	569	ret = IIO_VAL_INT;
570	}	570	}

drivers/iio/proximity/ping.c+1−1

@@ -269,7 +269,7 @@ static const struct iio_chan_spec ping_chan_spec[] = { · 268 unmodified lines
269		269
270	static const struct of_device_id of_ping_match[] = {	270	static const struct of_device_id of_ping_match[] = {
271	{ .compatible = "parallax,ping", .data = &pa_ping_cfg},	271	{ .compatible = "parallax,ping", .data = &pa_ping_cfg},
272	{ .compatible = "parallax,laserping", .data = &pa_ping_cfg},	272	{ .compatible = "parallax,laserping", .data = &pa_laser_ping_cfg},
273	{},	273	{},
274	};	274	};
275		275

drivers/iio/trigger/stm32-timer-trigger.c+9−2

 	return 0;
 }
-static void stm32_timer_stop(struct stm32_timer_trigger *priv)
+static void stm32_timer_stop(struct stm32_timer_trigger *priv,
+			     struct iio_trigger *trig)
 {
 	u32 ccer, cr1;
 	regmap_write(priv->regmap, TIM_PSC, 0);
 	regmap_write(priv->regmap, TIM_ARR, 0);
+	/* Force disable master mode */
+	if (stm32_timer_is_trgo2_name(trig->name))
+		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
+	else
+		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);
 	/* Make sure that registers are updated */
 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 }
 		return ret;
 	if (freq == 0) {
-		stm32_timer_stop(priv);
+		stm32_timer_stop(priv, trig);
 	} else {
 		ret = stm32_timer_start(priv, trig, freq);
 		if (ret)

drivers/infiniband/core/cm.c+1−0

@@ -1191,6 +1191,7 @@ struct ib_cm_id ib_cm_insert_listen(struct ib_device device, · 1190 unmodified lines
1191	/* Sharing an ib_cm_id with different handlers is not	1191	/* Sharing an ib_cm_id with different handlers is not
1192	* supported */	1192	* supported */
1193	spin_unlock_irqrestore(&cm.lock, flags);	1193	spin_unlock_irqrestore(&cm.lock, flags);
		1194	ib_destroy_cm_id(cm_id);
1194	return ERR_PTR(-EINVAL);	1195	return ERR_PTR(-EINVAL);
1195	}	1196	}
1196	refcount_inc(&cm_id_priv->refcount);	1197	refcount_inc(&cm_id_priv->refcount);

drivers/infiniband/core/cma.c+11−4

 	int ret;
 	id_priv = container_of(id, struct rdma_id_private, id);
+	memcpy(cma_dst_addr(id_priv), dst_addr, rdma_addr_size(dst_addr));
 	if (id_priv->state == RDMA_CM_IDLE) {
 		ret = cma_bind_addr(id, src_addr, dst_addr);
-		if (ret)
+		if (ret) {
+			memset(cma_dst_addr(id_priv), 0,
+			       rdma_addr_size(dst_addr));
 			return ret;
+		}
 	}
-	if (cma_family(id_priv) != dst_addr->sa_family)
+	if (cma_family(id_priv) != dst_addr->sa_family) {
+		memset(cma_dst_addr(id_priv), 0, rdma_addr_size(dst_addr));
 		return -EINVAL;
+	}
-	if (!cma_comp_exch(id_priv, RDMA_CM_ADDR_BOUND, RDMA_CM_ADDR_QUERY))
+	if (!cma_comp_exch(id_priv, RDMA_CM_ADDR_BOUND, RDMA_CM_ADDR_QUERY)) {
+		memset(cma_dst_addr(id_priv), 0, rdma_addr_size(dst_addr));
 		return -EINVAL;
+	}
-	memcpy(cma_dst_addr(id_priv), dst_addr, rdma_addr_size(dst_addr));
 	if (cma_any_addr(dst_addr)) {
 		ret = cma_resolve_loopback(id_priv);
 	} else {

drivers/infiniband/core/core_priv.h+14−0

@@ -338,6 +338,20 @@ static inline struct ib_qp _ib_create_qp(struct ib_device dev, · 337 unmodified lines
338	qp->pd = pd;	338	qp->pd = pd;
339	qp->uobject = uobj;	339	qp->uobject = uobj;
340	qp->real_qp = qp;	340	qp->real_qp = qp;
		341
		342	qp->qp_type = attr->qp_type;
		343	qp->rwq_ind_tbl = attr->rwq_ind_tbl;
		344	qp->send_cq = attr->send_cq;
		345	qp->recv_cq = attr->recv_cq;
		346	qp->srq = attr->srq;
		347	qp->rwq_ind_tbl = attr->rwq_ind_tbl;
		348	qp->event_handler = attr->event_handler;
		349
		350	atomic_set(&qp->usecnt, 0);
		351	spin_lock_init(&qp->mr_lock);
		352	INIT_LIST_HEAD(&qp->rdma_mrs);
		353	INIT_LIST_HEAD(&qp->sig_mrs);
		354
341	/*	355	/*
342	* We don't track XRC QPs for now, because they don't have PD	356	* We don't track XRC QPs for now, because they don't have PD
343	* and more importantly they are created internaly by driver,	357	* and more importantly they are created internaly by driver,

drivers/infiniband/core/iwcm.c+3−1

 {
 	struct list_head *e, *tmp;
-	list_for_each_safe(e, tmp, &cm_id_priv->work_free_list)
+	list_for_each_safe(e, tmp, &cm_id_priv->work_free_list) {
+		list_del(e);
 		kfree(list_entry(e, struct iwcm_work, free_list));
+	}
 }
 static int alloc_work_entries(struct iwcm_id_private *cm_id_priv, int count)

drivers/infiniband/core/nldev.c+2−0

 		if (ret)
 			goto err_msg;
 	} else {
+		if (!tb[RDMA_NLDEV_ATTR_RES_LQPN])
+			goto err_msg;
 		qpn = nla_get_u32(tb[RDMA_NLDEV_ATTR_RES_LQPN]);
 		if (tb[RDMA_NLDEV_ATTR_STAT_COUNTER_ID]) {
 			cntn = nla_get_u32(tb[RDMA_NLDEV_ATTR_STAT_COUNTER_ID]);

drivers/infiniband/core/rw.c+20−11

 	return 1;
 }
+static void rdma_rw_unmap_sg(struct ib_device *dev, struct scatterlist *sg,
+			     u32 sg_cnt, enum dma_data_direction dir)
+{
+	if (is_pci_p2pdma_page(sg_page(sg)))
+		pci_p2pdma_unmap_sg(dev->dma_device, sg, sg_cnt, dir);
+	else
+		ib_dma_unmap_sg(dev, sg, sg_cnt, dir);
+}
+static int rdma_rw_map_sg(struct ib_device *dev, struct scatterlist *sg,
+			  u32 sg_cnt, enum dma_data_direction dir)
+{
+	if (is_pci_p2pdma_page(sg_page(sg)))
+		return pci_p2pdma_map_sg(dev->dma_device, sg, sg_cnt, dir);
+	return ib_dma_map_sg(dev, sg, sg_cnt, dir);
+}
 /**
  * rdma_rw_ctx_init - initialize a RDMA READ/WRITE context
  * @ctx:	context to initialize
 	struct ib_device *dev = qp->pd->device;
 	int ret;
-	if (is_pci_p2pdma_page(sg_page(sg)))
+	ret = rdma_rw_map_sg(dev, sg, sg_cnt, dir);
-		ret = pci_p2pdma_map_sg(dev->dma_device, sg, sg_cnt, dir);
-	else
-		ret = ib_dma_map_sg(dev, sg, sg_cnt, dir);
 	if (!ret)
 		return -ENOMEM;
 	sg_cnt = ret;
 	return ret;
 out_unmap_sg:
-	ib_dma_unmap_sg(dev, sg, sg_cnt, dir);
+	rdma_rw_unmap_sg(dev, sg, sg_cnt, dir);
 	return ret;
 }
 EXPORT_SYMBOL(rdma_rw_ctx_init);
 		break;
 	}
-	if (is_pci_p2pdma_page(sg_page(sg)))
+	rdma_rw_unmap_sg(qp->pd->device, sg, sg_cnt, dir);
-		pci_p2pdma_unmap_sg(qp->pd->device->dma_device, sg,
-				    sg_cnt, dir);
-	else
-		ib_dma_unmap_sg(qp->pd->device, sg, sg_cnt, dir);
 }
 EXPORT_SYMBOL(rdma_rw_ctx_destroy);

drivers/infiniband/core/security.c+9−5

 		return NULL;
 	if (qp_attr_mask & IB_QP_PORT)
-		new_pps->main.port_num =
+		new_pps->main.port_num = qp_attr->port_num;
-			(qp_pps) ? qp_pps->main.port_num : qp_attr->port_num;
+	else if (qp_pps)
+		new_pps->main.port_num = qp_pps->main.port_num;
 	if (qp_attr_mask & IB_QP_PKEY_INDEX)
-		new_pps->main.pkey_index = (qp_pps) ? qp_pps->main.pkey_index :
+		new_pps->main.pkey_index = qp_attr->pkey_index;
-						      qp_attr->pkey_index;
+	else if (qp_pps)
+		new_pps->main.pkey_index = qp_pps->main.pkey_index;
 	if ((qp_attr_mask & IB_QP_PKEY_INDEX) && (qp_attr_mask & IB_QP_PORT))
 		new_pps->main.state = IB_PORT_PKEY_VALID;
-	if (!(qp_attr_mask & (IB_QP_PKEY_INDEX || IB_QP_PORT)) && qp_pps) {
+	if (!(qp_attr_mask & (IB_QP_PKEY_INDEX | IB_QP_PORT)) && qp_pps) {
 		new_pps->main.port_num = qp_pps->main.port_num;
 		new_pps->main.pkey_index = qp_pps->main.pkey_index;
 		if (qp_pps->main.state != IB_PORT_PKEY_NOT_VALID)

drivers/infiniband/core/umem_odp.c+19−5

@@ -181,14 +181,28 @@ ib_umem_odp_alloc_child(struct ib_umem_odp *root, unsigned long addr, · 180 unmodified lines
181	odp_data->page_shift = PAGE_SHIFT;	181	odp_data->page_shift = PAGE_SHIFT;
182	odp_data->notifier.ops = ops;	182	odp_data->notifier.ops = ops;
183		183
		184	/*
		185	* A mmget must be held when registering a notifier, the owming_mm only
		186	* has a mm_grab at this point.
		187	*/
		188	if (!mmget_not_zero(umem->owning_mm)) {
		189	ret = -EFAULT;
		190	goto out_free;
		191	}
		192
184	odp_data->tgid = get_pid(root->tgid);	193	odp_data->tgid = get_pid(root->tgid);
185	ret = ib_init_umem_odp(odp_data, ops);	194	ret = ib_init_umem_odp(odp_data, ops);
186	if (ret) {	195	if (ret)
187	put_pid(odp_data->tgid);	196	goto out_tgid;
188	kfree(odp_data);	197	mmput(umem->owning_mm);
189	return ERR_PTR(ret);
190	}
191	return odp_data;	198	return odp_data;
		199
		200	out_tgid:
		201	put_pid(odp_data->tgid);
		202	mmput(umem->owning_mm);
		203	out_free:
		204	kfree(odp_data);
		205	return ERR_PTR(ret);
192	}	206	}
193	EXPORT_SYMBOL(ib_umem_odp_alloc_child);	207	EXPORT_SYMBOL(ib_umem_odp_alloc_child);
194		208

drivers/infiniband/core/uverbs_cmd.c+0−9

@@ -1445,16 +1445,7 @@ static int create_qp(struct uverbs_attr_bundle *attrs, · 1444 unmodified lines
1445	if (ret)	1445	if (ret)
1446	goto err_cb;	1446	goto err_cb;
1447		1447
1448	qp->pd = pd;
1449	qp->send_cq = attr.send_cq;
1450	qp->recv_cq = attr.recv_cq;
1451	qp->srq = attr.srq;
1452	qp->rwq_ind_tbl = ind_tbl;
1453	qp->event_handler = attr.event_handler;
1454	qp->qp_type = attr.qp_type;
1455	atomic_set(&qp->usecnt, 0);
1456	atomic_inc(&pd->usecnt);	1448	atomic_inc(&pd->usecnt);
1457	qp->port = 0;
1458	if (attr.send_cq)	1449	if (attr.send_cq)
1459	atomic_inc(&attr.send_cq->usecnt);	1450	atomic_inc(&attr.send_cq->usecnt);
1460	if (attr.recv_cq)	1451	if (attr.recv_cq)

drivers/infiniband/core/verbs.c+0−10

@@ -1185,16 +1185,6 @@ struct ib_qp ib_create_qp_user(struct ib_pd pd, · 1184 unmodified lines
1185	if (ret)	1185	if (ret)
1186	goto err;	1186	goto err;
1187		1187
1188	qp->qp_type = qp_init_attr->qp_type;
1189	qp->rwq_ind_tbl = qp_init_attr->rwq_ind_tbl;
1190
1191	atomic_set(&qp->usecnt, 0);
1192	qp->mrs_used = 0;
1193	spin_lock_init(&qp->mr_lock);
1194	INIT_LIST_HEAD(&qp->rdma_mrs);
1195	INIT_LIST_HEAD(&qp->sig_mrs);
1196	qp->port = 0;
1197
1198	if (qp_init_attr->qp_type == IB_QPT_XRC_TGT) {	1188	if (qp_init_attr->qp_type == IB_QPT_XRC_TGT) {
1199	struct ib_qp *xrc_qp =	1189	struct ib_qp *xrc_qp =
1200	create_xrc_qp_user(qp, qp_init_attr, udata);	1190	create_xrc_qp_user(qp, qp_init_attr, udata);

drivers/infiniband/hw/hfi1/verbs.c+3−1

 				       opa_get_lid(packet->dlid, 9B));
 		if (!mcast)
 			goto drop;
+		rcu_read_lock();
 		list_for_each_entry_rcu(p, &mcast->qp_list, list) {
 			packet->qp = p->qp;
 			if (hfi1_do_pkey_check(packet))
-				goto drop;
+				goto unlock_drop;
 			spin_lock_irqsave(&packet->qp->r_lock, flags);
 			packet_handler = qp_ok(packet);
 			if (likely(packet_handler))
 				ibp->rvp.n_pkt_drops++;
 			spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 		}
+		rcu_read_unlock();
 		/*
 		 * Notify rvt_multicast_detach() if it is waiting for us
 		 * to finish.

drivers/infiniband/hw/mlx5/mlx5_ib.h+1−0

@@ -636,6 +636,7 @@ struct mlx5_ib_mr { · 635 unmodified lines
636		636
637	/* For ODP and implicit */	637	/* For ODP and implicit */
638	atomic_t num_deferred_work;	638	atomic_t num_deferred_work;
		639	wait_queue_head_t q_deferred_work;
639	struct xarray implicit_children;	640	struct xarray implicit_children;
640	union {	641	union {
641	struct rcu_head rcu;	642	struct rcu_head rcu;

drivers/infiniband/hw/mlx5/odp.c+7−10

 	mr->parent = NULL;
 	mlx5_mr_cache_free(mr->dev, mr);
 	ib_umem_odp_release(odp);
-	atomic_dec(&imr->num_deferred_work);
+	if (atomic_dec_and_test(&imr->num_deferred_work))
+		wake_up(&imr->q_deferred_work);
 }
 static void free_implicit_child_mr_work(struct work_struct *work)
 	imr->umem = &umem_odp->umem;
 	imr->is_odp_implicit = true;
 	atomic_set(&imr->num_deferred_work, 0);
+	init_waitqueue_head(&imr->q_deferred_work);
 	xa_init(&imr->implicit_children);
 	err = mlx5_ib_update_xlt(imr, 0,
 	 * under xa_lock while the child is in the xarray. Thus at this point
 	 * it is only decreasing, and all work holding it is now on the wq.
 	 */
-	if (atomic_read(&imr->num_deferred_work)) {
+	wait_event(imr->q_deferred_work, !atomic_read(&imr->num_deferred_work));
-		flush_workqueue(system_unbound_wq);
-		WARN_ON(atomic_read(&imr->num_deferred_work));
-	}
 	/*
 	 * Fence the imr before we destroy the children. This allows us to
 	/* Wait for all running page-fault handlers to finish. */
 	synchronize_srcu(&mr->dev->odp_srcu);
-	if (atomic_read(&mr->num_deferred_work)) {
+	wait_event(mr->q_deferred_work, !atomic_read(&mr->num_deferred_work));
-		flush_workqueue(system_unbound_wq);
-		WARN_ON(atomic_read(&mr->num_deferred_work));
-	}
 	dma_fence_odp_mr(mr);
 }
 	u32 i;
 	for (i = 0; i < work->num_sge; ++i)
-		atomic_dec(&work->frags[i].mr->num_deferred_work);
+		if (atomic_dec_and_test(&work->frags[i].mr->num_deferred_work))
+			wake_up(&work->frags[i].mr->q_deferred_work);
 	kvfree(work);
 }

drivers/infiniband/hw/qib/qib_verbs.c+2−0

 		if (mcast == NULL)
 			goto drop;
 		this_cpu_inc(ibp->pmastats->n_multicast_rcv);
+		rcu_read_lock();
 		list_for_each_entry_rcu(p, &mcast->qp_list, list)
 			qib_qp_rcv(rcd, hdr, 1, data, tlen, p->qp);
+		rcu_read_unlock();
 		/*
 		 * Notify rvt_multicast_detach() if it is waiting for us
 		 * to finish.

drivers/infiniband/sw/siw/siw_main.c+3−3

 		{ .max_segment_size = SZ_2G };
 	base_dev->num_comp_vectors = num_possible_cpus();
+	xa_init_flags(&sdev->qp_xa, XA_FLAGS_ALLOC1);
+	xa_init_flags(&sdev->mem_xa, XA_FLAGS_ALLOC1);
 	ib_set_device_ops(base_dev, &siw_device_ops);
 	rv = ib_device_set_netdev(base_dev, netdev, 1);
 	if (rv)
 	sdev->attrs.max_srq_wr = SIW_MAX_SRQ_WR;
 	sdev->attrs.max_srq_sge = SIW_MAX_SGE;
-	xa_init_flags(&sdev->qp_xa, XA_FLAGS_ALLOC1);
-	xa_init_flags(&sdev->mem_xa, XA_FLAGS_ALLOC1);
 	INIT_LIST_HEAD(&sdev->cep_list);
 	INIT_LIST_HEAD(&sdev->qp_list);

drivers/interconnect/core.c+9−0

 		path->name = kasprintf(GFP_KERNEL, "%s-%s",
 				       src_node->name, dst_node->name);
+	if (!path->name) {
+		kfree(path);
+		return ERR_PTR(-ENOMEM);
+	}
 	return path;
 }
 EXPORT_SYMBOL_GPL(of_icc_get);
 	}
 	path->name = kasprintf(GFP_KERNEL, "%s-%s", src->name, dst->name);
+	if (!path->name) {
+		kfree(path);
+		path = ERR_PTR(-ENOMEM);
+	}
 out:
 	mutex_unlock(&icc_lock);
 	return path;

drivers/iommu/amd_iommu.c+2−2

@@ -3826,7 +3826,7 @@ int amd_iommu_activate_guest_mode(void *data) · 3825 unmodified lines
3826	entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;	3826	entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
3827		3827
3828	return modify_irte_ga(ir_data->irq_2_irte.devid,	3828	return modify_irte_ga(ir_data->irq_2_irte.devid,
3829	ir_data->irq_2_irte.index, entry, NULL);	3829	ir_data->irq_2_irte.index, entry, ir_data);
3830	}	3830	}
3831	EXPORT_SYMBOL(amd_iommu_activate_guest_mode);	3831	EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
3832		3832
@@ -3852,7 +3852,7 @@ int amd_iommu_deactivate_guest_mode(void *data) · 19 unmodified lines
3852	APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);	3852	APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
3853		3853
3854	return modify_irte_ga(ir_data->irq_2_irte.devid,	3854	return modify_irte_ga(ir_data->irq_2_irte.devid,
3855	ir_data->irq_2_irte.index, entry, NULL);	3855	ir_data->irq_2_irte.index, entry, ir_data);
3856	}	3856	}
3857	EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);	3857	EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
3858		3858

drivers/iommu/dma-iommu.c+8−8

@@ -177,15 +177,15 @@ static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie, · 176 unmodified lines
177	start -= iova_offset(iovad, start);	177	start -= iova_offset(iovad, start);
178	num_pages = iova_align(iovad, end - start) >> iova_shift(iovad);	178	num_pages = iova_align(iovad, end - start) >> iova_shift(iovad);
179		179
180	msi_page = kcalloc(num_pages, sizeof(*msi_page), GFP_KERNEL);
181	if (!msi_page)
182	return -ENOMEM;
183
184	for (i = 0; i < num_pages; i++) {	180	for (i = 0; i < num_pages; i++) {
185	msi_page[i].phys = start;	181	msi_page = kmalloc(sizeof(*msi_page), GFP_KERNEL);
186	msi_page[i].iova = start;	182	if (!msi_page)
187	INIT_LIST_HEAD(&msi_page[i].list);	183	return -ENOMEM;
188	list_add(&msi_page[i].list, &cookie->msi_page_list);	184
		185	msi_page->phys = start;
		186	msi_page->iova = start;
		187	INIT_LIST_HEAD(&msi_page->list);
		188	list_add(&msi_page->list, &cookie->msi_page_list);
189	start += iovad->granule;	189	start += iovad->granule;
190	}	190	}
191		191

drivers/iommu/dmar.c+17−7

 #include <linux/slab.h>
 #include <linux/iommu.h>
 #include <linux/numa.h>
+#include <linux/limits.h>
 #include <asm/irq_remapping.h>
 #include <asm/iommu_table.h>
 	BUG_ON(dev->is_virtfn);
+	/*
+	 * Ignore devices that have a domain number higher than what can
+	 * be looked up in DMAR, e.g. VMD subdevices with domain 0x10000
+	 */
+	if (pci_domain_nr(dev->bus) > U16_MAX)
+		return NULL;
 	/* Only generate path[] for device addition event */
 	if (event == BUS_NOTIFY_ADD_DEVICE)
 		for (tmp = dev; tmp; tmp = tmp->bus->self)
 {
 	struct dmar_drhd_unit *dmaru;
-	list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list)
+	list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list,
+				dmar_rcu_check())
 		if (dmaru->segment == drhd->segment &&
 		    dmaru->reg_base_addr == drhd->address)
 			return dmaru;
 	/* Check for NUL termination within the designated length */
 	if (strnlen(andd->device_name, header->length - 8) == header->length - 8) {
-		WARN_TAINT(1, TAINT_FIRMWARE_WORKAROUND,
+		pr_warn(FW_BUG
 			   "Your BIOS is broken; ANDD object name is not NUL-terminated\n"
 			   "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 			   dmi_get_system_info(DMI_BIOS_VENDOR),
 			   dmi_get_system_info(DMI_BIOS_VERSION),
 			   dmi_get_system_info(DMI_PRODUCT_VERSION));
+		add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 		return -EINVAL;
 	}
 	pr_info("ANDD device: %x name: %s\n", andd->device_number,
 			return 0;
 		}
 	}
-	WARN_TAINT(
+	pr_warn(FW_BUG
-		1, TAINT_FIRMWARE_WORKAROUND,
 		"Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n"
 		"BIOS vendor: %s; Ver: %s; Product Version: %s\n",
-		drhd->reg_base_addr,
+		rhsa->base_address,
 		dmi_get_system_info(DMI_BIOS_VENDOR),
 		dmi_get_system_info(DMI_BIOS_VERSION),
 		dmi_get_system_info(DMI_PRODUCT_VERSION));
+	add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 	return 0;
 }
 static void warn_invalid_dmar(u64 addr, const char *message)
 {
-	WARN_TAINT_ONCE(
+	pr_warn_once(FW_BUG
-		1, TAINT_FIRMWARE_WORKAROUND,
 		"Your BIOS is broken; DMAR reported at address %llx%s!\n"
 		"BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 		addr, message,
 		dmi_get_system_info(DMI_BIOS_VENDOR),
 		dmi_get_system_info(DMI_BIOS_VERSION),
 		dmi_get_system_info(DMI_PRODUCT_VERSION));
+	add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 }
 static int __ref

drivers/iommu/intel-iommu-debugfs.c+35−16

@@ -33,38 +33,42 @@ struct iommu_regset { · 32 unmodified lines
33		33
34	#define IOMMU_REGSET_ENTRY(_reg_) \	34	#define IOMMU_REGSET_ENTRY(_reg_) \
35	{ DMAR_##_reg_##_REG, __stringify(_reg_) }	35	{ DMAR_##_reg_##_REG, __stringify(_reg_) }
36	static const struct iommu_regset iommu_regs[] = {	36
		37	static const struct iommu_regset iommu_regs_32[] = {
37	IOMMU_REGSET_ENTRY(VER),	38	IOMMU_REGSET_ENTRY(VER),
38	IOMMU_REGSET_ENTRY(CAP),
39	IOMMU_REGSET_ENTRY(ECAP),
40	IOMMU_REGSET_ENTRY(GCMD),	39	IOMMU_REGSET_ENTRY(GCMD),
41	IOMMU_REGSET_ENTRY(GSTS),	40	IOMMU_REGSET_ENTRY(GSTS),
42	IOMMU_REGSET_ENTRY(RTADDR),
43	IOMMU_REGSET_ENTRY(CCMD),
44	IOMMU_REGSET_ENTRY(FSTS),	41	IOMMU_REGSET_ENTRY(FSTS),
45	IOMMU_REGSET_ENTRY(FECTL),	42	IOMMU_REGSET_ENTRY(FECTL),
46	IOMMU_REGSET_ENTRY(FEDATA),	43	IOMMU_REGSET_ENTRY(FEDATA),
47	IOMMU_REGSET_ENTRY(FEADDR),	44	IOMMU_REGSET_ENTRY(FEADDR),
48	IOMMU_REGSET_ENTRY(FEUADDR),	45	IOMMU_REGSET_ENTRY(FEUADDR),
49	IOMMU_REGSET_ENTRY(AFLOG),
50	IOMMU_REGSET_ENTRY(PMEN),	46	IOMMU_REGSET_ENTRY(PMEN),
51	IOMMU_REGSET_ENTRY(PLMBASE),	47	IOMMU_REGSET_ENTRY(PLMBASE),
52	IOMMU_REGSET_ENTRY(PLMLIMIT),	48	IOMMU_REGSET_ENTRY(PLMLIMIT),
		49	IOMMU_REGSET_ENTRY(ICS),
		50	IOMMU_REGSET_ENTRY(PRS),
		51	IOMMU_REGSET_ENTRY(PECTL),
		52	IOMMU_REGSET_ENTRY(PEDATA),
		53	IOMMU_REGSET_ENTRY(PEADDR),
		54	IOMMU_REGSET_ENTRY(PEUADDR),
		55	};
		56
		57	static const struct iommu_regset iommu_regs_64[] = {
		58	IOMMU_REGSET_ENTRY(CAP),
		59	IOMMU_REGSET_ENTRY(ECAP),
		60	IOMMU_REGSET_ENTRY(RTADDR),
		61	IOMMU_REGSET_ENTRY(CCMD),
		62	IOMMU_REGSET_ENTRY(AFLOG),
53	IOMMU_REGSET_ENTRY(PHMBASE),	63	IOMMU_REGSET_ENTRY(PHMBASE),
54	IOMMU_REGSET_ENTRY(PHMLIMIT),	64	IOMMU_REGSET_ENTRY(PHMLIMIT),
55	IOMMU_REGSET_ENTRY(IQH),	65	IOMMU_REGSET_ENTRY(IQH),
56	IOMMU_REGSET_ENTRY(IQT),	66	IOMMU_REGSET_ENTRY(IQT),
57	IOMMU_REGSET_ENTRY(IQA),	67	IOMMU_REGSET_ENTRY(IQA),
58	IOMMU_REGSET_ENTRY(ICS),
59	IOMMU_REGSET_ENTRY(IRTA),	68	IOMMU_REGSET_ENTRY(IRTA),
60	IOMMU_REGSET_ENTRY(PQH),	69	IOMMU_REGSET_ENTRY(PQH),
61	IOMMU_REGSET_ENTRY(PQT),	70	IOMMU_REGSET_ENTRY(PQT),
62	IOMMU_REGSET_ENTRY(PQA),	71	IOMMU_REGSET_ENTRY(PQA),
63	IOMMU_REGSET_ENTRY(PRS),
64	IOMMU_REGSET_ENTRY(PECTL),
65	IOMMU_REGSET_ENTRY(PEDATA),
66	IOMMU_REGSET_ENTRY(PEADDR),
67	IOMMU_REGSET_ENTRY(PEUADDR),
68	IOMMU_REGSET_ENTRY(MTRRCAP),	72	IOMMU_REGSET_ENTRY(MTRRCAP),
69	IOMMU_REGSET_ENTRY(MTRRDEF),	73	IOMMU_REGSET_ENTRY(MTRRDEF),
70	IOMMU_REGSET_ENTRY(MTRR_FIX64K_00000),	74	IOMMU_REGSET_ENTRY(MTRR_FIX64K_00000),
@@ -127,10 +131,16 @@ static int iommu_regset_show(struct seq_file m, void unused) · 56 unmodified lines
127	* by adding the offset to the pointer (virtual address).	131	* by adding the offset to the pointer (virtual address).
128	*/	132	*/
129	raw_spin_lock_irqsave(&iommu->register_lock, flag);	133	raw_spin_lock_irqsave(&iommu->register_lock, flag);
130	for (i = 0 ; i < ARRAY_SIZE(iommu_regs); i++) {	134	for (i = 0 ; i < ARRAY_SIZE(iommu_regs_32); i++) {
131	value = dmar_readq(iommu->reg + iommu_regs[i].offset);	135	value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);
		136	seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
		137	iommu_regs_32[i].regs, iommu_regs_32[i].offset,
		138	value);
		139	}
		140	for (i = 0 ; i < ARRAY_SIZE(iommu_regs_64); i++) {
		141	value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);
132	seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",	142	seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
133	iommu_regs[i].regs, iommu_regs[i].offset,	143	iommu_regs_64[i].regs, iommu_regs_64[i].offset,
134	value);	144	value);
135	}	145	}
136	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);	146	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
@@ -272,9 +282,16 @@ static int dmar_translation_struct_show(struct seq_file m, void unused) · 135 unmodified lines
272	{	282	{
273	struct dmar_drhd_unit *drhd;	283	struct dmar_drhd_unit *drhd;
274	struct intel_iommu *iommu;	284	struct intel_iommu *iommu;
		285	u32 sts;
275		286
276	rcu_read_lock();	287	rcu_read_lock();
277	for_each_active_iommu(iommu, drhd) {	288	for_each_active_iommu(iommu, drhd) {
		289	sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
		290	if (!(sts & DMA_GSTS_TES)) {
		291	seq_printf(m, "DMA Remapping is not enabled on %s\n",
		292	iommu->name);
		293	continue;
		294	}
278	root_tbl_walk(m, iommu);	295	root_tbl_walk(m, iommu);
279	seq_putc(m, '\n');	296	seq_putc(m, '\n');
280	}	297	}
@@ -415,6 +432,7 @@ static int ir_translation_struct_show(struct seq_file m, void unused) · 134 unmodified lines
415	struct dmar_drhd_unit *drhd;	432	struct dmar_drhd_unit *drhd;
416	struct intel_iommu *iommu;	433	struct intel_iommu *iommu;
417	u64 irta;	434	u64 irta;
		435	u32 sts;
418		436
419	rcu_read_lock();	437	rcu_read_lock();
420	for_each_active_iommu(iommu, drhd) {	438	for_each_active_iommu(iommu, drhd) {
@@ -424,7 +442,8 @@ static int ir_translation_struct_show(struct seq_file m, void unused) · 3 unmodified lines
424	seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",	442	seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",
425	iommu->name);	443	iommu->name);
426		444
427	if (iommu->ir_table) {	445	sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
		446	if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {
428	irta = virt_to_phys(iommu->ir_table->base);	447	irta = virt_to_phys(iommu->ir_table->base);
429	seq_printf(m, " IR table address:%llx\n", irta);	448	seq_printf(m, " IR table address:%llx\n", irta);
430	ir_tbl_remap_entry_show(m, iommu);	449	ir_tbl_remap_entry_show(m, iommu);

drivers/iommu/intel-iommu.c+19−9

 	/* we know that the this iommu should be at offset 0xa000 from vtbar */
 	drhd = dmar_find_matched_drhd_unit(pdev);
-	if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
+	if (!drhd || drhd->reg_base_addr - vtbar != 0xa000) {
-			    TAINT_FIRMWARE_WORKAROUND,
+		pr_warn_once(FW_BUG "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n");
-			    "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
+		add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 		pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
+	}
 }
 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
 	struct dmar_rmrr_unit *rmrru;
 	rmrr = (struct acpi_dmar_reserved_memory *)header;
-	if (rmrr_sanity_check(rmrr))
+	if (rmrr_sanity_check(rmrr)) {
-		WARN_TAINT(1, TAINT_FIRMWARE_WORKAROUND,
+		pr_warn(FW_BUG
 			   "Your BIOS is broken; bad RMRR [%#018Lx-%#018Lx]\n"
 			   "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 			   rmrr->base_address, rmrr->end_address,
 			   dmi_get_system_info(DMI_BIOS_VENDOR),
 			   dmi_get_system_info(DMI_BIOS_VERSION),
 			   dmi_get_system_info(DMI_PRODUCT_VERSION));
+		add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
+	}
 	rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
 	if (!rmrru)
 	down_write(&dmar_global_lock);
+	if (!no_iommu)
+		intel_iommu_debugfs_init();
 	if (no_iommu || dmar_disabled) {
 		/*
 		 * We exit the function here to ensure IOMMU's remapping and
 	init_iommu_pm_ops();
+	down_read(&dmar_global_lock);
 	for_each_active_iommu(iommu, drhd) {
 		iommu_device_sysfs_add(&iommu->iommu, NULL,
 				       intel_iommu_groups,
 		iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops);
 		iommu_device_register(&iommu->iommu);
 	}
+	up_read(&dmar_global_lock);
 	bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
 	if (si_domain && !hw_pass_through)
 	down_read(&dmar_global_lock);
 	if (probe_acpi_namespace_devices())
 		pr_warn("ACPI name space devices didn't probe correctly\n");
-	up_read(&dmar_global_lock);
 	/* Finally, we enable the DMA remapping hardware. */
 	for_each_iommu(iommu, drhd) {
 		iommu_disable_protect_mem_regions(iommu);
 	}
+	up_read(&dmar_global_lock);
 	pr_info("Intel(R) Virtualization Technology for Directed I/O\n");
 	intel_iommu_enabled = 1;
-	intel_iommu_debugfs_init();
 	return 0;
 	u64 phys = 0;
 	pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
-	if (pte)
+	if (pte && dma_pte_present(pte))
-		phys = dma_pte_addr(pte);
+		phys = dma_pte_addr(pte) +
+			(iova & (BIT_MASK(level_to_offset_bits(level) +
+						VTD_PAGE_SHIFT) - 1));
 	return phys;
 }

drivers/iommu/io-pgtable-arm.c+2−2

@@ -468,7 +468,7 @@ static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova, · 467 unmodified lines
468	arm_lpae_iopte *ptep = data->pgd;	468	arm_lpae_iopte *ptep = data->pgd;
469	int ret, lvl = data->start_level;	469	int ret, lvl = data->start_level;
470	arm_lpae_iopte prot;	470	arm_lpae_iopte prot;
471	long iaext = (long)iova >> cfg->ias;	471	long iaext = (s64)iova >> cfg->ias;
472		472
473	/* If no access, then nothing to do */	473	/* If no access, then nothing to do */
474	if (!(iommu_prot & (IOMMU_READ \| IOMMU_WRITE)))	474	if (!(iommu_prot & (IOMMU_READ \| IOMMU_WRITE)))
@@ -645,7 +645,7 @@ static size_t arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova, · 170 unmodified lines
645	struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);	645	struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
646	struct io_pgtable_cfg *cfg = &data->iop.cfg;	646	struct io_pgtable_cfg *cfg = &data->iop.cfg;
647	arm_lpae_iopte *ptep = data->pgd;	647	arm_lpae_iopte *ptep = data->pgd;
648	long iaext = (long)iova >> cfg->ias;	648	long iaext = (s64)iova >> cfg->ias;
649		649
650	if (WARN_ON(!size \|\| (size & cfg->pgsize_bitmap) != size))	650	if (WARN_ON(!size \|\| (size & cfg->pgsize_bitmap) != size))
651	return 0;	651	return 0;

drivers/irqchip/irq-gic-v3.c+29−1

@@ -34,6 +34,7 @@ · 33 unmodified lines
34	#define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)	34	#define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
35		35
36	#define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)	36	#define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
		37	#define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
37		38
38	struct redist_region {	39	struct redist_region {
39	void __iomem *redist_base;	40	void __iomem *redist_base;
@@ -1464,6 +1465,15 @@ static bool gic_enable_quirk_msm8996(void *data) · 1424 unmodified lines
1464	return true;	1465	return true;
1465	}	1466	}
1466		1467
		1468	static bool gic_enable_quirk_cavium_38539(void *data)
		1469	{
		1470	struct gic_chip_data *d = data;
		1471
		1472	d->flags \|= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
		1473
		1474	return true;
		1475	}
		1476
1467	static bool gic_enable_quirk_hip06_07(void *data)	1477	static bool gic_enable_quirk_hip06_07(void *data)
1468	{	1478	{
1469	struct gic_chip_data *d = data;	1479	struct gic_chip_data *d = data;
@@ -1502,6 +1512,19 @@ static const struct gic_quirk gic_quirks[] = { · 32 unmodified lines
1502	.mask = 0xffffffff,	1512	.mask = 0xffffffff,
1503	.init = gic_enable_quirk_hip06_07,	1513	.init = gic_enable_quirk_hip06_07,
1504	},	1514	},
		1515	{
		1516	/*
		1517	* Reserved register accesses generate a Synchronous
		1518	* External Abort. This erratum applies to:
		1519	* - ThunderX: CN88xx
		1520	* - OCTEON TX: CN83xx, CN81xx
		1521	* - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
		1522	*/
		1523	.desc = "GICv3: Cavium erratum 38539",
		1524	.iidr = 0xa000034c,
		1525	.mask = 0xe8f00fff,
		1526	.init = gic_enable_quirk_cavium_38539,
		1527	},
1505	{	1528	{
1506	}	1529	}
1507	};	1530	};
@@ -1577,7 +1600,12 @@ static int __init gic_init_bases(void __iomem *dist_base, · 69 unmodified lines
1577	pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);	1600	pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
1578	pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);	1601	pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
1579		1602
1580	gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);	1603	/*
		1604	* ThunderX1 explodes on reading GICD_TYPER2, in violation of the
		1605	* architecture spec (which says that reserved registers are RES0).
		1606	*/
		1607	if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
		1608	gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
1581		1609
1582	gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,	1610	gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1583	&gic_data);	1611	&gic_data);

drivers/macintosh/therm_windtunnel.c+31−21

@@ -300,9 +300,11 @@ static int control_loop(void *dummy) · 299 unmodified lines
300	/* i2c probing and setup */	300	/* i2c probing and setup */
301	/************************************************************************/	301	/************************************************************************/
302		302
303	static int	303	static void do_attach(struct i2c_adapter *adapter)
304	do_attach( struct i2c_adapter *adapter )
305	{	304	{
		305	struct i2c_board_info info = { };
		306	struct device_node *np;
		307
306	/* scan 0x48-0x4f (DS1775) and 0x2c-2x2f (ADM1030) */	308	/* scan 0x48-0x4f (DS1775) and 0x2c-2x2f (ADM1030) */
307	static const unsigned short scan_ds1775[] = {	309	static const unsigned short scan_ds1775[] = {
308	0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,	310	0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
@@ -313,25 +315,24 @@ do_attach( struct i2c_adapter *adapter ) · 4 unmodified lines
313	I2C_CLIENT_END	315	I2C_CLIENT_END
314	};	316	};
315		317
316	if( strncmp(adapter->name, "uni-n", 5) )	318	if (x.running \|\| strncmp(adapter->name, "uni-n", 5))
317	return 0;	319	return;
318
319	if( !x.running ) {
320	struct i2c_board_info info;
321		320
322	memset(&info, 0, sizeof(struct i2c_board_info));	321	np = of_find_compatible_node(adapter->dev.of_node, NULL, "MAC,ds1775");
323	strlcpy(info.type, "therm_ds1775", I2C_NAME_SIZE);	322	if (np) {
		323	of_node_put(np);
		324	} else {
		325	strlcpy(info.type, "MAC,ds1775", I2C_NAME_SIZE);
324	i2c_new_probed_device(adapter, &info, scan_ds1775, NULL);	326	i2c_new_probed_device(adapter, &info, scan_ds1775, NULL);
		327	}
325		328
326	strlcpy(info.type, "therm_adm1030", I2C_NAME_SIZE);	329	np = of_find_compatible_node(adapter->dev.of_node, NULL, "MAC,adm1030");
		330	if (np) {
		331	of_node_put(np);
		332	} else {
		333	strlcpy(info.type, "MAC,adm1030", I2C_NAME_SIZE);
327	i2c_new_probed_device(adapter, &info, scan_adm1030, NULL);	334	i2c_new_probed_device(adapter, &info, scan_adm1030, NULL);
328
329	if( x.thermostat && x.fan ) {
330	x.running = 1;
331	x.poll_task = kthread_run(control_loop, NULL, "g4fand");
332	}
333	}	335	}
334	return 0;
335	}	336	}
336		337
337	static int	338	static int
@@ -404,8 +405,8 @@ out: · 66 unmodified lines
404	enum chip { ds1775, adm1030 };	405	enum chip { ds1775, adm1030 };
405		406
406	static const struct i2c_device_id therm_windtunnel_id[] = {	407	static const struct i2c_device_id therm_windtunnel_id[] = {
407	{ "therm_ds1775", ds1775 },	408	{ "MAC,ds1775", ds1775 },
408	{ "therm_adm1030", adm1030 },	409	{ "MAC,adm1030", adm1030 },
409	{ }	410	{ }
410	};	411	};
411	MODULE_DEVICE_TABLE(i2c, therm_windtunnel_id);	412	MODULE_DEVICE_TABLE(i2c, therm_windtunnel_id);
@@ -414,6 +415,7 @@ static int · 2 unmodified lines
414	do_probe(struct i2c_client cl, const struct i2c_device_id id)	415	do_probe(struct i2c_client cl, const struct i2c_device_id id)
415	{	416	{
416	struct i2c_adapter *adapter = cl->adapter;	417	struct i2c_adapter *adapter = cl->adapter;
		418	int ret = 0;
417		419
418	if( !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA	420	if( !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA
419	\| I2C_FUNC_SMBUS_WRITE_BYTE) )	421	\| I2C_FUNC_SMBUS_WRITE_BYTE) )
@@ -421,11 +423,19 @@ do_probe(struct i2c_client cl, const struct i2c_device_id id) · 1 unmodified line
421		423
422	switch (id->driver_data) {	424	switch (id->driver_data) {
423	case adm1030:	425	case adm1030:
424	return attach_fan( cl );	426	ret = attach_fan(cl);
		427	break;
425	case ds1775:	428	case ds1775:
426	return attach_thermostat(cl);	429	ret = attach_thermostat(cl);
		430	break;
427	}	431	}
428	return 0;	432
		433	if (!x.running && x.thermostat && x.fan) {
		434	x.running = 1;
		435	x.poll_task = kthread_run(control_loop, NULL, "g4fand");
		436	}
		437
		438	return ret;
429	}	439	}
430		440
431	static struct i2c_driver g4fan_driver = {	441	static struct i2c_driver g4fan_driver = {

drivers/macintosh/windfarm_ad7417_sensor.c+7−0

 };
 MODULE_DEVICE_TABLE(i2c, wf_ad7417_id);
+static const struct of_device_id wf_ad7417_of_id[] = {
+	{ .compatible = "ad7417", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, wf_ad7417_of_id);
 static struct i2c_driver wf_ad7417_driver = {
 	.driver = {
 		.name	= "wf_ad7417",
+		.of_match_table = wf_ad7417_of_id,
 	},
 	.probe		= wf_ad7417_probe,
 	.remove		= wf_ad7417_remove,

drivers/macintosh/windfarm_fcu_controls.c+7−0

 };
 MODULE_DEVICE_TABLE(i2c, wf_fcu_id);
+static const struct of_device_id wf_fcu_of_id[] = {
+	{ .compatible = "fcu", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, wf_fcu_of_id);
 static struct i2c_driver wf_fcu_driver = {
 	.driver = {
 		.name	= "wf_fcu",
+		.of_match_table = wf_fcu_of_id,
 	},
 	.probe		= wf_fcu_probe,
 	.remove		= wf_fcu_remove,

drivers/macintosh/windfarm_lm75_sensor.c+15−1

 #include <linux/init.h>
 #include <linux/wait.h>
 #include <linux/i2c.h>
+#include <linux/of_device.h>
 #include <asm/prom.h>
 #include <asm/machdep.h>
 #include <asm/io.h>
 			 const struct i2c_device_id *id)
 {
 	struct wf_lm75_sensor *lm;
-	int rc, ds1775 = id->driver_data;
+	int rc, ds1775;
 	const char *name, *loc;
+	if (id)
+		ds1775 = id->driver_data;
+	else
+		ds1775 = !!of_device_get_match_data(&client->dev);
 	DBG("wf_lm75: creating  %s device at address 0x%02x\n",
 	    ds1775 ? "ds1775" : "lm75", client->addr);
 };
 MODULE_DEVICE_TABLE(i2c, wf_lm75_id);
+static const struct of_device_id wf_lm75_of_id[] = {
+	{ .compatible = "lm75", .data = (void *)0},
+	{ .compatible = "ds1775", .data = (void *)1 },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, wf_lm75_of_id);
 static struct i2c_driver wf_lm75_driver = {
 	.driver = {
 		.name	= "wf_lm75",
+		.of_match_table = wf_lm75_of_id,
 	},
 	.probe		= wf_lm75_probe,
 	.remove		= wf_lm75_remove,

drivers/macintosh/windfarm_lm87_sensor.c+7−0

 };
 MODULE_DEVICE_TABLE(i2c, wf_lm87_id);
+static const struct of_device_id wf_lm87_of_id[] = {
+	{ .compatible = "lm87cimt", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, wf_lm87_of_id);
 static struct i2c_driver wf_lm87_driver = {
 	.driver = {
 		.name	= "wf_lm87",
+		.of_match_table = wf_lm87_of_id,
 	},
 	.probe		= wf_lm87_probe,
 	.remove		= wf_lm87_remove,

drivers/macintosh/windfarm_max6690_sensor.c+7−0

 };
 MODULE_DEVICE_TABLE(i2c, wf_max6690_id);
+static const struct of_device_id wf_max6690_of_id[] = {
+	{ .compatible = "max6690", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, wf_max6690_of_id);
 static struct i2c_driver wf_max6690_driver = {
 	.driver = {
 		.name		= "wf_max6690",
+		.of_match_table = wf_max6690_of_id,
 	},
 	.probe		= wf_max6690_probe,
 	.remove		= wf_max6690_remove,

drivers/macintosh/windfarm_smu_sat.c+7−0

 };
 MODULE_DEVICE_TABLE(i2c, wf_sat_id);
+static const struct of_device_id wf_sat_of_id[] = {
+	{ .compatible = "smu-sat", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, wf_sat_of_id);
 static struct i2c_driver wf_sat_driver = {
 	.driver = {
 		.name		= "wf_smu_sat",
+		.of_match_table = wf_sat_of_id,
 	},
 	.probe		= wf_sat_probe,
 	.remove		= wf_sat_remove,

drivers/md/bcache/alloc.c+2−16

@@ -67,7 +67,6 @@ · 66 unmodified lines
67	#include <linux/blkdev.h>	67	#include <linux/blkdev.h>
68	#include <linux/kthread.h>	68	#include <linux/kthread.h>
69	#include <linux/random.h>	69	#include <linux/random.h>
70	#include <linux/sched/signal.h>
71	#include <trace/events/bcache.h>	70	#include <trace/events/bcache.h>
72		71
73	#define MAX_OPEN_BUCKETS 128	72	#define MAX_OPEN_BUCKETS 128
@@ -734,21 +733,8 @@ int bch_open_buckets_alloc(struct cache_set *c) · 660 unmodified lines
734		733
735	int bch_cache_allocator_start(struct cache *ca)	734	int bch_cache_allocator_start(struct cache *ca)
736	{	735	{
737	struct task_struct *k;	736	struct task_struct *k = kthread_run(bch_allocator_thread,
738		737	ca, "bcache_allocator");
739	/*
740	* In case previous btree check operation occupies too many
741	* system memory for bcache btree node cache, and the
742	* registering process is selected by OOM killer. Here just
743	* ignore the SIGKILL sent by OOM killer if there is, to
744	* avoid kthread_run() being failed by pending signals. The
745	* bcache registering process will exit after the registration
746	* done.
747	*/
748	if (signal_pending(current))
749	flush_signals(current);
750
751	k = kthread_run(bch_allocator_thread, ca, "bcache_allocator");
752	if (IS_ERR(k))	738	if (IS_ERR(k))
753	return PTR_ERR(k);	739	return PTR_ERR(k);
754		740

drivers/md/bcache/btree.c+0−13

@@ -34,7 +34,6 @@ · 33 unmodified lines
34	#include <linux/random.h>	34	#include <linux/random.h>
35	#include <linux/rcupdate.h>	35	#include <linux/rcupdate.h>
36	#include <linux/sched/clock.h>	36	#include <linux/sched/clock.h>
37	#include <linux/sched/signal.h>
38	#include <linux/rculist.h>	37	#include <linux/rculist.h>
39	#include <linux/delay.h>	38	#include <linux/delay.h>
40	#include <trace/events/bcache.h>	39	#include <trace/events/bcache.h>
@@ -1914,18 +1913,6 @@ static int bch_gc_thread(void *arg) · 1873 unmodified lines
1914		1913
1915	int bch_gc_thread_start(struct cache_set *c)	1914	int bch_gc_thread_start(struct cache_set *c)
1916	{	1915	{
1917	/*
1918	* In case previous btree check operation occupies too many
1919	* system memory for bcache btree node cache, and the
1920	* registering process is selected by OOM killer. Here just
1921	* ignore the SIGKILL sent by OOM killer if there is, to
1922	* avoid kthread_run() being failed by pending signals. The
1923	* bcache registering process will exit after the registration
1924	* done.
1925	*/
1926	if (signal_pending(current))
1927	flush_signals(current);
1928
1929	c->gc_thread = kthread_run(bch_gc_thread, c, "bcache_gc");	1916	c->gc_thread = kthread_run(bch_gc_thread, c, "bcache_gc");
1930	return PTR_ERR_OR_ZERO(c->gc_thread);	1917	return PTR_ERR_OR_ZERO(c->gc_thread);
1931	}	1918	}

drivers/md/dm-bio-record.h+15−0

 struct dm_bio_details {
 	struct gendisk *bi_disk;
 	u8 bi_partno;
+	int __bi_remaining;
 	unsigned long bi_flags;
 	struct bvec_iter bi_iter;
+	bio_end_io_t *bi_end_io;
+#if defined(CONFIG_BLK_DEV_INTEGRITY)
+	struct bio_integrity_payload *bi_integrity;
+#endif
 };
 static inline void dm_bio_record(struct dm_bio_details *bd, struct bio *bio)
 	bd->bi_partno = bio->bi_partno;
 	bd->bi_flags = bio->bi_flags;
 	bd->bi_iter = bio->bi_iter;
+	bd->__bi_remaining = atomic_read(&bio->__bi_remaining);
+	bd->bi_end_io = bio->bi_end_io;
+#if defined(CONFIG_BLK_DEV_INTEGRITY)
+	bd->bi_integrity = bio_integrity(bio);
+#endif
 }
 static inline void dm_bio_restore(struct dm_bio_details *bd, struct bio *bio)
 	bio->bi_partno = bd->bi_partno;
 	bio->bi_flags = bd->bi_flags;
 	bio->bi_iter = bd->bi_iter;
+	atomic_set(&bio->__bi_remaining, bd->__bi_remaining);
+	bio->bi_end_io = bd->bi_end_io;
+#if defined(CONFIG_BLK_DEV_INTEGRITY)
+	bio->bi_integrity = bd->bi_integrity;
+#endif
 }
 #endif

drivers/md/dm-cache-target.c+3−3

@@ -2846,8 +2846,8 @@ static void cache_postsuspend(struct dm_target *ti) · 2845 unmodified lines
2846	prevent_background_work(cache);	2846	prevent_background_work(cache);
2847	BUG_ON(atomic_read(&cache->nr_io_migrations));	2847	BUG_ON(atomic_read(&cache->nr_io_migrations));
2848		2848
2849	cancel_delayed_work(&cache->waker);	2849	cancel_delayed_work_sync(&cache->waker);
2850	flush_workqueue(cache->wq);	2850	drain_workqueue(cache->wq);
2851	WARN_ON(cache->tracker.in_flight);	2851	WARN_ON(cache->tracker.in_flight);
2852		2852
2853	/*	2853	/*
@@ -3492,7 +3492,7 @@ static void cache_io_hints(struct dm_target ti, struct queue_limits limits) · 638 unmodified lines
3492		3492
3493	static struct target_type cache_target = {	3493	static struct target_type cache_target = {
3494	.name = "cache",	3494	.name = "cache",
3495	.version = {2, 1, 0},	3495	.version = {2, 2, 0},
3496	.module = THIS_MODULE,	3496	.module = THIS_MODULE,
3497	.ctr = cache_ctr,	3497	.ctr = cache_ctr,
3498	.dtr = cache_dtr,	3498	.dtr = cache_dtr,

drivers/md/dm-integrity.c+43−41

  * This file is released under the GPL.
  */
+#include "dm-bio-record.h"
 #include <linux/compiler.h>
 #include <linux/module.h>
 #include <linux/device-mapper.h>
 	__u8 log2_blocks_per_bitmap_bit;
 	unsigned char mode;
-	int suspending;
 	int failed;
 	struct crypto_shash *internal_hash;
+	struct dm_target *ti;
 	/* these variables are locked with endio_wait.lock */
 	struct rb_root in_progress;
 	struct list_head wait_list;
 	wait_queue_head_t endio_wait;
 	struct workqueue_struct *wait_wq;
+	struct workqueue_struct *offload_wq;
 	unsigned char commit_seq;
 	commit_id_t commit_ids[N_COMMIT_IDS];
 	struct completion *completion;
-	struct gendisk *orig_bi_disk;
+	struct dm_bio_details bio_details;
-	u8 orig_bi_partno;
-	bio_end_io_t *orig_bi_end_io;
-	struct bio_integrity_payload *orig_bi_integrity;
-	struct bvec_iter orig_bi_iter;
 };
 struct journal_completion {
 			dio->range.logical_sector += dio->range.n_sectors;
 			bio_advance(bio, dio->range.n_sectors << SECTOR_SHIFT);
 			INIT_WORK(&dio->work, integrity_bio_wait);
-			queue_work(ic->wait_wq, &dio->work);
+			queue_work(ic->offload_wq, &dio->work);
 			return;
 		}
 		do_endio_flush(ic, dio);
 {
 	struct dm_integrity_io *dio = dm_per_bio_data(bio, sizeof(struct dm_integrity_io));
-	bio->bi_iter = dio->orig_bi_iter;
+	dm_bio_restore(&dio->bio_details, bio);
-	bio->bi_disk = dio->orig_bi_disk;
+	if (bio->bi_integrity)
-	bio->bi_partno = dio->orig_bi_partno;
-	if (dio->orig_bi_integrity) {
-		bio->bi_integrity = dio->orig_bi_integrity;
 		bio->bi_opf |= REQ_INTEGRITY;
-	}
-	bio->bi_end_io = dio->orig_bi_end_io;
 	if (dio->completion)
 		complete(dio->completion);
 			}
 		}
-		__bio_for_each_segment(bv, bio, iter, dio->orig_bi_iter) {
+		__bio_for_each_segment(bv, bio, iter, dio->bio_details.bi_iter) {
 			unsigned pos;
 			char *mem, *checksums_ptr;
 		if (likely(checksums != checksums_onstack))
 			kfree(checksums);
 	} else {
-		struct bio_integrity_payload *bip = dio->orig_bi_integrity;
+		struct bio_integrity_payload *bip = dio->bio_details.bi_integrity;
 		if (bip) {
 			struct bio_vec biv;
 	if (need_sync_io && from_map) {
 		INIT_WORK(&dio->work, integrity_bio_wait);
-		queue_work(ic->metadata_wq, &dio->work);
+		queue_work(ic->offload_wq, &dio->work);
 		return;
 	}
 	} else
 		dio->completion = NULL;
-	dio->orig_bi_iter = bio->bi_iter;
+	dm_bio_record(&dio->bio_details, bio);
-	dio->orig_bi_disk = bio->bi_disk;
-	dio->orig_bi_partno = bio->bi_partno;
 	bio_set_dev(bio, ic->dev->bdev);
-	dio->orig_bi_integrity = bio_integrity(bio);
 	bio->bi_integrity = NULL;
 	bio->bi_opf &= ~REQ_INTEGRITY;
-	dio->orig_bi_end_io = bio->bi_end_io;
 	bio->bi_end_io = integrity_end_io;
 	bio->bi_iter.bi_size = dio->range.n_sectors << SECTOR_SHIFT;
 	generic_make_request(bio);
 	if (need_sync_io) {
 	unsigned prev_free_sectors;
 	/* the following test is not needed, but it tests the replay code */
-	if (READ_ONCE(ic->suspending) && !ic->meta_dev)
+	if (unlikely(dm_suspended(ic->ti)) && !ic->meta_dev)
 		return;
 	spin_lock_irq(&ic->endio_wait.lock);
 next_chunk:
-	if (unlikely(READ_ONCE(ic->suspending)))
+	if (unlikely(dm_suspended(ic->ti)))
 		goto unlock_ret;
 	range.logical_sector = le64_to_cpu(ic->sb->recalc_sector);
 				    dio->range.n_sectors, BITMAP_OP_TEST_ALL_SET)) {
 			remove_range(ic, &dio->range);
 			INIT_WORK(&dio->work, integrity_bio_wait);
-			queue_work(ic->wait_wq, &dio->work);
+			queue_work(ic->offload_wq, &dio->work);
 		} else {
 			block_bitmap_op(ic, ic->journal, dio->range.logical_sector,
 					dio->range.n_sectors, BITMAP_OP_SET);
 		remove_range(ic, &dio->range);
 		INIT_WORK(&dio->work, integrity_bio_wait);
-		queue_work(ic->wait_wq, &dio->work);
+		queue_work(ic->offload_wq, &dio->work);
 	}
 	queue_delayed_work(ic->commit_wq, &ic->bitmap_flush_work, ic->bitmap_flush_interval);
 	del_timer_sync(&ic->autocommit_timer);
-	WRITE_ONCE(ic->suspending, 1);
 	if (ic->recalc_wq)
 		drain_workqueue(ic->recalc_wq);
 #endif
 	}
-	WRITE_ONCE(ic->suspending, 0);
 	BUG_ON(!RB_EMPTY_ROOT(&ic->in_progress));
 	ic->journal_uptodate = true;
 	} else {
 		replay_journal(ic);
 		if (ic->mode == 'B') {
-			int mode;
 			ic->sb->flags |= cpu_to_le32(SB_FLAG_DIRTY_BITMAP);
 			ic->sb->log2_blocks_per_bitmap_bit = ic->log2_blocks_per_bitmap_bit;
 			r = sync_rw_sb(ic, REQ_OP_WRITE, REQ_FUA);
 			if (unlikely(r))
 				dm_integrity_io_error(ic, "writing superblock", r);
-			mode = ic->recalculate_flag ? BITMAP_OP_SET : BITMAP_OP_CLEAR;
+			block_bitmap_op(ic, ic->journal, 0, ic->provided_data_sectors, BITMAP_OP_CLEAR);
-			block_bitmap_op(ic, ic->journal, 0, ic->provided_data_sectors, mode);
+			block_bitmap_op(ic, ic->recalc_bitmap, 0, ic->provided_data_sectors, BITMAP_OP_CLEAR);
-			block_bitmap_op(ic, ic->recalc_bitmap, 0, ic->provided_data_sectors, mode);
+			block_bitmap_op(ic, ic->may_write_bitmap, 0, ic->provided_data_sectors, BITMAP_OP_CLEAR);
-			block_bitmap_op(ic, ic->may_write_bitmap, 0, ic->provided_data_sectors, mode);
+			if (ic->sb->flags & cpu_to_le32(SB_FLAG_RECALCULATING) &&
+			    le64_to_cpu(ic->sb->recalc_sector) < ic->provided_data_sectors) {
+				block_bitmap_op(ic, ic->journal, le64_to_cpu(ic->sb->recalc_sector),
+						ic->provided_data_sectors - le64_to_cpu(ic->sb->recalc_sector), BITMAP_OP_SET);
+				block_bitmap_op(ic, ic->recalc_bitmap, le64_to_cpu(ic->sb->recalc_sector),
+						ic->provided_data_sectors - le64_to_cpu(ic->sb->recalc_sector), BITMAP_OP_SET);
+				block_bitmap_op(ic, ic->may_write_bitmap, le64_to_cpu(ic->sb->recalc_sector),
+						ic->provided_data_sectors - le64_to_cpu(ic->sb->recalc_sector), BITMAP_OP_SET);
+			}
 			rw_journal_sectors(ic, REQ_OP_WRITE, REQ_FUA | REQ_SYNC, 0,
 					   ic->n_bitmap_blocks * (BITMAP_BLOCK_SIZE >> SECTOR_SHIFT), NULL);
 		}
 			DMEMIT(" meta_device:%s", ic->meta_dev->name);
 		if (ic->sectors_per_block != 1)
 			DMEMIT(" block_size:%u", ic->sectors_per_block << SECTOR_SHIFT);
-		if (ic->recalculate_flag)
+		if (ic->sb->flags & cpu_to_le32(SB_FLAG_RECALCULATING))
 			DMEMIT(" recalculate");
 		DMEMIT(" journal_sectors:%u", ic->initial_sectors - SB_SECTORS);
 		DMEMIT(" interleave_sectors:%u", 1U << ic->sb->log2_interleave_sectors);
 	}
 	ti->private = ic;
 	ti->per_io_data_size = sizeof(struct dm_integrity_io);
+	ic->ti = ti;
 	ic->in_progress = RB_ROOT;
 	INIT_LIST_HEAD(&ic->wait_list);
 		goto bad;
 	}
+	ic->offload_wq = alloc_workqueue("dm-integrity-offload", WQ_MEM_RECLAIM,
+					  METADATA_WORKQUEUE_MAX_ACTIVE);
+	if (!ic->offload_wq) {
+		ti->error = "Cannot allocate workqueue";
+		r = -ENOMEM;
+		goto bad;
+	}
 	ic->commit_wq = alloc_workqueue("dm-integrity-commit", WQ_MEM_RECLAIM, 1);
 	if (!ic->commit_wq) {
 		ti->error = "Cannot allocate workqueue";
 		destroy_workqueue(ic->metadata_wq);
 	if (ic->wait_wq)
 		destroy_workqueue(ic->wait_wq);
+	if (ic->offload_wq)
+		destroy_workqueue(ic->offload_wq);
 	if (ic->commit_wq)
 		destroy_workqueue(ic->commit_wq);
 	if (ic->writer_wq)
 static struct target_type integrity_target = {
 	.name			= "integrity",
-	.version		= {1, 4, 0},
+	.version		= {1, 5, 0},
 	.module			= THIS_MODULE,
 	.features		= DM_TARGET_SINGLETON | DM_TARGET_INTEGRITY,
 	.ctr			= dm_integrity_ctr,

drivers/md/dm-mpath.c+1−1

@@ -2053,7 +2053,7 @@ static int multipath_busy(struct dm_target *ti) · 2052 unmodified lines
2053	---------------------------------------------------------------/	2053	---------------------------------------------------------------/
2054	static struct target_type multipath_target = {	2054	static struct target_type multipath_target = {
2055	.name = "multipath",	2055	.name = "multipath",
2056	.version = {1, 13, 0},	2056	.version = {1, 14, 0},
2057	.features = DM_TARGET_SINGLETON \| DM_TARGET_IMMUTABLE \|	2057	.features = DM_TARGET_SINGLETON \| DM_TARGET_IMMUTABLE \|
2058	DM_TARGET_PASSES_INTEGRITY,	2058	DM_TARGET_PASSES_INTEGRITY,
2059	.module = THIS_MODULE,	2059	.module = THIS_MODULE,

drivers/md/dm-thin-metadata.c+1−1

 			DMWARN("%s: __commit_transaction() failed, error = %d",
 			       __func__, r);
 	}
+	pmd_write_unlock(pmd);
 	if (!pmd->fail_io)
 		__destroy_persistent_data_objects(pmd);
-	pmd_write_unlock(pmd);
 	kfree(pmd);
 	return 0;

drivers/md/dm-verity-target.c+1−1

@@ -1221,7 +1221,7 @@ bad: · 1220 unmodified lines
1221		1221
1222	static struct target_type verity_target = {	1222	static struct target_type verity_target = {
1223	.name = "verity",	1223	.name = "verity",
1224	.version = {1, 5, 0},	1224	.version = {1, 6, 0},
1225	.module = THIS_MODULE,	1225	.module = THIS_MODULE,
1226	.ctr = verity_ctr,	1226	.ctr = verity_ctr,
1227	.dtr = verity_dtr,	1227	.dtr = verity_dtr,

drivers/md/dm-writecache.c+12−4

@@ -625,6 +625,12 @@ static void writecache_add_to_freelist(struct dm_writecache *wc, struct wc_entry · 624 unmodified lines
625	wc->freelist_size++;	625	wc->freelist_size++;
626	}	626	}
627		627
		628	static inline void writecache_verify_watermark(struct dm_writecache *wc)
		629	{
		630	if (unlikely(wc->freelist_size + wc->writeback_size <= wc->freelist_high_watermark))
		631	queue_work(wc->writeback_wq, &wc->writeback_work);
		632	}
		633
628	static struct wc_entry writecache_pop_from_freelist(struct dm_writecache wc, sector_t expected_sector)	634	static struct wc_entry writecache_pop_from_freelist(struct dm_writecache wc, sector_t expected_sector)
629	{	635	{
630	struct wc_entry *e;	636	struct wc_entry *e;
@@ -650,8 +656,8 @@ static struct wc_entry writecache_pop_from_freelist(struct dm_writecache wc, s · 19 unmodified lines
650	list_del(&e->lru);	656	list_del(&e->lru);
651	}	657	}
652	wc->freelist_size--;	658	wc->freelist_size--;
653	if (unlikely(wc->freelist_size + wc->writeback_size <= wc->freelist_high_watermark))	659
654	queue_work(wc->writeback_wq, &wc->writeback_work);	660	writecache_verify_watermark(wc);
655		661
656	return e;	662	return e;
657	}	663	}
@@ -842,7 +848,7 @@ static void writecache_suspend(struct dm_target *ti) · 184 unmodified lines
842	}	848	}
843	wc_unlock(wc);	849	wc_unlock(wc);
844		850
845	flush_workqueue(wc->writeback_wq);	851	drain_workqueue(wc->writeback_wq);
846		852
847	wc_lock(wc);	853	wc_lock(wc);
848	if (flush_on_suspend)	854	if (flush_on_suspend)
@@ -965,6 +971,8 @@ erase_this: · 116 unmodified lines
965	writecache_commit_flushed(wc, false);	971	writecache_commit_flushed(wc, false);
966	}	972	}
967		973
		974	writecache_verify_watermark(wc);
		975
968	wc_unlock(wc);	976	wc_unlock(wc);
969	}	977	}
970		978
@@ -2312,7 +2320,7 @@ static void writecache_status(struct dm_target *ti, status_type_t type, · 1341 unmodified lines
2312		2320
2313	static struct target_type writecache_target = {	2321	static struct target_type writecache_target = {
2314	.name = "writecache",	2322	.name = "writecache",
2315	.version = {1, 1, 1},	2323	.version = {1, 2, 0},
2316	.module = THIS_MODULE,	2324	.module = THIS_MODULE,
2317	.ctr = writecache_ctr,	2325	.ctr = writecache_ctr,
2318	.dtr = writecache_dtr,	2326	.dtr = writecache_dtr,

drivers/md/dm-zoned-target.c+5−5

@@ -533,8 +533,9 @@ static int dmz_queue_chunk_work(struct dmz_target dmz, struct bio bio) · 532 unmodified lines
533		533
534	/* Get the BIO chunk work. If one is not active yet, create one */	534	/* Get the BIO chunk work. If one is not active yet, create one */
535	cw = radix_tree_lookup(&dmz->chunk_rxtree, chunk);	535	cw = radix_tree_lookup(&dmz->chunk_rxtree, chunk);
536	if (!cw) {	536	if (cw) {
537		537	dmz_get_chunk_work(cw);
		538	} else {
538	/* Create a new chunk work */	539	/* Create a new chunk work */
539	cw = kmalloc(sizeof(struct dm_chunk_work), GFP_NOIO);	540	cw = kmalloc(sizeof(struct dm_chunk_work), GFP_NOIO);
540	if (unlikely(!cw)) {	541	if (unlikely(!cw)) {
@@ -543,7 +544,7 @@ static int dmz_queue_chunk_work(struct dmz_target dmz, struct bio bio) · 2 unmodified lines
543	}	544	}
544		545
545	INIT_WORK(&cw->work, dmz_chunk_work);	546	INIT_WORK(&cw->work, dmz_chunk_work);
546	refcount_set(&cw->refcount, 0);	547	refcount_set(&cw->refcount, 1);
547	cw->target = dmz;	548	cw->target = dmz;
548	cw->chunk = chunk;	549	cw->chunk = chunk;
549	bio_list_init(&cw->bio_list);	550	bio_list_init(&cw->bio_list);
@@ -556,7 +557,6 @@ static int dmz_queue_chunk_work(struct dmz_target dmz, struct bio bio) · 6 unmodified lines
556	}	557	}
557		558
558	bio_list_add(&cw->bio_list, bio);	559	bio_list_add(&cw->bio_list, bio);
559	dmz_get_chunk_work(cw);
560		560
561	dmz_reclaim_bio_acc(dmz->reclaim);	561	dmz_reclaim_bio_acc(dmz->reclaim);
562	if (queue_work(dmz->chunk_wq, &cw->work))	562	if (queue_work(dmz->chunk_wq, &cw->work))
@@ -967,7 +967,7 @@ static int dmz_iterate_devices(struct dm_target *ti, · 404 unmodified lines
967		967
968	static struct target_type dmz_type = {	968	static struct target_type dmz_type = {
969	.name = "zoned",	969	.name = "zoned",
970	.version = {1, 0, 0},	970	.version = {1, 1, 0},
971	.features = DM_TARGET_SINGLETON \| DM_TARGET_ZONED_HM,	971	.features = DM_TARGET_SINGLETON \| DM_TARGET_ZONED_HM,
972	.module = THIS_MODULE,	972	.module = THIS_MODULE,
973	.ctr = dmz_ctr,	973	.ctr = dmz_ctr,

drivers/md/dm.c+11−11

 			 * With request-based DM we only need to check the
 			 * top-level queue for congestion.
 			 */
-			r = md->queue->backing_dev_info->wb.state & bdi_bits;
+			struct backing_dev_info *bdi = md->queue->backing_dev_info;
+			r = bdi->wb.congested->state & bdi_bits;
 		} else {
 			map = dm_get_live_table_fast(md);
 			if (map)
 static void dm_wq_work(struct work_struct *work);
-static void dm_init_normal_md_queue(struct mapped_device *md)
-{
-	/*
-	 * Initialize aspects of queue that aren't relevant for blk-mq
-	 */
-	md->queue->backing_dev_info->congested_data = md;
-	md->queue->backing_dev_info->congested_fn = dm_any_congested;
-}
 static void cleanup_mapped_device(struct mapped_device *md)
 {
 	if (md->wq)
 }
 EXPORT_SYMBOL_GPL(dm_get_queue_limits);
+static void dm_init_congested_fn(struct mapped_device *md)
+{
+	md->queue->backing_dev_info->congested_data = md;
+	md->queue->backing_dev_info->congested_fn = dm_any_congested;
+}
 /*
  * Setup the DM device's queue based on md's type
  */
 			DMERR("Cannot initialize queue for request-based dm-mq mapped device");
 			return r;
 		}
+		dm_init_congested_fn(md);
 		break;
 	case DM_TYPE_BIO_BASED:
 	case DM_TYPE_DAX_BIO_BASED:
 	case DM_TYPE_NVME_BIO_BASED:
-		dm_init_normal_md_queue(md);
+		dm_init_congested_fn(md);
 		break;
 	case DM_TYPE_NONE:
 		WARN_ON_ONCE(true);
 	map = dm_get_live_table(md, &srcu_idx);
 	if (!dm_suspended_md(md)) {
 		dm_table_presuspend_targets(map);
+		set_bit(DMF_SUSPENDED, &md->flags);
 		dm_table_postsuspend_targets(map);
 	}
 	/* dm_put_live_table must be before msleep, otherwise deadlock is possible */

drivers/media/mc/mc-entity.c+2−2

@@ -639,9 +639,9 @@ int media_get_pad_index(struct media_entity *entity, bool is_sink, · 638 unmodified lines
639	return -EINVAL;	639	return -EINVAL;
640		640
641	for (i = 0; i < entity->num_pads; i++) {	641	for (i = 0; i < entity->num_pads; i++) {
642	if (entity->pads[i].flags == MEDIA_PAD_FL_SINK)	642	if (entity->pads[i].flags & MEDIA_PAD_FL_SINK)
643	pad_is_sink = true;	643	pad_is_sink = true;
644	else if (entity->pads[i].flags == MEDIA_PAD_FL_SOURCE)	644	else if (entity->pads[i].flags & MEDIA_PAD_FL_SOURCE)
645	pad_is_sink = false;	645	pad_is_sink = false;
646	else	646	else
647	continue; /* This is an error! */	647	continue; /* This is an error! */

drivers/media/platform/vicodec/codec-v4l2-fwht.c+9−25

 	{ V4L2_PIX_FMT_BGR24,   3, 3, 1, 3, 3, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
 	{ V4L2_PIX_FMT_RGB24,   3, 3, 1, 3, 3, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
 	{ V4L2_PIX_FMT_HSV24,   3, 3, 1, 3, 3, 1, 1, 3, 1, FWHT_FL_PIXENC_HSV},
-	{ V4L2_PIX_FMT_BGR32,   4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
+	{ V4L2_PIX_FMT_BGR32,   4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
-	{ V4L2_PIX_FMT_XBGR32,  4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
+	{ V4L2_PIX_FMT_XBGR32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
 	{ V4L2_PIX_FMT_ABGR32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
-	{ V4L2_PIX_FMT_RGB32,   4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
+	{ V4L2_PIX_FMT_RGB32,   4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
-	{ V4L2_PIX_FMT_XRGB32,  4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
+	{ V4L2_PIX_FMT_XRGB32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
 	{ V4L2_PIX_FMT_ARGB32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
-	{ V4L2_PIX_FMT_BGRX32,  4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
+	{ V4L2_PIX_FMT_BGRX32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
 	{ V4L2_PIX_FMT_BGRA32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
-	{ V4L2_PIX_FMT_RGBX32,  4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
+	{ V4L2_PIX_FMT_RGBX32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
 	{ V4L2_PIX_FMT_RGBA32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
-	{ V4L2_PIX_FMT_HSV32,   4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_HSV},
+	{ V4L2_PIX_FMT_HSV32,   4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_HSV},
 	{ V4L2_PIX_FMT_GREY,    1, 1, 1, 1, 0, 1, 1, 1, 1, FWHT_FL_PIXENC_RGB},
 };
 	case V4L2_PIX_FMT_RGB32:
 	case V4L2_PIX_FMT_XRGB32:
 	case V4L2_PIX_FMT_HSV32:
-		rf->cr = rf->luma + 1;
-		rf->cb = rf->cr + 2;
-		rf->luma += 2;
-		break;
-	case V4L2_PIX_FMT_BGR32:
-	case V4L2_PIX_FMT_XBGR32:
-		rf->cb = rf->luma;
-		rf->cr = rf->cb + 2;
-		rf->luma++;
-		break;
 	case V4L2_PIX_FMT_ARGB32:
 		rf->alpha = rf->luma;
 		rf->cr = rf->luma + 1;
 		rf->cb = rf->cr + 2;
 		rf->luma += 2;
 		break;
+	case V4L2_PIX_FMT_BGR32:
+	case V4L2_PIX_FMT_XBGR32:
 	case V4L2_PIX_FMT_ABGR32:
 		rf->cb = rf->luma;
 		rf->cr = rf->cb + 2;
 		rf->alpha = rf->cr + 1;
 		break;
 	case V4L2_PIX_FMT_BGRX32:
-		rf->cb = rf->luma + 1;
-		rf->cr = rf->cb + 2;
-		rf->luma += 2;
-		break;
 	case V4L2_PIX_FMT_BGRA32:
 		rf->alpha = rf->luma;
 		rf->cb = rf->luma + 1;
 		rf->luma += 2;
 		break;
 	case V4L2_PIX_FMT_RGBX32:
-		rf->cr = rf->luma;
-		rf->cb = rf->cr + 2;
-		rf->luma++;
-		break;
 	case V4L2_PIX_FMT_RGBA32:
 		rf->alpha = rf->luma + 3;
 		rf->cr = rf->luma;

drivers/media/usb/pulse8-cec/pulse8-cec.c+7−5

 	cancel_delayed_work_sync(&pulse8->ping_eeprom_work);
 	cancel_work_sync(&pulse8->irq_work);
 	cancel_work_sync(&pulse8->tx_work);
-	serio_close(pulse8->serio);
-	serio_set_drvdata(pulse8->serio, NULL);
 	kfree(pulse8);
 }
 	struct pulse8 *pulse8 = serio_get_drvdata(serio);
 	cec_unregister_adapter(pulse8->adap);
+	pulse8->serio = NULL;
+	serio_set_drvdata(serio, NULL);
+	serio_close(serio);
 }
 static int pulse8_setup(struct pulse8 *pulse8, struct serio *serio,
 	serio_set_drvdata(serio, pulse8);
 	INIT_WORK(&pulse8->irq_work, pulse8_irq_work_handler);
 	INIT_WORK(&pulse8->tx_work, pulse8_tx_work_handler);
+	INIT_DELAYED_WORK(&pulse8->ping_eeprom_work,
+			  pulse8_ping_eeprom_work_handler);
 	mutex_init(&pulse8->lock);
 	spin_lock_init(&pulse8->msg_lock);
 	pulse8->config_pending = false;
 		pulse8->restoring_config = true;
 	}
-	INIT_DELAYED_WORK(&pulse8->ping_eeprom_work,
-			  pulse8_ping_eeprom_work_handler);
 	schedule_delayed_work(&pulse8->ping_eeprom_work, PING_PERIOD);
 	return 0;
 close_serio:
+	pulse8->serio = NULL;
+	serio_set_drvdata(serio, NULL);
 	serio_close(serio);
 delete_adap:
 	cec_delete_adapter(pulse8->adap);
-	serio_set_drvdata(serio, NULL);
 free_device:
 	kfree(pulse8);
 	return err;

drivers/media/v4l2-core/v4l2-mem2mem.c+2−2

@@ -880,12 +880,12 @@ int v4l2_m2m_register_media_controller(struct v4l2_m2m_dev *m2m_dev, · 879 unmodified lines
880	goto err_rel_entity1;	880	goto err_rel_entity1;
881		881
882	/* Connect the three entities */	882	/* Connect the three entities */
883	ret = media_create_pad_link(m2m_dev->source, 0, &m2m_dev->proc, 1,	883	ret = media_create_pad_link(m2m_dev->source, 0, &m2m_dev->proc, 0,
884	MEDIA_LNK_FL_IMMUTABLE \| MEDIA_LNK_FL_ENABLED);	884	MEDIA_LNK_FL_IMMUTABLE \| MEDIA_LNK_FL_ENABLED);
885	if (ret)	885	if (ret)
886	goto err_rel_entity2;	886	goto err_rel_entity2;
887		887
888	ret = media_create_pad_link(&m2m_dev->proc, 0, &m2m_dev->sink, 0,	888	ret = media_create_pad_link(&m2m_dev->proc, 1, &m2m_dev->sink, 0,
889	MEDIA_LNK_FL_IMMUTABLE \| MEDIA_LNK_FL_ENABLED);	889	MEDIA_LNK_FL_IMMUTABLE \| MEDIA_LNK_FL_ENABLED);
890	if (ret)	890	if (ret)
891	goto err_rm_links0;	891	goto err_rm_links0;

drivers/misc/altera-stapl/altera.c+6−6

@@ -2112,8 +2112,8 @@ exit_done: · 2111 unmodified lines
2112	return status;	2112	return status;
2113	}	2113	}
2114		2114
2115	static int altera_get_note(u8 *p, s32 program_size,	2115	static int altera_get_note(u8 p, s32 program_size, s32 offset,
2116	s32 offset, char key, char *value, int length)	2116	char key, char value, int keylen, int vallen)
2117	/*	2117	/*
2118	* Gets key and value of NOTE fields in the JBC file.	2118	* Gets key and value of NOTE fields in the JBC file.
2119	* Can be called in two modes: if offset pointer is NULL,	2119	* Can be called in two modes: if offset pointer is NULL,
@@ -2170,7 +2170,7 @@ static int altera_get_note(u8 *p, s32 program_size, · 50 unmodified lines
2170	&p[note_table + (8 * i) + 4])];	2170	&p[note_table + (8 * i) + 4])];
2171		2171
2172	if (value != NULL)	2172	if (value != NULL)
2173	strlcpy(value, value_ptr, length);	2173	strlcpy(value, value_ptr, vallen);
2174		2174
2175	}	2175	}
2176	}	2176	}
@@ -2189,13 +2189,13 @@ static int altera_get_note(u8 *p, s32 program_size, · 12 unmodified lines
2189	strlcpy(key, &p[note_strings +	2189	strlcpy(key, &p[note_strings +
2190	get_unaligned_be32(	2190	get_unaligned_be32(
2191	&p[note_table + (8 * i)])],	2191	&p[note_table + (8 * i)])],
2192	length);	2192	keylen);
2193		2193
2194	if (value != NULL)	2194	if (value != NULL)
2195	strlcpy(value, &p[note_strings +	2195	strlcpy(value, &p[note_strings +
2196	get_unaligned_be32(	2196	get_unaligned_be32(
2197	&p[note_table + (8 * i) + 4])],	2197	&p[note_table + (8 * i) + 4])],
2198	length);	2198	vallen);
2199		2199
2200	*offset = i + 1;	2200	*offset = i + 1;
2201	}	2201	}
@@ -2449,7 +2449,7 @@ int altera_init(struct altera_config config, const struct firmware fw) · 247 unmodified lines
2449	__func__, (format_version == 2) ? "Jam STAPL" :	2449	__func__, (format_version == 2) ? "Jam STAPL" :
2450	"pre-standardized Jam 1.1");	2450	"pre-standardized Jam 1.1");
2451	while (altera_get_note((u8 *)fw->data, fw->size,	2451	while (altera_get_note((u8 *)fw->data, fw->size,
2452	&offset, key, value, 256) == 0)	2452	&offset, key, value, 32, 256) == 0)
2453	printk(KERN_INFO "%s: NOTE \"%s\" = \"%s\"\n",	2453	printk(KERN_INFO "%s: NOTE \"%s\" = \"%s\"\n",
2454	__func__, key, value);	2454	__func__, key, value);
2455	}	2455	}

drivers/misc/cardreader/rts5227.c+1−1

@@ -394,7 +394,7 @@ static const struct pcr_ops rts522a_pcr_ops = { · 393 unmodified lines
394	void rts522a_init_params(struct rtsx_pcr *pcr)	394	void rts522a_init_params(struct rtsx_pcr *pcr)
395	{	395	{
396	rts5227_init_params(pcr);	396	rts5227_init_params(pcr);
397		397	pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
398	pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;	398	pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
399		399
400	pcr->option.ocp_en = 1;	400	pcr->option.ocp_en = 1;

drivers/misc/cardreader/rts5249.c+2−0

 void rts524a_init_params(struct rtsx_pcr *pcr)
 {
 	rts5249_init_params(pcr);
+	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
 	pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
 	pcr->option.ltr_l1off_snooze_sspwrgate =
 		LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
 void rts525a_init_params(struct rtsx_pcr *pcr)
 {
 	rts5249_init_params(pcr);
+	pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
 	pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
 	pcr->option.ltr_l1off_snooze_sspwrgate =
 		LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;

drivers/misc/cardreader/rts5260.c+1−1

@@ -662,7 +662,7 @@ void rts5260_init_params(struct rtsx_pcr *pcr) · 661 unmodified lines
662	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;	662	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
663	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;	663	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
664	pcr->aspm_en = ASPM_L1_EN;	664	pcr->aspm_en = ASPM_L1_EN;
665	pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);	665	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
666	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);	666	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
667		667
668	pcr->ic_version = rts5260_get_ic_version(pcr);	668	pcr->ic_version = rts5260_get_ic_version(pcr);

drivers/misc/cardreader/rts5261.c+1−1

@@ -764,7 +764,7 @@ void rts5261_init_params(struct rtsx_pcr *pcr) · 763 unmodified lines
764	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;	764	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
765	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;	765	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
766	pcr->aspm_en = ASPM_L1_EN;	766	pcr->aspm_en = ASPM_L1_EN;
767	pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 27, 16);	767	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
768	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);	768	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
769		769
770	pcr->ic_version = rts5261_get_ic_version(pcr);	770	pcr->ic_version = rts5261_get_ic_version(pcr);

drivers/misc/eeprom/at24.c+2−1

 	 * chip is functional.
 	 */
 	err = at24_read(at24, 0, &test_byte, 1);
-	pm_runtime_idle(dev);
 	if (err) {
 		pm_runtime_disable(dev);
 		regulator_disable(at24->vcc_reg);
 		return -ENODEV;
 	}
+	pm_runtime_idle(dev);
 	if (writable)
 		dev_info(dev, "%u byte %s EEPROM, writable, %u bytes/write\n",
 			 byte_len, client->name, at24->write_max);

drivers/mmc/core/core.c+4−1

 	 * the erase operation does not exceed the max_busy_timeout, we should
 	 * use R1B response. Or we need to prevent the host from doing hw busy
 	 * detection, which is done by converting to a R1 response instead.
+	 * Note, some hosts requires R1B, which also means they are on their own
+	 * when it comes to deal with the busy timeout.
 	 */
-	if (card->host->max_busy_timeout &&
+	if (!(card->host->caps & MMC_CAP_NEED_RSP_BUSY) &&
+	    card->host->max_busy_timeout &&
 	    busy_timeout > card->host->max_busy_timeout) {
 		cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
 	} else {

drivers/mmc/core/mmc.c+5−2

 	 * If the max_busy_timeout of the host is specified, validate it against
 	 * the sleep cmd timeout. A failure means we need to prevent the host
 	 * from doing hw busy detection, which is done by converting to a R1
-	 * response instead of a R1B.
+	 * response instead of a R1B. Note, some hosts requires R1B, which also
+	 * means they are on their own when it comes to deal with the busy
+	 * timeout.
 	 */
-	if (host->max_busy_timeout && (timeout_ms > host->max_busy_timeout)) {
+	if (!(host->caps & MMC_CAP_NEED_RSP_BUSY) && host->max_busy_timeout &&
+	    (timeout_ms > host->max_busy_timeout)) {
 		cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
 	} else {
 		cmd.flags = MMC_RSP_R1B | MMC_CMD_AC;

drivers/mmc/core/mmc_ops.c+4−2

 	 * If the max_busy_timeout of the host is specified, make sure it's
 	 * enough to fit the used timeout_ms. In case it's not, let's instruct
 	 * the host to avoid HW busy detection, by converting to a R1 response
-	 * instead of a R1B.
+	 * instead of a R1B. Note, some hosts requires R1B, which also means
+	 * they are on their own when it comes to deal with the busy timeout.
 	 */
-	if (host->max_busy_timeout && (timeout_ms > host->max_busy_timeout))
+	if (!(host->caps & MMC_CAP_NEED_RSP_BUSY) && host->max_busy_timeout &&
+	    (timeout_ms > host->max_busy_timeout))
 		use_r1b_resp = false;
 	cmd.opcode = MMC_SWITCH;

drivers/mmc/host/rtsx_pci_sdmmc.c+8−5

@@ -606,19 +606,22 @@ static int sd_change_phase(struct realtek_pci_sdmmc *host, · 605 unmodified lines
606	u8 sample_point, bool rx)	606	u8 sample_point, bool rx)
607	{	607	{
608	struct rtsx_pcr *pcr = host->pcr;	608	struct rtsx_pcr *pcr = host->pcr;
609		609	u16 SD_VP_CTL = 0;
610	dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",	610	dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
611	__func__, rx ? "RX" : "TX", sample_point);	611	__func__, rx ? "RX" : "TX", sample_point);
612		612
613	rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);	613	rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
614	if (rx)	614	if (rx) {
		615	SD_VP_CTL = SD_VPRX_CTL;
615	rtsx_pci_write_register(pcr, SD_VPRX_CTL,	616	rtsx_pci_write_register(pcr, SD_VPRX_CTL,
616	PHASE_SELECT_MASK, sample_point);	617	PHASE_SELECT_MASK, sample_point);
617	else	618	} else {
		619	SD_VP_CTL = SD_VPTX_CTL;
618	rtsx_pci_write_register(pcr, SD_VPTX_CTL,	620	rtsx_pci_write_register(pcr, SD_VPTX_CTL,
619	PHASE_SELECT_MASK, sample_point);	621	PHASE_SELECT_MASK, sample_point);
620	rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);	622	}
621	rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET,	623	rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);
		624	rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,
622	PHASE_NOT_RESET);	625	PHASE_NOT_RESET);
623	rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);	626	rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
624	rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);	627	rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);

drivers/mmc/host/sdhci-acpi.c+82−2

@@ -23,6 +23,7 @@ · 22 unmodified lines
23	#include <linux/pm.h>	23	#include <linux/pm.h>
24	#include <linux/pm_runtime.h>	24	#include <linux/pm_runtime.h>
25	#include <linux/delay.h>	25	#include <linux/delay.h>
		26	#include <linux/dmi.h>
26		27
27	#include <linux/mmc/host.h>	28	#include <linux/mmc/host.h>
28	#include <linux/mmc/pm.h>	29	#include <linux/mmc/pm.h>
@@ -72,9 +73,16 @@ struct sdhci_acpi_host { · 43 unmodified lines
72	const struct sdhci_acpi_slot *slot;	73	const struct sdhci_acpi_slot *slot;
73	struct platform_device *pdev;	74	struct platform_device *pdev;
74	bool use_runtime_pm;	75	bool use_runtime_pm;
		76	bool is_intel;
		77	bool reset_signal_volt_on_suspend;
75	unsigned long private[0] ____cacheline_aligned;	78	unsigned long private[0] ____cacheline_aligned;
76	};	79	};
77		80
		81	enum {
		82	DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP = BIT(0),
		83	DMI_QUIRK_SD_NO_WRITE_PROTECT = BIT(1),
		84	};
		85
78	static inline void sdhci_acpi_priv(struct sdhci_acpi_host c)	86	static inline void sdhci_acpi_priv(struct sdhci_acpi_host c)
79	{	87	{
80	return (void *)c->private;	88	return (void *)c->private;
@@ -391,6 +399,8 @@ static int intel_probe_slot(struct platform_device pdev, struct acpi_device ad · 310 unmodified lines
391	host->mmc_host_ops.start_signal_voltage_switch =	399	host->mmc_host_ops.start_signal_voltage_switch =
392	intel_start_signal_voltage_switch;	400	intel_start_signal_voltage_switch;
393		401
		402	c->is_intel = true;
		403
394	return 0;	404	return 0;
395	}	405	}
396		406
@@ -647,6 +657,36 @@ static const struct acpi_device_id sdhci_acpi_ids[] = { · 250 unmodified lines
647	};	657	};
648	MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);	658	MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
649		659
		660	static const struct dmi_system_id sdhci_acpi_quirks[] = {
		661	{
		662	/*
		663	* The Lenovo Miix 320-10ICR has a bug in the _PS0 method of
		664	* the SHC1 ACPI device, this bug causes it to reprogram the
		665	* wrong LDO (DLDO3) to 1.8V if 1.8V modes are used and the
		666	* card is (runtime) suspended + resumed. DLDO3 is used for
		667	* the LCD and setting it to 1.8V causes the LCD to go black.
		668	*/
		669	.matches = {
		670	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
		671	DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
		672	},
		673	.driver_data = (void *)DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP,
		674	},
		675	{
		676	/*
		677	* The Acer Aspire Switch 10 (SW5-012) microSD slot always
		678	* reports the card being write-protected even though microSD
		679	* cards do not have a write-protect switch at all.
		680	*/
		681	.matches = {
		682	DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
		683	DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"),
		684	},
		685	.driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
		686	},
		687	{} /* Terminating entry */
		688	};
		689
650	static const struct sdhci_acpi_slot sdhci_acpi_get_slot(struct acpi_device adev)	690	static const struct sdhci_acpi_slot sdhci_acpi_get_slot(struct acpi_device adev)
651	{	691	{
652	const struct sdhci_acpi_uid_slot *u;	692	const struct sdhci_acpi_uid_slot *u;
@@ -663,17 +703,23 @@ static int sdhci_acpi_probe(struct platform_device *pdev) · 10 unmodified lines
663	struct device *dev = &pdev->dev;	703	struct device *dev = &pdev->dev;
664	const struct sdhci_acpi_slot *slot;	704	const struct sdhci_acpi_slot *slot;
665	struct acpi_device device, child;	705	struct acpi_device device, child;
		706	const struct dmi_system_id *id;
666	struct sdhci_acpi_host *c;	707	struct sdhci_acpi_host *c;
667	struct sdhci_host *host;	708	struct sdhci_host *host;
668	struct resource *iomem;	709	struct resource *iomem;
669	resource_size_t len;	710	resource_size_t len;
670	size_t priv_size;	711	size_t priv_size;
		712	int quirks = 0;
671	int err;	713	int err;
672		714
673	device = ACPI_COMPANION(dev);	715	device = ACPI_COMPANION(dev);
674	if (!device)	716	if (!device)
675	return -ENODEV;	717	return -ENODEV;
676		718
		719	id = dmi_first_match(sdhci_acpi_quirks);
		720	if (id)
		721	quirks = (long)id->driver_data;
		722
677	slot = sdhci_acpi_get_slot(device);	723	slot = sdhci_acpi_get_slot(device);
678		724
679	/* Power on the SDHCI controller and its children */	725	/* Power on the SDHCI controller and its children */
@@ -759,6 +805,12 @@ static int sdhci_acpi_probe(struct platform_device *pdev) · 79 unmodified lines
759	dev_warn(dev, "failed to setup card detect gpio\n");	805	dev_warn(dev, "failed to setup card detect gpio\n");
760	c->use_runtime_pm = false;	806	c->use_runtime_pm = false;
761	}	807	}
		808
		809	if (quirks & DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP)
		810	c->reset_signal_volt_on_suspend = true;
		811
		812	if (quirks & DMI_QUIRK_SD_NO_WRITE_PROTECT)
		813	host->mmc->caps2 \|= MMC_CAP2_NO_WRITE_PROTECT;
762	}	814	}
763		815
764	err = sdhci_setup_host(host);	816	err = sdhci_setup_host(host);
@@ -823,17 +875,39 @@ static int sdhci_acpi_remove(struct platform_device *pdev) · 58 unmodified lines
823	return 0;	875	return 0;
824	}	876	}
825		877
		878	static void __maybe_unused sdhci_acpi_reset_signal_voltage_if_needed(
		879	struct device *dev)
		880	{
		881	struct sdhci_acpi_host *c = dev_get_drvdata(dev);
		882	struct sdhci_host *host = c->host;
		883
		884	if (c->is_intel && c->reset_signal_volt_on_suspend &&
		885	host->mmc->ios.signal_voltage != MMC_SIGNAL_VOLTAGE_330) {
		886	struct intel_host *intel_host = sdhci_acpi_priv(c);
		887	unsigned int fn = INTEL_DSM_V33_SWITCH;
		888	u32 result = 0;
		889
		890	intel_dsm(intel_host, dev, fn, &result);
		891	}
		892	}
		893
826	#ifdef CONFIG_PM_SLEEP	894	#ifdef CONFIG_PM_SLEEP
827		895
828	static int sdhci_acpi_suspend(struct device *dev)	896	static int sdhci_acpi_suspend(struct device *dev)
829	{	897	{
830	struct sdhci_acpi_host *c = dev_get_drvdata(dev);	898	struct sdhci_acpi_host *c = dev_get_drvdata(dev);
831	struct sdhci_host *host = c->host;	899	struct sdhci_host *host = c->host;
		900	int ret;
832		901
833	if (host->tuning_mode != SDHCI_TUNING_MODE_3)	902	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
834	mmc_retune_needed(host->mmc);	903	mmc_retune_needed(host->mmc);
835		904
836	return sdhci_suspend_host(host);	905	ret = sdhci_suspend_host(host);
		906	if (ret)
		907	return ret;
		908
		909	sdhci_acpi_reset_signal_voltage_if_needed(dev);
		910	return 0;
837	}	911	}
838		912
839	static int sdhci_acpi_resume(struct device *dev)	913	static int sdhci_acpi_resume(struct device *dev)
@@ -853,11 +927,17 @@ static int sdhci_acpi_runtime_suspend(struct device *dev) · 13 unmodified lines
853	{	927	{
854	struct sdhci_acpi_host *c = dev_get_drvdata(dev);	928	struct sdhci_acpi_host *c = dev_get_drvdata(dev);
855	struct sdhci_host *host = c->host;	929	struct sdhci_host *host = c->host;
		930	int ret;
856		931
857	if (host->tuning_mode != SDHCI_TUNING_MODE_3)	932	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
858	mmc_retune_needed(host->mmc);	933	mmc_retune_needed(host->mmc);
859		934
860	return sdhci_runtime_suspend_host(host);	935	ret = sdhci_runtime_suspend_host(host);
		936	if (ret)
		937	return ret;
		938
		939	sdhci_acpi_reset_signal_voltage_if_needed(dev);
		940	return 0;
861	}	941	}
862		942
863	static int sdhci_acpi_runtime_resume(struct device *dev)	943	static int sdhci_acpi_runtime_resume(struct device *dev)

drivers/mmc/host/sdhci-cadence.c+16−2

 #include <linux/mmc/host.h>
 #include <linux/mmc/mmc.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include "sdhci-pltfm.h"
 	.set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
 };
+static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = {
+	.ops = &sdhci_cdns_ops,
+	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
+};
 static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
 	.ops = &sdhci_cdns_ops,
 };
 static int sdhci_cdns_probe(struct platform_device *pdev)
 {
 	struct sdhci_host *host;
+	const struct sdhci_pltfm_data *data;
 	struct sdhci_pltfm_host *pltfm_host;
 	struct sdhci_cdns_priv *priv;
 	struct clk *clk;
 	if (ret)
 		return ret;
+	data = of_device_get_match_data(dev);
+	if (!data)
+		data = &sdhci_cdns_pltfm_data;
 	nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
-	host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data,
+	host = sdhci_pltfm_init(pdev, data,
 				struct_size(priv, phy_params, nr_phy_params));
 	if (IS_ERR(host)) {
 		ret = PTR_ERR(host);
 };
 static const struct of_device_id sdhci_cdns_match[] = {
-	{ .compatible = "socionext,uniphier-sd4hc" },
+	{
+		.compatible = "socionext,uniphier-sd4hc",
+		.data = &sdhci_cdns_uniphier_pltfm_data,
+	},
 	{ .compatible = "cdns,sd4hc" },
 	{ /* sentinel */ }
 };

drivers/mmc/host/sdhci-msm.c+1−1

@@ -1590,7 +1590,7 @@ static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask) · 1589 unmodified lines
1590	return 0;	1590	return 0;
1591	}	1591	}
1592		1592
1593	void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)	1593	static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
1594	{	1594	{
1595	struct sdhci_host *host = mmc_priv(mmc);	1595	struct sdhci_host *host = mmc_priv(mmc);
1596	unsigned long flags;	1596	unsigned long flags;

drivers/mmc/host/sdhci-of-at91.c+6−2

 	sdhci_reset(host, mask);
-	if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
+	if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
+	    || mmc_gpio_get_cd(host->mmc) >= 0)
 		sdhci_at91_set_force_card_detect(host);
 	if (priv->cal_always_on && (mask & SDHCI_RESET_ALL))
 	 * detection procedure using the SDMCC_CD signal is bypassed.
 	 * This bit is reset when a software reset for all command is performed
 	 * so we need to implement our own reset function to set back this bit.
+	 *
+	 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
 	 */
-	if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
+	if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
+	    || mmc_gpio_get_cd(host->mmc) >= 0)
 		sdhci_at91_set_force_card_detect(host);
 	pm_runtime_put_autosuspend(&pdev->dev);

drivers/mmc/host/sdhci-omap.c+3−0

@@ -1192,6 +1192,9 @@ static int sdhci_omap_probe(struct platform_device *pdev) · 1191 unmodified lines
1192	if (of_find_property(dev->of_node, "dmas", NULL))	1192	if (of_find_property(dev->of_node, "dmas", NULL))
1193	sdhci_switch_external_dma(host, true);	1193	sdhci_switch_external_dma(host, true);
1194		1194
		1195	/* R1B responses is required to properly manage HW busy detection. */
		1196	mmc->caps \|= MMC_CAP_NEED_RSP_BUSY;
		1197
1195	ret = sdhci_setup_host(host);	1198	ret = sdhci_setup_host(host);
1196	if (ret)	1199	if (ret)
1197	goto err_put_sync;	1200	goto err_put_sync;

drivers/mmc/host/sdhci-pci-gli.c+17−0

@@ -262,10 +262,26 @@ static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) · 261 unmodified lines
262	return 0;	262	return 0;
263	}	263	}
264		264
		265	static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
		266	{
		267	int ret;
		268
		269	ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
		270	PCI_IRQ_MSI \| PCI_IRQ_MSIX);
		271	if (ret < 0) {
		272	pr_warn("%s: enable PCI MSI failed, error=%d\n",
		273	mmc_hostname(slot->host->mmc), ret);
		274	return;
		275	}
		276
		277	slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
		278	}
		279
265	static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)	280	static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
266	{	281	{
267	struct sdhci_host *host = slot->host;	282	struct sdhci_host *host = slot->host;
268		283
		284	gli_pcie_enable_msi(slot);
269	slot->host->mmc->caps2 \|= MMC_CAP2_NO_SDIO;	285	slot->host->mmc->caps2 \|= MMC_CAP2_NO_SDIO;
270	sdhci_enable_v4_mode(host);	286	sdhci_enable_v4_mode(host);
271		287
@@ -276,6 +292,7 @@ static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) · 4 unmodified lines
276	{	292	{
277	struct sdhci_host *host = slot->host;	293	struct sdhci_host *host = slot->host;
278		294
		295	gli_pcie_enable_msi(slot);
279	slot->host->mmc->caps2 \|= MMC_CAP2_NO_SDIO;	296	slot->host->mmc->caps2 \|= MMC_CAP2_NO_SDIO;
280	sdhci_enable_v4_mode(host);	297	sdhci_enable_v4_mode(host);
281		298

drivers/mmc/host/sdhci-tegra.c+3−0

@@ -1552,6 +1552,9 @@ static int sdhci_tegra_probe(struct platform_device *pdev) · 1551 unmodified lines
1552	if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)	1552	if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
1553	host->mmc->caps \|= MMC_CAP_1_8V_DDR;	1553	host->mmc->caps \|= MMC_CAP_1_8V_DDR;
1554		1554
		1555	/* R1B responses is required to properly manage HW busy detection. */
		1556	host->mmc->caps \|= MMC_CAP_NEED_RSP_BUSY;
		1557
1555	tegra_sdhci_parse_dt(host);	1558	tegra_sdhci_parse_dt(host);
1556		1559
1557	tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",	1560	tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",

drivers/net/bonding/bond_alb.c+10−10

 };
 #pragma pack()
-static inline struct arp_pkt *arp_pkt(const struct sk_buff *skb)
-{
-	return (struct arp_pkt *)skb_network_header(skb);
-}
 /* Forward declaration */
 static void alb_send_learning_packets(struct slave *slave, u8 mac_addr[],
 				      bool strict_match);
 	spin_unlock(&bond->mode_lock);
 }
-static struct slave *rlb_choose_channel(struct sk_buff *skb, struct bonding *bond)
+static struct slave *rlb_choose_channel(struct sk_buff *skb,
+					struct bonding *bond,
+					const struct arp_pkt *arp)
 {
 	struct alb_bond_info *bond_info = &(BOND_ALB_INFO(bond));
-	struct arp_pkt *arp = arp_pkt(skb);
 	struct slave *assigned_slave, *curr_active_slave;
 	struct rlb_client_info *client_info;
 	u32 hash_index = 0;
  */
 static struct slave *rlb_arp_xmit(struct sk_buff *skb, struct bonding *bond)
 {
-	struct arp_pkt *arp = arp_pkt(skb);
 	struct slave *tx_slave = NULL;
+	struct arp_pkt *arp;
+	if (!pskb_network_may_pull(skb, sizeof(*arp)))
+		return NULL;
+	arp = (struct arp_pkt *)skb_network_header(skb);
 	/* Don't modify or load balance ARPs that do not originate locally
 	 * (e.g.,arrive via a bridge).
 	if (arp->op_code == htons(ARPOP_REPLY)) {
 		/* the arp must be sent on the selected rx channel */
-		tx_slave = rlb_choose_channel(skb, bond);
+		tx_slave = rlb_choose_channel(skb, bond, arp);
 		if (tx_slave)
 			bond_hw_addr_copy(arp->mac_src, tx_slave->dev->dev_addr,
 					  tx_slave->dev->addr_len);
 		 * When the arp reply is received the entry will be updated
 		 * with the correct unicast address of the client.
 		 */
-		tx_slave = rlb_choose_channel(skb, bond);
+		tx_slave = rlb_choose_channel(skb, bond, arp);
 		/* The ARP reply packets must be delayed so that
 		 * they can cancel out the influence of the ARP request.

drivers/net/can/dev.c+1−0

@@ -883,6 +883,7 @@ static const struct nla_policy can_policy[IFLA_CAN_MAX + 1] = { · 882 unmodified lines
883	= { .len = sizeof(struct can_bittiming) },	883	= { .len = sizeof(struct can_bittiming) },
884	[IFLA_CAN_DATA_BITTIMING_CONST]	884	[IFLA_CAN_DATA_BITTIMING_CONST]
885	= { .len = sizeof(struct can_bittiming_const) },	885	= { .len = sizeof(struct can_bittiming_const) },
		886	[IFLA_CAN_TERMINATION] = { .type = NLA_U16 },
886	};	887	};
887		888
888	static int can_validate(struct nlattr tb[], struct nlattr data[],	889	static int can_validate(struct nlattr tb[], struct nlattr data[],

drivers/net/dsa/bcm_sf2.c+1−2

@@ -69,8 +69,7 @@ static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) · 68 unmodified lines
69	/* Force link status for IMP port */	69	/* Force link status for IMP port */
70	reg = core_readl(priv, offset);	70	reg = core_readl(priv, offset);
71	reg \|= (MII_SW_OR \| LINK_STS);	71	reg \|= (MII_SW_OR \| LINK_STS);
72	if (priv->type == BCM7278_DEVICE_ID)	72	reg &= ~GMII_SPEED_UP_2G;
73	reg \|= GMII_SPEED_UP_2G;
74	core_writel(priv, reg, offset);	73	core_writel(priv, reg, offset);
75		74
76	/* Enable Broadcast, Multicast, Unicast forwarding to IMP port */	75	/* Enable Broadcast, Multicast, Unicast forwarding to IMP port */

drivers/net/dsa/mv88e6xxx/chip.c+2−0

@@ -2769,6 +2769,8 @@ static u64 mv88e6xxx_devlink_atu_bin_get(struct mv88e6xxx_chip *chip, · 2768 unmodified lines
2769	goto unlock;	2769	goto unlock;
2770	}	2770	}
2771		2771
		2772	occupancy &= MV88E6XXX_G2_ATU_STATS_MASK;
		2773
2772	unlock:	2774	unlock:
2773	mv88e6xxx_reg_unlock(chip);	2775	mv88e6xxx_reg_unlock(chip);
2774		2776

drivers/net/dsa/mv88e6xxx/global1.c+2−2

@@ -278,13 +278,13 @@ int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, · 277 unmodified lines
278	switch (direction) {	278	switch (direction) {
279	case MV88E6XXX_EGRESS_DIR_INGRESS:	279	case MV88E6XXX_EGRESS_DIR_INGRESS:
280	dest_port_chip = &chip->ingress_dest_port;	280	dest_port_chip = &chip->ingress_dest_port;
281	reg &= MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;	281	reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;
282	reg \|= port <<	282	reg \|= port <<
283	__bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);	283	__bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);
284	break;	284	break;
285	case MV88E6XXX_EGRESS_DIR_EGRESS:	285	case MV88E6XXX_EGRESS_DIR_EGRESS:
286	dest_port_chip = &chip->egress_dest_port;	286	dest_port_chip = &chip->egress_dest_port;
287	reg &= MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;	287	reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;
288	reg \|= port <<	288	reg \|= port <<
289	__bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);	289	__bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
290	break;	290	break;

drivers/net/dsa/mv88e6xxx/global2.c+7−1

 {
 	int err, irq, virq;
+	chip->g2_irq.masked = ~0;
+	mv88e6xxx_reg_lock(chip);
+	err = mv88e6xxx_g2_int_mask(chip, ~chip->g2_irq.masked);
+	mv88e6xxx_reg_unlock(chip);
+	if (err)
+		return err;
 	chip->g2_irq.domain = irq_domain_add_simple(
 		chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip);
 	if (!chip->g2_irq.domain)
 		irq_create_mapping(chip->g2_irq.domain, irq);
 	chip->g2_irq.chip = mv88e6xxx_g2_irq_chip;
-	chip->g2_irq.masked = ~0;
 	chip->device_irq = irq_find_mapping(chip->g1_irq.domain,
 					    MV88E6XXX_G1_STS_IRQ_DEVICE);

drivers/net/dsa/sja1105/sja1105_main.c+2−1

@@ -1741,7 +1741,8 @@ static void sja1105_teardown(struct dsa_switch *ds) · 1740 unmodified lines
1741	if (!dsa_is_user_port(ds, port))	1741	if (!dsa_is_user_port(ds, port))
1742	continue;	1742	continue;
1743		1743
1744	kthread_destroy_worker(sp->xmit_worker);	1744	if (sp->xmit_worker)
		1745	kthread_destroy_worker(sp->xmit_worker);
1745	}	1746	}
1746		1747
1747	sja1105_tas_teardown(ds);	1748	sja1105_tas_teardown(ds);

drivers/net/ethernet/broadcom/bcmsysport.c+1−1

@@ -2135,7 +2135,7 @@ static int bcm_sysport_rule_set(struct bcm_sysport_priv *priv, · 2134 unmodified lines
2135	return -ENOSPC;	2135	return -ENOSPC;
2136		2136
2137	index = find_first_zero_bit(priv->filters, RXCHK_BRCM_TAG_MAX);	2137	index = find_first_zero_bit(priv->filters, RXCHK_BRCM_TAG_MAX);
2138	if (index > RXCHK_BRCM_TAG_MAX)	2138	if (index >= RXCHK_BRCM_TAG_MAX)
2139	return -ENOSPC;	2139	return -ENOSPC;
2140		2140
2141	/* Location is the classification ID, and index is the position	2141	/* Location is the classification ID, and index is the position

drivers/net/ethernet/broadcom/bnxt/bnxt.c+4−4

@@ -10982,13 +10982,13 @@ static int bnxt_change_mtu(struct net_device *dev, int new_mtu) · 10981 unmodified lines
10982	struct bnxt *bp = netdev_priv(dev);	10982	struct bnxt *bp = netdev_priv(dev);
10983		10983
10984	if (netif_running(dev))	10984	if (netif_running(dev))
10985	bnxt_close_nic(bp, false, false);	10985	bnxt_close_nic(bp, true, false);
10986		10986
10987	dev->mtu = new_mtu;	10987	dev->mtu = new_mtu;
10988	bnxt_set_ring_params(bp);	10988	bnxt_set_ring_params(bp);
10989		10989
10990	if (netif_running(dev))	10990	if (netif_running(dev))
10991	return bnxt_open_nic(bp, false, false);	10991	return bnxt_open_nic(bp, true, false);
10992		10992
10993	return 0;	10993	return 0;
10994	}	10994	}
@@ -11252,7 +11252,7 @@ static void bnxt_cfg_ntp_filters(struct bnxt *bp) · 257 unmodified lines
11252	}	11252	}
11253	}	11253	}
11254	if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))	11254	if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
11255	netdev_info(bp->dev, "Receive PF driver unload event!");	11255	netdev_info(bp->dev, "Receive PF driver unload event!\n");
11256	}	11256	}
11257		11257
11258	#else	11258	#else
@@ -11759,7 +11759,7 @@ static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) · 500 unmodified lines
11759	u32 dw;	11759	u32 dw;
11760		11760
11761	if (!pos) {	11761	if (!pos) {
11762	netdev_info(bp->dev, "Unable do read adapter's DSN");	11762	netdev_info(bp->dev, "Unable do read adapter's DSN\n");
11763	return -EOPNOTSUPP;	11763	return -EOPNOTSUPP;
11764	}	11764	}
11765		11765

drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c+5−5

@@ -641,14 +641,14 @@ static int bnxt_dl_params_register(struct bnxt *bp) · 640 unmodified lines
641	rc = devlink_params_register(bp->dl, bnxt_dl_params,	641	rc = devlink_params_register(bp->dl, bnxt_dl_params,
642	ARRAY_SIZE(bnxt_dl_params));	642	ARRAY_SIZE(bnxt_dl_params));
643	if (rc) {	643	if (rc) {
644	netdev_warn(bp->dev, "devlink_params_register failed. rc=%d",	644	netdev_warn(bp->dev, "devlink_params_register failed. rc=%d\n",
645	rc);	645	rc);
646	return rc;	646	return rc;
647	}	647	}
648	rc = devlink_port_params_register(&bp->dl_port, bnxt_dl_port_params,	648	rc = devlink_port_params_register(&bp->dl_port, bnxt_dl_port_params,
649	ARRAY_SIZE(bnxt_dl_port_params));	649	ARRAY_SIZE(bnxt_dl_port_params));
650	if (rc) {	650	if (rc) {
651	netdev_err(bp->dev, "devlink_port_params_register failed");	651	netdev_err(bp->dev, "devlink_port_params_register failed\n");
652	devlink_params_unregister(bp->dl, bnxt_dl_params,	652	devlink_params_unregister(bp->dl, bnxt_dl_params,
653	ARRAY_SIZE(bnxt_dl_params));	653	ARRAY_SIZE(bnxt_dl_params));
654	return rc;	654	return rc;
@@ -679,7 +679,7 @@ int bnxt_dl_register(struct bnxt *bp) · 24 unmodified lines
679	else	679	else
680	dl = devlink_alloc(&bnxt_vf_dl_ops, sizeof(struct bnxt_dl));	680	dl = devlink_alloc(&bnxt_vf_dl_ops, sizeof(struct bnxt_dl));
681	if (!dl) {	681	if (!dl) {
682	netdev_warn(bp->dev, "devlink_alloc failed");	682	netdev_warn(bp->dev, "devlink_alloc failed\n");
683	return -ENOMEM;	683	return -ENOMEM;
684	}	684	}
685		685
@@ -692,7 +692,7 @@ int bnxt_dl_register(struct bnxt *bp) · 6 unmodified lines
692		692
693	rc = devlink_register(dl, &bp->pdev->dev);	693	rc = devlink_register(dl, &bp->pdev->dev);
694	if (rc) {	694	if (rc) {
695	netdev_warn(bp->dev, "devlink_register failed. rc=%d", rc);	695	netdev_warn(bp->dev, "devlink_register failed. rc=%d\n", rc);
696	goto err_dl_free;	696	goto err_dl_free;
697	}	697	}
698		698
@@ -704,7 +704,7 @@ int bnxt_dl_register(struct bnxt *bp) · 5 unmodified lines
704	sizeof(bp->dsn));	704	sizeof(bp->dsn));
705	rc = devlink_port_register(dl, &bp->dl_port, bp->pf.port_id);	705	rc = devlink_port_register(dl, &bp->dl_port, bp->pf.port_id);
706	if (rc) {	706	if (rc) {
707	netdev_err(bp->dev, "devlink_port_register failed");	707	netdev_err(bp->dev, "devlink_port_register failed\n");
708	goto err_dl_unreg;	708	goto err_dl_unreg;
709	}	709	}
710		710

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c+13−15

 	struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr;
 	struct hwrm_nvm_install_update_input install = {0};
 	const struct firmware *fw;
-	int rc, hwrm_err = 0;
 	u32 item_len;
+	int rc = 0;
 	u16 index;
 	bnxt_hwrm_fw_set_time(bp);
 	}
 	if (fw->size > item_len) {
-		netdev_err(dev, "PKG insufficient update area in nvram: %lu",
+		netdev_err(dev, "PKG insufficient update area in nvram: %lu\n",
 			   (unsigned long)fw->size);
 		rc = -EFBIG;
 	} else {
 			memcpy(kmem, fw->data, fw->size);
 			modify.host_src_addr = cpu_to_le64(dma_handle);
-			hwrm_err = hwrm_send_message(bp, &modify,
+			rc = hwrm_send_message(bp, &modify, sizeof(modify),
-						     sizeof(modify),
+					       FLASH_PACKAGE_TIMEOUT);
-						     FLASH_PACKAGE_TIMEOUT);
 			dma_free_coherent(&bp->pdev->dev, fw->size, kmem,
 					  dma_handle);
 		}
 	}
 	release_firmware(fw);
-	if (rc || hwrm_err)
+	if (rc)
 		goto err_exit;
 	if ((install_type & 0xffff) == 0)
 	install.install_type = cpu_to_le32(install_type);
 	mutex_lock(&bp->hwrm_cmd_lock);
-	hwrm_err = _hwrm_send_message(bp, &install, sizeof(install),
+	rc = _hwrm_send_message(bp, &install, sizeof(install),
-				      INSTALL_PACKAGE_TIMEOUT);
+				INSTALL_PACKAGE_TIMEOUT);
-	if (hwrm_err) {
+	if (rc) {
 		u8 error_code = ((struct hwrm_err_output *)resp)->cmd_err;
 		if (resp->error_code && error_code ==
 		    NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) {
 			install.flags |= cpu_to_le16(
 			       NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
-			hwrm_err = _hwrm_send_message(bp, &install,
+			rc = _hwrm_send_message(bp, &install, sizeof(install),
-						      sizeof(install),
+						INSTALL_PACKAGE_TIMEOUT);
-						      INSTALL_PACKAGE_TIMEOUT);
 		}
-		if (hwrm_err)
+		if (rc)
 			goto flash_pkg_exit;
 	}
 flash_pkg_exit:
 	mutex_unlock(&bp->hwrm_cmd_lock);
 err_exit:
-	if (hwrm_err == -EACCES)
+	if (rc == -EACCES)
 		bnxt_print_admin_err(bp);
 	return rc;
 }
 	kfree(coredump.data);
 	*dump_len += sizeof(struct bnxt_coredump_record);
 	if (rc == -ENOBUFS)
-		netdev_err(bp->dev, "Firmware returned large coredump buffer");
+		netdev_err(bp->dev, "Firmware returned large coredump buffer\n");
 	return rc;
 }

drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c+24−24

@@ -50,7 +50,7 @@ static u16 bnxt_flow_get_dst_fid(struct bnxt pf_bp, struct net_device dev) · 49 unmodified lines
50		50
51	/* check if dev belongs to the same switch */	51	/* check if dev belongs to the same switch */
52	if (!netdev_port_same_parent_id(pf_bp->dev, dev)) {	52	if (!netdev_port_same_parent_id(pf_bp->dev, dev)) {
53	netdev_info(pf_bp->dev, "dev(ifindex=%d) not on same switch",	53	netdev_info(pf_bp->dev, "dev(ifindex=%d) not on same switch\n",
54	dev->ifindex);	54	dev->ifindex);
55	return BNXT_FID_INVALID;	55	return BNXT_FID_INVALID;
56	}	56	}
@@ -70,7 +70,7 @@ static int bnxt_tc_parse_redir(struct bnxt *bp, · 13 unmodified lines
70	struct net_device *dev = act->dev;	70	struct net_device *dev = act->dev;
71		71
72	if (!dev) {	72	if (!dev) {
73	netdev_info(bp->dev, "no dev in mirred action");	73	netdev_info(bp->dev, "no dev in mirred action\n");
74	return -EINVAL;	74	return -EINVAL;
75	}	75	}
76		76
@@ -106,7 +106,7 @@ static int bnxt_tc_parse_tunnel_set(struct bnxt *bp, · 29 unmodified lines
106	const struct ip_tunnel_key *tun_key = &tun_info->key;	106	const struct ip_tunnel_key *tun_key = &tun_info->key;
107		107
108	if (ip_tunnel_info_af(tun_info) != AF_INET) {	108	if (ip_tunnel_info_af(tun_info) != AF_INET) {
109	netdev_info(bp->dev, "only IPv4 tunnel-encap is supported");	109	netdev_info(bp->dev, "only IPv4 tunnel-encap is supported\n");
110	return -EOPNOTSUPP;	110	return -EOPNOTSUPP;
111	}	111	}
112		112
@@ -295,7 +295,7 @@ static int bnxt_tc_parse_actions(struct bnxt *bp, · 182 unmodified lines
295	int i, rc;	295	int i, rc;
296		296
297	if (!flow_action_has_entries(flow_action)) {	297	if (!flow_action_has_entries(flow_action)) {
298	netdev_info(bp->dev, "no actions");	298	netdev_info(bp->dev, "no actions\n");
299	return -EINVAL;	299	return -EINVAL;
300	}	300	}
301		301
@@ -370,7 +370,7 @@ static int bnxt_tc_parse_flow(struct bnxt *bp, · 68 unmodified lines
370	/* KEY_CONTROL and KEY_BASIC are needed for forming a meaningful key */	370	/* KEY_CONTROL and KEY_BASIC are needed for forming a meaningful key */
371	if ((dissector->used_keys & BIT(FLOW_DISSECTOR_KEY_CONTROL)) == 0 \|\|	371	if ((dissector->used_keys & BIT(FLOW_DISSECTOR_KEY_CONTROL)) == 0 \|\|
372	(dissector->used_keys & BIT(FLOW_DISSECTOR_KEY_BASIC)) == 0) {	372	(dissector->used_keys & BIT(FLOW_DISSECTOR_KEY_BASIC)) == 0) {
373	netdev_info(bp->dev, "cannot form TC key: used_keys = 0x%x",	373	netdev_info(bp->dev, "cannot form TC key: used_keys = 0x%x\n",
374	dissector->used_keys);	374	dissector->used_keys);
375	return -EOPNOTSUPP;	375	return -EOPNOTSUPP;
376	}	376	}
@@ -508,7 +508,7 @@ static int bnxt_hwrm_cfa_flow_free(struct bnxt *bp, · 131 unmodified lines
508		508
509	rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);	509	rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
510	if (rc)	510	if (rc)
511	netdev_info(bp->dev, "%s: Error rc=%d", __func__, rc);	511	netdev_info(bp->dev, "%s: Error rc=%d\n", __func__, rc);
512		512
513	return rc;	513	return rc;
514	}	514	}
@@ -841,7 +841,7 @@ static int hwrm_cfa_decap_filter_alloc(struct bnxt *bp, · 326 unmodified lines
841	resp = bnxt_get_hwrm_resp_addr(bp, &req);	841	resp = bnxt_get_hwrm_resp_addr(bp, &req);
842	*decap_filter_handle = resp->decap_filter_id;	842	*decap_filter_handle = resp->decap_filter_id;
843	} else {	843	} else {
844	netdev_info(bp->dev, "%s: Error rc=%d", __func__, rc);	844	netdev_info(bp->dev, "%s: Error rc=%d\n", __func__, rc);
845	}	845	}
846	mutex_unlock(&bp->hwrm_cmd_lock);	846	mutex_unlock(&bp->hwrm_cmd_lock);
847		847
@@ -859,7 +859,7 @@ static int hwrm_cfa_decap_filter_free(struct bnxt *bp, · 11 unmodified lines
859		859
860	rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);	860	rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
861	if (rc)	861	if (rc)
862	netdev_info(bp->dev, "%s: Error rc=%d", __func__, rc);	862	netdev_info(bp->dev, "%s: Error rc=%d\n", __func__, rc);
863		863
864	return rc;	864	return rc;
865	}	865	}
@@ -906,7 +906,7 @@ static int hwrm_cfa_encap_record_alloc(struct bnxt *bp, · 40 unmodified lines
906	resp = bnxt_get_hwrm_resp_addr(bp, &req);	906	resp = bnxt_get_hwrm_resp_addr(bp, &req);
907	*encap_record_handle = resp->encap_record_id;	907	*encap_record_handle = resp->encap_record_id;
908	} else {	908	} else {
909	netdev_info(bp->dev, "%s: Error rc=%d", __func__, rc);	909	netdev_info(bp->dev, "%s: Error rc=%d\n", __func__, rc);
910	}	910	}
911	mutex_unlock(&bp->hwrm_cmd_lock);	911	mutex_unlock(&bp->hwrm_cmd_lock);
912		912
@@ -924,7 +924,7 @@ static int hwrm_cfa_encap_record_free(struct bnxt *bp, · 11 unmodified lines
924		924
925	rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);	925	rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
926	if (rc)	926	if (rc)
927	netdev_info(bp->dev, "%s: Error rc=%d", __func__, rc);	927	netdev_info(bp->dev, "%s: Error rc=%d\n", __func__, rc);
928		928
929	return rc;	929	return rc;
930	}	930	}
@@ -943,7 +943,7 @@ static int bnxt_tc_put_l2_node(struct bnxt *bp, · 12 unmodified lines
943	tc_info->l2_ht_params);	943	tc_info->l2_ht_params);
944	if (rc)	944	if (rc)
945	netdev_err(bp->dev,	945	netdev_err(bp->dev,
946	"Error: %s: rhashtable_remove_fast: %d",	946	"Error: %s: rhashtable_remove_fast: %d\n",
947	__func__, rc);	947	__func__, rc);
948	kfree_rcu(l2_node, rcu);	948	kfree_rcu(l2_node, rcu);
949	}	949	}
@@ -972,7 +972,7 @@ bnxt_tc_get_l2_node(struct bnxt bp, struct rhashtable l2_table, · 22 unmodified lines
972	if (rc) {	972	if (rc) {
973	kfree_rcu(l2_node, rcu);	973	kfree_rcu(l2_node, rcu);
974	netdev_err(bp->dev,	974	netdev_err(bp->dev,
975	"Error: %s: rhashtable_insert_fast: %d",	975	"Error: %s: rhashtable_insert_fast: %d\n",
976	__func__, rc);	976	__func__, rc);
977	return NULL;	977	return NULL;
978	}	978	}
@@ -1031,7 +1031,7 @@ static bool bnxt_tc_can_offload(struct bnxt bp, struct bnxt_tc_flow flow) · 52 unmodified lines
1031	if ((flow->flags & BNXT_TC_FLOW_FLAGS_PORTS) &&	1031	if ((flow->flags & BNXT_TC_FLOW_FLAGS_PORTS) &&
1032	(flow->l4_key.ip_proto != IPPROTO_TCP &&	1032	(flow->l4_key.ip_proto != IPPROTO_TCP &&
1033	flow->l4_key.ip_proto != IPPROTO_UDP)) {	1033	flow->l4_key.ip_proto != IPPROTO_UDP)) {
1034	netdev_info(bp->dev, "Cannot offload non-TCP/UDP (%d) ports",	1034	netdev_info(bp->dev, "Cannot offload non-TCP/UDP (%d) ports\n",
1035	flow->l4_key.ip_proto);	1035	flow->l4_key.ip_proto);
1036	return false;	1036	return false;
1037	}	1037	}
@@ -1088,7 +1088,7 @@ static int bnxt_tc_put_tunnel_node(struct bnxt *bp, · 50 unmodified lines
1088	rc = rhashtable_remove_fast(tunnel_table, &tunnel_node->node,	1088	rc = rhashtable_remove_fast(tunnel_table, &tunnel_node->node,
1089	*ht_params);	1089	*ht_params);
1090	if (rc) {	1090	if (rc) {
1091	netdev_err(bp->dev, "rhashtable_remove_fast rc=%d", rc);	1091	netdev_err(bp->dev, "rhashtable_remove_fast rc=%d\n", rc);
1092	rc = -1;	1092	rc = -1;
1093	}	1093	}
1094	kfree_rcu(tunnel_node, rcu);	1094	kfree_rcu(tunnel_node, rcu);
@@ -1129,7 +1129,7 @@ bnxt_tc_get_tunnel_node(struct bnxt bp, struct rhashtable tunnel_table, · 34 unmodified lines
1129	tunnel_node->refcount++;	1129	tunnel_node->refcount++;
1130	return tunnel_node;	1130	return tunnel_node;
1131	err:	1131	err:
1132	netdev_info(bp->dev, "error rc=%d", rc);	1132	netdev_info(bp->dev, "error rc=%d\n", rc);
1133	return NULL;	1133	return NULL;
1134	}	1134	}
1135		1135
@@ -1187,7 +1187,7 @@ static void bnxt_tc_put_decap_l2_node(struct bnxt *bp, · 51 unmodified lines
1187	&decap_l2_node->node,	1187	&decap_l2_node->node,
1188	tc_info->decap_l2_ht_params);	1188	tc_info->decap_l2_ht_params);
1189	if (rc)	1189	if (rc)
1190	netdev_err(bp->dev, "rhashtable_remove_fast rc=%d", rc);	1190	netdev_err(bp->dev, "rhashtable_remove_fast rc=%d\n", rc);
1191	kfree_rcu(decap_l2_node, rcu);	1191	kfree_rcu(decap_l2_node, rcu);
1192	}	1192	}
1193	}	1193	}
@@ -1227,7 +1227,7 @@ static int bnxt_tc_resolve_tunnel_hdrs(struct bnxt *bp, · 33 unmodified lines
1227		1227
1228	rt = ip_route_output_key(dev_net(real_dst_dev), &flow);	1228	rt = ip_route_output_key(dev_net(real_dst_dev), &flow);
1229	if (IS_ERR(rt)) {	1229	if (IS_ERR(rt)) {
1230	netdev_info(bp->dev, "no route to %pI4b", &flow.daddr);	1230	netdev_info(bp->dev, "no route to %pI4b\n", &flow.daddr);
1231	return -EOPNOTSUPP;	1231	return -EOPNOTSUPP;
1232	}	1232	}
1233		1233
@@ -1241,7 +1241,7 @@ static int bnxt_tc_resolve_tunnel_hdrs(struct bnxt *bp, · 7 unmodified lines
1241		1241
1242	if (vlan->real_dev != real_dst_dev) {	1242	if (vlan->real_dev != real_dst_dev) {
1243	netdev_info(bp->dev,	1243	netdev_info(bp->dev,
1244	"dst_dev(%s) doesn't use PF-if(%s)",	1244	"dst_dev(%s) doesn't use PF-if(%s)\n",
1245	netdev_name(dst_dev),	1245	netdev_name(dst_dev),
1246	netdev_name(real_dst_dev));	1246	netdev_name(real_dst_dev));
1247	rc = -EOPNOTSUPP;	1247	rc = -EOPNOTSUPP;
@@ -1253,7 +1253,7 @@ static int bnxt_tc_resolve_tunnel_hdrs(struct bnxt *bp, · 5 unmodified lines
1253	#endif	1253	#endif
1254	} else if (dst_dev != real_dst_dev) {	1254	} else if (dst_dev != real_dst_dev) {
1255	netdev_info(bp->dev,	1255	netdev_info(bp->dev,
1256	"dst_dev(%s) for %pI4b is not PF-if(%s)",	1256	"dst_dev(%s) for %pI4b is not PF-if(%s)\n",
1257	netdev_name(dst_dev), &flow.daddr,	1257	netdev_name(dst_dev), &flow.daddr,
1258	netdev_name(real_dst_dev));	1258	netdev_name(real_dst_dev));
1259	rc = -EOPNOTSUPP;	1259	rc = -EOPNOTSUPP;
@@ -1262,7 +1262,7 @@ static int bnxt_tc_resolve_tunnel_hdrs(struct bnxt *bp, · 2 unmodified lines
1262		1262
1263	nbr = dst_neigh_lookup(&rt->dst, &flow.daddr);	1263	nbr = dst_neigh_lookup(&rt->dst, &flow.daddr);
1264	if (!nbr) {	1264	if (!nbr) {
1265	netdev_info(bp->dev, "can't lookup neighbor for %pI4b",	1265	netdev_info(bp->dev, "can't lookup neighbor for %pI4b\n",
1266	&flow.daddr);	1266	&flow.daddr);
1267	rc = -EOPNOTSUPP;	1267	rc = -EOPNOTSUPP;
1268	goto put_rt;	1268	goto put_rt;
@@ -1472,7 +1472,7 @@ static int __bnxt_tc_del_flow(struct bnxt *bp, · 203 unmodified lines
1472	rc = rhashtable_remove_fast(&tc_info->flow_table, &flow_node->node,	1472	rc = rhashtable_remove_fast(&tc_info->flow_table, &flow_node->node,
1473	tc_info->flow_ht_params);	1473	tc_info->flow_ht_params);
1474	if (rc)	1474	if (rc)
1475	netdev_err(bp->dev, "Error: %s: rhashtable_remove_fast rc=%d",	1475	netdev_err(bp->dev, "Error: %s: rhashtable_remove_fast rc=%d\n",
1476	__func__, rc);	1476	__func__, rc);
1477		1477
1478	kfree_rcu(flow_node, rcu);	1478	kfree_rcu(flow_node, rcu);
@@ -1587,7 +1587,7 @@ unlock: · 108 unmodified lines
1587	free_node:	1587	free_node:
1588	kfree_rcu(new_node, rcu);	1588	kfree_rcu(new_node, rcu);
1589	done:	1589	done:
1590	netdev_err(bp->dev, "Error: %s: cookie=0x%lx error=%d",	1590	netdev_err(bp->dev, "Error: %s: cookie=0x%lx error=%d\n",
1591	__func__, tc_flow_cmd->cookie, rc);	1591	__func__, tc_flow_cmd->cookie, rc);
1592	return rc;	1592	return rc;
1593	}	1593	}
@@ -1700,7 +1700,7 @@ bnxt_hwrm_cfa_flow_stats_get(struct bnxt *bp, int num_flows, · 106 unmodified lines
1700	le64_to_cpu(resp_bytes[i]);	1700	le64_to_cpu(resp_bytes[i]);
1701	}	1701	}
1702	} else {	1702	} else {
1703	netdev_info(bp->dev, "error rc=%d", rc);	1703	netdev_info(bp->dev, "error rc=%d\n", rc);
1704	}	1704	}
1705	mutex_unlock(&bp->hwrm_cmd_lock);	1705	mutex_unlock(&bp->hwrm_cmd_lock);
1706		1706
@@ -1970,7 +1970,7 @@ static int bnxt_tc_indr_block_event(struct notifier_block *nb, · 263 unmodified lines
1970	bp);	1970	bp);
1971	if (rc)	1971	if (rc)
1972	netdev_info(bp->dev,	1972	netdev_info(bp->dev,
1973	"Failed to register indirect blk: dev: %s",	1973	"Failed to register indirect blk: dev: %s\n",
1974	netdev->name);	1974	netdev->name);
1975	break;	1975	break;
1976	case NETDEV_UNREGISTER:	1976	case NETDEV_UNREGISTER:

drivers/net/ethernet/broadcom/bnxt/bnxt_vfr.c+5−5

@@ -43,7 +43,7 @@ static int hwrm_cfa_vfr_alloc(struct bnxt *bp, u16 vf_idx, · 42 unmodified lines
43	netdev_dbg(bp->dev, "tx_cfa_action=0x%x, rx_cfa_code=0x%x",	43	netdev_dbg(bp->dev, "tx_cfa_action=0x%x, rx_cfa_code=0x%x",
44	tx_cfa_action, rx_cfa_code);	44	tx_cfa_action, rx_cfa_code);
45	} else {	45	} else {
46	netdev_info(bp->dev, "%s error rc=%d", __func__, rc);	46	netdev_info(bp->dev, "%s error rc=%d\n", __func__, rc);
47	}	47	}
48		48
49	mutex_unlock(&bp->hwrm_cmd_lock);	49	mutex_unlock(&bp->hwrm_cmd_lock);
@@ -60,7 +60,7 @@ static int hwrm_cfa_vfr_free(struct bnxt *bp, u16 vf_idx) · 10 unmodified lines
60		60
61	rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);	61	rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
62	if (rc)	62	if (rc)
63	netdev_info(bp->dev, "%s error rc=%d", __func__, rc);	63	netdev_info(bp->dev, "%s error rc=%d\n", __func__, rc);
64	return rc;	64	return rc;
65	}	65	}
66		66
@@ -465,7 +465,7 @@ static int bnxt_vf_reps_create(struct bnxt *bp) · 398 unmodified lines
465	return 0;	465	return 0;
466		466
467	err:	467	err:
468	netdev_info(bp->dev, "%s error=%d", __func__, rc);	468	netdev_info(bp->dev, "%s error=%d\n", __func__, rc);
469	kfree(cfa_code_map);	469	kfree(cfa_code_map);
470	__bnxt_vf_reps_destroy(bp);	470	__bnxt_vf_reps_destroy(bp);
471	return rc;	471	return rc;
@@ -488,7 +488,7 @@ int bnxt_dl_eswitch_mode_set(struct devlink *devlink, u16 mode, · 16 unmodified lines
488		488
489	mutex_lock(&bp->sriov_lock);	489	mutex_lock(&bp->sriov_lock);
490	if (bp->eswitch_mode == mode) {	490	if (bp->eswitch_mode == mode) {
491	netdev_info(bp->dev, "already in %s eswitch mode",	491	netdev_info(bp->dev, "already in %s eswitch mode\n",
492	mode == DEVLINK_ESWITCH_MODE_LEGACY ?	492	mode == DEVLINK_ESWITCH_MODE_LEGACY ?
493	"legacy" : "switchdev");	493	"legacy" : "switchdev");
494	rc = -EINVAL;	494	rc = -EINVAL;
@@ -508,7 +508,7 @@ int bnxt_dl_eswitch_mode_set(struct devlink *devlink, u16 mode, · 13 unmodified lines
508	}	508	}
509		509
510	if (pci_num_vf(bp->pdev) == 0) {	510	if (pci_num_vf(bp->pdev) == 0) {
511	netdev_info(bp->dev, "Enable VFs before setting switchdev mode");	511	netdev_info(bp->dev, "Enable VFs before setting switchdev mode\n");
512	rc = -EPERM;	512	rc = -EPERM;
513	goto done;	513	goto done;
514	}	514	}

drivers/net/ethernet/broadcom/genet/bcmmii.c+1−0

@@ -294,6 +294,7 @@ int bcmgenet_mii_config(struct net_device *dev, bool init) · 293 unmodified lines
294	*/	294	*/
295	if (priv->ext_phy) {	295	if (priv->ext_phy) {
296	reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);	296	reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
		297	reg &= ~ID_MODE_DIS;
297	reg \|= id_mode_dis;	298	reg \|= id_mode_dis;
298	if (GENET_IS_V1(priv) \|\| GENET_IS_V2(priv) \|\| GENET_IS_V3(priv))	299	if (GENET_IS_V1(priv) \|\| GENET_IS_V2(priv) \|\| GENET_IS_V3(priv))
299	reg \|= RGMII_MODE_EN_V123;	300	reg \|= RGMII_MODE_EN_V123;

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c+27−22

 static int cfg_queues(struct adapter *adap)
 {
 	u32 avail_qsets, avail_eth_qsets, avail_uld_qsets;
+	u32 i, n10g = 0, qidx = 0, n1g = 0;
+	u32 ncpus = num_online_cpus();
 	u32 niqflint, neq, num_ulds;
 	struct sge *s = &adap->sge;
-	u32 i, n10g = 0, qidx = 0;
+	u32 q10g = 0, q1g;
-#ifndef CONFIG_CHELSIO_T4_DCB
-	int q10g = 0;
-#endif
 	/* Reduce memory usage in kdump environment, disable all offload. */
 	if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
 		n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
 	avail_eth_qsets = min_t(u32, avail_qsets, MAX_ETH_QSETS);
+	/* We default to 1 queue per non-10G port and up to # of cores queues
+	 * per 10G port.
+	 */
+	if (n10g)
+		q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g;
+	n1g = adap->params.nports - n10g;
 #ifdef CONFIG_CHELSIO_T4_DCB
 	/* For Data Center Bridging support we need to be able to support up
 	 * to 8 Traffic Priorities; each of which will be assigned to its
 	 * own TX Queue in order to prevent Head-Of-Line Blocking.
 	 */
+	q1g = 8;
 	if (adap->params.nports * 8 > avail_eth_qsets) {
 		dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n",
 			avail_eth_qsets, adap->params.nports * 8);
 		return -ENOMEM;
 	}
-	for_each_port(adap, i) {
+	if (adap->params.nports * ncpus < avail_eth_qsets)
-		struct port_info *pi = adap2pinfo(adap, i);
+		q10g = max(8U, ncpus);
+	else
+		q10g = max(8U, q10g);
-		pi->first_qset = qidx;
+	while ((q10g * n10g) > (avail_eth_qsets - n1g * q1g))
-		pi->nqsets = is_kdump_kernel() ? 1 : 8;
+		q10g--;
-		qidx += pi->nqsets;
-	}
-#else /* !CONFIG_CHELSIO_T4_DCB */
-	/* We default to 1 queue per non-10G port and up to # of cores queues
-	 * per 10G port.
-	 */
-	if (n10g)
-		q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g;
-	if (q10g > netif_get_num_default_rss_queues())
-		q10g = netif_get_num_default_rss_queues();
-	if (is_kdump_kernel())
+#else /* !CONFIG_CHELSIO_T4_DCB */
+	q1g = 1;
+	q10g = min(q10g, ncpus);
+#endif /* !CONFIG_CHELSIO_T4_DCB */
+	if (is_kdump_kernel()) {
 		q10g = 1;
+		q1g = 1;
+	}
 	for_each_port(adap, i) {
 		struct port_info *pi = adap2pinfo(adap, i);
 		pi->first_qset = qidx;
-		pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
+		pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : q1g;
 		qidx += pi->nqsets;
 	}
-#endif /* !CONFIG_CHELSIO_T4_DCB */
 	s->ethqsets = qidx;
 	s->max_ethqsets = qidx;   /* MSI-X may lower it later */
 		 * capped by the number of available cores.
 		 */
 		num_ulds = adap->num_uld + adap->num_ofld_uld;
-		i = min_t(u32, MAX_OFLD_QSETS, num_online_cpus());
+		i = min_t(u32, MAX_OFLD_QSETS, ncpus);
 		avail_uld_qsets = roundup(i, adap->params.nports);
 		if (avail_qsets < num_ulds * adap->params.nports) {
 			adap->params.offload = 0;

drivers/net/ethernet/freescale/dpaa/dpaa_eth.c+108−6

@@ -1,4 +1,5 @@
1	/* Copyright 2008 - 2016 Freescale Semiconductor Inc.	1	/* Copyright 2008 - 2016 Freescale Semiconductor Inc.
		2	* Copyright 2020 NXP
2	*	3	*
3	* Redistribution and use in source and binary forms, with or without	4	* Redistribution and use in source and binary forms, with or without
4	* modification, are permitted provided that the following conditions are met:	5	* modification, are permitted provided that the following conditions are met:
@@ -123,7 +124,22 @@ MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms"); · 118 unmodified lines
123	#define FSL_QMAN_MAX_OAL 127	124	#define FSL_QMAN_MAX_OAL 127
124		125
125	/* Default alignment for start of data in an Rx FD */	126	/* Default alignment for start of data in an Rx FD */
		127	#ifdef CONFIG_DPAA_ERRATUM_A050385
		128	/* aligning data start to 64 avoids DMA transaction splits, unless the buffer
		129	* is crossing a 4k page boundary
		130	*/
		131	#define DPAA_FD_DATA_ALIGNMENT (fman_has_errata_a050385() ? 64 : 16)
		132	/* aligning to 256 avoids DMA transaction splits caused by 4k page boundary
		133	* crossings; also, all SG fragments except the last must have a size multiple
		134	* of 256 to avoid DMA transaction splits
		135	*/
		136	#define DPAA_A050385_ALIGN 256
		137	#define DPAA_FD_RX_DATA_ALIGNMENT (fman_has_errata_a050385() ? \
		138	DPAA_A050385_ALIGN : 16)
		139	#else
126	#define DPAA_FD_DATA_ALIGNMENT 16	140	#define DPAA_FD_DATA_ALIGNMENT 16
		141	#define DPAA_FD_RX_DATA_ALIGNMENT DPAA_FD_DATA_ALIGNMENT
		142	#endif
127		143
128	/* The DPAA requires 256 bytes reserved and mapped for the SGT */	144	/* The DPAA requires 256 bytes reserved and mapped for the SGT */
129	#define DPAA_SGT_SIZE 256	145	#define DPAA_SGT_SIZE 256
@@ -158,8 +174,13 @@ MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms"); · 28 unmodified lines
158	#define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result)	174	#define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result)
159	#define DPAA_TIME_STAMP_SIZE 8	175	#define DPAA_TIME_STAMP_SIZE 8
160	#define DPAA_HASH_RESULTS_SIZE 8	176	#define DPAA_HASH_RESULTS_SIZE 8
		177	#ifdef CONFIG_DPAA_ERRATUM_A050385
		178	#define DPAA_RX_PRIV_DATA_SIZE (DPAA_A050385_ALIGN - (DPAA_PARSE_RESULTS_SIZE\
		179	+ DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE))
		180	#else
161	#define DPAA_RX_PRIV_DATA_SIZE (u16)(DPAA_TX_PRIV_DATA_SIZE + \	181	#define DPAA_RX_PRIV_DATA_SIZE (u16)(DPAA_TX_PRIV_DATA_SIZE + \
162	dpaa_rx_extra_headroom)	182	dpaa_rx_extra_headroom)
		183	#endif
163		184
164	#define DPAA_ETH_PCD_RXQ_NUM 128	185	#define DPAA_ETH_PCD_RXQ_NUM 128
165		186
@@ -180,7 +201,12 @@ static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS]; · 14 unmodified lines
180		201
181	#define DPAA_BP_RAW_SIZE 4096	202	#define DPAA_BP_RAW_SIZE 4096
182		203
		204	#ifdef CONFIG_DPAA_ERRATUM_A050385
		205	#define dpaa_bp_size(raw_size) (SKB_WITH_OVERHEAD(raw_size) & \
		206	~(DPAA_A050385_ALIGN - 1))
		207	#else
183	#define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD(raw_size)	208	#define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD(raw_size)
		209	#endif
184		210
185	static int dpaa_max_frm;	211	static int dpaa_max_frm;
186		212
@@ -1192,7 +1218,7 @@ static int dpaa_eth_init_rx_port(struct fman_port port, struct dpaa_bp bp, · 1005 unmodified lines
1192	buf_prefix_content.pass_prs_result = true;	1218	buf_prefix_content.pass_prs_result = true;
1193	buf_prefix_content.pass_hash_result = true;	1219	buf_prefix_content.pass_hash_result = true;
1194	buf_prefix_content.pass_time_stamp = true;	1220	buf_prefix_content.pass_time_stamp = true;
1195	buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;	1221	buf_prefix_content.data_align = DPAA_FD_RX_DATA_ALIGNMENT;
1196		1222
1197	rx_p = &params.specific_params.rx_params;	1223	rx_p = &params.specific_params.rx_params;
1198	rx_p->err_fqid = errq->fqid;	1224	rx_p->err_fqid = errq->fqid;
@@ -1662,6 +1688,8 @@ static u8 rx_csum_offload(const struct dpaa_priv priv, const struct qm_fd fd) · 463 unmodified lines
1662	return CHECKSUM_NONE;	1688	return CHECKSUM_NONE;
1663	}	1689	}
1664		1690
		1691	#define PTR_IS_ALIGNED(x, a) (IS_ALIGNED((unsigned long)(x), (a)))
		1692
1665	/* Build a linear skb around the received buffer.	1693	/* Build a linear skb around the received buffer.
1666	* We are guaranteed there is enough room at the end of the data buffer to	1694	* We are guaranteed there is enough room at the end of the data buffer to
1667	* accommodate the shared info area of the skb.	1695	* accommodate the shared info area of the skb.
@@ -1733,8 +1761,7 @@ static struct sk_buff sg_fd_to_skb(const struct dpaa_priv priv, · 65 unmodified lines
1733		1761
1734	sg_addr = qm_sg_addr(&sgt[i]);	1762	sg_addr = qm_sg_addr(&sgt[i]);
1735	sg_vaddr = phys_to_virt(sg_addr);	1763	sg_vaddr = phys_to_virt(sg_addr);
1736	WARN_ON(!IS_ALIGNED((unsigned long)sg_vaddr,	1764	WARN_ON(!PTR_IS_ALIGNED(sg_vaddr, SMP_CACHE_BYTES));
1737	SMP_CACHE_BYTES));
1738		1765
1739	dma_unmap_page(priv->rx_dma_dev, sg_addr,	1766	dma_unmap_page(priv->rx_dma_dev, sg_addr,
1740	DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);	1767	DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
@@ -2022,6 +2049,75 @@ static inline int dpaa_xmit(struct dpaa_priv *priv, · 281 unmodified lines
2022	return 0;	2049	return 0;
2023	}	2050	}
2024		2051
		2052	#ifdef CONFIG_DPAA_ERRATUM_A050385
		2053	int dpaa_a050385_wa(struct net_device net_dev, struct sk_buff *s)
		2054	{
		2055	struct dpaa_priv *priv = netdev_priv(net_dev);
		2056	struct sk_buff new_skb, skb = *s;
		2057	unsigned char *start, i;
		2058
		2059	/* check linear buffer alignment */
		2060	if (!PTR_IS_ALIGNED(skb->data, DPAA_A050385_ALIGN))
		2061	goto workaround;
		2062
		2063	/* linear buffers just need to have an aligned start */
		2064	if (!skb_is_nonlinear(skb))
		2065	return 0;
		2066
		2067	/* linear data size for nonlinear skbs needs to be aligned */
		2068	if (!IS_ALIGNED(skb_headlen(skb), DPAA_A050385_ALIGN))
		2069	goto workaround;
		2070
		2071	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
		2072	skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
		2073
		2074	/* all fragments need to have aligned start addresses */
		2075	if (!IS_ALIGNED(skb_frag_off(frag), DPAA_A050385_ALIGN))
		2076	goto workaround;
		2077
		2078	/* all but last fragment need to have aligned sizes */
		2079	if (!IS_ALIGNED(skb_frag_size(frag), DPAA_A050385_ALIGN) &&
		2080	(i < skb_shinfo(skb)->nr_frags - 1))
		2081	goto workaround;
		2082	}
		2083
		2084	return 0;
		2085
		2086	workaround:
		2087	/* copy all the skb content into a new linear buffer */
		2088	new_skb = netdev_alloc_skb(net_dev, skb->len + DPAA_A050385_ALIGN - 1 +
		2089	priv->tx_headroom);
		2090	if (!new_skb)
		2091	return -ENOMEM;
		2092
		2093	/* NET_SKB_PAD bytes already reserved, adding up to tx_headroom */
		2094	skb_reserve(new_skb, priv->tx_headroom - NET_SKB_PAD);
		2095
		2096	/* Workaround for DPAA_A050385 requires data start to be aligned */
		2097	start = PTR_ALIGN(new_skb->data, DPAA_A050385_ALIGN);
		2098	if (start - new_skb->data != 0)
		2099	skb_reserve(new_skb, start - new_skb->data);
		2100
		2101	skb_put(new_skb, skb->len);
		2102	skb_copy_bits(skb, 0, new_skb->data, skb->len);
		2103	skb_copy_header(new_skb, skb);
		2104	new_skb->dev = skb->dev;
		2105
		2106	/* We move the headroom when we align it so we have to reset the
		2107	* network and transport header offsets relative to the new data
		2108	* pointer. The checksum offload relies on these offsets.
		2109	*/
		2110	skb_set_network_header(new_skb, skb_network_offset(skb));
		2111	skb_set_transport_header(new_skb, skb_transport_offset(skb));
		2112
		2113	/* TODO: does timestamping need the result in the old skb? */
		2114	dev_kfree_skb(skb);
		2115	*s = new_skb;
		2116
		2117	return 0;
		2118	}
		2119	#endif
		2120
2025	static netdev_tx_t	2121	static netdev_tx_t
2026	dpaa_start_xmit(struct sk_buff skb, struct net_device net_dev)	2122	dpaa_start_xmit(struct sk_buff skb, struct net_device net_dev)
2027	{	2123	{
@@ -2068,6 +2164,14 @@ dpaa_start_xmit(struct sk_buff skb, struct net_device net_dev) · 40 unmodified lines
2068	nonlinear = skb_is_nonlinear(skb);	2164	nonlinear = skb_is_nonlinear(skb);
2069	}	2165	}
2070		2166
		2167	#ifdef CONFIG_DPAA_ERRATUM_A050385
		2168	if (unlikely(fman_has_errata_a050385())) {
		2169	if (dpaa_a050385_wa(net_dev, &skb))
		2170	goto enomem;
		2171	nonlinear = skb_is_nonlinear(skb);
		2172	}
		2173	#endif
		2174
2071	if (nonlinear) {	2175	if (nonlinear) {
2072	/* Just create a S/G fd based on the skb */	2176	/* Just create a S/G fd based on the skb */
2073	err = skb_to_sg_fd(priv, skb, &fd);	2177	err = skb_to_sg_fd(priv, skb, &fd);
@@ -2741,9 +2845,7 @@ static inline u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl) · 667 unmodified lines
2741	headroom = (u16)(bl->priv_data_size + DPAA_PARSE_RESULTS_SIZE +	2845	headroom = (u16)(bl->priv_data_size + DPAA_PARSE_RESULTS_SIZE +
2742	DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE);	2846	DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE);
2743		2847
2744	return DPAA_FD_DATA_ALIGNMENT ? ALIGN(headroom,	2848	return ALIGN(headroom, DPAA_FD_DATA_ALIGNMENT);
2745	DPAA_FD_DATA_ALIGNMENT) :
2746	headroom;
2747	}	2849	}
2748		2850
2749	static int dpaa_eth_probe(struct platform_device *pdev)	2851	static int dpaa_eth_probe(struct platform_device *pdev)

drivers/net/ethernet/freescale/fec_main.c+3−3

@@ -2529,15 +2529,15 @@ fec_enet_set_coalesce(struct net_device ndev, struct ethtool_coalesce ec) · 2528 unmodified lines
2529	return -EINVAL;	2529	return -EINVAL;
2530	}	2530	}
2531		2531
2532	cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);	2532	cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs);
2533	if (cycle > 0xFFFF) {	2533	if (cycle > 0xFFFF) {
2534	dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");	2534	dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
2535	return -EINVAL;	2535	return -EINVAL;
2536	}	2536	}
2537		2537
2538	cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);	2538	cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs);
2539	if (cycle > 0xFFFF) {	2539	if (cycle > 0xFFFF) {
2540	dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");	2540	dev_err(dev, "Tx coalesced usec exceed hardware limitation\n");
2541	return -EINVAL;	2541	return -EINVAL;
2542	}	2542	}
2543		2543

drivers/net/ethernet/freescale/fman/Kconfig+28−0

@@ -8,3 +8,31 @@ config FSL_FMAN · 7 unmodified lines
8	help	8	help
9	Freescale Data-Path Acceleration Architecture Frame Manager	9	Freescale Data-Path Acceleration Architecture Frame Manager
10	(FMan) support	10	(FMan) support
		11
		12	config DPAA_ERRATUM_A050385
		13	bool
		14	depends on ARM64 && FSL_DPAA
		15	default y
		16	help
		17	DPAA FMan erratum A050385 software workaround implementation:
		18	align buffers, data start, SG fragment length to avoid FMan DMA
		19	splits.
		20	FMAN DMA read or writes under heavy traffic load may cause FMAN
		21	internal resource leak thus stopping further packet processing.
		22	The FMAN internal queue can overflow when FMAN splits single
		23	read or write transactions into multiple smaller transactions
		24	such that more than 17 AXI transactions are in flight from FMAN
		25	to interconnect. When the FMAN internal queue overflows, it can
		26	stall further packet processing. The issue can occur with any
		27	one of the following three conditions:
		28	1. FMAN AXI transaction crosses 4K address boundary (Errata
		29	A010022)
		30	2. FMAN DMA address for an AXI transaction is not 16 byte
		31	aligned, i.e. the last 4 bits of an address are non-zero
		32	3. Scatter Gather (SG) frames have more than one SG buffer in
		33	the SG list and any one of the buffers, except the last
		34	buffer in the SG list has data size that is not a multiple
		35	of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
		36	With any one of the above three conditions present, there is
		37	likelihood of stalled FMAN packet processing, especially under
		38	stress with multiple ports injecting line-rate traffic.

drivers/net/ethernet/freescale/fman/fman.c+18−0

 /*
  * Copyright 2008-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
 	u32 qmi_def_tnums_thresh;
 };
+#ifdef CONFIG_DPAA_ERRATUM_A050385
+static bool fman_has_err_a050385;
+#endif
 static irqreturn_t fman_exceptions(struct fman *fman,
 				   enum fman_exceptions exception)
 {
 }
 EXPORT_SYMBOL(fman_bind);
+#ifdef CONFIG_DPAA_ERRATUM_A050385
+bool fman_has_errata_a050385(void)
+{
+	return fman_has_err_a050385;
+}
+EXPORT_SYMBOL(fman_has_errata_a050385);
+#endif
 static irqreturn_t fman_err_irq(int irq, void *handle)
 {
 	struct fman *fman = (struct fman *)handle;
 		goto fman_free;
 	}
+#ifdef CONFIG_DPAA_ERRATUM_A050385
+	fman_has_err_a050385 =
+		of_property_read_bool(fm_node, "fsl,erratum-a050385");
+#endif
 	return fman;
 fman_node_put:

drivers/net/ethernet/freescale/fman/fman.h+5−0

 /*
  * Copyright 2008-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
 int fman_get_rx_extra_headroom(void);
+#ifdef CONFIG_DPAA_ERRATUM_A050385
+bool fman_has_errata_a050385(void);
+#endif
 struct fman *fman_bind(struct device *dev);
 #endif /* __FM_H */

drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h+1−0

@@ -46,6 +46,7 @@ enum HCLGE_MBX_OPCODE { · 45 unmodified lines
46	HCLGE_MBX_PUSH_VLAN_INFO, /* (PF -> VF) push port base vlan */	46	HCLGE_MBX_PUSH_VLAN_INFO, /* (PF -> VF) push port base vlan */
47	HCLGE_MBX_GET_MEDIA_TYPE, /* (VF -> PF) get media type */	47	HCLGE_MBX_GET_MEDIA_TYPE, /* (VF -> PF) get media type */
48	HCLGE_MBX_PUSH_PROMISC_INFO, /* (PF -> VF) push vf promisc info */	48	HCLGE_MBX_PUSH_PROMISC_INFO, /* (PF -> VF) push vf promisc info */
		49	HCLGE_MBX_VF_UNINIT, /* (VF -> PF) vf is unintializing */
49		50
50	HCLGE_MBX_GET_VF_FLR_STATUS = 200, /* (M7 -> PF) get vf flr status */	51	HCLGE_MBX_GET_VF_FLR_STATUS = 200, /* (M7 -> PF) get vf flr status */
51	HCLGE_MBX_PUSH_LINK_STATUS, /* (M7 -> PF) get port link status */	52	HCLGE_MBX_PUSH_LINK_STATUS, /* (M7 -> PF) get port link status */

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c+1−1

@@ -1711,7 +1711,7 @@ static int hns3_setup_tc(struct net_device netdev, void type_data) · 1710 unmodified lines
1711	netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);	1711	netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
1712		1712
1713	return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?	1713	return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1714	kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;	1714	kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP;
1715	}	1715	}
1716		1716
1717	static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,	1717	static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c+42−5

@@ -2446,10 +2446,12 @@ static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, · 2445 unmodified lines
2446		2446
2447	int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)	2447	int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2448	{	2448	{
		2449	struct hclge_mac *mac = &hdev->hw.mac;
2449	int ret;	2450	int ret;
2450		2451
2451	duplex = hclge_check_speed_dup(duplex, speed);	2452	duplex = hclge_check_speed_dup(duplex, speed);
2452	if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)	2453	if (!mac->support_autoneg && mac->speed == speed &&
		2454	mac->duplex == duplex)
2453	return 0;	2455	return 0;
2454		2456
2455	ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);	2457	ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
@@ -7743,16 +7745,27 @@ static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, · 5287 unmodified lines
7743	struct hclge_desc desc;	7745	struct hclge_desc desc;
7744	int ret;	7746	int ret;
7745		7747
7746	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);	7748	/* read current vlan filter parameter */
7747		7749	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true);
7748	req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;	7750	req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
7749	req->vlan_type = vlan_type;	7751	req->vlan_type = vlan_type;
7750	req->vlan_fe = filter_en ? fe_type : 0;
7751	req->vf_id = vf_id;	7752	req->vf_id = vf_id;
7752		7753
		7754	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
		7755	if (ret) {
		7756	dev_err(&hdev->pdev->dev,
		7757	"failed to get vlan filter config, ret = %d.\n", ret);
		7758	return ret;
		7759	}
		7760
		7761	/* modify and write new config parameter */
		7762	hclge_cmd_reuse_desc(&desc, false);
		7763	req->vlan_fe = filter_en ?
		7764	(req->vlan_fe \| fe_type) : (req->vlan_fe & ~fe_type);
		7765
7753	ret = hclge_cmd_send(&hdev->hw, &desc, 1);	7766	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7754	if (ret)	7767	if (ret)
7755	dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",	7768	dev_err(&hdev->pdev->dev, "failed to set vlan filter, ret = %d.\n",
7756	ret);	7769	ret);
7757		7770
7758	return ret;	7771	return ret;
@@ -8270,6 +8283,7 @@ void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) · 511 unmodified lines
8270	kfree(vlan);	8283	kfree(vlan);
8271	}	8284	}
8272	}	8285	}
		8286	clear_bit(vport->vport_id, hdev->vf_vlan_full);
8273	}	8287	}
8274		8288
8275	void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev)	8289	void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev)
@@ -8486,6 +8500,28 @@ static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, · 210 unmodified lines
8486	}	8500	}
8487	}	8501	}
8488		8502
		8503	static void hclge_clear_vf_vlan(struct hclge_dev *hdev)
		8504	{
		8505	struct hclge_vlan_info *vlan_info;
		8506	struct hclge_vport *vport;
		8507	int ret;
		8508	int vf;
		8509
		8510	/* clear port base vlan for all vf */
		8511	for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) {
		8512	vport = &hdev->vport[vf];
		8513	vlan_info = &vport->port_base_vlan_cfg.vlan_info;
		8514
		8515	ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
		8516	vport->vport_id,
		8517	vlan_info->vlan_tag, true);
		8518	if (ret)
		8519	dev_err(&hdev->pdev->dev,
		8520	"failed to clear vf vlan for vf%d, ret = %d\n",
		8521	vf - HCLGE_VF_VPORT_START_NUM, ret);
		8522	}
		8523	}
		8524
8489	int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,	8525	int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
8490	u16 vlan_id, bool is_kill)	8526	u16 vlan_id, bool is_kill)
8491	{	8527	{
@@ -9895,6 +9931,7 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) · 1403 unmodified lines
9895	struct hclge_mac *mac = &hdev->hw.mac;	9931	struct hclge_mac *mac = &hdev->hw.mac;
9896		9932
9897	hclge_reset_vf_rate(hdev);	9933	hclge_reset_vf_rate(hdev);
		9934	hclge_clear_vf_vlan(hdev);
9898	hclge_misc_affinity_teardown(hdev);	9935	hclge_misc_affinity_teardown(hdev);
9899	hclge_state_uninit(hdev);	9936	hclge_state_uninit(hdev);
9900		9937

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c+1−0

@@ -799,6 +799,7 @@ void hclge_mbx_handler(struct hclge_dev *hdev) · 798 unmodified lines
799	hclge_get_link_mode(vport, req);	799	hclge_get_link_mode(vport, req);
800	break;	800	break;
801	case HCLGE_MBX_GET_VF_FLR_STATUS:	801	case HCLGE_MBX_GET_VF_FLR_STATUS:
		802	case HCLGE_MBX_VF_UNINIT:
802	hclge_rm_vport_all_mac_table(vport, true,	803	hclge_rm_vport_all_mac_table(vport, true,
803	HCLGE_MAC_ADDR_UC);	804	HCLGE_MAC_ADDR_UC);
804	hclge_rm_vport_all_mac_table(vport, true,	805	hclge_rm_vport_all_mac_table(vport, true,

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c+3−0

@@ -2803,6 +2803,9 @@ static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) · 2802 unmodified lines
2803	{	2803	{
2804	hclgevf_state_uninit(hdev);	2804	hclgevf_state_uninit(hdev);
2805		2805
		2806	hclgevf_send_mbx_msg(hdev, HCLGE_MBX_VF_UNINIT, 0, NULL, 0,
		2807	false, NULL, 0);
		2808
2806	if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {	2809	if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2807	hclgevf_misc_irq_uninit(hdev);	2810	hclgevf_misc_irq_uninit(hdev);
2808	hclgevf_uninit_msi(hdev);	2811	hclgevf_uninit_msi(hdev);

drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c+1−0

@@ -297,6 +297,7 @@ static int set_hw_ioctxt(struct hinic_hwdev *hwdev, unsigned int rq_depth, · 296 unmodified lines
297	}	297	}
298		298
299	hw_ioctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif);	299	hw_ioctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
		300	hw_ioctxt.ppf_idx = HINIC_HWIF_PPF_IDX(hwif);
300		301
301	hw_ioctxt.set_cmdq_depth = HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT;	302	hw_ioctxt.set_cmdq_depth = HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT;
302	hw_ioctxt.cmdq_depth = 0;	303	hw_ioctxt.cmdq_depth = 0;

drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h+1−1

@@ -151,8 +151,8 @@ struct hinic_cmd_hw_ioctxt { · 150 unmodified lines
151		151
152	u8 lro_en;	152	u8 lro_en;
153	u8 rsvd3;	153	u8 rsvd3;
		154	u8 ppf_idx;
154	u8 rsvd4;	155	u8 rsvd4;
155	u8 rsvd5;
156		156
157	u16 rq_depth;	157	u16 rq_depth;
158	u16 rx_buf_sz_idx;	158	u16 rx_buf_sz_idx;

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h+1−0

@@ -137,6 +137,7 @@ · 136 unmodified lines
137	#define HINIC_HWIF_FUNC_IDX(hwif) ((hwif)->attr.func_idx)	137	#define HINIC_HWIF_FUNC_IDX(hwif) ((hwif)->attr.func_idx)
138	#define HINIC_HWIF_PCI_INTF(hwif) ((hwif)->attr.pci_intf_idx)	138	#define HINIC_HWIF_PCI_INTF(hwif) ((hwif)->attr.pci_intf_idx)
139	#define HINIC_HWIF_PF_IDX(hwif) ((hwif)->attr.pf_idx)	139	#define HINIC_HWIF_PF_IDX(hwif) ((hwif)->attr.pf_idx)
		140	#define HINIC_HWIF_PPF_IDX(hwif) ((hwif)->attr.ppf_idx)
140		141
141	#define HINIC_FUNC_TYPE(hwif) ((hwif)->attr.func_type)	142	#define HINIC_FUNC_TYPE(hwif) ((hwif)->attr.func_type)
142	#define HINIC_IS_PF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PF)	143	#define HINIC_IS_PF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PF)

drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h+1−0

@@ -94,6 +94,7 @@ struct hinic_rq { · 93 unmodified lines
94		94
95	struct hinic_wq *wq;	95	struct hinic_wq *wq;
96		96
		97	struct cpumask affinity_mask;
97	u32 irq;	98	u32 irq;
98	u16 msix_entry;	99	u16 msix_entry;
99		100

drivers/net/ethernet/huawei/hinic/hinic_main.c+2−1

@@ -356,7 +356,8 @@ static void hinic_enable_rss(struct hinic_dev *nic_dev) · 355 unmodified lines
356	if (!num_cpus)	356	if (!num_cpus)
357	num_cpus = num_online_cpus();	357	num_cpus = num_online_cpus();
358		358
359	nic_dev->num_qps = min_t(u16, nic_dev->max_qps, num_cpus);	359	nic_dev->num_qps = hinic_hwdev_num_qps(hwdev);
		360	nic_dev->num_qps = min_t(u16, nic_dev->num_qps, num_cpus);
360		361
361	nic_dev->rss_limit = nic_dev->num_qps;	362	nic_dev->rss_limit = nic_dev->num_qps;
362	nic_dev->num_rss = nic_dev->num_qps;	363	nic_dev->num_rss = nic_dev->num_qps;

drivers/net/ethernet/huawei/hinic/hinic_rx.c+2−3

 	struct hinic_hwdev *hwdev = nic_dev->hwdev;
 	struct hinic_rq *rq = rxq->rq;
 	struct hinic_qp *qp;
-	struct cpumask mask;
 	int err;
 	rx_add_napi(rxq);
 	}
 	qp = container_of(rq, struct hinic_qp, rq);
-	cpumask_set_cpu(qp->q_id % num_online_cpus(), &mask);
+	cpumask_set_cpu(qp->q_id % num_online_cpus(), &rq->affinity_mask);
-	return irq_set_affinity_hint(rq->irq, &mask);
+	return irq_set_affinity_hint(rq->irq, &rq->affinity_mask);
 }
 static void rx_free_irq(struct hinic_rxq *rxq)

drivers/net/ethernet/ibm/ibmvnic.c+22−2

 {
 	struct ibmvnic_rwi *rwi;
 	struct ibmvnic_adapter *adapter;
+	bool saved_state = false;
+	unsigned long flags;
 	u32 reset_state;
 	int rc = 0;
 		return;
 	}
-	reset_state = adapter->state;
 	rwi = get_next_rwi(adapter);
 	while (rwi) {
+		spin_lock_irqsave(&adapter->state_lock, flags);
 		if (adapter->state == VNIC_REMOVING ||
 		    adapter->state == VNIC_REMOVED) {
+			spin_unlock_irqrestore(&adapter->state_lock, flags);
 			kfree(rwi);
 			rc = EBUSY;
 			break;
 		}
+		if (!saved_state) {
+			reset_state = adapter->state;
+			adapter->state = VNIC_RESETTING;
+			saved_state = true;
+		}
+		spin_unlock_irqrestore(&adapter->state_lock, flags);
 		if (rwi->reset_reason == VNIC_RESET_CHANGE_PARAM) {
 			/* CHANGE_PARAM requestor holds rtnl_lock */
 			rc = do_change_param_reset(adapter, rwi, reset_state);
 			  __ibmvnic_delayed_reset);
 	INIT_LIST_HEAD(&adapter->rwi_list);
 	spin_lock_init(&adapter->rwi_lock);
+	spin_lock_init(&adapter->state_lock);
 	mutex_init(&adapter->fw_lock);
 	init_completion(&adapter->init_done);
 	init_completion(&adapter->fw_done);
 {
 	struct net_device *netdev = dev_get_drvdata(&dev->dev);
 	struct ibmvnic_adapter *adapter = netdev_priv(netdev);
+	unsigned long flags;
+	spin_lock_irqsave(&adapter->state_lock, flags);
+	if (adapter->state == VNIC_RESETTING) {
+		spin_unlock_irqrestore(&adapter->state_lock, flags);
+		return -EBUSY;
+	}
 	adapter->state = VNIC_REMOVING;
+	spin_unlock_irqrestore(&adapter->state_lock, flags);
 	rtnl_lock();
 	unregister_netdevice(netdev);

drivers/net/ethernet/ibm/ibmvnic.h+5−1

 		 VNIC_CLOSING,
 		 VNIC_CLOSED,
 		 VNIC_REMOVING,
-		 VNIC_REMOVED};
+		 VNIC_REMOVED,
+		 VNIC_RESETTING};
 enum ibmvnic_reset_reason {VNIC_RESET_FAILOVER = 1,
 			   VNIC_RESET_MOBILITY,
 	struct ibmvnic_tunables desired;
 	struct ibmvnic_tunables fallback;
+	/* Used for serializatin of state field */
+	spinlock_t state_lock;
 };

drivers/net/ethernet/marvell/mvmdio.c+3−3

@@ -347,7 +347,7 @@ static int orion_mdio_probe(struct platform_device *pdev) · 346 unmodified lines
347	}	347	}
348		348
349		349
350	dev->err_interrupt = platform_get_irq(pdev, 0);	350	dev->err_interrupt = platform_get_irq_optional(pdev, 0);
351	if (dev->err_interrupt > 0 &&	351	if (dev->err_interrupt > 0 &&
352	resource_size(r) < MVMDIO_ERR_INT_MASK + 4) {	352	resource_size(r) < MVMDIO_ERR_INT_MASK + 4) {
353	dev_err(&pdev->dev,	353	dev_err(&pdev->dev,
@@ -364,8 +364,8 @@ static int orion_mdio_probe(struct platform_device *pdev) · 10 unmodified lines
364	writel(MVMDIO_ERR_INT_SMI_DONE,	364	writel(MVMDIO_ERR_INT_SMI_DONE,
365	dev->regs + MVMDIO_ERR_INT_MASK);	365	dev->regs + MVMDIO_ERR_INT_MASK);
366		366
367	} else if (dev->err_interrupt == -EPROBE_DEFER) {	367	} else if (dev->err_interrupt < 0) {
368	ret = -EPROBE_DEFER;	368	ret = dev->err_interrupt;
369	goto out_mdio;	369	goto out_mdio;
370	}	370	}
371		371

drivers/net/ethernet/mellanox/mlx5/core/en_main.c+1−2

 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
 {
-	struct net_device *netdev = priv->netdev;
 	struct mlx5_core_dev *mdev = priv->mdev;
 #ifdef CONFIG_MLX5_CORE_EN_DCB
 		mlx5e_monitor_counter_cleanup(priv);
 	mlx5e_disable_async_events(priv);
-	mlx5_lag_remove(mdev, netdev);
+	mlx5_lag_remove(mdev);
 }
 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)

drivers/net/ethernet/mellanox/mlx5/core/en_rep.c+1−2

 static void mlx5e_uplink_rep_disable(struct mlx5e_priv *priv)
 {
-	struct net_device *netdev = priv->netdev;
 	struct mlx5_core_dev *mdev = priv->mdev;
 	struct mlx5e_rep_priv *rpriv = priv->ppriv;
 #endif
 	mlx5_notifier_unregister(mdev, &priv->events_nb);
 	cancel_work_sync(&rpriv->uplink_priv.reoffload_flows_work);
-	mlx5_lag_remove(mdev, netdev);
+	mlx5_lag_remove(mdev);
 }
 static MLX5E_DEFINE_STATS_GRP(sw_rep, 0);

drivers/net/ethernet/mellanox/mlx5/core/lag.c+3−8

 	struct mlx5_lag *ldev;
 	int changed = 0;
-	if (!net_eq(dev_net(ndev), &init_net))
-		return NOTIFY_DONE;
 	if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE))
 		return NOTIFY_DONE;
 	if (!ldev->nb.notifier_call) {
 		ldev->nb.notifier_call = mlx5_lag_netdev_event;
-		if (register_netdevice_notifier_dev_net(netdev, &ldev->nb,
+		if (register_netdevice_notifier_net(&init_net, &ldev->nb)) {
-							&ldev->nn)) {
 			ldev->nb.notifier_call = NULL;
 			mlx5_core_err(dev, "Failed to register LAG netdev notifier\n");
 		}
 }
 /* Must be called with intf_mutex held */
-void mlx5_lag_remove(struct mlx5_core_dev *dev, struct net_device *netdev)
+void mlx5_lag_remove(struct mlx5_core_dev *dev)
 {
 	struct mlx5_lag *ldev;
 	int i;
 	if (i == MLX5_MAX_PORTS) {
 		if (ldev->nb.notifier_call)
-			unregister_netdevice_notifier_dev_net(netdev, &ldev->nb,
+			unregister_netdevice_notifier_net(&init_net, &ldev->nb);
-							      &ldev->nn);
 		mlx5_lag_mp_cleanup(ldev);
 		cancel_delayed_work_sync(&ldev->bond_work);
 		mlx5_lag_dev_free(ldev);

drivers/net/ethernet/mellanox/mlx5/core/lag.h+0−1

@@ -44,7 +44,6 @@ struct mlx5_lag { · 43 unmodified lines
44	struct workqueue_struct *wq;	44	struct workqueue_struct *wq;
45	struct delayed_work bond_work;	45	struct delayed_work bond_work;
46	struct notifier_block nb;	46	struct notifier_block nb;
47	struct netdev_net_notifier nn;
48	struct lag_mp lag_mp;	47	struct lag_mp lag_mp;
49	};	48	};
50		49

drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h+1−1

@@ -157,7 +157,7 @@ int mlx5_query_qcam_reg(struct mlx5_core_dev mdev, u32 qcam, · 156 unmodified lines
157	u8 feature_group, u8 access_reg_group);	157	u8 feature_group, u8 access_reg_group);
158		158
159	void mlx5_lag_add(struct mlx5_core_dev dev, struct net_device netdev);	159	void mlx5_lag_add(struct mlx5_core_dev dev, struct net_device netdev);
160	void mlx5_lag_remove(struct mlx5_core_dev dev, struct net_device netdev);	160	void mlx5_lag_remove(struct mlx5_core_dev *dev);
161		161
162	int mlx5_irq_table_init(struct mlx5_core_dev *dev);	162	int mlx5_irq_table_init(struct mlx5_core_dev *dev);
163	void mlx5_irq_table_cleanup(struct mlx5_core_dev *dev);	163	void mlx5_irq_table_cleanup(struct mlx5_core_dev *dev);

drivers/net/ethernet/mellanox/mlxsw/pci_hw.h+1−1

@@ -28,7 +28,7 @@ · 27 unmodified lines
28	#define MLXSW_PCI_SW_RESET 0xF0010	28	#define MLXSW_PCI_SW_RESET 0xF0010
29	#define MLXSW_PCI_SW_RESET_RST_BIT BIT(0)	29	#define MLXSW_PCI_SW_RESET_RST_BIT BIT(0)
30	#define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 900000	30	#define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 900000
31	#define MLXSW_PCI_SW_RESET_WAIT_MSECS 100	31	#define MLXSW_PCI_SW_RESET_WAIT_MSECS 200
32	#define MLXSW_PCI_FW_READY 0xA1844	32	#define MLXSW_PCI_FW_READY 0xA1844
33	#define MLXSW_PCI_FW_READY_MASK 0xFFFF	33	#define MLXSW_PCI_FW_READY_MASK 0xFFFF
34	#define MLXSW_PCI_FW_READY_MAGIC 0x5E	34	#define MLXSW_PCI_FW_READY_MAGIC 0x5E

drivers/net/ethernet/micrel/ks8851_mll.c+8−6

 {
 	struct net_device *netdev = pw;
 	struct ks_net *ks = netdev_priv(netdev);
+	unsigned long flags;
 	u16 status;
+	spin_lock_irqsave(&ks->statelock, flags);
 	/*this should be the first in IRQ handler */
 	ks_save_cmd_reg(ks);
 	status = ks_rdreg16(ks, KS_ISR);
 	if (unlikely(!status)) {
 		ks_restore_cmd_reg(ks);
+		spin_unlock_irqrestore(&ks->statelock, flags);
 		return IRQ_NONE;
 	}
 		ks->netdev->stats.rx_over_errors++;
 	/* this should be the last in IRQ handler*/
 	ks_restore_cmd_reg(ks);
+	spin_unlock_irqrestore(&ks->statelock, flags);
 	return IRQ_HANDLED;
 }
 	/* shutdown RX/TX QMU */
 	ks_disable_qmu(ks);
+	ks_disable_int(ks);
 	/* set powermode to soft power down to save power */
 	ks_set_powermode(ks, PMECR_PM_SOFTDOWN);
 {
 	netdev_tx_t retv = NETDEV_TX_OK;
 	struct ks_net *ks = netdev_priv(netdev);
+	unsigned long flags;
-	disable_irq(netdev->irq);
+	spin_lock_irqsave(&ks->statelock, flags);
-	ks_disable_int(ks);
-	spin_lock(&ks->statelock);
 	/* Extra space are required:
 	*  4 byte for alignment, 4 for status/length, 4 for CRC
 		dev_kfree_skb(skb);
 	} else
 		retv = NETDEV_TX_BUSY;
-	spin_unlock(&ks->statelock);
+	spin_unlock_irqrestore(&ks->statelock, flags);
-	ks_enable_int(ks);
-	enable_irq(netdev->irq);
 	return retv;
 }

drivers/net/ethernet/mscc/ocelot.c+17−11

 	return 0;
 }
-static void ocelot_port_set_mtu(struct ocelot *ocelot, int port, size_t mtu)
+/* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
+ * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
+ */
+static void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
 {
 	struct ocelot_port *ocelot_port = ocelot->ports[port];
+	int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
 	int atop_wm;
-	ocelot_port_writel(ocelot_port, mtu, DEV_MAC_MAXLEN_CFG);
+	ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
 	/* Set Pause WM hysteresis
-	 * 152 = 6 * mtu / OCELOT_BUFFER_CELL_SZ
+	 * 152 = 6 * maxlen / OCELOT_BUFFER_CELL_SZ
-	 * 101 = 4 * mtu / OCELOT_BUFFER_CELL_SZ
+	 * 101 = 4 * maxlen / OCELOT_BUFFER_CELL_SZ
 	 */
 	ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
 			 SYS_PAUSE_CFG_PAUSE_STOP(101) |
 			 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
 	/* Tail dropping watermark */
-	atop_wm = (ocelot->shared_queue_sz - 9 * mtu) / OCELOT_BUFFER_CELL_SZ;
+	atop_wm = (ocelot->shared_queue_sz - 9 * maxlen) /
-	ocelot_write_rix(ocelot, ocelot_wm_enc(9 * mtu),
+		   OCELOT_BUFFER_CELL_SZ;
+	ocelot_write_rix(ocelot, ocelot_wm_enc(9 * maxlen),
 			 SYS_ATOP, port);
 	ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
 }
 			   DEV_MAC_HDX_CFG);
 	/* Set Max Length and maximum tags allowed */
-	ocelot_port_set_mtu(ocelot, port, VLAN_ETH_FRAME_LEN);
+	ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
 	ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
 			   DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
+			   DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
 			   DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
 			   DEV_MAC_TAGS_CFG);
 	 * Only one port can be an NPI at the same time.
 	 */
 	if (cpu < ocelot->num_phys_ports) {
-		int mtu = VLAN_ETH_FRAME_LEN + OCELOT_TAG_LEN;
+		int sdu = ETH_DATA_LEN + OCELOT_TAG_LEN;
 		ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M |
 			     QSYS_EXT_CPU_CFG_EXT_CPU_PORT(cpu),
 			     QSYS_EXT_CPU_CFG);
 		if (injection == OCELOT_TAG_PREFIX_SHORT)
-			mtu += OCELOT_SHORT_PREFIX_LEN;
+			sdu += OCELOT_SHORT_PREFIX_LEN;
 		else if (injection == OCELOT_TAG_PREFIX_LONG)
-			mtu += OCELOT_LONG_PREFIX_LEN;
+			sdu += OCELOT_LONG_PREFIX_LEN;
-		ocelot_port_set_mtu(ocelot, cpu, mtu);
+		ocelot_port_set_maxlen(ocelot, cpu, sdu);
 	}
 	/* CPU port Injection/Extraction configuration */

drivers/net/ethernet/pensando/ionic/ionic_lif.c+4−4

@@ -1688,7 +1688,7 @@ static int ionic_set_vf_mac(struct net_device netdev, int vf, u8 mac) · 1687 unmodified lines
1688	if (!(is_zero_ether_addr(mac) \|\| is_valid_ether_addr(mac)))	1688	if (!(is_zero_ether_addr(mac) \|\| is_valid_ether_addr(mac)))
1689	return -EINVAL;	1689	return -EINVAL;
1690		1690
1691	down_read(&ionic->vf_op_lock);	1691	down_write(&ionic->vf_op_lock);
1692		1692
1693	if (vf >= pci_num_vf(ionic->pdev) \|\| !ionic->vfs) {	1693	if (vf >= pci_num_vf(ionic->pdev) \|\| !ionic->vfs) {
1694	ret = -EINVAL;	1694	ret = -EINVAL;
@@ -1698,7 +1698,7 @@ static int ionic_set_vf_mac(struct net_device netdev, int vf, u8 mac) · 3 unmodified lines
1698	ether_addr_copy(ionic->vfs[vf].macaddr, mac);	1698	ether_addr_copy(ionic->vfs[vf].macaddr, mac);
1699	}	1699	}
1700		1700
1701	up_read(&ionic->vf_op_lock);	1701	up_write(&ionic->vf_op_lock);
1702	return ret;	1702	return ret;
1703	}	1703	}
1704		1704
@@ -1719,7 +1719,7 @@ static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, · 14 unmodified lines
1719	if (proto != htons(ETH_P_8021Q))	1719	if (proto != htons(ETH_P_8021Q))
1720	return -EPROTONOSUPPORT;	1720	return -EPROTONOSUPPORT;
1721		1721
1722	down_read(&ionic->vf_op_lock);	1722	down_write(&ionic->vf_op_lock);
1723		1723
1724	if (vf >= pci_num_vf(ionic->pdev) \|\| !ionic->vfs) {	1724	if (vf >= pci_num_vf(ionic->pdev) \|\| !ionic->vfs) {
1725	ret = -EINVAL;	1725	ret = -EINVAL;
@@ -1730,7 +1730,7 @@ static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, · 4 unmodified lines
1730	ionic->vfs[vf].vlanid = vlan;	1730	ionic->vfs[vf].vlanid = vlan;
1731	}	1731	}
1732		1732
1733	up_read(&ionic->vf_op_lock);	1733	up_write(&ionic->vf_op_lock);
1734	return ret;	1734	return ret;
1735	}	1735	}
1736		1736

drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c+91−95

@@ -13,25 +13,6 @@ · 12 unmodified lines
13	#include "rmnet_vnd.h"	13	#include "rmnet_vnd.h"
14	#include "rmnet_private.h"	14	#include "rmnet_private.h"
15		15
16	/* Locking scheme -
17	* The shared resource which needs to be protected is realdev->rx_handler_data.
18	* For the writer path, this is using rtnl_lock(). The writer paths are
19	* rmnet_newlink(), rmnet_dellink() and rmnet_force_unassociate_device(). These
20	* paths are already called with rtnl_lock() acquired in. There is also an
21	* ASSERT_RTNL() to ensure that we are calling with rtnl acquired. For
22	* dereference here, we will need to use rtnl_dereference(). Dev list writing
23	* needs to happen with rtnl_lock() acquired for netdev_master_upper_dev_link().
24	* For the reader path, the real_dev->rx_handler_data is called in the TX / RX
25	* path. We only need rcu_read_lock() for these scenarios. In these cases,
26	* the rcu_read_lock() is held in __dev_queue_xmit() and
27	* netif_receive_skb_internal(), so readers need to use rcu_dereference_rtnl()
28	* to get the relevant information. For dev list reading, we again acquire
29	* rcu_read_lock() in rmnet_dellink() for netdev_master_upper_dev_get_rcu().
30	* We also use unregister_netdevice_many() to free all rmnet devices in
31	* rmnet_force_unassociate_device() so we dont lose the rtnl_lock() and free in
32	* same context.
33	*/
34
35	/* Local Definitions and Declarations */	16	/* Local Definitions and Declarations */
36		17
37	static const struct nla_policy rmnet_policy[IFLA_RMNET_MAX + 1] = {	18	static const struct nla_policy rmnet_policy[IFLA_RMNET_MAX + 1] = {
@@ -51,9 +32,10 @@ rmnet_get_port_rtnl(const struct net_device *real_dev) · 13 unmodified lines
51	return rtnl_dereference(real_dev->rx_handler_data);	32	return rtnl_dereference(real_dev->rx_handler_data);
52	}	33	}
53		34
54	static int rmnet_unregister_real_device(struct net_device *real_dev,	35	static int rmnet_unregister_real_device(struct net_device *real_dev)
55	struct rmnet_port *port)
56	{	36	{
		37	struct rmnet_port *port = rmnet_get_port_rtnl(real_dev);
		38
57	if (port->nr_rmnet_devs)	39	if (port->nr_rmnet_devs)
58	return -EINVAL;	40	return -EINVAL;
59		41
@@ -61,9 +43,6 @@ static int rmnet_unregister_real_device(struct net_device *real_dev, · 1 unmodified line
61		43
62	kfree(port);	44	kfree(port);
63		45
64	/* release reference on real_dev */
65	dev_put(real_dev);
66
67	netdev_dbg(real_dev, "Removed from rmnet\n");	46	netdev_dbg(real_dev, "Removed from rmnet\n");
68	return 0;	47	return 0;
69	}	48	}
@@ -89,9 +68,6 @@ static int rmnet_register_real_device(struct net_device *real_dev) · 19 unmodified lines
89	return -EBUSY;	68	return -EBUSY;
90	}	69	}
91		70
92	/* hold on to real dev for MAP data */
93	dev_hold(real_dev);
94
95	for (entry = 0; entry < RMNET_MAX_LOGICAL_EP; entry++)	71	for (entry = 0; entry < RMNET_MAX_LOGICAL_EP; entry++)
96	INIT_HLIST_HEAD(&port->muxed_ep[entry]);	72	INIT_HLIST_HEAD(&port->muxed_ep[entry]);
97		73
@@ -99,28 +75,33 @@ static int rmnet_register_real_device(struct net_device *real_dev) · 1 unmodified line
99	return 0;	75	return 0;
100	}	76	}
101		77
102	static void rmnet_unregister_bridge(struct net_device *dev,	78	static void rmnet_unregister_bridge(struct rmnet_port *port)
103	struct rmnet_port *port)
104	{	79	{
105	struct rmnet_port *bridge_port;	80	struct net_device bridge_dev, real_dev, *rmnet_dev;
106	struct net_device *bridge_dev;	81	struct rmnet_port *real_port;
107		82
108	if (port->rmnet_mode != RMNET_EPMODE_BRIDGE)	83	if (port->rmnet_mode != RMNET_EPMODE_BRIDGE)
109	return;	84	return;
110		85
111	/* bridge slave handling */	86	rmnet_dev = port->rmnet_dev;
112	if (!port->nr_rmnet_devs) {	87	if (!port->nr_rmnet_devs) {
113	bridge_dev = port->bridge_ep;	88	/* bridge device */
		89	real_dev = port->bridge_ep;
		90	bridge_dev = port->dev;
114		91
115	bridge_port = rmnet_get_port_rtnl(bridge_dev);	92	real_port = rmnet_get_port_rtnl(real_dev);
116	bridge_port->bridge_ep = NULL;	93	real_port->bridge_ep = NULL;
117	bridge_port->rmnet_mode = RMNET_EPMODE_VND;	94	real_port->rmnet_mode = RMNET_EPMODE_VND;
118	} else {	95	} else {
		96	/* real device */
119	bridge_dev = port->bridge_ep;	97	bridge_dev = port->bridge_ep;
120		98
121	bridge_port = rmnet_get_port_rtnl(bridge_dev);	99	port->bridge_ep = NULL;
122	rmnet_unregister_real_device(bridge_dev, bridge_port);	100	port->rmnet_mode = RMNET_EPMODE_VND;
123	}	101	}
		102
		103	netdev_upper_dev_unlink(bridge_dev, rmnet_dev);
		104	rmnet_unregister_real_device(bridge_dev);
124	}	105	}
125		106
126	static int rmnet_newlink(struct net src_net, struct net_device dev,	107	static int rmnet_newlink(struct net src_net, struct net_device dev,
@@ -135,6 +116,11 @@ static int rmnet_newlink(struct net src_net, struct net_device dev, · 8 unmodified lines
135	int err = 0;	116	int err = 0;
136	u16 mux_id;	117	u16 mux_id;
137		118
		119	if (!tb[IFLA_LINK]) {
		120	NL_SET_ERR_MSG_MOD(extack, "link not specified");
		121	return -EINVAL;
		122	}
		123
138	real_dev = __dev_get_by_index(src_net, nla_get_u32(tb[IFLA_LINK]));	124	real_dev = __dev_get_by_index(src_net, nla_get_u32(tb[IFLA_LINK]));
139	if (!real_dev \|\| !dev)	125	if (!real_dev \|\| !dev)
140	return -ENODEV;	126	return -ENODEV;
@@ -157,7 +143,12 @@ static int rmnet_newlink(struct net src_net, struct net_device dev, · 16 unmodified lines
157	if (err)	143	if (err)
158	goto err1;	144	goto err1;
159		145
		146	err = netdev_upper_dev_link(real_dev, dev, extack);
		147	if (err < 0)
		148	goto err2;
		149
160	port->rmnet_mode = mode;	150	port->rmnet_mode = mode;
		151	port->rmnet_dev = dev;
161		152
162	hlist_add_head_rcu(&ep->hlnode, &port->muxed_ep[mux_id]);	153	hlist_add_head_rcu(&ep->hlnode, &port->muxed_ep[mux_id]);
163		154
@@ -173,8 +164,11 @@ static int rmnet_newlink(struct net src_net, struct net_device dev, · 9 unmodified lines
173		164
174	return 0;	165	return 0;
175		166
		167	err2:
		168	unregister_netdevice(dev);
		169	rmnet_vnd_dellink(mux_id, port, ep);
176	err1:	170	err1:
177	rmnet_unregister_real_device(real_dev, port);	171	rmnet_unregister_real_device(real_dev);
178	err0:	172	err0:
179	kfree(ep);	173	kfree(ep);
180	return err;	174	return err;
@@ -183,77 +177,74 @@ err0: · 2 unmodified lines
183	static void rmnet_dellink(struct net_device dev, struct list_head head)	177	static void rmnet_dellink(struct net_device dev, struct list_head head)
184	{	178	{
185	struct rmnet_priv *priv = netdev_priv(dev);	179	struct rmnet_priv *priv = netdev_priv(dev);
186	struct net_device *real_dev;	180	struct net_device real_dev, bridge_dev;
		181	struct rmnet_port real_port, bridge_port;
187	struct rmnet_endpoint *ep;	182	struct rmnet_endpoint *ep;
188	struct rmnet_port *port;	183	u8 mux_id = priv->mux_id;
189	u8 mux_id;
190		184
191	real_dev = priv->real_dev;	185	real_dev = priv->real_dev;
192		186
193	if (!real_dev \|\| !rmnet_is_real_dev_registered(real_dev))	187	if (!rmnet_is_real_dev_registered(real_dev))
194	return;	188	return;
195		189
196	port = rmnet_get_port_rtnl(real_dev);	190	real_port = rmnet_get_port_rtnl(real_dev);
197		191	bridge_dev = real_port->bridge_ep;
198	mux_id = rmnet_vnd_get_mux(dev);	192	if (bridge_dev) {
		193	bridge_port = rmnet_get_port_rtnl(bridge_dev);
		194	rmnet_unregister_bridge(bridge_port);
		195	}
199		196
200	ep = rmnet_get_endpoint(port, mux_id);	197	ep = rmnet_get_endpoint(real_port, mux_id);
201	if (ep) {	198	if (ep) {
202	hlist_del_init_rcu(&ep->hlnode);	199	hlist_del_init_rcu(&ep->hlnode);
203	rmnet_unregister_bridge(dev, port);	200	rmnet_vnd_dellink(mux_id, real_port, ep);
204	rmnet_vnd_dellink(mux_id, port, ep);
205	kfree(ep);	201	kfree(ep);
206	}	202	}
207	rmnet_unregister_real_device(real_dev, port);
208		203
		204	netdev_upper_dev_unlink(real_dev, dev);
		205	rmnet_unregister_real_device(real_dev);
209	unregister_netdevice_queue(dev, head);	206	unregister_netdevice_queue(dev, head);
210	}	207	}
211		208
212	static void rmnet_force_unassociate_device(struct net_device *dev)	209	static void rmnet_force_unassociate_device(struct net_device *real_dev)
213	{	210	{
214	struct net_device *real_dev = dev;
215	struct hlist_node *tmp_ep;	211	struct hlist_node *tmp_ep;
216	struct rmnet_endpoint *ep;	212	struct rmnet_endpoint *ep;
217	struct rmnet_port *port;	213	struct rmnet_port *port;
218	unsigned long bkt_ep;	214	unsigned long bkt_ep;
219	LIST_HEAD(list);	215	LIST_HEAD(list);
220		216
221	if (!rmnet_is_real_dev_registered(real_dev))	217	port = rmnet_get_port_rtnl(real_dev);
222	return;
223
224	ASSERT_RTNL();
225
226	port = rmnet_get_port_rtnl(dev);
227
228	rcu_read_lock();
229	rmnet_unregister_bridge(dev, port);
230
231	hash_for_each_safe(port->muxed_ep, bkt_ep, tmp_ep, ep, hlnode) {
232	unregister_netdevice_queue(ep->egress_dev, &list);
233	rmnet_vnd_dellink(ep->mux_id, port, ep);
234		218
235	hlist_del_init_rcu(&ep->hlnode);	219	if (port->nr_rmnet_devs) {
236	kfree(ep);	220	/* real device */
		221	rmnet_unregister_bridge(port);
		222	hash_for_each_safe(port->muxed_ep, bkt_ep, tmp_ep, ep, hlnode) {
		223	unregister_netdevice_queue(ep->egress_dev, &list);
		224	netdev_upper_dev_unlink(real_dev, ep->egress_dev);
		225	rmnet_vnd_dellink(ep->mux_id, port, ep);
		226	hlist_del_init_rcu(&ep->hlnode);
		227	kfree(ep);
		228	}
		229	rmnet_unregister_real_device(real_dev);
		230	unregister_netdevice_many(&list);
		231	} else {
		232	rmnet_unregister_bridge(port);
237	}	233	}
238
239	rcu_read_unlock();
240	unregister_netdevice_many(&list);
241
242	rmnet_unregister_real_device(real_dev, port);
243	}	234	}
244		235
245	static int rmnet_config_notify_cb(struct notifier_block *nb,	236	static int rmnet_config_notify_cb(struct notifier_block *nb,
246	unsigned long event, void *data)	237	unsigned long event, void *data)
247	{	238	{
248	struct net_device *dev = netdev_notifier_info_to_dev(data);	239	struct net_device *real_dev = netdev_notifier_info_to_dev(data);
249		240
250	if (!dev)	241	if (!rmnet_is_real_dev_registered(real_dev))
251	return NOTIFY_DONE;	242	return NOTIFY_DONE;
252		243
253	switch (event) {	244	switch (event) {
254	case NETDEV_UNREGISTER:	245	case NETDEV_UNREGISTER:
255	netdev_dbg(dev, "Kernel unregister\n");	246	netdev_dbg(real_dev, "Kernel unregister\n");
256	rmnet_force_unassociate_device(dev);	247	rmnet_force_unassociate_device(real_dev);
257	break;	248	break;
258		249
259	default:	250	default:
@@ -295,16 +286,18 @@ static int rmnet_changelink(struct net_device dev, struct nlattr tb[], · 35 unmodified lines
295	if (!dev)	286	if (!dev)
296	return -ENODEV;	287	return -ENODEV;
297		288
298	real_dev = __dev_get_by_index(dev_net(dev),	289	real_dev = priv->real_dev;
299	nla_get_u32(tb[IFLA_LINK]));	290	if (!rmnet_is_real_dev_registered(real_dev))
300
301	if (!real_dev \|\| !rmnet_is_real_dev_registered(real_dev))
302	return -ENODEV;	291	return -ENODEV;
303		292
304	port = rmnet_get_port_rtnl(real_dev);	293	port = rmnet_get_port_rtnl(real_dev);
305		294
306	if (data[IFLA_RMNET_MUX_ID]) {	295	if (data[IFLA_RMNET_MUX_ID]) {
307	mux_id = nla_get_u16(data[IFLA_RMNET_MUX_ID]);	296	mux_id = nla_get_u16(data[IFLA_RMNET_MUX_ID]);
		297	if (rmnet_get_endpoint(port, mux_id)) {
		298	NL_SET_ERR_MSG_MOD(extack, "MUX ID already exists");
		299	return -EINVAL;
		300	}
308	ep = rmnet_get_endpoint(port, priv->mux_id);	301	ep = rmnet_get_endpoint(port, priv->mux_id);
309	if (!ep)	302	if (!ep)
310	return -ENODEV;	303	return -ENODEV;
@@ -379,11 +372,10 @@ struct rtnl_link_ops rmnet_link_ops __read_mostly = { · 68 unmodified lines
379	.fill_info = rmnet_fill_info,	372	.fill_info = rmnet_fill_info,
380	};	373	};
381		374
382	/* Needs either rcu_read_lock() or rtnl lock */	375	struct rmnet_port rmnet_get_port_rcu(struct net_device real_dev)
383	struct rmnet_port rmnet_get_port(struct net_device real_dev)
384	{	376	{
385	if (rmnet_is_real_dev_registered(real_dev))	377	if (rmnet_is_real_dev_registered(real_dev))
386	return rcu_dereference_rtnl(real_dev->rx_handler_data);	378	return rcu_dereference_bh(real_dev->rx_handler_data);
387	else	379	else
388	return NULL;	380	return NULL;
389	}	381	}
@@ -409,7 +401,7 @@ int rmnet_add_bridge(struct net_device *rmnet_dev, · 19 unmodified lines
409	struct rmnet_port port, slave_port;	401	struct rmnet_port port, slave_port;
410	int err;	402	int err;
411		403
412	port = rmnet_get_port(real_dev);	404	port = rmnet_get_port_rtnl(real_dev);
413		405
414	/* If there is more than one rmnet dev attached, its probably being	406	/* If there is more than one rmnet dev attached, its probably being
415	* used for muxing. Skip the briding in that case	407	* used for muxing. Skip the briding in that case
@@ -417,6 +409,9 @@ int rmnet_add_bridge(struct net_device *rmnet_dev, · 1 unmodified line
417	if (port->nr_rmnet_devs > 1)	409	if (port->nr_rmnet_devs > 1)
418	return -EINVAL;	410	return -EINVAL;
419		411
		412	if (port->rmnet_mode != RMNET_EPMODE_VND)
		413	return -EINVAL;
		414
420	if (rmnet_is_real_dev_registered(slave_dev))	415	if (rmnet_is_real_dev_registered(slave_dev))
421	return -EBUSY;	416	return -EBUSY;
422		417
@@ -424,9 +419,17 @@ int rmnet_add_bridge(struct net_device *rmnet_dev, · 1 unmodified line
424	if (err)	419	if (err)
425	return -EBUSY;	420	return -EBUSY;
426		421
427	slave_port = rmnet_get_port(slave_dev);	422	err = netdev_master_upper_dev_link(slave_dev, rmnet_dev, NULL, NULL,
		423	extack);
		424	if (err) {
		425	rmnet_unregister_real_device(slave_dev);
		426	return err;
		427	}
		428
		429	slave_port = rmnet_get_port_rtnl(slave_dev);
428	slave_port->rmnet_mode = RMNET_EPMODE_BRIDGE;	430	slave_port->rmnet_mode = RMNET_EPMODE_BRIDGE;
429	slave_port->bridge_ep = real_dev;	431	slave_port->bridge_ep = real_dev;
		432	slave_port->rmnet_dev = rmnet_dev;
430		433
431	port->rmnet_mode = RMNET_EPMODE_BRIDGE;	434	port->rmnet_mode = RMNET_EPMODE_BRIDGE;
432	port->bridge_ep = slave_dev;	435	port->bridge_ep = slave_dev;
@@ -438,16 +441,9 @@ int rmnet_add_bridge(struct net_device *rmnet_dev, · 5 unmodified lines
438	int rmnet_del_bridge(struct net_device *rmnet_dev,	441	int rmnet_del_bridge(struct net_device *rmnet_dev,
439	struct net_device *slave_dev)	442	struct net_device *slave_dev)
440	{	443	{
441	struct rmnet_priv *priv = netdev_priv(rmnet_dev);	444	struct rmnet_port *port = rmnet_get_port_rtnl(slave_dev);
442	struct net_device *real_dev = priv->real_dev;
443	struct rmnet_port port, slave_port;
444		445
445	port = rmnet_get_port(real_dev);	446	rmnet_unregister_bridge(port);
446	port->rmnet_mode = RMNET_EPMODE_VND;
447	port->bridge_ep = NULL;
448
449	slave_port = rmnet_get_port(slave_dev);
450	rmnet_unregister_real_device(slave_dev, slave_port);
451		447
452	netdev_dbg(slave_dev, "removed from rmnet as slave\n");	448	netdev_dbg(slave_dev, "removed from rmnet as slave\n");
453	return 0;	449	return 0;
@@ -473,8 +469,8 @@ static int __init rmnet_init(void) · 19 unmodified lines
473		469
474	static void __exit rmnet_exit(void)	470	static void __exit rmnet_exit(void)
475	{	471	{
476	unregister_netdevice_notifier(&rmnet_dev_notifier);
477	rtnl_link_unregister(&rmnet_link_ops);	472	rtnl_link_unregister(&rmnet_link_ops);
		473	unregister_netdevice_notifier(&rmnet_dev_notifier);
478	}	474	}
479		475
480	module_init(rmnet_init)	476	module_init(rmnet_init)

drivers/net/ethernet/qualcomm/rmnet/rmnet_config.h+2−1

 	u8 rmnet_mode;
 	struct hlist_head muxed_ep[RMNET_MAX_LOGICAL_EP];
 	struct net_device *bridge_ep;
+	struct net_device *rmnet_dev;
 };
 extern struct rtnl_link_ops rmnet_link_ops;
 	struct rmnet_priv_stats stats;
 };
-struct rmnet_port *rmnet_get_port(struct net_device *real_dev);
+struct rmnet_port *rmnet_get_port_rcu(struct net_device *real_dev);
 struct rmnet_endpoint *rmnet_get_endpoint(struct rmnet_port *port, u8 mux_id);
 int rmnet_add_bridge(struct net_device *rmnet_dev,
 		     struct net_device *slave_dev,

drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c+5−2

 static void
 rmnet_bridge_handler(struct sk_buff *skb, struct net_device *bridge_dev)
 {
+	if (skb_mac_header_was_set(skb))
+		skb_push(skb, skb->mac_len);
 	if (bridge_dev) {
 		skb->dev = bridge_dev;
 		dev_queue_xmit(skb);
 		return RX_HANDLER_PASS;
 	dev = skb->dev;
-	port = rmnet_get_port(dev);
+	port = rmnet_get_port_rcu(dev);
 	switch (port->rmnet_mode) {
 	case RMNET_EPMODE_VND:
 	skb->dev = priv->real_dev;
 	mux_id = priv->mux_id;
-	port = rmnet_get_port(skb->dev);
+	port = rmnet_get_port_rcu(skb->dev);
 	if (!port)
 		goto drop;

drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c+0−8

@@ -266,14 +266,6 @@ int rmnet_vnd_dellink(u8 id, struct rmnet_port *port, · 265 unmodified lines
266	return 0;	266	return 0;
267	}	267	}
268		268
269	u8 rmnet_vnd_get_mux(struct net_device *rmnet_dev)
270	{
271	struct rmnet_priv *priv;
272
273	priv = netdev_priv(rmnet_dev);
274	return priv->mux_id;
275	}
276
277	int rmnet_vnd_do_flow_control(struct net_device *rmnet_dev, int enable)	269	int rmnet_vnd_do_flow_control(struct net_device *rmnet_dev, int enable)
278	{	270	{
279	netdev_dbg(rmnet_dev, "Setting VND TX queue state to %d\n", enable);	271	netdev_dbg(rmnet_dev, "Setting VND TX queue state to %d\n", enable);

drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.h+0−1

@@ -16,6 +16,5 @@ int rmnet_vnd_dellink(u8 id, struct rmnet_port *port, · 15 unmodified lines
16	struct rmnet_endpoint *ep);	16	struct rmnet_endpoint *ep);
17	void rmnet_vnd_rx_fixup(struct sk_buff skb, struct net_device dev);	17	void rmnet_vnd_rx_fixup(struct sk_buff skb, struct net_device dev);
18	void rmnet_vnd_tx_fixup(struct sk_buff skb, struct net_device dev);	18	void rmnet_vnd_tx_fixup(struct sk_buff skb, struct net_device dev);
19	u8 rmnet_vnd_get_mux(struct net_device *rmnet_dev);
20	void rmnet_vnd_setup(struct net_device *dev);	19	void rmnet_vnd_setup(struct net_device *dev);
21	#endif /* _RMNET_VND_H_ */	20	#endif /* _RMNET_VND_H_ */

drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c+1−1

@@ -2277,7 +2277,7 @@ static int __init sxgbe_cmdline_opt(char *str) · 2276 unmodified lines
2277	if (!str \|\| !*str)	2277	if (!str \|\| !*str)
2278	return -EINVAL;	2278	return -EINVAL;
2279	while ((opt = strsep(&str, ",")) != NULL) {	2279	while ((opt = strsep(&str, ",")) != NULL) {
2280	if (!strncmp(opt, "eee_timer:", 6)) {	2280	if (!strncmp(opt, "eee_timer:", 10)) {
2281	if (kstrtoint(opt + 10, 0, &eee_timer))	2281	if (kstrtoint(opt + 10, 0, &eee_timer))
2282	goto err;	2282	goto err;
2283	}	2283	}

drivers/net/ethernet/sfc/ef10.c+17−15

 	}
 	/* Transmit timestamps are only available for 8XXX series. They result
-	 * in three events per packet. These occur in order, and are:
+	 * in up to three events per packet. These occur in order, and are:
-	 *  - the normal completion event
+	 *  - the normal completion event (may be omitted)
 	 *  - the low part of the timestamp
 	 *  - the high part of the timestamp
 	 *
+	 * It's possible for multiple completion events to appear before the
+	 * corresponding timestamps. So we can for example get:
+	 *  COMP N
+	 *  COMP N+1
+	 *  TS_LO N
+	 *  TS_HI N
+	 *  TS_LO N+1
+	 *  TS_HI N+1
+	 *
+	 * In addition it's also possible for the adjacent completions to be
+	 * merged, so we may not see COMP N above. As such, the completion
+	 * events are not very useful here.
+	 *
 	 * Each part of the timestamp is itself split across two 16 bit
 	 * fields in the event.
 	 */
 	switch (tx_ev_type) {
 	case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION:
-		/* In case of Queue flush or FLR, we might have received
+		/* Ignore this event - see above. */
-		 * the previous TX completion event but not the Timestamp
-		 * events.
-		 */
-		if (tx_queue->completed_desc_ptr != tx_queue->ptr_mask)
-			efx_xmit_done(tx_queue, tx_queue->completed_desc_ptr);
-		tx_ev_desc_ptr = EFX_QWORD_FIELD(*event,
-						 ESF_DZ_TX_DESCR_INDX);
-		tx_queue->completed_desc_ptr =
-					tx_ev_desc_ptr & tx_queue->ptr_mask;
 		break;
 	case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO:
 		ts_part = efx_ef10_extract_event_ts(event);
 		tx_queue->completed_timestamp_major = ts_part;
-		efx_xmit_done(tx_queue, tx_queue->completed_desc_ptr);
+		efx_xmit_done_single(tx_queue);
-		tx_queue->completed_desc_ptr = tx_queue->ptr_mask;
 		break;
 	default:

drivers/net/ethernet/sfc/efx.h+1−0

@@ -20,6 +20,7 @@ netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb, · 19 unmodified lines
20	struct net_device *net_dev);	20	struct net_device *net_dev);
21	netdev_tx_t efx_enqueue_skb(struct efx_tx_queue tx_queue, struct sk_buff skb);	21	netdev_tx_t efx_enqueue_skb(struct efx_tx_queue tx_queue, struct sk_buff skb);
22	void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index);	22	void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index);
		23	void efx_xmit_done_single(struct efx_tx_queue *tx_queue);
23	int efx_setup_tc(struct net_device *net_dev, enum tc_setup_type type,	24	int efx_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
24	void *type_data);	25	void *type_data);
25	extern unsigned int efx_piobuf_size;	26	extern unsigned int efx_piobuf_size;

drivers/net/ethernet/sfc/efx_channels.c+1−0

@@ -583,6 +583,7 @@ struct efx_channel efx_copy_channel(const struct efx_channel old_channel) · 582 unmodified lines
583	if (tx_queue->channel)	583	if (tx_queue->channel)
584	tx_queue->channel = channel;	584	tx_queue->channel = channel;
585	tx_queue->buffer = NULL;	585	tx_queue->buffer = NULL;
		586	tx_queue->cb_page = NULL;
586	memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));	587	memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
587	}	588	}
588		589

drivers/net/ethernet/sfc/net_driver.h+0−3

  *	avoid cache-line ping-pong between the xmit path and the
  *	completion path.
  * @merge_events: Number of TX merged completion events
- * @completed_desc_ptr: Most recent completed pointer - only used with
- *      timestamping.
  * @completed_timestamp_major: Top part of the most recent tx timestamp.
  * @completed_timestamp_minor: Low part of the most recent tx timestamp.
  * @insert_count: Current insert pointer
 	unsigned int merge_events;
 	unsigned int bytes_compl;
 	unsigned int pkts_compl;
-	unsigned int completed_desc_ptr;
 	u32 completed_timestamp_major;
 	u32 completed_timestamp_minor;

drivers/net/ethernet/sfc/ptp.c+35−3

@@ -560,13 +560,45 @@ efx_ptp_mac_nic_to_ktime_correction(struct efx_nic *efx, · 559 unmodified lines
560	u32 nic_major, u32 nic_minor,	560	u32 nic_major, u32 nic_minor,
561	s32 correction)	561	s32 correction)
562	{	562	{
		563	u32 sync_timestamp;
563	ktime_t kt = { 0 };	564	ktime_t kt = { 0 };
		565	s16 delta;
564		566
565	if (!(nic_major & 0x80000000)) {	567	if (!(nic_major & 0x80000000)) {
566	WARN_ON_ONCE(nic_major >> 16);	568	WARN_ON_ONCE(nic_major >> 16);
567	/* Use the top bits from the latest sync event. */	569
568	nic_major &= 0xffff;	570	/* Medford provides 48 bits of timestamp, so we must get the top
569	nic_major \|= (last_sync_timestamp_major(efx) & 0xffff0000);	571	* 16 bits from the timesync event state.
		572	*
		573	* We only have the lower 16 bits of the time now, but we do
		574	* have a full resolution timestamp at some point in past. As
		575	* long as the difference between the (real) now and the sync
		576	* is less than 2^15, then we can reconstruct the difference
		577	* between those two numbers using only the lower 16 bits of
		578	* each.
		579	*
		580	* Put another way
		581	*
		582	* a - b = ((a mod k) - b) mod k
		583	*
		584	* when -k/2 < (a-b) < k/2. In our case k is 2^16. We know
		585	* (a mod k) and b, so can calculate the delta, a - b.
		586	*
		587	*/
		588	sync_timestamp = last_sync_timestamp_major(efx);
		589
		590	/* Because delta is s16 this does an implicit mask down to
		591	* 16 bits which is what we need, assuming
		592	* MEDFORD_TX_SECS_EVENT_BITS is 16. delta is signed so that
		593	* we can deal with the (unlikely) case of sync timestamps
		594	* arriving from the future.
		595	*/
		596	delta = nic_major - sync_timestamp;
		597
		598	/* Recover the fully specified time now, by applying the offset
		599	* to the (fully specified) sync time.
		600	*/
		601	nic_major = sync_timestamp + delta;
570		602
571	kt = ptp->nic_to_kernel_time(nic_major, nic_minor,	603	kt = ptp->nic_to_kernel_time(nic_major, nic_minor,
572	correction);	604	correction);

drivers/net/ethernet/sfc/tx.c+38−0

@@ -535,6 +535,44 @@ netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb, · 534 unmodified lines
535	return efx_enqueue_skb(tx_queue, skb);	535	return efx_enqueue_skb(tx_queue, skb);
536	}	536	}
537		537
		538	void efx_xmit_done_single(struct efx_tx_queue *tx_queue)
		539	{
		540	unsigned int pkts_compl = 0, bytes_compl = 0;
		541	unsigned int read_ptr;
		542	bool finished = false;
		543
		544	read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
		545
		546	while (!finished) {
		547	struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
		548
		549	if (!efx_tx_buffer_in_use(buffer)) {
		550	struct efx_nic *efx = tx_queue->efx;
		551
		552	netif_err(efx, hw, efx->net_dev,
		553	"TX queue %d spurious single TX completion\n",
		554	tx_queue->queue);
		555	efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
		556	return;
		557	}
		558
		559	/* Need to check the flag before dequeueing. */
		560	if (buffer->flags & EFX_TX_BUF_SKB)
		561	finished = true;
		562	efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
		563
		564	++tx_queue->read_count;
		565	read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
		566	}
		567
		568	tx_queue->pkts_compl += pkts_compl;
		569	tx_queue->bytes_compl += bytes_compl;
		570
		571	EFX_WARN_ON_PARANOID(pkts_compl != 1);
		572
		573	efx_xmit_done_check_empty(tx_queue);
		574	}
		575
538	void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue)	576	void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue)
539	{	577	{
540	struct efx_nic *efx = tx_queue->efx;	578	struct efx_nic *efx = tx_queue->efx;

drivers/net/ethernet/sfc/tx_common.c+16−13

 	tx_queue->xmit_more_available = false;
 	tx_queue->timestamping = (efx_ptp_use_mac_tx_timestamps(efx) &&
 				  tx_queue->channel == efx_ptp_channel(efx));
-	tx_queue->completed_desc_ptr = tx_queue->ptr_mask;
 	tx_queue->completed_timestamp_major = 0;
 	tx_queue->completed_timestamp_minor = 0;
 	while (read_ptr != stop_index) {
 		struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
-		if (!(buffer->flags & EFX_TX_BUF_OPTION) &&
+		if (!efx_tx_buffer_in_use(buffer)) {
-		    unlikely(buffer->len == 0)) {
 			netif_err(efx, tx_err, efx->net_dev,
-				  "TX queue %d spurious TX completion id %x\n",
+				  "TX queue %d spurious TX completion id %d\n",
 				  tx_queue->queue, read_ptr);
 			efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
 			return;
 	}
 }
+void efx_xmit_done_check_empty(struct efx_tx_queue *tx_queue)
+{
+	if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
+		tx_queue->old_write_count = READ_ONCE(tx_queue->write_count);
+		if (tx_queue->read_count == tx_queue->old_write_count) {
+			/* Ensure that read_count is flushed. */
+			smp_mb();
+			tx_queue->empty_read_count =
+				tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
+		}
+	}
+}
 void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
 {
 	unsigned int fill_level, pkts_compl = 0, bytes_compl = 0;
 			netif_tx_wake_queue(tx_queue->core_txq);
 	}
-	/* Check whether the hardware queue is now empty */
+	efx_xmit_done_check_empty(tx_queue);
-	if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
-		tx_queue->old_write_count = READ_ONCE(tx_queue->write_count);
-		if (tx_queue->read_count == tx_queue->old_write_count) {
-			smp_mb();
-			tx_queue->empty_read_count =
-				tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
-		}
-	}
 }
 /* Remove buffers put into a tx_queue for the current packet.

drivers/net/ethernet/sfc/tx_common.h+6−0

 			unsigned int *pkts_compl,
 			unsigned int *bytes_compl);
+static inline bool efx_tx_buffer_in_use(struct efx_tx_buffer *buffer)
+{
+	return buffer->len || (buffer->flags & EFX_TX_BUF_OPTION);
+}
+void efx_xmit_done_check_empty(struct efx_tx_queue *tx_queue);
 void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index);
 void efx_enqueue_unwind(struct efx_tx_queue *tx_queue,

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c+2−1

 static void dwmac1000_core_init(struct mac_device_info *hw,
 				struct net_device *dev)
 {
+	struct stmmac_priv *priv = netdev_priv(dev);
 	void __iomem *ioaddr = hw->pcsr;
 	u32 value = readl(ioaddr + GMAC_CONTROL);
 	int mtu = dev->mtu;
 	 * Broadcom tags can look like invalid LLC/SNAP packets and cause the
 	 * hardware to truncate packets on reception.
 	 */
-	if (netdev_uses_dsa(dev))
+	if (netdev_uses_dsa(dev) || !priv->plat->enh_desc)
 		value &= ~GMAC_CONTROL_ACS;
 	if (mtu > 1500)

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c+8−5

 {
 	struct stmmac_priv *priv = netdev_priv(dev);
+	rtnl_lock();
 	/* Create per netdev entries */
 	priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
 	debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
 			    &stmmac_dma_cap_fops);
-	register_netdevice_notifier(&stmmac_notifier);
+	rtnl_unlock();
 }
 static void stmmac_exit_fs(struct net_device *dev)
 {
 	struct stmmac_priv *priv = netdev_priv(dev);
-	unregister_netdevice_notifier(&stmmac_notifier);
 	debugfs_remove_recursive(priv->dbgfs_dir);
 }
 #endif /* CONFIG_DEBUG_FS */
 	netdev_info(priv->dev, "%s: removing driver", __func__);
-#ifdef CONFIG_DEBUG_FS
-	stmmac_exit_fs(ndev);
-#endif
 	stmmac_stop_all_dma(priv);
 	stmmac_mac_set(priv, priv->ioaddr, false);
 	netif_carrier_off(ndev);
 	unregister_netdev(ndev);
+#ifdef CONFIG_DEBUG_FS
+	stmmac_exit_fs(ndev);
+#endif
 	phylink_destroy(priv->phylink);
 	if (priv->plat->stmmac_rst)
 		reset_control_assert(priv->plat->stmmac_rst);
 	/* Create debugfs main directory if it doesn't exist yet */
 	if (!stmmac_fs_dir)
 		stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
+	register_netdevice_notifier(&stmmac_notifier);
 #endif
 	return 0;
 static void __exit stmmac_exit(void)
 {
 #ifdef CONFIG_DEBUG_FS
+	unregister_netdevice_notifier(&stmmac_notifier);
 	debugfs_remove_recursive(stmmac_fs_dir);
 #endif
 }

drivers/net/ethernet/xilinx/ll_temac.h+4−0

 	int tx_bd_next;
 	int tx_bd_tail;
 	int rx_bd_ci;
+	int rx_bd_tail;
 	/* DMA channel control setup */
 	u32 tx_chnl_ctrl;
 	u32 rx_chnl_ctrl;
+	u8 coalesce_count_rx;
+	struct delayed_work restart_work;
 };
 /* Wrappers for temac_ior()/temac_iow() function pointers above */

drivers/net/ethernet/xilinx/ll_temac_main.c+171−38

@@ -51,6 +51,7 @@ · 50 unmodified lines
51	#include <linux/ip.h>	51	#include <linux/ip.h>
52	#include <linux/slab.h>	52	#include <linux/slab.h>
53	#include <linux/interrupt.h>	53	#include <linux/interrupt.h>
		54	#include <linux/workqueue.h>
54	#include <linux/dma-mapping.h>	55	#include <linux/dma-mapping.h>
55	#include <linux/processor.h>	56	#include <linux/processor.h>
56	#include <linux/platform_data/xilinx-ll-temac.h>	57	#include <linux/platform_data/xilinx-ll-temac.h>
@@ -367,6 +368,8 @@ static int temac_dma_bd_init(struct net_device *ndev) · 310 unmodified lines
367	skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,	368	skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
368	XTE_MAX_JUMBO_FRAME_SIZE,	369	XTE_MAX_JUMBO_FRAME_SIZE,
369	DMA_FROM_DEVICE);	370	DMA_FROM_DEVICE);
		371	if (dma_mapping_error(ndev->dev.parent, skb_dma_addr))
		372	goto out;
370	lp->rx_bd_v[i].phys = cpu_to_be32(skb_dma_addr);	373	lp->rx_bd_v[i].phys = cpu_to_be32(skb_dma_addr);
371	lp->rx_bd_v[i].len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);	374	lp->rx_bd_v[i].len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
372	lp->rx_bd_v[i].app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);	375	lp->rx_bd_v[i].app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
@@ -387,12 +390,13 @@ static int temac_dma_bd_init(struct net_device *ndev) · 14 unmodified lines
387	lp->tx_bd_next = 0;	390	lp->tx_bd_next = 0;
388	lp->tx_bd_tail = 0;	391	lp->tx_bd_tail = 0;
389	lp->rx_bd_ci = 0;	392	lp->rx_bd_ci = 0;
		393	lp->rx_bd_tail = RX_BD_NUM - 1;
390		394
391	/* Enable RX DMA transfers */	395	/* Enable RX DMA transfers */
392	wmb();	396	wmb();
393	lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);	397	lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
394	lp->dma_out(lp, RX_TAILDESC_PTR,	398	lp->dma_out(lp, RX_TAILDESC_PTR,
395	lp->rx_bd_p + (sizeof(lp->rx_bd_v) (RX_BD_NUM - 1)));	399	lp->rx_bd_p + (sizeof(lp->rx_bd_v) lp->rx_bd_tail));
396		400
397	/* Prepare for TX DMA transfer */	401	/* Prepare for TX DMA transfer */
398	lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);	402	lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
@@ -788,6 +792,9 @@ static void temac_start_xmit_done(struct net_device *ndev) · 389 unmodified lines
788	stat = be32_to_cpu(cur_p->app0);	792	stat = be32_to_cpu(cur_p->app0);
789	}	793	}
790		794
		795	/* Matches barrier in temac_start_xmit */
		796	smp_mb();
		797
791	netif_wake_queue(ndev);	798	netif_wake_queue(ndev);
792	}	799	}
793		800
@@ -830,9 +837,19 @@ temac_start_xmit(struct sk_buff skb, struct net_device ndev) · 36 unmodified lines
830	cur_p = &lp->tx_bd_v[lp->tx_bd_tail];	837	cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
831		838
832	if (temac_check_tx_bd_space(lp, num_frag + 1)) {	839	if (temac_check_tx_bd_space(lp, num_frag + 1)) {
833	if (!netif_queue_stopped(ndev))	840	if (netif_queue_stopped(ndev))
834	netif_stop_queue(ndev);	841	return NETDEV_TX_BUSY;
835	return NETDEV_TX_BUSY;	842
		843	netif_stop_queue(ndev);
		844
		845	/* Matches barrier in temac_start_xmit_done */
		846	smp_mb();
		847
		848	/* Space might have just been freed - check again */
		849	if (temac_check_tx_bd_space(lp, num_frag))
		850	return NETDEV_TX_BUSY;
		851
		852	netif_wake_queue(ndev);
836	}	853	}
837		854
838	cur_p->app0 = 0;	855	cur_p->app0 = 0;
@@ -850,12 +867,16 @@ temac_start_xmit(struct sk_buff skb, struct net_device ndev) · 11 unmodified lines
850	skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,	867	skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
851	skb_headlen(skb), DMA_TO_DEVICE);	868	skb_headlen(skb), DMA_TO_DEVICE);
852	cur_p->len = cpu_to_be32(skb_headlen(skb));	869	cur_p->len = cpu_to_be32(skb_headlen(skb));
		870	if (WARN_ON_ONCE(dma_mapping_error(ndev->dev.parent, skb_dma_addr))) {
		871	dev_kfree_skb_any(skb);
		872	ndev->stats.tx_dropped++;
		873	return NETDEV_TX_OK;
		874	}
853	cur_p->phys = cpu_to_be32(skb_dma_addr);	875	cur_p->phys = cpu_to_be32(skb_dma_addr);
854	ptr_to_txbd((void *)skb, cur_p);	876	ptr_to_txbd((void *)skb, cur_p);
855		877
856	for (ii = 0; ii < num_frag; ii++) {	878	for (ii = 0; ii < num_frag; ii++) {
857	lp->tx_bd_tail++;	879	if (++lp->tx_bd_tail >= TX_BD_NUM)
858	if (lp->tx_bd_tail >= TX_BD_NUM)
859	lp->tx_bd_tail = 0;	880	lp->tx_bd_tail = 0;
860		881
861	cur_p = &lp->tx_bd_v[lp->tx_bd_tail];	882	cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
@@ -863,6 +884,27 @@ temac_start_xmit(struct sk_buff skb, struct net_device ndev) · 1 unmodified line
863	skb_frag_address(frag),	884	skb_frag_address(frag),
864	skb_frag_size(frag),	885	skb_frag_size(frag),
865	DMA_TO_DEVICE);	886	DMA_TO_DEVICE);
		887	if (dma_mapping_error(ndev->dev.parent, skb_dma_addr)) {
		888	if (--lp->tx_bd_tail < 0)
		889	lp->tx_bd_tail = TX_BD_NUM - 1;
		890	cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
		891	while (--ii >= 0) {
		892	--frag;
		893	dma_unmap_single(ndev->dev.parent,
		894	be32_to_cpu(cur_p->phys),
		895	skb_frag_size(frag),
		896	DMA_TO_DEVICE);
		897	if (--lp->tx_bd_tail < 0)
		898	lp->tx_bd_tail = TX_BD_NUM - 1;
		899	cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
		900	}
		901	dma_unmap_single(ndev->dev.parent,
		902	be32_to_cpu(cur_p->phys),
		903	skb_headlen(skb), DMA_TO_DEVICE);
		904	dev_kfree_skb_any(skb);
		905	ndev->stats.tx_dropped++;
		906	return NETDEV_TX_OK;
		907	}
866	cur_p->phys = cpu_to_be32(skb_dma_addr);	908	cur_p->phys = cpu_to_be32(skb_dma_addr);
867	cur_p->len = cpu_to_be32(skb_frag_size(frag));	909	cur_p->len = cpu_to_be32(skb_frag_size(frag));
868	cur_p->app0 = 0;	910	cur_p->app0 = 0;
@@ -884,31 +926,56 @@ temac_start_xmit(struct sk_buff skb, struct net_device ndev) · 15 unmodified lines
884	return NETDEV_TX_OK;	926	return NETDEV_TX_OK;
885	}	927	}
886		928
		929	static int ll_temac_recv_buffers_available(struct temac_local *lp)
		930	{
		931	int available;
		932
		933	if (!lp->rx_skb[lp->rx_bd_ci])
		934	return 0;
		935	available = 1 + lp->rx_bd_tail - lp->rx_bd_ci;
		936	if (available <= 0)
		937	available += RX_BD_NUM;
		938	return available;
		939	}
887		940
888	static void ll_temac_recv(struct net_device *ndev)	941	static void ll_temac_recv(struct net_device *ndev)
889	{	942	{
890	struct temac_local *lp = netdev_priv(ndev);	943	struct temac_local *lp = netdev_priv(ndev);
891	struct sk_buff skb, new_skb;
892	unsigned int bdstat;
893	struct cdmac_bd *cur_p;
894	dma_addr_t tail_p, skb_dma_addr;
895	int length;
896	unsigned long flags;	944	unsigned long flags;
		945	int rx_bd;
		946	bool update_tail = false;
897		947
898	spin_lock_irqsave(&lp->rx_lock, flags);	948	spin_lock_irqsave(&lp->rx_lock, flags);
899		949
900	tail_p = lp->rx_bd_p + sizeof(lp->rx_bd_v) lp->rx_bd_ci;	950	/* Process all received buffers, passing them on network
901	cur_p = &lp->rx_bd_v[lp->rx_bd_ci];	951	* stack. After this, the buffer descriptors will be in an
902		952	* un-allocated stage, where no skb is allocated for it, and
903	bdstat = be32_to_cpu(cur_p->app0);	953	* they are therefore not available for TEMAC/DMA.
904	while ((bdstat & STS_CTRL_APP0_CMPLT)) {	954	*/
		955	do {
		956	struct cdmac_bd *bd = &lp->rx_bd_v[lp->rx_bd_ci];
		957	struct sk_buff *skb = lp->rx_skb[lp->rx_bd_ci];
		958	unsigned int bdstat = be32_to_cpu(bd->app0);
		959	int length;
		960
		961	/* While this should not normally happen, we can end
		962	* here when GFP_ATOMIC allocations fail, and we
		963	* therefore have un-allocated buffers.
		964	*/
		965	if (!skb)
		966	break;
905		967
906	skb = lp->rx_skb[lp->rx_bd_ci];	968	/* Loop over all completed buffer descriptors */
907	length = be32_to_cpu(cur_p->app4) & 0x3FFF;	969	if (!(bdstat & STS_CTRL_APP0_CMPLT))
		970	break;
908		971
909	dma_unmap_single(ndev->dev.parent, be32_to_cpu(cur_p->phys),	972	dma_unmap_single(ndev->dev.parent, be32_to_cpu(bd->phys),
910	XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);	973	XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
		974	/* The buffer is not valid for DMA anymore */
		975	bd->phys = 0;
		976	bd->len = 0;
911		977
		978	length = be32_to_cpu(bd->app4) & 0x3FFF;
912	skb_put(skb, length);	979	skb_put(skb, length);
913	skb->protocol = eth_type_trans(skb, ndev);	980	skb->protocol = eth_type_trans(skb, ndev);
914	skb_checksum_none_assert(skb);	981	skb_checksum_none_assert(skb);
@@ -923,43 +990,102 @@ static void ll_temac_recv(struct net_device *ndev) · 8 unmodified lines
923	* (back) for proper IP checksum byte order	990	* (back) for proper IP checksum byte order
924	* (be16).	991	* (be16).
925	*/	992	*/
926	skb->csum = htons(be32_to_cpu(cur_p->app3) & 0xFFFF);	993	skb->csum = htons(be32_to_cpu(bd->app3) & 0xFFFF);
927	skb->ip_summed = CHECKSUM_COMPLETE;	994	skb->ip_summed = CHECKSUM_COMPLETE;
928	}	995	}
929		996
930	if (!skb_defer_rx_timestamp(skb))	997	if (!skb_defer_rx_timestamp(skb))
931	netif_rx(skb);	998	netif_rx(skb);
		999	/* The skb buffer is now owned by network stack above */
		1000	lp->rx_skb[lp->rx_bd_ci] = NULL;
932		1001
933	ndev->stats.rx_packets++;	1002	ndev->stats.rx_packets++;
934	ndev->stats.rx_bytes += length;	1003	ndev->stats.rx_bytes += length;
935		1004
936	new_skb = netdev_alloc_skb_ip_align(ndev,	1005	rx_bd = lp->rx_bd_ci;
937	XTE_MAX_JUMBO_FRAME_SIZE);	1006	if (++lp->rx_bd_ci >= RX_BD_NUM)
938	if (!new_skb) {	1007	lp->rx_bd_ci = 0;
939	spin_unlock_irqrestore(&lp->rx_lock, flags);	1008	} while (rx_bd != lp->rx_bd_tail);
940	return;	1009
		1010	/* DMA operations will halt when the last buffer descriptor is
		1011	* processed (ie. the one pointed to by RX_TAILDESC_PTR).
		1012	* When that happens, no more interrupt events will be
		1013	* generated. No IRQ_COAL or IRQ_DLY, and not even an
		1014	* IRQ_ERR. To avoid stalling, we schedule a delayed work
		1015	* when there is a potential risk of that happening. The work
		1016	* will call this function, and thus re-schedule itself until
		1017	* enough buffers are available again.
		1018	*/
		1019	if (ll_temac_recv_buffers_available(lp) < lp->coalesce_count_rx)
		1020	schedule_delayed_work(&lp->restart_work, HZ / 1000);
		1021
		1022	/* Allocate new buffers for those buffer descriptors that were
		1023	* passed to network stack. Note that GFP_ATOMIC allocations
		1024	* can fail (e.g. when a larger burst of GFP_ATOMIC
		1025	* allocations occurs), so while we try to allocate all
		1026	* buffers in the same interrupt where they were processed, we
		1027	* continue with what we could get in case of allocation
		1028	* failure. Allocation of remaining buffers will be retried
		1029	* in following calls.
		1030	*/
		1031	while (1) {
		1032	struct sk_buff *skb;
		1033	struct cdmac_bd *bd;
		1034	dma_addr_t skb_dma_addr;
		1035
		1036	rx_bd = lp->rx_bd_tail + 1;
		1037	if (rx_bd >= RX_BD_NUM)
		1038	rx_bd = 0;
		1039	bd = &lp->rx_bd_v[rx_bd];
		1040
		1041	if (bd->phys)
		1042	break; /* All skb's allocated */
		1043
		1044	skb = netdev_alloc_skb_ip_align(ndev, XTE_MAX_JUMBO_FRAME_SIZE);
		1045	if (!skb) {
		1046	dev_warn(&ndev->dev, "skb alloc failed\n");
		1047	break;
941	}	1048	}
942		1049
943	cur_p->app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);	1050	skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
944	skb_dma_addr = dma_map_single(ndev->dev.parent, new_skb->data,
945	XTE_MAX_JUMBO_FRAME_SIZE,	1051	XTE_MAX_JUMBO_FRAME_SIZE,
946	DMA_FROM_DEVICE);	1052	DMA_FROM_DEVICE);
947	cur_p->phys = cpu_to_be32(skb_dma_addr);	1053	if (WARN_ON_ONCE(dma_mapping_error(ndev->dev.parent,
948	cur_p->len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);	1054	skb_dma_addr))) {
949	lp->rx_skb[lp->rx_bd_ci] = new_skb;	1055	dev_kfree_skb_any(skb);
		1056	break;
		1057	}
950		1058
951	lp->rx_bd_ci++;	1059	bd->phys = cpu_to_be32(skb_dma_addr);
952	if (lp->rx_bd_ci >= RX_BD_NUM)	1060	bd->len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
953	lp->rx_bd_ci = 0;	1061	bd->app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
		1062	lp->rx_skb[rx_bd] = skb;
954		1063
955	cur_p = &lp->rx_bd_v[lp->rx_bd_ci];	1064	lp->rx_bd_tail = rx_bd;
956	bdstat = be32_to_cpu(cur_p->app0);	1065	update_tail = true;
		1066	}
		1067
		1068	/* Move tail pointer when buffers have been allocated */
		1069	if (update_tail) {
		1070	lp->dma_out(lp, RX_TAILDESC_PTR,
		1071	lp->rx_bd_p + sizeof(lp->rx_bd_v) lp->rx_bd_tail);
957	}	1072	}
958	lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
959		1073
960	spin_unlock_irqrestore(&lp->rx_lock, flags);	1074	spin_unlock_irqrestore(&lp->rx_lock, flags);
961	}	1075	}
962		1076
		1077	/* Function scheduled to ensure a restart in case of DMA halt
		1078	* condition caused by running out of buffer descriptors.
		1079	*/
		1080	static void ll_temac_restart_work_func(struct work_struct *work)
		1081	{
		1082	struct temac_local *lp = container_of(work, struct temac_local,
		1083	restart_work.work);
		1084	struct net_device *ndev = lp->ndev;
		1085
		1086	ll_temac_recv(ndev);
		1087	}
		1088
963	static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)	1089	static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
964	{	1090	{
965	struct net_device *ndev = _ndev;	1091	struct net_device *ndev = _ndev;
@@ -1052,6 +1178,8 @@ static int temac_stop(struct net_device *ndev) · 86 unmodified lines
1052		1178
1053	dev_dbg(&ndev->dev, "temac_close()\n");	1179	dev_dbg(&ndev->dev, "temac_close()\n");
1054		1180
		1181	cancel_delayed_work_sync(&lp->restart_work);
		1182
1055	free_irq(lp->tx_irq, ndev);	1183	free_irq(lp->tx_irq, ndev);
1056	free_irq(lp->rx_irq, ndev);	1184	free_irq(lp->rx_irq, ndev);
1057		1185
@@ -1173,6 +1301,7 @@ static int temac_probe(struct platform_device *pdev) · 115 unmodified lines
1173	lp->dev = &pdev->dev;	1301	lp->dev = &pdev->dev;
1174	lp->options = XTE_OPTION_DEFAULTS;	1302	lp->options = XTE_OPTION_DEFAULTS;
1175	spin_lock_init(&lp->rx_lock);	1303	spin_lock_init(&lp->rx_lock);
		1304	INIT_DELAYED_WORK(&lp->restart_work, ll_temac_restart_work_func);
1176		1305
1177	/* Setup mutex for synchronization of indirect register access */	1306	/* Setup mutex for synchronization of indirect register access */
1178	if (pdata) {	1307	if (pdata) {
@@ -1279,6 +1408,7 @@ static int temac_probe(struct platform_device *pdev) · 100 unmodified lines
1279	*/	1408	*/
1280	lp->tx_chnl_ctrl = 0x10220000;	1409	lp->tx_chnl_ctrl = 0x10220000;
1281	lp->rx_chnl_ctrl = 0xff070000;	1410	lp->rx_chnl_ctrl = 0xff070000;
		1411	lp->coalesce_count_rx = 0x07;
1282		1412
1283	/* Finished with the DMA node; drop the reference */	1413	/* Finished with the DMA node; drop the reference */
1284	of_node_put(dma_np);	1414	of_node_put(dma_np);
@@ -1310,11 +1440,14 @@ static int temac_probe(struct platform_device *pdev) · 25 unmodified lines
1310	(pdata->tx_irq_count << 16);	1440	(pdata->tx_irq_count << 16);
1311	else	1441	else
1312	lp->tx_chnl_ctrl = 0x10220000;	1442	lp->tx_chnl_ctrl = 0x10220000;
1313	if (pdata->rx_irq_timeout \|\| pdata->rx_irq_count)	1443	if (pdata->rx_irq_timeout \|\| pdata->rx_irq_count) {
1314	lp->rx_chnl_ctrl = (pdata->rx_irq_timeout << 24) \|	1444	lp->rx_chnl_ctrl = (pdata->rx_irq_timeout << 24) \|
1315	(pdata->rx_irq_count << 16);	1445	(pdata->rx_irq_count << 16);
1316	else	1446	lp->coalesce_count_rx = pdata->rx_irq_count;
		1447	} else {
1317	lp->rx_chnl_ctrl = 0xff070000;	1448	lp->rx_chnl_ctrl = 0xff070000;
		1449	lp->coalesce_count_rx = 0x07;
		1450	}
1318	}	1451	}
1319		1452
1320	/* Error handle returned DMA RX and TX interrupts */	1453	/* Error handle returned DMA RX and TX interrupts */

drivers/net/hyperv/netvsc.c+1−1

@@ -99,7 +99,7 @@ static struct netvsc_device *alloc_net_device(void) · 98 unmodified lines
99		99
100	init_waitqueue_head(&net_device->wait_drain);	100	init_waitqueue_head(&net_device->wait_drain);
101	net_device->destroy = false;	101	net_device->destroy = false;
102	net_device->tx_disable = false;	102	net_device->tx_disable = true;
103		103
104	net_device->max_pkt = RNDIS_MAX_PKT_DEFAULT;	104	net_device->max_pkt = RNDIS_MAX_PKT_DEFAULT;
105	net_device->pkt_align = RNDIS_PKT_ALIGN_DEFAULT;	105	net_device->pkt_align = RNDIS_PKT_ALIGN_DEFAULT;

drivers/net/hyperv/netvsc_drv.c+3−0

 	}
 	/* In any case device is now ready */
+	nvdev->tx_disable = false;
 	netif_device_attach(ndev);
 	/* Note: enable and attach happen when sub-channels setup */
 	else
 		net->max_mtu = ETH_DATA_LEN;
+	nvdev->tx_disable = false;
 	ret = register_netdevice(net);
 	if (ret != 0) {
 		pr_err("Unable to register netdev.\n");

drivers/net/ipvlan/ipvlan_core.c+11−8

 		}
 		if (dev)
 			dev_put(dev);
+		cond_resched();
 	}
 }
 	struct ethhdr *ethh = eth_hdr(skb);
 	int ret = NET_XMIT_DROP;
-	/* In this mode we dont care about multicast and broadcast traffic */
-	if (is_multicast_ether_addr(ethh->h_dest)) {
-		pr_debug_ratelimited("Dropped {multi|broad}cast of type=[%x]\n",
-				     ntohs(skb->protocol));
-		kfree_skb(skb);
-		goto out;
-	}
 	/* The ipvlan is a pseudo-L2 device, so the packets that we receive
 	 * will have L2; which need to discarded and processed further
 	 * in the net-ns of the main-device.
 	 */
 	if (skb_mac_header_was_set(skb)) {
+		/* In this mode we dont care about
+		 * multicast and broadcast traffic */
+		if (is_multicast_ether_addr(ethh->h_dest)) {
+			pr_debug_ratelimited(
+				"Dropped {multi|broad}cast of type=[%x]\n",
+				ntohs(skb->protocol));
+			kfree_skb(skb);
+			goto out;
+		}
 		skb_pull(skb, sizeof(*ethh));
 		skb->mac_header = (typeof(skb->mac_header))~0U;
 		skb_reset_network_header(skb);

drivers/net/ipvlan/ipvlan_main.c+1−4

 static int ipvlan_open(struct net_device *dev)
 {
 	struct ipvl_dev *ipvlan = netdev_priv(dev);
-	struct net_device *phy_dev = ipvlan->phy_dev;
 	struct ipvl_addr *addr;
 	if (ipvlan->port->mode == IPVLAN_MODE_L3 ||
 		ipvlan_ht_addr_add(ipvlan, addr);
 	rcu_read_unlock();
-	return dev_uc_add(phy_dev, phy_dev->dev_addr);
+	return 0;
 }
 static int ipvlan_stop(struct net_device *dev)
 	dev_uc_unsync(phy_dev, dev);
 	dev_mc_unsync(phy_dev, dev);
-	dev_uc_del(phy_dev, phy_dev->dev_addr);
 	rcu_read_lock();
 	list_for_each_entry_rcu(addr, &ipvlan->addrs, anode)
 		ipvlan_ht_addr_del(addr);

drivers/net/macsec.c+20−5

 	return (struct macsec_eth_header *)skb_mac_header(skb);
 }
+static sci_t dev_to_sci(struct net_device *dev, __be16 port)
+{
+	return make_sci(dev->dev_addr, port);
+}
 static void __macsec_pn_wrapped(struct macsec_secy *secy,
 				struct macsec_tx_sa *tx_sa)
 {
 out:
 	ether_addr_copy(dev->dev_addr, addr->sa_data);
+	macsec->secy.sci = dev_to_sci(dev, MACSEC_PORT_ES);
+	/* If h/w offloading is available, propagate to the device */
+	if (macsec_is_offloaded(macsec)) {
+		const struct macsec_ops *ops;
+		struct macsec_context ctx;
+		ops = macsec_get_ops(macsec, &ctx);
+		if (ops) {
+			ctx.secy = &macsec->secy;
+			macsec_offload(ops->mdo_upd_secy, &ctx);
+		}
+	}
 	return 0;
 }
 static const struct nla_policy macsec_rtnl_policy[IFLA_MACSEC_MAX + 1] = {
 	[IFLA_MACSEC_SCI] = { .type = NLA_U64 },
+	[IFLA_MACSEC_PORT] = { .type = NLA_U16 },
 	[IFLA_MACSEC_ICV_LEN] = { .type = NLA_U8 },
 	[IFLA_MACSEC_CIPHER_SUITE] = { .type = NLA_U64 },
 	[IFLA_MACSEC_WINDOW] = { .type = NLA_U32 },
 	return false;
 }
-static sci_t dev_to_sci(struct net_device *dev, __be16 port)
-{
-	return make_sci(dev->dev_addr, port);
-}
 static int macsec_add_dev(struct net_device *dev, sci_t sci, u8 icv_len)
 {
 	struct macsec_dev *macsec = macsec_priv(dev);

drivers/net/macvlan.c+2−0

@@ -334,6 +334,8 @@ static void macvlan_process_broadcast(struct work_struct *w) · 333 unmodified lines
334	if (src)	334	if (src)
335	dev_put(src->dev);	335	dev_put(src->dev);
336	consume_skb(skb);	336	consume_skb(skb);
		337
		338	cond_resched();
337	}	339	}
338	}	340	}
339		341

drivers/net/phy/bcm63xx.c+1−0

@@ -73,6 +73,7 @@ static struct phy_driver bcm63xx_driver[] = { · 72 unmodified lines
73	/* same phy as above, with just a different OUI */	73	/* same phy as above, with just a different OUI */
74	.phy_id = 0x002bdc00,	74	.phy_id = 0x002bdc00,
75	.phy_id_mask = 0xfffffc00,	75	.phy_id_mask = 0xfffffc00,
		76	.name = "Broadcom BCM63XX (2)",
76	/* PHY_BASIC_FEATURES */	77	/* PHY_BASIC_FEATURES */
77	.flags = PHY_IS_INTERNAL,	78	.flags = PHY_IS_INTERNAL,
78	.config_init = bcm63xx_config_init,	79	.config_init = bcm63xx_config_init,

drivers/net/phy/marvell.c+5−0

 		}
 	}
+	if (!(status & MII_M1011_PHY_STATUS_RESOLVED))
+		return 0;
 	if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
 		phydev->duplex = DUPLEX_FULL;
 	else
 	linkmode_zero(phydev->lp_advertising);
 	phydev->pause = 0;
 	phydev->asym_pause = 0;
+	phydev->speed = SPEED_UNKNOWN;
+	phydev->duplex = DUPLEX_UNKNOWN;
 	if (phydev->autoneg == AUTONEG_ENABLE)
 		err = marvell_read_status_page_an(phydev, fiber, status);

drivers/net/phy/mscc.c+2−2

@@ -345,11 +345,11 @@ enum macsec_bank { · 344 unmodified lines
345	BIT(VSC8531_FORCE_LED_OFF) \| \	345	BIT(VSC8531_FORCE_LED_OFF) \| \
346	BIT(VSC8531_FORCE_LED_ON))	346	BIT(VSC8531_FORCE_LED_ON))
347		347
348	#define MSCC_VSC8584_REVB_INT8051_FW "mscc_vsc8584_revb_int8051_fb48.bin"	348	#define MSCC_VSC8584_REVB_INT8051_FW "microchip/mscc_vsc8584_revb_int8051_fb48.bin"
349	#define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800	349	#define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800
350	#define MSCC_VSC8584_REVB_INT8051_FW_CRC 0xfb48	350	#define MSCC_VSC8584_REVB_INT8051_FW_CRC 0xfb48
351		351
352	#define MSCC_VSC8574_REVB_INT8051_FW "mscc_vsc8574_revb_int8051_29e8.bin"	352	#define MSCC_VSC8574_REVB_INT8051_FW "microchip/mscc_vsc8574_revb_int8051_29e8.bin"
353	#define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000	353	#define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000
354	#define MSCC_VSC8574_REVB_INT8051_FW_CRC 0x29e8	354	#define MSCC_VSC8574_REVB_INT8051_FW_CRC 0x29e8
355		355

drivers/net/phy/phy-c45.c+3−3

@@ -167,7 +167,7 @@ EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); · 166 unmodified lines
167	*/	167	*/
168	int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)	168	int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
169	{	169	{
170	int ret = 0;	170	int ret;
171		171
172	if (!restart) {	172	if (!restart) {
173	/* Configure and restart aneg if it wasn't set before */	173	/* Configure and restart aneg if it wasn't set before */
@@ -180,9 +180,9 @@ int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) · 6 unmodified lines
180	}	180	}
181		181
182	if (restart)	182	if (restart)
183	ret = genphy_c45_restart_aneg(phydev);	183	return genphy_c45_restart_aneg(phydev);
184		184
185	return ret;	185	return 0;
186	}	186	}
187	EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);	187	EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
188		188

drivers/net/phy/phy.c+2−1

@@ -727,7 +727,8 @@ static irqreturn_t phy_interrupt(int irq, void *phy_dat) · 726 unmodified lines
727	phy_trigger_machine(phydev);	727	phy_trigger_machine(phydev);
728	}	728	}
729		729
730	if (phy_clear_interrupt(phydev))	730	/* did_interrupt() may have cleared the interrupt already */
		731	if (!phydev->drv->did_interrupt && phy_clear_interrupt(phydev))
731	goto phy_err;	732	goto phy_err;
732	return IRQ_HANDLED;	733	return IRQ_HANDLED;
733		734

drivers/net/phy/phy_device.c+11−6

 	 * MDIO bus driver and clock gated at this point.
 	 */
 	if (!netdev)
-		return !phydev->suspended;
+		goto out;
 	if (netdev->wol_enabled)
 		return false;
 	if (device_may_wakeup(&netdev->dev))
 		return false;
-	return true;
+out:
+	return !phydev->suspended;
 }
 static int mdio_bus_phy_suspend(struct device *dev)
 	if (!mdio_bus_phy_may_suspend(phydev))
 		return 0;
+	phydev->suspended_by_mdio_bus = 1;
 	return phy_suspend(phydev);
 }
 	struct phy_device *phydev = to_phy_device(dev);
 	int ret;
-	if (!mdio_bus_phy_may_suspend(phydev))
+	if (!phydev->suspended_by_mdio_bus)
 		goto no_resume;
+	phydev->suspended_by_mdio_bus = 0;
 	ret = phy_resume(phydev);
 	if (ret < 0)
 		return ret;
  */
 int genphy_check_and_restart_aneg(struct phy_device *phydev, bool restart)
 {
-	int ret = 0;
+	int ret;
 	if (!restart) {
 		/* Advertisement hasn't changed, but maybe aneg was never on to
 	}
 	if (restart)
-		ret = genphy_restart_aneg(phydev);
+		return genphy_restart_aneg(phydev);
-	return ret;
+	return 0;
 }
 EXPORT_SYMBOL(genphy_check_and_restart_aneg);

drivers/net/phy/phylink.c+7−1

 		config.interface = interface;
 	ret = phylink_validate(pl, supported, &config);
-	if (ret)
+	if (ret) {
+		phylink_warn(pl, "validation of %s with support %*pb and advertisement %*pb failed: %d\n",
+			     phy_modes(config.interface),
+			     __ETHTOOL_LINK_MODE_MASK_NBITS, phy->supported,
+			     __ETHTOOL_LINK_MODE_MASK_NBITS, config.advertising,
+			     ret);
 		return ret;
+	}
 	phy->phylink = pl;
 	phy->phy_link_change = phylink_phy_change;

drivers/net/slip/slhc.c+10−4

 	struct cstate *cs = lcs->next;
 	unsigned long deltaS, deltaA;
 	short changes = 0;
-	int hlen;
+	int nlen, hlen;
 	unsigned char new_seq[16];
 	unsigned char *cp = new_seq;
 	struct iphdr *ip;
 		return isize;
 	ip = (struct iphdr *) icp;
+	if (ip->version != 4 || ip->ihl < 5)
+		return isize;
 	/* Bail if this packet isn't TCP, or is an IP fragment */
 	if (ip->protocol != IPPROTO_TCP || (ntohs(ip->frag_off) & 0x3fff)) {
 			comp->sls_o_tcp++;
 		return isize;
 	}
-	/* Extract TCP header */
+	nlen = ip->ihl * 4;
+	if (isize < nlen + sizeof(*th))
+		return isize;
-	th = (struct tcphdr *)(((unsigned char *)ip) + ip->ihl*4);
+	th = (struct tcphdr *)(icp + nlen);
-	hlen = ip->ihl*4 + th->doff*4;
+	if (th->doff < sizeof(struct tcphdr) / 4)
+		return isize;
+	hlen = nlen + th->doff * 4;
 	/*  Bail if the TCP packet isn't `compressible' (i.e., ACK isn't set or
 	 *  some other control bit is set). Also uncompressible if

drivers/net/slip/slip.c+3−0

 	tty->disc_data = NULL;
 	clear_bit(SLF_INUSE, &sl->flags);
 	sl_free_netdev(sl->dev);
+	/* do not call free_netdev before rtnl_unlock */
+	rtnl_unlock();
 	free_netdev(sl->dev);
+	return err;
 err_exit:
 	rtnl_unlock();

drivers/net/team/team.c+2−0

@@ -2240,6 +2240,8 @@ team_nl_option_policy[TEAM_ATTR_OPTION_MAX + 1] = { · 2239 unmodified lines
2240	[TEAM_ATTR_OPTION_CHANGED] = { .type = NLA_FLAG },	2240	[TEAM_ATTR_OPTION_CHANGED] = { .type = NLA_FLAG },
2241	[TEAM_ATTR_OPTION_TYPE] = { .type = NLA_U8 },	2241	[TEAM_ATTR_OPTION_TYPE] = { .type = NLA_U8 },
2242	[TEAM_ATTR_OPTION_DATA] = { .type = NLA_BINARY },	2242	[TEAM_ATTR_OPTION_DATA] = { .type = NLA_BINARY },
		2243	[TEAM_ATTR_OPTION_PORT_IFINDEX] = { .type = NLA_U32 },
		2244	[TEAM_ATTR_OPTION_ARRAY_INDEX] = { .type = NLA_U32 },
2243	};	2245	};
2244		2246
2245	static int team_nl_cmd_noop(struct sk_buff skb, struct genl_info info)	2247	static int team_nl_cmd_noop(struct sk_buff skb, struct genl_info info)

drivers/net/usb/qmi_wwan.c+3−0

 		netdev_dbg(net, "mode: raw IP\n");
 	} else if (!net->header_ops) { /* don't bother if already set */
 		ether_setup(net);
+		/* Restoring min/max mtu values set originally by usbnet */
+		net->min_mtu = 0;
+		net->max_mtu = ETH_MAX_MTU;
 		clear_bit(EVENT_NO_IP_ALIGN, &dev->flags);
 		netdev_dbg(net, "mode: Ethernet\n");
 	}

drivers/net/usb/r8152.c+8−0

 		}
 		msleep(20);
+		if (test_bit(RTL8152_UNPLUG, &tp->flags))
+			break;
 	}
 	return data;
 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
 		    AUTOLOAD_DONE)
 			break;
 		msleep(20);
+		if (test_bit(RTL8152_UNPLUG, &tp->flags))
+			break;
 	}
 	data = r8153_phy_status(tp, 0);
 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
 		    AUTOLOAD_DONE)
 			break;
 		msleep(20);
+		if (test_bit(RTL8152_UNPLUG, &tp->flags))
+			break;
 	}
 	data = r8153_phy_status(tp, 0);

drivers/net/veth.c+1−1

@@ -328,7 +328,7 @@ static void veth_get_stats64(struct net_device *dev, · 327 unmodified lines
328	rcu_read_lock();	328	rcu_read_lock();
329	peer = rcu_dereference(priv->peer);	329	peer = rcu_dereference(priv->peer);
330	if (peer) {	330	if (peer) {
331	tot->rx_dropped += veth_stats_tx(peer, &packets, &bytes);	331	veth_stats_tx(peer, &packets, &bytes);
332	tot->rx_bytes += bytes;	332	tot->rx_bytes += bytes;
333	tot->rx_packets += packets;	333	tot->rx_packets += packets;
334		334

drivers/net/wireless/intel/iwlwifi/mvm/nvm.c+2−1

@@ -308,7 +308,8 @@ iwl_parse_nvm_sections(struct iwl_mvm *mvm) · 307 unmodified lines
308	}	308	}
309		309
310	/* PHY_SKU section is mandatory in B0 */	310	/* PHY_SKU section is mandatory in B0 */
311	if (!mvm->nvm_sections[NVM_SECTION_TYPE_PHY_SKU].data) {	311	if (mvm->trans->cfg->nvm_type == IWL_NVM_EXT &&
		312	!mvm->nvm_sections[NVM_SECTION_TYPE_PHY_SKU].data) {
312	IWL_ERR(mvm,	313	IWL_ERR(mvm,
313	"Can't parse phy_sku in B0, empty sections\n");	314	"Can't parse phy_sku in B0, empty sections\n");
314	return NULL;	315	return NULL;

drivers/net/wireless/mediatek/mt76/dma.c+6−3

 	struct page *page = virt_to_head_page(data);
 	int offset = data - page_address(page);
 	struct sk_buff *skb = q->rx_head;
+	struct skb_shared_info *shinfo = skb_shinfo(skb);
-	offset += q->buf_offset;
+	if (shinfo->nr_frags < ARRAY_SIZE(shinfo->frags)) {
-	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, offset, len,
+		offset += q->buf_offset;
-			q->buf_size);
+		skb_add_rx_frag(skb, shinfo->nr_frags, page, offset, len,
+				q->buf_size);
+	}
 	if (more)
 		return;

drivers/nvme/host/pci.c+1−1

@@ -1078,9 +1078,9 @@ static int nvme_poll(struct blk_mq_hw_ctx *hctx) · 1077 unmodified lines
1078		1078
1079	spin_lock(&nvmeq->cq_poll_lock);	1079	spin_lock(&nvmeq->cq_poll_lock);
1080	found = nvme_process_cq(nvmeq, &start, &end, -1);	1080	found = nvme_process_cq(nvmeq, &start, &end, -1);
		1081	nvme_complete_cqes(nvmeq, start, end);
1081	spin_unlock(&nvmeq->cq_poll_lock);	1082	spin_unlock(&nvmeq->cq_poll_lock);
1082		1083
1083	nvme_complete_cqes(nvmeq, start, end);
1084	return found;	1084	return found;
1085	}	1085	}
1086		1086

drivers/of/of_mdio.c+1−0

@@ -306,6 +306,7 @@ int of_mdiobus_register(struct mii_bus mdio, struct device_node np) · 305 unmodified lines
306	rc = of_mdiobus_register_phy(mdio, child, addr);	306	rc = of_mdiobus_register_phy(mdio, child, addr);
307	if (rc && rc != -ENODEV)	307	if (rc && rc != -ENODEV)
308	goto unregister;	308	goto unregister;
		309	break;
309	}	310	}
310	}	311	}
311	}	312	}

drivers/pci/controller/pcie-brcmstb.c+1−1

@@ -670,7 +670,7 @@ static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, · 669 unmodified lines
670	* outbound memory @ 3GB). So instead it will start at the 1x	670	* outbound memory @ 3GB). So instead it will start at the 1x
671	* multiple of its size	671	* multiple of its size
672	*/	672	*/
673	if (!rc_bar2_size \|\| rc_bar2_offset % *rc_bar2_size \|\|	673	if (!rc_bar2_size \|\| (rc_bar2_offset & (*rc_bar2_size - 1)) \|\|
674	(rc_bar2_offset < SZ_4G && rc_bar2_offset > SZ_2G)) {	674	(rc_bar2_offset < SZ_4G && rc_bar2_offset > SZ_2G)) {
675	dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",	675	dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
676	rc_bar2_size, rc_bar2_offset);	676	rc_bar2_size, rc_bar2_offset);

drivers/perf/arm_pmu_acpi.c+2−5

 	int gsi, trigger;
 	gicc = acpi_cpu_get_madt_gicc(cpu);
-	if (WARN_ON(!gicc))
-		return -EINVAL;
 	gsi = gicc->performance_interrupt;
 	int gsi;
 	gicc = acpi_cpu_get_madt_gicc(cpu);
-	if (!gicc)
-		return;
 	gsi = gicc->performance_interrupt;
-	acpi_unregister_gsi(gsi);
+	if (gsi)
+		acpi_unregister_gsi(gsi);
 }
 #if IS_ENABLED(CONFIG_ARM_SPE_PMU)

drivers/perf/fsl_imx8_ddr_perf.c+6−4

 	if (enable) {
 		/*
-		 * must disable first, then enable again
+		 * cycle counter is special which should firstly write 0 then
-		 * otherwise, cycle counter will not work
+		 * write 1 into CLEAR bit to clear it. Other counters only
-		 * if previous state is enabled.
+		 * need write 0 into CLEAR bit and it turns out to be 1 by
+		 * hardware. Below enable flow is harmless for all counters.
 		 */
 		writel(0, pmu->base + reg);
 		val = CNTL_EN | CNTL_CLEAR;
 		writel(val, pmu->base + reg);
 	} else {
 		/* Disable counter */
-		writel(0, pmu->base + reg);
+		val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK;
+		writel(val, pmu->base + reg);
 	}
 }

drivers/phy/allwinner/phy-sun50i-usb3.c+1−1

@@ -49,7 +49,7 @@ · 48 unmodified lines
49	#define SUNXI_LOS_BIAS(n) ((n) << 3)	49	#define SUNXI_LOS_BIAS(n) ((n) << 3)
50	#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3)	50	#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3)
51	#define SUNXI_TXVBOOSTLVL(n) ((n) << 0)	51	#define SUNXI_TXVBOOSTLVL(n) ((n) << 0)
52	#define SUNXI_TXVBOOSTLVL_MASK GENMASK(0, 2)	52	#define SUNXI_TXVBOOSTLVL_MASK GENMASK(2, 0)
53		53
54	struct sun50i_usb3_phy {	54	struct sun50i_usb3_phy {
55	struct phy *phy;	55	struct phy *phy;

drivers/phy/broadcom/phy-brcm-sata.c+65−83

 	PHY_CTRL_1_RESET			= BIT(0),
 };
-static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port)
-{
-	struct brcm_sata_phy *priv = port->phy_priv;
-	u32 size = 0;
-	switch (priv->version) {
-	case BRCM_SATA_PHY_STB_16NM:
-	case BRCM_SATA_PHY_STB_28NM:
-	case BRCM_SATA_PHY_IPROC_NS2:
-	case BRCM_SATA_PHY_DSL_28NM:
-		size = SATA_PCB_REG_28NM_SPACE_SIZE;
-		break;
-	case BRCM_SATA_PHY_STB_40NM:
-		size = SATA_PCB_REG_40NM_SPACE_SIZE;
-		break;
-	default:
-		dev_err(priv->dev, "invalid phy version\n");
-		break;
-	}
-	return priv->phy_base + (port->portnum * size);
-}
 static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
 {
 	struct brcm_sata_phy *priv = port->phy_priv;
 	return priv->ctrl_base + (port->portnum * size);
 }
-static void brcm_sata_phy_wr(void __iomem *pcb_base, u32 bank,
+static void brcm_sata_phy_wr(struct brcm_sata_port *port, u32 bank,
 			     u32 ofs, u32 msk, u32 value)
 {
+	struct brcm_sata_phy *priv = port->phy_priv;
+	void __iomem *pcb_base = priv->phy_base;
 	u32 tmp;
+	if (priv->version == BRCM_SATA_PHY_STB_40NM)
+		bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
+	else
+		pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
 	writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
 	tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
 	tmp = (tmp & msk) | value;
 	writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
 }
-static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs)
+static u32 brcm_sata_phy_rd(struct brcm_sata_port *port, u32 bank, u32 ofs)
 {
+	struct brcm_sata_phy *priv = port->phy_priv;
+	void __iomem *pcb_base = priv->phy_base;
+	if (priv->version == BRCM_SATA_PHY_STB_40NM)
+		bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
+	else
+		pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
 	writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
 	return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
 }
 static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
 {
-	void __iomem *base = brcm_sata_pcb_base(port);
 	struct brcm_sata_phy *priv = port->phy_priv;
 	u32 tmp;
 	/* override the TX spread spectrum setting */
 	tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
-	brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
+	brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
 	/* set fixed min freq */
-	brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
+	brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
 			 ~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
 			 STB_FMIN_VAL_DEFAULT);
 		tmp = STB_FMAX_VAL_DEFAULT;
 	}
-	brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
+	brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
 			  ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
 }
 static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port)
 {
-	void __iomem *base = brcm_sata_pcb_base(port);
 	u32 tmp = 0, reg = 0;
 	switch (port->rxaeq_mode) {
 		break;
 	}
-	brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
-	brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
 	return 0;
 }
 static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
 {
-	void __iomem *base = brcm_sata_pcb_base(port);
 	u32 tmp, value;
 	/* Reduce CP tail current to 1/16th of its default value */
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
 	/* Turn off CP tail current boost */
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
 	/* Set a specific AEQ equalizer value */
 	tmp = AEQ_FRC_EQ_FORCE_VAL | AEQ_FRC_EQ_FORCE;
-	brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
 			 ~(tmp | AEQ_RFZ_FRC_VAL |
 			   AEQ_FRC_EQ_VAL_MASK << AEQ_FRC_EQ_VAL_SHIFT),
 			 tmp | 32 << AEQ_FRC_EQ_VAL_SHIFT);
 		value = 0x52;
 	else
 		value = 0;
-	brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
 			 ~RXPMD_RX_PPM_VAL_MASK, value);
 	/* Set proportional loop bandwith Gen1/2/3 */
 		value = 1 << RXPMD_G1_CDR_PROP_BW_SHIFT |
 			1 << RXPMD_G2_CDR_PROP_BW_SHIFT |
 			1 << RXPMD_G3_CDR_PROB_BW_SHIFT;
-	brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
 			 value);
 	/* Set CDR integral loop acquisition bandwidth for Gen1/2/3 */
 			1 << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
 	else
 		value = 0;
-	brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
 			 ~tmp, value);
 	/* Set CDR integral loop locking bandwidth to 1 for Gen 1/2/3 */
 			1 << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
 	else
 		value = 0;
-	brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
 			 ~tmp, value);
 	/* Set no guard band and clamp CDR */
 		value = 0x51;
 	else
 		value = 0;
-	brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
 			 ~tmp, RXPMD_MON_CORRECT_EN | value);
 	/* Turn on/off SSC */
-	brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
+	brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
 			 port->ssc_en ? TX_ACTRL5_SSC_EN : 0);
 	return 0;
 {
 	int try;
 	unsigned int val;
-	void __iomem *base = brcm_sata_pcb_base(port);
 	void __iomem *ctrl_base = brcm_sata_ctrl_base(port);
 	struct device *dev = port->phy_priv->dev;
 	val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
 	val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
 	val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
-	brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
+	brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
 	val = 0x0;
 	val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
 	val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
 	val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
-	brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
+	brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
 	/* Configure PHY PLL register bank 1 */
 	val = NS2_PLL1_ACTRL2_MAGIC;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
 	val = NS2_PLL1_ACTRL3_MAGIC;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
 	val = NS2_PLL1_ACTRL4_MAGIC;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
 	/* Configure PHY BLOCK0 register bank */
 	/* Set oob_clk_sel to refclk/2 */
-	brcm_sata_phy_wr(base, BLOCK0_REG_BANK, BLOCK0_SPARE,
+	brcm_sata_phy_wr(port, BLOCK0_REG_BANK, BLOCK0_SPARE,
 			 ~BLOCK0_SPARE_OOB_CLK_SEL_MASK,
 			 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2);
 	/* Wait for PHY PLL lock by polling pll_lock bit */
 	try = 50;
 	while (try) {
-		val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
+		val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
 					BLOCK0_XGXSSTATUS);
 		if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
 			break;
 static int brcm_nsp_sata_init(struct brcm_sata_port *port)
 {
-	struct brcm_sata_phy *priv = port->phy_priv;
 	struct device *dev = port->phy_priv->dev;
-	void __iomem *base = priv->phy_base;
 	unsigned int oob_bank;
 	unsigned int val, try;
 	val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
 	val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
 	val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
-	brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val);
+	brcm_sata_phy_wr(port, oob_bank, OOB_CTRL1, 0x0, val);
 	val = 0x0;
 	val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
 	val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
 	val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
-	brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val);
+	brcm_sata_phy_wr(port, oob_bank, OOB_CTRL2, 0x0, val);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL2,
 		~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT),
 		0x0c << PLL_ACTRL2_SELDIV_SHIFT);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CONTROL,
 						0xff0, 0x4f0);
 	val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 								~val, val);
 	val = PLLCONTROL_0_SEQ_START;
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 								~val, 0);
 	mdelay(10);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 								~val, val);
 	/* Wait for pll_seq_done bit */
 	try = 50;
 	while (--try) {
-		val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
+		val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
 					BLOCK0_XGXSSTATUS);
 		if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
 			break;
 static int brcm_sr_sata_init(struct brcm_sata_port *port)
 {
-	struct brcm_sata_phy *priv = port->phy_priv;
 	struct device *dev = port->phy_priv->dev;
-	void __iomem *base = priv->phy_base;
 	unsigned int val, try;
 	/* Configure PHY PLL register bank 1 */
 	val = SR_PLL1_ACTRL2_MAGIC;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
 	val = SR_PLL1_ACTRL3_MAGIC;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
 	val = SR_PLL1_ACTRL4_MAGIC;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
 	/* Configure PHY PLL register bank 0 */
 	val = SR_PLL0_ACTRL6_MAGIC;
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
 	/* Wait for PHY PLL lock by polling pll_lock bit */
 	try = 50;
 	do {
-		val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
+		val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
 					BLOCK0_XGXSSTATUS);
 		if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
 			break;
 	}
 	/* Invert Tx polarity */
-	brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL0,
+	brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL0,
 			 ~TX_ACTRL0_TXPOL_FLIP, TX_ACTRL0_TXPOL_FLIP);
 	/* Configure OOB control to handle 100MHz reference clock */
 		(0x4 << OOB_CTRL1_BURST_MIN_SHIFT) |
 		(0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) |
 		(0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT));
-	brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
+	brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
 	val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) |
 		(0x2 << OOB_CTRL2_BURST_CNT_SHIFT) |
 		(0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT));
-	brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
+	brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
 	return 0;
 }
 static int brcm_dsl_sata_init(struct brcm_sata_port *port)
 {
-	void __iomem *base = brcm_sata_pcb_base(port);
 	struct device *dev = port->phy_priv->dev;
 	unsigned int try;
 	u32 tmp;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 			 0, 0x3089);
 	usleep_range(1000, 2000);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 			 0, 0x3088);
 	usleep_range(1000, 2000);
-	brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
 			 0, 0x3000);
-	brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
 			 0, 0x3000);
 	usleep_range(1000, 2000);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
 	usleep_range(1000, 2000);
 	/* Acquire PLL lock */
 	try = 50;
 	while (try) {
-		tmp = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
+		tmp = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
 				       BLOCK0_XGXSSTATUS);
 		if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
 			break;
 static void brcm_stb_sata_calibrate(struct brcm_sata_port *port)
 {
-	void __iomem *base = brcm_sata_pcb_base(port);
 	u32 tmp = BIT(8);
-	brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
 			 ~tmp, tmp);
 }

drivers/phy/motorola/phy-mapphone-mdm6600.c+24−3

 #define PHY_MDM6600_PHY_DELAY_MS	4000	/* PHY enable 2.2s to 3.5s */
 #define PHY_MDM6600_ENABLED_DELAY_MS	8000	/* 8s more total for MDM6600 */
+#define PHY_MDM6600_WAKE_KICK_MS	600	/* time on after GPIO toggle */
 #define MDM6600_MODEM_IDLE_DELAY_MS	1000	/* modem after USB suspend */
 #define MDM6600_MODEM_WAKE_DELAY_MS	200	/* modem response after idle */
 {
 	struct phy_mdm6600 *ddata = data;
 	struct gpio_desc *mode_gpio1;
+	int error, wakeup;
 	mode_gpio1 = ddata->mode_gpios->desc[PHY_MDM6600_MODE1];
-	dev_dbg(ddata->dev, "OOB wake on mode_gpio1: %i\n",
+	wakeup = gpiod_get_value(mode_gpio1);
-		gpiod_get_value(mode_gpio1));
+	if (!wakeup)
+		return IRQ_NONE;
+	dev_dbg(ddata->dev, "OOB wake on mode_gpio1: %i\n", wakeup);
+	error = pm_runtime_get_sync(ddata->dev);
+	if (error < 0) {
+		pm_runtime_put_noidle(ddata->dev);
+		return IRQ_NONE;
+	}
+	/* Just wake-up and kick the autosuspend timer */
+	pm_runtime_mark_last_busy(ddata->dev);
+	pm_runtime_put_autosuspend(ddata->dev);
 	return IRQ_HANDLED;
 }
 	ddata = container_of(work, struct phy_mdm6600, modem_wake_work.work);
 	phy_mdm6600_wake_modem(ddata);
+	/*
+	 * The modem does not always stay awake 1.2 seconds after toggling
+	 * the wake GPIO, and sometimes it idles after about some 600 ms
+	 * making writes time out.
+	 */
 	schedule_delayed_work(&ddata->modem_wake_work,
-			      msecs_to_jiffies(MDM6600_MODEM_IDLE_DELAY_MS));
+			      msecs_to_jiffies(PHY_MDM6600_WAKE_KICK_MS));
 }
 static int __maybe_unused phy_mdm6600_runtime_suspend(struct device *dev)

drivers/phy/phy-core.c+6−12

 	get_device(&phy->dev);
 	link = device_link_add(dev, &phy->dev, DL_FLAG_STATELESS);
-	if (!link) {
+	if (!link)
-		dev_err(dev, "failed to create device link to %s\n",
+		dev_dbg(dev, "failed to create device link to %s\n",
 			dev_name(phy->dev.parent));
-		return ERR_PTR(-EINVAL);
-	}
 	return phy;
 }
 	}
 	link = device_link_add(dev, &phy->dev, DL_FLAG_STATELESS);
-	if (!link) {
+	if (!link)
-		dev_err(dev, "failed to create device link to %s\n",
+		dev_dbg(dev, "failed to create device link to %s\n",
 			dev_name(phy->dev.parent));
-		return ERR_PTR(-EINVAL);
-	}
 	return phy;
 }
 	devres_add(dev, ptr);
 	link = device_link_add(dev, &phy->dev, DL_FLAG_STATELESS);
-	if (!link) {
+	if (!link)
-		dev_err(dev, "failed to create device link to %s\n",
+		dev_dbg(dev, "failed to create device link to %s\n",
 			dev_name(phy->dev.parent));
-		return ERR_PTR(-EINVAL);
-	}
 	return phy;
 }

drivers/phy/ti/phy-gmii-sel.c+5−5

 		break;
 	case PHY_INTERFACE_MODE_MII:
-		mode = AM33XX_GMII_SEL_MODE_MII;
+	case PHY_INTERFACE_MODE_GMII:
+		gmii_sel_mode = AM33XX_GMII_SEL_MODE_MII;
 		break;
 	default:
-		dev_warn(dev,
+		dev_warn(dev, "port%u: unsupported mode: \"%s\"\n",
-			 "port%u: unsupported mode: \"%s\". Defaulting to MII.\n",
+			 if_phy->id, phy_modes(submode));
-			 if_phy->id, phy_modes(rgmii_id));
 		return -EINVAL;
 	}
 	if_phy->phy_if_mode = submode;
 	dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n",
-		__func__, if_phy->id, mode, rgmii_id,
+		__func__, if_phy->id, submode, rgmii_id,
 		if_phy->rmii_clock_external);
 	regfield = if_phy->fields[PHY_GMII_SEL_PORT_MODE];

drivers/pinctrl/cirrus/pinctrl-madera-core.c+13−0

 		return ret;
 	}
+	platform_set_drvdata(pdev, priv);
 	dev_dbg(priv->dev, "pinctrl probed ok\n");
 	return 0;
 }
+static int madera_pin_remove(struct platform_device *pdev)
+{
+	struct madera_pin_private *priv = platform_get_drvdata(pdev);
+	if (priv->madera->pdata.gpio_configs)
+		pinctrl_unregister_mappings(priv->madera->pdata.gpio_configs);
+	return 0;
+}
 static struct platform_driver madera_pin_driver = {
 	.probe = madera_pin_probe,
+	.remove = madera_pin_remove,
 	.driver = {
 		.name = "madera-pinctrl",
 	},

drivers/pinctrl/core.c+0−1

@@ -2021,7 +2021,6 @@ static int pinctrl_claim_hogs(struct pinctrl_dev *pctldev) · 2020 unmodified lines
2021	return PTR_ERR(pctldev->p);	2021	return PTR_ERR(pctldev->p);
2022	}	2022	}
2023		2023
2024	kref_get(&pctldev->p->users);
2025	pctldev->hog_default =	2024	pctldev->hog_default =
2026	pinctrl_lookup_state(pctldev->p, PINCTRL_STATE_DEFAULT);	2025	pinctrl_lookup_state(pctldev->p, PINCTRL_STATE_DEFAULT);
2027	if (IS_ERR(pctldev->hog_default)) {	2026	if (IS_ERR(pctldev->hog_default)) {

drivers/pinctrl/freescale/pinctrl-scu.c+2−2

@@ -23,12 +23,12 @@ struct imx_sc_msg_req_pad_set { · 22 unmodified lines
23	struct imx_sc_rpc_msg hdr;	23	struct imx_sc_rpc_msg hdr;
24	u32 val;	24	u32 val;
25	u16 pad;	25	u16 pad;
26	} __packed;	26	} __packed __aligned(4);
27		27
28	struct imx_sc_msg_req_pad_get {	28	struct imx_sc_msg_req_pad_get {
29	struct imx_sc_rpc_msg hdr;	29	struct imx_sc_rpc_msg hdr;
30	u16 pad;	30	u16 pad;
31	} __packed;	31	} __packed __aligned(4);
32		32
33	struct imx_sc_msg_resp_pad_get {	33	struct imx_sc_msg_resp_pad_get {
34	struct imx_sc_rpc_msg hdr;	34	struct imx_sc_rpc_msg hdr;

drivers/pinctrl/meson/pinctrl-meson-gxl.c+2−2

@@ -147,8 +147,8 @@ static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; · 146 unmodified lines
147	static const unsigned int sdio_d1_pins[] = { GPIOX_1 };	147	static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
148	static const unsigned int sdio_d2_pins[] = { GPIOX_2 };	148	static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
149	static const unsigned int sdio_d3_pins[] = { GPIOX_3 };	149	static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
150	static const unsigned int sdio_cmd_pins[] = { GPIOX_4 };	150	static const unsigned int sdio_clk_pins[] = { GPIOX_4 };
151	static const unsigned int sdio_clk_pins[] = { GPIOX_5 };	151	static const unsigned int sdio_cmd_pins[] = { GPIOX_5 };
152	static const unsigned int sdio_irq_pins[] = { GPIOX_7 };	152	static const unsigned int sdio_irq_pins[] = { GPIOX_7 };
153		153
154	static const unsigned int nand_ce0_pins[] = { BOOT_8 };	154	static const unsigned int nand_ce0_pins[] = { BOOT_8 };

drivers/pinctrl/pinctrl-falcon.c+1−1

@@ -451,7 +451,7 @@ static int pinctrl_falcon_probe(struct platform_device *pdev) · 450 unmodified lines
451	falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);	451	falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
452	if (IS_ERR(falcon_info.clk[*bank])) {	452	if (IS_ERR(falcon_info.clk[*bank])) {
453	dev_err(&ppdev->dev, "failed to get clock\n");	453	dev_err(&ppdev->dev, "failed to get clock\n");
454	of_node_put(np)	454	of_node_put(np);
455	return PTR_ERR(falcon_info.clk[*bank]);	455	return PTR_ERR(falcon_info.clk[*bank]);
456	}	456	}
457	falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,	457	falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,

drivers/pinctrl/qcom/pinctrl-msm.c+1−2

drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c+1−1

@@ -794,7 +794,7 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) · 793 unmodified lines
794	girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node);	794	girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node);
795	girq->parent_domain = parent_domain;	795	girq->parent_domain = parent_domain;
796	girq->child_to_parent_hwirq = pm8xxx_child_to_parent_hwirq;	796	girq->child_to_parent_hwirq = pm8xxx_child_to_parent_hwirq;
797	girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_fourcell;	797	girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell;
798	girq->child_offset_to_irq = pm8xxx_child_offset_to_irq;	798	girq->child_offset_to_irq = pm8xxx_child_offset_to_irq;
799	girq->child_irq_domain_ops.translate = pm8xxx_domain_translate;	799	girq->child_irq_domain_ops.translate = pm8xxx_domain_translate;
800		800

drivers/platform/chrome/wilco_ec/properties.c+1−1

@@ -5,7 +5,7 @@ · 4 unmodified lines
5		5
6	#include <linux/platform_data/wilco-ec.h>	6	#include <linux/platform_data/wilco-ec.h>
7	#include <linux/string.h>	7	#include <linux/string.h>
8	#include <linux/unaligned/le_memmove.h>	8	#include <asm/unaligned.h>
9		9
10	/* Operation code; what the EC should do with the property */	10	/* Operation code; what the EC should do with the property */
11	enum ec_property_op {	11	enum ec_property_op {

drivers/regulator/stm32-vrefbuf.c+2−1

 	}
 	val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
-	val = (val & ~STM32_ENVR) | STM32_HIZ;
+	val &= ~STM32_ENVR;
 	writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
 	pm_runtime_mark_last_busy(priv->dev);
 	.volt_table = stm32_vrefbuf_voltages,
 	.n_voltages = ARRAY_SIZE(stm32_vrefbuf_voltages),
 	.ops = &stm32_vrefbuf_volt_ops,
+	.off_on_delay = 1000,
 	.type = REGULATOR_VOLTAGE,
 	.owner = THIS_MODULE,
 };

drivers/reset/Kconfig+2−1

 config RESET_BRCMSTB_RESCAL
 	bool "Broadcom STB RESCAL reset controller"
+	depends on HAS_IOMEM
 	default ARCH_BRCMSTB || COMPILE_TEST
 	help
 	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
 config RESET_INTEL_GW
 	bool "Intel Reset Controller Driver"
-	depends on OF
+	depends on OF && HAS_IOMEM
 	select REGMAP_MMIO
 	help
 	  This enables the reset controller driver for Intel Gateway SoCs.

drivers/rtc/Kconfig+1−0

@@ -327,6 +327,7 @@ config RTC_DRV_MAX6900 · 326 unmodified lines
327	config RTC_DRV_MAX8907	327	config RTC_DRV_MAX8907
328	tristate "Maxim MAX8907"	328	tristate "Maxim MAX8907"
329	depends on MFD_MAX8907 \|\| COMPILE_TEST	329	depends on MFD_MAX8907 \|\| COMPILE_TEST
		330	select REGMAP_IRQ
330	help	331	help
331	If you say yes here you will get support for the	332	If you say yes here you will get support for the
332	RTC of Maxim MAX8907 PMIC.	333	RTC of Maxim MAX8907 PMIC.

drivers/s390/block/dasd.c+24−3

 		     (unsigned long) block);
 	INIT_LIST_HEAD(&block->ccw_queue);
 	spin_lock_init(&block->queue_lock);
+	INIT_LIST_HEAD(&block->format_list);
+	spin_lock_init(&block->format_lock);
 	timer_setup(&block->timer, dasd_block_timeout, 0);
 	spin_lock_init(&block->profile.lock);
 	if (dasd_ese_needs_format(cqr->block, irb)) {
 		if (rq_data_dir((struct request *)cqr->callback_data) == READ) {
-			device->discipline->ese_read(cqr);
+			device->discipline->ese_read(cqr, irb);
 			cqr->status = DASD_CQR_SUCCESS;
 			cqr->stopclk = now;
 			dasd_device_clear_timer(device);
 			dasd_schedule_device_bh(device);
 			return;
 		}
-		fcqr = device->discipline->ese_format(device, cqr);
+		fcqr = device->discipline->ese_format(device, cqr, irb);
 		if (IS_ERR(fcqr)) {
+			if (PTR_ERR(fcqr) == -EINVAL) {
+				cqr->status = DASD_CQR_ERROR;
+				return;
+			}
 			/*
 			 * If we can't format now, let the request go
 			 * one extra round. Maybe we can format later.
 			 */
 			cqr->status = DASD_CQR_QUEUED;
+			dasd_schedule_device_bh(device);
+			return;
 		} else {
 			fcqr->status = DASD_CQR_QUEUED;
 			cqr->status = DASD_CQR_QUEUED;
 {
 	struct request *req;
 	blk_status_t error = BLK_STS_OK;
+	unsigned int proc_bytes;
 	int status;
 	req = (struct request *) cqr->callback_data;
 	dasd_profile_end(cqr->block, cqr, req);
+	proc_bytes = cqr->proc_bytes;
 	status = cqr->block->base->discipline->free_cp(cqr, req);
 	if (status < 0)
 		error = errno_to_blk_status(status);
 		blk_mq_end_request(req, error);
 		blk_mq_run_hw_queues(req->q, true);
 	} else {
-		blk_mq_complete_request(req);
+		/*
+		 * Partial completed requests can happen with ESE devices.
+		 * During read we might have gotten a NRF error and have to
+		 * complete a request partially.
+		 */
+		if (proc_bytes) {
+			blk_update_request(req, BLK_STS_OK,
+					   blk_rq_bytes(req) - proc_bytes);
+			blk_mq_requeue_request(req, true);
+		} else {
+			blk_mq_complete_request(req);
+		}
 	}
 }

drivers/s390/block/dasd_eckd.c+156−7

@@ -207,6 +207,45 @@ static void set_ch_t(struct ch_t *geo, __u32 cyl, __u8 head) · 206 unmodified lines
207	geo->head \|= head;	207	geo->head \|= head;
208	}	208	}
209		209
		210	/*
		211	* calculate failing track from sense data depending if
		212	* it is an EAV device or not
		213	*/
		214	static int dasd_eckd_track_from_irb(struct irb irb, struct dasd_device device,
		215	sector_t *track)
		216	{
		217	struct dasd_eckd_private *private = device->private;
		218	u8 *sense = NULL;
		219	u32 cyl;
		220	u8 head;
		221
		222	sense = dasd_get_sense(irb);
		223	if (!sense) {
		224	DBF_DEV_EVENT(DBF_WARNING, device, "%s",
		225	"ESE error no sense data\n");
		226	return -EINVAL;
		227	}
		228	if (!(sense[27] & DASD_SENSE_BIT_2)) {
		229	DBF_DEV_EVENT(DBF_WARNING, device, "%s",
		230	"ESE error no valid track data\n");
		231	return -EINVAL;
		232	}
		233
		234	if (sense[27] & DASD_SENSE_BIT_3) {
		235	/* enhanced addressing */
		236	cyl = sense[30] << 20;
		237	cyl \|= (sense[31] & 0xF0) << 12;
		238	cyl \|= sense[28] << 8;
		239	cyl \|= sense[29];
		240	} else {
		241	cyl = sense[29] << 8;
		242	cyl \|= sense[30];
		243	}
		244	head = sense[31] & 0x0F;
		245	track = cyl private->rdc_data.trk_per_cyl + head;
		246	return 0;
		247	}
		248
210	static int set_timestamp(struct ccw1 ccw, struct DE_eckd_data data,	249	static int set_timestamp(struct ccw1 ccw, struct DE_eckd_data data,
211	struct dasd_device *device)	250	struct dasd_device *device)
212	{	251	{
@@ -2986,6 +3025,37 @@ static int dasd_eckd_format_device(struct dasd_device *base, · 2773 unmodified lines
2986	0, NULL);	3025	0, NULL);
2987	}	3026	}
2988		3027
		3028	static bool test_and_set_format_track(struct dasd_format_entry *to_format,
		3029	struct dasd_block *block)
		3030	{
		3031	struct dasd_format_entry *format;
		3032	unsigned long flags;
		3033	bool rc = false;
		3034
		3035	spin_lock_irqsave(&block->format_lock, flags);
		3036	list_for_each_entry(format, &block->format_list, list) {
		3037	if (format->track == to_format->track) {
		3038	rc = true;
		3039	goto out;
		3040	}
		3041	}
		3042	list_add_tail(&to_format->list, &block->format_list);
		3043
		3044	out:
		3045	spin_unlock_irqrestore(&block->format_lock, flags);
		3046	return rc;
		3047	}
		3048
		3049	static void clear_format_track(struct dasd_format_entry *format,
		3050	struct dasd_block *block)
		3051	{
		3052	unsigned long flags;
		3053
		3054	spin_lock_irqsave(&block->format_lock, flags);
		3055	list_del_init(&format->list);
		3056	spin_unlock_irqrestore(&block->format_lock, flags);
		3057	}
		3058
2989	/*	3059	/*
2990	* Callback function to free ESE format requests.	3060	* Callback function to free ESE format requests.
2991	*/	3061	*/
@@ -2993,15 +3063,19 @@ static void dasd_eckd_ese_format_cb(struct dasd_ccw_req cqr, void data) · 1 unmodified line
2993	{	3063	{
2994	struct dasd_device *device = cqr->startdev;	3064	struct dasd_device *device = cqr->startdev;
2995	struct dasd_eckd_private *private = device->private;	3065	struct dasd_eckd_private *private = device->private;
		3066	struct dasd_format_entry *format = data;
2996		3067
		3068	clear_format_track(format, cqr->basedev->block);
2997	private->count--;	3069	private->count--;
2998	dasd_ffree_request(cqr, device);	3070	dasd_ffree_request(cqr, device);
2999	}	3071	}
3000		3072
3001	static struct dasd_ccw_req *	3073	static struct dasd_ccw_req *
3002	dasd_eckd_ese_format(struct dasd_device startdev, struct dasd_ccw_req cqr)	3074	dasd_eckd_ese_format(struct dasd_device startdev, struct dasd_ccw_req cqr,
		3075	struct irb *irb)
3003	{	3076	{
3004	struct dasd_eckd_private *private;	3077	struct dasd_eckd_private *private;
		3078	struct dasd_format_entry *format;
3005	struct format_data_t fdata;	3079	struct format_data_t fdata;
3006	unsigned int recs_per_trk;	3080	unsigned int recs_per_trk;
3007	struct dasd_ccw_req *fcqr;	3081	struct dasd_ccw_req *fcqr;
@@ -3011,23 +3085,39 @@ dasd_eckd_ese_format(struct dasd_device startdev, struct dasd_ccw_req cqr) · 3 unmodified lines
3011	struct request *req;	3085	struct request *req;
3012	sector_t first_trk;	3086	sector_t first_trk;
3013	sector_t last_trk;	3087	sector_t last_trk;
		3088	sector_t curr_trk;
3014	int rc;	3089	int rc;
3015		3090
3016	req = cqr->callback_data;	3091	req = cqr->callback_data;
3017	base = cqr->block->base;	3092	block = cqr->block;
		3093	base = block->base;
3018	private = base->private;	3094	private = base->private;
3019	block = base->block;
3020	blksize = block->bp_block;	3095	blksize = block->bp_block;
3021	recs_per_trk = recs_per_track(&private->rdc_data, 0, blksize);	3096	recs_per_trk = recs_per_track(&private->rdc_data, 0, blksize);
		3097	format = &startdev->format_entry;
3022		3098
3023	first_trk = blk_rq_pos(req) >> block->s2b_shift;	3099	first_trk = blk_rq_pos(req) >> block->s2b_shift;
3024	sector_div(first_trk, recs_per_trk);	3100	sector_div(first_trk, recs_per_trk);
3025	last_trk =	3101	last_trk =
3026	(blk_rq_pos(req) + blk_rq_sectors(req) - 1) >> block->s2b_shift;	3102	(blk_rq_pos(req) + blk_rq_sectors(req) - 1) >> block->s2b_shift;
3027	sector_div(last_trk, recs_per_trk);	3103	sector_div(last_trk, recs_per_trk);
		3104	rc = dasd_eckd_track_from_irb(irb, base, &curr_trk);
		3105	if (rc)
		3106	return ERR_PTR(rc);
3028		3107
3029	fdata.start_unit = first_trk;	3108	if (curr_trk < first_trk \|\| curr_trk > last_trk) {
3030	fdata.stop_unit = last_trk;	3109	DBF_DEV_EVENT(DBF_WARNING, startdev,
		3110	"ESE error track %llu not within range %llu - %llu\n",
		3111	curr_trk, first_trk, last_trk);
		3112	return ERR_PTR(-EINVAL);
		3113	}
		3114	format->track = curr_trk;
		3115	/* test if track is already in formatting by another thread */
		3116	if (test_and_set_format_track(format, block))
		3117	return ERR_PTR(-EEXIST);
		3118
		3119	fdata.start_unit = curr_trk;
		3120	fdata.stop_unit = curr_trk;
3031	fdata.blksize = blksize;	3121	fdata.blksize = blksize;
3032	fdata.intensity = private->uses_cdl ? DASD_FMT_INT_COMPAT : 0;	3122	fdata.intensity = private->uses_cdl ? DASD_FMT_INT_COMPAT : 0;
3033		3123
@@ -3044,6 +3134,7 @@ dasd_eckd_ese_format(struct dasd_device startdev, struct dasd_ccw_req cqr) · 10 unmodified lines
3044	return fcqr;	3134	return fcqr;
3045		3135
3046	fcqr->callback = dasd_eckd_ese_format_cb;	3136	fcqr->callback = dasd_eckd_ese_format_cb;
		3137	fcqr->callback_data = (void *) format;
3047		3138
3048	return fcqr;	3139	return fcqr;
3049	}	3140	}
@@ -3051,29 +3142,87 @@ dasd_eckd_ese_format(struct dasd_device startdev, struct dasd_ccw_req cqr) · 1 unmodified line
3051	/*	3142	/*
3052	* When data is read from an unformatted area of an ESE volume, this function	3143	* When data is read from an unformatted area of an ESE volume, this function
3053	* returns zeroed data and thereby mimics a read of zero data.	3144	* returns zeroed data and thereby mimics a read of zero data.
		3145	*
		3146	* The first unformatted track is the one that got the NRF error, the address is
		3147	* encoded in the sense data.
		3148	*
		3149	* All tracks before have returned valid data and should not be touched.
		3150	* All tracks after the unformatted track might be formatted or not. This is
		3151	* currently not known, remember the processed data and return the remainder of
		3152	* the request to the blocklayer in __dasd_cleanup_cqr().
3054	*/	3153	*/
3055	static void dasd_eckd_ese_read(struct dasd_ccw_req *cqr)	3154	static int dasd_eckd_ese_read(struct dasd_ccw_req cqr, struct irb irb)
3056	{	3155	{
		3156	struct dasd_eckd_private *private;
		3157	sector_t first_trk, last_trk;
		3158	sector_t first_blk, last_blk;
3057	unsigned int blksize, off;	3159	unsigned int blksize, off;
		3160	unsigned int recs_per_trk;
3058	struct dasd_device *base;	3161	struct dasd_device *base;
3059	struct req_iterator iter;	3162	struct req_iterator iter;
		3163	struct dasd_block *block;
		3164	unsigned int skip_block;
		3165	unsigned int blk_count;
3060	struct request *req;	3166	struct request *req;
3061	struct bio_vec bv;	3167	struct bio_vec bv;
		3168	sector_t curr_trk;
		3169	sector_t end_blk;
3062	char *dst;	3170	char *dst;
		3171	int rc;
3063		3172
3064	req = (struct request *) cqr->callback_data;	3173	req = (struct request *) cqr->callback_data;
3065	base = cqr->block->base;	3174	base = cqr->block->base;
3066	blksize = base->block->bp_block;	3175	blksize = base->block->bp_block;
		3176	block = cqr->block;
		3177	private = base->private;
		3178	skip_block = 0;
		3179	blk_count = 0;
		3180
		3181	recs_per_trk = recs_per_track(&private->rdc_data, 0, blksize);
		3182	first_trk = first_blk = blk_rq_pos(req) >> block->s2b_shift;
		3183	sector_div(first_trk, recs_per_trk);
		3184	last_trk = last_blk =
		3185	(blk_rq_pos(req) + blk_rq_sectors(req) - 1) >> block->s2b_shift;
		3186	sector_div(last_trk, recs_per_trk);
		3187	rc = dasd_eckd_track_from_irb(irb, base, &curr_trk);
		3188	if (rc)
		3189	return rc;
		3190
		3191	/* sanity check if the current track from sense data is valid */
		3192	if (curr_trk < first_trk \|\| curr_trk > last_trk) {
		3193	DBF_DEV_EVENT(DBF_WARNING, base,
		3194	"ESE error track %llu not within range %llu - %llu\n",
		3195	curr_trk, first_trk, last_trk);
		3196	return -EINVAL;
		3197	}
		3198
		3199	/*
		3200	* if not the first track got the NRF error we have to skip over valid
		3201	* blocks
		3202	*/
		3203	if (curr_trk != first_trk)
		3204	skip_block = curr_trk * recs_per_trk - first_blk;
		3205
		3206	/* we have no information beyond the current track */
		3207	end_blk = (curr_trk + 1) * recs_per_trk;
3067		3208
3068	rq_for_each_segment(bv, req, iter) {	3209	rq_for_each_segment(bv, req, iter) {
3069	dst = page_address(bv.bv_page) + bv.bv_offset;	3210	dst = page_address(bv.bv_page) + bv.bv_offset;
3070	for (off = 0; off < bv.bv_len; off += blksize) {	3211	for (off = 0; off < bv.bv_len; off += blksize) {
3071	if (dst && rq_data_dir(req) == READ) {	3212	if (first_blk + blk_count >= end_blk) {
		3213	cqr->proc_bytes = blk_count * blksize;
		3214	return 0;
		3215	}
		3216	if (dst && !skip_block) {
3072	dst += off;	3217	dst += off;
3073	memset(dst, 0, blksize);	3218	memset(dst, 0, blksize);
		3219	} else {
		3220	skip_block--;
3074	}	3221	}
		3222	blk_count++;
3075	}	3223	}
3076	}	3224	}
		3225	return 0;
3077	}	3226	}
3078		3227
3079	/*	3228	/*

drivers/s390/block/dasd_int.h+13−2

 	void (*callback)(struct dasd_ccw_req *, void *data);
 	void *callback_data;
+	unsigned int proc_bytes;	/* bytes for partial completion */
 };
 /*
 	int (*ext_pool_warn_thrshld)(struct dasd_device *);
 	int (*ext_pool_oos)(struct dasd_device *);
 	int (*ext_pool_exhaust)(struct dasd_device *, struct dasd_ccw_req *);
-	struct dasd_ccw_req *(*ese_format)(struct dasd_device *, struct dasd_ccw_req *);
+	struct dasd_ccw_req *(*ese_format)(struct dasd_device *,
-	void (*ese_read)(struct dasd_ccw_req *);
+					   struct dasd_ccw_req *, struct irb *);
+	int (*ese_read)(struct dasd_ccw_req *, struct irb *);
 };
 extern struct dasd_discipline *dasd_diag_discipline_pointer;
 	spinlock_t lock;
 };
+struct dasd_format_entry {
+	struct list_head list;
+	sector_t track;
+};
 struct dasd_device {
 	/* Block device stuff. */
 	struct dasd_block *block;
 	struct dentry *debugfs_dentry;
 	struct dentry *hosts_dentry;
 	struct dasd_profile profile;
+	struct dasd_format_entry format_entry;
 };
 struct dasd_block {
 	struct dentry *debugfs_dentry;
 	struct dasd_profile profile;
+	struct list_head format_list;
+	spinlock_t format_lock;
 };
 struct dasd_attention_data {

drivers/s390/net/qeth_core.h+2−2

@@ -369,7 +369,7 @@ enum qeth_qdio_info_states { · 368 unmodified lines
369	struct qeth_buffer_pool_entry {	369	struct qeth_buffer_pool_entry {
370	struct list_head list;	370	struct list_head list;
371	struct list_head init_list;	371	struct list_head init_list;
372	void *elements[QDIO_MAX_ELEMENTS_PER_BUFFER];	372	struct page *elements[QDIO_MAX_ELEMENTS_PER_BUFFER];
373	};	373	};
374		374
375	struct qeth_qdio_buffer_pool {	375	struct qeth_qdio_buffer_pool {
@@ -983,7 +983,7 @@ extern const struct attribute_group qeth_device_blkt_group; · 607 unmodified lines
983	extern const struct device_type qeth_generic_devtype;	983	extern const struct device_type qeth_generic_devtype;
984		984
985	const char qeth_get_cardname_short(struct qeth_card );	985	const char qeth_get_cardname_short(struct qeth_card );
986	int qeth_realloc_buffer_pool(struct qeth_card *, int);	986	int qeth_resize_buffer_pool(struct qeth_card *card, unsigned int count);
987	int qeth_core_load_discipline(struct qeth_card *, enum qeth_discipline_id);	987	int qeth_core_load_discipline(struct qeth_card *, enum qeth_discipline_id);
988	void qeth_core_free_discipline(struct qeth_card *);	988	void qeth_core_free_discipline(struct qeth_card *);
989		989

drivers/s390/net/qeth_core_main.c+118−58

@@ -65,7 +65,6 @@ static struct lock_class_key qdio_out_skb_queue_key; · 64 unmodified lines
65	static void qeth_issue_next_read_cb(struct qeth_card *card,	65	static void qeth_issue_next_read_cb(struct qeth_card *card,
66	struct qeth_cmd_buffer *iob,	66	struct qeth_cmd_buffer *iob,
67	unsigned int data_length);	67	unsigned int data_length);
68	static void qeth_free_buffer_pool(struct qeth_card *);
69	static int qeth_qdio_establish(struct qeth_card *);	68	static int qeth_qdio_establish(struct qeth_card *);
70	static void qeth_free_qdio_queues(struct qeth_card *card);	69	static void qeth_free_qdio_queues(struct qeth_card *card);
71	static void qeth_notify_skbs(struct qeth_qdio_out_q *queue,	70	static void qeth_notify_skbs(struct qeth_qdio_out_q *queue,
@@ -212,49 +211,121 @@ void qeth_clear_working_pool_list(struct qeth_card *card) · 140 unmodified lines
212	}	211	}
213	EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);	212	EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
214		213
		214	static void qeth_free_pool_entry(struct qeth_buffer_pool_entry *entry)
		215	{
		216	unsigned int i;
		217
		218	for (i = 0; i < ARRAY_SIZE(entry->elements); i++) {
		219	if (entry->elements[i])
		220	__free_page(entry->elements[i]);
		221	}
		222
		223	kfree(entry);
		224	}
		225
		226	static void qeth_free_buffer_pool(struct qeth_card *card)
		227	{
		228	struct qeth_buffer_pool_entry entry, tmp;
		229
		230	list_for_each_entry_safe(entry, tmp, &card->qdio.init_pool.entry_list,
		231	init_list) {
		232	list_del(&entry->init_list);
		233	qeth_free_pool_entry(entry);
		234	}
		235	}
		236
		237	static struct qeth_buffer_pool_entry *qeth_alloc_pool_entry(unsigned int pages)
		238	{
		239	struct qeth_buffer_pool_entry *entry;
		240	unsigned int i;
		241
		242	entry = kzalloc(sizeof(*entry), GFP_KERNEL);
		243	if (!entry)
		244	return NULL;
		245
		246	for (i = 0; i < pages; i++) {
		247	entry->elements[i] = alloc_page(GFP_KERNEL);
		248
		249	if (!entry->elements[i]) {
		250	qeth_free_pool_entry(entry);
		251	return NULL;
		252	}
		253	}
		254
		255	return entry;
		256	}
		257
215	static int qeth_alloc_buffer_pool(struct qeth_card *card)	258	static int qeth_alloc_buffer_pool(struct qeth_card *card)
216	{	259	{
217	struct qeth_buffer_pool_entry *pool_entry;	260	unsigned int buf_elements = QETH_MAX_BUFFER_ELEMENTS(card);
218	void *ptr;	261	unsigned int i;
219	int i, j;
220		262
221	QETH_CARD_TEXT(card, 5, "alocpool");	263	QETH_CARD_TEXT(card, 5, "alocpool");
222	for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {	264	for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
223	pool_entry = kzalloc(sizeof(*pool_entry), GFP_KERNEL);	265	struct qeth_buffer_pool_entry *entry;
224	if (!pool_entry) {	266
		267	entry = qeth_alloc_pool_entry(buf_elements);
		268	if (!entry) {
225	qeth_free_buffer_pool(card);	269	qeth_free_buffer_pool(card);
226	return -ENOMEM;	270	return -ENOMEM;
227	}	271	}
228	for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {	272
229	ptr = (void *) __get_free_page(GFP_KERNEL);	273	list_add(&entry->init_list, &card->qdio.init_pool.entry_list);
230	if (!ptr) {
231	while (j > 0)
232	free_page((unsigned long)
233	pool_entry->elements[--j]);
234	kfree(pool_entry);
235	qeth_free_buffer_pool(card);
236	return -ENOMEM;
237	}
238	pool_entry->elements[j] = ptr;
239	}
240	list_add(&pool_entry->init_list,
241	&card->qdio.init_pool.entry_list);
242	}	274	}
243	return 0;	275	return 0;
244	}	276	}
245		277
246	int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)	278	int qeth_resize_buffer_pool(struct qeth_card *card, unsigned int count)
247	{	279	{
		280	unsigned int buf_elements = QETH_MAX_BUFFER_ELEMENTS(card);
		281	struct qeth_qdio_buffer_pool *pool = &card->qdio.init_pool;
		282	struct qeth_buffer_pool_entry entry, tmp;
		283	int delta = count - pool->buf_count;
		284	LIST_HEAD(entries);
		285
248	QETH_CARD_TEXT(card, 2, "realcbp");	286	QETH_CARD_TEXT(card, 2, "realcbp");
249		287
250	/* TODO: steel/add buffers from/to a running card's buffer pool (?) */	288	/* Defer until queue is allocated: */
251	qeth_clear_working_pool_list(card);	289	if (!card->qdio.in_q)
252	qeth_free_buffer_pool(card);	290	goto out;
253	card->qdio.in_buf_pool.buf_count = bufcnt;	291
254	card->qdio.init_pool.buf_count = bufcnt;	292	/* Remove entries from the pool: */
255	return qeth_alloc_buffer_pool(card);	293	while (delta < 0) {
		294	entry = list_first_entry(&pool->entry_list,
		295	struct qeth_buffer_pool_entry,
		296	init_list);
		297	list_del(&entry->init_list);
		298	qeth_free_pool_entry(entry);
		299
		300	delta++;
		301	}
		302
		303	/* Allocate additional entries: */
		304	while (delta > 0) {
		305	entry = qeth_alloc_pool_entry(buf_elements);
		306	if (!entry) {
		307	list_for_each_entry_safe(entry, tmp, &entries,
		308	init_list) {
		309	list_del(&entry->init_list);
		310	qeth_free_pool_entry(entry);
		311	}
		312
		313	return -ENOMEM;
		314	}
		315
		316	list_add(&entry->init_list, &entries);
		317
		318	delta--;
		319	}
		320
		321	list_splice(&entries, &pool->entry_list);
		322
		323	out:
		324	card->qdio.in_buf_pool.buf_count = count;
		325	pool->buf_count = count;
		326	return 0;
256	}	327	}
257	EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);	328	EXPORT_SYMBOL_GPL(qeth_resize_buffer_pool);
258		329
259	static void qeth_free_qdio_queue(struct qeth_qdio_q *q)	330	static void qeth_free_qdio_queue(struct qeth_qdio_q *q)
260	{	331	{
@@ -1170,19 +1241,6 @@ void qeth_drain_output_queues(struct qeth_card *card) · 909 unmodified lines
1170	}	1241	}
1171	EXPORT_SYMBOL_GPL(qeth_drain_output_queues);	1242	EXPORT_SYMBOL_GPL(qeth_drain_output_queues);
1172		1243
1173	static void qeth_free_buffer_pool(struct qeth_card *card)
1174	{
1175	struct qeth_buffer_pool_entry pool_entry, tmp;
1176	int i = 0;
1177	list_for_each_entry_safe(pool_entry, tmp,
1178	&card->qdio.init_pool.entry_list, init_list){
1179	for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
1180	free_page((unsigned long)pool_entry->elements[i]);
1181	list_del(&pool_entry->init_list);
1182	kfree(pool_entry);
1183	}
1184	}
1185
1186	static int qeth_osa_set_output_queues(struct qeth_card *card, bool single)	1244	static int qeth_osa_set_output_queues(struct qeth_card *card, bool single)
1187	{	1245	{
1188	unsigned int count = single ? 1 : card->dev->num_tx_queues;	1246	unsigned int count = single ? 1 : card->dev->num_tx_queues;
@@ -1204,7 +1262,6 @@ static int qeth_osa_set_output_queues(struct qeth_card *card, bool single) · 15 unmodified lines
1204	if (count == 1)	1262	if (count == 1)
1205	dev_info(&card->gdev->dev, "Priority Queueing not supported\n");	1263	dev_info(&card->gdev->dev, "Priority Queueing not supported\n");
1206		1264
1207	card->qdio.default_out_queue = single ? 0 : QETH_DEFAULT_QUEUE;
1208	card->qdio.no_out_queues = count;	1265	card->qdio.no_out_queues = count;
1209	return 0;	1266	return 0;
1210	}	1267	}
@@ -2393,7 +2450,6 @@ static void qeth_free_qdio_queues(struct qeth_card *card) · 1182 unmodified lines
2393	return;	2450	return;
2394		2451
2395	qeth_free_cq(card);	2452	qeth_free_cq(card);
2396	cancel_delayed_work_sync(&card->buffer_reclaim_work);
2397	for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {	2453	for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
2398	if (card->qdio.in_q->bufs[j].rx_skb)	2454	if (card->qdio.in_q->bufs[j].rx_skb)
2399	dev_kfree_skb_any(card->qdio.in_q->bufs[j].rx_skb);	2455	dev_kfree_skb_any(card->qdio.in_q->bufs[j].rx_skb);
@@ -2575,7 +2631,6 @@ static struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry( · 175 unmodified lines
2575	struct list_head *plh;	2631	struct list_head *plh;
2576	struct qeth_buffer_pool_entry *entry;	2632	struct qeth_buffer_pool_entry *entry;
2577	int i, free;	2633	int i, free;
2578	struct page *page;
2579		2634
2580	if (list_empty(&card->qdio.in_buf_pool.entry_list))	2635	if (list_empty(&card->qdio.in_buf_pool.entry_list))
2581	return NULL;	2636	return NULL;
@@ -2584,7 +2639,7 @@ static struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry( · 2 unmodified lines
2584	entry = list_entry(plh, struct qeth_buffer_pool_entry, list);	2639	entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
2585	free = 1;	2640	free = 1;
2586	for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {	2641	for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2587	if (page_count(virt_to_page(entry->elements[i])) > 1) {	2642	if (page_count(entry->elements[i]) > 1) {
2588	free = 0;	2643	free = 0;
2589	break;	2644	break;
2590	}	2645	}
@@ -2599,15 +2654,15 @@ static struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry( · 8 unmodified lines
2599	entry = list_entry(card->qdio.in_buf_pool.entry_list.next,	2654	entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
2600	struct qeth_buffer_pool_entry, list);	2655	struct qeth_buffer_pool_entry, list);
2601	for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {	2656	for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2602	if (page_count(virt_to_page(entry->elements[i])) > 1) {	2657	if (page_count(entry->elements[i]) > 1) {
2603	page = alloc_page(GFP_ATOMIC);	2658	struct page *page = alloc_page(GFP_ATOMIC);
2604	if (!page) {	2659
		2660	if (!page)
2605	return NULL;	2661	return NULL;
2606	} else {	2662
2607	free_page((unsigned long)entry->elements[i]);	2663	__free_page(entry->elements[i]);
2608	entry->elements[i] = page_address(page);	2664	entry->elements[i] = page;
2609	QETH_CARD_STAT_INC(card, rx_sg_alloc_page);	2665	QETH_CARD_STAT_INC(card, rx_sg_alloc_page);
2610	}
2611	}	2666	}
2612	}	2667	}
2613	list_del_init(&entry->list);	2668	list_del_init(&entry->list);
@@ -2625,12 +2680,12 @@ static int qeth_init_input_buffer(struct qeth_card *card, · 11 unmodified lines
2625	ETH_HLEN +	2680	ETH_HLEN +
2626	sizeof(struct ipv6hdr));	2681	sizeof(struct ipv6hdr));
2627	if (!buf->rx_skb)	2682	if (!buf->rx_skb)
2628	return 1;	2683	return -ENOMEM;
2629	}	2684	}
2630		2685
2631	pool_entry = qeth_find_free_buffer_pool_entry(card);	2686	pool_entry = qeth_find_free_buffer_pool_entry(card);
2632	if (!pool_entry)	2687	if (!pool_entry)
2633	return 1;	2688	return -ENOBUFS;
2634		2689
2635	/*	2690	/*
2636	* since the buffer is accessed only from the input_tasklet	2691	* since the buffer is accessed only from the input_tasklet
@@ -2643,7 +2698,7 @@ static int qeth_init_input_buffer(struct qeth_card *card, · 6 unmodified lines
2643	for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {	2698	for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2644	buf->buffer->element[i].length = PAGE_SIZE;	2699	buf->buffer->element[i].length = PAGE_SIZE;
2645	buf->buffer->element[i].addr =	2700	buf->buffer->element[i].addr =
2646	virt_to_phys(pool_entry->elements[i]);	2701	page_to_phys(pool_entry->elements[i]);
2647	if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)	2702	if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
2648	buf->buffer->element[i].eflags = SBAL_EFLAGS_LAST_ENTRY;	2703	buf->buffer->element[i].eflags = SBAL_EFLAGS_LAST_ENTRY;
2649	else	2704	else
@@ -2675,10 +2730,15 @@ static int qeth_init_qdio_queues(struct qeth_card *card) · 25 unmodified lines
2675	/* inbound queue */	2730	/* inbound queue */
2676	qdio_reset_buffers(card->qdio.in_q->qdio_bufs, QDIO_MAX_BUFFERS_PER_Q);	2731	qdio_reset_buffers(card->qdio.in_q->qdio_bufs, QDIO_MAX_BUFFERS_PER_Q);
2677	memset(&card->rx, 0, sizeof(struct qeth_rx));	2732	memset(&card->rx, 0, sizeof(struct qeth_rx));
		2733
2678	qeth_initialize_working_pool_list(card);	2734	qeth_initialize_working_pool_list(card);
2679	/give only as many buffers to hardware as we have buffer pool entries/	2735	/give only as many buffers to hardware as we have buffer pool entries/
2680	for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)	2736	for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; i++) {
2681	qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);	2737	rc = qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
		2738	if (rc)
		2739	return rc;
		2740	}
		2741
2682	card->qdio.in_q->next_buf_to_init =	2742	card->qdio.in_q->next_buf_to_init =
2683	card->qdio.in_buf_pool.buf_count - 1;	2743	card->qdio.in_buf_pool.buf_count - 1;
2684	rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,	2744	rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,

drivers/s390/net/qeth_core_sys.c+4−5

@@ -247,8 +247,8 @@ static ssize_t qeth_dev_bufcnt_store(struct device *dev, · 246 unmodified lines
247	struct device_attribute attr, const char buf, size_t count)	247	struct device_attribute attr, const char buf, size_t count)
248	{	248	{
249	struct qeth_card *card = dev_get_drvdata(dev);	249	struct qeth_card *card = dev_get_drvdata(dev);
		250	unsigned int cnt;
250	char *tmp;	251	char *tmp;
251	int cnt, old_cnt;
252	int rc = 0;	252	int rc = 0;
253		253
254	mutex_lock(&card->conf_mutex);	254	mutex_lock(&card->conf_mutex);
@@ -257,13 +257,12 @@ static ssize_t qeth_dev_bufcnt_store(struct device *dev, · 2 unmodified lines
257	goto out;	257	goto out;
258	}	258	}
259		259
260	old_cnt = card->qdio.in_buf_pool.buf_count;
261	cnt = simple_strtoul(buf, &tmp, 10);	260	cnt = simple_strtoul(buf, &tmp, 10);
262	cnt = (cnt < QETH_IN_BUF_COUNT_MIN) ? QETH_IN_BUF_COUNT_MIN :	261	cnt = (cnt < QETH_IN_BUF_COUNT_MIN) ? QETH_IN_BUF_COUNT_MIN :
263	((cnt > QETH_IN_BUF_COUNT_MAX) ? QETH_IN_BUF_COUNT_MAX : cnt);	262	((cnt > QETH_IN_BUF_COUNT_MAX) ? QETH_IN_BUF_COUNT_MAX : cnt);
264	if (old_cnt != cnt) {	263
265	rc = qeth_realloc_buffer_pool(card, cnt);	264	rc = qeth_resize_buffer_pool(card, cnt);
266	}	265
267	out:	266	out:
268	mutex_unlock(&card->conf_mutex);	267	mutex_unlock(&card->conf_mutex);
269	return rc ? rc : count;	268	return rc ? rc : count;

drivers/s390/net/qeth_l2_main.c+1−0

@@ -284,6 +284,7 @@ static void qeth_l2_stop_card(struct qeth_card *card) · 283 unmodified lines
284	if (card->state == CARD_STATE_SOFTSETUP) {	284	if (card->state == CARD_STATE_SOFTSETUP) {
285	qeth_clear_ipacmd_list(card);	285	qeth_clear_ipacmd_list(card);
286	qeth_drain_output_queues(card);	286	qeth_drain_output_queues(card);
		287	cancel_delayed_work_sync(&card->buffer_reclaim_work);
287	card->state = CARD_STATE_DOWN;	288	card->state = CARD_STATE_DOWN;
288	}	289	}
289		290

drivers/s390/net/qeth_l3_main.c+1−0

@@ -1178,6 +1178,7 @@ static void qeth_l3_stop_card(struct qeth_card *card) · 1177 unmodified lines
1178	qeth_l3_clear_ip_htable(card, 1);	1178	qeth_l3_clear_ip_htable(card, 1);
1179	qeth_clear_ipacmd_list(card);	1179	qeth_clear_ipacmd_list(card);
1180	qeth_drain_output_queues(card);	1180	qeth_drain_output_queues(card);
		1181	cancel_delayed_work_sync(&card->buffer_reclaim_work);
1181	card->state = CARD_STATE_DOWN;	1182	card->state = CARD_STATE_DOWN;
1182	}	1183	}
1183		1184

drivers/s390/net/qeth_l3_sys.c+4−5

 		qdio_get_ssqd_desc(CARD_DDEV(card), &card->ssqd);
 		if (card->ssqd.qdioac2 & CHSC_AC2_SNIFFER_AVAILABLE) {
 			card->options.sniffer = i;
-			if (card->qdio.init_pool.buf_count !=
+			qeth_resize_buffer_pool(card, QETH_IN_BUF_COUNT_MAX);
-					QETH_IN_BUF_COUNT_MAX)
+		} else {
-				qeth_realloc_buffer_pool(card,
-					QETH_IN_BUF_COUNT_MAX);
-		} else
 			rc = -EPERM;
+		}
 		break;
 	default:
 		rc = -EINVAL;

drivers/s390/scsi/zfcp_fsf.h+1−1

@@ -410,7 +410,7 @@ struct fsf_qtcb_bottom_port { · 409 unmodified lines
410	u8 cb_util;	410	u8 cb_util;
411	u8 a_util;	411	u8 a_util;
412	u8 res2;	412	u8 res2;
413	u16 temperature;	413	s16 temperature;
414	u16 vcc;	414	u16 vcc;
415	u16 tx_bias;	415	u16 tx_bias;
416	u16 tx_power;	416	u16 tx_power;

drivers/s390/scsi/zfcp_sysfs.c+1−1

@@ -800,7 +800,7 @@ static ZFCP_DEV_ATTR(adapter_diag, b2b_credit, 0400, · 799 unmodified lines
800	static ZFCP_DEV_ATTR(adapter_diag_sfp, _name, 0400, \	800	static ZFCP_DEV_ATTR(adapter_diag_sfp, _name, 0400, \
801	zfcp_sysfs_adapter_diag_sfp_##_name##_show, NULL)	801	zfcp_sysfs_adapter_diag_sfp_##_name##_show, NULL)
802		802
803	ZFCP_DEFINE_DIAG_SFP_ATTR(temperature, temperature, 5, "%hu");	803	ZFCP_DEFINE_DIAG_SFP_ATTR(temperature, temperature, 6, "%hd");
804	ZFCP_DEFINE_DIAG_SFP_ATTR(vcc, vcc, 5, "%hu");	804	ZFCP_DEFINE_DIAG_SFP_ATTR(vcc, vcc, 5, "%hu");
805	ZFCP_DEFINE_DIAG_SFP_ATTR(tx_bias, tx_bias, 5, "%hu");	805	ZFCP_DEFINE_DIAG_SFP_ATTR(tx_bias, tx_bias, 5, "%hu");
806	ZFCP_DEFINE_DIAG_SFP_ATTR(tx_power, tx_power, 5, "%hu");	806	ZFCP_DEFINE_DIAG_SFP_ATTR(tx_power, tx_power, 5, "%hu");

drivers/scsi/ipr.c+2−1

 	ioa_cfg->max_devs_supported = ipr_max_devs;
 	if (ioa_cfg->sis64) {
+		host->max_channel = IPR_MAX_SIS64_BUSES;
 		host->max_id = IPR_MAX_SIS64_TARGETS_PER_BUS;
 		host->max_lun = IPR_MAX_SIS64_LUNS_PER_TARGET;
 		if (ipr_max_devs > IPR_MAX_SIS64_DEVS)
 					   + ((sizeof(struct ipr_config_table_entry64)
 					       * ioa_cfg->max_devs_supported)));
 	} else {
+		host->max_channel = IPR_VSET_BUS;
 		host->max_id = IPR_MAX_NUM_TARGETS_PER_BUS;
 		host->max_lun = IPR_MAX_NUM_LUNS_PER_TARGET;
 		if (ipr_max_devs > IPR_MAX_PHYSICAL_DEVS)
 					       * ioa_cfg->max_devs_supported)));
 	}
-	host->max_channel = IPR_VSET_BUS;
 	host->unique_id = host->host_no;
 	host->max_cmd_len = IPR_MAX_CDB_LEN;
 	host->can_queue = ioa_cfg->max_cmds;

drivers/scsi/ipr.h+1−0

@@ -1300,6 +1300,7 @@ struct ipr_resource_entry { · 1299 unmodified lines
1300	#define IPR_ARRAY_VIRTUAL_BUS 0x1	1300	#define IPR_ARRAY_VIRTUAL_BUS 0x1
1301	#define IPR_VSET_VIRTUAL_BUS 0x2	1301	#define IPR_VSET_VIRTUAL_BUS 0x2
1302	#define IPR_IOAFP_VIRTUAL_BUS 0x3	1302	#define IPR_IOAFP_VIRTUAL_BUS 0x3
		1303	#define IPR_MAX_SIS64_BUSES 0x4
1303		1304
1304	#define IPR_GET_RES_PHYS_LOC(res) \	1305	#define IPR_GET_RES_PHYS_LOC(res) \
1305	(((res)->bus << 24) \| ((res)->target << 8) \| (res)->lun)	1306	(((res)->bus << 24) \| ((res)->target << 8) \| (res)->lun)

drivers/scsi/libfc/fc_disc.c+2−0

@@ -628,6 +628,8 @@ redisc: · 627 unmodified lines
628	}	628	}
629	out:	629	out:
630	kref_put(&rdata->kref, fc_rport_destroy);	630	kref_put(&rdata->kref, fc_rport_destroy);
		631	if (!IS_ERR(fp))
		632	fc_frame_free(fp);
631	}	633	}
632		634
633	/**	635	/**

drivers/scsi/sd_zbc.c+6−1

 			unsigned int nr_zones, report_zones_cb cb, void *data)
 {
 	struct scsi_disk *sdkp = scsi_disk(disk);
+	sector_t capacity = logical_to_sectors(sdkp->device, sdkp->capacity);
 	unsigned int nr, i;
 	unsigned char *buf;
 	size_t offset, buflen = 0;
 		/* Not a zoned device */
 		return -EOPNOTSUPP;
+	if (!capacity)
+		/* Device gone or invalid */
+		return -ENODEV;
 	buf = sd_zbc_alloc_report_buffer(sdkp, nr_zones, &buflen);
 	if (!buf)
 		return -ENOMEM;
-	while (zone_idx < nr_zones && sector < get_capacity(disk)) {
+	while (zone_idx < nr_zones && sector < capacity) {
 		ret = sd_zbc_do_report_zones(sdkp, buf, buflen,
 				sectors_to_logical(sdkp->device, sector), true);
 		if (ret)

drivers/scsi/sr.c+1−1

@@ -688,7 +688,7 @@ static const struct block_device_operations sr_bdops = · 687 unmodified lines
688	.release = sr_block_release,	688	.release = sr_block_release,
689	.ioctl = sr_block_ioctl,	689	.ioctl = sr_block_ioctl,
690	#ifdef CONFIG_COMPAT	690	#ifdef CONFIG_COMPAT
691	.ioctl = sr_block_compat_ioctl,	691	.compat_ioctl = sr_block_compat_ioctl,
692	#endif	692	#endif
693	.check_events = sr_block_check_events,	693	.check_events = sr_block_check_events,
694	.revalidate_disk = sr_block_revalidate_disk,	694	.revalidate_disk = sr_block_revalidate_disk,

drivers/scsi/ufs/ufshcd.c+14−7

 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
 {
 	unsigned long flags;
+	bool update = false;
-	if (!(hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT))
+	if (!ufshcd_is_auto_hibern8_supported(hba))
 		return;
 	spin_lock_irqsave(hba->host->host_lock, flags);
-	if (hba->ahit == ahit)
+	if (hba->ahit != ahit) {
-		goto out_unlock;
+		hba->ahit = ahit;
-	hba->ahit = ahit;
+		update = true;
-	if (!pm_runtime_suspended(hba->dev))
+	}
-		ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
-out_unlock:
 	spin_unlock_irqrestore(hba->host->host_lock, flags);
+	if (update && !pm_runtime_suspended(hba->dev)) {
+		pm_runtime_get_sync(hba->dev);
+		ufshcd_hold(hba, false);
+		ufshcd_auto_hibern8_enable(hba);
+		ufshcd_release(hba);
+		pm_runtime_put(hba->dev);
+	}
 }
 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);

drivers/slimbus/qcom-ngd-ctrl.c+3−0

 	{
 		.compatible = "qcom,slim-ngd-v1.5.0",
 		.data = &ngd_v1_5_offset_info,
+	},{
+		.compatible = "qcom,slim-ngd-v2.1.0",
+		.data = &ngd_v1_5_offset_info,
 	},
 	{}
 };

drivers/soc/imx/soc-imx-scu.c+1−1

@@ -25,7 +25,7 @@ struct imx_sc_msg_misc_get_soc_id { · 24 unmodified lines
25	u32 id;	25	u32 id;
26	} resp;	26	} resp;
27	} data;	27	} data;
28	} __packed;	28	} __packed __aligned(4);
29		29
30	struct imx_sc_msg_misc_get_soc_uid {	30	struct imx_sc_msg_misc_get_soc_uid {
31	struct imx_sc_rpc_msg hdr;	31	struct imx_sc_rpc_msg hdr;

drivers/spi/atmel-quadspi.c+11−0

 	struct clk		*qspick;
 	struct platform_device	*pdev;
 	const struct atmel_qspi_caps *caps;
+	resource_size_t		mmap_size;
 	u32			pending;
 	u32			mr;
 	u32			scr;
 	u32 sr, offset;
 	int err;
+	/*
+	 * Check if the address exceeds the MMIO window size. An improvement
+	 * would be to add support for regular SPI mode and fall back to it
+	 * when the flash memories overrun the controller's memory space.
+	 */
+	if (op->addr.val + op->data.nbytes > aq->mmap_size)
+		return -ENOTSUPP;
 	err = atmel_qspi_set_cfg(aq, op, &offset);
 	if (err)
 		return err;
 		goto exit;
 	}
+	aq->mmap_size = resource_size(res);
 	/* Get the peripheral clock */
 	aq->pclk = devm_clk_get(&pdev->dev, "pclk");
 	if (IS_ERR(aq->pclk))

drivers/spi/spi-bcm63xx-hsspi.c+0−1

@@ -366,7 +366,6 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) · 365 unmodified lines
366	goto out_disable_clk;	366	goto out_disable_clk;
367		367
368	rate = clk_get_rate(pll_clk);	368	rate = clk_get_rate(pll_clk);
369	clk_disable_unprepare(pll_clk);
370	if (!rate) {	369	if (!rate) {
371	ret = -EINVAL;	370	ret = -EINVAL;
372	goto out_disable_pll_clk;	371	goto out_disable_pll_clk;

drivers/spi/spi-omap2-mcspi.c+64−39

 	int			fifo_depth;
 	bool			slave_aborted;
 	unsigned int		pin_dir:1;
+	size_t			max_xfer_len;
 };
 struct omap2_mcspi_cs {
  * Note that we currently allow DMA only if we get a channel
  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
  */
-static int omap2_mcspi_request_dma(struct spi_device *spi)
+static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi,
+				   struct omap2_mcspi_dma *mcspi_dma)
 {
-	struct spi_master	*master = spi->master;
-	struct omap2_mcspi	*mcspi;
-	struct omap2_mcspi_dma	*mcspi_dma;
 	int ret = 0;
-	mcspi = spi_master_get_devdata(master);
+	mcspi_dma->dma_rx = dma_request_chan(mcspi->dev,
-	mcspi_dma = mcspi->dma_channels + spi->chip_select;
-	init_completion(&mcspi_dma->dma_rx_completion);
-	init_completion(&mcspi_dma->dma_tx_completion);
-	mcspi_dma->dma_rx = dma_request_chan(&master->dev,
 					     mcspi_dma->dma_rx_ch_name);
 	if (IS_ERR(mcspi_dma->dma_rx)) {
 		ret = PTR_ERR(mcspi_dma->dma_rx);
 		goto no_dma;
 	}
-	mcspi_dma->dma_tx = dma_request_chan(&master->dev,
+	mcspi_dma->dma_tx = dma_request_chan(mcspi->dev,
 					     mcspi_dma->dma_tx_ch_name);
 	if (IS_ERR(mcspi_dma->dma_tx)) {
 		ret = PTR_ERR(mcspi_dma->dma_tx);
 		mcspi_dma->dma_rx = NULL;
 	}
+	init_completion(&mcspi_dma->dma_rx_completion);
+	init_completion(&mcspi_dma->dma_tx_completion);
 no_dma:
 	return ret;
 }
+static void omap2_mcspi_release_dma(struct spi_master *master)
+{
+	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
+	struct omap2_mcspi_dma	*mcspi_dma;
+	int i;
+	for (i = 0; i < master->num_chipselect; i++) {
+		mcspi_dma = &mcspi->dma_channels[i];
+		if (mcspi_dma->dma_rx) {
+			dma_release_channel(mcspi_dma->dma_rx);
+			mcspi_dma->dma_rx = NULL;
+		}
+		if (mcspi_dma->dma_tx) {
+			dma_release_channel(mcspi_dma->dma_tx);
+			mcspi_dma->dma_tx = NULL;
+		}
+	}
+}
 static int omap2_mcspi_setup(struct spi_device *spi)
 {
 	int			ret;
 	struct omap2_mcspi	*mcspi = spi_master_get_devdata(spi->master);
 	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
-	struct omap2_mcspi_dma	*mcspi_dma;
 	struct omap2_mcspi_cs	*cs = spi->controller_state;
-	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 	if (!cs) {
 		cs = kzalloc(sizeof *cs, GFP_KERNEL);
 		if (!cs)
 		}
 	}
-	if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
-		ret = omap2_mcspi_request_dma(spi);
-		if (ret)
-			dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
-				 ret);
-	}
 	ret = pm_runtime_get_sync(mcspi->dev);
 	if (ret < 0) {
 		pm_runtime_put_noidle(mcspi->dev);
 static void omap2_mcspi_cleanup(struct spi_device *spi)
 {
-	struct omap2_mcspi	*mcspi;
-	struct omap2_mcspi_dma	*mcspi_dma;
 	struct omap2_mcspi_cs	*cs;
-	mcspi = spi_master_get_devdata(spi->master);
 	if (spi->controller_state) {
 		/* Unlink controller state from context save list */
 		cs = spi->controller_state;
 		kfree(cs);
 	}
-	if (spi->chip_select < spi->master->num_chipselect) {
-		mcspi_dma = &mcspi->dma_channels[spi->chip_select];
-		if (mcspi_dma->dma_rx) {
-			dma_release_channel(mcspi_dma->dma_rx);
-			mcspi_dma->dma_rx = NULL;
-		}
-		if (mcspi_dma->dma_tx) {
-			dma_release_channel(mcspi_dma->dma_tx);
-			mcspi_dma->dma_tx = NULL;
-		}
-	}
 	if (gpio_is_valid(spi->cs_gpio))
 		gpio_free(spi->cs_gpio);
 }
 	if (spi_controller_is_slave(master))
 		return true;
+	master->dma_rx = mcspi_dma->dma_rx;
+	master->dma_tx = mcspi_dma->dma_tx;
 	return (xfer->len >= DMA_MIN_BYTES);
 }
+static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi)
+{
+	struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
+	struct omap2_mcspi_dma *mcspi_dma =
+		&mcspi->dma_channels[spi->chip_select];
+	if (mcspi->max_xfer_len && mcspi_dma->dma_rx)
+		return mcspi->max_xfer_len;
+	return SIZE_MAX;
+}
 static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
 {
 	struct spi_master	*master = mcspi->master;
 	.regs_offset = OMAP4_MCSPI_REG_OFFSET,
 };
+static struct omap2_mcspi_platform_config am654_pdata = {
+	.regs_offset = OMAP4_MCSPI_REG_OFFSET,
+	.max_xfer_len = SZ_4K - 1,
+};
 static const struct of_device_id omap_mcspi_of_match[] = {
 	{
 		.compatible = "ti,omap2-mcspi",
 		.compatible = "ti,omap4-mcspi",
 		.data = &omap4_pdata,
 	},
+	{
+		.compatible = "ti,am654-mcspi",
+		.data = &am654_pdata,
+	},
 	{ },
 };
 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
 		mcspi->pin_dir = pdata->pin_dir;
 	}
 	regs_offset = pdata->regs_offset;
+	if (pdata->max_xfer_len) {
+		mcspi->max_xfer_len = pdata->max_xfer_len;
+		master->max_transfer_size = omap2_mcspi_max_xfer_size;
+	}
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	mcspi->base = devm_ioremap_resource(&pdev->dev, r);
 	for (i = 0; i < master->num_chipselect; i++) {
 		sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
 		sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
+		status = omap2_mcspi_request_dma(mcspi,
+						 &mcspi->dma_channels[i]);
+		if (status == -EPROBE_DEFER)
+			goto free_master;
 	}
 	status = platform_get_irq(pdev, 0);
 	pm_runtime_put_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 free_master:
+	omap2_mcspi_release_dma(master);
 	spi_master_put(master);
 	return status;
 }
 	struct spi_master *master = platform_get_drvdata(pdev);
 	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
+	omap2_mcspi_release_dma(master);
 	pm_runtime_dont_use_autosuspend(mcspi->dev);
 	pm_runtime_put_sync(mcspi->dev);
 	pm_runtime_disable(&pdev->dev);

drivers/spi/spi-pxa2xx.c+23−0

 #define LPSS_CAPS_CS_EN_SHIFT			9
 #define LPSS_CAPS_CS_EN_MASK			(0xf << LPSS_CAPS_CS_EN_SHIFT)
+#define LPSS_PRIV_CLOCK_GATE 0x38
+#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
+#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
 struct lpss_config {
 	/* LPSS offset from drv_data->ioaddr */
 	unsigned offset;
 	unsigned cs_sel_shift;
 	unsigned cs_sel_mask;
 	unsigned cs_num;
+	/* Quirks */
+	unsigned cs_clk_stays_gated : 1;
 };
 /* Keep these sorted with enum pxa_ssp_type */
 		.tx_threshold_hi = 56,
 		.cs_sel_shift = 8,
 		.cs_sel_mask = 3 << 8,
+		.cs_clk_stays_gated = true,
 	},
 };
 	else
 		value |= LPSS_CS_CONTROL_CS_HIGH;
 	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
+	if (config->cs_clk_stays_gated) {
+		u32 clkgate;
+		/*
+		 * Changing CS alone when dynamic clock gating is on won't
+		 * actually flip CS at that time. This ruins SPI transfers
+		 * that specify delays, or have no data. Toggle the clock mode
+		 * to force on briefly to poke the CS pin to move.
+		 */
+		clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
+		value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
+			LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
+		__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
+		__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
+	}
 }
 static void cs_assert(struct spi_device *spi)

drivers/spi/spi-qup.c+7−4

 	struct spi_qup *controller = spi_master_get_devdata(master);
 	int ret;
+	if (pm_runtime_suspended(device)) {
+		ret = spi_qup_pm_resume_runtime(device);
+		if (ret)
+			return ret;
+	}
 	ret = spi_master_suspend(master);
 	if (ret)
 		return ret;
 	if (ret)
 		return ret;
-	if (!pm_runtime_suspended(device)) {
+	clk_disable_unprepare(controller->cclk);
-		clk_disable_unprepare(controller->cclk);
+	clk_disable_unprepare(controller->iclk);
-		clk_disable_unprepare(controller->iclk);
-	}
 	return 0;
 }

drivers/spi/spi-zynqmp-gqspi.c+0−3

@@ -401,9 +401,6 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) · 400 unmodified lines
401		401
402	zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);	402	zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
403		403
404	/* Dummy generic FIFO entry */
405	zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
406
407	/* Manually start the generic FIFO command */	404	/* Manually start the generic FIFO command */
408	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,	405	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
409	zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) \|	406	zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) \|

drivers/spi/spi.c+15−17

 		if (ctlr->use_gpio_descriptors) {
 			status = spi_get_gpio_descs(ctlr);
 			if (status)
-				return status;
+				goto free_bus_id;
 			/*
 			 * A controller using GPIO descriptors always
 			 * supports SPI_CS_HIGH if need be.
 			/* Legacy code path for GPIOs from DT */
 			status = of_spi_get_gpio_numbers(ctlr);
 			if (status)
-				return status;
+				goto free_bus_id;
 		}
 	}
 	 * Even if it's just one always-selected device, there must
 	 * be at least one chipselect.
 	 */
-	if (!ctlr->num_chipselect)
+	if (!ctlr->num_chipselect) {
-		return -EINVAL;
+		status = -EINVAL;
+		goto free_bus_id;
+	}
 	status = device_add(&ctlr->dev);
-	if (status < 0) {
+	if (status < 0)
-		/* free bus id */
+		goto free_bus_id;
-		mutex_lock(&board_lock);
-		idr_remove(&spi_master_idr, ctlr->bus_num);
-		mutex_unlock(&board_lock);
-		goto done;
-	}
 	dev_dbg(dev, "registered %s %s\n",
 			spi_controller_is_slave(ctlr) ? "slave" : "master",
 			dev_name(&ctlr->dev));
 		status = spi_controller_initialize_queue(ctlr);
 		if (status) {
 			device_del(&ctlr->dev);
-			/* free bus id */
+			goto free_bus_id;
-			mutex_lock(&board_lock);
-			idr_remove(&spi_master_idr, ctlr->bus_num);
-			mutex_unlock(&board_lock);
-			goto done;
 		}
 	}
 	/* add statistics */
 	/* Register devices from the device tree and ACPI */
 	of_register_spi_devices(ctlr);
 	acpi_register_spi_devices(ctlr);
-done:
+	return status;
+free_bus_id:
+	mutex_lock(&board_lock);
+	idr_remove(&spi_master_idr, ctlr->bus_num);
+	mutex_unlock(&board_lock);
 	return status;
 }
 EXPORT_SYMBOL_GPL(spi_register_controller);

drivers/spi/spidev.c+5−0

 		else
 			retval = get_user(tmp, (u32 __user *)arg);
 		if (retval == 0) {
+			struct spi_controller *ctlr = spi->controller;
 			u32	save = spi->mode;
 			if (tmp & ~SPI_MODE_MASK) {
 				break;
 			}
+			if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods &&
+			    ctlr->cs_gpiods[spi->chip_select])
+				tmp |= SPI_CS_HIGH;
 			tmp |= spi->mode & ~SPI_MODE_MASK;
 			spi->mode = (u16)tmp;
 			retval = spi_setup(spi);

drivers/staging/greybus/tools/loopback_test.c+11−10

 #include <signal.h>
 #define MAX_NUM_DEVICES 10
+#define MAX_SYSFS_PREFIX 0x80
 #define MAX_SYSFS_PATH	0x200
 #define CSV_MAX_LINE	0x1000
 #define SYSFS_MAX_INT	0x20
 };
 struct loopback_device {
-	char name[MAX_SYSFS_PATH];
+	char name[MAX_STR_LEN];
 	char sysfs_entry[MAX_SYSFS_PATH];
 	char debugfs_entry[MAX_SYSFS_PATH];
 	struct loopback_results results;
 	int stop_all;
 	int poll_count;
 	char test_name[MAX_STR_LEN];
-	char sysfs_prefix[MAX_SYSFS_PATH];
+	char sysfs_prefix[MAX_SYSFS_PREFIX];
-	char debugfs_prefix[MAX_SYSFS_PATH];
+	char debugfs_prefix[MAX_SYSFS_PREFIX];
 	struct timespec poll_timeout;
 	struct loopback_device devices[MAX_NUM_DEVICES];
 	struct loopback_results aggregate_results;
 static int open_poll_files(struct loopback_test *t)
 {
 	struct loopback_device *dev;
-	char buf[MAX_STR_LEN];
+	char buf[MAX_SYSFS_PATH + MAX_STR_LEN];
 	char dummy;
 	int fds_idx = 0;
 	int i;
 			goto err;
 		}
 		read(t->fds[fds_idx].fd, &dummy, 1);
-		t->fds[fds_idx].events = EPOLLERR|EPOLLPRI;
+		t->fds[fds_idx].events = POLLERR | POLLPRI;
 		t->fds[fds_idx].revents = 0;
 		fds_idx++;
 	}
 		}
 		for (i = 0; i < t->poll_count; i++) {
-			if (t->fds[i].revents & EPOLLPRI) {
+			if (t->fds[i].revents & POLLPRI) {
 				/* Dummy read to clear the event */
 				read(t->fds[i].fd, &dummy, 1);
 				number_of_events++;
 			t.iteration_max = atoi(optarg);
 			break;
 		case 'S':
-			snprintf(t.sysfs_prefix, MAX_SYSFS_PATH, "%s", optarg);
+			snprintf(t.sysfs_prefix, MAX_SYSFS_PREFIX, "%s", optarg);
 			break;
 		case 'D':
-			snprintf(t.debugfs_prefix, MAX_SYSFS_PATH, "%s", optarg);
+			snprintf(t.debugfs_prefix, MAX_SYSFS_PREFIX, "%s", optarg);
 			break;
 		case 'm':
 			t.mask = atol(optarg);
 	}
 	if (!strcmp(t.sysfs_prefix, ""))
-		snprintf(t.sysfs_prefix, MAX_SYSFS_PATH, "%s", sysfs_prefix);
+		snprintf(t.sysfs_prefix, MAX_SYSFS_PREFIX, "%s", sysfs_prefix);
 	if (!strcmp(t.debugfs_prefix, ""))
-		snprintf(t.debugfs_prefix, MAX_SYSFS_PATH, "%s", debugfs_prefix);
+		snprintf(t.debugfs_prefix, MAX_SYSFS_PREFIX, "%s", debugfs_prefix);
 	ret = find_loopback_devices(&t);
 	if (ret)

drivers/staging/media/hantro/hantro_drv.c+2−2

@@ -558,13 +558,13 @@ static int hantro_attach_func(struct hantro_dev *vpu, · 557 unmodified lines
558	goto err_rel_entity1;	558	goto err_rel_entity1;
559		559
560	/* Connect the three entities */	560	/* Connect the three entities */
561	ret = media_create_pad_link(&func->vdev.entity, 0, &func->proc, 1,	561	ret = media_create_pad_link(&func->vdev.entity, 0, &func->proc, 0,
562	MEDIA_LNK_FL_IMMUTABLE \|	562	MEDIA_LNK_FL_IMMUTABLE \|
563	MEDIA_LNK_FL_ENABLED);	563	MEDIA_LNK_FL_ENABLED);
564	if (ret)	564	if (ret)
565	goto err_rel_entity2;	565	goto err_rel_entity2;
566		566
567	ret = media_create_pad_link(&func->proc, 0, &func->sink, 0,	567	ret = media_create_pad_link(&func->proc, 1, &func->sink, 0,
568	MEDIA_LNK_FL_IMMUTABLE \|	568	MEDIA_LNK_FL_IMMUTABLE \|
569	MEDIA_LNK_FL_ENABLED);	569	MEDIA_LNK_FL_ENABLED);
570	if (ret)	570	if (ret)

drivers/staging/rtl8188eu/os_dep/usb_intf.c+1−0

@@ -38,6 +38,7 @@ static const struct usb_device_id rtw_usb_id_tbl[] = { · 37 unmodified lines
38	{USB_DEVICE(0x2001, 0x331B)}, /* D-Link DWA-121 rev B1 */	38	{USB_DEVICE(0x2001, 0x331B)}, /* D-Link DWA-121 rev B1 */
39	{USB_DEVICE(0x2357, 0x010c)}, /* TP-Link TL-WN722N v2 */	39	{USB_DEVICE(0x2357, 0x010c)}, /* TP-Link TL-WN722N v2 */
40	{USB_DEVICE(0x2357, 0x0111)}, /* TP-Link TL-WN727N v5.21 */	40	{USB_DEVICE(0x2357, 0x0111)}, /* TP-Link TL-WN727N v5.21 */
		41	{USB_DEVICE(0x2C4E, 0x0102)}, /* MERCUSYS MW150US v2 */
41	{USB_DEVICE(0x0df6, 0x0076)}, /* Sitecom N150 v2 */	42	{USB_DEVICE(0x0df6, 0x0076)}, /* Sitecom N150 v2 */
42	{USB_DEVICE(USB_VENDER_ID_REALTEK, 0xffef)}, /* Rosewill RNX-N150NUB */	43	{USB_DEVICE(USB_VENDER_ID_REALTEK, 0xffef)}, /* Rosewill RNX-N150NUB */
43	{} /* Terminating entry */	44	{} /* Terminating entry */

drivers/staging/speakup/main.c+1−1

@@ -561,7 +561,7 @@ static u_long get_word(struct vc_data *vc) · 560 unmodified lines
561	return 0;	561	return 0;
562	} else if (tmpx < vc->vc_cols - 2 &&	562	} else if (tmpx < vc->vc_cols - 2 &&
563	(ch == SPACE \|\| ch == 0 \|\| (ch < 0x100 && IS_WDLM(ch))) &&	563	(ch == SPACE \|\| ch == 0 \|\| (ch < 0x100 && IS_WDLM(ch))) &&
564	get_char(vc, (u_short *)&tmp_pos + 1, &temp) > SPACE) {	564	get_char(vc, (u_short *)tmp_pos + 1, &temp) > SPACE) {
565	tmp_pos += 2;	565	tmp_pos += 2;
566	tmpx++;	566	tmpx++;
567	} else {	567	} else {

drivers/staging/speakup/selection.c+0−2

@@ -51,9 +51,7 @@ static void __speakup_set_selection(struct work_struct *work) · 50 unmodified lines
51	goto unref;	51	goto unref;
52	}	52	}
53		53
54	console_lock();
55	set_selection_kernel(&sel, tty);	54	set_selection_kernel(&sel, tty);
56	console_unlock();
57		55
58	unref:	56	unref:
59	tty_kref_put(tty);	57	tty_kref_put(tty);

drivers/staging/wfx/Documentation/devicetree/bindings/net/wireless/siliabs,wfx.txt+1−1

@@ -93,5 +93,5 @@ Some properties are recognized either by SPI and SDIO versions: · 92 unmodified lines
93	Must contains 64 hexadecimal digits. Not supported in current version.	93	Must contains 64 hexadecimal digits. Not supported in current version.
94		94
95	WFx driver also supports `mac-address` and `local-mac-address` as described in	95	WFx driver also supports `mac-address` and `local-mac-address` as described in
96	Documentation/devicetree/binding/net/ethernet.txt	96	Documentation/devicetree/bindings/net/ethernet.txt
97		97

drivers/staging/wfx/hif_tx.c+8−7

 	else
 		control_reg_write(wdev, 0);
 	mutex_unlock(&wdev->hif_cmd.lock);
+	mutex_unlock(&wdev->hif_cmd.key_renew_lock);
 	kfree(hif);
 	return ret;
 }
 }
 int hif_join(struct wfx_vif *wvif, const struct ieee80211_bss_conf *conf,
-	     const struct ieee80211_channel *channel, const u8 *ssidie)
+	     struct ieee80211_channel *channel, const u8 *ssid, int ssidlen)
 {
 	int ret;
 	struct hif_msg *hif;
 	body->basic_rate_set =
 		cpu_to_le32(wfx_rate_mask_to_hw(wvif->wdev, conf->basic_rates));
 	memcpy(body->bssid, conf->bssid, sizeof(body->bssid));
-	if (!conf->ibss_joined && ssidie) {
+	if (!conf->ibss_joined && ssid) {
-		body->ssid_length = cpu_to_le32(ssidie[1]);
+		body->ssid_length = cpu_to_le32(ssidlen);
-		memcpy(body->ssid, &ssidie[2], ssidie[1]);
+		memcpy(body->ssid, ssid, ssidlen);
 	}
 	wfx_fill_header(hif, wvif->id, HIF_REQ_ID_JOIN, sizeof(*body));
 	ret = wfx_cmd_send(wvif->wdev, hif, NULL, 0, false);
 	struct hif_msg *hif;
 	struct hif_req_start *body = wfx_alloc_hif(sizeof(*body), &hif);
-	body->dtim_period = conf->dtim_period,
+	body->dtim_period = conf->dtim_period;
-	body->short_preamble = conf->use_short_preamble,
+	body->short_preamble = conf->use_short_preamble;
-	body->channel_number = cpu_to_le16(channel->hw_value),
+	body->channel_number = cpu_to_le16(channel->hw_value);
 	body->beacon_interval = cpu_to_le32(conf->beacon_int);
 	body->basic_rate_set =
 		cpu_to_le32(wfx_rate_mask_to_hw(wvif->wdev, conf->basic_rates));

drivers/staging/wfx/hif_tx.h+1−1

@@ -46,7 +46,7 @@ int hif_scan(struct wfx_vif wvif, struct cfg80211_scan_request req80211, · 45 unmodified lines
46	int chan_start, int chan_num);	46	int chan_start, int chan_num);
47	int hif_stop_scan(struct wfx_vif *wvif);	47	int hif_stop_scan(struct wfx_vif *wvif);
48	int hif_join(struct wfx_vif wvif, const struct ieee80211_bss_conf conf,	48	int hif_join(struct wfx_vif wvif, const struct ieee80211_bss_conf conf,
49	const struct ieee80211_channel channel, const u8 ssidie);	49	struct ieee80211_channel channel, const u8 ssid, int ssidlen);
50	int hif_set_pm(struct wfx_vif *wvif, bool ps, int dynamic_ps_timeout);	50	int hif_set_pm(struct wfx_vif *wvif, bool ps, int dynamic_ps_timeout);
51	int hif_set_bss_params(struct wfx_vif *wvif,	51	int hif_set_bss_params(struct wfx_vif *wvif,
52	const struct hif_req_set_bss_params *arg);	52	const struct hif_req_set_bss_params *arg);

drivers/staging/wfx/hif_tx_mib.h+10−5

 }
 static inline int hif_set_association_mode(struct wfx_vif *wvif,
-					   struct ieee80211_bss_conf *info,
+					   struct ieee80211_bss_conf *info)
-					   struct ieee80211_sta_ht_cap *ht_cap)
 {
 	int basic_rates = wfx_rate_mask_to_hw(wvif->wdev, info->basic_rates);
+	struct ieee80211_sta *sta = NULL;
 	struct hif_mib_set_association_mode val = {
 		.preambtype_use = 1,
 		.mode = 1,
 		.basic_rate_set = cpu_to_le32(basic_rates)
 	};
+	rcu_read_lock(); // protect sta
+	if (info->bssid && !info->ibss_joined)
+		sta = ieee80211_find_sta(wvif->vif, info->bssid);
 	// FIXME: it is strange to not retrieve all information from bss_info
-	if (ht_cap && ht_cap->ht_supported) {
+	if (sta && sta->ht_cap.ht_supported) {
-		val.mpdu_start_spacing = ht_cap->ampdu_density;
+		val.mpdu_start_spacing = sta->ht_cap.ampdu_density;
 		if (!(info->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT))
-			val.greenfield = !!(ht_cap->cap & IEEE80211_HT_CAP_GRN_FLD);
+			val.greenfield = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_GRN_FLD);
 	}
+	rcu_read_unlock();
 	return hif_write_mib(wvif->wdev, wvif->id,
 			     HIF_MIB_ID_SET_ASSOCIATION_MODE, &val, sizeof(val));

drivers/staging/wfx/sta.c+15−10

 static void wfx_do_join(struct wfx_vif *wvif)
 {
 	int ret;
-	const u8 *ssidie;
 	struct ieee80211_bss_conf *conf = &wvif->vif->bss_conf;
 	struct cfg80211_bss *bss = NULL;
+	u8 ssid[IEEE80211_MAX_SSID_LEN];
+	const u8 *ssidie = NULL;
+	int ssidlen = 0;
 	wfx_tx_lock_flush(wvif->wdev);
 	if (!wvif->beacon_int)
 		wvif->beacon_int = 1;
-	rcu_read_lock();
+	rcu_read_lock(); // protect ssidie
 	if (!conf->ibss_joined)
 		ssidie = ieee80211_bss_get_ie(bss, WLAN_EID_SSID);
-	else
+	if (ssidie) {
-		ssidie = NULL;
+		ssidlen = ssidie[1];
+		memcpy(ssid, &ssidie[2], ssidie[1]);
+	}
+	rcu_read_unlock();
 	wfx_tx_flush(wvif->wdev);
 	wfx_set_mfp(wvif, bss);
-	/* Perform actual join */
 	wvif->wdev->tx_burst_idx = -1;
-	ret = hif_join(wvif, conf, wvif->channel, ssidie);
+	ret = hif_join(wvif, conf, wvif->channel, ssid, ssidlen);
-	rcu_read_unlock();
 	if (ret) {
 		ieee80211_connection_loss(wvif->vif);
 		wvif->join_complete_status = -1;
 	int i;
 	for (i = 0; i < ARRAY_SIZE(sta_priv->buffered); i++)
-		WARN(sta_priv->buffered[i], "release station while Tx is in progress");
+		if (sta_priv->buffered[i])
+			dev_warn(wvif->wdev->dev, "release station while %d pending frame on queue %d",
+				 sta_priv->buffered[i], i);
 	// FIXME: see note in wfx_sta_add()
 	if (vif->type == NL80211_IFTYPE_STATION)
 		return 0;
 			wfx_rate_mask_to_hw(wvif->wdev, sta->supp_rates[wvif->channel->band]);
 	else
 		wvif->bss_params.operational_rate_set = -1;
+	rcu_read_unlock();
 	if (sta &&
 	    info->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT)
 		hif_dual_cts_protection(wvif, true);
 	wvif->bss_params.beacon_lost_count = 20;
 	wvif->bss_params.aid = info->aid;
-	hif_set_association_mode(wvif, info, sta ? &sta->ht_cap : NULL);
+	hif_set_association_mode(wvif, info);
-	rcu_read_unlock();
 	if (!info->ibss_joined) {
 		hif_keep_alive_period(wvif, 30 /* sec */);

drivers/tee/amdtee/Kconfig+1−1

@@ -3,6 +3,6 @@ · 2 unmodified lines
3	config AMDTEE	3	config AMDTEE
4	tristate "AMD-TEE"	4	tristate "AMD-TEE"
5	default m	5	default m
6	depends on CRYPTO_DEV_SP_PSP	6	depends on CRYPTO_DEV_SP_PSP && CRYPTO_DEV_CCP_DD
7	help	7	help
8	This implements AMD's Trusted Execution Environment (TEE) driver.	8	This implements AMD's Trusted Execution Environment (TEE) driver.

drivers/tee/amdtee/core.c+24−24

@@ -212,6 +212,19 @@ unlock: · 211 unmodified lines
212	return rc;	212	return rc;
213	}	213	}
214		214
		215	static void destroy_session(struct kref *ref)
		216	{
		217	struct amdtee_session *sess = container_of(ref, struct amdtee_session,
		218	refcount);
		219
		220	/* Unload the TA from TEE */
		221	handle_unload_ta(sess->ta_handle);
		222	mutex_lock(&session_list_mutex);
		223	list_del(&sess->list_node);
		224	mutex_unlock(&session_list_mutex);
		225	kfree(sess);
		226	}
		227
215	int amdtee_open_session(struct tee_context *ctx,	228	int amdtee_open_session(struct tee_context *ctx,
216	struct tee_ioctl_open_session_arg *arg,	229	struct tee_ioctl_open_session_arg *arg,
217	struct tee_param *param)	230	struct tee_param *param)
@@ -236,15 +249,13 @@ int amdtee_open_session(struct tee_context *ctx, · 18 unmodified lines
236		249
237	/* Load the TA binary into TEE environment */	250	/* Load the TA binary into TEE environment */
238	handle_load_ta(ta, ta_size, arg);	251	handle_load_ta(ta, ta_size, arg);
239	if (arg->ret == TEEC_SUCCESS) {
240	mutex_lock(&session_list_mutex);
241	sess = alloc_session(ctxdata, arg->session);
242	mutex_unlock(&session_list_mutex);
243	}
244
245	if (arg->ret != TEEC_SUCCESS)	252	if (arg->ret != TEEC_SUCCESS)
246	goto out;	253	goto out;
247		254
		255	mutex_lock(&session_list_mutex);
		256	sess = alloc_session(ctxdata, arg->session);
		257	mutex_unlock(&session_list_mutex);
		258
248	if (!sess) {	259	if (!sess) {
249	rc = -ENOMEM;	260	rc = -ENOMEM;
250	goto out;	261	goto out;
@@ -259,40 +270,29 @@ int amdtee_open_session(struct tee_context *ctx, · 8 unmodified lines
259		270
260	if (i >= TEE_NUM_SESSIONS) {	271	if (i >= TEE_NUM_SESSIONS) {
261	pr_err("reached maximum session count %d\n", TEE_NUM_SESSIONS);	272	pr_err("reached maximum session count %d\n", TEE_NUM_SESSIONS);
		273	kref_put(&sess->refcount, destroy_session);
262	rc = -ENOMEM;	274	rc = -ENOMEM;
263	goto out;	275	goto out;
264	}	276	}
265		277
266	/* Open session with loaded TA */	278	/* Open session with loaded TA */
267	handle_open_session(arg, &session_info, param);	279	handle_open_session(arg, &session_info, param);
268		280	if (arg->ret != TEEC_SUCCESS) {
269	if (arg->ret == TEEC_SUCCESS) {
270	sess->session_info[i] = session_info;
271	set_session_id(sess->ta_handle, i, &arg->session);
272	} else {
273	pr_err("open_session failed %d\n", arg->ret);	281	pr_err("open_session failed %d\n", arg->ret);
274	spin_lock(&sess->lock);	282	spin_lock(&sess->lock);
275	clear_bit(i, sess->sess_mask);	283	clear_bit(i, sess->sess_mask);
276	spin_unlock(&sess->lock);	284	spin_unlock(&sess->lock);
		285	kref_put(&sess->refcount, destroy_session);
		286	goto out;
277	}	287	}
		288
		289	sess->session_info[i] = session_info;
		290	set_session_id(sess->ta_handle, i, &arg->session);
278	out:	291	out:
279	free_pages((u64)ta, get_order(ta_size));	292	free_pages((u64)ta, get_order(ta_size));
280	return rc;	293	return rc;
281	}	294	}
282		295
283	static void destroy_session(struct kref *ref)
284	{
285	struct amdtee_session *sess = container_of(ref, struct amdtee_session,
286	refcount);
287
288	/* Unload the TA from TEE */
289	handle_unload_ta(sess->ta_handle);
290	mutex_lock(&session_list_mutex);
291	list_del(&sess->list_node);
292	mutex_unlock(&session_list_mutex);
293	kfree(sess);
294	}
295
296	int amdtee_close_session(struct tee_context *ctx, u32 session)	296	int amdtee_close_session(struct tee_context *ctx, u32 session)
297	{	297	{
298	struct amdtee_context_data *ctxdata = ctx->data;	298	struct amdtee_context_data *ctxdata = ctx->data;

drivers/thunderbolt/switch.c+1−1

@@ -954,7 +954,7 @@ static bool tb_port_is_width_supported(struct tb_port *port, int width) · 953 unmodified lines
954	ret = tb_port_read(port, &phy, TB_CFG_PORT,	954	ret = tb_port_read(port, &phy, TB_CFG_PORT,
955	port->cap_phy + LANE_ADP_CS_0, 1);	955	port->cap_phy + LANE_ADP_CS_0, 1);
956	if (ret)	956	if (ret)
957	return ret;	957	return false;
958		958
959	widths = (phy & LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK) >>	959	widths = (phy & LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK) >>
960	LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT;	960	LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT;

drivers/tty/serdev/core.c+10−0

 #include <linux/sched.h>
 #include <linux/serdev.h>
 #include <linux/slab.h>
+#include <linux/platform_data/x86/apple.h>
 static bool is_registered;
 static DEFINE_IDA(ctrl_ida);
 	if (ret)
 		return ret;
+	/*
+	 * Apple machines provide an empty resource template, so on those
+	 * machines just look for immediate children with a "baud" property
+	 * (from the _DSM method) instead.
+	 */
+	if (!lookup.controller_handle && x86_apple_machine &&
+	    !acpi_dev_get_property(adev, "baud", ACPI_TYPE_BUFFER, NULL))
+		acpi_get_parent(adev->handle, &lookup.controller_handle);
 	/* Make sure controller and ResourceSource handle match */
 	if (ACPI_HANDLE(ctrl->dev.parent) != lookup.controller_handle)
 		return -ENODEV;

drivers/tty/serial/8250/8250_exar.c+33−0

@@ -25,6 +25,14 @@ · 24 unmodified lines
25		25
26	#include "8250.h"	26	#include "8250.h"
27		27
		28	#define PCI_DEVICE_ID_ACCES_COM_2S 0x1052
		29	#define PCI_DEVICE_ID_ACCES_COM_4S 0x105d
		30	#define PCI_DEVICE_ID_ACCES_COM_8S 0x106c
		31	#define PCI_DEVICE_ID_ACCES_COM232_8 0x10a8
		32	#define PCI_DEVICE_ID_ACCES_COM_2SM 0x10d2
		33	#define PCI_DEVICE_ID_ACCES_COM_4SM 0x10db
		34	#define PCI_DEVICE_ID_ACCES_COM_8SM 0x10ea
		35
28	#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002	36	#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
29	#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004	37	#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
30	#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a	38	#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
@@ -677,6 +685,22 @@ static int __maybe_unused exar_resume(struct device *dev) · 646 unmodified lines
677		685
678	static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);	686	static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
679		687
		688	static const struct exar8250_board acces_com_2x = {
		689	.num_ports = 2,
		690	.setup = pci_xr17c154_setup,
		691	};
		692
		693	static const struct exar8250_board acces_com_4x = {
		694	.num_ports = 4,
		695	.setup = pci_xr17c154_setup,
		696	};
		697
		698	static const struct exar8250_board acces_com_8x = {
		699	.num_ports = 8,
		700	.setup = pci_xr17c154_setup,
		701	};
		702
		703
680	static const struct exar8250_board pbn_fastcom335_2 = {	704	static const struct exar8250_board pbn_fastcom335_2 = {
681	.num_ports = 2,	705	.num_ports = 2,
682	.setup = pci_fastcom335_setup,	706	.setup = pci_fastcom335_setup,
@@ -745,6 +769,15 @@ static const struct exar8250_board pbn_exar_XR17V8358 = { · 62 unmodified lines
745	}	769	}
746		770
747	static const struct pci_device_id exar_pci_tbl[] = {	771	static const struct pci_device_id exar_pci_tbl[] = {
		772	EXAR_DEVICE(ACCESSIO, ACCES_COM_2S, acces_com_2x),
		773	EXAR_DEVICE(ACCESSIO, ACCES_COM_4S, acces_com_4x),
		774	EXAR_DEVICE(ACCESSIO, ACCES_COM_8S, acces_com_8x),
		775	EXAR_DEVICE(ACCESSIO, ACCES_COM232_8, acces_com_8x),
		776	EXAR_DEVICE(ACCESSIO, ACCES_COM_2SM, acces_com_2x),
		777	EXAR_DEVICE(ACCESSIO, ACCES_COM_4SM, acces_com_4x),
		778	EXAR_DEVICE(ACCESSIO, ACCES_COM_8SM, acces_com_8x),
		779
		780
748	CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),	781	CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
749	CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),	782	CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
750	CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),	783	CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),

drivers/tty/serial/fsl_lpuart.c+26−15

 	int			rx_dma_rng_buf_len;
 	unsigned int		dma_tx_nents;
 	wait_queue_head_t	dma_wait;
+	bool			id_allocated;
 };
 struct lpuart_soc_data {
 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
+EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
+EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
 #define LPUART_CONSOLE	(&lpuart_console)
 #define LPUART32_CONSOLE	(&lpuart32_console)
 	if (!sport)
 		return -ENOMEM;
-	ret = of_alias_get_id(np, "serial");
-	if (ret < 0) {
-		ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
-		if (ret < 0) {
-			dev_err(&pdev->dev, "port line is full, add device failed\n");
-			return ret;
-		}
-	}
-	if (ret >= ARRAY_SIZE(lpuart_ports)) {
-		dev_err(&pdev->dev, "serial%d out of range\n", ret);
-		return -EINVAL;
-	}
-	sport->port.line = ret;
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(sport->port.membase))
 		}
 	}
+	ret = of_alias_get_id(np, "serial");
+	if (ret < 0) {
+		ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "port line is full, add device failed\n");
+			return ret;
+		}
+		sport->id_allocated = true;
+	}
+	if (ret >= ARRAY_SIZE(lpuart_ports)) {
+		dev_err(&pdev->dev, "serial%d out of range\n", ret);
+		ret = -EINVAL;
+		goto failed_out_of_range;
+	}
+	sport->port.line = ret;
 	ret = lpuart_enable_clks(sport);
 	if (ret)
-		return ret;
+		goto failed_clock_enable;
 	sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
 	lpuart_ports[sport->port.line] = sport;
 failed_attach_port:
 failed_irq_request:
 	lpuart_disable_clks(sport);
+failed_clock_enable:
+failed_out_of_range:
+	if (sport->id_allocated)
+		ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
 	return ret;
 }
 	uart_remove_one_port(&lpuart_reg, &sport->port);
-	ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
+	if (sport->id_allocated)
+		ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
 	lpuart_disable_clks(sport);

drivers/tty/serial/mvebu-uart.c+1−1

@@ -851,7 +851,7 @@ static int mvebu_uart_probe(struct platform_device *pdev) · 850 unmodified lines
851		851
852	port->membase = devm_ioremap_resource(&pdev->dev, reg);	852	port->membase = devm_ioremap_resource(&pdev->dev, reg);
853	if (IS_ERR(port->membase))	853	if (IS_ERR(port->membase))
854	return -PTR_ERR(port->membase);	854	return PTR_ERR(port->membase);
855		855
856	mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),	856	mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
857	GFP_KERNEL);	857	GFP_KERNEL);

drivers/tty/tty_io.c+6−8

 	tty_debug_hangup(tty, "freeing structure\n");
 	/*
 	 * The release_tty function takes care of the details of clearing
-	 * the slots and preserving the termios structure. The tty_unlock_pair
+	 * the slots and preserving the termios structure.
-	 * should be safe as we keep a kref while the tty is locked (so the
-	 * unlock never unlocks a freed tty).
 	 */
 	mutex_lock(&tty_mutex);
 	tty_port_set_kopened(tty->port, 0);
 	tty_debug_hangup(tty, "freeing structure\n");
 	/*
 	 * The release_tty function takes care of the details of clearing
-	 * the slots and preserving the termios structure. The tty_unlock_pair
+	 * the slots and preserving the termios structure.
-	 * should be safe as we keep a kref while the tty is locked (so the
-	 * unlock never unlocks a freed tty).
 	 */
 	mutex_lock(&tty_mutex);
 	release_tty(tty, idx);
 	struct serial_struct32 v32;
 	struct serial_struct v;
 	int err;
-	memset(&v, 0, sizeof(struct serial_struct));
-	if (!tty->ops->set_serial)
+	memset(&v, 0, sizeof(v));
+	memset(&v32, 0, sizeof(v32));
+	if (!tty->ops->get_serial)
 		return -ENOTTY;
 	err = tty->ops->get_serial(tty, &v);
 	if (!err) {

drivers/tty/vt/selection.c+18−9

@@ -181,7 +181,7 @@ int set_selection_user(const struct tiocl_selection __user *sel, · 180 unmodified lines
181	return set_selection_kernel(&v, tty);	181	return set_selection_kernel(&v, tty);
182	}	182	}
183		183
184	int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty)	184	static int __set_selection_kernel(struct tiocl_selection v, struct tty_struct tty)
185	{	185	{
186	struct vc_data *vc = vc_cons[fg_console].d;	186	struct vc_data *vc = vc_cons[fg_console].d;
187	int new_sel_start, new_sel_end, spc;	187	int new_sel_start, new_sel_end, spc;
@@ -214,7 +214,6 @@ int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty) · 26 unmodified lines
214	if (ps > pe) /* make sel_start <= sel_end */	214	if (ps > pe) /* make sel_start <= sel_end */
215	swap(ps, pe);	215	swap(ps, pe);
216		216
217	mutex_lock(&sel_lock);
218	if (sel_cons != vc_cons[fg_console].d) {	217	if (sel_cons != vc_cons[fg_console].d) {
219	clear_selection();	218	clear_selection();
220	sel_cons = vc_cons[fg_console].d;	219	sel_cons = vc_cons[fg_console].d;
@@ -260,10 +259,9 @@ int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty) · 39 unmodified lines
260	break;	259	break;
261	case TIOCL_SELPOINTER:	260	case TIOCL_SELPOINTER:
262	highlight_pointer(pe);	261	highlight_pointer(pe);
263	goto unlock;	262	return 0;
264	default:	263	default:
265	ret = -EINVAL;	264	return -EINVAL;
266	goto unlock;
267	}	265	}
268		266
269	/* remove the pointer */	267	/* remove the pointer */
@@ -285,7 +283,7 @@ int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty) · 15 unmodified lines
285	else if (new_sel_start == sel_start)	283	else if (new_sel_start == sel_start)
286	{	284	{
287	if (new_sel_end == sel_end) /* no action required */	285	if (new_sel_end == sel_end) /* no action required */
288	goto unlock;	286	return 0;
289	else if (new_sel_end > sel_end) /* extend to right */	287	else if (new_sel_end > sel_end) /* extend to right */
290	highlight(sel_end + 2, new_sel_end);	288	highlight(sel_end + 2, new_sel_end);
291	else /* contract from right */	289	else /* contract from right */
@@ -313,8 +311,7 @@ int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty) · 21 unmodified lines
313	if (!bp) {	311	if (!bp) {
314	printk(KERN_WARNING "selection: kmalloc() failed\n");	312	printk(KERN_WARNING "selection: kmalloc() failed\n");
315	clear_selection();	313	clear_selection();
316	ret = -ENOMEM;	314	return -ENOMEM;
317	goto unlock;
318	}	315	}
319	kfree(sel_buffer);	316	kfree(sel_buffer);
320	sel_buffer = bp;	317	sel_buffer = bp;
@@ -339,8 +336,20 @@ int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty) · 18 unmodified lines
339	}	336	}
340	}	337	}
341	sel_buffer_lth = bp - sel_buffer;	338	sel_buffer_lth = bp - sel_buffer;
342	unlock:	339
		340	return ret;
		341	}
		342
		343	int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty)
		344	{
		345	int ret;
		346
		347	mutex_lock(&sel_lock);
		348	console_lock();
		349	ret = __set_selection_kernel(v, tty);
		350	console_unlock();
343	mutex_unlock(&sel_lock);	351	mutex_unlock(&sel_lock);
		352
344	return ret;	353	return ret;
345	}	354	}
346	EXPORT_SYMBOL_GPL(set_selection_kernel);	355	EXPORT_SYMBOL_GPL(set_selection_kernel);

drivers/tty/vt/vt.c+0−2

 	switch (type)
 	{
 		case TIOCL_SETSEL:
-			console_lock();
 			ret = set_selection_user((struct tiocl_selection
 						 __user *)(p+1), tty);
-			console_unlock();
 			break;
 		case TIOCL_PASTESEL:
 			ret = paste_selection(tty);

drivers/usb/cdns3/gadget.c+15−4

 	/* Update ring only if removed request is on pending_req_list list */
 	if (req_on_hw_ring) {
 		link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma +
-					      (priv_req->start_trb * TRB_SIZE));
+			((priv_req->end_trb + 1) * TRB_SIZE));
 		link_trb->control = (link_trb->control & TRB_CYCLE) |
 				    TRB_TYPE(TRB_LINK) | TRB_CHAIN;
 {
 	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
 	struct usb_request *request;
+	struct cdns3_request *priv_req;
+	struct cdns3_trb *trb = NULL;
 	int ret;
 	int val;
 	trace_cdns3_halt(priv_ep, 0, 0);
+	request = cdns3_next_request(&priv_ep->pending_req_list);
+	if (request) {
+		priv_req = to_cdns3_request(request);
+		trb = priv_req->trb;
+		if (trb)
+			trb->control = trb->control ^ TRB_CYCLE;
+	}

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@@ -435,13 +435,13 @@ cpuid_feature_extract_signed_field(u64 features, int field) · 434 unmodified lines
435	return cpuid_feature_extract_signed_field_width(features, field, 4);	435	return cpuid_feature_extract_signed_field_width(features, field, 4);
436	}	436	}
437		437
438	static inline unsigned int __attribute_const__	438	static __always_inline unsigned int __attribute_const__
439	cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)	439	cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
440	{	440	{
441	return (u64)(features << (64 - width - field)) >> (64 - width);	441	return (u64)(features << (64 - width - field)) >> (64 - width);
442	}	442	}
443		443
444	static inline unsigned int __attribute_const__	444	static __always_inline unsigned int __attribute_const__
445	cpuid_feature_extract_unsigned_field(u64 features, int field)	445	cpuid_feature_extract_unsigned_field(u64 features, int field)
446	{	446	{
447	return cpuid_feature_extract_unsigned_field_width(features, field, 4);	447	return cpuid_feature_extract_unsigned_field_width(features, field, 4);
@@ -564,7 +564,7 @@ static inline bool system_supports_mixed_endian(void) · 116 unmodified lines
564	return val == 0x1;	564	return val == 0x1;
565	}	565	}
566		566
567	static inline bool system_supports_fpsimd(void)	567	static __always_inline bool system_supports_fpsimd(void)
568	{	568	{
569	return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD);	569	return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD);
570	}	570	}
@@ -575,13 +575,13 @@ static inline bool system_uses_ttbr0_pan(void) · 4 unmodified lines
575	!cpus_have_const_cap(ARM64_HAS_PAN);	575	!cpus_have_const_cap(ARM64_HAS_PAN);
576	}	576	}
577		577
578	static inline bool system_supports_sve(void)	578	static __always_inline bool system_supports_sve(void)
579	{	579	{
580	return IS_ENABLED(CONFIG_ARM64_SVE) &&	580	return IS_ENABLED(CONFIG_ARM64_SVE) &&
581	cpus_have_const_cap(ARM64_SVE);	581	cpus_have_const_cap(ARM64_SVE);
582	}	582	}
583		583
584	static inline bool system_supports_cnp(void)	584	static __always_inline bool system_supports_cnp(void)
585	{	585	{
586	return IS_ENABLED(CONFIG_ARM64_CNP) &&	586	return IS_ENABLED(CONFIG_ARM64_CNP) &&
587	cpus_have_const_cap(ARM64_HAS_CNP);	587	cpus_have_const_cap(ARM64_HAS_CNP);

@@ -36,7 +36,7 @@ void kvm_inject_undef32(struct kvm_vcpu *vcpu); · 35 unmodified lines
36	void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);	36	void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);
37	void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);	37	void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);
38		38
39	static inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)	39	static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
40	{	40	{
41	return !(vcpu->arch.hcr_el2 & HCR_RW);	41	return !(vcpu->arch.hcr_el2 & HCR_RW);
42	}	42	}
@@ -127,7 +127,7 @@ static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr) · 84 unmodified lines
127	vcpu->arch.vsesr_el2 = vsesr;	127	vcpu->arch.vsesr_el2 = vsesr;
128	}	128	}
129		129
130	static inline unsigned long vcpu_pc(const struct kvm_vcpu vcpu)	130	static __always_inline unsigned long vcpu_pc(const struct kvm_vcpu vcpu)
131	{	131	{
132	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;	132	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;
133	}	133	}
@@ -153,17 +153,17 @@ static inline void vcpu_write_elr_el1(const struct kvm_vcpu *vcpu, unsigned long · 19 unmodified lines
153	*__vcpu_elr_el1(vcpu) = v;	153	*__vcpu_elr_el1(vcpu) = v;
154	}	154	}
155		155
156	static inline unsigned long vcpu_cpsr(const struct kvm_vcpu vcpu)	156	static __always_inline unsigned long vcpu_cpsr(const struct kvm_vcpu vcpu)
157	{	157	{
158	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;	158	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
159	}	159	}
160		160
161	static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)	161	static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
162	{	162	{
163	return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);	163	return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
164	}	164	}
165		165
166	static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)	166	static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
167	{	167	{
168	if (vcpu_mode_is_32bit(vcpu))	168	if (vcpu_mode_is_32bit(vcpu))
169	return kvm_condition_valid32(vcpu);	169	return kvm_condition_valid32(vcpu);
@@ -181,13 +181,13 @@ static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu) · 11 unmodified lines
181	* coming from a read of ESR_EL2. Otherwise, it may give the wrong result on	181	* coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
182	* AArch32 with banked registers.	182	* AArch32 with banked registers.
183	*/	183	*/
184	static inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,	184	static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
185	u8 reg_num)	185	u8 reg_num)
186	{	186	{
187	return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num];	187	return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num];
188	}	188	}
189		189
190	static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,	190	static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
191	unsigned long val)	191	unsigned long val)
192	{	192	{
193	if (reg_num != 31)	193	if (reg_num != 31)
@@ -264,12 +264,12 @@ static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) · 70 unmodified lines
264	return mode != PSR_MODE_EL0t;	264	return mode != PSR_MODE_EL0t;
265	}	265	}
266		266
267	static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)	267	static __always_inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
268	{	268	{
269	return vcpu->arch.fault.esr_el2;	269	return vcpu->arch.fault.esr_el2;
270	}	270	}
271		271
272	static inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)	272	static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
273	{	273	{
274	u32 esr = kvm_vcpu_get_hsr(vcpu);	274	u32 esr = kvm_vcpu_get_hsr(vcpu);
275		275
@@ -279,12 +279,12 @@ static inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu) · 3 unmodified lines
279	return -1;	279	return -1;
280	}	280	}
281		281
282	static inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)	282	static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
283	{	283	{
284	return vcpu->arch.fault.far_el2;	284	return vcpu->arch.fault.far_el2;
285	}	285	}
286		286
287	static inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)	287	static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
288	{	288	{
289	return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;	289	return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
290	}	290	}
@@ -299,7 +299,7 @@ static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu) · 8 unmodified lines
299	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_xVC_IMM_MASK;	299	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_xVC_IMM_MASK;
300	}	300	}
301		301
302	static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)	302	static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
303	{	303	{
304	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);	304	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);
305	}	305	}
@@ -319,17 +319,17 @@ static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu) · 13 unmodified lines
319	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SF);	319	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SF);
320	}	320	}
321		321
322	static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)	322	static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
323	{	323	{
324	return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;	324	return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
325	}	325	}
326		326
327	static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)	327	static __always_inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
328	{	328	{
329	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);	329	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);
330	}	330	}
331		331
332	static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)	332	static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
333	{	333	{
334	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) \|\|	334	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) \|\|
335	kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */	335	kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */
@@ -340,18 +340,18 @@ static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu) · 4 unmodified lines
340	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM);	340	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM);
341	}	341	}
342		342
343	static inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)	343	static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
344	{	344	{
345	return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);	345	return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
346	}	346	}
347		347
348	/* This one is not specific to Data Abort */	348	/* This one is not specific to Data Abort */
349	static inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)	349	static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
350	{	350	{
351	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL);	351	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL);
352	}	352	}
353		353
354	static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)	354	static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
355	{	355	{
356	return ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu));	356	return ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu));
357	}	357	}
@@ -361,17 +361,17 @@ static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu) · 3 unmodified lines
361	return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;	361	return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
362	}	362	}
363		363
364	static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)	364	static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
365	{	365	{
366	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC;	366	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC;
367	}	367	}
368		368
369	static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)	369	static __always_inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
370	{	370	{
371	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;	371	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;
372	}	372	}
373		373
374	static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)	374	static __always_inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
375	{	375	{
376	switch (kvm_vcpu_trap_get_fault(vcpu)) {	376	switch (kvm_vcpu_trap_get_fault(vcpu)) {
377	case FSC_SEA:	377	case FSC_SEA:
@@ -390,7 +390,7 @@ static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu) · 12 unmodified lines
390	}	390	}
391	}	391	}
392		392
393	static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)	393	static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
394	{	394	{
395	u32 esr = kvm_vcpu_get_hsr(vcpu);	395	u32 esr = kvm_vcpu_get_hsr(vcpu);
396	return ESR_ELx_SYS64_ISS_RT(esr);	396	return ESR_ELx_SYS64_ISS_RT(esr);
@@ -504,7 +504,7 @@ static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu, · 107 unmodified lines
504	return data; /* Leave LE untouched */	504	return data; /* Leave LE untouched */
505	}	505	}
506		506
507	static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)	507	static __always_inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
508	{	508	{
509	if (vcpu_mode_is_32bit(vcpu))	509	if (vcpu_mode_is_32bit(vcpu))
510	kvm_skip_instr32(vcpu, is_wide_instr);	510	kvm_skip_instr32(vcpu, is_wide_instr);
@@ -519,7 +519,7 @@ static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr) · 8 unmodified lines
519	* Skip an instruction which has been emulated at hyp while most guest sysregs	519	* Skip an instruction which has been emulated at hyp while most guest sysregs
520	* are live.	520	* are live.
521	*/	521	*/
522	static inline void __hyp_text __kvm_skip_instr(struct kvm_vcpu *vcpu)	522	static __always_inline void __hyp_text __kvm_skip_instr(struct kvm_vcpu *vcpu)
523	{	523	{
524	*vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);	524	*vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
525	vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(SYS_SPSR);	525	vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(SYS_SPSR);

@@ -1104,7 +1104,6 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) · 1103 unmodified lines
1104	pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;	1104	pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
1105	pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;	1105	pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
1106	pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;	1106	pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
1107	pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent;
1108	pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;	1107	pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
1109	pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;	1108	pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
1110	pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;	1109	pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
@@ -1118,7 +1117,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) · 7 unmodified lines
1118	if (!chip->irq.parent_domain)	1117	if (!chip->irq.parent_domain)
1119	return -EPROBE_DEFER;	1118	return -EPROBE_DEFER;
1120	chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;	1119	chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
1121		1120	pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent;
1122	/*	1121	/*
1123	* Let's skip handling the GPIOs, if the parent irqchip	1122	* Let's skip handling the GPIOs, if the parent irqchip
1124	* is handling the direct connect IRQ of the GPIO.	1123	* is handling the direct connect IRQ of the GPIO.