Merge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile

Pull clk patches from Brian Masney: - New clock controller drivers for the Cix Sky1 audio subsystem (AUDSS), UltraRISC DP1000, and MediaTek MT8173 MFG_TOP, along with their devicetree bindings. Si549 support was added to the existing si544 driver. - New clock and reset support for the Aspeed AST2700 PECI controller and Airoha EN7523 PCIe PERSTOUT reset lines. - The clk core gains devm_clk_bulk_get_enable() as the mandatory counterpart to the existing optional variant, and exports devm_clk_hw_register_composite_pdata() for modular drivers. - Tegra gets a proper EMC clock implementation for Tegra114, 48MHz pll_p_out1 support needed for UEFI on Surface2, and the Xilinx clocking-wizard gains PLL charge pump/lock parameter programming during dynamic reconfiguration. - Bug fixes for a NULL pointer dereference from uninitialized clk_init_data in the eswin driver, an IO remap leak in the MediaTek pllfh error path, inverted gate control for MT8135 devapc_ck, a missing OF node put in tegra124-emc on registration failure, a prepare reference leak in the palmas driver, unregistered PLLs on MT6735 probe failure, a missing kasprintf NULL check in pmc_atom, PCIe warm boot instability in the Airoha EN7523 driver, and a clocking-wizard clock difference detection bug. - Various cleanups across tegra, st, and mvebu providers to stop misusing the consumer clock API, along with other minor fixes and improvements. Signed-off-by: Brian Masney <bmasney@redhat.com> * tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux: (45 commits) clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 clk: aspeed: add AST2700 PECI clock dt-bindings: clock: ast2700: add PECI clock clk: mediatek: Add mt8173-mfgtop driver dt-bindings: clock: mediatek: Add mt8173 mfgtop clk: tegra: clean-up simple provider misuse of the consumer API clk: st: clean-up simple provider misuse of the consumer API clk: mvebu: clean-up simple provider misuse of the consumer API clk: remove conditional return with no effect clk: Add devm_clk_bulk_get_enable() clk: en7523: add support for dedicated PCIe PERSTOUT reset dt-bindings: clock: airoha: Add additional reset for PCIe PERSTOUT arm64: dts: cix: sky1: add audss cru reset: cix: add sky1 audss auxiliary reset driver ...

Stephen Boyd committed 3 months ago

Commit df822f22 parents 804b10d cf5612856 files · +3063 −151Browse files

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include/dt-bindings/clock/aspeed,ast2700-scu.h +2 −0
include/dt-bindings/clock/cix,sky1-audss-cru.h +60 −0
include/dt-bindings/clock/mt8173-clk.h +7 −0
include/dt-bindings/clock/ultrarisc,dp1000-clk.h +27 −0
include/dt-bindings/reset/airoha,en7581-reset.h +4 −0
include/dt-bindings/reset/cix,sky1-audss-cru.h +25 −0
include/linux/clk.h +25 −2

include/dt-bindings/clock/aspeed,ast2700-scu.h+2−0

@@ -163,5 +163,7 @@ · 162 unmodified lines
163	163	#define SCU1_CLK_GATE_PORTDUSB2CLK 85
164	164	#define SCU1_CLK_GATE_LTPI1TXCLK 86
165	165	#define SCU1_CLK_I3C 87
	166	+#define SCU1_CLK_HPLL_DIV4 88
	167	+#define SCU1_CLK_PECI 89
166	168
167	169	#endif

include/dt-bindings/clock/cix,sky1-audss-cru.h+60−0

@@ -0,0 +1,60 @@
	1	+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
	2	+/*
	3	+ * Copyright 2026 Cix Technology Group Co., Ltd.
	4	+ */
	5	+
	6	+#ifndef _DT_BINDINGS_CLOCK_CIX_SKY1_AUDSS_CRU_H
	7	+#define _DT_BINDINGS_CLOCK_CIX_SKY1_AUDSS_CRU_H
	8	+
	9	+#define CLK_AUD_CLK4_DIV2 0
	10	+#define CLK_AUD_CLK4_DIV4 1
	11	+#define CLK_AUD_CLK5_DIV2 2
	12	+
	13	+#define CLK_DSP_CLK 3
	14	+#define CLK_DSP_BCLK 4
	15	+#define CLK_DSP_PBCLK 5
	16	+
	17	+#define CLK_SRAM_AXI 6
	18	+
	19	+#define CLK_HDA_SYS 7
	20	+#define CLK_HDA_HDA 8
	21	+
	22	+#define CLK_DMAC_AXI 9
	23	+
	24	+#define CLK_WDG_APB 10
	25	+#define CLK_WDG_WDG 11
	26	+
	27	+#define CLK_TIMER_APB 12
	28	+#define CLK_TIMER_TIMER 13
	29	+
	30	+#define CLK_MB_0_APB 14 /* MB0: ap->dsp */
	31	+#define CLK_MB_1_APB 15 /* MB1: dsp->ap */
	32	+
	33	+#define CLK_I2S0_APB 16
	34	+#define CLK_I2S1_APB 17
	35	+#define CLK_I2S2_APB 18
	36	+#define CLK_I2S3_APB 19
	37	+#define CLK_I2S4_APB 20
	38	+#define CLK_I2S5_APB 21
	39	+#define CLK_I2S6_APB 22
	40	+#define CLK_I2S7_APB 23
	41	+#define CLK_I2S8_APB 24
	42	+#define CLK_I2S9_APB 25
	43	+#define CLK_I2S0 26
	44	+#define CLK_I2S1 27
	45	+#define CLK_I2S2 28
	46	+#define CLK_I2S3 29
	47	+#define CLK_I2S4 30
	48	+#define CLK_I2S5 31
	49	+#define CLK_I2S6 32
	50	+#define CLK_I2S7 33
	51	+#define CLK_I2S8 34
	52	+#define CLK_I2S9 35
	53	+
	54	+#define CLK_MCLK0 36
	55	+#define CLK_MCLK1 37
	56	+#define CLK_MCLK2 38
	57	+#define CLK_MCLK3 39
	58	+#define CLK_MCLK4 40
	59	+
	60	+#endif

include/dt-bindings/clock/mt8173-clk.h+7−0

@@ -243,6 +243,13 @@ · 242 unmodified lines
243	243	#define CLK_IMG_FD 7
244	244	#define CLK_IMG_NR_CLK 8
245	245
	246	+/* MFG_SYS */
	247	+
	248	+#define CLK_MFG_AXI 0
	249	+#define CLK_MFG_MEM 1
	250	+#define CLK_MFG_G3D 2
	251	+#define CLK_MFG_26M 3
	252	+
246	253	/* MM_SYS */
247	254
248	255	#define CLK_MM_SMI_COMMON 1

include/dt-bindings/clock/ultrarisc,dp1000-clk.h+27−0

@@ -0,0 +1,27 @@
	1	+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
	2	+#ifndef _DT_BINDINGS_CLOCK_ULTRARISC_DP1000_CLK_H
	3	+#define _DT_BINDINGS_CLOCK_ULTRARISC_DP1000_CLK_H
	4	+
	5	+#define DP1000_CLK_SYSPLL 0
	6	+#define DP1000_CLK_SYSPLL_DIV2 1
	7	+#define DP1000_CLK_SUBSYS 2
	8	+#define DP1000_CLK_GMAC 3
	9	+#define DP1000_CLK_UART_ROOT 4
	10	+#define DP1000_CLK_I2C_ROOT 5
	11	+#define DP1000_CLK_SPI_ROOT 6
	12	+#define DP1000_CLK_PCIE_DBI 7
	13	+#define DP1000_CLK_PCIEX4_CORE 8
	14	+#define DP1000_CLK_PCIEX16_CORE 9
	15	+#define DP1000_CLK_PCIE_AUX 10
	16	+#define DP1000_CLK_UART0 11
	17	+#define DP1000_CLK_UART1 12
	18	+#define DP1000_CLK_UART2 13
	19	+#define DP1000_CLK_UART3 14
	20	+#define DP1000_CLK_I2C0 15
	21	+#define DP1000_CLK_I2C1 16
	22	+#define DP1000_CLK_I2C2 17
	23	+#define DP1000_CLK_I2C3 18
	24	+#define DP1000_CLK_SPI0 19
	25	+#define DP1000_CLK_SPI1 20
	26	+
	27	+#endif /* _DT_BINDINGS_CLOCK_ULTRARISC_DP1000_CLK_H */

include/dt-bindings/reset/airoha,en7581-reset.h+4−0

@@ -62,5 +62,9 @@ · 61 unmodified lines
62	62	#define EN7581_CPU_TIMER_RST 50
63	63	#define EN7581_PCIE_HB_RST 51
64	64	#define EN7581_XPON_MAC_RST 52
	65	+/* RST_PCIC */
	66	+#define EN7581_PCIC_PERSTOUT0_RST 53
	67	+#define EN7581_PCIC_PERSTOUT1_RST 54
	68	+#define EN7581_PCIC_PERSTOUT2_RST 55
65	69
66	70	#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */

include/dt-bindings/reset/cix,sky1-audss-cru.h+25−0

@@ -0,0 +1,25 @@
	1	+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
	2	+/*
	3	+ * Copyright 2026 Cix Technology Group Co., Ltd.
	4	+ */
	5	+#ifndef DT_BINDINGS_RESET_CIX_SKY1_AUDSS_CRU_H
	6	+#define DT_BINDINGS_RESET_CIX_SKY1_AUDSS_CRU_H
	7	+
	8	+#define AUDSS_I2S0_SW_RST 0
	9	+#define AUDSS_I2S1_SW_RST 1
	10	+#define AUDSS_I2S2_SW_RST 2
	11	+#define AUDSS_I2S3_SW_RST 3
	12	+#define AUDSS_I2S4_SW_RST 4
	13	+#define AUDSS_I2S5_SW_RST 5
	14	+#define AUDSS_I2S6_SW_RST 6
	15	+#define AUDSS_I2S7_SW_RST 7
	16	+#define AUDSS_I2S8_SW_RST 8
	17	+#define AUDSS_I2S9_SW_RST 9
	18	+#define AUDSS_WDT_SW_RST 10
	19	+#define AUDSS_TIMER_SW_RST 11
	20	+#define AUDSS_MB0_SW_RST 12
	21	+#define AUDSS_MB1_SW_RST 13
	22	+#define AUDSS_HDA_SW_RST 14
	23	+#define AUDSS_DMAC_SW_RST 15
	24	+
	25	+#endif

include/linux/clk.h+25−2

@@ -502,6 +502,22 @@ int __must_check devm_clk_bulk_get(struct device *dev, int num_clks, · 501 unmodified lines
502	502	*/
503	503	int __must_check devm_clk_bulk_get_optional(struct device *dev, int num_clks,
504	504	struct clk_bulk_data *clks);
	505	+/**
	506	+ * devm_clk_bulk_get_enable - Get and enable bulk clocks (managed)
	507	+ * @dev: device for clock "consumer"
	508	+ * @num_clks: the number of clk_bulk_data
	509	+ * @clks: pointer to the clk_bulk_data table of consumer
	510	+ *
	511	+ * Behaves the same as devm_clk_bulk_get() but also prepares and enables the
	512	+ * clocks in one operation with management. The clks will automatically be
	513	+ * disabled, unprepared and freed when the device is unbound.
	514	+ *
	515	+ * Return: 0 if all clocks specified in clk_bulk_data table are obtained and
	516	+ * enabled successfully. Otherwise returns valid IS_ERR() condition containing
	517	+ * errno.
	518	+ */
	519	+int __must_check devm_clk_bulk_get_enable(struct device *dev, int num_clks,
	520	+ struct clk_bulk_data *clks);
505	521	/**
506	522	* devm_clk_bulk_get_optional_enable - Get and enable optional bulk clocks (managed)
507	523	* @dev: device for clock "consumer"
@@ -951,8 +967,8 @@ int clk_set_parent(struct clk clk, struct clk parent); · 443 unmodified lines
951	967	* clk_get_parent - get the parent clock source for this clock
952	968	* @clk: clock source
953	969	*
954		− * Returns struct clk corresponding to parent clock source, or
955		− * valid IS_ERR() condition containing errno.
	970	+ * Returns struct clk corresponding to parent clock source, or NULL
	971	+ * if clk is NULL.
956	972	*/
957	973	struct clk clk_get_parent(struct clk clk);
958	974
@@ -1052,6 +1068,13 @@ static inline int __must_check devm_clk_bulk_get_optional(struct device *dev, · 93 unmodified lines
1052	1068	return 0;
1053	1069	}
1054	1070
	1071	+static inline int __must_check devm_clk_bulk_get_enable(struct device *dev,
	1072	+ int num_clks,
	1073	+ struct clk_bulk_data *clks)
	1074	+{
	1075	+ return 0;
	1076	+}
	1077	+
1055	1078	static inline int __must_check devm_clk_bulk_get_optional_enable(struct device *dev,
1056	1079	int num_clks,
1057	1080	struct clk_bulk_data *clks)

Merge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile

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