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phy: qualcomm: qcom-uniphy-pcie 28LP add support for IPQ5018

The Qualcomm UNIPHY PCIe PHY 28LP is found on both IPQ5332 and IPQ5018. Adding the PHY init sequence, pipe clock rate, and compatible for IPQ5018.

Nitheesh Sekar committed 1 year ago

Commit dfc820d1 parent aae29081 file · +45 −0Browse files

Unified · Split

drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c+45−0
@@ -75,6 +75,40 @@ struct qcom_uniphy_pcie { · 74 unmodified lines
75 75
76#define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy)76#define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy)
77 77
78static const struct qcom_uniphy_pcie_regs ipq5018_regs[] = {
79 {
80 .offset = SSCG_CTRL_REG_4,
81 .val = 0x1cb9,
82 }, {
83 .offset = SSCG_CTRL_REG_5,
84 .val = 0x023a,
85 }, {
86 .offset = SSCG_CTRL_REG_3,
87 .val = 0xd360,
88 }, {
89 .offset = SSCG_CTRL_REG_1,
90 .val = 0x1,
91 }, {
92 .offset = SSCG_CTRL_REG_2,
93 .val = 0xeb,
94 }, {
95 .offset = CDR_CTRL_REG_4,
96 .val = 0x3f9,
97 }, {
98 .offset = CDR_CTRL_REG_5,
99 .val = 0x1c9,
100 }, {
101 .offset = CDR_CTRL_REG_2,
102 .val = 0x419,
103 }, {
104 .offset = CDR_CTRL_REG_1,
105 .val = 0x200,
106 }, {
107 .offset = PCS_INTERNAL_CONTROL_2,
108 .val = 0xf101,
109 },
110};
111
78static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = {112static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = {
79 {113 {
80 .offset = PHY_CFG_PLLCFG,114 .offset = PHY_CFG_PLLCFG,
@@ -88,6 +122,14 @@ static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = { · 7 unmodified lines
88 },122 },
89};123};
90 124
125static const struct qcom_uniphy_pcie_data ipq5018_data = {
126 .lane_offset = 0x800,
127 .phy_type = PHY_TYPE_PCIE_GEN2,
128 .init_seq = ipq5018_regs,
129 .init_seq_num = ARRAY_SIZE(ipq5018_regs),
130 .pipe_clk_rate = 125 * MEGA,
131};
132
91static const struct qcom_uniphy_pcie_data ipq5332_data = {133static const struct qcom_uniphy_pcie_data ipq5332_data = {
92 .lane_offset = 0x800,134 .lane_offset = 0x800,
93 .phy_type = PHY_TYPE_PCIE_GEN3,135 .phy_type = PHY_TYPE_PCIE_GEN3,
@@ -212,6 +254,9 @@ static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, int id) · 118 unmodified lines
212 254
213static const struct of_device_id qcom_uniphy_pcie_id_table[] = {255static const struct of_device_id qcom_uniphy_pcie_id_table[] = {
214 {256 {
257 .compatible = "qcom,ipq5018-uniphy-pcie-phy",
258 .data = &ipq5018_data,
259 }, {
215 .compatible = "qcom,ipq5332-uniphy-pcie-phy",260 .compatible = "qcom,ipq5332-uniphy-pcie-phy",
216 .data = &ipq5332_data,261 .data = &ipq5332_data,
217 }, {262 }, {