Merge tag 'renesas-fixes-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes

Renesas fixes for v5.14 - Fix a clock/reset handling design issue on the new RZ/G2L SoC, requiring an atomic change to DT binding definitions, clock driver, and DTS, - Restore graphical consoles in the shmobile_defconfig. * tag 'renesas-fixes-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: ARM: shmobile: defconfig: Restore graphical consoles dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions clk: renesas: r9a07g044: Add P2 Clock support clk: renesas: r9a07g044: Fix P1 Clock clk: renesas: r9a07g044: Rename divider table clk: renesas: rzg2l: Add multi clock PM support

Arnd Bergmann committed 5 years ago

Commit e0129a02 parents b6e473d 432b52e6 files · +320 −147Browse files

Unified · Split

6 files

arch/arm/configs/shmobile_defconfig +1 −0
arch/arm64/boot/dts/renesas/r9a07g044.dtsi +2 −2
drivers/clk/renesas/r9a07g044-cpg.c +47 −32
drivers/clk/renesas/renesas-rzg2l-cpg.c +59 −51
drivers/clk/renesas/renesas-rzg2l-cpg.h +28 −9
include/dt-bindings/clock/r9a07g044-cpg.h +183 −53

arch/arm/configs/shmobile_defconfig+1−0

@@ -135,6 +135,7 @@ CONFIG_DRM_SII902X=y · 134 unmodified lines
135	135	CONFIG_DRM_SIMPLE_BRIDGE=y
136	136	CONFIG_DRM_I2C_ADV7511=y
137	137	CONFIG_DRM_I2C_ADV7511_AUDIO=y
	138	+CONFIG_FB=y
138	139	CONFIG_FB_SH_MOBILE_LCDC=y
139	140	CONFIG_BACKLIGHT_PWM=y
140	141	CONFIG_BACKLIGHT_AS3711=y

arch/arm64/boot/dts/renesas/r9a07g044.dtsi+2−2

@@ -82,10 +82,10 @@ · 81 unmodified lines
82	82	<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
83	83	interrupt-names = "eri", "rxi", "txi",
84	84	"bri", "dri", "tei";
85		− clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>;
	85	+ clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
86	86	clock-names = "fck";
87	87	power-domains = <&cpg>;
88		− resets = <&cpg R9A07G044_CLK_SCIF0>;
	88	+ resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
89	89	status = "disabled";
90	90	};
91	91

drivers/clk/renesas/r9a07g044-cpg.c+47−32

@@ -30,8 +30,9 @@ enum clk_ids { · 29 unmodified lines
30	30	CLK_PLL2_DIV20,
31	31	CLK_PLL3,
32	32	CLK_PLL3_DIV2,
	33	+ CLK_PLL3_DIV2_4,
	34	+ CLK_PLL3_DIV2_4_2,
33	35	CLK_PLL3_DIV4,
34		− CLK_PLL3_DIV8,
35	36	CLK_PLL4,
36	37	CLK_PLL5,
37	38	CLK_PLL5_DIV2,
@@ -42,12 +43,13 @@ enum clk_ids { · 4 unmodified lines
42	43	};
43	44
44	45	/* Divider tables */
45		−static const struct clk_div_table dtable_3b[] = {
	46	+static const struct clk_div_table dtable_1_32[] = {
46	47	{0, 1},
47	48	{1, 2},
48	49	{2, 4},
49	50	{3, 8},
50	51	{4, 32},
	52	+ {0, 0},
51	53	};
52	54
53	55	static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
@@ -66,47 +68,56 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { · 12 unmodified lines
66	68	DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
67	69
68	70	DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
	71	+ DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
	72	+ DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
69	73	DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
70		− DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8),
71	74
72	75	/* Core output clk */
73	76	DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
74	77	DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
75		− dtable_3b, CLK_DIVIDER_HIWORD_MASK),
	78	+ dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
76	79	DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
77		− DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
78		− DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK),
	80	+ DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
	81	+ DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
	82	+ DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
	83	+ DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
79	84	};
80	85
81	86	static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
82		− DEF_MOD("gic", R9A07G044_CLK_GIC600,
83		− R9A07G044_CLK_P1,
84		− 0x514, BIT(0), (BIT(0) \| BIT(1))),
85		− DEF_MOD("ia55", R9A07G044_CLK_IA55,
86		− R9A07G044_CLK_P1,
87		− 0x518, (BIT(0) \| BIT(1)), BIT(0)),
88		− DEF_MOD("scif0", R9A07G044_CLK_SCIF0,
89		− R9A07G044_CLK_P0,
90		− 0x584, BIT(0), BIT(0)),
91		− DEF_MOD("scif1", R9A07G044_CLK_SCIF1,
92		− R9A07G044_CLK_P0,
93		− 0x584, BIT(1), BIT(1)),
94		− DEF_MOD("scif2", R9A07G044_CLK_SCIF2,
95		− R9A07G044_CLK_P0,
96		− 0x584, BIT(2), BIT(2)),
97		− DEF_MOD("scif3", R9A07G044_CLK_SCIF3,
98		− R9A07G044_CLK_P0,
99		− 0x584, BIT(3), BIT(3)),
100		− DEF_MOD("scif4", R9A07G044_CLK_SCIF4,
101		− R9A07G044_CLK_P0,
102		− 0x584, BIT(4), BIT(4)),
103		− DEF_MOD("sci0", R9A07G044_CLK_SCI0,
104		− R9A07G044_CLK_P0,
105		− 0x588, BIT(0), BIT(0)),
	87	+ DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
	88	+ 0x514, 0),
	89	+ DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
	90	+ 0x518, 0),
	91	+ DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
	92	+ 0x518, 1),
	93	+ DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
	94	+ 0x584, 0),
	95	+ DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
	96	+ 0x584, 1),
	97	+ DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
	98	+ 0x584, 2),
	99	+ DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
	100	+ 0x584, 3),
	101	+ DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
	102	+ 0x584, 4),
	103	+ DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
	104	+ 0x588, 0),
	105	+};
	106	+
	107	+static struct rzg2l_reset r9a07g044_resets[] = {
	108	+ DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
	109	+ DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
	110	+ DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
	111	+ DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
	112	+ DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
	113	+ DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
	114	+ DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
	115	+ DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
	116	+ DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
106	117	};
107	118
108	119	static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
109		− MOD_CLK_BASE + R9A07G044_CLK_GIC600,
	120	+ MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
110	121	};
111	122
112	123	const struct rzg2l_cpg_info r9a07g044_cpg_info = {
@@ -123,5 +134,9 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { · 10 unmodified lines
123	134	/* Module Clocks */
124	135	.mod_clks = r9a07g044_mod_clks,
125	136	.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
126		− .num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1,
	137	+ .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
	138	+
	139	+ /* Resets */
	140	+ .resets = r9a07g044_resets,
	141	+ .num_resets = ARRAY_SIZE(r9a07g044_resets),
127	142	};

drivers/clk/renesas/renesas-rzg2l-cpg.c+59−51

@@ -47,9 +47,9 @@ · 46 unmodified lines
47	47	#define SDIV(val) DIV_RSMASK(val, 0, 0x7)
48	48
49	49	#define CLK_ON_R(reg) (reg)
50		−#define CLK_MON_R(reg) (0x680 - 0x500 + (reg))
51		−#define CLK_RST_R(reg) (0x800 - 0x500 + (reg))
52		−#define CLK_MRST_R(reg) (0x980 - 0x500 + (reg))
	50	+#define CLK_MON_R(reg) (0x180 + (reg))
	51	+#define CLK_RST_R(reg) (reg)
	52	+#define CLK_MRST_R(reg) (0x180 + (reg))
53	53
54	54	#define GET_REG_OFFSET(val) ((val >> 20) & 0xfff)
55	55	#define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff)
@@ -78,6 +78,7 @@ struct rzg2l_cpg_priv { · 22 unmodified lines
78	78	struct clk **clks;
79	79	unsigned int num_core_clks;
80	80	unsigned int num_mod_clks;
	81	+ unsigned int num_resets;
81	82	unsigned int last_dt_core_clk;
82	83
83	84	struct raw_notifier_head notifiers;
@@ -315,15 +316,13 @@ fail: · 231 unmodified lines
315	316	*
316	317	* @hw: handle between common and hardware-specific interfaces
317	318	* @off: register offset
318		− * @onoff: ON/MON bits
319		− * @reset: reset bits
	319	+ * @bit: ON/MON bit
320	320	* @priv: CPG/MSTP private data
321	321	*/
322	322	struct mstp_clock {
323	323	struct clk_hw hw;
324	324	u16 off;
325		− u8 onoff;
326		− u8 reset;
	325	+ u8 bit;
327	326	struct rzg2l_cpg_priv *priv;
328	327	};
329	328
@@ -337,6 +336,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) · 7 unmodified lines
337	336	struct device *dev = priv->dev;
338	337	unsigned long flags;
339	338	unsigned int i;
	339	+ u32 bitmask = BIT(clock->bit);
340	340	u32 value;
341	341
342	342	if (!clock->off) {
@@ -349,9 +349,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) · 6 unmodified lines
349	349	spin_lock_irqsave(&priv->rmw_lock, flags);
350	350
351	351	if (enable)
352		− value = (clock->onoff << 16) \| clock->onoff;
	352	+ value = (bitmask << 16) \| bitmask;
353	353	else
354		− value = clock->onoff << 16;
	354	+ value = bitmask << 16;
355	355	writel(value, priv->base + CLK_ON_R(reg));
356	356
357	357	spin_unlock_irqrestore(&priv->rmw_lock, flags);
@@ -360,7 +360,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) · 2 unmodified lines
360	360	return 0;
361	361
362	362	for (i = 1000; i > 0; --i) {
363		− if (((readl(priv->base + CLK_MON_R(reg))) & clock->onoff))
	363	+ if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
364	364	break;
365	365	cpu_relax();
366	366	}
@@ -388,6 +388,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw) · 21 unmodified lines
388	388	{
389	389	struct mstp_clock *clock = to_mod_clock(hw);
390	390	struct rzg2l_cpg_priv *priv = clock->priv;
	391	+ u32 bitmask = BIT(clock->bit);
391	392	u32 value;
392	393
393	394	if (!clock->off) {
@@ -397,7 +398,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw) · 3 unmodified lines
397	398
398	399	value = readl(priv->base + CLK_MON_R(clock->off));
399	400
400		− return !(value & clock->onoff);
	401	+ return !(value & bitmask);
401	402	}
402	403
403	404	static const struct clk_ops rzg2l_mod_clock_ops = {
@@ -457,8 +458,7 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, · 53 unmodified lines
457	458	init.num_parents = 1;
458	459
459	460	clock->off = mod->off;
460		− clock->onoff = mod->onoff;
461		− clock->reset = mod->reset;
	461	+ clock->bit = mod->bit;
462	462	clock->priv = priv;
463	463	clock->hw.init = &init;
464	464
@@ -483,12 +483,11 @@ static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, · 18 unmodified lines
483	483	{
484	484	struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
485	485	const struct rzg2l_cpg_info *info = priv->info;
486		− unsigned int reg = info->mod_clks[id].off;
487		− u32 dis = info->mod_clks[id].reset;
	486	+ unsigned int reg = info->resets[id].off;
	487	+ u32 dis = BIT(info->resets[id].bit);
488	488	u32 we = dis << 16;
489	489
490		− dev_dbg(rcdev->dev, "reset name:%s id:%ld offset:0x%x\n",
491		− info->mod_clks[id].name, id, CLK_RST_R(reg));
	490	+ dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
492	491
493	492	/* Reset module */
494	493	writel(we, priv->base + CLK_RST_R(reg));
@@ -507,11 +506,10 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev, · 12 unmodified lines
507	506	{
508	507	struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
509	508	const struct rzg2l_cpg_info *info = priv->info;
510		− unsigned int reg = info->mod_clks[id].off;
511		− u32 value = info->mod_clks[id].reset << 16;
	509	+ unsigned int reg = info->resets[id].off;
	510	+ u32 value = BIT(info->resets[id].bit) << 16;
512	511
513		− dev_dbg(rcdev->dev, "assert name:%s id:%ld offset:0x%x\n",
514		− info->mod_clks[id].name, id, CLK_RST_R(reg));
	512	+ dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
515	513
516	514	writel(value, priv->base + CLK_RST_R(reg));
517	515	return 0;
@@ -522,12 +520,12 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, · 4 unmodified lines
522	520	{
523	521	struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
524	522	const struct rzg2l_cpg_info *info = priv->info;
525		− unsigned int reg = info->mod_clks[id].off;
526		− u32 dis = info->mod_clks[id].reset;
	523	+ unsigned int reg = info->resets[id].off;
	524	+ u32 dis = BIT(info->resets[id].bit);
527	525	u32 value = (dis << 16) \| dis;
528	526
529		− dev_dbg(rcdev->dev, "deassert name:%s id:%ld offset:0x%x\n",
530		− info->mod_clks[id].name, id, CLK_RST_R(reg));
	527	+ dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id,
	528	+ CLK_RST_R(reg));
531	529
532	530	writel(value, priv->base + CLK_RST_R(reg));
533	531	return 0;
@@ -538,8 +536,8 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, · 4 unmodified lines
538	536	{
539	537	struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
540	538	const struct rzg2l_cpg_info *info = priv->info;
541		− unsigned int reg = info->mod_clks[id].off;
542		− u32 bitmask = info->mod_clks[id].reset;
	539	+ unsigned int reg = info->resets[id].off;
	540	+ u32 bitmask = BIT(info->resets[id].bit);
543	541
544	542	return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
545	543	}
@@ -554,9 +552,11 @@ static const struct reset_control_ops rzg2l_cpg_reset_ops = { · 8 unmodified lines
554	552	static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev,
555	553	const struct of_phandle_args *reset_spec)
556	554	{
	555	+ struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
	556	+ const struct rzg2l_cpg_info *info = priv->info;
557	557	unsigned int id = reset_spec->args[0];
558	558
559		− if (id >= rcdev->nr_resets) {
	559	+ if (id >= rcdev->nr_resets \|\| !info->resets[id].off) {
560	560	dev_err(rcdev->dev, "Invalid reset index %u\n", id);
561	561	return -EINVAL;
562	562	}
@@ -571,7 +571,7 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv) · 8 unmodified lines
571	571	priv->rcdev.dev = priv->dev;
572	572	priv->rcdev.of_reset_n_cells = 1;
573	573	priv->rcdev.of_xlate = rzg2l_cpg_reset_xlate;
574		− priv->rcdev.nr_resets = priv->num_mod_clks;
	574	+ priv->rcdev.nr_resets = priv->num_resets;
575	575
576	576	return devm_reset_controller_register(priv->dev, &priv->rcdev);
577	577	}
@@ -594,42 +594,49 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device · 16 unmodified lines
594	594	{
595	595	struct device_node *np = dev->of_node;
596	596	struct of_phandle_args clkspec;
	597	+ bool once = true;
597	598	struct clk *clk;
598	599	int error;
599	600	int i = 0;
600	601
601	602	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
602	603	&clkspec)) {
603		− if (rzg2l_cpg_is_pm_clk(&clkspec))
604		− goto found;
605		−
606		− of_node_put(clkspec.np);
	604	+ if (rzg2l_cpg_is_pm_clk(&clkspec)) {
	605	+ if (once) {
	606	+ once = false;
	607	+ error = pm_clk_create(dev);
	608	+ if (error) {
	609	+ of_node_put(clkspec.np);
	610	+ goto err;
	611	+ }
	612	+ }
	613	+ clk = of_clk_get_from_provider(&clkspec);
	614	+ of_node_put(clkspec.np);
	615	+ if (IS_ERR(clk)) {
	616	+ error = PTR_ERR(clk);
	617	+ goto fail_destroy;
	618	+ }
	619	+
	620	+ error = pm_clk_add_clk(dev, clk);
	621	+ if (error) {
	622	+ dev_err(dev, "pm_clk_add_clk failed %d\n",
	623	+ error);
	624	+ goto fail_put;
	625	+ }
	626	+ } else {
	627	+ of_node_put(clkspec.np);
	628	+ }
607	629	i++;
608	630	}
609	631
610	632	return 0;
611	633
612		−found:
613		− clk = of_clk_get_from_provider(&clkspec);
614		− of_node_put(clkspec.np);
615		−
616		− if (IS_ERR(clk))
617		− return PTR_ERR(clk);
618		−
619		− error = pm_clk_create(dev);
620		− if (error)
621		− goto fail_put;
622		−
623		− error = pm_clk_add_clk(dev, clk);
624		− if (error)
625		− goto fail_destroy;
626		−
627		− return 0;
	634	+fail_put:
	635	+ clk_put(clk);
628	636
629	637	fail_destroy:
630	638	pm_clk_destroy(dev);
631		−fail_put:
632		− clk_put(clk);
	639	+err:
633	640	return error;
634	641	}
635	642
@@ -692,6 +699,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev) · 56 unmodified lines
692	699	priv->clks = clks;
693	700	priv->num_core_clks = info->num_total_core_clks;
694	701	priv->num_mod_clks = info->num_hw_mod_clks;
	702	+ priv->num_resets = info->num_resets;
695	703	priv->last_dt_core_clk = info->last_dt_core_clk;
696	704
697	705	for (i = 0; i < nclks; i++)

drivers/clk/renesas/renesas-rzg2l-cpg.h+28−9

@@ -21,6 +21,7 @@ · 20 unmodified lines
21	21	#define DDIV_PACK(offset, bitpos, size) \
22	22	(((offset) << 20) \| ((bitpos) << 12) \| ((size) << 8))
23	23	#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
	24	+#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
24	25	#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
25	26
26	27	/**
@@ -76,26 +77,40 @@ enum clk_types { · 49 unmodified lines
76	77	* @id: clock index in array containing all Core and Module Clocks
77	78	* @parent: id of parent clock
78	79	* @off: register offset
79		− * @onoff: ON/MON bits
80		− * @reset: reset bits
	80	+ * @bit: ON/MON bit
81	81	*/
82	82	struct rzg2l_mod_clk {
83	83	const char *name;
84	84	unsigned int id;
85	85	unsigned int parent;
86	86	u16 off;
87		− u8 onoff;
88		− u8 reset;
	87	+ u8 bit;
89	88	};
90	89
91		−#define DEF_MOD(_name, _id, _parent, _off, _onoff, _reset) \
92		− [_id] = { \
	90	+#define DEF_MOD(_name, _id, _parent, _off, _bit) \
	91	+ { \
93	92	.name = _name, \
94		− .id = MOD_CLK_BASE + _id, \
	93	+ .id = MOD_CLK_BASE + (_id), \
95	94	.parent = (_parent), \
96	95	.off = (_off), \
97		− .onoff = (_onoff), \
98		− .reset = (_reset) \
	96	+ .bit = (_bit), \
	97	+ }
	98	+
	99	+/**
	100	+ * struct rzg2l_reset - Reset definitions
	101	+ *
	102	+ * @off: register offset
	103	+ * @bit: reset bit
	104	+ */
	105	+struct rzg2l_reset {
	106	+ u16 off;
	107	+ u8 bit;
	108	+};
	109	+
	110	+#define DEF_RST(_id, _off, _bit) \
	111	+ [_id] = { \
	112	+ .off = (_off), \
	113	+ .bit = (_bit) \
99	114	}
100	115
101	116	/**
@@ -126,6 +141,10 @@ struct rzg2l_cpg_info { · 24 unmodified lines
126	141	unsigned int num_mod_clks;
127	142	unsigned int num_hw_mod_clks;
128	143
	144	+ /* Resets */
	145	+ const struct rzg2l_reset *resets;
	146	+ unsigned int num_resets;
	147	+
129	148	/* Critical Module Clocks that should not be disabled */
130	149	const unsigned int *crit_mod_clks;
131	150	unsigned int num_crit_mod_clks;

include/dt-bindings/clock/r9a07g044-cpg.h+183−53

@@ -32,58 +32,188 @@ · 31 unmodified lines
32	32	#define R9A07G044_OSCCLK 21
33	33
34	34	/* R9A07G044 Module Clocks */
35		−#define R9A07G044_CLK_GIC600 0
36		−#define R9A07G044_CLK_IA55 1
37		−#define R9A07G044_CLK_SYC 2
38		−#define R9A07G044_CLK_DMAC 3
39		−#define R9A07G044_CLK_SYSC 4
40		−#define R9A07G044_CLK_MTU 5
41		−#define R9A07G044_CLK_GPT 6
42		−#define R9A07G044_CLK_ETH0 7
43		−#define R9A07G044_CLK_ETH1 8
44		−#define R9A07G044_CLK_I2C0 9
45		−#define R9A07G044_CLK_I2C1 10
46		−#define R9A07G044_CLK_I2C2 11
47		−#define R9A07G044_CLK_I2C3 12
48		−#define R9A07G044_CLK_SCIF0 13
49		−#define R9A07G044_CLK_SCIF1 14
50		−#define R9A07G044_CLK_SCIF2 15
51		−#define R9A07G044_CLK_SCIF3 16
52		−#define R9A07G044_CLK_SCIF4 17
53		−#define R9A07G044_CLK_SCI0 18
54		−#define R9A07G044_CLK_SCI1 19
55		−#define R9A07G044_CLK_GPIO 20
56		−#define R9A07G044_CLK_SDHI0 21
57		−#define R9A07G044_CLK_SDHI1 22
58		−#define R9A07G044_CLK_USB0 23
59		−#define R9A07G044_CLK_USB1 24
60		−#define R9A07G044_CLK_CANFD 25
61		−#define R9A07G044_CLK_SSI0 26
62		−#define R9A07G044_CLK_SSI1 27
63		−#define R9A07G044_CLK_SSI2 28
64		−#define R9A07G044_CLK_SSI3 29
65		−#define R9A07G044_CLK_MHU 30
66		−#define R9A07G044_CLK_OSTM0 31
67		−#define R9A07G044_CLK_OSTM1 32
68		−#define R9A07G044_CLK_OSTM2 33
69		−#define R9A07G044_CLK_WDT0 34
70		−#define R9A07G044_CLK_WDT1 35
71		−#define R9A07G044_CLK_WDT2 36
72		−#define R9A07G044_CLK_WDT_PON 37
73		−#define R9A07G044_CLK_GPU 38
74		−#define R9A07G044_CLK_ISU 39
75		−#define R9A07G044_CLK_H264 40
76		−#define R9A07G044_CLK_CRU 41
77		−#define R9A07G044_CLK_MIPI_DSI 42
78		−#define R9A07G044_CLK_LCDC 43
79		−#define R9A07G044_CLK_SRC 44
80		−#define R9A07G044_CLK_RSPI0 45
81		−#define R9A07G044_CLK_RSPI1 46
82		−#define R9A07G044_CLK_RSPI2 47
83		−#define R9A07G044_CLK_ADC 48
84		−#define R9A07G044_CLK_TSU_PCLK 49
85		−#define R9A07G044_CLK_SPI 50
86		−#define R9A07G044_CLK_MIPI_DSI_V 51
87		−#define R9A07G044_CLK_MIPI_DSI_PIN 52
	35	+#define R9A07G044_CA55_SCLK 0
	36	+#define R9A07G044_CA55_PCLK 1
	37	+#define R9A07G044_CA55_ATCLK 2
	38	+#define R9A07G044_CA55_GICCLK 3
	39	+#define R9A07G044_CA55_PERICLK 4
	40	+#define R9A07G044_CA55_ACLK 5
	41	+#define R9A07G044_CA55_TSCLK 6
	42	+#define R9A07G044_GIC600_GICCLK 7
	43	+#define R9A07G044_IA55_CLK 8
	44	+#define R9A07G044_IA55_PCLK 9
	45	+#define R9A07G044_MHU_PCLK 10
	46	+#define R9A07G044_SYC_CNT_CLK 11
	47	+#define R9A07G044_DMAC_ACLK 12
	48	+#define R9A07G044_DMAC_PCLK 13
	49	+#define R9A07G044_OSTM0_PCLK 14
	50	+#define R9A07G044_OSTM1_PCLK 15
	51	+#define R9A07G044_OSTM2_PCLK 16
	52	+#define R9A07G044_MTU_X_MCK_MTU3 17
	53	+#define R9A07G044_POE3_CLKM_POE 18
	54	+#define R9A07G044_GPT_PCLK 19
	55	+#define R9A07G044_POEG_A_CLKP 20
	56	+#define R9A07G044_POEG_B_CLKP 21
	57	+#define R9A07G044_POEG_C_CLKP 22
	58	+#define R9A07G044_POEG_D_CLKP 23
	59	+#define R9A07G044_WDT0_PCLK 24
	60	+#define R9A07G044_WDT0_CLK 25
	61	+#define R9A07G044_WDT1_PCLK 26
	62	+#define R9A07G044_WDT1_CLK 27
	63	+#define R9A07G044_WDT2_PCLK 28
	64	+#define R9A07G044_WDT2_CLK 29
	65	+#define R9A07G044_SPI_CLK2 30
	66	+#define R9A07G044_SPI_CLK 31
	67	+#define R9A07G044_SDHI0_IMCLK 32
	68	+#define R9A07G044_SDHI0_IMCLK2 33
	69	+#define R9A07G044_SDHI0_CLK_HS 34
	70	+#define R9A07G044_SDHI0_ACLK 35
	71	+#define R9A07G044_SDHI1_IMCLK 36
	72	+#define R9A07G044_SDHI1_IMCLK2 37
	73	+#define R9A07G044_SDHI1_CLK_HS 38
	74	+#define R9A07G044_SDHI1_ACLK 39
	75	+#define R9A07G044_GPU_CLK 40
	76	+#define R9A07G044_GPU_AXI_CLK 41
	77	+#define R9A07G044_GPU_ACE_CLK 42
	78	+#define R9A07G044_ISU_ACLK 43
	79	+#define R9A07G044_ISU_PCLK 44
	80	+#define R9A07G044_H264_CLK_A 45
	81	+#define R9A07G044_H264_CLK_P 46
	82	+#define R9A07G044_CRU_SYSCLK 47
	83	+#define R9A07G044_CRU_VCLK 48
	84	+#define R9A07G044_CRU_PCLK 49
	85	+#define R9A07G044_CRU_ACLK 50
	86	+#define R9A07G044_MIPI_DSI_PLLCLK 51
	87	+#define R9A07G044_MIPI_DSI_SYSCLK 52
	88	+#define R9A07G044_MIPI_DSI_ACLK 53
	89	+#define R9A07G044_MIPI_DSI_PCLK 54
	90	+#define R9A07G044_MIPI_DSI_VCLK 55
	91	+#define R9A07G044_MIPI_DSI_LPCLK 56
	92	+#define R9A07G044_LCDC_CLK_A 57
	93	+#define R9A07G044_LCDC_CLK_P 58
	94	+#define R9A07G044_LCDC_CLK_D 59
	95	+#define R9A07G044_SSI0_PCLK2 60
	96	+#define R9A07G044_SSI0_PCLK_SFR 61
	97	+#define R9A07G044_SSI1_PCLK2 62
	98	+#define R9A07G044_SSI1_PCLK_SFR 63
	99	+#define R9A07G044_SSI2_PCLK2 64
	100	+#define R9A07G044_SSI2_PCLK_SFR 65
	101	+#define R9A07G044_SSI3_PCLK2 66
	102	+#define R9A07G044_SSI3_PCLK_SFR 67
	103	+#define R9A07G044_SRC_CLKP 68
	104	+#define R9A07G044_USB_U2H0_HCLK 69
	105	+#define R9A07G044_USB_U2H1_HCLK 70
	106	+#define R9A07G044_USB_U2P_EXR_CPUCLK 71
	107	+#define R9A07G044_USB_PCLK 72
	108	+#define R9A07G044_ETH0_CLK_AXI 73
	109	+#define R9A07G044_ETH0_CLK_CHI 74
	110	+#define R9A07G044_ETH1_CLK_AXI 75
	111	+#define R9A07G044_ETH1_CLK_CHI 76
	112	+#define R9A07G044_I2C0_PCLK 77
	113	+#define R9A07G044_I2C1_PCLK 78
	114	+#define R9A07G044_I2C2_PCLK 79
	115	+#define R9A07G044_I2C3_PCLK 80
	116	+#define R9A07G044_SCIF0_CLK_PCK 81
	117	+#define R9A07G044_SCIF1_CLK_PCK 82
	118	+#define R9A07G044_SCIF2_CLK_PCK 83
	119	+#define R9A07G044_SCIF3_CLK_PCK 84
	120	+#define R9A07G044_SCIF4_CLK_PCK 85
	121	+#define R9A07G044_SCI0_CLKP 86
	122	+#define R9A07G044_SCI1_CLKP 87
	123	+#define R9A07G044_IRDA_CLKP 88
	124	+#define R9A07G044_RSPI0_CLKB 89
	125	+#define R9A07G044_RSPI1_CLKB 90
	126	+#define R9A07G044_RSPI2_CLKB 91
	127	+#define R9A07G044_CANFD_PCLK 92
	128	+#define R9A07G044_GPIO_HCLK 93
	129	+#define R9A07G044_ADC_ADCLK 94
	130	+#define R9A07G044_ADC_PCLK 95
	131	+#define R9A07G044_TSU_PCLK 96
	132	+
	133	+/* R9A07G044 Resets */
	134	+#define R9A07G044_CA55_RST_1_0 0
	135	+#define R9A07G044_CA55_RST_1_1 1
	136	+#define R9A07G044_CA55_RST_3_0 2
	137	+#define R9A07G044_CA55_RST_3_1 3
	138	+#define R9A07G044_CA55_RST_4 4
	139	+#define R9A07G044_CA55_RST_5 5
	140	+#define R9A07G044_CA55_RST_6 6
	141	+#define R9A07G044_CA55_RST_7 7
	142	+#define R9A07G044_CA55_RST_8 8
	143	+#define R9A07G044_CA55_RST_9 9
	144	+#define R9A07G044_CA55_RST_10 10
	145	+#define R9A07G044_CA55_RST_11 11
	146	+#define R9A07G044_CA55_RST_12 12
	147	+#define R9A07G044_GIC600_GICRESET_N 13
	148	+#define R9A07G044_GIC600_DBG_GICRESET_N 14
	149	+#define R9A07G044_IA55_RESETN 15
	150	+#define R9A07G044_MHU_RESETN 16
	151	+#define R9A07G044_DMAC_ARESETN 17
	152	+#define R9A07G044_DMAC_RST_ASYNC 18
	153	+#define R9A07G044_SYC_RESETN 19
	154	+#define R9A07G044_OSTM0_PRESETZ 20
	155	+#define R9A07G044_OSTM1_PRESETZ 21
	156	+#define R9A07G044_OSTM2_PRESETZ 22
	157	+#define R9A07G044_MTU_X_PRESET_MTU3 23
	158	+#define R9A07G044_POE3_RST_M_REG 24
	159	+#define R9A07G044_GPT_RST_C 25
	160	+#define R9A07G044_POEG_A_RST 26
	161	+#define R9A07G044_POEG_B_RST 27
	162	+#define R9A07G044_POEG_C_RST 28
	163	+#define R9A07G044_POEG_D_RST 29
	164	+#define R9A07G044_WDT0_PRESETN 30
	165	+#define R9A07G044_WDT1_PRESETN 31
	166	+#define R9A07G044_WDT2_PRESETN 32
	167	+#define R9A07G044_SPI_RST 33
	168	+#define R9A07G044_SDHI0_IXRST 34
	169	+#define R9A07G044_SDHI1_IXRST 35
	170	+#define R9A07G044_GPU_RESETN 36
	171	+#define R9A07G044_GPU_AXI_RESETN 37
	172	+#define R9A07G044_GPU_ACE_RESETN 38
	173	+#define R9A07G044_ISU_ARESETN 39
	174	+#define R9A07G044_ISU_PRESETN 40
	175	+#define R9A07G044_H264_X_RESET_VCP 41
	176	+#define R9A07G044_H264_CP_PRESET_P 42
	177	+#define R9A07G044_CRU_CMN_RSTB 43
	178	+#define R9A07G044_CRU_PRESETN 44
	179	+#define R9A07G044_CRU_ARESETN 45
	180	+#define R9A07G044_MIPI_DSI_CMN_RSTB 46
	181	+#define R9A07G044_MIPI_DSI_ARESET_N 47
	182	+#define R9A07G044_MIPI_DSI_PRESET_N 48
	183	+#define R9A07G044_LCDC_RESET_N 49
	184	+#define R9A07G044_SSI0_RST_M2_REG 50
	185	+#define R9A07G044_SSI1_RST_M2_REG 51
	186	+#define R9A07G044_SSI2_RST_M2_REG 52
	187	+#define R9A07G044_SSI3_RST_M2_REG 53
	188	+#define R9A07G044_SRC_RST 54
	189	+#define R9A07G044_USB_U2H0_HRESETN 55
	190	+#define R9A07G044_USB_U2H1_HRESETN 56
	191	+#define R9A07G044_USB_U2P_EXL_SYSRST 57
	192	+#define R9A07G044_USB_PRESETN 58
	193	+#define R9A07G044_ETH0_RST_HW_N 59
	194	+#define R9A07G044_ETH1_RST_HW_N 60
	195	+#define R9A07G044_I2C0_MRST 61
	196	+#define R9A07G044_I2C1_MRST 62
	197	+#define R9A07G044_I2C2_MRST 63
	198	+#define R9A07G044_I2C3_MRST 64
	199	+#define R9A07G044_SCIF0_RST_SYSTEM_N 65
	200	+#define R9A07G044_SCIF1_RST_SYSTEM_N 66
	201	+#define R9A07G044_SCIF2_RST_SYSTEM_N 67
	202	+#define R9A07G044_SCIF3_RST_SYSTEM_N 68
	203	+#define R9A07G044_SCIF4_RST_SYSTEM_N 69
	204	+#define R9A07G044_SCI0_RST 70
	205	+#define R9A07G044_SCI1_RST 71
	206	+#define R9A07G044_IRDA_RST 72
	207	+#define R9A07G044_RSPI0_RST 73
	208	+#define R9A07G044_RSPI1_RST 74
	209	+#define R9A07G044_RSPI2_RST 75
	210	+#define R9A07G044_CANFD_RSTP_N 76
	211	+#define R9A07G044_CANFD_RSTC_N 77
	212	+#define R9A07G044_GPIO_RSTN 78
	213	+#define R9A07G044_GPIO_PORT_RESETN 79
	214	+#define R9A07G044_GPIO_SPARE_RESETN 80
	215	+#define R9A07G044_ADC_PRESETN 81
	216	+#define R9A07G044_ADC_ADRST_N 82
	217	+#define R9A07G044_TSU_PRESETN 83
88	218
89	219	#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */

Merge tag 'renesas-fixes-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes

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