Merge tag 'char-misc-5.11-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver fixes from Greg KH: "Here are some small char and misc driver fixes for 5.11-rc3. The majority here are fixes for the habanalabs drivers, but also in here are: - crypto driver fix - pvpanic driver fix - updated font file - interconnect driver fixes All of these have been in linux-next for a while with no reported issues" * tag 'char-misc-5.11-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (26 commits) Fonts: font_ter16x32: Update font with new upstream Terminus release misc: pvpanic: Check devm_ioport_map() for NULL speakup: Add github repository URL and bug tracker MAINTAINERS: Update Georgi's email address crypto: asym_tpm: correct zero out potential secrets habanalabs: Fix memleak in hl_device_reset interconnect: imx8mq: Use icc_sync_state interconnect: imx: Remove a useless test interconnect: imx: Add a missing of_node_put after of_device_is_available interconnect: qcom: fix rpmh link failures habanalabs: fix order of status check habanalabs: register to pci shutdown callback habanalabs: add validation cs counter, fix misplaced counters habanalabs/gaudi: retry loading TPC f/w on -EINTR habanalabs: adjust pci controller init to new firmware habanalabs: update comment in hl_boot_if.h habanalabs/gaudi: enhance reset message habanalabs: full FW hard reset support habanalabs/gaudi: disable CGM at HW initialization habanalabs: Revise comment to align with mirror list name ...

Linus Torvalds committed 5 years ago

Commit e07cd2f2 parents 0653161 384b77f21 files · +322 −217Browse files

Unified · Split

21 files

MAINTAINERS +3 −1
crypto/asymmetric_keys/asym_tpm.c +1 −1
drivers/interconnect/imx/imx.c +2 −1
drivers/interconnect/imx/imx8mq.c +2 −0
drivers/interconnect/qcom/Kconfig +15 −8
drivers/misc/habanalabs/common/command_submission.c +58 −19
drivers/misc/habanalabs/common/device.c +5 −3
drivers/misc/habanalabs/common/firmware_if.c +44 −16
drivers/misc/habanalabs/common/habanalabs.h +3 −1
drivers/misc/habanalabs/common/habanalabs_drv.c +1 −0
drivers/misc/habanalabs/common/habanalabs_ioctl.c +6 −1
drivers/misc/habanalabs/common/hw_queue.c +4 −1
drivers/misc/habanalabs/common/pci.c +17 −11
drivers/misc/habanalabs/gaudi/gaudi.c +83 −108
drivers/misc/habanalabs/gaudi/gaudiP.h +0 −7
drivers/misc/habanalabs/gaudi/gaudi_coresight.c +2 −1
drivers/misc/habanalabs/goya/goya.c +45 −30
drivers/misc/habanalabs/include/common/hl_boot_if.h +8 −1
drivers/misc/pvpanic.c +15 −4
include/uapi/misc/habanalabs.h +5 −0
lib/fonts/font_ter16x32.c +3 −3

MAINTAINERS+3−1

@@ -9240,7 +9240,7 @@ F: tools/testing/selftests/sgx/* · 9239 unmodified lines
9240	9240	K: \bSGX_
9241	9241
9242	9242	INTERCONNECT API
9243		−M: Georgi Djakov <georgi.djakov@linaro.org>
	9243	+M: Georgi Djakov <djakov@kernel.org>
9244	9244	L: linux-pm@vger.kernel.org
9245	9245	S: Maintained
9246	9246	F: Documentation/devicetree/bindings/interconnect/
@@ -16709,6 +16709,8 @@ M: Samuel Thibault <samuel.thibault@ens-lyon.org> · 7462 unmodified lines
16709	16709	L: speakup@linux-speakup.org
16710	16710	S: Odd Fixes
16711	16711	W: http://www.linux-speakup.org/
	16712	+W: https://github.com/linux-speakup/speakup
	16713	+B: https://github.com/linux-speakup/speakup/issues
16712	16714	F: drivers/accessibility/speakup/
16713	16715
16714	16716	SPEAR CLOCK FRAMEWORK SUPPORT

crypto/asymmetric_keys/asym_tpm.c+1−1

@@ -354,7 +354,7 @@ static uint32_t derive_pub_key(const void pub_key, uint32_t len, uint8_t buf) · 353 unmodified lines
354	354	memcpy(cur, e, sizeof(e));
355	355	cur += sizeof(e);
356	356	/* Zero parameters to satisfy set_pub_key ABI. */
357		− memset(cur, 0, SETKEY_PARAMS_SIZE);
	357	+ memzero_explicit(cur, SETKEY_PARAMS_SIZE);
358	358
359	359	return cur - buf;
360	360	}

drivers/interconnect/imx/imx.c+2−1

@@ -96,9 +96,10 @@ static int imx_icc_node_init_qos(struct icc_provider *provider, · 95 unmodified lines
96	96	return -ENODEV;
97	97	}
98	98	/* Allow scaling to be disabled on a per-node basis */
99		− if (!dn \|\| !of_device_is_available(dn)) {
	99	+ if (!of_device_is_available(dn)) {
100	100	dev_warn(dev, "Missing property %s, skip scaling %s\n",
101	101	adj->phandle_name, node->name);
	102	+ of_node_put(dn);
102	103	return 0;
103	104	}
104	105

drivers/interconnect/imx/imx8mq.c+2−0

@@ -7,6 +7,7 @@ · 6 unmodified lines
7	7
8	8	#include <linux/module.h>
9	9	#include <linux/platform_device.h>
	10	+#include <linux/interconnect-provider.h>
10	11	#include <dt-bindings/interconnect/imx8mq.h>
11	12
12	13	#include "imx.h"
@@ -94,6 +95,7 @@ static struct platform_driver imx8mq_icc_driver = { · 81 unmodified lines
94	95	.remove = imx8mq_icc_remove,
95	96	.driver = {
96	97	.name = "imx8mq-interconnect",
	98	+ .sync_state = icc_sync_state,
97	99	},
98	100	};
99	101

drivers/interconnect/qcom/Kconfig+15−8

@@ -42,13 +42,23 @@ config INTERCONNECT_QCOM_QCS404 · 41 unmodified lines
42	42	This is a driver for the Qualcomm Network-on-Chip on qcs404-based
43	43	platforms.
44	44
	45	+config INTERCONNECT_QCOM_RPMH_POSSIBLE
	46	+ tristate
	47	+ default INTERCONNECT_QCOM
	48	+ depends on QCOM_RPMH \|\| (COMPILE_TEST && !QCOM_RPMH)
	49	+ depends on QCOM_COMMAND_DB \|\| (COMPILE_TEST && !QCOM_COMMAND_DB)
	50	+ depends on OF \|\| COMPILE_TEST
	51	+ help
	52	+ Compile-testing RPMH drivers is possible on other platforms,
	53	+ but in order to avoid link failures, drivers must not be built-in
	54	+ when QCOM_RPMH or QCOM_COMMAND_DB are loadable modules
	55	+
45	56	config INTERCONNECT_QCOM_RPMH
46	57	tristate
47	58
48	59	config INTERCONNECT_QCOM_SC7180
49	60	tristate "Qualcomm SC7180 interconnect driver"
50		− depends on INTERCONNECT_QCOM
51		− depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) \|\| COMPILE_TEST
	61	+ depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
52	62	select INTERCONNECT_QCOM_RPMH
53	63	select INTERCONNECT_QCOM_BCM_VOTER
54	64	help
@@ -57,8 +67,7 @@ config INTERCONNECT_QCOM_SC7180 · 2 unmodified lines
57	67
58	68	config INTERCONNECT_QCOM_SDM845
59	69	tristate "Qualcomm SDM845 interconnect driver"
60		− depends on INTERCONNECT_QCOM
61		− depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) \|\| COMPILE_TEST
	70	+ depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
62	71	select INTERCONNECT_QCOM_RPMH
63	72	select INTERCONNECT_QCOM_BCM_VOTER
64	73	help
@@ -67,8 +76,7 @@ config INTERCONNECT_QCOM_SDM845 · 2 unmodified lines
67	76
68	77	config INTERCONNECT_QCOM_SM8150
69	78	tristate "Qualcomm SM8150 interconnect driver"
70		− depends on INTERCONNECT_QCOM
71		− depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) \|\| COMPILE_TEST
	79	+ depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
72	80	select INTERCONNECT_QCOM_RPMH
73	81	select INTERCONNECT_QCOM_BCM_VOTER
74	82	help
@@ -77,8 +85,7 @@ config INTERCONNECT_QCOM_SM8150 · 2 unmodified lines
77	85
78	86	config INTERCONNECT_QCOM_SM8250
79	87	tristate "Qualcomm SM8250 interconnect driver"
80		− depends on INTERCONNECT_QCOM
81		− depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) \|\| COMPILE_TEST
	88	+ depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
82	89	select INTERCONNECT_QCOM_RPMH
83	90	select INTERCONNECT_QCOM_BCM_VOTER
84	91	help

drivers/misc/habanalabs/common/command_submission.c+58−19

@@ -472,8 +472,11 @@ static int allocate_cs(struct hl_device hdev, struct hl_ctx ctx, · 471 unmodified lines
472	472	cntr = &hdev->aggregated_cs_counters;
473	473
474	474	cs = kzalloc(sizeof(*cs), GFP_ATOMIC);
475		− if (!cs)
	475	+ if (!cs) {
	476	+ atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
	477	+ atomic64_inc(&cntr->out_of_mem_drop_cnt);
476	478	return -ENOMEM;
	479	+ }
477	480
478	481	cs->ctx = ctx;
479	482	cs->submitted = false;
@@ -486,6 +489,8 @@ static int allocate_cs(struct hl_device hdev, struct hl_ctx ctx, · 6 unmodified lines
486	489
487	490	cs_cmpl = kmalloc(sizeof(*cs_cmpl), GFP_ATOMIC);
488	491	if (!cs_cmpl) {
	492	+ atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
	493	+ atomic64_inc(&cntr->out_of_mem_drop_cnt);
489	494	rc = -ENOMEM;
490	495	goto free_cs;
491	496	}
@@ -513,6 +518,8 @@ static int allocate_cs(struct hl_device hdev, struct hl_ctx ctx, · 21 unmodified lines
513	518	cs->jobs_in_queue_cnt = kcalloc(hdev->asic_prop.max_queues,
514	519	sizeof(*cs->jobs_in_queue_cnt), GFP_ATOMIC);
515	520	if (!cs->jobs_in_queue_cnt) {
	521	+ atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
	522	+ atomic64_inc(&cntr->out_of_mem_drop_cnt);
516	523	rc = -ENOMEM;
517	524	goto free_fence;
518	525	}
@@ -562,7 +569,7 @@ void hl_cs_rollback_all(struct hl_device *hdev) · 43 unmodified lines
562	569	for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
563	570	flush_workqueue(hdev->cq_wq[i]);
564	571
565		− /* Make sure we don't have leftovers in the H/W queues mirror list */
	572	+ /* Make sure we don't have leftovers in the CS mirror list */
566	573	list_for_each_entry_safe(cs, tmp, &hdev->cs_mirror_list, mirror_node) {
567	574	cs_get(cs);
568	575	cs->aborted = true;
@@ -764,11 +771,14 @@ static int hl_cs_sanity_checks(struct hl_fpriv hpriv, union hl_cs_args args) · 195 unmodified lines
764	771
765	772	static int hl_cs_copy_chunk_array(struct hl_device *hdev,
766	773	struct hl_cs_chunk **cs_chunk_array,
767		− void __user *chunks, u32 num_chunks)
	774	+ void __user *chunks, u32 num_chunks,
	775	+ struct hl_ctx *ctx)
768	776	{
769	777	u32 size_to_copy;
770	778
771	779	if (num_chunks > HL_MAX_JOBS_PER_CS) {
	780	+ atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
	781	+ atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt);
772	782	dev_err(hdev->dev,
773	783	"Number of chunks can NOT be larger than %d\n",
774	784	HL_MAX_JOBS_PER_CS);
@@ -777,11 +787,16 @@ static int hl_cs_copy_chunk_array(struct hl_device *hdev, · 2 unmodified lines
777	787
778	788	cs_chunk_array = kmalloc_array(num_chunks, sizeof(*cs_chunk_array),
779	789	GFP_ATOMIC);
780		− if (!*cs_chunk_array)
	790	+ if (!*cs_chunk_array) {
	791	+ atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
	792	+ atomic64_inc(&hdev->aggregated_cs_counters.out_of_mem_drop_cnt);
781	793	return -ENOMEM;
	794	+ }
782	795
783	796	size_to_copy = num_chunks * sizeof(struct hl_cs_chunk);
784	797	if (copy_from_user(*cs_chunk_array, chunks, size_to_copy)) {
	798	+ atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
	799	+ atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt);
785	800	dev_err(hdev->dev, "Failed to copy cs chunk array from user\n");
786	801	kfree(*cs_chunk_array);
787	802	return -EFAULT;
@@ -797,6 +812,7 @@ static int cs_ioctl_default(struct hl_fpriv hpriv, void __user chunks, · 9 unmodified lines
797	812	struct hl_device *hdev = hpriv->hdev;
798	813	struct hl_cs_chunk *cs_chunk_array;
799	814	struct hl_cs_counters_atomic *cntr;
	815	+ struct hl_ctx *ctx = hpriv->ctx;
800	816	struct hl_cs_job *job;
801	817	struct hl_cs *cs;
802	818	struct hl_cb *cb;
@@ -805,7 +821,8 @@ static int cs_ioctl_default(struct hl_fpriv hpriv, void __user chunks, · 2 unmodified lines
805	821	cntr = &hdev->aggregated_cs_counters;
806	822	*cs_seq = ULLONG_MAX;
807	823
808		− rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks);
	824	+ rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks,
	825	+ hpriv->ctx);
809	826	if (rc)
810	827	goto out;
811	828
@@ -832,8 +849,8 @@ static int cs_ioctl_default(struct hl_fpriv hpriv, void __user chunks, · 20 unmodified lines
832	849	rc = validate_queue_index(hdev, chunk, &queue_type,
833	850	&is_kernel_allocated_cb);
834	851	if (rc) {
835		− atomic64_inc(&hpriv->ctx->cs_counters.parsing_drop_cnt);
836		− atomic64_inc(&cntr->parsing_drop_cnt);
	852	+ atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
	853	+ atomic64_inc(&cntr->validation_drop_cnt);
837	854	goto free_cs_object;
838	855	}
839	856
@@ -841,8 +858,8 @@ static int cs_ioctl_default(struct hl_fpriv hpriv, void __user chunks, · 1 unmodified line
841	858	cb = get_cb_from_cs_chunk(hdev, &hpriv->cb_mgr, chunk);
842	859	if (!cb) {
843	860	atomic64_inc(
844		− &hpriv->ctx->cs_counters.parsing_drop_cnt);
845		− atomic64_inc(&cntr->parsing_drop_cnt);
	861	+ &ctx->cs_counters.validation_drop_cnt);
	862	+ atomic64_inc(&cntr->validation_drop_cnt);
846	863	rc = -EINVAL;
847	864	goto free_cs_object;
848	865	}
@@ -856,8 +873,7 @@ static int cs_ioctl_default(struct hl_fpriv hpriv, void __user chunks, · 7 unmodified lines
856	873	job = hl_cs_allocate_job(hdev, queue_type,
857	874	is_kernel_allocated_cb);
858	875	if (!job) {
859		− atomic64_inc(
860		− &hpriv->ctx->cs_counters.out_of_mem_drop_cnt);
	876	+ atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
861	877	atomic64_inc(&cntr->out_of_mem_drop_cnt);
862	878	dev_err(hdev->dev, "Failed to allocate a new job\n");
863	879	rc = -ENOMEM;
@@ -891,7 +907,7 @@ static int cs_ioctl_default(struct hl_fpriv hpriv, void __user chunks, · 27 unmodified lines
891	907
892	908	rc = cs_parser(hpriv, job);
893	909	if (rc) {
894		− atomic64_inc(&hpriv->ctx->cs_counters.parsing_drop_cnt);
	910	+ atomic64_inc(&ctx->cs_counters.parsing_drop_cnt);
895	911	atomic64_inc(&cntr->parsing_drop_cnt);
896	912	dev_err(hdev->dev,
897	913	"Failed to parse JOB %d.%llu.%d, err %d, rejecting the CS\n",
@@ -901,8 +917,8 @@ static int cs_ioctl_default(struct hl_fpriv hpriv, void __user chunks, · 3 unmodified lines
901	917	}
902	918
903	919	if (int_queues_only) {
904		− atomic64_inc(&hpriv->ctx->cs_counters.parsing_drop_cnt);
905		− atomic64_inc(&cntr->parsing_drop_cnt);
	920	+ atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
	921	+ atomic64_inc(&cntr->validation_drop_cnt);
906	922	dev_err(hdev->dev,
907	923	"Reject CS %d.%llu because only internal queues jobs are present\n",
908	924	cs->ctx->asid, cs->sequence);
@@ -1042,7 +1058,7 @@ out: · 133 unmodified lines
1042	1058	}
1043	1059
1044	1060	static int cs_ioctl_extract_signal_seq(struct hl_device *hdev,
1045		− struct hl_cs_chunk chunk, u64 signal_seq)
	1061	+ struct hl_cs_chunk chunk, u64 signal_seq, struct hl_ctx *ctx)
1046	1062	{
1047	1063	u64 *signal_seq_arr = NULL;
1048	1064	u32 size_to_copy, signal_seq_arr_len;
@@ -1052,6 +1068,8 @@ static int cs_ioctl_extract_signal_seq(struct hl_device *hdev, · 3 unmodified lines
1052	1068
1053	1069	/* currently only one signal seq is supported */
1054	1070	if (signal_seq_arr_len != 1) {
	1071	+ atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
	1072	+ atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt);
1055	1073	dev_err(hdev->dev,
1056	1074	"Wait for signal CS supports only one signal CS seq\n");
1057	1075	return -EINVAL;
@@ -1060,13 +1078,18 @@ static int cs_ioctl_extract_signal_seq(struct hl_device *hdev, · 2 unmodified lines
1060	1078	signal_seq_arr = kmalloc_array(signal_seq_arr_len,
1061	1079	sizeof(*signal_seq_arr),
1062	1080	GFP_ATOMIC);
1063		− if (!signal_seq_arr)
	1081	+ if (!signal_seq_arr) {
	1082	+ atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
	1083	+ atomic64_inc(&hdev->aggregated_cs_counters.out_of_mem_drop_cnt);
1064	1084	return -ENOMEM;
	1085	+ }
1065	1086
1066	1087	size_to_copy = chunk->num_signal_seq_arr * sizeof(*signal_seq_arr);
1067	1088	if (copy_from_user(signal_seq_arr,
1068	1089	u64_to_user_ptr(chunk->signal_seq_arr),
1069	1090	size_to_copy)) {
	1091	+ atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
	1092	+ atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt);
1070	1093	dev_err(hdev->dev,
1071	1094	"Failed to copy signal seq array from user\n");
1072	1095	rc = -EFAULT;
@@ -1153,6 +1176,7 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, · 80 unmodified lines
1153	1176	struct hl_device *hdev = hpriv->hdev;
1154	1177	struct hl_cs_compl *sig_waitcs_cmpl;
1155	1178	u32 q_idx, collective_engine_id = 0;
	1179	+ struct hl_cs_counters_atomic *cntr;
1156	1180	struct hl_fence *sig_fence = NULL;
1157	1181	struct hl_ctx *ctx = hpriv->ctx;
1158	1182	enum hl_queue_type q_type;
@@ -1160,9 +1184,11 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, · 1 unmodified line
1160	1184	u64 signal_seq;
1161	1185	int rc;
1162	1186
	1187	+ cntr = &hdev->aggregated_cs_counters;
1163	1188	*cs_seq = ULLONG_MAX;
1164	1189
1165		− rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks);
	1190	+ rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks,
	1191	+ ctx);
1166	1192	if (rc)
1167	1193	goto out;
1168	1194
@@ -1170,6 +1196,8 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, · 1 unmodified line
1170	1196	chunk = &cs_chunk_array[0];
1171	1197
1172	1198	if (chunk->queue_index >= hdev->asic_prop.max_queues) {
	1199	+ atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
	1200	+ atomic64_inc(&cntr->validation_drop_cnt);
1173	1201	dev_err(hdev->dev, "Queue index %d is invalid\n",
1174	1202	chunk->queue_index);
1175	1203	rc = -EINVAL;
@@ -1181,6 +1209,8 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, · 5 unmodified lines
1181	1209	q_type = hw_queue_prop->type;
1182	1210
1183	1211	if (!hw_queue_prop->supports_sync_stream) {
	1212	+ atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
	1213	+ atomic64_inc(&cntr->validation_drop_cnt);
1184	1214	dev_err(hdev->dev,
1185	1215	"Queue index %d does not support sync stream operations\n",
1186	1216	q_idx);
@@ -1190,6 +1220,8 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, · 3 unmodified lines
1190	1220
1191	1221	if (cs_type == CS_TYPE_COLLECTIVE_WAIT) {
1192	1222	if (!(hw_queue_prop->collective_mode == HL_COLLECTIVE_MASTER)) {
	1223	+ atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
	1224	+ atomic64_inc(&cntr->validation_drop_cnt);
1193	1225	dev_err(hdev->dev,
1194	1226	"Queue index %d is invalid\n", q_idx);
1195	1227	rc = -EINVAL;
@@ -1200,12 +1232,14 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, · 4 unmodified lines
1200	1232	}
1201	1233
1202	1234	if (cs_type == CS_TYPE_WAIT \|\| cs_type == CS_TYPE_COLLECTIVE_WAIT) {
1203		− rc = cs_ioctl_extract_signal_seq(hdev, chunk, &signal_seq);
	1235	+ rc = cs_ioctl_extract_signal_seq(hdev, chunk, &signal_seq, ctx);
1204	1236	if (rc)
1205	1237	goto free_cs_chunk_array;
1206	1238
1207	1239	sig_fence = hl_ctx_get_fence(ctx, signal_seq);
1208	1240	if (IS_ERR(sig_fence)) {
	1241	+ atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
	1242	+ atomic64_inc(&cntr->validation_drop_cnt);
1209	1243	dev_err(hdev->dev,
1210	1244	"Failed to get signal CS with seq 0x%llx\n",
1211	1245	signal_seq);
@@ -1223,6 +1257,8 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, · 11 unmodified lines
1223	1257	container_of(sig_fence, struct hl_cs_compl, base_fence);
1224	1258
1225	1259	if (sig_waitcs_cmpl->type != CS_TYPE_SIGNAL) {
	1260	+ atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
	1261	+ atomic64_inc(&cntr->validation_drop_cnt);
1226	1262	dev_err(hdev->dev,
1227	1263	"CS seq 0x%llx is not of a signal CS\n",
1228	1264	signal_seq);
@@ -1270,8 +1306,11 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, · 41 unmodified lines
1270	1306	else if (cs_type == CS_TYPE_COLLECTIVE_WAIT)
1271	1307	rc = hdev->asic_funcs->collective_wait_create_jobs(hdev, ctx,
1272	1308	cs, q_idx, collective_engine_id);
1273		− else
	1309	+ else {
	1310	+ atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
	1311	+ atomic64_inc(&cntr->validation_drop_cnt);
1274	1312	rc = -EINVAL;
	1313	+ }
1275	1314
1276	1315	if (rc)
1277	1316	goto free_cs_object;

drivers/misc/habanalabs/common/device.c+5−3

@@ -17,12 +17,12 @@ enum hl_device_status hl_device_status(struct hl_device *hdev) · 16 unmodified lines
17	17	{
18	18	enum hl_device_status status;
19	19
20		− if (hdev->disabled)
21		− status = HL_DEVICE_STATUS_MALFUNCTION;
22		− else if (atomic_read(&hdev->in_reset))
	20	+ if (atomic_read(&hdev->in_reset))
23	21	status = HL_DEVICE_STATUS_IN_RESET;
24	22	else if (hdev->needs_reset)
25	23	status = HL_DEVICE_STATUS_NEEDS_RESET;
	24	+ else if (hdev->disabled)
	25	+ status = HL_DEVICE_STATUS_MALFUNCTION;
26	26	else
27	27	status = HL_DEVICE_STATUS_OPERATIONAL;
28	28
@@ -1092,6 +1092,7 @@ kill_processes: · 1063 unmodified lines
1092	1092	GFP_KERNEL);
1093	1093	if (!hdev->kernel_ctx) {
1094	1094	rc = -ENOMEM;
	1095	+ hl_mmu_fini(hdev);
1095	1096	goto out_err;
1096	1097	}
1097	1098
@@ -1103,6 +1104,7 @@ kill_processes: · 5 unmodified lines
1103	1104	"failed to init kernel ctx in hard reset\n");
1104	1105	kfree(hdev->kernel_ctx);
1105	1106	hdev->kernel_ctx = NULL;
	1107	+ hl_mmu_fini(hdev);
1106	1108	goto out_err;
1107	1109	}
1108	1110	}

drivers/misc/habanalabs/common/firmware_if.c+44−16

@@ -627,25 +627,38 @@ int hl_fw_read_preboot_status(struct hl_device *hdev, u32 cpu_boot_status_reg, · 626 unmodified lines
627	627	security_status = RREG32(cpu_security_boot_status_reg);
628	628
629	629	/* We read security status multiple times during boot:
630		− * 1. preboot - we check if fw security feature is supported
631		− * 2. boot cpu - we get boot cpu security status
632		− * 3. FW application - we get FW application security status
	630	+ * 1. preboot - a. Check whether the security status bits are valid
	631	+ * b. Check whether fw security is enabled
	632	+ * c. Check whether hard reset is done by preboot
	633	+ * 2. boot cpu - a. Fetch boot cpu security status
	634	+ * b. Check whether hard reset is done by boot cpu
	635	+ * 3. FW application - a. Fetch fw application security status
	636	+ * b. Check whether hard reset is done by fw app
633	637	*
634	638	* Preboot:
635	639	* Check security status bit (CPU_BOOT_DEV_STS0_ENABLED), if it is set
636	640	* check security enabled bit (CPU_BOOT_DEV_STS0_SECURITY_EN)
637	641	*/
638	642	if (security_status & CPU_BOOT_DEV_STS0_ENABLED) {
639		− hdev->asic_prop.fw_security_status_valid = 1;
640		− prop->fw_security_disabled =
641		− !(security_status & CPU_BOOT_DEV_STS0_SECURITY_EN);
	643	+ prop->fw_security_status_valid = 1;
	644	+
	645	+ if (security_status & CPU_BOOT_DEV_STS0_SECURITY_EN)
	646	+ prop->fw_security_disabled = false;
	647	+ else
	648	+ prop->fw_security_disabled = true;
	649	+
	650	+ if (security_status & CPU_BOOT_DEV_STS0_FW_HARD_RST_EN)
	651	+ prop->hard_reset_done_by_fw = true;
642	652	} else {
643		− hdev->asic_prop.fw_security_status_valid = 0;
	653	+ prop->fw_security_status_valid = 0;
644	654	prop->fw_security_disabled = true;
645	655	}
646	656
	657	+ dev_dbg(hdev->dev, "Firmware preboot hard-reset is %s\n",
	658	+ prop->hard_reset_done_by_fw ? "enabled" : "disabled");
	659	+
647	660	dev_info(hdev->dev, "firmware-level security is %s\n",
648		− prop->fw_security_disabled ? "disabled" : "enabled");
	661	+ prop->fw_security_disabled ? "disabled" : "enabled");
649	662
650	663	return 0;
651	664	}
@@ -655,6 +668,7 @@ int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, · 3 unmodified lines
655	668	u32 cpu_security_boot_status_reg, u32 boot_err0_reg,
656	669	bool skip_bmc, u32 cpu_timeout, u32 boot_fit_timeout)
657	670	{
	671	+ struct asic_fixed_properties *prop = &hdev->asic_prop;
658	672	u32 status;
659	673	int rc;
660	674
@@ -723,11 +737,22 @@ int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, · 62 unmodified lines
723	737	/* Read U-Boot version now in case we will later fail */
724	738	hdev->asic_funcs->read_device_fw_version(hdev, FW_COMP_UBOOT);
725	739
	740	+ /* Clear reset status since we need to read it again from boot CPU */
	741	+ prop->hard_reset_done_by_fw = false;
	742	+
726	743	/* Read boot_cpu security bits */
727		− if (hdev->asic_prop.fw_security_status_valid)
728		− hdev->asic_prop.fw_boot_cpu_security_map =
	744	+ if (prop->fw_security_status_valid) {
	745	+ prop->fw_boot_cpu_security_map =
729	746	RREG32(cpu_security_boot_status_reg);
730	747
	748	+ if (prop->fw_boot_cpu_security_map &
	749	+ CPU_BOOT_DEV_STS0_FW_HARD_RST_EN)
	750	+ prop->hard_reset_done_by_fw = true;
	751	+ }
	752	+
	753	+ dev_dbg(hdev->dev, "Firmware boot CPU hard-reset is %s\n",
	754	+ prop->hard_reset_done_by_fw ? "enabled" : "disabled");
	755	+
731	756	if (rc) {
732	757	detect_cpu_boot_status(hdev, status);
733	758	rc = -EIO;
@@ -796,18 +821,21 @@ int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, · 62 unmodified lines
796	821	goto out;
797	822	}
798	823
	824	+ /* Clear reset status since we need to read again from app */
	825	+ prop->hard_reset_done_by_fw = false;
	826	+
799	827	/* Read FW application security bits */
800		− if (hdev->asic_prop.fw_security_status_valid) {
801		− hdev->asic_prop.fw_app_security_map =
	828	+ if (prop->fw_security_status_valid) {
	829	+ prop->fw_app_security_map =
802	830	RREG32(cpu_security_boot_status_reg);
803	831
804		− if (hdev->asic_prop.fw_app_security_map &
	832	+ if (prop->fw_app_security_map &
805	833	CPU_BOOT_DEV_STS0_FW_HARD_RST_EN)
806		− hdev->asic_prop.hard_reset_done_by_fw = true;
	834	+ prop->hard_reset_done_by_fw = true;
807	835	}
808	836
809		− dev_dbg(hdev->dev, "Firmware hard-reset is %s\n",
810		− hdev->asic_prop.hard_reset_done_by_fw ? "enabled" : "disabled");
	837	+ dev_dbg(hdev->dev, "Firmware application CPU hard-reset is %s\n",
	838	+ prop->hard_reset_done_by_fw ? "enabled" : "disabled");
811	839
812	840	dev_info(hdev->dev, "Successfully loaded firmware to device\n");
813	841

drivers/misc/habanalabs/common/habanalabs.h+3−1

@@ -944,7 +944,7 @@ struct hl_asic_funcs { · 943 unmodified lines
944	944	u32 (get_signal_cb_size)(struct hl_device hdev);
945	945	u32 (get_wait_cb_size)(struct hl_device hdev);
946	946	u32 (gen_signal_cb)(struct hl_device hdev, void *data, u16 sob_id,
947		− u32 size);
	947	+ u32 size, bool eb);
948	948	u32 (gen_wait_cb)(struct hl_device hdev,
949	949	struct hl_gen_wait_properties *prop);
950	950	void (reset_sob)(struct hl_device hdev, void *data);
@@ -1000,6 +1000,7 @@ struct hl_va_range { · 49 unmodified lines
1000	1000	* @queue_full_drop_cnt: dropped due to queue full
1001	1001	* @device_in_reset_drop_cnt: dropped due to device in reset
1002	1002	* @max_cs_in_flight_drop_cnt: dropped due to maximum CS in-flight
	1003	+ * @validation_drop_cnt: dropped due to error in validation
1003	1004	*/
1004	1005	struct hl_cs_counters_atomic {
1005	1006	atomic64_t out_of_mem_drop_cnt;
@@ -1007,6 +1008,7 @@ struct hl_cs_counters_atomic { · 1 unmodified line
1007	1008	atomic64_t queue_full_drop_cnt;
1008	1009	atomic64_t device_in_reset_drop_cnt;
1009	1010	atomic64_t max_cs_in_flight_drop_cnt;
	1011	+ atomic64_t validation_drop_cnt;
1010	1012	};
1011	1013
1012	1014	/**

drivers/misc/habanalabs/common/habanalabs_drv.c+1−0

@@ -544,6 +544,7 @@ static struct pci_driver hl_pci_driver = { · 543 unmodified lines
544	544	.id_table = ids,
545	545	.probe = hl_pci_probe,
546	546	.remove = hl_pci_remove,
	547	+ .shutdown = hl_pci_remove,
547	548	.driver.pm = &hl_pm_ops,
548	549	.err_handler = &hl_pci_err_handler,
549	550	};

drivers/misc/habanalabs/common/habanalabs_ioctl.c+6−1

@@ -335,6 +335,8 @@ static int cs_counters_info(struct hl_fpriv hpriv, struct hl_info_args args) · 334 unmodified lines
335	335	atomic64_read(&cntr->device_in_reset_drop_cnt);
336	336	cs_counters.total_max_cs_in_flight_drop_cnt =
337	337	atomic64_read(&cntr->max_cs_in_flight_drop_cnt);
	338	+ cs_counters.total_validation_drop_cnt =
	339	+ atomic64_read(&cntr->validation_drop_cnt);
338	340
339	341	if (hpriv->ctx) {
340	342	cs_counters.ctx_out_of_mem_drop_cnt =
@@ -352,6 +354,9 @@ static int cs_counters_info(struct hl_fpriv hpriv, struct hl_info_args args) · 11 unmodified lines
352	354	cs_counters.ctx_max_cs_in_flight_drop_cnt =
353	355	atomic64_read(
354	356	&hpriv->ctx->cs_counters.max_cs_in_flight_drop_cnt);
	357	+ cs_counters.ctx_validation_drop_cnt =
	358	+ atomic64_read(
	359	+ &hpriv->ctx->cs_counters.validation_drop_cnt);
355	360	}
356	361
357	362	return copy_to_user(out, &cs_counters,
@@ -406,7 +411,7 @@ static int total_energy_consumption_info(struct hl_fpriv *hpriv, · 48 unmodified lines
406	411	static int pll_frequency_info(struct hl_fpriv hpriv, struct hl_info_args args)
407	412	{
408	413	struct hl_device *hdev = hpriv->hdev;
409		− struct hl_pll_frequency_info freq_info = {0};
	414	+ struct hl_pll_frequency_info freq_info = { {0} };
410	415	u32 max_size = args->return_size;
411	416	void __user out = (void __user ) (uintptr_t) args->return_pointer;
412	417	int rc;

drivers/misc/habanalabs/common/hw_queue.c+4−1

@@ -418,8 +418,11 @@ static void init_signal_cs(struct hl_device *hdev, · 417 unmodified lines
418	418	"generate signal CB, sob_id: %d, sob val: 0x%x, q_idx: %d\n",
419	419	cs_cmpl->hw_sob->sob_id, cs_cmpl->sob_val, q_idx);
420	420
	421	+ /* we set an EB since we must make sure all oeprations are done
	422	+ * when sending the signal
	423	+ */
421	424	hdev->asic_funcs->gen_signal_cb(hdev, job->patched_cb,
422		− cs_cmpl->hw_sob->sob_id, 0);
	425	+ cs_cmpl->hw_sob->sob_id, 0, true);
423	426
424	427	kref_get(&hw_sob->kref);
425	428

drivers/misc/habanalabs/common/pci.c+17−11

@@ -130,10 +130,8 @@ static int hl_pci_elbi_write(struct hl_device *hdev, u64 addr, u32 data) · 129 unmodified lines
130	130	if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE)
131	131	return 0;
132	132
133		− if (val & PCI_CONFIG_ELBI_STS_ERR) {
134		− dev_err(hdev->dev, "Error writing to ELBI\n");
	133	+ if (val & PCI_CONFIG_ELBI_STS_ERR)
135	134	return -EIO;
136		− }
137	135
138	136	if (!(val & PCI_CONFIG_ELBI_STS_MASK)) {
139	137	dev_err(hdev->dev, "ELBI write didn't finish in time\n");
@@ -160,8 +158,12 @@ int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data) · 20 unmodified lines
160	158
161	159	dbi_offset = addr & 0xFFF;
162	160
163		− rc = hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0x00300000);
164		− rc \|= hl_pci_elbi_write(hdev, prop->pcie_dbi_base_address + dbi_offset,
	161	+ /* Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
	162	+ * in case the firmware security is enabled
	163	+ */
	164	+ hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0x00300000);
	165	+
	166	+ rc = hl_pci_elbi_write(hdev, prop->pcie_dbi_base_address + dbi_offset,
165	167	data);
166	168
167	169	if (rc)
@@ -244,9 +246,11 @@ int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region, · 76 unmodified lines
244	246
245	247	rc \|= hl_pci_iatu_write(hdev, offset + 0x4, ctrl_reg_val);
246	248
247		− /* Return the DBI window to the default location */
248		− rc \|= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
249		− rc \|= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr + 4, 0);
	249	+ /* Return the DBI window to the default location
	250	+ * Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
	251	+ * in case the firmware security is enabled
	252	+ */
	253	+ hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
250	254
251	255	if (rc)
252	256	dev_err(hdev->dev, "failed to map bar %u to 0x%08llx\n",
@@ -294,9 +298,11 @@ int hl_pci_set_outbound_region(struct hl_device *hdev, · 41 unmodified lines
294	298	/* Enable */
295	299	rc \|= hl_pci_iatu_write(hdev, 0x004, 0x80000000);
296	300
297		− /* Return the DBI window to the default location */
298		− rc \|= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
299		− rc \|= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr + 4, 0);
	301	+ /* Return the DBI window to the default location
	302	+ * Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
	303	+ * in case the firmware security is enabled
	304	+ */
	305	+ hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
300	306
301	307	return rc;
302	308	}

drivers/misc/habanalabs/gaudi/gaudi.c+83−108

@@ -151,19 +151,6 @@ static const u16 gaudi_packet_sizes[MAX_PACKET_ID] = { · 150 unmodified lines
151	151	[PACKET_LOAD_AND_EXE] = sizeof(struct packet_load_and_exe)
152	152	};
153	153
154		−static const u32 gaudi_pll_base_addresses[GAUDI_PLL_MAX] = {
155		− [CPU_PLL] = mmPSOC_CPU_PLL_NR,
156		− [PCI_PLL] = mmPSOC_PCI_PLL_NR,
157		− [SRAM_PLL] = mmSRAM_W_PLL_NR,
158		− [HBM_PLL] = mmPSOC_HBM_PLL_NR,
159		− [NIC_PLL] = mmNIC0_PLL_NR,
160		− [DMA_PLL] = mmDMA_W_PLL_NR,
161		− [MESH_PLL] = mmMESH_W_PLL_NR,
162		− [MME_PLL] = mmPSOC_MME_PLL_NR,
163		− [TPC_PLL] = mmPSOC_TPC_PLL_NR,
164		− [IF_PLL] = mmIF_W_PLL_NR
165		−};
166		−
167	154	static inline bool validate_packet_id(enum packet_id id)
168	155	{
169	156	switch (id) {
@@ -374,7 +361,7 @@ static int gaudi_cpucp_info_get(struct hl_device *hdev); · 204 unmodified lines
374	361	static void gaudi_disable_clock_gating(struct hl_device *hdev);
375	362	static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid);
376	363	static u32 gaudi_gen_signal_cb(struct hl_device hdev, void data, u16 sob_id,
377		− u32 size);
	364	+ u32 size, bool eb);
378	365	static u32 gaudi_gen_wait_cb(struct hl_device *hdev,
379	366	struct hl_gen_wait_properties *prop);
380	367
@@ -667,12 +654,6 @@ static int gaudi_early_init(struct hl_device *hdev) · 286 unmodified lines
667	654	if (rc)
668	655	goto free_queue_props;
669	656
670		− if (gaudi_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
671		− dev_info(hdev->dev,
672		− "H/W state is dirty, must reset before initializing\n");
673		− hdev->asic_funcs->hw_fini(hdev, true);
674		− }
675		−
676	657	/* Before continuing in the initialization, we need to read the preboot
677	658	* version to determine whether we run with a security-enabled firmware
678	659	*/
@@ -685,6 +666,12 @@ static int gaudi_early_init(struct hl_device *hdev) · 6 unmodified lines
685	666	goto pci_fini;
686	667	}
687	668
	669	+ if (gaudi_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
	670	+ dev_info(hdev->dev,
	671	+ "H/W state is dirty, must reset before initializing\n");
	672	+ hdev->asic_funcs->hw_fini(hdev, true);
	673	+ }
	674	+
688	675	return 0;
689	676
690	677	pci_fini:
@@ -703,93 +690,60 @@ static int gaudi_early_fini(struct hl_device *hdev) · 12 unmodified lines
703	690	}
704	691
705	692	/**
706		− * gaudi_fetch_pll_frequency - Fetch PLL frequency values
	693	+ * gaudi_fetch_psoc_frequency - Fetch PSOC frequency values
707	694	*
708	695	* @hdev: pointer to hl_device structure
709		− * @pll_index: index of the pll to fetch frequency from
710		− * @pll_freq: pointer to store the pll frequency in MHz in each of the available
711		− * outputs. if a certain output is not available a 0 will be set
712	696	*
713	697	*/
714		−static int gaudi_fetch_pll_frequency(struct hl_device *hdev,
715		− enum gaudi_pll_index pll_index,
716		− u16 *pll_freq_arr)
	698	+static int gaudi_fetch_psoc_frequency(struct hl_device *hdev)
717	699	{
718		− u32 nr = 0, nf = 0, od = 0, pll_clk = 0, div_fctr, div_sel,
719		− pll_base_addr = gaudi_pll_base_addresses[pll_index];
720		− u16 freq = 0;
721		− int i, rc;
722		−
723		− if (hdev->asic_prop.fw_security_status_valid &&
724		− (hdev->asic_prop.fw_app_security_map &
725		− CPU_BOOT_DEV_STS0_PLL_INFO_EN)) {
726		− rc = hl_fw_cpucp_pll_info_get(hdev, pll_index, pll_freq_arr);
	700	+ struct asic_fixed_properties *prop = &hdev->asic_prop;
	701	+ u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;
	702	+ u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq;
	703	+ int rc;
727	704
728		− if (rc)
729		− return rc;
730		− } else if (hdev->asic_prop.fw_security_disabled) {
	705	+ if (hdev->asic_prop.fw_security_disabled) {
731	706	/* Backward compatibility */
732		− nr = RREG32(pll_base_addr + PLL_NR_OFFSET);
733		− nf = RREG32(pll_base_addr + PLL_NF_OFFSET);
734		− od = RREG32(pll_base_addr + PLL_OD_OFFSET);
735		−
736		− for (i = 0; i < HL_PLL_NUM_OUTPUTS; i++) {
737		− div_fctr = RREG32(pll_base_addr +
738		− PLL_DIV_FACTOR_0_OFFSET + i * 4);
739		− div_sel = RREG32(pll_base_addr +
740		− PLL_DIV_SEL_0_OFFSET + i * 4);
	707	+ div_fctr = RREG32(mmPSOC_CPU_PLL_DIV_FACTOR_2);
	708	+ div_sel = RREG32(mmPSOC_CPU_PLL_DIV_SEL_2);
	709	+ nr = RREG32(mmPSOC_CPU_PLL_NR);
	710	+ nf = RREG32(mmPSOC_CPU_PLL_NF);
	711	+ od = RREG32(mmPSOC_CPU_PLL_OD);
741	712
742		− if (div_sel == DIV_SEL_REF_CLK \|\|
	713	+ if (div_sel == DIV_SEL_REF_CLK \|\|
743	714	div_sel == DIV_SEL_DIVIDED_REF) {
744		− if (div_sel == DIV_SEL_REF_CLK)
745		− freq = PLL_REF_CLK;
746		− else
747		− freq = PLL_REF_CLK / (div_fctr + 1);
748		− } else if (div_sel == DIV_SEL_PLL_CLK \|\|
749		− div_sel == DIV_SEL_DIVIDED_PLL) {
750		− pll_clk = PLL_REF_CLK * (nf + 1) /
751		− ((nr + 1) * (od + 1));
752		− if (div_sel == DIV_SEL_PLL_CLK)
753		− freq = pll_clk;
754		− else
755		− freq = pll_clk / (div_fctr + 1);
756		− } else {
757		− dev_warn(hdev->dev,
758		− "Received invalid div select value: %d",
759		− div_sel);
760		− }
761		−
762		− pll_freq_arr[i] = freq;
	715	+ if (div_sel == DIV_SEL_REF_CLK)
	716	+ freq = PLL_REF_CLK;
	717	+ else
	718	+ freq = PLL_REF_CLK / (div_fctr + 1);
	719	+ } else if (div_sel == DIV_SEL_PLL_CLK \|\|
	720	+ div_sel == DIV_SEL_DIVIDED_PLL) {
	721	+ pll_clk = PLL_REF_CLK * (nf + 1) /
	722	+ ((nr + 1) * (od + 1));
	723	+ if (div_sel == DIV_SEL_PLL_CLK)
	724	+ freq = pll_clk;
	725	+ else
	726	+ freq = pll_clk / (div_fctr + 1);
	727	+ } else {
	728	+ dev_warn(hdev->dev,
	729	+ "Received invalid div select value: %d",
	730	+ div_sel);
	731	+ freq = 0;
763	732	}
764	733	} else {
765		− dev_err(hdev->dev, "Failed to fetch PLL frequency values\n");
766		− return -EIO;
767		− }
	734	+ rc = hl_fw_cpucp_pll_info_get(hdev, CPU_PLL, pll_freq_arr);
768	735
769		− return 0;
770		−}
771		−
772		−/**
773		− * gaudi_fetch_psoc_frequency - Fetch PSOC frequency values
774		− *
775		− * @hdev: pointer to hl_device structure
776		− *
777		− */
778		−static int gaudi_fetch_psoc_frequency(struct hl_device *hdev)
779		−{
780		− struct asic_fixed_properties *prop = &hdev->asic_prop;
781		− u16 pll_freq[HL_PLL_NUM_OUTPUTS];
782		− int rc;
	736	+ if (rc)
	737	+ return rc;
783	738
784		− rc = gaudi_fetch_pll_frequency(hdev, CPU_PLL, pll_freq);
785		− if (rc)
786		− return rc;
	739	+ freq = pll_freq_arr[2];
	740	+ }
787	741
788		− prop->psoc_timestamp_frequency = pll_freq[2];
789		− prop->psoc_pci_pll_nr = 0;
790		− prop->psoc_pci_pll_nf = 0;
791		− prop->psoc_pci_pll_od = 0;
792		− prop->psoc_pci_pll_div_factor = 0;
	742	+ prop->psoc_timestamp_frequency = freq;
	743	+ prop->psoc_pci_pll_nr = nr;
	744	+ prop->psoc_pci_pll_nf = nf;
	745	+ prop->psoc_pci_pll_od = od;
	746	+ prop->psoc_pci_pll_div_factor = div_fctr;
793	747
794	748	return 0;
795	749	}
@@ -884,11 +838,17 @@ static int gaudi_init_tpc_mem(struct hl_device *hdev) · 88 unmodified lines
884	838	size_t fw_size;
885	839	void *cpu_addr;
886	840	dma_addr_t dma_handle;
887		− int rc;
	841	+ int rc, count = 5;
888	842
	843	+again:
889	844	rc = request_firmware(&fw, GAUDI_TPC_FW_FILE, hdev->dev);
	845	+ if (rc == -EINTR && count-- > 0) {
	846	+ msleep(50);
	847	+ goto again;
	848	+ }
	849	+
890	850	if (rc) {
891		− dev_err(hdev->dev, "Firmware file %s is not found!\n",
	851	+ dev_err(hdev->dev, "Failed to load firmware file %s\n",
892	852	GAUDI_TPC_FW_FILE);
893	853	goto out;
894	854	}
@@ -1110,7 +1070,7 @@ static void gaudi_collective_slave_init_job(struct hl_device *hdev, · 215 unmodified lines
1110	1070	prop->collective_sob_id, queue_id);
1111	1071
1112	1072	cb_size += gaudi_gen_signal_cb(hdev, job->user_cb,
1113		− prop->collective_sob_id, cb_size);
	1073	+ prop->collective_sob_id, cb_size, false);
1114	1074	}
1115	1075
1116	1076	static void gaudi_collective_wait_init_cs(struct hl_cs *cs)
@@ -2449,8 +2409,6 @@ static void gaudi_init_golden_registers(struct hl_device *hdev) · 1332 unmodified lines
2449	2409	gaudi_init_e2e(hdev);
2450	2410	gaudi_init_hbm_cred(hdev);
2451	2411
2452		− hdev->asic_funcs->disable_clock_gating(hdev);
2453		−
2454	2412	for (tpc_id = 0, tpc_offset = 0;
2455	2413	tpc_id < TPC_NUMBER_OF_ENGINES;
2456	2414	tpc_id++, tpc_offset += TPC_CFG_OFFSET) {
@@ -3462,6 +3420,9 @@ static void gaudi_set_clock_gating(struct hl_device *hdev) · 1005 unmodified lines
3462	3420	if (hdev->in_debug)
3463	3421	return;
3464	3422
	3423	+ if (!hdev->asic_prop.fw_security_disabled)
	3424	+ return;
	3425	+
3465	3426	for (i = GAUDI_PCI_DMA_1, qman_offset = 0 ; i < GAUDI_HBM_DMA_1 ; i++) {
3466	3427	enable = !!(hdev->clock_gating_mask &
3467	3428	(BIT_ULL(gaudi_dma_assignment[i])));
@@ -3513,7 +3474,7 @@ static void gaudi_disable_clock_gating(struct hl_device *hdev) · 45 unmodified lines
3513	3474	u32 qman_offset;
3514	3475	int i;
3515	3476
3516		− if (!(gaudi->hw_cap_initialized & HW_CAP_CLK_GATE))
	3477	+ if (!hdev->asic_prop.fw_security_disabled)
3517	3478	return;
3518	3479
3519	3480	for (i = 0, qman_offset = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) {
@@ -3806,7 +3767,7 @@ static int gaudi_init_cpu_queues(struct hl_device *hdev, u32 cpu_timeout) · 286 unmodified lines
3806	3767	static void gaudi_pre_hw_init(struct hl_device *hdev)
3807	3768	{
3808	3769	/* Perform read from the device to make sure device is up */
3809		− RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
	3770	+ RREG32(mmHW_STATE);
3810	3771
3811	3772	if (hdev->asic_prop.fw_security_disabled) {
3812	3773	/* Set the access through PCI bars (Linux driver only) as
@@ -3847,6 +3808,13 @@ static int gaudi_hw_init(struct hl_device *hdev) · 34 unmodified lines
3847	3808	return rc;
3848	3809	}
3849	3810
	3811	+ /* In case the clock gating was enabled in preboot we need to disable
	3812	+ * it here before touching the MME/TPC registers.
	3813	+ * There is no need to take clk gating mutex because when this function
	3814	+ * runs, no other relevant code can run
	3815	+ */
	3816	+ hdev->asic_funcs->disable_clock_gating(hdev);
	3817	+
3850	3818	/* SRAM scrambler must be initialized after CPU is running from HBM */
3851	3819	gaudi_init_scrambler_sram(hdev);
3852	3820
@@ -3885,7 +3853,7 @@ static int gaudi_hw_init(struct hl_device *hdev) · 32 unmodified lines
3885	3853	}
3886	3854
3887	3855	/* Perform read from the device to flush all configuration */
3888		− RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
	3856	+ RREG32(mmHW_STATE);
3889	3857
3890	3858	return 0;
3891	3859
@@ -3927,7 +3895,10 @@ static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset) · 35 unmodified lines
3927	3895	/* I don't know what is the state of the CPU so make sure it is
3928	3896	* stopped in any means necessary
3929	3897	*/
3930		− WREG32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, KMD_MSG_GOTO_WFE);
	3898	+ if (hdev->asic_prop.hard_reset_done_by_fw)
	3899	+ WREG32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, KMD_MSG_RST_DEV);
	3900	+ else
	3901	+ WREG32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, KMD_MSG_GOTO_WFE);
3931	3902
3932	3903	WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_HALT_MACHINE);
3933	3904
@@ -3971,11 +3942,15 @@ static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset) · 37 unmodified lines
3971	3942
3972	3943	WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST,
3973	3944	1 << PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT);
3974		− }
3975	3945
3976		− dev_info(hdev->dev,
3977		− "Issued HARD reset command, going to wait %dms\n",
3978		− reset_timeout_ms);
	3946	+ dev_info(hdev->dev,
	3947	+ "Issued HARD reset command, going to wait %dms\n",
	3948	+ reset_timeout_ms);
	3949	+ } else {
	3950	+ dev_info(hdev->dev,
	3951	+ "Firmware performs HARD reset, going to wait %dms\n",
	3952	+ reset_timeout_ms);
	3953	+ }
3979	3954
3980	3955	/*
3981	3956	* After hard reset, we can't poll the BTM_FSM register because the PSOC
@@ -7936,7 +7911,7 @@ static u32 gaudi_get_wait_cb_size(struct hl_device *hdev) · 3954 unmodified lines
7936	7911	}
7937	7912
7938	7913	static u32 gaudi_gen_signal_cb(struct hl_device hdev, void data, u16 sob_id,
7939		− u32 size)
	7914	+ u32 size, bool eb)
7940	7915	{
7941	7916	struct hl_cb cb = (struct hl_cb ) data;
7942	7917	struct packet_msg_short *pkt;
@@ -7953,7 +7928,7 @@ static u32 gaudi_gen_signal_cb(struct hl_device hdev, void data, u16 sob_id, · 10 unmodified lines
7953	7928	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_OP_MASK, 0); /* write the value */
7954	7929	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_BASE_MASK, 3); /* W_S SOB base */
7955	7930	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_OPCODE_MASK, PACKET_MSG_SHORT);
7956		− ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_EB_MASK, 1);
	7931	+ ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_EB_MASK, eb);
7957	7932	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_RB_MASK, 1);
7958	7933	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_MB_MASK, 1);
7959	7934

drivers/misc/habanalabs/gaudi/gaudiP.h+0−7

@@ -105,13 +105,6 @@ · 104 unmodified lines
105	105	#define MME_ACC_OFFSET (mmMME1_ACC_BASE - mmMME0_ACC_BASE)
106	106	#define SRAM_BANK_OFFSET (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE)
107	107
108		−#define PLL_NR_OFFSET 0
109		−#define PLL_NF_OFFSET (mmPSOC_CPU_PLL_NF - mmPSOC_CPU_PLL_NR)
110		−#define PLL_OD_OFFSET (mmPSOC_CPU_PLL_OD - mmPSOC_CPU_PLL_NR)
111		−#define PLL_DIV_FACTOR_0_OFFSET (mmPSOC_CPU_PLL_DIV_FACTOR_0 - \
112		− mmPSOC_CPU_PLL_NR)
113		−#define PLL_DIV_SEL_0_OFFSET (mmPSOC_CPU_PLL_DIV_SEL_0 - mmPSOC_CPU_PLL_NR)
114		−
115	108	#define NUM_OF_SOB_IN_BLOCK \
116	109	(((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \
117	110	mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)

drivers/misc/habanalabs/gaudi/gaudi_coresight.c+2−1

@@ -9,6 +9,7 @@ · 8 unmodified lines
9	9	#include "../include/gaudi/gaudi_coresight.h"
10	10	#include "../include/gaudi/asic_reg/gaudi_regs.h"
11	11	#include "../include/gaudi/gaudi_masks.h"
	12	+#include "../include/gaudi/gaudi_reg_map.h"
12	13
13	14	#include <uapi/misc/habanalabs.h>
14	15	#define SPMU_SECTION_SIZE MME0_ACC_SPMU_MAX_OFFSET
@@ -874,7 +875,7 @@ int gaudi_debug_coresight(struct hl_device hdev, void data) · 859 unmodified lines
874	875	}
875	876
876	877	/* Perform read from the device to flush all configuration */
877		− RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
	878	+ RREG32(mmHW_STATE);
878	879
879	880	return rc;
880	881	}

drivers/misc/habanalabs/goya/goya.c+45−30

@@ -613,12 +613,6 @@ static int goya_early_init(struct hl_device *hdev) · 612 unmodified lines
613	613	if (rc)
614	614	goto free_queue_props;
615	615
616		− if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
617		− dev_info(hdev->dev,
618		− "H/W state is dirty, must reset before initializing\n");
619		− hdev->asic_funcs->hw_fini(hdev, true);
620		− }
621		−
622	616	/* Before continuing in the initialization, we need to read the preboot
623	617	* version to determine whether we run with a security-enabled firmware
624	618	*/
@@ -631,6 +625,12 @@ static int goya_early_init(struct hl_device *hdev) · 6 unmodified lines
631	625	goto pci_fini;
632	626	}
633	627
	628	+ if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
	629	+ dev_info(hdev->dev,
	630	+ "H/W state is dirty, must reset before initializing\n");
	631	+ hdev->asic_funcs->hw_fini(hdev, true);
	632	+ }
	633	+
634	634	if (!hdev->pldm) {
635	635	val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
636	636	if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
@@ -694,32 +694,47 @@ static void goya_qman0_set_security(struct hl_device *hdev, bool secure) · 57 unmodified lines
694	694	static void goya_fetch_psoc_frequency(struct hl_device *hdev)
695	695	{
696	696	struct asic_fixed_properties *prop = &hdev->asic_prop;
697		− u32 trace_freq = 0;
698		− u32 pll_clk = 0;
699		− u32 div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
700		− u32 div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1);
701		− u32 nr = RREG32(mmPSOC_PCI_PLL_NR);
702		− u32 nf = RREG32(mmPSOC_PCI_PLL_NF);
703		− u32 od = RREG32(mmPSOC_PCI_PLL_OD);
704		−
705		− if (div_sel == DIV_SEL_REF_CLK \|\| div_sel == DIV_SEL_DIVIDED_REF) {
706		− if (div_sel == DIV_SEL_REF_CLK)
707		− trace_freq = PLL_REF_CLK;
708		− else
709		− trace_freq = PLL_REF_CLK / (div_fctr + 1);
710		− } else if (div_sel == DIV_SEL_PLL_CLK \|\|
711		− div_sel == DIV_SEL_DIVIDED_PLL) {
712		− pll_clk = PLL_REF_CLK * (nf + 1) / ((nr + 1) * (od + 1));
713		− if (div_sel == DIV_SEL_PLL_CLK)
714		− trace_freq = pll_clk;
715		− else
716		− trace_freq = pll_clk / (div_fctr + 1);
	697	+ u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;
	698	+ u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq;
	699	+ int rc;
	700	+
	701	+ if (hdev->asic_prop.fw_security_disabled) {
	702	+ div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
	703	+ div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1);
	704	+ nr = RREG32(mmPSOC_PCI_PLL_NR);
	705	+ nf = RREG32(mmPSOC_PCI_PLL_NF);
	706	+ od = RREG32(mmPSOC_PCI_PLL_OD);
	707	+
	708	+ if (div_sel == DIV_SEL_REF_CLK \|\|
	709	+ div_sel == DIV_SEL_DIVIDED_REF) {
	710	+ if (div_sel == DIV_SEL_REF_CLK)
	711	+ freq = PLL_REF_CLK;
	712	+ else
	713	+ freq = PLL_REF_CLK / (div_fctr + 1);
	714	+ } else if (div_sel == DIV_SEL_PLL_CLK \|\|
	715	+ div_sel == DIV_SEL_DIVIDED_PLL) {
	716	+ pll_clk = PLL_REF_CLK * (nf + 1) /
	717	+ ((nr + 1) * (od + 1));
	718	+ if (div_sel == DIV_SEL_PLL_CLK)
	719	+ freq = pll_clk;
	720	+ else
	721	+ freq = pll_clk / (div_fctr + 1);
	722	+ } else {
	723	+ dev_warn(hdev->dev,
	724	+ "Received invalid div select value: %d",
	725	+ div_sel);
	726	+ freq = 0;
	727	+ }
717	728	} else {
718		− dev_warn(hdev->dev,
719		− "Received invalid div select value: %d", div_sel);
	729	+ rc = hl_fw_cpucp_pll_info_get(hdev, PCI_PLL, pll_freq_arr);
	730	+
	731	+ if (rc)
	732	+ return;
	733	+
	734	+ freq = pll_freq_arr[1];
720	735	}
721	736
722		− prop->psoc_timestamp_frequency = trace_freq;
	737	+ prop->psoc_timestamp_frequency = freq;
723	738	prop->psoc_pci_pll_nr = nr;
724	739	prop->psoc_pci_pll_nf = nf;
725	740	prop->psoc_pci_pll_od = od;
@@ -5324,7 +5339,7 @@ static u32 goya_get_wait_cb_size(struct hl_device *hdev) · 4598 unmodified lines
5324	5339	}
5325	5340
5326	5341	static u32 goya_gen_signal_cb(struct hl_device hdev, void data, u16 sob_id,
5327		− u32 size)
	5342	+ u32 size, bool eb)
5328	5343	{
5329	5344	return 0;
5330	5345	}

drivers/misc/habanalabs/include/common/hl_boot_if.h+8−1

@@ -145,11 +145,15 @@ · 144 unmodified lines
145	145	* implemented. This means that FW will
146	146	* perform hard reset procedure on
147	147	* receiving the halt-machine event.
148		− * Initialized in: linux
	148	+ * Initialized in: preboot, u-boot, linux
149	149	*
150	150	* CPU_BOOT_DEV_STS0_PLL_INFO_EN FW retrieval of PLL info is enabled.
151	151	* Initialized in: linux
152	152	*
	153	+ * CPU_BOOT_DEV_STS0_CLK_GATE_EN Clock Gating enabled.
	154	+ * FW initialized Clock Gating.
	155	+ * Initialized in: preboot
	156	+ *
153	157	* CPU_BOOT_DEV_STS0_ENABLED Device status register enabled.
154	158	* This is a main indication that the
155	159	* running FW populates the device status
@@ -171,6 +175,7 @@ · 15 unmodified lines
171	175	#define CPU_BOOT_DEV_STS0_DRAM_SCR_EN (1 << 9)
172	176	#define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN (1 << 10)
173	177	#define CPU_BOOT_DEV_STS0_PLL_INFO_EN (1 << 11)
	178	+#define CPU_BOOT_DEV_STS0_CLK_GATE_EN (1 << 13)
174	179	#define CPU_BOOT_DEV_STS0_ENABLED (1 << 31)
175	180
176	181	enum cpu_boot_status {
@@ -204,6 +209,8 @@ enum kmd_msg { · 27 unmodified lines
204	209	KMD_MSG_GOTO_WFE,
205	210	KMD_MSG_FIT_RDY,
206	211	KMD_MSG_SKIP_BMC,
	212	+ RESERVED,
	213	+ KMD_MSG_RST_DEV,
207	214	};
208	215
209	216	enum cpu_msg_status {

drivers/misc/pvpanic.c+15−4

@@ -55,12 +55,23 @@ static int pvpanic_mmio_probe(struct platform_device *pdev) · 54 unmodified lines
55	55	struct resource *res;
56	56
57	57	res = platform_get_mem_or_io(pdev, 0);
58		− if (res && resource_type(res) == IORESOURCE_IO)
	58	+ if (!res)
	59	+ return -EINVAL;
	60	+
	61	+ switch (resource_type(res)) {
	62	+ case IORESOURCE_IO:
59	63	base = devm_ioport_map(dev, res->start, resource_size(res));
60		− else
	64	+ if (!base)
	65	+ return -ENOMEM;
	66	+ break;
	67	+ case IORESOURCE_MEM:
61	68	base = devm_ioremap_resource(dev, res);
62		− if (IS_ERR(base))
63		− return PTR_ERR(base);
	69	+ if (IS_ERR(base))
	70	+ return PTR_ERR(base);
	71	+ break;
	72	+ default:
	73	+ return -EINVAL;
	74	+ }
64	75
65	76	atomic_notifier_chain_register(&panic_notifier_list,
66	77	&pvpanic_panic_nb);

include/uapi/misc/habanalabs.h+5−0

@@ -279,6 +279,7 @@ enum hl_device_status { · 278 unmodified lines
279	279	* HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason
280	280	* HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore
281	281	* HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption
	282	+ * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency
282	283	*/
283	284	#define HL_INFO_HW_IP_INFO 0
284	285	#define HL_INFO_HW_EVENTS 1
@@ -425,6 +426,8 @@ struct hl_info_sync_manager { · 140 unmodified lines
425	426	* @ctx_device_in_reset_drop_cnt: context dropped due to device in reset
426	427	* @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight
427	428	* @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight
	429	+ * @total_validation_drop_cnt: total dropped due to validation error
	430	+ * @ctx_validation_drop_cnt: context dropped due to validation error
428	431	*/
429	432	struct hl_info_cs_counters {
430	433	__u64 total_out_of_mem_drop_cnt;
@@ -437,6 +440,8 @@ struct hl_info_cs_counters { · 6 unmodified lines
437	440	__u64 ctx_device_in_reset_drop_cnt;
438	441	__u64 total_max_cs_in_flight_drop_cnt;
439	442	__u64 ctx_max_cs_in_flight_drop_cnt;
	443	+ __u64 total_validation_drop_cnt;
	444	+ __u64 ctx_validation_drop_cnt;
440	445	};
441	446
442	447	enum gaudi_dcores {

lib/fonts/font_ter16x32.c+3−3

@@ -774,8 +774,8 @@ static const struct font_data fontdata_ter16x32 = { · 773 unmodified lines
774	774	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
775	775	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xfc,
776	776	0x7f, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 95 */
777		− 0x00, 0x00, 0x1c, 0x00, 0x0e, 0x00, 0x07, 0x00,
778		− 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	777	+ 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x0e, 0x00,
	778	+ 0x07, 0x00, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00,
779	779	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
780	780	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
781	781	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1169,7 +1169,7 @@ static const struct font_data fontdata_ter16x32 = { · 387 unmodified lines
1169	1169	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1170	1170	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1171	1171	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1172		− 0x7f, 0xf8, 0x7f, 0xfc, 0x03, 0x9e, 0x03, 0x8e,
	1172	+ 0x7e, 0xf8, 0x7f, 0xfc, 0x03, 0x9e, 0x03, 0x8e,
1173	1173	0x03, 0x8e, 0x3f, 0x8e, 0x7f, 0xfe, 0xf3, 0xfe,
1174	1174	0xe3, 0x80, 0xe3, 0x80, 0xe3, 0x80, 0xf3, 0xce,
1175	1175	0x7f, 0xfe, 0x3e, 0xfc, 0x00, 0x00, 0x00, 0x00,