History

Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux

Misc updates from mlx5-next branch: 1) Add the required HW definitions and structures for upcoming TLS support. 2) Add support for MCQI and MCQS hardware registers for fw version query. 3) Added hardware bits and structures definitions for sub-functions 4) Small code cleanup and improvement for PF pci driver. 5) Bluefield (ECPF) updates and refactoring for better E-Switch management on ECPF embedded CPU NIC: 5.1) Consolidate querying eswitch number of VFs 5.2) Register event handler at the correct E-Switch init stage 5.3) Setup PF's inline mode and vlan pop when the ECPF is the E-Swtich manager ( the host PF is basically a VF ). 5.4) Handle Vport UC address changes in switchdev mode. 6) Cleanup the rep and netdev reference when unloading IB rep. Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> i# All conflicts fixed but you are still merging.

Saeed Mahameed committed 7 years ago

Commit e08a9762 parents e2c7469 f8efee036 files · +786 −360Browse files

Showing the changes to include/linux (8 of 36 files). Show all

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8 files
  1. include/linux/mlx5/cq.h +3 −3
  2. include/linux/mlx5/device.h +19 −1
  3. include/linux/mlx5/driver.h +15 −7
  4. include/linux/mlx5/eq.h +1 −1
  5. include/linux/mlx5/eswitch.h +8 −3
  6. include/linux/mlx5/mlx5_ifc.h +289 −14
  7. include/linux/mlx5/qp.h +6 −1
  8. include/linux/mlx5/vport.h +3 −4
include/linux/mlx5/cq.h+3−3
@@ -47,7 +47,7 @@ struct mlx5_core_cq { · 46 unmodified lines
47 struct completion free;47 struct completion free;
48 unsigned vector;48 unsigned vector;
49 unsigned int irqn;49 unsigned int irqn;
50 void (*comp) (struct mlx5_core_cq *);50 void (*comp)(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe);
51 void (*event) (struct mlx5_core_cq *, enum mlx5_event);51 void (*event) (struct mlx5_core_cq *, enum mlx5_event);
52 u32 cons_index;52 u32 cons_index;
53 unsigned arm_sn;53 unsigned arm_sn;
@@ -55,7 +55,7 @@ struct mlx5_core_cq { · 1 unmodified line
55 int pid;55 int pid;
56 struct {56 struct {
57 struct list_head list;57 struct list_head list;
58 void (*comp)(struct mlx5_core_cq *);58 void (*comp)(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe);
59 void *priv;59 void *priv;
60 } tasklet_ctx;60 } tasklet_ctx;
61 int reset_notify_added;61 int reset_notify_added;
@@ -185,7 +185,7 @@ static inline void mlx5_cq_put(struct mlx5_core_cq *cq) · 123 unmodified lines
185}185}
186 186
187int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,187int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
188 u32 *in, int inlen);188 u32 *in, int inlen, u32 *out, int outlen);
189int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);189int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
190int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,190int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
191 u32 *out, int outlen);191 u32 *out, int outlen);
include/linux/mlx5/device.h+19−1
@@ -351,7 +351,7 @@ enum mlx5_event { · 350 unmodified lines
351 351
352 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,352 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
353 353
354 MLX5_EVENT_TYPE_MAX = MLX5_EVENT_TYPE_DEVICE_TRACER + 1,354 MLX5_EVENT_TYPE_MAX = 0x100,
355};355};
356 356
357enum {357enum {
@@ -437,6 +437,7 @@ enum { · 79 unmodified lines
437 MLX5_OPCODE_SET_PSV = 0x20,437 MLX5_OPCODE_SET_PSV = 0x20,
438 MLX5_OPCODE_GET_PSV = 0x21,438 MLX5_OPCODE_GET_PSV = 0x21,
439 MLX5_OPCODE_CHECK_PSV = 0x22,439 MLX5_OPCODE_CHECK_PSV = 0x22,
440 MLX5_OPCODE_DUMP = 0x23,
440 MLX5_OPCODE_RGET_PSV = 0x26,441 MLX5_OPCODE_RGET_PSV = 0x26,
441 MLX5_OPCODE_RCHECK_PSV = 0x27,442 MLX5_OPCODE_RCHECK_PSV = 0x27,
442 443
@@ -444,6 +445,14 @@ enum { · 1 unmodified line
444 445
445};446};
446 447
448enum {
449 MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x20,
450};
451
452enum {
453 MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x20,
454};
455
447enum {456enum {
448 MLX5_SET_PORT_RESET_QKEY = 0,457 MLX5_SET_PORT_RESET_QKEY = 0,
449 MLX5_SET_PORT_GUID0 = 16,458 MLX5_SET_PORT_GUID0 = 16,
@@ -1085,6 +1094,9 @@ enum mlx5_cap_type { · 635 unmodified lines
1085 MLX5_CAP_DEBUG,1094 MLX5_CAP_DEBUG,
1086 MLX5_CAP_RESERVED_14,1095 MLX5_CAP_RESERVED_14,
1087 MLX5_CAP_DEV_MEM,1096 MLX5_CAP_DEV_MEM,
1097 MLX5_CAP_RESERVED_16,
1098 MLX5_CAP_TLS,
1099 MLX5_CAP_DEV_EVENT = 0x14,
1088 /* NUM OF CAP Types */1100 /* NUM OF CAP Types */
1089 MLX5_CAP_NUM1101 MLX5_CAP_NUM
1090};1102};
@@ -1263,6 +1275,12 @@ enum mlx5_qcam_feature_groups { · 172 unmodified lines
1263#define MLX5_CAP64_DEV_MEM(mdev, cap)\1275#define MLX5_CAP64_DEV_MEM(mdev, cap)\
1264 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)1276 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1265 1277
1278#define MLX5_CAP_TLS(mdev, cap) \
1279 MLX5_GET(tls_cap, (mdev)->caps.hca_cur[MLX5_CAP_TLS], cap)
1280
1281#define MLX5_CAP_DEV_EVENT(mdev, cap)\
1282 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)
1283
1266enum {1284enum {
1267 MLX5_CMD_STAT_OK = 0x0,1285 MLX5_CMD_STAT_OK = 0x0,
1268 MLX5_CMD_STAT_INT_ERR = 0x1,1286 MLX5_CMD_STAT_INT_ERR = 0x1,
include/linux/mlx5/driver.h+15−7
@@ -139,6 +139,7 @@ enum { · 138 unmodified lines
139 MLX5_REG_MTPPS = 0x9053,139 MLX5_REG_MTPPS = 0x9053,
140 MLX5_REG_MTPPSE = 0x9054,140 MLX5_REG_MTPPSE = 0x9054,
141 MLX5_REG_MPEGC = 0x9056,141 MLX5_REG_MPEGC = 0x9056,
142 MLX5_REG_MCQS = 0x9060,
142 MLX5_REG_MCQI = 0x9061,143 MLX5_REG_MCQI = 0x9061,
143 MLX5_REG_MCC = 0x9062,144 MLX5_REG_MCC = 0x9062,
144 MLX5_REG_MCDA = 0x9063,145 MLX5_REG_MCDA = 0x9063,
@@ -182,6 +183,11 @@ enum port_state_policy { · 37 unmodified lines
182 MLX5_POLICY_INVALID = 0xffffffff183 MLX5_POLICY_INVALID = 0xffffffff
183};184};
184 185
186enum mlx5_coredev_type {
187 MLX5_COREDEV_PF,
188 MLX5_COREDEV_VF
189};
190
185struct mlx5_field_desc {191struct mlx5_field_desc {
186 struct dentry *dent;192 struct dentry *dent;
187 int i;193 int i;
@@ -468,7 +474,6 @@ struct mlx5_vf_context { · 280 unmodified lines
468struct mlx5_core_sriov {474struct mlx5_core_sriov {
469 struct mlx5_vf_context *vfs_ctx;475 struct mlx5_vf_context *vfs_ctx;
470 int num_vfs;476 int num_vfs;
471 int enabled_vfs;
472 u16 max_vfs;477 u16 max_vfs;
473};478};
474 479
@@ -572,7 +577,6 @@ struct mlx5_priv { · 97 unmodified lines
572 struct mlx5_core_sriov sriov;577 struct mlx5_core_sriov sriov;
573 struct mlx5_lag *lag;578 struct mlx5_lag *lag;
574 struct mlx5_devcom *devcom;579 struct mlx5_devcom *devcom;
575 unsigned long pci_dev_data;
576 struct mlx5_core_roce roce;580 struct mlx5_core_roce roce;
577 struct mlx5_fc_stats fc_stats;581 struct mlx5_fc_stats fc_stats;
578 struct mlx5_rl_table rl_table;582 struct mlx5_rl_table rl_table;
@@ -653,6 +657,7 @@ struct mlx5_geneve; · 74 unmodified lines
653 657
654struct mlx5_core_dev {658struct mlx5_core_dev {
655 struct device *device;659 struct device *device;
660 enum mlx5_coredev_type coredev_type;
656 struct pci_dev *pdev;661 struct pci_dev *pdev;
657 /* sync pci state */662 /* sync pci state */
658 struct mutex pci_status_mutex;663 struct mutex pci_status_mutex;
@@ -1047,6 +1052,8 @@ int mlx5_register_interface(struct mlx5_interface *intf); · 388 unmodified lines
1047void mlx5_unregister_interface(struct mlx5_interface *intf);1052void mlx5_unregister_interface(struct mlx5_interface *intf);
1048int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);1053int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1049int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);1054int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1055int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1056int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1050 1057
1051int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);1058int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1052 1059
@@ -1087,9 +1094,9 @@ enum { · 34 unmodified lines
1087 MLX5_PCI_DEV_IS_VF = 1 << 0,1094 MLX5_PCI_DEV_IS_VF = 1 << 0,
1088};1095};
1089 1096
1090static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)1097static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1091{1098{
1092 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);1099 return dev->coredev_type == MLX5_COREDEV_PF;
1093}1100}
1094 1101
1095static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev)1102static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev)
@@ -1097,17 +1104,18 @@ static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) · 1 unmodified line
1097 return dev->caps.embedded_cpu;1104 return dev->caps.embedded_cpu;
1098}1105}
1099 1106
1100static inline bool mlx5_core_is_ecpf_esw_manager(struct mlx5_core_dev *dev)1107static inline bool
1108mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1101{1109{
1102 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);1110 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1103}1111}
1104 1112
1105static inline bool mlx5_ecpf_vport_exists(struct mlx5_core_dev *dev)1113static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1106{1114{
1107 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);1115 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1108}1116}
1109 1117
1110static inline u16 mlx5_core_max_vfs(struct mlx5_core_dev *dev)1118static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1111{1119{
1112 return dev->priv.sriov.max_vfs;1120 return dev->priv.sriov.max_vfs;
1113}1121}
include/linux/mlx5/eq.h+1−1
@@ -15,7 +15,7 @@ struct mlx5_core_dev; · 14 unmodified lines
15struct mlx5_eq_param {15struct mlx5_eq_param {
16 u8 irq_index;16 u8 irq_index;
17 int nent;17 int nent;
18 u64 mask;18 u64 mask[4];
19};19};
20 20
21struct mlx5_eq *21struct mlx5_eq *
include/linux/mlx5/eswitch.h+8−3
@@ -12,9 +12,9 @@ · 11 unmodified lines
12#define MLX5_ESWITCH_MANAGER(mdev) MLX5_CAP_GEN(mdev, eswitch_manager)12#define MLX5_ESWITCH_MANAGER(mdev) MLX5_CAP_GEN(mdev, eswitch_manager)
13 13
14enum {14enum {
15 SRIOV_NONE,15 MLX5_ESWITCH_NONE,
16 SRIOV_LEGACY,16 MLX5_ESWITCH_LEGACY,
17 SRIOV_OFFLOADS17 MLX5_ESWITCH_OFFLOADS
18};18};
19 19
20enum {20enum {
@@ -46,6 +46,8 @@ struct mlx5_eswitch_rep { · 25 unmodified lines
46 u16 vport;46 u16 vport;
47 u8 hw_id[ETH_ALEN];47 u8 hw_id[ETH_ALEN];
48 u16 vlan;48 u16 vlan;
49 /* Only IB rep is using vport_index */
50 u16 vport_index;
49 u32 vlan_refcount;51 u32 vlan_refcount;
50};52};
51 53
@@ -64,6 +66,8 @@ struct mlx5_flow_handle * · 12 unmodified lines
64mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw,66mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw,
65 u16 vport_num, u32 sqn);67 u16 vport_num, u32 sqn);
66 68
69u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev);
70
67#ifdef CONFIG_MLX5_ESWITCH71#ifdef CONFIG_MLX5_ESWITCH
68enum devlink_eswitch_encap_mode72enum devlink_eswitch_encap_mode
69mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev);73mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev);
@@ -91,4 +95,5 @@ mlx5_eswitch_get_vport_metadata_for_match(const struct mlx5_eswitch *esw, · 21 unmodified lines
91 return 0;95 return 0;
92};96};
93#endif /* CONFIG_MLX5_ESWITCH */97#endif /* CONFIG_MLX5_ESWITCH */
98
94#endif99#endif
include/linux/mlx5/mlx5_ifc.h+289−14
@@ -91,6 +91,20 @@ enum { · 90 unmodified lines
91 91
92enum {92enum {
93 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,93 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
94 MLX5_OBJ_TYPE_MKEY = 0xff01,
95 MLX5_OBJ_TYPE_QP = 0xff02,
96 MLX5_OBJ_TYPE_PSV = 0xff03,
97 MLX5_OBJ_TYPE_RMP = 0xff04,
98 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
99 MLX5_OBJ_TYPE_RQ = 0xff06,
100 MLX5_OBJ_TYPE_SQ = 0xff07,
101 MLX5_OBJ_TYPE_TIR = 0xff08,
102 MLX5_OBJ_TYPE_TIS = 0xff09,
103 MLX5_OBJ_TYPE_DCT = 0xff0a,
104 MLX5_OBJ_TYPE_XRQ = 0xff0b,
105 MLX5_OBJ_TYPE_RQT = 0xff0e,
106 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
107 MLX5_OBJ_TYPE_CQ = 0xff10,
94};108};
95 109
96enum {110enum {
@@ -106,6 +120,9 @@ enum { · 9 unmodified lines
106 MLX5_CMD_OP_QUERY_ISSI = 0x10a,120 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
107 MLX5_CMD_OP_SET_ISSI = 0x10b,121 MLX5_CMD_OP_SET_ISSI = 0x10b,
108 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,122 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
123 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
124 MLX5_CMD_OP_ALLOC_SF = 0x113,
125 MLX5_CMD_OP_DEALLOC_SF = 0x114,
109 MLX5_CMD_OP_CREATE_MKEY = 0x200,126 MLX5_CMD_OP_CREATE_MKEY = 0x200,
110 MLX5_CMD_OP_QUERY_MKEY = 0x201,127 MLX5_CMD_OP_QUERY_MKEY = 0x201,
111 MLX5_CMD_OP_DESTROY_MKEY = 0x202,128 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
@@ -713,7 +730,11 @@ struct mlx5_ifc_e_switch_cap_bits { · 601 unmodified lines
713 u8 reserved_2b[0x6];730 u8 reserved_2b[0x6];
714 u8 max_encap_header_size[0xa];731 u8 max_encap_header_size[0xa];
715 732
716 u8 reserved_40[0x7c0];733 u8 reserved_at_40[0xb];
734 u8 log_max_esw_sf[0x5];
735 u8 esw_sf_base_id[0x10];
736
737 u8 reserved_at_60[0x7a0];
717 738
718};739};
719 740
@@ -853,6 +874,12 @@ struct mlx5_ifc_device_mem_cap_bits { · 133 unmodified lines
853 u8 reserved_at_180[0x680];874 u8 reserved_at_180[0x680];
854};875};
855 876
877struct mlx5_ifc_device_event_cap_bits {
878 u8 user_affiliated_events[4][0x40];
879
880 u8 user_unaffiliated_events[4][0x40];
881};
882
856enum {883enum {
857 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,884 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
858 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,885 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
@@ -946,6 +973,16 @@ struct mlx5_ifc_vector_calc_cap_bits { · 87 unmodified lines
946 u8 reserved_at_c0[0x720];973 u8 reserved_at_c0[0x720];
947};974};
948 975
976struct mlx5_ifc_tls_cap_bits {
977 u8 tls_1_2_aes_gcm_128[0x1];
978 u8 tls_1_3_aes_gcm_128[0x1];
979 u8 tls_1_2_aes_gcm_256[0x1];
980 u8 tls_1_3_aes_gcm_256[0x1];
981 u8 reserved_at_4[0x1c];
982
983 u8 reserved_at_20[0x7e0];
984};
985
949enum {986enum {
950 MLX5_WQ_TYPE_LINKED_LIST = 0x0,987 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
951 MLX5_WQ_TYPE_CYCLIC = 0x1,988 MLX5_WQ_TYPE_CYCLIC = 0x1,
@@ -1010,7 +1047,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 58 unmodified lines
1010 1047
1011 u8 log_max_srq_sz[0x8];1048 u8 log_max_srq_sz[0x8];
1012 u8 log_max_qp_sz[0x8];1049 u8 log_max_qp_sz[0x8];
1013 u8 reserved_at_90[0x8];1050 u8 event_cap[0x1];
1051 u8 reserved_at_91[0x7];
1014 u8 prio_tag_required[0x1];1052 u8 prio_tag_required[0x1];
1015 u8 reserved_at_99[0x2];1053 u8 reserved_at_99[0x2];
1016 u8 log_max_qp[0x5];1054 u8 log_max_qp[0x5];
@@ -1058,7 +1096,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 41 unmodified lines
1058 u8 cc_modify_allowed[0x1];1096 u8 cc_modify_allowed[0x1];
1059 u8 start_pad[0x1];1097 u8 start_pad[0x1];
1060 u8 cache_line_128byte[0x1];1098 u8 cache_line_128byte[0x1];
1061 u8 reserved_at_165[0xa];1099 u8 reserved_at_165[0x4];
1100 u8 rts2rts_qp_counters_set_id[0x1];
1101 u8 reserved_at_16a[0x5];
1062 u8 qcam_reg[0x1];1102 u8 qcam_reg[0x1];
1063 u8 gid_table_size[0x10];1103 u8 gid_table_size[0x10];
1064 1104
@@ -1275,7 +1315,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 210 unmodified lines
1275 1315
1276 u8 reserved_at_440[0x20];1316 u8 reserved_at_440[0x20];
1277 1317
1278 u8 reserved_at_460[0x3];1318 u8 tls[0x1];
1319 u8 reserved_at_461[0x2];
1279 u8 log_max_uctx[0x5];1320 u8 log_max_uctx[0x5];
1280 u8 reserved_at_468[0x3];1321 u8 reserved_at_468[0x3];
1281 u8 log_max_umem[0x5];1322 u8 log_max_umem[0x5];
@@ -1300,7 +1341,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 18 unmodified lines
1300 u8 max_geneve_tlv_option_data_len[0x5];1341 u8 max_geneve_tlv_option_data_len[0x5];
1301 u8 reserved_at_570[0x10];1342 u8 reserved_at_570[0x10];
1302 1343
1303 u8 reserved_at_580[0x3c];1344 u8 reserved_at_580[0x33];
1345 u8 log_max_dek[0x5];
1346 u8 reserved_at_5b8[0x4];
1304 u8 mini_cqe_resp_stride_index[0x1];1347 u8 mini_cqe_resp_stride_index[0x1];
1305 u8 cqe_128_always[0x1];1348 u8 cqe_128_always[0x1];
1306 u8 cqe_compression_128[0x1];1349 u8 cqe_compression_128[0x1];
@@ -1330,13 +1373,24 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 23 unmodified lines
1330 u8 reserved_at_640[0x10];1373 u8 reserved_at_640[0x10];
1331 u8 num_q_monitor_counters[0x10];1374 u8 num_q_monitor_counters[0x10];
1332 1375
1333 u8 reserved_at_660[0x40];1376 u8 reserved_at_660[0x20];
1377
1378 u8 sf[0x1];
1379 u8 sf_set_partition[0x1];
1380 u8 reserved_at_682[0x1];
1381 u8 log_max_sf[0x5];
1382 u8 reserved_at_688[0x8];
1383 u8 log_min_sf_size[0x8];
1384 u8 max_num_sf_partitions[0x8];
1334 1385
1335 u8 uctx_cap[0x20];1386 u8 uctx_cap[0x20];
1336 1387
1337 u8 reserved_at_6c0[0x4];1388 u8 reserved_at_6c0[0x4];
1338 u8 flex_parser_id_geneve_tlv_option_0[0x4];1389 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1339 u8 reserved_at_6c8[0x138];1390 u8 reserved_at_6c8[0x28];
1391 u8 sf_base_id[0x10];
1392
1393 u8 reserved_at_700[0x100];
1340};1394};
1341 1395
1342enum mlx5_flow_destination_type {1396enum mlx5_flow_destination_type {
@@ -2568,6 +2622,7 @@ union mlx5_ifc_hca_cap_union_bits { · 1225 unmodified lines
2568 struct mlx5_ifc_qos_cap_bits qos_cap;2622 struct mlx5_ifc_qos_cap_bits qos_cap;
2569 struct mlx5_ifc_debug_cap_bits debug_cap;2623 struct mlx5_ifc_debug_cap_bits debug_cap;
2570 struct mlx5_ifc_fpga_cap_bits fpga_cap;2624 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2625 struct mlx5_ifc_tls_cap_bits tls_cap;
2571 u8 reserved_at_0[0x8000];2626 u8 reserved_at_0[0x8000];
2572};2627};
2573 2628
@@ -2707,7 +2762,8 @@ struct mlx5_ifc_traffic_counter_bits { · 133 unmodified lines
2707 2762
2708struct mlx5_ifc_tisc_bits {2763struct mlx5_ifc_tisc_bits {
2709 u8 strict_lag_tx_port_affinity[0x1];2764 u8 strict_lag_tx_port_affinity[0x1];
2710 u8 reserved_at_1[0x3];2765 u8 tls_en[0x1];
2766 u8 reserved_at_1[0x2];
2711 u8 lag_tx_port_affinity[0x04];2767 u8 lag_tx_port_affinity[0x04];
2712 2768
2713 u8 reserved_at_8[0x4];2769 u8 reserved_at_8[0x4];
@@ -2721,7 +2777,11 @@ struct mlx5_ifc_tisc_bits { · 7 unmodified lines
2721 2777
2722 u8 reserved_at_140[0x8];2778 u8 reserved_at_140[0x8];
2723 u8 underlay_qpn[0x18];2779 u8 underlay_qpn[0x18];
2724 u8 reserved_at_160[0x3a0];2780
2781 u8 reserved_at_160[0x8];
2782 u8 pd[0x18];
2783
2784 u8 reserved_at_180[0x380];
2725};2785};
2726 2786
2727enum {2787enum {
@@ -7404,9 +7464,9 @@ struct mlx5_ifc_create_eq_in_bits { · 4676 unmodified lines
7404 7464
7405 u8 reserved_at_280[0x40];7465 u8 reserved_at_280[0x40];
7406 7466
7407 u8 event_bitmask[0x40];7467 u8 event_bitmask[4][0x40];
7408 7468
7409 u8 reserved_at_300[0x580];7469 u8 reserved_at_3c0[0x4c0];
7410 7470
7411 u8 pas[0][0x40];7471 u8 pas[0][0x40];
7412};7472};
@@ -8524,7 +8584,7 @@ struct mlx5_ifc_mcam_access_reg_bits { · 1111 unmodified lines
8524 u8 mcda[0x1];8584 u8 mcda[0x1];
8525 u8 mcc[0x1];8585 u8 mcc[0x1];
8526 u8 mcqi[0x1];8586 u8 mcqi[0x1];
8527 u8 reserved_at_1f[0x1];8587 u8 mcqs[0x1];
8528 8588
8529 u8 regs_95_to_87[0x9];8589 u8 regs_95_to_87[0x9];
8530 u8 mpegc[0x1];8590 u8 mpegc[0x1];
@@ -9016,6 +9076,24 @@ struct mlx5_ifc_mtppse_reg_bits { · 485 unmodified lines
9016 u8 reserved_at_40[0x40];9076 u8 reserved_at_40[0x40];
9017};9077};
9018 9078
9079struct mlx5_ifc_mcqs_reg_bits {
9080 u8 last_index_flag[0x1];
9081 u8 reserved_at_1[0x7];
9082 u8 fw_device[0x8];
9083 u8 component_index[0x10];
9084
9085 u8 reserved_at_20[0x10];
9086 u8 identifier[0x10];
9087
9088 u8 reserved_at_40[0x17];
9089 u8 component_status[0x5];
9090 u8 component_update_state[0x4];
9091
9092 u8 last_update_state_changer_type[0x4];
9093 u8 last_update_state_changer_host_id[0x4];
9094 u8 reserved_at_68[0x18];
9095};
9096
9019struct mlx5_ifc_mcqi_cap_bits {9097struct mlx5_ifc_mcqi_cap_bits {
9020 u8 supported_info_bitmask[0x20];9098 u8 supported_info_bitmask[0x20];
9021 9099
@@ -9036,6 +9114,43 @@ struct mlx5_ifc_mcqi_cap_bits { · 14 unmodified lines
9036 u8 reserved_at_86[0x1a];9114 u8 reserved_at_86[0x1a];
9037};9115};
9038 9116
9117struct mlx5_ifc_mcqi_version_bits {
9118 u8 reserved_at_0[0x2];
9119 u8 build_time_valid[0x1];
9120 u8 user_defined_time_valid[0x1];
9121 u8 reserved_at_4[0x14];
9122 u8 version_string_length[0x8];
9123
9124 u8 version[0x20];
9125
9126 u8 build_time[0x40];
9127
9128 u8 user_defined_time[0x40];
9129
9130 u8 build_tool_version[0x20];
9131
9132 u8 reserved_at_e0[0x20];
9133
9134 u8 version_string[92][0x8];
9135};
9136
9137struct mlx5_ifc_mcqi_activation_method_bits {
9138 u8 pending_server_ac_power_cycle[0x1];
9139 u8 pending_server_dc_power_cycle[0x1];
9140 u8 pending_server_reboot[0x1];
9141 u8 pending_fw_reset[0x1];
9142 u8 auto_activate[0x1];
9143 u8 all_hosts_sync[0x1];
9144 u8 device_hw_reset[0x1];
9145 u8 reserved_at_7[0x19];
9146};
9147
9148union mlx5_ifc_mcqi_reg_data_bits {
9149 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9150 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9151 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9152};
9153
9039struct mlx5_ifc_mcqi_reg_bits {9154struct mlx5_ifc_mcqi_reg_bits {
9040 u8 read_pending_component[0x1];9155 u8 read_pending_component[0x1];
9041 u8 reserved_at_1[0xf];9156 u8 reserved_at_1[0xf];
@@ -9053,7 +9168,7 @@ struct mlx5_ifc_mcqi_reg_bits { · 11 unmodified lines
9053 u8 reserved_at_a0[0x10];9168 u8 reserved_at_a0[0x10];
9054 u8 data_size[0x10];9169 u8 data_size[0x10];
9055 9170
9056 u8 data[0][0x20];9171 union mlx5_ifc_mcqi_reg_data_bits data[0];
9057};9172};
9058 9173
9059struct mlx5_ifc_mcc_reg_bits {9174struct mlx5_ifc_mcc_reg_bits {
@@ -9750,7 +9865,8 @@ struct mlx5_ifc_mtrc_ctrl_bits { · 690 unmodified lines
9750 9865
9751struct mlx5_ifc_host_params_context_bits {9866struct mlx5_ifc_host_params_context_bits {
9752 u8 host_number[0x8];9867 u8 host_number[0x8];
9753 u8 reserved_at_8[0x8];9868 u8 reserved_at_8[0x7];
9869 u8 host_pf_disabled[0x1];
9754 u8 host_num_of_vfs[0x10];9870 u8 host_num_of_vfs[0x10];
9755 9871
9756 u8 host_total_vfs[0x10];9872 u8 host_total_vfs[0x10];
@@ -9786,6 +9902,165 @@ struct mlx5_ifc_query_esw_functions_out_bits { · 29 unmodified lines
9786 struct mlx5_ifc_host_params_context_bits host_params_context;9902 struct mlx5_ifc_host_params_context_bits host_params_context;
9787 9903
9788 u8 reserved_at_280[0x180];9904 u8 reserved_at_280[0x180];
9905 u8 host_sf_enable[0][0x40];
9906};
9907
9908struct mlx5_ifc_sf_partition_bits {
9909 u8 reserved_at_0[0x10];
9910 u8 log_num_sf[0x8];
9911 u8 log_sf_bar_size[0x8];
9912};
9913
9914struct mlx5_ifc_query_sf_partitions_out_bits {
9915 u8 status[0x8];
9916 u8 reserved_at_8[0x18];
9917
9918 u8 syndrome[0x20];
9919
9920 u8 reserved_at_40[0x18];
9921 u8 num_sf_partitions[0x8];
9922
9923 u8 reserved_at_60[0x20];
9924
9925 struct mlx5_ifc_sf_partition_bits sf_partition[0];
9926};
9927
9928struct mlx5_ifc_query_sf_partitions_in_bits {
9929 u8 opcode[0x10];
9930 u8 reserved_at_10[0x10];
9931
9932 u8 reserved_at_20[0x10];
9933 u8 op_mod[0x10];
9934
9935 u8 reserved_at_40[0x40];
9936};
9937
9938struct mlx5_ifc_dealloc_sf_out_bits {
9939 u8 status[0x8];
9940 u8 reserved_at_8[0x18];
9941
9942 u8 syndrome[0x20];
9943
9944 u8 reserved_at_40[0x40];
9945};
9946
9947struct mlx5_ifc_dealloc_sf_in_bits {
9948 u8 opcode[0x10];
9949 u8 reserved_at_10[0x10];
9950
9951 u8 reserved_at_20[0x10];
9952 u8 op_mod[0x10];
9953
9954 u8 reserved_at_40[0x10];
9955 u8 function_id[0x10];
9956
9957 u8 reserved_at_60[0x20];
9958};
9959
9960struct mlx5_ifc_alloc_sf_out_bits {
9961 u8 status[0x8];
9962 u8 reserved_at_8[0x18];
9963
9964 u8 syndrome[0x20];
9965
9966 u8 reserved_at_40[0x40];
9967};
9968
9969struct mlx5_ifc_alloc_sf_in_bits {
9970 u8 opcode[0x10];
9971 u8 reserved_at_10[0x10];
9972
9973 u8 reserved_at_20[0x10];
9974 u8 op_mod[0x10];
9975
9976 u8 reserved_at_40[0x10];
9977 u8 function_id[0x10];
9978
9979 u8 reserved_at_60[0x20];
9980};
9981
9982struct mlx5_ifc_affiliated_event_header_bits {
9983 u8 reserved_at_0[0x10];
9984 u8 obj_type[0x10];
9985
9986 u8 obj_id[0x20];
9987};
9988
9989enum {
9990 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
9991};
9992
9993enum {
9994 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
9995};
9996
9997struct mlx5_ifc_encryption_key_obj_bits {
9998 u8 modify_field_select[0x40];
9999
10000 u8 reserved_at_40[0x14];
10001 u8 key_size[0x4];
10002 u8 reserved_at_58[0x4];
10003 u8 key_type[0x4];
10004
10005 u8 reserved_at_60[0x8];
10006 u8 pd[0x18];
10007
10008 u8 reserved_at_80[0x180];
10009 u8 key[8][0x20];
10010
10011 u8 reserved_at_300[0x500];
10012};
10013
10014struct mlx5_ifc_create_encryption_key_in_bits {
10015 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10016 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10017};
10018
10019enum {
10020 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10021 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10022};
10023
10024enum {
10025 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10026};
10027
10028struct mlx5_ifc_tls_static_params_bits {
10029 u8 const_2[0x2];
10030 u8 tls_version[0x4];
10031 u8 const_1[0x2];
10032 u8 reserved_at_8[0x14];
10033 u8 encryption_standard[0x4];
10034
10035 u8 reserved_at_20[0x20];
10036
10037 u8 initial_record_number[0x40];
10038
10039 u8 resync_tcp_sn[0x20];
10040
10041 u8 gcm_iv[0x20];
10042
10043 u8 implicit_iv[0x40];
10044
10045 u8 reserved_at_100[0x8];
10046 u8 dek_index[0x18];
10047
10048 u8 reserved_at_120[0xe0];
10049};
10050
10051struct mlx5_ifc_tls_progress_params_bits {
10052 u8 valid[0x1];
10053 u8 reserved_at_1[0x7];
10054 u8 pd[0x18];
10055
10056 u8 next_record_tcp_sn[0x20];
10057
10058 u8 hw_resync_tcp_sn[0x20];
10059
10060 u8 record_tracker_state[0x2];
10061 u8 auth_state[0x2];
10062 u8 reserved_at_64[0x4];
10063 u8 hw_offset_record_number[0x18];
9789};10064};
9790 10065
9791#endif /* MLX5_IFC_H */10066#endif /* MLX5_IFC_H */
include/linux/mlx5/qp.h+6−1
@@ -202,7 +202,12 @@ struct mlx5_wqe_ctrl_seg { · 201 unmodified lines
202 u8 signature;202 u8 signature;
203 u8 rsvd[2];203 u8 rsvd[2];
204 u8 fm_ce_se;204 u8 fm_ce_se;
205 __be32 imm;205 union {
206 __be32 general_id;
207 __be32 imm;
208 __be32 umr_mkey;
209 __be32 tisn;
210 };
206};211};
207 212
208#define MLX5_WQE_CTRL_DS_MASK 0x3f213#define MLX5_WQE_CTRL_DS_MASK 0x3f
include/linux/mlx5/vport.h+3−4
@@ -44,9 +44,6 @@ · 43 unmodified lines
44 MLX5_VPORT_UPLINK_PLACEHOLDER + \44 MLX5_VPORT_UPLINK_PLACEHOLDER + \
45 MLX5_VPORT_ECPF_PLACEHOLDER(mdev))45 MLX5_VPORT_ECPF_PLACEHOLDER(mdev))
46 46
47#define MLX5_TOTAL_VPORTS(mdev) (MLX5_SPECIAL_VPORTS(mdev) + \
48 mlx5_core_max_vfs(mdev))
49
50#define MLX5_VPORT_MANAGER(mdev) \47#define MLX5_VPORT_MANAGER(mdev) \
51 (MLX5_CAP_GEN(mdev, vport_group_manager) && \48 (MLX5_CAP_GEN(mdev, vport_group_manager) && \
52 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \49 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \
@@ -58,6 +55,7 @@ enum { · 5 unmodified lines
58 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,55 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
59};56};
60 57
58/* Vport number for each function must keep unchanged */
61enum {59enum {
62 MLX5_VPORT_PF = 0x0,60 MLX5_VPORT_PF = 0x0,
63 MLX5_VPORT_FIRST_VF = 0x1,61 MLX5_VPORT_FIRST_VF = 0x1,
@@ -69,7 +67,8 @@ u8 mlx5_query_vport_state(struct mlx5_core_dev *mdev, u8 opmod, u16 vport); · 5 unmodified lines
69int mlx5_modify_vport_admin_state(struct mlx5_core_dev *mdev, u8 opmod,67int mlx5_modify_vport_admin_state(struct mlx5_core_dev *mdev, u8 opmod,
70 u16 vport, u8 other_vport, u8 state);68 u16 vport, u8 other_vport, u8 state);
71int mlx5_query_nic_vport_mac_address(struct mlx5_core_dev *mdev,69int mlx5_query_nic_vport_mac_address(struct mlx5_core_dev *mdev,
72 u16 vport, u8 *addr);70 u16 vport, bool other, u8 *addr);
71int mlx5_query_mac_address(struct mlx5_core_dev *mdev, u8 *addr);
73int mlx5_query_nic_vport_min_inline(struct mlx5_core_dev *mdev,72int mlx5_query_nic_vport_min_inline(struct mlx5_core_dev *mdev,
74 u16 vport, u8 *min_inline);73 u16 vport, u8 *min_inline);
75void mlx5_query_min_inline(struct mlx5_core_dev *mdev, u8 *min_inline);74void mlx5_query_min_inline(struct mlx5_core_dev *mdev, u8 *min_inline);

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