History

Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux

Misc updates from mlx5-next branch: 1) Add the required HW definitions and structures for upcoming TLS support. 2) Add support for MCQI and MCQS hardware registers for fw version query. 3) Added hardware bits and structures definitions for sub-functions 4) Small code cleanup and improvement for PF pci driver. 5) Bluefield (ECPF) updates and refactoring for better E-Switch management on ECPF embedded CPU NIC: 5.1) Consolidate querying eswitch number of VFs 5.2) Register event handler at the correct E-Switch init stage 5.3) Setup PF's inline mode and vlan pop when the ECPF is the E-Swtich manager ( the host PF is basically a VF ). 5.4) Handle Vport UC address changes in switchdev mode. 6) Cleanup the rep and netdev reference when unloading IB rep. Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> i# All conflicts fixed but you are still merging.

Saeed Mahameed committed 7 years ago

Commit e08a9762 parents e2c7469 f8efee036 files · +786 −360Browse files

Showing the changes to include/linux (8 of 36 files). Show all

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8 files
  1. include/linux/mlx5/cq.h +3 −3
  2. include/linux/mlx5/device.h +19 −1
  3. include/linux/mlx5/driver.h +15 −7
  4. include/linux/mlx5/eq.h +1 −1
  5. include/linux/mlx5/eswitch.h +8 −3
  6. include/linux/mlx5/mlx5_ifc.h +289 −14
  7. include/linux/mlx5/qp.h +6 −1
  8. include/linux/mlx5/vport.h +3 −4
include/linux/mlx5/cq.h+3−3
@@ -47,7 +47,7 @@ struct mlx5_core_cq { · 46 unmodified lines
4747 struct completion free;
4848 unsigned vector;
4949 unsigned int irqn;
50− void (*comp) (struct mlx5_core_cq *);
50+ void (*comp)(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe);
5151 void (*event) (struct mlx5_core_cq *, enum mlx5_event);
5252 u32 cons_index;
5353 unsigned arm_sn;
@@ -55,7 +55,7 @@ struct mlx5_core_cq { · 1 unmodified line
5555 int pid;
5656 struct {
5757 struct list_head list;
58− void (*comp)(struct mlx5_core_cq *);
58+ void (*comp)(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe);
5959 void *priv;
6060 } tasklet_ctx;
6161 int reset_notify_added;
@@ -185,7 +185,7 @@ static inline void mlx5_cq_put(struct mlx5_core_cq *cq) · 123 unmodified lines
185185 }
186186
187187 int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
188− u32 *in, int inlen);
188+ u32 *in, int inlen, u32 *out, int outlen);
189189 int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
190190 int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
191191 u32 *out, int outlen);
include/linux/mlx5/device.h+19−1
@@ -351,7 +351,7 @@ enum mlx5_event { · 350 unmodified lines
351351
352352 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
353353
354− MLX5_EVENT_TYPE_MAX = MLX5_EVENT_TYPE_DEVICE_TRACER + 1,
354+ MLX5_EVENT_TYPE_MAX = 0x100,
355355 };
356356
357357 enum {
@@ -437,6 +437,7 @@ enum { · 79 unmodified lines
437437 MLX5_OPCODE_SET_PSV = 0x20,
438438 MLX5_OPCODE_GET_PSV = 0x21,
439439 MLX5_OPCODE_CHECK_PSV = 0x22,
440+ MLX5_OPCODE_DUMP = 0x23,
440441 MLX5_OPCODE_RGET_PSV = 0x26,
441442 MLX5_OPCODE_RCHECK_PSV = 0x27,
442443
@@ -444,6 +445,14 @@ enum { · 1 unmodified line
444445
445446 };
446447
448+enum {
449+ MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x20,
450+};
451+
452+enum {
453+ MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x20,
454+};
455+
447456 enum {
448457 MLX5_SET_PORT_RESET_QKEY = 0,
449458 MLX5_SET_PORT_GUID0 = 16,
@@ -1085,6 +1094,9 @@ enum mlx5_cap_type { · 635 unmodified lines
10851094 MLX5_CAP_DEBUG,
10861095 MLX5_CAP_RESERVED_14,
10871096 MLX5_CAP_DEV_MEM,
1097+ MLX5_CAP_RESERVED_16,
1098+ MLX5_CAP_TLS,
1099+ MLX5_CAP_DEV_EVENT = 0x14,
10881100 /* NUM OF CAP Types */
10891101 MLX5_CAP_NUM
10901102 };
@@ -1263,6 +1275,12 @@ enum mlx5_qcam_feature_groups { · 172 unmodified lines
12631275 #define MLX5_CAP64_DEV_MEM(mdev, cap)\
12641276 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
12651277
1278+#define MLX5_CAP_TLS(mdev, cap) \
1279+ MLX5_GET(tls_cap, (mdev)->caps.hca_cur[MLX5_CAP_TLS], cap)
1280+
1281+#define MLX5_CAP_DEV_EVENT(mdev, cap)\
1282+ MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)
1283+
12661284 enum {
12671285 MLX5_CMD_STAT_OK = 0x0,
12681286 MLX5_CMD_STAT_INT_ERR = 0x1,
include/linux/mlx5/driver.h+15−7
@@ -139,6 +139,7 @@ enum { · 138 unmodified lines
139139 MLX5_REG_MTPPS = 0x9053,
140140 MLX5_REG_MTPPSE = 0x9054,
141141 MLX5_REG_MPEGC = 0x9056,
142+ MLX5_REG_MCQS = 0x9060,
142143 MLX5_REG_MCQI = 0x9061,
143144 MLX5_REG_MCC = 0x9062,
144145 MLX5_REG_MCDA = 0x9063,
@@ -182,6 +183,11 @@ enum port_state_policy { · 37 unmodified lines
182183 MLX5_POLICY_INVALID = 0xffffffff
183184 };
184185
186+enum mlx5_coredev_type {
187+ MLX5_COREDEV_PF,
188+ MLX5_COREDEV_VF
189+};
190+
185191 struct mlx5_field_desc {
186192 struct dentry *dent;
187193 int i;
@@ -468,7 +474,6 @@ struct mlx5_vf_context { · 280 unmodified lines
468474 struct mlx5_core_sriov {
469475 struct mlx5_vf_context *vfs_ctx;
470476 int num_vfs;
471− int enabled_vfs;
472477 u16 max_vfs;
473478 };
474479
@@ -572,7 +577,6 @@ struct mlx5_priv { · 97 unmodified lines
572577 struct mlx5_core_sriov sriov;
573578 struct mlx5_lag *lag;
574579 struct mlx5_devcom *devcom;
575− unsigned long pci_dev_data;
576580 struct mlx5_core_roce roce;
577581 struct mlx5_fc_stats fc_stats;
578582 struct mlx5_rl_table rl_table;
@@ -653,6 +657,7 @@ struct mlx5_geneve; · 74 unmodified lines
653657
654658 struct mlx5_core_dev {
655659 struct device *device;
660+ enum mlx5_coredev_type coredev_type;
656661 struct pci_dev *pdev;
657662 /* sync pci state */
658663 struct mutex pci_status_mutex;
@@ -1047,6 +1052,8 @@ int mlx5_register_interface(struct mlx5_interface *intf); · 388 unmodified lines
10471052 void mlx5_unregister_interface(struct mlx5_interface *intf);
10481053 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
10491054 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1055+int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1056+int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
10501057
10511058 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
10521059
@@ -1087,9 +1094,9 @@ enum { · 34 unmodified lines
10871094 MLX5_PCI_DEV_IS_VF = 1 << 0,
10881095 };
10891096
1090−static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1097+static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
10911098 {
1092− return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1099+ return dev->coredev_type == MLX5_COREDEV_PF;
10931100 }
10941101
10951102 static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev)
@@ -1097,17 +1104,18 @@ static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) · 1 unmodified line
10971104 return dev->caps.embedded_cpu;
10981105 }
10991106
1100−static inline bool mlx5_core_is_ecpf_esw_manager(struct mlx5_core_dev *dev)
1107+static inline bool
1108+mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
11011109 {
11021110 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
11031111 }
11041112
1105−static inline bool mlx5_ecpf_vport_exists(struct mlx5_core_dev *dev)
1113+static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
11061114 {
11071115 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
11081116 }
11091117
1110−static inline u16 mlx5_core_max_vfs(struct mlx5_core_dev *dev)
1118+static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
11111119 {
11121120 return dev->priv.sriov.max_vfs;
11131121 }
include/linux/mlx5/eq.h+1−1
@@ -15,7 +15,7 @@ struct mlx5_core_dev; · 14 unmodified lines
1515 struct mlx5_eq_param {
1616 u8 irq_index;
1717 int nent;
18− u64 mask;
18+ u64 mask[4];
1919 };
2020
2121 struct mlx5_eq *
include/linux/mlx5/eswitch.h+8−3
@@ -12,9 +12,9 @@ · 11 unmodified lines
1212 #define MLX5_ESWITCH_MANAGER(mdev) MLX5_CAP_GEN(mdev, eswitch_manager)
1313
1414 enum {
15− SRIOV_NONE,
16− SRIOV_LEGACY,
17− SRIOV_OFFLOADS
15+ MLX5_ESWITCH_NONE,
16+ MLX5_ESWITCH_LEGACY,
17+ MLX5_ESWITCH_OFFLOADS
1818 };
1919
2020 enum {
@@ -46,6 +46,8 @@ struct mlx5_eswitch_rep { · 25 unmodified lines
4646 u16 vport;
4747 u8 hw_id[ETH_ALEN];
4848 u16 vlan;
49+ /* Only IB rep is using vport_index */
50+ u16 vport_index;
4951 u32 vlan_refcount;
5052 };
5153
@@ -64,6 +66,8 @@ struct mlx5_flow_handle * · 12 unmodified lines
6466 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw,
6567 u16 vport_num, u32 sqn);
6668
69+u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev);
70+
6771 #ifdef CONFIG_MLX5_ESWITCH
6872 enum devlink_eswitch_encap_mode
6973 mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev);
@@ -91,4 +95,5 @@ mlx5_eswitch_get_vport_metadata_for_match(const struct mlx5_eswitch *esw, · 21 unmodified lines
9195 return 0;
9296 };
9397 #endif /* CONFIG_MLX5_ESWITCH */
98+
9499 #endif
include/linux/mlx5/mlx5_ifc.h+289−14
@@ -91,6 +91,20 @@ enum { · 90 unmodified lines
9191
9292 enum {
9393 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
94+ MLX5_OBJ_TYPE_MKEY = 0xff01,
95+ MLX5_OBJ_TYPE_QP = 0xff02,
96+ MLX5_OBJ_TYPE_PSV = 0xff03,
97+ MLX5_OBJ_TYPE_RMP = 0xff04,
98+ MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
99+ MLX5_OBJ_TYPE_RQ = 0xff06,
100+ MLX5_OBJ_TYPE_SQ = 0xff07,
101+ MLX5_OBJ_TYPE_TIR = 0xff08,
102+ MLX5_OBJ_TYPE_TIS = 0xff09,
103+ MLX5_OBJ_TYPE_DCT = 0xff0a,
104+ MLX5_OBJ_TYPE_XRQ = 0xff0b,
105+ MLX5_OBJ_TYPE_RQT = 0xff0e,
106+ MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
107+ MLX5_OBJ_TYPE_CQ = 0xff10,
94108 };
95109
96110 enum {
@@ -106,6 +120,9 @@ enum { · 9 unmodified lines
106120 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
107121 MLX5_CMD_OP_SET_ISSI = 0x10b,
108122 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
123+ MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
124+ MLX5_CMD_OP_ALLOC_SF = 0x113,
125+ MLX5_CMD_OP_DEALLOC_SF = 0x114,
109126 MLX5_CMD_OP_CREATE_MKEY = 0x200,
110127 MLX5_CMD_OP_QUERY_MKEY = 0x201,
111128 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
@@ -713,7 +730,11 @@ struct mlx5_ifc_e_switch_cap_bits { · 601 unmodified lines
713730 u8 reserved_2b[0x6];
714731 u8 max_encap_header_size[0xa];
715732
716− u8 reserved_40[0x7c0];
733+ u8 reserved_at_40[0xb];
734+ u8 log_max_esw_sf[0x5];
735+ u8 esw_sf_base_id[0x10];
736+
737+ u8 reserved_at_60[0x7a0];
717738
718739 };
719740
@@ -853,6 +874,12 @@ struct mlx5_ifc_device_mem_cap_bits { · 133 unmodified lines
853874 u8 reserved_at_180[0x680];
854875 };
855876
877+struct mlx5_ifc_device_event_cap_bits {
878+ u8 user_affiliated_events[4][0x40];
879+
880+ u8 user_unaffiliated_events[4][0x40];
881+};
882+
856883 enum {
857884 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
858885 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
@@ -946,6 +973,16 @@ struct mlx5_ifc_vector_calc_cap_bits { · 87 unmodified lines
946973 u8 reserved_at_c0[0x720];
947974 };
948975
976+struct mlx5_ifc_tls_cap_bits {
977+ u8 tls_1_2_aes_gcm_128[0x1];
978+ u8 tls_1_3_aes_gcm_128[0x1];
979+ u8 tls_1_2_aes_gcm_256[0x1];
980+ u8 tls_1_3_aes_gcm_256[0x1];
981+ u8 reserved_at_4[0x1c];
982+
983+ u8 reserved_at_20[0x7e0];
984+};
985+
949986 enum {
950987 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
951988 MLX5_WQ_TYPE_CYCLIC = 0x1,
@@ -1010,7 +1047,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 58 unmodified lines
10101047
10111048 u8 log_max_srq_sz[0x8];
10121049 u8 log_max_qp_sz[0x8];
1013− u8 reserved_at_90[0x8];
1050+ u8 event_cap[0x1];
1051+ u8 reserved_at_91[0x7];
10141052 u8 prio_tag_required[0x1];
10151053 u8 reserved_at_99[0x2];
10161054 u8 log_max_qp[0x5];
@@ -1058,7 +1096,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 41 unmodified lines
10581096 u8 cc_modify_allowed[0x1];
10591097 u8 start_pad[0x1];
10601098 u8 cache_line_128byte[0x1];
1061− u8 reserved_at_165[0xa];
1099+ u8 reserved_at_165[0x4];
1100+ u8 rts2rts_qp_counters_set_id[0x1];
1101+ u8 reserved_at_16a[0x5];
10621102 u8 qcam_reg[0x1];
10631103 u8 gid_table_size[0x10];
10641104
@@ -1275,7 +1315,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 210 unmodified lines
12751315
12761316 u8 reserved_at_440[0x20];
12771317
1278− u8 reserved_at_460[0x3];
1318+ u8 tls[0x1];
1319+ u8 reserved_at_461[0x2];
12791320 u8 log_max_uctx[0x5];
12801321 u8 reserved_at_468[0x3];
12811322 u8 log_max_umem[0x5];
@@ -1300,7 +1341,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 18 unmodified lines
13001341 u8 max_geneve_tlv_option_data_len[0x5];
13011342 u8 reserved_at_570[0x10];
13021343
1303− u8 reserved_at_580[0x3c];
1344+ u8 reserved_at_580[0x33];
1345+ u8 log_max_dek[0x5];
1346+ u8 reserved_at_5b8[0x4];
13041347 u8 mini_cqe_resp_stride_index[0x1];
13051348 u8 cqe_128_always[0x1];
13061349 u8 cqe_compression_128[0x1];
@@ -1330,13 +1373,24 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 23 unmodified lines
13301373 u8 reserved_at_640[0x10];
13311374 u8 num_q_monitor_counters[0x10];
13321375
1333− u8 reserved_at_660[0x40];
1376+ u8 reserved_at_660[0x20];
1377+
1378+ u8 sf[0x1];
1379+ u8 sf_set_partition[0x1];
1380+ u8 reserved_at_682[0x1];
1381+ u8 log_max_sf[0x5];
1382+ u8 reserved_at_688[0x8];
1383+ u8 log_min_sf_size[0x8];
1384+ u8 max_num_sf_partitions[0x8];
13341385
13351386 u8 uctx_cap[0x20];
13361387
13371388 u8 reserved_at_6c0[0x4];
13381389 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1339− u8 reserved_at_6c8[0x138];
1390+ u8 reserved_at_6c8[0x28];
1391+ u8 sf_base_id[0x10];
1392+
1393+ u8 reserved_at_700[0x100];
13401394 };
13411395
13421396 enum mlx5_flow_destination_type {
@@ -2568,6 +2622,7 @@ union mlx5_ifc_hca_cap_union_bits { · 1225 unmodified lines
25682622 struct mlx5_ifc_qos_cap_bits qos_cap;
25692623 struct mlx5_ifc_debug_cap_bits debug_cap;
25702624 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2625+ struct mlx5_ifc_tls_cap_bits tls_cap;
25712626 u8 reserved_at_0[0x8000];
25722627 };
25732628
@@ -2707,7 +2762,8 @@ struct mlx5_ifc_traffic_counter_bits { · 133 unmodified lines
27072762
27082763 struct mlx5_ifc_tisc_bits {
27092764 u8 strict_lag_tx_port_affinity[0x1];
2710− u8 reserved_at_1[0x3];
2765+ u8 tls_en[0x1];
2766+ u8 reserved_at_1[0x2];
27112767 u8 lag_tx_port_affinity[0x04];
27122768
27132769 u8 reserved_at_8[0x4];
@@ -2721,7 +2777,11 @@ struct mlx5_ifc_tisc_bits { · 7 unmodified lines
27212777
27222778 u8 reserved_at_140[0x8];
27232779 u8 underlay_qpn[0x18];
2724− u8 reserved_at_160[0x3a0];
2780+
2781+ u8 reserved_at_160[0x8];
2782+ u8 pd[0x18];
2783+
2784+ u8 reserved_at_180[0x380];
27252785 };
27262786
27272787 enum {
@@ -7404,9 +7464,9 @@ struct mlx5_ifc_create_eq_in_bits { · 4676 unmodified lines
74047464
74057465 u8 reserved_at_280[0x40];
74067466
7407− u8 event_bitmask[0x40];
7467+ u8 event_bitmask[4][0x40];
74087468
7409− u8 reserved_at_300[0x580];
7469+ u8 reserved_at_3c0[0x4c0];
74107470
74117471 u8 pas[0][0x40];
74127472 };
@@ -8524,7 +8584,7 @@ struct mlx5_ifc_mcam_access_reg_bits { · 1111 unmodified lines
85248584 u8 mcda[0x1];
85258585 u8 mcc[0x1];
85268586 u8 mcqi[0x1];
8527− u8 reserved_at_1f[0x1];
8587+ u8 mcqs[0x1];
85288588
85298589 u8 regs_95_to_87[0x9];
85308590 u8 mpegc[0x1];
@@ -9016,6 +9076,24 @@ struct mlx5_ifc_mtppse_reg_bits { · 485 unmodified lines
90169076 u8 reserved_at_40[0x40];
90179077 };
90189078
9079+struct mlx5_ifc_mcqs_reg_bits {
9080+ u8 last_index_flag[0x1];
9081+ u8 reserved_at_1[0x7];
9082+ u8 fw_device[0x8];
9083+ u8 component_index[0x10];
9084+
9085+ u8 reserved_at_20[0x10];
9086+ u8 identifier[0x10];
9087+
9088+ u8 reserved_at_40[0x17];
9089+ u8 component_status[0x5];
9090+ u8 component_update_state[0x4];
9091+
9092+ u8 last_update_state_changer_type[0x4];
9093+ u8 last_update_state_changer_host_id[0x4];
9094+ u8 reserved_at_68[0x18];
9095+};
9096+
90199097 struct mlx5_ifc_mcqi_cap_bits {
90209098 u8 supported_info_bitmask[0x20];
90219099
@@ -9036,6 +9114,43 @@ struct mlx5_ifc_mcqi_cap_bits { · 14 unmodified lines
90369114 u8 reserved_at_86[0x1a];
90379115 };
90389116
9117+struct mlx5_ifc_mcqi_version_bits {
9118+ u8 reserved_at_0[0x2];
9119+ u8 build_time_valid[0x1];
9120+ u8 user_defined_time_valid[0x1];
9121+ u8 reserved_at_4[0x14];
9122+ u8 version_string_length[0x8];
9123+
9124+ u8 version[0x20];
9125+
9126+ u8 build_time[0x40];
9127+
9128+ u8 user_defined_time[0x40];
9129+
9130+ u8 build_tool_version[0x20];
9131+
9132+ u8 reserved_at_e0[0x20];
9133+
9134+ u8 version_string[92][0x8];
9135+};
9136+
9137+struct mlx5_ifc_mcqi_activation_method_bits {
9138+ u8 pending_server_ac_power_cycle[0x1];
9139+ u8 pending_server_dc_power_cycle[0x1];
9140+ u8 pending_server_reboot[0x1];
9141+ u8 pending_fw_reset[0x1];
9142+ u8 auto_activate[0x1];
9143+ u8 all_hosts_sync[0x1];
9144+ u8 device_hw_reset[0x1];
9145+ u8 reserved_at_7[0x19];
9146+};
9147+
9148+union mlx5_ifc_mcqi_reg_data_bits {
9149+ struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9150+ struct mlx5_ifc_mcqi_version_bits mcqi_version;
9151+ struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9152+};
9153+
90399154 struct mlx5_ifc_mcqi_reg_bits {
90409155 u8 read_pending_component[0x1];
90419156 u8 reserved_at_1[0xf];
@@ -9053,7 +9168,7 @@ struct mlx5_ifc_mcqi_reg_bits { · 11 unmodified lines
90539168 u8 reserved_at_a0[0x10];
90549169 u8 data_size[0x10];
90559170
9056− u8 data[0][0x20];
9171+ union mlx5_ifc_mcqi_reg_data_bits data[0];
90579172 };
90589173
90599174 struct mlx5_ifc_mcc_reg_bits {
@@ -9750,7 +9865,8 @@ struct mlx5_ifc_mtrc_ctrl_bits { · 690 unmodified lines
97509865
97519866 struct mlx5_ifc_host_params_context_bits {
97529867 u8 host_number[0x8];
9753− u8 reserved_at_8[0x8];
9868+ u8 reserved_at_8[0x7];
9869+ u8 host_pf_disabled[0x1];
97549870 u8 host_num_of_vfs[0x10];
97559871
97569872 u8 host_total_vfs[0x10];
@@ -9786,6 +9902,165 @@ struct mlx5_ifc_query_esw_functions_out_bits { · 29 unmodified lines
97869902 struct mlx5_ifc_host_params_context_bits host_params_context;
97879903
97889904 u8 reserved_at_280[0x180];
9905+ u8 host_sf_enable[0][0x40];
9906+};
9907+
9908+struct mlx5_ifc_sf_partition_bits {
9909+ u8 reserved_at_0[0x10];
9910+ u8 log_num_sf[0x8];
9911+ u8 log_sf_bar_size[0x8];
9912+};
9913+
9914+struct mlx5_ifc_query_sf_partitions_out_bits {
9915+ u8 status[0x8];
9916+ u8 reserved_at_8[0x18];
9917+
9918+ u8 syndrome[0x20];
9919+
9920+ u8 reserved_at_40[0x18];
9921+ u8 num_sf_partitions[0x8];
9922+
9923+ u8 reserved_at_60[0x20];
9924+
9925+ struct mlx5_ifc_sf_partition_bits sf_partition[0];
9926+};
9927+
9928+struct mlx5_ifc_query_sf_partitions_in_bits {
9929+ u8 opcode[0x10];
9930+ u8 reserved_at_10[0x10];
9931+
9932+ u8 reserved_at_20[0x10];
9933+ u8 op_mod[0x10];
9934+
9935+ u8 reserved_at_40[0x40];
9936+};
9937+
9938+struct mlx5_ifc_dealloc_sf_out_bits {
9939+ u8 status[0x8];
9940+ u8 reserved_at_8[0x18];
9941+
9942+ u8 syndrome[0x20];
9943+
9944+ u8 reserved_at_40[0x40];
9945+};
9946+
9947+struct mlx5_ifc_dealloc_sf_in_bits {
9948+ u8 opcode[0x10];
9949+ u8 reserved_at_10[0x10];
9950+
9951+ u8 reserved_at_20[0x10];
9952+ u8 op_mod[0x10];
9953+
9954+ u8 reserved_at_40[0x10];
9955+ u8 function_id[0x10];
9956+
9957+ u8 reserved_at_60[0x20];
9958+};
9959+
9960+struct mlx5_ifc_alloc_sf_out_bits {
9961+ u8 status[0x8];
9962+ u8 reserved_at_8[0x18];
9963+
9964+ u8 syndrome[0x20];
9965+
9966+ u8 reserved_at_40[0x40];
9967+};
9968+
9969+struct mlx5_ifc_alloc_sf_in_bits {
9970+ u8 opcode[0x10];
9971+ u8 reserved_at_10[0x10];
9972+
9973+ u8 reserved_at_20[0x10];
9974+ u8 op_mod[0x10];
9975+
9976+ u8 reserved_at_40[0x10];
9977+ u8 function_id[0x10];
9978+
9979+ u8 reserved_at_60[0x20];
9980+};
9981+
9982+struct mlx5_ifc_affiliated_event_header_bits {
9983+ u8 reserved_at_0[0x10];
9984+ u8 obj_type[0x10];
9985+
9986+ u8 obj_id[0x20];
9987+};
9988+
9989+enum {
9990+ MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
9991+};
9992+
9993+enum {
9994+ MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
9995+};
9996+
9997+struct mlx5_ifc_encryption_key_obj_bits {
9998+ u8 modify_field_select[0x40];
9999+
10000+ u8 reserved_at_40[0x14];
10001+ u8 key_size[0x4];
10002+ u8 reserved_at_58[0x4];
10003+ u8 key_type[0x4];
10004+
10005+ u8 reserved_at_60[0x8];
10006+ u8 pd[0x18];
10007+
10008+ u8 reserved_at_80[0x180];
10009+ u8 key[8][0x20];
10010+
10011+ u8 reserved_at_300[0x500];
10012+};
10013+
10014+struct mlx5_ifc_create_encryption_key_in_bits {
10015+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10016+ struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10017+};
10018+
10019+enum {
10020+ MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10021+ MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10022+};
10023+
10024+enum {
10025+ MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10026+};
10027+
10028+struct mlx5_ifc_tls_static_params_bits {
10029+ u8 const_2[0x2];
10030+ u8 tls_version[0x4];
10031+ u8 const_1[0x2];
10032+ u8 reserved_at_8[0x14];
10033+ u8 encryption_standard[0x4];
10034+
10035+ u8 reserved_at_20[0x20];
10036+
10037+ u8 initial_record_number[0x40];
10038+
10039+ u8 resync_tcp_sn[0x20];
10040+
10041+ u8 gcm_iv[0x20];
10042+
10043+ u8 implicit_iv[0x40];
10044+
10045+ u8 reserved_at_100[0x8];
10046+ u8 dek_index[0x18];
10047+
10048+ u8 reserved_at_120[0xe0];
10049+};
10050+
10051+struct mlx5_ifc_tls_progress_params_bits {
10052+ u8 valid[0x1];
10053+ u8 reserved_at_1[0x7];
10054+ u8 pd[0x18];
10055+
10056+ u8 next_record_tcp_sn[0x20];
10057+
10058+ u8 hw_resync_tcp_sn[0x20];
10059+
10060+ u8 record_tracker_state[0x2];
10061+ u8 auth_state[0x2];
10062+ u8 reserved_at_64[0x4];
10063+ u8 hw_offset_record_number[0x18];
978910064 };
979010065
979110066 #endif /* MLX5_IFC_H */
include/linux/mlx5/qp.h+6−1
@@ -202,7 +202,12 @@ struct mlx5_wqe_ctrl_seg { · 201 unmodified lines
202202 u8 signature;
203203 u8 rsvd[2];
204204 u8 fm_ce_se;
205− __be32 imm;
205+ union {
206+ __be32 general_id;
207+ __be32 imm;
208+ __be32 umr_mkey;
209+ __be32 tisn;
210+ };
206211 };
207212
208213 #define MLX5_WQE_CTRL_DS_MASK 0x3f
include/linux/mlx5/vport.h+3−4
@@ -44,9 +44,6 @@ · 43 unmodified lines
4444 MLX5_VPORT_UPLINK_PLACEHOLDER + \
4545 MLX5_VPORT_ECPF_PLACEHOLDER(mdev))
4646
47−#define MLX5_TOTAL_VPORTS(mdev) (MLX5_SPECIAL_VPORTS(mdev) + \
48− mlx5_core_max_vfs(mdev))
49−
5047 #define MLX5_VPORT_MANAGER(mdev) \
5148 (MLX5_CAP_GEN(mdev, vport_group_manager) && \
5249 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \
@@ -58,6 +55,7 @@ enum { · 5 unmodified lines
5855 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
5956 };
6057
58+/* Vport number for each function must keep unchanged */
6159 enum {
6260 MLX5_VPORT_PF = 0x0,
6361 MLX5_VPORT_FIRST_VF = 0x1,
@@ -69,7 +67,8 @@ u8 mlx5_query_vport_state(struct mlx5_core_dev *mdev, u8 opmod, u16 vport); · 5 unmodified lines
6967 int mlx5_modify_vport_admin_state(struct mlx5_core_dev *mdev, u8 opmod,
7068 u16 vport, u8 other_vport, u8 state);
7169 int mlx5_query_nic_vport_mac_address(struct mlx5_core_dev *mdev,
72− u16 vport, u8 *addr);
70+ u16 vport, bool other, u8 *addr);
71+int mlx5_query_mac_address(struct mlx5_core_dev *mdev, u8 *addr);
7372 int mlx5_query_nic_vport_min_inline(struct mlx5_core_dev *mdev,
7473 u16 vport, u8 *min_inline);
7574 void mlx5_query_min_inline(struct mlx5_core_dev *mdev, u8 *min_inline);

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