Merge branches 'clk-renesas', 'clk-socfpga', 'clk-amlogic' and 'clk-canaan' into clk-next

* clk-renesas: (36 commits) clk: renesas: r9a08g045: Drop unused pm_domain header file clk: renesas: r8a779g0: Add DSC clock clk: renesas: rzg2l: Rename iterator in for_each_mod_clock() to avoid shadowing clk: renesas: r9a08g045: Drop unused DEF_G3S_MUX macro clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed ones clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macro clk: renesas: rzg2l: Simplify SAM PLL configuration macro clk: renesas: r8a73a4: Add ZT/ZTR trace clocks dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6 clk: renesas: r9a08g046: Add RSPI clocks and resets clk: renesas: r9a08g046: Add SSIF-2 clocks and resets clk: renesas: r9a08g046: Add RSCI clocks and resets clk: renesas: cpg-mssr: Add number of clock cells check clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable() clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS() clk: renesas: r9a08g046: Add IA55_PCLK to critical module clocks clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resets clk: renesas: r9a09g047: Add support for DSI clocks and resets clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks ... * clk-socfpga: clk: socfpga: agilex: implement l3_main_free_clk * clk-amlogic: dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock dt-bindings: clock: amlogic: Fix redundant hyphen in "amlogic,t7-gp1--pll" string. * clk-canaan: clk: canaan: Add clock driver for Canaan K230 dt-bindings: clock: Add Canaan K230 clock controller

Stephen Boyd committed 4 months ago

Commit e08f2085 parents 124e5c5 5c2fd8b c0c0752 3926276 df2e28927 files · +3510 −47Browse files

Unified · Split

27 files

Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml +8 −4
Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml +1 −1
Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml +59 −0
Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml +6 −2
drivers/clk/Kconfig +6 −0
drivers/clk/Makefile +1 −0
drivers/clk/clk-k230.c +2452 −0
drivers/clk/renesas/clk-r8a73a4.c +2 −0
drivers/clk/renesas/clk-r8a7740.c +2 −0
drivers/clk/renesas/r8a779g0-cpg-mssr.c +1 −0
drivers/clk/renesas/r9a07g043-cpg.c +1 −1
drivers/clk/renesas/r9a07g044-cpg.c +1 −1
drivers/clk/renesas/r9a08g045-cpg.c +1 −12
drivers/clk/renesas/r9a08g046-cpg.c +355 −0
drivers/clk/renesas/r9a09g011-cpg.c +1 −6
drivers/clk/renesas/r9a09g047-cpg.c +84 −0
drivers/clk/renesas/r9a09g077-cpg.c +1 −0
drivers/clk/renesas/renesas-cpg-mssr.c +3 −0
drivers/clk/renesas/rzg2l-cpg.c +75 −13
drivers/clk/renesas/rzg2l-cpg.h +11 −7
drivers/clk/renesas/rzv2h-cpg.c +181 −0
drivers/clk/renesas/rzv2h-cpg.h +12 −0
drivers/clk/socfpga/clk-agilex.c +2 −0
include/dt-bindings/clock/canaan,k230-clk.h +220 −0
include/dt-bindings/clock/r8a73a4-clock.h +2 −0
include/dt-bindings/clock/r8a7740-clock.h +2 −0
include/linux/clk/renesas.h +20 −0

Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml+8−4

     const: 1
   clocks:
-    minItems: 14
+    minItems: 15
     items:
       - description: input oscillator
       - description: input sys clk
       - description: input gp1 pll
       - description: input mpll1
       - description: input mpll2
+      - description: input mpll3
       - description: external input rmii oscillator (optional)
       - description: input video pll0 (optional)
       - description: external pad input for rtc (optional)
   clock-names:
-    minItems: 14
+    minItems: 15
     items:
       - const: xtal
       - const: sys
       - const: gp1
       - const: mpll1
       - const: mpll2
+      - const: mpll3
       - const: ext_rmii
       - const: vid_pll0
       - const: ext_rtc
                      <&gp0 1>,
                      <&gp1 1>,
                      <&mpll 4>,
-                     <&mpll 6>;
+                     <&mpll 6>,
+                     <&mpll 8>;
             clock-names = "xtal",
                           "sys",
                           "fix",
                           "gp0",
                           "gp1",
                           "mpll1",
-                          "mpll2";
+                          "mpll2",
+                          "mpll3";
         };
     };

Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml+1−1

@@ -72,7 +72,7 @@ allOf: · 71 unmodified lines
72	contains:	72	contains:
73	enum:	73	enum:
74	- amlogic,t7-gp0-pll	74	- amlogic,t7-gp0-pll
75	- amlogic,t7-gp1--pll	75	- amlogic,t7-gp1-pll
76	- amlogic,t7-hifi-pll	76	- amlogic,t7-hifi-pll
77	- amlogic,t7-pcie-pll	77	- amlogic,t7-pcie-pll
78	- amlogic,t7-mpll	78	- amlogic,t7-mpll

Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml+59−0

@@ -0,0 +1,59 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/clock/canaan,k230-clk.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Canaan Kendryte K230 Clock
	8
	9	maintainers:
	10	- Xukai Wang <kingxukai@zohomail.com>
	11
	12	description:
	13	The Canaan K230 clock controller generates various clocks for SoC
	14	peripherals. See include/dt-bindings/clock/canaan,k230-clk.h for
	15	valid clock IDs.
	16
	17	properties:
	18	compatible:
	19	const: canaan,k230-clk
	20
	21	reg:
	22	items:
	23	- description: PLL control registers
	24	- description: Sysclk control registers
	25
	26	clocks:
	27	items:
	28	- description: Main external reference clock
	29	- description:
	30	External clock which used as the pulse input
	31	for the timer to provide timing signals.
	32
	33	clock-names:
	34	items:
	35	- const: osc24m
	36	- const: timer-pulse-in
	37
	38	'#clock-cells':
	39	const: 1
	40
	41	required:
	42	- compatible
	43	- reg
	44	- clocks
	45	- clock-names
	46	- '#clock-cells'
	47
	48	additionalProperties: false
	49
	50	examples:
	51	- \|
	52	clock-controller@91102000 {
	53	compatible = "canaan,k230-clk";
	54	reg = <0x91102000 0x40>,
	55	<0x91100000 0x108>;
	56	clocks = <&osc24m>, <&timerx_pulse_in>;
	57	clock-names = "osc24m", "timer-pulse-in";
	58	#clock-cells = <1>;
	59	};

Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml+6−2

   clock-output-names:
     minItems: 3
-    maxItems: 17
+    maxItems: 19
   renesas,mode:
     description: Board-specific settings of the MD_CK* bits on R-Mobile A1
             - const: zx
             - const: zs
             - const: hp
+            - const: ztr
+            - const: zt
   - if:
       properties:
             - const: zb
             - const: m3
             - const: cp
+            - const: ztr
+            - const: zt
       required:
         - renesas,mode
             #clock-cells = <1>;
             clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
                                  "usb24s", "i", "zg", "b", "m1", "hp", "hpp",
-                                 "usbp", "s", "zb", "m3", "cp";
+                                 "usbp", "s", "zb", "m3", "cp", "ztr", "zt";
             renesas,mode = <0x05>;
     };

drivers/clk/Kconfig+6−0

 	help
 	  Support for the Canaan Kendryte K210 RISC-V SoC clocks.
+config COMMON_CLK_K230
+	bool "Clock driver for the Canaan Kendryte K230 SoC"
+	depends on ARCH_CANAAN || COMPILE_TEST
+	help
+	  Support for the Canaan Kendryte K230 RISC-V SoC clocks.
 config COMMON_CLK_SP7021
 	tristate "Clock driver for Sunplus SP7021 SoC"
 	depends on SOC_SP7021 || COMPILE_TEST

drivers/clk/Makefile+1−0

@@ -65,6 +65,7 @@ obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o · 64 unmodified lines
65	obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o	65	obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
66	obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o	66	obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
67	obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o	67	obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o
		68	obj-$(CONFIG_COMMON_CLK_K230) += clk-k230.o
68	obj-$(CONFIG_LMK04832) += clk-lmk04832.o	69	obj-$(CONFIG_LMK04832) += clk-lmk04832.o
69	obj-$(CONFIG_COMMON_CLK_LAN966X) += clk-lan966x.o	70	obj-$(CONFIG_COMMON_CLK_LAN966X) += clk-lan966x.o
70	obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o	71	obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o

drivers/clk/clk-k230.c+2452−0

@@ -0,0 +1,2452 @@
	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Kendryte Canaan K230 Clock Drivers
	4	*
	5	* Author: Xukai Wang <kingxukai@zohomail.com>
	6	* Author: Troy Mitchell <troymitchell988@gmail.com>
	7	*/
	8
	9	#include <linux/bitfield.h>
	10	#include <linux/clk.h>
	11	#include <linux/clkdev.h>
	12	#include <linux/clk-provider.h>
	13	#include <linux/iopoll.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/rational.h>
	16	#include <linux/spinlock.h>
	17
	18	#include <dt-bindings/clock/canaan,k230-clk.h>
	19
	20	/* PLL control register bits. */
	21	#define K230_PLL_BYPASS_ENABLE BIT(19)
	22	#define K230_PLL_GATE_ENABLE BIT(2)
	23	#define K230_PLL_GATE_WRITE_ENABLE BIT(18)
	24	#define K230_PLL_OD_MASK GENMASK(27, 24)
	25	#define K230_PLL_R_MASK GENMASK(21, 16)
	26	#define K230_PLL_F_MASK GENMASK(12, 0)
	27	#define K230_PLL_DIV_REG_OFFSET 0x00
	28	#define K230_PLL_BYPASS_REG_OFFSET 0x04
	29	#define K230_PLL_GATE_REG_OFFSET 0x08
	30	#define K230_PLL_LOCK_REG_OFFSET 0x0C
	31
	32	/* PLL lock register */
	33	#define K230_PLL_LOCK_STATUS_MASK BIT(0)
	34	#define K230_PLL_LOCK_TIME_DELAY 400
	35	#define K230_PLL_LOCK_TIMEOUT 0
	36
	37	/* K230 CLK registers offset */
	38	#define K230_CLK_AUDIO_CLKDIV_OFFSET 0x34
	39	#define K230_CLK_PDM_CLKDIV_OFFSET 0x40
	40	#define K230_CLK_CODEC_ADC_MCLKDIV_OFFSET 0x38
	41	#define K230_CLK_CODEC_DAC_MCLKDIV_OFFSET 0x3c
	42
	43	#define K230_PLLX_DIV_ADDR(base, idx) \
	44	(K230_PLL_DIV_REG_OFFSET + (base) + (idx) * 0x10)
	45
	46	#define K230_PLLX_BYPASS_ADDR(base, idx) \
	47	(K230_PLL_BYPASS_REG_OFFSET + (base) + (idx) * 0x10)
	48
	49	#define K230_PLLX_GATE_ADDR(base, idx) \
	50	(K230_PLL_GATE_REG_OFFSET + (base) + (idx) * 0x10)
	51
	52	#define K230_PLLX_LOCK_ADDR(base, idx) \
	53	(K230_PLL_LOCK_REG_OFFSET + (base) + (idx) * 0x10)
	54
	55	#define K230_CLK_RATE_FORMAT_PNAME(_var, _id, \
	56	_mul_min, _mul_max, _mul_shift, _mul_mask, \
	57	_div_min, _div_max, _div_shift, _div_mask, \
	58	_reg, _bit, _method, _reg2, \
	59	_read_only, _flags, \
	60	_pname) \
	61	static struct k230_clk_rate _var = { \
	62	.div_reg_off = _reg, \
	63	.mul_reg_off = _reg2, \
	64	.id = _id, \
	65	.clk = { \
	66	.write_enable_bit = _bit, \
	67	.mul_min = _mul_min, \
	68	.mul_max = _mul_max, \
	69	.mul_shift = _mul_shift, \
	70	.mul_mask = _mul_mask, \
	71	.div_min = _div_min, \
	72	.div_max = _div_max, \
	73	.div_shift = _div_shift, \
	74	.div_mask = _div_mask, \
	75	.read_only = _read_only, \
	76	.hw.init = CLK_HW_INIT_FW_NAME(#_var, \
	77	_pname, &k230_clk_ops_##_method, \
	78	_flags), \
	79	}, \
	80	}
	81
	82	#define K230_CLK_RATE_FORMAT(_var, _id, \
	83	_mul_min, _mul_max, _mul_shift, _mul_mask, \
	84	_div_min, _div_max, _div_shift, _div_mask, \
	85	_reg, _bit, _method, _reg2, \
	86	_read_only, _flags, \
	87	_phw) \
	88	static struct k230_clk_rate _var = { \
	89	.div_reg_off = _reg, \
	90	.mul_reg_off = _reg2, \
	91	.id = _id, \
	92	.clk = { \
	93	.write_enable_bit = _bit, \
	94	.mul_min = _mul_min, \
	95	.mul_max = _mul_max, \
	96	.mul_shift = _mul_shift, \
	97	.mul_mask = _mul_mask, \
	98	.div_min = _div_min, \
	99	.div_max = _div_max, \
	100	.div_shift = _div_shift, \
	101	.div_mask = _div_mask, \
	102	.read_only = _read_only, \
	103	.hw.init = CLK_HW_INIT_HW(#_var, \
	104	_phw, &k230_clk_ops_##_method, \
	105	_flags), \
	106	}, \
	107	}
	108
	109	#define K230_CLK_GATE_FORMAT_PNAME(_var, _id, \
	110	_reg, _bit, _flags, _gate_flags, \
	111	_pname) \
	112	static struct k230_clk_gate _var = { \
	113	.reg_off = _reg, \
	114	.id = _id, \
	115	.clk = { \
	116	.bit_idx = _bit, \
	117	.flags = _gate_flags, \
	118	.hw.init = CLK_HW_INIT_FW_NAME(#_var, \
	119	_pname, &clk_gate_ops, _flags), \
	120	}, \
	121	}
	122
	123	#define K230_CLK_GATE_FORMAT(_var, _id, \
	124	_reg, _bit, _flags, _gate_flags, \
	125	_phw) \
	126	static struct k230_clk_gate _var = { \
	127	.reg_off = _reg, \
	128	.id = _id, \
	129	.clk = { \
	130	.bit_idx = _bit, \
	131	.flags = _gate_flags, \
	132	.hw.init = CLK_HW_INIT_HW(#_var, \
	133	_phw, &clk_gate_ops, _flags), \
	134	}, \
	135	}
	136
	137	#define K230_CLK_MUX_FORMAT(_var, _id, \
	138	_reg, _shift, _mask, _flags, _mux_flags, _pdata) \
	139	static struct k230_clk_mux _var = { \
	140	.reg_off = _reg, \
	141	.id = _id, \
	142	.clk = { \
	143	.flags = _mux_flags, \
	144	.shift = _shift, \
	145	.mask = _mask, \
	146	.hw.init = CLK_HW_INIT_PARENTS_DATA(#_var, \
	147	_pdata, &clk_mux_ops, _flags), \
	148	}, \
	149	}
	150
	151	#define K230_CLK_FIXED_FACTOR_FORMAT(_var, \
	152	_mul, _div, _flags, \
	153	_phw) \
	154	static struct clk_fixed_factor _var = { \
	155	.mult = _mul, \
	156	.div = _div, \
	157	.hw.init = CLK_HW_INIT_HW(#_var, \
	158	_phw, &clk_fixed_factor_ops, _flags), \
	159	}
	160
	161	#define K230_CLK_PLL_FORMAT(_var, _id, _flags, _pname) \
	162	static struct k230_pll _var = { \
	163	.hw.init = CLK_HW_INIT_FW_NAME(#_var, \
	164	_pname, &k230_pll_ops, _flags), \
	165	.id = _id, \
	166	}
	167
	168	struct k230_pll {
	169	struct clk_hw hw;
	170	void __iomem *reg;
	171	/* ensures mutual exclusion for concurrent register access. */
	172	spinlock_t *lock;
	173	int id;
	174	};
	175
	176	#define hw_to_k230_pll(_hw) container_of(_hw, struct k230_pll, hw)
	177
	178	struct k230_clk_rate_self {
	179	struct clk_hw hw;
	180	void __iomem *reg;
	181	bool read_only;
	182	u32 write_enable_bit;
	183	u32 mul_min;
	184	u32 mul_max;
	185	u32 mul_shift;
	186	u32 mul_mask;
	187	u32 div_min;
	188	u32 div_max;
	189	u32 div_shift;
	190	u32 div_mask;
	191	/* ensures mutual exclusion for concurrent register access. */
	192	spinlock_t *lock;
	193	};
	194
	195	#define hw_to_k230_clk_rate_self(_hw) container_of(_hw, \
	196	struct k230_clk_rate_self, hw)
	197
	198	struct k230_clk_rate {
	199	u32 mul_reg_off;
	200	u32 div_reg_off;
	201	struct k230_clk_rate_self clk;
	202	int id;
	203	};
	204
	205	static inline struct k230_clk_rate hw_to_k230_clk_rate(struct clk_hw hw)
	206	{
	207	return container_of(hw_to_k230_clk_rate_self(hw), struct k230_clk_rate,
	208	clk);
	209	}
	210
	211	struct k230_clk_gate {
	212	u32 reg_off;
	213	struct clk_gate clk;
	214	int id;
	215	};
	216
	217	struct k230_clk_mux {
	218	u32 reg_off;
	219	struct clk_mux clk;
	220	int id;
	221	};
	222
	223	static int k230_pll_prepare(struct clk_hw *hw);
	224	static int k230_pll_enable(struct clk_hw *hw);
	225	static void k230_pll_disable(struct clk_hw *hw);
	226	static int k230_pll_is_enabled(struct clk_hw *hw);
	227	static unsigned long k230_pll_get_rate(struct clk_hw *hw, unsigned long parent_rate);
	228	static int k230_clk_set_rate_mul(struct clk_hw *hw, unsigned long rate,
	229	unsigned long parent_rate);
	230	static int k230_clk_determine_rate_mul(struct clk_hw hw, struct clk_rate_request req);
	231	static unsigned long k230_clk_get_rate_mul(struct clk_hw *hw,
	232	unsigned long parent_rate);
	233	static int k230_clk_set_rate_div(struct clk_hw *hw, unsigned long rate,
	234	unsigned long parent_rate);
	235	static int k230_clk_determine_rate_div(struct clk_hw hw, struct clk_rate_request req);
	236	static unsigned long k230_clk_get_rate_div(struct clk_hw *hw,
	237	unsigned long parent_rate);
	238	static int k230_clk_set_rate_mul_div(struct clk_hw *hw, unsigned long rate,
	239	unsigned long parent_rate);
	240	static int k230_clk_determine_rate_mul_div(struct clk_hw hw, struct clk_rate_request req);
	241	static unsigned long k230_clk_get_rate_mul_div(struct clk_hw *hw,
	242	unsigned long parent_rate);
	243
	244	static const struct clk_ops k230_pll_ops = {
	245	.prepare = k230_pll_prepare,
	246	.enable = k230_pll_enable,
	247	.disable = k230_pll_disable,
	248	.is_enabled = k230_pll_is_enabled,
	249	.recalc_rate = k230_pll_get_rate,
	250	};
	251
	252	/* clk_ops for clocks whose rate is determined by a configurable multiplier */
	253	static const struct clk_ops k230_clk_ops_mul = {
	254	.set_rate = k230_clk_set_rate_mul,
	255	.determine_rate = k230_clk_determine_rate_mul,
	256	.recalc_rate = k230_clk_get_rate_mul,
	257	};
	258
	259	/* clk_ops for clocks whose rate is determined by a configurable divider */
	260	static const struct clk_ops k230_clk_ops_div = {
	261	.set_rate = k230_clk_set_rate_div,
	262	.determine_rate = k230_clk_determine_rate_div,
	263	.recalc_rate = k230_clk_get_rate_div,
	264	};
	265
	266	/* clk_ops for clocks whose rate is determined by both a multiplier and a divider */
	267	static const struct clk_ops k230_clk_ops_mul_div = {
	268	.set_rate = k230_clk_set_rate_mul_div,
	269	.determine_rate = k230_clk_determine_rate_mul_div,
	270	.recalc_rate = k230_clk_get_rate_mul_div,
	271	};
	272
	273	K230_CLK_PLL_FORMAT(pll0, 0, CLK_IS_CRITICAL, NULL);
	274	K230_CLK_PLL_FORMAT(pll1, 1, CLK_IS_CRITICAL, NULL);
	275	K230_CLK_PLL_FORMAT(pll2, 2, CLK_IS_CRITICAL, NULL);
	276	K230_CLK_PLL_FORMAT(pll3, 3, CLK_IS_CRITICAL, NULL);
	277
	278	static struct k230_pll *k230_plls[] = {
	279	&pll0,
	280	&pll1,
	281	&pll2,
	282	&pll3,
	283	};
	284
	285	K230_CLK_FIXED_FACTOR_FORMAT(pll0_div2, 1, 2, 0, &pll0.hw);
	286	K230_CLK_FIXED_FACTOR_FORMAT(pll0_div3, 1, 3, 0, &pll0.hw);
	287	K230_CLK_FIXED_FACTOR_FORMAT(pll0_div4, 1, 4, 0, &pll0.hw);
	288	K230_CLK_FIXED_FACTOR_FORMAT(pll0_div16, 1, 16, 0, &pll0.hw);
	289	K230_CLK_FIXED_FACTOR_FORMAT(pll1_div2, 1, 2, 0, &pll1.hw);
	290	K230_CLK_FIXED_FACTOR_FORMAT(pll1_div3, 1, 3, 0, &pll1.hw);
	291	K230_CLK_FIXED_FACTOR_FORMAT(pll1_div4, 1, 4, 0, &pll1.hw);
	292	K230_CLK_FIXED_FACTOR_FORMAT(pll2_div2, 1, 2, 0, &pll2.hw);
	293	K230_CLK_FIXED_FACTOR_FORMAT(pll2_div3, 1, 3, 0, &pll2.hw);
	294	K230_CLK_FIXED_FACTOR_FORMAT(pll2_div4, 1, 4, 0, &pll2.hw);
	295	K230_CLK_FIXED_FACTOR_FORMAT(pll3_div2, 1, 2, 0, &pll3.hw);
	296	K230_CLK_FIXED_FACTOR_FORMAT(pll3_div3, 1, 3, 0, &pll3.hw);
	297	K230_CLK_FIXED_FACTOR_FORMAT(pll3_div4, 1, 4, 0, &pll3.hw);
	298
	299	static struct clk_fixed_factor *k230_pll_divs[] = {
	300	&pll0_div2,
	301	&pll0_div3,
	302	&pll0_div4,
	303	&pll0_div16,
	304	&pll1_div2,
	305	&pll1_div3,
	306	&pll1_div4,
	307	&pll2_div2,
	308	&pll2_div3,
	309	&pll2_div4,
	310	&pll3_div2,
	311	&pll3_div3,
	312	&pll3_div4,
	313	};
	314
	315	K230_CLK_GATE_FORMAT(cpu0_src_gate,
	316	K230_CPU0_SRC_GATE,
	317	0, 0, CLK_IS_CRITICAL, 0,
	318	&pll0_div2.hw);
	319
	320	K230_CLK_RATE_FORMAT(cpu0_src_rate,
	321	K230_CPU0_SRC_RATE,
	322	1, 16, 1, 0xF,
	323	16, 16, 0, 0x0,
	324	0x0, 31, mul, 0x0,
	325	false, 0,
	326	&cpu0_src_gate.clk.hw);
	327
	328	K230_CLK_RATE_FORMAT(cpu0_axi_rate,
	329	K230_CPU0_AXI_RATE,
	330	1, 1, 0, 0,
	331	1, 8, 6, 0x7,
	332	0x0, 31, div, 0x0,
	333	0, 0,
	334	&cpu0_src_rate.clk.hw);
	335
	336	K230_CLK_GATE_FORMAT(cpu0_plic_gate,
	337	K230_CPU0_PLIC_GATE,
	338	0x0, 9, CLK_IS_CRITICAL, 0,
	339	&cpu0_src_rate.clk.hw);
	340
	341	K230_CLK_RATE_FORMAT(cpu0_plic_rate,
	342	K230_CPU0_PLIC_RATE,
	343	1, 1, 0, 0,
	344	1, 8, 10, 0x7,
	345	0x0, 31, div, 0x0,
	346	false, 0,
	347	&cpu0_plic_gate.clk.hw);
	348
	349	K230_CLK_GATE_FORMAT(cpu0_noc_ddrcp4_gate,
	350	K230_CPU0_NOC_DDRCP4_GATE,
	351	0x60, 7, CLK_IS_CRITICAL, 0,
	352	&cpu0_src_rate.clk.hw);
	353
	354	K230_CLK_GATE_FORMAT(cpu0_apb_gate,
	355	K230_CPU0_APB_GATE,
	356	0x0, 13, CLK_IS_CRITICAL, 0,
	357	&pll0_div4.hw);
	358
	359	K230_CLK_RATE_FORMAT(cpu0_apb_rate,
	360	K230_CPU0_APB_RATE,
	361	1, 1, 0, 0,
	362	1, 8, 15, 0x7,
	363	0x0, 31, div, 0x0,
	364	false, 0,
	365	&cpu0_apb_gate.clk.hw);
	366
	367	static const struct clk_parent_data k230_cpu1_src_mux_pdata[] = {
	368	{ .hw = &pll1_div2.hw, },
	369	{ .hw = &pll3.hw, },
	370	{ .hw = &pll0.hw, },
	371	};
	372
	373	K230_CLK_MUX_FORMAT(cpu1_src_mux,
	374	K230_CPU1_SRC_MUX,
	375	0x4, 1, 0x3,
	376	0, 0,
	377	k230_cpu1_src_mux_pdata);
	378
	379	K230_CLK_GATE_FORMAT(cpu1_src_gate,
	380	K230_CPU1_SRC_GATE,
	381	0x4, 0, CLK_IS_CRITICAL, 0,
	382	&cpu1_src_mux.clk.hw);
	383
	384	K230_CLK_RATE_FORMAT(cpu1_src_rate,
	385	K230_CPU1_SRC_RATE,
	386	1, 1, 0, 0,
	387	1, 8, 3, 0x7,
	388	0x4, 31, div, 0x0,
	389	false, 0,
	390	&cpu1_src_gate.clk.hw);
	391
	392	K230_CLK_RATE_FORMAT(cpu1_axi_rate,
	393	K230_CPU1_AXI_RATE,
	394	1, 1, 0, 0,
	395	1, 8, 12, 0x7,
	396	0x4, 31, div, 0x0,
	397	false, 0,
	398	&cpu1_src_rate.clk.hw);
	399
	400	K230_CLK_GATE_FORMAT(cpu1_plic_gate,
	401	K230_CPU1_PLIC_GATE,
	402	0x4, 15, CLK_IS_CRITICAL, 0,
	403	&cpu1_src_rate.clk.hw);
	404
	405	K230_CLK_RATE_FORMAT(cpu1_plic_rate,
	406	K230_CPU1_PLIC_RATE,
	407	1, 1, 0, 0,
	408	1, 8, 16, 0x7,
	409	0x4, 31, div, 0x0,
	410	false, 0,
	411	&cpu1_plic_gate.clk.hw);
	412
	413	K230_CLK_GATE_FORMAT(cpu1_apb_gate,
	414	K230_CPU1_APB_GATE,
	415	0x4, 19, CLK_IS_CRITICAL, 0,
	416	&pll0_div4.hw);
	417
	418	K230_CLK_GATE_FORMAT_PNAME(pmu_apb_gate,
	419	K230_PMU_APB_GATE,
	420	0x10, 0, 0, 0,
	421	"osc24m");
	422
	423	K230_CLK_GATE_FORMAT(hs_hclk_high_gate,
	424	K230_HS_HCLK_HIGH_GATE,
	425	0x18, 1, 0, 0,
	426	&pll0_div4.hw);
	427
	428	K230_CLK_RATE_FORMAT(hs_hclk_high_rate,
	429	K230_HS_HCLK_HIGH_RATE,
	430	1, 1, 0, 0,
	431	1, 8, 0, 0x7,
	432	0x1C, 31, div, 0x0,
	433	false, 0,
	434	&hs_hclk_high_gate.clk.hw);
	435
	436	K230_CLK_GATE_FORMAT(hs_hclk_gate,
	437	K230_HS_HCLK_GATE,
	438	0x18, 0, 0, 0,
	439	&hs_hclk_high_rate.clk.hw);
	440
	441	K230_CLK_RATE_FORMAT(hs_hclk_rate,
	442	K230_HS_HCLK_RATE,
	443	1, 1, 0, 0,
	444	1, 8, 3, 0x7,
	445	0x1C, 31, div, 0x0,
	446	false, 0,
	447	&hs_hclk_gate.clk.hw);
	448
	449	K230_CLK_GATE_FORMAT(hs_sd0_ahb_gate,
	450	K230_HS_SD0_AHB_GATE,
	451	0x18, 2, 0, 0,
	452	&hs_hclk_rate.clk.hw);
	453
	454	K230_CLK_GATE_FORMAT(hs_sd1_ahb_gate,
	455	K230_HS_SD1_AHB_GATE,
	456	0x18, 3, 0, 0,
	457	&hs_hclk_rate.clk.hw);
	458
	459	K230_CLK_GATE_FORMAT(hs_ssi1_ahb_gate,
	460	K230_HS_SSI1_AHB_GATE,
	461	0x18, 7, 0, 0,
	462	&hs_hclk_rate.clk.hw);
	463
	464	K230_CLK_GATE_FORMAT(hs_ssi2_ahb_gate,
	465	K230_HS_SSI2_AHB_GATE,
	466	0x18, 8, 0, 0,
	467	&hs_hclk_rate.clk.hw);
	468
	469	K230_CLK_GATE_FORMAT(hs_usb0_ahb_gate,
	470	K230_HS_USB0_AHB_GATE,
	471	0x18, 4, 0, 0,
	472	&hs_hclk_rate.clk.hw);
	473
	474	K230_CLK_GATE_FORMAT(hs_usb1_ahb_gate,
	475	K230_HS_USB1_AHB_GATE,
	476	0x18, 5, 0, 0,
	477	&hs_hclk_rate.clk.hw);
	478
	479	K230_CLK_GATE_FORMAT(hs_ssi0_axi_gate,
	480	K230_HS_SSI0_AXI_GATE,
	481	0x18, 27, 0, 0,
	482	&pll0_div4.hw);
	483
	484	K230_CLK_RATE_FORMAT(hs_ssi0_axi_rate,
	485	K230_HS_SSI0_AXI_RATE,
	486	1, 1, 0, 0,
	487	1, 8, 9, 0x7,
	488	0x20, 31, div, 0x0,
	489	false, 0,
	490	&hs_ssi0_axi_gate.clk.hw);
	491
	492	K230_CLK_GATE_FORMAT(hs_ssi1_gate,
	493	K230_HS_SSI1_GATE,
	494	0x18, 25, 0, 0,
	495	&pll0_div4.hw);
	496
	497	K230_CLK_RATE_FORMAT(hs_ssi1_rate,
	498	K230_HS_SSI1_RATE,
	499	1, 1, 0, 0,
	500	1, 8, 3, 0x7,
	501	0x20, 31, div, 0x0,
	502	false, 0,
	503	&hs_ssi1_gate.clk.hw);
	504
	505	K230_CLK_GATE_FORMAT(hs_ssi2_gate,
	506	K230_HS_SSI2_GATE,
	507	0x18, 26, 0, 0,
	508	&pll0_div4.hw);
	509
	510	K230_CLK_RATE_FORMAT(hs_ssi2_rate,
	511	K230_HS_SSI2_RATE,
	512	1, 1, 0, 0,
	513	1, 8, 6, 0x7,
	514	0x20, 31, div, 0x0,
	515	false, 0,
	516	&hs_ssi2_gate.clk.hw);
	517
	518	K230_CLK_GATE_FORMAT(hs_qspi_axi_src_gate,
	519	K230_HS_QSPI_AXI_SRC_GATE,
	520	0x18, 28, 0, 0,
	521	&pll0_div4.hw);
	522
	523	K230_CLK_RATE_FORMAT(hs_qspi_axi_src_rate,
	524	K230_HS_QSPI_AXI_SRC_RATE,
	525	1, 1, 0, 0,
	526	1, 8, 12, 0x7,
	527	0x20, 31, div, 0x0,
	528	false, 0,
	529	&hs_qspi_axi_src_gate.clk.hw);
	530
	531	K230_CLK_GATE_FORMAT(hs_ssi1_axi_gate,
	532	K230_HS_SSI1_AXI_GATE,
	533	0x18, 29, 0, 0,
	534	&hs_qspi_axi_src_rate.clk.hw);
	535
	536	K230_CLK_GATE_FORMAT(hs_ssi2_axi_gate,
	537	K230_HS_SSI2_AXI_GATE,
	538	0x18, 30, 0, 0,
	539	&hs_qspi_axi_src_rate.clk.hw);
	540
	541	K230_CLK_GATE_FORMAT(hs_sd_card_src_gate,
	542	K230_HS_SD_CARD_SRC_GATE,
	543	0x18, 11, 0, 0,
	544	&pll0_div4.hw);
	545
	546	K230_CLK_RATE_FORMAT(hs_sd_card_src_rate,
	547	K230_HS_SD_CARD_SRC_RATE,
	548	1, 1, 0, 0,
	549	2, 8, 12, 0x7,
	550	0x1C, 31, div, 0x0,
	551	false, 0,
	552	&hs_sd_card_src_gate.clk.hw);
	553
	554	K230_CLK_GATE_FORMAT(hs_sd0_card_gate,
	555	K230_HS_SD0_CARD_GATE,
	556	0x18, 15, 0, 0,
	557	&hs_sd_card_src_rate.clk.hw);
	558
	559	K230_CLK_GATE_FORMAT(hs_sd1_card_gate,
	560	K230_HS_SD1_CARD_GATE,
	561	0x18, 19, 0, 0,
	562	&hs_sd_card_src_rate.clk.hw);
	563
	564	K230_CLK_GATE_FORMAT(hs_sd_axi_src_gate,
	565	K230_HS_SD_AXI_SRC_GATE,
	566	0x18, 9, 0, 0,
	567	&pll2_div4.hw);
	568
	569	K230_CLK_RATE_FORMAT(hs_sd_axi_src_rate,
	570	K230_HS_SD_AXI_SRC_RATE,
	571	1, 1, 0, 0,
	572	1, 8, 6, 0x7,
	573	0x1C, 31, div, 0x0,
	574	false, 0,
	575	&hs_sd_axi_src_gate.clk.hw);
	576
	577	K230_CLK_GATE_FORMAT(hs_sd0_axi_gate,
	578	K230_HS_SD0_AXI_GATE,
	579	0x18, 13, 0, 0,
	580	&hs_sd_axi_src_rate.clk.hw);
	581
	582	K230_CLK_GATE_FORMAT(hs_sd1_axi_gate,
	583	K230_HS_SD1_AXI_GATE,
	584	0x18, 17, 0, 0,
	585	&hs_sd_axi_src_rate.clk.hw);
	586
	587	K230_CLK_GATE_FORMAT(hs_sd0_base_gate,
	588	K230_HS_SD0_BASE_GATE,
	589	0x18, 14, 0, 0,
	590	&hs_sd_axi_src_rate.clk.hw);
	591
	592	K230_CLK_GATE_FORMAT(hs_sd1_base_gate,
	593	K230_HS_SD1_BASE_GATE,
	594	0x18, 18, 0, 0,
	595	&hs_sd_axi_src_rate.clk.hw);
	596
	597	static const struct clk_parent_data k230_hs_ssi0_mux_pdata[] = {
	598	{ .hw = &pll0_div2.hw, },
	599	{ .hw = &pll2_div4.hw, },
	600	};
	601
	602	K230_CLK_MUX_FORMAT(hs_ssi0_mux,
	603	K230_HS_SSI0_MUX,
	604	0x20, 18, 0x1,
	605	0, 0,
	606	k230_hs_ssi0_mux_pdata);
	607
	608	K230_CLK_GATE_FORMAT(hs_ssi0_gate,
	609	K230_HS_SSI0_GATE,
	610	0x18, 24, CLK_IGNORE_UNUSED, 0,
	611	&hs_ssi0_mux.clk.hw);
	612
	613	K230_CLK_RATE_FORMAT(hs_usb_ref_50m_rate,
	614	K230_HS_USB_REF_50M_RATE,
	615	1, 1, 0, 0,
	616	1, 8, 15, 0x7,
	617	0x20, 31, div, 0x0,
	618	false, 0,
	619	&pll0_div16.hw);
	620
	621	K230_CLK_GATE_FORMAT_PNAME(hs_sd_timer_src_gate,
	622	K230_HS_SD_TIMER_SRC_GATE,
	623	0x18, 12, 0, 0,
	624	"osc24m");
	625
	626	K230_CLK_RATE_FORMAT(hs_sd_timer_src_rate,
	627	K230_HS_SD_TIMER_SRC_RATE,
	628	1, 1, 0, 0,
	629	24, 32, 15, 0x1F,
	630	0x1C, 31, div, 0x0,
	631	false, 0,
	632	&hs_sd_timer_src_gate.clk.hw);
	633
	634	K230_CLK_GATE_FORMAT(hs_sd0_timer_gate,
	635	K230_HS_SD0_TIMER_GATE,
	636	0x18, 16, 0, 0,
	637	&hs_sd_timer_src_rate.clk.hw);
	638
	639	K230_CLK_GATE_FORMAT(hs_sd1_timer_gate,
	640	K230_HS_SD1_TIMER_GATE,
	641	0x18, 20, 0, 0,
	642	&hs_sd_timer_src_rate.clk.hw);
	643
	644	static const struct clk_parent_data k230_hs_usb_ref_mux_pdata[] = {
	645	{ .fw_name = "osc24m", },
	646	{ .hw = &hs_usb_ref_50m_rate.clk.hw, },
	647	};
	648
	649	K230_CLK_MUX_FORMAT(hs_usb_ref_mux,
	650	K230_HS_USB_REF_MUX,
	651	0x18, 23, 0x1,
	652	0, 0,
	653	k230_hs_usb_ref_mux_pdata);
	654
	655	K230_CLK_GATE_FORMAT(hs_usb0_ref_gate,
	656	K230_HS_USB0_REF_GATE,
	657	0x18, 21, CLK_IGNORE_UNUSED, 0,
	658	&hs_usb_ref_mux.clk.hw);
	659
	660	K230_CLK_GATE_FORMAT(hs_usb1_ref_gate,
	661	K230_HS_USB1_REF_GATE,
	662	0x18, 22, CLK_IGNORE_UNUSED, 0,
	663	&hs_usb_ref_mux.clk.hw);
	664
	665	K230_CLK_GATE_FORMAT(ls_apb_src_gate,
	666	K230_LS_APB_SRC_GATE,
	667	0x24, 0, CLK_IS_CRITICAL, 0,
	668	&pll0_div4.hw);
	669
	670	K230_CLK_RATE_FORMAT(ls_apb_src_rate,
	671	K230_LS_APB_SRC_RATE,
	672	1, 1, 0, 0,
	673	1, 8, 0, 0x7,
	674	0x30, 31, div, 0x0,
	675	false, 0,
	676	&ls_apb_src_gate.clk.hw);
	677
	678	K230_CLK_GATE_FORMAT(ls_uart0_apb_gate,
	679	K230_LS_UART0_APB_GATE,
	680	0x24, 1, CLK_IS_CRITICAL, 0,
	681	&ls_apb_src_rate.clk.hw);
	682
	683	K230_CLK_GATE_FORMAT(ls_uart1_apb_gate,
	684	K230_LS_UART1_APB_GATE,
	685	0x24, 2, CLK_IS_CRITICAL, 0,
	686	&ls_apb_src_rate.clk.hw);
	687
	688	K230_CLK_GATE_FORMAT(ls_uart2_apb_gate,
	689	K230_LS_UART2_APB_GATE,
	690	0x24, 3, CLK_IS_CRITICAL, 0,
	691	&ls_apb_src_rate.clk.hw);
	692
	693	K230_CLK_GATE_FORMAT(ls_uart3_apb_gate,
	694	K230_LS_UART3_APB_GATE,
	695	0x24, 4, CLK_IS_CRITICAL, 0,
	696	&ls_apb_src_rate.clk.hw);
	697
	698	K230_CLK_GATE_FORMAT(ls_uart4_apb_gate,
	699	K230_LS_UART4_APB_GATE,
	700	0x24, 5, CLK_IS_CRITICAL, 0,
	701	&ls_apb_src_rate.clk.hw);
	702
	703	K230_CLK_GATE_FORMAT(ls_i2c0_apb_gate,
	704	K230_LS_I2C0_APB_GATE,
	705	0x24, 6, 0, 0,
	706	&ls_apb_src_rate.clk.hw);
	707
	708	K230_CLK_GATE_FORMAT(ls_i2c1_apb_gate,
	709	K230_LS_I2C1_APB_GATE,
	710	0x24, 7, 0, 0,
	711	&ls_apb_src_rate.clk.hw);
	712
	713	K230_CLK_GATE_FORMAT(ls_i2c2_apb_gate,
	714	K230_LS_I2C2_APB_GATE,
	715	0x24, 8, 0, 0,
	716	&ls_apb_src_rate.clk.hw);
	717
	718	K230_CLK_GATE_FORMAT(ls_i2c3_apb_gate,
	719	K230_LS_I2C3_APB_GATE,
	720	0x24, 9, 0, 0,
	721	&ls_apb_src_rate.clk.hw);
	722
	723	K230_CLK_GATE_FORMAT(ls_i2c4_apb_gate,
	724	K230_LS_I2C4_APB_GATE,
	725	0x24, 10, 0, 0,
	726	&ls_apb_src_rate.clk.hw);
	727
	728	K230_CLK_GATE_FORMAT(ls_gpio_apb_gate,
	729	K230_LS_GPIO_APB_GATE,
	730	0x24, 11, 0, 0,
	731	&ls_apb_src_rate.clk.hw);
	732
	733	K230_CLK_GATE_FORMAT(ls_pwm_apb_gate,
	734	K230_LS_PWM_APB_GATE,
	735	0x24, 12, 0, 0,
	736	&ls_apb_src_rate.clk.hw);
	737
	738	K230_CLK_GATE_FORMAT(ls_jamlink0_apb_gate,
	739	K230_LS_JAMLINK0_APB_GATE,
	740	0x28, 4, 0, 0,
	741	&ls_apb_src_rate.clk.hw);
	742
	743	K230_CLK_GATE_FORMAT(ls_jamlink1_apb_gate,
	744	K230_LS_JAMLINK1_APB_GATE,
	745	0x28, 5, 0, 0,
	746	&ls_apb_src_rate.clk.hw);
	747
	748	K230_CLK_GATE_FORMAT(ls_jamlink2_apb_gate,
	749	K230_LS_JAMLINK2_APB_GATE,
	750	0x28, 6, 0, 0,
	751	&ls_apb_src_rate.clk.hw);
	752
	753	K230_CLK_GATE_FORMAT(ls_jamlink3_apb_gate,
	754	K230_LS_JAMLINK3_APB_GATE,
	755	0x28, 7, 0, 0,
	756	&ls_apb_src_rate.clk.hw);
	757
	758	K230_CLK_GATE_FORMAT(ls_audio_apb_gate,
	759	K230_LS_AUDIO_APB_GATE,
	760	0x24, 13, 0, 0,
	761	&ls_apb_src_rate.clk.hw);
	762
	763	K230_CLK_GATE_FORMAT(ls_adc_apb_gate,
	764	K230_LS_ADC_APB_GATE,
	765	0x24, 15, 0, 0,
	766	&ls_apb_src_rate.clk.hw);
	767
	768	K230_CLK_GATE_FORMAT(ls_codec_apb_gate,
	769	K230_LS_CODEC_APB_GATE,
	770	0x24, 14, 0, 0,
	771	&ls_apb_src_rate.clk.hw);
	772
	773	K230_CLK_GATE_FORMAT(ls_i2c0_gate,
	774	K230_LS_I2C0_GATE,
	775	0x24, 21, 0, 0,
	776	&pll0_div4.hw);
	777
	778	K230_CLK_RATE_FORMAT(ls_i2c0_rate,
	779	K230_LS_I2C0_RATE,
	780	1, 1, 0, 0,
	781	1, 8, 15, 0x7,
	782	0x2C, 31, div, 0x0,
	783	false, 0,
	784	&ls_i2c0_gate.clk.hw);
	785
	786	K230_CLK_GATE_FORMAT(ls_i2c1_gate,
	787	K230_LS_I2C1_GATE,
	788	0x24, 22, 0, 0,
	789	&pll0_div4.hw);
	790
	791	K230_CLK_RATE_FORMAT(ls_i2c1_rate,
	792	K230_LS_I2C1_RATE,
	793	1, 1, 0, 0,
	794	1, 8, 18, 0x7,
	795	0x2C, 31, div, 0x0,
	796	false, 0,
	797	&ls_i2c1_gate.clk.hw);
	798
	799	K230_CLK_GATE_FORMAT(ls_i2c2_gate,
	800	K230_LS_I2C2_GATE,
	801	0x24, 23, 0, 0,
	802	&pll0_div4.hw);
	803
	804	K230_CLK_RATE_FORMAT(ls_i2c2_rate,
	805	K230_LS_I2C2_RATE,
	806	1, 1, 0, 0,
	807	1, 8, 21, 0x7,
	808	0x2C, 31, div, 0x0,
	809	false, 0,
	810	&ls_i2c2_gate.clk.hw);
	811
	812	K230_CLK_GATE_FORMAT(ls_i2c3_gate,
	813	K230_LS_I2C3_GATE,
	814	0x24, 24, 0, 0,
	815	&pll0_div4.hw);
	816
	817	K230_CLK_RATE_FORMAT(ls_i2c3_rate,
	818	K230_LS_I2C3_RATE,
	819	1, 1, 0, 0,
	820	1, 8, 24, 0x7,
	821	0x2C, 31, div, 0x0,
	822	false, 0,
	823	&ls_i2c3_gate.clk.hw);
	824
	825	K230_CLK_GATE_FORMAT(ls_i2c4_gate,
	826	K230_LS_I2C4_GATE,
	827	0x24, 25, 0, 0,
	828	&pll0_div4.hw);
	829
	830	K230_CLK_RATE_FORMAT(ls_i2c4_rate,
	831	K230_LS_I2C4_RATE,
	832	1, 1, 0, 0,
	833	1, 8, 27, 0x7,
	834	0x2C, 31, div, 0x0,
	835	false, 0,
	836	&ls_i2c4_gate.clk.hw);
	837
	838	K230_CLK_GATE_FORMAT(ls_codec_adc_gate,
	839	K230_LS_CODEC_ADC_GATE,
	840	0x24, 29, 0, 0,
	841	&pll0_div4.hw);
	842
	843	K230_CLK_RATE_FORMAT(ls_codec_adc_rate,
	844	K230_LS_CODEC_ADC_RATE,
	845	0x10, 0x1B9, 14, 0x1FFF,
	846	0xC35, 0x3D09, 0, 0x3FFF,
	847	0x38, 31, mul_div, 0x38,
	848	false, 0,
	849	&ls_codec_adc_gate.clk.hw);
	850
	851	K230_CLK_GATE_FORMAT(ls_codec_dac_gate,
	852	K230_LS_CODEC_DAC_GATE,
	853	0x24, 30, 0, 0,
	854	&pll0_div4.hw);
	855
	856	K230_CLK_RATE_FORMAT(ls_codec_dac_rate,
	857	K230_LS_CODEC_DAC_RATE,
	858	0x10, 0x1B9, 14, 0x1FFF,
	859	0xC35, 0x3D09, 0, 0x3FFF,
	860	0x3C, 31, mul_div, 0x3C,
	861	false, 0,
	862	&ls_codec_dac_gate.clk.hw);
	863
	864	K230_CLK_GATE_FORMAT(ls_audio_dev_gate,
	865	K230_LS_AUDIO_DEV_GATE,
	866	0x24, 28, 0, 0,
	867	&pll0_div4.hw);
	868
	869	K230_CLK_RATE_FORMAT(ls_audio_dev_rate,
	870	K230_LS_AUDIO_DEV_RATE,
	871	0x4, 0x1B9, 16, 0x7FFF,
	872	0xC35, 0xF424, 0, 0xFFFF,
	873	0x34, 31, mul_div, 0x34,
	874	false, 0,
	875	&ls_audio_dev_gate.clk.hw);
	876
	877	K230_CLK_GATE_FORMAT(ls_pdm_gate,
	878	K230_LS_PDM_GATE,
	879	0x24, 31, 0, 0,
	880	&pll0_div4.hw);
	881
	882	K230_CLK_RATE_FORMAT(ls_pdm_rate,
	883	K230_LS_PDM_RATE,
	884	0x2, 0x1B9, 0, 0xFFFF,
	885	0xC35, 0x1E848, 0, 0x1FFFF,
	886	0x40, 0, mul_div, 0x44,
	887	false, 0,
	888	&ls_pdm_gate.clk.hw);
	889
	890	K230_CLK_GATE_FORMAT(ls_adc_gate,
	891	K230_LS_ADC_GATE,
	892	0x24, 26, 0, 0,
	893	&pll0_div4.hw);
	894
	895	K230_CLK_RATE_FORMAT(ls_adc_rate,
	896	K230_LS_ADC_RATE,
	897	1, 1, 0, 0,
	898	1, 1024, 3, 0x3FF,
	899	0x30, 31, div, 0x0,
	900	false, 0,
	901	&ls_adc_gate.clk.hw);
	902
	903	K230_CLK_GATE_FORMAT(ls_uart0_gate,
	904	K230_LS_UART0_GATE,
	905	0x24, 16, CLK_IS_CRITICAL, 0,
	906	&pll0_div16.hw);
	907
	908	K230_CLK_RATE_FORMAT(ls_uart0_rate,
	909	K230_LS_UART0_RATE,
	910	1, 1, 0, 0,
	911	1, 8, 0, 0x7,
	912	0x2C, 31, div, 0x0,
	913	false, 0,
	914	&ls_uart0_gate.clk.hw);
	915
	916	K230_CLK_GATE_FORMAT(ls_uart1_gate,
	917	K230_LS_UART1_GATE,
	918	0x24, 17, CLK_IS_CRITICAL, 0,
	919	&pll0_div16.hw);
	920
	921	K230_CLK_RATE_FORMAT(ls_uart1_rate,
	922	K230_LS_UART1_RATE,
	923	1, 1, 0, 0,
	924	1, 8, 3, 0x7,
	925	0x2C, 31, div, 0x0,
	926	false, 0,
	927	&ls_uart1_gate.clk.hw);
	928
	929	K230_CLK_GATE_FORMAT(ls_uart2_gate,
	930	K230_LS_UART2_GATE,
	931	0x24, 18, CLK_IS_CRITICAL, 0,
	932	&pll0_div16.hw);
	933
	934	K230_CLK_RATE_FORMAT(ls_uart2_rate,
	935	K230_LS_UART2_RATE,
	936	1, 1, 0, 0,
	937	1, 8, 6, 0x7,
	938	0x2C, 31, div, 0x0,
	939	false, 0,
	940	&ls_uart2_gate.clk.hw);
	941
	942	K230_CLK_GATE_FORMAT(ls_uart3_gate,
	943	K230_LS_UART3_GATE,
	944	0x24, 19, CLK_IS_CRITICAL, 0,
	945	&pll0_div16.hw);
	946
	947	K230_CLK_RATE_FORMAT(ls_uart3_rate,
	948	K230_LS_UART3_RATE,
	949	1, 1, 0, 0,
	950	1, 8, 9, 0x7,
	951	0x2C, 31, div, 0x0,
	952	false, 0,
	953	&ls_uart3_gate.clk.hw);
	954
	955	K230_CLK_GATE_FORMAT(ls_uart4_gate,
	956	K230_LS_UART4_GATE,
	957	0x24, 20, CLK_IS_CRITICAL, 0,
	958	&pll0_div16.hw);
	959
	960	K230_CLK_RATE_FORMAT(ls_uart4_rate,
	961	K230_LS_UART4_RATE,
	962	1, 1, 0, 0,
	963	1, 8, 12, 0x7,
	964	0x2C, 31, div, 0x0,
	965	false, 0,
	966	&ls_uart4_gate.clk.hw);
	967
	968	K230_CLK_RATE_FORMAT(ls_jamlinkco_src_rate,
	969	K230_LS_JAMLINKCO_SRC_RATE,
	970	1, 1, 0, 0,
	971	2, 512, 23, 0xFF,
	972	0x30, 31, div, 0x0,
	973	false, 0,
	974	&pll0_div16.hw);
	975
	976	K230_CLK_GATE_FORMAT(ls_jamlink0co_gate,
	977	K230_LS_JAMLINK0CO_GATE,
	978	0x28, 0, 0, 0,
	979	&ls_jamlinkco_src_rate.clk.hw);
	980
	981	K230_CLK_GATE_FORMAT(ls_jamlink1co_gate,
	982	K230_LS_JAMLINK1CO_GATE,
	983	0x28, 1, 0, 0,
	984	&ls_jamlinkco_src_rate.clk.hw);
	985
	986	K230_CLK_GATE_FORMAT(ls_jamlink2co_gate,
	987	K230_LS_JAMLINK2CO_GATE,
	988	0x28, 2, 0, 0,
	989	&ls_jamlinkco_src_rate.clk.hw);
	990
	991	K230_CLK_GATE_FORMAT(ls_jamlink3co_gate,
	992	K230_LS_JAMLINK3CO_GATE,
	993	0x28, 3, 0, 0,
	994	&ls_jamlinkco_src_rate.clk.hw);
	995
	996	K230_CLK_GATE_FORMAT_PNAME(ls_gpio_debounce_gate,
	997	K230_LS_GPIO_DEBOUNCE_GATE,
	998	0x24, 27, 0, 0,
	999	"osc24m");
	1000
	1001	K230_CLK_RATE_FORMAT(ls_gpio_debounce_rate,
	1002	K230_LS_GPIO_DEBOUNCE_RATE,
	1003	1, 1, 0, 0,
	1004	1, 1024, 13, 0x3FF,
	1005	0x30, 31, div, 0x0,
	1006	false, 0,
	1007	&ls_gpio_debounce_gate.clk.hw);
	1008
	1009	K230_CLK_GATE_FORMAT(sysctl_wdt0_apb_gate,
	1010	K230_SYSCTL_WDT0_APB_GATE,
	1011	0x50, 1, 0, 0,
	1012	&pll0_div16.hw);
	1013
	1014	K230_CLK_GATE_FORMAT(sysctl_wdt1_apb_gate,
	1015	K230_SYSCTL_WDT1_APB_GATE,
	1016	0x50, 2, 0, 0,
	1017	&pll0_div16.hw);
	1018
	1019	K230_CLK_GATE_FORMAT(sysctl_timer_apb_gate,
	1020	K230_SYSCTL_TIMER_APB_GATE,
	1021	0x50, 3, 0, 0,
	1022	&pll0_div16.hw);
	1023
	1024	K230_CLK_GATE_FORMAT(sysctl_iomux_apb_gate,
	1025	K230_SYSCTL_IOMUX_APB_GATE,
	1026	0x50, 20, 0, 0,
	1027	&pll0_div16.hw);
	1028
	1029	K230_CLK_GATE_FORMAT(sysctl_mailbox_apb_gate,
	1030	K230_SYSCTL_MAILBOX_APB_GATE,
	1031	0x50, 4, 0, 0,
	1032	&pll0_div16.hw);
	1033
	1034	K230_CLK_GATE_FORMAT(sysctl_hdi_gate,
	1035	K230_SYSCTL_HDI_GATE,
	1036	0x50, 21, 0, 0,
	1037	&pll0_div4.hw);
	1038
	1039	K230_CLK_RATE_FORMAT(sysctl_hdi_rate,
	1040	K230_SYSCTL_HDI_RATE,
	1041	1, 1, 0, 0,
	1042	1, 8, 28, 0x7,
	1043	0x58, 31, div, 0x0,
	1044	false, 0,
	1045	&sysctl_hdi_gate.clk.hw);
	1046
	1047	K230_CLK_GATE_FORMAT(sysctl_time_stamp_gate,
	1048	K230_SYSCTL_TIME_STAMP_GATE,
	1049	0x50, 19, CLK_IS_CRITICAL, 0,
	1050	&pll1_div4.hw);
	1051
	1052	K230_CLK_RATE_FORMAT(sysctl_time_stamp_rate,
	1053	K230_SYSCTL_TIME_STAMP_RATE,
	1054	1, 1, 0, 0,
	1055	1, 32, 15, 0x1F,
	1056	0x58, 31, div, 0x0,
	1057	false, 0,
	1058	&sysctl_time_stamp_gate.clk.hw);
	1059
	1060	K230_CLK_RATE_FORMAT_PNAME(sysctl_temp_sensor_rate,
	1061	K230_SYSCTL_TEMP_SENSOR_RATE,
	1062	1, 1, 0, 0,
	1063	1, 256, 20, 0xFF,
	1064	0x58, 31, div, 0x0,
	1065	false, 0,
	1066	"osc24m");
	1067
	1068	K230_CLK_GATE_FORMAT_PNAME(sysctl_wdt0_gate,
	1069	K230_SYSCTL_WDT0_GATE,
	1070	0x50, 5, 0, 0,
	1071	"osc24m");
	1072
	1073	K230_CLK_RATE_FORMAT(sysctl_wdt0_rate,
	1074	K230_SYSCTL_WDT0_RATE,
	1075	1, 1, 0, 0,
	1076	1, 64, 3, 0x3F,
	1077	0x58, 31, div, 0x0,
	1078	false, 0,
	1079	&sysctl_wdt0_gate.clk.hw);
	1080
	1081	K230_CLK_GATE_FORMAT_PNAME(sysctl_wdt1_gate,
	1082	K230_SYSCTL_WDT1_GATE,
	1083	0x50, 6, 0, 0,
	1084	"osc24m");
	1085
	1086	K230_CLK_RATE_FORMAT(sysctl_wdt1_rate,
	1087	K230_SYSCTL_WDT1_RATE,
	1088	1, 1, 0, 0,
	1089	1, 64, 9, 0x3F,
	1090	0x58, 31, div, 0x0,
	1091	false, 0,
	1092	&sysctl_wdt1_gate.clk.hw);
	1093
	1094	K230_CLK_RATE_FORMAT(timer0_src_rate,
	1095	K230_TIMER0_SRC_RATE,
	1096	1, 1, 0, 0,
	1097	1, 8, 0, 0x7,
	1098	0x54, 31, div, 0x0,
	1099	false, 0,
	1100	&pll0_div16.hw);
	1101
	1102	K230_CLK_RATE_FORMAT(timer1_src_rate,
	1103	K230_TIMER1_SRC_RATE,
	1104	1, 1, 0, 0,
	1105	1, 8, 3, 0x7,
	1106	0x54, 31, div, 0x0,
	1107	false, 0,
	1108	&pll0_div16.hw);
	1109
	1110	K230_CLK_RATE_FORMAT(timer2_src_rate,
	1111	K230_TIMER2_SRC_RATE,
	1112	1, 1, 0, 0,
	1113	1, 8, 6, 0x7,
	1114	0x54, 31, div, 0x0,
	1115	false, 0,
	1116	&pll0_div16.hw);
	1117
	1118	K230_CLK_RATE_FORMAT(timer3_src_rate,
	1119	K230_TIMER3_SRC_RATE,
	1120	1, 1, 0, 0,
	1121	1, 8, 9, 0x7,
	1122	0x54, 31, div, 0x0,
	1123	false, 0,
	1124	&pll0_div16.hw);
	1125
	1126	K230_CLK_RATE_FORMAT(timer4_src_rate,
	1127	K230_TIMER4_SRC_RATE,
	1128	1, 1, 0, 0,
	1129	1, 8, 12, 0x7,
	1130	0x54, 31, div, 0x0,
	1131	false, 0,
	1132	&pll0_div16.hw);
	1133
	1134	K230_CLK_RATE_FORMAT(timer5_src_rate,
	1135	K230_TIMER5_SRC_RATE,
	1136	1, 1, 0, 0,
	1137	1, 8, 15, 0x7,
	1138	0x54, 31, div, 0x0,
	1139	false, 0,
	1140	&pll0_div16.hw);
	1141
	1142	static const struct clk_parent_data k230_timer0_mux_pdata[] = {
	1143	{ .fw_name = "timer-pulse-in", },
	1144	{ .hw = &timer0_src_rate.clk.hw, },
	1145	};
	1146
	1147	K230_CLK_MUX_FORMAT(timer0_mux,
	1148	K230_TIMER0_MUX,
	1149	0x50, 7, 0x1,
	1150	0, 0,
	1151	k230_timer0_mux_pdata);
	1152
	1153	K230_CLK_GATE_FORMAT(timer0_gate,
	1154	K230_TIMER0_GATE,
	1155	0x50, 13, CLK_IGNORE_UNUSED, 0,
	1156	&timer0_mux.clk.hw);
	1157
	1158	static const struct clk_parent_data k230_timer1_mux_pdata[] = {
	1159	{ .fw_name = "timer-pulse-in", },
	1160	{ .hw = &timer1_src_rate.clk.hw, },
	1161	};
	1162
	1163	K230_CLK_MUX_FORMAT(timer1_mux,
	1164	K230_TIMER1_MUX,
	1165	0x50, 8, 0x1,
	1166	0, 0,
	1167	k230_timer1_mux_pdata);
	1168
	1169	K230_CLK_GATE_FORMAT(timer1_gate,
	1170	K230_TIMER1_GATE,
	1171	0x50, 14, CLK_IGNORE_UNUSED, 0,
	1172	&timer1_mux.clk.hw);
	1173
	1174	static const struct clk_parent_data k230_timer2_mux_pdata[] = {
	1175	{ .fw_name = "timer-pulse-in", },
	1176	{ .hw = &timer2_src_rate.clk.hw, },
	1177	};
	1178
	1179	K230_CLK_MUX_FORMAT(timer2_mux,
	1180	K230_TIMER2_MUX,
	1181	0x50, 9, 0x1,
	1182	0, 0,
	1183	k230_timer2_mux_pdata);
	1184
	1185	K230_CLK_GATE_FORMAT(timer2_gate,
	1186	K230_TIMER2_GATE,
	1187	0x50, 15, CLK_IGNORE_UNUSED, 0,
	1188	&timer2_mux.clk.hw);
	1189
	1190	static const struct clk_parent_data k230_timer3_mux_pdata[] = {
	1191	{ .fw_name = "timer-pulse-in", },
	1192	{ .hw = &timer3_src_rate.clk.hw, },
	1193	};
	1194
	1195	K230_CLK_MUX_FORMAT(timer3_mux,
	1196	K230_TIMER3_MUX,
	1197	0x50, 10, 0x1,
	1198	0, 0,
	1199	k230_timer3_mux_pdata);
	1200
	1201	K230_CLK_GATE_FORMAT(timer3_gate,
	1202	K230_TIMER3_GATE,
	1203	0x50, 16, CLK_IGNORE_UNUSED, 0,
	1204	&timer3_mux.clk.hw);
	1205
	1206	static const struct clk_parent_data k230_timer4_mux_pdata[] = {
	1207	{ .fw_name = "timer-pulse-in", },
	1208	{ .hw = &timer4_src_rate.clk.hw, },
	1209	};
	1210
	1211	K230_CLK_MUX_FORMAT(timer4_mux,
	1212	K230_TIMER4_MUX,
	1213	0x50, 11, 0x1,
	1214	0, 0,
	1215	k230_timer4_mux_pdata);
	1216
	1217	K230_CLK_GATE_FORMAT(timer4_gate,
	1218	K230_TIMER4_GATE,
	1219	0x50, 17, CLK_IGNORE_UNUSED, 0,
	1220	&timer4_mux.clk.hw);
	1221
	1222	static const struct clk_parent_data k230_timer5_mux_pdata[] = {
	1223	{ .fw_name = "timer-pulse-in", },
	1224	{ .hw = &timer5_src_rate.clk.hw, },
	1225	};
	1226
	1227	K230_CLK_MUX_FORMAT(timer5_mux,
	1228	K230_TIMER5_MUX,
	1229	0x50, 12, 0x1,
	1230	0, 0,
	1231	k230_timer5_mux_pdata);
	1232
	1233	K230_CLK_GATE_FORMAT(timer5_gate,
	1234	K230_TIMER5_GATE,
	1235	0x50, 18, CLK_IGNORE_UNUSED, 0,
	1236	&timer5_mux.clk.hw);
	1237
	1238	K230_CLK_GATE_FORMAT(shrm_apb_gate,
	1239	K230_SHRM_APB_GATE,
	1240	0x5C, 0, 0, 0,
	1241	&pll0_div4.hw);
	1242
	1243	K230_CLK_RATE_FORMAT(shrm_apb_rate,
	1244	K230_SHRM_APB_RATE,
	1245	1, 1, 0, 0,
	1246	1, 8, 18, 0x7,
	1247	0x5C, 31, div, 0x0,
	1248	false, 0,
	1249	&shrm_apb_gate.clk.hw);
	1250
	1251	static const struct clk_parent_data k230_shrm_sram_mux_pdata[] = {
	1252	{ .hw = &pll3_div2.hw, },
	1253	{ .hw = &pll0_div2.hw, },
	1254	};
	1255
	1256	K230_CLK_MUX_FORMAT(shrm_sram_mux,
	1257	K230_SHRM_SRAM_MUX,
	1258	0x50, 14, 0x1,
	1259	0, 0,
	1260	k230_shrm_sram_mux_pdata);
	1261
	1262	K230_CLK_GATE_FORMAT(shrm_sram_gate,
	1263	K230_SHRM_SRAM_GATE,
	1264	0x5c, 10, CLK_IGNORE_UNUSED, 0,
	1265	&shrm_sram_mux.clk.hw);
	1266
	1267	K230_CLK_FIXED_FACTOR_FORMAT(shrm_sram_div2,
	1268	1, 2, 0,
	1269	&shrm_sram_gate.clk.hw);
	1270
	1271	K230_CLK_GATE_FORMAT(shrm_axi_slave_gate,
	1272	K230_SHRM_AXI_SLAVE_GATE,
	1273	0x5C, 11, CLK_IGNORE_UNUSED, 0,
	1274	&shrm_sram_div2.hw);
	1275
	1276	K230_CLK_GATE_FORMAT(shrm_axi_gate,
	1277	K230_SHRM_AXI_GATE,
	1278	0x5C, 12, 0, 0,
	1279	&pll0_div4.hw);
	1280
	1281	K230_CLK_GATE_FORMAT(shrm_nonai2d_axi_gate,
	1282	K230_SHRM_NONAI2D_AXI_GATE,
	1283	0x5C, 9, 0, 0,
	1284	&shrm_axi_gate.clk.hw);
	1285
	1286	K230_CLK_GATE_FORMAT(shrm_decompress_axi_gate,
	1287	K230_SHRM_DECOMPRESS_AXI_GATE,
	1288	0x5C, 7, CLK_IGNORE_UNUSED, 0,
	1289	&shrm_sram_gate.clk.hw);
	1290
	1291	K230_CLK_GATE_FORMAT(shrm_sdma_axi_gate,
	1292	K230_SHRM_SDMA_AXI_GATE,
	1293	0x5C, 5, 0, 0,
	1294	&shrm_axi_gate.clk.hw);
	1295
	1296	K230_CLK_GATE_FORMAT(shrm_pdma_axi_gate,
	1297	K230_SHRM_PDMA_AXI_GATE,
	1298	0x5C, 3, 0, 0,
	1299	&shrm_axi_gate.clk.hw);
	1300
	1301	static const struct clk_parent_data k230_ddrc_src_mux_pdata[] = {
	1302	{ .hw = &pll0_div2.hw, },
	1303	{ .hw = &pll0_div3.hw, },
	1304	{ .hw = &pll2_div4.hw, },
	1305	};
	1306
	1307	K230_CLK_MUX_FORMAT(ddrc_src_mux,
	1308	K230_DDRC_SRC_MUX,
	1309	0x60, 0, 0x3,
	1310	0, 0,
	1311	k230_ddrc_src_mux_pdata);
	1312
	1313	K230_CLK_GATE_FORMAT(ddrc_src_gate,
	1314	K230_DDRC_SRC_GATE,
	1315	0x60, 2, CLK_IGNORE_UNUSED, 0,
	1316	&ddrc_src_mux.clk.hw);
	1317
	1318	K230_CLK_RATE_FORMAT(ddrc_src_rate,
	1319	K230_DDRC_SRC_RATE,
	1320	1, 1, 0, 0,
	1321	1, 16, 10, 0xF,
	1322	0x60, 31, div, 0x0,
	1323	false, 0,
	1324	&ddrc_src_gate.clk.hw);
	1325
	1326	K230_CLK_GATE_FORMAT(ddrc_bypass_gate,
	1327	K230_DDRC_BYPASS_GATE,
	1328	0x60, 8, 0, 0,
	1329	&pll2_div4.hw);
	1330
	1331	K230_CLK_GATE_FORMAT(ddrc_apb_gate,
	1332	K230_DDRC_APB_GATE,
	1333	0x60, 9, 0, 0,
	1334	&pll0_div4.hw);
	1335
	1336	K230_CLK_RATE_FORMAT(ddrc_apb_rate,
	1337	K230_DDRC_APB_RATE,
	1338	1, 1, 0, 0,
	1339	1, 16, 14, 0xF,
	1340	0x60, 31, div, 0x0,
	1341	false, 0,
	1342	&ddrc_apb_gate.clk.hw);
	1343
	1344	K230_CLK_GATE_FORMAT(display_ahb_gate,
	1345	K230_DISPLAY_AHB_GATE,
	1346	0x74, 0, 0, 0,
	1347	&pll0_div4.hw);
	1348
	1349	K230_CLK_RATE_FORMAT(display_ahb_rate,
	1350	K230_DISPLAY_AHB_RATE,
	1351	1, 1, 0, 0,
	1352	1, 8, 0, 0x7,
	1353	0x78, 31, div, 0x0,
	1354	false, 0,
	1355	&display_ahb_gate.clk.hw);
	1356
	1357	K230_CLK_GATE_FORMAT(display_axi_gate,
	1358	K230_DISPLAY_AXI_GATE,
	1359	0x74, 1, 0, 0,
	1360	&pll0_div4.hw);
	1361
	1362	K230_CLK_RATE_FORMAT(display_clkext_rate,
	1363	K230_DISPLAY_CLKEXT_RATE,
	1364	1, 1, 0, 0,
	1365	1, 16, 16, 0xF,
	1366	0x78, 31, div, 0x0,
	1367	false, 0,
	1368	&pll0_div3.hw);
	1369
	1370	K230_CLK_GATE_FORMAT(display_gpu_gate,
	1371	K230_DISPLAY_GPU_GATE,
	1372	0x74, 6, 0, 0,
	1373	&pll0_div3.hw);
	1374
	1375	K230_CLK_RATE_FORMAT(display_gpu_rate,
	1376	K230_DISPLAY_GPU_RATE,
	1377	1, 1, 0, 0,
	1378	1, 16, 20, 0xF,
	1379	0x78, 31, div, 0x0,
	1380	false, 0,
	1381	&display_gpu_gate.clk.hw);
	1382
	1383	K230_CLK_GATE_FORMAT(display_dpip_gate,
	1384	K230_DISPLAY_DPIP_GATE,
	1385	0x74, 2, 0, 0,
	1386	&pll1_div4.hw);
	1387
	1388	K230_CLK_RATE_FORMAT(display_dpip_rate,
	1389	K230_DISPLAY_DPIP_RATE,
	1390	1, 1, 0, 0,
	1391	1, 256, 3, 0xFF,
	1392	0x78, 31, div, 0x0,
	1393	false, 0,
	1394	&display_dpip_gate.clk.hw);
	1395
	1396	K230_CLK_GATE_FORMAT(display_cfg_gate,
	1397	K230_DISPLAY_CFG_GATE,
	1398	0x74, 4, 0, 0,
	1399	&pll1_div4.hw);
	1400
	1401	K230_CLK_RATE_FORMAT(display_cfg_rate,
	1402	K230_DISPLAY_CFG_RATE,
	1403	1, 1, 0, 0,
	1404	1, 32, 11, 0x1F,
	1405	0x78, 31, div, 0x0,
	1406	false, 0,
	1407	&display_cfg_gate.clk.hw);
	1408
	1409	K230_CLK_GATE_FORMAT_PNAME(display_ref_gate,
	1410	K230_DISPLAY_REF_GATE,
	1411	0x74, 3, 0, 0,
	1412	"osc24m");
	1413
	1414	K230_CLK_GATE_FORMAT(vpu_src_gate,
	1415	K230_VPU_SRC_GATE,
	1416	0xC, 0, 0, 0,
	1417	&pll0_div2.hw);
	1418
	1419	K230_CLK_RATE_FORMAT(vpu_src_rate,
	1420	K230_VPU_SRC_RATE,
	1421	1, 16, 1, 0xF,
	1422	16, 16, 0, 0,
	1423	0x0, 31, mul, 0xC,
	1424	false, 0,
	1425	&vpu_src_gate.clk.hw);
	1426
	1427	K230_CLK_RATE_FORMAT(vpu_axi_src_rate,
	1428	K230_VPU_AXI_SRC_RATE,
	1429	1, 1, 0, 0,
	1430	1, 16, 6, 0xF,
	1431	0xC, 31, div, 0x0,
	1432	false, 0,
	1433	&vpu_src_rate.clk.hw);
	1434
	1435	K230_CLK_GATE_FORMAT(vpu_axi_gate,
	1436	K230_VPU_AXI_GATE,
	1437	0xC, 5, 0, 0,
	1438	&vpu_axi_src_rate.clk.hw);
	1439
	1440	K230_CLK_GATE_FORMAT(vpu_ddrcp2_gate,
	1441	K230_VPU_DDRCP2_GATE,
	1442	0x60, 5, 0, 0,
	1443	&vpu_axi_src_rate.clk.hw);
	1444
	1445	K230_CLK_GATE_FORMAT(vpu_cfg_gate,
	1446	K230_VPU_CFG_GATE,
	1447	0xC, 10, 0, 0,
	1448	&pll0_div4.hw);
	1449
	1450	K230_CLK_RATE_FORMAT(vpu_cfg_rate,
	1451	K230_VPU_CFG_RATE,
	1452	1, 1, 0, 0,
	1453	1, 16, 11, 0xF,
	1454	0xC, 31, div, 0x0,
	1455	false, 0,
	1456	&vpu_cfg_gate.clk.hw);
	1457
	1458	K230_CLK_GATE_FORMAT(sec_apb_gate,
	1459	K230_SEC_APB_GATE,
	1460	0x80, 0, 0, 0,
	1461	&pll1_div4.hw);
	1462
	1463	K230_CLK_RATE_FORMAT(sec_apb_rate,
	1464	K230_SEC_APB_RATE,
	1465	1, 1, 0, 0,
	1466	1, 8, 1, 0x7,
	1467	0x80, 31, div, 0x0,
	1468	false, 0,
	1469	&sec_apb_gate.clk.hw);
	1470
	1471	K230_CLK_GATE_FORMAT(sec_fix_gate,
	1472	K230_SEC_FIX_GATE,
	1473	0x80, 5, 0, 0,
	1474	&pll1_div4.hw);
	1475
	1476	K230_CLK_RATE_FORMAT(sec_fix_rate,
	1477	K230_SEC_FIX_RATE,
	1478	1, 1, 0, 0,
	1479	1, 32, 6, 0x1F,
	1480	0x80, 31, div, 0x0,
	1481	false, 0,
	1482	&sec_fix_gate.clk.hw);
	1483
	1484	K230_CLK_GATE_FORMAT(sec_axi_gate,
	1485	K230_SEC_AXI_GATE,
	1486	0x80, 4, 0, 0,
	1487	&pll1_div4.hw);
	1488
	1489	K230_CLK_RATE_FORMAT(sec_axi_rate,
	1490	K230_SEC_AXI_RATE,
	1491	1, 1, 0, 0,
	1492	1, 8, 11, 0x3,
	1493	0x80, 31, div, 0,
	1494	false, 0,
	1495	&sec_axi_gate.clk.hw);
	1496
	1497	K230_CLK_GATE_FORMAT(usb_480m_gate,
	1498	K230_USB_480M_GATE,
	1499	0x100, 0, 0, 0,
	1500	&pll1.hw);
	1501
	1502	K230_CLK_RATE_FORMAT(usb_480m_rate,
	1503	K230_USB_480M_RATE,
	1504	1, 1, 0, 0,
	1505	1, 8, 1, 0x7,
	1506	0x100, 31, div, 0,
	1507	false, 0,
	1508	&usb_480m_gate.clk.hw);
	1509
	1510	K230_CLK_GATE_FORMAT(usb_100m_gate,
	1511	K230_USB_100M_GATE,
	1512	0x100, 0, 0, 0,
	1513	&pll0_div4.hw);
	1514
	1515	K230_CLK_RATE_FORMAT(usb_100m_rate,
	1516	K230_USB_100M_RATE,
	1517	1, 1, 0, 0,
	1518	1, 8, 4, 0x7,
	1519	0x100, 31, div, 0,
	1520	false, 0,
	1521	&usb_100m_gate.clk.hw);
	1522
	1523	K230_CLK_GATE_FORMAT(dphy_dft_gate,
	1524	K230_DPHY_DFT_GATE,
	1525	0x100, 0, 0, 0,
	1526	&pll0.hw);
	1527
	1528	K230_CLK_RATE_FORMAT(dphy_dft_rate,
	1529	K230_DPHY_DFT_RATE,
	1530	1, 1, 0, 0,
	1531	1, 16, 1, 0xF,
	1532	0x104, 31, div, 0,
	1533	false, 0,
	1534	&dphy_dft_gate.clk.hw);
	1535
	1536	K230_CLK_GATE_FORMAT(spi2axi_gate,
	1537	K230_SPI2AXI_GATE,
	1538	0x108, 0, 0, 0,
	1539	&pll0_div4.hw);
	1540
	1541	K230_CLK_RATE_FORMAT(spi2axi_rate,
	1542	K230_SPI2AXI_RATE,
	1543	1, 1, 0, 0,
	1544	1, 8, 1, 0x7,
	1545	0x108, 31, div, 0x0,
	1546	false, 0,
	1547	&spi2axi_gate.clk.hw);
	1548
	1549	static const struct clk_parent_data k230_ai_src_mux_pdata[] = {
	1550	{ .hw = &pll0_div2.hw, },
	1551	{ .hw = &pll3_div2.hw, },
	1552	};
	1553
	1554	K230_CLK_MUX_FORMAT(ai_src_mux,
	1555	K230_AI_SRC_MUX,
	1556	0x8, 2, 0x1,
	1557	0, 0,
	1558	k230_ai_src_mux_pdata);
	1559
	1560	K230_CLK_GATE_FORMAT(ai_src_gate,
	1561	K230_AI_SRC_GATE,
	1562	0x8, 0, CLK_IGNORE_UNUSED, 0,
	1563	&ai_src_mux.clk.hw);
	1564
	1565	K230_CLK_RATE_FORMAT(ai_src_rate,
	1566	K230_AI_SRC_RATE,
	1567	1, 1, 0, 0,
	1568	1, 8, 3, 0x7,
	1569	0x8, 31, div, 0x0,
	1570	false, 0,
	1571	&ai_src_gate.clk.hw);
	1572
	1573	K230_CLK_GATE_FORMAT(ai_axi_gate,
	1574	K230_AI_AXI_GATE,
	1575	0x8, 10, 0, 0,
	1576	&pll0_div4.hw);
	1577
	1578	static const struct clk_parent_data k230_camera0_mux_pdata[] = {
	1579	{ .hw = &pll1_div3.hw, },
	1580	{ .hw = &pll1_div4.hw, },
	1581	{ .hw = &pll0_div4.hw, },
	1582	};
	1583
	1584	K230_CLK_MUX_FORMAT(camera0_mux,
	1585	K230_CAMERA0_MUX,
	1586	0x6C, 3, 0x3,
	1587	0, 0,
	1588	k230_camera0_mux_pdata);
	1589
	1590	K230_CLK_GATE_FORMAT(camera0_gate,
	1591	K230_CAMERA0_GATE,
	1592	0x6C, 0, CLK_IGNORE_UNUSED, 0,
	1593	&camera0_mux.clk.hw);
	1594
	1595	K230_CLK_RATE_FORMAT(camera0_rate,
	1596	K230_CAMERA0_RATE,
	1597	1, 1, 0, 0,
	1598	1, 32, 5, 0x1f,
	1599	0x6C, 31, div, 0x0,
	1600	false, 0,
	1601	&camera0_gate.clk.hw);
	1602
	1603	static const struct clk_parent_data k230_camera1_mux_pdata[] = {
	1604	{ .hw = &pll1_div3.hw, },
	1605	{ .hw = &pll1_div4.hw, },
	1606	{ .hw = &pll0_div4.hw, },
	1607	};
	1608
	1609	K230_CLK_MUX_FORMAT(camera1_mux,
	1610	K230_CAMERA1_MUX,
	1611	0x6C, 10, 0x3,
	1612	0, 0,
	1613	k230_camera1_mux_pdata);
	1614
	1615	K230_CLK_GATE_FORMAT(camera1_gate,
	1616	K230_CAMERA1_GATE,
	1617	0x6C, 1, CLK_IGNORE_UNUSED, 0,
	1618	&camera1_mux.clk.hw);
	1619
	1620	K230_CLK_RATE_FORMAT(camera1_rate,
	1621	K230_CAMERA1_RATE,
	1622	1, 1, 0, 0,
	1623	1, 32, 12, 0x1f,
	1624	0x6C, 31, div, 0x0,
	1625	false, 0,
	1626	&camera1_gate.clk.hw);
	1627
	1628	static const struct clk_parent_data k230_camera2_mux_pdata[] = {
	1629	{ .hw = &pll1_div3.hw, },
	1630	{ .hw = &pll1_div4.hw, },
	1631	{ .hw = &pll0_div4.hw, },
	1632	};
	1633
	1634	K230_CLK_MUX_FORMAT(camera2_mux,
	1635	K230_CAMERA2_MUX,
	1636	0x6C, 17, 0x3,
	1637	0, 0,
	1638	k230_camera2_mux_pdata);
	1639
	1640	K230_CLK_GATE_FORMAT(camera2_gate,
	1641	K230_CAMERA2_GATE,
	1642	0x6C, 2, CLK_IGNORE_UNUSED, 0,
	1643	&camera2_mux.clk.hw);
	1644
	1645	K230_CLK_RATE_FORMAT(camera2_rate,
	1646	K230_CAMERA2_RATE,
	1647	1, 1, 0, 0,
	1648	1, 32, 19, 0x1f,
	1649	0x6C, 31, div, 0x0,
	1650	false, 0,
	1651	&camera2_gate.clk.hw);
	1652
	1653	static struct k230_clk_mux *k230_clk_muxs[] = {
	1654	&hs_ssi0_mux,
	1655	&hs_usb_ref_mux,
	1656	&cpu1_src_mux,
	1657	&timer0_mux,
	1658	&timer1_mux,
	1659	&timer2_mux,
	1660	&timer3_mux,
	1661	&timer4_mux,
	1662	&timer5_mux,
	1663	&shrm_sram_mux,
	1664	&ddrc_src_mux,
	1665	&ai_src_mux,
	1666	&camera0_mux,
	1667	&camera1_mux,
	1668	&camera2_mux,
	1669	};
	1670
	1671	#define K230_CLK_MUX_NUM ARRAY_SIZE(k230_clk_muxs)
	1672
	1673	static struct k230_clk_gate *k230_clk_gates[] = {
	1674	&cpu0_src_gate,
	1675	&cpu0_plic_gate,
	1676	&cpu0_noc_ddrcp4_gate,
	1677	&cpu0_apb_gate,
	1678	&cpu1_src_gate,
	1679	&cpu1_plic_gate,
	1680	&cpu1_apb_gate,
	1681	&pmu_apb_gate,
	1682	&hs_hclk_high_gate,
	1683	&hs_hclk_gate,
	1684	&hs_sd0_ahb_gate,
	1685	&hs_sd1_ahb_gate,
	1686	&hs_ssi1_ahb_gate,
	1687	&hs_ssi2_ahb_gate,
	1688	&hs_usb0_ahb_gate,
	1689	&hs_usb1_ahb_gate,
	1690	&hs_ssi0_axi_gate,
	1691	&hs_ssi1_gate,
	1692	&hs_ssi2_gate,
	1693	&hs_qspi_axi_src_gate,
	1694	&hs_ssi1_axi_gate,
	1695	&hs_ssi2_axi_gate,
	1696	&hs_sd_card_src_gate,
	1697	&hs_sd0_card_gate,
	1698	&hs_sd1_card_gate,
	1699	&hs_sd_axi_src_gate,
	1700	&hs_sd0_axi_gate,
	1701	&hs_sd1_axi_gate,
	1702	&hs_sd0_base_gate,
	1703	&hs_sd1_base_gate,
	1704	&hs_ssi0_gate,
	1705	&hs_sd_timer_src_gate,
	1706	&hs_sd0_timer_gate,
	1707	&hs_sd1_timer_gate,
	1708	&hs_usb0_ref_gate,
	1709	&hs_usb1_ref_gate,
	1710	&ls_apb_src_gate,
	1711	&ls_uart0_apb_gate,
	1712	&ls_uart1_apb_gate,
	1713	&ls_uart2_apb_gate,
	1714	&ls_uart3_apb_gate,
	1715	&ls_uart4_apb_gate,
	1716	&ls_i2c0_apb_gate,
	1717	&ls_i2c1_apb_gate,
	1718	&ls_i2c2_apb_gate,
	1719	&ls_i2c3_apb_gate,
	1720	&ls_i2c4_apb_gate,
	1721	&ls_gpio_apb_gate,
	1722	&ls_pwm_apb_gate,
	1723	&ls_jamlink0_apb_gate,
	1724	&ls_jamlink1_apb_gate,
	1725	&ls_jamlink2_apb_gate,
	1726	&ls_jamlink3_apb_gate,
	1727	&ls_audio_apb_gate,
	1728	&ls_adc_apb_gate,
	1729	&ls_codec_apb_gate,
	1730	&ls_i2c0_gate,
	1731	&ls_i2c1_gate,
	1732	&ls_i2c2_gate,
	1733	&ls_i2c3_gate,
	1734	&ls_i2c4_gate,
	1735	&ls_codec_adc_gate,
	1736	&ls_codec_dac_gate,
	1737	&ls_audio_dev_gate,
	1738	&ls_pdm_gate,
	1739	&ls_adc_gate,
	1740	&ls_uart0_gate,
	1741	&ls_uart1_gate,
	1742	&ls_uart2_gate,
	1743	&ls_uart3_gate,
	1744	&ls_uart4_gate,
	1745	&ls_jamlink0co_gate,
	1746	&ls_jamlink1co_gate,
	1747	&ls_jamlink2co_gate,
	1748	&ls_jamlink3co_gate,
	1749	&ls_gpio_debounce_gate,
	1750	&sysctl_wdt0_apb_gate,
	1751	&sysctl_wdt1_apb_gate,
	1752	&sysctl_timer_apb_gate,
	1753	&sysctl_iomux_apb_gate,
	1754	&sysctl_mailbox_apb_gate,
	1755	&sysctl_hdi_gate,
	1756	&sysctl_time_stamp_gate,
	1757	&sysctl_wdt0_gate,
	1758	&sysctl_wdt1_gate,
	1759	&timer0_gate,
	1760	&timer1_gate,
	1761	&timer2_gate,
	1762	&timer3_gate,
	1763	&timer4_gate,
	1764	&timer5_gate,
	1765	&shrm_apb_gate,
	1766	&shrm_sram_gate,
	1767	&shrm_axi_gate,
	1768	&shrm_axi_slave_gate,
	1769	&shrm_nonai2d_axi_gate,
	1770	&shrm_decompress_axi_gate,
	1771	&shrm_sdma_axi_gate,
	1772	&shrm_pdma_axi_gate,
	1773	&ddrc_src_gate,
	1774	&ddrc_bypass_gate,
	1775	&ddrc_apb_gate,
	1776	&display_ahb_gate,
	1777	&display_axi_gate,
	1778	&display_gpu_gate,
	1779	&display_dpip_gate,
	1780	&display_cfg_gate,
	1781	&display_ref_gate,
	1782	&vpu_src_gate,
	1783	&vpu_axi_gate,
	1784	&vpu_ddrcp2_gate,
	1785	&vpu_cfg_gate,
	1786	&sec_apb_gate,
	1787	&sec_fix_gate,
	1788	&sec_axi_gate,
	1789	&usb_480m_gate,
	1790	&usb_100m_gate,
	1791	&dphy_dft_gate,
	1792	&spi2axi_gate,
	1793	&ai_src_gate,
	1794	&ai_axi_gate,
	1795	&camera0_gate,
	1796	&camera1_gate,
	1797	&camera2_gate,
	1798	};
	1799
	1800	#define K230_CLK_GATE_NUM ARRAY_SIZE(k230_clk_gates)
	1801
	1802	static struct k230_clk_rate *k230_clk_rates[] = {
	1803	&cpu0_src_rate,
	1804	&cpu0_axi_rate,
	1805	&cpu0_plic_rate,
	1806	&cpu0_apb_rate,
	1807	&cpu1_src_rate,
	1808	&cpu1_axi_rate,
	1809	&cpu1_plic_rate,
	1810	&hs_hclk_high_rate,
	1811	&hs_hclk_rate,
	1812	&hs_ssi0_axi_rate,
	1813	&hs_ssi1_rate,
	1814	&hs_ssi2_rate,
	1815	&hs_qspi_axi_src_rate,
	1816	&hs_sd_card_src_rate,
	1817	&hs_sd_axi_src_rate,
	1818	&hs_usb_ref_50m_rate,
	1819	&hs_sd_timer_src_rate,
	1820	&ls_apb_src_rate,
	1821	&ls_gpio_debounce_rate,
	1822	&ls_i2c0_rate,
	1823	&ls_i2c1_rate,
	1824	&ls_i2c2_rate,
	1825	&ls_i2c3_rate,
	1826	&ls_i2c4_rate,
	1827	&ls_codec_adc_rate,
	1828	&ls_codec_dac_rate,
	1829	&ls_audio_dev_rate,
	1830	&ls_pdm_rate,
	1831	&ls_adc_rate,
	1832	&ls_uart0_rate,
	1833	&ls_uart1_rate,
	1834	&ls_uart2_rate,
	1835	&ls_uart3_rate,
	1836	&ls_uart4_rate,
	1837	&ls_jamlinkco_src_rate,
	1838	&sysctl_hdi_rate,
	1839	&sysctl_time_stamp_rate,
	1840	&sysctl_temp_sensor_rate,
	1841	&sysctl_wdt0_rate,
	1842	&sysctl_wdt1_rate,
	1843	&timer0_src_rate,
	1844	&timer1_src_rate,
	1845	&timer2_src_rate,
	1846	&timer3_src_rate,
	1847	&timer4_src_rate,
	1848	&timer5_src_rate,
	1849	&shrm_apb_rate,
	1850	&ddrc_src_rate,
	1851	&ddrc_apb_rate,
	1852	&display_ahb_rate,
	1853	&display_clkext_rate,
	1854	&display_gpu_rate,
	1855	&display_dpip_rate,
	1856	&display_cfg_rate,
	1857	&vpu_src_rate,
	1858	&vpu_axi_src_rate,
	1859	&vpu_cfg_rate,
	1860	&sec_apb_rate,
	1861	&sec_fix_rate,
	1862	&sec_axi_rate,
	1863	&usb_480m_rate,
	1864	&usb_100m_rate,
	1865	&dphy_dft_rate,
	1866	&spi2axi_rate,
	1867	&ai_src_rate,
	1868	&camera0_rate,
	1869	&camera1_rate,
	1870	&camera2_rate,
	1871	};
	1872
	1873	#define K230_CLK_RATE_NUM ARRAY_SIZE(k230_clk_rates)
	1874
	1875	#define K230_CLK_NUM (K230_CLK_MUX_NUM + K230_CLK_GATE_NUM + K230_CLK_RATE_NUM + 1)
	1876
	1877	static int k230_pll_prepare(struct clk_hw *hw)
	1878	{
	1879	struct k230_pll *pll = hw_to_k230_pll(hw);
	1880	u32 reg;
	1881
	1882	/* wait for PLL lock until it reaches lock status */
	1883	return readl_poll_timeout(K230_PLLX_LOCK_ADDR(pll->reg, pll->id), reg,
	1884	reg & K230_PLL_LOCK_STATUS_MASK,
	1885	K230_PLL_LOCK_TIME_DELAY, K230_PLL_LOCK_TIMEOUT);
	1886	}
	1887
	1888	static inline bool k230_pll_hw_is_enabled(struct k230_pll *pll)
	1889	{
	1890	return readl(K230_PLLX_GATE_ADDR(pll->reg, pll->id)) & K230_PLL_GATE_ENABLE;
	1891	}
	1892
	1893	static void k230_pll_enable_hw(struct k230_pll *pll)
	1894	{
	1895	u32 reg;
	1896
	1897	if (k230_pll_hw_is_enabled(pll))
	1898	return;
	1899
	1900	reg = readl(K230_PLLX_GATE_ADDR(pll->reg, pll->id));
	1901	reg \|= K230_PLL_GATE_ENABLE \| K230_PLL_GATE_WRITE_ENABLE;
	1902	writel(reg, K230_PLLX_GATE_ADDR(pll->reg, pll->id));
	1903	}
	1904
	1905	static int k230_pll_enable(struct clk_hw *hw)
	1906	{
	1907	struct k230_pll *pll = hw_to_k230_pll(hw);
	1908
	1909	guard(spinlock)(pll->lock);
	1910
	1911	k230_pll_enable_hw(pll);
	1912
	1913	return 0;
	1914	}
	1915
	1916	static void k230_pll_disable(struct clk_hw *hw)
	1917	{
	1918	struct k230_pll *pll = hw_to_k230_pll(hw);
	1919	u32 reg;
	1920
	1921	guard(spinlock)(pll->lock);
	1922
	1923	reg = readl(K230_PLLX_GATE_ADDR(pll->reg, pll->id));
	1924	reg &= ~(K230_PLL_GATE_ENABLE);
	1925	reg \|= (K230_PLL_GATE_WRITE_ENABLE);
	1926	writel(reg, K230_PLLX_GATE_ADDR(pll->reg, pll->id));
	1927	}
	1928
	1929	static int k230_pll_is_enabled(struct clk_hw *hw)
	1930	{
	1931	return k230_pll_hw_is_enabled(hw_to_k230_pll(hw));
	1932	}
	1933
	1934	static unsigned long k230_pll_get_rate(struct clk_hw *hw, unsigned long parent_rate)
	1935	{
	1936	struct k230_pll *pll = hw_to_k230_pll(hw);
	1937	u32 reg;
	1938	u32 r, f, od;
	1939
	1940	guard(spinlock)(pll->lock);
	1941
	1942	reg = readl(K230_PLLX_BYPASS_ADDR(pll->reg, pll->id));
	1943	if (reg & K230_PLL_BYPASS_ENABLE)
	1944	return parent_rate;
	1945
	1946	reg = readl(K230_PLLX_LOCK_ADDR(pll->reg, pll->id));
	1947	if (!(reg & (K230_PLL_LOCK_STATUS_MASK)))
	1948	return 0;
	1949
	1950	reg = readl(K230_PLLX_DIV_ADDR(pll->reg, pll->id));
	1951	r = FIELD_GET(K230_PLL_R_MASK, reg) + 1;
	1952	f = FIELD_GET(K230_PLL_F_MASK, reg) + 1;
	1953	od = FIELD_GET(K230_PLL_OD_MASK, reg) + 1;
	1954
	1955	return mul_u64_u32_div(parent_rate, f, r * od);
	1956	}
	1957
	1958	static int k230_register_plls(struct platform_device pdev, spinlock_t lock,
	1959	void __iomem *reg)
	1960	{
	1961	int i, ret;
	1962	struct k230_pll *pll;
	1963
	1964	for (i = 0; i < ARRAY_SIZE(k230_plls); i++) {
	1965	const char *name;
	1966
	1967	pll = k230_plls[i];
	1968
	1969	name = pll->hw.init->name;
	1970	pll->lock = lock;
	1971	pll->reg = reg;
	1972
	1973	ret = devm_clk_hw_register(&pdev->dev, &pll->hw);
	1974	if (ret)
	1975	return ret;
	1976
	1977	ret = devm_clk_hw_register_clkdev(&pdev->dev, &pll->hw, name, NULL);
	1978	if (ret)
	1979	return ret;
	1980	}
	1981
	1982	return 0;
	1983	}
	1984
	1985	static int k230_register_pll_divs(struct platform_device *pdev)
	1986	{
	1987	struct clk_fixed_factor *pll_div;
	1988	int ret;
	1989
	1990	for (int i = 0; i < ARRAY_SIZE(k230_pll_divs); i++) {
	1991	const char *name;
	1992
	1993	pll_div = k230_pll_divs[i];
	1994
	1995	name = pll_div->hw.init->name;
	1996
	1997	ret = devm_clk_hw_register(&pdev->dev, &pll_div->hw);
	1998	if (ret)
	1999	return ret;
	2000
	2001	ret = devm_clk_hw_register_clkdev(&pdev->dev, &pll_div->hw,
	2002	name, NULL);
	2003	if (ret)
	2004	return ret;
	2005	}
	2006
	2007	return 0;
	2008	}
	2009
	2010	static unsigned long k230_clk_get_rate_mul(struct clk_hw *hw,
	2011	unsigned long parent_rate)
	2012	{
	2013	struct k230_clk_rate *clk = hw_to_k230_clk_rate(hw);
	2014	struct k230_clk_rate_self *rate_self = &clk->clk;
	2015	u32 mul, div;
	2016
	2017	guard(spinlock)(rate_self->lock);
	2018
	2019	div = rate_self->div_max;
	2020	mul = (readl(rate_self->reg + clk->mul_reg_off) >> rate_self->mul_shift)
	2021	& rate_self->mul_mask;
	2022
	2023	return mul_u64_u32_div(parent_rate, mul + 1, div);
	2024	}
	2025
	2026	static unsigned long k230_clk_get_rate_div(struct clk_hw *hw,
	2027	unsigned long parent_rate)
	2028	{
	2029	struct k230_clk_rate *clk = hw_to_k230_clk_rate(hw);
	2030	struct k230_clk_rate_self *rate_self = &clk->clk;
	2031	u32 mul, div;
	2032
	2033	guard(spinlock)(rate_self->lock);
	2034
	2035	mul = rate_self->mul_max;
	2036	div = (readl(rate_self->reg + clk->div_reg_off) >> rate_self->div_shift)
	2037	& rate_self->div_mask;
	2038
	2039	return mul_u64_u32_div(parent_rate, mul, div + 1);
	2040	}
	2041
	2042	static unsigned long k230_clk_get_rate_mul_div(struct clk_hw *hw,
	2043	unsigned long parent_rate)
	2044	{
	2045	struct k230_clk_rate *clk = hw_to_k230_clk_rate(hw);
	2046	struct k230_clk_rate_self *rate_self = &clk->clk;
	2047	u32 mul, div;
	2048
	2049	guard(spinlock)(rate_self->lock);
	2050
	2051	div = (readl(rate_self->reg + clk->div_reg_off) >> rate_self->div_shift)
	2052	& rate_self->div_mask;
	2053	mul = (readl(rate_self->reg + clk->mul_reg_off) >> rate_self->mul_shift)
	2054	& rate_self->mul_mask;
	2055
	2056	return mul_u64_u32_div(parent_rate, mul, div);
	2057	}
	2058
	2059	static int k230_clk_find_approximate_mul(u32 mul_min, u32 mul_max,
	2060	u32 div_min, u32 div_max,
	2061	unsigned long rate, unsigned long parent_rate,
	2062	u32 div, u32 mul)
	2063	{
	2064	long abs_min;
	2065	long abs_current;
	2066	long perfect_divide;
	2067
	2068	if (!rate \|\| !parent_rate \|\| !mul_min)
	2069	return -EINVAL;
	2070
	2071	perfect_divide = (long)((parent_rate * 1000) / rate);
	2072	abs_min = abs(perfect_divide -
	2073	(long)(((long)div_max * 1000) / (long)mul_min));
	2074	*mul = mul_min;
	2075
	2076	for (u32 i = mul_min + 1; i <= mul_max; i++) {
	2077	abs_current = abs(perfect_divide -
	2078	(long)(((long)div_max * 1000) / (long)i));
	2079
	2080	if (abs_min > abs_current) {
	2081	abs_min = abs_current;
	2082	*mul = i;
	2083	}
	2084	}
	2085
	2086	*div = div_max;
	2087
	2088	return 0;
	2089	}
	2090
	2091	static int k230_clk_find_approximate_div(u32 mul_min, u32 mul_max,
	2092	u32 div_min, u32 div_max,
	2093	unsigned long rate, unsigned long parent_rate,
	2094	u32 div, u32 mul)
	2095	{
	2096	long abs_min;
	2097	long abs_current;
	2098	long perfect_divide;
	2099
	2100	if (!rate \|\| !parent_rate \|\| !mul_max)
	2101	return -EINVAL;
	2102
	2103	perfect_divide = (long)((parent_rate * 1000) / rate);
	2104	abs_min = abs(perfect_divide -
	2105	(long)(((long)div_min * 1000) / (long)mul_max));
	2106	*div = div_min;
	2107
	2108	for (u32 i = div_min + 1; i <= div_max; i++) {
	2109	abs_current = abs(perfect_divide -
	2110	(long)(((long)i * 1000) / (long)mul_max));
	2111
	2112	if (abs_min > abs_current) {
	2113	abs_min = abs_current;
	2114	*div = i;
	2115	}
	2116	}
	2117
	2118	*mul = mul_max;
	2119
	2120	return 0;
	2121	}
	2122
	2123	static int k230_clk_find_approximate_mul_div(u32 mul_min, u32 mul_max,
	2124	u32 div_min, u32 div_max,
	2125	unsigned long rate,
	2126	unsigned long parent_rate,
	2127	u32 div, u32 mul)
	2128	{
	2129	unsigned long best_mul, best_div;
	2130
	2131	if (!rate \|\| !parent_rate \|\| !mul_min)
	2132	return -EINVAL;
	2133
	2134	rational_best_approximation(rate, parent_rate,
	2135	(unsigned long)mul_max, (unsigned long)div_max,
	2136	&best_mul, &best_div);
	2137
	2138	if (best_mul < mul_min)
	2139	best_mul = mul_min;
	2140
	2141	if (best_div < div_min)
	2142	best_div = div_min;
	2143
	2144	*mul = (u32)best_mul;
	2145	*div = (u32)best_div;
	2146
	2147	return 0;
	2148	}
	2149
	2150	static int k230_clk_determine_rate_mul(struct clk_hw hw, struct clk_rate_request req)
	2151	{
	2152	int ret;
	2153	struct k230_clk_rate_self *rate_self = hw_to_k230_clk_rate_self(hw);
	2154	unsigned long rate = req->rate;
	2155	unsigned long parent_rate = req->best_parent_rate;
	2156	u32 div, mul;
	2157
	2158	ret = k230_clk_find_approximate_mul(rate_self->mul_min, rate_self->mul_max,
	2159	rate_self->div_min, rate_self->div_max,
	2160	rate, parent_rate, &div, &mul);
	2161	if (ret)
	2162	return ret;
	2163
	2164	req->rate = mul_u64_u32_div(parent_rate, mul, div);
	2165
	2166	return 0;
	2167	}
	2168
	2169	static int k230_clk_determine_rate_div(struct clk_hw hw, struct clk_rate_request req)
	2170	{
	2171	int ret;
	2172	struct k230_clk_rate_self *rate_self = hw_to_k230_clk_rate_self(hw);
	2173	unsigned long rate = req->rate;
	2174	unsigned long parent_rate = req->best_parent_rate;
	2175	u32 div, mul;
	2176
	2177	ret = k230_clk_find_approximate_div(rate_self->mul_min, rate_self->mul_max,
	2178	rate_self->div_min, rate_self->div_max,
	2179	rate, parent_rate, &div, &mul);
	2180	if (ret)
	2181	return ret;
	2182
	2183	req->rate = mul_u64_u32_div(parent_rate, mul, div);
	2184
	2185	return 0;
	2186	}
	2187
	2188	static int k230_clk_determine_rate_mul_div(struct clk_hw hw, struct clk_rate_request req)
	2189	{
	2190	int ret;
	2191	struct k230_clk_rate_self *rate_self = hw_to_k230_clk_rate_self(hw);
	2192	unsigned long rate = req->rate;
	2193	unsigned long parent_rate = req->best_parent_rate;
	2194	u32 div, mul;
	2195
	2196	ret = k230_clk_find_approximate_mul_div(rate_self->mul_min, rate_self->mul_max,
	2197	rate_self->div_min, rate_self->div_max,
	2198	rate, parent_rate, &div, &mul);
	2199	if (ret)
	2200	return ret;
	2201
	2202	req->rate = mul_u64_u32_div(parent_rate, mul, div);
	2203
	2204	return 0;
	2205	}
	2206
	2207	static int k230_clk_set_rate_mul(struct clk_hw *hw, unsigned long rate,
	2208	unsigned long parent_rate)
	2209	{
	2210	int ret;
	2211	struct k230_clk_rate *clk = hw_to_k230_clk_rate(hw);
	2212	struct k230_clk_rate_self *rate_self = &clk->clk;
	2213	u32 div, mul, mul_reg;
	2214
	2215	if (rate > parent_rate)
	2216	return -EINVAL;
	2217
	2218	if (rate_self->read_only)
	2219	return 0;
	2220
	2221	ret = k230_clk_find_approximate_mul(rate_self->mul_min, rate_self->mul_max,
	2222	rate_self->div_min, rate_self->div_max,
	2223	rate, parent_rate, &div, &mul);
	2224	if (ret)
	2225	return ret;
	2226
	2227	guard(spinlock)(rate_self->lock);
	2228
	2229	mul_reg = readl(rate_self->reg + clk->mul_reg_off);
	2230	mul_reg \|= ((mul - 1) & rate_self->mul_mask) << (rate_self->mul_shift);
	2231	mul_reg \|= BIT(rate_self->write_enable_bit);
	2232	writel(mul_reg, rate_self->reg + clk->mul_reg_off);
	2233
	2234	return 0;
	2235	}
	2236
	2237	static int k230_clk_set_rate_div(struct clk_hw *hw, unsigned long rate,
	2238	unsigned long parent_rate)
	2239	{
	2240	int ret;
	2241	struct k230_clk_rate *clk = hw_to_k230_clk_rate(hw);
	2242	struct k230_clk_rate_self *rate_self = &clk->clk;
	2243	u32 div, mul, div_reg;
	2244
	2245	if (rate > parent_rate)
	2246	return -EINVAL;
	2247
	2248	if (rate_self->read_only)
	2249	return 0;
	2250
	2251	ret = k230_clk_find_approximate_div(rate_self->mul_min, rate_self->mul_max,
	2252	rate_self->div_min, rate_self->div_max,
	2253	rate, parent_rate, &div, &mul);
	2254	if (ret)
	2255	return ret;
	2256
	2257	guard(spinlock)(rate_self->lock);
	2258
	2259	div_reg = readl(rate_self->reg + clk->div_reg_off);
	2260	div_reg \|= ((div - 1) & rate_self->div_mask) << (rate_self->div_shift);
	2261	div_reg \|= BIT(rate_self->write_enable_bit);
	2262	writel(div_reg, rate_self->reg + clk->div_reg_off);
	2263
	2264	return 0;
	2265	}
	2266
	2267	static int k230_clk_set_rate_mul_div(struct clk_hw *hw, unsigned long rate,
	2268	unsigned long parent_rate)
	2269	{
	2270	int ret;
	2271	struct k230_clk_rate *clk = hw_to_k230_clk_rate(hw);
	2272	struct k230_clk_rate_self *rate_self = &clk->clk;
	2273	u32 div, mul, div_reg, mul_reg;
	2274
	2275	if (rate > parent_rate)
	2276	return -EINVAL;
	2277
	2278	if (rate_self->read_only)
	2279	return 0;
	2280
	2281	ret = k230_clk_find_approximate_mul_div(rate_self->mul_min, rate_self->mul_max,
	2282	rate_self->div_min, rate_self->div_max,
	2283	rate, parent_rate, &div, &mul);
	2284	if (ret)
	2285	return ret;
	2286
	2287	guard(spinlock)(rate_self->lock);
	2288
	2289	div_reg = readl(rate_self->reg + clk->div_reg_off);
	2290	div_reg \|= ((div - 1) & rate_self->div_mask) << (rate_self->div_shift);
	2291	div_reg \|= BIT(rate_self->write_enable_bit);
	2292	writel(div_reg, rate_self->reg + clk->div_reg_off);
	2293
	2294	mul_reg = readl(rate_self->reg + clk->mul_reg_off);
	2295	mul_reg \|= ((mul - 1) & rate_self->mul_mask) << (rate_self->mul_shift);
	2296	mul_reg \|= BIT(rate_self->write_enable_bit);
	2297	writel(mul_reg, rate_self->reg + clk->mul_reg_off);
	2298
	2299	return 0;
	2300	}
	2301
	2302	static int k230_register_clk(int id, struct clk_hw hw, struct device dev,
	2303	struct clk_hw_onecell_data *hw_data)
	2304	{
	2305	int ret;
	2306
	2307	ret = devm_clk_hw_register(dev, hw);
	2308	if (ret)
	2309	return ret;
	2310
	2311	hw_data->hws[id] = hw;
	2312
	2313	return 0;
	2314	}
	2315
	2316	static int k230_register_clks(struct platform_device *pdev,
	2317	struct clk_hw_onecell_data *hw_data,
	2318	spinlock_t lock, void __iomem reg)
	2319	{
	2320	int i, ret;
	2321	struct device *dev = &pdev->dev;
	2322	struct clk_fixed_factor *fixed_factor = &shrm_sram_div2;
	2323	struct k230_clk_mux *mux;
	2324	struct k230_clk_gate *gate;
	2325	struct k230_clk_rate *rate;
	2326
	2327	for (i = 0; i < K230_CLK_MUX_NUM; i++) {
	2328	mux = k230_clk_muxs[i];
	2329	mux->clk.lock = lock;
	2330	mux->clk.reg = reg + mux->reg_off;
	2331
	2332	ret = k230_register_clk(mux->id, &mux->clk.hw, dev, hw_data);
	2333	if (ret)
	2334	return ret;
	2335	}
	2336
	2337	for (i = 0; i < K230_CLK_GATE_NUM; i++) {
	2338	gate = k230_clk_gates[i];
	2339	gate->clk.lock = lock;
	2340	gate->clk.reg = reg + gate->reg_off;
	2341
	2342	ret = k230_register_clk(gate->id, &gate->clk.hw, dev, hw_data);
	2343	if (ret)
	2344	return ret;
	2345	}
	2346
	2347	for (i = 0; i < K230_CLK_RATE_NUM; i++) {
	2348	rate = k230_clk_rates[i];
	2349	rate->clk.lock = lock;
	2350	rate->clk.reg = reg;
	2351
	2352	ret = k230_register_clk(rate->id, &rate->clk.hw, dev, hw_data);
	2353	if (ret)
	2354	return ret;
	2355	}
	2356
	2357	ret = k230_register_clk(K230_SHRM_SRAM_DIV2, &fixed_factor->hw, dev, hw_data);
	2358	if (ret)
	2359	return ret;
	2360
	2361	return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, hw_data);
	2362	}
	2363
	2364	static int k230_clk_init_plls(struct platform_device *pdev)
	2365	{
	2366	int ret;
	2367	void __iomem *reg;
	2368	/* used for all the plls */
	2369	spinlock_t *lock;
	2370
	2371	lock = devm_kzalloc(&pdev->dev, sizeof(*lock), GFP_KERNEL);
	2372	if (!lock)
	2373	return -ENOMEM;
	2374
	2375	spin_lock_init(lock);
	2376
	2377	reg = devm_platform_ioremap_resource(pdev, 0);
	2378	if (IS_ERR(reg))
	2379	return PTR_ERR(reg);
	2380
	2381	ret = k230_register_plls(pdev, lock, reg);
	2382	if (ret)
	2383	return ret;
	2384
	2385	ret = k230_register_pll_divs(pdev);
	2386	if (ret)
	2387	return ret;
	2388
	2389	return 0;
	2390	}
	2391
	2392	static int k230_clk_init_clks(struct platform_device *pdev,
	2393	struct clk_hw_onecell_data *hw_data)
	2394	{
	2395	int ret;
	2396	void __iomem *reg;
	2397	/* used for all the clocks */
	2398	spinlock_t *lock;
	2399
	2400	lock = devm_kzalloc(&pdev->dev, sizeof(*lock), GFP_KERNEL);
	2401	if (!lock)
	2402	return -ENOMEM;
	2403
	2404	spin_lock_init(lock);
	2405
	2406	hw_data->num = K230_CLK_NUM;
	2407
	2408	reg = devm_platform_ioremap_resource(pdev, 1);
	2409	if (IS_ERR(reg))
	2410	return PTR_ERR(reg);
	2411
	2412	ret = k230_register_clks(pdev, hw_data, lock, reg);
	2413	if (ret)
	2414	return ret;
	2415
	2416	return 0;
	2417	}
	2418
	2419	static int k230_clk_probe(struct platform_device *pdev)
	2420	{
	2421	int ret;
	2422	struct clk_hw_onecell_data *hw_data;
	2423
	2424	hw_data = devm_kzalloc(&pdev->dev, struct_size(hw_data, hws, K230_CLK_NUM),
	2425	GFP_KERNEL);
	2426	if (!hw_data)
	2427	return -ENOMEM;
	2428
	2429	ret = k230_clk_init_plls(pdev);
	2430	if (ret)
	2431	return dev_err_probe(&pdev->dev, ret, "init plls failed\n");
	2432
	2433	ret = k230_clk_init_clks(pdev, hw_data);
	2434	if (ret)
	2435	return dev_err_probe(&pdev->dev, ret, "init clks failed\n");
	2436
	2437	return 0;
	2438	}
	2439
	2440	static const struct of_device_id k230_clk_ids[] = {
	2441	{ .compatible = "canaan,k230-clk" },
	2442	{ /* Sentinel */ }
	2443	};
	2444
	2445	static struct platform_driver k230_clk_driver = {
	2446	.driver = {
	2447	.name = "k230_clock_controller",
	2448	.of_match_table = k230_clk_ids,
	2449	},
	2450	.probe = k230_clk_probe,
	2451	};
	2452	builtin_platform_driver(k230_clk_driver);

drivers/clk/renesas/clk-r8a73a4.c+2−0

 	{ "b",	CPG_FRQCRA,  8 },
 	{ "m1", CPG_FRQCRA,  4 },
 	{ "m2", CPG_FRQCRA,  0 },
+	{ "ztr", CPG_FRQCRB, 20 },
+	{ "zt", CPG_FRQCRB, 16 },
 	{ "zx", CPG_FRQCRB, 12 },
 	{ "zs", CPG_FRQCRB,  8 },
 	{ "hp", CPG_FRQCRB,  4 },

drivers/clk/renesas/clk-r8a7740.c+2−0

 	{ "zg", CPG_FRQCRA, 16 },
 	{ "b", CPG_FRQCRA,  8 },
 	{ "m1", CPG_FRQCRA,  4 },
+	{ "ztr", CPG_FRQCRB,  20 },
+	{ "zt", CPG_FRQCRB,  16 },
 	{ "hp", CPG_FRQCRB,  4 },
 	{ "hpp", CPG_FRQCRC, 20 },
 	{ "usbp", CPG_FRQCRC, 16 },

drivers/clk/renesas/r8a779g0-cpg-mssr.c+1−0

@@ -245,6 +245,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { · 244 unmodified lines
245	DEF_MOD("fcpvx0", 1100, R8A779G0_CLK_S0D1_VIO),	245	DEF_MOD("fcpvx0", 1100, R8A779G0_CLK_S0D1_VIO),
246	DEF_MOD("fcpvx1", 1101, R8A779G0_CLK_S0D1_VIO),	246	DEF_MOD("fcpvx1", 1101, R8A779G0_CLK_S0D1_VIO),
247	DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC),	247	DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC),
		248	DEF_MOD("dsc", 2819, R8A779G0_CLK_VIOBUSD2),
248	DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),	249	DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
249	DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),	250	DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
250	};	251	};

drivers/clk/renesas/r9a07g043-cpg.c+1−1

@@ -103,7 +103,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { · 102 unmodified lines
103	/* Internal Core Clocks */	103	/* Internal Core Clocks */
104	DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1),	104	DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1),
105	DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),	105	DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
106	DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),	106	DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, CPG_SAM_PLL_CONF(0)),
107	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),	107	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
108	DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),	108	DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
109	DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),	109	DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),

drivers/clk/renesas/r9a07g044-cpg.c+1−1

@@ -159,7 +159,7 @@ static const struct { · 158 unmodified lines
159	/* Internal Core Clocks */	159	/* Internal Core Clocks */
160	DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),	160	DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
161	DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),	161	DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
162	DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),	162	DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, CPG_SAM_PLL_CONF(0)),
163	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),	163	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
164	DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3),	164	DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3),
165	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),	165	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),

drivers/clk/renesas/r9a08g045-cpg.c+1−12

 #include <linux/device.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/pm_domain.h>
 #include <dt-bindings/clock/r9a08g045-cpg.h>
 #define G3S_SEL_SDHI1		SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 4, 2)
 #define G3S_SEL_SDHI2		SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2)
-/* PLL 1/4/6 configuration registers macro. */
-#define G3S_PLL146_CONF(clk1, clk2, setting)	((clk1) << 22 | (clk2) << 12 | (setting))
-#define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \
-	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \
-		 .parent_names = (_parent_names), \
-		 .num_parents = ARRAY_SIZE((_parent_names)), \
-		 .mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \
-		 .flag = (_clk_flags))
 enum clk_ids {
 	/* Core Clock Outputs exported to DT */
 	LAST_DT_CORE_CLK = R9A08G045_SWD,
 	/* Internal Core Clocks */
 	DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
-	DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8, 0x100),
+	DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, CPG_PLL_CONF(0, 0x100),
 		    1100000000UL),
 	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
 	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),

drivers/clk/renesas/r9a08g046-cpg.c+355−0

@@ -17,17 +17,69 @@ · 16 unmodified lines
17	/* RZ/G3L Specific registers. */	17	/* RZ/G3L Specific registers. */
18	#define G3L_CPG_PL2_DDIV (0x204)	18	#define G3L_CPG_PL2_DDIV (0x204)
19	#define G3L_CPG_PL3_DDIV (0x208)	19	#define G3L_CPG_PL3_DDIV (0x208)
		20	#define G3L_CPG_CA55CORE_DDIV (0x234)
		21	#define G3L_CPG_RSCI_DDIV (0x238)
		22	#define G3L_CPG_RSPI_DDIV (0x23c)
20	#define G3L_CLKDIVSTATUS (0x280)	23	#define G3L_CLKDIVSTATUS (0x280)
		24	#define G3L_CPG_ETH_SSEL (0x410)
		25	#define G3L_CPG_RSCI_SSEL (0x414)
		26	#define G3L_CPG_RSPI_SSEL (0x418)
		27	#define G3L_CPG_ETH_SDIV (0x434)
21		28
22	/* RZ/G3L Specific division configuration. */	29	/* RZ/G3L Specific division configuration. */
23	#define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2)	30	#define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2)
24	#define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2)	31	#define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2)
25	#define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2)	32	#define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2)
		33	#define G3L_DIV_CA55_CORE0 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 0, 3)
		34	#define G3L_DIV_CA55_CORE1 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 4, 3)
		35	#define G3L_DIV_CA55_CORE2 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 8, 3)
		36	#define G3L_DIV_CA55_CORE3 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 12, 3)
		37	#define G3L_DIV_RSCI0 DDIV_PACK(G3L_CPG_RSCI_DDIV, 0, 2)
		38	#define G3L_DIV_RSCI1 DDIV_PACK(G3L_CPG_RSCI_DDIV, 2, 2)
		39	#define G3L_DIV_RSCI2 DDIV_PACK(G3L_CPG_RSCI_DDIV, 4, 2)
		40	#define G3L_DIV_RSCI3 DDIV_PACK(G3L_CPG_RSCI_DDIV, 6, 2)
		41	#define G3L_DIV_RSPI0 DDIV_PACK(G3L_CPG_RSPI_DDIV, 0, 2)
		42	#define G3L_DIV_RSPI1 DDIV_PACK(G3L_CPG_RSPI_DDIV, 2, 2)
		43	#define G3L_DIV_RSPI2 DDIV_PACK(G3L_CPG_RSPI_DDIV, 4, 2)
		44	#define G3L_SDIV_ETH_A DDIV_PACK(G3L_CPG_ETH_SDIV, 0, 2)
		45	#define G3L_SDIV_ETH_B DDIV_PACK(G3L_CPG_ETH_SDIV, 4, 1)
		46	#define G3L_SDIV_ETH_C DDIV_PACK(G3L_CPG_ETH_SDIV, 8, 2)
		47	#define G3L_SDIV_ETH_D DDIV_PACK(G3L_CPG_ETH_SDIV, 12, 1)
26		48
27	/* RZ/G3L Clock status configuration. */	49	/* RZ/G3L Clock status configuration. */
28	#define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1)	50	#define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1)
29	#define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1)	51	#define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1)
30	#define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1)	52	#define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1)
		53	#define G3L_DIV_CA55_CORE0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 12, 1)
		54	#define G3L_DIV_CA55_CORE1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 13, 1)
		55	#define G3L_DIV_CA55_CORE2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 14, 1)
		56	#define G3L_DIV_CA55_CORE3_STS DDIV_PACK(G3L_CLKDIVSTATUS, 15, 1)
		57	#define G3L_DIV_RSCI0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 16, 1)
		58	#define G3L_DIV_RSCI1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 17, 1)
		59	#define G3L_DIV_RSCI2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 18, 1)
		60	#define G3L_DIV_RSCI3_STS DDIV_PACK(G3L_CLKDIVSTATUS, 19, 1)
		61	#define G3L_DIV_RSPI0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 20, 1)
		62	#define G3L_DIV_RSPI1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 21, 1)
		63	#define G3L_DIV_RSPI2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 22, 1)
		64
		65	/* RZ/G3L Specific clocks select. */
		66	#define G3L_SEL_ETH0_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 0, 1)
		67	#define G3L_SEL_ETH0_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 1, 1)
		68	#define G3L_SEL_ETH0_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 2, 1)
		69	#define G3L_SEL_ETH0_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 3, 1)
		70	#define G3L_SEL_ETH0_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 4, 1)
		71	#define G3L_SEL_ETH1_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 8, 1)
		72	#define G3L_SEL_ETH1_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 9, 1)
		73	#define G3L_SEL_ETH1_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 10, 1)
		74	#define G3L_SEL_ETH1_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 11, 1)
		75	#define G3L_SEL_ETH1_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 12, 1)
		76	#define G3L_SEL_RSCI0 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 0, 2)
		77	#define G3L_SEL_RSCI1 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 2, 2)
		78	#define G3L_SEL_RSCI2 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 4, 2)
		79	#define G3L_SEL_RSCI3 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 6, 2)
		80	#define G3L_SEL_RSPI0 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 0, 2)
		81	#define G3L_SEL_RSPI1 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 2, 2)
		82	#define G3L_SEL_RSPI2 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 4, 2)
31		83
32	enum clk_ids {	84	enum clk_ids {
33	/* Core Clock Outputs exported to DT */	85	/* Core Clock Outputs exported to DT */
@@ -41,16 +93,72 @@ enum clk_ids { · 7 unmodified lines
41	CLK_ETH1_RXC_RX_CLK_IN,	93	CLK_ETH1_RXC_RX_CLK_IN,
42		94
43	/* Internal Core Clocks */	95	/* Internal Core Clocks */
		96	CLK_PLL1,
44	CLK_PLL2,	97	CLK_PLL2,
45	CLK_PLL2_DIV2,	98	CLK_PLL2_DIV2,
		99	CLK_PLL2_DIV2_4,
		100	CLK_PLL2_DIV5,
		101	CLK_PLL2_DIV6,
		102	CLK_PLL2_DIV7,
46	CLK_PLL3,	103	CLK_PLL3,
47	CLK_PLL3_DIV2,	104	CLK_PLL3_DIV2,
		105	CLK_PLL6,
		106	CLK_PLL6_DIV10,
		107	CLK_SEL_ETH0_TX,
		108	CLK_SEL_ETH0_RX,
		109	CLK_SEL_ETH0_RM,
		110	CLK_SEL_ETH1_TX,
		111	CLK_SEL_ETH1_RX,
		112	CLK_SEL_ETH1_RM,
		113	CLK_SEL_RSCI0,
		114	CLK_SEL_RSCI1,
		115	CLK_SEL_RSCI2,
		116	CLK_SEL_RSCI3,
		117	CLK_SEL_RSPI0,
		118	CLK_SEL_RSPI1,
		119	CLK_SEL_RSPI2,
		120	CLK_ETH0_TR,
		121	CLK_ETH0_RM,
		122	CLK_ETH1_TR,
		123	CLK_ETH1_RM,
48		124
49	/* Module Clocks */	125	/* Module Clocks */
50	MOD_CLK_BASE,	126	MOD_CLK_BASE,
51	};	127	};
52		128
53	/* Divider tables */	129	/* Divider tables */
		130	static const struct clk_div_table dtable_1_8[] = {
		131	{ 0, 1 },
		132	{ 1, 2 },
		133	{ 2, 4 },
		134	{ 3, 8 },
		135	{ 0, 0 },
		136	};
		137
		138	static const struct clk_div_table dtable_1_32[] = {
		139	{ 0, 1 },
		140	{ 1, 2 },
		141	{ 2, 4 },
		142	{ 3, 8 },
		143	{ 4, 16 },
		144	{ 5, 32 },
		145	{ 0, 0 },
		146	};
		147
		148	static const struct clk_div_table dtable_2_20[] = {
		149	{ 0, 2 },
		150	{ 1, 20 },
		151	{ 0, 0 },
		152	};
		153
		154	static const struct clk_div_table dtable_2_16[] = {
		155	{ 0, 2 },
		156	{ 1, 4 },
		157	{ 2, 8 },
		158	{ 3, 16 },
		159	{ 0, 0 },
		160	};
		161
54	static const struct clk_div_table dtable_4_128[] = {	162	static const struct clk_div_table dtable_4_128[] = {
55	{ 0, 4 },	163	{ 0, 4 },
56	{ 1, 8 },	164	{ 1, 8 },
@@ -59,6 +167,13 @@ static const struct clk_div_table dtable_4_128[] = { · 2 unmodified lines
59	{ 0, 0 },	167	{ 0, 0 },
60	};	168	};
61		169
		170	static const struct clk_div_table dtable_4_200[] = {
		171	{ 0, 4 },
		172	{ 1, 20 },
		173	{ 2, 200 },
		174	{ 0, 0 },
		175	};
		176
62	static const struct clk_div_table dtable_8_256[] = {	177	static const struct clk_div_table dtable_8_256[] = {
63	{ 0, 8 },	178	{ 0, 8 },
64	{ 1, 16 },	179	{ 1, 16 },
@@ -67,6 +182,19 @@ static const struct clk_div_table dtable_8_256[] = { · 2 unmodified lines
67	{ 0, 0 },	182	{ 0, 0 },
68	};	183	};
69		184
		185	/* Mux clock names tables. */
		186	static const char * const sel_eth0_tx[] = { ".div_eth0_tr", "eth0_txc_tx_clk" };
		187	static const char * const sel_eth0_rx[] = { ".div_eth0_tr", "eth0_rxc_rx_clk" };
		188	static const char * const sel_eth0_rm[] = { ".pll6_div10", "eth0_rxc_rx_clk" };
		189	static const char * const sel_eth1_tx[] = { ".div_eth1_tr", "eth1_txc_tx_clk" };
		190	static const char * const sel_eth1_rx[] = { ".div_eth1_tr", "eth1_rxc_rx_clk" };
		191	static const char * const sel_eth1_rm[] = { ".pll6_div10", "eth1_rxc_rx_clk" };
		192	static const char * const sel_rsci_rspi[] = { ".pll2_div5", ".pll2_div6", ".pll2_div7", ".pll2_div2_4" };
		193	static const char * const sel_eth0_clk_tx_i[] = { ".sel_eth0_tx", ".div_eth0_rm" };
		194	static const char * const sel_eth0_clk_rx_i[] = { ".sel_eth0_rx", ".div_eth0_rm" };
		195	static const char * const sel_eth1_clk_tx_i[] = { ".sel_eth1_tx", ".div_eth1_rm" };
		196	static const char * const sel_eth1_clk_rx_i[] = { ".sel_eth1_rx", ".div_eth1_rm" };
		197
70	static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {	198	static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
71	/* External Clock Inputs */	199	/* External Clock Inputs */
72	DEF_INPUT("extal", CLK_EXTAL),	200	DEF_INPUT("extal", CLK_EXTAL),
@@ -76,18 +204,82 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = { · 3 unmodified lines
76	DEF_INPUT("eth1_rxc_rx_clk", CLK_ETH1_RXC_RX_CLK_IN),	204	DEF_INPUT("eth1_rxc_rx_clk", CLK_ETH1_RXC_RX_CLK_IN),
77		205
78	/* Internal Core Clocks */	206	/* Internal Core Clocks */
		207	DEF_G3L_PLL(".pll1", CLK_PLL1, CLK_EXTAL, CPG_PLL_CONF(0, 0x100),
		208	1200000000UL),
79	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),	209	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
80	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),	210	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
		211	DEF_G3L_PLL(".pll6", CLK_PLL6, CLK_EXTAL, CPG_PLL_CONF(0x50, 0),
		212	500000000UL),
81	DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),	213	DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
		214	DEF_FIXED(".pll2_div2_4", CLK_PLL2_DIV2_4, CLK_PLL2_DIV2, 1, 4),
		215	DEF_FIXED(".pll2_div5", CLK_PLL2_DIV5, CLK_PLL2, 1, 5),
		216	DEF_FIXED(".pll2_div6", CLK_PLL2_DIV6, CLK_PLL2, 1, 6),
		217	DEF_FIXED(".pll2_div7", CLK_PLL2_DIV7, CLK_PLL2, 1, 7),
82	DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),	218	DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
		219	DEF_FIXED(".pll6_div10", CLK_PLL6_DIV10, CLK_PLL6, 1, 10),
		220	DEF_MUX(".sel_rsci0", CLK_SEL_RSCI0, G3L_SEL_RSCI0, sel_rsci_rspi),
		221	DEF_MUX(".sel_rsci1", CLK_SEL_RSCI1, G3L_SEL_RSCI1, sel_rsci_rspi),
		222	DEF_MUX(".sel_rsci2", CLK_SEL_RSCI2, G3L_SEL_RSCI2, sel_rsci_rspi),
		223	DEF_MUX(".sel_rsci3", CLK_SEL_RSCI3, G3L_SEL_RSCI3, sel_rsci_rspi),
		224	DEF_MUX(".sel_rspi0", CLK_SEL_RSPI0, G3L_SEL_RSPI0, sel_rsci_rspi),
		225	DEF_MUX(".sel_rspi1", CLK_SEL_RSPI1, G3L_SEL_RSPI1, sel_rsci_rspi),
		226	DEF_MUX(".sel_rspi2", CLK_SEL_RSPI2, G3L_SEL_RSPI2, sel_rsci_rspi),
		227	DEF_MUX(".sel_eth0_tx", CLK_SEL_ETH0_TX, G3L_SEL_ETH0_TX, sel_eth0_tx),
		228	DEF_MUX(".sel_eth0_rx", CLK_SEL_ETH0_RX, G3L_SEL_ETH0_RX, sel_eth0_rx),
		229	DEF_MUX(".sel_eth0_rm", CLK_SEL_ETH0_RM, G3L_SEL_ETH0_RM, sel_eth0_rm),
		230	DEF_MUX(".sel_eth1_tx", CLK_SEL_ETH1_TX, G3L_SEL_ETH1_TX, sel_eth1_tx),
		231	DEF_MUX(".sel_eth1_rx", CLK_SEL_ETH1_RX, G3L_SEL_ETH1_RX, sel_eth1_rx),
		232	DEF_MUX(".sel_eth1_rm", CLK_SEL_ETH1_RM, G3L_SEL_ETH1_RM, sel_eth1_rm),
		233	DEF_DIV(".div_eth0_tr", CLK_ETH0_TR, CLK_PLL6, G3L_SDIV_ETH_A, dtable_4_200),
		234	DEF_DIV(".div_eth1_tr", CLK_ETH1_TR, CLK_PLL6, G3L_SDIV_ETH_C, dtable_4_200),
		235	DEF_DIV(".div_eth0_rm", CLK_ETH0_RM, CLK_SEL_ETH0_RM, G3L_SDIV_ETH_B, dtable_2_20),
		236	DEF_DIV(".div_eth1_rm", CLK_ETH1_RM, CLK_SEL_ETH1_RM, G3L_SDIV_ETH_D, dtable_2_20),
83		237
84	/* Core output clk */	238	/* Core output clk */
		239	DEF_G3S_DIV("IC0", R9A08G046_CLK_IC0, CLK_PLL1, G3L_DIV_CA55_CORE0, G3L_DIV_CA55_CORE0_STS,
		240	dtable_1_32, 0, 0, 0, NULL),
		241	DEF_G3S_DIV("IC1", R9A08G046_CLK_IC1, CLK_PLL1, G3L_DIV_CA55_CORE1, G3L_DIV_CA55_CORE1_STS,
		242	dtable_1_32, 0, 0, 0, NULL),
		243	DEF_G3S_DIV("IC2", R9A08G046_CLK_IC2, CLK_PLL1, G3L_DIV_CA55_CORE2, G3L_DIV_CA55_CORE2_STS,
		244	dtable_1_32, 0, 0, 0, NULL),
		245	DEF_G3S_DIV("IC3", R9A08G046_CLK_IC3, CLK_PLL1, G3L_DIV_CA55_CORE3, G3L_DIV_CA55_CORE3_STS,
		246	dtable_1_32, 0, 0, 0, NULL),
85	DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL2B_STS,	247	DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL2B_STS,
86	dtable_8_256, 0, 0, 0, NULL),	248	dtable_8_256, 0, 0, 0, NULL),
87	DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL3A_STS,	249	DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL3A_STS,
88	dtable_4_128, 0, 0, 0, NULL),	250	dtable_4_128, 0, 0, 0, NULL),
89	DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL2A_STS,	251	DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL2A_STS,
90	dtable_4_128, 0, 0, 0, NULL),	252	dtable_4_128, 0, 0, 0, NULL),
		253	DEF_G3S_DIV("P13", R9A08G046_CLK_P13, CLK_SEL_RSCI0, G3L_DIV_RSCI0, G3L_DIV_RSCI0_STS,
		254	dtable_2_16, 0, 100000000UL, 0, NULL),
		255	DEF_G3S_DIV("P14", R9A08G046_CLK_P14, CLK_SEL_RSCI1, G3L_DIV_RSCI1, G3L_DIV_RSCI1_STS,
		256	dtable_2_16, 0, 100000000UL, 0, NULL),
		257	DEF_G3S_DIV("P15", R9A08G046_CLK_P15, CLK_SEL_RSCI2, G3L_DIV_RSCI2, G3L_DIV_RSCI2_STS,
		258	dtable_2_16, 0, 100000000UL, 0, NULL),
		259	DEF_G3S_DIV("P16", R9A08G046_CLK_P16, CLK_SEL_RSCI3, G3L_DIV_RSCI3, G3L_DIV_RSCI3_STS,
		260	dtable_2_16, 0, 100000000UL, 0, NULL),
		261	DEF_G3S_DIV("P17", R9A08G046_CLK_P17, CLK_SEL_RSPI0, G3L_DIV_RSPI0, G3L_DIV_RSPI0_STS,
		262	dtable_1_8, 0, 200000000UL, 0, NULL),
		263	DEF_G3S_DIV("P18", R9A08G046_CLK_P18, CLK_SEL_RSPI1, G3L_DIV_RSPI1, G3L_DIV_RSPI1_STS,
		264	dtable_1_8, 0, 200000000UL, 0, NULL),
		265	DEF_G3S_DIV("P19", R9A08G046_CLK_P19, CLK_SEL_RSPI2, G3L_DIV_RSPI2, G3L_DIV_RSPI2_STS,
		266	dtable_1_8, 0, 200000000UL, 0, NULL),
		267	DEF_FIXED("HP", R9A08G046_CLK_HP, CLK_PLL6_DIV10, 1, 1),
		268	DEF_MUX_FLAGS("ETHTX01", R9A08G046_CLK_ETHTX01, G3L_SEL_ETH0_CLK_TX_I, sel_eth0_clk_tx_i,
		269	CLK_SET_RATE_PARENT),
		270	DEF_MUX_FLAGS("ETHRX01", R9A08G046_CLK_ETHRX01, G3L_SEL_ETH0_CLK_RX_I, sel_eth0_clk_rx_i,
		271	CLK_SET_RATE_PARENT),
		272	DEF_MUX_FLAGS("ETHTX11", R9A08G046_CLK_ETHTX11, G3L_SEL_ETH1_CLK_TX_I, sel_eth1_clk_tx_i,
		273	CLK_SET_RATE_PARENT),
		274	DEF_MUX_FLAGS("ETHRX11", R9A08G046_CLK_ETHRX11, G3L_SEL_ETH1_CLK_RX_I, sel_eth1_clk_rx_i,
		275	CLK_SET_RATE_PARENT),
		276	DEF_FIXED("ETHRM0", R9A08G046_CLK_ETHRM0, CLK_SEL_ETH0_RM, 1, 1),
		277	DEF_FIXED("ETHTX02", R9A08G046_CLK_ETHTX02, CLK_SEL_ETH0_TX, 1, 1),
		278	DEF_FIXED("ETHRX02", R9A08G046_CLK_ETHRX02, CLK_SEL_ETH0_RX, 1, 1),
		279	DEF_FIXED("ETHRM1", R9A08G046_CLK_ETHRM1, CLK_SEL_ETH1_RM, 1, 1),
		280	DEF_FIXED("ETHTX12", R9A08G046_CLK_ETHTX12, CLK_SEL_ETH1_TX, 1, 1),
		281	DEF_FIXED("ETHRX12", R9A08G046_CLK_ETHRX12, CLK_SEL_ETH1_RX, 1, 1),
		282	DEF_FIXED("OSCCLK", R9A08G046_OSCCLK, CLK_EXTAL, 1, 1),
91	};	283	};
92		284
93	static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {	285	static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
@@ -101,8 +293,116 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = { · 7 unmodified lines
101	MSTOP(BUS_REG1, BIT(2))),	293	MSTOP(BUS_REG1, BIT(2))),
102	DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1,	294	DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1,
103	MSTOP(BUS_REG1, BIT(3))),	295	MSTOP(BUS_REG1, BIT(3))),
		296	DEF_MOD("wdt0_pclk", R9A08G046_WDT0_PCLK, R9A08G046_CLK_P0, 0x548, 0,
		297	MSTOP(BUS_REG0, BIT(0))),
		298	DEF_MOD("wdt0_clk", R9A08G046_WDT0_CLK, R9A08G046_OSCCLK, 0x548, 1,
		299	MSTOP(BUS_REG0, BIT(0))),
		300	DEF_MOD("ssi0_pclk2", R9A08G046_SSI0_PCLK2, R9A08G046_CLK_P0, 0x570, 0,
		301	MSTOP(BUS_MCPU1, BIT(10))),
		302	DEF_MOD("ssi0_pclk_sfr", R9A08G046_SSI0_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 1,
		303	MSTOP(BUS_MCPU1, BIT(10))),
		304	DEF_MOD("ssi1_pclk2", R9A08G046_SSI1_PCLK2, R9A08G046_CLK_P0, 0x570, 2,
		305	MSTOP(BUS_MCPU1, BIT(11))),
		306	DEF_MOD("ssi1_pclk_sfr", R9A08G046_SSI1_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 3,
		307	MSTOP(BUS_MCPU1, BIT(11))),
		308	DEF_MOD("ssi2_pclk2", R9A08G046_SSI2_PCLK2, R9A08G046_CLK_P0, 0x570, 4,
		309	MSTOP(BUS_MCPU1, BIT(12))),
		310	DEF_MOD("ssi2_pclk_sfr", R9A08G046_SSI2_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 5,
		311	MSTOP(BUS_MCPU1, BIT(12))),
		312	DEF_MOD("ssi3_pclk2", R9A08G046_SSI3_PCLK2, R9A08G046_CLK_P0, 0x570, 6,
		313	MSTOP(BUS_MCPU1, BIT(13))),
		314	DEF_MOD("ssi3_pclk_sfr", R9A08G046_SSI3_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 7,
		315	MSTOP(BUS_MCPU1, BIT(13))),
		316	DEF_MOD("eth0_clk_axi", R9A08G046_ETH0_CLK_AXI, R9A08G046_CLK_P1, 0x57c, 0,
		317	MSTOP(BUS_PERI_COM, BIT(2))),
		318	DEF_MOD("eth1_clk_axi", R9A08G046_ETH1_CLK_AXI, R9A08G046_CLK_P1, 0x57c, 1,
		319	MSTOP(BUS_PERI_COM, BIT(3))),
		320	DEF_MOD("eth0_clk_chi", R9A08G046_ETH0_CLK_CHI, R9A08G046_CLK_P1, 0x57c, 2,
		321	MSTOP(BUS_PERI_COM, BIT(2))),
		322	DEF_MOD("eth1_clk_chi", R9A08G046_ETH1_CLK_CHI, R9A08G046_CLK_P1, 0x57c, 3,
		323	MSTOP(BUS_PERI_COM, BIT(3))),
		324	DEF_COUPLED("eth0_tx_i", R9A08G046_ETH0_CLK_TX_I, R9A08G046_CLK_ETHTX01, 0x57c, 4,
		325	MSTOP(BUS_PERI_COM, BIT(2))),
		326	DEF_COUPLED("eth0_tx_180_i", R9A08G046_ETH0_CLK_TX_180_I, R9A08G046_CLK_ETHTX02, 0x57c, 4,
		327	MSTOP(BUS_PERI_COM, BIT(2))),
		328	DEF_COUPLED("eth1_tx_i", R9A08G046_ETH1_CLK_TX_I, R9A08G046_CLK_ETHTX11, 0x57c, 5,
		329	MSTOP(BUS_PERI_COM, BIT(3))),
		330	DEF_COUPLED("eth1_tx_180_i", R9A08G046_ETH1_CLK_TX_180_I, R9A08G046_CLK_ETHTX12, 0x57c, 5,
		331	MSTOP(BUS_PERI_COM, BIT(3))),
		332	DEF_COUPLED("eth0_rx_i", R9A08G046_ETH0_CLK_RX_I, R9A08G046_CLK_ETHRX01, 0x57c, 6,
		333	MSTOP(BUS_PERI_COM, BIT(2))),
		334	DEF_COUPLED("eth0_rx_180_i", R9A08G046_ETH0_CLK_RX_180_I, R9A08G046_CLK_ETHRX02, 0x57c, 6,
		335	MSTOP(BUS_PERI_COM, BIT(2))),
		336	DEF_COUPLED("eth1_rx_i", R9A08G046_ETH1_CLK_RX_I, R9A08G046_CLK_ETHRX11, 0x57c, 7,
		337	MSTOP(BUS_PERI_COM, BIT(3))),
		338	DEF_COUPLED("eth1_rx_180_i", R9A08G046_ETH1_CLK_RX_180_I, R9A08G046_CLK_ETHRX12, 0x57c, 7,
		339	MSTOP(BUS_PERI_COM, BIT(3))),
		340	DEF_MOD("eth0_ptp_ref_i", R9A08G046_ETH0_CLK_PTP_REF_I, R9A08G046_CLK_HP, 0x57c, 8,
		341	MSTOP(BUS_PERI_COM, BIT(2))),
		342	DEF_MOD("eth1_ptp_ref_i", R9A08G046_ETH1_CLK_PTP_REF_I, R9A08G046_CLK_HP, 0x57c, 9,
		343	MSTOP(BUS_PERI_COM, BIT(3))),
		344	DEF_MOD("eth0_rmii_i", R9A08G046_ETH0_CLK_RMII_I, R9A08G046_CLK_ETHRM0, 0x57c, 10,
		345	MSTOP(BUS_PERI_COM, BIT(2))),
		346	DEF_MOD("eth1_rmii_i", R9A08G046_ETH1_CLK_RMII_I, R9A08G046_CLK_ETHRM1, 0x57c, 11,
		347	MSTOP(BUS_PERI_COM, BIT(3))),
		348	DEF_COUPLED("eth0_tx_i_rmii", R9A08G046_ETH0_CLK_TX_I_RMII, R9A08G046_CLK_ETHTX01, 0x57c, 12,
		349	MSTOP(BUS_PERI_COM, BIT(2))),
		350	DEF_COUPLED("eth0_rx_i_rmii", R9A08G046_ETH0_CLK_RX_I_RMII, R9A08G046_CLK_ETHRX01, 0x57c, 12,
		351	MSTOP(BUS_PERI_COM, BIT(2))),
		352	DEF_COUPLED("eth1_tx_i_rmii", R9A08G046_ETH1_CLK_TX_I_RMII, R9A08G046_CLK_ETHTX11, 0x57c, 13,
		353	MSTOP(BUS_PERI_COM, BIT(3))),
		354	DEF_COUPLED("eth1_rx_i_rmii", R9A08G046_ETH1_CLK_RX_I_RMII, R9A08G046_CLK_ETHRX11, 0x57c, 13,
		355	MSTOP(BUS_PERI_COM, BIT(3))),
		356	DEF_MOD("i2c0_pclk", R9A08G046_I2C0_PCLK, R9A08G046_CLK_P0, 0x580, 0,
		357	MSTOP(BUS_MCPU2, BIT(10))),
		358	DEF_MOD("i2c1_pclk", R9A08G046_I2C1_PCLK, R9A08G046_CLK_P0, 0x580, 1,
		359	MSTOP(BUS_MCPU2, BIT(11))),
		360	DEF_MOD("i2c2_pclk", R9A08G046_I2C2_PCLK, R9A08G046_CLK_P0, 0x580, 2,
		361	MSTOP(BUS_MCPU2, BIT(12))),
		362	DEF_MOD("i2c3_pclk", R9A08G046_I2C3_PCLK, R9A08G046_CLK_P0, 0x580, 3,
		363	MSTOP(BUS_MCPU2, BIT(13))),
104	DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584, 0,	364	DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584, 0,
105	MSTOP(BUS_MCPU2, BIT(1))),	365	MSTOP(BUS_MCPU2, BIT(1))),
		366	DEF_MOD("scif1_clk_pck", R9A08G046_SCIF1_CLK_PCK, R9A08G046_CLK_P0, 0x584, 1,
		367	MSTOP(BUS_MCPU2, BIT(2))),
		368	DEF_MOD("scif2_clk_pck", R9A08G046_SCIF2_CLK_PCK, R9A08G046_CLK_P0, 0x584, 2,
		369	MSTOP(BUS_MCPU2, BIT(3))),
		370	DEF_MOD("scif3_clk_pck", R9A08G046_SCIF3_CLK_PCK, R9A08G046_CLK_P0, 0x584, 3,
		371	MSTOP(BUS_MCPU2, BIT(4))),
		372	DEF_MOD("scif4_clk_pck", R9A08G046_SCIF4_CLK_PCK, R9A08G046_CLK_P0, 0x584, 4,
		373	MSTOP(BUS_MCPU2, BIT(5))),
		374	DEF_MOD("scif5_clk_pck", R9A08G046_SCIF5_CLK_PCK, R9A08G046_CLK_P0, 0x584, 5,
		375	MSTOP(BUS_MCPU3, BIT(4))),
		376	DEF_MOD("rspi0_pclk", R9A08G046_RSPI0_PCLK, R9A08G046_CLK_P3, 0x590, 0,
		377	MSTOP(BUS_MCPU1, BIT(14))),
		378	DEF_MOD("rspi1_pclk", R9A08G046_RSPI1_PCLK, R9A08G046_CLK_P3, 0x590, 1,
		379	MSTOP(BUS_MCPU1, BIT(15))),
		380	DEF_MOD("rspi2_pclk", R9A08G046_RSPI2_PCLK, R9A08G046_CLK_P3, 0x590, 2,
		381	MSTOP(BUS_MCPU2, BIT(0))),
		382	DEF_MOD("rspi0_tclk", R9A08G046_RSPI0_TCLK, R9A08G046_CLK_P17, 0x590, 8,
		383	MSTOP(BUS_MCPU1, BIT(14))),
		384	DEF_MOD("rspi1_tclk", R9A08G046_RSPI1_TCLK, R9A08G046_CLK_P18, 0x590, 9,
		385	MSTOP(BUS_MCPU1, BIT(15))),
		386	DEF_MOD("rspi2_tclk", R9A08G046_RSPI2_TCLK, R9A08G046_CLK_P19, 0x590, 10,
		387	MSTOP(BUS_MCPU2, BIT(0))),
		388	DEF_MOD("gpio_hclk", R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0,
		389	MSTOP(BUS_PERI_CPU, BIT(6))),
		390	DEF_MOD("rsci0_pclk", R9A08G046_RSCI0_PCLK, R9A08G046_CLK_P0, 0x618, 0,
		391	MSTOP(BUS_MCPU2, BIT(7))),
		392	DEF_MOD("rsci1_pclk", R9A08G046_RSCI1_PCLK, R9A08G046_CLK_P0, 0x618, 1,
		393	MSTOP(BUS_MCPU2, BIT(8))),
		394	DEF_MOD("rsci2_pclk", R9A08G046_RSCI2_PCLK, R9A08G046_CLK_P0, 0x618, 2,
		395	MSTOP(BUS_MCPU3, BIT(11))),
		396	DEF_MOD("rsci3_pclk", R9A08G046_RSCI3_PCLK, R9A08G046_CLK_P0, 0x618, 3,
		397	MSTOP(BUS_MCPU3, BIT(12))),
		398	DEF_MOD("rsci0_tclk", R9A08G046_RSCI0_TCLK, R9A08G046_CLK_P13, 0x618, 8,
		399	MSTOP(BUS_MCPU2, BIT(7))),
		400	DEF_MOD("rsci1_tclk", R9A08G046_RSCI1_TCLK, R9A08G046_CLK_P14, 0x618, 9,
		401	MSTOP(BUS_MCPU2, BIT(8))),
		402	DEF_MOD("rsci2_tclk", R9A08G046_RSCI2_TCLK, R9A08G046_CLK_P15, 0x618, 10,
		403	MSTOP(BUS_MCPU3, BIT(11))),
		404	DEF_MOD("rsci3_tclk", R9A08G046_RSCI3_TCLK, R9A08G046_CLK_P16, 0x618, 11,
		405	MSTOP(BUS_MCPU3, BIT(12))),
106	};	406	};
107		407
108	static const struct rzg2l_reset r9a08g046_resets[] = {	408	static const struct rzg2l_reset r9a08g046_resets[] = {
@@ -111,11 +411,45 @@ static const struct rzg2l_reset r9a08g046_resets[] = { · 2 unmodified lines
111	DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0),	411	DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0),
112	DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0),	412	DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0),
113	DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1),	413	DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1),
		414	DEF_RST(R9A08G046_WDT0_PRESETN, 0x848, 0),
		415	DEF_RST(R9A08G046_SSI0_RST_M2_REG, 0x870, 0),
		416	DEF_RST(R9A08G046_SSI1_RST_M2_REG, 0x870, 1),
		417	DEF_RST(R9A08G046_SSI2_RST_M2_REG, 0x870, 2),
		418	DEF_RST(R9A08G046_SSI3_RST_M2_REG, 0x870, 3),
		419	DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0),
		420	DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1),
		421	DEF_RST(R9A08G046_I2C0_MRST, 0x880, 0),
		422	DEF_RST(R9A08G046_I2C1_MRST, 0x880, 1),
		423	DEF_RST(R9A08G046_I2C2_MRST, 0x880, 2),
		424	DEF_RST(R9A08G046_I2C3_MRST, 0x880, 3),
114	DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),	425	DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),
		426	DEF_RST(R9A08G046_SCIF1_RST_SYSTEM_N, 0x884, 1),
		427	DEF_RST(R9A08G046_SCIF2_RST_SYSTEM_N, 0x884, 2),
		428	DEF_RST(R9A08G046_SCIF3_RST_SYSTEM_N, 0x884, 3),
		429	DEF_RST(R9A08G046_SCIF4_RST_SYSTEM_N, 0x884, 4),
		430	DEF_RST(R9A08G046_SCIF5_RST_SYSTEM_N, 0x884, 5),
		431	DEF_RST(R9A08G046_RSPI0_PRESETN, 0x890, 0),
		432	DEF_RST(R9A08G046_RSPI1_PRESETN, 0x890, 1),
		433	DEF_RST(R9A08G046_RSPI2_PRESETN, 0x890, 2),
		434	DEF_RST(R9A08G046_RSPI0_TRESETN, 0x890, 8),
		435	DEF_RST(R9A08G046_RSPI1_TRESETN, 0x890, 9),
		436	DEF_RST(R9A08G046_RSPI2_TRESETN, 0x890, 10),
		437	DEF_RST(R9A08G046_GPIO_RSTN, 0x898, 0),
		438	DEF_RST(R9A08G046_GPIO_PORT_RESETN, 0x898, 1),
		439	DEF_RST(R9A08G046_GPIO_SPARE_RESETN, 0x898, 2),
		440	DEF_RST(R9A08G046_RSCI0_PRESETN, 0x918, 0),
		441	DEF_RST(R9A08G046_RSCI1_PRESETN, 0x918, 1),
		442	DEF_RST(R9A08G046_RSCI2_PRESETN, 0x918, 2),
		443	DEF_RST(R9A08G046_RSCI3_PRESETN, 0x918, 3),
		444	DEF_RST(R9A08G046_RSCI0_TRESETN, 0x918, 8),
		445	DEF_RST(R9A08G046_RSCI1_TRESETN, 0x918, 9),
		446	DEF_RST(R9A08G046_RSCI2_TRESETN, 0x918, 10),
		447	DEF_RST(R9A08G046_RSCI3_TRESETN, 0x918, 11),
115	};	448	};
116		449
117	static const unsigned int r9a08g046_crit_mod_clks[] __initconst = {	450	static const unsigned int r9a08g046_crit_mod_clks[] __initconst = {
118	MOD_CLK_BASE + R9A08G046_GIC600_GICCLK,	451	MOD_CLK_BASE + R9A08G046_GIC600_GICCLK,
		452	MOD_CLK_BASE + R9A08G046_IA55_PCLK,
119	MOD_CLK_BASE + R9A08G046_IA55_CLK,	453	MOD_CLK_BASE + R9A08G046_IA55_CLK,
120	MOD_CLK_BASE + R9A08G046_DMAC_ACLK,	454	MOD_CLK_BASE + R9A08G046_DMAC_ACLK,
121	};	455	};
@@ -125,6 +459,23 @@ static const unsigned int r9a08g046_crit_resets[] = { · 3 unmodified lines
125	R9A08G046_DMAC_RST_ASYNC,	459	R9A08G046_DMAC_RST_ASYNC,
126	};	460	};
127		461
		462	static const unsigned int r9a08g046_no_pm_mod_clks[] = {
		463	MOD_CLK_BASE + R9A08G046_ETH0_CLK_TX_I,
		464	MOD_CLK_BASE + R9A08G046_ETH0_CLK_TX_180_I,
		465	MOD_CLK_BASE + R9A08G046_ETH0_CLK_RX_I,
		466	MOD_CLK_BASE + R9A08G046_ETH0_CLK_RX_180_I,
		467	MOD_CLK_BASE + R9A08G046_ETH0_CLK_RMII_I,
		468	MOD_CLK_BASE + R9A08G046_ETH0_CLK_TX_I_RMII,
		469	MOD_CLK_BASE + R9A08G046_ETH0_CLK_RX_I_RMII,
		470	MOD_CLK_BASE + R9A08G046_ETH1_CLK_TX_I,
		471	MOD_CLK_BASE + R9A08G046_ETH1_CLK_TX_180_I,
		472	MOD_CLK_BASE + R9A08G046_ETH1_CLK_RX_I,
		473	MOD_CLK_BASE + R9A08G046_ETH1_CLK_RX_180_I,
		474	MOD_CLK_BASE + R9A08G046_ETH1_CLK_RMII_I,
		475	MOD_CLK_BASE + R9A08G046_ETH1_CLK_TX_I_RMII,
		476	MOD_CLK_BASE + R9A08G046_ETH1_CLK_RX_I_RMII,
		477	};
		478
128	const struct rzg2l_cpg_info r9a08g046_cpg_info = {	479	const struct rzg2l_cpg_info r9a08g046_cpg_info = {
129	/* Core Clocks */	480	/* Core Clocks */
130	.core_clks = r9a08g046_core_clks,	481	.core_clks = r9a08g046_core_clks,
@@ -141,6 +492,10 @@ const struct rzg2l_cpg_info r9a08g046_cpg_info = { · 10 unmodified lines
141	.num_mod_clks = ARRAY_SIZE(r9a08g046_mod_clks),	492	.num_mod_clks = ARRAY_SIZE(r9a08g046_mod_clks),
142	.num_hw_mod_clks = R9A08G046_BSC_X_BCK_BSC + 1,	493	.num_hw_mod_clks = R9A08G046_BSC_X_BCK_BSC + 1,
143		494
		495	/* No PM modules Clocks */
		496	.no_pm_mod_clks = r9a08g046_no_pm_mod_clks,
		497	.num_no_pm_mod_clks = ARRAY_SIZE(r9a08g046_no_pm_mod_clks),
		498
144	/* Resets */	499	/* Resets */
145	.resets = r9a08g046_resets,	500	.resets = r9a08g046_resets,
146	.num_resets = R9A08G046_BSC_X_PRESET_BSC + 1, /* Last reset ID + 1 */	501	.num_resets = R9A08G046_BSC_X_PRESET_BSC + 1, /* Last reset ID + 1 */

drivers/clk/renesas/r9a09g011-cpg.c+1−6

 #include "rzg2l-cpg.h"
-#define RZV2M_SAMPLL4_CLK1	0x104
-#define RZV2M_SAMPLL4_CLK2	0x108
-#define PLL4_CONF	(RZV2M_SAMPLL4_CLK1 << 22 | RZV2M_SAMPLL4_CLK2 << 12)
 #define DIV_A		DDIV_PACK(0x200, 0, 3)
 #define DIV_B		DDIV_PACK(0x204, 0, 2)
 #define DIV_D		DDIV_PACK(0x204, 4, 2)
 	DEF_FIXED(".pll2_400",	CLK_PLL2_400,	CLK_PLL2_800,	1,	2),
 	DEF_FIXED(".pll2_200",	CLK_PLL2_200,	CLK_PLL2_800,	1,	4),
 	DEF_FIXED(".pll2_100",	CLK_PLL2_100,	CLK_PLL2_800,	1,	8),
-	DEF_SAMPLL(".pll4",	CLK_PLL4,	CLK_MAIN_2,	PLL4_CONF),
+	DEF_SAMPLL(".pll4",	CLK_PLL4,	CLK_MAIN_2,	CPG_SAM_PLL_CONF(0x100)),
 	DEF_DIV_RO(".diva",	CLK_DIV_A,	CLK_PLL1,	DIV_A,	dtable_diva),
 	DEF_DIV_RO(".divb",	CLK_DIV_B,	CLK_PLL2_400,	DIV_B,	dtable_divb),

drivers/clk/renesas/r9a09g047-cpg.c+84−0

@@ -6,6 +6,7 @@ · 5 unmodified lines
6	*/	6	*/
7		7
8	#include <linux/clk-provider.h>	8	#include <linux/clk-provider.h>
		9	#include <linux/clk/renesas.h>
9	#include <linux/device.h>	10	#include <linux/device.h>
10	#include <linux/init.h>	11	#include <linux/init.h>
11	#include <linux/kernel.h>	12	#include <linux/kernel.h>
@@ -30,6 +31,8 @@ enum clk_ids { · 18 unmodified lines
30	CLK_PLLCA55,	31	CLK_PLLCA55,
31	CLK_PLLVDO,	32	CLK_PLLVDO,
32	CLK_PLLETH,	33	CLK_PLLETH,
		34	CLK_PLLDSI0,
		35	CLK_PLLDSI1,
33		36
34	/* Internal Core Clocks */	37	/* Internal Core Clocks */
35	CLK_PLLCM33_DIV3,	38	CLK_PLLCM33_DIV3,
@@ -57,6 +60,8 @@ enum clk_ids { · 21 unmodified lines
57	CLK_PLLETH_DIV_125_FIX,	60	CLK_PLLETH_DIV_125_FIX,
58	CLK_CSDIV_PLLETH_GBE0,	61	CLK_CSDIV_PLLETH_GBE0,
59	CLK_CSDIV_PLLETH_GBE1,	62	CLK_CSDIV_PLLETH_GBE1,
		63	CLK_SMUX2_DSI0_CLK,
		64	CLK_SMUX2_DSI1_CLK,
60	CLK_SMUX2_GBE0_TXCLK,	65	CLK_SMUX2_GBE0_TXCLK,
61	CLK_SMUX2_GBE0_RXCLK,	66	CLK_SMUX2_GBE0_RXCLK,
62	CLK_SMUX2_GBE1_TXCLK,	67	CLK_SMUX2_GBE1_TXCLK,
@@ -64,6 +69,12 @@ enum clk_ids { · 1 unmodified line
64	CLK_PLLDTY_DIV16,	69	CLK_PLLDTY_DIV16,
65	CLK_PLLVDO_CRU0,	70	CLK_PLLVDO_CRU0,
66	CLK_PLLVDO_GPU,	71	CLK_PLLVDO_GPU,
		72	CLK_PLLETH_DIV4_LPCLK,
		73	CLK_PLLETH_LPCLK,
		74	CLK_PLLDSI0_DIV7,
		75	CLK_PLLDSI1_DIV7,
		76	CLK_PLLDSI0_CSDIV,
		77	CLK_PLLDSI1_CSDIV,
67		78
68	/* Module Clocks */	79	/* Module Clocks */
69	MOD_CLK_BASE,	80	MOD_CLK_BASE,
@@ -91,6 +102,18 @@ static const struct clk_div_table dtable_2_16[] = { · 21 unmodified lines
91	{0, 0},	102	{0, 0},
92	};	103	};
93		104
		105	static const struct clk_div_table dtable_2_16_plldsi[] = {
		106	{0, 2},
		107	{1, 4},
		108	{2, 6},
		109	{3, 8},
		110	{4, 10},
		111	{5, 12},
		112	{6, 14},
		113	{7, 16},
		114	{0, 0},
		115	};
		116
94	static const struct clk_div_table dtable_2_64[] = {	117	static const struct clk_div_table dtable_2_64[] = {
95	{0, 2},	118	{0, 2},
96	{1, 4},	119	{1, 4},
@@ -107,7 +130,23 @@ static const struct clk_div_table dtable_2_100[] = { · 10 unmodified lines
107	{0, 0},	130	{0, 0},
108	};	131	};
109		132
		133	static const struct clk_div_table dtable_16_128[] = {
		134	{0, 16},
		135	{1, 32},
		136	{2, 64},
		137	{3, 128},
		138	{0, 0},
		139	};
		140
		141	RZG3E_CPG_PLL_DSI0_LIMITS(rzg3e_cpg_pll_dsi0_limits);
		142	RZG3E_CPG_PLL_DSI1_LIMITS(rzg3e_cpg_pll_dsi1_limits);
		143
		144	#define PLLDSI0 PLL_PACK_LIMITS(0xc0, 1, 0, &rzg3e_cpg_pll_dsi0_limits)
		145	#define PLLDSI1 PLL_PACK_LIMITS(0x160, 1, 1, &rzg3e_cpg_pll_dsi1_limits)
		146
110	/* Mux clock tables */	147	/* Mux clock tables */
		148	static const char * const smux2_dsi0_clk[] = { ".plldsi0_div7", ".plldsi0_csdiv" };
		149	static const char * const smux2_dsi1_clk[] = { ".plldsi1_div7", ".plldsi1_csdiv" };
111	static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };	150	static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
112	static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };	151	static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
113	static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };	152	static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
@@ -128,6 +167,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { · 14 unmodified lines
128	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),	167	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
129	DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),	168	DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
130	DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),	169	DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
		170	DEF_PLLDSI(".plldsi0", CLK_PLLDSI0, CLK_QEXTAL, PLLDSI0),
		171	DEF_PLLDSI(".plldsi1", CLK_PLLDSI1, CLK_QEXTAL, PLLDSI1),
131		172
132	/* Internal Core Clocks */	173	/* Internal Core Clocks */
133	DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),	174	DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
@@ -171,6 +212,21 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { · 37 unmodified lines
171	DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),	212	DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
172	DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),	213	DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
173		214
		215	DEF_FIXED(".plleth_div4_lpclk", CLK_PLLETH_DIV4_LPCLK, CLK_PLLETH, 1, 4),
		216	DEF_CSDIV(".plleth_lpclk", CLK_PLLETH_LPCLK, CLK_PLLETH_DIV4_LPCLK,
		217	CSDIV0_DIVCTL2, dtable_16_128),
		218
		219	DEF_PLLDSI_DIV(".plldsi0_csdiv", CLK_PLLDSI0_CSDIV, CLK_PLLDSI0,
		220	CSDIV1_DIVCTL2, dtable_2_16_plldsi),
		221	DEF_PLLDSI_DIV(".plldsi1_csdiv", CLK_PLLDSI1_CSDIV, CLK_PLLDSI1,
		222	CSDIV1_DIVCTL3, dtable_2_16_plldsi),
		223	DEF_FIXED(".plldsi0_div7", CLK_PLLDSI0_DIV7, CLK_PLLDSI0, 1, 7),
		224	DEF_FIXED(".plldsi1_div7", CLK_PLLDSI1_DIV7, CLK_PLLDSI1, 1, 7),
		225	DEF_PLLDSI_SMUX(".smux2_dsi0_clk", CLK_SMUX2_DSI0_CLK,
		226	SSEL3_SELCTL0, smux2_dsi0_clk),
		227	DEF_PLLDSI_SMUX(".smux2_dsi1_clk", CLK_SMUX2_DSI1_CLK,
		228	SSEL3_SELCTL1, smux2_dsi1_clk),
		229
174	/* Core Clocks */	230	/* Core Clocks */
175	DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),	231	DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
176	DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,	232	DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,
@@ -452,6 +508,22 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { · 275 unmodified lines
452	BUS_MSTOP(9, BIT(4))),	508	BUS_MSTOP(9, BIT(4))),
453	DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,	509	DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
454	BUS_MSTOP(9, BIT(4))),	510	BUS_MSTOP(9, BIT(4))),
		511	DEF_MOD("dsi_0_pclk", CLK_PLLDTY_DIV16, 14, 8, 7, 8,
		512	BUS_MSTOP(9, BIT(15) \| BIT(14))),
		513	DEF_MOD("dsi_0_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
		514	BUS_MSTOP(9, BIT(15) \| BIT(14))),
		515	DEF_MOD("dsi_0_vclk1", CLK_SMUX2_DSI0_CLK, 14, 10, 7, 10,
		516	BUS_MSTOP(9, BIT(15) \| BIT(14))),
		517	DEF_MOD("dsi_0_lpclk", CLK_PLLETH_LPCLK, 14, 11, 7, 11,
		518	BUS_MSTOP(9, BIT(15) \| BIT(14))),
		519	DEF_MOD("dsi_0_pllref_clk", CLK_QEXTAL, 14, 12, 7, 12,
		520	BUS_MSTOP(9, BIT(15) \| BIT(14))),
		521	DEF_MOD("lcdc_0_clk_a", CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,
		522	BUS_MSTOP(10, BIT(3) \| BIT(2) \| BIT(1))),
		523	DEF_MOD("lcdc_0_clk_p", CLK_PLLDTY_DIV16, 14, 14, 7, 14,
		524	BUS_MSTOP(10, BIT(3) \| BIT(2) \| BIT(1))),
		525	DEF_MOD("lcdc_0_clk_d", CLK_SMUX2_DSI0_CLK, 14, 15, 7, 15,
		526	BUS_MSTOP(10, BIT(3) \| BIT(2) \| BIT(1))),
455	DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16,	527	DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16,
456	BUS_MSTOP(3, BIT(4))),	528	BUS_MSTOP(3, BIT(4))),
457	DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,	529	DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
@@ -460,6 +532,14 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { · 2 unmodified lines
460	BUS_MSTOP(3, BIT(4))),	532	BUS_MSTOP(3, BIT(4))),
461	DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,	533	DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
462	BUS_MSTOP(2, BIT(15))),	534	BUS_MSTOP(2, BIT(15))),
		535	DEF_MOD("dsi_0_vclk2", CLK_SMUX2_DSI1_CLK, 25, 0, 10, 21,
		536	BUS_MSTOP(9, BIT(15) \| BIT(14))),
		537	DEF_MOD("lcdc_1_clk_a", CLK_PLLDTY_ACPU_DIV2, 26, 8, 10, 30,
		538	BUS_MSTOP(13, BIT(5) \| BIT(4) \| BIT(3))),
		539	DEF_MOD("lcdc_1_clk_p", CLK_PLLDTY_DIV16, 26, 9, 10, 31,
		540	BUS_MSTOP(13, BIT(5) \| BIT(4) \| BIT(3))),
		541	DEF_MOD("lcdc_1_clk_d", CLK_SMUX2_DSI1_CLK, 26, 10, 11, 0,
		542	BUS_MSTOP(13, BIT(5) \| BIT(4) \| BIT(3))),
463	};	543	};
464		544
465	static const struct rzv2h_reset r9a09g047_resets[] __initconst = {	545	static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
@@ -535,10 +615,14 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { · 69 unmodified lines
535	DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */	615	DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
536	DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */	616	DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
537	DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */	617	DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
		618	DEF_RST(13, 7, 6, 8), /* DSI_0_PRESETN */
		619	DEF_RST(13, 8, 6, 9), /* DSI_0_ARESETN */
		620	DEF_RST(13, 12, 6, 13), /* LCDC_0_RESET_N */
538	DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */	621	DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */
539	DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */	622	DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */
540	DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */	623	DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */
541	DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */	624	DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
		625	DEF_RST(17, 14, 8, 15), /* LCDC_1_RESET_N */
542	};	626	};
543		627
544	const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {	628	const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {

drivers/clk/renesas/r9a09g077-cpg.c+1−0

@@ -257,6 +257,7 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = { · 256 unmodified lines
257	DEF_MOD("spi0", 104, CLK_SPI0ASYNC),	257	DEF_MOD("spi0", 104, CLK_SPI0ASYNC),
258	DEF_MOD("spi1", 105, CLK_SPI1ASYNC),	258	DEF_MOD("spi1", 105, CLK_SPI1ASYNC),
259	DEF_MOD("spi2", 106, CLK_SPI2ASYNC),	259	DEF_MOD("spi2", 106, CLK_SPI2ASYNC),
		260	DEF_MOD("mtu3", 200, R9A09G077_CLK_PCLKH),
260	DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),	261	DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),
261	DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),	262	DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),
262	DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),	263	DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),

drivers/clk/renesas/renesas-cpg-mssr.c+3−0

@@ -370,6 +370,9 @@ struct clk cpg_mssr_clk_src_twocell_get(struct of_phandle_args clkspec, · 369 unmodified lines
370	struct clk *clk;	370	struct clk *clk;
371	int range_check;	371	int range_check;
372		372
		373	if (clkspec->args_count != 2)
		374	return ERR_PTR(-EINVAL);
		375
373	switch (clkspec->args[0]) {	376	switch (clkspec->args[0]) {
374	case CPG_CORE:	377	case CPG_CORE:
375	type = "core";	378	type = "core";

drivers/clk/renesas/rzg2l-cpg.c+75−13

@@ -58,15 +58,22 @@ · 57 unmodified lines
58	#define RZG3S_DIV_NF GENMASK(12, 1)	58	#define RZG3S_DIV_NF GENMASK(12, 1)
59	#define RZG3S_SEL_PLL BIT(0)	59	#define RZG3S_SEL_PLL BIT(0)
60		60
		61	#define CPG_PLL1_SETTING_OFFSET(conf) FIELD_GET(GENMASK(11, 0), (conf))
		62	#define CPG_PLL_STBY_OFFSET(conf) FIELD_GET(GENMASK(23, 12), (conf))
		63	#define CPG_PLL_STBY_RESETB_WEN BIT(16)
		64	#define CPG_PLL_STBY_RESETB BIT(0)
		65	#define CPG_PLL_CLK1_OFFSET(x) (CPG_PLL_STBY_OFFSET(x) + 0x4)
		66	#define CPG_PLL_CLK2_OFFSET(x) (CPG_PLL_STBY_OFFSET(x) + 0x8)
		67	#define CPG_PLL_MON_OFFSET(x) (CPG_PLL_STBY_OFFSET(x) + 0xc)
		68	#define CPG_PLL_MON_LOCK BIT(4)
		69	#define CPG_PLL_MON_RESETB BIT(0)
		70
61	#define CLK_ON_R(reg) (reg)	71	#define CLK_ON_R(reg) (reg)
62	#define CLK_MON_R(reg) (0x180 + (reg))	72	#define CLK_MON_R(reg) (0x180 + (reg))
63	#define CLK_RST_R(reg) (reg)	73	#define CLK_RST_R(reg) (reg)
64	#define CLK_MRST_R(reg) (0x180 + (reg))	74	#define CLK_MRST_R(reg) (0x180 + (reg))
65		75
66	#define GET_REG_OFFSET(val) ((val >> 20) & 0xfff)	76	#define GET_REG_OFFSET(val) ((val >> 20) & 0xfff)
67	#define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff)
68	#define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff)
69	#define GET_REG_SAMPLL_SETTING(val) ((val) & 0xfff)
70		77
71	#define CPG_WEN_BIT BIT(16)	78	#define CPG_WEN_BIT BIT(16)
72		79
@@ -1086,8 +1093,8 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw, · 1013 unmodified lines
1086	if (pll_clk->type != CLK_TYPE_SAM_PLL)	1093	if (pll_clk->type != CLK_TYPE_SAM_PLL)
1087	return parent_rate;	1094	return parent_rate;
1088		1095
1089	val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));	1096	val1 = readl(priv->base + CPG_PLL_CLK1_OFFSET(pll_clk->conf));
1090	val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));	1097	val2 = readl(priv->base + CPG_PLL_CLK2_OFFSET(pll_clk->conf));
1091		1098
1092	rate = mul_u64_u32_shr(parent_rate, (MDIV(val1) << 16) + KDIV(val1),	1099	rate = mul_u64_u32_shr(parent_rate, (MDIV(val1) << 16) + KDIV(val1),
1093	16 + SDIV(val2));	1100	16 + SDIV(val2));
@@ -1107,17 +1114,14 @@ static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw, · 13 unmodified lines
1107	u32 nir, nfr, mr, pr, val, setting;	1114	u32 nir, nfr, mr, pr, val, setting;
1108	u64 rate;	1115	u64 rate;
1109		1116
1110	if (pll_clk->type != CLK_TYPE_G3S_PLL)	1117	setting = CPG_PLL1_SETTING_OFFSET(pll_clk->conf);
1111	return parent_rate;
1112
1113	setting = GET_REG_SAMPLL_SETTING(pll_clk->conf);
1114	if (setting) {	1118	if (setting) {
1115	val = readl(priv->base + setting);	1119	val = readl(priv->base + setting);
1116	if (val & RZG3S_SEL_PLL)	1120	if (val & RZG3S_SEL_PLL)
1117	return pll_clk->default_rate;	1121	return pll_clk->default_rate;
1118	}	1122	}
1119		1123
1120	val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));	1124	val = readl(priv->base + CPG_PLL_CLK1_OFFSET(pll_clk->conf));
1121		1125
1122	pr = 1 << FIELD_GET(RZG3S_DIV_P, val);	1126	pr = 1 << FIELD_GET(RZG3S_DIV_P, val);
1123	/* Hardware interprets values higher than 8 as p = 16. */	1127	/* Hardware interprets values higher than 8 as p = 16. */
@@ -1178,6 +1182,61 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, · 54 unmodified lines
1178	return pll_clk->hw.clk;	1182	return pll_clk->hw.clk;
1179	}	1183	}
1180		1184
		1185	static int rzg3l_cpg_pll_clk_is_enabled(struct clk_hw *hw)
		1186	{
		1187	struct pll_clk *pll_clk = to_pll(hw);
		1188	struct rzg2l_cpg_priv *priv = pll_clk->priv;
		1189	u32 val = readl(priv->base + CPG_PLL_MON_OFFSET(pll_clk->conf));
		1190	u32 mon_val = CPG_PLL_MON_RESETB \| CPG_PLL_MON_LOCK;
		1191
		1192	/* Ensure both RESETB and LOCK bits are set */
		1193	return (mon_val == (val & mon_val));
		1194	}
		1195
		1196	static int rzg3l_cpg_pll_clk_endisable(struct clk_hw *hw, bool enable)
		1197	{
		1198	struct pll_clk *pll_clk = to_pll(hw);
		1199	struct rzg2l_cpg_priv *priv = pll_clk->priv;
		1200	u32 mon_mask = CPG_PLL_MON_RESETB \| CPG_PLL_MON_LOCK;
		1201	u32 val = CPG_PLL_STBY_RESETB_WEN;
		1202	u32 stby_offset, mon_offset;
		1203	u32 mon_val = 0;
		1204	int ret;
		1205
		1206	stby_offset = CPG_PLL_STBY_OFFSET(pll_clk->conf);
		1207	mon_offset = CPG_PLL_MON_OFFSET(pll_clk->conf);
		1208
		1209	if (enable) {
		1210	val \|= CPG_PLL_STBY_RESETB;
		1211	mon_val = mon_mask;
		1212	}
		1213
		1214	writel(val, priv->base + stby_offset);
		1215
		1216	/* ensure PLL is in normal/standby mode */
		1217	ret = readl_poll_timeout_atomic(priv->base + mon_offset, val,
		1218	mon_val == (val & mon_mask), 10, 100);
		1219	if (ret)
		1220	dev_err(priv->dev, "Failed to %s PLL 0x%x/%pC\n", enable ?
		1221	"enable" : "disable", stby_offset, hw->clk);
		1222
		1223	return ret;
		1224	}
		1225
		1226	static int rzg3l_cpg_pll_clk_enable(struct clk_hw *hw)
		1227	{
		1228	if (rzg3l_cpg_pll_clk_is_enabled(hw))
		1229	return 0;
		1230
		1231	return rzg3l_cpg_pll_clk_endisable(hw, true);
		1232	}
		1233
		1234	static const struct clk_ops rzg3l_cpg_pll_ops = {
		1235	.is_enabled = rzg3l_cpg_pll_clk_is_enabled,
		1236	.enable = rzg3l_cpg_pll_clk_enable,
		1237	.recalc_rate = rzg3s_cpg_pll_clk_recalc_rate,
		1238	};
		1239
1181	static struct clk	1240	static struct clk
1182	rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args clkspec,	1241	rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args clkspec,
1183	void *data)	1242	void *data)
@@ -1261,6 +1320,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, · 77 unmodified lines
1261	case CLK_TYPE_SAM_PLL:	1320	case CLK_TYPE_SAM_PLL:
1262	clk = rzg2l_cpg_pll_clk_register(core, priv, &rzg2l_cpg_pll_ops);	1321	clk = rzg2l_cpg_pll_clk_register(core, priv, &rzg2l_cpg_pll_ops);
1263	break;	1322	break;
		1323	case CLK_TYPE_G3L_PLL:
		1324	clk = rzg2l_cpg_pll_clk_register(core, priv, &rzg3l_cpg_pll_ops);
		1325	break;
1264	case CLK_TYPE_G3S_PLL:	1326	case CLK_TYPE_G3S_PLL:
1265	clk = rzg2l_cpg_pll_clk_register(core, priv, &rzg3s_cpg_pll_ops);	1327	clk = rzg2l_cpg_pll_clk_register(core, priv, &rzg3s_cpg_pll_ops);
1266	break;	1328	break;
@@ -1340,10 +1402,10 @@ struct mod_clock { · 73 unmodified lines
1340	#define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)	1402	#define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
1341		1403
1342	#define for_each_mod_clock(mod_clock, hw, priv) \	1404	#define for_each_mod_clock(mod_clock, hw, priv) \
1343	for (unsigned int i = 0; (priv) && i < (priv)->num_mod_clks; i++) \	1405	for (unsigned int __i = 0; (priv) && __i < (priv)->num_mod_clks; __i++) \
1344	if ((priv)->clks[(priv)->num_core_clks + i] == ERR_PTR(-ENOENT)) \	1406	if ((priv)->clks[(priv)->num_core_clks + __i] == ERR_PTR(-ENOENT)) \
1345	continue; \	1407	continue; \
1346	else if (((hw) = __clk_get_hw((priv)->clks[(priv)->num_core_clks + i])) && \	1408	else if (((hw) = __clk_get_hw((priv)->clks[(priv)->num_core_clks + __i])) && \
1347	((mod_clock) = to_mod_clock(hw)))	1409	((mod_clock) = to_mod_clock(hw)))
1348		1410
1349	/* Need to be called with a lock held to avoid concurrent access to mstop->usecnt. */	1411	/* Need to be called with a lock held to avoid concurrent access to mstop->usecnt. */

drivers/clk/renesas/rzg2l-cpg.h+11−7

 #define CPG_CLKSTATUS_SELSDHI0_STS	BIT(28)
 #define CPG_CLKSTATUS_SELSDHI1_STS	BIT(29)
-/* n = 0/1/2 for PLL1/4/6 */
+#define CPG_SAM_PLL_CONF(stby)		((stby) << 12)
-#define CPG_SAMPLL_CLK1(n)	(0x04 + (16 * n))
+#define CPG_PLL_CONF(stby, setting)	((stby) << 12 | (setting))
-#define CPG_SAMPLL_CLK2(n)	(0x08 + (16 * n))
-#define PLL146_CONF(n)	(CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12)
 #define DDIV_PACK(offset, bitpos, size) \
 		(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
 	CLK_TYPE_IN,		/* External Clock Input */
 	CLK_TYPE_FF,		/* Fixed Factor Clock */
 	CLK_TYPE_SAM_PLL,
+	CLK_TYPE_G3L_PLL,
 	CLK_TYPE_G3S_PLL,
 	/* Clock with divider */
 	DEF_TYPE(_name, _id, _type, .parent = _parent)
 #define DEF_SAMPLL(_name, _id, _parent, _conf) \
 	DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
+#define DEF_G3L_PLL(_name, _id, _parent, _conf, _default_rate) \
+	DEF_TYPE(_name, _id, CLK_TYPE_G3L_PLL, .parent = _parent, .conf = _conf, \
+		 .default_rate = _default_rate)
 #define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \
 	DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf, \
 		 .default_rate = _default_rate)
 		 .invalid_rate = _invalid_rate, \
 		 .max_rate = _max_rate, .flag = (_clk_flags), \
 		 .notifier = _notif)
-#define DEF_MUX(_name, _id, _conf, _parent_names) \
+#define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flag) \
 	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
 		 .parent_names = _parent_names, \
 		 .num_parents = ARRAY_SIZE(_parent_names), \
-		 .mux_flags = CLK_MUX_HIWORD_MASK)
+		 .mux_flags = CLK_MUX_HIWORD_MASK, \
+		 .flag = _flag)
+#define DEF_MUX(_name, _id, _conf, _parent_names) \
+	DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, 0)
 #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \
 	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
 		 .parent_names = _parent_names, \

drivers/clk/renesas/rzv2h-cpg.c+181−0

@@ -76,6 +76,11 @@ · 75 unmodified lines
76	/* On RZ/G3E SoC we have two DSI PLLs */	76	/* On RZ/G3E SoC we have two DSI PLLs */
77	#define MAX_CPG_DSI_PLL 2	77	#define MAX_CPG_DSI_PLL 2
78		78
		79	#define CPG_PLLDSI_SMUX_LVDS_DUTY_NUM 4
		80	#define CPG_PLLDSI_SMUX_LVDS_DUTY_DEN 7
		81	#define CPG_PLLDSI_SMUX_DSI_RGB_DUTY_NUM 1
		82	#define CPG_PLLDSI_SMUX_DSI_RGB_DUTY_DEN 2
		83
79	/**	84	/**
80	* struct rzv2h_pll_dsi_info - PLL DSI information, holds the limits and parameters	85	* struct rzv2h_pll_dsi_info - PLL DSI information, holds the limits and parameters
81	*	86	*
@@ -418,6 +423,20 @@ bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits, · 336 unmodified lines
418	}	423	}
419	EXPORT_SYMBOL_NS_GPL(rzv2h_get_pll_divs_pars, "RZV2H_CPG");	424	EXPORT_SYMBOL_NS_GPL(rzv2h_get_pll_divs_pars, "RZV2H_CPG");
420		425
		426	/**
		427	* struct rzv2h_plldsi_mux_clk - PLL DSI MUX clock
		428	*
		429	* @priv: CPG private data
		430	* @mux: mux clk
		431	*/
		432	struct rzv2h_plldsi_mux_clk {
		433	struct rzv2h_cpg_priv *priv;
		434	struct clk_mux mux;
		435	};
		436
		437	#define to_plldsi_clk_mux(_mux) \
		438	container_of(_mux, struct rzv2h_plldsi_mux_clk, mux)
		439
421	static unsigned long rzv2h_cpg_plldsi_div_recalc_rate(struct clk_hw *hw,	440	static unsigned long rzv2h_cpg_plldsi_div_recalc_rate(struct clk_hw *hw,
422	unsigned long parent_rate)	441	unsigned long parent_rate)
423	{	442	{
@@ -649,6 +668,165 @@ static int rzv2h_cpg_plldsi_set_rate(struct clk_hw *hw, unsigned long rate, · 225 unmodified lines
649	return rzv2h_cpg_pll_set_rate(pll_clk, &dsi_info->pll_dsi_parameters.pll, true);	668	return rzv2h_cpg_pll_set_rate(pll_clk, &dsi_info->pll_dsi_parameters.pll, true);
650	}	669	}
651		670
		671	static u8 rzv2h_cpg_plldsi_smux_get_parent(struct clk_hw *hw)
		672	{
		673	return clk_mux_ops.get_parent(hw);
		674	}
		675
		676	static int rzv2h_cpg_plldsi_smux_set_parent(struct clk_hw *hw, u8 index)
		677	{
		678	return clk_mux_ops.set_parent(hw, index);
		679	}
		680
		681	static int rzv2h_cpg_plldsi_smux_lvds_determine_rate(struct rzv2h_cpg_priv *priv,
		682	struct pll_clk *pll_clk,
		683	struct clk_rate_request *req)
		684	{
		685	struct rzv2h_pll_div_pars *dsi_params;
		686	struct rzv2h_pll_dsi_info *dsi_info;
		687	u8 lvds_table[] = { 7 };
		688	u64 rate_millihz;
		689
		690	dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];
		691	dsi_params = &dsi_info->pll_dsi_parameters;
		692
		693	rate_millihz = mul_u32_u32(req->rate, MILLI);
		694	if (!rzv2h_get_pll_divs_pars(dsi_info->pll_dsi_limits, dsi_params,
		695	lvds_table, ARRAY_SIZE(lvds_table), rate_millihz)) {
		696	dev_err(priv->dev, "failed to determine rate for req->rate: %lu\n",
		697	req->rate);
		698	return -EINVAL;
		699	}
		700
		701	req->rate = DIV_ROUND_CLOSEST_ULL(dsi_params->div.freq_millihz, MILLI);
		702	req->best_parent_rate = req->rate;
		703	dsi_info->req_pll_dsi_rate = req->best_parent_rate * dsi_params->div.divider_value;
		704
		705	return 0;
		706	}
		707
		708	static int rzv2h_cpg_plldsi_smux_determine_rate(struct clk_hw *hw,
		709	struct clk_rate_request *req)
		710	{
		711	struct clk_mux *mux = to_clk_mux(hw);
		712	struct rzv2h_plldsi_mux_clk *dsi_mux = to_plldsi_clk_mux(mux);
		713	struct pll_clk *pll_clk = to_pll(clk_hw_get_parent(hw));
		714	struct rzv2h_cpg_priv *priv = dsi_mux->priv;
		715
		716	/*
		717	* For LVDS output (parent index 0), calculate PLL parameters with
		718	* fixed divider value of 7. For DSI/RGB output (parent index 1) skip
		719	* PLL calculation here as it's handled by determine_rate of the
		720	* divider (up one level).
		721	*/
		722	if (!clk_mux_ops.get_parent(hw))
		723	return rzv2h_cpg_plldsi_smux_lvds_determine_rate(priv, pll_clk, req);
		724
		725	req->best_parent_rate = req->rate;
		726	return 0;
		727	}
		728
		729	static int rzv2h_cpg_plldsi_smux_get_duty_cycle(struct clk_hw *hw,
		730	struct clk_duty *duty)
		731	{
		732	u8 parent = clk_mux_ops.get_parent(hw);
		733
		734	/*
		735	* CDIV7_DSIx_CLK - LVDS path (div7) - duty 4/7.
		736	* CSDIV_DSIx - DSI/RGB path (csdiv) - duty 1/2.
		737	*/
		738	if (parent == 0) {
		739	duty->num = CPG_PLLDSI_SMUX_LVDS_DUTY_NUM;
		740	duty->den = CPG_PLLDSI_SMUX_LVDS_DUTY_DEN;
		741	} else {
		742	duty->num = CPG_PLLDSI_SMUX_DSI_RGB_DUTY_NUM;
		743	duty->den = CPG_PLLDSI_SMUX_DSI_RGB_DUTY_DEN;
		744	}
		745
		746	return 0;
		747	}
		748
		749	static int rzv2h_cpg_plldsi_smux_set_duty_cycle(struct clk_hw *hw,
		750	struct clk_duty *duty)
		751	{
		752	struct clk_hw *parent_hw;
		753	u8 parent_idx;
		754
		755	/*
		756	* Select parent based on requested duty cycle:
		757	* - If duty > 50% (num/den > 1/2), select LVDS path (parent 0)
		758	* - Otherwise, select DSI/RGB path (parent 1)
		759	*/
		760	if (duty->num * CPG_PLLDSI_SMUX_DSI_RGB_DUTY_DEN >
		761	duty->den * CPG_PLLDSI_SMUX_DSI_RGB_DUTY_NUM)
		762	parent_idx = 0;
		763	else
		764	parent_idx = 1;
		765
		766	if (parent_idx >= clk_hw_get_num_parents(hw))
		767	return -EINVAL;
		768
		769	parent_hw = clk_hw_get_parent_by_index(hw, parent_idx);
		770	if (!parent_hw)
		771	return -EINVAL;
		772
		773	return clk_hw_set_parent(hw, parent_hw);
		774	}
		775
		776	static const struct clk_ops rzv2h_cpg_plldsi_smux_ops = {
		777	.determine_rate = rzv2h_cpg_plldsi_smux_determine_rate,
		778	.get_parent = rzv2h_cpg_plldsi_smux_get_parent,
		779	.set_parent = rzv2h_cpg_plldsi_smux_set_parent,
		780	.get_duty_cycle = rzv2h_cpg_plldsi_smux_get_duty_cycle,
		781	.set_duty_cycle = rzv2h_cpg_plldsi_smux_set_duty_cycle,
		782	};
		783
		784	static struct clk * __init
		785	rzv2h_cpg_plldsi_smux_clk_register(const struct cpg_core_clk *core,
		786	struct rzv2h_cpg_priv *priv)
		787	{
		788	struct rzv2h_plldsi_mux_clk *clk_hw_data;
		789	struct clk_init_data init;
		790	struct clk_hw *clk_hw;
		791	struct smuxed smux;
		792	int ret;
		793
		794	smux = core->cfg.smux;
		795
		796	if (smux.shift + smux.width > 16) {
		797	dev_err(priv->dev, "mux value exceeds LOWORD field\n");
		798	return ERR_PTR(-EINVAL);
		799	}
		800
		801	clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
		802	if (!clk_hw_data)
		803	return ERR_PTR(-ENOMEM);
		804
		805	clk_hw_data->priv = priv;
		806
		807	init.name = core->name;
		808	init.ops = &rzv2h_cpg_plldsi_smux_ops;
		809	init.flags = core->flag;
		810	init.parent_names = core->parent_names;
		811	init.num_parents = core->num_parents;
		812
		813	clk_hw_data->mux.reg = priv->base + smux.offset;
		814
		815	clk_hw_data->mux.shift = smux.shift;
		816	clk_hw_data->mux.mask = clk_div_mask(smux.width);
		817	clk_hw_data->mux.flags = core->mux_flags;
		818	clk_hw_data->mux.lock = &priv->rmw_lock;
		819
		820	clk_hw = &clk_hw_data->mux.hw;
		821	clk_hw->init = &init;
		822
		823	ret = devm_clk_hw_register(priv->dev, clk_hw);
		824	if (ret)
		825	return ERR_PTR(ret);
		826
		827	return clk_hw->clk;
		828	}
		829
652	static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw)	830	static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw)
653	{	831	{
654	struct pll_clk *pll_clk = to_pll(hw);	832	struct pll_clk *pll_clk = to_pll(hw);
@@ -1085,6 +1263,9 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core, · 430 unmodified lines
1085	case CLK_TYPE_PLLDSI_DIV:	1263	case CLK_TYPE_PLLDSI_DIV:
1086	clk = rzv2h_cpg_plldsi_div_clk_register(core, priv);	1264	clk = rzv2h_cpg_plldsi_div_clk_register(core, priv);
1087	break;	1265	break;
		1266	case CLK_TYPE_PLLDSI_SMUX:
		1267	clk = rzv2h_cpg_plldsi_smux_clk_register(core, priv);
		1268	break;
1088	default:	1269	default:
1089	goto fail;	1270	goto fail;
1090	}	1271	}

drivers/clk/renesas/rzv2h-cpg.h+12−0

 #define CPG_SSEL0		(0x300)
 #define CPG_SSEL1		(0x304)
+#define CPG_SSEL3		(0x30C)
 #define CPG_CDDIV0		(0x400)
 #define CPG_CDDIV1		(0x404)
 #define CPG_CDDIV2		(0x408)
 #define CSDIV0_DIVCTL2	DDIV_PACK(CPG_CSDIV0, 8, 2, CSDIV_NO_MON)
 #define CSDIV0_DIVCTL3	DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
 #define CSDIV1_DIVCTL2	DDIV_PACK(CPG_CSDIV1, 8, 4, CSDIV_NO_MON)
+#define CSDIV1_DIVCTL3	DDIV_PACK(CPG_CSDIV1, 12, 4, CSDIV_NO_MON)
 #define SSEL0_SELCTL2	SMUX_PACK(CPG_SSEL0, 8, 1)
 #define SSEL0_SELCTL3	SMUX_PACK(CPG_SSEL0, 12, 1)
 #define SSEL1_SELCTL1	SMUX_PACK(CPG_SSEL1, 4, 1)
 #define SSEL1_SELCTL2	SMUX_PACK(CPG_SSEL1, 8, 1)
 #define SSEL1_SELCTL3	SMUX_PACK(CPG_SSEL1, 12, 1)
+#define SSEL3_SELCTL0	SMUX_PACK(CPG_SSEL3, 0, 1)
+#define SSEL3_SELCTL1	SMUX_PACK(CPG_SSEL3, 4, 1)
 #define BUS_MSTOP_IDX_MASK	GENMASK(31, 16)
 #define BUS_MSTOP_BITS_MASK	GENMASK(15, 0)
 	CLK_TYPE_SMUX,		/* Static Mux */
 	CLK_TYPE_PLLDSI,	/* PLLDSI */
 	CLK_TYPE_PLLDSI_DIV,	/* PLLDSI divider */
+	CLK_TYPE_PLLDSI_SMUX,	/* PLLDSI Static Mux */
 };
 #define DEF_TYPE(_name, _id, _type...) \
 		 .dtable = _dtable, \
 		 .parent = _parent, \
 		 .flag = CLK_SET_RATE_PARENT)
+#define DEF_PLLDSI_SMUX(_name, _id, _smux_packed, _parent_names) \
+	DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI_SMUX, \
+		 .cfg.smux = _smux_packed, \
+		 .parent_names = _parent_names, \
+		 .num_parents = ARRAY_SIZE(_parent_names), \
+		 .flag = CLK_SET_RATE_PARENT, \
+		 .mux_flags = CLK_MUX_HIWORD_MASK)
 /**
  * struct rzv2h_mod_clk - Module Clocks definitions

drivers/clk/socfpga/clk-agilex.c+2−0

 	   0, 0x3C, 0, 0, 0},
 	{ AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
 	  0, 0x40, 0, 0, 0},
+	{ AGILEX_L3_MAIN_FREE_CLK, "l3_main_free_clk", "noc_free_clk", NULL,
+	  1, 0, 0, 1, 0, 0},
 	{ AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
 	  0, 4, 0x30, 1},
 	{ AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),

include/dt-bindings/clock/canaan,k230-clk.h+220−0

@@ -0,0 +1,220 @@
	1	/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
	2	/*
	3	* Kendryte Canaan K230 Clock Drivers
	4	*
	5	* Author: Xukai Wang <kingxukai@zohomail.com>
	6	*/
	7
	8	#ifndef __DT_BINDINGS_CANAAN_K230_CLOCK_H__
	9	#define __DT_BINDINGS_CANAAN_K230_CLOCK_H__
	10
	11	#define K230_CPU0_SRC_GATE 0
	12	#define K230_CPU0_PLIC_GATE 1
	13	#define K230_CPU0_NOC_DDRCP4_GATE 2
	14	#define K230_CPU0_APB_GATE 3
	15	#define K230_CPU0_SRC_RATE 4
	16	#define K230_CPU0_AXI_RATE 5
	17	#define K230_CPU0_PLIC_RATE 6
	18	#define K230_CPU0_APB_RATE 7
	19	#define K230_HS_SSI0_MUX 8
	20	#define K230_HS_USB_REF_MUX 9
	21	#define K230_HS_HCLK_HIGH_GATE 10
	22	#define K230_HS_HCLK_GATE 11
	23	#define K230_HS_SD0_AHB_GATE 12
	24	#define K230_HS_SD1_AHB_GATE 13
	25	#define K230_HS_SSI1_AHB_GATE 14
	26	#define K230_HS_SSI2_AHB_GATE 15
	27	#define K230_HS_USB0_AHB_GATE 16
	28	#define K230_HS_USB1_AHB_GATE 17
	29	#define K230_HS_SSI0_AXI_GATE 18
	30	#define K230_HS_SSI1_GATE 19
	31	#define K230_HS_SSI2_GATE 20
	32	#define K230_HS_QSPI_AXI_SRC_GATE 21
	33	#define K230_HS_SSI1_AXI_GATE 22
	34	#define K230_HS_SSI2_AXI_GATE 23
	35	#define K230_HS_SD_CARD_SRC_GATE 24
	36	#define K230_HS_SD0_CARD_GATE 25
	37	#define K230_HS_SD1_CARD_GATE 26
	38	#define K230_HS_SD_AXI_SRC_GATE 27
	39	#define K230_HS_SD0_AXI_GATE 28
	40	#define K230_HS_SD1_AXI_GATE 29
	41	#define K230_HS_SD0_BASE_GATE 30
	42	#define K230_HS_SD1_BASE_GATE 31
	43	#define K230_HS_SSI0_GATE 32
	44	#define K230_HS_SD_TIMER_SRC_GATE 33
	45	#define K230_HS_SD0_TIMER_GATE 34
	46	#define K230_HS_SD1_TIMER_GATE 35
	47	#define K230_HS_USB0_REF_GATE 36
	48	#define K230_HS_USB1_REF_GATE 37
	49	#define K230_HS_HCLK_HIGH_RATE 38
	50	#define K230_HS_HCLK_RATE 39
	51	#define K230_HS_SSI0_AXI_RATE 40
	52	#define K230_HS_SSI1_RATE 41
	53	#define K230_HS_SSI2_RATE 42
	54	#define K230_HS_QSPI_AXI_SRC_RATE 43
	55	#define K230_HS_SD_CARD_SRC_RATE 44
	56	#define K230_HS_SD_AXI_SRC_RATE 45
	57	#define K230_HS_USB_REF_50M_RATE 46
	58	#define K230_HS_SD_TIMER_SRC_RATE 47
	59	#define K230_TIMER0_MUX 48
	60	#define K230_TIMER1_MUX 49
	61	#define K230_TIMER2_MUX 50
	62	#define K230_TIMER3_MUX 51
	63	#define K230_TIMER4_MUX 52
	64	#define K230_TIMER5_MUX 53
	65	#define K230_SHRM_SRAM_MUX 54
	66	#define K230_DDRC_SRC_MUX 55
	67	#define K230_AI_SRC_MUX 56
	68	#define K230_CAMERA0_MUX 57
	69	#define K230_CAMERA1_MUX 58
	70	#define K230_CAMERA2_MUX 59
	71	#define K230_CPU1_SRC_MUX 60
	72	#define K230_CPU1_SRC_GATE 61
	73	#define K230_CPU1_PLIC_GATE 62
	74	#define K230_CPU1_APB_GATE 63
	75	#define K230_CPU1_SRC_RATE 64
	76	#define K230_CPU1_AXI_RATE 65
	77	#define K230_CPU1_PLIC_RATE 66
	78	#define K230_PMU_APB_GATE 67
	79	#define K230_LS_APB_SRC_GATE 68
	80	#define K230_LS_UART0_APB_GATE 69
	81	#define K230_LS_UART1_APB_GATE 70
	82	#define K230_LS_UART2_APB_GATE 71
	83	#define K230_LS_UART3_APB_GATE 72
	84	#define K230_LS_UART4_APB_GATE 73
	85	#define K230_LS_I2C0_APB_GATE 74
	86	#define K230_LS_I2C1_APB_GATE 75
	87	#define K230_LS_I2C2_APB_GATE 76
	88	#define K230_LS_I2C3_APB_GATE 77
	89	#define K230_LS_I2C4_APB_GATE 78
	90	#define K230_LS_GPIO_APB_GATE 79
	91	#define K230_LS_PWM_APB_GATE 80
	92	#define K230_LS_JAMLINK0_APB_GATE 81
	93	#define K230_LS_JAMLINK1_APB_GATE 82
	94	#define K230_LS_JAMLINK2_APB_GATE 83
	95	#define K230_LS_JAMLINK3_APB_GATE 84
	96	#define K230_LS_AUDIO_APB_GATE 85
	97	#define K230_LS_ADC_APB_GATE 86
	98	#define K230_LS_CODEC_APB_GATE 87
	99	#define K230_LS_I2C0_GATE 88
	100	#define K230_LS_I2C1_GATE 89
	101	#define K230_LS_I2C2_GATE 90
	102	#define K230_LS_I2C3_GATE 91
	103	#define K230_LS_I2C4_GATE 92
	104	#define K230_LS_CODEC_ADC_GATE 93
	105	#define K230_LS_CODEC_DAC_GATE 94
	106	#define K230_LS_AUDIO_DEV_GATE 95
	107	#define K230_LS_PDM_GATE 96
	108	#define K230_LS_ADC_GATE 97
	109	#define K230_LS_UART0_GATE 98
	110	#define K230_LS_UART1_GATE 99
	111	#define K230_LS_UART2_GATE 100
	112	#define K230_LS_UART3_GATE 101
	113	#define K230_LS_UART4_GATE 102
	114	#define K230_LS_JAMLINK0CO_GATE 103
	115	#define K230_LS_JAMLINK1CO_GATE 104
	116	#define K230_LS_JAMLINK2CO_GATE 105
	117	#define K230_LS_JAMLINK3CO_GATE 106
	118	#define K230_LS_GPIO_DEBOUNCE_GATE 107
	119	#define K230_SYSCTL_WDT0_APB_GATE 108
	120	#define K230_SYSCTL_WDT1_APB_GATE 109
	121	#define K230_SYSCTL_TIMER_APB_GATE 110
	122	#define K230_SYSCTL_IOMUX_APB_GATE 111
	123	#define K230_SYSCTL_MAILBOX_APB_GATE 112
	124	#define K230_SYSCTL_HDI_GATE 113
	125	#define K230_SYSCTL_TIME_STAMP_GATE 114
	126	#define K230_SYSCTL_WDT0_GATE 115
	127	#define K230_SYSCTL_WDT1_GATE 116
	128	#define K230_TIMER0_GATE 117
	129	#define K230_TIMER1_GATE 118
	130	#define K230_TIMER2_GATE 119
	131	#define K230_TIMER3_GATE 120
	132	#define K230_TIMER4_GATE 121
	133	#define K230_TIMER5_GATE 122
	134	#define K230_SHRM_APB_GATE 123
	135	#define K230_SHRM_AXI_GATE 124
	136	#define K230_SHRM_AXI_SLAVE_GATE 125
	137	#define K230_SHRM_NONAI2D_AXI_GATE 126
	138	#define K230_SHRM_SRAM_GATE 127
	139	#define K230_SHRM_DECOMPRESS_AXI_GATE 128
	140	#define K230_SHRM_SDMA_AXI_GATE 129
	141	#define K230_SHRM_PDMA_AXI_GATE 130
	142	#define K230_DDRC_SRC_GATE 131
	143	#define K230_DDRC_BYPASS_GATE 132
	144	#define K230_DDRC_APB_GATE 133
	145	#define K230_DISPLAY_AHB_GATE 134
	146	#define K230_DISPLAY_AXI_GATE 135
	147	#define K230_DISPLAY_GPU_GATE 136
	148	#define K230_DISPLAY_DPIP_GATE 137
	149	#define K230_DISPLAY_CFG_GATE 138
	150	#define K230_DISPLAY_REF_GATE 139
	151	#define K230_USB_480M_GATE 140
	152	#define K230_USB_100M_GATE 141
	153	#define K230_DPHY_DFT_GATE 142
	154	#define K230_SPI2AXI_GATE 143
	155	#define K230_AI_SRC_GATE 144
	156	#define K230_AI_AXI_GATE 145
	157	#define K230_AI_SRC_RATE 146
	158	#define K230_CAMERA0_GATE 147
	159	#define K230_CAMERA1_GATE 148
	160	#define K230_CAMERA2_GATE 149
	161	#define K230_LS_APB_SRC_RATE 150
	162	#define K230_LS_I2C0_RATE 151
	163	#define K230_LS_I2C1_RATE 152
	164	#define K230_LS_I2C2_RATE 153
	165	#define K230_LS_I2C3_RATE 154
	166	#define K230_LS_I2C4_RATE 155
	167	#define K230_LS_CODEC_ADC_RATE 156
	168	#define K230_LS_CODEC_DAC_RATE 157
	169	#define K230_LS_AUDIO_DEV_RATE 158
	170	#define K230_LS_PDM_RATE 159
	171	#define K230_LS_ADC_RATE 160
	172	#define K230_LS_UART0_RATE 161
	173	#define K230_LS_UART1_RATE 162
	174	#define K230_LS_UART2_RATE 163
	175	#define K230_LS_UART3_RATE 164
	176	#define K230_LS_UART4_RATE 165
	177	#define K230_LS_JAMLINKCO_SRC_RATE 166
	178	#define K230_LS_GPIO_DEBOUNCE_RATE 167
	179	#define K230_SYSCTL_HDI_RATE 168
	180	#define K230_SYSCTL_TIME_STAMP_RATE 169
	181	#define K230_SYSCTL_TEMP_SENSOR_RATE 170
	182	#define K230_SYSCTL_WDT0_RATE 171
	183	#define K230_SYSCTL_WDT1_RATE 172
	184	#define K230_TIMER0_SRC_RATE 173
	185	#define K230_TIMER1_SRC_RATE 174
	186	#define K230_TIMER2_SRC_RATE 175
	187	#define K230_TIMER3_SRC_RATE 176
	188	#define K230_TIMER4_SRC_RATE 177
	189	#define K230_TIMER5_SRC_RATE 178
	190	#define K230_SHRM_APB_RATE 179
	191	#define K230_DDRC_SRC_RATE 180
	192	#define K230_DDRC_APB_RATE 181
	193	#define K230_DISPLAY_AHB_RATE 182
	194	#define K230_DISPLAY_CLKEXT_RATE 183
	195	#define K230_DISPLAY_GPU_RATE 184
	196	#define K230_DISPLAY_DPIP_RATE 185
	197	#define K230_DISPLAY_CFG_RATE 186
	198	#define K230_VPU_SRC_GATE 187
	199	#define K230_VPU_AXI_GATE 188
	200	#define K230_VPU_DDRCP2_GATE 189
	201	#define K230_VPU_CFG_GATE 190
	202	#define K230_VPU_SRC_RATE 191
	203	#define K230_VPU_AXI_SRC_RATE 192
	204	#define K230_VPU_CFG_RATE 193
	205	#define K230_SEC_APB_GATE 194
	206	#define K230_SEC_FIX_GATE 195
	207	#define K230_SEC_AXI_GATE 196
	208	#define K230_SEC_APB_RATE 197
	209	#define K230_SEC_FIX_RATE 198
	210	#define K230_SEC_AXI_RATE 199
	211	#define K230_USB_480M_RATE 200
	212	#define K230_USB_100M_RATE 201
	213	#define K230_DPHY_DFT_RATE 202
	214	#define K230_SPI2AXI_RATE 203
	215	#define K230_CAMERA0_RATE 204
	216	#define K230_CAMERA1_RATE 205
	217	#define K230_CAMERA2_RATE 206
	218	#define K230_SHRM_SRAM_DIV2 207
	219
	220	#endif /* __DT_BINDINGS_CANAAN_K230_CLOCK_H__ */

include/dt-bindings/clock/r8a73a4-clock.h+2−0

@@ -23,6 +23,8 @@ · 22 unmodified lines
23	#define R8A73A4_CLK_ZX 13	23	#define R8A73A4_CLK_ZX 13
24	#define R8A73A4_CLK_ZS 14	24	#define R8A73A4_CLK_ZS 14
25	#define R8A73A4_CLK_HP 15	25	#define R8A73A4_CLK_HP 15
		26	#define R8A73A4_CLK_ZTR 16
		27	#define R8A73A4_CLK_ZT 17
26		28
27	/* MSTP1 */	29	/* MSTP1 */
28	#define R8A73A4_CLK_TMU0 25	30	#define R8A73A4_CLK_TMU0 25

include/dt-bindings/clock/r8a7740-clock.h+2−0

@@ -24,6 +24,8 @@ · 23 unmodified lines
24	#define R8A7740_CLK_ZB 14	24	#define R8A7740_CLK_ZB 14
25	#define R8A7740_CLK_M3 15	25	#define R8A7740_CLK_M3 15
26	#define R8A7740_CLK_CP 16	26	#define R8A7740_CLK_CP 16
		27	#define R8A7740_CLK_ZTR 17
		28	#define R8A7740_CLK_ZT 18
27		29
28	/* MSTP1 */	30	/* MSTP1 */
29	#define R8A7740_CLK_CEU21 28	31	#define R8A7740_CLK_CEU21 28

include/linux/clk/renesas.h+20−0

@@ -164,6 +164,26 @@ struct rzv2h_pll_div_pars { · 163 unmodified lines
164	.k = { .min = -32768, .max = 32767 }, \	164	.k = { .min = -32768, .max = 32767 }, \
165	} \	165	} \
166		166
		167	#define RZG3E_CPG_PLL_DSI0_LIMITS(name) \
		168	static const struct rzv2h_pll_limits (name) = { \
		169	.fout = { .min = 25 * MEGA, .max = 1218 * MEGA }, \
		170	.fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \
		171	.m = { .min = 64, .max = 533 }, \
		172	.p = { .min = 1, .max = 4 }, \
		173	.s = { .min = 0, .max = 6 }, \
		174	.k = { .min = -32768, .max = 32767 }, \
		175	} \
		176
		177	#define RZG3E_CPG_PLL_DSI1_LIMITS(name) \
		178	static const struct rzv2h_pll_limits (name) = { \
		179	.fout = { .min = 25 * MEGA, .max = 609 * MEGA }, \
		180	.fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \
		181	.m = { .min = 64, .max = 533 }, \
		182	.p = { .min = 1, .max = 4 }, \
		183	.s = { .min = 0, .max = 6 }, \
		184	.k = { .min = -32768, .max = 32767 }, \
		185	} \
		186
167	#ifdef CONFIG_CLK_RZV2H	187	#ifdef CONFIG_CLK_RZV2H
168	bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,	188	bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
169	struct rzv2h_pll_pars *pars, u64 freq_millihz);	189	struct rzv2h_pll_pars *pars, u64 freq_millihz);