History

Merge tag 'mtd/for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull MTD updates from Miquel Raynal: "MTD core changes: - Fix issue where write_cached_data() fails but write() still returns success - maps: sa1100-flash: Replace zero-length array with flexible-array member - phram: Fix a double free issue in error path - Convert fallthrough comments into statements - MAINTAINERS: Add the IRC channel to the MTD related subsystems Raw NAND core changes: - Add support for manufacturer specific suspend/resume operation - Add support for manufacturer specific lock/unlock operation - Replace zero-length array with flexible-array member - Fix a typo ("manufecturer") - Ensure nand_soft_waitrdy wait period is enough Raw NAND controller driver changes: - Brcmnand: * Add support for flash-edu for dma transfers (+ bindings) - Cadence: * Reinit completion before executing a new command * Change bad block marker size * Fix the calculation of the avaialble OOB size * Get meta data size from registers - Qualcom: * Use dma_request_chan() instead dma_request_slave_channel() * Release resources on failure within qcom_nandc_alloc() - Allwinner: * Use dma_request_chan() instead dma_request_slave_channel() - Marvell: * Use dma_request_chan() instead dma_request_slave_channel() * Release DMA channel on error - Freescale: * Use dma_request_chan() instead dma_request_slave_channel() - Macronix: * Add support for Macronix NAND randomizer (+ bindings) - Ams-delta: * Rename structures and functions to gpio_nand* * Make the driver custom I/O ready * Drop useless local variable * Support custom driver initialisation * Add module device tables * Handle more GPIO pins as optional * Make read pulses optional * Don't hardcode read/write pulse widths * Push inversion handling to gpiolib * Enable OF partition info support * Drop board specific partition info * Use struct gpio_nand_platdata * Write protect device during probe - Ingenic: * Use devm_platform_ioremap_resource() * Add dependency on MIPS || COMPILE_TEST - Denali: * Deassert write protect pin - ST: * Use dma_request_chan() instead dma_request_slave_channel() Raw NAND chip driver changes: - Toshiba: * Support reading the number of bitflips for BENAND (Built-in ECC NAND) - Macronix: * Add support for deep power down mode * Add support for block protection SPI-NAND core changes: - Do not erase the block before writing a bad block marker - Explicitly use MTD_OPS_RAW to write the bad block marker to OOB - Stop using spinand->oobbuf for buffering bad block markers - Rework detect procedure for different READ_ID operation SPI-NAND driver changes: - Toshiba: * Support for new Kioxia Serial NAND * Rename function name to change suffix and prefix (8Gbit) * Add comment about Kioxia ID - Micron: * Add new Micron SPI NAND devices with multiple dies * Add M70A series Micron SPI NAND devices * identify SPI NAND device with Continuous Read mode * Add new Micron SPI NAND devices * Describe the SPI NAND device MT29F2G01ABAGD * Generalize the OOB layout structure and function names SPI NOR core changes: - Move all the manufacturer specific quirks/code out of the core, to make the core logic more readable and thus ease maintenance. - Move the SFDP logic out of the core, it provides a better separation between the SFDP parsing and core logic. - Trim what is exposed in spi-nor.h. The SPI NOR controllers drivers must not be able to use structures that are meant just for the SPI NOR core. - Use the spi-mem direct mapping API to let advanced controllers optimize the read/write operations when they support direct mapping. - Add generic formula for the Status Register block protection handling. It fixes some long standing locking limitations and eases the addition of the 4bit block protection support. - Add block protection support for flashes with 4 block protection bits in the Status Register. SPI NOR controller drivers changes: - The mtk-quadspi driver is replaced by the new spi-mem spi-mtk-nor driver. - Merge tag 'mtk-mtd-spi-move' into spi-nor/next to avoid conflicts. HyperBus changes: - Print error msg when compatible is wrong or missing - Move mapping of direct access window from core to individual drivers" * tag 'mtd/for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (103 commits) mtd: Convert fallthrough comments into statements mtd: rawnand: toshiba: Support reading the number of bitflips for BENAND (Built-in ECC NAND) MAINTAINERS: Add the IRC channel to the MTD related subsystems mtd: Fix issue where write_cached_data() fails but write() still returns success mtd: maps: sa1100-flash: Replace zero-length array with flexible-array member mtd: phram: fix a double free issue in error path mtd: spinand: toshiba: Support for new Kioxia Serial NAND mtd: spinand: toshiba: Rename function name to change suffix and prefix (8Gbit) mtd: rawnand: macronix: Add support for deep power down mode mtd: rawnand: Add support for manufacturer specific suspend/resume operation mtd: spi-nor: Enable locking for n25q512ax3/n25q512a mtd: spi-nor: Add SR 4bit block protection support mtd: spi-nor: Add generic formula for SR block protection handling mtd: spi-nor: Set all BP bits to one when lock_len == mtd->size mtd: spi-nor: controllers: aspeed-smc: Replace zero-length array with flexible-array member mtd: spi-nor: Clear WEL bit when erase or program errors occur MAINTAINERS: update entry after SPI NOR controller move mtd: spi-nor: Trim what is exposed in spi-nor.h mtd: spi-nor: Drop the MFR definitions mtd: spi-nor: Get rid of the now empty spi_nor_ids[] table ...

Linus Torvalds committed 6 years ago

Commit e109f502 parents e964f1e 025a06c95 files · +8455 −6932Browse files

Unified · Split

95 files
  1. Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt +5 −5
  2. Documentation/devicetree/bindings/mtd/nand-macronix.txt +27 −0
  3. MAINTAINERS +7 −1
  4. arch/arm/mach-omap1/board-ams-delta.c +43 −4
  5. arch/mips/boot/dts/brcm/bcm7425.dtsi +2 −2
  6. drivers/mtd/chips/cfi_cmdset_0001.c +2 −2
  7. drivers/mtd/chips/cfi_cmdset_0002.c +2 −3
  8. drivers/mtd/chips/cfi_cmdset_0020.c +6 −11
  9. drivers/mtd/chips/cfi_util.c +6 −6
  10. drivers/mtd/devices/block2mtd.c +2 −2
  11. drivers/mtd/devices/phram.c +11 −8
  12. drivers/mtd/hyperbus/hbmc-am654.c +12 −0
  13. drivers/mtd/hyperbus/hyperbus-core.c +3 −12
  14. drivers/mtd/inftlmount.c +1 −1
  15. drivers/mtd/lpddr/lpddr_cmds.c +1 −3
  16. drivers/mtd/maps/sa1100-flash.c +2 −3
  17. drivers/mtd/mtdblock.c +3 −2
  18. drivers/mtd/mtdchar.c +7 −5
  19. drivers/mtd/mtdcore.c +179 −71
  20. drivers/mtd/mtdpart.c +177 −518
  21. drivers/mtd/nand/onenand/onenand_base.c +1 −1
  22. drivers/mtd/nand/raw/ams-delta.c +155 −82
  23. drivers/mtd/nand/raw/brcmnand/brcmnand.c +287 −6
  24. drivers/mtd/nand/raw/cadence-nand-controller.c +20 −14
  25. drivers/mtd/nand/raw/denali.c +1 −0
  26. drivers/mtd/nand/raw/denali.h +1 −1
  27. drivers/mtd/nand/raw/diskonchip.c +2 −2
  28. drivers/mtd/nand/raw/fsl_elbc_nand.c +1 −2
  29. drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c +11 −10
  30. drivers/mtd/nand/raw/ingenic/Kconfig +1 −0
  31. drivers/mtd/nand/raw/ingenic/ingenic_ecc.c +1 −3
  32. drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c +1 −1
  33. drivers/mtd/nand/raw/ingenic/jz4725b_bch.c +2 −2
  34. drivers/mtd/nand/raw/ingenic/jz4780_bch.c +2 −2
  35. drivers/mtd/nand/raw/internals.h +1 −0
  36. drivers/mtd/nand/raw/marvell_nand.c +28 −12
  37. drivers/mtd/nand/raw/meson_nand.c +1 −1
  38. drivers/mtd/nand/raw/mtk_nand.c +1 −1
  39. drivers/mtd/nand/raw/nand_base.c +58 −13
  40. drivers/mtd/nand/raw/nand_hynix.c +1 −1
  41. drivers/mtd/nand/raw/nand_legacy.c +2 −4
  42. drivers/mtd/nand/raw/nand_macronix.c +227 −0
  43. drivers/mtd/nand/raw/nand_toshiba.c +56 −2
  44. drivers/mtd/nand/raw/nandsim.c +2 −2
  45. drivers/mtd/nand/raw/omap_elm.c +4 −4
  46. drivers/mtd/nand/raw/qcom_nandc.c +64 −41
  47. drivers/mtd/nand/raw/stm32_fmc2_nand.c +37 −7
  48. drivers/mtd/nand/raw/sunxi_nand.c +11 −6
  49. drivers/mtd/nand/spi/core.c +71 −33
  50. drivers/mtd/nand/spi/gigadevice.c +12 −33
  51. drivers/mtd/nand/spi/macronix.c +6 −24
  52. drivers/mtd/nand/spi/micron.c +142 −30
  53. drivers/mtd/nand/spi/paragon.c +6 −22
  54. drivers/mtd/nand/spi/toshiba.c +145 −63
  55. drivers/mtd/nand/spi/winbond.c +6 −28
  56. drivers/mtd/spi-nor/Kconfig +1 −74
  57. drivers/mtd/spi-nor/Makefile +18 −7
  58. drivers/mtd/spi-nor/atmel.c +46 −0
  59. drivers/mtd/spi-nor/catalyst.c +29 −0
  60. drivers/mtd/spi-nor/controllers/Kconfig +75 −0
  61. drivers/mtd/spi-nor/controllers/Makefile +8 −0
  62. drivers/mtd/spi-nor/controllers/aspeed-smc.c +2 −2
  63. drivers/mtd/spi-nor/controllers/cadence-quadspi.c +0 −0
  64. drivers/mtd/spi-nor/controllers/hisi-sfc.c +0 −0
  65. drivers/mtd/spi-nor/controllers/intel-spi-pci.c +0 −0
  66. drivers/mtd/spi-nor/controllers/intel-spi-platform.c +0 −0
  67. drivers/mtd/spi-nor/controllers/intel-spi.c +0 −0
  68. drivers/mtd/spi-nor/controllers/intel-spi.h +0 −0
  69. drivers/mtd/spi-nor/controllers/nxp-spifi.c +0 −0
  70. drivers/mtd/spi-nor/core.c +3466 −0
  71. drivers/mtd/spi-nor/core.h +441 −0
  72. drivers/mtd/spi-nor/eon.c +34 −0
  73. drivers/mtd/spi-nor/esmt.c +25 −0
  74. drivers/mtd/spi-nor/everspin.c +27 −0
  75. drivers/mtd/spi-nor/fujitsu.c +20 −0
  76. drivers/mtd/spi-nor/gigadevice.c +59 −0
  77. drivers/mtd/spi-nor/intel.c +32 −0
  78. drivers/mtd/spi-nor/issi.c +83 −0
  79. drivers/mtd/spi-nor/macronix.c +98 −0
  80. drivers/mtd/spi-nor/micron-st.c +157 −0
  81. drivers/mtd/spi-nor/sfdp.c +1204 −0
  82. drivers/mtd/spi-nor/sfdp.h +98 −0
  83. drivers/mtd/spi-nor/spansion.c +95 −0
  84. drivers/mtd/spi-nor/spi-nor.c +0 −5434
  85. drivers/mtd/spi-nor/sst.c +151 −0
  86. drivers/mtd/spi-nor/winbond.c +112 −0
  87. drivers/mtd/spi-nor/xilinx.c +94 −0
  88. drivers/mtd/spi-nor/xmc.c +23 −0
  89. drivers/mtd/ubi/attach.c +1 −1
  90. drivers/mtd/ubi/build.c +2 −2
  91. include/linux/mtd/mtd.h +115 −10
  92. include/linux/mtd/partitions.h +0 −1
  93. include/linux/mtd/rawnand.h +10 −1
  94. include/linux/mtd/spi-nor.h +19 −266
  95. include/linux/mtd/spinand.h +45 −22
Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt+5−5
@@ -35,11 +35,11 @@ Required properties: · 34 unmodified lines
3535 (optional) NAND flash cache range (if at non-standard offset)
3636 - reg-names : a list of the names corresponding to the previous register
3737 ranges. Should contain "nand" and (optionally)
38− "flash-dma" and/or "nand-cache".
39−- interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available)
40− FLASH_DMA_DONE
41−- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done", if broken out as
42− individual interrupts.
38+ "flash-dma" or "flash-edu" and/or "nand-cache".
39+- interrupts : The NAND CTLRDY interrupt, (if Flash DMA is available)
40+ FLASH_DMA_DONE and if EDU is avaialble and used FLASH_EDU_DONE
41+- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done" or "flash_edu_done",
42+ if broken out as individual interrupts.
4343 May be "nand", if the SoC has the individual NAND
4444 interrupts multiplexed behind another custom piece of
4545 hardware
Documentation/devicetree/bindings/mtd/nand-macronix.txt+27−0
@@ -0,0 +1,27 @@
1+Macronix NANDs Device Tree Bindings
2+-----------------------------------
3+
4+Macronix NANDs support randomizer operation for scrambling user data,
5+which can be enabled with a SET_FEATURE. The penalty when using the
6+randomizer are subpage accesses prohibited and more time period needed
7+for program operation, i.e., tPROG 300us to 340us (randomizer enabled).
8+Enabling the randomizer is a one time persistent and non reversible
9+operation.
10+
11+For more high-reliability concern, if subpage write is not available
12+with hardware ECC and not enabled at UBI level, then enabling the
13+randomizer is recommended by default by adding a new specific property
14+in children nodes.
15+
16+Required NAND chip properties in children mode:
17+- randomizer enable: should be "mxic,enable-randomizer-otp"
18+
19+Example:
20+
21+ nand: nand-controller@unit-address {
22+
23+ nand@0 {
24+ reg = <0>;
25+ mxic,enable-randomizer-otp;
26+ };
27+ };
MAINTAINERS+7−1
@@ -1945,7 +1945,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-lpc2k.txt · 1944 unmodified lines
19451945 F: arch/arm/boot/dts/lpc43*
19461946 F: drivers/i2c/busses/i2c-lpc2k.c
19471947 F: drivers/memory/pl172.c
1948−F: drivers/mtd/spi-nor/nxp-spifi.c
1948+F: drivers/mtd/spi-nor/controllers/nxp-spifi.c
19491949 F: drivers/rtc/rtc-lpc24xx.c
19501950 N: lpc18xx
19511951
@@ -7851,6 +7851,10 @@ F: Documentation/ABI/testing/debugfs-hyperv · 5899 unmodified lines
78517851
78527852 HYPERBUS SUPPORT
78537853 M: Vignesh Raghavendra <vigneshr@ti.com>
7854+L: linux-mtd@lists.infradead.org
7855+Q: http://patchwork.ozlabs.org/project/linux-mtd/list/
7856+T: git git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git cfi/next
7857+C: irc://irc.oftc.net/mtd
78547858 S: Supported
78557859 F: drivers/mtd/hyperbus/
78567860 F: include/linux/mtd/hyperbus.h
@@ -11552,6 +11556,7 @@ L: linux-mtd@lists.infradead.org · 3695 unmodified lines
1155211556 W: http://www.linux-mtd.infradead.org/
1155311557 Q: http://patchwork.ozlabs.org/project/linux-mtd/list/
1155411558 T: git git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next
11559+C: irc://irc.oftc.net/mtd
1155511560 S: Maintained
1155611561 F: drivers/mtd/nand/
1155711562 F: include/linux/mtd/*nand*.h
@@ -15835,6 +15840,7 @@ L: linux-mtd@lists.infradead.org · 4277 unmodified lines
1583515840 W: http://www.linux-mtd.infradead.org/
1583615841 Q: http://patchwork.ozlabs.org/project/linux-mtd/list/
1583715842 T: git git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git spi-nor/next
15843+C: irc://irc.oftc.net/mtd
1583815844 S: Maintained
1583915845 F: drivers/mtd/spi-nor/
1584015846 F: include/linux/mtd/spi-nor.h
arch/arm/mach-omap1/board-ams-delta.c+43−4
@@ -17,6 +17,8 @@ · 16 unmodified lines
1717 #include <linux/input.h>
1818 #include <linux/interrupt.h>
1919 #include <linux/leds.h>
20+#include <linux/mtd/nand-gpio.h>
21+#include <linux/mtd/partitions.h>
2022 #include <linux/platform_device.h>
2123 #include <linux/regulator/consumer.h>
2224 #include <linux/regulator/fixed.h>
@@ -294,9 +296,42 @@ struct modem_private_data { · 271 unmodified lines
294296
295297 static struct modem_private_data modem_priv;
296298
299+/*
300+ * Define partitions for flash device
301+ */
302+
303+static struct mtd_partition partition_info[] = {
304+ { .name = "Kernel",
305+ .offset = 0,
306+ .size = 3 * SZ_1M + SZ_512K },
307+ { .name = "u-boot",
308+ .offset = 3 * SZ_1M + SZ_512K,
309+ .size = SZ_256K },
310+ { .name = "u-boot params",
311+ .offset = 3 * SZ_1M + SZ_512K + SZ_256K,
312+ .size = SZ_256K },
313+ { .name = "Amstrad LDR",
314+ .offset = 4 * SZ_1M,
315+ .size = SZ_256K },
316+ { .name = "File system",
317+ .offset = 4 * SZ_1M + 1 * SZ_256K,
318+ .size = 27 * SZ_1M },
319+ { .name = "PBL reserved",
320+ .offset = 32 * SZ_1M - 3 * SZ_256K,
321+ .size = 3 * SZ_256K },
322+};
323+
324+static struct gpio_nand_platdata nand_platdata = {
325+ .parts = partition_info,
326+ .num_parts = ARRAY_SIZE(partition_info),
327+};
328+
297329 static struct platform_device ams_delta_nand_device = {
298330 .name = "ams-delta-nand",
299331 .id = -1,
332+ .dev = {
333+ .platform_data = &nand_platdata,
334+ },
300335 };
301336
302337 #define OMAP_GPIO_LABEL "gpio-0-15"
@@ -306,10 +341,14 @@ static struct gpiod_lookup_table ams_delta_nand_gpio_table = { · 3 unmodified lines
306341 .table = {
307342 GPIO_LOOKUP(OMAP_GPIO_LABEL, AMS_DELTA_GPIO_PIN_NAND_RB, "rdy",
308343 0),
309− GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NCE, "nce", 0),
310− GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NRE, "nre", 0),
311− GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NWP, "nwp", 0),
312− GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NWE, "nwe", 0),
344+ GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NCE, "nce",
345+ GPIO_ACTIVE_LOW),
346+ GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NRE, "nre",
347+ GPIO_ACTIVE_LOW),
348+ GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NWP, "nwp",
349+ GPIO_ACTIVE_LOW),
350+ GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NWE, "nwe",
351+ GPIO_ACTIVE_LOW),
313352 GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_ALE, "ale", 0),
314353 GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_CLE, "cle", 0),
315354 GPIO_LOOKUP_IDX(OMAP_MPUIO_LABEL, 0, "data", 0, 0),
arch/mips/boot/dts/brcm/bcm7425.dtsi+2−2
@@ -403,8 +403,8 @@ · 402 unmodified lines
403403 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
404404 #address-cells = <1>;
405405 #size-cells = <0>;
406− reg-names = "nand";
407− reg = <0x41b800 0x400>;
406+ reg-names = "nand", "flash-edu";
407+ reg = <0x41b800 0x400>, <0x41bc00 0x24>;
408408 interrupt-parent = <&hif_l2_intc>;
409409 interrupts = <24>;
410410 status = "disabled";
drivers/mtd/chips/cfi_cmdset_0001.c+2−2
@@ -834,7 +834,7 @@ static int chip_ready (struct map_info *map, struct flchip *chip, unsigned long · 833 unmodified lines
834834 /* Someone else might have been playing with it. */
835835 return -EAGAIN;
836836 }
837− /* Fall through */
837+ fallthrough;
838838 case FL_READY:
839839 case FL_CFI_QUERY:
840840 case FL_JEDEC_QUERY:
@@ -907,7 +907,7 @@ static int chip_ready (struct map_info *map, struct flchip *chip, unsigned long · 66 unmodified lines
907907 /* Only if there's no operation suspended... */
908908 if (mode == FL_READY && chip->oldstate == FL_READY)
909909 return 0;
910− /* Fall through */
910+ fallthrough;
911911 default:
912912 sleep:
913913 set_current_state(TASK_UNINTERRUPTIBLE);
drivers/mtd/chips/cfi_cmdset_0002.c+2−3
@@ -966,8 +966,7 @@ static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr · 965 unmodified lines
966966 /* Only if there's no operation suspended... */
967967 if (mode == FL_READY && chip->oldstate == FL_READY)
968968 return 0;
969− /* fall through */
970−
969+ fallthrough;
971970 default:
972971 sleep:
973972 set_current_state(TASK_UNINTERRUPTIBLE);
@@ -2935,7 +2934,7 @@ static void cfi_amdstd_sync (struct mtd_info *mtd) · 1961 unmodified lines
29352934 * as the whole point is that nobody can do anything
29362935 * with the chip now anyway.
29372936 */
2938− /* fall through */
2937+ fallthrough;
29392938 case FL_SYNCING:
29402939 mutex_unlock(&chip->mutex);
29412940 break;
drivers/mtd/chips/cfi_cmdset_0020.c+6−11
@@ -324,8 +324,7 @@ static inline int do_read_onechip(struct map_info *map, struct flchip *chip, lof · 323 unmodified lines
324324 case FL_JEDEC_QUERY:
325325 map_write(map, CMD(0x70), cmd_addr);
326326 chip->state = FL_STATUS;
327− /* Fall through */
328−
327+ fallthrough;
329328 case FL_STATUS:
330329 status = map_read(map, cmd_addr);
331330 if (map_word_andequal(map, status, status_OK, status_OK)) {
@@ -462,8 +461,7 @@ static int do_write_buffer(struct map_info *map, struct flchip *chip, · 130 unmodified lines
462461 #ifdef DEBUG_CFI_FEATURES
463462 printk("%s: 1 status[%x]\n", __func__, map_read(map, cmd_adr));
464463 #endif
465− /* Fall through */
466−
464+ fallthrough;
467465 case FL_STATUS:
468466 status = map_read(map, cmd_adr);
469467 if (map_word_andequal(map, status, status_OK, status_OK))
@@ -756,8 +754,7 @@ retry: · 286 unmodified lines
756754 case FL_READY:
757755 map_write(map, CMD(0x70), adr);
758756 chip->state = FL_STATUS;
759− /* Fall through */
760−
757+ fallthrough;
761758 case FL_STATUS:
762759 status = map_read(map, adr);
763760 if (map_word_andequal(map, status, status_OK, status_OK))
@@ -998,7 +995,7 @@ static void cfi_staa_sync (struct mtd_info *mtd) · 234 unmodified lines
998995 * as the whole point is that nobody can do anything
999996 * with the chip now anyway.
1000997 */
1001− /* Fall through */
998+ fallthrough;
1002999 case FL_SYNCING:
10031000 mutex_unlock(&chip->mutex);
10041001 break;
@@ -1054,8 +1051,7 @@ retry: · 49 unmodified lines
10541051 case FL_READY:
10551052 map_write(map, CMD(0x70), adr);
10561053 chip->state = FL_STATUS;
1057− /* Fall through */
1058−
1054+ fallthrough;
10591055 case FL_STATUS:
10601056 status = map_read(map, adr);
10611057 if (map_word_andequal(map, status, status_OK, status_OK))
@@ -1201,8 +1197,7 @@ retry: · 139 unmodified lines
12011197 case FL_READY:
12021198 map_write(map, CMD(0x70), adr);
12031199 chip->state = FL_STATUS;
1204− /* Fall through */
1205−
1200+ fallthrough;
12061201 case FL_STATUS:
12071202 status = map_read(map, adr);
12081203 if (map_word_andequal(map, status, status_OK, status_OK))
drivers/mtd/chips/cfi_util.c+6−6
@@ -109,13 +109,13 @@ map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi · 108 unmodified lines
109109 case 8:
110110 onecmd |= (onecmd << (chip_mode * 32));
111111 #endif
112− /* fall through */
112+ fallthrough;
113113 case 4:
114114 onecmd |= (onecmd << (chip_mode * 16));
115− /* fall through */
115+ fallthrough;
116116 case 2:
117117 onecmd |= (onecmd << (chip_mode * 8));
118− /* fall through */
118+ fallthrough;
119119 case 1:
120120 ;
121121 }
@@ -165,13 +165,13 @@ unsigned long cfi_merge_status(map_word val, struct map_info *map, · 43 unmodified lines
165165 case 8:
166166 res |= (onestat >> (chip_mode * 32));
167167 #endif
168− /* fall through */
168+ fallthrough;
169169 case 4:
170170 res |= (onestat >> (chip_mode * 16));
171− /* fall through */
171+ fallthrough;
172172 case 2:
173173 res |= (onestat >> (chip_mode * 8));
174− /* fall through */
174+ fallthrough;
175175 case 1:
176176 ;
177177 }
drivers/mtd/devices/block2mtd.c+2−2
@@ -329,10 +329,10 @@ static int ustrtoul(const char *cp, char **endp, unsigned int base) · 328 unmodified lines
329329 switch (**endp) {
330330 case 'G' :
331331 result *= 1024;
332− /* fall through */
332+ fallthrough;
333333 case 'M':
334334 result *= 1024;
335− /* fall through */
335+ fallthrough;
336336 case 'K':
337337 case 'k':
338338 result *= 1024;
drivers/mtd/devices/phram.c+11−8
@@ -148,10 +148,10 @@ static int parse_num64(uint64_t *num64, char *token) · 147 unmodified lines
148148 switch (token[len - 2]) {
149149 case 'G':
150150 shift += 10;
151− /* fall through */
151+ fallthrough;
152152 case 'M':
153153 shift += 10;
154− /* fall through */
154+ fallthrough;
155155 case 'k':
156156 shift += 10;
157157 token[len - 2] = 0;
@@ -243,22 +243,25 @@ static int phram_setup(const char *val) · 85 unmodified lines
243243
244244 ret = parse_num64(&start, token[1]);
245245 if (ret) {
246− kfree(name);
247246 parse_err("illegal start address\n");
247+ goto error;
248248 }
249249
250250 ret = parse_num64(&len, token[2]);
251251 if (ret) {
252− kfree(name);
253252 parse_err("illegal device length\n");
253+ goto error;
254254 }
255255
256256 ret = register_device(name, start, len);
257− if (!ret)
258− pr_info("%s device: %#llx at %#llx\n", name, len, start);
259− else
260− kfree(name);
257+ if (ret)
258+ goto error;
259+
260+ pr_info("%s device: %#llx at %#llx\n", name, len, start);
261+ return 0;
261262
263+error:
264+ kfree(name);
262265 return ret;
263266 }
264267
drivers/mtd/hyperbus/hbmc-am654.c+12−0
@@ -11,6 +11,7 @@ · 10 unmodified lines
1111 #include <linux/mtd/mtd.h>
1212 #include <linux/mux/consumer.h>
1313 #include <linux/of.h>
14+#include <linux/of_address.h>
1415 #include <linux/platform_device.h>
1516 #include <linux/pm_runtime.h>
1617 #include <linux/types.h>
@@ -57,8 +58,10 @@ static const struct hyperbus_ops am654_hbmc_ops = { · 40 unmodified lines
5758
5859 static int am654_hbmc_probe(struct platform_device *pdev)
5960 {
61+ struct device_node *np = pdev->dev.of_node;
6062 struct device *dev = &pdev->dev;
6163 struct am654_hbmc_priv *priv;
64+ struct resource res;
6265 int ret;
6366
6467 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@@ -67,6 +70,10 @@ static int am654_hbmc_probe(struct platform_device *pdev) · 2 unmodified lines
6770
6871 platform_set_drvdata(pdev, priv);
6972
73+ ret = of_address_to_resource(np, 0, &res);
74+ if (ret)
75+ return ret;
76+
7077 if (of_property_read_bool(dev->of_node, "mux-controls")) {
7178 struct mux_control *control = devm_mux_control_get(dev, NULL);
7279
@@ -88,6 +95,11 @@ static int am654_hbmc_probe(struct platform_device *pdev) · 15 unmodified lines
8895 goto disable_pm;
8996 }
9097
98+ priv->hbdev.map.size = resource_size(&res);
99+ priv->hbdev.map.virt = devm_ioremap_resource(dev, &res);
100+ if (IS_ERR(priv->hbdev.map.virt))
101+ return PTR_ERR(priv->hbdev.map.virt);
102+
91103 priv->ctlr.dev = dev;
92104 priv->ctlr.ops = &am654_hbmc_ops;
93105 priv->hbdev.ctlr = &priv->ctlr;
drivers/mtd/hyperbus/hyperbus-core.c+3−12
@@ -10,7 +10,6 @@ · 9 unmodified lines
1010 #include <linux/mtd/map.h>
1111 #include <linux/mtd/mtd.h>
1212 #include <linux/of.h>
13−#include <linux/of_address.h>
1413 #include <linux/types.h>
1514
1615 static struct hyperbus_device *map_to_hbdev(struct map_info *map)
@@ -62,7 +61,6 @@ int hyperbus_register_device(struct hyperbus_device *hbdev) · 45 unmodified lines
6261 struct hyperbus_ctlr *ctlr;
6362 struct device_node *np;
6463 struct map_info *map;
65− struct resource res;
6664 struct device *dev;
6765 int ret;
6866
@@ -73,22 +71,15 @@ int hyperbus_register_device(struct hyperbus_device *hbdev) · 4 unmodified lines
7371
7472 np = hbdev->np;
7573 ctlr = hbdev->ctlr;
76− if (!of_device_is_compatible(np, "cypress,hyperflash"))
74+ if (!of_device_is_compatible(np, "cypress,hyperflash")) {
75+ dev_err(ctlr->dev, "\"cypress,hyperflash\" compatible missing\n");
7776 return -ENODEV;
77+ }
7878
7979 hbdev->memtype = HYPERFLASH;
8080
81− ret = of_address_to_resource(np, 0, &res);
82− if (ret)
83− return ret;
84−
8581 dev = ctlr->dev;
8682 map = &hbdev->map;
87− map->size = resource_size(&res);
88− map->virt = devm_ioremap_resource(dev, &res);
89− if (IS_ERR(map->virt))
90− return PTR_ERR(map->virt);
91−
9283 map->name = dev_name(dev);
9384 map->bankwidth = 2;
9485 map->device_node = np;
drivers/mtd/inftlmount.c+1−1
@@ -130,7 +130,7 @@ static int find_boot_record(struct INFTLrecord *inftl) · 129 unmodified lines
130130 " NoOfBootImageBlocks = %d\n"
131131 " NoOfBinaryPartitions = %d\n"
132132 " NoOfBDTLPartitions = %d\n"
133− " BlockMultiplerBits = %d\n"
133+ " BlockMultiplierBits = %d\n"
134134 " FormatFlgs = %d\n"
135135 " OsakVersion = 0x%x\n"
136136 " PercentUsed = %d\n",
drivers/mtd/lpddr/lpddr_cmds.c+1−3
@@ -68,7 +68,6 @@ struct mtd_info *lpddr_cmdset(struct map_info *map) · 67 unmodified lines
6868 shared = kmalloc_array(lpddr->numchips, sizeof(struct flchip_shared),
6969 GFP_KERNEL);
7070 if (!shared) {
71− kfree(lpddr);
7271 kfree(mtd);
7372 return NULL;
7473 }
@@ -305,8 +304,7 @@ static int chip_ready(struct map_info *map, struct flchip *chip, int mode) · 230 unmodified lines
305304 /* Only if there's no operation suspended... */
306305 if (mode == FL_READY && chip->oldstate == FL_READY)
307306 return 0;
308− /* fall through */
309−
307+ fallthrough;
310308 default:
311309 sleep:
312310 set_current_state(TASK_UNINTERRUPTIBLE);
drivers/mtd/maps/sa1100-flash.c+2−3
@@ -34,7 +34,7 @@ struct sa_subdev_info { · 33 unmodified lines
3434 struct sa_info {
3535 struct mtd_info *mtd;
3636 int num_subdev;
37− struct sa_subdev_info subdev[0];
37+ struct sa_subdev_info subdev[];
3838 };
3939
4040 static DEFINE_SPINLOCK(sa1100_vpp_lock);
@@ -81,8 +81,7 @@ static int sa1100_probe_subdev(struct sa_subdev_info *subdev, struct resource *r · 40 unmodified lines
8181 default:
8282 printk(KERN_WARNING "SA1100 flash: unknown base address "
8383 "0x%08lx, assuming CS0\n", phys);
84− /* Fall through */
85−
84+ fallthrough;
8685 case SA1100_CS0_PHYS:
8786 subdev->map.bankwidth = (MSC0 & MSC_RBW) ? 2 : 4;
8887 break;
drivers/mtd/mtdblock.c+3−2
@@ -294,12 +294,13 @@ static void mtdblock_release(struct mtd_blktrans_dev *mbd) · 293 unmodified lines
294294 static int mtdblock_flush(struct mtd_blktrans_dev *dev)
295295 {
296296 struct mtdblk_dev *mtdblk = container_of(dev, struct mtdblk_dev, mbd);
297+ int ret;
297298
298299 mutex_lock(&mtdblk->cache_mutex);
299− write_cached_data(mtdblk);
300+ ret = write_cached_data(mtdblk);
300301 mutex_unlock(&mtdblk->cache_mutex);
301302 mtd_sync(dev->mtd);
302− return 0;
303+ return ret;
303304 }
304305
305306 static void mtdblock_add_mtd(struct mtd_blktrans_ops *tr, struct mtd_info *mtd)
drivers/mtd/mtdchar.c+7−5
@@ -349,6 +349,7 @@ static int mtdchar_writeoob(struct file *file, struct mtd_info *mtd, · 348 unmodified lines
349349 uint64_t start, uint32_t length, void __user *ptr,
350350 uint32_t __user *retp)
351351 {
352+ struct mtd_info *master = mtd_get_master(mtd);
352353 struct mtd_file_info *mfi = file->private_data;
353354 struct mtd_oob_ops ops = {};
354355 uint32_t retlen;
@@ -360,7 +361,7 @@ static int mtdchar_writeoob(struct file *file, struct mtd_info *mtd, · 5 unmodified lines
360361 if (length > 4096)
361362 return -EINVAL;
362363
363− if (!mtd->_write_oob)
364+ if (!master->_write_oob)
364365 return -EOPNOTSUPP;
365366
366367 ops.ooblen = length;
@@ -586,6 +587,7 @@ static int mtdchar_blkpg_ioctl(struct mtd_info *mtd, · 219 unmodified lines
586587 static int mtdchar_write_ioctl(struct mtd_info *mtd,
587588 struct mtd_write_req __user *argp)
588589 {
590+ struct mtd_info *master = mtd_get_master(mtd);
589591 struct mtd_write_req req;
590592 struct mtd_oob_ops ops = {};
591593 const void __user *usr_data, *usr_oob;
@@ -597,9 +599,8 @@ static int mtdchar_write_ioctl(struct mtd_info *mtd, · 5 unmodified lines
597599 usr_data = (const void __user *)(uintptr_t)req.usr_data;
598600 usr_oob = (const void __user *)(uintptr_t)req.usr_oob;
599601
600− if (!mtd->_write_oob)
602+ if (!master->_write_oob)
601603 return -EOPNOTSUPP;
602−
603604 ops.mode = req.mode;
604605 ops.len = (size_t)req.len;
605606 ops.ooblen = (size_t)req.ooblen;
@@ -635,6 +636,7 @@ static int mtdchar_ioctl(struct file *file, u_int cmd, u_long arg) · 29 unmodified lines
635636 {
636637 struct mtd_file_info *mfi = file->private_data;
637638 struct mtd_info *mtd = mfi->mtd;
639+ struct mtd_info *master = mtd_get_master(mtd);
638640 void __user *argp = (void __user *)arg;
639641 int ret = 0;
640642 struct mtd_info_user info;
@@ -824,7 +826,7 @@ static int mtdchar_ioctl(struct file *file, u_int cmd, u_long arg) · 183 unmodified lines
824826 {
825827 struct nand_oobinfo oi;
826828
827− if (!mtd->ooblayout)
829+ if (!master->ooblayout)
828830 return -EOPNOTSUPP;
829831
830832 ret = get_oobinfo(mtd, &oi);
@@ -918,7 +920,7 @@ static int mtdchar_ioctl(struct file *file, u_int cmd, u_long arg) · 87 unmodified lines
918920 {
919921 struct nand_ecclayout_user *usrlay;
920922
921− if (!mtd->ooblayout)
923+ if (!master->ooblayout)
922924 return -EOPNOTSUPP;
923925
924926 usrlay = kmalloc(sizeof(*usrlay), GFP_KERNEL);
drivers/mtd/mtdcore.c+179−71
@@ -456,13 +456,14 @@ static int mtd_reboot_notifier(struct notifier_block *n, unsigned long state, · 455 unmodified lines
456456 int mtd_wunit_to_pairing_info(struct mtd_info *mtd, int wunit,
457457 struct mtd_pairing_info *info)
458458 {
459− int npairs = mtd_wunit_per_eb(mtd) / mtd_pairing_groups(mtd);
459+ struct mtd_info *master = mtd_get_master(mtd);
460+ int npairs = mtd_wunit_per_eb(master) / mtd_pairing_groups(master);
460461
461462 if (wunit < 0 || wunit >= npairs)
462463 return -EINVAL;
463464
464− if (mtd->pairing && mtd->pairing->get_info)
465− return mtd->pairing->get_info(mtd, wunit, info);
465+ if (master->pairing && master->pairing->get_info)
466+ return master->pairing->get_info(master, wunit, info);
466467
467468 info->group = 0;
468469 info->pair = wunit;
@@ -498,15 +499,16 @@ EXPORT_SYMBOL_GPL(mtd_wunit_to_pairing_info); · 29 unmodified lines
498499 int mtd_pairing_info_to_wunit(struct mtd_info *mtd,
499500 const struct mtd_pairing_info *info)
500501 {
501− int ngroups = mtd_pairing_groups(mtd);
502− int npairs = mtd_wunit_per_eb(mtd) / ngroups;
502+ struct mtd_info *master = mtd_get_master(mtd);
503+ int ngroups = mtd_pairing_groups(master);
504+ int npairs = mtd_wunit_per_eb(master) / ngroups;
503505
504506 if (!info || info->pair < 0 || info->pair >= npairs ||
505507 info->group < 0 || info->group >= ngroups)
506508 return -EINVAL;
507509
508− if (mtd->pairing && mtd->pairing->get_wunit)
509− return mtd->pairing->get_wunit(mtd, info);
510+ if (master->pairing && master->pairing->get_wunit)
511+ return mtd->pairing->get_wunit(master, info);
510512
511513 return info->pair;
512514 }
@@ -524,10 +526,12 @@ EXPORT_SYMBOL_GPL(mtd_pairing_info_to_wunit); · 11 unmodified lines
524526 */
525527 int mtd_pairing_groups(struct mtd_info *mtd)
526528 {
527− if (!mtd->pairing || !mtd->pairing->ngroups)
529+ struct mtd_info *master = mtd_get_master(mtd);
530+
531+ if (!master->pairing || !master->pairing->ngroups)
528532 return 1;
529533
530− return mtd->pairing->ngroups;
534+ return master->pairing->ngroups;
531535 }
532536 EXPORT_SYMBOL_GPL(mtd_pairing_groups);
533537
@@ -587,6 +591,7 @@ static int mtd_nvmem_add(struct mtd_info *mtd) · 53 unmodified lines
587591
588592 int add_mtd_device(struct mtd_info *mtd)
589593 {
594+ struct mtd_info *master = mtd_get_master(mtd);
590595 struct mtd_notifier *not;
591596 int i, error;
592597
@@ -608,7 +613,7 @@ int add_mtd_device(struct mtd_info *mtd) · 15 unmodified lines
608613 (mtd->_read && mtd->_read_oob)))
609614 return -EINVAL;
610615
611− if (WARN_ON((!mtd->erasesize || !mtd->_erase) &&
616+ if (WARN_ON((!mtd->erasesize || !master->_erase) &&
612617 !(mtd->flags & MTD_NO_ERASE)))
613618 return -EINVAL;
614619
@@ -765,7 +770,8 @@ static void mtd_set_dev_defaults(struct mtd_info *mtd) · 150 unmodified lines
765770 pr_debug("mtd device won't show a device symlink in sysfs\n");
766771 }
767772
768− mtd->orig_flags = mtd->flags;
773+ INIT_LIST_HEAD(&mtd->partitions);
774+ mutex_init(&mtd->master.partitions_lock);
769775 }
770776
771777 /**
@@ -971,20 +977,26 @@ EXPORT_SYMBOL_GPL(get_mtd_device); · 199 unmodified lines
971977
972978 int __get_mtd_device(struct mtd_info *mtd)
973979 {
980+ struct mtd_info *master = mtd_get_master(mtd);
974981 int err;
975982
976− if (!try_module_get(mtd->owner))
983+ if (!try_module_get(master->owner))
977984 return -ENODEV;
978985
979− if (mtd->_get_device) {
980− err = mtd->_get_device(mtd);
986+ if (master->_get_device) {
987+ err = master->_get_device(mtd);
981988
982989 if (err) {
983− module_put(mtd->owner);
990+ module_put(master->owner);
984991 return err;
985992 }
986993 }
987− mtd->usecount++;
994+
995+ while (mtd->parent) {
996+ mtd->usecount++;
997+ mtd = mtd->parent;
998+ }
999+
9881000 return 0;
9891001 }
9901002 EXPORT_SYMBOL_GPL(__get_mtd_device);
@@ -1038,13 +1050,18 @@ EXPORT_SYMBOL_GPL(put_mtd_device); · 47 unmodified lines
10381050
10391051 void __put_mtd_device(struct mtd_info *mtd)
10401052 {
1041− --mtd->usecount;
1042− BUG_ON(mtd->usecount < 0);
1053+ struct mtd_info *master = mtd_get_master(mtd);
10431054
1044− if (mtd->_put_device)
1045− mtd->_put_device(mtd);
1055+ while (mtd->parent) {
1056+ --mtd->usecount;
1057+ BUG_ON(mtd->usecount < 0);
1058+ mtd = mtd->parent;
1059+ }
1060+
1061+ if (master->_put_device)
1062+ master->_put_device(master);
10461063
1047− module_put(mtd->owner);
1064+ module_put(master->owner);
10481065 }
10491066 EXPORT_SYMBOL_GPL(__put_mtd_device);
10501067
@@ -1055,9 +1072,13 @@ EXPORT_SYMBOL_GPL(__put_mtd_device); · 4 unmodified lines
10551072 */
10561073 int mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
10571074 {
1075+ struct mtd_info *master = mtd_get_master(mtd);
1076+ u64 mst_ofs = mtd_get_master_ofs(mtd, 0);
1077+ int ret;
1078+
10581079 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
10591080
1060− if (!mtd->erasesize || !mtd->_erase)
1081+ if (!mtd->erasesize || !master->_erase)
10611082 return -ENOTSUPP;
10621083
10631084 if (instr->addr >= mtd->size || instr->len > mtd->size - instr->addr)
@@ -1069,7 +1090,14 @@ int mtd_erase(struct mtd_info *mtd, struct erase_info *instr) · 5 unmodified lines
10691090 return 0;
10701091
10711092 ledtrig_mtd_activity();
1072− return mtd->_erase(mtd, instr);
1093+
1094+ instr->addr += mst_ofs;
1095+ ret = master->_erase(master, instr);
1096+ if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN)
1097+ instr->fail_addr -= mst_ofs;
1098+
1099+ instr->addr -= mst_ofs;
1100+ return ret;
10731101 }
10741102 EXPORT_SYMBOL_GPL(mtd_erase);
10751103
@@ -1079,30 +1107,36 @@ EXPORT_SYMBOL_GPL(mtd_erase); · 3 unmodified lines
10791107 int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
10801108 void **virt, resource_size_t *phys)
10811109 {
1110+ struct mtd_info *master = mtd_get_master(mtd);
1111+
10821112 *retlen = 0;
10831113 *virt = NULL;
10841114 if (phys)
10851115 *phys = 0;
1086− if (!mtd->_point)
1116+ if (!master->_point)
10871117 return -EOPNOTSUPP;
10881118 if (from < 0 || from >= mtd->size || len > mtd->size - from)
10891119 return -EINVAL;
10901120 if (!len)
10911121 return 0;
1092− return mtd->_point(mtd, from, len, retlen, virt, phys);
1122+
1123+ from = mtd_get_master_ofs(mtd, from);
1124+ return master->_point(master, from, len, retlen, virt, phys);
10931125 }
10941126 EXPORT_SYMBOL_GPL(mtd_point);
10951127
10961128 /* We probably shouldn't allow XIP if the unpoint isn't a NULL */
10971129 int mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len)
10981130 {
1099− if (!mtd->_unpoint)
1131+ struct mtd_info *master = mtd_get_master(mtd);
1132+
1133+ if (!master->_unpoint)
11001134 return -EOPNOTSUPP;
11011135 if (from < 0 || from >= mtd->size || len > mtd->size - from)
11021136 return -EINVAL;
11031137 if (!len)
11041138 return 0;
1105− return mtd->_unpoint(mtd, from, len);
1139+ return master->_unpoint(master, mtd_get_master_ofs(mtd, from), len);
11061140 }
11071141 EXPORT_SYMBOL_GPL(mtd_unpoint);
11081142
@@ -1129,6 +1163,25 @@ unsigned long mtd_get_unmapped_area(struct mtd_info *mtd, unsigned long len, · 20 unmodified lines
11291163 }
11301164 EXPORT_SYMBOL_GPL(mtd_get_unmapped_area);
11311165
1166+static void mtd_update_ecc_stats(struct mtd_info *mtd, struct mtd_info *master,
1167+ const struct mtd_ecc_stats *old_stats)
1168+{
1169+ struct mtd_ecc_stats diff;
1170+
1171+ if (master == mtd)
1172+ return;
1173+
1174+ diff = master->ecc_stats;
1175+ diff.failed -= old_stats->failed;
1176+ diff.corrected -= old_stats->corrected;
1177+
1178+ while (mtd->parent) {
1179+ mtd->ecc_stats.failed += diff.failed;
1180+ mtd->ecc_stats.corrected += diff.corrected;
1181+ mtd = mtd->parent;
1182+ }
1183+}
1184+
11321185 int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
11331186 u_char *buf)
11341187 {
@@ -1171,8 +1224,10 @@ EXPORT_SYMBOL_GPL(mtd_write); · 36 unmodified lines
11711224 int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
11721225 const u_char *buf)
11731226 {
1227+ struct mtd_info *master = mtd_get_master(mtd);
1228+
11741229 *retlen = 0;
1175− if (!mtd->_panic_write)
1230+ if (!master->_panic_write)
11761231 return -EOPNOTSUPP;
11771232 if (to < 0 || to >= mtd->size || len > mtd->size - to)
11781233 return -EINVAL;
@@ -1183,7 +1238,8 @@ int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, · 4 unmodified lines
11831238 if (!mtd->oops_panic_write)
11841239 mtd->oops_panic_write = true;
11851240
1186− return mtd->_panic_write(mtd, to, len, retlen, buf);
1241+ return master->_panic_write(master, mtd_get_master_ofs(mtd, to), len,
1242+ retlen, buf);
11871243 }
11881244 EXPORT_SYMBOL_GPL(mtd_panic_write);
11891245
@@ -1222,7 +1278,10 @@ static int mtd_check_oob_ops(struct mtd_info *mtd, loff_t offs, · 32 unmodified lines
12221278
12231279 int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops)
12241280 {
1281+ struct mtd_info *master = mtd_get_master(mtd);
1282+ struct mtd_ecc_stats old_stats = master->ecc_stats;
12251283 int ret_code;
1284+
12261285 ops->retlen = ops->oobretlen = 0;
12271286
12281287 ret_code = mtd_check_oob_ops(mtd, from, ops);
@@ -1232,14 +1291,17 @@ int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) · 3 unmodified lines
12321291 ledtrig_mtd_activity();
12331292
12341293 /* Check the validity of a potential fallback on mtd->_read */
1235− if (!mtd->_read_oob && (!mtd->_read || ops->oobbuf))
1294+ if (!master->_read_oob && (!master->_read || ops->oobbuf))
12361295 return -EOPNOTSUPP;
12371296
1238− if (mtd->_read_oob)
1239− ret_code = mtd->_read_oob(mtd, from, ops);
1297+ from = mtd_get_master_ofs(mtd, from);
1298+ if (master->_read_oob)
1299+ ret_code = master->_read_oob(master, from, ops);
12401300 else
1241− ret_code = mtd->_read(mtd, from, ops->len, &ops->retlen,
1242− ops->datbuf);
1301+ ret_code = master->_read(master, from, ops->len, &ops->retlen,
1302+ ops->datbuf);
1303+
1304+ mtd_update_ecc_stats(mtd, master, &old_stats);
12431305
12441306 /*
12451307 * In cases where ops->datbuf != NULL, mtd->_read_oob() has semantics
@@ -1258,6 +1320,7 @@ EXPORT_SYMBOL_GPL(mtd_read_oob); · 12 unmodified lines
12581320 int mtd_write_oob(struct mtd_info *mtd, loff_t to,
12591321 struct mtd_oob_ops *ops)
12601322 {
1323+ struct mtd_info *master = mtd_get_master(mtd);
12611324 int ret;
12621325
12631326 ops->retlen = ops->oobretlen = 0;
@@ -1272,14 +1335,16 @@ int mtd_write_oob(struct mtd_info *mtd, loff_t to, · 8 unmodified lines
12721335 ledtrig_mtd_activity();
12731336
12741337 /* Check the validity of a potential fallback on mtd->_write */
1275− if (!mtd->_write_oob && (!mtd->_write || ops->oobbuf))
1338+ if (!master->_write_oob && (!master->_write || ops->oobbuf))
12761339 return -EOPNOTSUPP;
12771340
1278− if (mtd->_write_oob)
1279− return mtd->_write_oob(mtd, to, ops);
1341+ to = mtd_get_master_ofs(mtd, to);
1342+
1343+ if (master->_write_oob)
1344+ return master->_write_oob(master, to, ops);
12801345 else
1281− return mtd->_write(mtd, to, ops->len, &ops->retlen,
1282− ops->datbuf);
1346+ return master->_write(master, to, ops->len, &ops->retlen,
1347+ ops->datbuf);
12831348 }
12841349 EXPORT_SYMBOL_GPL(mtd_write_oob);
12851350
@@ -1302,15 +1367,17 @@ EXPORT_SYMBOL_GPL(mtd_write_oob); · 16 unmodified lines
13021367 int mtd_ooblayout_ecc(struct mtd_info *mtd, int section,
13031368 struct mtd_oob_region *oobecc)
13041369 {
1370+ struct mtd_info *master = mtd_get_master(mtd);
1371+
13051372 memset(oobecc, 0, sizeof(*oobecc));
13061373
1307− if (!mtd || section < 0)
1374+ if (!master || section < 0)
13081375 return -EINVAL;
13091376
1310− if (!mtd->ooblayout || !mtd->ooblayout->ecc)
1377+ if (!master->ooblayout || !master->ooblayout->ecc)
13111378 return -ENOTSUPP;
13121379
1313− return mtd->ooblayout->ecc(mtd, section, oobecc);
1380+ return master->ooblayout->ecc(master, section, oobecc);
13141381 }
13151382 EXPORT_SYMBOL_GPL(mtd_ooblayout_ecc);
13161383
@@ -1334,15 +1401,17 @@ EXPORT_SYMBOL_GPL(mtd_ooblayout_ecc); · 17 unmodified lines
13341401 int mtd_ooblayout_free(struct mtd_info *mtd, int section,
13351402 struct mtd_oob_region *oobfree)
13361403 {
1404+ struct mtd_info *master = mtd_get_master(mtd);
1405+
13371406 memset(oobfree, 0, sizeof(*oobfree));
13381407
1339− if (!mtd || section < 0)
1408+ if (!master || section < 0)
13401409 return -EINVAL;
13411410
1342− if (!mtd->ooblayout || !mtd->ooblayout->free)
1411+ if (!master->ooblayout || !master->ooblayout->free)
13431412 return -ENOTSUPP;
13441413
1345− return mtd->ooblayout->free(mtd, section, oobfree);
1414+ return master->ooblayout->free(master, section, oobfree);
13461415 }
13471416 EXPORT_SYMBOL_GPL(mtd_ooblayout_free);
13481417
@@ -1651,60 +1720,69 @@ EXPORT_SYMBOL_GPL(mtd_ooblayout_count_eccbytes); · 302 unmodified lines
16511720 int mtd_get_fact_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
16521721 struct otp_info *buf)
16531722 {
1654− if (!mtd->_get_fact_prot_info)
1723+ struct mtd_info *master = mtd_get_master(mtd);
1724+
1725+ if (!master->_get_fact_prot_info)
16551726 return -EOPNOTSUPP;
16561727 if (!len)
16571728 return 0;
1658− return mtd->_get_fact_prot_info(mtd, len, retlen, buf);
1729+ return master->_get_fact_prot_info(master, len, retlen, buf);
16591730 }
16601731 EXPORT_SYMBOL_GPL(mtd_get_fact_prot_info);
16611732
16621733 int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
16631734 size_t *retlen, u_char *buf)
16641735 {
1736+ struct mtd_info *master = mtd_get_master(mtd);
1737+
16651738 *retlen = 0;
1666− if (!mtd->_read_fact_prot_reg)
1739+ if (!master->_read_fact_prot_reg)
16671740 return -EOPNOTSUPP;
16681741 if (!len)
16691742 return 0;
1670− return mtd->_read_fact_prot_reg(mtd, from, len, retlen, buf);
1743+ return master->_read_fact_prot_reg(master, from, len, retlen, buf);
16711744 }
16721745 EXPORT_SYMBOL_GPL(mtd_read_fact_prot_reg);
16731746
16741747 int mtd_get_user_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
16751748 struct otp_info *buf)
16761749 {
1677− if (!mtd->_get_user_prot_info)
1750+ struct mtd_info *master = mtd_get_master(mtd);
1751+
1752+ if (!master->_get_user_prot_info)
16781753 return -EOPNOTSUPP;
16791754 if (!len)
16801755 return 0;
1681− return mtd->_get_user_prot_info(mtd, len, retlen, buf);
1756+ return master->_get_user_prot_info(master, len, retlen, buf);
16821757 }
16831758 EXPORT_SYMBOL_GPL(mtd_get_user_prot_info);
16841759
16851760 int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
16861761 size_t *retlen, u_char *buf)
16871762 {
1763+ struct mtd_info *master = mtd_get_master(mtd);
1764+
16881765 *retlen = 0;
1689− if (!mtd->_read_user_prot_reg)
1766+ if (!master->_read_user_prot_reg)
16901767 return -EOPNOTSUPP;
16911768 if (!len)
16921769 return 0;
1693− return mtd->_read_user_prot_reg(mtd, from, len, retlen, buf);
1770+ return master->_read_user_prot_reg(master, from, len, retlen, buf);
16941771 }
16951772 EXPORT_SYMBOL_GPL(mtd_read_user_prot_reg);
16961773
16971774 int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len,
16981775 size_t *retlen, u_char *buf)
16991776 {
1777+ struct mtd_info *master = mtd_get_master(mtd);
17001778 int ret;
17011779
17021780 *retlen = 0;
1703− if (!mtd->_write_user_prot_reg)
1781+ if (!master->_write_user_prot_reg)
17041782 return -EOPNOTSUPP;
17051783 if (!len)
17061784 return 0;
1707− ret = mtd->_write_user_prot_reg(mtd, to, len, retlen, buf);
1785+ ret = master->_write_user_prot_reg(master, to, len, retlen, buf);
17081786 if (ret)
17091787 return ret;
17101788
@@ -1718,80 +1796,105 @@ EXPORT_SYMBOL_GPL(mtd_write_user_prot_reg); · 7 unmodified lines
17181796
17191797 int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len)
17201798 {
1721− if (!mtd->_lock_user_prot_reg)
1799+ struct mtd_info *master = mtd_get_master(mtd);
1800+
1801+ if (!master->_lock_user_prot_reg)
17221802 return -EOPNOTSUPP;
17231803 if (!len)
17241804 return 0;
1725− return mtd->_lock_user_prot_reg(mtd, from, len);
1805+ return master->_lock_user_prot_reg(master, from, len);
17261806 }
17271807 EXPORT_SYMBOL_GPL(mtd_lock_user_prot_reg);
17281808
17291809 /* Chip-supported device locking */
17301810 int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
17311811 {
1732− if (!mtd->_lock)
1812+ struct mtd_info *master = mtd_get_master(mtd);
1813+
1814+ if (!master->_lock)
17331815 return -EOPNOTSUPP;
17341816 if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
17351817 return -EINVAL;
17361818 if (!len)
17371819 return 0;
1738− return mtd->_lock(mtd, ofs, len);
1820+ return master->_lock(master, mtd_get_master_ofs(mtd, ofs), len);
17391821 }
17401822 EXPORT_SYMBOL_GPL(mtd_lock);
17411823
17421824 int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
17431825 {
1744− if (!mtd->_unlock)
1826+ struct mtd_info *master = mtd_get_master(mtd);
1827+
1828+ if (!master->_unlock)
17451829 return -EOPNOTSUPP;
17461830 if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
17471831 return -EINVAL;
17481832 if (!len)
17491833 return 0;
1750− return mtd->_unlock(mtd, ofs, len);
1834+ return master->_unlock(master, mtd_get_master_ofs(mtd, ofs), len);
17511835 }
17521836 EXPORT_SYMBOL_GPL(mtd_unlock);
17531837
17541838 int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
17551839 {
1756− if (!mtd->_is_locked)
1840+ struct mtd_info *master = mtd_get_master(mtd);
1841+
1842+ if (!master->_is_locked)
17571843 return -EOPNOTSUPP;
17581844 if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
17591845 return -EINVAL;
17601846 if (!len)
17611847 return 0;
1762− return mtd->_is_locked(mtd, ofs, len);
1848+ return master->_is_locked(master, mtd_get_master_ofs(mtd, ofs), len);
17631849 }
17641850 EXPORT_SYMBOL_GPL(mtd_is_locked);
17651851
17661852 int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs)
17671853 {
1854+ struct mtd_info *master = mtd_get_master(mtd);
1855+
17681856 if (ofs < 0 || ofs >= mtd->size)
17691857 return -EINVAL;
1770− if (!mtd->_block_isreserved)
1858+ if (!master->_block_isreserved)
17711859 return 0;
1772− return mtd->_block_isreserved(mtd, ofs);
1860+ return master->_block_isreserved(master, mtd_get_master_ofs(mtd, ofs));
17731861 }
17741862 EXPORT_SYMBOL_GPL(mtd_block_isreserved);
17751863
17761864 int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs)
17771865 {
1866+ struct mtd_info *master = mtd_get_master(mtd);
1867+
17781868 if (ofs < 0 || ofs >= mtd->size)
17791869 return -EINVAL;
1780− if (!mtd->_block_isbad)
1870+ if (!master->_block_isbad)
17811871 return 0;
1782− return mtd->_block_isbad(mtd, ofs);
1872+ return master->_block_isbad(master, mtd_get_master_ofs(mtd, ofs));
17831873 }
17841874 EXPORT_SYMBOL_GPL(mtd_block_isbad);
17851875
17861876 int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs)
17871877 {
1788− if (!mtd->_block_markbad)
1878+ struct mtd_info *master = mtd_get_master(mtd);
1879+ int ret;
1880+
1881+ if (!master->_block_markbad)
17891882 return -EOPNOTSUPP;
17901883 if (ofs < 0 || ofs >= mtd->size)
17911884 return -EINVAL;
17921885 if (!(mtd->flags & MTD_WRITEABLE))
17931886 return -EROFS;
1794− return mtd->_block_markbad(mtd, ofs);
1887+
1888+ ret = master->_block_markbad(master, mtd_get_master_ofs(mtd, ofs));
1889+ if (ret)
1890+ return ret;
1891+
1892+ while (mtd->parent) {
1893+ mtd->ecc_stats.badblocks++;
1894+ mtd = mtd->parent;
1895+ }
1896+
1897+ return 0;
17951898 }
17961899 EXPORT_SYMBOL_GPL(mtd_block_markbad);
17971900
@@ -1841,12 +1944,17 @@ static int default_mtd_writev(struct mtd_info *mtd, const struct kvec *vecs, · 43 unmodified lines
18411944 int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
18421945 unsigned long count, loff_t to, size_t *retlen)
18431946 {
1947+ struct mtd_info *master = mtd_get_master(mtd);
1948+
18441949 *retlen = 0;
18451950 if (!(mtd->flags & MTD_WRITEABLE))
18461951 return -EROFS;
1847− if (!mtd->_writev)
1952+
1953+ if (!master->_writev)
18481954 return default_mtd_writev(mtd, vecs, count, to, retlen);
1849− return mtd->_writev(mtd, vecs, count, to, retlen);
1955+
1956+ return master->_writev(master, vecs, count,
1957+ mtd_get_master_ofs(mtd, to), retlen);
18501958 }
18511959 EXPORT_SYMBOL_GPL(mtd_writev);
18521960
drivers/mtd/mtdpart.c+177−518
@@ -20,339 +20,52 @@ · 19 unmodified lines
2020
2121 #include "mtdcore.h"
2222
23−/* Our partition linked list */
24−static LIST_HEAD(mtd_partitions);
25−static DEFINE_MUTEX(mtd_partitions_mutex);
26−
27−/**
28− * struct mtd_part - our partition node structure
29− *
30− * @mtd: struct holding partition details
31− * @parent: parent mtd - flash device or another partition
32− * @offset: partition offset relative to the *flash device*
33− */
34−struct mtd_part {
35− struct mtd_info mtd;
36− struct mtd_info *parent;
37− uint64_t offset;
38− struct list_head list;
39−};
40−
41−/*
42− * Given a pointer to the MTD object in the mtd_part structure, we can retrieve
43− * the pointer to that structure.
44− */
45−static inline struct mtd_part *mtd_to_part(const struct mtd_info *mtd)
46−{
47− return container_of(mtd, struct mtd_part, mtd);
48−}
49−
50−static u64 part_absolute_offset(struct mtd_info *mtd)
51−{
52− struct mtd_part *part = mtd_to_part(mtd);
53−
54− if (!mtd_is_partition(mtd))
55− return 0;
56−
57− return part_absolute_offset(part->parent) + part->offset;
58−}
59−
6023 /*
6124 * MTD methods which simply translate the effective address and pass through
6225 * to the _real_ device.
6326 */
6427
65−static int part_read(struct mtd_info *mtd, loff_t from, size_t len,
66− size_t *retlen, u_char *buf)
67−{
68− struct mtd_part *part = mtd_to_part(mtd);
69− struct mtd_ecc_stats stats;
70− int res;
71−
72− stats = part->parent->ecc_stats;
73− res = part->parent->_read(part->parent, from + part->offset, len,
74− retlen, buf);
75− if (unlikely(mtd_is_eccerr(res)))
76− mtd->ecc_stats.failed +=
77− part->parent->ecc_stats.failed - stats.failed;
78− else
79− mtd->ecc_stats.corrected +=
80− part->parent->ecc_stats.corrected - stats.corrected;
81− return res;
82−}
83−
84−static int part_point(struct mtd_info *mtd, loff_t from, size_t len,
85− size_t *retlen, void **virt, resource_size_t *phys)
86−{
87− struct mtd_part *part = mtd_to_part(mtd);
88−
89− return part->parent->_point(part->parent, from + part->offset, len,
90− retlen, virt, phys);
91−}
92−
93−static int part_unpoint(struct mtd_info *mtd, loff_t from, size_t len)
94−{
95− struct mtd_part *part = mtd_to_part(mtd);
96−
97− return part->parent->_unpoint(part->parent, from + part->offset, len);
98−}
99−
100−static int part_read_oob(struct mtd_info *mtd, loff_t from,
101− struct mtd_oob_ops *ops)
102−{
103− struct mtd_part *part = mtd_to_part(mtd);
104− struct mtd_ecc_stats stats;
105− int res;
106−
107− stats = part->parent->ecc_stats;
108− res = part->parent->_read_oob(part->parent, from + part->offset, ops);
109− if (unlikely(mtd_is_eccerr(res)))
110− mtd->ecc_stats.failed +=
111− part->parent->ecc_stats.failed - stats.failed;
112− else
113− mtd->ecc_stats.corrected +=
114− part->parent->ecc_stats.corrected - stats.corrected;
115− return res;
116−}
117−
118−static int part_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
119− size_t len, size_t *retlen, u_char *buf)
120−{
121− struct mtd_part *part = mtd_to_part(mtd);
122− return part->parent->_read_user_prot_reg(part->parent, from, len,
123− retlen, buf);
124−}
125−
126−static int part_get_user_prot_info(struct mtd_info *mtd, size_t len,
127− size_t *retlen, struct otp_info *buf)
128−{
129− struct mtd_part *part = mtd_to_part(mtd);
130− return part->parent->_get_user_prot_info(part->parent, len, retlen,
131− buf);
132−}
133−
134−static int part_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
135− size_t len, size_t *retlen, u_char *buf)
136−{
137− struct mtd_part *part = mtd_to_part(mtd);
138− return part->parent->_read_fact_prot_reg(part->parent, from, len,
139− retlen, buf);
140−}
141−
142−static int part_get_fact_prot_info(struct mtd_info *mtd, size_t len,
143− size_t *retlen, struct otp_info *buf)
144−{
145− struct mtd_part *part = mtd_to_part(mtd);
146− return part->parent->_get_fact_prot_info(part->parent, len, retlen,
147− buf);
148−}
149−
150−static int part_write(struct mtd_info *mtd, loff_t to, size_t len,
151− size_t *retlen, const u_char *buf)
152−{
153− struct mtd_part *part = mtd_to_part(mtd);
154− return part->parent->_write(part->parent, to + part->offset, len,
155− retlen, buf);
156−}
157−
158−static int part_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
159− size_t *retlen, const u_char *buf)
160−{
161− struct mtd_part *part = mtd_to_part(mtd);
162− return part->parent->_panic_write(part->parent, to + part->offset, len,
163− retlen, buf);
164−}
165−
166−static int part_write_oob(struct mtd_info *mtd, loff_t to,
167− struct mtd_oob_ops *ops)
168−{
169− struct mtd_part *part = mtd_to_part(mtd);
170−
171− return part->parent->_write_oob(part->parent, to + part->offset, ops);
172−}
173−
174−static int part_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
175− size_t len, size_t *retlen, u_char *buf)
176−{
177− struct mtd_part *part = mtd_to_part(mtd);
178− return part->parent->_write_user_prot_reg(part->parent, from, len,
179− retlen, buf);
180−}
181−
182−static int part_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
183− size_t len)
184−{
185− struct mtd_part *part = mtd_to_part(mtd);
186− return part->parent->_lock_user_prot_reg(part->parent, from, len);
187−}
188−
189−static int part_writev(struct mtd_info *mtd, const struct kvec *vecs,
190− unsigned long count, loff_t to, size_t *retlen)
191−{
192− struct mtd_part *part = mtd_to_part(mtd);
193− return part->parent->_writev(part->parent, vecs, count,
194− to + part->offset, retlen);
195−}
196−
197−static int part_erase(struct mtd_info *mtd, struct erase_info *instr)
198−{
199− struct mtd_part *part = mtd_to_part(mtd);
200− int ret;
201−
202− instr->addr += part->offset;
203− ret = part->parent->_erase(part->parent, instr);
204− if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN)
205− instr->fail_addr -= part->offset;
206− instr->addr -= part->offset;
207−
208− return ret;
209−}
210−
211−static int part_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
212−{
213− struct mtd_part *part = mtd_to_part(mtd);
214− return part->parent->_lock(part->parent, ofs + part->offset, len);
215−}
216−
217−static int part_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
218−{
219− struct mtd_part *part = mtd_to_part(mtd);
220− return part->parent->_unlock(part->parent, ofs + part->offset, len);
221−}
222−
223−static int part_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
224−{
225− struct mtd_part *part = mtd_to_part(mtd);
226− return part->parent->_is_locked(part->parent, ofs + part->offset, len);
227−}
228−
229−static void part_sync(struct mtd_info *mtd)
230−{
231− struct mtd_part *part = mtd_to_part(mtd);
232− part->parent->_sync(part->parent);
233−}
234−
235−static int part_suspend(struct mtd_info *mtd)
236−{
237− struct mtd_part *part = mtd_to_part(mtd);
238− return part->parent->_suspend(part->parent);
239−}
240−
241−static void part_resume(struct mtd_info *mtd)
242−{
243− struct mtd_part *part = mtd_to_part(mtd);
244− part->parent->_resume(part->parent);
245−}
246−
247−static int part_block_isreserved(struct mtd_info *mtd, loff_t ofs)
248−{
249− struct mtd_part *part = mtd_to_part(mtd);
250− ofs += part->offset;
251− return part->parent->_block_isreserved(part->parent, ofs);
252−}
253−
254−static int part_block_isbad(struct mtd_info *mtd, loff_t ofs)
255−{
256− struct mtd_part *part = mtd_to_part(mtd);
257− ofs += part->offset;
258− return part->parent->_block_isbad(part->parent, ofs);
259−}
260−
261−static int part_block_markbad(struct mtd_info *mtd, loff_t ofs)
262−{
263− struct mtd_part *part = mtd_to_part(mtd);
264− int res;
265−
266− ofs += part->offset;
267− res = part->parent->_block_markbad(part->parent, ofs);
268− if (!res)
269− mtd->ecc_stats.badblocks++;
270− return res;
271−}
272−
273−static int part_get_device(struct mtd_info *mtd)
274−{
275− struct mtd_part *part = mtd_to_part(mtd);
276− return part->parent->_get_device(part->parent);
277−}
278−
279−static void part_put_device(struct mtd_info *mtd)
280−{
281− struct mtd_part *part = mtd_to_part(mtd);
282− part->parent->_put_device(part->parent);
283−}
284−
285−static int part_ooblayout_ecc(struct mtd_info *mtd, int section,
286− struct mtd_oob_region *oobregion)
287−{
288− struct mtd_part *part = mtd_to_part(mtd);
289−
290− return mtd_ooblayout_ecc(part->parent, section, oobregion);
291−}
292−
293−static int part_ooblayout_free(struct mtd_info *mtd, int section,
294− struct mtd_oob_region *oobregion)
295−{
296− struct mtd_part *part = mtd_to_part(mtd);
297−
298− return mtd_ooblayout_free(part->parent, section, oobregion);
299−}
300−
301−static const struct mtd_ooblayout_ops part_ooblayout_ops = {
302− .ecc = part_ooblayout_ecc,
303− .free = part_ooblayout_free,
304−};
305−
306−static int part_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len)
307−{
308− struct mtd_part *part = mtd_to_part(mtd);
309−
310− return part->parent->_max_bad_blocks(part->parent,
311− ofs + part->offset, len);
312−}
313−
314−static inline void free_partition(struct mtd_part *p)
28+static inline void free_partition(struct mtd_info *mtd)
31529 {
316− kfree(p->mtd.name);
317− kfree(p);
30+ kfree(mtd->name);
31+ kfree(mtd);
31832 }
31933
320−static struct mtd_part *allocate_partition(struct mtd_info *parent,
321− const struct mtd_partition *part, int partno,
322− uint64_t cur_offset)
34+static struct mtd_info *allocate_partition(struct mtd_info *parent,
35+ const struct mtd_partition *part,
36+ int partno, uint64_t cur_offset)
32337 {
32438 int wr_alignment = (parent->flags & MTD_NO_ERASE) ? parent->writesize :
32539 parent->erasesize;
326− struct mtd_part *slave;
40+ struct mtd_info *child, *master = mtd_get_master(parent);
32741 u32 remainder;
32842 char *name;
32943 u64 tmp;
33044
33145 /* allocate the partition structure */
332− slave = kzalloc(sizeof(*slave), GFP_KERNEL);
46+ child = kzalloc(sizeof(*child), GFP_KERNEL);
33347 name = kstrdup(part->name, GFP_KERNEL);
334− if (!name || !slave) {
48+ if (!name || !child) {
33549 printk(KERN_ERR"memory allocation error while creating partitions for \"%s\"\n",
33650 parent->name);
33751 kfree(name);
338− kfree(slave);
52+ kfree(child);
33953 return ERR_PTR(-ENOMEM);
34054 }
34155
34256 /* set up the MTD object for this partition */
343− slave->mtd.type = parent->type;
344− slave->mtd.flags = parent->orig_flags & ~part->mask_flags;
345− slave->mtd.orig_flags = slave->mtd.flags;
346− slave->mtd.size = part->size;
347− slave->mtd.writesize = parent->writesize;
348− slave->mtd.writebufsize = parent->writebufsize;
349− slave->mtd.oobsize = parent->oobsize;
350− slave->mtd.oobavail = parent->oobavail;
351− slave->mtd.subpage_sft = parent->subpage_sft;
352− slave->mtd.pairing = parent->pairing;
353−
354− slave->mtd.name = name;
355− slave->mtd.owner = parent->owner;
57+ child->type = parent->type;
58+ child->part.flags = parent->flags & ~part->mask_flags;
59+ child->flags = child->part.flags;
60+ child->size = part->size;
61+ child->writesize = parent->writesize;
62+ child->writebufsize = parent->writebufsize;
63+ child->oobsize = parent->oobsize;
64+ child->oobavail = parent->oobavail;
65+ child->subpage_sft = parent->subpage_sft;
66+
67+ child->name = name;
68+ child->owner = parent->owner;
35669
35770 /* NOTE: Historically, we didn't arrange MTDs as a tree out of
35871 * concern for showing the same data in multiple partitions.
@@ -360,134 +73,76 @@ static struct mtd_part *allocate_partition(struct mtd_info *parent, · 1 unmodified line
36073 * so the MTD_PARTITIONED_MASTER option allows that. The master
36174 * will have device nodes etc only if this is set, so make the
36275 * parent conditional on that option. Note, this is a way to
363− * distinguish between the master and the partition in sysfs.
76+ * distinguish between the parent and its partitions in sysfs.
36477 */
365− slave->mtd.dev.parent = IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER) || mtd_is_partition(parent) ?
366− &parent->dev :
367− parent->dev.parent;
368− slave->mtd.dev.of_node = part->of_node;
369−
370− if (parent->_read)
371− slave->mtd._read = part_read;
372− if (parent->_write)
373− slave->mtd._write = part_write;
374−
375− if (parent->_panic_write)
376− slave->mtd._panic_write = part_panic_write;
377−
378− if (parent->_point && parent->_unpoint) {
379− slave->mtd._point = part_point;
380− slave->mtd._unpoint = part_unpoint;
381− }
382−
383− if (parent->_read_oob)
384− slave->mtd._read_oob = part_read_oob;
385− if (parent->_write_oob)
386− slave->mtd._write_oob = part_write_oob;
387− if (parent->_read_user_prot_reg)
388− slave->mtd._read_user_prot_reg = part_read_user_prot_reg;
389− if (parent->_read_fact_prot_reg)
390− slave->mtd._read_fact_prot_reg = part_read_fact_prot_reg;
391− if (parent->_write_user_prot_reg)
392− slave->mtd._write_user_prot_reg = part_write_user_prot_reg;
393− if (parent->_lock_user_prot_reg)
394− slave->mtd._lock_user_prot_reg = part_lock_user_prot_reg;
395− if (parent->_get_user_prot_info)
396− slave->mtd._get_user_prot_info = part_get_user_prot_info;
397− if (parent->_get_fact_prot_info)
398− slave->mtd._get_fact_prot_info = part_get_fact_prot_info;
399− if (parent->_sync)
400− slave->mtd._sync = part_sync;
401− if (!partno && !parent->dev.class && parent->_suspend &&
402− parent->_resume) {
403− slave->mtd._suspend = part_suspend;
404− slave->mtd._resume = part_resume;
405− }
406− if (parent->_writev)
407− slave->mtd._writev = part_writev;
408− if (parent->_lock)
409− slave->mtd._lock = part_lock;
410− if (parent->_unlock)
411− slave->mtd._unlock = part_unlock;
412− if (parent->_is_locked)
413− slave->mtd._is_locked = part_is_locked;
414− if (parent->_block_isreserved)
415− slave->mtd._block_isreserved = part_block_isreserved;
416− if (parent->_block_isbad)
417− slave->mtd._block_isbad = part_block_isbad;
418− if (parent->_block_markbad)
419− slave->mtd._block_markbad = part_block_markbad;
420− if (parent->_max_bad_blocks)
421− slave->mtd._max_bad_blocks = part_max_bad_blocks;
422−
423− if (parent->_get_device)
424− slave->mtd._get_device = part_get_device;
425− if (parent->_put_device)
426− slave->mtd._put_device = part_put_device;
427−
428− slave->mtd._erase = part_erase;
429− slave->parent = parent;
430− slave->offset = part->offset;
431−
432− if (slave->offset == MTDPART_OFS_APPEND)
433− slave->offset = cur_offset;
434− if (slave->offset == MTDPART_OFS_NXTBLK) {
78+ child->dev.parent = IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER) || mtd_is_partition(parent) ?
79+ &parent->dev : parent->dev.parent;
80+ child->dev.of_node = part->of_node;
81+ child->parent = parent;
82+ child->part.offset = part->offset;
83+ INIT_LIST_HEAD(&child->partitions);
84+
85+ if (child->part.offset == MTDPART_OFS_APPEND)
86+ child->part.offset = cur_offset;
87+ if (child->part.offset == MTDPART_OFS_NXTBLK) {
43588 tmp = cur_offset;
436− slave->offset = cur_offset;
89+ child->part.offset = cur_offset;
43790 remainder = do_div(tmp, wr_alignment);
43891 if (remainder) {
439− slave->offset += wr_alignment - remainder;
92+ child->part.offset += wr_alignment - remainder;
44093 printk(KERN_NOTICE "Moving partition %d: "
44194 "0x%012llx -> 0x%012llx\n", partno,
442− (unsigned long long)cur_offset, (unsigned long long)slave->offset);
95+ (unsigned long long)cur_offset,
96+ child->part.offset);
44397 }
44498 }
445− if (slave->offset == MTDPART_OFS_RETAIN) {
446− slave->offset = cur_offset;
447− if (parent->size - slave->offset >= slave->mtd.size) {
448− slave->mtd.size = parent->size - slave->offset
449− - slave->mtd.size;
99+ if (child->part.offset == MTDPART_OFS_RETAIN) {
100+ child->part.offset = cur_offset;
101+ if (parent->size - child->part.offset >= child->size) {
102+ child->size = parent->size - child->part.offset -
103+ child->size;
450104 } else {
451105 printk(KERN_ERR "mtd partition \"%s\" doesn't have enough space: %#llx < %#llx, disabled\n",
452− part->name, parent->size - slave->offset,
453− slave->mtd.size);
106+ part->name, parent->size - child->part.offset,
107+ child->size);
454108 /* register to preserve ordering */
455109 goto out_register;
456110 }
457111 }
458− if (slave->mtd.size == MTDPART_SIZ_FULL)
459− slave->mtd.size = parent->size - slave->offset;
112+ if (child->size == MTDPART_SIZ_FULL)
113+ child->size = parent->size - child->part.offset;
460114
461− printk(KERN_NOTICE "0x%012llx-0x%012llx : \"%s\"\n", (unsigned long long)slave->offset,
462− (unsigned long long)(slave->offset + slave->mtd.size), slave->mtd.name);
115+ printk(KERN_NOTICE "0x%012llx-0x%012llx : \"%s\"\n",
116+ child->part.offset, child->part.offset + child->size,
117+ child->name);
463118
464119 /* let's do some sanity checks */
465− if (slave->offset >= parent->size) {
120+ if (child->part.offset >= parent->size) {
466121 /* let's register it anyway to preserve ordering */
467− slave->offset = 0;
468− slave->mtd.size = 0;
122+ child->part.offset = 0;
123+ child->size = 0;
469124
470125 /* Initialize ->erasesize to make add_mtd_device() happy. */
471− slave->mtd.erasesize = parent->erasesize;
472−
126+ child->erasesize = parent->erasesize;
473127 printk(KERN_ERR"mtd: partition \"%s\" is out of reach -- disabled\n",
474128 part->name);
475129 goto out_register;
476130 }
477− if (slave->offset + slave->mtd.size > parent->size) {
478− slave->mtd.size = parent->size - slave->offset;
131+ if (child->part.offset + child->size > parent->size) {
132+ child->size = parent->size - child->part.offset;
479133 printk(KERN_WARNING"mtd: partition \"%s\" extends beyond the end of device \"%s\" -- size truncated to %#llx\n",
480− part->name, parent->name, (unsigned long long)slave->mtd.size);
134+ part->name, parent->name, child->size);
481135 }
482136 if (parent->numeraseregions > 1) {
483137 /* Deal with variable erase size stuff */
484138 int i, max = parent->numeraseregions;
485− u64 end = slave->offset + slave->mtd.size;
139+ u64 end = child->part.offset + child->size;
486140 struct mtd_erase_region_info *regions = parent->eraseregions;
487141
488142 /* Find the first erase regions which is part of this
489143 * partition. */
490− for (i = 0; i < max && regions[i].offset <= slave->offset; i++)
144+ for (i = 0; i < max && regions[i].offset <= child->part.offset;
145+ i++)
491146 ;
492147 /* The loop searched for the region _behind_ the first one */
493148 if (i > 0)
@@ -495,70 +150,68 @@ static struct mtd_part *allocate_partition(struct mtd_info *parent, · 1 unmodified line
495150
496151 /* Pick biggest erasesize */
497152 for (; i < max && regions[i].offset < end; i++) {
498− if (slave->mtd.erasesize < regions[i].erasesize) {
499− slave->mtd.erasesize = regions[i].erasesize;
500− }
153+ if (child->erasesize < regions[i].erasesize)
154+ child->erasesize = regions[i].erasesize;
501155 }
502− BUG_ON(slave->mtd.erasesize == 0);
156+ BUG_ON(child->erasesize == 0);
503157 } else {
504158 /* Single erase size */
505− slave->mtd.erasesize = parent->erasesize;
159+ child->erasesize = parent->erasesize;
506160 }
507161
508162 /*
509− * Slave erasesize might differ from the master one if the master
163+ * Child erasesize might differ from the parent one if the parent
510164 * exposes several regions with different erasesize. Adjust
511165 * wr_alignment accordingly.
512166 */
513− if (!(slave->mtd.flags & MTD_NO_ERASE))
514− wr_alignment = slave->mtd.erasesize;
167+ if (!(child->flags & MTD_NO_ERASE))
168+ wr_alignment = child->erasesize;
515169
516− tmp = part_absolute_offset(parent) + slave->offset;
170+ tmp = mtd_get_master_ofs(child, 0);
517171 remainder = do_div(tmp, wr_alignment);
518− if ((slave->mtd.flags & MTD_WRITEABLE) && remainder) {
172+ if ((child->flags & MTD_WRITEABLE) && remainder) {
519173 /* Doesn't start on a boundary of major erase size */
520174 /* FIXME: Let it be writable if it is on a boundary of
521175 * _minor_ erase size though */
522− slave->mtd.flags &= ~MTD_WRITEABLE;
176+ child->flags &= ~MTD_WRITEABLE;
523177 printk(KERN_WARNING"mtd: partition \"%s\" doesn't start on an erase/write block boundary -- force read-only\n",
524178 part->name);
525179 }
526180
527− tmp = part_absolute_offset(parent) + slave->mtd.size;
181+ tmp = mtd_get_master_ofs(child, 0) + child->size;
528182 remainder = do_div(tmp, wr_alignment);
529− if ((slave->mtd.flags & MTD_WRITEABLE) && remainder) {
530− slave->mtd.flags &= ~MTD_WRITEABLE;
183+ if ((child->flags & MTD_WRITEABLE) && remainder) {
184+ child->flags &= ~MTD_WRITEABLE;
531185 printk(KERN_WARNING"mtd: partition \"%s\" doesn't end on an erase/write block -- force read-only\n",
532186 part->name);
533187 }
534188
535− mtd_set_ooblayout(&slave->mtd, &part_ooblayout_ops);
536− slave->mtd.ecc_step_size = parent->ecc_step_size;
537− slave->mtd.ecc_strength = parent->ecc_strength;
538− slave->mtd.bitflip_threshold = parent->bitflip_threshold;
189+ child->ecc_step_size = parent->ecc_step_size;
190+ child->ecc_strength = parent->ecc_strength;
191+ child->bitflip_threshold = parent->bitflip_threshold;
539192
540− if (parent->_block_isbad) {
193+ if (master->_block_isbad) {
541194 uint64_t offs = 0;
542195
543− while (offs < slave->mtd.size) {
544− if (mtd_block_isreserved(parent, offs + slave->offset))
545− slave->mtd.ecc_stats.bbtblocks++;
546− else if (mtd_block_isbad(parent, offs + slave->offset))
547− slave->mtd.ecc_stats.badblocks++;
548− offs += slave->mtd.erasesize;
196+ while (offs < child->size) {
197+ if (mtd_block_isreserved(child, offs))
198+ child->ecc_stats.bbtblocks++;
199+ else if (mtd_block_isbad(child, offs))
200+ child->ecc_stats.badblocks++;
201+ offs += child->erasesize;
549202 }
550203 }
551204
552205 out_register:
553− return slave;
206+ return child;
554207 }
555208
556209 static ssize_t mtd_partition_offset_show(struct device *dev,
557210 struct device_attribute *attr, char *buf)
558211 {
559212 struct mtd_info *mtd = dev_get_drvdata(dev);
560− struct mtd_part *part = mtd_to_part(mtd);
561− return snprintf(buf, PAGE_SIZE, "%llu\n", part->offset);
213+
214+ return snprintf(buf, PAGE_SIZE, "%lld\n", mtd->part.offset);
562215 }
563216
564217 static DEVICE_ATTR(offset, S_IRUGO, mtd_partition_offset_show, NULL);
@@ -568,9 +221,9 @@ static const struct attribute *mtd_partition_attrs[] = { · 3 unmodified lines
568221 NULL
569222 };
570223
571−static int mtd_add_partition_attrs(struct mtd_part *new)
224+static int mtd_add_partition_attrs(struct mtd_info *new)
572225 {
573− int ret = sysfs_create_files(&new->mtd.dev.kobj, mtd_partition_attrs);
226+ int ret = sysfs_create_files(&new->dev.kobj, mtd_partition_attrs);
574227 if (ret)
575228 printk(KERN_WARNING
576229 "mtd: failed to create partition attrs, err=%d\n", ret);
@@ -580,8 +233,9 @@ static int mtd_add_partition_attrs(struct mtd_part *new) · 3 unmodified lines
580233 int mtd_add_partition(struct mtd_info *parent, const char *name,
581234 long long offset, long long length)
582235 {
236+ struct mtd_info *master = mtd_get_master(parent);
583237 struct mtd_partition part;
584− struct mtd_part *new;
238+ struct mtd_info *child;
585239 int ret = 0;
586240
587241 /* the direct offset is expected */
@@ -600,28 +254,28 @@ int mtd_add_partition(struct mtd_info *parent, const char *name, · 12 unmodified lines
600254 part.size = length;
601255 part.offset = offset;
602256
603− new = allocate_partition(parent, &part, -1, offset);
604− if (IS_ERR(new))
605− return PTR_ERR(new);
257+ child = allocate_partition(parent, &part, -1, offset);
258+ if (IS_ERR(child))
259+ return PTR_ERR(child);
606260
607− mutex_lock(&mtd_partitions_mutex);
608− list_add(&new->list, &mtd_partitions);
609− mutex_unlock(&mtd_partitions_mutex);
261+ mutex_lock(&master->master.partitions_lock);
262+ list_add_tail(&child->part.node, &parent->partitions);
263+ mutex_unlock(&master->master.partitions_lock);
610264
611− ret = add_mtd_device(&new->mtd);
265+ ret = add_mtd_device(child);
612266 if (ret)
613267 goto err_remove_part;
614268
615− mtd_add_partition_attrs(new);
269+ mtd_add_partition_attrs(child);
616270
617271 return 0;
618272
619273 err_remove_part:
620− mutex_lock(&mtd_partitions_mutex);
621− list_del(&new->list);
622− mutex_unlock(&mtd_partitions_mutex);
274+ mutex_lock(&master->master.partitions_lock);
275+ list_del(&child->part.node);
276+ mutex_unlock(&master->master.partitions_lock);
623277
624− free_partition(new);
278+ free_partition(child);
625279
626280 return ret;
627281 }
@@ -630,119 +284,142 @@ EXPORT_SYMBOL_GPL(mtd_add_partition); · 2 unmodified lines
630284 /**
631285 * __mtd_del_partition - delete MTD partition
632286 *
633− * @priv: internal MTD struct for partition to be deleted
287+ * @priv: MTD structure to be deleted
634288 *
635289 * This function must be called with the partitions mutex locked.
636290 */
637−static int __mtd_del_partition(struct mtd_part *priv)
291+static int __mtd_del_partition(struct mtd_info *mtd)
638292 {
639− struct mtd_part *child, *next;
293+ struct mtd_info *child, *next;
640294 int err;
641295
642− list_for_each_entry_safe(child, next, &mtd_partitions, list) {
643− if (child->parent == &priv->mtd) {
644− err = __mtd_del_partition(child);
645− if (err)
646− return err;
647− }
296+ list_for_each_entry_safe(child, next, &mtd->partitions, part.node) {
297+ err = __mtd_del_partition(child);
298+ if (err)
299+ return err;
648300 }
649301
650− sysfs_remove_files(&priv->mtd.dev.kobj, mtd_partition_attrs);
302+ sysfs_remove_files(&mtd->dev.kobj, mtd_partition_attrs);
651303
652− err = del_mtd_device(&priv->mtd);
304+ err = del_mtd_device(mtd);
653305 if (err)
654306 return err;
655307
656− list_del(&priv->list);
657− free_partition(priv);
308+ list_del(&child->part.node);
309+ free_partition(mtd);
658310
659311 return 0;
660312 }
661313
662314 /*
663315 * This function unregisters and destroy all slave MTD objects which are
664− * attached to the given MTD object.
316+ * attached to the given MTD object, recursively.
665317 */
666−int del_mtd_partitions(struct mtd_info *mtd)
318+static int __del_mtd_partitions(struct mtd_info *mtd)
667319 {
668− struct mtd_part *slave, *next;
320+ struct mtd_info *child, *next;
321+ LIST_HEAD(tmp_list);
669322 int ret, err = 0;
670323
671− mutex_lock(&mtd_partitions_mutex);
672− list_for_each_entry_safe(slave, next, &mtd_partitions, list)
673− if (slave->parent == mtd) {
674− ret = __mtd_del_partition(slave);
675− if (ret < 0)
676− err = ret;
324+ list_for_each_entry_safe(child, next, &mtd->partitions, part.node) {
325+ if (mtd_has_partitions(child))
326+ del_mtd_partitions(child);
327+
328+ pr_info("Deleting %s MTD partition\n", child->name);
329+ ret = del_mtd_device(child);
330+ if (ret < 0) {
331+ pr_err("Error when deleting partition \"%s\" (%d)\n",
332+ child->name, ret);
333+ err = ret;
334+ continue;
677335 }
678− mutex_unlock(&mtd_partitions_mutex);
336+
337+ list_del(&child->part.node);
338+ free_partition(child);
339+ }
679340
680341 return err;
681342 }
682343
344+int del_mtd_partitions(struct mtd_info *mtd)
345+{
346+ struct mtd_info *master = mtd_get_master(mtd);
347+ int ret;
348+
349+ pr_info("Deleting MTD partitions on \"%s\":\n", mtd->name);
350+
351+ mutex_lock(&master->master.partitions_lock);
352+ ret = __del_mtd_partitions(mtd);
353+ mutex_unlock(&master->master.partitions_lock);
354+
355+ return ret;
356+}
357+
683358 int mtd_del_partition(struct mtd_info *mtd, int partno)
684359 {
685− struct mtd_part *slave, *next;
360+ struct mtd_info *child, *master = mtd_get_master(mtd);
686361 int ret = -EINVAL;
687362
688− mutex_lock(&mtd_partitions_mutex);
689− list_for_each_entry_safe(slave, next, &mtd_partitions, list)
690− if ((slave->parent == mtd) &&
691− (slave->mtd.index == partno)) {
692− ret = __mtd_del_partition(slave);
363+ mutex_lock(&master->master.partitions_lock);
364+ list_for_each_entry(child, &mtd->partitions, part.node) {
365+ if (child->index == partno) {
366+ ret = __mtd_del_partition(child);
693367 break;
694368 }
695− mutex_unlock(&mtd_partitions_mutex);
369+ }
370+ mutex_unlock(&master->master.partitions_lock);
696371
697372 return ret;
698373 }
699374 EXPORT_SYMBOL_GPL(mtd_del_partition);
700375
701376 /*
702− * This function, given a master MTD object and a partition table, creates
703− * and registers slave MTD objects which are bound to the master according to
704− * the partition definitions.
377+ * This function, given a parent MTD object and a partition table, creates
378+ * and registers the child MTD objects which are bound to the parent according
379+ * to the partition definitions.
705380 *
706− * For historical reasons, this function's caller only registers the master
381+ * For historical reasons, this function's caller only registers the parent
707382 * if the MTD_PARTITIONED_MASTER config option is set.
708383 */
709384
710−int add_mtd_partitions(struct mtd_info *master,
385+int add_mtd_partitions(struct mtd_info *parent,
711386 const struct mtd_partition *parts,
712387 int nbparts)
713388 {
714− struct mtd_part *slave;
389+ struct mtd_info *child, *master = mtd_get_master(parent);
715390 uint64_t cur_offset = 0;
716391 int i, ret;
717392
718− printk(KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", nbparts, master->name);
393+ printk(KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n",
394+ nbparts, parent->name);
719395
720396 for (i = 0; i < nbparts; i++) {
721− slave = allocate_partition(master, parts + i, i, cur_offset);
722− if (IS_ERR(slave)) {
723− ret = PTR_ERR(slave);
397+ child = allocate_partition(parent, parts + i, i, cur_offset);
398+ if (IS_ERR(child)) {
399+ ret = PTR_ERR(child);
724400 goto err_del_partitions;
725401 }
726402
727− mutex_lock(&mtd_partitions_mutex);
728− list_add(&slave->list, &mtd_partitions);
729− mutex_unlock(&mtd_partitions_mutex);
403+ mutex_lock(&master->master.partitions_lock);
404+ list_add_tail(&child->part.node, &parent->partitions);
405+ mutex_unlock(&master->master.partitions_lock);
730406
731− ret = add_mtd_device(&slave->mtd);
407+ ret = add_mtd_device(child);
732408 if (ret) {
733− mutex_lock(&mtd_partitions_mutex);
734− list_del(&slave->list);
735− mutex_unlock(&mtd_partitions_mutex);
409+ mutex_lock(&master->master.partitions_lock);
410+ list_del(&child->part.node);
411+ mutex_unlock(&master->master.partitions_lock);
736412
737− free_partition(slave);
413+ free_partition(child);
738414 goto err_del_partitions;
739415 }
740416
741− mtd_add_partition_attrs(slave);
417+ mtd_add_partition_attrs(child);
418+
742419 /* Look for subpartitions */
743− parse_mtd_partitions(&slave->mtd, parts[i].types, NULL);
420+ parse_mtd_partitions(child, parts[i].types, NULL);
744421
745− cur_offset = slave->offset + slave->mtd.size;
422+ cur_offset = child->part.offset + child->size;
746423 }
747424
748425 return 0;
@@ -1023,29 +700,11 @@ void mtd_part_parser_cleanup(struct mtd_partitions *parts) · 274 unmodified lines
1023700 }
1024701 }
1025702
1026−int mtd_is_partition(const struct mtd_info *mtd)
1027−{
1028− struct mtd_part *part;
1029− int ispart = 0;
1030−
1031− mutex_lock(&mtd_partitions_mutex);
1032− list_for_each_entry(part, &mtd_partitions, list)
1033− if (&part->mtd == mtd) {
1034− ispart = 1;
1035− break;
1036− }
1037− mutex_unlock(&mtd_partitions_mutex);
1038−
1039− return ispart;
1040−}
1041−EXPORT_SYMBOL_GPL(mtd_is_partition);
1042−
1043703 /* Returns the size of the entire flash chip */
1044704 uint64_t mtd_get_device_size(const struct mtd_info *mtd)
1045705 {
1046− if (!mtd_is_partition(mtd))
1047− return mtd->size;
706+ struct mtd_info *master = mtd_get_master((struct mtd_info *)mtd);
1048707
1049− return mtd_get_device_size(mtd_to_part(mtd)->parent);
708+ return master->size;
1050709 }
1051710 EXPORT_SYMBOL_GPL(mtd_get_device_size);
drivers/mtd/nand/onenand/onenand_base.c+1−1
@@ -3259,7 +3259,7 @@ static void onenand_check_features(struct mtd_info *mtd) · 3258 unmodified lines
32593259 switch (density) {
32603260 case ONENAND_DEVICE_DENSITY_8Gb:
32613261 this->options |= ONENAND_HAS_NOP_1;
3262− /* fall through */
3262+ fallthrough;
32633263 case ONENAND_DEVICE_DENSITY_4Gb:
32643264 if (ONENAND_IS_DDP(this))
32653265 this->options |= ONENAND_HAS_2PLANE;
drivers/mtd/nand/raw/ams-delta.c+155−82
@@ -19,15 +19,17 @@ · 18 unmodified lines
1919 #include <linux/delay.h>
2020 #include <linux/gpio/consumer.h>
2121 #include <linux/mtd/mtd.h>
22+#include <linux/mtd/nand-gpio.h>
2223 #include <linux/mtd/rawnand.h>
2324 #include <linux/mtd/partitions.h>
25+#include <linux/of_device.h>
2426 #include <linux/platform_device.h>
2527 #include <linux/sizes.h>
2628
2729 /*
2830 * MTD structure for E3 (Delta)
2931 */
30−struct ams_delta_nand {
32+struct gpio_nand {
3133 struct nand_controller base;
3234 struct nand_chip nand_chip;
3335 struct gpio_desc *gpiod_rdy;
@@ -39,41 +41,20 @@ struct ams_delta_nand { · 5 unmodified lines
3941 struct gpio_desc *gpiod_cle;
4042 struct gpio_descs *data_gpiods;
4143 bool data_in;
44+ unsigned int tRP;
45+ unsigned int tWP;
46+ u8 (*io_read)(struct gpio_nand *this);
47+ void (*io_write)(struct gpio_nand *this, u8 byte);
4248 };
4349
44−/*
45− * Define partitions for flash devices
46− */
47−
48−static const struct mtd_partition partition_info[] = {
49− { .name = "Kernel",
50− .offset = 0,
51− .size = 3 * SZ_1M + SZ_512K },
52− { .name = "u-boot",
53− .offset = 3 * SZ_1M + SZ_512K,
54− .size = SZ_256K },
55− { .name = "u-boot params",
56− .offset = 3 * SZ_1M + SZ_512K + SZ_256K,
57− .size = SZ_256K },
58− { .name = "Amstrad LDR",
59− .offset = 4 * SZ_1M,
60− .size = SZ_256K },
61− { .name = "File system",
62− .offset = 4 * SZ_1M + 1 * SZ_256K,
63− .size = 27 * SZ_1M },
64− { .name = "PBL reserved",
65− .offset = 32 * SZ_1M - 3 * SZ_256K,
66− .size = 3 * SZ_256K },
67−};
68−
69−static void ams_delta_write_commit(struct ams_delta_nand *priv)
50+static void gpio_nand_write_commit(struct gpio_nand *priv)
7051 {
71− gpiod_set_value(priv->gpiod_nwe, 0);
72− ndelay(40);
7352 gpiod_set_value(priv->gpiod_nwe, 1);
53+ ndelay(priv->tWP);
54+ gpiod_set_value(priv->gpiod_nwe, 0);
7455 }
7556
76−static void ams_delta_io_write(struct ams_delta_nand *priv, u8 byte)
57+static void gpio_nand_io_write(struct gpio_nand *priv, u8 byte)
7758 {
7859 struct gpio_descs *data_gpiods = priv->data_gpiods;
7960 DECLARE_BITMAP(values, BITS_PER_TYPE(byte)) = { byte, };
@@ -81,10 +62,10 @@ static void ams_delta_io_write(struct ams_delta_nand *priv, u8 byte) · 1 unmodified line
8162 gpiod_set_raw_array_value(data_gpiods->ndescs, data_gpiods->desc,
8263 data_gpiods->info, values);
8364
84− ams_delta_write_commit(priv);
65+ gpio_nand_write_commit(priv);
8566 }
8667
87−static void ams_delta_dir_output(struct ams_delta_nand *priv, u8 byte)
68+static void gpio_nand_dir_output(struct gpio_nand *priv, u8 byte)
8869 {
8970 struct gpio_descs *data_gpiods = priv->data_gpiods;
9071 DECLARE_BITMAP(values, BITS_PER_TYPE(byte)) = { byte, };
@@ -94,30 +75,30 @@ static void ams_delta_dir_output(struct ams_delta_nand *priv, u8 byte) · 3 unmodified lines
9475 gpiod_direction_output_raw(data_gpiods->desc[i],
9576 test_bit(i, values));
9677
97− ams_delta_write_commit(priv);
78+ gpio_nand_write_commit(priv);
9879
9980 priv->data_in = false;
10081 }
10182
102−static u8 ams_delta_io_read(struct ams_delta_nand *priv)
83+static u8 gpio_nand_io_read(struct gpio_nand *priv)
10384 {
10485 u8 res;
10586 struct gpio_descs *data_gpiods = priv->data_gpiods;
10687 DECLARE_BITMAP(values, BITS_PER_TYPE(res)) = { 0, };
10788
108− gpiod_set_value(priv->gpiod_nre, 0);
109− ndelay(40);
89+ gpiod_set_value(priv->gpiod_nre, 1);
90+ ndelay(priv->tRP);
11091
11192 gpiod_get_raw_array_value(data_gpiods->ndescs, data_gpiods->desc,
11293 data_gpiods->info, values);
11394
114− gpiod_set_value(priv->gpiod_nre, 1);
95+ gpiod_set_value(priv->gpiod_nre, 0);
11596
11697 res = values[0];
11798 return res;
11899 }
119100
120−static void ams_delta_dir_input(struct ams_delta_nand *priv)
101+static void gpio_nand_dir_input(struct gpio_nand *priv)
121102 {
122103 struct gpio_descs *data_gpiods = priv->data_gpiods;
123104 int i;
@@ -128,68 +109,67 @@ static void ams_delta_dir_input(struct ams_delta_nand *priv) · 4 unmodified lines
128109 priv->data_in = true;
129110 }
130111
131−static void ams_delta_write_buf(struct ams_delta_nand *priv, const u8 *buf,
132− int len)
112+static void gpio_nand_write_buf(struct gpio_nand *priv, const u8 *buf, int len)
133113 {
134114 int i = 0;
135115
136116 if (len > 0 && priv->data_in)
137− ams_delta_dir_output(priv, buf[i++]);
117+ gpio_nand_dir_output(priv, buf[i++]);
138118
139119 while (i < len)
140− ams_delta_io_write(priv, buf[i++]);
120+ priv->io_write(priv, buf[i++]);
141121 }
142122
143−static void ams_delta_read_buf(struct ams_delta_nand *priv, u8 *buf, int len)
123+static void gpio_nand_read_buf(struct gpio_nand *priv, u8 *buf, int len)
144124 {
145125 int i;
146126
147− if (!priv->data_in)
148− ams_delta_dir_input(priv);
127+ if (priv->data_gpiods && !priv->data_in)
128+ gpio_nand_dir_input(priv);
149129
150130 for (i = 0; i < len; i++)
151− buf[i] = ams_delta_io_read(priv);
131+ buf[i] = priv->io_read(priv);
152132 }
153133
154−static void ams_delta_ctrl_cs(struct ams_delta_nand *priv, bool assert)
134+static void gpio_nand_ctrl_cs(struct gpio_nand *priv, bool assert)
155135 {
156− gpiod_set_value(priv->gpiod_nce, assert ? 0 : 1);
136+ gpiod_set_value(priv->gpiod_nce, assert);
157137 }
158138
159−static int ams_delta_exec_op(struct nand_chip *this,
139+static int gpio_nand_exec_op(struct nand_chip *this,
160140 const struct nand_operation *op, bool check_only)
161141 {
162− struct ams_delta_nand *priv = nand_get_controller_data(this);
142+ struct gpio_nand *priv = nand_get_controller_data(this);
163143 const struct nand_op_instr *instr;
164144 int ret = 0;
165145
166146 if (check_only)
167147 return 0;
168148
169− ams_delta_ctrl_cs(priv, 1);
149+ gpio_nand_ctrl_cs(priv, 1);
170150
171151 for (instr = op->instrs; instr < op->instrs + op->ninstrs; instr++) {
172152 switch (instr->type) {
173153 case NAND_OP_CMD_INSTR:
174154 gpiod_set_value(priv->gpiod_cle, 1);
175− ams_delta_write_buf(priv, &instr->ctx.cmd.opcode, 1);
155+ gpio_nand_write_buf(priv, &instr->ctx.cmd.opcode, 1);
176156 gpiod_set_value(priv->gpiod_cle, 0);
177157 break;
178158
179159 case NAND_OP_ADDR_INSTR:
180160 gpiod_set_value(priv->gpiod_ale, 1);
181− ams_delta_write_buf(priv, instr->ctx.addr.addrs,
161+ gpio_nand_write_buf(priv, instr->ctx.addr.addrs,
182162 instr->ctx.addr.naddrs);
183163 gpiod_set_value(priv->gpiod_ale, 0);
184164 break;
185165
186166 case NAND_OP_DATA_IN_INSTR:
187− ams_delta_read_buf(priv, instr->ctx.data.buf.in,
167+ gpio_nand_read_buf(priv, instr->ctx.data.buf.in,
188168 instr->ctx.data.len);
189169 break;
190170
191171 case NAND_OP_DATA_OUT_INSTR:
192− ams_delta_write_buf(priv, instr->ctx.data.buf.out,
172+ gpio_nand_write_buf(priv, instr->ctx.data.buf.out,
193173 instr->ctx.data.len);
194174 break;
195175
@@ -206,28 +186,61 @@ static int ams_delta_exec_op(struct nand_chip *this, · 10 unmodified lines
206186 break;
207187 }
208188
209− ams_delta_ctrl_cs(priv, 0);
189+ gpio_nand_ctrl_cs(priv, 0);
210190
211191 return ret;
212192 }
213193
214−static const struct nand_controller_ops ams_delta_ops = {
215− .exec_op = ams_delta_exec_op,
194+static int gpio_nand_setup_data_interface(struct nand_chip *this, int csline,
195+ const struct nand_data_interface *cf)
196+{
197+ struct gpio_nand *priv = nand_get_controller_data(this);
198+ const struct nand_sdr_timings *sdr = nand_get_sdr_timings(cf);
199+ struct device *dev = &nand_to_mtd(this)->dev;
200+
201+ if (IS_ERR(sdr))
202+ return PTR_ERR(sdr);
203+
204+ if (csline == NAND_DATA_IFACE_CHECK_ONLY)
205+ return 0;
206+
207+ if (priv->gpiod_nre) {
208+ priv->tRP = DIV_ROUND_UP(sdr->tRP_min, 1000);
209+ dev_dbg(dev, "using %u ns read pulse width\n", priv->tRP);
210+ }
211+
212+ priv->tWP = DIV_ROUND_UP(sdr->tWP_min, 1000);
213+ dev_dbg(dev, "using %u ns write pulse width\n", priv->tWP);
214+
215+ return 0;
216+}
217+
218+static const struct nand_controller_ops gpio_nand_ops = {
219+ .exec_op = gpio_nand_exec_op,
220+ .setup_data_interface = gpio_nand_setup_data_interface,
216221 };
217222
218223 /*
219224 * Main initialization routine
220225 */
221−static int ams_delta_init(struct platform_device *pdev)
226+static int gpio_nand_probe(struct platform_device *pdev)
222227 {
223− struct ams_delta_nand *priv;
228+ struct gpio_nand_platdata *pdata = dev_get_platdata(&pdev->dev);
229+ const struct mtd_partition *partitions = NULL;
230+ int num_partitions = 0;
231+ struct gpio_nand *priv;
224232 struct nand_chip *this;
225233 struct mtd_info *mtd;
226− struct gpio_descs *data_gpiods;
234+ int (*probe)(struct platform_device *pdev, struct gpio_nand *priv);
227235 int err = 0;
228236
237+ if (pdata) {
238+ partitions = pdata->parts;
239+ num_partitions = pdata->num_parts;
240+ }
241+
229242 /* Allocate memory for MTD device structure and private data */
230− priv = devm_kzalloc(&pdev->dev, sizeof(struct ams_delta_nand),
243+ priv = devm_kzalloc(&pdev->dev, sizeof(struct gpio_nand),
231244 GFP_KERNEL);
232245 if (!priv)
233246 return -ENOMEM;
@@ -238,6 +251,7 @@ static int ams_delta_init(struct platform_device *pdev) · 4 unmodified lines
238251 mtd->dev.parent = &pdev->dev;
239252
240253 nand_set_controller_data(this, priv);
254+ nand_set_flash_node(this, pdev->dev.of_node);
241255
242256 priv->gpiod_rdy = devm_gpiod_get_optional(&pdev->dev, "rdy", GPIOD_IN);
243257 if (IS_ERR(priv->gpiod_rdy)) {
@@ -251,29 +265,33 @@ static int ams_delta_init(struct platform_device *pdev) · 7 unmodified lines
251265
252266 platform_set_drvdata(pdev, priv);
253267
254− /* Set chip enabled, but */
255− priv->gpiod_nwp = devm_gpiod_get(&pdev->dev, "nwp", GPIOD_OUT_HIGH);
268+ /* Set chip enabled but write protected */
269+ priv->gpiod_nwp = devm_gpiod_get_optional(&pdev->dev, "nwp",
270+ GPIOD_OUT_HIGH);
256271 if (IS_ERR(priv->gpiod_nwp)) {
257272 err = PTR_ERR(priv->gpiod_nwp);
258273 dev_err(&pdev->dev, "NWP GPIO request failed (%d)\n", err);
259274 return err;
260275 }
261276
262− priv->gpiod_nce = devm_gpiod_get(&pdev->dev, "nce", GPIOD_OUT_HIGH);
277+ priv->gpiod_nce = devm_gpiod_get_optional(&pdev->dev, "nce",
278+ GPIOD_OUT_LOW);
263279 if (IS_ERR(priv->gpiod_nce)) {
264280 err = PTR_ERR(priv->gpiod_nce);
265281 dev_err(&pdev->dev, "NCE GPIO request failed (%d)\n", err);
266282 return err;
267283 }
268284
269− priv->gpiod_nre = devm_gpiod_get(&pdev->dev, "nre", GPIOD_OUT_HIGH);
285+ priv->gpiod_nre = devm_gpiod_get_optional(&pdev->dev, "nre",
286+ GPIOD_OUT_LOW);
270287 if (IS_ERR(priv->gpiod_nre)) {
271288 err = PTR_ERR(priv->gpiod_nre);
272289 dev_err(&pdev->dev, "NRE GPIO request failed (%d)\n", err);
273290 return err;
274291 }
275292
276− priv->gpiod_nwe = devm_gpiod_get(&pdev->dev, "nwe", GPIOD_OUT_HIGH);
293+ priv->gpiod_nwe = devm_gpiod_get_optional(&pdev->dev, "nwe",
294+ GPIOD_OUT_LOW);
277295 if (IS_ERR(priv->gpiod_nwe)) {
278296 err = PTR_ERR(priv->gpiod_nwe);
279297 dev_err(&pdev->dev, "NWE GPIO request failed (%d)\n", err);
@@ -295,28 +313,62 @@ static int ams_delta_init(struct platform_device *pdev) · 15 unmodified lines
295313 }
296314
297315 /* Request array of data pins, initialize them as input */
298− data_gpiods = devm_gpiod_get_array(&pdev->dev, "data", GPIOD_IN);
299− if (IS_ERR(data_gpiods)) {
300− err = PTR_ERR(data_gpiods);
316+ priv->data_gpiods = devm_gpiod_get_array_optional(&pdev->dev, "data",
317+ GPIOD_IN);
318+ if (IS_ERR(priv->data_gpiods)) {
319+ err = PTR_ERR(priv->data_gpiods);
301320 dev_err(&pdev->dev, "data GPIO request failed: %d\n", err);
302321 return err;
303322 }
304− priv->data_gpiods = data_gpiods;
305− priv->data_in = true;
323+ if (priv->data_gpiods) {
324+ if (!priv->gpiod_nwe) {
325+ dev_err(&pdev->dev,
326+ "mandatory NWE pin not provided by platform\n");
327+ return -ENODEV;
328+ }
306329
307− /* Initialize the NAND controller object embedded in ams_delta_nand. */
308− priv->base.ops = &ams_delta_ops;
330+ priv->io_read = gpio_nand_io_read;
331+ priv->io_write = gpio_nand_io_write;
332+ priv->data_in = true;
333+ }
334+
335+ if (pdev->id_entry)
336+ probe = (void *) pdev->id_entry->driver_data;
337+ else
338+ probe = of_device_get_match_data(&pdev->dev);
339+ if (probe)
340+ err = probe(pdev, priv);
341+ if (err)
342+ return err;
343+
344+ if (!priv->io_read || !priv->io_write) {
345+ dev_err(&pdev->dev, "incomplete device configuration\n");
346+ return -ENODEV;
347+ }
348+
349+ /* Initialize the NAND controller object embedded in gpio_nand. */
350+ priv->base.ops = &gpio_nand_ops;
309351 nand_controller_init(&priv->base);
310352 this->controller = &priv->base;
311353
354+ /*
355+ * FIXME: We should release write protection only after nand_scan() to
356+ * be on the safe side but we can't do that until we have a generic way
357+ * to assert/deassert WP from the core. Even if the core shouldn't
358+ * write things in the nand_scan() path, it should have control on this
359+ * pin just in case we ever need to disable write protection during
360+ * chip detection/initialization.
361+ */
362+ /* Release write protection */
363+ gpiod_set_value(priv->gpiod_nwp, 0);
364+
312365 /* Scan to find existence of the device */
313366 err = nand_scan(this, 1);
314367 if (err)
315368 return err;
316369
317370 /* Register the partitions */
318− err = mtd_device_register(mtd, partition_info,
319− ARRAY_SIZE(partition_info));
371+ err = mtd_device_register(mtd, partitions, num_partitions);
320372 if (err)
321373 goto err_nand_cleanup;
322374
@@ -331,26 +383,47 @@ err_nand_cleanup: · 8 unmodified lines
331383 /*
332384 * Clean up routine
333385 */
334−static int ams_delta_cleanup(struct platform_device *pdev)
386+static int gpio_nand_remove(struct platform_device *pdev)
335387 {
336− struct ams_delta_nand *priv = platform_get_drvdata(pdev);
388+ struct gpio_nand *priv = platform_get_drvdata(pdev);
337389 struct mtd_info *mtd = nand_to_mtd(&priv->nand_chip);
338390
391+ /* Apply write protection */
392+ gpiod_set_value(priv->gpiod_nwp, 1);
393+
339394 /* Unregister device */
340395 nand_release(mtd_to_nand(mtd));
341396
342397 return 0;
343398 }
344399
345−static struct platform_driver ams_delta_nand_driver = {
346− .probe = ams_delta_init,
347− .remove = ams_delta_cleanup,
400+static const struct of_device_id gpio_nand_of_id_table[] = {
401+ {
402+ /* sentinel */
403+ },
404+};
405+MODULE_DEVICE_TABLE(of, gpio_nand_of_id_table);
406+
407+static const struct platform_device_id gpio_nand_plat_id_table[] = {
408+ {
409+ .name = "ams-delta-nand",
410+ }, {
411+ /* sentinel */
412+ },
413+};
414+MODULE_DEVICE_TABLE(platform, gpio_nand_plat_id_table);
415+
416+static struct platform_driver gpio_nand_driver = {
417+ .probe = gpio_nand_probe,
418+ .remove = gpio_nand_remove,
419+ .id_table = gpio_nand_plat_id_table,
348420 .driver = {
349421 .name = "ams-delta-nand",
422+ .of_match_table = of_match_ptr(gpio_nand_of_id_table),
350423 },
351424 };
352425
353−module_platform_driver(ams_delta_nand_driver);
426+module_platform_driver(gpio_nand_driver);
354427
355428 MODULE_LICENSE("GPL v2");
356429 MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");
drivers/mtd/nand/raw/brcmnand/brcmnand.c+287−6
@@ -102,6 +102,45 @@ struct brcm_nand_dma_desc { · 101 unmodified lines
102102 #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY)
103103 #define NAND_POLL_STATUS_TIMEOUT_MS 100
104104
105+#define EDU_CMD_WRITE 0x00
106+#define EDU_CMD_READ 0x01
107+#define EDU_STATUS_ACTIVE BIT(0)
108+#define EDU_ERR_STATUS_ERRACK BIT(0)
109+#define EDU_DONE_MASK GENMASK(1, 0)
110+
111+#define EDU_CONFIG_MODE_NAND BIT(0)
112+#define EDU_CONFIG_SWAP_BYTE BIT(1)
113+#ifdef CONFIG_CPU_BIG_ENDIAN
114+#define EDU_CONFIG_SWAP_CFG EDU_CONFIG_SWAP_BYTE
115+#else
116+#define EDU_CONFIG_SWAP_CFG 0
117+#endif
118+
119+/* edu registers */
120+enum edu_reg {
121+ EDU_CONFIG = 0,
122+ EDU_DRAM_ADDR,
123+ EDU_EXT_ADDR,
124+ EDU_LENGTH,
125+ EDU_CMD,
126+ EDU_STOP,
127+ EDU_STATUS,
128+ EDU_DONE,
129+ EDU_ERR_STATUS,
130+};
131+
132+static const u16 edu_regs[] = {
133+ [EDU_CONFIG] = 0x00,
134+ [EDU_DRAM_ADDR] = 0x04,
135+ [EDU_EXT_ADDR] = 0x08,
136+ [EDU_LENGTH] = 0x0c,
137+ [EDU_CMD] = 0x10,
138+ [EDU_STOP] = 0x14,
139+ [EDU_STATUS] = 0x18,
140+ [EDU_DONE] = 0x1c,
141+ [EDU_ERR_STATUS] = 0x20,
142+};
143+
105144 /* flash_dma registers */
106145 enum flash_dma_reg {
107146 FLASH_DMA_REVISION = 0,
@@ -167,6 +206,8 @@ enum { · 59 unmodified lines
167206 BRCMNAND_HAS_WP = BIT(3),
168207 };
169208
209+struct brcmnand_host;
210+
170211 struct brcmnand_controller {
171212 struct device *dev;
172213 struct nand_controller controller;
@@ -185,17 +226,32 @@ struct brcmnand_controller { · 12 unmodified lines
185226
186227 int cmd_pending;
187228 bool dma_pending;
229+ bool edu_pending;
188230 struct completion done;
189231 struct completion dma_done;
232+ struct completion edu_done;
190233
191234 /* List of NAND hosts (one for each chip-select) */
192235 struct list_head host_list;
193236
237+ /* EDU info, per-transaction */
238+ const u16 *edu_offsets;
239+ void __iomem *edu_base;
240+ int edu_irq;
241+ int edu_count;
242+ u64 edu_dram_addr;
243+ u32 edu_ext_addr;
244+ u32 edu_cmd;
245+ u32 edu_config;
246+
194247 /* flash_dma reg */
195248 const u16 *flash_dma_offsets;
196249 struct brcm_nand_dma_desc *dma_desc;
197250 dma_addr_t dma_pa;
198251
252+ int (*dma_trans)(struct brcmnand_host *host, u64 addr, u32 *buf,
253+ u32 len, u8 dma_cmd);
254+
199255 /* in-memory cache of the FLASH_CACHE, used only for some commands */
200256 u8 flash_cache[FC_BYTES];
201257
@@ -216,6 +272,7 @@ struct brcmnand_controller { · 14 unmodified lines
216272 u32 nand_cs_nand_xor;
217273 u32 corr_stat_threshold;
218274 u32 flash_dma_mode;
275+ u32 flash_edu_mode;
219276 bool pio_poll_mode;
220277 };
221278
@@ -657,6 +714,22 @@ static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, · 435 unmodified lines
657714 __raw_writel(val, ctrl->nand_fc + word * 4);
658715 }
659716
717+static inline void edu_writel(struct brcmnand_controller *ctrl,
718+ enum edu_reg reg, u32 val)
719+{
720+ u16 offs = ctrl->edu_offsets[reg];
721+
722+ brcmnand_writel(val, ctrl->edu_base + offs);
723+}
724+
725+static inline u32 edu_readl(struct brcmnand_controller *ctrl,
726+ enum edu_reg reg)
727+{
728+ u16 offs = ctrl->edu_offsets[reg];
729+
730+ return brcmnand_readl(ctrl->edu_base + offs);
731+}
732+
660733 static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl)
661734 {
662735
@@ -926,6 +999,16 @@ static inline bool has_flash_dma(struct brcmnand_controller *ctrl) · 263 unmodified lines
926999 return ctrl->flash_dma_base;
9271000 }
9281001
1002+static inline bool has_edu(struct brcmnand_controller *ctrl)
1003+{
1004+ return ctrl->edu_base;
1005+}
1006+
1007+static inline bool use_dma(struct brcmnand_controller *ctrl)
1008+{
1009+ return has_flash_dma(ctrl) || has_edu(ctrl);
1010+}
1011+
9291012 static inline void disable_ctrl_irqs(struct brcmnand_controller *ctrl)
9301013 {
9311014 if (ctrl->pio_poll_mode)
@@ -1299,6 +1382,52 @@ static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, · 367 unmodified lines
12991382 return tbytes;
13001383 }
13011384
1385+static void brcmnand_edu_init(struct brcmnand_controller *ctrl)
1386+{
1387+ /* initialize edu */
1388+ edu_writel(ctrl, EDU_ERR_STATUS, 0);
1389+ edu_readl(ctrl, EDU_ERR_STATUS);
1390+ edu_writel(ctrl, EDU_DONE, 0);
1391+ edu_writel(ctrl, EDU_DONE, 0);
1392+ edu_writel(ctrl, EDU_DONE, 0);
1393+ edu_writel(ctrl, EDU_DONE, 0);
1394+ edu_readl(ctrl, EDU_DONE);
1395+}
1396+
1397+/* edu irq */
1398+static irqreturn_t brcmnand_edu_irq(int irq, void *data)
1399+{
1400+ struct brcmnand_controller *ctrl = data;
1401+
1402+ if (ctrl->edu_count) {
1403+ ctrl->edu_count--;
1404+ while (!(edu_readl(ctrl, EDU_DONE) & EDU_DONE_MASK))
1405+ udelay(1);
1406+ edu_writel(ctrl, EDU_DONE, 0);
1407+ edu_readl(ctrl, EDU_DONE);
1408+ }
1409+
1410+ if (ctrl->edu_count) {
1411+ ctrl->edu_dram_addr += FC_BYTES;
1412+ ctrl->edu_ext_addr += FC_BYTES;
1413+
1414+ edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr);
1415+ edu_readl(ctrl, EDU_DRAM_ADDR);
1416+ edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr);
1417+ edu_readl(ctrl, EDU_EXT_ADDR);
1418+
1419+ mb(); /* flush previous writes */
1420+ edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd);
1421+ edu_readl(ctrl, EDU_CMD);
1422+
1423+ return IRQ_HANDLED;
1424+ }
1425+
1426+ complete(&ctrl->edu_done);
1427+
1428+ return IRQ_HANDLED;
1429+}
1430+
13021431 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
13031432 {
13041433 struct brcmnand_controller *ctrl = data;
@@ -1307,6 +1436,16 @@ static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data) · 2 unmodified lines
13071436 if (ctrl->dma_pending)
13081437 return IRQ_HANDLED;
13091438
1439+ /* check if you need to piggy back on the ctrlrdy irq */
1440+ if (ctrl->edu_pending) {
1441+ if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0))
1442+ /* Discard interrupts while using dedicated edu irq */
1443+ return IRQ_HANDLED;
1444+
1445+ /* no registered edu irq, call handler */
1446+ return brcmnand_edu_irq(irq, data);
1447+ }
1448+
13101449 complete(&ctrl->done);
13111450 return IRQ_HANDLED;
13121451 }
@@ -1644,6 +1783,81 @@ static void brcmnand_write_buf(struct nand_chip *chip, const uint8_t *buf, · 331 unmodified lines
16441783 }
16451784 }
16461785
1786+/**
1787+ * Kick EDU engine
1788+ */
1789+static int brcmnand_edu_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1790+ u32 len, u8 cmd)
1791+{
1792+ struct brcmnand_controller *ctrl = host->ctrl;
1793+ unsigned long timeo = msecs_to_jiffies(200);
1794+ int ret = 0;
1795+ int dir = (cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
1796+ u8 edu_cmd = (cmd == CMD_PAGE_READ ? EDU_CMD_READ : EDU_CMD_WRITE);
1797+ unsigned int trans = len >> FC_SHIFT;
1798+ dma_addr_t pa;
1799+
1800+ pa = dma_map_single(ctrl->dev, buf, len, dir);
1801+ if (dma_mapping_error(ctrl->dev, pa)) {
1802+ dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n");
1803+ return -ENOMEM;
1804+ }
1805+
1806+ ctrl->edu_pending = true;
1807+ ctrl->edu_dram_addr = pa;
1808+ ctrl->edu_ext_addr = addr;
1809+ ctrl->edu_cmd = edu_cmd;
1810+ ctrl->edu_count = trans;
1811+
1812+ edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr);
1813+ edu_readl(ctrl, EDU_DRAM_ADDR);
1814+ edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr);
1815+ edu_readl(ctrl, EDU_EXT_ADDR);
1816+ edu_writel(ctrl, EDU_LENGTH, FC_BYTES);
1817+ edu_readl(ctrl, EDU_LENGTH);
1818+
1819+ /* Start edu engine */
1820+ mb(); /* flush previous writes */
1821+ edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd);
1822+ edu_readl(ctrl, EDU_CMD);
1823+
1824+ if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) {
1825+ dev_err(ctrl->dev,
1826+ "timeout waiting for EDU; status %#x, error status %#x\n",
1827+ edu_readl(ctrl, EDU_STATUS),
1828+ edu_readl(ctrl, EDU_ERR_STATUS));
1829+ }
1830+
1831+ dma_unmap_single(ctrl->dev, pa, len, dir);
1832+
1833+ /* for program page check NAND status */
1834+ if (((brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1835+ INTFC_FLASH_STATUS) & NAND_STATUS_FAIL) &&
1836+ edu_cmd == EDU_CMD_WRITE) {
1837+ dev_info(ctrl->dev, "program failed at %llx\n",
1838+ (unsigned long long)addr);
1839+ ret = -EIO;
1840+ }
1841+
1842+ /* Make sure the EDU status is clean */
1843+ if (edu_readl(ctrl, EDU_STATUS) & EDU_STATUS_ACTIVE)
1844+ dev_warn(ctrl->dev, "EDU still active: %#x\n",
1845+ edu_readl(ctrl, EDU_STATUS));
1846+
1847+ if (unlikely(edu_readl(ctrl, EDU_ERR_STATUS) & EDU_ERR_STATUS_ERRACK)) {
1848+ dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n",
1849+ (unsigned long long)addr);
1850+ ret = -EIO;
1851+ }
1852+
1853+ ctrl->edu_pending = false;
1854+ brcmnand_edu_init(ctrl);
1855+ edu_writel(ctrl, EDU_STOP, 0); /* force stop */
1856+ edu_readl(ctrl, EDU_STOP);
1857+
1858+ return ret;
1859+}
1860+
16471861 /**
16481862 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
16491863 * following ahead of time:
@@ -1850,9 +2064,11 @@ static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip, · 200 unmodified lines
18502064 try_dmaread:
18512065 brcmnand_clear_ecc_addr(ctrl);
18522066
1853− if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1854− err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1855− CMD_PAGE_READ);
2067+ if (ctrl->dma_trans && !oob && flash_dma_buf_ok(buf)) {
2068+ err = ctrl->dma_trans(host, addr, buf,
2069+ trans * FC_BYTES,
2070+ CMD_PAGE_READ);
2071+
18562072 if (err) {
18572073 if (mtd_is_bitflip_or_eccerr(err))
18582074 err_addr = addr;
@@ -1988,10 +2204,12 @@ static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip, · 129 unmodified lines
19882204 for (i = 0; i < ctrl->max_oob; i += 4)
19892205 oob_reg_write(ctrl, i, 0xffffffff);
19902206
1991− if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1992− if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1993− mtd->writesize, CMD_PROGRAM_PAGE))
2207+ if (use_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
2208+ if (ctrl->dma_trans(host, addr, (u32 *)buf, mtd->writesize,
2209+ CMD_PROGRAM_PAGE))
2210+
19942211 ret = -EIO;
2212+
19952213 goto out;
19962214 }
19972215
@@ -2494,6 +2712,8 @@ static int brcmnand_suspend(struct device *dev) · 496 unmodified lines
24942712
24952713 if (has_flash_dma(ctrl))
24962714 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2715+ else if (has_edu(ctrl))
2716+ ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG);
24972717
24982718 return 0;
24992719 }
@@ -2508,6 +2728,14 @@ static int brcmnand_resume(struct device *dev) · 8 unmodified lines
25082728 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
25092729 }
25102730
2731+ if (has_edu(ctrl))
2732+ ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG);
2733+ else {
2734+ edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config);
2735+ edu_readl(ctrl, EDU_CONFIG);
2736+ brcmnand_edu_init(ctrl);
2737+ }
2738+
25112739 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
25122740 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
25132741 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
@@ -2553,6 +2781,49 @@ MODULE_DEVICE_TABLE(of, brcmnand_of_match); · 39 unmodified lines
25532781 /***********************************************************************
25542782 * Platform driver setup (per controller)
25552783 ***********************************************************************/
2784+static int brcmnand_edu_setup(struct platform_device *pdev)
2785+{
2786+ struct device *dev = &pdev->dev;
2787+ struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2788+ struct resource *res;
2789+ int ret;
2790+
2791+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-edu");
2792+ if (res) {
2793+ ctrl->edu_base = devm_ioremap_resource(dev, res);
2794+ if (IS_ERR(ctrl->edu_base))
2795+ return PTR_ERR(ctrl->edu_base);
2796+
2797+ ctrl->edu_offsets = edu_regs;
2798+
2799+ edu_writel(ctrl, EDU_CONFIG, EDU_CONFIG_MODE_NAND |
2800+ EDU_CONFIG_SWAP_CFG);
2801+ edu_readl(ctrl, EDU_CONFIG);
2802+
2803+ /* initialize edu */
2804+ brcmnand_edu_init(ctrl);
2805+
2806+ ctrl->edu_irq = platform_get_irq_optional(pdev, 1);
2807+ if (ctrl->edu_irq < 0) {
2808+ dev_warn(dev,
2809+ "FLASH EDU enabled, using ctlrdy irq\n");
2810+ } else {
2811+ ret = devm_request_irq(dev, ctrl->edu_irq,
2812+ brcmnand_edu_irq, 0,
2813+ "brcmnand-edu", ctrl);
2814+ if (ret < 0) {
2815+ dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n",
2816+ ctrl->edu_irq, ret);
2817+ return ret;
2818+ }
2819+
2820+ dev_info(dev, "FLASH EDU enabled using irq %u\n",
2821+ ctrl->edu_irq);
2822+ }
2823+ }
2824+
2825+ return 0;
2826+}
25562827
25572828 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
25582829 {
@@ -2578,6 +2849,7 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) · 19 unmodified lines
25782849
25792850 init_completion(&ctrl->done);
25802851 init_completion(&ctrl->dma_done);
2852+ init_completion(&ctrl->edu_done);
25812853 nand_controller_init(&ctrl->controller);
25822854 ctrl->controller.ops = &brcmnand_controller_ops;
25832855 INIT_LIST_HEAD(&ctrl->host_list);
@@ -2675,6 +2947,15 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) · 91 unmodified lines
26752947 }
26762948
26772949 dev_info(dev, "enabling FLASH_DMA\n");
2950+ /* set flash dma transfer function to call */
2951+ ctrl->dma_trans = brcmnand_dma_trans;
2952+ } else {
2953+ ret = brcmnand_edu_setup(pdev);
2954+ if (ret < 0)
2955+ goto err;
2956+
2957+ /* set edu transfer function to call */
2958+ ctrl->dma_trans = brcmnand_edu_trans;
26782959 }
26792960
26802961 /* Disable automatic device ID config, direct addressing */
drivers/mtd/nand/raw/cadence-nand-controller.c+20−14
@@ -30,7 +30,6 @@ · 29 unmodified lines
3030 * Generic mode is used for executing rest of commands.
3131 */
3232
33−#define MAX_OOB_SIZE_PER_SECTOR 32
3433 #define MAX_ADDRESS_CYC 6
3534 #define MAX_ERASE_ADDRESS_CYC 3
3635 #define MAX_DATA_SIZE 0xFFFC
@@ -190,6 +189,7 @@ · 153 unmodified lines
190189
191190 /* BCH Engine identification register 3. */
192191 #define BCH_CFG_3 0x844
192+#define BCH_CFG_3_METADATA_SIZE GENMASK(23, 16)
193193
194194 /* Ready/Busy# line status. */
195195 #define RBN_SETINGS 0x1004
@@ -499,6 +499,7 @@ struct cdns_nand_ctrl { · 303 unmodified lines
499499
500500 unsigned long assigned_cs;
501501 struct list_head chips;
502+ u8 bch_metadata_size;
502503 };
503504
504505 struct cdns_nand_chip {
@@ -997,6 +998,7 @@ static int cadence_nand_cdma_send(struct cdns_nand_ctrl *cdns_ctrl, · 492 unmodified lines
997998 return status;
998999
9991000 cadence_nand_reset_irq(cdns_ctrl);
1001+ reinit_completion(&cdns_ctrl->complete);
10001002
10011003 writel_relaxed((u32)cdns_ctrl->dma_cdma_desc,
10021004 cdns_ctrl->reg + CMD_REG2);
@@ -1077,6 +1079,14 @@ static int cadence_nand_read_bch_caps(struct cdns_nand_ctrl *cdns_ctrl) · 74 unmodified lines
10771079 int max_step_size = 0, nstrengths, i;
10781080 u32 reg;
10791081
1082+ reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_3);
1083+ cdns_ctrl->bch_metadata_size = FIELD_GET(BCH_CFG_3_METADATA_SIZE, reg);
1084+ if (cdns_ctrl->bch_metadata_size < 4) {
1085+ dev_err(cdns_ctrl->dev,
1086+ "Driver needs at least 4 bytes of BCH meta data\n");
1087+ return -EIO;
1088+ }
1089+
10801090 reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_0);
10811091 cdns_ctrl->ecc_strengths[0] = FIELD_GET(BCH_CFG_0_CORR_CAP_0, reg);
10821092 cdns_ctrl->ecc_strengths[1] = FIELD_GET(BCH_CFG_0_CORR_CAP_1, reg);
@@ -1170,7 +1180,8 @@ static int cadence_nand_hw_init(struct cdns_nand_ctrl *cdns_ctrl) · 87 unmodified lines
11701180 writel_relaxed(0xFFFFFFFF, cdns_ctrl->reg + INTR_STATUS);
11711181
11721182 cadence_nand_get_caps(cdns_ctrl);
1173− cadence_nand_read_bch_caps(cdns_ctrl);
1183+ if (cadence_nand_read_bch_caps(cdns_ctrl))
1184+ return -EIO;
11741185
11751186 /*
11761187 * Set IO width access to 8.
@@ -2585,9 +2596,8 @@ int cadence_nand_attach_chip(struct nand_chip *chip) · 1408 unmodified lines
25852596 {
25862597 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
25872598 struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
2588− u32 ecc_size = cdns_chip->sector_count * chip->ecc.bytes;
2599+ u32 ecc_size;
25892600 struct mtd_info *mtd = nand_to_mtd(chip);
2590− u32 max_oob_data_size;
25912601 int ret;
25922602
25932603 if (chip->options & NAND_BUSWIDTH_16) {
@@ -2603,12 +2613,9 @@ int cadence_nand_attach_chip(struct nand_chip *chip) · 9 unmodified lines
26032613 chip->options |= NAND_NO_SUBPAGE_WRITE;
26042614
26052615 cdns_chip->bbm_offs = chip->badblockpos;
2606− if (chip->options & NAND_BUSWIDTH_16) {
2607− cdns_chip->bbm_offs &= ~0x01;
2608− cdns_chip->bbm_len = 2;
2609− } else {
2610− cdns_chip->bbm_len = 1;
2611− }
2616+ cdns_chip->bbm_offs &= ~0x01;
2617+ /* this value should be even number */
2618+ cdns_chip->bbm_len = 2;
26122619
26132620 ret = nand_ecc_choose_conf(chip,
26142621 &cdns_ctrl->ecc_caps,
@@ -2625,13 +2632,12 @@ int cadence_nand_attach_chip(struct nand_chip *chip) · 10 unmodified lines
26252632 /* Error correction configuration. */
26262633 cdns_chip->sector_size = chip->ecc.size;
26272634 cdns_chip->sector_count = mtd->writesize / cdns_chip->sector_size;
2635+ ecc_size = cdns_chip->sector_count * chip->ecc.bytes;
26282636
26292637 cdns_chip->avail_oob_size = mtd->oobsize - ecc_size;
26302638
2631− max_oob_data_size = MAX_OOB_SIZE_PER_SECTOR;
2632−
2633− if (cdns_chip->avail_oob_size > max_oob_data_size)
2634− cdns_chip->avail_oob_size = max_oob_data_size;
2639+ if (cdns_chip->avail_oob_size > cdns_ctrl->bch_metadata_size)
2640+ cdns_chip->avail_oob_size = cdns_ctrl->bch_metadata_size;
26352641
26362642 if ((cdns_chip->avail_oob_size + cdns_chip->bbm_len + ecc_size)
26372643 > mtd->oobsize)
drivers/mtd/nand/raw/denali.c+1−0
@@ -1317,6 +1317,7 @@ int denali_init(struct denali_controller *denali) · 1316 unmodified lines
13171317 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
13181318 iowrite32(ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
13191319 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
1320+ iowrite32(WRITE_PROTECT__FLAG, denali->reg + WRITE_PROTECT);
13201321
13211322 denali_clear_irq_all(denali);
13221323
drivers/mtd/nand/raw/denali.h+1−1
@@ -328,7 +328,7 @@ struct denali_chip { · 327 unmodified lines
328328 struct nand_chip chip;
329329 struct list_head node;
330330 unsigned int nsels;
331− struct denali_chip_sel sels[0];
331+ struct denali_chip_sel sels[];
332332 };
333333
334334 /**
drivers/mtd/nand/raw/diskonchip.c+2−2
@@ -1169,7 +1169,7 @@ static inline int __init inftl_partscan(struct mtd_info *mtd, struct mtd_partiti · 1168 unmodified lines
11691169 " NoOfBootImageBlocks = %d\n"
11701170 " NoOfBinaryPartitions = %d\n"
11711171 " NoOfBDTLPartitions = %d\n"
1172− " BlockMultiplerBits = %d\n"
1172+ " BlockMultiplierBits = %d\n"
11731173 " FormatFlgs = %d\n"
11741174 " OsakVersion = %d.%d.%d.%d\n"
11751175 " PercentUsed = %d\n",
@@ -1482,7 +1482,7 @@ static int __init doc_probe(unsigned long physadr) · 306 unmodified lines
14821482 break;
14831483 case DOC_ChipID_DocMilPlus32:
14841484 pr_err("DiskOnChip Millennium Plus 32MB is not supported, ignoring.\n");
1485− /* fall through */
1485+ fallthrough;
14861486 default:
14871487 ret = -ENODEV;
14881488 goto notfound;
drivers/mtd/nand/raw/fsl_elbc_nand.c+1−2
@@ -324,8 +324,7 @@ static void fsl_elbc_cmdfunc(struct nand_chip *chip, unsigned int command, · 323 unmodified lines
324324 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
325325 case NAND_CMD_READ1:
326326 column += 256;
327−
328− /* fall-through */
327+ fallthrough;
329328 case NAND_CMD_READ0:
330329 dev_dbg(priv->dev,
331330 "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c+11−10
@@ -1148,20 +1148,21 @@ static int acquire_dma_channels(struct gpmi_nand_data *this) · 1147 unmodified lines
11481148 {
11491149 struct platform_device *pdev = this->pdev;
11501150 struct dma_chan *dma_chan;
1151+ int ret = 0;
11511152
11521153 /* request dma channel */
1153− dma_chan = dma_request_slave_channel(&pdev->dev, "rx-tx");
1154− if (!dma_chan) {
1155− dev_err(this->dev, "Failed to request DMA channel.\n");
1156− goto acquire_err;
1154+ dma_chan = dma_request_chan(&pdev->dev, "rx-tx");
1155+ if (IS_ERR(dma_chan)) {
1156+ ret = PTR_ERR(dma_chan);
1157+ if (ret != -EPROBE_DEFER)
1158+ dev_err(this->dev, "DMA channel request failed: %d\n",
1159+ ret);
1160+ release_dma_channels(this);
1161+ } else {
1162+ this->dma_chans[0] = dma_chan;
11571163 }
11581164
1159− this->dma_chans[0] = dma_chan;
1160− return 0;
1161−
1162−acquire_err:
1163− release_dma_channels(this);
1164− return -EINVAL;
1165+ return ret;
11651166 }
11661167
11671168 static int gpmi_get_clks(struct gpmi_nand_data *this)
drivers/mtd/nand/raw/ingenic/Kconfig+1−0
@@ -1,6 +1,7 @@
11 # SPDX-License-Identifier: GPL-2.0-only
22 config MTD_NAND_JZ4780
33 tristate "JZ4780 NAND controller"
4+ depends on MIPS || COMPILE_TEST
45 depends on JZ4780_NEMC
56 help
67 Enables support for NAND Flash connected to the NEMC on JZ4780 SoC
drivers/mtd/nand/raw/ingenic/ingenic_ecc.c+1−3
@@ -124,7 +124,6 @@ int ingenic_ecc_probe(struct platform_device *pdev) · 123 unmodified lines
124124 {
125125 struct device *dev = &pdev->dev;
126126 struct ingenic_ecc *ecc;
127− struct resource *res;
128127
129128 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
130129 if (!ecc)
@@ -134,8 +133,7 @@ int ingenic_ecc_probe(struct platform_device *pdev) · 3 unmodified lines
134133 if (!ecc->ops)
135134 return -EINVAL;
136135
137− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
138− ecc->base = devm_ioremap_resource(dev, res);
136+ ecc->base = devm_platform_ioremap_resource(pdev, 0);
139137 if (IS_ERR(ecc->base))
140138 return PTR_ERR(ecc->base);
141139
drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c+1−1
@@ -253,7 +253,7 @@ static int ingenic_nand_attach_chip(struct nand_chip *chip) · 252 unmodified lines
253253 chip->ecc.hwctl = ingenic_nand_ecc_hwctl;
254254 chip->ecc.calculate = ingenic_nand_ecc_calculate;
255255 chip->ecc.correct = ingenic_nand_ecc_correct;
256− /* fall through */
256+ fallthrough;
257257 case NAND_ECC_SOFT:
258258 dev_info(nfc->dev, "using %s (strength %d, size %d, bytes %d)\n",
259259 (nfc->ecc) ? "hardware ECC" : "software ECC",
drivers/mtd/nand/raw/ingenic/jz4725b_bch.c+2−2
@@ -145,10 +145,10 @@ static void jz4725b_bch_read_parity(struct ingenic_ecc *bch, u8 *buf, · 144 unmodified lines
145145 switch (size8) {
146146 case 3:
147147 dest8[2] = (val >> 16) & 0xff;
148− /* fall-through */
148+ fallthrough;
149149 case 2:
150150 dest8[1] = (val >> 8) & 0xff;
151− /* fall-through */
151+ fallthrough;
152152 case 1:
153153 dest8[0] = val & 0xff;
154154 break;
drivers/mtd/nand/raw/ingenic/jz4780_bch.c+2−2
@@ -123,10 +123,10 @@ static void jz4780_bch_read_parity(struct ingenic_ecc *bch, void *buf, · 122 unmodified lines
123123 switch (size8) {
124124 case 3:
125125 dest8[2] = (val >> 16) & 0xff;
126− /* fall through */
126+ fallthrough;
127127 case 2:
128128 dest8[1] = (val >> 8) & 0xff;
129− /* fall through */
129+ fallthrough;
130130 case 1:
131131 dest8[0] = val & 0xff;
132132 break;
drivers/mtd/nand/raw/internals.h+1−0
@@ -30,6 +30,7 @@ · 29 unmodified lines
3030 #define NAND_MFR_SAMSUNG 0xec
3131 #define NAND_MFR_SANDISK 0x45
3232 #define NAND_MFR_STMICRO 0x20
33+/* Kioxia is new name of Toshiba memory. */
3334 #define NAND_MFR_TOSHIBA 0x98
3435 #define NAND_MFR_WINBOND 0xef
3536
drivers/mtd/nand/raw/marvell_nand.c+28−12
@@ -334,7 +334,7 @@ struct marvell_nand_chip { · 333 unmodified lines
334334 int addr_cyc;
335335 int selected_die;
336336 unsigned int nsels;
337− struct marvell_nand_chip_sel sels[0];
337+ struct marvell_nand_chip_sel sels[];
338338 };
339339
340340 static inline struct marvell_nand_chip *to_marvell_nand(struct nand_chip *chip)
@@ -2743,16 +2743,21 @@ static int marvell_nfc_init_dma(struct marvell_nfc *nfc) · 2402 unmodified lines
27432743 if (ret)
27442744 return ret;
27452745
2746− nfc->dma_chan = dma_request_slave_channel(nfc->dev, "data");
2747− if (!nfc->dma_chan) {
2748− dev_err(nfc->dev,
2749− "Unable to request data DMA channel\n");
2750− return -ENODEV;
2746+ nfc->dma_chan = dma_request_chan(nfc->dev, "data");
2747+ if (IS_ERR(nfc->dma_chan)) {
2748+ ret = PTR_ERR(nfc->dma_chan);
2749+ nfc->dma_chan = NULL;
2750+ if (ret != -EPROBE_DEFER)
2751+ dev_err(nfc->dev, "DMA channel request failed: %d\n",
2752+ ret);
2753+ return ret;
27512754 }
27522755
27532756 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2754− if (!r)
2755− return -ENXIO;
2757+ if (!r) {
2758+ ret = -ENXIO;
2759+ goto release_channel;
2760+ }
27562761
27572762 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
27582763 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
@@ -2763,7 +2768,7 @@ static int marvell_nfc_init_dma(struct marvell_nfc *nfc) · 4 unmodified lines
27632768 ret = dmaengine_slave_config(nfc->dma_chan, &config);
27642769 if (ret < 0) {
27652770 dev_err(nfc->dev, "Failed to configure DMA channel\n");
2766− return ret;
2771+ goto release_channel;
27672772 }
27682773
27692774 /*
@@ -2773,12 +2778,20 @@ static int marvell_nfc_init_dma(struct marvell_nfc *nfc) · 3 unmodified lines
27732778 * the provided buffer.
27742779 */
27752780 nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA);
2776− if (!nfc->dma_buf)
2777− return -ENOMEM;
2781+ if (!nfc->dma_buf) {
2782+ ret = -ENOMEM;
2783+ goto release_channel;
2784+ }
27782785
27792786 nfc->use_dma = true;
27802787
27812788 return 0;
2789+
2790+release_channel:
2791+ dma_release_channel(nfc->dma_chan);
2792+ nfc->dma_chan = NULL;
2793+
2794+ return ret;
27822795 }
27832796
27842797 static void marvell_nfc_reset(struct marvell_nfc *nfc)
@@ -2920,10 +2933,13 @@ static int marvell_nfc_probe(struct platform_device *pdev) · 135 unmodified lines
29202933
29212934 ret = marvell_nand_chips_init(dev, nfc);
29222935 if (ret)
2923− goto unprepare_reg_clk;
2936+ goto release_dma;
29242937
29252938 return 0;
29262939
2940+release_dma:
2941+ if (nfc->use_dma)
2942+ dma_release_channel(nfc->dma_chan);
29272943 unprepare_reg_clk:
29282944 clk_disable_unprepare(nfc->reg_clk);
29292945 unprepare_core_clk:
drivers/mtd/nand/raw/meson_nand.c+1−1
@@ -118,7 +118,7 @@ struct meson_nfc_nand_chip { · 117 unmodified lines
118118 u8 *data_buf;
119119 __le64 *info_buf;
120120 u32 nsels;
121− u8 sels[0];
121+ u8 sels[];
122122 };
123123
124124 struct meson_nand_ecc {
drivers/mtd/nand/raw/mtk_nand.c+1−1
@@ -131,7 +131,7 @@ struct mtk_nfc_nand_chip { · 130 unmodified lines
131131 u32 spare_per_sector;
132132
133133 int nsels;
134− u8 sels[0];
134+ u8 sels[];
135135 /* nothing after this field */
136136 };
137137
drivers/mtd/nand/raw/nand_base.c+58−13
@@ -683,7 +683,12 @@ int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms) · 682 unmodified lines
683683 if (ret)
684684 return ret;
685685
686− timeout_ms = jiffies + msecs_to_jiffies(timeout_ms);
686+ /*
687+ * +1 below is necessary because if we are now in the last fraction
688+ * of jiffy and msecs_to_jiffies is 1 then we will wait only that
689+ * small jiffy fraction - possibly leading to false timeout
690+ */
691+ timeout_ms = jiffies + msecs_to_jiffies(timeout_ms) + 1;
687692 do {
688693 ret = nand_read_data_op(chip, &status, sizeof(status), true);
689694 if (ret)
@@ -4321,16 +4326,22 @@ static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) · 3631 unmodified lines
43214326 /**
43224327 * nand_suspend - [MTD Interface] Suspend the NAND flash
43234328 * @mtd: MTD device structure
4329+ *
4330+ * Returns 0 for success or negative error code otherwise.
43244331 */
43254332 static int nand_suspend(struct mtd_info *mtd)
43264333 {
43274334 struct nand_chip *chip = mtd_to_nand(mtd);
4335+ int ret = 0;
43284336
43294337 mutex_lock(&chip->lock);
4330− chip->suspended = 1;
4338+ if (chip->suspend)
4339+ ret = chip->suspend(chip);
4340+ if (!ret)
4341+ chip->suspended = 1;
43314342 mutex_unlock(&chip->lock);
43324343
4333− return 0;
4344+ return ret;
43344345 }
43354346
43364347 /**
@@ -4342,11 +4353,14 @@ static void nand_resume(struct mtd_info *mtd) · 5 unmodified lines
43424353 struct nand_chip *chip = mtd_to_nand(mtd);
43434354
43444355 mutex_lock(&chip->lock);
4345− if (chip->suspended)
4356+ if (chip->suspended) {
4357+ if (chip->resume)
4358+ chip->resume(chip);
43464359 chip->suspended = 0;
4347− else
4360+ } else {
43484361 pr_err("%s called for a chip which is not in suspended state\n",
43494362 __func__);
4363+ }
43504364 mutex_unlock(&chip->lock);
43514365 }
43524366
@@ -4360,6 +4374,38 @@ static void nand_shutdown(struct mtd_info *mtd) · 7 unmodified lines
43604374 nand_suspend(mtd);
43614375 }
43624376
4377+/**
4378+ * nand_lock - [MTD Interface] Lock the NAND flash
4379+ * @mtd: MTD device structure
4380+ * @ofs: offset byte address
4381+ * @len: number of bytes to lock (must be a multiple of block/page size)
4382+ */
4383+static int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
4384+{
4385+ struct nand_chip *chip = mtd_to_nand(mtd);
4386+
4387+ if (!chip->lock_area)
4388+ return -ENOTSUPP;
4389+
4390+ return chip->lock_area(chip, ofs, len);
4391+}
4392+
4393+/**
4394+ * nand_unlock - [MTD Interface] Unlock the NAND flash
4395+ * @mtd: MTD device structure
4396+ * @ofs: offset byte address
4397+ * @len: number of bytes to unlock (must be a multiple of block/page size)
4398+ */
4399+static int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
4400+{
4401+ struct nand_chip *chip = mtd_to_nand(mtd);
4402+
4403+ if (!chip->unlock_area)
4404+ return -ENOTSUPP;
4405+
4406+ return chip->unlock_area(chip, ofs, len);
4407+}
4408+
43634409 /* Set default functions */
43644410 static void nand_set_defaults(struct nand_chip *chip)
43654411 {
@@ -5591,8 +5637,7 @@ static int nand_scan_tail(struct nand_chip *chip) · 1225 unmodified lines
55915637 }
55925638 if (!ecc->read_page)
55935639 ecc->read_page = nand_read_page_hwecc_oob_first;
5594− /* fall through */
5595−
5640+ fallthrough;
55965641 case NAND_ECC_HW:
55975642 /* Use standard hwecc read page function? */
55985643 if (!ecc->read_page)
@@ -5611,8 +5656,7 @@ static int nand_scan_tail(struct nand_chip *chip) · 12 unmodified lines
56115656 ecc->read_subpage = nand_read_subpage;
56125657 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
56135658 ecc->write_subpage = nand_write_subpage_hwecc;
5614− /* fall through */
5615−
5659+ fallthrough;
56165660 case NAND_ECC_HW_SYNDROME:
56175661 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
56185662 (!ecc->read_page ||
@@ -5649,8 +5693,7 @@ static int nand_scan_tail(struct nand_chip *chip) · 30 unmodified lines
56495693 ecc->size, mtd->writesize);
56505694 ecc->mode = NAND_ECC_SOFT;
56515695 ecc->algo = NAND_ECC_HAMMING;
5652− /* fall through */
5653−
5696+ fallthrough;
56545697 case NAND_ECC_SOFT:
56555698 ret = nand_set_ecc_soft_ops(chip);
56565699 if (ret) {
@@ -5786,8 +5829,8 @@ static int nand_scan_tail(struct nand_chip *chip) · 129 unmodified lines
57865829 mtd->_read_oob = nand_read_oob;
57875830 mtd->_write_oob = nand_write_oob;
57885831 mtd->_sync = nand_sync;
5789− mtd->_lock = NULL;
5790− mtd->_unlock = NULL;
5832+ mtd->_lock = nand_lock;
5833+ mtd->_unlock = nand_unlock;
57915834 mtd->_suspend = nand_suspend;
57925835 mtd->_resume = nand_resume;
57935836 mtd->_reboot = nand_shutdown;
@@ -5907,6 +5950,8 @@ void nand_cleanup(struct nand_chip *chip) · 113 unmodified lines
59075950 chip->ecc.algo == NAND_ECC_BCH)
59085951 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
59095952
5953+ nanddev_cleanup(&chip->base);
5954+
59105955 /* Free bad block table memory */
59115956 kfree(chip->bbt);
59125957 kfree(chip->data_buf);
drivers/mtd/nand/raw/nand_hynix.c+1−1
@@ -26,7 +26,7 @@ · 25 unmodified lines
2626 struct hynix_read_retry {
2727 int nregs;
2828 const u8 *regs;
29− u8 values[0];
29+ u8 values[];
3030 };
3131
3232 /**
drivers/mtd/nand/raw/nand_legacy.c+2−4
@@ -331,8 +331,7 @@ static void nand_command(struct nand_chip *chip, unsigned int command, · 330 unmodified lines
331331 */
332332 if (column == -1 && page_addr == -1)
333333 return;
334− /* fall through */
335−
334+ fallthrough;
336335 default:
337336 /*
338337 * If we don't have access to the busy pin, we apply the given
@@ -483,8 +482,7 @@ static void nand_command_lp(struct nand_chip *chip, unsigned int command, · 144 unmodified lines
483482 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
484483 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
485484 NAND_NCE | NAND_CTRL_CHANGE);
486−
487− /* fall through - This applies to read commands */
485+ fallthrough; /* This applies to read commands */
488486 default:
489487 /*
490488 * If we don't have access to the busy pin, we apply the given
drivers/mtd/nand/raw/nand_macronix.c+227−0
@@ -6,11 +6,31 @@ · 5 unmodified lines
66 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
77 */
88
9+#include "linux/delay.h"
910 #include "internals.h"
1011
1112 #define MACRONIX_READ_RETRY_BIT BIT(0)
1213 #define MACRONIX_NUM_READ_RETRY_MODES 6
1314
15+#define ONFI_FEATURE_ADDR_MXIC_PROTECTION 0xA0
16+#define MXIC_BLOCK_PROTECTION_ALL_LOCK 0x38
17+#define MXIC_BLOCK_PROTECTION_ALL_UNLOCK 0x0
18+
19+#define ONFI_FEATURE_ADDR_MXIC_RANDOMIZER 0xB0
20+#define MACRONIX_RANDOMIZER_BIT BIT(1)
21+#define MACRONIX_RANDOMIZER_ENPGM BIT(0)
22+#define MACRONIX_RANDOMIZER_RANDEN BIT(1)
23+#define MACRONIX_RANDOMIZER_RANDOPT BIT(2)
24+#define MACRONIX_RANDOMIZER_MODE_ENTER \
25+ (MACRONIX_RANDOMIZER_ENPGM | \
26+ MACRONIX_RANDOMIZER_RANDEN | \
27+ MACRONIX_RANDOMIZER_RANDOPT)
28+#define MACRONIX_RANDOMIZER_MODE_EXIT \
29+ (MACRONIX_RANDOMIZER_RANDEN | \
30+ MACRONIX_RANDOMIZER_RANDOPT)
31+
32+#define MXIC_CMD_POWER_DOWN 0xB9
33+
1434 struct nand_onfi_vendor_macronix {
1535 u8 reserved;
1636 u8 reliability_func;
@@ -29,15 +49,83 @@ static int macronix_nand_setup_read_retry(struct nand_chip *chip, int mode) · 12 unmodified lines
2949 return nand_set_features(chip, ONFI_FEATURE_ADDR_READ_RETRY, feature);
3050 }
3151
52+static int macronix_nand_randomizer_check_enable(struct nand_chip *chip)
53+{
54+ u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
55+ int ret;
56+
57+ ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
58+ feature);
59+ if (ret < 0)
60+ return ret;
61+
62+ if (feature[0])
63+ return feature[0];
64+
65+ feature[0] = MACRONIX_RANDOMIZER_MODE_ENTER;
66+ ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
67+ feature);
68+ if (ret < 0)
69+ return ret;
70+
71+ /* RANDEN and RANDOPT OTP bits are programmed */
72+ feature[0] = 0x0;
73+ ret = nand_prog_page_op(chip, 0, 0, feature, 1);
74+ if (ret < 0)
75+ return ret;
76+
77+ ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
78+ feature);
79+ if (ret < 0)
80+ return ret;
81+
82+ feature[0] &= MACRONIX_RANDOMIZER_MODE_EXIT;
83+ ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
84+ feature);
85+ if (ret < 0)
86+ return ret;
87+
88+ return 0;
89+}
90+
3291 static void macronix_nand_onfi_init(struct nand_chip *chip)
3392 {
3493 struct nand_parameters *p = &chip->parameters;
3594 struct nand_onfi_vendor_macronix *mxic;
95+ struct device_node *dn = nand_get_flash_node(chip);
96+ int rand_otp = 0;
97+ int ret;
3698
3799 if (!p->onfi)
38100 return;
39101
102+ if (of_find_property(dn, "mxic,enable-randomizer-otp", NULL))
103+ rand_otp = 1;
104+
40105 mxic = (struct nand_onfi_vendor_macronix *)p->onfi->vendor;
106+ /* Subpage write is prohibited in randomizer operatoin */
107+ if (rand_otp && chip->options & NAND_NO_SUBPAGE_WRITE &&
108+ mxic->reliability_func & MACRONIX_RANDOMIZER_BIT) {
109+ if (p->supports_set_get_features) {
110+ bitmap_set(p->set_feature_list,
111+ ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 1);
112+ bitmap_set(p->get_feature_list,
113+ ONFI_FEATURE_ADDR_MXIC_RANDOMIZER, 1);
114+ ret = macronix_nand_randomizer_check_enable(chip);
115+ if (ret < 0) {
116+ bitmap_clear(p->set_feature_list,
117+ ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
118+ 1);
119+ bitmap_clear(p->get_feature_list,
120+ ONFI_FEATURE_ADDR_MXIC_RANDOMIZER,
121+ 1);
122+ pr_info("Macronix NAND randomizer failed\n");
123+ } else {
124+ pr_info("Macronix NAND randomizer enabled\n");
125+ }
126+ }
127+ }
128+
41129 if ((mxic->reliability_func & MACRONIX_READ_RETRY_BIT) == 0)
42130 return;
43131
@@ -91,6 +179,143 @@ static void macronix_nand_fix_broken_get_timings(struct nand_chip *chip) · 47 unmodified lines
91179 ONFI_FEATURE_ADDR_TIMING_MODE, 1);
92180 }
93181
182+/*
183+ * Macronix NAND supports Block Protection by Protectoin(PT) pin;
184+ * active high at power-on which protects the entire chip even the #WP is
185+ * disabled. Lock/unlock protection area can be partition according to
186+ * protection bits, i.e. upper 1/2 locked, upper 1/4 locked and so on.
187+ */
188+static int mxic_nand_lock(struct nand_chip *chip, loff_t ofs, uint64_t len)
189+{
190+ u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
191+ int ret;
192+
193+ feature[0] = MXIC_BLOCK_PROTECTION_ALL_LOCK;
194+ nand_select_target(chip, 0);
195+ ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
196+ feature);
197+ nand_deselect_target(chip);
198+ if (ret)
199+ pr_err("%s all blocks failed\n", __func__);
200+
201+ return ret;
202+}
203+
204+static int mxic_nand_unlock(struct nand_chip *chip, loff_t ofs, uint64_t len)
205+{
206+ u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
207+ int ret;
208+
209+ feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
210+ nand_select_target(chip, 0);
211+ ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
212+ feature);
213+ nand_deselect_target(chip);
214+ if (ret)
215+ pr_err("%s all blocks failed\n", __func__);
216+
217+ return ret;
218+}
219+
220+static void macronix_nand_block_protection_support(struct nand_chip *chip)
221+{
222+ u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
223+ int ret;
224+
225+ bitmap_set(chip->parameters.get_feature_list,
226+ ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
227+
228+ feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
229+ nand_select_target(chip, 0);
230+ ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
231+ feature);
232+ nand_deselect_target(chip);
233+ if (ret || feature[0] != MXIC_BLOCK_PROTECTION_ALL_LOCK) {
234+ if (ret)
235+ pr_err("Block protection check failed\n");
236+
237+ bitmap_clear(chip->parameters.get_feature_list,
238+ ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
239+ return;
240+ }
241+
242+ bitmap_set(chip->parameters.set_feature_list,
243+ ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
244+
245+ chip->lock_area = mxic_nand_lock;
246+ chip->unlock_area = mxic_nand_unlock;
247+}
248+
249+static int nand_power_down_op(struct nand_chip *chip)
250+{
251+ int ret;
252+
253+ if (nand_has_exec_op(chip)) {
254+ struct nand_op_instr instrs[] = {
255+ NAND_OP_CMD(MXIC_CMD_POWER_DOWN, 0),
256+ };
257+
258+ struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
259+
260+ ret = nand_exec_op(chip, &op);
261+ if (ret)
262+ return ret;
263+
264+ } else {
265+ chip->legacy.cmdfunc(chip, MXIC_CMD_POWER_DOWN, -1, -1);
266+ }
267+
268+ return 0;
269+}
270+
271+static int mxic_nand_suspend(struct nand_chip *chip)
272+{
273+ int ret;
274+
275+ nand_select_target(chip, 0);
276+ ret = nand_power_down_op(chip);
277+ if (ret < 0)
278+ pr_err("Suspending MXIC NAND chip failed (%d)\n", ret);
279+ nand_deselect_target(chip);
280+
281+ return ret;
282+}
283+
284+static void mxic_nand_resume(struct nand_chip *chip)
285+{
286+ /*
287+ * Toggle #CS pin to resume NAND device and don't care
288+ * of the others CLE, #WE, #RE pins status.
289+ * A NAND controller ensure it is able to assert/de-assert #CS
290+ * by sending any byte over the NAND bus.
291+ * i.e.,
292+ * NAND power down command or reset command w/o R/B# status checking.
293+ */
294+ nand_select_target(chip, 0);
295+ nand_power_down_op(chip);
296+ /* The minimum of a recovery time tRDP is 35 us */
297+ usleep_range(35, 100);
298+ nand_deselect_target(chip);
299+}
300+
301+static void macronix_nand_deep_power_down_support(struct nand_chip *chip)
302+{
303+ int i;
304+ static const char * const deep_power_down_dev[] = {
305+ "MX30UF1G28AD",
306+ "MX30UF2G28AD",
307+ "MX30UF4G28AD",
308+ };
309+
310+ i = match_string(deep_power_down_dev, ARRAY_SIZE(deep_power_down_dev),
311+ chip->parameters.model);
312+ if (i < 0)
313+ return;
314+
315+ chip->suspend = mxic_nand_suspend;
316+ chip->resume = mxic_nand_resume;
317+}
318+
94319 static int macronix_nand_init(struct nand_chip *chip)
95320 {
96321 if (nand_is_slc(chip))
@@ -98,6 +323,8 @@ static int macronix_nand_init(struct nand_chip *chip) · 1 unmodified line
98323
99324 macronix_nand_fix_broken_get_timings(chip);
100325 macronix_nand_onfi_init(chip);
326+ macronix_nand_block_protection_support(chip);
327+ macronix_nand_deep_power_down_support(chip);
101328
102329 return 0;
103330 }
drivers/mtd/nand/raw/nand_toshiba.c+56−2
@@ -14,14 +14,68 @@ · 13 unmodified lines
1414 /* Recommended to rewrite for BENAND */
1515 #define TOSHIBA_NAND_STATUS_REWRITE_RECOMMENDED BIT(3)
1616
17+/* ECC Status Read Command for BENAND */
18+#define TOSHIBA_NAND_CMD_ECC_STATUS_READ 0x7A
19+
20+/* ECC Status Mask for BENAND */
21+#define TOSHIBA_NAND_ECC_STATUS_MASK 0x0F
22+
23+/* Uncorrectable Error for BENAND */
24+#define TOSHIBA_NAND_ECC_STATUS_UNCORR 0x0F
25+
26+/* Max ECC Steps for BENAND */
27+#define TOSHIBA_NAND_MAX_ECC_STEPS 8
28+
29+static int toshiba_nand_benand_read_eccstatus_op(struct nand_chip *chip,
30+ u8 *buf)
31+{
32+ u8 *ecc_status = buf;
33+
34+ if (nand_has_exec_op(chip)) {
35+ const struct nand_sdr_timings *sdr =
36+ nand_get_sdr_timings(&chip->data_interface);
37+ struct nand_op_instr instrs[] = {
38+ NAND_OP_CMD(TOSHIBA_NAND_CMD_ECC_STATUS_READ,
39+ PSEC_TO_NSEC(sdr->tADL_min)),
40+ NAND_OP_8BIT_DATA_IN(chip->ecc.steps, ecc_status, 0),
41+ };
42+ struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
43+
44+ return nand_exec_op(chip, &op);
45+ }
46+
47+ return -ENOTSUPP;
48+}
49+
1750 static int toshiba_nand_benand_eccstatus(struct nand_chip *chip)
1851 {
1952 struct mtd_info *mtd = nand_to_mtd(chip);
2053 int ret;
2154 unsigned int max_bitflips = 0;
22− u8 status;
55+ u8 status, ecc_status[TOSHIBA_NAND_MAX_ECC_STEPS];
2356
2457 /* Check Status */
58+ ret = toshiba_nand_benand_read_eccstatus_op(chip, ecc_status);
59+ if (!ret) {
60+ unsigned int i, bitflips = 0;
61+
62+ for (i = 0; i < chip->ecc.steps; i++) {
63+ bitflips = ecc_status[i] & TOSHIBA_NAND_ECC_STATUS_MASK;
64+ if (bitflips == TOSHIBA_NAND_ECC_STATUS_UNCORR) {
65+ mtd->ecc_stats.failed++;
66+ } else {
67+ mtd->ecc_stats.corrected += bitflips;
68+ max_bitflips = max(max_bitflips, bitflips);
69+ }
70+ }
71+
72+ return max_bitflips;
73+ }
74+
75+ /*
76+ * Fallback to regular status check if
77+ * toshiba_nand_benand_read_eccstatus_op() failed.
78+ */
2579 ret = nand_status_op(chip, &status);
2680 if (ret)
2781 return ret;
@@ -108,7 +162,7 @@ static void toshiba_nand_decode_id(struct nand_chip *chip) · 80 unmodified lines
108162 */
109163 if (chip->id.len >= 6 && nand_is_slc(chip) &&
110164 (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ &&
111− !(chip->id.data[4] & 0x80) /* !BENAND */) {
165+ !(chip->id.data[4] & TOSHIBA_NAND_ID4_IS_BENAND) /* !BENAND */) {
112166 memorg->oobsize = 32 * memorg->pagesize >> 9;
113167 mtd->oobsize = memorg->oobsize;
114168 }
drivers/mtd/nand/raw/nandsim.c+2−2
@@ -2251,10 +2251,10 @@ static int __init ns_init_module(void) · 2250 unmodified lines
22512251 switch (bbt) {
22522252 case 2:
22532253 chip->bbt_options |= NAND_BBT_NO_OOB;
2254− /* fall through */
2254+ fallthrough;
22552255 case 1:
22562256 chip->bbt_options |= NAND_BBT_USE_FLASH;
2257− /* fall through */
2257+ fallthrough;
22582258 case 0:
22592259 break;
22602260 default:
drivers/mtd/nand/raw/omap_elm.c+4−4
@@ -455,13 +455,13 @@ static int elm_context_save(struct elm_info *info) · 454 unmodified lines
455455 ELM_SYNDROME_FRAGMENT_5 + offset);
456456 regs->elm_syndrome_fragment_4[i] = elm_read_reg(info,
457457 ELM_SYNDROME_FRAGMENT_4 + offset);
458− /* fall through */
458+ fallthrough;
459459 case BCH8_ECC:
460460 regs->elm_syndrome_fragment_3[i] = elm_read_reg(info,
461461 ELM_SYNDROME_FRAGMENT_3 + offset);
462462 regs->elm_syndrome_fragment_2[i] = elm_read_reg(info,
463463 ELM_SYNDROME_FRAGMENT_2 + offset);
464− /* fall through */
464+ fallthrough;
465465 case BCH4_ECC:
466466 regs->elm_syndrome_fragment_1[i] = elm_read_reg(info,
467467 ELM_SYNDROME_FRAGMENT_1 + offset);
@@ -503,13 +503,13 @@ static int elm_context_restore(struct elm_info *info) · 35 unmodified lines
503503 regs->elm_syndrome_fragment_5[i]);
504504 elm_write_reg(info, ELM_SYNDROME_FRAGMENT_4 + offset,
505505 regs->elm_syndrome_fragment_4[i]);
506− /* fall through */
506+ fallthrough;
507507 case BCH8_ECC:
508508 elm_write_reg(info, ELM_SYNDROME_FRAGMENT_3 + offset,
509509 regs->elm_syndrome_fragment_3[i]);
510510 elm_write_reg(info, ELM_SYNDROME_FRAGMENT_2 + offset,
511511 regs->elm_syndrome_fragment_2[i]);
512− /* fall through */
512+ fallthrough;
513513 case BCH4_ECC:
514514 elm_write_reg(info, ELM_SYNDROME_FRAGMENT_1 + offset,
515515 regs->elm_syndrome_fragment_1[i]);
drivers/mtd/nand/raw/qcom_nandc.c+64−41
@@ -2628,6 +2628,29 @@ static const struct nand_controller_ops qcom_nandc_ops = { · 2627 unmodified lines
26282628 .attach_chip = qcom_nand_attach_chip,
26292629 };
26302630
2631+static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
2632+{
2633+ if (nandc->props->is_bam) {
2634+ if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
2635+ dma_unmap_single(nandc->dev, nandc->reg_read_dma,
2636+ MAX_REG_RD *
2637+ sizeof(*nandc->reg_read_buf),
2638+ DMA_FROM_DEVICE);
2639+
2640+ if (nandc->tx_chan)
2641+ dma_release_channel(nandc->tx_chan);
2642+
2643+ if (nandc->rx_chan)
2644+ dma_release_channel(nandc->rx_chan);
2645+
2646+ if (nandc->cmd_chan)
2647+ dma_release_channel(nandc->cmd_chan);
2648+ } else {
2649+ if (nandc->chan)
2650+ dma_release_channel(nandc->chan);
2651+ }
2652+}
2653+
26312654 static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
26322655 {
26332656 int ret;
@@ -2673,22 +2696,37 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) · 39 unmodified lines
26732696 return -EIO;
26742697 }
26752698
2676− nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
2677− if (!nandc->tx_chan) {
2678− dev_err(nandc->dev, "failed to request tx channel\n");
2679− return -ENODEV;
2699+ nandc->tx_chan = dma_request_chan(nandc->dev, "tx");
2700+ if (IS_ERR(nandc->tx_chan)) {
2701+ ret = PTR_ERR(nandc->tx_chan);
2702+ nandc->tx_chan = NULL;
2703+ if (ret != -EPROBE_DEFER)
2704+ dev_err(nandc->dev,
2705+ "tx DMA channel request failed: %d\n",
2706+ ret);
2707+ goto unalloc;
26802708 }
26812709
2682− nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
2683− if (!nandc->rx_chan) {
2684− dev_err(nandc->dev, "failed to request rx channel\n");
2685− return -ENODEV;
2710+ nandc->rx_chan = dma_request_chan(nandc->dev, "rx");
2711+ if (IS_ERR(nandc->rx_chan)) {
2712+ ret = PTR_ERR(nandc->rx_chan);
2713+ nandc->rx_chan = NULL;
2714+ if (ret != -EPROBE_DEFER)
2715+ dev_err(nandc->dev,
2716+ "rx DMA channel request failed: %d\n",
2717+ ret);
2718+ goto unalloc;
26862719 }
26872720
2688− nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
2689− if (!nandc->cmd_chan) {
2690− dev_err(nandc->dev, "failed to request cmd channel\n");
2691− return -ENODEV;
2721+ nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd");
2722+ if (IS_ERR(nandc->cmd_chan)) {
2723+ ret = PTR_ERR(nandc->cmd_chan);
2724+ nandc->cmd_chan = NULL;
2725+ if (ret != -EPROBE_DEFER)
2726+ dev_err(nandc->dev,
2727+ "cmd DMA channel request failed: %d\n",
2728+ ret);
2729+ goto unalloc;
26922730 }
26932731
26942732 /*
@@ -2702,14 +2740,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) · 7 unmodified lines
27022740 if (!nandc->bam_txn) {
27032741 dev_err(nandc->dev,
27042742 "failed to allocate bam transaction\n");
2705− return -ENOMEM;
2743+ ret = -ENOMEM;
2744+ goto unalloc;
27062745 }
27072746 } else {
2708− nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
2709− if (!nandc->chan) {
2710− dev_err(nandc->dev,
2711− "failed to request slave channel\n");
2712− return -ENODEV;
2747+ nandc->chan = dma_request_chan(nandc->dev, "rxtx");
2748+ if (IS_ERR(nandc->chan)) {
2749+ ret = PTR_ERR(nandc->chan);
2750+ nandc->chan = NULL;
2751+ if (ret != -EPROBE_DEFER)
2752+ dev_err(nandc->dev,
2753+ "rxtx DMA channel request failed: %d\n",
2754+ ret);
2755+ return ret;
27132756 }
27142757 }
27152758
@@ -2720,29 +2763,9 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) · 4 unmodified lines
27202763 nandc->controller.ops = &qcom_nandc_ops;
27212764
27222765 return 0;
2723−}
2724−
2725−static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
2726−{
2727− if (nandc->props->is_bam) {
2728− if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
2729− dma_unmap_single(nandc->dev, nandc->reg_read_dma,
2730− MAX_REG_RD *
2731− sizeof(*nandc->reg_read_buf),
2732− DMA_FROM_DEVICE);
2733−
2734− if (nandc->tx_chan)
2735− dma_release_channel(nandc->tx_chan);
2736−
2737− if (nandc->rx_chan)
2738− dma_release_channel(nandc->rx_chan);
2739−
2740− if (nandc->cmd_chan)
2741− dma_release_channel(nandc->cmd_chan);
2742− } else {
2743− if (nandc->chan)
2744− dma_release_channel(nandc->chan);
2745− }
2766+unalloc:
2767+ qcom_nandc_unalloc(nandc);
2768+ return ret;
27462769 }
27472770
27482771 /* one time setup of a few nand controller registers */
drivers/mtd/nand/raw/stm32_fmc2_nand.c+37−7
@@ -1606,15 +1606,36 @@ static int stm32_fmc2_setup_interface(struct nand_chip *chip, int chipnr, · 1605 unmodified lines
16061606 /* DMA configuration */
16071607 static int stm32_fmc2_dma_setup(struct stm32_fmc2_nfc *fmc2)
16081608 {
1609− int ret;
1609+ int ret = 0;
16101610
1611− fmc2->dma_tx_ch = dma_request_slave_channel(fmc2->dev, "tx");
1612− fmc2->dma_rx_ch = dma_request_slave_channel(fmc2->dev, "rx");
1613− fmc2->dma_ecc_ch = dma_request_slave_channel(fmc2->dev, "ecc");
1611+ fmc2->dma_tx_ch = dma_request_chan(fmc2->dev, "tx");
1612+ if (IS_ERR(fmc2->dma_tx_ch)) {
1613+ ret = PTR_ERR(fmc2->dma_tx_ch);
1614+ if (ret != -ENODEV)
1615+ dev_err(fmc2->dev,
1616+ "failed to request tx DMA channel: %d\n", ret);
1617+ fmc2->dma_tx_ch = NULL;
1618+ goto err_dma;
1619+ }
16141620
1615− if (!fmc2->dma_tx_ch || !fmc2->dma_rx_ch || !fmc2->dma_ecc_ch) {
1616− dev_warn(fmc2->dev, "DMAs not defined in the device tree, polling mode is used\n");
1617− return 0;
1621+ fmc2->dma_rx_ch = dma_request_chan(fmc2->dev, "rx");
1622+ if (IS_ERR(fmc2->dma_rx_ch)) {
1623+ ret = PTR_ERR(fmc2->dma_rx_ch);
1624+ if (ret != -ENODEV)
1625+ dev_err(fmc2->dev,
1626+ "failed to request rx DMA channel: %d\n", ret);
1627+ fmc2->dma_rx_ch = NULL;
1628+ goto err_dma;
1629+ }
1630+
1631+ fmc2->dma_ecc_ch = dma_request_chan(fmc2->dev, "ecc");
1632+ if (IS_ERR(fmc2->dma_ecc_ch)) {
1633+ ret = PTR_ERR(fmc2->dma_ecc_ch);
1634+ if (ret != -ENODEV)
1635+ dev_err(fmc2->dev,
1636+ "failed to request ecc DMA channel: %d\n", ret);
1637+ fmc2->dma_ecc_ch = NULL;
1638+ goto err_dma;
16181639 }
16191640
16201641 ret = sg_alloc_table(&fmc2->dma_ecc_sg, FMC2_MAX_SG, GFP_KERNEL);
@@ -1635,6 +1656,15 @@ static int stm32_fmc2_dma_setup(struct stm32_fmc2_nfc *fmc2) · 14 unmodified lines
16351656 init_completion(&fmc2->dma_ecc_complete);
16361657
16371658 return 0;
1659+
1660+err_dma:
1661+ if (ret == -ENODEV) {
1662+ dev_warn(fmc2->dev,
1663+ "DMAs not defined in the DT, polling mode is used\n");
1664+ ret = 0;
1665+ }
1666+
1667+ return ret;
16381668 }
16391669
16401670 /* NAND callbacks setup */
drivers/mtd/nand/raw/sunxi_nand.c+11−6
@@ -195,7 +195,7 @@ struct sunxi_nand_chip { · 194 unmodified lines
195195 u32 timing_cfg;
196196 u32 timing_ctl;
197197 int nsels;
198− struct sunxi_nand_chip_sel sels[0];
198+ struct sunxi_nand_chip_sel sels[];
199199 };
200200
201201 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
@@ -2123,8 +2123,16 @@ static int sunxi_nfc_probe(struct platform_device *pdev) · 1921 unmodified lines
21232123 if (ret)
21242124 goto out_ahb_reset_reassert;
21252125
2126− nfc->dmac = dma_request_slave_channel(dev, "rxtx");
2127− if (nfc->dmac) {
2126+ nfc->dmac = dma_request_chan(dev, "rxtx");
2127+ if (IS_ERR(nfc->dmac)) {
2128+ ret = PTR_ERR(nfc->dmac);
2129+ if (ret == -EPROBE_DEFER)
2130+ goto out_ahb_reset_reassert;
2131+
2132+ /* Ignore errors to fall back to PIO mode */
2133+ dev_warn(dev, "failed to request rxtx DMA channel: %d\n", ret);
2134+ nfc->dmac = NULL;
2135+ } else {
21282136 struct dma_slave_config dmac_cfg = { };
21292137
21302138 dmac_cfg.src_addr = r->start + nfc->caps->reg_io_data;
@@ -2138,9 +2146,6 @@ static int sunxi_nfc_probe(struct platform_device *pdev) · 7 unmodified lines
21382146 if (nfc->caps->extra_mbus_conf)
21392147 writel(readl(nfc->regs + NFC_REG_CTL) |
21402148 NFC_DMA_TYPE_NORMAL, nfc->regs + NFC_REG_CTL);
2141−
2142− } else {
2143− dev_warn(dev, "failed to request rxtx DMA channel\n");
21442149 }
21452150
21462151 platform_set_drvdata(pdev, nfc);
drivers/mtd/nand/spi/core.c+71−33
@@ -16,6 +16,7 @@ · 15 unmodified lines
1616 #include <linux/mtd/spinand.h>
1717 #include <linux/of.h>
1818 #include <linux/slab.h>
19+#include <linux/string.h>
1920 #include <linux/spi/spi.h>
2021 #include <linux/spi/spi-mem.h>
2122
@@ -370,10 +371,11 @@ out: · 348 unmodified lines
370371 return status & STATUS_BUSY ? -ETIMEDOUT : 0;
371372 }
372373
373−static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
374+static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr,
375+ u8 ndummy, u8 *buf)
374376 {
375− struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf,
376− SPINAND_MAX_ID_LEN);
377+ struct spi_mem_op op = SPINAND_READID_OP(
378+ naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
377379 int ret;
378380
379381 ret = spi_mem_exec_op(spinand->spimem, &op);
@@ -568,18 +570,18 @@ static int spinand_mtd_write(struct mtd_info *mtd, loff_t to, · 188 unmodified lines
568570 static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
569571 {
570572 struct spinand_device *spinand = nand_to_spinand(nand);
573+ u8 marker[2] = { };
571574 struct nand_page_io_req req = {
572575 .pos = *pos,
573− .ooblen = 2,
576+ .ooblen = sizeof(marker),
574577 .ooboffs = 0,
575− .oobbuf.in = spinand->oobbuf,
578+ .oobbuf.in = marker,
576579 .mode = MTD_OPS_RAW,
577580 };
578581
579− memset(spinand->oobbuf, 0, 2);
580582 spinand_select_target(spinand, pos->target);
581583 spinand_read_page(spinand, &req, false);
582− if (spinand->oobbuf[0] != 0xff || spinand->oobbuf[1] != 0xff)
584+ if (marker[0] != 0xff || marker[1] != 0xff)
583585 return true;
584586
585587 return false;
@@ -603,15 +605,16 @@ static int spinand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs) · 17 unmodified lines
603605 static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos)
604606 {
605607 struct spinand_device *spinand = nand_to_spinand(nand);
608+ u8 marker[2] = { };
606609 struct nand_page_io_req req = {
607610 .pos = *pos,
608611 .ooboffs = 0,
609− .ooblen = 2,
610− .oobbuf.out = spinand->oobbuf,
612+ .ooblen = sizeof(marker),
613+ .oobbuf.out = marker,
614+ .mode = MTD_OPS_RAW,
611615 };
612616 int ret;
613617
614− /* Erase block before marking it bad. */
615618 ret = spinand_select_target(spinand, pos->target);
616619 if (ret)
617620 return ret;
@@ -620,9 +623,6 @@ static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos) · 2 unmodified lines
620623 if (ret)
621624 return ret;
622625
623− spinand_erase_op(spinand, pos);
624−
625− memset(spinand->oobbuf, 0, 2);
626626 return spinand_write_page(spinand, &req);
627627 }
628628
@@ -762,24 +762,62 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { · 133 unmodified lines
762762 &winbond_spinand_manufacturer,
763763 };
764764
765−static int spinand_manufacturer_detect(struct spinand_device *spinand)
765+static int spinand_manufacturer_match(struct spinand_device *spinand,
766+ enum spinand_readid_method rdid_method)
766767 {
768+ u8 *id = spinand->id.data;
767769 unsigned int i;
768770 int ret;
769771
770772 for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) {
771− ret = spinand_manufacturers[i]->ops->detect(spinand);
772− if (ret > 0) {
773− spinand->manufacturer = spinand_manufacturers[i];
774− return 0;
775− } else if (ret < 0) {
776− return ret;
777− }
778− }
773+ const struct spinand_manufacturer *manufacturer =
774+ spinand_manufacturers[i];
775+
776+ if (id[0] != manufacturer->id)
777+ continue;
778+
779+ ret = spinand_match_and_init(spinand,
780+ manufacturer->chips,
781+ manufacturer->nchips,
782+ rdid_method);
783+ if (ret < 0)
784+ continue;
779785
786+ spinand->manufacturer = manufacturer;
787+ return 0;
788+ }
780789 return -ENOTSUPP;
781790 }
782791
792+static int spinand_id_detect(struct spinand_device *spinand)
793+{
794+ u8 *id = spinand->id.data;
795+ int ret;
796+
797+ ret = spinand_read_id_op(spinand, 0, 0, id);
798+ if (ret)
799+ return ret;
800+ ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE);
801+ if (!ret)
802+ return 0;
803+
804+ ret = spinand_read_id_op(spinand, 1, 0, id);
805+ if (ret)
806+ return ret;
807+ ret = spinand_manufacturer_match(spinand,
808+ SPINAND_READID_METHOD_OPCODE_ADDR);
809+ if (!ret)
810+ return 0;
811+
812+ ret = spinand_read_id_op(spinand, 0, 1, id);
813+ if (ret)
814+ return ret;
815+ ret = spinand_manufacturer_match(spinand,
816+ SPINAND_READID_METHOD_OPCODE_DUMMY);
817+
818+ return ret;
819+}
820+
783821 static int spinand_manufacturer_init(struct spinand_device *spinand)
784822 {
785823 if (spinand->manufacturer->ops->init)
@@ -835,9 +873,9 @@ spinand_select_op_variant(struct spinand_device *spinand, · 49 unmodified lines
835873 * @spinand: SPI NAND object
836874 * @table: SPI NAND device description table
837875 * @table_size: size of the device description table
876+ * @rdid_method: read id method to match
838877 *
839− * Should be used by SPI NAND manufacturer drivers when they want to find a
840− * match between a device ID retrieved through the READ_ID command and an
878+ * Match between a device ID retrieved through the READ_ID command and an
841879 * entry in the SPI NAND description table. If a match is found, the spinand
842880 * object will be initialized with information provided by the matching
843881 * spinand_info entry.
@@ -846,8 +884,10 @@ spinand_select_op_variant(struct spinand_device *spinand, · 2 unmodified lines
846884 */
847885 int spinand_match_and_init(struct spinand_device *spinand,
848886 const struct spinand_info *table,
849− unsigned int table_size, u16 devid)
887+ unsigned int table_size,
888+ enum spinand_readid_method rdid_method)
850889 {
890+ u8 *id = spinand->id.data;
851891 struct nand_device *nand = spinand_to_nand(spinand);
852892 unsigned int i;
853893
@@ -855,13 +895,17 @@ int spinand_match_and_init(struct spinand_device *spinand, · 1 unmodified line
855895 const struct spinand_info *info = &table[i];
856896 const struct spi_mem_op *op;
857897
858− if (devid != info->devid)
898+ if (rdid_method != info->devid.method)
899+ continue;
900+
901+ if (memcmp(id + 1, info->devid.id, info->devid.len))
859902 continue;
860903
861904 nand->memorg = table[i].memorg;
862905 nand->eccreq = table[i].eccreq;
863906 spinand->eccinfo = table[i].eccinfo;
864907 spinand->flags = table[i].flags;
908+ spinand->id.len = 1 + table[i].devid.len;
865909 spinand->select_target = table[i].select_target;
866910
867911 op = spinand_select_op_variant(spinand,
@@ -898,13 +942,7 @@ static int spinand_detect(struct spinand_device *spinand) · 30 unmodified lines
898942 if (ret)
899943 return ret;
900944
901− ret = spinand_read_id_op(spinand, spinand->id.data);
902− if (ret)
903− return ret;
904−
905− spinand->id.len = SPINAND_MAX_ID_LEN;
906−
907− ret = spinand_manufacturer_detect(spinand);
945+ ret = spinand_id_detect(spinand);
908946 if (ret) {
909947 dev_err(dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN,
910948 spinand->id.data);
drivers/mtd/nand/spi/gigadevice.c+12−33
@@ -195,7 +195,8 @@ static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand, · 194 unmodified lines
195195 }
196196
197197 static const struct spinand_info gigadevice_spinand_table[] = {
198− SPINAND_INFO("GD5F1GQ4xA", 0xF1,
198+ SPINAND_INFO("GD5F1GQ4xA",
199+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
199200 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
200201 NAND_ECCREQ(8, 512),
201202 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -204,7 +205,8 @@ static const struct spinand_info gigadevice_spinand_table[] = { · 2 unmodified lines
204205 0,
205206 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
206207 gd5fxgq4xa_ecc_get_status)),
207− SPINAND_INFO("GD5F2GQ4xA", 0xF2,
208+ SPINAND_INFO("GD5F2GQ4xA",
209+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2),
208210 NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
209211 NAND_ECCREQ(8, 512),
210212 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -213,7 +215,8 @@ static const struct spinand_info gigadevice_spinand_table[] = { · 2 unmodified lines
213215 0,
214216 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
215217 gd5fxgq4xa_ecc_get_status)),
216− SPINAND_INFO("GD5F4GQ4xA", 0xF4,
218+ SPINAND_INFO("GD5F4GQ4xA",
219+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4),
217220 NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),
218221 NAND_ECCREQ(8, 512),
219222 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -222,7 +225,8 @@ static const struct spinand_info gigadevice_spinand_table[] = { · 2 unmodified lines
222225 0,
223226 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
224227 gd5fxgq4xa_ecc_get_status)),
225− SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
228+ SPINAND_INFO("GD5F1GQ4UExxG",
229+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1),
226230 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
227231 NAND_ECCREQ(8, 512),
228232 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -231,7 +235,8 @@ static const struct spinand_info gigadevice_spinand_table[] = { · 2 unmodified lines
231235 0,
232236 SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
233237 gd5fxgq4uexxg_ecc_get_status)),
234− SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148,
238+ SPINAND_INFO("GD5F1GQ4UFxxG",
239+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
235240 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
236241 NAND_ECCREQ(8, 512),
237242 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
@@ -242,39 +247,13 @@ static const struct spinand_info gigadevice_spinand_table[] = { · 4 unmodified lines
242247 gd5fxgq4ufxxg_ecc_get_status)),
243248 };
244249
245−static int gigadevice_spinand_detect(struct spinand_device *spinand)
246−{
247− u8 *id = spinand->id.data;
248− u16 did;
249− int ret;
250−
251− /*
252− * Earlier GDF5-series devices (A,E) return [0][MID][DID]
253− * Later (F) devices return [MID][DID1][DID2]
254− */
255−
256− if (id[0] == SPINAND_MFR_GIGADEVICE)
257− did = (id[1] << 8) + id[2];
258− else if (id[0] == 0 && id[1] == SPINAND_MFR_GIGADEVICE)
259− did = id[2];
260− else
261− return 0;
262−
263− ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
264− ARRAY_SIZE(gigadevice_spinand_table),
265− did);
266− if (ret)
267− return ret;
268−
269− return 1;
270−}
271−
272250 static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
273− .detect = gigadevice_spinand_detect,
274251 };
275252
276253 const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
277254 .id = SPINAND_MFR_GIGADEVICE,
278255 .name = "GigaDevice",
256+ .chips = gigadevice_spinand_table,
257+ .nchips = ARRAY_SIZE(gigadevice_spinand_table),
279258 .ops = &gigadevice_spinand_manuf_ops,
280259 };
drivers/mtd/nand/spi/macronix.c+6−24
@@ -99,7 +99,8 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand, · 98 unmodified lines
9999 }
100100
101101 static const struct spinand_info macronix_spinand_table[] = {
102− SPINAND_INFO("MX35LF1GE4AB", 0x12,
102+ SPINAND_INFO("MX35LF1GE4AB",
103+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12),
103104 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
104105 NAND_ECCREQ(4, 512),
105106 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -108,7 +109,8 @@ static const struct spinand_info macronix_spinand_table[] = { · 2 unmodified lines
108109 SPINAND_HAS_QE_BIT,
109110 SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
110111 mx35lf1ge4ab_ecc_get_status)),
111− SPINAND_INFO("MX35LF2GE4AB", 0x22,
112+ SPINAND_INFO("MX35LF2GE4AB",
113+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
112114 NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
113115 NAND_ECCREQ(4, 512),
114116 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -118,33 +120,13 @@ static const struct spinand_info macronix_spinand_table[] = { · 3 unmodified lines
118120 SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
119121 };
120122
121−static int macronix_spinand_detect(struct spinand_device *spinand)
122−{
123− u8 *id = spinand->id.data;
124− int ret;
125−
126− /*
127− * Macronix SPI NAND read ID needs a dummy byte, so the first byte in
128− * raw_id is garbage.
129− */
130− if (id[1] != SPINAND_MFR_MACRONIX)
131− return 0;
132−
133− ret = spinand_match_and_init(spinand, macronix_spinand_table,
134− ARRAY_SIZE(macronix_spinand_table),
135− id[2]);
136− if (ret)
137− return ret;
138−
139− return 1;
140−}
141−
142123 static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
143− .detect = macronix_spinand_detect,
144124 };
145125
146126 const struct spinand_manufacturer macronix_spinand_manufacturer = {
147127 .id = SPINAND_MFR_MACRONIX,
148128 .name = "Macronix",
129+ .chips = macronix_spinand_table,
130+ .nchips = ARRAY_SIZE(macronix_spinand_table),
149131 .ops = &macronix_spinand_manuf_ops,
150132 };
drivers/mtd/nand/spi/micron.c+142−30
@@ -18,6 +18,16 @@ · 17 unmodified lines
1818 #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)
1919 #define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4)
2020
21+#define MICRON_CFG_CR BIT(0)
22+
23+/*
24+ * As per datasheet, die selection is done by the 6th bit of Die
25+ * Select Register (Address 0xD0).
26+ */
27+#define MICRON_DIE_SELECT_REG 0xD0
28+
29+#define MICRON_SELECT_DIE(x) ((x) << 6)
30+
2131 static SPINAND_OP_VARIANTS(read_cache_variants,
2232 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
2333 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
@@ -34,38 +44,52 @@ static SPINAND_OP_VARIANTS(update_cache_variants, · 10 unmodified lines
3444 SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
3545 SPINAND_PROG_LOAD(false, 0, NULL, 0));
3646
37−static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
38− struct mtd_oob_region *region)
47+static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section,
48+ struct mtd_oob_region *region)
3949 {
4050 if (section)
4151 return -ERANGE;
4252
43− region->offset = 64;
44− region->length = 64;
53+ region->offset = mtd->oobsize / 2;
54+ region->length = mtd->oobsize / 2;
4555
4656 return 0;
4757 }
4858
49−static int mt29f2g01abagd_ooblayout_free(struct mtd_info *mtd, int section,
50− struct mtd_oob_region *region)
59+static int micron_8_ooblayout_free(struct mtd_info *mtd, int section,
60+ struct mtd_oob_region *region)
5161 {
5262 if (section)
5363 return -ERANGE;
5464
5565 /* Reserve 2 bytes for the BBM. */
5666 region->offset = 2;
57− region->length = 62;
67+ region->length = (mtd->oobsize / 2) - 2;
5868
5969 return 0;
6070 }
6171
62−static const struct mtd_ooblayout_ops mt29f2g01abagd_ooblayout = {
63− .ecc = mt29f2g01abagd_ooblayout_ecc,
64− .free = mt29f2g01abagd_ooblayout_free,
72+static const struct mtd_ooblayout_ops micron_8_ooblayout = {
73+ .ecc = micron_8_ooblayout_ecc,
74+ .free = micron_8_ooblayout_free,
6575 };
6676
67−static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
68− u8 status)
77+static int micron_select_target(struct spinand_device *spinand,
78+ unsigned int target)
79+{
80+ struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG,
81+ spinand->scratchbuf);
82+
83+ if (target > 1)
84+ return -EINVAL;
85+
86+ *spinand->scratchbuf = MICRON_SELECT_DIE(target);
87+
88+ return spi_mem_exec_op(spinand->spimem, &op);
89+}
90+
91+static int micron_8_ecc_get_status(struct spinand_device *spinand,
92+ u8 status)
6993 {
7094 switch (status & MICRON_STATUS_ECC_MASK) {
7195 case STATUS_ECC_NO_BITFLIPS:
@@ -91,43 +115,131 @@ static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand, · 19 unmodified lines
91115 }
92116
93117 static const struct spinand_info micron_spinand_table[] = {
94− SPINAND_INFO("MT29F2G01ABAGD", 0x24,
118+ /* M79A 2Gb 3.3V */
119+ SPINAND_INFO("MT29F2G01ABAGD",
120+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
121+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
122+ NAND_ECCREQ(8, 512),
123+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
124+ &write_cache_variants,
125+ &update_cache_variants),
126+ 0,
127+ SPINAND_ECCINFO(&micron_8_ooblayout,
128+ micron_8_ecc_get_status)),
129+ /* M79A 2Gb 1.8V */
130+ SPINAND_INFO("MT29F2G01ABBGD",
131+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
95132 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
96133 NAND_ECCREQ(8, 512),
97134 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
98135 &write_cache_variants,
99136 &update_cache_variants),
100137 0,
101− SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout,
102− mt29f2g01abagd_ecc_get_status)),
138+ SPINAND_ECCINFO(&micron_8_ooblayout,
139+ micron_8_ecc_get_status)),
140+ /* M78A 1Gb 3.3V */
141+ SPINAND_INFO("MT29F1G01ABAFD",
142+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
143+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
144+ NAND_ECCREQ(8, 512),
145+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
146+ &write_cache_variants,
147+ &update_cache_variants),
148+ 0,
149+ SPINAND_ECCINFO(&micron_8_ooblayout,
150+ micron_8_ecc_get_status)),
151+ /* M78A 1Gb 1.8V */
152+ SPINAND_INFO("MT29F1G01ABAFD",
153+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
154+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
155+ NAND_ECCREQ(8, 512),
156+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
157+ &write_cache_variants,
158+ &update_cache_variants),
159+ 0,
160+ SPINAND_ECCINFO(&micron_8_ooblayout,
161+ micron_8_ecc_get_status)),
162+ /* M79A 4Gb 3.3V */
163+ SPINAND_INFO("MT29F4G01ADAGD",
164+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36),
165+ NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2),
166+ NAND_ECCREQ(8, 512),
167+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
168+ &write_cache_variants,
169+ &update_cache_variants),
170+ 0,
171+ SPINAND_ECCINFO(&micron_8_ooblayout,
172+ micron_8_ecc_get_status),
173+ SPINAND_SELECT_TARGET(micron_select_target)),
174+ /* M70A 4Gb 3.3V */
175+ SPINAND_INFO("MT29F4G01ABAFD",
176+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
177+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
178+ NAND_ECCREQ(8, 512),
179+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
180+ &write_cache_variants,
181+ &update_cache_variants),
182+ SPINAND_HAS_CR_FEAT_BIT,
183+ SPINAND_ECCINFO(&micron_8_ooblayout,
184+ micron_8_ecc_get_status)),
185+ /* M70A 4Gb 1.8V */
186+ SPINAND_INFO("MT29F4G01ABBFD",
187+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
188+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
189+ NAND_ECCREQ(8, 512),
190+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
191+ &write_cache_variants,
192+ &update_cache_variants),
193+ SPINAND_HAS_CR_FEAT_BIT,
194+ SPINAND_ECCINFO(&micron_8_ooblayout,
195+ micron_8_ecc_get_status)),
196+ /* M70A 8Gb 3.3V */
197+ SPINAND_INFO("MT29F8G01ADAFD",
198+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46),
199+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
200+ NAND_ECCREQ(8, 512),
201+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
202+ &write_cache_variants,
203+ &update_cache_variants),
204+ SPINAND_HAS_CR_FEAT_BIT,
205+ SPINAND_ECCINFO(&micron_8_ooblayout,
206+ micron_8_ecc_get_status),
207+ SPINAND_SELECT_TARGET(micron_select_target)),
208+ /* M70A 8Gb 1.8V */
209+ SPINAND_INFO("MT29F8G01ADBFD",
210+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47),
211+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
212+ NAND_ECCREQ(8, 512),
213+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
214+ &write_cache_variants,
215+ &update_cache_variants),
216+ SPINAND_HAS_CR_FEAT_BIT,
217+ SPINAND_ECCINFO(&micron_8_ooblayout,
218+ micron_8_ecc_get_status),
219+ SPINAND_SELECT_TARGET(micron_select_target)),
103220 };
104221
105−static int micron_spinand_detect(struct spinand_device *spinand)
222+static int micron_spinand_init(struct spinand_device *spinand)
106223 {
107− u8 *id = spinand->id.data;
108− int ret;
109−
110224 /*
111− * Micron SPI NAND read ID need a dummy byte,
112− * so the first byte in raw_id is dummy.
225+ * M70A device series enable Continuous Read feature at Power-up,
226+ * which is not supported. Disable this bit to avoid any possible
227+ * failure.
113228 */
114− if (id[1] != SPINAND_MFR_MICRON)
115− return 0;
116−
117− ret = spinand_match_and_init(spinand, micron_spinand_table,
118− ARRAY_SIZE(micron_spinand_table), id[2]);
119− if (ret)
120− return ret;
229+ if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT)
230+ return spinand_upd_cfg(spinand, MICRON_CFG_CR, 0);
121231
122− return 1;
232+ return 0;
123233 }
124234
125235 static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
126− .detect = micron_spinand_detect,
236+ .init = micron_spinand_init,
127237 };
128238
129239 const struct spinand_manufacturer micron_spinand_manufacturer = {
130240 .id = SPINAND_MFR_MICRON,
131241 .name = "Micron",
242+ .chips = micron_spinand_table,
243+ .nchips = ARRAY_SIZE(micron_spinand_table),
132244 .ops = &micron_spinand_manuf_ops,
133245 };
drivers/mtd/nand/spi/paragon.c+6−22
@@ -97,7 +97,8 @@ static const struct mtd_ooblayout_ops pn26g0xa_ooblayout = { · 96 unmodified lines
9797
9898
9999 static const struct spinand_info paragon_spinand_table[] = {
100− SPINAND_INFO("PN26G01A", 0xe1,
100+ SPINAND_INFO("PN26G01A",
101+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe1),
101102 NAND_MEMORG(1, 2048, 128, 64, 1024, 21, 1, 1, 1),
102103 NAND_ECCREQ(8, 512),
103104 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -106,7 +107,8 @@ static const struct spinand_info paragon_spinand_table[] = { · 2 unmodified lines
106107 0,
107108 SPINAND_ECCINFO(&pn26g0xa_ooblayout,
108109 pn26g0xa_ecc_get_status)),
109− SPINAND_INFO("PN26G02A", 0xe2,
110+ SPINAND_INFO("PN26G02A",
111+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe2),
110112 NAND_MEMORG(1, 2048, 128, 64, 2048, 41, 1, 1, 1),
111113 NAND_ECCREQ(8, 512),
112114 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -117,31 +119,13 @@ static const struct spinand_info paragon_spinand_table[] = { · 4 unmodified lines
117119 pn26g0xa_ecc_get_status)),
118120 };
119121
120−static int paragon_spinand_detect(struct spinand_device *spinand)
121−{
122− u8 *id = spinand->id.data;
123− int ret;
124−
125− /* Read ID returns [0][MID][DID] */
126−
127− if (id[1] != SPINAND_MFR_PARAGON)
128− return 0;
129−
130− ret = spinand_match_and_init(spinand, paragon_spinand_table,
131− ARRAY_SIZE(paragon_spinand_table),
132− id[2]);
133− if (ret)
134− return ret;
135−
136− return 1;
137−}
138−
139122 static const struct spinand_manufacturer_ops paragon_spinand_manuf_ops = {
140− .detect = paragon_spinand_detect,
141123 };
142124
143125 const struct spinand_manufacturer paragon_spinand_manufacturer = {
144126 .id = SPINAND_MFR_PARAGON,
145127 .name = "Paragon",
128+ .chips = paragon_spinand_table,
129+ .nchips = ARRAY_SIZE(paragon_spinand_table),
146130 .ops = &paragon_spinand_manuf_ops,
147131 };
drivers/mtd/nand/spi/toshiba.c+145−63
@@ -10,6 +10,7 @@ · 9 unmodified lines
1010 #include <linux/kernel.h>
1111 #include <linux/mtd/spinand.h>
1212
13+/* Kioxia is new name of Toshiba memory. */
1314 #define SPINAND_MFR_TOSHIBA 0x98
1415 #define TOSH_STATUS_ECC_HAS_BITFLIPS_T (3 << 4)
1516
@@ -19,14 +20,26 @@ static SPINAND_OP_VARIANTS(read_cache_variants, · 3 unmodified lines
1920 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
2021 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
2122
23+static SPINAND_OP_VARIANTS(write_cache_x4_variants,
24+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
25+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
26+
27+static SPINAND_OP_VARIANTS(update_cache_x4_variants,
28+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
29+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
30+
31+/**
32+ * Backward compatibility for 1st generation Serial NAND devices
33+ * which don't support Quad Program Load operation.
34+ */
2235 static SPINAND_OP_VARIANTS(write_cache_variants,
2336 SPINAND_PROG_LOAD(true, 0, NULL, 0));
2437
2538 static SPINAND_OP_VARIANTS(update_cache_variants,
2639 SPINAND_PROG_LOAD(false, 0, NULL, 0));
2740
28−static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section,
29− struct mtd_oob_region *region)
41+static int tx58cxgxsxraix_ooblayout_ecc(struct mtd_info *mtd, int section,
42+ struct mtd_oob_region *region)
3043 {
3144 if (section > 0)
3245 return -ERANGE;
@@ -37,8 +50,8 @@ static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section, · 4 unmodified lines
3750 return 0;
3851 }
3952
40−static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section,
41− struct mtd_oob_region *region)
53+static int tx58cxgxsxraix_ooblayout_free(struct mtd_info *mtd, int section,
54+ struct mtd_oob_region *region)
4255 {
4356 if (section > 0)
4457 return -ERANGE;
@@ -50,13 +63,13 @@ static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section, · 5 unmodified lines
5063 return 0;
5164 }
5265
53−static const struct mtd_ooblayout_ops tc58cxgxsx_ooblayout = {
54− .ecc = tc58cxgxsx_ooblayout_ecc,
55− .free = tc58cxgxsx_ooblayout_free,
66+static const struct mtd_ooblayout_ops tx58cxgxsxraix_ooblayout = {
67+ .ecc = tx58cxgxsxraix_ooblayout_ecc,
68+ .free = tx58cxgxsxraix_ooblayout_free,
5669 };
5770
58−static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand,
59− u8 status)
71+static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
72+ u8 status)
6073 {
6174 struct nand_device *nand = spinand_to_nand(spinand);
6275 u8 mbf = 0;
@@ -94,105 +107,174 @@ static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand, · 31 unmodified lines
94107 }
95108
96109 static const struct spinand_info toshiba_spinand_table[] = {
97− /* 3.3V 1Gb */
98− SPINAND_INFO("TC58CVG0S3", 0xC2,
110+ /* 3.3V 1Gb (1st generation) */
111+ SPINAND_INFO("TC58CVG0S3HRAIG",
112+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2),
99113 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
100114 NAND_ECCREQ(8, 512),
101115 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
102116 &write_cache_variants,
103117 &update_cache_variants),
104118 0,
105− SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
106− tc58cxgxsx_ecc_get_status)),
107− /* 3.3V 2Gb */
108− SPINAND_INFO("TC58CVG1S3", 0xCB,
119+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
120+ tx58cxgxsxraix_ecc_get_status)),
121+ /* 3.3V 2Gb (1st generation) */
122+ SPINAND_INFO("TC58CVG1S3HRAIG",
123+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB),
109124 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
110125 NAND_ECCREQ(8, 512),
111126 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
112127 &write_cache_variants,
113128 &update_cache_variants),
114129 0,
115− SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
116− tc58cxgxsx_ecc_get_status)),
117− /* 3.3V 4Gb */
118− SPINAND_INFO("TC58CVG2S0", 0xCD,
119− NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
120− NAND_ECCREQ(8, 512),
121− SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
122− &write_cache_variants,
123− &update_cache_variants),
124− 0,
125− SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
126− tc58cxgxsx_ecc_get_status)),
127− /* 3.3V 4Gb */
128− SPINAND_INFO("TC58CVG2S0", 0xED,
130+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
131+ tx58cxgxsxraix_ecc_get_status)),
132+ /* 3.3V 4Gb (1st generation) */
133+ SPINAND_INFO("TC58CVG2S0HRAIG",
134+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD),
129135 NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
130136 NAND_ECCREQ(8, 512),
131137 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
132138 &write_cache_variants,
133139 &update_cache_variants),
134140 0,
135− SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
136− tc58cxgxsx_ecc_get_status)),
137− /* 1.8V 1Gb */
138− SPINAND_INFO("TC58CYG0S3", 0xB2,
141+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
142+ tx58cxgxsxraix_ecc_get_status)),
143+ /* 1.8V 1Gb (1st generation) */
144+ SPINAND_INFO("TC58CYG0S3HRAIG",
145+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
139146 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
140147 NAND_ECCREQ(8, 512),
141148 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
142149 &write_cache_variants,
143150 &update_cache_variants),
144151 0,
145− SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
146− tc58cxgxsx_ecc_get_status)),
147− /* 1.8V 2Gb */
148− SPINAND_INFO("TC58CYG1S3", 0xBB,
152+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
153+ tx58cxgxsxraix_ecc_get_status)),
154+ /* 1.8V 2Gb (1st generation) */
155+ SPINAND_INFO("TC58CYG1S3HRAIG",
156+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB),
149157 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
150158 NAND_ECCREQ(8, 512),
151159 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
152160 &write_cache_variants,
153161 &update_cache_variants),
154162 0,
155− SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
156− tc58cxgxsx_ecc_get_status)),
157− /* 1.8V 4Gb */
158− SPINAND_INFO("TC58CYG2S0", 0xBD,
163+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
164+ tx58cxgxsxraix_ecc_get_status)),
165+ /* 1.8V 4Gb (1st generation) */
166+ SPINAND_INFO("TC58CYG2S0HRAIG",
167+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD),
159168 NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
160169 NAND_ECCREQ(8, 512),
161170 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
162171 &write_cache_variants,
163172 &update_cache_variants),
164173 0,
165− SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
166− tc58cxgxsx_ecc_get_status)),
167−};
168−
169−static int toshiba_spinand_detect(struct spinand_device *spinand)
170−{
171− u8 *id = spinand->id.data;
172− int ret;
174+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
175+ tx58cxgxsxraix_ecc_get_status)),
173176
174177 /*
175− * Toshiba SPI NAND read ID needs a dummy byte,
176− * so the first byte in id is garbage.
178+ * 2nd generation serial nand has HOLD_D which is equivalent to
179+ * QE_BIT.
177180 */
178− if (id[1] != SPINAND_MFR_TOSHIBA)
179− return 0;
180−
181− ret = spinand_match_and_init(spinand, toshiba_spinand_table,
182− ARRAY_SIZE(toshiba_spinand_table),
183− id[2]);
184− if (ret)
185− return ret;
186−
187− return 1;
188−}
181+ /* 3.3V 1Gb (2nd generation) */
182+ SPINAND_INFO("TC58CVG0S3HRAIJ",
183+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2),
184+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
185+ NAND_ECCREQ(8, 512),
186+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
187+ &write_cache_x4_variants,
188+ &update_cache_x4_variants),
189+ SPINAND_HAS_QE_BIT,
190+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
191+ tx58cxgxsxraix_ecc_get_status)),
192+ /* 3.3V 2Gb (2nd generation) */
193+ SPINAND_INFO("TC58CVG1S3HRAIJ",
194+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB),
195+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
196+ NAND_ECCREQ(8, 512),
197+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
198+ &write_cache_x4_variants,
199+ &update_cache_x4_variants),
200+ SPINAND_HAS_QE_BIT,
201+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
202+ tx58cxgxsxraix_ecc_get_status)),
203+ /* 3.3V 4Gb (2nd generation) */
204+ SPINAND_INFO("TC58CVG2S0HRAIJ",
205+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED),
206+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
207+ NAND_ECCREQ(8, 512),
208+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
209+ &write_cache_x4_variants,
210+ &update_cache_x4_variants),
211+ SPINAND_HAS_QE_BIT,
212+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
213+ tx58cxgxsxraix_ecc_get_status)),
214+ /* 3.3V 8Gb (2nd generation) */
215+ SPINAND_INFO("TH58CVG3S0HRAIJ",
216+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
217+ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
218+ NAND_ECCREQ(8, 512),
219+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
220+ &write_cache_x4_variants,
221+ &update_cache_x4_variants),
222+ SPINAND_HAS_QE_BIT,
223+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
224+ tx58cxgxsxraix_ecc_get_status)),
225+ /* 1.8V 1Gb (2nd generation) */
226+ SPINAND_INFO("TC58CYG0S3HRAIJ",
227+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2),
228+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
229+ NAND_ECCREQ(8, 512),
230+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
231+ &write_cache_x4_variants,
232+ &update_cache_x4_variants),
233+ SPINAND_HAS_QE_BIT,
234+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
235+ tx58cxgxsxraix_ecc_get_status)),
236+ /* 1.8V 2Gb (2nd generation) */
237+ SPINAND_INFO("TC58CYG1S3HRAIJ",
238+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB),
239+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
240+ NAND_ECCREQ(8, 512),
241+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
242+ &write_cache_x4_variants,
243+ &update_cache_x4_variants),
244+ SPINAND_HAS_QE_BIT,
245+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
246+ tx58cxgxsxraix_ecc_get_status)),
247+ /* 1.8V 4Gb (2nd generation) */
248+ SPINAND_INFO("TC58CYG2S0HRAIJ",
249+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD),
250+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
251+ NAND_ECCREQ(8, 512),
252+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
253+ &write_cache_x4_variants,
254+ &update_cache_x4_variants),
255+ SPINAND_HAS_QE_BIT,
256+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
257+ tx58cxgxsxraix_ecc_get_status)),
258+ /* 1.8V 8Gb (2nd generation) */
259+ SPINAND_INFO("TH58CYG3S0HRAIJ",
260+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
261+ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
262+ NAND_ECCREQ(8, 512),
263+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
264+ &write_cache_x4_variants,
265+ &update_cache_x4_variants),
266+ SPINAND_HAS_QE_BIT,
267+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
268+ tx58cxgxsxraix_ecc_get_status)),
269+};
189270
190271 static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = {
191− .detect = toshiba_spinand_detect,
192272 };
193273
194274 const struct spinand_manufacturer toshiba_spinand_manufacturer = {
195275 .id = SPINAND_MFR_TOSHIBA,
196276 .name = "Toshiba",
277+ .chips = toshiba_spinand_table,
278+ .nchips = ARRAY_SIZE(toshiba_spinand_table),
197279 .ops = &toshiba_spinand_manuf_ops,
198280 };
drivers/mtd/nand/spi/winbond.c+6−28
@@ -75,7 +75,8 @@ static int w25m02gv_select_target(struct spinand_device *spinand, · 74 unmodified lines
7575 }
7676
7777 static const struct spinand_info winbond_spinand_table[] = {
78− SPINAND_INFO("W25M02GV", 0xAB,
78+ SPINAND_INFO("W25M02GV",
79+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab),
7980 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2),
8081 NAND_ECCREQ(1, 512),
8182 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -84,7 +85,8 @@ static const struct spinand_info winbond_spinand_table[] = { · 2 unmodified lines
8485 0,
8586 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
8687 SPINAND_SELECT_TARGET(w25m02gv_select_target)),
87− SPINAND_INFO("W25N01GV", 0xAA,
88+ SPINAND_INFO("W25N01GV",
89+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa),
8890 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
8991 NAND_ECCREQ(1, 512),
9092 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -94,31 +96,6 @@ static const struct spinand_info winbond_spinand_table[] = { · 3 unmodified lines
9496 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
9597 };
9698
97−/**
98− * winbond_spinand_detect - initialize device related part in spinand_device
99− * struct if it is a Winbond device.
100− * @spinand: SPI NAND device structure
101− */
102−static int winbond_spinand_detect(struct spinand_device *spinand)
103−{
104− u8 *id = spinand->id.data;
105− int ret;
106−
107− /*
108− * Winbond SPI NAND read ID need a dummy byte,
109− * so the first byte in raw_id is dummy.
110− */
111− if (id[1] != SPINAND_MFR_WINBOND)
112− return 0;
113−
114− ret = spinand_match_and_init(spinand, winbond_spinand_table,
115− ARRAY_SIZE(winbond_spinand_table), id[2]);
116− if (ret)
117− return ret;
118−
119− return 1;
120−}
121−
12299 static int winbond_spinand_init(struct spinand_device *spinand)
123100 {
124101 struct nand_device *nand = spinand_to_nand(spinand);
@@ -138,12 +115,13 @@ static int winbond_spinand_init(struct spinand_device *spinand) · 13 unmodified lines
138115 }
139116
140117 static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
141− .detect = winbond_spinand_detect,
142118 .init = winbond_spinand_init,
143119 };
144120
145121 const struct spinand_manufacturer winbond_spinand_manufacturer = {
146122 .id = SPINAND_MFR_WINBOND,
147123 .name = "Winbond",
124+ .chips = winbond_spinand_table,
125+ .nchips = ARRAY_SIZE(winbond_spinand_table),
148126 .ops = &winbond_spinand_manuf_ops,
149127 };
drivers/mtd/spi-nor/Kconfig+1−74
@@ -24,79 +24,6 @@ config MTD_SPI_NOR_USE_4K_SECTORS · 23 unmodified lines
2424 Please note that some tools/drivers/filesystems may not work with
2525 4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).
2626
27−config SPI_ASPEED_SMC
28− tristate "Aspeed flash controllers in SPI mode"
29− depends on ARCH_ASPEED || COMPILE_TEST
30− depends on HAS_IOMEM && OF
31− help
32− This enables support for the Firmware Memory controller (FMC)
33− in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips,
34− and support for the SPI flash memory controller (SPI) for
35− the host firmware. The implementation only supports SPI NOR.
36−
37−config SPI_CADENCE_QUADSPI
38− tristate "Cadence Quad SPI controller"
39− depends on OF && (ARM || ARM64 || COMPILE_TEST)
40− help
41− Enable support for the Cadence Quad SPI Flash controller.
42−
43− Cadence QSPI is a specialized controller for connecting an SPI
44− Flash over 1/2/4-bit wide bus. Enable this option if you have a
45− device with a Cadence QSPI controller and want to access the
46− Flash as an MTD device.
47−
48−config SPI_HISI_SFC
49− tristate "Hisilicon FMC SPI-NOR Flash Controller(SFC)"
50− depends on ARCH_HISI || COMPILE_TEST
51− depends on HAS_IOMEM
52− help
53− This enables support for HiSilicon FMC SPI-NOR flash controller.
54−
55−config SPI_NXP_SPIFI
56− tristate "NXP SPI Flash Interface (SPIFI)"
57− depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
58− depends on HAS_IOMEM
59− help
60− Enable support for the NXP LPC SPI Flash Interface controller.
61−
62− SPIFI is a specialized controller for connecting serial SPI
63− Flash. Enable this option if you have a device with a SPIFI
64− controller and want to access the Flash as a mtd device.
65−
66−config SPI_INTEL_SPI
67− tristate
68−
69−config SPI_INTEL_SPI_PCI
70− tristate "Intel PCH/PCU SPI flash PCI driver (DANGEROUS)"
71− depends on X86 && PCI
72− select SPI_INTEL_SPI
73− help
74− This enables PCI support for the Intel PCH/PCU SPI controller in
75− master mode. This controller is present in modern Intel hardware
76− and is used to hold BIOS and other persistent settings. Using
77− this driver it is possible to upgrade BIOS directly from Linux.
78−
79− Say N here unless you know what you are doing. Overwriting the
80− SPI flash may render the system unbootable.
81−
82− To compile this driver as a module, choose M here: the module
83− will be called intel-spi-pci.
84−
85−config SPI_INTEL_SPI_PLATFORM
86− tristate "Intel PCH/PCU SPI flash platform driver (DANGEROUS)"
87− depends on X86
88− select SPI_INTEL_SPI
89− help
90− This enables platform support for the Intel PCH/PCU SPI
91− controller in master mode. This controller is present in modern
92− Intel hardware and is used to hold BIOS and other persistent
93− settings. Using this driver it is possible to upgrade BIOS
94− directly from Linux.
95−
96− Say N here unless you know what you are doing. Overwriting the
97− SPI flash may render the system unbootable.
98−
99− To compile this driver as a module, choose M here: the module
100− will be called intel-spi-platform.
27+source "drivers/mtd/spi-nor/controllers/Kconfig"
10128
10229 endif # MTD_SPI_NOR
drivers/mtd/spi-nor/Makefile+18−7
@@ -1,9 +1,20 @@
11 # SPDX-License-Identifier: GPL-2.0
2+
3+spi-nor-objs := core.o sfdp.o
4+spi-nor-objs += atmel.o
5+spi-nor-objs += catalyst.o
6+spi-nor-objs += eon.o
7+spi-nor-objs += esmt.o
8+spi-nor-objs += everspin.o
9+spi-nor-objs += fujitsu.o
10+spi-nor-objs += gigadevice.o
11+spi-nor-objs += intel.o
12+spi-nor-objs += issi.o
13+spi-nor-objs += macronix.o
14+spi-nor-objs += micron-st.o
15+spi-nor-objs += spansion.o
16+spi-nor-objs += sst.o
17+spi-nor-objs += winbond.o
18+spi-nor-objs += xilinx.o
19+spi-nor-objs += xmc.o
220 obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
3−obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
4−obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o
5−obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
6−obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
7−obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
8−obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o
9−obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o
drivers/mtd/spi-nor/atmel.c+46−0
@@ -0,0 +1,46 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static const struct flash_info atmel_parts[] = {
12+ /* Atmel -- some are (confusingly) marketed as "DataFlash" */
13+ { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
14+ { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
15+
16+ { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
17+ { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
18+ { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
19+ { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
20+
21+ { "at25sl321", INFO(0x1f4216, 0, 64 * 1024, 64,
22+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
23+
24+ { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
25+ { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
26+ { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
27+ { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
28+
29+ { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
30+};
31+
32+static void atmel_default_init(struct spi_nor *nor)
33+{
34+ nor->flags |= SNOR_F_HAS_LOCK;
35+}
36+
37+static const struct spi_nor_fixups atmel_fixups = {
38+ .default_init = atmel_default_init,
39+};
40+
41+const struct spi_nor_manufacturer spi_nor_atmel = {
42+ .name = "atmel",
43+ .parts = atmel_parts,
44+ .nparts = ARRAY_SIZE(atmel_parts),
45+ .fixups = &atmel_fixups,
46+};
drivers/mtd/spi-nor/catalyst.c+29−0
@@ -0,0 +1,29 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static const struct flash_info catalyst_parts[] = {
12+ /* Catalyst / On Semiconductor -- non-JEDEC */
13+ { "cat25c11", CAT25_INFO(16, 8, 16, 1,
14+ SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
15+ { "cat25c03", CAT25_INFO(32, 8, 16, 2,
16+ SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
17+ { "cat25c09", CAT25_INFO(128, 8, 32, 2,
18+ SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
19+ { "cat25c17", CAT25_INFO(256, 8, 32, 2,
20+ SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
21+ { "cat25128", CAT25_INFO(2048, 8, 64, 2,
22+ SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
23+};
24+
25+const struct spi_nor_manufacturer spi_nor_catalyst = {
26+ .name = "catalyst",
27+ .parts = catalyst_parts,
28+ .nparts = ARRAY_SIZE(catalyst_parts),
29+};
drivers/mtd/spi-nor/controllers/Kconfig+75−0
@@ -0,0 +1,75 @@
1+# SPDX-License-Identifier: GPL-2.0-only
2+config SPI_ASPEED_SMC
3+ tristate "Aspeed flash controllers in SPI mode"
4+ depends on ARCH_ASPEED || COMPILE_TEST
5+ depends on HAS_IOMEM && OF
6+ help
7+ This enables support for the Firmware Memory controller (FMC)
8+ in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips,
9+ and support for the SPI flash memory controller (SPI) for
10+ the host firmware. The implementation only supports SPI NOR.
11+
12+config SPI_CADENCE_QUADSPI
13+ tristate "Cadence Quad SPI controller"
14+ depends on OF && (ARM || ARM64 || COMPILE_TEST)
15+ help
16+ Enable support for the Cadence Quad SPI Flash controller.
17+
18+ Cadence QSPI is a specialized controller for connecting an SPI
19+ Flash over 1/2/4-bit wide bus. Enable this option if you have a
20+ device with a Cadence QSPI controller and want to access the
21+ Flash as an MTD device.
22+
23+config SPI_HISI_SFC
24+ tristate "Hisilicon FMC SPI-NOR Flash Controller(SFC)"
25+ depends on ARCH_HISI || COMPILE_TEST
26+ depends on HAS_IOMEM
27+ help
28+ This enables support for HiSilicon FMC SPI-NOR flash controller.
29+
30+config SPI_NXP_SPIFI
31+ tristate "NXP SPI Flash Interface (SPIFI)"
32+ depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
33+ depends on HAS_IOMEM
34+ help
35+ Enable support for the NXP LPC SPI Flash Interface controller.
36+
37+ SPIFI is a specialized controller for connecting serial SPI
38+ Flash. Enable this option if you have a device with a SPIFI
39+ controller and want to access the Flash as a mtd device.
40+
41+config SPI_INTEL_SPI
42+ tristate
43+
44+config SPI_INTEL_SPI_PCI
45+ tristate "Intel PCH/PCU SPI flash PCI driver (DANGEROUS)"
46+ depends on X86 && PCI
47+ select SPI_INTEL_SPI
48+ help
49+ This enables PCI support for the Intel PCH/PCU SPI controller in
50+ master mode. This controller is present in modern Intel hardware
51+ and is used to hold BIOS and other persistent settings. Using
52+ this driver it is possible to upgrade BIOS directly from Linux.
53+
54+ Say N here unless you know what you are doing. Overwriting the
55+ SPI flash may render the system unbootable.
56+
57+ To compile this driver as a module, choose M here: the module
58+ will be called intel-spi-pci.
59+
60+config SPI_INTEL_SPI_PLATFORM
61+ tristate "Intel PCH/PCU SPI flash platform driver (DANGEROUS)"
62+ depends on X86
63+ select SPI_INTEL_SPI
64+ help
65+ This enables platform support for the Intel PCH/PCU SPI
66+ controller in master mode. This controller is present in modern
67+ Intel hardware and is used to hold BIOS and other persistent
68+ settings. Using this driver it is possible to upgrade BIOS
69+ directly from Linux.
70+
71+ Say N here unless you know what you are doing. Overwriting the
72+ SPI flash may render the system unbootable.
73+
74+ To compile this driver as a module, choose M here: the module
75+ will be called intel-spi-platform.
drivers/mtd/spi-nor/controllers/Makefile+8−0
@@ -0,0 +1,8 @@
1+# SPDX-License-Identifier: GPL-2.0
2+obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
3+obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o
4+obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
5+obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
6+obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
7+obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o
8+obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o
drivers/mtd/spi-nor/controllers/aspeed-smc.crenamed from drivers/mtd/spi-nor/aspeed-smc.c+2−2
@@ -109,7 +109,7 @@ struct aspeed_smc_controller { · 108 unmodified lines
109109 void __iomem *ahb_base; /* per-chip windows resource */
110110 u32 ahb_window_size; /* full mapping window size */
111111
112− struct aspeed_smc_chip *chips[0]; /* pointers to attached chips */
112+ struct aspeed_smc_chip *chips[]; /* pointers to attached chips */
113113 };
114114
115115 /*
@@ -354,7 +354,7 @@ static void aspeed_smc_send_cmd_addr(struct spi_nor *nor, u8 cmd, u32 addr) · 238 unmodified lines
354354 default:
355355 WARN_ONCE(1, "Unexpected address width %u, defaulting to 3\n",
356356 nor->addr_width);
357− /* FALLTHROUGH */
357+ fallthrough;
358358 case 3:
359359 cmdaddr = addr & 0xFFFFFF;
360360 cmdaddr |= cmd << 24;
drivers/mtd/spi-nor/controllers/cadence-quadspi.crenamed from drivers/mtd/spi-nor/cadence-quadspi.c+0−0

File renamed without changes.

drivers/mtd/spi-nor/controllers/hisi-sfc.crenamed from drivers/mtd/spi-nor/hisi-sfc.c+0−0

File renamed without changes.

drivers/mtd/spi-nor/controllers/intel-spi-pci.crenamed from drivers/mtd/spi-nor/intel-spi-pci.c+0−0

File renamed without changes.

drivers/mtd/spi-nor/controllers/intel-spi-platform.crenamed from drivers/mtd/spi-nor/intel-spi-platform.c+0−0

File renamed without changes.

drivers/mtd/spi-nor/controllers/intel-spi.crenamed from drivers/mtd/spi-nor/intel-spi.c+0−0

File renamed without changes.

drivers/mtd/spi-nor/controllers/intel-spi.hrenamed from drivers/mtd/spi-nor/intel-spi.h+0−0

File renamed without changes.

drivers/mtd/spi-nor/controllers/nxp-spifi.crenamed from drivers/mtd/spi-nor/nxp-spifi.c+0−0

File renamed without changes.

drivers/mtd/spi-nor/core.c+3466−0
@@ -0,0 +1,3466 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4+ * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5+ *
6+ * Copyright (C) 2005, Intec Automation Inc.
7+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
8+ */
9+
10+#include <linux/err.h>
11+#include <linux/errno.h>
12+#include <linux/module.h>
13+#include <linux/device.h>
14+#include <linux/mutex.h>
15+#include <linux/math64.h>
16+#include <linux/sizes.h>
17+#include <linux/slab.h>
18+
19+#include <linux/mtd/mtd.h>
20+#include <linux/of_platform.h>
21+#include <linux/sched/task_stack.h>
22+#include <linux/spi/flash.h>
23+#include <linux/mtd/spi-nor.h>
24+
25+#include "core.h"
26+
27+/* Define max times to check status register before we give up. */
28+
29+/*
30+ * For everything but full-chip erase; probably could be much smaller, but kept
31+ * around for safety for now
32+ */
33+#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
34+
35+/*
36+ * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
37+ * for larger flash
38+ */
39+#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
40+
41+#define SPI_NOR_MAX_ADDR_WIDTH 4
42+
43+/**
44+ * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data
45+ * transfer
46+ * @nor: pointer to 'struct spi_nor'
47+ * @op: pointer to 'struct spi_mem_op' template for transfer
48+ *
49+ * If we have to use the bounce buffer, the data field in @op will be updated.
50+ *
51+ * Return: true if the bounce buffer is needed, false if not
52+ */
53+static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op)
54+{
55+ /* op->data.buf.in occupies the same memory as op->data.buf.out */
56+ if (object_is_on_stack(op->data.buf.in) ||
57+ !virt_addr_valid(op->data.buf.in)) {
58+ if (op->data.nbytes > nor->bouncebuf_size)
59+ op->data.nbytes = nor->bouncebuf_size;
60+ op->data.buf.in = nor->bouncebuf;
61+ return true;
62+ }
63+
64+ return false;
65+}
66+
67+/**
68+ * spi_nor_spimem_exec_op() - execute a memory operation
69+ * @nor: pointer to 'struct spi_nor'
70+ * @op: pointer to 'struct spi_mem_op' template for transfer
71+ *
72+ * Return: 0 on success, -error otherwise.
73+ */
74+static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op)
75+{
76+ int error;
77+
78+ error = spi_mem_adjust_op_size(nor->spimem, op);
79+ if (error)
80+ return error;
81+
82+ return spi_mem_exec_op(nor->spimem, op);
83+}
84+
85+/**
86+ * spi_nor_spimem_read_data() - read data from flash's memory region via
87+ * spi-mem
88+ * @nor: pointer to 'struct spi_nor'
89+ * @from: offset to read from
90+ * @len: number of bytes to read
91+ * @buf: pointer to dst buffer
92+ *
93+ * Return: number of bytes read successfully, -errno otherwise
94+ */
95+static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,
96+ size_t len, u8 *buf)
97+{
98+ struct spi_mem_op op =
99+ SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
100+ SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
101+ SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
102+ SPI_MEM_OP_DATA_IN(len, buf, 1));
103+ bool usebouncebuf;
104+ ssize_t nbytes;
105+ int error;
106+
107+ /* get transfer protocols. */
108+ op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
109+ op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
110+ op.dummy.buswidth = op.addr.buswidth;
111+ op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
112+
113+ /* convert the dummy cycles to the number of bytes */
114+ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
115+
116+ usebouncebuf = spi_nor_spimem_bounce(nor, &op);
117+
118+ if (nor->dirmap.rdesc) {
119+ nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val,
120+ op.data.nbytes, op.data.buf.in);
121+ } else {
122+ error = spi_nor_spimem_exec_op(nor, &op);
123+ if (error)
124+ return error;
125+ nbytes = op.data.nbytes;
126+ }
127+
128+ if (usebouncebuf && nbytes > 0)
129+ memcpy(buf, op.data.buf.in, nbytes);
130+
131+ return nbytes;
132+}
133+
134+/**
135+ * spi_nor_read_data() - read data from flash memory
136+ * @nor: pointer to 'struct spi_nor'
137+ * @from: offset to read from
138+ * @len: number of bytes to read
139+ * @buf: pointer to dst buffer
140+ *
141+ * Return: number of bytes read successfully, -errno otherwise
142+ */
143+ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf)
144+{
145+ if (nor->spimem)
146+ return spi_nor_spimem_read_data(nor, from, len, buf);
147+
148+ return nor->controller_ops->read(nor, from, len, buf);
149+}
150+
151+/**
152+ * spi_nor_spimem_write_data() - write data to flash memory via
153+ * spi-mem
154+ * @nor: pointer to 'struct spi_nor'
155+ * @to: offset to write to
156+ * @len: number of bytes to write
157+ * @buf: pointer to src buffer
158+ *
159+ * Return: number of bytes written successfully, -errno otherwise
160+ */
161+static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
162+ size_t len, const u8 *buf)
163+{
164+ struct spi_mem_op op =
165+ SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
166+ SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
167+ SPI_MEM_OP_NO_DUMMY,
168+ SPI_MEM_OP_DATA_OUT(len, buf, 1));
169+ ssize_t nbytes;
170+ int error;
171+
172+ op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
173+ op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
174+ op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
175+
176+ if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
177+ op.addr.nbytes = 0;
178+
179+ if (spi_nor_spimem_bounce(nor, &op))
180+ memcpy(nor->bouncebuf, buf, op.data.nbytes);
181+
182+ if (nor->dirmap.wdesc) {
183+ nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val,
184+ op.data.nbytes, op.data.buf.out);
185+ } else {
186+ error = spi_nor_spimem_exec_op(nor, &op);
187+ if (error)
188+ return error;
189+ nbytes = op.data.nbytes;
190+ }
191+
192+ return nbytes;
193+}
194+
195+/**
196+ * spi_nor_write_data() - write data to flash memory
197+ * @nor: pointer to 'struct spi_nor'
198+ * @to: offset to write to
199+ * @len: number of bytes to write
200+ * @buf: pointer to src buffer
201+ *
202+ * Return: number of bytes written successfully, -errno otherwise
203+ */
204+ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
205+ const u8 *buf)
206+{
207+ if (nor->spimem)
208+ return spi_nor_spimem_write_data(nor, to, len, buf);
209+
210+ return nor->controller_ops->write(nor, to, len, buf);
211+}
212+
213+/**
214+ * spi_nor_write_enable() - Set write enable latch with Write Enable command.
215+ * @nor: pointer to 'struct spi_nor'.
216+ *
217+ * Return: 0 on success, -errno otherwise.
218+ */
219+int spi_nor_write_enable(struct spi_nor *nor)
220+{
221+ int ret;
222+
223+ if (nor->spimem) {
224+ struct spi_mem_op op =
225+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1),
226+ SPI_MEM_OP_NO_ADDR,
227+ SPI_MEM_OP_NO_DUMMY,
228+ SPI_MEM_OP_NO_DATA);
229+
230+ ret = spi_mem_exec_op(nor->spimem, &op);
231+ } else {
232+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREN,
233+ NULL, 0);
234+ }
235+
236+ if (ret)
237+ dev_dbg(nor->dev, "error %d on Write Enable\n", ret);
238+
239+ return ret;
240+}
241+
242+/**
243+ * spi_nor_write_disable() - Send Write Disable instruction to the chip.
244+ * @nor: pointer to 'struct spi_nor'.
245+ *
246+ * Return: 0 on success, -errno otherwise.
247+ */
248+int spi_nor_write_disable(struct spi_nor *nor)
249+{
250+ int ret;
251+
252+ if (nor->spimem) {
253+ struct spi_mem_op op =
254+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1),
255+ SPI_MEM_OP_NO_ADDR,
256+ SPI_MEM_OP_NO_DUMMY,
257+ SPI_MEM_OP_NO_DATA);
258+
259+ ret = spi_mem_exec_op(nor->spimem, &op);
260+ } else {
261+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI,
262+ NULL, 0);
263+ }
264+
265+ if (ret)
266+ dev_dbg(nor->dev, "error %d on Write Disable\n", ret);
267+
268+ return ret;
269+}
270+
271+/**
272+ * spi_nor_read_sr() - Read the Status Register.
273+ * @nor: pointer to 'struct spi_nor'.
274+ * @sr: pointer to a DMA-able buffer where the value of the
275+ * Status Register will be written.
276+ *
277+ * Return: 0 on success, -errno otherwise.
278+ */
279+static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
280+{
281+ int ret;
282+
283+ if (nor->spimem) {
284+ struct spi_mem_op op =
285+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1),
286+ SPI_MEM_OP_NO_ADDR,
287+ SPI_MEM_OP_NO_DUMMY,
288+ SPI_MEM_OP_DATA_IN(1, sr, 1));
289+
290+ ret = spi_mem_exec_op(nor->spimem, &op);
291+ } else {
292+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR,
293+ sr, 1);
294+ }
295+
296+ if (ret)
297+ dev_dbg(nor->dev, "error %d reading SR\n", ret);
298+
299+ return ret;
300+}
301+
302+/**
303+ * spi_nor_read_fsr() - Read the Flag Status Register.
304+ * @nor: pointer to 'struct spi_nor'
305+ * @fsr: pointer to a DMA-able buffer where the value of the
306+ * Flag Status Register will be written.
307+ *
308+ * Return: 0 on success, -errno otherwise.
309+ */
310+static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
311+{
312+ int ret;
313+
314+ if (nor->spimem) {
315+ struct spi_mem_op op =
316+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 1),
317+ SPI_MEM_OP_NO_ADDR,
318+ SPI_MEM_OP_NO_DUMMY,
319+ SPI_MEM_OP_DATA_IN(1, fsr, 1));
320+
321+ ret = spi_mem_exec_op(nor->spimem, &op);
322+ } else {
323+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDFSR,
324+ fsr, 1);
325+ }
326+
327+ if (ret)
328+ dev_dbg(nor->dev, "error %d reading FSR\n", ret);
329+
330+ return ret;
331+}
332+
333+/**
334+ * spi_nor_read_cr() - Read the Configuration Register using the
335+ * SPINOR_OP_RDCR (35h) command.
336+ * @nor: pointer to 'struct spi_nor'
337+ * @cr: pointer to a DMA-able buffer where the value of the
338+ * Configuration Register will be written.
339+ *
340+ * Return: 0 on success, -errno otherwise.
341+ */
342+static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
343+{
344+ int ret;
345+
346+ if (nor->spimem) {
347+ struct spi_mem_op op =
348+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 1),
349+ SPI_MEM_OP_NO_ADDR,
350+ SPI_MEM_OP_NO_DUMMY,
351+ SPI_MEM_OP_DATA_IN(1, cr, 1));
352+
353+ ret = spi_mem_exec_op(nor->spimem, &op);
354+ } else {
355+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR, cr, 1);
356+ }
357+
358+ if (ret)
359+ dev_dbg(nor->dev, "error %d reading CR\n", ret);
360+
361+ return ret;
362+}
363+
364+/**
365+ * spi_nor_set_4byte_addr_mode() - Enter/Exit 4-byte address mode.
366+ * @nor: pointer to 'struct spi_nor'.
367+ * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
368+ * address mode.
369+ *
370+ * Return: 0 on success, -errno otherwise.
371+ */
372+int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
373+{
374+ int ret;
375+
376+ if (nor->spimem) {
377+ struct spi_mem_op op =
378+ SPI_MEM_OP(SPI_MEM_OP_CMD(enable ?
379+ SPINOR_OP_EN4B :
380+ SPINOR_OP_EX4B,
381+ 1),
382+ SPI_MEM_OP_NO_ADDR,
383+ SPI_MEM_OP_NO_DUMMY,
384+ SPI_MEM_OP_NO_DATA);
385+
386+ ret = spi_mem_exec_op(nor->spimem, &op);
387+ } else {
388+ ret = nor->controller_ops->write_reg(nor,
389+ enable ? SPINOR_OP_EN4B :
390+ SPINOR_OP_EX4B,
391+ NULL, 0);
392+ }
393+
394+ if (ret)
395+ dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
396+
397+ return ret;
398+}
399+
400+/**
401+ * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion
402+ * flashes.
403+ * @nor: pointer to 'struct spi_nor'.
404+ * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
405+ * address mode.
406+ *
407+ * Return: 0 on success, -errno otherwise.
408+ */
409+static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
410+{
411+ int ret;
412+
413+ nor->bouncebuf[0] = enable << 7;
414+
415+ if (nor->spimem) {
416+ struct spi_mem_op op =
417+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 1),
418+ SPI_MEM_OP_NO_ADDR,
419+ SPI_MEM_OP_NO_DUMMY,
420+ SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1));
421+
422+ ret = spi_mem_exec_op(nor->spimem, &op);
423+ } else {
424+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_BRWR,
425+ nor->bouncebuf, 1);
426+ }
427+
428+ if (ret)
429+ dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
430+
431+ return ret;
432+}
433+
434+/**
435+ * spi_nor_write_ear() - Write Extended Address Register.
436+ * @nor: pointer to 'struct spi_nor'.
437+ * @ear: value to write to the Extended Address Register.
438+ *
439+ * Return: 0 on success, -errno otherwise.
440+ */
441+int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
442+{
443+ int ret;
444+
445+ nor->bouncebuf[0] = ear;
446+
447+ if (nor->spimem) {
448+ struct spi_mem_op op =
449+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 1),
450+ SPI_MEM_OP_NO_ADDR,
451+ SPI_MEM_OP_NO_DUMMY,
452+ SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1));
453+
454+ ret = spi_mem_exec_op(nor->spimem, &op);
455+ } else {
456+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREAR,
457+ nor->bouncebuf, 1);
458+ }
459+
460+ if (ret)
461+ dev_dbg(nor->dev, "error %d writing EAR\n", ret);
462+
463+ return ret;
464+}
465+
466+/**
467+ * spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
468+ * @nor: pointer to 'struct spi_nor'.
469+ * @sr: pointer to a DMA-able buffer where the value of the
470+ * Status Register will be written.
471+ *
472+ * Return: 0 on success, -errno otherwise.
473+ */
474+int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
475+{
476+ int ret;
477+
478+ if (nor->spimem) {
479+ struct spi_mem_op op =
480+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 1),
481+ SPI_MEM_OP_NO_ADDR,
482+ SPI_MEM_OP_NO_DUMMY,
483+ SPI_MEM_OP_DATA_IN(1, sr, 1));
484+
485+ ret = spi_mem_exec_op(nor->spimem, &op);
486+ } else {
487+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR,
488+ sr, 1);
489+ }
490+
491+ if (ret)
492+ dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
493+
494+ return ret;
495+}
496+
497+/**
498+ * spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to see if
499+ * the flash is ready for new commands.
500+ * @nor: pointer to 'struct spi_nor'.
501+ *
502+ * Return: 0 on success, -errno otherwise.
503+ */
504+static int spi_nor_xsr_ready(struct spi_nor *nor)
505+{
506+ int ret;
507+
508+ ret = spi_nor_xread_sr(nor, nor->bouncebuf);
509+ if (ret)
510+ return ret;
511+
512+ return !!(nor->bouncebuf[0] & XSR_RDY);
513+}
514+
515+/**
516+ * spi_nor_clear_sr() - Clear the Status Register.
517+ * @nor: pointer to 'struct spi_nor'.
518+ */
519+static void spi_nor_clear_sr(struct spi_nor *nor)
520+{
521+ int ret;
522+
523+ if (nor->spimem) {
524+ struct spi_mem_op op =
525+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 1),
526+ SPI_MEM_OP_NO_ADDR,
527+ SPI_MEM_OP_NO_DUMMY,
528+ SPI_MEM_OP_NO_DATA);
529+
530+ ret = spi_mem_exec_op(nor->spimem, &op);
531+ } else {
532+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR,
533+ NULL, 0);
534+ }
535+
536+ if (ret)
537+ dev_dbg(nor->dev, "error %d clearing SR\n", ret);
538+}
539+
540+/**
541+ * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
542+ * for new commands.
543+ * @nor: pointer to 'struct spi_nor'.
544+ *
545+ * Return: 0 on success, -errno otherwise.
546+ */
547+static int spi_nor_sr_ready(struct spi_nor *nor)
548+{
549+ int ret = spi_nor_read_sr(nor, nor->bouncebuf);
550+
551+ if (ret)
552+ return ret;
553+
554+ if (nor->flags & SNOR_F_USE_CLSR &&
555+ nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
556+ if (nor->bouncebuf[0] & SR_E_ERR)
557+ dev_err(nor->dev, "Erase Error occurred\n");
558+ else
559+ dev_err(nor->dev, "Programming Error occurred\n");
560+
561+ spi_nor_clear_sr(nor);
562+
563+ /*
564+ * WEL bit remains set to one when an erase or page program
565+ * error occurs. Issue a Write Disable command to protect
566+ * against inadvertent writes that can possibly corrupt the
567+ * contents of the memory.
568+ */
569+ ret = spi_nor_write_disable(nor);
570+ if (ret)
571+ return ret;
572+
573+ return -EIO;
574+ }
575+
576+ return !(nor->bouncebuf[0] & SR_WIP);
577+}
578+
579+/**
580+ * spi_nor_clear_fsr() - Clear the Flag Status Register.
581+ * @nor: pointer to 'struct spi_nor'.
582+ */
583+static void spi_nor_clear_fsr(struct spi_nor *nor)
584+{
585+ int ret;
586+
587+ if (nor->spimem) {
588+ struct spi_mem_op op =
589+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 1),
590+ SPI_MEM_OP_NO_ADDR,
591+ SPI_MEM_OP_NO_DUMMY,
592+ SPI_MEM_OP_NO_DATA);
593+
594+ ret = spi_mem_exec_op(nor->spimem, &op);
595+ } else {
596+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR,
597+ NULL, 0);
598+ }
599+
600+ if (ret)
601+ dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
602+}
603+
604+/**
605+ * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is
606+ * ready for new commands.
607+ * @nor: pointer to 'struct spi_nor'.
608+ *
609+ * Return: 0 on success, -errno otherwise.
610+ */
611+static int spi_nor_fsr_ready(struct spi_nor *nor)
612+{
613+ int ret = spi_nor_read_fsr(nor, nor->bouncebuf);
614+
615+ if (ret)
616+ return ret;
617+
618+ if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
619+ if (nor->bouncebuf[0] & FSR_E_ERR)
620+ dev_err(nor->dev, "Erase operation failed.\n");
621+ else
622+ dev_err(nor->dev, "Program operation failed.\n");
623+
624+ if (nor->bouncebuf[0] & FSR_PT_ERR)
625+ dev_err(nor->dev,
626+ "Attempted to modify a protected sector.\n");
627+
628+ spi_nor_clear_fsr(nor);
629+
630+ /*
631+ * WEL bit remains set to one when an erase or page program
632+ * error occurs. Issue a Write Disable command to protect
633+ * against inadvertent writes that can possibly corrupt the
634+ * contents of the memory.
635+ */
636+ ret = spi_nor_write_disable(nor);
637+ if (ret)
638+ return ret;
639+
640+ return -EIO;
641+ }
642+
643+ return nor->bouncebuf[0] & FSR_READY;
644+}
645+
646+/**
647+ * spi_nor_ready() - Query the flash to see if it is ready for new commands.
648+ * @nor: pointer to 'struct spi_nor'.
649+ *
650+ * Return: 0 on success, -errno otherwise.
651+ */
652+static int spi_nor_ready(struct spi_nor *nor)
653+{
654+ int sr, fsr;
655+
656+ if (nor->flags & SNOR_F_READY_XSR_RDY)
657+ sr = spi_nor_xsr_ready(nor);
658+ else
659+ sr = spi_nor_sr_ready(nor);
660+ if (sr < 0)
661+ return sr;
662+ fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
663+ if (fsr < 0)
664+ return fsr;
665+ return sr && fsr;
666+}
667+
668+/**
669+ * spi_nor_wait_till_ready_with_timeout() - Service routine to read the
670+ * Status Register until ready, or timeout occurs.
671+ * @nor: pointer to "struct spi_nor".
672+ * @timeout_jiffies: jiffies to wait until timeout.
673+ *
674+ * Return: 0 on success, -errno otherwise.
675+ */
676+static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
677+ unsigned long timeout_jiffies)
678+{
679+ unsigned long deadline;
680+ int timeout = 0, ret;
681+
682+ deadline = jiffies + timeout_jiffies;
683+
684+ while (!timeout) {
685+ if (time_after_eq(jiffies, deadline))
686+ timeout = 1;
687+
688+ ret = spi_nor_ready(nor);
689+ if (ret < 0)
690+ return ret;
691+ if (ret)
692+ return 0;
693+
694+ cond_resched();
695+ }
696+
697+ dev_dbg(nor->dev, "flash operation timed out\n");
698+
699+ return -ETIMEDOUT;
700+}
701+
702+/**
703+ * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the
704+ * flash to be ready, or timeout occurs.
705+ * @nor: pointer to "struct spi_nor".
706+ *
707+ * Return: 0 on success, -errno otherwise.
708+ */
709+int spi_nor_wait_till_ready(struct spi_nor *nor)
710+{
711+ return spi_nor_wait_till_ready_with_timeout(nor,
712+ DEFAULT_READY_WAIT_JIFFIES);
713+}
714+
715+/**
716+ * spi_nor_write_sr() - Write the Status Register.
717+ * @nor: pointer to 'struct spi_nor'.
718+ * @sr: pointer to DMA-able buffer to write to the Status Register.
719+ * @len: number of bytes to write to the Status Register.
720+ *
721+ * Return: 0 on success, -errno otherwise.
722+ */
723+static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
724+{
725+ int ret;
726+
727+ ret = spi_nor_write_enable(nor);
728+ if (ret)
729+ return ret;
730+
731+ if (nor->spimem) {
732+ struct spi_mem_op op =
733+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1),
734+ SPI_MEM_OP_NO_ADDR,
735+ SPI_MEM_OP_NO_DUMMY,
736+ SPI_MEM_OP_DATA_OUT(len, sr, 1));
737+
738+ ret = spi_mem_exec_op(nor->spimem, &op);
739+ } else {
740+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
741+ sr, len);
742+ }
743+
744+ if (ret) {
745+ dev_dbg(nor->dev, "error %d writing SR\n", ret);
746+ return ret;
747+ }
748+
749+ return spi_nor_wait_till_ready(nor);
750+}
751+
752+/**
753+ * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
754+ * ensure that the byte written match the received value.
755+ * @nor: pointer to a 'struct spi_nor'.
756+ * @sr1: byte value to be written to the Status Register.
757+ *
758+ * Return: 0 on success, -errno otherwise.
759+ */
760+static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
761+{
762+ int ret;
763+
764+ nor->bouncebuf[0] = sr1;
765+
766+ ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
767+ if (ret)
768+ return ret;
769+
770+ ret = spi_nor_read_sr(nor, nor->bouncebuf);
771+ if (ret)
772+ return ret;
773+
774+ if (nor->bouncebuf[0] != sr1) {
775+ dev_dbg(nor->dev, "SR1: read back test failed\n");
776+ return -EIO;
777+ }
778+
779+ return 0;
780+}
781+
782+/**
783+ * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
784+ * Status Register 2 in one shot. Ensure that the byte written in the Status
785+ * Register 1 match the received value, and that the 16-bit Write did not
786+ * affect what was already in the Status Register 2.
787+ * @nor: pointer to a 'struct spi_nor'.
788+ * @sr1: byte value to be written to the Status Register 1.
789+ *
790+ * Return: 0 on success, -errno otherwise.
791+ */
792+static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
793+{
794+ int ret;
795+ u8 *sr_cr = nor->bouncebuf;
796+ u8 cr_written;
797+
798+ /* Make sure we don't overwrite the contents of Status Register 2. */
799+ if (!(nor->flags & SNOR_F_NO_READ_CR)) {
800+ ret = spi_nor_read_cr(nor, &sr_cr[1]);
801+ if (ret)
802+ return ret;
803+ } else if (nor->params->quad_enable) {
804+ /*
805+ * If the Status Register 2 Read command (35h) is not
806+ * supported, we should at least be sure we don't
807+ * change the value of the SR2 Quad Enable bit.
808+ *
809+ * We can safely assume that when the Quad Enable method is
810+ * set, the value of the QE bit is one, as a consequence of the
811+ * nor->params->quad_enable() call.
812+ *
813+ * We can safely assume that the Quad Enable bit is present in
814+ * the Status Register 2 at BIT(1). According to the JESD216
815+ * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
816+ * Write Status (01h) command is available just for the cases
817+ * in which the QE bit is described in SR2 at BIT(1).
818+ */
819+ sr_cr[1] = SR2_QUAD_EN_BIT1;
820+ } else {
821+ sr_cr[1] = 0;
822+ }
823+
824+ sr_cr[0] = sr1;
825+
826+ ret = spi_nor_write_sr(nor, sr_cr, 2);
827+ if (ret)
828+ return ret;
829+
830+ if (nor->flags & SNOR_F_NO_READ_CR)
831+ return 0;
832+
833+ cr_written = sr_cr[1];
834+
835+ ret = spi_nor_read_cr(nor, &sr_cr[1]);
836+ if (ret)
837+ return ret;
838+
839+ if (cr_written != sr_cr[1]) {
840+ dev_dbg(nor->dev, "CR: read back test failed\n");
841+ return -EIO;
842+ }
843+
844+ return 0;
845+}
846+
847+/**
848+ * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
849+ * Configuration Register in one shot. Ensure that the byte written in the
850+ * Configuration Register match the received value, and that the 16-bit Write
851+ * did not affect what was already in the Status Register 1.
852+ * @nor: pointer to a 'struct spi_nor'.
853+ * @cr: byte value to be written to the Configuration Register.
854+ *
855+ * Return: 0 on success, -errno otherwise.
856+ */
857+static int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)
858+{
859+ int ret;
860+ u8 *sr_cr = nor->bouncebuf;
861+ u8 sr_written;
862+
863+ /* Keep the current value of the Status Register 1. */
864+ ret = spi_nor_read_sr(nor, sr_cr);
865+ if (ret)
866+ return ret;
867+
868+ sr_cr[1] = cr;
869+
870+ ret = spi_nor_write_sr(nor, sr_cr, 2);
871+ if (ret)
872+ return ret;
873+
874+ sr_written = sr_cr[0];
875+
876+ ret = spi_nor_read_sr(nor, sr_cr);
877+ if (ret)
878+ return ret;
879+
880+ if (sr_written != sr_cr[0]) {
881+ dev_dbg(nor->dev, "SR: Read back test failed\n");
882+ return -EIO;
883+ }
884+
885+ if (nor->flags & SNOR_F_NO_READ_CR)
886+ return 0;
887+
888+ ret = spi_nor_read_cr(nor, &sr_cr[1]);
889+ if (ret)
890+ return ret;
891+
892+ if (cr != sr_cr[1]) {
893+ dev_dbg(nor->dev, "CR: read back test failed\n");
894+ return -EIO;
895+ }
896+
897+ return 0;
898+}
899+
900+/**
901+ * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
902+ * the byte written match the received value without affecting other bits in the
903+ * Status Register 1 and 2.
904+ * @nor: pointer to a 'struct spi_nor'.
905+ * @sr1: byte value to be written to the Status Register.
906+ *
907+ * Return: 0 on success, -errno otherwise.
908+ */
909+static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)
910+{
911+ if (nor->flags & SNOR_F_HAS_16BIT_SR)
912+ return spi_nor_write_16bit_sr_and_check(nor, sr1);
913+
914+ return spi_nor_write_sr1_and_check(nor, sr1);
915+}
916+
917+/**
918+ * spi_nor_write_sr2() - Write the Status Register 2 using the
919+ * SPINOR_OP_WRSR2 (3eh) command.
920+ * @nor: pointer to 'struct spi_nor'.
921+ * @sr2: pointer to DMA-able buffer to write to the Status Register 2.
922+ *
923+ * Return: 0 on success, -errno otherwise.
924+ */
925+static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
926+{
927+ int ret;
928+
929+ ret = spi_nor_write_enable(nor);
930+ if (ret)
931+ return ret;
932+
933+ if (nor->spimem) {
934+ struct spi_mem_op op =
935+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1),
936+ SPI_MEM_OP_NO_ADDR,
937+ SPI_MEM_OP_NO_DUMMY,
938+ SPI_MEM_OP_DATA_OUT(1, sr2, 1));
939+
940+ ret = spi_mem_exec_op(nor->spimem, &op);
941+ } else {
942+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2,
943+ sr2, 1);
944+ }
945+
946+ if (ret) {
947+ dev_dbg(nor->dev, "error %d writing SR2\n", ret);
948+ return ret;
949+ }
950+
951+ return spi_nor_wait_till_ready(nor);
952+}
953+
954+/**
955+ * spi_nor_read_sr2() - Read the Status Register 2 using the
956+ * SPINOR_OP_RDSR2 (3fh) command.
957+ * @nor: pointer to 'struct spi_nor'.
958+ * @sr2: pointer to DMA-able buffer where the value of the
959+ * Status Register 2 will be written.
960+ *
961+ * Return: 0 on success, -errno otherwise.
962+ */
963+static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
964+{
965+ int ret;
966+
967+ if (nor->spimem) {
968+ struct spi_mem_op op =
969+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1),
970+ SPI_MEM_OP_NO_ADDR,
971+ SPI_MEM_OP_NO_DUMMY,
972+ SPI_MEM_OP_DATA_IN(1, sr2, 1));
973+
974+ ret = spi_mem_exec_op(nor->spimem, &op);
975+ } else {
976+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2,
977+ sr2, 1);
978+ }
979+
980+ if (ret)
981+ dev_dbg(nor->dev, "error %d reading SR2\n", ret);
982+
983+ return ret;
984+}
985+
986+/**
987+ * spi_nor_erase_chip() - Erase the entire flash memory.
988+ * @nor: pointer to 'struct spi_nor'.
989+ *
990+ * Return: 0 on success, -errno otherwise.
991+ */
992+static int spi_nor_erase_chip(struct spi_nor *nor)
993+{
994+ int ret;
995+
996+ dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
997+
998+ if (nor->spimem) {
999+ struct spi_mem_op op =
1000+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 1),
1001+ SPI_MEM_OP_NO_ADDR,
1002+ SPI_MEM_OP_NO_DUMMY,
1003+ SPI_MEM_OP_NO_DATA);
1004+
1005+ ret = spi_mem_exec_op(nor->spimem, &op);
1006+ } else {
1007+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CHIP_ERASE,
1008+ NULL, 0);
1009+ }
1010+
1011+ if (ret)
1012+ dev_dbg(nor->dev, "error %d erasing chip\n", ret);
1013+
1014+ return ret;
1015+}
1016+
1017+static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
1018+{
1019+ size_t i;
1020+
1021+ for (i = 0; i < size; i++)
1022+ if (table[i][0] == opcode)
1023+ return table[i][1];
1024+
1025+ /* No conversion found, keep input op code. */
1026+ return opcode;
1027+}
1028+
1029+u8 spi_nor_convert_3to4_read(u8 opcode)
1030+{
1031+ static const u8 spi_nor_3to4_read[][2] = {
1032+ { SPINOR_OP_READ, SPINOR_OP_READ_4B },
1033+ { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
1034+ { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
1035+ { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
1036+ { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
1037+ { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
1038+ { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
1039+ { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
1040+
1041+ { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
1042+ { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
1043+ { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
1044+ };
1045+
1046+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
1047+ ARRAY_SIZE(spi_nor_3to4_read));
1048+}
1049+
1050+static u8 spi_nor_convert_3to4_program(u8 opcode)
1051+{
1052+ static const u8 spi_nor_3to4_program[][2] = {
1053+ { SPINOR_OP_PP, SPINOR_OP_PP_4B },
1054+ { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
1055+ { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
1056+ { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
1057+ { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
1058+ };
1059+
1060+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
1061+ ARRAY_SIZE(spi_nor_3to4_program));
1062+}
1063+
1064+static u8 spi_nor_convert_3to4_erase(u8 opcode)
1065+{
1066+ static const u8 spi_nor_3to4_erase[][2] = {
1067+ { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
1068+ { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
1069+ { SPINOR_OP_SE, SPINOR_OP_SE_4B },
1070+ };
1071+
1072+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
1073+ ARRAY_SIZE(spi_nor_3to4_erase));
1074+}
1075+
1076+static bool spi_nor_has_uniform_erase(const struct spi_nor *nor)
1077+{
1078+ return !!nor->params->erase_map.uniform_erase_type;
1079+}
1080+
1081+static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
1082+{
1083+ nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
1084+ nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
1085+ nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
1086+
1087+ if (!spi_nor_has_uniform_erase(nor)) {
1088+ struct spi_nor_erase_map *map = &nor->params->erase_map;
1089+ struct spi_nor_erase_type *erase;
1090+ int i;
1091+
1092+ for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
1093+ erase = &map->erase_type[i];
1094+ erase->opcode =
1095+ spi_nor_convert_3to4_erase(erase->opcode);
1096+ }
1097+ }
1098+}
1099+
1100+int spi_nor_lock_and_prep(struct spi_nor *nor)
1101+{
1102+ int ret = 0;
1103+
1104+ mutex_lock(&nor->lock);
1105+
1106+ if (nor->controller_ops && nor->controller_ops->prepare) {
1107+ ret = nor->controller_ops->prepare(nor);
1108+ if (ret) {
1109+ mutex_unlock(&nor->lock);
1110+ return ret;
1111+ }
1112+ }
1113+ return ret;
1114+}
1115+
1116+void spi_nor_unlock_and_unprep(struct spi_nor *nor)
1117+{
1118+ if (nor->controller_ops && nor->controller_ops->unprepare)
1119+ nor->controller_ops->unprepare(nor);
1120+ mutex_unlock(&nor->lock);
1121+}
1122+
1123+static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
1124+{
1125+ if (!nor->params->convert_addr)
1126+ return addr;
1127+
1128+ return nor->params->convert_addr(nor, addr);
1129+}
1130+
1131+/*
1132+ * Initiate the erasure of a single sector
1133+ */
1134+static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
1135+{
1136+ int i;
1137+
1138+ addr = spi_nor_convert_addr(nor, addr);
1139+
1140+ if (nor->spimem) {
1141+ struct spi_mem_op op =
1142+ SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1),
1143+ SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
1144+ SPI_MEM_OP_NO_DUMMY,
1145+ SPI_MEM_OP_NO_DATA);
1146+
1147+ return spi_mem_exec_op(nor->spimem, &op);
1148+ } else if (nor->controller_ops->erase) {
1149+ return nor->controller_ops->erase(nor, addr);
1150+ }
1151+
1152+ /*
1153+ * Default implementation, if driver doesn't have a specialized HW
1154+ * control
1155+ */
1156+ for (i = nor->addr_width - 1; i >= 0; i--) {
1157+ nor->bouncebuf[i] = addr & 0xff;
1158+ addr >>= 8;
1159+ }
1160+
1161+ return nor->controller_ops->write_reg(nor, nor->erase_opcode,
1162+ nor->bouncebuf, nor->addr_width);
1163+}
1164+
1165+/**
1166+ * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
1167+ * @erase: pointer to a structure that describes a SPI NOR erase type
1168+ * @dividend: dividend value
1169+ * @remainder: pointer to u32 remainder (will be updated)
1170+ *
1171+ * Return: the result of the division
1172+ */
1173+static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
1174+ u64 dividend, u32 *remainder)
1175+{
1176+ /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
1177+ *remainder = (u32)dividend & erase->size_mask;
1178+ return dividend >> erase->size_shift;
1179+}
1180+
1181+/**
1182+ * spi_nor_find_best_erase_type() - find the best erase type for the given
1183+ * offset in the serial flash memory and the
1184+ * number of bytes to erase. The region in
1185+ * which the address fits is expected to be
1186+ * provided.
1187+ * @map: the erase map of the SPI NOR
1188+ * @region: pointer to a structure that describes a SPI NOR erase region
1189+ * @addr: offset in the serial flash memory
1190+ * @len: number of bytes to erase
1191+ *
1192+ * Return: a pointer to the best fitted erase type, NULL otherwise.
1193+ */
1194+static const struct spi_nor_erase_type *
1195+spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
1196+ const struct spi_nor_erase_region *region,
1197+ u64 addr, u32 len)
1198+{
1199+ const struct spi_nor_erase_type *erase;
1200+ u32 rem;
1201+ int i;
1202+ u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
1203+
1204+ /*
1205+ * Erase types are ordered by size, with the smallest erase type at
1206+ * index 0.
1207+ */
1208+ for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
1209+ /* Does the erase region support the tested erase type? */
1210+ if (!(erase_mask & BIT(i)))
1211+ continue;
1212+
1213+ erase = &map->erase_type[i];
1214+
1215+ /* Don't erase more than what the user has asked for. */
1216+ if (erase->size > len)
1217+ continue;
1218+
1219+ /* Alignment is not mandatory for overlaid regions */
1220+ if (region->offset & SNOR_OVERLAID_REGION)
1221+ return erase;
1222+
1223+ spi_nor_div_by_erase_size(erase, addr, &rem);
1224+ if (rem)
1225+ continue;
1226+ else
1227+ return erase;
1228+ }
1229+
1230+ return NULL;
1231+}
1232+
1233+static u64 spi_nor_region_is_last(const struct spi_nor_erase_region *region)
1234+{
1235+ return region->offset & SNOR_LAST_REGION;
1236+}
1237+
1238+static u64 spi_nor_region_end(const struct spi_nor_erase_region *region)
1239+{
1240+ return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size;
1241+}
1242+
1243+/**
1244+ * spi_nor_region_next() - get the next spi nor region
1245+ * @region: pointer to a structure that describes a SPI NOR erase region
1246+ *
1247+ * Return: the next spi nor region or NULL if last region.
1248+ */
1249+struct spi_nor_erase_region *
1250+spi_nor_region_next(struct spi_nor_erase_region *region)
1251+{
1252+ if (spi_nor_region_is_last(region))
1253+ return NULL;
1254+ region++;
1255+ return region;
1256+}
1257+
1258+/**
1259+ * spi_nor_find_erase_region() - find the region of the serial flash memory in
1260+ * which the offset fits
1261+ * @map: the erase map of the SPI NOR
1262+ * @addr: offset in the serial flash memory
1263+ *
1264+ * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno)
1265+ * otherwise.
1266+ */
1267+static struct spi_nor_erase_region *
1268+spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr)
1269+{
1270+ struct spi_nor_erase_region *region = map->regions;
1271+ u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1272+ u64 region_end = region_start + region->size;
1273+
1274+ while (addr < region_start || addr >= region_end) {
1275+ region = spi_nor_region_next(region);
1276+ if (!region)
1277+ return ERR_PTR(-EINVAL);
1278+
1279+ region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1280+ region_end = region_start + region->size;
1281+ }
1282+
1283+ return region;
1284+}
1285+
1286+/**
1287+ * spi_nor_init_erase_cmd() - initialize an erase command
1288+ * @region: pointer to a structure that describes a SPI NOR erase region
1289+ * @erase: pointer to a structure that describes a SPI NOR erase type
1290+ *
1291+ * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
1292+ * otherwise.
1293+ */
1294+static struct spi_nor_erase_command *
1295+spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,
1296+ const struct spi_nor_erase_type *erase)
1297+{
1298+ struct spi_nor_erase_command *cmd;
1299+
1300+ cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
1301+ if (!cmd)
1302+ return ERR_PTR(-ENOMEM);
1303+
1304+ INIT_LIST_HEAD(&cmd->list);
1305+ cmd->opcode = erase->opcode;
1306+ cmd->count = 1;
1307+
1308+ if (region->offset & SNOR_OVERLAID_REGION)
1309+ cmd->size = region->size;
1310+ else
1311+ cmd->size = erase->size;
1312+
1313+ return cmd;
1314+}
1315+
1316+/**
1317+ * spi_nor_destroy_erase_cmd_list() - destroy erase command list
1318+ * @erase_list: list of erase commands
1319+ */
1320+static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)
1321+{
1322+ struct spi_nor_erase_command *cmd, *next;
1323+
1324+ list_for_each_entry_safe(cmd, next, erase_list, list) {
1325+ list_del(&cmd->list);
1326+ kfree(cmd);
1327+ }
1328+}
1329+
1330+/**
1331+ * spi_nor_init_erase_cmd_list() - initialize erase command list
1332+ * @nor: pointer to a 'struct spi_nor'
1333+ * @erase_list: list of erase commands to be executed once we validate that the
1334+ * erase can be performed
1335+ * @addr: offset in the serial flash memory
1336+ * @len: number of bytes to erase
1337+ *
1338+ * Builds the list of best fitted erase commands and verifies if the erase can
1339+ * be performed.
1340+ *
1341+ * Return: 0 on success, -errno otherwise.
1342+ */
1343+static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
1344+ struct list_head *erase_list,
1345+ u64 addr, u32 len)
1346+{
1347+ const struct spi_nor_erase_map *map = &nor->params->erase_map;
1348+ const struct spi_nor_erase_type *erase, *prev_erase = NULL;
1349+ struct spi_nor_erase_region *region;
1350+ struct spi_nor_erase_command *cmd = NULL;
1351+ u64 region_end;
1352+ int ret = -EINVAL;
1353+
1354+ region = spi_nor_find_erase_region(map, addr);
1355+ if (IS_ERR(region))
1356+ return PTR_ERR(region);
1357+
1358+ region_end = spi_nor_region_end(region);
1359+
1360+ while (len) {
1361+ erase = spi_nor_find_best_erase_type(map, region, addr, len);
1362+ if (!erase)
1363+ goto destroy_erase_cmd_list;
1364+
1365+ if (prev_erase != erase ||
1366+ region->offset & SNOR_OVERLAID_REGION) {
1367+ cmd = spi_nor_init_erase_cmd(region, erase);
1368+ if (IS_ERR(cmd)) {
1369+ ret = PTR_ERR(cmd);
1370+ goto destroy_erase_cmd_list;
1371+ }
1372+
1373+ list_add_tail(&cmd->list, erase_list);
1374+ } else {
1375+ cmd->count++;
1376+ }
1377+
1378+ addr += cmd->size;
1379+ len -= cmd->size;
1380+
1381+ if (len && addr >= region_end) {
1382+ region = spi_nor_region_next(region);
1383+ if (!region)
1384+ goto destroy_erase_cmd_list;
1385+ region_end = spi_nor_region_end(region);
1386+ }
1387+
1388+ prev_erase = erase;
1389+ }
1390+
1391+ return 0;
1392+
1393+destroy_erase_cmd_list:
1394+ spi_nor_destroy_erase_cmd_list(erase_list);
1395+ return ret;
1396+}
1397+
1398+/**
1399+ * spi_nor_erase_multi_sectors() - perform a non-uniform erase
1400+ * @nor: pointer to a 'struct spi_nor'
1401+ * @addr: offset in the serial flash memory
1402+ * @len: number of bytes to erase
1403+ *
1404+ * Build a list of best fitted erase commands and execute it once we validate
1405+ * that the erase can be performed.
1406+ *
1407+ * Return: 0 on success, -errno otherwise.
1408+ */
1409+static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
1410+{
1411+ LIST_HEAD(erase_list);
1412+ struct spi_nor_erase_command *cmd, *next;
1413+ int ret;
1414+
1415+ ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);
1416+ if (ret)
1417+ return ret;
1418+
1419+ list_for_each_entry_safe(cmd, next, &erase_list, list) {
1420+ nor->erase_opcode = cmd->opcode;
1421+ while (cmd->count) {
1422+ ret = spi_nor_write_enable(nor);
1423+ if (ret)
1424+ goto destroy_erase_cmd_list;
1425+
1426+ ret = spi_nor_erase_sector(nor, addr);
1427+ if (ret)
1428+ goto destroy_erase_cmd_list;
1429+
1430+ addr += cmd->size;
1431+ cmd->count--;
1432+
1433+ ret = spi_nor_wait_till_ready(nor);
1434+ if (ret)
1435+ goto destroy_erase_cmd_list;
1436+ }
1437+ list_del(&cmd->list);
1438+ kfree(cmd);
1439+ }
1440+
1441+ return 0;
1442+
1443+destroy_erase_cmd_list:
1444+ spi_nor_destroy_erase_cmd_list(&erase_list);
1445+ return ret;
1446+}
1447+
1448+/*
1449+ * Erase an address range on the nor chip. The address range may extend
1450+ * one or more erase sectors. Return an error is there is a problem erasing.
1451+ */
1452+static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
1453+{
1454+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
1455+ u32 addr, len;
1456+ uint32_t rem;
1457+ int ret;
1458+
1459+ dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
1460+ (long long)instr->len);
1461+
1462+ if (spi_nor_has_uniform_erase(nor)) {
1463+ div_u64_rem(instr->len, mtd->erasesize, &rem);
1464+ if (rem)
1465+ return -EINVAL;
1466+ }
1467+
1468+ addr = instr->addr;
1469+ len = instr->len;
1470+
1471+ ret = spi_nor_lock_and_prep(nor);
1472+ if (ret)
1473+ return ret;
1474+
1475+ /* whole-chip erase? */
1476+ if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
1477+ unsigned long timeout;
1478+
1479+ ret = spi_nor_write_enable(nor);
1480+ if (ret)
1481+ goto erase_err;
1482+
1483+ ret = spi_nor_erase_chip(nor);
1484+ if (ret)
1485+ goto erase_err;
1486+
1487+ /*
1488+ * Scale the timeout linearly with the size of the flash, with
1489+ * a minimum calibrated to an old 2MB flash. We could try to
1490+ * pull these from CFI/SFDP, but these values should be good
1491+ * enough for now.
1492+ */
1493+ timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
1494+ CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
1495+ (unsigned long)(mtd->size / SZ_2M));
1496+ ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
1497+ if (ret)
1498+ goto erase_err;
1499+
1500+ /* REVISIT in some cases we could speed up erasing large regions
1501+ * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
1502+ * to use "small sector erase", but that's not always optimal.
1503+ */
1504+
1505+ /* "sector"-at-a-time erase */
1506+ } else if (spi_nor_has_uniform_erase(nor)) {
1507+ while (len) {
1508+ ret = spi_nor_write_enable(nor);
1509+ if (ret)
1510+ goto erase_err;
1511+
1512+ ret = spi_nor_erase_sector(nor, addr);
1513+ if (ret)
1514+ goto erase_err;
1515+
1516+ addr += mtd->erasesize;
1517+ len -= mtd->erasesize;
1518+
1519+ ret = spi_nor_wait_till_ready(nor);
1520+ if (ret)
1521+ goto erase_err;
1522+ }
1523+
1524+ /* erase multiple sectors */
1525+ } else {
1526+ ret = spi_nor_erase_multi_sectors(nor, addr, len);
1527+ if (ret)
1528+ goto erase_err;
1529+ }
1530+
1531+ ret = spi_nor_write_disable(nor);
1532+
1533+erase_err:
1534+ spi_nor_unlock_and_unprep(nor);
1535+
1536+ return ret;
1537+}
1538+
1539+static u8 spi_nor_get_sr_bp_mask(struct spi_nor *nor)
1540+{
1541+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1542+
1543+ if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6)
1544+ return mask | SR_BP3_BIT6;
1545+
1546+ if (nor->flags & SNOR_F_HAS_4BIT_BP)
1547+ return mask | SR_BP3;
1548+
1549+ return mask;
1550+}
1551+
1552+static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor)
1553+{
1554+ if (nor->flags & SNOR_F_HAS_SR_TB_BIT6)
1555+ return SR_TB_BIT6;
1556+ else
1557+ return SR_TB_BIT5;
1558+}
1559+
1560+static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor)
1561+{
1562+ unsigned int bp_slots, bp_slots_needed;
1563+ u8 mask = spi_nor_get_sr_bp_mask(nor);
1564+
1565+ /* Reserved one for "protect none" and one for "protect all". */
1566+ bp_slots = (1 << hweight8(mask)) - 2;
1567+ bp_slots_needed = ilog2(nor->info->n_sectors);
1568+
1569+ if (bp_slots_needed > bp_slots)
1570+ return nor->info->sector_size <<
1571+ (bp_slots_needed - bp_slots);
1572+ else
1573+ return nor->info->sector_size;
1574+}
1575+
1576+static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs,
1577+ uint64_t *len)
1578+{
1579+ struct mtd_info *mtd = &nor->mtd;
1580+ u64 min_prot_len;
1581+ u8 mask = spi_nor_get_sr_bp_mask(nor);
1582+ u8 tb_mask = spi_nor_get_sr_tb_mask(nor);
1583+ u8 bp, val = sr & mask;
1584+
1585+ if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6)
1586+ val = (val & ~SR_BP3_BIT6) | SR_BP3;
1587+
1588+ bp = val >> SR_BP_SHIFT;
1589+
1590+ if (!bp) {
1591+ /* No protection */
1592+ *ofs = 0;
1593+ *len = 0;
1594+ return;
1595+ }
1596+
1597+ min_prot_len = spi_nor_get_min_prot_length_sr(nor);
1598+ *len = min_prot_len << (bp - 1);
1599+
1600+ if (*len > mtd->size)
1601+ *len = mtd->size;
1602+
1603+ if (nor->flags & SNOR_F_HAS_SR_TB && sr & tb_mask)
1604+ *ofs = 0;
1605+ else
1606+ *ofs = mtd->size - *len;
1607+}
1608+
1609+/*
1610+ * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
1611+ * @locked is false); 0 otherwise
1612+ */
1613+static int spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs,
1614+ uint64_t len, u8 sr, bool locked)
1615+{
1616+ loff_t lock_offs;
1617+ uint64_t lock_len;
1618+
1619+ if (!len)
1620+ return 1;
1621+
1622+ spi_nor_get_locked_range_sr(nor, sr, &lock_offs, &lock_len);
1623+
1624+ if (locked)
1625+ /* Requested range is a sub-range of locked range */
1626+ return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
1627+ else
1628+ /* Requested range does not overlap with locked range */
1629+ return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
1630+}
1631+
1632+static int spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1633+ u8 sr)
1634+{
1635+ return spi_nor_check_lock_status_sr(nor, ofs, len, sr, true);
1636+}
1637+
1638+static int spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1639+ u8 sr)
1640+{
1641+ return spi_nor_check_lock_status_sr(nor, ofs, len, sr, false);
1642+}
1643+
1644+/*
1645+ * Lock a region of the flash. Compatible with ST Micro and similar flash.
1646+ * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the status
1647+ * register
1648+ * (SR). Does not support these features found in newer SR bitfields:
1649+ * - SEC: sector/block protect - only handle SEC=0 (block protect)
1650+ * - CMP: complement protect - only support CMP=0 (range is not complemented)
1651+ *
1652+ * Support for the following is provided conditionally for some flash:
1653+ * - TB: top/bottom protect
1654+ *
1655+ * Sample table portion for 8MB flash (Winbond w25q64fw):
1656+ *
1657+ * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
1658+ * --------------------------------------------------------------------------
1659+ * X | X | 0 | 0 | 0 | NONE | NONE
1660+ * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
1661+ * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
1662+ * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
1663+ * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
1664+ * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
1665+ * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
1666+ * X | X | 1 | 1 | 1 | 8 MB | ALL
1667+ * ------|-------|-------|-------|-------|---------------|-------------------
1668+ * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
1669+ * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
1670+ * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
1671+ * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
1672+ * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
1673+ * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
1674+ *
1675+ * Returns negative on errors, 0 on success.
1676+ */
1677+static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1678+{
1679+ struct mtd_info *mtd = &nor->mtd;
1680+ u64 min_prot_len;
1681+ int ret, status_old, status_new;
1682+ u8 mask = spi_nor_get_sr_bp_mask(nor);
1683+ u8 tb_mask = spi_nor_get_sr_tb_mask(nor);
1684+ u8 pow, val;
1685+ loff_t lock_len;
1686+ bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1687+ bool use_top;
1688+
1689+ ret = spi_nor_read_sr(nor, nor->bouncebuf);
1690+ if (ret)
1691+ return ret;
1692+
1693+ status_old = nor->bouncebuf[0];
1694+
1695+ /* If nothing in our range is unlocked, we don't need to do anything */
1696+ if (spi_nor_is_locked_sr(nor, ofs, len, status_old))
1697+ return 0;
1698+
1699+ /* If anything below us is unlocked, we can't use 'bottom' protection */
1700+ if (!spi_nor_is_locked_sr(nor, 0, ofs, status_old))
1701+ can_be_bottom = false;
1702+
1703+ /* If anything above us is unlocked, we can't use 'top' protection */
1704+ if (!spi_nor_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
1705+ status_old))
1706+ can_be_top = false;
1707+
1708+ if (!can_be_bottom && !can_be_top)
1709+ return -EINVAL;
1710+
1711+ /* Prefer top, if both are valid */
1712+ use_top = can_be_top;
1713+
1714+ /* lock_len: length of region that should end up locked */
1715+ if (use_top)
1716+ lock_len = mtd->size - ofs;
1717+ else
1718+ lock_len = ofs + len;
1719+
1720+ if (lock_len == mtd->size) {
1721+ val = mask;
1722+ } else {
1723+ min_prot_len = spi_nor_get_min_prot_length_sr(nor);
1724+ pow = ilog2(lock_len) - ilog2(min_prot_len) + 1;
1725+ val = pow << SR_BP_SHIFT;
1726+
1727+ if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)
1728+ val = (val & ~SR_BP3) | SR_BP3_BIT6;
1729+
1730+ if (val & ~mask)
1731+ return -EINVAL;
1732+
1733+ /* Don't "lock" with no region! */
1734+ if (!(val & mask))
1735+ return -EINVAL;
1736+ }
1737+
1738+ status_new = (status_old & ~mask & ~tb_mask) | val;
1739+
1740+ /* Disallow further writes if WP pin is asserted */
1741+ status_new |= SR_SRWD;
1742+
1743+ if (!use_top)
1744+ status_new |= tb_mask;
1745+
1746+ /* Don't bother if they're the same */
1747+ if (status_new == status_old)
1748+ return 0;
1749+
1750+ /* Only modify protection if it will not unlock other areas */
1751+ if ((status_new & mask) < (status_old & mask))
1752+ return -EINVAL;
1753+
1754+ return spi_nor_write_sr_and_check(nor, status_new);
1755+}
1756+
1757+/*
1758+ * Unlock a region of the flash. See spi_nor_sr_lock() for more info
1759+ *
1760+ * Returns negative on errors, 0 on success.
1761+ */
1762+static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1763+{
1764+ struct mtd_info *mtd = &nor->mtd;
1765+ u64 min_prot_len;
1766+ int ret, status_old, status_new;
1767+ u8 mask = spi_nor_get_sr_bp_mask(nor);
1768+ u8 tb_mask = spi_nor_get_sr_tb_mask(nor);
1769+ u8 pow, val;
1770+ loff_t lock_len;
1771+ bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1772+ bool use_top;
1773+
1774+ ret = spi_nor_read_sr(nor, nor->bouncebuf);
1775+ if (ret)
1776+ return ret;
1777+
1778+ status_old = nor->bouncebuf[0];
1779+
1780+ /* If nothing in our range is locked, we don't need to do anything */
1781+ if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old))
1782+ return 0;
1783+
1784+ /* If anything below us is locked, we can't use 'top' protection */
1785+ if (!spi_nor_is_unlocked_sr(nor, 0, ofs, status_old))
1786+ can_be_top = false;
1787+
1788+ /* If anything above us is locked, we can't use 'bottom' protection */
1789+ if (!spi_nor_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
1790+ status_old))
1791+ can_be_bottom = false;
1792+
1793+ if (!can_be_bottom && !can_be_top)
1794+ return -EINVAL;
1795+
1796+ /* Prefer top, if both are valid */
1797+ use_top = can_be_top;
1798+
1799+ /* lock_len: length of region that should remain locked */
1800+ if (use_top)
1801+ lock_len = mtd->size - (ofs + len);
1802+ else
1803+ lock_len = ofs;
1804+
1805+ if (lock_len == 0) {
1806+ val = 0; /* fully unlocked */
1807+ } else {
1808+ min_prot_len = spi_nor_get_min_prot_length_sr(nor);
1809+ pow = ilog2(lock_len) - ilog2(min_prot_len) + 1;
1810+ val = pow << SR_BP_SHIFT;
1811+
1812+ if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)
1813+ val = (val & ~SR_BP3) | SR_BP3_BIT6;
1814+
1815+ /* Some power-of-two sizes are not supported */
1816+ if (val & ~mask)
1817+ return -EINVAL;
1818+ }
1819+
1820+ status_new = (status_old & ~mask & ~tb_mask) | val;
1821+
1822+ /* Don't protect status register if we're fully unlocked */
1823+ if (lock_len == 0)
1824+ status_new &= ~SR_SRWD;
1825+
1826+ if (!use_top)
1827+ status_new |= tb_mask;
1828+
1829+ /* Don't bother if they're the same */
1830+ if (status_new == status_old)
1831+ return 0;
1832+
1833+ /* Only modify protection if it will not lock other areas */
1834+ if ((status_new & mask) > (status_old & mask))
1835+ return -EINVAL;
1836+
1837+ return spi_nor_write_sr_and_check(nor, status_new);
1838+}
1839+
1840+/*
1841+ * Check if a region of the flash is (completely) locked. See spi_nor_sr_lock()
1842+ * for more info.
1843+ *
1844+ * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
1845+ * negative on errors.
1846+ */
1847+static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1848+{
1849+ int ret;
1850+
1851+ ret = spi_nor_read_sr(nor, nor->bouncebuf);
1852+ if (ret)
1853+ return ret;
1854+
1855+ return spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]);
1856+}
1857+
1858+static const struct spi_nor_locking_ops spi_nor_sr_locking_ops = {
1859+ .lock = spi_nor_sr_lock,
1860+ .unlock = spi_nor_sr_unlock,
1861+ .is_locked = spi_nor_sr_is_locked,
1862+};
1863+
1864+static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1865+{
1866+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
1867+ int ret;
1868+
1869+ ret = spi_nor_lock_and_prep(nor);
1870+ if (ret)
1871+ return ret;
1872+
1873+ ret = nor->params->locking_ops->lock(nor, ofs, len);
1874+
1875+ spi_nor_unlock_and_unprep(nor);
1876+ return ret;
1877+}
1878+
1879+static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1880+{
1881+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
1882+ int ret;
1883+
1884+ ret = spi_nor_lock_and_prep(nor);
1885+ if (ret)
1886+ return ret;
1887+
1888+ ret = nor->params->locking_ops->unlock(nor, ofs, len);
1889+
1890+ spi_nor_unlock_and_unprep(nor);
1891+ return ret;
1892+}
1893+
1894+static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1895+{
1896+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
1897+ int ret;
1898+
1899+ ret = spi_nor_lock_and_prep(nor);
1900+ if (ret)
1901+ return ret;
1902+
1903+ ret = nor->params->locking_ops->is_locked(nor, ofs, len);
1904+
1905+ spi_nor_unlock_and_unprep(nor);
1906+ return ret;
1907+}
1908+
1909+/**
1910+ * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
1911+ * Register 1.
1912+ * @nor: pointer to a 'struct spi_nor'
1913+ *
1914+ * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
1915+ *
1916+ * Return: 0 on success, -errno otherwise.
1917+ */
1918+int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
1919+{
1920+ int ret;
1921+
1922+ ret = spi_nor_read_sr(nor, nor->bouncebuf);
1923+ if (ret)
1924+ return ret;
1925+
1926+ if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
1927+ return 0;
1928+
1929+ nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
1930+
1931+ return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
1932+}
1933+
1934+/**
1935+ * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
1936+ * Register 2.
1937+ * @nor: pointer to a 'struct spi_nor'.
1938+ *
1939+ * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
1940+ *
1941+ * Return: 0 on success, -errno otherwise.
1942+ */
1943+int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
1944+{
1945+ int ret;
1946+
1947+ if (nor->flags & SNOR_F_NO_READ_CR)
1948+ return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
1949+
1950+ ret = spi_nor_read_cr(nor, nor->bouncebuf);
1951+ if (ret)
1952+ return ret;
1953+
1954+ if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
1955+ return 0;
1956+
1957+ nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
1958+
1959+ return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
1960+}
1961+
1962+/**
1963+ * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1964+ * @nor: pointer to a 'struct spi_nor'
1965+ *
1966+ * Set the Quad Enable (QE) bit in the Status Register 2.
1967+ *
1968+ * This is one of the procedures to set the QE bit described in the SFDP
1969+ * (JESD216 rev B) specification but no manufacturer using this procedure has
1970+ * been identified yet, hence the name of the function.
1971+ *
1972+ * Return: 0 on success, -errno otherwise.
1973+ */
1974+int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
1975+{
1976+ u8 *sr2 = nor->bouncebuf;
1977+ int ret;
1978+ u8 sr2_written;
1979+
1980+ /* Check current Quad Enable bit value. */
1981+ ret = spi_nor_read_sr2(nor, sr2);
1982+ if (ret)
1983+ return ret;
1984+ if (*sr2 & SR2_QUAD_EN_BIT7)
1985+ return 0;
1986+
1987+ /* Update the Quad Enable bit. */
1988+ *sr2 |= SR2_QUAD_EN_BIT7;
1989+
1990+ ret = spi_nor_write_sr2(nor, sr2);
1991+ if (ret)
1992+ return ret;
1993+
1994+ sr2_written = *sr2;
1995+
1996+ /* Read back and check it. */
1997+ ret = spi_nor_read_sr2(nor, sr2);
1998+ if (ret)
1999+ return ret;
2000+
2001+ if (*sr2 != sr2_written) {
2002+ dev_dbg(nor->dev, "SR2: Read back test failed\n");
2003+ return -EIO;
2004+ }
2005+
2006+ return 0;
2007+}
2008+
2009+static const struct spi_nor_manufacturer *manufacturers[] = {
2010+ &spi_nor_atmel,
2011+ &spi_nor_catalyst,
2012+ &spi_nor_eon,
2013+ &spi_nor_esmt,
2014+ &spi_nor_everspin,
2015+ &spi_nor_fujitsu,
2016+ &spi_nor_gigadevice,
2017+ &spi_nor_intel,
2018+ &spi_nor_issi,
2019+ &spi_nor_macronix,
2020+ &spi_nor_micron,
2021+ &spi_nor_st,
2022+ &spi_nor_spansion,
2023+ &spi_nor_sst,
2024+ &spi_nor_winbond,
2025+ &spi_nor_xilinx,
2026+ &spi_nor_xmc,
2027+};
2028+
2029+static const struct flash_info *
2030+spi_nor_search_part_by_id(const struct flash_info *parts, unsigned int nparts,
2031+ const u8 *id)
2032+{
2033+ unsigned int i;
2034+
2035+ for (i = 0; i < nparts; i++) {
2036+ if (parts[i].id_len &&
2037+ !memcmp(parts[i].id, id, parts[i].id_len))
2038+ return &parts[i];
2039+ }
2040+
2041+ return NULL;
2042+}
2043+
2044+static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
2045+{
2046+ const struct flash_info *info;
2047+ u8 *id = nor->bouncebuf;
2048+ unsigned int i;
2049+ int ret;
2050+
2051+ if (nor->spimem) {
2052+ struct spi_mem_op op =
2053+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1),
2054+ SPI_MEM_OP_NO_ADDR,
2055+ SPI_MEM_OP_NO_DUMMY,
2056+ SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, id, 1));
2057+
2058+ ret = spi_mem_exec_op(nor->spimem, &op);
2059+ } else {
2060+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
2061+ SPI_NOR_MAX_ID_LEN);
2062+ }
2063+ if (ret) {
2064+ dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret);
2065+ return ERR_PTR(ret);
2066+ }
2067+
2068+ for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
2069+ info = spi_nor_search_part_by_id(manufacturers[i]->parts,
2070+ manufacturers[i]->nparts,
2071+ id);
2072+ if (info) {
2073+ nor->manufacturer = manufacturers[i];
2074+ return info;
2075+ }
2076+ }
2077+
2078+ dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
2079+ SPI_NOR_MAX_ID_LEN, id);
2080+ return ERR_PTR(-ENODEV);
2081+}
2082+
2083+static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
2084+ size_t *retlen, u_char *buf)
2085+{
2086+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
2087+ ssize_t ret;
2088+
2089+ dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
2090+
2091+ ret = spi_nor_lock_and_prep(nor);
2092+ if (ret)
2093+ return ret;
2094+
2095+ while (len) {
2096+ loff_t addr = from;
2097+
2098+ addr = spi_nor_convert_addr(nor, addr);
2099+
2100+ ret = spi_nor_read_data(nor, addr, len, buf);
2101+ if (ret == 0) {
2102+ /* We shouldn't see 0-length reads */
2103+ ret = -EIO;
2104+ goto read_err;
2105+ }
2106+ if (ret < 0)
2107+ goto read_err;
2108+
2109+ WARN_ON(ret > len);
2110+ *retlen += ret;
2111+ buf += ret;
2112+ from += ret;
2113+ len -= ret;
2114+ }
2115+ ret = 0;
2116+
2117+read_err:
2118+ spi_nor_unlock_and_unprep(nor);
2119+ return ret;
2120+}
2121+
2122+/*
2123+ * Write an address range to the nor chip. Data must be written in
2124+ * FLASH_PAGESIZE chunks. The address range may be any size provided
2125+ * it is within the physical boundaries.
2126+ */
2127+static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
2128+ size_t *retlen, const u_char *buf)
2129+{
2130+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
2131+ size_t page_offset, page_remain, i;
2132+ ssize_t ret;
2133+
2134+ dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
2135+
2136+ ret = spi_nor_lock_and_prep(nor);
2137+ if (ret)
2138+ return ret;
2139+
2140+ for (i = 0; i < len; ) {
2141+ ssize_t written;
2142+ loff_t addr = to + i;
2143+
2144+ /*
2145+ * If page_size is a power of two, the offset can be quickly
2146+ * calculated with an AND operation. On the other cases we
2147+ * need to do a modulus operation (more expensive).
2148+ * Power of two numbers have only one bit set and we can use
2149+ * the instruction hweight32 to detect if we need to do a
2150+ * modulus (do_div()) or not.
2151+ */
2152+ if (hweight32(nor->page_size) == 1) {
2153+ page_offset = addr & (nor->page_size - 1);
2154+ } else {
2155+ uint64_t aux = addr;
2156+
2157+ page_offset = do_div(aux, nor->page_size);
2158+ }
2159+ /* the size of data remaining on the first page */
2160+ page_remain = min_t(size_t,
2161+ nor->page_size - page_offset, len - i);
2162+
2163+ addr = spi_nor_convert_addr(nor, addr);
2164+
2165+ ret = spi_nor_write_enable(nor);
2166+ if (ret)
2167+ goto write_err;
2168+
2169+ ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
2170+ if (ret < 0)
2171+ goto write_err;
2172+ written = ret;
2173+
2174+ ret = spi_nor_wait_till_ready(nor);
2175+ if (ret)
2176+ goto write_err;
2177+ *retlen += written;
2178+ i += written;
2179+ }
2180+
2181+write_err:
2182+ spi_nor_unlock_and_unprep(nor);
2183+ return ret;
2184+}
2185+
2186+static int spi_nor_check(struct spi_nor *nor)
2187+{
2188+ if (!nor->dev ||
2189+ (!nor->spimem && !nor->controller_ops) ||
2190+ (!nor->spimem && nor->controller_ops &&
2191+ (!nor->controller_ops->read ||
2192+ !nor->controller_ops->write ||
2193+ !nor->controller_ops->read_reg ||
2194+ !nor->controller_ops->write_reg))) {
2195+ pr_err("spi-nor: please fill all the necessary fields!\n");
2196+ return -EINVAL;
2197+ }
2198+
2199+ if (nor->spimem && nor->controller_ops) {
2200+ dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n");
2201+ return -EINVAL;
2202+ }
2203+
2204+ return 0;
2205+}
2206+
2207+static void
2208+spi_nor_set_read_settings(struct spi_nor_read_command *read,
2209+ u8 num_mode_clocks,
2210+ u8 num_wait_states,
2211+ u8 opcode,
2212+ enum spi_nor_protocol proto)
2213+{
2214+ read->num_mode_clocks = num_mode_clocks;
2215+ read->num_wait_states = num_wait_states;
2216+ read->opcode = opcode;
2217+ read->proto = proto;
2218+}
2219+
2220+void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
2221+ enum spi_nor_protocol proto)
2222+{
2223+ pp->opcode = opcode;
2224+ pp->proto = proto;
2225+}
2226+
2227+static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2228+{
2229+ size_t i;
2230+
2231+ for (i = 0; i < size; i++)
2232+ if (table[i][0] == (int)hwcaps)
2233+ return table[i][1];
2234+
2235+ return -EINVAL;
2236+}
2237+
2238+int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2239+{
2240+ static const int hwcaps_read2cmd[][2] = {
2241+ { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2242+ { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2243+ { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2244+ { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2245+ { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2246+ { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2247+ { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2248+ { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2249+ { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2250+ { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2251+ { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2252+ { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2253+ { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2254+ { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2255+ { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2256+ };
2257+
2258+ return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2259+ ARRAY_SIZE(hwcaps_read2cmd));
2260+}
2261+
2262+static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2263+{
2264+ static const int hwcaps_pp2cmd[][2] = {
2265+ { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2266+ { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2267+ { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2268+ { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2269+ { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2270+ { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2271+ { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2272+ };
2273+
2274+ return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2275+ ARRAY_SIZE(hwcaps_pp2cmd));
2276+}
2277+
2278+/**
2279+ * spi_nor_spimem_check_op - check if the operation is supported
2280+ * by controller
2281+ *@nor: pointer to a 'struct spi_nor'
2282+ *@op: pointer to op template to be checked
2283+ *
2284+ * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2285+ */
2286+static int spi_nor_spimem_check_op(struct spi_nor *nor,
2287+ struct spi_mem_op *op)
2288+{
2289+ /*
2290+ * First test with 4 address bytes. The opcode itself might
2291+ * be a 3B addressing opcode but we don't care, because
2292+ * SPI controller implementation should not check the opcode,
2293+ * but just the sequence.
2294+ */
2295+ op->addr.nbytes = 4;
2296+ if (!spi_mem_supports_op(nor->spimem, op)) {
2297+ if (nor->mtd.size > SZ_16M)
2298+ return -ENOTSUPP;
2299+
2300+ /* If flash size <= 16MB, 3 address bytes are sufficient */
2301+ op->addr.nbytes = 3;
2302+ if (!spi_mem_supports_op(nor->spimem, op))
2303+ return -ENOTSUPP;
2304+ }
2305+
2306+ return 0;
2307+}
2308+
2309+/**
2310+ * spi_nor_spimem_check_readop - check if the read op is supported
2311+ * by controller
2312+ *@nor: pointer to a 'struct spi_nor'
2313+ *@read: pointer to op template to be checked
2314+ *
2315+ * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2316+ */
2317+static int spi_nor_spimem_check_readop(struct spi_nor *nor,
2318+ const struct spi_nor_read_command *read)
2319+{
2320+ struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 1),
2321+ SPI_MEM_OP_ADDR(3, 0, 1),
2322+ SPI_MEM_OP_DUMMY(0, 1),
2323+ SPI_MEM_OP_DATA_IN(0, NULL, 1));
2324+
2325+ op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(read->proto);
2326+ op.addr.buswidth = spi_nor_get_protocol_addr_nbits(read->proto);
2327+ op.data.buswidth = spi_nor_get_protocol_data_nbits(read->proto);
2328+ op.dummy.buswidth = op.addr.buswidth;
2329+ op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
2330+ op.dummy.buswidth / 8;
2331+
2332+ return spi_nor_spimem_check_op(nor, &op);
2333+}
2334+
2335+/**
2336+ * spi_nor_spimem_check_pp - check if the page program op is supported
2337+ * by controller
2338+ *@nor: pointer to a 'struct spi_nor'
2339+ *@pp: pointer to op template to be checked
2340+ *
2341+ * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2342+ */
2343+static int spi_nor_spimem_check_pp(struct spi_nor *nor,
2344+ const struct spi_nor_pp_command *pp)
2345+{
2346+ struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 1),
2347+ SPI_MEM_OP_ADDR(3, 0, 1),
2348+ SPI_MEM_OP_NO_DUMMY,
2349+ SPI_MEM_OP_DATA_OUT(0, NULL, 1));
2350+
2351+ op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(pp->proto);
2352+ op.addr.buswidth = spi_nor_get_protocol_addr_nbits(pp->proto);
2353+ op.data.buswidth = spi_nor_get_protocol_data_nbits(pp->proto);
2354+
2355+ return spi_nor_spimem_check_op(nor, &op);
2356+}
2357+
2358+/**
2359+ * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol
2360+ * based on SPI controller capabilities
2361+ * @nor: pointer to a 'struct spi_nor'
2362+ * @hwcaps: pointer to resulting capabilities after adjusting
2363+ * according to controller and flash's capability
2364+ */
2365+static void
2366+spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
2367+{
2368+ struct spi_nor_flash_parameter *params = nor->params;
2369+ unsigned int cap;
2370+
2371+ /* DTR modes are not supported yet, mask them all. */
2372+ *hwcaps &= ~SNOR_HWCAPS_DTR;
2373+
2374+ /* X-X-X modes are not supported yet, mask them all. */
2375+ *hwcaps &= ~SNOR_HWCAPS_X_X_X;
2376+
2377+ for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
2378+ int rdidx, ppidx;
2379+
2380+ if (!(*hwcaps & BIT(cap)))
2381+ continue;
2382+
2383+ rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
2384+ if (rdidx >= 0 &&
2385+ spi_nor_spimem_check_readop(nor, &params->reads[rdidx]))
2386+ *hwcaps &= ~BIT(cap);
2387+
2388+ ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
2389+ if (ppidx < 0)
2390+ continue;
2391+
2392+ if (spi_nor_spimem_check_pp(nor,
2393+ &params->page_programs[ppidx]))
2394+ *hwcaps &= ~BIT(cap);
2395+ }
2396+}
2397+
2398+/**
2399+ * spi_nor_set_erase_type() - set a SPI NOR erase type
2400+ * @erase: pointer to a structure that describes a SPI NOR erase type
2401+ * @size: the size of the sector/block erased by the erase type
2402+ * @opcode: the SPI command op code to erase the sector/block
2403+ */
2404+void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
2405+ u8 opcode)
2406+{
2407+ erase->size = size;
2408+ erase->opcode = opcode;
2409+ /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
2410+ erase->size_shift = ffs(erase->size) - 1;
2411+ erase->size_mask = (1 << erase->size_shift) - 1;
2412+}
2413+
2414+/**
2415+ * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
2416+ * @map: the erase map of the SPI NOR
2417+ * @erase_mask: bitmask encoding erase types that can erase the entire
2418+ * flash memory
2419+ * @flash_size: the spi nor flash memory size
2420+ */
2421+void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
2422+ u8 erase_mask, u64 flash_size)
2423+{
2424+ /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */
2425+ map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) |
2426+ SNOR_LAST_REGION;
2427+ map->uniform_region.size = flash_size;
2428+ map->regions = &map->uniform_region;
2429+ map->uniform_erase_type = erase_mask;
2430+}
2431+
2432+int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
2433+ const struct sfdp_parameter_header *bfpt_header,
2434+ const struct sfdp_bfpt *bfpt,
2435+ struct spi_nor_flash_parameter *params)
2436+{
2437+ int ret;
2438+
2439+ if (nor->manufacturer && nor->manufacturer->fixups &&
2440+ nor->manufacturer->fixups->post_bfpt) {
2441+ ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header,
2442+ bfpt, params);
2443+ if (ret)
2444+ return ret;
2445+ }
2446+
2447+ if (nor->info->fixups && nor->info->fixups->post_bfpt)
2448+ return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt,
2449+ params);
2450+
2451+ return 0;
2452+}
2453+
2454+static int spi_nor_select_read(struct spi_nor *nor,
2455+ u32 shared_hwcaps)
2456+{
2457+ int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2458+ const struct spi_nor_read_command *read;
2459+
2460+ if (best_match < 0)
2461+ return -EINVAL;
2462+
2463+ cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2464+ if (cmd < 0)
2465+ return -EINVAL;
2466+
2467+ read = &nor->params->reads[cmd];
2468+ nor->read_opcode = read->opcode;
2469+ nor->read_proto = read->proto;
2470+
2471+ /*
2472+ * In the spi-nor framework, we don't need to make the difference
2473+ * between mode clock cycles and wait state clock cycles.
2474+ * Indeed, the value of the mode clock cycles is used by a QSPI
2475+ * flash memory to know whether it should enter or leave its 0-4-4
2476+ * (Continuous Read / XIP) mode.
2477+ * eXecution In Place is out of the scope of the mtd sub-system.
2478+ * Hence we choose to merge both mode and wait state clock cycles
2479+ * into the so called dummy clock cycles.
2480+ */
2481+ nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2482+ return 0;
2483+}
2484+
2485+static int spi_nor_select_pp(struct spi_nor *nor,
2486+ u32 shared_hwcaps)
2487+{
2488+ int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2489+ const struct spi_nor_pp_command *pp;
2490+
2491+ if (best_match < 0)
2492+ return -EINVAL;
2493+
2494+ cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2495+ if (cmd < 0)
2496+ return -EINVAL;
2497+
2498+ pp = &nor->params->page_programs[cmd];
2499+ nor->program_opcode = pp->opcode;
2500+ nor->write_proto = pp->proto;
2501+ return 0;
2502+}
2503+
2504+/**
2505+ * spi_nor_select_uniform_erase() - select optimum uniform erase type
2506+ * @map: the erase map of the SPI NOR
2507+ * @wanted_size: the erase type size to search for. Contains the value of
2508+ * info->sector_size or of the "small sector" size in case
2509+ * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined.
2510+ *
2511+ * Once the optimum uniform sector erase command is found, disable all the
2512+ * other.
2513+ *
2514+ * Return: pointer to erase type on success, NULL otherwise.
2515+ */
2516+static const struct spi_nor_erase_type *
2517+spi_nor_select_uniform_erase(struct spi_nor_erase_map *map,
2518+ const u32 wanted_size)
2519+{
2520+ const struct spi_nor_erase_type *tested_erase, *erase = NULL;
2521+ int i;
2522+ u8 uniform_erase_type = map->uniform_erase_type;
2523+
2524+ for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2525+ if (!(uniform_erase_type & BIT(i)))
2526+ continue;
2527+
2528+ tested_erase = &map->erase_type[i];
2529+
2530+ /*
2531+ * If the current erase size is the one, stop here:
2532+ * we have found the right uniform Sector Erase command.
2533+ */
2534+ if (tested_erase->size == wanted_size) {
2535+ erase = tested_erase;
2536+ break;
2537+ }
2538+
2539+ /*
2540+ * Otherwise, the current erase size is still a valid canditate.
2541+ * Select the biggest valid candidate.
2542+ */
2543+ if (!erase && tested_erase->size)
2544+ erase = tested_erase;
2545+ /* keep iterating to find the wanted_size */
2546+ }
2547+
2548+ if (!erase)
2549+ return NULL;
2550+
2551+ /* Disable all other Sector Erase commands. */
2552+ map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK;
2553+ map->uniform_erase_type |= BIT(erase - map->erase_type);
2554+ return erase;
2555+}
2556+
2557+static int spi_nor_select_erase(struct spi_nor *nor)
2558+{
2559+ struct spi_nor_erase_map *map = &nor->params->erase_map;
2560+ const struct spi_nor_erase_type *erase = NULL;
2561+ struct mtd_info *mtd = &nor->mtd;
2562+ u32 wanted_size = nor->info->sector_size;
2563+ int i;
2564+
2565+ /*
2566+ * The previous implementation handling Sector Erase commands assumed
2567+ * that the SPI flash memory has an uniform layout then used only one
2568+ * of the supported erase sizes for all Sector Erase commands.
2569+ * So to be backward compatible, the new implementation also tries to
2570+ * manage the SPI flash memory as uniform with a single erase sector
2571+ * size, when possible.
2572+ */
2573+#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
2574+ /* prefer "small sector" erase if possible */
2575+ wanted_size = 4096u;
2576+#endif
2577+
2578+ if (spi_nor_has_uniform_erase(nor)) {
2579+ erase = spi_nor_select_uniform_erase(map, wanted_size);
2580+ if (!erase)
2581+ return -EINVAL;
2582+ nor->erase_opcode = erase->opcode;
2583+ mtd->erasesize = erase->size;
2584+ return 0;
2585+ }
2586+
2587+ /*
2588+ * For non-uniform SPI flash memory, set mtd->erasesize to the
2589+ * maximum erase sector size. No need to set nor->erase_opcode.
2590+ */
2591+ for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2592+ if (map->erase_type[i].size) {
2593+ erase = &map->erase_type[i];
2594+ break;
2595+ }
2596+ }
2597+
2598+ if (!erase)
2599+ return -EINVAL;
2600+
2601+ mtd->erasesize = erase->size;
2602+ return 0;
2603+}
2604+
2605+static int spi_nor_default_setup(struct spi_nor *nor,
2606+ const struct spi_nor_hwcaps *hwcaps)
2607+{
2608+ struct spi_nor_flash_parameter *params = nor->params;
2609+ u32 ignored_mask, shared_mask;
2610+ int err;
2611+
2612+ /*
2613+ * Keep only the hardware capabilities supported by both the SPI
2614+ * controller and the SPI flash memory.
2615+ */
2616+ shared_mask = hwcaps->mask & params->hwcaps.mask;
2617+
2618+ if (nor->spimem) {
2619+ /*
2620+ * When called from spi_nor_probe(), all caps are set and we
2621+ * need to discard some of them based on what the SPI
2622+ * controller actually supports (using spi_mem_supports_op()).
2623+ */
2624+ spi_nor_spimem_adjust_hwcaps(nor, &shared_mask);
2625+ } else {
2626+ /*
2627+ * SPI n-n-n protocols are not supported when the SPI
2628+ * controller directly implements the spi_nor interface.
2629+ * Yet another reason to switch to spi-mem.
2630+ */
2631+ ignored_mask = SNOR_HWCAPS_X_X_X;
2632+ if (shared_mask & ignored_mask) {
2633+ dev_dbg(nor->dev,
2634+ "SPI n-n-n protocols are not supported.\n");
2635+ shared_mask &= ~ignored_mask;
2636+ }
2637+ }
2638+
2639+ /* Select the (Fast) Read command. */
2640+ err = spi_nor_select_read(nor, shared_mask);
2641+ if (err) {
2642+ dev_dbg(nor->dev,
2643+ "can't select read settings supported by both the SPI controller and memory.\n");
2644+ return err;
2645+ }
2646+
2647+ /* Select the Page Program command. */
2648+ err = spi_nor_select_pp(nor, shared_mask);
2649+ if (err) {
2650+ dev_dbg(nor->dev,
2651+ "can't select write settings supported by both the SPI controller and memory.\n");
2652+ return err;
2653+ }
2654+
2655+ /* Select the Sector Erase command. */
2656+ err = spi_nor_select_erase(nor);
2657+ if (err) {
2658+ dev_dbg(nor->dev,
2659+ "can't select erase settings supported by both the SPI controller and memory.\n");
2660+ return err;
2661+ }
2662+
2663+ return 0;
2664+}
2665+
2666+static int spi_nor_setup(struct spi_nor *nor,
2667+ const struct spi_nor_hwcaps *hwcaps)
2668+{
2669+ if (!nor->params->setup)
2670+ return 0;
2671+
2672+ return nor->params->setup(nor, hwcaps);
2673+}
2674+
2675+/**
2676+ * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
2677+ * settings based on MFR register and ->default_init() hook.
2678+ * @nor: pointer to a 'struct spi-nor'.
2679+ */
2680+static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
2681+{
2682+ if (nor->manufacturer && nor->manufacturer->fixups &&
2683+ nor->manufacturer->fixups->default_init)
2684+ nor->manufacturer->fixups->default_init(nor);
2685+
2686+ if (nor->info->fixups && nor->info->fixups->default_init)
2687+ nor->info->fixups->default_init(nor);
2688+}
2689+
2690+/**
2691+ * spi_nor_sfdp_init_params() - Initialize the flash's parameters and settings
2692+ * based on JESD216 SFDP standard.
2693+ * @nor: pointer to a 'struct spi-nor'.
2694+ *
2695+ * The method has a roll-back mechanism: in case the SFDP parsing fails, the
2696+ * legacy flash parameters and settings will be restored.
2697+ */
2698+static void spi_nor_sfdp_init_params(struct spi_nor *nor)
2699+{
2700+ struct spi_nor_flash_parameter sfdp_params;
2701+
2702+ memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));
2703+
2704+ if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
2705+ nor->addr_width = 0;
2706+ nor->flags &= ~SNOR_F_4B_OPCODES;
2707+ } else {
2708+ memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
2709+ }
2710+}
2711+
2712+/**
2713+ * spi_nor_info_init_params() - Initialize the flash's parameters and settings
2714+ * based on nor->info data.
2715+ * @nor: pointer to a 'struct spi-nor'.
2716+ */
2717+static void spi_nor_info_init_params(struct spi_nor *nor)
2718+{
2719+ struct spi_nor_flash_parameter *params = nor->params;
2720+ struct spi_nor_erase_map *map = &params->erase_map;
2721+ const struct flash_info *info = nor->info;
2722+ struct device_node *np = spi_nor_get_flash_node(nor);
2723+ u8 i, erase_mask;
2724+
2725+ /* Initialize legacy flash parameters and settings. */
2726+ params->quad_enable = spi_nor_sr2_bit1_quad_enable;
2727+ params->set_4byte_addr_mode = spansion_set_4byte_addr_mode;
2728+ params->setup = spi_nor_default_setup;
2729+ /* Default to 16-bit Write Status (01h) Command */
2730+ nor->flags |= SNOR_F_HAS_16BIT_SR;
2731+
2732+ /* Set SPI NOR sizes. */
2733+ params->size = (u64)info->sector_size * info->n_sectors;
2734+ params->page_size = info->page_size;
2735+
2736+ if (!(info->flags & SPI_NOR_NO_FR)) {
2737+ /* Default to Fast Read for DT and non-DT platform devices. */
2738+ params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2739+
2740+ /* Mask out Fast Read if not requested at DT instantiation. */
2741+ if (np && !of_property_read_bool(np, "m25p,fast-read"))
2742+ params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2743+ }
2744+
2745+ /* (Fast) Read settings. */
2746+ params->hwcaps.mask |= SNOR_HWCAPS_READ;
2747+ spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
2748+ 0, 0, SPINOR_OP_READ,
2749+ SNOR_PROTO_1_1_1);
2750+
2751+ if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
2752+ spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
2753+ 0, 8, SPINOR_OP_READ_FAST,
2754+ SNOR_PROTO_1_1_1);
2755+
2756+ if (info->flags & SPI_NOR_DUAL_READ) {
2757+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2758+ spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
2759+ 0, 8, SPINOR_OP_READ_1_1_2,
2760+ SNOR_PROTO_1_1_2);
2761+ }
2762+
2763+ if (info->flags & SPI_NOR_QUAD_READ) {
2764+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2765+ spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
2766+ 0, 8, SPINOR_OP_READ_1_1_4,
2767+ SNOR_PROTO_1_1_4);
2768+ }
2769+
2770+ if (info->flags & SPI_NOR_OCTAL_READ) {
2771+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2772+ spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
2773+ 0, 8, SPINOR_OP_READ_1_1_8,
2774+ SNOR_PROTO_1_1_8);
2775+ }
2776+
2777+ /* Page Program settings. */
2778+ params->hwcaps.mask |= SNOR_HWCAPS_PP;
2779+ spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
2780+ SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2781+
2782+ /*
2783+ * Sector Erase settings. Sort Erase Types in ascending order, with the
2784+ * smallest erase size starting at BIT(0).
2785+ */
2786+ erase_mask = 0;
2787+ i = 0;
2788+ if (info->flags & SECT_4K_PMC) {
2789+ erase_mask |= BIT(i);
2790+ spi_nor_set_erase_type(&map->erase_type[i], 4096u,
2791+ SPINOR_OP_BE_4K_PMC);
2792+ i++;
2793+ } else if (info->flags & SECT_4K) {
2794+ erase_mask |= BIT(i);
2795+ spi_nor_set_erase_type(&map->erase_type[i], 4096u,
2796+ SPINOR_OP_BE_4K);
2797+ i++;
2798+ }
2799+ erase_mask |= BIT(i);
2800+ spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
2801+ SPINOR_OP_SE);
2802+ spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
2803+}
2804+
2805+/**
2806+ * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings
2807+ * after SFDP has been parsed (is also called for SPI NORs that do not
2808+ * support RDSFDP).
2809+ * @nor: pointer to a 'struct spi_nor'
2810+ *
2811+ * Typically used to tweak various parameters that could not be extracted by
2812+ * other means (i.e. when information provided by the SFDP/flash_info tables
2813+ * are incomplete or wrong).
2814+ */
2815+static void spi_nor_post_sfdp_fixups(struct spi_nor *nor)
2816+{
2817+ if (nor->manufacturer && nor->manufacturer->fixups &&
2818+ nor->manufacturer->fixups->post_sfdp)
2819+ nor->manufacturer->fixups->post_sfdp(nor);
2820+
2821+ if (nor->info->fixups && nor->info->fixups->post_sfdp)
2822+ nor->info->fixups->post_sfdp(nor);
2823+}
2824+
2825+/**
2826+ * spi_nor_late_init_params() - Late initialization of default flash parameters.
2827+ * @nor: pointer to a 'struct spi_nor'
2828+ *
2829+ * Used to set default flash parameters and settings when the ->default_init()
2830+ * hook or the SFDP parser let voids.
2831+ */
2832+static void spi_nor_late_init_params(struct spi_nor *nor)
2833+{
2834+ /*
2835+ * NOR protection support. When locking_ops are not provided, we pick
2836+ * the default ones.
2837+ */
2838+ if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops)
2839+ nor->params->locking_ops = &spi_nor_sr_locking_ops;
2840+}
2841+
2842+/**
2843+ * spi_nor_init_params() - Initialize the flash's parameters and settings.
2844+ * @nor: pointer to a 'struct spi-nor'.
2845+ *
2846+ * The flash parameters and settings are initialized based on a sequence of
2847+ * calls that are ordered by priority:
2848+ *
2849+ * 1/ Default flash parameters initialization. The initializations are done
2850+ * based on nor->info data:
2851+ * spi_nor_info_init_params()
2852+ *
2853+ * which can be overwritten by:
2854+ * 2/ Manufacturer flash parameters initialization. The initializations are
2855+ * done based on MFR register, or when the decisions can not be done solely
2856+ * based on MFR, by using specific flash_info tweeks, ->default_init():
2857+ * spi_nor_manufacturer_init_params()
2858+ *
2859+ * which can be overwritten by:
2860+ * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and
2861+ * should be more accurate that the above.
2862+ * spi_nor_sfdp_init_params()
2863+ *
2864+ * Please note that there is a ->post_bfpt() fixup hook that can overwrite
2865+ * the flash parameters and settings immediately after parsing the Basic
2866+ * Flash Parameter Table.
2867+ *
2868+ * which can be overwritten by:
2869+ * 4/ Post SFDP flash parameters initialization. Used to tweak various
2870+ * parameters that could not be extracted by other means (i.e. when
2871+ * information provided by the SFDP/flash_info tables are incomplete or
2872+ * wrong).
2873+ * spi_nor_post_sfdp_fixups()
2874+ *
2875+ * 5/ Late default flash parameters initialization, used when the
2876+ * ->default_init() hook or the SFDP parser do not set specific params.
2877+ * spi_nor_late_init_params()
2878+ */
2879+static int spi_nor_init_params(struct spi_nor *nor)
2880+{
2881+ nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL);
2882+ if (!nor->params)
2883+ return -ENOMEM;
2884+
2885+ spi_nor_info_init_params(nor);
2886+
2887+ spi_nor_manufacturer_init_params(nor);
2888+
2889+ if ((nor->info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
2890+ !(nor->info->flags & SPI_NOR_SKIP_SFDP))
2891+ spi_nor_sfdp_init_params(nor);
2892+
2893+ spi_nor_post_sfdp_fixups(nor);
2894+
2895+ spi_nor_late_init_params(nor);
2896+
2897+ return 0;
2898+}
2899+
2900+/**
2901+ * spi_nor_quad_enable() - enable Quad I/O if needed.
2902+ * @nor: pointer to a 'struct spi_nor'
2903+ *
2904+ * Return: 0 on success, -errno otherwise.
2905+ */
2906+static int spi_nor_quad_enable(struct spi_nor *nor)
2907+{
2908+ if (!nor->params->quad_enable)
2909+ return 0;
2910+
2911+ if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2912+ spi_nor_get_protocol_width(nor->write_proto) == 4))
2913+ return 0;
2914+
2915+ return nor->params->quad_enable(nor);
2916+}
2917+
2918+/**
2919+ * spi_nor_unlock_all() - Unlocks the entire flash memory array.
2920+ * @nor: pointer to a 'struct spi_nor'.
2921+ *
2922+ * Some SPI NOR flashes are write protected by default after a power-on reset
2923+ * cycle, in order to avoid inadvertent writes during power-up. Backward
2924+ * compatibility imposes to unlock the entire flash memory array at power-up
2925+ * by default.
2926+ */
2927+static int spi_nor_unlock_all(struct spi_nor *nor)
2928+{
2929+ if (nor->flags & SNOR_F_HAS_LOCK)
2930+ return spi_nor_unlock(&nor->mtd, 0, nor->params->size);
2931+
2932+ return 0;
2933+}
2934+
2935+static int spi_nor_init(struct spi_nor *nor)
2936+{
2937+ int err;
2938+
2939+ err = spi_nor_quad_enable(nor);
2940+ if (err) {
2941+ dev_dbg(nor->dev, "quad mode not supported\n");
2942+ return err;
2943+ }
2944+
2945+ err = spi_nor_unlock_all(nor);
2946+ if (err) {
2947+ dev_dbg(nor->dev, "Failed to unlock the entire flash memory array\n");
2948+ return err;
2949+ }
2950+
2951+ if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES)) {
2952+ /*
2953+ * If the RESET# pin isn't hooked up properly, or the system
2954+ * otherwise doesn't perform a reset command in the boot
2955+ * sequence, it's impossible to 100% protect against unexpected
2956+ * reboots (e.g., crashes). Warn the user (or hopefully, system
2957+ * designer) that this is bad.
2958+ */
2959+ WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
2960+ "enabling reset hack; may not recover from unexpected reboots\n");
2961+ nor->params->set_4byte_addr_mode(nor, true);
2962+ }
2963+
2964+ return 0;
2965+}
2966+
2967+/* mtd resume handler */
2968+static void spi_nor_resume(struct mtd_info *mtd)
2969+{
2970+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
2971+ struct device *dev = nor->dev;
2972+ int ret;
2973+
2974+ /* re-initialize the nor chip */
2975+ ret = spi_nor_init(nor);
2976+ if (ret)
2977+ dev_err(dev, "resume() failed\n");
2978+}
2979+
2980+void spi_nor_restore(struct spi_nor *nor)
2981+{
2982+ /* restore the addressing mode */
2983+ if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
2984+ nor->flags & SNOR_F_BROKEN_RESET)
2985+ nor->params->set_4byte_addr_mode(nor, false);
2986+}
2987+EXPORT_SYMBOL_GPL(spi_nor_restore);
2988+
2989+static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,
2990+ const char *name)
2991+{
2992+ unsigned int i, j;
2993+
2994+ for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
2995+ for (j = 0; j < manufacturers[i]->nparts; j++) {
2996+ if (!strcmp(name, manufacturers[i]->parts[j].name)) {
2997+ nor->manufacturer = manufacturers[i];
2998+ return &manufacturers[i]->parts[j];
2999+ }
3000+ }
3001+ }
3002+
3003+ return NULL;
3004+}
3005+
3006+static int spi_nor_set_addr_width(struct spi_nor *nor)
3007+{
3008+ if (nor->addr_width) {
3009+ /* already configured from SFDP */
3010+ } else if (nor->info->addr_width) {
3011+ nor->addr_width = nor->info->addr_width;
3012+ } else if (nor->mtd.size > 0x1000000) {
3013+ /* enable 4-byte addressing if the device exceeds 16MiB */
3014+ nor->addr_width = 4;
3015+ } else {
3016+ nor->addr_width = 3;
3017+ }
3018+
3019+ if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
3020+ dev_dbg(nor->dev, "address width is too large: %u\n",
3021+ nor->addr_width);
3022+ return -EINVAL;
3023+ }
3024+
3025+ /* Set 4byte opcodes when possible. */
3026+ if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES &&
3027+ !(nor->flags & SNOR_F_HAS_4BAIT))
3028+ spi_nor_set_4byte_opcodes(nor);
3029+
3030+ return 0;
3031+}
3032+
3033+static void spi_nor_debugfs_init(struct spi_nor *nor,
3034+ const struct flash_info *info)
3035+{
3036+ struct mtd_info *mtd = &nor->mtd;
3037+
3038+ mtd->dbg.partname = info->name;
3039+ mtd->dbg.partid = devm_kasprintf(nor->dev, GFP_KERNEL, "spi-nor:%*phN",
3040+ info->id_len, info->id);
3041+}
3042+
3043+static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
3044+ const char *name)
3045+{
3046+ const struct flash_info *info = NULL;
3047+
3048+ if (name)
3049+ info = spi_nor_match_id(nor, name);
3050+ /* Try to auto-detect if chip name wasn't specified or not found */
3051+ if (!info)
3052+ info = spi_nor_read_id(nor);
3053+ if (IS_ERR_OR_NULL(info))
3054+ return ERR_PTR(-ENOENT);
3055+
3056+ /*
3057+ * If caller has specified name of flash model that can normally be
3058+ * detected using JEDEC, let's verify it.
3059+ */
3060+ if (name && info->id_len) {
3061+ const struct flash_info *jinfo;
3062+
3063+ jinfo = spi_nor_read_id(nor);
3064+ if (IS_ERR(jinfo)) {
3065+ return jinfo;
3066+ } else if (jinfo != info) {
3067+ /*
3068+ * JEDEC knows better, so overwrite platform ID. We
3069+ * can't trust partitions any longer, but we'll let
3070+ * mtd apply them anyway, since some partitions may be
3071+ * marked read-only, and we don't want to lose that
3072+ * information, even if it's not 100% accurate.
3073+ */
3074+ dev_warn(nor->dev, "found %s, expected %s\n",
3075+ jinfo->name, info->name);
3076+ info = jinfo;
3077+ }
3078+ }
3079+
3080+ return info;
3081+}
3082+
3083+int spi_nor_scan(struct spi_nor *nor, const char *name,
3084+ const struct spi_nor_hwcaps *hwcaps)
3085+{
3086+ const struct flash_info *info;
3087+ struct device *dev = nor->dev;
3088+ struct mtd_info *mtd = &nor->mtd;
3089+ struct device_node *np = spi_nor_get_flash_node(nor);
3090+ int ret;
3091+ int i;
3092+
3093+ ret = spi_nor_check(nor);
3094+ if (ret)
3095+ return ret;
3096+
3097+ /* Reset SPI protocol for all commands. */
3098+ nor->reg_proto = SNOR_PROTO_1_1_1;
3099+ nor->read_proto = SNOR_PROTO_1_1_1;
3100+ nor->write_proto = SNOR_PROTO_1_1_1;
3101+
3102+ /*
3103+ * We need the bounce buffer early to read/write registers when going
3104+ * through the spi-mem layer (buffers have to be DMA-able).
3105+ * For spi-mem drivers, we'll reallocate a new buffer if
3106+ * nor->page_size turns out to be greater than PAGE_SIZE (which
3107+ * shouldn't happen before long since NOR pages are usually less
3108+ * than 1KB) after spi_nor_scan() returns.
3109+ */
3110+ nor->bouncebuf_size = PAGE_SIZE;
3111+ nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size,
3112+ GFP_KERNEL);
3113+ if (!nor->bouncebuf)
3114+ return -ENOMEM;
3115+
3116+ info = spi_nor_get_flash_info(nor, name);
3117+ if (IS_ERR(info))
3118+ return PTR_ERR(info);
3119+
3120+ nor->info = info;
3121+
3122+ spi_nor_debugfs_init(nor, info);
3123+
3124+ mutex_init(&nor->lock);
3125+
3126+ /*
3127+ * Make sure the XSR_RDY flag is set before calling
3128+ * spi_nor_wait_till_ready(). Xilinx S3AN share MFR
3129+ * with Atmel spi-nor
3130+ */
3131+ if (info->flags & SPI_NOR_XSR_RDY)
3132+ nor->flags |= SNOR_F_READY_XSR_RDY;
3133+
3134+ if (info->flags & SPI_NOR_HAS_LOCK)
3135+ nor->flags |= SNOR_F_HAS_LOCK;
3136+
3137+ mtd->_write = spi_nor_write;
3138+
3139+ /* Init flash parameters based on flash_info struct and SFDP */
3140+ ret = spi_nor_init_params(nor);
3141+ if (ret)
3142+ return ret;
3143+
3144+ if (!mtd->name)
3145+ mtd->name = dev_name(dev);
3146+ mtd->priv = nor;
3147+ mtd->type = MTD_NORFLASH;
3148+ mtd->writesize = 1;
3149+ mtd->flags = MTD_CAP_NORFLASH;
3150+ mtd->size = nor->params->size;
3151+ mtd->_erase = spi_nor_erase;
3152+ mtd->_read = spi_nor_read;
3153+ mtd->_resume = spi_nor_resume;
3154+
3155+ if (nor->params->locking_ops) {
3156+ mtd->_lock = spi_nor_lock;
3157+ mtd->_unlock = spi_nor_unlock;
3158+ mtd->_is_locked = spi_nor_is_locked;
3159+ }
3160+
3161+ if (info->flags & USE_FSR)
3162+ nor->flags |= SNOR_F_USE_FSR;
3163+ if (info->flags & SPI_NOR_HAS_TB) {
3164+ nor->flags |= SNOR_F_HAS_SR_TB;
3165+ if (info->flags & SPI_NOR_TB_SR_BIT6)
3166+ nor->flags |= SNOR_F_HAS_SR_TB_BIT6;
3167+ }
3168+
3169+ if (info->flags & NO_CHIP_ERASE)
3170+ nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
3171+ if (info->flags & USE_CLSR)
3172+ nor->flags |= SNOR_F_USE_CLSR;
3173+
3174+ if (info->flags & SPI_NOR_4BIT_BP) {
3175+ nor->flags |= SNOR_F_HAS_4BIT_BP;
3176+ if (info->flags & SPI_NOR_BP3_SR_BIT6)
3177+ nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;
3178+ }
3179+
3180+ if (info->flags & SPI_NOR_NO_ERASE)
3181+ mtd->flags |= MTD_NO_ERASE;
3182+
3183+ mtd->dev.parent = dev;
3184+ nor->page_size = nor->params->page_size;
3185+ mtd->writebufsize = nor->page_size;
3186+
3187+ if (of_property_read_bool(np, "broken-flash-reset"))
3188+ nor->flags |= SNOR_F_BROKEN_RESET;
3189+
3190+ /*
3191+ * Configure the SPI memory:
3192+ * - select op codes for (Fast) Read, Page Program and Sector Erase.
3193+ * - set the number of dummy cycles (mode cycles + wait states).
3194+ * - set the SPI protocols for register and memory accesses.
3195+ */
3196+ ret = spi_nor_setup(nor, hwcaps);
3197+ if (ret)
3198+ return ret;
3199+
3200+ if (info->flags & SPI_NOR_4B_OPCODES)
3201+ nor->flags |= SNOR_F_4B_OPCODES;
3202+
3203+ ret = spi_nor_set_addr_width(nor);
3204+ if (ret)
3205+ return ret;
3206+
3207+ /* Send all the required SPI flash commands to initialize device */
3208+ ret = spi_nor_init(nor);
3209+ if (ret)
3210+ return ret;
3211+
3212+ dev_info(dev, "%s (%lld Kbytes)\n", info->name,
3213+ (long long)mtd->size >> 10);
3214+
3215+ dev_dbg(dev,
3216+ "mtd .name = %s, .size = 0x%llx (%lldMiB), "
3217+ ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
3218+ mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
3219+ mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
3220+
3221+ if (mtd->numeraseregions)
3222+ for (i = 0; i < mtd->numeraseregions; i++)
3223+ dev_dbg(dev,
3224+ "mtd.eraseregions[%d] = { .offset = 0x%llx, "
3225+ ".erasesize = 0x%.8x (%uKiB), "
3226+ ".numblocks = %d }\n",
3227+ i, (long long)mtd->eraseregions[i].offset,
3228+ mtd->eraseregions[i].erasesize,
3229+ mtd->eraseregions[i].erasesize / 1024,
3230+ mtd->eraseregions[i].numblocks);
3231+ return 0;
3232+}
3233+EXPORT_SYMBOL_GPL(spi_nor_scan);
3234+
3235+static int spi_nor_create_read_dirmap(struct spi_nor *nor)
3236+{
3237+ struct spi_mem_dirmap_info info = {
3238+ .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
3239+ SPI_MEM_OP_ADDR(nor->addr_width, 0, 1),
3240+ SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
3241+ SPI_MEM_OP_DATA_IN(0, NULL, 1)),
3242+ .offset = 0,
3243+ .length = nor->mtd.size,
3244+ };
3245+ struct spi_mem_op *op = &info.op_tmpl;
3246+
3247+ /* get transfer protocols. */
3248+ op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
3249+ op->addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
3250+ op->dummy.buswidth = op->addr.buswidth;
3251+ op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
3252+
3253+ /* convert the dummy cycles to the number of bytes */
3254+ op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8;
3255+
3256+ nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3257+ &info);
3258+ return PTR_ERR_OR_ZERO(nor->dirmap.rdesc);
3259+}
3260+
3261+static int spi_nor_create_write_dirmap(struct spi_nor *nor)
3262+{
3263+ struct spi_mem_dirmap_info info = {
3264+ .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
3265+ SPI_MEM_OP_ADDR(nor->addr_width, 0, 1),
3266+ SPI_MEM_OP_NO_DUMMY,
3267+ SPI_MEM_OP_DATA_OUT(0, NULL, 1)),
3268+ .offset = 0,
3269+ .length = nor->mtd.size,
3270+ };
3271+ struct spi_mem_op *op = &info.op_tmpl;
3272+
3273+ /* get transfer protocols. */
3274+ op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
3275+ op->addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
3276+ op->dummy.buswidth = op->addr.buswidth;
3277+ op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
3278+
3279+ if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
3280+ op->addr.nbytes = 0;
3281+
3282+ nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3283+ &info);
3284+ return PTR_ERR_OR_ZERO(nor->dirmap.wdesc);
3285+}
3286+
3287+static int spi_nor_probe(struct spi_mem *spimem)
3288+{
3289+ struct spi_device *spi = spimem->spi;
3290+ struct flash_platform_data *data = dev_get_platdata(&spi->dev);
3291+ struct spi_nor *nor;
3292+ /*
3293+ * Enable all caps by default. The core will mask them after
3294+ * checking what's really supported using spi_mem_supports_op().
3295+ */
3296+ const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL };
3297+ char *flash_name;
3298+ int ret;
3299+
3300+ nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL);
3301+ if (!nor)
3302+ return -ENOMEM;
3303+
3304+ nor->spimem = spimem;
3305+ nor->dev = &spi->dev;
3306+ spi_nor_set_flash_node(nor, spi->dev.of_node);
3307+
3308+ spi_mem_set_drvdata(spimem, nor);
3309+
3310+ if (data && data->name)
3311+ nor->mtd.name = data->name;
3312+
3313+ if (!nor->mtd.name)
3314+ nor->mtd.name = spi_mem_get_name(spimem);
3315+
3316+ /*
3317+ * For some (historical?) reason many platforms provide two different
3318+ * names in flash_platform_data: "name" and "type". Quite often name is
3319+ * set to "m25p80" and then "type" provides a real chip name.
3320+ * If that's the case, respect "type" and ignore a "name".
3321+ */
3322+ if (data && data->type)
3323+ flash_name = data->type;
3324+ else if (!strcmp(spi->modalias, "spi-nor"))
3325+ flash_name = NULL; /* auto-detect */
3326+ else
3327+ flash_name = spi->modalias;
3328+
3329+ ret = spi_nor_scan(nor, flash_name, &hwcaps);
3330+ if (ret)
3331+ return ret;
3332+
3333+ /*
3334+ * None of the existing parts have > 512B pages, but let's play safe
3335+ * and add this logic so that if anyone ever adds support for such
3336+ * a NOR we don't end up with buffer overflows.
3337+ */
3338+ if (nor->page_size > PAGE_SIZE) {
3339+ nor->bouncebuf_size = nor->page_size;
3340+ devm_kfree(nor->dev, nor->bouncebuf);
3341+ nor->bouncebuf = devm_kmalloc(nor->dev,
3342+ nor->bouncebuf_size,
3343+ GFP_KERNEL);
3344+ if (!nor->bouncebuf)
3345+ return -ENOMEM;
3346+ }
3347+
3348+ ret = spi_nor_create_read_dirmap(nor);
3349+ if (ret)
3350+ return ret;
3351+
3352+ ret = spi_nor_create_write_dirmap(nor);
3353+ if (ret)
3354+ return ret;
3355+
3356+ return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
3357+ data ? data->nr_parts : 0);
3358+}
3359+
3360+static int spi_nor_remove(struct spi_mem *spimem)
3361+{
3362+ struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3363+
3364+ spi_nor_restore(nor);
3365+
3366+ /* Clean up MTD stuff. */
3367+ return mtd_device_unregister(&nor->mtd);
3368+}
3369+
3370+static void spi_nor_shutdown(struct spi_mem *spimem)
3371+{
3372+ struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3373+
3374+ spi_nor_restore(nor);
3375+}
3376+
3377+/*
3378+ * Do NOT add to this array without reading the following:
3379+ *
3380+ * Historically, many flash devices are bound to this driver by their name. But
3381+ * since most of these flash are compatible to some extent, and their
3382+ * differences can often be differentiated by the JEDEC read-ID command, we
3383+ * encourage new users to add support to the spi-nor library, and simply bind
3384+ * against a generic string here (e.g., "jedec,spi-nor").
3385+ *
3386+ * Many flash names are kept here in this list (as well as in spi-nor.c) to
3387+ * keep them available as module aliases for existing platforms.
3388+ */
3389+static const struct spi_device_id spi_nor_dev_ids[] = {
3390+ /*
3391+ * Allow non-DT platform devices to bind to the "spi-nor" modalias, and
3392+ * hack around the fact that the SPI core does not provide uevent
3393+ * matching for .of_match_table
3394+ */
3395+ {"spi-nor"},
3396+
3397+ /*
3398+ * Entries not used in DTs that should be safe to drop after replacing
3399+ * them with "spi-nor" in platform data.
3400+ */
3401+ {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"},
3402+
3403+ /*
3404+ * Entries that were used in DTs without "jedec,spi-nor" fallback and
3405+ * should be kept for backward compatibility.
3406+ */
3407+ {"at25df321a"}, {"at25df641"}, {"at26df081a"},
3408+ {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},
3409+ {"mx25l25635e"},{"mx66l51235l"},
3410+ {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},
3411+ {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"},
3412+ {"s25fl064k"},
3413+ {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
3414+ {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"},
3415+ {"m25p64"}, {"m25p128"},
3416+ {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
3417+ {"w25q80bl"}, {"w25q128"}, {"w25q256"},
3418+
3419+ /* Flashes that can't be detected using JEDEC */
3420+ {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
3421+ {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
3422+ {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
3423+
3424+ /* Everspin MRAMs (non-JEDEC) */
3425+ { "mr25h128" }, /* 128 Kib, 40 MHz */
3426+ { "mr25h256" }, /* 256 Kib, 40 MHz */
3427+ { "mr25h10" }, /* 1 Mib, 40 MHz */
3428+ { "mr25h40" }, /* 4 Mib, 40 MHz */
3429+
3430+ { },
3431+};
3432+MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids);
3433+
3434+static const struct of_device_id spi_nor_of_table[] = {
3435+ /*
3436+ * Generic compatibility for SPI NOR that can be identified by the
3437+ * JEDEC READ ID opcode (0x9F). Use this, if possible.
3438+ */
3439+ { .compatible = "jedec,spi-nor" },
3440+ { /* sentinel */ },
3441+};
3442+MODULE_DEVICE_TABLE(of, spi_nor_of_table);
3443+
3444+/*
3445+ * REVISIT: many of these chips have deep power-down modes, which
3446+ * should clearly be entered on suspend() to minimize power use.
3447+ * And also when they're otherwise idle...
3448+ */
3449+static struct spi_mem_driver spi_nor_driver = {
3450+ .spidrv = {
3451+ .driver = {
3452+ .name = "spi-nor",
3453+ .of_match_table = spi_nor_of_table,
3454+ },
3455+ .id_table = spi_nor_dev_ids,
3456+ },
3457+ .probe = spi_nor_probe,
3458+ .remove = spi_nor_remove,
3459+ .shutdown = spi_nor_shutdown,
3460+};
3461+module_spi_mem_driver(spi_nor_driver);
3462+
3463+MODULE_LICENSE("GPL v2");
3464+MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
3465+MODULE_AUTHOR("Mike Lavender");
3466+MODULE_DESCRIPTION("framework for SPI NOR");
drivers/mtd/spi-nor/core.h+441−0
@@ -0,0 +1,441 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#ifndef __LINUX_MTD_SPI_NOR_INTERNAL_H
8+#define __LINUX_MTD_SPI_NOR_INTERNAL_H
9+
10+#include "sfdp.h"
11+
12+#define SPI_NOR_MAX_ID_LEN 6
13+
14+enum spi_nor_option_flags {
15+ SNOR_F_USE_FSR = BIT(0),
16+ SNOR_F_HAS_SR_TB = BIT(1),
17+ SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
18+ SNOR_F_READY_XSR_RDY = BIT(3),
19+ SNOR_F_USE_CLSR = BIT(4),
20+ SNOR_F_BROKEN_RESET = BIT(5),
21+ SNOR_F_4B_OPCODES = BIT(6),
22+ SNOR_F_HAS_4BAIT = BIT(7),
23+ SNOR_F_HAS_LOCK = BIT(8),
24+ SNOR_F_HAS_16BIT_SR = BIT(9),
25+ SNOR_F_NO_READ_CR = BIT(10),
26+ SNOR_F_HAS_SR_TB_BIT6 = BIT(11),
27+ SNOR_F_HAS_4BIT_BP = BIT(12),
28+ SNOR_F_HAS_SR_BP3_BIT6 = BIT(13),
29+};
30+
31+struct spi_nor_read_command {
32+ u8 num_mode_clocks;
33+ u8 num_wait_states;
34+ u8 opcode;
35+ enum spi_nor_protocol proto;
36+};
37+
38+struct spi_nor_pp_command {
39+ u8 opcode;
40+ enum spi_nor_protocol proto;
41+};
42+
43+enum spi_nor_read_command_index {
44+ SNOR_CMD_READ,
45+ SNOR_CMD_READ_FAST,
46+ SNOR_CMD_READ_1_1_1_DTR,
47+
48+ /* Dual SPI */
49+ SNOR_CMD_READ_1_1_2,
50+ SNOR_CMD_READ_1_2_2,
51+ SNOR_CMD_READ_2_2_2,
52+ SNOR_CMD_READ_1_2_2_DTR,
53+
54+ /* Quad SPI */
55+ SNOR_CMD_READ_1_1_4,
56+ SNOR_CMD_READ_1_4_4,
57+ SNOR_CMD_READ_4_4_4,
58+ SNOR_CMD_READ_1_4_4_DTR,
59+
60+ /* Octal SPI */
61+ SNOR_CMD_READ_1_1_8,
62+ SNOR_CMD_READ_1_8_8,
63+ SNOR_CMD_READ_8_8_8,
64+ SNOR_CMD_READ_1_8_8_DTR,
65+
66+ SNOR_CMD_READ_MAX
67+};
68+
69+enum spi_nor_pp_command_index {
70+ SNOR_CMD_PP,
71+
72+ /* Quad SPI */
73+ SNOR_CMD_PP_1_1_4,
74+ SNOR_CMD_PP_1_4_4,
75+ SNOR_CMD_PP_4_4_4,
76+
77+ /* Octal SPI */
78+ SNOR_CMD_PP_1_1_8,
79+ SNOR_CMD_PP_1_8_8,
80+ SNOR_CMD_PP_8_8_8,
81+
82+ SNOR_CMD_PP_MAX
83+};
84+
85+/**
86+ * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
87+ * @size: the size of the sector/block erased by the erase type.
88+ * JEDEC JESD216B imposes erase sizes to be a power of 2.
89+ * @size_shift: @size is a power of 2, the shift is stored in
90+ * @size_shift.
91+ * @size_mask: the size mask based on @size_shift.
92+ * @opcode: the SPI command op code to erase the sector/block.
93+ * @idx: Erase Type index as sorted in the Basic Flash Parameter
94+ * Table. It will be used to synchronize the supported
95+ * Erase Types with the ones identified in the SFDP
96+ * optional tables.
97+ */
98+struct spi_nor_erase_type {
99+ u32 size;
100+ u32 size_shift;
101+ u32 size_mask;
102+ u8 opcode;
103+ u8 idx;
104+};
105+
106+/**
107+ * struct spi_nor_erase_command - Used for non-uniform erases
108+ * The structure is used to describe a list of erase commands to be executed
109+ * once we validate that the erase can be performed. The elements in the list
110+ * are run-length encoded.
111+ * @list: for inclusion into the list of erase commands.
112+ * @count: how many times the same erase command should be
113+ * consecutively used.
114+ * @size: the size of the sector/block erased by the command.
115+ * @opcode: the SPI command op code to erase the sector/block.
116+ */
117+struct spi_nor_erase_command {
118+ struct list_head list;
119+ u32 count;
120+ u32 size;
121+ u8 opcode;
122+};
123+
124+/**
125+ * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region
126+ * @offset: the offset in the data array of erase region start.
127+ * LSB bits are used as a bitmask encoding flags to
128+ * determine if this region is overlaid, if this region is
129+ * the last in the SPI NOR flash memory and to indicate
130+ * all the supported erase commands inside this region.
131+ * The erase types are sorted in ascending order with the
132+ * smallest Erase Type size being at BIT(0).
133+ * @size: the size of the region in bytes.
134+ */
135+struct spi_nor_erase_region {
136+ u64 offset;
137+ u64 size;
138+};
139+
140+#define SNOR_ERASE_TYPE_MAX 4
141+#define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0)
142+
143+#define SNOR_LAST_REGION BIT(4)
144+#define SNOR_OVERLAID_REGION BIT(5)
145+
146+#define SNOR_ERASE_FLAGS_MAX 6
147+#define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0)
148+
149+/**
150+ * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map
151+ * @regions: array of erase regions. The regions are consecutive in
152+ * address space. Walking through the regions is done
153+ * incrementally.
154+ * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform
155+ * sector size (legacy implementation).
156+ * @erase_type: an array of erase types shared by all the regions.
157+ * The erase types are sorted in ascending order, with the
158+ * smallest Erase Type size being the first member in the
159+ * erase_type array.
160+ * @uniform_erase_type: bitmask encoding erase types that can erase the
161+ * entire memory. This member is completed at init by
162+ * uniform and non-uniform SPI NOR flash memories if they
163+ * support at least one erase type that can erase the
164+ * entire memory.
165+ */
166+struct spi_nor_erase_map {
167+ struct spi_nor_erase_region *regions;
168+ struct spi_nor_erase_region uniform_region;
169+ struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX];
170+ u8 uniform_erase_type;
171+};
172+
173+/**
174+ * struct spi_nor_locking_ops - SPI NOR locking methods
175+ * @lock: lock a region of the SPI NOR.
176+ * @unlock: unlock a region of the SPI NOR.
177+ * @is_locked: check if a region of the SPI NOR is completely locked
178+ */
179+struct spi_nor_locking_ops {
180+ int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
181+ int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
182+ int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
183+};
184+
185+/**
186+ * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings.
187+ * Includes legacy flash parameters and settings that can be overwritten
188+ * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216
189+ * Serial Flash Discoverable Parameters (SFDP) tables.
190+ *
191+ * @size: the flash memory density in bytes.
192+ * @page_size: the page size of the SPI NOR flash memory.
193+ * @hwcaps: describes the read and page program hardware
194+ * capabilities.
195+ * @reads: read capabilities ordered by priority: the higher index
196+ * in the array, the higher priority.
197+ * @page_programs: page program capabilities ordered by priority: the
198+ * higher index in the array, the higher priority.
199+ * @erase_map: the erase map parsed from the SFDP Sector Map Parameter
200+ * Table.
201+ * @quad_enable: enables SPI NOR quad mode.
202+ * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
203+ * @convert_addr: converts an absolute address into something the flash
204+ * will understand. Particularly useful when pagesize is
205+ * not a power-of-2.
206+ * @setup: configures the SPI NOR memory. Useful for SPI NOR
207+ * flashes that have peculiarities to the SPI NOR standard
208+ * e.g. different opcodes, specific address calculation,
209+ * page size, etc.
210+ * @locking_ops: SPI NOR locking methods.
211+ */
212+struct spi_nor_flash_parameter {
213+ u64 size;
214+ u32 page_size;
215+
216+ struct spi_nor_hwcaps hwcaps;
217+ struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
218+ struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
219+
220+ struct spi_nor_erase_map erase_map;
221+
222+ int (*quad_enable)(struct spi_nor *nor);
223+ int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
224+ u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
225+ int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
226+
227+ const struct spi_nor_locking_ops *locking_ops;
228+};
229+
230+/**
231+ * struct spi_nor_fixups - SPI NOR fixup hooks
232+ * @default_init: called after default flash parameters init. Used to tweak
233+ * flash parameters when information provided by the flash_info
234+ * table is incomplete or wrong.
235+ * @post_bfpt: called after the BFPT table has been parsed
236+ * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
237+ * that do not support RDSFDP). Typically used to tweak various
238+ * parameters that could not be extracted by other means (i.e.
239+ * when information provided by the SFDP/flash_info tables are
240+ * incomplete or wrong).
241+ *
242+ * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
243+ * table is broken or not available.
244+ */
245+struct spi_nor_fixups {
246+ void (*default_init)(struct spi_nor *nor);
247+ int (*post_bfpt)(struct spi_nor *nor,
248+ const struct sfdp_parameter_header *bfpt_header,
249+ const struct sfdp_bfpt *bfpt,
250+ struct spi_nor_flash_parameter *params);
251+ void (*post_sfdp)(struct spi_nor *nor);
252+};
253+
254+struct flash_info {
255+ char *name;
256+
257+ /*
258+ * This array stores the ID bytes.
259+ * The first three bytes are the JEDIC ID.
260+ * JEDEC ID zero means "no ID" (mostly older chips).
261+ */
262+ u8 id[SPI_NOR_MAX_ID_LEN];
263+ u8 id_len;
264+
265+ /* The size listed here is what works with SPINOR_OP_SE, which isn't
266+ * necessarily called a "sector" by the vendor.
267+ */
268+ unsigned sector_size;
269+ u16 n_sectors;
270+
271+ u16 page_size;
272+ u16 addr_width;
273+
274+ u32 flags;
275+#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
276+#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
277+#define SST_WRITE BIT(2) /* use SST byte programming */
278+#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
279+#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
280+#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
281+#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
282+#define USE_FSR BIT(7) /* use flag status register */
283+#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
284+#define SPI_NOR_HAS_TB BIT(9) /*
285+ * Flash SR has Top/Bottom (TB) protect
286+ * bit. Must be used with
287+ * SPI_NOR_HAS_LOCK.
288+ */
289+#define SPI_NOR_XSR_RDY BIT(10) /*
290+ * S3AN flashes have specific opcode to
291+ * read the status register.
292+ */
293+#define SPI_NOR_4B_OPCODES BIT(11) /*
294+ * Use dedicated 4byte address op codes
295+ * to support memory size above 128Mib.
296+ */
297+#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
298+#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
299+#define USE_CLSR BIT(14) /* use CLSR command */
300+#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
301+#define SPI_NOR_TB_SR_BIT6 BIT(16) /*
302+ * Top/Bottom (TB) is bit 6 of
303+ * status register. Must be used with
304+ * SPI_NOR_HAS_TB.
305+ */
306+#define SPI_NOR_4BIT_BP BIT(17) /*
307+ * Flash SR has 4 bit fields (BP0-3)
308+ * for block protection.
309+ */
310+#define SPI_NOR_BP3_SR_BIT6 BIT(18) /*
311+ * BP3 is bit 6 of status register.
312+ * Must be used with SPI_NOR_4BIT_BP.
313+ */
314+
315+ /* Part specific fixup hooks. */
316+ const struct spi_nor_fixups *fixups;
317+};
318+
319+/* Used when the "_ext_id" is two bytes at most */
320+#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
321+ .id = { \
322+ ((_jedec_id) >> 16) & 0xff, \
323+ ((_jedec_id) >> 8) & 0xff, \
324+ (_jedec_id) & 0xff, \
325+ ((_ext_id) >> 8) & 0xff, \
326+ (_ext_id) & 0xff, \
327+ }, \
328+ .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
329+ .sector_size = (_sector_size), \
330+ .n_sectors = (_n_sectors), \
331+ .page_size = 256, \
332+ .flags = (_flags),
333+
334+#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
335+ .id = { \
336+ ((_jedec_id) >> 16) & 0xff, \
337+ ((_jedec_id) >> 8) & 0xff, \
338+ (_jedec_id) & 0xff, \
339+ ((_ext_id) >> 16) & 0xff, \
340+ ((_ext_id) >> 8) & 0xff, \
341+ (_ext_id) & 0xff, \
342+ }, \
343+ .id_len = 6, \
344+ .sector_size = (_sector_size), \
345+ .n_sectors = (_n_sectors), \
346+ .page_size = 256, \
347+ .flags = (_flags),
348+
349+#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
350+ .sector_size = (_sector_size), \
351+ .n_sectors = (_n_sectors), \
352+ .page_size = (_page_size), \
353+ .addr_width = (_addr_width), \
354+ .flags = (_flags),
355+
356+#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
357+ .id = { \
358+ ((_jedec_id) >> 16) & 0xff, \
359+ ((_jedec_id) >> 8) & 0xff, \
360+ (_jedec_id) & 0xff \
361+ }, \
362+ .id_len = 3, \
363+ .sector_size = (8*_page_size), \
364+ .n_sectors = (_n_sectors), \
365+ .page_size = _page_size, \
366+ .addr_width = 3, \
367+ .flags = SPI_NOR_NO_FR | SPI_NOR_XSR_RDY,
368+
369+/**
370+ * struct spi_nor_manufacturer - SPI NOR manufacturer object
371+ * @name: manufacturer name
372+ * @parts: array of parts supported by this manufacturer
373+ * @nparts: number of entries in the parts array
374+ * @fixups: hooks called at various points in time during spi_nor_scan()
375+ */
376+struct spi_nor_manufacturer {
377+ const char *name;
378+ const struct flash_info *parts;
379+ unsigned int nparts;
380+ const struct spi_nor_fixups *fixups;
381+};
382+
383+/* Manufacturer drivers. */
384+extern const struct spi_nor_manufacturer spi_nor_atmel;
385+extern const struct spi_nor_manufacturer spi_nor_catalyst;
386+extern const struct spi_nor_manufacturer spi_nor_eon;
387+extern const struct spi_nor_manufacturer spi_nor_esmt;
388+extern const struct spi_nor_manufacturer spi_nor_everspin;
389+extern const struct spi_nor_manufacturer spi_nor_fujitsu;
390+extern const struct spi_nor_manufacturer spi_nor_gigadevice;
391+extern const struct spi_nor_manufacturer spi_nor_intel;
392+extern const struct spi_nor_manufacturer spi_nor_issi;
393+extern const struct spi_nor_manufacturer spi_nor_macronix;
394+extern const struct spi_nor_manufacturer spi_nor_micron;
395+extern const struct spi_nor_manufacturer spi_nor_st;
396+extern const struct spi_nor_manufacturer spi_nor_spansion;
397+extern const struct spi_nor_manufacturer spi_nor_sst;
398+extern const struct spi_nor_manufacturer spi_nor_winbond;
399+extern const struct spi_nor_manufacturer spi_nor_xilinx;
400+extern const struct spi_nor_manufacturer spi_nor_xmc;
401+
402+int spi_nor_write_enable(struct spi_nor *nor);
403+int spi_nor_write_disable(struct spi_nor *nor);
404+int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable);
405+int spi_nor_write_ear(struct spi_nor *nor, u8 ear);
406+int spi_nor_wait_till_ready(struct spi_nor *nor);
407+int spi_nor_lock_and_prep(struct spi_nor *nor);
408+void spi_nor_unlock_and_unprep(struct spi_nor *nor);
409+int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);
410+int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
411+int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
412+
413+int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr);
414+ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
415+ u8 *buf);
416+ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
417+ const u8 *buf);
418+
419+int spi_nor_hwcaps_read2cmd(u32 hwcaps);
420+u8 spi_nor_convert_3to4_read(u8 opcode);
421+void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
422+ enum spi_nor_protocol proto);
423+
424+void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
425+ u8 opcode);
426+struct spi_nor_erase_region *
427+spi_nor_region_next(struct spi_nor_erase_region *region);
428+void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
429+ u8 erase_mask, u64 flash_size);
430+
431+int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
432+ const struct sfdp_parameter_header *bfpt_header,
433+ const struct sfdp_bfpt *bfpt,
434+ struct spi_nor_flash_parameter *params);
435+
436+static struct spi_nor __maybe_unused *mtd_to_spi_nor(struct mtd_info *mtd)
437+{
438+ return mtd->priv;
439+}
440+
441+#endif /* __LINUX_MTD_SPI_NOR_INTERNAL_H */
drivers/mtd/spi-nor/eon.c+34−0
@@ -0,0 +1,34 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static const struct flash_info eon_parts[] = {
12+ /* EON -- en25xxx */
13+ { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
14+ { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
15+ { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
16+ { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
17+ { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
18+ { "en25q80a", INFO(0x1c3014, 0, 64 * 1024, 16,
19+ SECT_4K | SPI_NOR_DUAL_READ) },
20+ { "en25qh16", INFO(0x1c7015, 0, 64 * 1024, 32,
21+ SECT_4K | SPI_NOR_DUAL_READ) },
22+ { "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) },
23+ { "en25qh64", INFO(0x1c7017, 0, 64 * 1024, 128,
24+ SECT_4K | SPI_NOR_DUAL_READ) },
25+ { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
26+ { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
27+ { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
28+};
29+
30+const struct spi_nor_manufacturer spi_nor_eon = {
31+ .name = "eon",
32+ .parts = eon_parts,
33+ .nparts = ARRAY_SIZE(eon_parts),
34+};
drivers/mtd/spi-nor/esmt.c+25−0
@@ -0,0 +1,25 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static const struct flash_info esmt_parts[] = {
12+ /* ESMT */
13+ { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64,
14+ SECT_4K | SPI_NOR_HAS_LOCK) },
15+ { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64,
16+ SECT_4K | SPI_NOR_HAS_LOCK) },
17+ { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128,
18+ SECT_4K | SPI_NOR_HAS_LOCK) },
19+};
20+
21+const struct spi_nor_manufacturer spi_nor_esmt = {
22+ .name = "esmt",
23+ .parts = esmt_parts,
24+ .nparts = ARRAY_SIZE(esmt_parts),
25+};
drivers/mtd/spi-nor/everspin.c+27−0
@@ -0,0 +1,27 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static const struct flash_info everspin_parts[] = {
12+ /* Everspin */
13+ { "mr25h128", CAT25_INFO(16 * 1024, 1, 256, 2,
14+ SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
15+ { "mr25h256", CAT25_INFO(32 * 1024, 1, 256, 2,
16+ SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
17+ { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3,
18+ SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
19+ { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3,
20+ SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
21+};
22+
23+const struct spi_nor_manufacturer spi_nor_everspin = {
24+ .name = "everspin",
25+ .parts = everspin_parts,
26+ .nparts = ARRAY_SIZE(everspin_parts),
27+};
drivers/mtd/spi-nor/fujitsu.c+20−0
@@ -0,0 +1,20 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static const struct flash_info fujitsu_parts[] = {
12+ /* Fujitsu */
13+ { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
14+};
15+
16+const struct spi_nor_manufacturer spi_nor_fujitsu = {
17+ .name = "fujitsu",
18+ .parts = fujitsu_parts,
19+ .nparts = ARRAY_SIZE(fujitsu_parts),
20+};
drivers/mtd/spi-nor/gigadevice.c+59−0
@@ -0,0 +1,59 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static void gd25q256_default_init(struct spi_nor *nor)
12+{
13+ /*
14+ * Some manufacturer like GigaDevice may use different
15+ * bit to set QE on different memories, so the MFR can't
16+ * indicate the quad_enable method for this case, we need
17+ * to set it in the default_init fixup hook.
18+ */
19+ nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
20+}
21+
22+static struct spi_nor_fixups gd25q256_fixups = {
23+ .default_init = gd25q256_default_init,
24+};
25+
26+static const struct flash_info gigadevice_parts[] = {
27+ { "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
28+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
29+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
30+ { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
31+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
32+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
33+ { "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
34+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
35+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
36+ { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
37+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
38+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
39+ { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
40+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
41+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
42+ { "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256,
43+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
44+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
45+ { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
46+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
47+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
48+ { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
49+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
50+ SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
51+ SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
52+ .fixups = &gd25q256_fixups },
53+};
54+
55+const struct spi_nor_manufacturer spi_nor_gigadevice = {
56+ .name = "gigadevice",
57+ .parts = gigadevice_parts,
58+ .nparts = ARRAY_SIZE(gigadevice_parts),
59+};
drivers/mtd/spi-nor/intel.c+32−0
@@ -0,0 +1,32 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static const struct flash_info intel_parts[] = {
12+ /* Intel/Numonyx -- xxxs33b */
13+ { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
14+ { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
15+ { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
16+};
17+
18+static void intel_default_init(struct spi_nor *nor)
19+{
20+ nor->flags |= SNOR_F_HAS_LOCK;
21+}
22+
23+static const struct spi_nor_fixups intel_fixups = {
24+ .default_init = intel_default_init,
25+};
26+
27+const struct spi_nor_manufacturer spi_nor_intel = {
28+ .name = "intel",
29+ .parts = intel_parts,
30+ .nparts = ARRAY_SIZE(intel_parts),
31+ .fixups = &intel_fixups,
32+};
drivers/mtd/spi-nor/issi.c+83−0
@@ -0,0 +1,83 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static int
12+is25lp256_post_bfpt_fixups(struct spi_nor *nor,
13+ const struct sfdp_parameter_header *bfpt_header,
14+ const struct sfdp_bfpt *bfpt,
15+ struct spi_nor_flash_parameter *params)
16+{
17+ /*
18+ * IS25LP256 supports 4B opcodes, but the BFPT advertises a
19+ * BFPT_DWORD1_ADDRESS_BYTES_3_ONLY address width.
20+ * Overwrite the address width advertised by the BFPT.
21+ */
22+ if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==
23+ BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)
24+ nor->addr_width = 4;
25+
26+ return 0;
27+}
28+
29+static struct spi_nor_fixups is25lp256_fixups = {
30+ .post_bfpt = is25lp256_post_bfpt_fixups,
31+};
32+
33+static const struct flash_info issi_parts[] = {
34+ /* ISSI */
35+ { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
36+ { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
37+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
38+ { "is25lp016d", INFO(0x9d6015, 0, 64 * 1024, 32,
39+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
40+ { "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16,
41+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
42+ { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64,
43+ SECT_4K | SPI_NOR_DUAL_READ) },
44+ { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128,
45+ SECT_4K | SPI_NOR_DUAL_READ) },
46+ { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
47+ SECT_4K | SPI_NOR_DUAL_READ) },
48+ { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
49+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
50+ SPI_NOR_4B_OPCODES)
51+ .fixups = &is25lp256_fixups },
52+ { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
53+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
54+ { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
55+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
56+ { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
57+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
58+ { "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512,
59+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
60+ SPI_NOR_4B_OPCODES)
61+ .fixups = &is25lp256_fixups },
62+
63+ /* PMC */
64+ { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
65+ { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
66+ { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
67+};
68+
69+static void issi_default_init(struct spi_nor *nor)
70+{
71+ nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
72+}
73+
74+static const struct spi_nor_fixups issi_fixups = {
75+ .default_init = issi_default_init,
76+};
77+
78+const struct spi_nor_manufacturer spi_nor_issi = {
79+ .name = "issi",
80+ .parts = issi_parts,
81+ .nparts = ARRAY_SIZE(issi_parts),
82+ .fixups = &issi_fixups,
83+};
drivers/mtd/spi-nor/macronix.c+98−0
@@ -0,0 +1,98 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static int
12+mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
13+ const struct sfdp_parameter_header *bfpt_header,
14+ const struct sfdp_bfpt *bfpt,
15+ struct spi_nor_flash_parameter *params)
16+{
17+ /*
18+ * MX25L25635F supports 4B opcodes but MX25L25635E does not.
19+ * Unfortunately, Macronix has re-used the same JEDEC ID for both
20+ * variants which prevents us from defining a new entry in the parts
21+ * table.
22+ * We need a way to differentiate MX25L25635E and MX25L25635F, and it
23+ * seems that the F version advertises support for Fast Read 4-4-4 in
24+ * its BFPT table.
25+ */
26+ if (bfpt->dwords[BFPT_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4)
27+ nor->flags |= SNOR_F_4B_OPCODES;
28+
29+ return 0;
30+}
31+
32+static struct spi_nor_fixups mx25l25635_fixups = {
33+ .post_bfpt = mx25l25635_post_bfpt_fixups,
34+};
35+
36+static const struct flash_info macronix_parts[] = {
37+ /* Macronix */
38+ { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
39+ { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
40+ { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
41+ { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
42+ { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
43+ { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
44+ { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
45+ { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
46+ { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
47+ { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64,
48+ SECT_4K | SPI_NOR_DUAL_READ |
49+ SPI_NOR_QUAD_READ) },
50+ { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
51+ { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
52+ { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
53+ { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
54+ { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
55+ { "mx25r3235f", INFO(0xc22816, 0, 64 * 1024, 64,
56+ SECT_4K | SPI_NOR_DUAL_READ |
57+ SPI_NOR_QUAD_READ) },
58+ { "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
59+ SECT_4K | SPI_NOR_DUAL_READ |
60+ SPI_NOR_QUAD_READ) },
61+ { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
62+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
63+ .fixups = &mx25l25635_fixups },
64+ { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512,
65+ SECT_4K | SPI_NOR_4B_OPCODES) },
66+ { "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16,
67+ SECT_4K | SPI_NOR_DUAL_READ |
68+ SPI_NOR_QUAD_READ) },
69+ { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
70+ { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024,
71+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
72+ SPI_NOR_4B_OPCODES) },
73+ { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024,
74+ SECT_4K | SPI_NOR_DUAL_READ |
75+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
76+ { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048,
77+ SECT_4K | SPI_NOR_DUAL_READ |
78+ SPI_NOR_QUAD_READ) },
79+ { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048,
80+ SPI_NOR_QUAD_READ) },
81+};
82+
83+static void macronix_default_init(struct spi_nor *nor)
84+{
85+ nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
86+ nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
87+}
88+
89+static const struct spi_nor_fixups macronix_fixups = {
90+ .default_init = macronix_default_init,
91+};
92+
93+const struct spi_nor_manufacturer spi_nor_macronix = {
94+ .name = "macronix",
95+ .parts = macronix_parts,
96+ .nparts = ARRAY_SIZE(macronix_parts),
97+ .fixups = &macronix_fixups,
98+};
drivers/mtd/spi-nor/micron-st.c+157−0
@@ -0,0 +1,157 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static const struct flash_info micron_parts[] = {
12+ { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
13+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
14+ SPI_NOR_4B_OPCODES) },
15+ { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048,
16+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
17+ SPI_NOR_4B_OPCODES) },
18+};
19+
20+static const struct flash_info st_parts[] = {
21+ { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32,
22+ SECT_4K | SPI_NOR_QUAD_READ) },
23+ { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64,
24+ SPI_NOR_QUAD_READ) },
25+ { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64,
26+ SPI_NOR_QUAD_READ) },
27+ { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128,
28+ SECT_4K | SPI_NOR_QUAD_READ) },
29+ { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128,
30+ SECT_4K | SPI_NOR_QUAD_READ) },
31+ { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256,
32+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
33+ { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256,
34+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
35+ { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
36+ SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
37+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
38+ { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
39+ USE_FSR | SPI_NOR_DUAL_READ |
40+ SPI_NOR_QUAD_READ) },
41+ { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512,
42+ SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
43+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
44+ { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512,
45+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
46+ { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
47+ SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
48+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
49+ { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024,
50+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
51+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
52+ SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
53+ { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
54+ SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
55+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
56+ { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024,
57+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
58+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
59+ SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
60+ { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048,
61+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
62+ NO_CHIP_ERASE) },
63+ { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048,
64+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
65+ NO_CHIP_ERASE) },
66+ { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
67+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
68+ NO_CHIP_ERASE) },
69+ { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096,
70+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
71+ NO_CHIP_ERASE) },
72+
73+ { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
74+ { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
75+ { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
76+ { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
77+ { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
78+ { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
79+ { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
80+ { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
81+ { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
82+
83+ { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
84+ { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
85+ { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
86+ { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
87+ { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
88+ { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
89+ { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
90+ { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
91+ { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
92+
93+ { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
94+ { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
95+ { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
96+
97+ { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
98+ { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
99+ { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
100+
101+ { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
102+ { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
103+ { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
104+ { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
105+ { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
106+ { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
107+};
108+
109+/**
110+ * st_micron_set_4byte_addr_mode() - Set 4-byte address mode for ST and Micron
111+ * flashes.
112+ * @nor: pointer to 'struct spi_nor'.
113+ * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
114+ * address mode.
115+ *
116+ * Return: 0 on success, -errno otherwise.
117+ */
118+static int st_micron_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
119+{
120+ int ret;
121+
122+ ret = spi_nor_write_enable(nor);
123+ if (ret)
124+ return ret;
125+
126+ ret = spi_nor_set_4byte_addr_mode(nor, enable);
127+ if (ret)
128+ return ret;
129+
130+ return spi_nor_write_disable(nor);
131+}
132+
133+static void micron_st_default_init(struct spi_nor *nor)
134+{
135+ nor->flags |= SNOR_F_HAS_LOCK;
136+ nor->flags &= ~SNOR_F_HAS_16BIT_SR;
137+ nor->params->quad_enable = NULL;
138+ nor->params->set_4byte_addr_mode = st_micron_set_4byte_addr_mode;
139+}
140+
141+static const struct spi_nor_fixups micron_st_fixups = {
142+ .default_init = micron_st_default_init,
143+};
144+
145+const struct spi_nor_manufacturer spi_nor_micron = {
146+ .name = "micron",
147+ .parts = micron_parts,
148+ .nparts = ARRAY_SIZE(micron_parts),
149+ .fixups = &micron_st_fixups,
150+};
151+
152+const struct spi_nor_manufacturer spi_nor_st = {
153+ .name = "st",
154+ .parts = st_parts,
155+ .nparts = ARRAY_SIZE(st_parts),
156+ .fixups = &micron_st_fixups,
157+};
drivers/mtd/spi-nor/sfdp.c+1204−0
@@ -0,0 +1,1204 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/slab.h>
8+#include <linux/sort.h>
9+#include <linux/mtd/spi-nor.h>
10+
11+#include "core.h"
12+
13+#define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
14+#define SFDP_PARAM_HEADER_PTP(p) \
15+ (((p)->parameter_table_pointer[2] << 16) | \
16+ ((p)->parameter_table_pointer[1] << 8) | \
17+ ((p)->parameter_table_pointer[0] << 0))
18+
19+#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
20+#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
21+#define SFDP_4BAIT_ID 0xff84 /* 4-byte Address Instruction Table */
22+
23+#define SFDP_SIGNATURE 0x50444653U
24+#define SFDP_JESD216_MAJOR 1
25+#define SFDP_JESD216_MINOR 0
26+#define SFDP_JESD216A_MINOR 5
27+#define SFDP_JESD216B_MINOR 6
28+
29+struct sfdp_header {
30+ u32 signature; /* Ox50444653U <=> "SFDP" */
31+ u8 minor;
32+ u8 major;
33+ u8 nph; /* 0-base number of parameter headers */
34+ u8 unused;
35+
36+ /* Basic Flash Parameter Table. */
37+ struct sfdp_parameter_header bfpt_header;
38+};
39+
40+/* Fast Read settings. */
41+struct sfdp_bfpt_read {
42+ /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
43+ u32 hwcaps;
44+
45+ /*
46+ * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
47+ * whether the Fast Read x-y-z command is supported.
48+ */
49+ u32 supported_dword;
50+ u32 supported_bit;
51+
52+ /*
53+ * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
54+ * encodes the op code, the number of mode clocks and the number of wait
55+ * states to be used by Fast Read x-y-z command.
56+ */
57+ u32 settings_dword;
58+ u32 settings_shift;
59+
60+ /* The SPI protocol for this Fast Read x-y-z command. */
61+ enum spi_nor_protocol proto;
62+};
63+
64+struct sfdp_bfpt_erase {
65+ /*
66+ * The half-word at offset <shift> in DWORD <dwoard> encodes the
67+ * op code and erase sector size to be used by Sector Erase commands.
68+ */
69+ u32 dword;
70+ u32 shift;
71+};
72+
73+#define SMPT_CMD_ADDRESS_LEN_MASK GENMASK(23, 22)
74+#define SMPT_CMD_ADDRESS_LEN_0 (0x0UL << 22)
75+#define SMPT_CMD_ADDRESS_LEN_3 (0x1UL << 22)
76+#define SMPT_CMD_ADDRESS_LEN_4 (0x2UL << 22)
77+#define SMPT_CMD_ADDRESS_LEN_USE_CURRENT (0x3UL << 22)
78+
79+#define SMPT_CMD_READ_DUMMY_MASK GENMASK(19, 16)
80+#define SMPT_CMD_READ_DUMMY_SHIFT 16
81+#define SMPT_CMD_READ_DUMMY(_cmd) \
82+ (((_cmd) & SMPT_CMD_READ_DUMMY_MASK) >> SMPT_CMD_READ_DUMMY_SHIFT)
83+#define SMPT_CMD_READ_DUMMY_IS_VARIABLE 0xfUL
84+
85+#define SMPT_CMD_READ_DATA_MASK GENMASK(31, 24)
86+#define SMPT_CMD_READ_DATA_SHIFT 24
87+#define SMPT_CMD_READ_DATA(_cmd) \
88+ (((_cmd) & SMPT_CMD_READ_DATA_MASK) >> SMPT_CMD_READ_DATA_SHIFT)
89+
90+#define SMPT_CMD_OPCODE_MASK GENMASK(15, 8)
91+#define SMPT_CMD_OPCODE_SHIFT 8
92+#define SMPT_CMD_OPCODE(_cmd) \
93+ (((_cmd) & SMPT_CMD_OPCODE_MASK) >> SMPT_CMD_OPCODE_SHIFT)
94+
95+#define SMPT_MAP_REGION_COUNT_MASK GENMASK(23, 16)
96+#define SMPT_MAP_REGION_COUNT_SHIFT 16
97+#define SMPT_MAP_REGION_COUNT(_header) \
98+ ((((_header) & SMPT_MAP_REGION_COUNT_MASK) >> \
99+ SMPT_MAP_REGION_COUNT_SHIFT) + 1)
100+
101+#define SMPT_MAP_ID_MASK GENMASK(15, 8)
102+#define SMPT_MAP_ID_SHIFT 8
103+#define SMPT_MAP_ID(_header) \
104+ (((_header) & SMPT_MAP_ID_MASK) >> SMPT_MAP_ID_SHIFT)
105+
106+#define SMPT_MAP_REGION_SIZE_MASK GENMASK(31, 8)
107+#define SMPT_MAP_REGION_SIZE_SHIFT 8
108+#define SMPT_MAP_REGION_SIZE(_region) \
109+ (((((_region) & SMPT_MAP_REGION_SIZE_MASK) >> \
110+ SMPT_MAP_REGION_SIZE_SHIFT) + 1) * 256)
111+
112+#define SMPT_MAP_REGION_ERASE_TYPE_MASK GENMASK(3, 0)
113+#define SMPT_MAP_REGION_ERASE_TYPE(_region) \
114+ ((_region) & SMPT_MAP_REGION_ERASE_TYPE_MASK)
115+
116+#define SMPT_DESC_TYPE_MAP BIT(1)
117+#define SMPT_DESC_END BIT(0)
118+
119+#define SFDP_4BAIT_DWORD_MAX 2
120+
121+struct sfdp_4bait {
122+ /* The hardware capability. */
123+ u32 hwcaps;
124+
125+ /*
126+ * The <supported_bit> bit in DWORD1 of the 4BAIT tells us whether
127+ * the associated 4-byte address op code is supported.
128+ */
129+ u32 supported_bit;
130+};
131+
132+/**
133+ * spi_nor_read_raw() - raw read of serial flash memory. read_opcode,
134+ * addr_width and read_dummy members of the struct spi_nor
135+ * should be previously
136+ * set.
137+ * @nor: pointer to a 'struct spi_nor'
138+ * @addr: offset in the serial flash memory
139+ * @len: number of bytes to read
140+ * @buf: buffer where the data is copied into (dma-safe memory)
141+ *
142+ * Return: 0 on success, -errno otherwise.
143+ */
144+static int spi_nor_read_raw(struct spi_nor *nor, u32 addr, size_t len, u8 *buf)
145+{
146+ ssize_t ret;
147+
148+ while (len) {
149+ ret = spi_nor_read_data(nor, addr, len, buf);
150+ if (ret < 0)
151+ return ret;
152+ if (!ret || ret > len)
153+ return -EIO;
154+
155+ buf += ret;
156+ addr += ret;
157+ len -= ret;
158+ }
159+ return 0;
160+}
161+
162+/**
163+ * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
164+ * @nor: pointer to a 'struct spi_nor'
165+ * @addr: offset in the SFDP area to start reading data from
166+ * @len: number of bytes to read
167+ * @buf: buffer where the SFDP data are copied into (dma-safe memory)
168+ *
169+ * Whatever the actual numbers of bytes for address and dummy cycles are
170+ * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
171+ * followed by a 3-byte address and 8 dummy clock cycles.
172+ *
173+ * Return: 0 on success, -errno otherwise.
174+ */
175+static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
176+ size_t len, void *buf)
177+{
178+ u8 addr_width, read_opcode, read_dummy;
179+ int ret;
180+
181+ read_opcode = nor->read_opcode;
182+ addr_width = nor->addr_width;
183+ read_dummy = nor->read_dummy;
184+
185+ nor->read_opcode = SPINOR_OP_RDSFDP;
186+ nor->addr_width = 3;
187+ nor->read_dummy = 8;
188+
189+ ret = spi_nor_read_raw(nor, addr, len, buf);
190+
191+ nor->read_opcode = read_opcode;
192+ nor->addr_width = addr_width;
193+ nor->read_dummy = read_dummy;
194+
195+ return ret;
196+}
197+
198+/**
199+ * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters.
200+ * @nor: pointer to a 'struct spi_nor'
201+ * @addr: offset in the SFDP area to start reading data from
202+ * @len: number of bytes to read
203+ * @buf: buffer where the SFDP data are copied into
204+ *
205+ * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not
206+ * guaranteed to be dma-safe.
207+ *
208+ * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp()
209+ * otherwise.
210+ */
211+static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr,
212+ size_t len, void *buf)
213+{
214+ void *dma_safe_buf;
215+ int ret;
216+
217+ dma_safe_buf = kmalloc(len, GFP_KERNEL);
218+ if (!dma_safe_buf)
219+ return -ENOMEM;
220+
221+ ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf);
222+ memcpy(buf, dma_safe_buf, len);
223+ kfree(dma_safe_buf);
224+
225+ return ret;
226+}
227+
228+static void
229+spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
230+ u16 half,
231+ enum spi_nor_protocol proto)
232+{
233+ read->num_mode_clocks = (half >> 5) & 0x07;
234+ read->num_wait_states = (half >> 0) & 0x1f;
235+ read->opcode = (half >> 8) & 0xff;
236+ read->proto = proto;
237+}
238+
239+static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
240+ /* Fast Read 1-1-2 */
241+ {
242+ SNOR_HWCAPS_READ_1_1_2,
243+ BFPT_DWORD(1), BIT(16), /* Supported bit */
244+ BFPT_DWORD(4), 0, /* Settings */
245+ SNOR_PROTO_1_1_2,
246+ },
247+
248+ /* Fast Read 1-2-2 */
249+ {
250+ SNOR_HWCAPS_READ_1_2_2,
251+ BFPT_DWORD(1), BIT(20), /* Supported bit */
252+ BFPT_DWORD(4), 16, /* Settings */
253+ SNOR_PROTO_1_2_2,
254+ },
255+
256+ /* Fast Read 2-2-2 */
257+ {
258+ SNOR_HWCAPS_READ_2_2_2,
259+ BFPT_DWORD(5), BIT(0), /* Supported bit */
260+ BFPT_DWORD(6), 16, /* Settings */
261+ SNOR_PROTO_2_2_2,
262+ },
263+
264+ /* Fast Read 1-1-4 */
265+ {
266+ SNOR_HWCAPS_READ_1_1_4,
267+ BFPT_DWORD(1), BIT(22), /* Supported bit */
268+ BFPT_DWORD(3), 16, /* Settings */
269+ SNOR_PROTO_1_1_4,
270+ },
271+
272+ /* Fast Read 1-4-4 */
273+ {
274+ SNOR_HWCAPS_READ_1_4_4,
275+ BFPT_DWORD(1), BIT(21), /* Supported bit */
276+ BFPT_DWORD(3), 0, /* Settings */
277+ SNOR_PROTO_1_4_4,
278+ },
279+
280+ /* Fast Read 4-4-4 */
281+ {
282+ SNOR_HWCAPS_READ_4_4_4,
283+ BFPT_DWORD(5), BIT(4), /* Supported bit */
284+ BFPT_DWORD(7), 16, /* Settings */
285+ SNOR_PROTO_4_4_4,
286+ },
287+};
288+
289+static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
290+ /* Erase Type 1 in DWORD8 bits[15:0] */
291+ {BFPT_DWORD(8), 0},
292+
293+ /* Erase Type 2 in DWORD8 bits[31:16] */
294+ {BFPT_DWORD(8), 16},
295+
296+ /* Erase Type 3 in DWORD9 bits[15:0] */
297+ {BFPT_DWORD(9), 0},
298+
299+ /* Erase Type 4 in DWORD9 bits[31:16] */
300+ {BFPT_DWORD(9), 16},
301+};
302+
303+/**
304+ * spi_nor_set_erase_settings_from_bfpt() - set erase type settings from BFPT
305+ * @erase: pointer to a structure that describes a SPI NOR erase type
306+ * @size: the size of the sector/block erased by the erase type
307+ * @opcode: the SPI command op code to erase the sector/block
308+ * @i: erase type index as sorted in the Basic Flash Parameter Table
309+ *
310+ * The supported Erase Types will be sorted at init in ascending order, with
311+ * the smallest Erase Type size being the first member in the erase_type array
312+ * of the spi_nor_erase_map structure. Save the Erase Type index as sorted in
313+ * the Basic Flash Parameter Table since it will be used later on to
314+ * synchronize with the supported Erase Types defined in SFDP optional tables.
315+ */
316+static void
317+spi_nor_set_erase_settings_from_bfpt(struct spi_nor_erase_type *erase,
318+ u32 size, u8 opcode, u8 i)
319+{
320+ erase->idx = i;
321+ spi_nor_set_erase_type(erase, size, opcode);
322+}
323+
324+/**
325+ * spi_nor_map_cmp_erase_type() - compare the map's erase types by size
326+ * @l: member in the left half of the map's erase_type array
327+ * @r: member in the right half of the map's erase_type array
328+ *
329+ * Comparison function used in the sort() call to sort in ascending order the
330+ * map's erase types, the smallest erase type size being the first member in the
331+ * sorted erase_type array.
332+ *
333+ * Return: the result of @l->size - @r->size
334+ */
335+static int spi_nor_map_cmp_erase_type(const void *l, const void *r)
336+{
337+ const struct spi_nor_erase_type *left = l, *right = r;
338+
339+ return left->size - right->size;
340+}
341+
342+/**
343+ * spi_nor_sort_erase_mask() - sort erase mask
344+ * @map: the erase map of the SPI NOR
345+ * @erase_mask: the erase type mask to be sorted
346+ *
347+ * Replicate the sort done for the map's erase types in BFPT: sort the erase
348+ * mask in ascending order with the smallest erase type size starting from
349+ * BIT(0) in the sorted erase mask.
350+ *
351+ * Return: sorted erase mask.
352+ */
353+static u8 spi_nor_sort_erase_mask(struct spi_nor_erase_map *map, u8 erase_mask)
354+{
355+ struct spi_nor_erase_type *erase_type = map->erase_type;
356+ int i;
357+ u8 sorted_erase_mask = 0;
358+
359+ if (!erase_mask)
360+ return 0;
361+
362+ /* Replicate the sort done for the map's erase types. */
363+ for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++)
364+ if (erase_type[i].size && erase_mask & BIT(erase_type[i].idx))
365+ sorted_erase_mask |= BIT(i);
366+
367+ return sorted_erase_mask;
368+}
369+
370+/**
371+ * spi_nor_regions_sort_erase_types() - sort erase types in each region
372+ * @map: the erase map of the SPI NOR
373+ *
374+ * Function assumes that the erase types defined in the erase map are already
375+ * sorted in ascending order, with the smallest erase type size being the first
376+ * member in the erase_type array. It replicates the sort done for the map's
377+ * erase types. Each region's erase bitmask will indicate which erase types are
378+ * supported from the sorted erase types defined in the erase map.
379+ * Sort the all region's erase type at init in order to speed up the process of
380+ * finding the best erase command at runtime.
381+ */
382+static void spi_nor_regions_sort_erase_types(struct spi_nor_erase_map *map)
383+{
384+ struct spi_nor_erase_region *region = map->regions;
385+ u8 region_erase_mask, sorted_erase_mask;
386+
387+ while (region) {
388+ region_erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
389+
390+ sorted_erase_mask = spi_nor_sort_erase_mask(map,
391+ region_erase_mask);
392+
393+ /* Overwrite erase mask. */
394+ region->offset = (region->offset & ~SNOR_ERASE_TYPE_MASK) |
395+ sorted_erase_mask;
396+
397+ region = spi_nor_region_next(region);
398+ }
399+}
400+
401+/**
402+ * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
403+ * @nor: pointer to a 'struct spi_nor'
404+ * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
405+ * the Basic Flash Parameter Table length and version
406+ * @params: pointer to the 'struct spi_nor_flash_parameter' to be
407+ * filled
408+ *
409+ * The Basic Flash Parameter Table is the main and only mandatory table as
410+ * defined by the SFDP (JESD216) specification.
411+ * It provides us with the total size (memory density) of the data array and
412+ * the number of address bytes for Fast Read, Page Program and Sector Erase
413+ * commands.
414+ * For Fast READ commands, it also gives the number of mode clock cycles and
415+ * wait states (regrouped in the number of dummy clock cycles) for each
416+ * supported instruction op code.
417+ * For Page Program, the page size is now available since JESD216 rev A, however
418+ * the supported instruction op codes are still not provided.
419+ * For Sector Erase commands, this table stores the supported instruction op
420+ * codes and the associated sector sizes.
421+ * Finally, the Quad Enable Requirements (QER) are also available since JESD216
422+ * rev A. The QER bits encode the manufacturer dependent procedure to be
423+ * executed to set the Quad Enable (QE) bit in some internal register of the
424+ * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
425+ * sending any Quad SPI command to the memory. Actually, setting the QE bit
426+ * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
427+ * and IO3 hence enabling 4 (Quad) I/O lines.
428+ *
429+ * Return: 0 on success, -errno otherwise.
430+ */
431+static int spi_nor_parse_bfpt(struct spi_nor *nor,
432+ const struct sfdp_parameter_header *bfpt_header,
433+ struct spi_nor_flash_parameter *params)
434+{
435+ struct spi_nor_erase_map *map = &params->erase_map;
436+ struct spi_nor_erase_type *erase_type = map->erase_type;
437+ struct sfdp_bfpt bfpt;
438+ size_t len;
439+ int i, cmd, err;
440+ u32 addr;
441+ u16 half;
442+ u8 erase_mask;
443+
444+ /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
445+ if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
446+ return -EINVAL;
447+
448+ /* Read the Basic Flash Parameter Table. */
449+ len = min_t(size_t, sizeof(bfpt),
450+ bfpt_header->length * sizeof(u32));
451+ addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
452+ memset(&bfpt, 0, sizeof(bfpt));
453+ err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt);
454+ if (err < 0)
455+ return err;
456+
457+ /* Fix endianness of the BFPT DWORDs. */
458+ le32_to_cpu_array(bfpt.dwords, BFPT_DWORD_MAX);
459+
460+ /* Number of address bytes. */
461+ switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
462+ case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
463+ nor->addr_width = 3;
464+ break;
465+
466+ case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
467+ nor->addr_width = 4;
468+ break;
469+
470+ default:
471+ break;
472+ }
473+
474+ /* Flash Memory Density (in bits). */
475+ params->size = bfpt.dwords[BFPT_DWORD(2)];
476+ if (params->size & BIT(31)) {
477+ params->size &= ~BIT(31);
478+
479+ /*
480+ * Prevent overflows on params->size. Anyway, a NOR of 2^64
481+ * bits is unlikely to exist so this error probably means
482+ * the BFPT we are reading is corrupted/wrong.
483+ */
484+ if (params->size > 63)
485+ return -EINVAL;
486+
487+ params->size = 1ULL << params->size;
488+ } else {
489+ params->size++;
490+ }
491+ params->size >>= 3; /* Convert to bytes. */
492+
493+ /* Fast Read settings. */
494+ for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
495+ const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
496+ struct spi_nor_read_command *read;
497+
498+ if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
499+ params->hwcaps.mask &= ~rd->hwcaps;
500+ continue;
501+ }
502+
503+ params->hwcaps.mask |= rd->hwcaps;
504+ cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
505+ read = &params->reads[cmd];
506+ half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
507+ spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
508+ }
509+
510+ /*
511+ * Sector Erase settings. Reinitialize the uniform erase map using the
512+ * Erase Types defined in the bfpt table.
513+ */
514+ erase_mask = 0;
515+ memset(&params->erase_map, 0, sizeof(params->erase_map));
516+ for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
517+ const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
518+ u32 erasesize;
519+ u8 opcode;
520+
521+ half = bfpt.dwords[er->dword] >> er->shift;
522+ erasesize = half & 0xff;
523+
524+ /* erasesize == 0 means this Erase Type is not supported. */
525+ if (!erasesize)
526+ continue;
527+
528+ erasesize = 1U << erasesize;
529+ opcode = (half >> 8) & 0xff;
530+ erase_mask |= BIT(i);
531+ spi_nor_set_erase_settings_from_bfpt(&erase_type[i], erasesize,
532+ opcode, i);
533+ }
534+ spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
535+ /*
536+ * Sort all the map's Erase Types in ascending order with the smallest
537+ * erase size being the first member in the erase_type array.
538+ */
539+ sort(erase_type, SNOR_ERASE_TYPE_MAX, sizeof(erase_type[0]),
540+ spi_nor_map_cmp_erase_type, NULL);
541+ /*
542+ * Sort the erase types in the uniform region in order to update the
543+ * uniform_erase_type bitmask. The bitmask will be used later on when
544+ * selecting the uniform erase.
545+ */
546+ spi_nor_regions_sort_erase_types(map);
547+ map->uniform_erase_type = map->uniform_region.offset &
548+ SNOR_ERASE_TYPE_MASK;
549+
550+ /* Stop here if not JESD216 rev A or later. */
551+ if (bfpt_header->length < BFPT_DWORD_MAX)
552+ return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
553+ params);
554+
555+ /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
556+ params->page_size = bfpt.dwords[BFPT_DWORD(11)];
557+ params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
558+ params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
559+ params->page_size = 1U << params->page_size;
560+
561+ /* Quad Enable Requirements. */
562+ switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
563+ case BFPT_DWORD15_QER_NONE:
564+ params->quad_enable = NULL;
565+ break;
566+
567+ case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
568+ /*
569+ * Writing only one byte to the Status Register has the
570+ * side-effect of clearing Status Register 2.
571+ */
572+ case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
573+ /*
574+ * Read Configuration Register (35h) instruction is not
575+ * supported.
576+ */
577+ nor->flags |= SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR;
578+ params->quad_enable = spi_nor_sr2_bit1_quad_enable;
579+ break;
580+
581+ case BFPT_DWORD15_QER_SR1_BIT6:
582+ nor->flags &= ~SNOR_F_HAS_16BIT_SR;
583+ params->quad_enable = spi_nor_sr1_bit6_quad_enable;
584+ break;
585+
586+ case BFPT_DWORD15_QER_SR2_BIT7:
587+ nor->flags &= ~SNOR_F_HAS_16BIT_SR;
588+ params->quad_enable = spi_nor_sr2_bit7_quad_enable;
589+ break;
590+
591+ case BFPT_DWORD15_QER_SR2_BIT1:
592+ /*
593+ * JESD216 rev B or later does not specify if writing only one
594+ * byte to the Status Register clears or not the Status
595+ * Register 2, so let's be cautious and keep the default
596+ * assumption of a 16-bit Write Status (01h) command.
597+ */
598+ nor->flags |= SNOR_F_HAS_16BIT_SR;
599+
600+ params->quad_enable = spi_nor_sr2_bit1_quad_enable;
601+ break;
602+
603+ default:
604+ return -EINVAL;
605+ }
606+
607+ return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
608+}
609+
610+/**
611+ * spi_nor_smpt_addr_width() - return the address width used in the
612+ * configuration detection command.
613+ * @nor: pointer to a 'struct spi_nor'
614+ * @settings: configuration detection command descriptor, dword1
615+ */
616+static u8 spi_nor_smpt_addr_width(const struct spi_nor *nor, const u32 settings)
617+{
618+ switch (settings & SMPT_CMD_ADDRESS_LEN_MASK) {
619+ case SMPT_CMD_ADDRESS_LEN_0:
620+ return 0;
621+ case SMPT_CMD_ADDRESS_LEN_3:
622+ return 3;
623+ case SMPT_CMD_ADDRESS_LEN_4:
624+ return 4;
625+ case SMPT_CMD_ADDRESS_LEN_USE_CURRENT:
626+ default:
627+ return nor->addr_width;
628+ }
629+}
630+
631+/**
632+ * spi_nor_smpt_read_dummy() - return the configuration detection command read
633+ * latency, in clock cycles.
634+ * @nor: pointer to a 'struct spi_nor'
635+ * @settings: configuration detection command descriptor, dword1
636+ *
637+ * Return: the number of dummy cycles for an SMPT read
638+ */
639+static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings)
640+{
641+ u8 read_dummy = SMPT_CMD_READ_DUMMY(settings);
642+
643+ if (read_dummy == SMPT_CMD_READ_DUMMY_IS_VARIABLE)
644+ return nor->read_dummy;
645+ return read_dummy;
646+}
647+
648+/**
649+ * spi_nor_get_map_in_use() - get the configuration map in use
650+ * @nor: pointer to a 'struct spi_nor'
651+ * @smpt: pointer to the sector map parameter table
652+ * @smpt_len: sector map parameter table length
653+ *
654+ * Return: pointer to the map in use, ERR_PTR(-errno) otherwise.
655+ */
656+static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt,
657+ u8 smpt_len)
658+{
659+ const u32 *ret;
660+ u8 *buf;
661+ u32 addr;
662+ int err;
663+ u8 i;
664+ u8 addr_width, read_opcode, read_dummy;
665+ u8 read_data_mask, map_id;
666+
667+ /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */
668+ buf = kmalloc(sizeof(*buf), GFP_KERNEL);
669+ if (!buf)
670+ return ERR_PTR(-ENOMEM);
671+
672+ addr_width = nor->addr_width;
673+ read_dummy = nor->read_dummy;
674+ read_opcode = nor->read_opcode;
675+
676+ map_id = 0;
677+ /* Determine if there are any optional Detection Command Descriptors */
678+ for (i = 0; i < smpt_len; i += 2) {
679+ if (smpt[i] & SMPT_DESC_TYPE_MAP)
680+ break;
681+
682+ read_data_mask = SMPT_CMD_READ_DATA(smpt[i]);
683+ nor->addr_width = spi_nor_smpt_addr_width(nor, smpt[i]);
684+ nor->read_dummy = spi_nor_smpt_read_dummy(nor, smpt[i]);
685+ nor->read_opcode = SMPT_CMD_OPCODE(smpt[i]);
686+ addr = smpt[i + 1];
687+
688+ err = spi_nor_read_raw(nor, addr, 1, buf);
689+ if (err) {
690+ ret = ERR_PTR(err);
691+ goto out;
692+ }
693+
694+ /*
695+ * Build an index value that is used to select the Sector Map
696+ * Configuration that is currently in use.
697+ */
698+ map_id = map_id << 1 | !!(*buf & read_data_mask);
699+ }
700+
701+ /*
702+ * If command descriptors are provided, they always precede map
703+ * descriptors in the table. There is no need to start the iteration
704+ * over smpt array all over again.
705+ *
706+ * Find the matching configuration map.
707+ */
708+ ret = ERR_PTR(-EINVAL);
709+ while (i < smpt_len) {
710+ if (SMPT_MAP_ID(smpt[i]) == map_id) {
711+ ret = smpt + i;
712+ break;
713+ }
714+
715+ /*
716+ * If there are no more configuration map descriptors and no
717+ * configuration ID matched the configuration identifier, the
718+ * sector address map is unknown.
719+ */
720+ if (smpt[i] & SMPT_DESC_END)
721+ break;
722+
723+ /* increment the table index to the next map */
724+ i += SMPT_MAP_REGION_COUNT(smpt[i]) + 1;
725+ }
726+
727+ /* fall through */
728+out:
729+ kfree(buf);
730+ nor->addr_width = addr_width;
731+ nor->read_dummy = read_dummy;
732+ nor->read_opcode = read_opcode;
733+ return ret;
734+}
735+
736+static void spi_nor_region_mark_end(struct spi_nor_erase_region *region)
737+{
738+ region->offset |= SNOR_LAST_REGION;
739+}
740+
741+static void spi_nor_region_mark_overlay(struct spi_nor_erase_region *region)
742+{
743+ region->offset |= SNOR_OVERLAID_REGION;
744+}
745+
746+/**
747+ * spi_nor_region_check_overlay() - set overlay bit when the region is overlaid
748+ * @region: pointer to a structure that describes a SPI NOR erase region
749+ * @erase: pointer to a structure that describes a SPI NOR erase type
750+ * @erase_type: erase type bitmask
751+ */
752+static void
753+spi_nor_region_check_overlay(struct spi_nor_erase_region *region,
754+ const struct spi_nor_erase_type *erase,
755+ const u8 erase_type)
756+{
757+ int i;
758+
759+ for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
760+ if (!(erase_type & BIT(i)))
761+ continue;
762+ if (region->size & erase[i].size_mask) {
763+ spi_nor_region_mark_overlay(region);
764+ return;
765+ }
766+ }
767+}
768+
769+/**
770+ * spi_nor_init_non_uniform_erase_map() - initialize the non-uniform erase map
771+ * @nor: pointer to a 'struct spi_nor'
772+ * @params: pointer to a duplicate 'struct spi_nor_flash_parameter' that is
773+ * used for storing SFDP parsed data
774+ * @smpt: pointer to the sector map parameter table
775+ *
776+ * Return: 0 on success, -errno otherwise.
777+ */
778+static int
779+spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
780+ struct spi_nor_flash_parameter *params,
781+ const u32 *smpt)
782+{
783+ struct spi_nor_erase_map *map = &params->erase_map;
784+ struct spi_nor_erase_type *erase = map->erase_type;
785+ struct spi_nor_erase_region *region;
786+ u64 offset;
787+ u32 region_count;
788+ int i, j;
789+ u8 uniform_erase_type, save_uniform_erase_type;
790+ u8 erase_type, regions_erase_type;
791+
792+ region_count = SMPT_MAP_REGION_COUNT(*smpt);
793+ /*
794+ * The regions will be freed when the driver detaches from the
795+ * device.
796+ */
797+ region = devm_kcalloc(nor->dev, region_count, sizeof(*region),
798+ GFP_KERNEL);
799+ if (!region)
800+ return -ENOMEM;
801+ map->regions = region;
802+
803+ uniform_erase_type = 0xff;
804+ regions_erase_type = 0;
805+ offset = 0;
806+ /* Populate regions. */
807+ for (i = 0; i < region_count; i++) {
808+ j = i + 1; /* index for the region dword */
809+ region[i].size = SMPT_MAP_REGION_SIZE(smpt[j]);
810+ erase_type = SMPT_MAP_REGION_ERASE_TYPE(smpt[j]);
811+ region[i].offset = offset | erase_type;
812+
813+ spi_nor_region_check_overlay(&region[i], erase, erase_type);
814+
815+ /*
816+ * Save the erase types that are supported in all regions and
817+ * can erase the entire flash memory.
818+ */
819+ uniform_erase_type &= erase_type;
820+
821+ /*
822+ * regions_erase_type mask will indicate all the erase types
823+ * supported in this configuration map.
824+ */
825+ regions_erase_type |= erase_type;
826+
827+ offset = (region[i].offset & ~SNOR_ERASE_FLAGS_MASK) +
828+ region[i].size;
829+ }
830+
831+ save_uniform_erase_type = map->uniform_erase_type;
832+ map->uniform_erase_type = spi_nor_sort_erase_mask(map,
833+ uniform_erase_type);
834+
835+ if (!regions_erase_type) {
836+ /*
837+ * Roll back to the previous uniform_erase_type mask, SMPT is
838+ * broken.
839+ */
840+ map->uniform_erase_type = save_uniform_erase_type;
841+ return -EINVAL;
842+ }
843+
844+ /*
845+ * BFPT advertises all the erase types supported by all the possible
846+ * map configurations. Mask out the erase types that are not supported
847+ * by the current map configuration.
848+ */
849+ for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++)
850+ if (!(regions_erase_type & BIT(erase[i].idx)))
851+ spi_nor_set_erase_type(&erase[i], 0, 0xFF);
852+
853+ spi_nor_region_mark_end(&region[i - 1]);
854+
855+ return 0;
856+}
857+
858+/**
859+ * spi_nor_parse_smpt() - parse Sector Map Parameter Table
860+ * @nor: pointer to a 'struct spi_nor'
861+ * @smpt_header: sector map parameter table header
862+ * @params: pointer to a duplicate 'struct spi_nor_flash_parameter'
863+ * that is used for storing SFDP parsed data
864+ *
865+ * This table is optional, but when available, we parse it to identify the
866+ * location and size of sectors within the main data array of the flash memory
867+ * device and to identify which Erase Types are supported by each sector.
868+ *
869+ * Return: 0 on success, -errno otherwise.
870+ */
871+static int spi_nor_parse_smpt(struct spi_nor *nor,
872+ const struct sfdp_parameter_header *smpt_header,
873+ struct spi_nor_flash_parameter *params)
874+{
875+ const u32 *sector_map;
876+ u32 *smpt;
877+ size_t len;
878+ u32 addr;
879+ int ret;
880+
881+ /* Read the Sector Map Parameter Table. */
882+ len = smpt_header->length * sizeof(*smpt);
883+ smpt = kmalloc(len, GFP_KERNEL);
884+ if (!smpt)
885+ return -ENOMEM;
886+
887+ addr = SFDP_PARAM_HEADER_PTP(smpt_header);
888+ ret = spi_nor_read_sfdp(nor, addr, len, smpt);
889+ if (ret)
890+ goto out;
891+
892+ /* Fix endianness of the SMPT DWORDs. */
893+ le32_to_cpu_array(smpt, smpt_header->length);
894+
895+ sector_map = spi_nor_get_map_in_use(nor, smpt, smpt_header->length);
896+ if (IS_ERR(sector_map)) {
897+ ret = PTR_ERR(sector_map);
898+ goto out;
899+ }
900+
901+ ret = spi_nor_init_non_uniform_erase_map(nor, params, sector_map);
902+ if (ret)
903+ goto out;
904+
905+ spi_nor_regions_sort_erase_types(&params->erase_map);
906+ /* fall through */
907+out:
908+ kfree(smpt);
909+ return ret;
910+}
911+
912+/**
913+ * spi_nor_parse_4bait() - parse the 4-Byte Address Instruction Table
914+ * @nor: pointer to a 'struct spi_nor'.
915+ * @param_header: pointer to the 'struct sfdp_parameter_header' describing
916+ * the 4-Byte Address Instruction Table length and version.
917+ * @params: pointer to the 'struct spi_nor_flash_parameter' to be.
918+ *
919+ * Return: 0 on success, -errno otherwise.
920+ */
921+static int spi_nor_parse_4bait(struct spi_nor *nor,
922+ const struct sfdp_parameter_header *param_header,
923+ struct spi_nor_flash_parameter *params)
924+{
925+ static const struct sfdp_4bait reads[] = {
926+ { SNOR_HWCAPS_READ, BIT(0) },
927+ { SNOR_HWCAPS_READ_FAST, BIT(1) },
928+ { SNOR_HWCAPS_READ_1_1_2, BIT(2) },
929+ { SNOR_HWCAPS_READ_1_2_2, BIT(3) },
930+ { SNOR_HWCAPS_READ_1_1_4, BIT(4) },
931+ { SNOR_HWCAPS_READ_1_4_4, BIT(5) },
932+ { SNOR_HWCAPS_READ_1_1_1_DTR, BIT(13) },
933+ { SNOR_HWCAPS_READ_1_2_2_DTR, BIT(14) },
934+ { SNOR_HWCAPS_READ_1_4_4_DTR, BIT(15) },
935+ };
936+ static const struct sfdp_4bait programs[] = {
937+ { SNOR_HWCAPS_PP, BIT(6) },
938+ { SNOR_HWCAPS_PP_1_1_4, BIT(7) },
939+ { SNOR_HWCAPS_PP_1_4_4, BIT(8) },
940+ };
941+ static const struct sfdp_4bait erases[SNOR_ERASE_TYPE_MAX] = {
942+ { 0u /* not used */, BIT(9) },
943+ { 0u /* not used */, BIT(10) },
944+ { 0u /* not used */, BIT(11) },
945+ { 0u /* not used */, BIT(12) },
946+ };
947+ struct spi_nor_pp_command *params_pp = params->page_programs;
948+ struct spi_nor_erase_map *map = &params->erase_map;
949+ struct spi_nor_erase_type *erase_type = map->erase_type;
950+ u32 *dwords;
951+ size_t len;
952+ u32 addr, discard_hwcaps, read_hwcaps, pp_hwcaps, erase_mask;
953+ int i, ret;
954+
955+ if (param_header->major != SFDP_JESD216_MAJOR ||
956+ param_header->length < SFDP_4BAIT_DWORD_MAX)
957+ return -EINVAL;
958+
959+ /* Read the 4-byte Address Instruction Table. */
960+ len = sizeof(*dwords) * SFDP_4BAIT_DWORD_MAX;
961+
962+ /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */
963+ dwords = kmalloc(len, GFP_KERNEL);
964+ if (!dwords)
965+ return -ENOMEM;
966+
967+ addr = SFDP_PARAM_HEADER_PTP(param_header);
968+ ret = spi_nor_read_sfdp(nor, addr, len, dwords);
969+ if (ret)
970+ goto out;
971+
972+ /* Fix endianness of the 4BAIT DWORDs. */
973+ le32_to_cpu_array(dwords, SFDP_4BAIT_DWORD_MAX);
974+
975+ /*
976+ * Compute the subset of (Fast) Read commands for which the 4-byte
977+ * version is supported.
978+ */
979+ discard_hwcaps = 0;
980+ read_hwcaps = 0;
981+ for (i = 0; i < ARRAY_SIZE(reads); i++) {
982+ const struct sfdp_4bait *read = &reads[i];
983+
984+ discard_hwcaps |= read->hwcaps;
985+ if ((params->hwcaps.mask & read->hwcaps) &&
986+ (dwords[0] & read->supported_bit))
987+ read_hwcaps |= read->hwcaps;
988+ }
989+
990+ /*
991+ * Compute the subset of Page Program commands for which the 4-byte
992+ * version is supported.
993+ */
994+ pp_hwcaps = 0;
995+ for (i = 0; i < ARRAY_SIZE(programs); i++) {
996+ const struct sfdp_4bait *program = &programs[i];
997+
998+ /*
999+ * The 4 Byte Address Instruction (Optional) Table is the only
1000+ * SFDP table that indicates support for Page Program Commands.
1001+ * Bypass the params->hwcaps.mask and consider 4BAIT the biggest
1002+ * authority for specifying Page Program support.
1003+ */
1004+ discard_hwcaps |= program->hwcaps;
1005+ if (dwords[0] & program->supported_bit)
1006+ pp_hwcaps |= program->hwcaps;
1007+ }
1008+
1009+ /*
1010+ * Compute the subset of Sector Erase commands for which the 4-byte
1011+ * version is supported.
1012+ */
1013+ erase_mask = 0;
1014+ for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
1015+ const struct sfdp_4bait *erase = &erases[i];
1016+
1017+ if (dwords[0] & erase->supported_bit)
1018+ erase_mask |= BIT(i);
1019+ }
1020+
1021+ /* Replicate the sort done for the map's erase types in BFPT. */
1022+ erase_mask = spi_nor_sort_erase_mask(map, erase_mask);
1023+
1024+ /*
1025+ * We need at least one 4-byte op code per read, program and erase
1026+ * operation; the .read(), .write() and .erase() hooks share the
1027+ * nor->addr_width value.
1028+ */
1029+ if (!read_hwcaps || !pp_hwcaps || !erase_mask)
1030+ goto out;
1031+
1032+ /*
1033+ * Discard all operations from the 4-byte instruction set which are
1034+ * not supported by this memory.
1035+ */
1036+ params->hwcaps.mask &= ~discard_hwcaps;
1037+ params->hwcaps.mask |= (read_hwcaps | pp_hwcaps);
1038+
1039+ /* Use the 4-byte address instruction set. */
1040+ for (i = 0; i < SNOR_CMD_READ_MAX; i++) {
1041+ struct spi_nor_read_command *read_cmd = &params->reads[i];
1042+
1043+ read_cmd->opcode = spi_nor_convert_3to4_read(read_cmd->opcode);
1044+ }
1045+
1046+ /* 4BAIT is the only SFDP table that indicates page program support. */
1047+ if (pp_hwcaps & SNOR_HWCAPS_PP)
1048+ spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP],
1049+ SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
1050+ if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_4)
1051+ spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP_1_1_4],
1052+ SPINOR_OP_PP_1_1_4_4B,
1053+ SNOR_PROTO_1_1_4);
1054+ if (pp_hwcaps & SNOR_HWCAPS_PP_1_4_4)
1055+ spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP_1_4_4],
1056+ SPINOR_OP_PP_1_4_4_4B,
1057+ SNOR_PROTO_1_4_4);
1058+
1059+ for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
1060+ if (erase_mask & BIT(i))
1061+ erase_type[i].opcode = (dwords[1] >>
1062+ erase_type[i].idx * 8) & 0xFF;
1063+ else
1064+ spi_nor_set_erase_type(&erase_type[i], 0u, 0xFF);
1065+ }
1066+
1067+ /*
1068+ * We set SNOR_F_HAS_4BAIT in order to skip spi_nor_set_4byte_opcodes()
1069+ * later because we already did the conversion to 4byte opcodes. Also,
1070+ * this latest function implements a legacy quirk for the erase size of
1071+ * Spansion memory. However this quirk is no longer needed with new
1072+ * SFDP compliant memories.
1073+ */
1074+ nor->addr_width = 4;
1075+ nor->flags |= SNOR_F_4B_OPCODES | SNOR_F_HAS_4BAIT;
1076+
1077+ /* fall through */
1078+out:
1079+ kfree(dwords);
1080+ return ret;
1081+}
1082+
1083+/**
1084+ * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
1085+ * @nor: pointer to a 'struct spi_nor'
1086+ * @params: pointer to the 'struct spi_nor_flash_parameter' to be
1087+ * filled
1088+ *
1089+ * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
1090+ * specification. This is a standard which tends to supported by almost all
1091+ * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
1092+ * runtime the main parameters needed to perform basic SPI flash operations such
1093+ * as Fast Read, Page Program or Sector Erase commands.
1094+ *
1095+ * Return: 0 on success, -errno otherwise.
1096+ */
1097+int spi_nor_parse_sfdp(struct spi_nor *nor,
1098+ struct spi_nor_flash_parameter *params)
1099+{
1100+ const struct sfdp_parameter_header *param_header, *bfpt_header;
1101+ struct sfdp_parameter_header *param_headers = NULL;
1102+ struct sfdp_header header;
1103+ struct device *dev = nor->dev;
1104+ size_t psize;
1105+ int i, err;
1106+
1107+ /* Get the SFDP header. */
1108+ err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header);
1109+ if (err < 0)
1110+ return err;
1111+
1112+ /* Check the SFDP header version. */
1113+ if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
1114+ header.major != SFDP_JESD216_MAJOR)
1115+ return -EINVAL;
1116+
1117+ /*
1118+ * Verify that the first and only mandatory parameter header is a
1119+ * Basic Flash Parameter Table header as specified in JESD216.
1120+ */
1121+ bfpt_header = &header.bfpt_header;
1122+ if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
1123+ bfpt_header->major != SFDP_JESD216_MAJOR)
1124+ return -EINVAL;
1125+
1126+ /*
1127+ * Allocate memory then read all parameter headers with a single
1128+ * Read SFDP command. These parameter headers will actually be parsed
1129+ * twice: a first time to get the latest revision of the basic flash
1130+ * parameter table, then a second time to handle the supported optional
1131+ * tables.
1132+ * Hence we read the parameter headers once for all to reduce the
1133+ * processing time. Also we use kmalloc() instead of devm_kmalloc()
1134+ * because we don't need to keep these parameter headers: the allocated
1135+ * memory is always released with kfree() before exiting this function.
1136+ */
1137+ if (header.nph) {
1138+ psize = header.nph * sizeof(*param_headers);
1139+
1140+ param_headers = kmalloc(psize, GFP_KERNEL);
1141+ if (!param_headers)
1142+ return -ENOMEM;
1143+
1144+ err = spi_nor_read_sfdp(nor, sizeof(header),
1145+ psize, param_headers);
1146+ if (err < 0) {
1147+ dev_dbg(dev, "failed to read SFDP parameter headers\n");
1148+ goto exit;
1149+ }
1150+ }
1151+
1152+ /*
1153+ * Check other parameter headers to get the latest revision of
1154+ * the basic flash parameter table.
1155+ */
1156+ for (i = 0; i < header.nph; i++) {
1157+ param_header = &param_headers[i];
1158+
1159+ if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
1160+ param_header->major == SFDP_JESD216_MAJOR &&
1161+ (param_header->minor > bfpt_header->minor ||
1162+ (param_header->minor == bfpt_header->minor &&
1163+ param_header->length > bfpt_header->length)))
1164+ bfpt_header = param_header;
1165+ }
1166+
1167+ err = spi_nor_parse_bfpt(nor, bfpt_header, params);
1168+ if (err)
1169+ goto exit;
1170+
1171+ /* Parse optional parameter tables. */
1172+ for (i = 0; i < header.nph; i++) {
1173+ param_header = &param_headers[i];
1174+
1175+ switch (SFDP_PARAM_HEADER_ID(param_header)) {
1176+ case SFDP_SECTOR_MAP_ID:
1177+ err = spi_nor_parse_smpt(nor, param_header, params);
1178+ break;
1179+
1180+ case SFDP_4BAIT_ID:
1181+ err = spi_nor_parse_4bait(nor, param_header, params);
1182+ break;
1183+
1184+ default:
1185+ break;
1186+ }
1187+
1188+ if (err) {
1189+ dev_warn(dev, "Failed to parse optional parameter table: %04x\n",
1190+ SFDP_PARAM_HEADER_ID(param_header));
1191+ /*
1192+ * Let's not drop all information we extracted so far
1193+ * if optional table parsers fail. In case of failing,
1194+ * each optional parser is responsible to roll back to
1195+ * the previously known spi_nor data.
1196+ */
1197+ err = 0;
1198+ }
1199+ }
1200+
1201+exit:
1202+ kfree(param_headers);
1203+ return err;
1204+}
drivers/mtd/spi-nor/sfdp.h+98−0
@@ -0,0 +1,98 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#ifndef __LINUX_MTD_SFDP_H
8+#define __LINUX_MTD_SFDP_H
9+
10+/* Basic Flash Parameter Table */
11+
12+/*
13+ * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
14+ * They are indexed from 1 but C arrays are indexed from 0.
15+ */
16+#define BFPT_DWORD(i) ((i) - 1)
17+#define BFPT_DWORD_MAX 16
18+
19+struct sfdp_bfpt {
20+ u32 dwords[BFPT_DWORD_MAX];
21+};
22+
23+/* The first version of JESD216 defined only 9 DWORDs. */
24+#define BFPT_DWORD_MAX_JESD216 9
25+
26+/* 1st DWORD. */
27+#define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
28+#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
29+#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
30+#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
31+#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
32+#define BFPT_DWORD1_DTR BIT(19)
33+#define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
34+#define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
35+#define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
36+
37+/* 5th DWORD. */
38+#define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
39+#define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
40+
41+/* 11th DWORD. */
42+#define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
43+#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
44+
45+/* 15th DWORD. */
46+
47+/*
48+ * (from JESD216 rev B)
49+ * Quad Enable Requirements (QER):
50+ * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
51+ * reads based on instruction. DQ3/HOLD# functions are hold during
52+ * instruction phase.
53+ * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
54+ * two data bytes where bit 1 of the second byte is one.
55+ * [...]
56+ * Writing only one byte to the status register has the side-effect of
57+ * clearing status register 2, including the QE bit. The 100b code is
58+ * used if writing one byte to the status register does not modify
59+ * status register 2.
60+ * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
61+ * one data byte where bit 6 is one.
62+ * [...]
63+ * - 011b: QE is bit 7 of status register 2. It is set via Write status
64+ * register 2 instruction 3Eh with one data byte where bit 7 is one.
65+ * [...]
66+ * The status register 2 is read using instruction 3Fh.
67+ * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
68+ * two data bytes where bit 1 of the second byte is one.
69+ * [...]
70+ * In contrast to the 001b code, writing one byte to the status
71+ * register does not modify status register 2.
72+ * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
73+ * Read Status instruction 05h. Status register2 is read using
74+ * instruction 35h. QE is set via Write Status instruction 01h with
75+ * two data bytes where bit 1 of the second byte is one.
76+ * [...]
77+ */
78+#define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
79+#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
80+#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
81+#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
82+#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
83+#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
84+#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
85+
86+struct sfdp_parameter_header {
87+ u8 id_lsb;
88+ u8 minor;
89+ u8 major;
90+ u8 length; /* in double words */
91+ u8 parameter_table_pointer[3]; /* byte address */
92+ u8 id_msb;
93+};
94+
95+int spi_nor_parse_sfdp(struct spi_nor *nor,
96+ struct spi_nor_flash_parameter *params);
97+
98+#endif /* __LINUX_MTD_SFDP_H */
drivers/mtd/spi-nor/spansion.c+95−0
@@ -0,0 +1,95 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static const struct flash_info spansion_parts[] = {
12+ /* Spansion/Cypress -- single (large) sector size only, at least
13+ * for the chips listed here (without boot sectors).
14+ */
15+ { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64,
16+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
17+ { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128,
18+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
19+ { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
20+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
21+ USE_CLSR) },
22+ { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
23+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
24+ USE_CLSR) },
25+ { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
26+ { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512,
27+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
28+ USE_CLSR) },
29+ { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
30+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
31+ SPI_NOR_HAS_LOCK | USE_CLSR) },
32+ { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256,
33+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
34+ USE_CLSR) },
35+ { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
36+ { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
37+ { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
38+ { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64,
39+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
40+ USE_CLSR) },
41+ { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256,
42+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
43+ USE_CLSR) },
44+ { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
45+ { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
46+ { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
47+ { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
48+ { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
49+ { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8,
50+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
51+ { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16,
52+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
53+ { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32,
54+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
55+ { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
56+ { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32,
57+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
58+ { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
59+ { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
60+ { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8,
61+ SECT_4K | SPI_NOR_DUAL_READ) },
62+ { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16,
63+ SECT_4K | SPI_NOR_DUAL_READ) },
64+ { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128,
65+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
66+ SPI_NOR_4B_OPCODES) },
67+ { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256,
68+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
69+ SPI_NOR_4B_OPCODES) },
70+ { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512,
71+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
72+ SPI_NOR_4B_OPCODES) },
73+};
74+
75+static void spansion_post_sfdp_fixups(struct spi_nor *nor)
76+{
77+ if (nor->params->size <= SZ_16M)
78+ return;
79+
80+ nor->flags |= SNOR_F_4B_OPCODES;
81+ /* No small sector erase for 4-byte command set */
82+ nor->erase_opcode = SPINOR_OP_SE;
83+ nor->mtd.erasesize = nor->info->sector_size;
84+}
85+
86+static const struct spi_nor_fixups spansion_fixups = {
87+ .post_sfdp = spansion_post_sfdp_fixups,
88+};
89+
90+const struct spi_nor_manufacturer spi_nor_spansion = {
91+ .name = "spansion",
92+ .parts = spansion_parts,
93+ .nparts = ARRAY_SIZE(spansion_parts),
94+ .fixups = &spansion_fixups,
95+};
drivers/mtd/spi-nor/spi-nor.c+0−5434
@@ -1,5434 +0,0 @@
1−// SPDX-License-Identifier: GPL-2.0
2−/*
3− * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4− * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5− *
6− * Copyright (C) 2005, Intec Automation Inc.
7− * Copyright (C) 2014, Freescale Semiconductor, Inc.
8− */
9−
10−#include <linux/err.h>
11−#include <linux/errno.h>
12−#include <linux/module.h>
13−#include <linux/device.h>
14−#include <linux/mutex.h>
15−#include <linux/math64.h>
16−#include <linux/sizes.h>
17−#include <linux/slab.h>
18−#include <linux/sort.h>
19−
20−#include <linux/mtd/mtd.h>
21−#include <linux/of_platform.h>
22−#include <linux/sched/task_stack.h>
23−#include <linux/spi/flash.h>
24−#include <linux/mtd/spi-nor.h>
25−
26−/* Define max times to check status register before we give up. */
27−
28−/*
29− * For everything but full-chip erase; probably could be much smaller, but kept
30− * around for safety for now
31− */
32−#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
33−
34−/*
35− * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
36− * for larger flash
37− */
38−#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
39−
40−#define SPI_NOR_MAX_ID_LEN 6
41−#define SPI_NOR_MAX_ADDR_WIDTH 4
42−
43−struct sfdp_parameter_header {
44− u8 id_lsb;
45− u8 minor;
46− u8 major;
47− u8 length; /* in double words */
48− u8 parameter_table_pointer[3]; /* byte address */
49− u8 id_msb;
50−};
51−
52−#define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
53−#define SFDP_PARAM_HEADER_PTP(p) \
54− (((p)->parameter_table_pointer[2] << 16) | \
55− ((p)->parameter_table_pointer[1] << 8) | \
56− ((p)->parameter_table_pointer[0] << 0))
57−
58−#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
59−#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
60−#define SFDP_4BAIT_ID 0xff84 /* 4-byte Address Instruction Table */
61−
62−#define SFDP_SIGNATURE 0x50444653U
63−#define SFDP_JESD216_MAJOR 1
64−#define SFDP_JESD216_MINOR 0
65−#define SFDP_JESD216A_MINOR 5
66−#define SFDP_JESD216B_MINOR 6
67−
68−struct sfdp_header {
69− u32 signature; /* Ox50444653U <=> "SFDP" */
70− u8 minor;
71− u8 major;
72− u8 nph; /* 0-base number of parameter headers */
73− u8 unused;
74−
75− /* Basic Flash Parameter Table. */
76− struct sfdp_parameter_header bfpt_header;
77−};
78−
79−/* Basic Flash Parameter Table */
80−
81−/*
82− * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
83− * They are indexed from 1 but C arrays are indexed from 0.
84− */
85−#define BFPT_DWORD(i) ((i) - 1)
86−#define BFPT_DWORD_MAX 16
87−
88−/* The first version of JESD216 defined only 9 DWORDs. */
89−#define BFPT_DWORD_MAX_JESD216 9
90−
91−/* 1st DWORD. */
92−#define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
93−#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
94−#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
95−#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
96−#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
97−#define BFPT_DWORD1_DTR BIT(19)
98−#define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
99−#define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
100−#define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
101−
102−/* 5th DWORD. */
103−#define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
104−#define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
105−
106−/* 11th DWORD. */
107−#define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
108−#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
109−
110−/* 15th DWORD. */
111−
112−/*
113− * (from JESD216 rev B)
114− * Quad Enable Requirements (QER):
115− * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
116− * reads based on instruction. DQ3/HOLD# functions are hold during
117− * instruction phase.
118− * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
119− * two data bytes where bit 1 of the second byte is one.
120− * [...]
121− * Writing only one byte to the status register has the side-effect of
122− * clearing status register 2, including the QE bit. The 100b code is
123− * used if writing one byte to the status register does not modify
124− * status register 2.
125− * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
126− * one data byte where bit 6 is one.
127− * [...]
128− * - 011b: QE is bit 7 of status register 2. It is set via Write status
129− * register 2 instruction 3Eh with one data byte where bit 7 is one.
130− * [...]
131− * The status register 2 is read using instruction 3Fh.
132− * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
133− * two data bytes where bit 1 of the second byte is one.
134− * [...]
135− * In contrast to the 001b code, writing one byte to the status
136− * register does not modify status register 2.
137− * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
138− * Read Status instruction 05h. Status register2 is read using
139− * instruction 35h. QE is set via Write Status instruction 01h with
140− * two data bytes where bit 1 of the second byte is one.
141− * [...]
142− */
143−#define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
144−#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
145−#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
146−#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
147−#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
148−#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
149−#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
150−
151−struct sfdp_bfpt {
152− u32 dwords[BFPT_DWORD_MAX];
153−};
154−
155−/**
156− * struct spi_nor_fixups - SPI NOR fixup hooks
157− * @default_init: called after default flash parameters init. Used to tweak
158− * flash parameters when information provided by the flash_info
159− * table is incomplete or wrong.
160− * @post_bfpt: called after the BFPT table has been parsed
161− * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
162− * that do not support RDSFDP). Typically used to tweak various
163− * parameters that could not be extracted by other means (i.e.
164− * when information provided by the SFDP/flash_info tables are
165− * incomplete or wrong).
166− *
167− * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
168− * table is broken or not available.
169− */
170−struct spi_nor_fixups {
171− void (*default_init)(struct spi_nor *nor);
172− int (*post_bfpt)(struct spi_nor *nor,
173− const struct sfdp_parameter_header *bfpt_header,
174− const struct sfdp_bfpt *bfpt,
175− struct spi_nor_flash_parameter *params);
176− void (*post_sfdp)(struct spi_nor *nor);
177−};
178−
179−struct flash_info {
180− char *name;
181−
182− /*
183− * This array stores the ID bytes.
184− * The first three bytes are the JEDIC ID.
185− * JEDEC ID zero means "no ID" (mostly older chips).
186− */
187− u8 id[SPI_NOR_MAX_ID_LEN];
188− u8 id_len;
189−
190− /* The size listed here is what works with SPINOR_OP_SE, which isn't
191− * necessarily called a "sector" by the vendor.
192− */
193− unsigned sector_size;
194− u16 n_sectors;
195−
196− u16 page_size;
197− u16 addr_width;
198−
199− u32 flags;
200−#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
201−#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
202−#define SST_WRITE BIT(2) /* use SST byte programming */
203−#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
204−#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
205−#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
206−#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
207−#define USE_FSR BIT(7) /* use flag status register */
208−#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
209−#define SPI_NOR_HAS_TB BIT(9) /*
210− * Flash SR has Top/Bottom (TB) protect
211− * bit. Must be used with
212− * SPI_NOR_HAS_LOCK.
213− */
214−#define SPI_NOR_XSR_RDY BIT(10) /*
215− * S3AN flashes have specific opcode to
216− * read the status register.
217− * Flags SPI_NOR_XSR_RDY and SPI_S3AN
218− * use the same bit as one implies the
219− * other, but we will get rid of
220− * SPI_S3AN soon.
221− */
222−#define SPI_S3AN BIT(10) /*
223− * Xilinx Spartan 3AN In-System Flash
224− * (MFR cannot be used for probing
225− * because it has the same value as
226− * ATMEL flashes)
227− */
228−#define SPI_NOR_4B_OPCODES BIT(11) /*
229− * Use dedicated 4byte address op codes
230− * to support memory size above 128Mib.
231− */
232−#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
233−#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
234−#define USE_CLSR BIT(14) /* use CLSR command */
235−#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
236−#define SPI_NOR_TB_SR_BIT6 BIT(16) /*
237− * Top/Bottom (TB) is bit 6 of
238− * status register. Must be used with
239− * SPI_NOR_HAS_TB.
240− */
241−
242− /* Part specific fixup hooks. */
243− const struct spi_nor_fixups *fixups;
244−};
245−
246−#define JEDEC_MFR(info) ((info)->id[0])
247−
248−/**
249− * spi_nor_spimem_xfer_data() - helper function to read/write data to
250− * flash's memory region
251− * @nor: pointer to 'struct spi_nor'
252− * @op: pointer to 'struct spi_mem_op' template for transfer
253− *
254− * Return: number of bytes transferred on success, -errno otherwise
255− */
256−static ssize_t spi_nor_spimem_xfer_data(struct spi_nor *nor,
257− struct spi_mem_op *op)
258−{
259− bool usebouncebuf = false;
260− void *rdbuf = NULL;
261− const void *buf;
262− int ret;
263−
264− if (op->data.dir == SPI_MEM_DATA_IN)
265− buf = op->data.buf.in;
266− else
267− buf = op->data.buf.out;
268−
269− if (object_is_on_stack(buf) || !virt_addr_valid(buf))
270− usebouncebuf = true;
271−
272− if (usebouncebuf) {
273− if (op->data.nbytes > nor->bouncebuf_size)
274− op->data.nbytes = nor->bouncebuf_size;
275−
276− if (op->data.dir == SPI_MEM_DATA_IN) {
277− rdbuf = op->data.buf.in;
278− op->data.buf.in = nor->bouncebuf;
279− } else {
280− op->data.buf.out = nor->bouncebuf;
281− memcpy(nor->bouncebuf, buf,
282− op->data.nbytes);
283− }
284− }
285−
286− ret = spi_mem_adjust_op_size(nor->spimem, op);
287− if (ret)
288− return ret;
289−
290− ret = spi_mem_exec_op(nor->spimem, op);
291− if (ret)
292− return ret;
293−
294− if (usebouncebuf && op->data.dir == SPI_MEM_DATA_IN)
295− memcpy(rdbuf, nor->bouncebuf, op->data.nbytes);
296−
297− return op->data.nbytes;
298−}
299−
300−/**
301− * spi_nor_spimem_read_data() - read data from flash's memory region via
302− * spi-mem
303− * @nor: pointer to 'struct spi_nor'
304− * @from: offset to read from
305− * @len: number of bytes to read
306− * @buf: pointer to dst buffer
307− *
308− * Return: number of bytes read successfully, -errno otherwise
309− */
310−static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,
311− size_t len, u8 *buf)
312−{
313− struct spi_mem_op op =
314− SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
315− SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
316− SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
317− SPI_MEM_OP_DATA_IN(len, buf, 1));
318−
319− /* get transfer protocols. */
320− op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
321− op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
322− op.dummy.buswidth = op.addr.buswidth;
323− op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
324−
325− /* convert the dummy cycles to the number of bytes */
326− op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
327−
328− return spi_nor_spimem_xfer_data(nor, &op);
329−}
330−
331−/**
332− * spi_nor_read_data() - read data from flash memory
333− * @nor: pointer to 'struct spi_nor'
334− * @from: offset to read from
335− * @len: number of bytes to read
336− * @buf: pointer to dst buffer
337− *
338− * Return: number of bytes read successfully, -errno otherwise
339− */
340−static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
341− u8 *buf)
342−{
343− if (nor->spimem)
344− return spi_nor_spimem_read_data(nor, from, len, buf);
345−
346− return nor->controller_ops->read(nor, from, len, buf);
347−}
348−
349−/**
350− * spi_nor_spimem_write_data() - write data to flash memory via
351− * spi-mem
352− * @nor: pointer to 'struct spi_nor'
353− * @to: offset to write to
354− * @len: number of bytes to write
355− * @buf: pointer to src buffer
356− *
357− * Return: number of bytes written successfully, -errno otherwise
358− */
359−static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
360− size_t len, const u8 *buf)
361−{
362− struct spi_mem_op op =
363− SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
364− SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
365− SPI_MEM_OP_NO_DUMMY,
366− SPI_MEM_OP_DATA_OUT(len, buf, 1));
367−
368− op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
369− op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
370− op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
371−
372− if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
373− op.addr.nbytes = 0;
374−
375− return spi_nor_spimem_xfer_data(nor, &op);
376−}
377−
378−/**
379− * spi_nor_write_data() - write data to flash memory
380− * @nor: pointer to 'struct spi_nor'
381− * @to: offset to write to
382− * @len: number of bytes to write
383− * @buf: pointer to src buffer
384− *
385− * Return: number of bytes written successfully, -errno otherwise
386− */
387−static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
388− const u8 *buf)
389−{
390− if (nor->spimem)
391− return spi_nor_spimem_write_data(nor, to, len, buf);
392−
393− return nor->controller_ops->write(nor, to, len, buf);
394−}
395−
396−/**
397− * spi_nor_write_enable() - Set write enable latch with Write Enable command.
398− * @nor: pointer to 'struct spi_nor'.
399− *
400− * Return: 0 on success, -errno otherwise.
401− */
402−static int spi_nor_write_enable(struct spi_nor *nor)
403−{
404− int ret;
405−
406− if (nor->spimem) {
407− struct spi_mem_op op =
408− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1),
409− SPI_MEM_OP_NO_ADDR,
410− SPI_MEM_OP_NO_DUMMY,
411− SPI_MEM_OP_NO_DATA);
412−
413− ret = spi_mem_exec_op(nor->spimem, &op);
414− } else {
415− ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREN,
416− NULL, 0);
417− }
418−
419− if (ret)
420− dev_dbg(nor->dev, "error %d on Write Enable\n", ret);
421−
422− return ret;
423−}
424−
425−/**
426− * spi_nor_write_disable() - Send Write Disable instruction to the chip.
427− * @nor: pointer to 'struct spi_nor'.
428− *
429− * Return: 0 on success, -errno otherwise.
430− */
431−static int spi_nor_write_disable(struct spi_nor *nor)
432−{
433− int ret;
434−
435− if (nor->spimem) {
436− struct spi_mem_op op =
437− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1),
438− SPI_MEM_OP_NO_ADDR,
439− SPI_MEM_OP_NO_DUMMY,
440− SPI_MEM_OP_NO_DATA);
441−
442− ret = spi_mem_exec_op(nor->spimem, &op);
443− } else {
444− ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI,
445− NULL, 0);
446− }
447−
448− if (ret)
449− dev_dbg(nor->dev, "error %d on Write Disable\n", ret);
450−
451− return ret;
452−}
453−
454−/**
455− * spi_nor_read_sr() - Read the Status Register.
456− * @nor: pointer to 'struct spi_nor'.
457− * @sr: pointer to a DMA-able buffer where the value of the
458− * Status Register will be written.
459− *
460− * Return: 0 on success, -errno otherwise.
461− */
462−static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
463−{
464− int ret;
465−
466− if (nor->spimem) {
467− struct spi_mem_op op =
468− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1),
469− SPI_MEM_OP_NO_ADDR,
470− SPI_MEM_OP_NO_DUMMY,
471− SPI_MEM_OP_DATA_IN(1, sr, 1));
472−
473− ret = spi_mem_exec_op(nor->spimem, &op);
474− } else {
475− ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR,
476− sr, 1);
477− }
478−
479− if (ret)
480− dev_dbg(nor->dev, "error %d reading SR\n", ret);
481−
482− return ret;
483−}
484−
485−/**
486− * spi_nor_read_fsr() - Read the Flag Status Register.
487− * @nor: pointer to 'struct spi_nor'
488− * @fsr: pointer to a DMA-able buffer where the value of the
489− * Flag Status Register will be written.
490− *
491− * Return: 0 on success, -errno otherwise.
492− */
493−static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
494−{
495− int ret;
496−
497− if (nor->spimem) {
498− struct spi_mem_op op =
499− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 1),
500− SPI_MEM_OP_NO_ADDR,
501− SPI_MEM_OP_NO_DUMMY,
502− SPI_MEM_OP_DATA_IN(1, fsr, 1));
503−
504− ret = spi_mem_exec_op(nor->spimem, &op);
505− } else {
506− ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDFSR,
507− fsr, 1);
508− }
509−
510− if (ret)
511− dev_dbg(nor->dev, "error %d reading FSR\n", ret);
512−
513− return ret;
514−}
515−
516−/**
517− * spi_nor_read_cr() - Read the Configuration Register using the
518− * SPINOR_OP_RDCR (35h) command.
519− * @nor: pointer to 'struct spi_nor'
520− * @cr: pointer to a DMA-able buffer where the value of the
521− * Configuration Register will be written.
522− *
523− * Return: 0 on success, -errno otherwise.
524− */
525−static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
526−{
527− int ret;
528−
529− if (nor->spimem) {
530− struct spi_mem_op op =
531− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 1),
532− SPI_MEM_OP_NO_ADDR,
533− SPI_MEM_OP_NO_DUMMY,
534− SPI_MEM_OP_DATA_IN(1, cr, 1));
535−
536− ret = spi_mem_exec_op(nor->spimem, &op);
537− } else {
538− ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR, cr, 1);
539− }
540−
541− if (ret)
542− dev_dbg(nor->dev, "error %d reading CR\n", ret);
543−
544− return ret;
545−}
546−
547−/**
548− * macronix_set_4byte() - Set 4-byte address mode for Macronix flashes.
549− * @nor: pointer to 'struct spi_nor'.
550− * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
551− * address mode.
552− *
553− * Return: 0 on success, -errno otherwise.
554− */
555−static int macronix_set_4byte(struct spi_nor *nor, bool enable)
556−{
557− int ret;
558−
559− if (nor->spimem) {
560− struct spi_mem_op op =
561− SPI_MEM_OP(SPI_MEM_OP_CMD(enable ?
562− SPINOR_OP_EN4B :
563− SPINOR_OP_EX4B,
564− 1),
565− SPI_MEM_OP_NO_ADDR,
566− SPI_MEM_OP_NO_DUMMY,
567− SPI_MEM_OP_NO_DATA);
568−
569− ret = spi_mem_exec_op(nor->spimem, &op);
570− } else {
571− ret = nor->controller_ops->write_reg(nor,
572− enable ? SPINOR_OP_EN4B :
573− SPINOR_OP_EX4B,
574− NULL, 0);
575− }
576−
577− if (ret)
578− dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
579−
580− return ret;
581−}
582−
583−/**
584− * st_micron_set_4byte() - Set 4-byte address mode for ST and Micron flashes.
585− * @nor: pointer to 'struct spi_nor'.
586− * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
587− * address mode.
588− *
589− * Return: 0 on success, -errno otherwise.
590− */
591−static int st_micron_set_4byte(struct spi_nor *nor, bool enable)
592−{
593− int ret;
594−
595− ret = spi_nor_write_enable(nor);
596− if (ret)
597− return ret;
598−
599− ret = macronix_set_4byte(nor, enable);
600− if (ret)
601− return ret;
602−
603− return spi_nor_write_disable(nor);
604−}
605−
606−/**
607− * spansion_set_4byte() - Set 4-byte address mode for Spansion flashes.
608− * @nor: pointer to 'struct spi_nor'.
609− * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
610− * address mode.
611− *
612− * Return: 0 on success, -errno otherwise.
613− */
614−static int spansion_set_4byte(struct spi_nor *nor, bool enable)
615−{
616− int ret;
617−
618− nor->bouncebuf[0] = enable << 7;
619−
620− if (nor->spimem) {
621− struct spi_mem_op op =
622− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 1),
623− SPI_MEM_OP_NO_ADDR,
624− SPI_MEM_OP_NO_DUMMY,
625− SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1));
626−
627− ret = spi_mem_exec_op(nor->spimem, &op);
628− } else {
629− ret = nor->controller_ops->write_reg(nor, SPINOR_OP_BRWR,
630− nor->bouncebuf, 1);
631− }
632−
633− if (ret)
634− dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
635−
636− return ret;
637−}
638−
639−/**
640− * spi_nor_write_ear() - Write Extended Address Register.
641− * @nor: pointer to 'struct spi_nor'.
642− * @ear: value to write to the Extended Address Register.
643− *
644− * Return: 0 on success, -errno otherwise.
645− */
646−static int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
647−{
648− int ret;
649−
650− nor->bouncebuf[0] = ear;
651−
652− if (nor->spimem) {
653− struct spi_mem_op op =
654− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 1),
655− SPI_MEM_OP_NO_ADDR,
656− SPI_MEM_OP_NO_DUMMY,
657− SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1));
658−
659− ret = spi_mem_exec_op(nor->spimem, &op);
660− } else {
661− ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREAR,
662− nor->bouncebuf, 1);
663− }
664−
665− if (ret)
666− dev_dbg(nor->dev, "error %d writing EAR\n", ret);
667−
668− return ret;
669−}
670−
671−/**
672− * winbond_set_4byte() - Set 4-byte address mode for Winbond flashes.
673− * @nor: pointer to 'struct spi_nor'.
674− * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
675− * address mode.
676− *
677− * Return: 0 on success, -errno otherwise.
678− */
679−static int winbond_set_4byte(struct spi_nor *nor, bool enable)
680−{
681− int ret;
682−
683− ret = macronix_set_4byte(nor, enable);
684− if (ret || enable)
685− return ret;
686−
687− /*
688− * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address
689− * Register to be set to 1, so all 3-byte-address reads come from the
690− * second 16M. We must clear the register to enable normal behavior.
691− */
692− ret = spi_nor_write_enable(nor);
693− if (ret)
694− return ret;
695−
696− ret = spi_nor_write_ear(nor, 0);
697− if (ret)
698− return ret;
699−
700− return spi_nor_write_disable(nor);
701−}
702−
703−/**
704− * spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
705− * @nor: pointer to 'struct spi_nor'.
706− * @sr: pointer to a DMA-able buffer where the value of the
707− * Status Register will be written.
708− *
709− * Return: 0 on success, -errno otherwise.
710− */
711−static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
712−{
713− int ret;
714−
715− if (nor->spimem) {
716− struct spi_mem_op op =
717− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 1),
718− SPI_MEM_OP_NO_ADDR,
719− SPI_MEM_OP_NO_DUMMY,
720− SPI_MEM_OP_DATA_IN(1, sr, 1));
721−
722− ret = spi_mem_exec_op(nor->spimem, &op);
723− } else {
724− ret = nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR,
725− sr, 1);
726− }
727−
728− if (ret)
729− dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
730−
731− return ret;
732−}
733−
734−/**
735− * s3an_sr_ready() - Query the Status Register of the S3AN flash to see if the
736− * flash is ready for new commands.
737− * @nor: pointer to 'struct spi_nor'.
738− *
739− * Return: 0 on success, -errno otherwise.
740− */
741−static int s3an_sr_ready(struct spi_nor *nor)
742−{
743− int ret;
744−
745− ret = spi_nor_xread_sr(nor, nor->bouncebuf);
746− if (ret)
747− return ret;
748−
749− return !!(nor->bouncebuf[0] & XSR_RDY);
750−}
751−
752−/**
753− * spi_nor_clear_sr() - Clear the Status Register.
754− * @nor: pointer to 'struct spi_nor'.
755− */
756−static void spi_nor_clear_sr(struct spi_nor *nor)
757−{
758− int ret;
759−
760− if (nor->spimem) {
761− struct spi_mem_op op =
762− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 1),
763− SPI_MEM_OP_NO_ADDR,
764− SPI_MEM_OP_NO_DUMMY,
765− SPI_MEM_OP_NO_DATA);
766−
767− ret = spi_mem_exec_op(nor->spimem, &op);
768− } else {
769− ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR,
770− NULL, 0);
771− }
772−
773− if (ret)
774− dev_dbg(nor->dev, "error %d clearing SR\n", ret);
775−}
776−
777−/**
778− * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
779− * for new commands.
780− * @nor: pointer to 'struct spi_nor'.
781− *
782− * Return: 0 on success, -errno otherwise.
783− */
784−static int spi_nor_sr_ready(struct spi_nor *nor)
785−{
786− int ret = spi_nor_read_sr(nor, nor->bouncebuf);
787−
788− if (ret)
789− return ret;
790−
791− if (nor->flags & SNOR_F_USE_CLSR &&
792− nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
793− if (nor->bouncebuf[0] & SR_E_ERR)
794− dev_err(nor->dev, "Erase Error occurred\n");
795− else
796− dev_err(nor->dev, "Programming Error occurred\n");
797−
798− spi_nor_clear_sr(nor);
799− return -EIO;
800− }
801−
802− return !(nor->bouncebuf[0] & SR_WIP);
803−}
804−
805−/**
806− * spi_nor_clear_fsr() - Clear the Flag Status Register.
807− * @nor: pointer to 'struct spi_nor'.
808− */
809−static void spi_nor_clear_fsr(struct spi_nor *nor)
810−{
811− int ret;
812−
813− if (nor->spimem) {
814− struct spi_mem_op op =
815− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 1),
816− SPI_MEM_OP_NO_ADDR,
817− SPI_MEM_OP_NO_DUMMY,
818− SPI_MEM_OP_NO_DATA);
819−
820− ret = spi_mem_exec_op(nor->spimem, &op);
821− } else {
822− ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR,
823− NULL, 0);
824− }
825−
826− if (ret)
827− dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
828−}
829−
830−/**
831− * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is
832− * ready for new commands.
833− * @nor: pointer to 'struct spi_nor'.
834− *
835− * Return: 0 on success, -errno otherwise.
836− */
837−static int spi_nor_fsr_ready(struct spi_nor *nor)
838−{
839− int ret = spi_nor_read_fsr(nor, nor->bouncebuf);
840−
841− if (ret)
842− return ret;
843−
844− if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
845− if (nor->bouncebuf[0] & FSR_E_ERR)
846− dev_err(nor->dev, "Erase operation failed.\n");
847− else
848− dev_err(nor->dev, "Program operation failed.\n");
849−
850− if (nor->bouncebuf[0] & FSR_PT_ERR)
851− dev_err(nor->dev,
852− "Attempted to modify a protected sector.\n");
853−
854− spi_nor_clear_fsr(nor);
855− return -EIO;
856− }
857−
858− return nor->bouncebuf[0] & FSR_READY;
859−}
860−
861−/**
862− * spi_nor_ready() - Query the flash to see if it is ready for new commands.
863− * @nor: pointer to 'struct spi_nor'.
864− *
865− * Return: 0 on success, -errno otherwise.
866− */
867−static int spi_nor_ready(struct spi_nor *nor)
868−{
869− int sr, fsr;
870−
871− if (nor->flags & SNOR_F_READY_XSR_RDY)
872− sr = s3an_sr_ready(nor);
873− else
874− sr = spi_nor_sr_ready(nor);
875− if (sr < 0)
876− return sr;
877− fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
878− if (fsr < 0)
879− return fsr;
880− return sr && fsr;
881−}
882−
883−/**
884− * spi_nor_wait_till_ready_with_timeout() - Service routine to read the
885− * Status Register until ready, or timeout occurs.
886− * @nor: pointer to "struct spi_nor".
887− * @timeout_jiffies: jiffies to wait until timeout.
888− *
889− * Return: 0 on success, -errno otherwise.
890− */
891−static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
892− unsigned long timeout_jiffies)
893−{
894− unsigned long deadline;
895− int timeout = 0, ret;
896−
897− deadline = jiffies + timeout_jiffies;
898−
899− while (!timeout) {
900− if (time_after_eq(jiffies, deadline))
901− timeout = 1;
902−
903− ret = spi_nor_ready(nor);
904− if (ret < 0)
905− return ret;
906− if (ret)
907− return 0;
908−
909− cond_resched();
910− }
911−
912− dev_dbg(nor->dev, "flash operation timed out\n");
913−
914− return -ETIMEDOUT;
915−}
916−
917−/**
918− * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the
919− * flash to be ready, or timeout occurs.
920− * @nor: pointer to "struct spi_nor".
921− *
922− * Return: 0 on success, -errno otherwise.
923− */
924−static int spi_nor_wait_till_ready(struct spi_nor *nor)
925−{
926− return spi_nor_wait_till_ready_with_timeout(nor,
927− DEFAULT_READY_WAIT_JIFFIES);
928−}
929−
930−/**
931− * spi_nor_write_sr() - Write the Status Register.
932− * @nor: pointer to 'struct spi_nor'.
933− * @sr: pointer to DMA-able buffer to write to the Status Register.
934− * @len: number of bytes to write to the Status Register.
935− *
936− * Return: 0 on success, -errno otherwise.
937− */
938−static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
939−{
940− int ret;
941−
942− ret = spi_nor_write_enable(nor);
943− if (ret)
944− return ret;
945−
946− if (nor->spimem) {
947− struct spi_mem_op op =
948− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1),
949− SPI_MEM_OP_NO_ADDR,
950− SPI_MEM_OP_NO_DUMMY,
951− SPI_MEM_OP_DATA_OUT(len, sr, 1));
952−
953− ret = spi_mem_exec_op(nor->spimem, &op);
954− } else {
955− ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
956− sr, len);
957− }
958−
959− if (ret) {
960− dev_dbg(nor->dev, "error %d writing SR\n", ret);
961− return ret;
962− }
963−
964− return spi_nor_wait_till_ready(nor);
965−}
966−
967−/**
968− * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
969− * ensure that the byte written match the received value.
970− * @nor: pointer to a 'struct spi_nor'.
971− * @sr1: byte value to be written to the Status Register.
972− *
973− * Return: 0 on success, -errno otherwise.
974− */
975−static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
976−{
977− int ret;
978−
979− nor->bouncebuf[0] = sr1;
980−
981− ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
982− if (ret)
983− return ret;
984−
985− ret = spi_nor_read_sr(nor, nor->bouncebuf);
986− if (ret)
987− return ret;
988−
989− if (nor->bouncebuf[0] != sr1) {
990− dev_dbg(nor->dev, "SR1: read back test failed\n");
991− return -EIO;
992− }
993−
994− return 0;
995−}
996−
997−/**
998− * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
999− * Status Register 2 in one shot. Ensure that the byte written in the Status
1000− * Register 1 match the received value, and that the 16-bit Write did not
1001− * affect what was already in the Status Register 2.
1002− * @nor: pointer to a 'struct spi_nor'.
1003− * @sr1: byte value to be written to the Status Register 1.
1004− *
1005− * Return: 0 on success, -errno otherwise.
1006− */
1007−static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
1008−{
1009− int ret;
1010− u8 *sr_cr = nor->bouncebuf;
1011− u8 cr_written;
1012−
1013− /* Make sure we don't overwrite the contents of Status Register 2. */
1014− if (!(nor->flags & SNOR_F_NO_READ_CR)) {
1015− ret = spi_nor_read_cr(nor, &sr_cr[1]);
1016− if (ret)
1017− return ret;
1018− } else if (nor->params.quad_enable) {
1019− /*
1020− * If the Status Register 2 Read command (35h) is not
1021− * supported, we should at least be sure we don't
1022− * change the value of the SR2 Quad Enable bit.
1023− *
1024− * We can safely assume that when the Quad Enable method is
1025− * set, the value of the QE bit is one, as a consequence of the
1026− * nor->params.quad_enable() call.
1027− *
1028− * We can safely assume that the Quad Enable bit is present in
1029− * the Status Register 2 at BIT(1). According to the JESD216
1030− * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
1031− * Write Status (01h) command is available just for the cases
1032− * in which the QE bit is described in SR2 at BIT(1).
1033− */
1034− sr_cr[1] = SR2_QUAD_EN_BIT1;
1035− } else {
1036− sr_cr[1] = 0;
1037− }
1038−
1039− sr_cr[0] = sr1;
1040−
1041− ret = spi_nor_write_sr(nor, sr_cr, 2);
1042− if (ret)
1043− return ret;
1044−
1045− if (nor->flags & SNOR_F_NO_READ_CR)
1046− return 0;
1047−
1048− cr_written = sr_cr[1];
1049−
1050− ret = spi_nor_read_cr(nor, &sr_cr[1]);
1051− if (ret)
1052− return ret;
1053−
1054− if (cr_written != sr_cr[1]) {
1055− dev_dbg(nor->dev, "CR: read back test failed\n");
1056− return -EIO;
1057− }
1058−
1059− return 0;
1060−}
1061−
1062−/**
1063− * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
1064− * Configuration Register in one shot. Ensure that the byte written in the
1065− * Configuration Register match the received value, and that the 16-bit Write
1066− * did not affect what was already in the Status Register 1.
1067− * @nor: pointer to a 'struct spi_nor'.
1068− * @cr: byte value to be written to the Configuration Register.
1069− *
1070− * Return: 0 on success, -errno otherwise.
1071− */
1072−static int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)
1073−{
1074− int ret;
1075− u8 *sr_cr = nor->bouncebuf;
1076− u8 sr_written;
1077−
1078− /* Keep the current value of the Status Register 1. */
1079− ret = spi_nor_read_sr(nor, sr_cr);
1080− if (ret)
1081− return ret;
1082−
1083− sr_cr[1] = cr;
1084−
1085− ret = spi_nor_write_sr(nor, sr_cr, 2);
1086− if (ret)
1087− return ret;
1088−
1089− sr_written = sr_cr[0];
1090−
1091− ret = spi_nor_read_sr(nor, sr_cr);
1092− if (ret)
1093− return ret;
1094−
1095− if (sr_written != sr_cr[0]) {
1096− dev_dbg(nor->dev, "SR: Read back test failed\n");
1097− return -EIO;
1098− }
1099−
1100− if (nor->flags & SNOR_F_NO_READ_CR)
1101− return 0;
1102−
1103− ret = spi_nor_read_cr(nor, &sr_cr[1]);
1104− if (ret)
1105− return ret;
1106−
1107− if (cr != sr_cr[1]) {
1108− dev_dbg(nor->dev, "CR: read back test failed\n");
1109− return -EIO;
1110− }
1111−
1112− return 0;
1113−}
1114−
1115−/**
1116− * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
1117− * the byte written match the received value without affecting other bits in the
1118− * Status Register 1 and 2.
1119− * @nor: pointer to a 'struct spi_nor'.
1120− * @sr1: byte value to be written to the Status Register.
1121− *
1122− * Return: 0 on success, -errno otherwise.
1123− */
1124−static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)
1125−{
1126− if (nor->flags & SNOR_F_HAS_16BIT_SR)
1127− return spi_nor_write_16bit_sr_and_check(nor, sr1);
1128−
1129− return spi_nor_write_sr1_and_check(nor, sr1);
1130−}
1131−
1132−/**
1133− * spi_nor_write_sr2() - Write the Status Register 2 using the
1134− * SPINOR_OP_WRSR2 (3eh) command.
1135− * @nor: pointer to 'struct spi_nor'.
1136− * @sr2: pointer to DMA-able buffer to write to the Status Register 2.
1137− *
1138− * Return: 0 on success, -errno otherwise.
1139− */
1140−static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
1141−{
1142− int ret;
1143−
1144− ret = spi_nor_write_enable(nor);
1145− if (ret)
1146− return ret;
1147−
1148− if (nor->spimem) {
1149− struct spi_mem_op op =
1150− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1),
1151− SPI_MEM_OP_NO_ADDR,
1152− SPI_MEM_OP_NO_DUMMY,
1153− SPI_MEM_OP_DATA_OUT(1, sr2, 1));
1154−
1155− ret = spi_mem_exec_op(nor->spimem, &op);
1156− } else {
1157− ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2,
1158− sr2, 1);
1159− }
1160−
1161− if (ret) {
1162− dev_dbg(nor->dev, "error %d writing SR2\n", ret);
1163− return ret;
1164− }
1165−
1166− return spi_nor_wait_till_ready(nor);
1167−}
1168−
1169−/**
1170− * spi_nor_read_sr2() - Read the Status Register 2 using the
1171− * SPINOR_OP_RDSR2 (3fh) command.
1172− * @nor: pointer to 'struct spi_nor'.
1173− * @sr2: pointer to DMA-able buffer where the value of the
1174− * Status Register 2 will be written.
1175− *
1176− * Return: 0 on success, -errno otherwise.
1177− */
1178−static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
1179−{
1180− int ret;
1181−
1182− if (nor->spimem) {
1183− struct spi_mem_op op =
1184− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1),
1185− SPI_MEM_OP_NO_ADDR,
1186− SPI_MEM_OP_NO_DUMMY,
1187− SPI_MEM_OP_DATA_IN(1, sr2, 1));
1188−
1189− ret = spi_mem_exec_op(nor->spimem, &op);
1190− } else {
1191− ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2,
1192− sr2, 1);
1193− }
1194−
1195− if (ret)
1196− dev_dbg(nor->dev, "error %d reading SR2\n", ret);
1197−
1198− return ret;
1199−}
1200−
1201−/**
1202− * spi_nor_erase_chip() - Erase the entire flash memory.
1203− * @nor: pointer to 'struct spi_nor'.
1204− *
1205− * Return: 0 on success, -errno otherwise.
1206− */
1207−static int spi_nor_erase_chip(struct spi_nor *nor)
1208−{
1209− int ret;
1210−
1211− dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
1212−
1213− if (nor->spimem) {
1214− struct spi_mem_op op =
1215− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 1),
1216− SPI_MEM_OP_NO_ADDR,
1217− SPI_MEM_OP_NO_DUMMY,
1218− SPI_MEM_OP_NO_DATA);
1219−
1220− ret = spi_mem_exec_op(nor->spimem, &op);
1221− } else {
1222− ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CHIP_ERASE,
1223− NULL, 0);
1224− }
1225−
1226− if (ret)
1227− dev_dbg(nor->dev, "error %d erasing chip\n", ret);
1228−
1229− return ret;
1230−}
1231−
1232−static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
1233−{
1234− return mtd->priv;
1235−}
1236−
1237−static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
1238−{
1239− size_t i;
1240−
1241− for (i = 0; i < size; i++)
1242− if (table[i][0] == opcode)
1243− return table[i][1];
1244−
1245− /* No conversion found, keep input op code. */
1246− return opcode;
1247−}
1248−
1249−static u8 spi_nor_convert_3to4_read(u8 opcode)
1250−{
1251− static const u8 spi_nor_3to4_read[][2] = {
1252− { SPINOR_OP_READ, SPINOR_OP_READ_4B },
1253− { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
1254− { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
1255− { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
1256− { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
1257− { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
1258− { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
1259− { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
1260−
1261− { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
1262− { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
1263− { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
1264− };
1265−
1266− return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
1267− ARRAY_SIZE(spi_nor_3to4_read));
1268−}
1269−
1270−static u8 spi_nor_convert_3to4_program(u8 opcode)
1271−{
1272− static const u8 spi_nor_3to4_program[][2] = {
1273− { SPINOR_OP_PP, SPINOR_OP_PP_4B },
1274− { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
1275− { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
1276− { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
1277− { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
1278− };
1279−
1280− return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
1281− ARRAY_SIZE(spi_nor_3to4_program));
1282−}
1283−
1284−static u8 spi_nor_convert_3to4_erase(u8 opcode)
1285−{
1286− static const u8 spi_nor_3to4_erase[][2] = {
1287− { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
1288− { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
1289− { SPINOR_OP_SE, SPINOR_OP_SE_4B },
1290− };
1291−
1292− return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
1293− ARRAY_SIZE(spi_nor_3to4_erase));
1294−}
1295−
1296−static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
1297−{
1298− nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
1299− nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
1300− nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
1301−
1302− if (!spi_nor_has_uniform_erase(nor)) {
1303− struct spi_nor_erase_map *map = &nor->params.erase_map;
1304− struct spi_nor_erase_type *erase;
1305− int i;
1306−
1307− for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
1308− erase = &map->erase_type[i];
1309− erase->opcode =
1310− spi_nor_convert_3to4_erase(erase->opcode);
1311− }
1312− }
1313−}
1314−
1315−static int spi_nor_lock_and_prep(struct spi_nor *nor)
1316−{
1317− int ret = 0;
1318−
1319− mutex_lock(&nor->lock);
1320−
1321− if (nor->controller_ops && nor->controller_ops->prepare) {
1322− ret = nor->controller_ops->prepare(nor);
1323− if (ret) {
1324− mutex_unlock(&nor->lock);
1325− return ret;
1326− }
1327− }
1328− return ret;
1329−}
1330−
1331−static void spi_nor_unlock_and_unprep(struct spi_nor *nor)
1332−{
1333− if (nor->controller_ops && nor->controller_ops->unprepare)
1334− nor->controller_ops->unprepare(nor);
1335− mutex_unlock(&nor->lock);
1336−}
1337−
1338−/*
1339− * This code converts an address to the Default Address Mode, that has non
1340− * power of two page sizes. We must support this mode because it is the default
1341− * mode supported by Xilinx tools, it can access the whole flash area and
1342− * changing over to the Power-of-two mode is irreversible and corrupts the
1343− * original data.
1344− * Addr can safely be unsigned int, the biggest S3AN device is smaller than
1345− * 4 MiB.
1346− */
1347−static u32 s3an_convert_addr(struct spi_nor *nor, u32 addr)
1348−{
1349− u32 offset, page;
1350−
1351− offset = addr % nor->page_size;
1352− page = addr / nor->page_size;
1353− page <<= (nor->page_size > 512) ? 10 : 9;
1354−
1355− return page | offset;
1356−}
1357−
1358−static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
1359−{
1360− if (!nor->params.convert_addr)
1361− return addr;
1362−
1363− return nor->params.convert_addr(nor, addr);
1364−}
1365−
1366−/*
1367− * Initiate the erasure of a single sector
1368− */
1369−static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
1370−{
1371− int i;
1372−
1373− addr = spi_nor_convert_addr(nor, addr);
1374−
1375− if (nor->spimem) {
1376− struct spi_mem_op op =
1377− SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1),
1378− SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
1379− SPI_MEM_OP_NO_DUMMY,
1380− SPI_MEM_OP_NO_DATA);
1381−
1382− return spi_mem_exec_op(nor->spimem, &op);
1383− } else if (nor->controller_ops->erase) {
1384− return nor->controller_ops->erase(nor, addr);
1385− }
1386−
1387− /*
1388− * Default implementation, if driver doesn't have a specialized HW
1389− * control
1390− */
1391− for (i = nor->addr_width - 1; i >= 0; i--) {
1392− nor->bouncebuf[i] = addr & 0xff;
1393− addr >>= 8;
1394− }
1395−
1396− return nor->controller_ops->write_reg(nor, nor->erase_opcode,
1397− nor->bouncebuf, nor->addr_width);
1398−}
1399−
1400−/**
1401− * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
1402− * @erase: pointer to a structure that describes a SPI NOR erase type
1403− * @dividend: dividend value
1404− * @remainder: pointer to u32 remainder (will be updated)
1405− *
1406− * Return: the result of the division
1407− */
1408−static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
1409− u64 dividend, u32 *remainder)
1410−{
1411− /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
1412− *remainder = (u32)dividend & erase->size_mask;
1413− return dividend >> erase->size_shift;
1414−}
1415−
1416−/**
1417− * spi_nor_find_best_erase_type() - find the best erase type for the given
1418− * offset in the serial flash memory and the
1419− * number of bytes to erase. The region in
1420− * which the address fits is expected to be
1421− * provided.
1422− * @map: the erase map of the SPI NOR
1423− * @region: pointer to a structure that describes a SPI NOR erase region
1424− * @addr: offset in the serial flash memory
1425− * @len: number of bytes to erase
1426− *
1427− * Return: a pointer to the best fitted erase type, NULL otherwise.
1428− */
1429−static const struct spi_nor_erase_type *
1430−spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
1431− const struct spi_nor_erase_region *region,
1432− u64 addr, u32 len)
1433−{
1434− const struct spi_nor_erase_type *erase;
1435− u32 rem;
1436− int i;
1437− u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
1438−
1439− /*
1440− * Erase types are ordered by size, with the smallest erase type at
1441− * index 0.
1442− */
1443− for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
1444− /* Does the erase region support the tested erase type? */
1445− if (!(erase_mask & BIT(i)))
1446− continue;
1447−
1448− erase = &map->erase_type[i];
1449−
1450− /* Don't erase more than what the user has asked for. */
1451− if (erase->size > len)
1452− continue;
1453−
1454− /* Alignment is not mandatory for overlaid regions */
1455− if (region->offset & SNOR_OVERLAID_REGION)
1456− return erase;
1457−
1458− spi_nor_div_by_erase_size(erase, addr, &rem);
1459− if (rem)
1460− continue;
1461− else
1462− return erase;
1463− }
1464−
1465− return NULL;
1466−}
1467−
1468−/**
1469− * spi_nor_region_next() - get the next spi nor region
1470− * @region: pointer to a structure that describes a SPI NOR erase region
1471− *
1472− * Return: the next spi nor region or NULL if last region.
1473− */
1474−static struct spi_nor_erase_region *
1475−spi_nor_region_next(struct spi_nor_erase_region *region)
1476−{
1477− if (spi_nor_region_is_last(region))
1478− return NULL;
1479− region++;
1480− return region;
1481−}
1482−
1483−/**
1484− * spi_nor_find_erase_region() - find the region of the serial flash memory in
1485− * which the offset fits
1486− * @map: the erase map of the SPI NOR
1487− * @addr: offset in the serial flash memory
1488− *
1489− * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno)
1490− * otherwise.
1491− */
1492−static struct spi_nor_erase_region *
1493−spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr)
1494−{
1495− struct spi_nor_erase_region *region = map->regions;
1496− u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1497− u64 region_end = region_start + region->size;
1498−
1499− while (addr < region_start || addr >= region_end) {
1500− region = spi_nor_region_next(region);
1501− if (!region)
1502− return ERR_PTR(-EINVAL);
1503−
1504− region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1505− region_end = region_start + region->size;
1506− }
1507−
1508− return region;
1509−}
1510−
1511−/**
1512− * spi_nor_init_erase_cmd() - initialize an erase command
1513− * @region: pointer to a structure that describes a SPI NOR erase region
1514− * @erase: pointer to a structure that describes a SPI NOR erase type
1515− *
1516− * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
1517− * otherwise.
1518− */
1519−static struct spi_nor_erase_command *
1520−spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,
1521− const struct spi_nor_erase_type *erase)
1522−{
1523− struct spi_nor_erase_command *cmd;
1524−
1525− cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
1526− if (!cmd)
1527− return ERR_PTR(-ENOMEM);
1528−
1529− INIT_LIST_HEAD(&cmd->list);
1530− cmd->opcode = erase->opcode;
1531− cmd->count = 1;
1532−
1533− if (region->offset & SNOR_OVERLAID_REGION)
1534− cmd->size = region->size;
1535− else
1536− cmd->size = erase->size;
1537−
1538− return cmd;
1539−}
1540−
1541−/**
1542− * spi_nor_destroy_erase_cmd_list() - destroy erase command list
1543− * @erase_list: list of erase commands
1544− */
1545−static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)
1546−{
1547− struct spi_nor_erase_command *cmd, *next;
1548−
1549− list_for_each_entry_safe(cmd, next, erase_list, list) {
1550− list_del(&cmd->list);
1551− kfree(cmd);
1552− }
1553−}
1554−
1555−/**
1556− * spi_nor_init_erase_cmd_list() - initialize erase command list
1557− * @nor: pointer to a 'struct spi_nor'
1558− * @erase_list: list of erase commands to be executed once we validate that the
1559− * erase can be performed
1560− * @addr: offset in the serial flash memory
1561− * @len: number of bytes to erase
1562− *
1563− * Builds the list of best fitted erase commands and verifies if the erase can
1564− * be performed.
1565− *
1566− * Return: 0 on success, -errno otherwise.
1567− */
1568−static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
1569− struct list_head *erase_list,
1570− u64 addr, u32 len)
1571−{
1572− const struct spi_nor_erase_map *map = &nor->params.erase_map;
1573− const struct spi_nor_erase_type *erase, *prev_erase = NULL;
1574− struct spi_nor_erase_region *region;
1575− struct spi_nor_erase_command *cmd = NULL;
1576− u64 region_end;
1577− int ret = -EINVAL;
1578−
1579− region = spi_nor_find_erase_region(map, addr);
1580− if (IS_ERR(region))
1581− return PTR_ERR(region);
1582−
1583− region_end = spi_nor_region_end(region);
1584−
1585− while (len) {
1586− erase = spi_nor_find_best_erase_type(map, region, addr, len);
1587− if (!erase)
1588− goto destroy_erase_cmd_list;
1589−
1590− if (prev_erase != erase ||
1591− region->offset & SNOR_OVERLAID_REGION) {
1592− cmd = spi_nor_init_erase_cmd(region, erase);
1593− if (IS_ERR(cmd)) {
1594− ret = PTR_ERR(cmd);
1595− goto destroy_erase_cmd_list;
1596− }
1597−
1598− list_add_tail(&cmd->list, erase_list);
1599− } else {
1600− cmd->count++;
1601− }
1602−
1603− addr += cmd->size;
1604− len -= cmd->size;
1605−
1606− if (len && addr >= region_end) {
1607− region = spi_nor_region_next(region);
1608− if (!region)
1609− goto destroy_erase_cmd_list;
1610− region_end = spi_nor_region_end(region);
1611− }
1612−
1613− prev_erase = erase;
1614− }
1615−
1616− return 0;
1617−
1618−destroy_erase_cmd_list:
1619− spi_nor_destroy_erase_cmd_list(erase_list);
1620− return ret;
1621−}
1622−
1623−/**
1624− * spi_nor_erase_multi_sectors() - perform a non-uniform erase
1625− * @nor: pointer to a 'struct spi_nor'
1626− * @addr: offset in the serial flash memory
1627− * @len: number of bytes to erase
1628− *
1629− * Build a list of best fitted erase commands and execute it once we validate
1630− * that the erase can be performed.
1631− *
1632− * Return: 0 on success, -errno otherwise.
1633− */
1634−static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
1635−{
1636− LIST_HEAD(erase_list);
1637− struct spi_nor_erase_command *cmd, *next;
1638− int ret;
1639−
1640− ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);
1641− if (ret)
1642− return ret;
1643−
1644− list_for_each_entry_safe(cmd, next, &erase_list, list) {
1645− nor->erase_opcode = cmd->opcode;
1646− while (cmd->count) {
1647− ret = spi_nor_write_enable(nor);
1648− if (ret)
1649− goto destroy_erase_cmd_list;
1650−
1651− ret = spi_nor_erase_sector(nor, addr);
1652− if (ret)
1653− goto destroy_erase_cmd_list;
1654−
1655− addr += cmd->size;
1656− cmd->count--;
1657−
1658− ret = spi_nor_wait_till_ready(nor);
1659− if (ret)
1660− goto destroy_erase_cmd_list;
1661− }
1662− list_del(&cmd->list);
1663− kfree(cmd);
1664− }
1665−
1666− return 0;
1667−
1668−destroy_erase_cmd_list:
1669− spi_nor_destroy_erase_cmd_list(&erase_list);
1670− return ret;
1671−}
1672−
1673−/*
1674− * Erase an address range on the nor chip. The address range may extend
1675− * one or more erase sectors. Return an error is there is a problem erasing.
1676− */
1677−static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
1678−{
1679− struct spi_nor *nor = mtd_to_spi_nor(mtd);
1680− u32 addr, len;
1681− uint32_t rem;
1682− int ret;
1683−
1684− dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
1685− (long long)instr->len);
1686−
1687− if (spi_nor_has_uniform_erase(nor)) {
1688− div_u64_rem(instr->len, mtd->erasesize, &rem);
1689− if (rem)
1690− return -EINVAL;
1691− }
1692−
1693− addr = instr->addr;
1694− len = instr->len;
1695−
1696− ret = spi_nor_lock_and_prep(nor);
1697− if (ret)
1698− return ret;
1699−
1700− /* whole-chip erase? */
1701− if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
1702− unsigned long timeout;
1703−
1704− ret = spi_nor_write_enable(nor);
1705− if (ret)
1706− goto erase_err;
1707−
1708− ret = spi_nor_erase_chip(nor);
1709− if (ret)
1710− goto erase_err;
1711−
1712− /*
1713− * Scale the timeout linearly with the size of the flash, with
1714− * a minimum calibrated to an old 2MB flash. We could try to
1715− * pull these from CFI/SFDP, but these values should be good
1716− * enough for now.
1717− */
1718− timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
1719− CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
1720− (unsigned long)(mtd->size / SZ_2M));
1721− ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
1722− if (ret)
1723− goto erase_err;
1724−
1725− /* REVISIT in some cases we could speed up erasing large regions
1726− * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
1727− * to use "small sector erase", but that's not always optimal.
1728− */
1729−
1730− /* "sector"-at-a-time erase */
1731− } else if (spi_nor_has_uniform_erase(nor)) {
1732− while (len) {
1733− ret = spi_nor_write_enable(nor);
1734− if (ret)
1735− goto erase_err;
1736−
1737− ret = spi_nor_erase_sector(nor, addr);
1738− if (ret)
1739− goto erase_err;
1740−
1741− addr += mtd->erasesize;
1742− len -= mtd->erasesize;
1743−
1744− ret = spi_nor_wait_till_ready(nor);
1745− if (ret)
1746− goto erase_err;
1747− }
1748−
1749− /* erase multiple sectors */
1750− } else {
1751− ret = spi_nor_erase_multi_sectors(nor, addr, len);
1752− if (ret)
1753− goto erase_err;
1754− }
1755−
1756− ret = spi_nor_write_disable(nor);
1757−
1758−erase_err:
1759− spi_nor_unlock_and_unprep(nor);
1760−
1761− return ret;
1762−}
1763−
1764−static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
1765− uint64_t *len)
1766−{
1767− struct mtd_info *mtd = &nor->mtd;
1768− u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1769− u8 tb_mask = SR_TB_BIT5;
1770− int shift = ffs(mask) - 1;
1771− int pow;
1772−
1773− if (nor->flags & SNOR_F_HAS_SR_TB_BIT6)
1774− tb_mask = SR_TB_BIT6;
1775−
1776− if (!(sr & mask)) {
1777− /* No protection */
1778− *ofs = 0;
1779− *len = 0;
1780− } else {
1781− pow = ((sr & mask) ^ mask) >> shift;
1782− *len = mtd->size >> pow;
1783− if (nor->flags & SNOR_F_HAS_SR_TB && sr & tb_mask)
1784− *ofs = 0;
1785− else
1786− *ofs = mtd->size - *len;
1787− }
1788−}
1789−
1790−/*
1791− * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
1792− * @locked is false); 0 otherwise
1793− */
1794−static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1795− u8 sr, bool locked)
1796−{
1797− loff_t lock_offs;
1798− uint64_t lock_len;
1799−
1800− if (!len)
1801− return 1;
1802−
1803− stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
1804−
1805− if (locked)
1806− /* Requested range is a sub-range of locked range */
1807− return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
1808− else
1809− /* Requested range does not overlap with locked range */
1810− return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
1811−}
1812−
1813−static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1814− u8 sr)
1815−{
1816− return stm_check_lock_status_sr(nor, ofs, len, sr, true);
1817−}
1818−
1819−static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1820− u8 sr)
1821−{
1822− return stm_check_lock_status_sr(nor, ofs, len, sr, false);
1823−}
1824−
1825−/*
1826− * Lock a region of the flash. Compatible with ST Micro and similar flash.
1827− * Supports the block protection bits BP{0,1,2} in the status register
1828− * (SR). Does not support these features found in newer SR bitfields:
1829− * - SEC: sector/block protect - only handle SEC=0 (block protect)
1830− * - CMP: complement protect - only support CMP=0 (range is not complemented)
1831− *
1832− * Support for the following is provided conditionally for some flash:
1833− * - TB: top/bottom protect
1834− *
1835− * Sample table portion for 8MB flash (Winbond w25q64fw):
1836− *
1837− * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
1838− * --------------------------------------------------------------------------
1839− * X | X | 0 | 0 | 0 | NONE | NONE
1840− * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
1841− * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
1842− * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
1843− * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
1844− * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
1845− * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
1846− * X | X | 1 | 1 | 1 | 8 MB | ALL
1847− * ------|-------|-------|-------|-------|---------------|-------------------
1848− * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
1849− * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
1850− * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
1851− * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
1852− * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
1853− * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
1854− *
1855− * Returns negative on errors, 0 on success.
1856− */
1857−static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1858−{
1859− struct mtd_info *mtd = &nor->mtd;
1860− int ret, status_old, status_new;
1861− u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1862− u8 tb_mask = SR_TB_BIT5;
1863− u8 shift = ffs(mask) - 1, pow, val;
1864− loff_t lock_len;
1865− bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1866− bool use_top;
1867−
1868− ret = spi_nor_read_sr(nor, nor->bouncebuf);
1869− if (ret)
1870− return ret;
1871−
1872− status_old = nor->bouncebuf[0];
1873−
1874− /* If nothing in our range is unlocked, we don't need to do anything */
1875− if (stm_is_locked_sr(nor, ofs, len, status_old))
1876− return 0;
1877−
1878− /* If anything below us is unlocked, we can't use 'bottom' protection */
1879− if (!stm_is_locked_sr(nor, 0, ofs, status_old))
1880− can_be_bottom = false;
1881−
1882− /* If anything above us is unlocked, we can't use 'top' protection */
1883− if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
1884− status_old))
1885− can_be_top = false;
1886−
1887− if (!can_be_bottom && !can_be_top)
1888− return -EINVAL;
1889−
1890− /* Prefer top, if both are valid */
1891− use_top = can_be_top;
1892−
1893− /* lock_len: length of region that should end up locked */
1894− if (use_top)
1895− lock_len = mtd->size - ofs;
1896− else
1897− lock_len = ofs + len;
1898−
1899− if (nor->flags & SNOR_F_HAS_SR_TB_BIT6)
1900− tb_mask = SR_TB_BIT6;
1901−
1902− /*
1903− * Need smallest pow such that:
1904− *
1905− * 1 / (2^pow) <= (len / size)
1906− *
1907− * so (assuming power-of-2 size) we do:
1908− *
1909− * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
1910− */
1911− pow = ilog2(mtd->size) - ilog2(lock_len);
1912− val = mask - (pow << shift);
1913− if (val & ~mask)
1914− return -EINVAL;
1915− /* Don't "lock" with no region! */
1916− if (!(val & mask))
1917− return -EINVAL;
1918−
1919− status_new = (status_old & ~mask & ~tb_mask) | val;
1920−
1921− /* Disallow further writes if WP pin is asserted */
1922− status_new |= SR_SRWD;
1923−
1924− if (!use_top)
1925− status_new |= tb_mask;
1926−
1927− /* Don't bother if they're the same */
1928− if (status_new == status_old)
1929− return 0;
1930−
1931− /* Only modify protection if it will not unlock other areas */
1932− if ((status_new & mask) < (status_old & mask))
1933− return -EINVAL;
1934−
1935− return spi_nor_write_sr_and_check(nor, status_new);
1936−}
1937−
1938−/*
1939− * Unlock a region of the flash. See stm_lock() for more info
1940− *
1941− * Returns negative on errors, 0 on success.
1942− */
1943−static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1944−{
1945− struct mtd_info *mtd = &nor->mtd;
1946− int ret, status_old, status_new;
1947− u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1948− u8 tb_mask = SR_TB_BIT5;
1949− u8 shift = ffs(mask) - 1, pow, val;
1950− loff_t lock_len;
1951− bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1952− bool use_top;
1953−
1954− ret = spi_nor_read_sr(nor, nor->bouncebuf);
1955− if (ret)
1956− return ret;
1957−
1958− status_old = nor->bouncebuf[0];
1959−
1960− /* If nothing in our range is locked, we don't need to do anything */
1961− if (stm_is_unlocked_sr(nor, ofs, len, status_old))
1962− return 0;
1963−
1964− /* If anything below us is locked, we can't use 'top' protection */
1965− if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
1966− can_be_top = false;
1967−
1968− /* If anything above us is locked, we can't use 'bottom' protection */
1969− if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
1970− status_old))
1971− can_be_bottom = false;
1972−
1973− if (!can_be_bottom && !can_be_top)
1974− return -EINVAL;
1975−
1976− /* Prefer top, if both are valid */
1977− use_top = can_be_top;
1978−
1979− /* lock_len: length of region that should remain locked */
1980− if (use_top)
1981− lock_len = mtd->size - (ofs + len);
1982− else
1983− lock_len = ofs;
1984−
1985− if (nor->flags & SNOR_F_HAS_SR_TB_BIT6)
1986− tb_mask = SR_TB_BIT6;
1987− /*
1988− * Need largest pow such that:
1989− *
1990− * 1 / (2^pow) >= (len / size)
1991− *
1992− * so (assuming power-of-2 size) we do:
1993− *
1994− * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
1995− */
1996− pow = ilog2(mtd->size) - order_base_2(lock_len);
1997− if (lock_len == 0) {
1998− val = 0; /* fully unlocked */
1999− } else {
2000− val = mask - (pow << shift);
2001− /* Some power-of-two sizes are not supported */
2002− if (val & ~mask)
2003− return -EINVAL;
2004− }
2005−
2006− status_new = (status_old & ~mask & ~tb_mask) | val;
2007−
2008− /* Don't protect status register if we're fully unlocked */
2009− if (lock_len == 0)
2010− status_new &= ~SR_SRWD;
2011−
2012− if (!use_top)
2013− status_new |= tb_mask;
2014−
2015− /* Don't bother if they're the same */
2016− if (status_new == status_old)
2017− return 0;
2018−
2019− /* Only modify protection if it will not lock other areas */
2020− if ((status_new & mask) > (status_old & mask))
2021− return -EINVAL;
2022−
2023− return spi_nor_write_sr_and_check(nor, status_new);
2024−}
2025−
2026−/*
2027− * Check if a region of the flash is (completely) locked. See stm_lock() for
2028− * more info.
2029− *
2030− * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
2031− * negative on errors.
2032− */
2033−static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
2034−{
2035− int ret;
2036−
2037− ret = spi_nor_read_sr(nor, nor->bouncebuf);
2038− if (ret)
2039− return ret;
2040−
2041− return stm_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]);
2042−}
2043−
2044−static const struct spi_nor_locking_ops stm_locking_ops = {
2045− .lock = stm_lock,
2046− .unlock = stm_unlock,
2047− .is_locked = stm_is_locked,
2048−};
2049−
2050−static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2051−{
2052− struct spi_nor *nor = mtd_to_spi_nor(mtd);
2053− int ret;
2054−
2055− ret = spi_nor_lock_and_prep(nor);
2056− if (ret)
2057− return ret;
2058−
2059− ret = nor->params.locking_ops->lock(nor, ofs, len);
2060−
2061− spi_nor_unlock_and_unprep(nor);
2062− return ret;
2063−}
2064−
2065−static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2066−{
2067− struct spi_nor *nor = mtd_to_spi_nor(mtd);
2068− int ret;
2069−
2070− ret = spi_nor_lock_and_prep(nor);
2071− if (ret)
2072− return ret;
2073−
2074− ret = nor->params.locking_ops->unlock(nor, ofs, len);
2075−
2076− spi_nor_unlock_and_unprep(nor);
2077− return ret;
2078−}
2079−
2080−static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2081−{
2082− struct spi_nor *nor = mtd_to_spi_nor(mtd);
2083− int ret;
2084−
2085− ret = spi_nor_lock_and_prep(nor);
2086− if (ret)
2087− return ret;
2088−
2089− ret = nor->params.locking_ops->is_locked(nor, ofs, len);
2090−
2091− spi_nor_unlock_and_unprep(nor);
2092− return ret;
2093−}
2094−
2095−/**
2096− * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
2097− * Register 1.
2098− * @nor: pointer to a 'struct spi_nor'
2099− *
2100− * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
2101− *
2102− * Return: 0 on success, -errno otherwise.
2103− */
2104−static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
2105−{
2106− int ret;
2107−
2108− ret = spi_nor_read_sr(nor, nor->bouncebuf);
2109− if (ret)
2110− return ret;
2111−
2112− if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
2113− return 0;
2114−
2115− nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
2116−
2117− return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
2118−}
2119−
2120−/**
2121− * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
2122− * Register 2.
2123− * @nor: pointer to a 'struct spi_nor'.
2124− *
2125− * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
2126− *
2127− * Return: 0 on success, -errno otherwise.
2128− */
2129−static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
2130−{
2131− int ret;
2132−
2133− if (nor->flags & SNOR_F_NO_READ_CR)
2134− return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
2135−
2136− ret = spi_nor_read_cr(nor, nor->bouncebuf);
2137− if (ret)
2138− return ret;
2139−
2140− if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
2141− return 0;
2142−
2143− nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
2144−
2145− return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
2146−}
2147−
2148−/**
2149− * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
2150− * @nor: pointer to a 'struct spi_nor'
2151− *
2152− * Set the Quad Enable (QE) bit in the Status Register 2.
2153− *
2154− * This is one of the procedures to set the QE bit described in the SFDP
2155− * (JESD216 rev B) specification but no manufacturer using this procedure has
2156− * been identified yet, hence the name of the function.
2157− *
2158− * Return: 0 on success, -errno otherwise.
2159− */
2160−static int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
2161−{
2162− u8 *sr2 = nor->bouncebuf;
2163− int ret;
2164− u8 sr2_written;
2165−
2166− /* Check current Quad Enable bit value. */
2167− ret = spi_nor_read_sr2(nor, sr2);
2168− if (ret)
2169− return ret;
2170− if (*sr2 & SR2_QUAD_EN_BIT7)
2171− return 0;
2172−
2173− /* Update the Quad Enable bit. */
2174− *sr2 |= SR2_QUAD_EN_BIT7;
2175−
2176− ret = spi_nor_write_sr2(nor, sr2);
2177− if (ret)
2178− return ret;
2179−
2180− sr2_written = *sr2;
2181−
2182− /* Read back and check it. */
2183− ret = spi_nor_read_sr2(nor, sr2);
2184− if (ret)
2185− return ret;
2186−
2187− if (*sr2 != sr2_written) {
2188− dev_dbg(nor->dev, "SR2: Read back test failed\n");
2189− return -EIO;
2190− }
2191−
2192− return 0;
2193−}
2194−
2195−/* Used when the "_ext_id" is two bytes at most */
2196−#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
2197− .id = { \
2198− ((_jedec_id) >> 16) & 0xff, \
2199− ((_jedec_id) >> 8) & 0xff, \
2200− (_jedec_id) & 0xff, \
2201− ((_ext_id) >> 8) & 0xff, \
2202− (_ext_id) & 0xff, \
2203− }, \
2204− .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
2205− .sector_size = (_sector_size), \
2206− .n_sectors = (_n_sectors), \
2207− .page_size = 256, \
2208− .flags = (_flags),
2209−
2210−#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
2211− .id = { \
2212− ((_jedec_id) >> 16) & 0xff, \
2213− ((_jedec_id) >> 8) & 0xff, \
2214− (_jedec_id) & 0xff, \
2215− ((_ext_id) >> 16) & 0xff, \
2216− ((_ext_id) >> 8) & 0xff, \
2217− (_ext_id) & 0xff, \
2218− }, \
2219− .id_len = 6, \
2220− .sector_size = (_sector_size), \
2221− .n_sectors = (_n_sectors), \
2222− .page_size = 256, \
2223− .flags = (_flags),
2224−
2225−#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
2226− .sector_size = (_sector_size), \
2227− .n_sectors = (_n_sectors), \
2228− .page_size = (_page_size), \
2229− .addr_width = (_addr_width), \
2230− .flags = (_flags),
2231−
2232−#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
2233− .id = { \
2234− ((_jedec_id) >> 16) & 0xff, \
2235− ((_jedec_id) >> 8) & 0xff, \
2236− (_jedec_id) & 0xff \
2237− }, \
2238− .id_len = 3, \
2239− .sector_size = (8*_page_size), \
2240− .n_sectors = (_n_sectors), \
2241− .page_size = _page_size, \
2242− .addr_width = 3, \
2243− .flags = SPI_NOR_NO_FR | SPI_S3AN,
2244−
2245−static int
2246−is25lp256_post_bfpt_fixups(struct spi_nor *nor,
2247− const struct sfdp_parameter_header *bfpt_header,
2248− const struct sfdp_bfpt *bfpt,
2249− struct spi_nor_flash_parameter *params)
2250−{
2251− /*
2252− * IS25LP256 supports 4B opcodes, but the BFPT advertises a
2253− * BFPT_DWORD1_ADDRESS_BYTES_3_ONLY address width.
2254− * Overwrite the address width advertised by the BFPT.
2255− */
2256− if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==
2257− BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)
2258− nor->addr_width = 4;
2259−
2260− return 0;
2261−}
2262−
2263−static struct spi_nor_fixups is25lp256_fixups = {
2264− .post_bfpt = is25lp256_post_bfpt_fixups,
2265−};
2266−
2267−static int
2268−mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
2269− const struct sfdp_parameter_header *bfpt_header,
2270− const struct sfdp_bfpt *bfpt,
2271− struct spi_nor_flash_parameter *params)
2272−{
2273− /*
2274− * MX25L25635F supports 4B opcodes but MX25L25635E does not.
2275− * Unfortunately, Macronix has re-used the same JEDEC ID for both
2276− * variants which prevents us from defining a new entry in the parts
2277− * table.
2278− * We need a way to differentiate MX25L25635E and MX25L25635F, and it
2279− * seems that the F version advertises support for Fast Read 4-4-4 in
2280− * its BFPT table.
2281− */
2282− if (bfpt->dwords[BFPT_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4)
2283− nor->flags |= SNOR_F_4B_OPCODES;
2284−
2285− return 0;
2286−}
2287−
2288−static struct spi_nor_fixups mx25l25635_fixups = {
2289− .post_bfpt = mx25l25635_post_bfpt_fixups,
2290−};
2291−
2292−static void gd25q256_default_init(struct spi_nor *nor)
2293−{
2294− /*
2295− * Some manufacturer like GigaDevice may use different
2296− * bit to set QE on different memories, so the MFR can't
2297− * indicate the quad_enable method for this case, we need
2298− * to set it in the default_init fixup hook.
2299− */
2300− nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable;
2301−}
2302−
2303−static struct spi_nor_fixups gd25q256_fixups = {
2304− .default_init = gd25q256_default_init,
2305−};
2306−
2307−/* NOTE: double check command sets and memory organization when you add
2308− * more nor chips. This current list focusses on newer chips, which
2309− * have been converging on command sets which including JEDEC ID.
2310− *
2311− * All newly added entries should describe *hardware* and should use SECT_4K
2312− * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
2313− * scenarios excluding small sectors there is config option that can be
2314− * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
2315− * For historical (and compatibility) reasons (before we got above config) some
2316− * old entries may be missing 4K flag.
2317− */
2318−static const struct flash_info spi_nor_ids[] = {
2319− /* Atmel -- some are (confusingly) marketed as "DataFlash" */
2320− { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
2321− { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
2322−
2323− { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
2324− { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
2325− { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
2326− { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
2327−
2328− { "at25sl321", INFO(0x1f4216, 0, 64 * 1024, 64,
2329− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2330−
2331− { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
2332− { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
2333− { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
2334− { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
2335−
2336− { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
2337−
2338− /* EON -- en25xxx */
2339− { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
2340− { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
2341− { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
2342− { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
2343− { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
2344− { "en25q80a", INFO(0x1c3014, 0, 64 * 1024, 16,
2345− SECT_4K | SPI_NOR_DUAL_READ) },
2346− { "en25qh16", INFO(0x1c7015, 0, 64 * 1024, 32,
2347− SECT_4K | SPI_NOR_DUAL_READ) },
2348− { "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) },
2349− { "en25qh64", INFO(0x1c7017, 0, 64 * 1024, 128,
2350− SECT_4K | SPI_NOR_DUAL_READ) },
2351− { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
2352− { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
2353− { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
2354−
2355− /* ESMT */
2356− { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
2357− { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
2358− { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
2359−
2360− /* Everspin */
2361− { "mr25h128", CAT25_INFO( 16 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2362− { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2363− { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2364− { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2365−
2366− /* Fujitsu */
2367− { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
2368−
2369− /* GigaDevice */
2370− {
2371− "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
2372− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2373− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2374− },
2375− {
2376− "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
2377− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2378− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2379− },
2380− {
2381− "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
2382− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2383− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2384− },
2385− {
2386− "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
2387− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2388− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2389− },
2390− {
2391− "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
2392− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2393− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2394− },
2395− {
2396− "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256,
2397− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2398− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2399− },
2400− {
2401− "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
2402− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2403− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2404− },
2405− {
2406− "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
2407− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2408− SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
2409− SPI_NOR_TB_SR_BIT6)
2410− .fixups = &gd25q256_fixups,
2411− },
2412−
2413− /* Intel/Numonyx -- xxxs33b */
2414− { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
2415− { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
2416− { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
2417−
2418− /* ISSI */
2419− { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
2420− { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
2421− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2422− { "is25lp016d", INFO(0x9d6015, 0, 64 * 1024, 32,
2423− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2424− { "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16,
2425− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2426− { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64,
2427− SECT_4K | SPI_NOR_DUAL_READ) },
2428− { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128,
2429− SECT_4K | SPI_NOR_DUAL_READ) },
2430− { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
2431− SECT_4K | SPI_NOR_DUAL_READ) },
2432− { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
2433− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2434− SPI_NOR_4B_OPCODES)
2435− .fixups = &is25lp256_fixups },
2436− { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
2437− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2438− { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
2439− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2440− { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
2441− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2442− { "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512,
2443− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2444− SPI_NOR_4B_OPCODES)
2445− .fixups = &is25lp256_fixups },
2446−
2447− /* Macronix */
2448− { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
2449− { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
2450− { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
2451− { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
2452− { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
2453− { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
2454− { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
2455− { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
2456− { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
2457− { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64,
2458− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2459− { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
2460− { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
2461− { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
2462− { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
2463− { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
2464− { "mx25r3235f", INFO(0xc22816, 0, 64 * 1024, 64,
2465− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2466− { "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
2467− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2468− { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
2469− SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
2470− .fixups = &mx25l25635_fixups },
2471− { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
2472− { "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16,
2473− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2474− { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
2475− { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2476− { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2477− { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2478− { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
2479−
2480− /* Micron <--> ST Micro */
2481− { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
2482− { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
2483− { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
2484− { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
2485− { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
2486− { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K |
2487− USE_FSR | SPI_NOR_QUAD_READ) },
2488− { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K |
2489− USE_FSR | SPI_NOR_QUAD_READ) },
2490− { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
2491− SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
2492− SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2493− { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
2494− USE_FSR | SPI_NOR_DUAL_READ |
2495− SPI_NOR_QUAD_READ) },
2496− { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512,
2497− SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
2498− SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2499− { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K |
2500− USE_FSR | SPI_NOR_QUAD_READ) },
2501− { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
2502− SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
2503− SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2504− { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
2505− { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
2506− SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
2507− SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2508− { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
2509− USE_FSR | SPI_NOR_QUAD_READ) },
2510− { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
2511− { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
2512− { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
2513− SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
2514− NO_CHIP_ERASE) },
2515− { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
2516−
2517− /* Micron */
2518− {
2519− "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
2520− SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
2521− SPI_NOR_4B_OPCODES)
2522− },
2523− { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048,
2524− SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
2525− SPI_NOR_4B_OPCODES) },
2526−
2527− /* PMC */
2528− { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
2529− { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
2530− { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
2531−
2532− /* Spansion/Cypress -- single (large) sector size only, at least
2533− * for the chips listed here (without boot sectors).
2534− */
2535− { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2536− { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2537− { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
2538− SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2539− { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
2540− SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2541− { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
2542− { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2543− { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
2544− SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2545− SPI_NOR_HAS_LOCK | USE_CLSR) },
2546− { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2547− { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
2548− { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
2549− { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
2550− { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2551− { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2552− { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
2553− { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
2554− { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
2555− { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
2556− { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
2557− { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2558− { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2559− { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2560− { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
2561− { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2562− { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
2563− { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
2564− { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
2565− { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
2566− { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2567− { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2568− { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2569−
2570− /* SST -- large erase sizes are "overlays", "sectors" are 4K */
2571− { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
2572− { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
2573− { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
2574− { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
2575− { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
2576− { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
2577− { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
2578− { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
2579− { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
2580− { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
2581− { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
2582− { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
2583− { "sst26wf016b", INFO(0xbf2651, 0, 64 * 1024, 32, SECT_4K |
2584− SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2585− { "sst26vf016b", INFO(0xbf2641, 0, 64 * 1024, 32, SECT_4K |
2586− SPI_NOR_DUAL_READ) },
2587− { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2588−
2589− /* ST Microelectronics -- newer production may have feature updates */
2590− { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
2591− { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
2592− { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
2593− { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
2594− { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
2595− { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
2596− { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
2597− { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
2598− { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
2599−
2600− { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
2601− { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
2602− { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
2603− { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
2604− { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
2605− { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
2606− { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
2607− { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
2608− { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
2609−
2610− { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
2611− { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
2612− { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
2613−
2614− { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
2615− { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
2616− { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
2617−
2618− { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
2619− { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
2620− { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
2621− { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
2622− { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
2623− { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
2624−
2625− /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
2626− { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
2627− { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
2628− { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
2629− { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
2630− { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
2631− { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
2632− {
2633− "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
2634− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2635− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2636− },
2637− { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
2638− {
2639− "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024, 32,
2640− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2641− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2642− },
2643− { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
2644− { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
2645− { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
2646− { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
2647− {
2648− "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
2649− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2650− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2651− },
2652− {
2653− "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
2654− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2655− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2656− },
2657− {
2658− "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64,
2659− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2660− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2661− },
2662− { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
2663− { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
2664− {
2665− "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
2666− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2667− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2668− },
2669− {
2670− "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
2671− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2672− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2673− },
2674− {
2675− "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256,
2676− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2677− SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2678− },
2679− { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
2680− { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
2681− { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
2682− { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512,
2683− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2684− SPI_NOR_4B_OPCODES) },
2685− { "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512,
2686− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2687− { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512,
2688− SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2689− { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
2690− SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
2691−
2692− /* Catalyst / On Semiconductor -- non-JEDEC */
2693− { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2694− { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2695− { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2696− { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2697− { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2698−
2699− /* Xilinx S3AN Internal Flash */
2700− { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
2701− { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
2702− { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
2703− { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
2704− { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
2705−
2706− /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
2707− { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2708− { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2709− { },
2710−};
2711−
2712−static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
2713−{
2714− int tmp;
2715− u8 *id = nor->bouncebuf;
2716− const struct flash_info *info;
2717−
2718− if (nor->spimem) {
2719− struct spi_mem_op op =
2720− SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1),
2721− SPI_MEM_OP_NO_ADDR,
2722− SPI_MEM_OP_NO_DUMMY,
2723− SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, id, 1));
2724−
2725− tmp = spi_mem_exec_op(nor->spimem, &op);
2726− } else {
2727− tmp = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
2728− SPI_NOR_MAX_ID_LEN);
2729− }
2730− if (tmp) {
2731− dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
2732− return ERR_PTR(tmp);
2733− }
2734−
2735− for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
2736− info = &spi_nor_ids[tmp];
2737− if (info->id_len) {
2738− if (!memcmp(info->id, id, info->id_len))
2739− return &spi_nor_ids[tmp];
2740− }
2741− }
2742− dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
2743− SPI_NOR_MAX_ID_LEN, id);
2744− return ERR_PTR(-ENODEV);
2745−}
2746−
2747−static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
2748− size_t *retlen, u_char *buf)
2749−{
2750− struct spi_nor *nor = mtd_to_spi_nor(mtd);
2751− ssize_t ret;
2752−
2753− dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
2754−
2755− ret = spi_nor_lock_and_prep(nor);
2756− if (ret)
2757− return ret;
2758−
2759− while (len) {
2760− loff_t addr = from;
2761−
2762− addr = spi_nor_convert_addr(nor, addr);
2763−
2764− ret = spi_nor_read_data(nor, addr, len, buf);
2765− if (ret == 0) {
2766− /* We shouldn't see 0-length reads */
2767− ret = -EIO;
2768− goto read_err;
2769− }
2770− if (ret < 0)
2771− goto read_err;
2772−
2773− WARN_ON(ret > len);
2774− *retlen += ret;
2775− buf += ret;
2776− from += ret;
2777− len -= ret;
2778− }
2779− ret = 0;
2780−
2781−read_err:
2782− spi_nor_unlock_and_unprep(nor);
2783− return ret;
2784−}
2785−
2786−static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
2787− size_t *retlen, const u_char *buf)
2788−{
2789− struct spi_nor *nor = mtd_to_spi_nor(mtd);
2790− size_t actual = 0;
2791− int ret;
2792−
2793− dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
2794−
2795− ret = spi_nor_lock_and_prep(nor);
2796− if (ret)
2797− return ret;
2798−
2799− ret = spi_nor_write_enable(nor);
2800− if (ret)
2801− goto out;
2802−
2803− nor->sst_write_second = false;
2804−
2805− /* Start write from odd address. */
2806− if (to % 2) {
2807− nor->program_opcode = SPINOR_OP_BP;
2808−
2809− /* write one byte. */
2810− ret = spi_nor_write_data(nor, to, 1, buf);
2811− if (ret < 0)
2812− goto out;
2813− WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret);
2814− ret = spi_nor_wait_till_ready(nor);
2815− if (ret)
2816− goto out;
2817−
2818− to++;
2819− actual++;
2820− }
2821−
2822− /* Write out most of the data here. */
2823− for (; actual < len - 1; actual += 2) {
2824− nor->program_opcode = SPINOR_OP_AAI_WP;
2825−
2826− /* write two bytes. */
2827− ret = spi_nor_write_data(nor, to, 2, buf + actual);
2828− if (ret < 0)
2829− goto out;
2830− WARN(ret != 2, "While writing 2 bytes written %i bytes\n", ret);
2831− ret = spi_nor_wait_till_ready(nor);
2832− if (ret)
2833− goto out;
2834− to += 2;
2835− nor->sst_write_second = true;
2836− }
2837− nor->sst_write_second = false;
2838−
2839− ret = spi_nor_write_disable(nor);
2840− if (ret)
2841− goto out;
2842−
2843− ret = spi_nor_wait_till_ready(nor);
2844− if (ret)
2845− goto out;
2846−
2847− /* Write out trailing byte if it exists. */
2848− if (actual != len) {
2849− ret = spi_nor_write_enable(nor);
2850− if (ret)
2851− goto out;
2852−
2853− nor->program_opcode = SPINOR_OP_BP;
2854− ret = spi_nor_write_data(nor, to, 1, buf + actual);
2855− if (ret < 0)
2856− goto out;
2857− WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret);
2858− ret = spi_nor_wait_till_ready(nor);
2859− if (ret)
2860− goto out;
2861−
2862− actual += 1;
2863−
2864− ret = spi_nor_write_disable(nor);
2865− }
2866−out:
2867− *retlen += actual;
2868− spi_nor_unlock_and_unprep(nor);
2869− return ret;
2870−}
2871−
2872−/*
2873− * Write an address range to the nor chip. Data must be written in
2874− * FLASH_PAGESIZE chunks. The address range may be any size provided
2875− * it is within the physical boundaries.
2876− */
2877−static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
2878− size_t *retlen, const u_char *buf)
2879−{
2880− struct spi_nor *nor = mtd_to_spi_nor(mtd);
2881− size_t page_offset, page_remain, i;
2882− ssize_t ret;
2883−
2884− dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
2885−
2886− ret = spi_nor_lock_and_prep(nor);
2887− if (ret)
2888− return ret;
2889−
2890− for (i = 0; i < len; ) {
2891− ssize_t written;
2892− loff_t addr = to + i;
2893−
2894− /*
2895− * If page_size is a power of two, the offset can be quickly
2896− * calculated with an AND operation. On the other cases we
2897− * need to do a modulus operation (more expensive).
2898− * Power of two numbers have only one bit set and we can use
2899− * the instruction hweight32 to detect if we need to do a
2900− * modulus (do_div()) or not.
2901− */
2902− if (hweight32(nor->page_size) == 1) {
2903− page_offset = addr & (nor->page_size - 1);
2904− } else {
2905− uint64_t aux = addr;
2906−
2907− page_offset = do_div(aux, nor->page_size);
2908− }
2909− /* the size of data remaining on the first page */
2910− page_remain = min_t(size_t,
2911− nor->page_size - page_offset, len - i);
2912−
2913− addr = spi_nor_convert_addr(nor, addr);
2914−
2915− ret = spi_nor_write_enable(nor);
2916− if (ret)
2917− goto write_err;
2918−
2919− ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
2920− if (ret < 0)
2921− goto write_err;
2922− written = ret;
2923−
2924− ret = spi_nor_wait_till_ready(nor);
2925− if (ret)
2926− goto write_err;
2927− *retlen += written;
2928− i += written;
2929− }
2930−
2931−write_err:
2932− spi_nor_unlock_and_unprep(nor);
2933− return ret;
2934−}
2935−
2936−static int spi_nor_check(struct spi_nor *nor)
2937−{
2938− if (!nor->dev ||
2939− (!nor->spimem && !nor->controller_ops) ||
2940− (!nor->spimem && nor->controller_ops &&
2941− (!nor->controller_ops->read ||
2942− !nor->controller_ops->write ||
2943− !nor->controller_ops->read_reg ||
2944− !nor->controller_ops->write_reg))) {
2945− pr_err("spi-nor: please fill all the necessary fields!\n");
2946− return -EINVAL;
2947− }
2948−
2949− if (nor->spimem && nor->controller_ops) {
2950− dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n");
2951− return -EINVAL;
2952− }
2953−
2954− return 0;
2955−}
2956−
2957−static int s3an_nor_setup(struct spi_nor *nor,
2958− const struct spi_nor_hwcaps *hwcaps)
2959−{
2960− int ret;
2961−
2962− ret = spi_nor_xread_sr(nor, nor->bouncebuf);
2963− if (ret)
2964− return ret;
2965−
2966− nor->erase_opcode = SPINOR_OP_XSE;
2967− nor->program_opcode = SPINOR_OP_XPP;
2968− nor->read_opcode = SPINOR_OP_READ;
2969− nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2970−
2971− /*
2972− * This flashes have a page size of 264 or 528 bytes (known as
2973− * Default addressing mode). It can be changed to a more standard
2974− * Power of two mode where the page size is 256/512. This comes
2975− * with a price: there is 3% less of space, the data is corrupted
2976− * and the page size cannot be changed back to default addressing
2977− * mode.
2978− *
2979− * The current addressing mode can be read from the XRDSR register
2980− * and should not be changed, because is a destructive operation.
2981− */
2982− if (nor->bouncebuf[0] & XSR_PAGESIZE) {
2983− /* Flash in Power of 2 mode */
2984− nor->page_size = (nor->page_size == 264) ? 256 : 512;
2985− nor->mtd.writebufsize = nor->page_size;
2986− nor->mtd.size = 8 * nor->page_size * nor->info->n_sectors;
2987− nor->mtd.erasesize = 8 * nor->page_size;
2988− } else {
2989− /* Flash in Default addressing mode */
2990− nor->params.convert_addr = s3an_convert_addr;
2991− nor->mtd.erasesize = nor->info->sector_size;
2992− }
2993−
2994− return 0;
2995−}
2996−
2997−static void
2998−spi_nor_set_read_settings(struct spi_nor_read_command *read,
2999− u8 num_mode_clocks,
3000− u8 num_wait_states,
3001− u8 opcode,
3002− enum spi_nor_protocol proto)
3003−{
3004− read->num_mode_clocks = num_mode_clocks;
3005− read->num_wait_states = num_wait_states;
3006− read->opcode = opcode;
3007− read->proto = proto;
3008−}
3009−
3010−static void
3011−spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
3012− u8 opcode,
3013− enum spi_nor_protocol proto)
3014−{
3015− pp->opcode = opcode;
3016− pp->proto = proto;
3017−}
3018−
3019−static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
3020−{
3021− size_t i;
3022−
3023− for (i = 0; i < size; i++)
3024− if (table[i][0] == (int)hwcaps)
3025− return table[i][1];
3026−
3027− return -EINVAL;
3028−}
3029−
3030−static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
3031−{
3032− static const int hwcaps_read2cmd[][2] = {
3033− { SNOR_HWCAPS_READ, SNOR_CMD_READ },
3034− { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
3035− { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
3036− { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
3037− { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
3038− { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
3039− { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
3040− { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
3041− { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
3042− { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
3043− { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
3044− { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
3045− { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
3046− { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
3047− { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
3048− };
3049−
3050− return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
3051− ARRAY_SIZE(hwcaps_read2cmd));
3052−}
3053−
3054−static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
3055−{
3056− static const int hwcaps_pp2cmd[][2] = {
3057− { SNOR_HWCAPS_PP, SNOR_CMD_PP },
3058− { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
3059− { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
3060− { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
3061− { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
3062− { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
3063− { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
3064− };
3065−
3066− return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
3067− ARRAY_SIZE(hwcaps_pp2cmd));
3068−}
3069−
3070−/*
3071− * Serial Flash Discoverable Parameters (SFDP) parsing.
3072− */
3073−
3074−/**
3075− * spi_nor_read_raw() - raw read of serial flash memory. read_opcode,
3076− * addr_width and read_dummy members of the struct spi_nor
3077− * should be previously
3078− * set.
3079− * @nor: pointer to a 'struct spi_nor'
3080− * @addr: offset in the serial flash memory
3081− * @len: number of bytes to read
3082− * @buf: buffer where the data is copied into (dma-safe memory)
3083− *
3084− * Return: 0 on success, -errno otherwise.
3085− */
3086−static int spi_nor_read_raw(struct spi_nor *nor, u32 addr, size_t len, u8 *buf)
3087−{
3088− ssize_t ret;
3089−
3090− while (len) {
3091− ret = spi_nor_read_data(nor, addr, len, buf);
3092− if (ret < 0)
3093− return ret;
3094− if (!ret || ret > len)
3095− return -EIO;
3096−
3097− buf += ret;
3098− addr += ret;
3099− len -= ret;
3100− }
3101− return 0;
3102−}
3103−
3104−/**
3105− * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
3106− * @nor: pointer to a 'struct spi_nor'
3107− * @addr: offset in the SFDP area to start reading data from
3108− * @len: number of bytes to read
3109− * @buf: buffer where the SFDP data are copied into (dma-safe memory)
3110− *
3111− * Whatever the actual numbers of bytes for address and dummy cycles are
3112− * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
3113− * followed by a 3-byte address and 8 dummy clock cycles.
3114− *
3115− * Return: 0 on success, -errno otherwise.
3116− */
3117−static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
3118− size_t len, void *buf)
3119−{
3120− u8 addr_width, read_opcode, read_dummy;
3121− int ret;
3122−
3123− read_opcode = nor->read_opcode;
3124− addr_width = nor->addr_width;
3125− read_dummy = nor->read_dummy;
3126−
3127− nor->read_opcode = SPINOR_OP_RDSFDP;
3128− nor->addr_width = 3;
3129− nor->read_dummy = 8;
3130−
3131− ret = spi_nor_read_raw(nor, addr, len, buf);
3132−
3133− nor->read_opcode = read_opcode;
3134− nor->addr_width = addr_width;
3135− nor->read_dummy = read_dummy;
3136−
3137− return ret;
3138−}
3139−
3140−/**
3141− * spi_nor_spimem_check_op - check if the operation is supported
3142− * by controller
3143− *@nor: pointer to a 'struct spi_nor'
3144− *@op: pointer to op template to be checked
3145− *
3146− * Returns 0 if operation is supported, -ENOTSUPP otherwise.
3147− */
3148−static int spi_nor_spimem_check_op(struct spi_nor *nor,
3149− struct spi_mem_op *op)
3150−{
3151− /*
3152− * First test with 4 address bytes. The opcode itself might
3153− * be a 3B addressing opcode but we don't care, because
3154− * SPI controller implementation should not check the opcode,
3155− * but just the sequence.
3156− */
3157− op->addr.nbytes = 4;
3158− if (!spi_mem_supports_op(nor->spimem, op)) {
3159− if (nor->mtd.size > SZ_16M)
3160− return -ENOTSUPP;
3161−
3162− /* If flash size <= 16MB, 3 address bytes are sufficient */
3163− op->addr.nbytes = 3;
3164− if (!spi_mem_supports_op(nor->spimem, op))
3165− return -ENOTSUPP;
3166− }
3167−
3168− return 0;
3169−}
3170−
3171−/**
3172− * spi_nor_spimem_check_readop - check if the read op is supported
3173− * by controller
3174− *@nor: pointer to a 'struct spi_nor'
3175− *@read: pointer to op template to be checked
3176− *
3177− * Returns 0 if operation is supported, -ENOTSUPP otherwise.
3178− */
3179−static int spi_nor_spimem_check_readop(struct spi_nor *nor,
3180− const struct spi_nor_read_command *read)
3181−{
3182− struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 1),
3183− SPI_MEM_OP_ADDR(3, 0, 1),
3184− SPI_MEM_OP_DUMMY(0, 1),
3185− SPI_MEM_OP_DATA_IN(0, NULL, 1));
3186−
3187− op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(read->proto);
3188− op.addr.buswidth = spi_nor_get_protocol_addr_nbits(read->proto);
3189− op.data.buswidth = spi_nor_get_protocol_data_nbits(read->proto);
3190− op.dummy.buswidth = op.addr.buswidth;
3191− op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
3192− op.dummy.buswidth / 8;
3193−
3194− return spi_nor_spimem_check_op(nor, &op);
3195−}
3196−
3197−/**
3198− * spi_nor_spimem_check_pp - check if the page program op is supported
3199− * by controller
3200− *@nor: pointer to a 'struct spi_nor'
3201− *@pp: pointer to op template to be checked
3202− *
3203− * Returns 0 if operation is supported, -ENOTSUPP otherwise.
3204− */
3205−static int spi_nor_spimem_check_pp(struct spi_nor *nor,
3206− const struct spi_nor_pp_command *pp)
3207−{
3208− struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 1),
3209− SPI_MEM_OP_ADDR(3, 0, 1),
3210− SPI_MEM_OP_NO_DUMMY,
3211− SPI_MEM_OP_DATA_OUT(0, NULL, 1));
3212−
3213− op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(pp->proto);
3214− op.addr.buswidth = spi_nor_get_protocol_addr_nbits(pp->proto);
3215− op.data.buswidth = spi_nor_get_protocol_data_nbits(pp->proto);
3216−
3217− return spi_nor_spimem_check_op(nor, &op);
3218−}
3219−
3220−/**
3221− * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol
3222− * based on SPI controller capabilities
3223− * @nor: pointer to a 'struct spi_nor'
3224− * @hwcaps: pointer to resulting capabilities after adjusting
3225− * according to controller and flash's capability
3226− */
3227−static void
3228−spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
3229−{
3230− struct spi_nor_flash_parameter *params = &nor->params;
3231− unsigned int cap;
3232−
3233− /* DTR modes are not supported yet, mask them all. */
3234− *hwcaps &= ~SNOR_HWCAPS_DTR;
3235−
3236− /* X-X-X modes are not supported yet, mask them all. */
3237− *hwcaps &= ~SNOR_HWCAPS_X_X_X;
3238−
3239− for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
3240− int rdidx, ppidx;
3241−
3242− if (!(*hwcaps & BIT(cap)))
3243− continue;
3244−
3245− rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
3246− if (rdidx >= 0 &&
3247− spi_nor_spimem_check_readop(nor, &params->reads[rdidx]))
3248− *hwcaps &= ~BIT(cap);
3249−
3250− ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
3251− if (ppidx < 0)
3252− continue;
3253−
3254− if (spi_nor_spimem_check_pp(nor,
3255− &params->page_programs[ppidx]))
3256− *hwcaps &= ~BIT(cap);
3257− }
3258−}
3259−
3260−/**
3261− * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters.
3262− * @nor: pointer to a 'struct spi_nor'
3263− * @addr: offset in the SFDP area to start reading data from
3264− * @len: number of bytes to read
3265− * @buf: buffer where the SFDP data are copied into
3266− *
3267− * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not
3268− * guaranteed to be dma-safe.
3269− *
3270− * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp()
3271− * otherwise.
3272− */
3273−static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr,
3274− size_t len, void *buf)
3275−{
3276− void *dma_safe_buf;
3277− int ret;
3278−
3279− dma_safe_buf = kmalloc(len, GFP_KERNEL);
3280− if (!dma_safe_buf)
3281− return -ENOMEM;
3282−
3283− ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf);
3284− memcpy(buf, dma_safe_buf, len);
3285− kfree(dma_safe_buf);
3286−
3287− return ret;
3288−}
3289−
3290−/* Fast Read settings. */
3291−
3292−static void
3293−spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
3294− u16 half,
3295− enum spi_nor_protocol proto)
3296−{
3297− read->num_mode_clocks = (half >> 5) & 0x07;
3298− read->num_wait_states = (half >> 0) & 0x1f;
3299− read->opcode = (half >> 8) & 0xff;
3300− read->proto = proto;
3301−}
3302−
3303−struct sfdp_bfpt_read {
3304− /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
3305− u32 hwcaps;
3306−
3307− /*
3308− * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
3309− * whether the Fast Read x-y-z command is supported.
3310− */
3311− u32 supported_dword;
3312− u32 supported_bit;
3313−
3314− /*
3315− * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
3316− * encodes the op code, the number of mode clocks and the number of wait
3317− * states to be used by Fast Read x-y-z command.
3318− */
3319− u32 settings_dword;
3320− u32 settings_shift;
3321−
3322− /* The SPI protocol for this Fast Read x-y-z command. */
3323− enum spi_nor_protocol proto;
3324−};
3325−
3326−static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
3327− /* Fast Read 1-1-2 */
3328− {
3329− SNOR_HWCAPS_READ_1_1_2,
3330− BFPT_DWORD(1), BIT(16), /* Supported bit */
3331− BFPT_DWORD(4), 0, /* Settings */
3332− SNOR_PROTO_1_1_2,
3333− },
3334−
3335− /* Fast Read 1-2-2 */
3336− {
3337− SNOR_HWCAPS_READ_1_2_2,
3338− BFPT_DWORD(1), BIT(20), /* Supported bit */
3339− BFPT_DWORD(4), 16, /* Settings */
3340− SNOR_PROTO_1_2_2,
3341− },
3342−
3343− /* Fast Read 2-2-2 */
3344− {
3345− SNOR_HWCAPS_READ_2_2_2,
3346− BFPT_DWORD(5), BIT(0), /* Supported bit */
3347− BFPT_DWORD(6), 16, /* Settings */
3348− SNOR_PROTO_2_2_2,
3349− },
3350−
3351− /* Fast Read 1-1-4 */
3352− {
3353− SNOR_HWCAPS_READ_1_1_4,
3354− BFPT_DWORD(1), BIT(22), /* Supported bit */
3355− BFPT_DWORD(3), 16, /* Settings */
3356− SNOR_PROTO_1_1_4,
3357− },
3358−
3359− /* Fast Read 1-4-4 */
3360− {
3361− SNOR_HWCAPS_READ_1_4_4,
3362− BFPT_DWORD(1), BIT(21), /* Supported bit */
3363− BFPT_DWORD(3), 0, /* Settings */
3364− SNOR_PROTO_1_4_4,
3365− },
3366−
3367− /* Fast Read 4-4-4 */
3368− {
3369− SNOR_HWCAPS_READ_4_4_4,
3370− BFPT_DWORD(5), BIT(4), /* Supported bit */
3371− BFPT_DWORD(7), 16, /* Settings */
3372− SNOR_PROTO_4_4_4,
3373− },
3374−};
3375−
3376−struct sfdp_bfpt_erase {
3377− /*
3378− * The half-word at offset <shift> in DWORD <dwoard> encodes the
3379− * op code and erase sector size to be used by Sector Erase commands.
3380− */
3381− u32 dword;
3382− u32 shift;
3383−};
3384−
3385−static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
3386− /* Erase Type 1 in DWORD8 bits[15:0] */
3387− {BFPT_DWORD(8), 0},
3388−
3389− /* Erase Type 2 in DWORD8 bits[31:16] */
3390− {BFPT_DWORD(8), 16},
3391−
3392− /* Erase Type 3 in DWORD9 bits[15:0] */
3393− {BFPT_DWORD(9), 0},
3394−
3395− /* Erase Type 4 in DWORD9 bits[31:16] */
3396− {BFPT_DWORD(9), 16},
3397−};
3398−
3399−/**
3400− * spi_nor_set_erase_type() - set a SPI NOR erase type
3401− * @erase: pointer to a structure that describes a SPI NOR erase type
3402− * @size: the size of the sector/block erased by the erase type
3403− * @opcode: the SPI command op code to erase the sector/block
3404− */
3405−static void spi_nor_set_erase_type(struct spi_nor_erase_type *erase,
3406− u32 size, u8 opcode)
3407−{
3408− erase->size = size;
3409− erase->opcode = opcode;
3410− /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
3411− erase->size_shift = ffs(erase->size) - 1;
3412− erase->size_mask = (1 << erase->size_shift) - 1;
3413−}
3414−
3415−/**
3416− * spi_nor_set_erase_settings_from_bfpt() - set erase type settings from BFPT
3417− * @erase: pointer to a structure that describes a SPI NOR erase type
3418− * @size: the size of the sector/block erased by the erase type
3419− * @opcode: the SPI command op code to erase the sector/block
3420− * @i: erase type index as sorted in the Basic Flash Parameter Table
3421− *
3422− * The supported Erase Types will be sorted at init in ascending order, with
3423− * the smallest Erase Type size being the first member in the erase_type array
3424− * of the spi_nor_erase_map structure. Save the Erase Type index as sorted in
3425− * the Basic Flash Parameter Table since it will be used later on to
3426− * synchronize with the supported Erase Types defined in SFDP optional tables.
3427− */
3428−static void
3429−spi_nor_set_erase_settings_from_bfpt(struct spi_nor_erase_type *erase,
3430− u32 size, u8 opcode, u8 i)
3431−{
3432− erase->idx = i;
3433− spi_nor_set_erase_type(erase, size, opcode);
3434−}
3435−
3436−/**
3437− * spi_nor_map_cmp_erase_type() - compare the map's erase types by size
3438− * @l: member in the left half of the map's erase_type array
3439− * @r: member in the right half of the map's erase_type array
3440− *
3441− * Comparison function used in the sort() call to sort in ascending order the
3442− * map's erase types, the smallest erase type size being the first member in the
3443− * sorted erase_type array.
3444− *
3445− * Return: the result of @l->size - @r->size
3446− */
3447−static int spi_nor_map_cmp_erase_type(const void *l, const void *r)
3448−{
3449− const struct spi_nor_erase_type *left = l, *right = r;
3450−
3451− return left->size - right->size;
3452−}
3453−
3454−/**
3455− * spi_nor_sort_erase_mask() - sort erase mask
3456− * @map: the erase map of the SPI NOR
3457− * @erase_mask: the erase type mask to be sorted
3458− *
3459− * Replicate the sort done for the map's erase types in BFPT: sort the erase
3460− * mask in ascending order with the smallest erase type size starting from
3461− * BIT(0) in the sorted erase mask.
3462− *
3463− * Return: sorted erase mask.
3464− */
3465−static u8 spi_nor_sort_erase_mask(struct spi_nor_erase_map *map, u8 erase_mask)
3466−{
3467− struct spi_nor_erase_type *erase_type = map->erase_type;
3468− int i;
3469− u8 sorted_erase_mask = 0;
3470−
3471− if (!erase_mask)
3472− return 0;
3473−
3474− /* Replicate the sort done for the map's erase types. */
3475− for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++)
3476− if (erase_type[i].size && erase_mask & BIT(erase_type[i].idx))
3477− sorted_erase_mask |= BIT(i);
3478−
3479− return sorted_erase_mask;
3480−}
3481−
3482−/**
3483− * spi_nor_regions_sort_erase_types() - sort erase types in each region
3484− * @map: the erase map of the SPI NOR
3485− *
3486− * Function assumes that the erase types defined in the erase map are already
3487− * sorted in ascending order, with the smallest erase type size being the first
3488− * member in the erase_type array. It replicates the sort done for the map's
3489− * erase types. Each region's erase bitmask will indicate which erase types are
3490− * supported from the sorted erase types defined in the erase map.
3491− * Sort the all region's erase type at init in order to speed up the process of
3492− * finding the best erase command at runtime.
3493− */
3494−static void spi_nor_regions_sort_erase_types(struct spi_nor_erase_map *map)
3495−{
3496− struct spi_nor_erase_region *region = map->regions;
3497− u8 region_erase_mask, sorted_erase_mask;
3498−
3499− while (region) {
3500− region_erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
3501−
3502− sorted_erase_mask = spi_nor_sort_erase_mask(map,
3503− region_erase_mask);
3504−
3505− /* Overwrite erase mask. */
3506− region->offset = (region->offset & ~SNOR_ERASE_TYPE_MASK) |
3507− sorted_erase_mask;
3508−
3509− region = spi_nor_region_next(region);
3510− }
3511−}
3512−
3513−/**
3514− * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
3515− * @map: the erase map of the SPI NOR
3516− * @erase_mask: bitmask encoding erase types that can erase the entire
3517− * flash memory
3518− * @flash_size: the spi nor flash memory size
3519− */
3520−static void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
3521− u8 erase_mask, u64 flash_size)
3522−{
3523− /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */
3524− map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) |
3525− SNOR_LAST_REGION;
3526− map->uniform_region.size = flash_size;
3527− map->regions = &map->uniform_region;
3528− map->uniform_erase_type = erase_mask;
3529−}
3530−
3531−static int
3532−spi_nor_post_bfpt_fixups(struct spi_nor *nor,
3533− const struct sfdp_parameter_header *bfpt_header,
3534− const struct sfdp_bfpt *bfpt,
3535− struct spi_nor_flash_parameter *params)
3536−{
3537− if (nor->info->fixups && nor->info->fixups->post_bfpt)
3538− return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt,
3539− params);
3540−
3541− return 0;
3542−}
3543−
3544−/**
3545− * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
3546− * @nor: pointer to a 'struct spi_nor'
3547− * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
3548− * the Basic Flash Parameter Table length and version
3549− * @params: pointer to the 'struct spi_nor_flash_parameter' to be
3550− * filled
3551− *
3552− * The Basic Flash Parameter Table is the main and only mandatory table as
3553− * defined by the SFDP (JESD216) specification.
3554− * It provides us with the total size (memory density) of the data array and
3555− * the number of address bytes for Fast Read, Page Program and Sector Erase
3556− * commands.
3557− * For Fast READ commands, it also gives the number of mode clock cycles and
3558− * wait states (regrouped in the number of dummy clock cycles) for each
3559− * supported instruction op code.
3560− * For Page Program, the page size is now available since JESD216 rev A, however
3561− * the supported instruction op codes are still not provided.
3562− * For Sector Erase commands, this table stores the supported instruction op
3563− * codes and the associated sector sizes.
3564− * Finally, the Quad Enable Requirements (QER) are also available since JESD216
3565− * rev A. The QER bits encode the manufacturer dependent procedure to be
3566− * executed to set the Quad Enable (QE) bit in some internal register of the
3567− * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
3568− * sending any Quad SPI command to the memory. Actually, setting the QE bit
3569− * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
3570− * and IO3 hence enabling 4 (Quad) I/O lines.
3571− *
3572− * Return: 0 on success, -errno otherwise.
3573− */
3574−static int spi_nor_parse_bfpt(struct spi_nor *nor,
3575− const struct sfdp_parameter_header *bfpt_header,
3576− struct spi_nor_flash_parameter *params)
3577−{
3578− struct spi_nor_erase_map *map = &params->erase_map;
3579− struct spi_nor_erase_type *erase_type = map->erase_type;
3580− struct sfdp_bfpt bfpt;
3581− size_t len;
3582− int i, cmd, err;
3583− u32 addr;
3584− u16 half;
3585− u8 erase_mask;
3586−
3587− /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
3588− if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
3589− return -EINVAL;
3590−
3591− /* Read the Basic Flash Parameter Table. */
3592− len = min_t(size_t, sizeof(bfpt),
3593− bfpt_header->length * sizeof(u32));
3594− addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
3595− memset(&bfpt, 0, sizeof(bfpt));
3596− err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt);
3597− if (err < 0)
3598− return err;
3599−
3600− /* Fix endianness of the BFPT DWORDs. */
3601− for (i = 0; i < BFPT_DWORD_MAX; i++)
3602− bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
3603−
3604− /* Number of address bytes. */
3605− switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
3606− case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
3607− nor->addr_width = 3;
3608− break;
3609−
3610− case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
3611− nor->addr_width = 4;
3612− break;
3613−
3614− default:
3615− break;
3616− }
3617−
3618− /* Flash Memory Density (in bits). */
3619− params->size = bfpt.dwords[BFPT_DWORD(2)];
3620− if (params->size & BIT(31)) {
3621− params->size &= ~BIT(31);
3622−
3623− /*
3624− * Prevent overflows on params->size. Anyway, a NOR of 2^64
3625− * bits is unlikely to exist so this error probably means
3626− * the BFPT we are reading is corrupted/wrong.
3627− */
3628− if (params->size > 63)
3629− return -EINVAL;
3630−
3631− params->size = 1ULL << params->size;
3632− } else {
3633− params->size++;
3634− }
3635− params->size >>= 3; /* Convert to bytes. */
3636−
3637− /* Fast Read settings. */
3638− for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
3639− const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
3640− struct spi_nor_read_command *read;
3641−
3642− if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
3643− params->hwcaps.mask &= ~rd->hwcaps;
3644− continue;
3645− }
3646−
3647− params->hwcaps.mask |= rd->hwcaps;
3648− cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
3649− read = &params->reads[cmd];
3650− half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
3651− spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
3652− }
3653−
3654− /*
3655− * Sector Erase settings. Reinitialize the uniform erase map using the
3656− * Erase Types defined in the bfpt table.
3657− */
3658− erase_mask = 0;
3659− memset(&params->erase_map, 0, sizeof(params->erase_map));
3660− for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
3661− const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
3662− u32 erasesize;
3663− u8 opcode;
3664−
3665− half = bfpt.dwords[er->dword] >> er->shift;
3666− erasesize = half & 0xff;
3667−
3668− /* erasesize == 0 means this Erase Type is not supported. */
3669− if (!erasesize)
3670− continue;
3671−
3672− erasesize = 1U << erasesize;
3673− opcode = (half >> 8) & 0xff;
3674− erase_mask |= BIT(i);
3675− spi_nor_set_erase_settings_from_bfpt(&erase_type[i], erasesize,
3676− opcode, i);
3677− }
3678− spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
3679− /*
3680− * Sort all the map's Erase Types in ascending order with the smallest
3681− * erase size being the first member in the erase_type array.
3682− */
3683− sort(erase_type, SNOR_ERASE_TYPE_MAX, sizeof(erase_type[0]),
3684− spi_nor_map_cmp_erase_type, NULL);
3685− /*
3686− * Sort the erase types in the uniform region in order to update the
3687− * uniform_erase_type bitmask. The bitmask will be used later on when
3688− * selecting the uniform erase.
3689− */
3690− spi_nor_regions_sort_erase_types(map);
3691− map->uniform_erase_type = map->uniform_region.offset &
3692− SNOR_ERASE_TYPE_MASK;
3693−
3694− /* Stop here if not JESD216 rev A or later. */
3695− if (bfpt_header->length < BFPT_DWORD_MAX)
3696− return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
3697− params);
3698−
3699− /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
3700− params->page_size = bfpt.dwords[BFPT_DWORD(11)];
3701− params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
3702− params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
3703− params->page_size = 1U << params->page_size;
3704−
3705− /* Quad Enable Requirements. */
3706− switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
3707− case BFPT_DWORD15_QER_NONE:
3708− params->quad_enable = NULL;
3709− break;
3710−
3711− case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
3712− /*
3713− * Writing only one byte to the Status Register has the
3714− * side-effect of clearing Status Register 2.
3715− */
3716− case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
3717− /*
3718− * Read Configuration Register (35h) instruction is not
3719− * supported.
3720− */
3721− nor->flags |= SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR;
3722− params->quad_enable = spi_nor_sr2_bit1_quad_enable;
3723− break;
3724−
3725− case BFPT_DWORD15_QER_SR1_BIT6:
3726− nor->flags &= ~SNOR_F_HAS_16BIT_SR;
3727− params->quad_enable = spi_nor_sr1_bit6_quad_enable;
3728− break;
3729−
3730− case BFPT_DWORD15_QER_SR2_BIT7:
3731− nor->flags &= ~SNOR_F_HAS_16BIT_SR;
3732− params->quad_enable = spi_nor_sr2_bit7_quad_enable;
3733− break;
3734−
3735− case BFPT_DWORD15_QER_SR2_BIT1:
3736− /*
3737− * JESD216 rev B or later does not specify if writing only one
3738− * byte to the Status Register clears or not the Status
3739− * Register 2, so let's be cautious and keep the default
3740− * assumption of a 16-bit Write Status (01h) command.
3741− */
3742− nor->flags |= SNOR_F_HAS_16BIT_SR;
3743−
3744− params->quad_enable = spi_nor_sr2_bit1_quad_enable;
3745− break;
3746−
3747− default:
3748− return -EINVAL;
3749− }
3750−
3751− return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
3752−}
3753−
3754−#define SMPT_CMD_ADDRESS_LEN_MASK GENMASK(23, 22)
3755−#define SMPT_CMD_ADDRESS_LEN_0 (0x0UL << 22)
3756−#define SMPT_CMD_ADDRESS_LEN_3 (0x1UL << 22)
3757−#define SMPT_CMD_ADDRESS_LEN_4 (0x2UL << 22)
3758−#define SMPT_CMD_ADDRESS_LEN_USE_CURRENT (0x3UL << 22)
3759−
3760−#define SMPT_CMD_READ_DUMMY_MASK GENMASK(19, 16)
3761−#define SMPT_CMD_READ_DUMMY_SHIFT 16
3762−#define SMPT_CMD_READ_DUMMY(_cmd) \
3763− (((_cmd) & SMPT_CMD_READ_DUMMY_MASK) >> SMPT_CMD_READ_DUMMY_SHIFT)
3764−#define SMPT_CMD_READ_DUMMY_IS_VARIABLE 0xfUL
3765−
3766−#define SMPT_CMD_READ_DATA_MASK GENMASK(31, 24)
3767−#define SMPT_CMD_READ_DATA_SHIFT 24
3768−#define SMPT_CMD_READ_DATA(_cmd) \
3769− (((_cmd) & SMPT_CMD_READ_DATA_MASK) >> SMPT_CMD_READ_DATA_SHIFT)
3770−
3771−#define SMPT_CMD_OPCODE_MASK GENMASK(15, 8)
3772−#define SMPT_CMD_OPCODE_SHIFT 8
3773−#define SMPT_CMD_OPCODE(_cmd) \
3774− (((_cmd) & SMPT_CMD_OPCODE_MASK) >> SMPT_CMD_OPCODE_SHIFT)
3775−
3776−#define SMPT_MAP_REGION_COUNT_MASK GENMASK(23, 16)
3777−#define SMPT_MAP_REGION_COUNT_SHIFT 16
3778−#define SMPT_MAP_REGION_COUNT(_header) \
3779− ((((_header) & SMPT_MAP_REGION_COUNT_MASK) >> \
3780− SMPT_MAP_REGION_COUNT_SHIFT) + 1)
3781−
3782−#define SMPT_MAP_ID_MASK GENMASK(15, 8)
3783−#define SMPT_MAP_ID_SHIFT 8
3784−#define SMPT_MAP_ID(_header) \
3785− (((_header) & SMPT_MAP_ID_MASK) >> SMPT_MAP_ID_SHIFT)
3786−
3787−#define SMPT_MAP_REGION_SIZE_MASK GENMASK(31, 8)
3788−#define SMPT_MAP_REGION_SIZE_SHIFT 8
3789−#define SMPT_MAP_REGION_SIZE(_region) \
3790− (((((_region) & SMPT_MAP_REGION_SIZE_MASK) >> \
3791− SMPT_MAP_REGION_SIZE_SHIFT) + 1) * 256)
3792−
3793−#define SMPT_MAP_REGION_ERASE_TYPE_MASK GENMASK(3, 0)
3794−#define SMPT_MAP_REGION_ERASE_TYPE(_region) \
3795− ((_region) & SMPT_MAP_REGION_ERASE_TYPE_MASK)
3796−
3797−#define SMPT_DESC_TYPE_MAP BIT(1)
3798−#define SMPT_DESC_END BIT(0)
3799−
3800−/**
3801− * spi_nor_smpt_addr_width() - return the address width used in the
3802− * configuration detection command.
3803− * @nor: pointer to a 'struct spi_nor'
3804− * @settings: configuration detection command descriptor, dword1
3805− */
3806−static u8 spi_nor_smpt_addr_width(const struct spi_nor *nor, const u32 settings)
3807−{
3808− switch (settings & SMPT_CMD_ADDRESS_LEN_MASK) {
3809− case SMPT_CMD_ADDRESS_LEN_0:
3810− return 0;
3811− case SMPT_CMD_ADDRESS_LEN_3:
3812− return 3;
3813− case SMPT_CMD_ADDRESS_LEN_4:
3814− return 4;
3815− case SMPT_CMD_ADDRESS_LEN_USE_CURRENT:
3816− /* fall through */
3817− default:
3818− return nor->addr_width;
3819− }
3820−}
3821−
3822−/**
3823− * spi_nor_smpt_read_dummy() - return the configuration detection command read
3824− * latency, in clock cycles.
3825− * @nor: pointer to a 'struct spi_nor'
3826− * @settings: configuration detection command descriptor, dword1
3827− *
3828− * Return: the number of dummy cycles for an SMPT read
3829− */
3830−static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings)
3831−{
3832− u8 read_dummy = SMPT_CMD_READ_DUMMY(settings);
3833−
3834− if (read_dummy == SMPT_CMD_READ_DUMMY_IS_VARIABLE)
3835− return nor->read_dummy;
3836− return read_dummy;
3837−}
3838−
3839−/**
3840− * spi_nor_get_map_in_use() - get the configuration map in use
3841− * @nor: pointer to a 'struct spi_nor'
3842− * @smpt: pointer to the sector map parameter table
3843− * @smpt_len: sector map parameter table length
3844− *
3845− * Return: pointer to the map in use, ERR_PTR(-errno) otherwise.
3846− */
3847−static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt,
3848− u8 smpt_len)
3849−{
3850− const u32 *ret;
3851− u8 *buf;
3852− u32 addr;
3853− int err;
3854− u8 i;
3855− u8 addr_width, read_opcode, read_dummy;
3856− u8 read_data_mask, map_id;
3857−
3858− /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */
3859− buf = kmalloc(sizeof(*buf), GFP_KERNEL);
3860− if (!buf)
3861− return ERR_PTR(-ENOMEM);
3862−
3863− addr_width = nor->addr_width;
3864− read_dummy = nor->read_dummy;
3865− read_opcode = nor->read_opcode;
3866−
3867− map_id = 0;
3868− /* Determine if there are any optional Detection Command Descriptors */
3869− for (i = 0; i < smpt_len; i += 2) {
3870− if (smpt[i] & SMPT_DESC_TYPE_MAP)
3871− break;
3872−
3873− read_data_mask = SMPT_CMD_READ_DATA(smpt[i]);
3874− nor->addr_width = spi_nor_smpt_addr_width(nor, smpt[i]);
3875− nor->read_dummy = spi_nor_smpt_read_dummy(nor, smpt[i]);
3876− nor->read_opcode = SMPT_CMD_OPCODE(smpt[i]);
3877− addr = smpt[i + 1];
3878−
3879− err = spi_nor_read_raw(nor, addr, 1, buf);
3880− if (err) {
3881− ret = ERR_PTR(err);
3882− goto out;
3883− }
3884−
3885− /*
3886− * Build an index value that is used to select the Sector Map
3887− * Configuration that is currently in use.
3888− */
3889− map_id = map_id << 1 | !!(*buf & read_data_mask);
3890− }
3891−
3892− /*
3893− * If command descriptors are provided, they always precede map
3894− * descriptors in the table. There is no need to start the iteration
3895− * over smpt array all over again.
3896− *
3897− * Find the matching configuration map.
3898− */
3899− ret = ERR_PTR(-EINVAL);
3900− while (i < smpt_len) {
3901− if (SMPT_MAP_ID(smpt[i]) == map_id) {
3902− ret = smpt + i;
3903− break;
3904− }
3905−
3906− /*
3907− * If there are no more configuration map descriptors and no
3908− * configuration ID matched the configuration identifier, the
3909− * sector address map is unknown.
3910− */
3911− if (smpt[i] & SMPT_DESC_END)
3912− break;
3913−
3914− /* increment the table index to the next map */
3915− i += SMPT_MAP_REGION_COUNT(smpt[i]) + 1;
3916− }
3917−
3918− /* fall through */
3919−out:
3920− kfree(buf);
3921− nor->addr_width = addr_width;
3922− nor->read_dummy = read_dummy;
3923− nor->read_opcode = read_opcode;
3924− return ret;
3925−}
3926−
3927−/**
3928− * spi_nor_region_check_overlay() - set overlay bit when the region is overlaid
3929− * @region: pointer to a structure that describes a SPI NOR erase region
3930− * @erase: pointer to a structure that describes a SPI NOR erase type
3931− * @erase_type: erase type bitmask
3932− */
3933−static void
3934−spi_nor_region_check_overlay(struct spi_nor_erase_region *region,
3935− const struct spi_nor_erase_type *erase,
3936− const u8 erase_type)
3937−{
3938− int i;
3939−
3940− for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
3941− if (!(erase_type & BIT(i)))
3942− continue;
3943− if (region->size & erase[i].size_mask) {
3944− spi_nor_region_mark_overlay(region);
3945− return;
3946− }
3947− }
3948−}
3949−
3950−/**
3951− * spi_nor_init_non_uniform_erase_map() - initialize the non-uniform erase map
3952− * @nor: pointer to a 'struct spi_nor'
3953− * @params: pointer to a duplicate 'struct spi_nor_flash_parameter' that is
3954− * used for storing SFDP parsed data
3955− * @smpt: pointer to the sector map parameter table
3956− *
3957− * Return: 0 on success, -errno otherwise.
3958− */
3959−static int
3960−spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
3961− struct spi_nor_flash_parameter *params,
3962− const u32 *smpt)
3963−{
3964− struct spi_nor_erase_map *map = &params->erase_map;
3965− struct spi_nor_erase_type *erase = map->erase_type;
3966− struct spi_nor_erase_region *region;
3967− u64 offset;
3968− u32 region_count;
3969− int i, j;
3970− u8 uniform_erase_type, save_uniform_erase_type;
3971− u8 erase_type, regions_erase_type;
3972−
3973− region_count = SMPT_MAP_REGION_COUNT(*smpt);
3974− /*
3975− * The regions will be freed when the driver detaches from the
3976− * device.
3977− */
3978− region = devm_kcalloc(nor->dev, region_count, sizeof(*region),
3979− GFP_KERNEL);
3980− if (!region)
3981− return -ENOMEM;
3982− map->regions = region;
3983−
3984− uniform_erase_type = 0xff;
3985− regions_erase_type = 0;
3986− offset = 0;
3987− /* Populate regions. */
3988− for (i = 0; i < region_count; i++) {
3989− j = i + 1; /* index for the region dword */
3990− region[i].size = SMPT_MAP_REGION_SIZE(smpt[j]);
3991− erase_type = SMPT_MAP_REGION_ERASE_TYPE(smpt[j]);
3992− region[i].offset = offset | erase_type;
3993−
3994− spi_nor_region_check_overlay(&region[i], erase, erase_type);
3995−
3996− /*
3997− * Save the erase types that are supported in all regions and
3998− * can erase the entire flash memory.
3999− */
4000− uniform_erase_type &= erase_type;
4001−
4002− /*
4003− * regions_erase_type mask will indicate all the erase types
4004− * supported in this configuration map.
4005− */
4006− regions_erase_type |= erase_type;
4007−
4008− offset = (region[i].offset & ~SNOR_ERASE_FLAGS_MASK) +
4009− region[i].size;
4010− }
4011−
4012− save_uniform_erase_type = map->uniform_erase_type;
4013− map->uniform_erase_type = spi_nor_sort_erase_mask(map,
4014− uniform_erase_type);
4015−
4016− if (!regions_erase_type) {
4017− /*
4018− * Roll back to the previous uniform_erase_type mask, SMPT is
4019− * broken.
4020− */
4021− map->uniform_erase_type = save_uniform_erase_type;
4022− return -EINVAL;
4023− }
4024−
4025− /*
4026− * BFPT advertises all the erase types supported by all the possible
4027− * map configurations. Mask out the erase types that are not supported
4028− * by the current map configuration.
4029− */
4030− for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++)
4031− if (!(regions_erase_type & BIT(erase[i].idx)))
4032− spi_nor_set_erase_type(&erase[i], 0, 0xFF);
4033−
4034− spi_nor_region_mark_end(&region[i - 1]);
4035−
4036− return 0;
4037−}
4038−
4039−/**
4040− * spi_nor_parse_smpt() - parse Sector Map Parameter Table
4041− * @nor: pointer to a 'struct spi_nor'
4042− * @smpt_header: sector map parameter table header
4043− * @params: pointer to a duplicate 'struct spi_nor_flash_parameter'
4044− * that is used for storing SFDP parsed data
4045− *
4046− * This table is optional, but when available, we parse it to identify the
4047− * location and size of sectors within the main data array of the flash memory
4048− * device and to identify which Erase Types are supported by each sector.
4049− *
4050− * Return: 0 on success, -errno otherwise.
4051− */
4052−static int spi_nor_parse_smpt(struct spi_nor *nor,
4053− const struct sfdp_parameter_header *smpt_header,
4054− struct spi_nor_flash_parameter *params)
4055−{
4056− const u32 *sector_map;
4057− u32 *smpt;
4058− size_t len;
4059− u32 addr;
4060− int i, ret;
4061−
4062− /* Read the Sector Map Parameter Table. */
4063− len = smpt_header->length * sizeof(*smpt);
4064− smpt = kmalloc(len, GFP_KERNEL);
4065− if (!smpt)
4066− return -ENOMEM;
4067−
4068− addr = SFDP_PARAM_HEADER_PTP(smpt_header);
4069− ret = spi_nor_read_sfdp(nor, addr, len, smpt);
4070− if (ret)
4071− goto out;
4072−
4073− /* Fix endianness of the SMPT DWORDs. */
4074− for (i = 0; i < smpt_header->length; i++)
4075− smpt[i] = le32_to_cpu(smpt[i]);
4076−
4077− sector_map = spi_nor_get_map_in_use(nor, smpt, smpt_header->length);
4078− if (IS_ERR(sector_map)) {
4079− ret = PTR_ERR(sector_map);
4080− goto out;
4081− }
4082−
4083− ret = spi_nor_init_non_uniform_erase_map(nor, params, sector_map);
4084− if (ret)
4085− goto out;
4086−
4087− spi_nor_regions_sort_erase_types(&params->erase_map);
4088− /* fall through */
4089−out:
4090− kfree(smpt);
4091− return ret;
4092−}
4093−
4094−#define SFDP_4BAIT_DWORD_MAX 2
4095−
4096−struct sfdp_4bait {
4097− /* The hardware capability. */
4098− u32 hwcaps;
4099−
4100− /*
4101− * The <supported_bit> bit in DWORD1 of the 4BAIT tells us whether
4102− * the associated 4-byte address op code is supported.
4103− */
4104− u32 supported_bit;
4105−};
4106−
4107−/**
4108− * spi_nor_parse_4bait() - parse the 4-Byte Address Instruction Table
4109− * @nor: pointer to a 'struct spi_nor'.
4110− * @param_header: pointer to the 'struct sfdp_parameter_header' describing
4111− * the 4-Byte Address Instruction Table length and version.
4112− * @params: pointer to the 'struct spi_nor_flash_parameter' to be.
4113− *
4114− * Return: 0 on success, -errno otherwise.
4115− */
4116−static int spi_nor_parse_4bait(struct spi_nor *nor,
4117− const struct sfdp_parameter_header *param_header,
4118− struct spi_nor_flash_parameter *params)
4119−{
4120− static const struct sfdp_4bait reads[] = {
4121− { SNOR_HWCAPS_READ, BIT(0) },
4122− { SNOR_HWCAPS_READ_FAST, BIT(1) },
4123− { SNOR_HWCAPS_READ_1_1_2, BIT(2) },
4124− { SNOR_HWCAPS_READ_1_2_2, BIT(3) },
4125− { SNOR_HWCAPS_READ_1_1_4, BIT(4) },
4126− { SNOR_HWCAPS_READ_1_4_4, BIT(5) },
4127− { SNOR_HWCAPS_READ_1_1_1_DTR, BIT(13) },
4128− { SNOR_HWCAPS_READ_1_2_2_DTR, BIT(14) },
4129− { SNOR_HWCAPS_READ_1_4_4_DTR, BIT(15) },
4130− };
4131− static const struct sfdp_4bait programs[] = {
4132− { SNOR_HWCAPS_PP, BIT(6) },
4133− { SNOR_HWCAPS_PP_1_1_4, BIT(7) },
4134− { SNOR_HWCAPS_PP_1_4_4, BIT(8) },
4135− };
4136− static const struct sfdp_4bait erases[SNOR_ERASE_TYPE_MAX] = {
4137− { 0u /* not used */, BIT(9) },
4138− { 0u /* not used */, BIT(10) },
4139− { 0u /* not used */, BIT(11) },
4140− { 0u /* not used */, BIT(12) },
4141− };
4142− struct spi_nor_pp_command *params_pp = params->page_programs;
4143− struct spi_nor_erase_map *map = &params->erase_map;
4144− struct spi_nor_erase_type *erase_type = map->erase_type;
4145− u32 *dwords;
4146− size_t len;
4147− u32 addr, discard_hwcaps, read_hwcaps, pp_hwcaps, erase_mask;
4148− int i, ret;
4149−
4150− if (param_header->major != SFDP_JESD216_MAJOR ||
4151− param_header->length < SFDP_4BAIT_DWORD_MAX)
4152− return -EINVAL;
4153−
4154− /* Read the 4-byte Address Instruction Table. */
4155− len = sizeof(*dwords) * SFDP_4BAIT_DWORD_MAX;
4156−
4157− /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */
4158− dwords = kmalloc(len, GFP_KERNEL);
4159− if (!dwords)
4160− return -ENOMEM;
4161−
4162− addr = SFDP_PARAM_HEADER_PTP(param_header);
4163− ret = spi_nor_read_sfdp(nor, addr, len, dwords);
4164− if (ret)
4165− goto out;
4166−
4167− /* Fix endianness of the 4BAIT DWORDs. */
4168− for (i = 0; i < SFDP_4BAIT_DWORD_MAX; i++)
4169− dwords[i] = le32_to_cpu(dwords[i]);
4170−
4171− /*
4172− * Compute the subset of (Fast) Read commands for which the 4-byte
4173− * version is supported.
4174− */
4175− discard_hwcaps = 0;
4176− read_hwcaps = 0;
4177− for (i = 0; i < ARRAY_SIZE(reads); i++) {
4178− const struct sfdp_4bait *read = &reads[i];
4179−
4180− discard_hwcaps |= read->hwcaps;
4181− if ((params->hwcaps.mask & read->hwcaps) &&
4182− (dwords[0] & read->supported_bit))
4183− read_hwcaps |= read->hwcaps;
4184− }
4185−
4186− /*
4187− * Compute the subset of Page Program commands for which the 4-byte
4188− * version is supported.
4189− */
4190− pp_hwcaps = 0;
4191− for (i = 0; i < ARRAY_SIZE(programs); i++) {
4192− const struct sfdp_4bait *program = &programs[i];
4193−
4194− /*
4195− * The 4 Byte Address Instruction (Optional) Table is the only
4196− * SFDP table that indicates support for Page Program Commands.
4197− * Bypass the params->hwcaps.mask and consider 4BAIT the biggest
4198− * authority for specifying Page Program support.
4199− */
4200− discard_hwcaps |= program->hwcaps;
4201− if (dwords[0] & program->supported_bit)
4202− pp_hwcaps |= program->hwcaps;
4203− }
4204−
4205− /*
4206− * Compute the subset of Sector Erase commands for which the 4-byte
4207− * version is supported.
4208− */
4209− erase_mask = 0;
4210− for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
4211− const struct sfdp_4bait *erase = &erases[i];
4212−
4213− if (dwords[0] & erase->supported_bit)
4214− erase_mask |= BIT(i);
4215− }
4216−
4217− /* Replicate the sort done for the map's erase types in BFPT. */
4218− erase_mask = spi_nor_sort_erase_mask(map, erase_mask);
4219−
4220− /*
4221− * We need at least one 4-byte op code per read, program and erase
4222− * operation; the .read(), .write() and .erase() hooks share the
4223− * nor->addr_width value.
4224− */
4225− if (!read_hwcaps || !pp_hwcaps || !erase_mask)
4226− goto out;
4227−
4228− /*
4229− * Discard all operations from the 4-byte instruction set which are
4230− * not supported by this memory.
4231− */
4232− params->hwcaps.mask &= ~discard_hwcaps;
4233− params->hwcaps.mask |= (read_hwcaps | pp_hwcaps);
4234−
4235− /* Use the 4-byte address instruction set. */
4236− for (i = 0; i < SNOR_CMD_READ_MAX; i++) {
4237− struct spi_nor_read_command *read_cmd = &params->reads[i];
4238−
4239− read_cmd->opcode = spi_nor_convert_3to4_read(read_cmd->opcode);
4240− }
4241−
4242− /* 4BAIT is the only SFDP table that indicates page program support. */
4243− if (pp_hwcaps & SNOR_HWCAPS_PP)
4244− spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP],
4245− SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
4246− if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_4)
4247− spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP_1_1_4],
4248− SPINOR_OP_PP_1_1_4_4B,
4249− SNOR_PROTO_1_1_4);
4250− if (pp_hwcaps & SNOR_HWCAPS_PP_1_4_4)
4251− spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP_1_4_4],
4252− SPINOR_OP_PP_1_4_4_4B,
4253− SNOR_PROTO_1_4_4);
4254−
4255− for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
4256− if (erase_mask & BIT(i))
4257− erase_type[i].opcode = (dwords[1] >>
4258− erase_type[i].idx * 8) & 0xFF;
4259− else
4260− spi_nor_set_erase_type(&erase_type[i], 0u, 0xFF);
4261− }
4262−
4263− /*
4264− * We set SNOR_F_HAS_4BAIT in order to skip spi_nor_set_4byte_opcodes()
4265− * later because we already did the conversion to 4byte opcodes. Also,
4266− * this latest function implements a legacy quirk for the erase size of
4267− * Spansion memory. However this quirk is no longer needed with new
4268− * SFDP compliant memories.
4269− */
4270− nor->addr_width = 4;
4271− nor->flags |= SNOR_F_4B_OPCODES | SNOR_F_HAS_4BAIT;
4272−
4273− /* fall through */
4274−out:
4275− kfree(dwords);
4276− return ret;
4277−}
4278−
4279−/**
4280− * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
4281− * @nor: pointer to a 'struct spi_nor'
4282− * @params: pointer to the 'struct spi_nor_flash_parameter' to be
4283− * filled
4284− *
4285− * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
4286− * specification. This is a standard which tends to supported by almost all
4287− * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
4288− * runtime the main parameters needed to perform basic SPI flash operations such
4289− * as Fast Read, Page Program or Sector Erase commands.
4290− *
4291− * Return: 0 on success, -errno otherwise.
4292− */
4293−static int spi_nor_parse_sfdp(struct spi_nor *nor,
4294− struct spi_nor_flash_parameter *params)
4295−{
4296− const struct sfdp_parameter_header *param_header, *bfpt_header;
4297− struct sfdp_parameter_header *param_headers = NULL;
4298− struct sfdp_header header;
4299− struct device *dev = nor->dev;
4300− size_t psize;
4301− int i, err;
4302−
4303− /* Get the SFDP header. */
4304− err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header);
4305− if (err < 0)
4306− return err;
4307−
4308− /* Check the SFDP header version. */
4309− if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
4310− header.major != SFDP_JESD216_MAJOR)
4311− return -EINVAL;
4312−
4313− /*
4314− * Verify that the first and only mandatory parameter header is a
4315− * Basic Flash Parameter Table header as specified in JESD216.
4316− */
4317− bfpt_header = &header.bfpt_header;
4318− if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
4319− bfpt_header->major != SFDP_JESD216_MAJOR)
4320− return -EINVAL;
4321−
4322− /*
4323− * Allocate memory then read all parameter headers with a single
4324− * Read SFDP command. These parameter headers will actually be parsed
4325− * twice: a first time to get the latest revision of the basic flash
4326− * parameter table, then a second time to handle the supported optional
4327− * tables.
4328− * Hence we read the parameter headers once for all to reduce the
4329− * processing time. Also we use kmalloc() instead of devm_kmalloc()
4330− * because we don't need to keep these parameter headers: the allocated
4331− * memory is always released with kfree() before exiting this function.
4332− */
4333− if (header.nph) {
4334− psize = header.nph * sizeof(*param_headers);
4335−
4336− param_headers = kmalloc(psize, GFP_KERNEL);
4337− if (!param_headers)
4338− return -ENOMEM;
4339−
4340− err = spi_nor_read_sfdp(nor, sizeof(header),
4341− psize, param_headers);
4342− if (err < 0) {
4343− dev_dbg(dev, "failed to read SFDP parameter headers\n");
4344− goto exit;
4345− }
4346− }
4347−
4348− /*
4349− * Check other parameter headers to get the latest revision of
4350− * the basic flash parameter table.
4351− */
4352− for (i = 0; i < header.nph; i++) {
4353− param_header = &param_headers[i];
4354−
4355− if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
4356− param_header->major == SFDP_JESD216_MAJOR &&
4357− (param_header->minor > bfpt_header->minor ||
4358− (param_header->minor == bfpt_header->minor &&
4359− param_header->length > bfpt_header->length)))
4360− bfpt_header = param_header;
4361− }
4362−
4363− err = spi_nor_parse_bfpt(nor, bfpt_header, params);
4364− if (err)
4365− goto exit;
4366−
4367− /* Parse optional parameter tables. */
4368− for (i = 0; i < header.nph; i++) {
4369− param_header = &param_headers[i];
4370−
4371− switch (SFDP_PARAM_HEADER_ID(param_header)) {
4372− case SFDP_SECTOR_MAP_ID:
4373− err = spi_nor_parse_smpt(nor, param_header, params);
4374− break;
4375−
4376− case SFDP_4BAIT_ID:
4377− err = spi_nor_parse_4bait(nor, param_header, params);
4378− break;
4379−
4380− default:
4381− break;
4382− }
4383−
4384− if (err) {
4385− dev_warn(dev, "Failed to parse optional parameter table: %04x\n",
4386− SFDP_PARAM_HEADER_ID(param_header));
4387− /*
4388− * Let's not drop all information we extracted so far
4389− * if optional table parsers fail. In case of failing,
4390− * each optional parser is responsible to roll back to
4391− * the previously known spi_nor data.
4392− */
4393− err = 0;
4394− }
4395− }
4396−
4397−exit:
4398− kfree(param_headers);
4399− return err;
4400−}
4401−
4402−static int spi_nor_select_read(struct spi_nor *nor,
4403− u32 shared_hwcaps)
4404−{
4405− int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
4406− const struct spi_nor_read_command *read;
4407−
4408− if (best_match < 0)
4409− return -EINVAL;
4410−
4411− cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
4412− if (cmd < 0)
4413− return -EINVAL;
4414−
4415− read = &nor->params.reads[cmd];
4416− nor->read_opcode = read->opcode;
4417− nor->read_proto = read->proto;
4418−
4419− /*
4420− * In the spi-nor framework, we don't need to make the difference
4421− * between mode clock cycles and wait state clock cycles.
4422− * Indeed, the value of the mode clock cycles is used by a QSPI
4423− * flash memory to know whether it should enter or leave its 0-4-4
4424− * (Continuous Read / XIP) mode.
4425− * eXecution In Place is out of the scope of the mtd sub-system.
4426− * Hence we choose to merge both mode and wait state clock cycles
4427− * into the so called dummy clock cycles.
4428− */
4429− nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
4430− return 0;
4431−}
4432−
4433−static int spi_nor_select_pp(struct spi_nor *nor,
4434− u32 shared_hwcaps)
4435−{
4436− int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
4437− const struct spi_nor_pp_command *pp;
4438−
4439− if (best_match < 0)
4440− return -EINVAL;
4441−
4442− cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
4443− if (cmd < 0)
4444− return -EINVAL;
4445−
4446− pp = &nor->params.page_programs[cmd];
4447− nor->program_opcode = pp->opcode;
4448− nor->write_proto = pp->proto;
4449− return 0;
4450−}
4451−
4452−/**
4453− * spi_nor_select_uniform_erase() - select optimum uniform erase type
4454− * @map: the erase map of the SPI NOR
4455− * @wanted_size: the erase type size to search for. Contains the value of
4456− * info->sector_size or of the "small sector" size in case
4457− * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined.
4458− *
4459− * Once the optimum uniform sector erase command is found, disable all the
4460− * other.
4461− *
4462− * Return: pointer to erase type on success, NULL otherwise.
4463− */
4464−static const struct spi_nor_erase_type *
4465−spi_nor_select_uniform_erase(struct spi_nor_erase_map *map,
4466− const u32 wanted_size)
4467−{
4468− const struct spi_nor_erase_type *tested_erase, *erase = NULL;
4469− int i;
4470− u8 uniform_erase_type = map->uniform_erase_type;
4471−
4472− for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
4473− if (!(uniform_erase_type & BIT(i)))
4474− continue;
4475−
4476− tested_erase = &map->erase_type[i];
4477−
4478− /*
4479− * If the current erase size is the one, stop here:
4480− * we have found the right uniform Sector Erase command.
4481− */
4482− if (tested_erase->size == wanted_size) {
4483− erase = tested_erase;
4484− break;
4485− }
4486−
4487− /*
4488− * Otherwise, the current erase size is still a valid canditate.
4489− * Select the biggest valid candidate.
4490− */
4491− if (!erase && tested_erase->size)
4492− erase = tested_erase;
4493− /* keep iterating to find the wanted_size */
4494− }
4495−
4496− if (!erase)
4497− return NULL;
4498−
4499− /* Disable all other Sector Erase commands. */
4500− map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK;
4501− map->uniform_erase_type |= BIT(erase - map->erase_type);
4502− return erase;
4503−}
4504−
4505−static int spi_nor_select_erase(struct spi_nor *nor)
4506−{
4507− struct spi_nor_erase_map *map = &nor->params.erase_map;
4508− const struct spi_nor_erase_type *erase = NULL;
4509− struct mtd_info *mtd = &nor->mtd;
4510− u32 wanted_size = nor->info->sector_size;
4511− int i;
4512−
4513− /*
4514− * The previous implementation handling Sector Erase commands assumed
4515− * that the SPI flash memory has an uniform layout then used only one
4516− * of the supported erase sizes for all Sector Erase commands.
4517− * So to be backward compatible, the new implementation also tries to
4518− * manage the SPI flash memory as uniform with a single erase sector
4519− * size, when possible.
4520− */
4521−#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
4522− /* prefer "small sector" erase if possible */
4523− wanted_size = 4096u;
4524−#endif
4525−
4526− if (spi_nor_has_uniform_erase(nor)) {
4527− erase = spi_nor_select_uniform_erase(map, wanted_size);
4528− if (!erase)
4529− return -EINVAL;
4530− nor->erase_opcode = erase->opcode;
4531− mtd->erasesize = erase->size;
4532− return 0;
4533− }
4534−
4535− /*
4536− * For non-uniform SPI flash memory, set mtd->erasesize to the
4537− * maximum erase sector size. No need to set nor->erase_opcode.
4538− */
4539− for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
4540− if (map->erase_type[i].size) {
4541− erase = &map->erase_type[i];
4542− break;
4543− }
4544− }
4545−
4546− if (!erase)
4547− return -EINVAL;
4548−
4549− mtd->erasesize = erase->size;
4550− return 0;
4551−}
4552−
4553−static int spi_nor_default_setup(struct spi_nor *nor,
4554− const struct spi_nor_hwcaps *hwcaps)
4555−{
4556− struct spi_nor_flash_parameter *params = &nor->params;
4557− u32 ignored_mask, shared_mask;
4558− int err;
4559−
4560− /*
4561− * Keep only the hardware capabilities supported by both the SPI
4562− * controller and the SPI flash memory.
4563− */
4564− shared_mask = hwcaps->mask & params->hwcaps.mask;
4565−
4566− if (nor->spimem) {
4567− /*
4568− * When called from spi_nor_probe(), all caps are set and we
4569− * need to discard some of them based on what the SPI
4570− * controller actually supports (using spi_mem_supports_op()).
4571− */
4572− spi_nor_spimem_adjust_hwcaps(nor, &shared_mask);
4573− } else {
4574− /*
4575− * SPI n-n-n protocols are not supported when the SPI
4576− * controller directly implements the spi_nor interface.
4577− * Yet another reason to switch to spi-mem.
4578− */
4579− ignored_mask = SNOR_HWCAPS_X_X_X;
4580− if (shared_mask & ignored_mask) {
4581− dev_dbg(nor->dev,
4582− "SPI n-n-n protocols are not supported.\n");
4583− shared_mask &= ~ignored_mask;
4584− }
4585− }
4586−
4587− /* Select the (Fast) Read command. */
4588− err = spi_nor_select_read(nor, shared_mask);
4589− if (err) {
4590− dev_dbg(nor->dev,
4591− "can't select read settings supported by both the SPI controller and memory.\n");
4592− return err;
4593− }
4594−
4595− /* Select the Page Program command. */
4596− err = spi_nor_select_pp(nor, shared_mask);
4597− if (err) {
4598− dev_dbg(nor->dev,
4599− "can't select write settings supported by both the SPI controller and memory.\n");
4600− return err;
4601− }
4602−
4603− /* Select the Sector Erase command. */
4604− err = spi_nor_select_erase(nor);
4605− if (err) {
4606− dev_dbg(nor->dev,
4607− "can't select erase settings supported by both the SPI controller and memory.\n");
4608− return err;
4609− }
4610−
4611− return 0;
4612−}
4613−
4614−static int spi_nor_setup(struct spi_nor *nor,
4615− const struct spi_nor_hwcaps *hwcaps)
4616−{
4617− if (!nor->params.setup)
4618− return 0;
4619−
4620− return nor->params.setup(nor, hwcaps);
4621−}
4622−
4623−static void atmel_set_default_init(struct spi_nor *nor)
4624−{
4625− nor->flags |= SNOR_F_HAS_LOCK;
4626−}
4627−
4628−static void intel_set_default_init(struct spi_nor *nor)
4629−{
4630− nor->flags |= SNOR_F_HAS_LOCK;
4631−}
4632−
4633−static void issi_set_default_init(struct spi_nor *nor)
4634−{
4635− nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable;
4636−}
4637−
4638−static void macronix_set_default_init(struct spi_nor *nor)
4639−{
4640− nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable;
4641− nor->params.set_4byte = macronix_set_4byte;
4642−}
4643−
4644−static void sst_set_default_init(struct spi_nor *nor)
4645−{
4646− nor->flags |= SNOR_F_HAS_LOCK;
4647−}
4648−
4649−static void st_micron_set_default_init(struct spi_nor *nor)
4650−{
4651− nor->flags |= SNOR_F_HAS_LOCK;
4652− nor->flags &= ~SNOR_F_HAS_16BIT_SR;
4653− nor->params.quad_enable = NULL;
4654− nor->params.set_4byte = st_micron_set_4byte;
4655−}
4656−
4657−static void winbond_set_default_init(struct spi_nor *nor)
4658−{
4659− nor->params.set_4byte = winbond_set_4byte;
4660−}
4661−
4662−/**
4663− * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
4664− * settings based on MFR register and ->default_init() hook.
4665− * @nor: pointer to a 'struct spi-nor'.
4666− */
4667−static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
4668−{
4669− /* Init flash parameters based on MFR */
4670− switch (JEDEC_MFR(nor->info)) {
4671− case SNOR_MFR_ATMEL:
4672− atmel_set_default_init(nor);
4673− break;
4674−
4675− case SNOR_MFR_INTEL:
4676− intel_set_default_init(nor);
4677− break;
4678−
4679− case SNOR_MFR_ISSI:
4680− issi_set_default_init(nor);
4681− break;
4682−
4683− case SNOR_MFR_MACRONIX:
4684− macronix_set_default_init(nor);
4685− break;
4686−
4687− case SNOR_MFR_ST:
4688− case SNOR_MFR_MICRON:
4689− st_micron_set_default_init(nor);
4690− break;
4691−
4692− case SNOR_MFR_SST:
4693− sst_set_default_init(nor);
4694− break;
4695−
4696− case SNOR_MFR_WINBOND:
4697− winbond_set_default_init(nor);
4698− break;
4699−
4700− default:
4701− break;
4702− }
4703−
4704− if (nor->info->fixups && nor->info->fixups->default_init)
4705− nor->info->fixups->default_init(nor);
4706−}
4707−
4708−/**
4709− * spi_nor_sfdp_init_params() - Initialize the flash's parameters and settings
4710− * based on JESD216 SFDP standard.
4711− * @nor: pointer to a 'struct spi-nor'.
4712− *
4713− * The method has a roll-back mechanism: in case the SFDP parsing fails, the
4714− * legacy flash parameters and settings will be restored.
4715− */
4716−static void spi_nor_sfdp_init_params(struct spi_nor *nor)
4717−{
4718− struct spi_nor_flash_parameter sfdp_params;
4719−
4720− memcpy(&sfdp_params, &nor->params, sizeof(sfdp_params));
4721−
4722− if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
4723− nor->addr_width = 0;
4724− nor->flags &= ~SNOR_F_4B_OPCODES;
4725− } else {
4726− memcpy(&nor->params, &sfdp_params, sizeof(nor->params));
4727− }
4728−}
4729−
4730−/**
4731− * spi_nor_info_init_params() - Initialize the flash's parameters and settings
4732− * based on nor->info data.
4733− * @nor: pointer to a 'struct spi-nor'.
4734− */
4735−static void spi_nor_info_init_params(struct spi_nor *nor)
4736−{
4737− struct spi_nor_flash_parameter *params = &nor->params;
4738− struct spi_nor_erase_map *map = &params->erase_map;
4739− const struct flash_info *info = nor->info;
4740− struct device_node *np = spi_nor_get_flash_node(nor);
4741− u8 i, erase_mask;
4742−
4743− /* Initialize legacy flash parameters and settings. */
4744− params->quad_enable = spi_nor_sr2_bit1_quad_enable;
4745− params->set_4byte = spansion_set_4byte;
4746− params->setup = spi_nor_default_setup;
4747− /* Default to 16-bit Write Status (01h) Command */
4748− nor->flags |= SNOR_F_HAS_16BIT_SR;
4749−
4750− /* Set SPI NOR sizes. */
4751− params->size = (u64)info->sector_size * info->n_sectors;
4752− params->page_size = info->page_size;
4753−
4754− if (!(info->flags & SPI_NOR_NO_FR)) {
4755− /* Default to Fast Read for DT and non-DT platform devices. */
4756− params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
4757−
4758− /* Mask out Fast Read if not requested at DT instantiation. */
4759− if (np && !of_property_read_bool(np, "m25p,fast-read"))
4760− params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
4761− }
4762−
4763− /* (Fast) Read settings. */
4764− params->hwcaps.mask |= SNOR_HWCAPS_READ;
4765− spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
4766− 0, 0, SPINOR_OP_READ,
4767− SNOR_PROTO_1_1_1);
4768−
4769− if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
4770− spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
4771− 0, 8, SPINOR_OP_READ_FAST,
4772− SNOR_PROTO_1_1_1);
4773−
4774− if (info->flags & SPI_NOR_DUAL_READ) {
4775− params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
4776− spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
4777− 0, 8, SPINOR_OP_READ_1_1_2,
4778− SNOR_PROTO_1_1_2);
4779− }
4780−
4781− if (info->flags & SPI_NOR_QUAD_READ) {
4782− params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
4783− spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
4784− 0, 8, SPINOR_OP_READ_1_1_4,
4785− SNOR_PROTO_1_1_4);
4786− }
4787−
4788− if (info->flags & SPI_NOR_OCTAL_READ) {
4789− params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
4790− spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
4791− 0, 8, SPINOR_OP_READ_1_1_8,
4792− SNOR_PROTO_1_1_8);
4793− }
4794−
4795− /* Page Program settings. */
4796− params->hwcaps.mask |= SNOR_HWCAPS_PP;
4797− spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
4798− SPINOR_OP_PP, SNOR_PROTO_1_1_1);
4799−
4800− /*
4801− * Sector Erase settings. Sort Erase Types in ascending order, with the
4802− * smallest erase size starting at BIT(0).
4803− */
4804− erase_mask = 0;
4805− i = 0;
4806− if (info->flags & SECT_4K_PMC) {
4807− erase_mask |= BIT(i);
4808− spi_nor_set_erase_type(&map->erase_type[i], 4096u,
4809− SPINOR_OP_BE_4K_PMC);
4810− i++;
4811− } else if (info->flags & SECT_4K) {
4812− erase_mask |= BIT(i);
4813− spi_nor_set_erase_type(&map->erase_type[i], 4096u,
4814− SPINOR_OP_BE_4K);
4815− i++;
4816− }
4817− erase_mask |= BIT(i);
4818− spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
4819− SPINOR_OP_SE);
4820− spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
4821−}
4822−
4823−static void spansion_post_sfdp_fixups(struct spi_nor *nor)
4824−{
4825− if (nor->params.size <= SZ_16M)
4826− return;
4827−
4828− nor->flags |= SNOR_F_4B_OPCODES;
4829− /* No small sector erase for 4-byte command set */
4830− nor->erase_opcode = SPINOR_OP_SE;
4831− nor->mtd.erasesize = nor->info->sector_size;
4832−}
4833−
4834−static void s3an_post_sfdp_fixups(struct spi_nor *nor)
4835−{
4836− nor->params.setup = s3an_nor_setup;
4837−}
4838−
4839−/**
4840− * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings
4841− * after SFDP has been parsed (is also called for SPI NORs that do not
4842− * support RDSFDP).
4843− * @nor: pointer to a 'struct spi_nor'
4844− *
4845− * Typically used to tweak various parameters that could not be extracted by
4846− * other means (i.e. when information provided by the SFDP/flash_info tables
4847− * are incomplete or wrong).
4848− */
4849−static void spi_nor_post_sfdp_fixups(struct spi_nor *nor)
4850−{
4851− switch (JEDEC_MFR(nor->info)) {
4852− case SNOR_MFR_SPANSION:
4853− spansion_post_sfdp_fixups(nor);
4854− break;
4855−
4856− default:
4857− break;
4858− }
4859−
4860− if (nor->info->flags & SPI_S3AN)
4861− s3an_post_sfdp_fixups(nor);
4862−
4863− if (nor->info->fixups && nor->info->fixups->post_sfdp)
4864− nor->info->fixups->post_sfdp(nor);
4865−}
4866−
4867−/**
4868− * spi_nor_late_init_params() - Late initialization of default flash parameters.
4869− * @nor: pointer to a 'struct spi_nor'
4870− *
4871− * Used to set default flash parameters and settings when the ->default_init()
4872− * hook or the SFDP parser let voids.
4873− */
4874−static void spi_nor_late_init_params(struct spi_nor *nor)
4875−{
4876− /*
4877− * NOR protection support. When locking_ops are not provided, we pick
4878− * the default ones.
4879− */
4880− if (nor->flags & SNOR_F_HAS_LOCK && !nor->params.locking_ops)
4881− nor->params.locking_ops = &stm_locking_ops;
4882−}
4883−
4884−/**
4885− * spi_nor_init_params() - Initialize the flash's parameters and settings.
4886− * @nor: pointer to a 'struct spi-nor'.
4887− *
4888− * The flash parameters and settings are initialized based on a sequence of
4889− * calls that are ordered by priority:
4890− *
4891− * 1/ Default flash parameters initialization. The initializations are done
4892− * based on nor->info data:
4893− * spi_nor_info_init_params()
4894− *
4895− * which can be overwritten by:
4896− * 2/ Manufacturer flash parameters initialization. The initializations are
4897− * done based on MFR register, or when the decisions can not be done solely
4898− * based on MFR, by using specific flash_info tweeks, ->default_init():
4899− * spi_nor_manufacturer_init_params()
4900− *
4901− * which can be overwritten by:
4902− * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and
4903− * should be more accurate that the above.
4904− * spi_nor_sfdp_init_params()
4905− *
4906− * Please note that there is a ->post_bfpt() fixup hook that can overwrite
4907− * the flash parameters and settings immediately after parsing the Basic
4908− * Flash Parameter Table.
4909− *
4910− * which can be overwritten by:
4911− * 4/ Post SFDP flash parameters initialization. Used to tweak various
4912− * parameters that could not be extracted by other means (i.e. when
4913− * information provided by the SFDP/flash_info tables are incomplete or
4914− * wrong).
4915− * spi_nor_post_sfdp_fixups()
4916− *
4917− * 5/ Late default flash parameters initialization, used when the
4918− * ->default_init() hook or the SFDP parser do not set specific params.
4919− * spi_nor_late_init_params()
4920− */
4921−static void spi_nor_init_params(struct spi_nor *nor)
4922−{
4923− spi_nor_info_init_params(nor);
4924−
4925− spi_nor_manufacturer_init_params(nor);
4926−
4927− if ((nor->info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
4928− !(nor->info->flags & SPI_NOR_SKIP_SFDP))
4929− spi_nor_sfdp_init_params(nor);
4930−
4931− spi_nor_post_sfdp_fixups(nor);
4932−
4933− spi_nor_late_init_params(nor);
4934−}
4935−
4936−/**
4937− * spi_nor_quad_enable() - enable Quad I/O if needed.
4938− * @nor: pointer to a 'struct spi_nor'
4939− *
4940− * Return: 0 on success, -errno otherwise.
4941− */
4942−static int spi_nor_quad_enable(struct spi_nor *nor)
4943−{
4944− if (!nor->params.quad_enable)
4945− return 0;
4946−
4947− if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
4948− spi_nor_get_protocol_width(nor->write_proto) == 4))
4949− return 0;
4950−
4951− return nor->params.quad_enable(nor);
4952−}
4953−
4954−/**
4955− * spi_nor_unlock_all() - Unlocks the entire flash memory array.
4956− * @nor: pointer to a 'struct spi_nor'.
4957− *
4958− * Some SPI NOR flashes are write protected by default after a power-on reset
4959− * cycle, in order to avoid inadvertent writes during power-up. Backward
4960− * compatibility imposes to unlock the entire flash memory array at power-up
4961− * by default.
4962− */
4963−static int spi_nor_unlock_all(struct spi_nor *nor)
4964−{
4965− if (nor->flags & SNOR_F_HAS_LOCK)
4966− return spi_nor_unlock(&nor->mtd, 0, nor->params.size);
4967−
4968− return 0;
4969−}
4970−
4971−static int spi_nor_init(struct spi_nor *nor)
4972−{
4973− int err;
4974−
4975− err = spi_nor_quad_enable(nor);
4976− if (err) {
4977− dev_dbg(nor->dev, "quad mode not supported\n");
4978− return err;
4979− }
4980−
4981− err = spi_nor_unlock_all(nor);
4982− if (err) {
4983− dev_dbg(nor->dev, "Failed to unlock the entire flash memory array\n");
4984− return err;
4985− }
4986−
4987− if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES)) {
4988− /*
4989− * If the RESET# pin isn't hooked up properly, or the system
4990− * otherwise doesn't perform a reset command in the boot
4991− * sequence, it's impossible to 100% protect against unexpected
4992− * reboots (e.g., crashes). Warn the user (or hopefully, system
4993− * designer) that this is bad.
4994− */
4995− WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
4996− "enabling reset hack; may not recover from unexpected reboots\n");
4997− nor->params.set_4byte(nor, true);
4998− }
4999−

435 more lines aren’t shown here.

drivers/mtd/spi-nor/sst.c+151−0
@@ -0,0 +1,151 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static const struct flash_info sst_parts[] = {
12+ /* SST -- large erase sizes are "overlays", "sectors" are 4K */
13+ { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8,
14+ SECT_4K | SST_WRITE) },
15+ { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16,
16+ SECT_4K | SST_WRITE) },
17+ { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32,
18+ SECT_4K | SST_WRITE) },
19+ { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64,
20+ SECT_4K | SST_WRITE) },
21+ { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
22+ { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1,
23+ SECT_4K | SST_WRITE) },
24+ { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2,
25+ SECT_4K | SST_WRITE) },
26+ { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4,
27+ SECT_4K | SST_WRITE) },
28+ { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
29+ { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
30+ { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8,
31+ SECT_4K | SST_WRITE) },
32+ { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16,
33+ SECT_4K | SST_WRITE) },
34+ { "sst26wf016b", INFO(0xbf2651, 0, 64 * 1024, 32,
35+ SECT_4K | SPI_NOR_DUAL_READ |
36+ SPI_NOR_QUAD_READ) },
37+ { "sst26vf016b", INFO(0xbf2641, 0, 64 * 1024, 32,
38+ SECT_4K | SPI_NOR_DUAL_READ) },
39+ { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128,
40+ SECT_4K | SPI_NOR_DUAL_READ |
41+ SPI_NOR_QUAD_READ) },
42+};
43+
44+static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
45+ size_t *retlen, const u_char *buf)
46+{
47+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
48+ size_t actual = 0;
49+ int ret;
50+
51+ dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
52+
53+ ret = spi_nor_lock_and_prep(nor);
54+ if (ret)
55+ return ret;
56+
57+ ret = spi_nor_write_enable(nor);
58+ if (ret)
59+ goto out;
60+
61+ nor->sst_write_second = false;
62+
63+ /* Start write from odd address. */
64+ if (to % 2) {
65+ nor->program_opcode = SPINOR_OP_BP;
66+
67+ /* write one byte. */
68+ ret = spi_nor_write_data(nor, to, 1, buf);
69+ if (ret < 0)
70+ goto out;
71+ WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret);
72+ ret = spi_nor_wait_till_ready(nor);
73+ if (ret)
74+ goto out;
75+
76+ to++;
77+ actual++;
78+ }
79+
80+ /* Write out most of the data here. */
81+ for (; actual < len - 1; actual += 2) {
82+ nor->program_opcode = SPINOR_OP_AAI_WP;
83+
84+ /* write two bytes. */
85+ ret = spi_nor_write_data(nor, to, 2, buf + actual);
86+ if (ret < 0)
87+ goto out;
88+ WARN(ret != 2, "While writing 2 bytes written %i bytes\n", ret);
89+ ret = spi_nor_wait_till_ready(nor);
90+ if (ret)
91+ goto out;
92+ to += 2;
93+ nor->sst_write_second = true;
94+ }
95+ nor->sst_write_second = false;
96+
97+ ret = spi_nor_write_disable(nor);
98+ if (ret)
99+ goto out;
100+
101+ ret = spi_nor_wait_till_ready(nor);
102+ if (ret)
103+ goto out;
104+
105+ /* Write out trailing byte if it exists. */
106+ if (actual != len) {
107+ ret = spi_nor_write_enable(nor);
108+ if (ret)
109+ goto out;
110+
111+ nor->program_opcode = SPINOR_OP_BP;
112+ ret = spi_nor_write_data(nor, to, 1, buf + actual);
113+ if (ret < 0)
114+ goto out;
115+ WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret);
116+ ret = spi_nor_wait_till_ready(nor);
117+ if (ret)
118+ goto out;
119+
120+ actual += 1;
121+
122+ ret = spi_nor_write_disable(nor);
123+ }
124+out:
125+ *retlen += actual;
126+ spi_nor_unlock_and_unprep(nor);
127+ return ret;
128+}
129+
130+static void sst_default_init(struct spi_nor *nor)
131+{
132+ nor->flags |= SNOR_F_HAS_LOCK;
133+}
134+
135+static void sst_post_sfdp_fixups(struct spi_nor *nor)
136+{
137+ if (nor->info->flags & SST_WRITE)
138+ nor->mtd._write = sst_write;
139+}
140+
141+static const struct spi_nor_fixups sst_fixups = {
142+ .default_init = sst_default_init,
143+ .post_sfdp = sst_post_sfdp_fixups,
144+};
145+
146+const struct spi_nor_manufacturer spi_nor_sst = {
147+ .name = "sst",
148+ .parts = sst_parts,
149+ .nparts = ARRAY_SIZE(sst_parts),
150+ .fixups = &sst_fixups,
151+};
drivers/mtd/spi-nor/winbond.c+112−0
@@ -0,0 +1,112 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static const struct flash_info winbond_parts[] = {
12+ /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
13+ { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
14+ { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
15+ { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
16+ { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
17+ { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
18+ { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
19+ { "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
20+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
21+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
22+ { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
23+ { "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024, 32,
24+ SECT_4K | SPI_NOR_DUAL_READ |
25+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
26+ SPI_NOR_HAS_TB) },
27+ { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
28+ { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
29+ { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
30+ { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
31+ { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
32+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
33+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
34+ { "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
35+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
36+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
37+ },
38+ { "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64,
39+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
40+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
41+ { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
42+ { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
43+ { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
44+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
45+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
46+ { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
47+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
48+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
49+ { "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256,
50+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
51+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
52+ { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
53+ { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
54+ { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
55+ { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512,
56+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
57+ SPI_NOR_4B_OPCODES) },
58+ { "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512,
59+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
60+ { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512,
61+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
62+ { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
63+ SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
64+};
65+
66+/**
67+ * winbond_set_4byte_addr_mode() - Set 4-byte address mode for Winbond flashes.
68+ * @nor: pointer to 'struct spi_nor'.
69+ * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
70+ * address mode.
71+ *
72+ * Return: 0 on success, -errno otherwise.
73+ */
74+static int winbond_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
75+{
76+ int ret;
77+
78+ ret = spi_nor_set_4byte_addr_mode(nor, enable);
79+ if (ret || enable)
80+ return ret;
81+
82+ /*
83+ * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address
84+ * Register to be set to 1, so all 3-byte-address reads come from the
85+ * second 16M. We must clear the register to enable normal behavior.
86+ */
87+ ret = spi_nor_write_enable(nor);
88+ if (ret)
89+ return ret;
90+
91+ ret = spi_nor_write_ear(nor, 0);
92+ if (ret)
93+ return ret;
94+
95+ return spi_nor_write_disable(nor);
96+}
97+
98+static void winbond_default_init(struct spi_nor *nor)
99+{
100+ nor->params->set_4byte_addr_mode = winbond_set_4byte_addr_mode;
101+}
102+
103+static const struct spi_nor_fixups winbond_fixups = {
104+ .default_init = winbond_default_init,
105+};
106+
107+const struct spi_nor_manufacturer spi_nor_winbond = {
108+ .name = "winbond",
109+ .parts = winbond_parts,
110+ .nparts = ARRAY_SIZE(winbond_parts),
111+ .fixups = &winbond_fixups,
112+};
drivers/mtd/spi-nor/xilinx.c+94−0
@@ -0,0 +1,94 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static const struct flash_info xilinx_parts[] = {
12+ /* Xilinx S3AN Internal Flash */
13+ { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
14+ { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
15+ { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
16+ { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
17+ { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
18+};
19+
20+/*
21+ * This code converts an address to the Default Address Mode, that has non
22+ * power of two page sizes. We must support this mode because it is the default
23+ * mode supported by Xilinx tools, it can access the whole flash area and
24+ * changing over to the Power-of-two mode is irreversible and corrupts the
25+ * original data.
26+ * Addr can safely be unsigned int, the biggest S3AN device is smaller than
27+ * 4 MiB.
28+ */
29+static u32 s3an_convert_addr(struct spi_nor *nor, u32 addr)
30+{
31+ u32 offset, page;
32+
33+ offset = addr % nor->page_size;
34+ page = addr / nor->page_size;
35+ page <<= (nor->page_size > 512) ? 10 : 9;
36+
37+ return page | offset;
38+}
39+
40+static int xilinx_nor_setup(struct spi_nor *nor,
41+ const struct spi_nor_hwcaps *hwcaps)
42+{
43+ int ret;
44+
45+ ret = spi_nor_xread_sr(nor, nor->bouncebuf);
46+ if (ret)
47+ return ret;
48+
49+ nor->erase_opcode = SPINOR_OP_XSE;
50+ nor->program_opcode = SPINOR_OP_XPP;
51+ nor->read_opcode = SPINOR_OP_READ;
52+ nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
53+
54+ /*
55+ * This flashes have a page size of 264 or 528 bytes (known as
56+ * Default addressing mode). It can be changed to a more standard
57+ * Power of two mode where the page size is 256/512. This comes
58+ * with a price: there is 3% less of space, the data is corrupted
59+ * and the page size cannot be changed back to default addressing
60+ * mode.
61+ *
62+ * The current addressing mode can be read from the XRDSR register
63+ * and should not be changed, because is a destructive operation.
64+ */
65+ if (nor->bouncebuf[0] & XSR_PAGESIZE) {
66+ /* Flash in Power of 2 mode */
67+ nor->page_size = (nor->page_size == 264) ? 256 : 512;
68+ nor->mtd.writebufsize = nor->page_size;
69+ nor->mtd.size = 8 * nor->page_size * nor->info->n_sectors;
70+ nor->mtd.erasesize = 8 * nor->page_size;
71+ } else {
72+ /* Flash in Default addressing mode */
73+ nor->params->convert_addr = s3an_convert_addr;
74+ nor->mtd.erasesize = nor->info->sector_size;
75+ }
76+
77+ return 0;
78+}
79+
80+static void xilinx_post_sfdp_fixups(struct spi_nor *nor)
81+{
82+ nor->params->setup = xilinx_nor_setup;
83+}
84+
85+static const struct spi_nor_fixups xilinx_fixups = {
86+ .post_sfdp = xilinx_post_sfdp_fixups,
87+};
88+
89+const struct spi_nor_manufacturer spi_nor_xilinx = {
90+ .name = "xilinx",
91+ .parts = xilinx_parts,
92+ .nparts = ARRAY_SIZE(xilinx_parts),
93+ .fixups = &xilinx_fixups,
94+};
drivers/mtd/spi-nor/xmc.c+23−0
@@ -0,0 +1,23 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2005, Intec Automation Inc.
4+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
5+ */
6+
7+#include <linux/mtd/spi-nor.h>
8+
9+#include "core.h"
10+
11+static const struct flash_info xmc_parts[] = {
12+ /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
13+ { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128,
14+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
15+ { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256,
16+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
17+};
18+
19+const struct spi_nor_manufacturer spi_nor_xmc = {
20+ .name = "xmc",
21+ .parts = xmc_parts,
22+ .nparts = ARRAY_SIZE(xmc_parts),
23+};
drivers/mtd/ubi/attach.c+1−1
@@ -1059,7 +1059,7 @@ static int scan_peb(struct ubi_device *ubi, struct ubi_attach_info *ai, · 1058 unmodified lines
10591059 * be a result of power cut during erasure.
10601060 */
10611061 ai->maybe_bad_peb_count += 1;
1062− /* fall through */
1062+ fallthrough;
10631063 case UBI_IO_BAD_HDR:
10641064 /*
10651065 * If we're facing a bad VID header we have to drop *all*
drivers/mtd/ubi/build.c+2−2
@@ -1342,10 +1342,10 @@ static int bytes_str_to_int(const char *str) · 1341 unmodified lines
13421342 switch (*endp) {
13431343 case 'G':
13441344 result *= 1024;
1345− /* fall through */
1345+ fallthrough;
13461346 case 'M':
13471347 result *= 1024;
1348− /* fall through */
1348+ fallthrough;
13491349 case 'K':
13501350 result *= 1024;
13511351 if (endp[1] == 'i' && endp[2] == 'B')
include/linux/mtd/mtd.h+115−10
@@ -8,6 +8,7 @@ · 7 unmodified lines
88
99 #include <linux/types.h>
1010 #include <linux/uio.h>
11+#include <linux/list.h>
1112 #include <linux/notifier.h>
1213 #include <linux/device.h>
1314 #include <linux/of.h>
@@ -194,10 +195,43 @@ struct mtd_debug_info { · 180 unmodified lines
194195 const char *partid;
195196 };
196197
198+/**
199+ * struct mtd_part - MTD partition specific fields
200+ *
201+ * @node: list node used to add an MTD partition to the parent partition list
202+ * @offset: offset of the partition relatively to the parent offset
203+ * @flags: original flags (before the mtdpart logic decided to tweak them based
204+ * on flash constraints, like eraseblock/pagesize alignment)
205+ *
206+ * This struct is embedded in mtd_info and contains partition-specific
207+ * properties/fields.
208+ */
209+struct mtd_part {
210+ struct list_head node;
211+ u64 offset;
212+ u32 flags;
213+};
214+
215+/**
216+ * struct mtd_master - MTD master specific fields
217+ *
218+ * @partitions_lock: lock protecting accesses to the partition list. Protects
219+ * not only the master partition list, but also all
220+ * sub-partitions.
221+ * @suspended: et to 1 when the device is suspended, 0 otherwise
222+ *
223+ * This struct is embedded in mtd_info and contains master-specific
224+ * properties/fields. The master is the root MTD device from the MTD partition
225+ * point of view.
226+ */
227+struct mtd_master {
228+ struct mutex partitions_lock;
229+ unsigned int suspended : 1;
230+};
231+
197232 struct mtd_info {
198233 u_char type;
199234 uint32_t flags;
200− uint32_t orig_flags; /* Flags as before running mtd checks */
201235 uint64_t size; // Total size of the MTD
202236
203237 /* "Major" erase size for the device. Naïve users may take this
@@ -339,8 +373,52 @@ struct mtd_info { · 135 unmodified lines
339373 int usecount;
340374 struct mtd_debug_info dbg;
341375 struct nvmem_device *nvmem;
376+
377+ /*
378+ * Parent device from the MTD partition point of view.
379+ *
380+ * MTD masters do not have any parent, MTD partitions do. The parent
381+ * MTD device can itself be a partition.
382+ */
383+ struct mtd_info *parent;
384+
385+ /* List of partitions attached to this MTD device */
386+ struct list_head partitions;
387+
388+ union {
389+ struct mtd_part part;
390+ struct mtd_master master;
391+ };
342392 };
343393
394+static inline struct mtd_info *mtd_get_master(struct mtd_info *mtd)
395+{
396+ while (mtd->parent)
397+ mtd = mtd->parent;
398+
399+ return mtd;
400+}
401+
402+static inline u64 mtd_get_master_ofs(struct mtd_info *mtd, u64 ofs)
403+{
404+ while (mtd->parent) {
405+ ofs += mtd->part.offset;
406+ mtd = mtd->parent;
407+ }
408+
409+ return ofs;
410+}
411+
412+static inline bool mtd_is_partition(const struct mtd_info *mtd)
413+{
414+ return mtd->parent;
415+}
416+
417+static inline bool mtd_has_partitions(const struct mtd_info *mtd)
418+{
419+ return !list_empty(&mtd->partitions);
420+}
421+
344422 int mtd_ooblayout_ecc(struct mtd_info *mtd, int section,
345423 struct mtd_oob_region *oobecc);
346424 int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte,
@@ -392,13 +470,16 @@ static inline u32 mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops) · 45 unmodified lines
392470 static inline int mtd_max_bad_blocks(struct mtd_info *mtd,
393471 loff_t ofs, size_t len)
394472 {
395− if (!mtd->_max_bad_blocks)
473+ struct mtd_info *master = mtd_get_master(mtd);
474+
475+ if (!master->_max_bad_blocks)
396476 return -ENOTSUPP;
397477
398478 if (mtd->size < (len + ofs) || ofs < 0)
399479 return -EINVAL;
400480
401− return mtd->_max_bad_blocks(mtd, ofs, len);
481+ return master->_max_bad_blocks(master, mtd_get_master_ofs(mtd, ofs),
482+ len);
402483 }
403484
404485 int mtd_wunit_to_pairing_info(struct mtd_info *mtd, int wunit,
@@ -439,8 +520,10 @@ int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs, · 34 unmodified lines
439520
440521 static inline void mtd_sync(struct mtd_info *mtd)
441522 {
442− if (mtd->_sync)
443− mtd->_sync(mtd);
523+ struct mtd_info *master = mtd_get_master(mtd);
524+
525+ if (master->_sync)
526+ master->_sync(master);
444527 }
445528
446529 int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
@@ -452,13 +535,31 @@ int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs); · 5 unmodified lines
452535
453536 static inline int mtd_suspend(struct mtd_info *mtd)
454537 {
455− return mtd->_suspend ? mtd->_suspend(mtd) : 0;
538+ struct mtd_info *master = mtd_get_master(mtd);
539+ int ret;
540+
541+ if (master->master.suspended)
542+ return 0;
543+
544+ ret = master->_suspend ? master->_suspend(master) : 0;
545+ if (ret)
546+ return ret;
547+
548+ master->master.suspended = 1;
549+ return 0;
456550 }
457551
458552 static inline void mtd_resume(struct mtd_info *mtd)
459553 {
460− if (mtd->_resume)
461− mtd->_resume(mtd);
554+ struct mtd_info *master = mtd_get_master(mtd);
555+
556+ if (!master->master.suspended)
557+ return;
558+
559+ if (master->_resume)
560+ master->_resume(master);
561+
562+ master->master.suspended = 0;
462563 }
463564
464565 static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd)
@@ -538,7 +639,9 @@ static inline loff_t mtd_wunit_to_offset(struct mtd_info *mtd, loff_t base, · 73 unmodified lines
538639
539640 static inline int mtd_has_oob(const struct mtd_info *mtd)
540641 {
541− return mtd->_read_oob && mtd->_write_oob;
642+ struct mtd_info *master = mtd_get_master((struct mtd_info *)mtd);
643+
644+ return master->_read_oob && master->_write_oob;
542645 }
543646
544647 static inline int mtd_type_is_nand(const struct mtd_info *mtd)
@@ -548,7 +651,9 @@ static inline int mtd_type_is_nand(const struct mtd_info *mtd) · 3 unmodified lines
548651
549652 static inline int mtd_can_have_bb(const struct mtd_info *mtd)
550653 {
551− return !!mtd->_block_isbad;
654+ struct mtd_info *master = mtd_get_master((struct mtd_info *)mtd);
655+
656+ return !!master->_block_isbad;
552657 }
553658
554659 /* Kernel-side ioctl definitions */
include/linux/mtd/partitions.h+0−1
@@ -105,7 +105,6 @@ extern void deregister_mtd_parser(struct mtd_part_parser *parser); · 104 unmodified lines
105105 module_driver(__mtd_part_parser, register_mtd_parser, \
106106 deregister_mtd_parser)
107107
108−int mtd_is_partition(const struct mtd_info *mtd);
109108 int mtd_add_partition(struct mtd_info *master, const char *name,
110109 long long offset, long long length);
111110 int mtd_del_partition(struct mtd_info *master, int partno);
include/linux/mtd/rawnand.h+10−1
@@ -1064,6 +1064,8 @@ struct nand_legacy { · 1063 unmodified lines
10641064 * @lock: lock protecting the suspended field. Also used to
10651065 * serialize accesses to the NAND device.
10661066 * @suspended: set to 1 when the device is suspended, 0 when it's not.
1067+ * @suspend: [REPLACEABLE] specific NAND device suspend operation
1068+ * @resume: [REPLACEABLE] specific NAND device resume operation
10671069 * @bbt: [INTERN] bad block table pointer
10681070 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
10691071 * lookup.
@@ -1077,6 +1079,8 @@ struct nand_legacy { · 7 unmodified lines
10771079 * @manufacturer: [INTERN] Contains manufacturer information
10781080 * @manufacturer.desc: [INTERN] Contains manufacturer's description
10791081 * @manufacturer.priv: [INTERN] Contains manufacturer private information
1082+ * @lock_area: [REPLACEABLE] specific NAND chip lock operation
1083+ * @unlock_area: [REPLACEABLE] specific NAND chip unlock operation
10801084 */
10811085
10821086 struct nand_chip {
@@ -1117,6 +1121,8 @@ struct nand_chip { · 34 unmodified lines
11171121
11181122 struct mutex lock;
11191123 unsigned int suspended : 1;
1124+ int (*suspend)(struct nand_chip *chip);
1125+ void (*resume)(struct nand_chip *chip);
11201126
11211127 uint8_t *oob_poi;
11221128 struct nand_controller *controller;
@@ -1136,6 +1142,9 @@ struct nand_chip { · 13 unmodified lines
11361142 const struct nand_manufacturer *desc;
11371143 void *priv;
11381144 } manufacturer;
1145+
1146+ int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1147+ int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
11391148 };
11401149
11411150 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
@@ -1215,7 +1224,7 @@ static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) · 73 unmodified lines
12151224 * struct nand_flash_dev - NAND Flash Device ID Structure
12161225 * @name: a human-readable name of the NAND chip
12171226 * @dev_id: the device ID (the second byte of the full chip ID array)
1218− * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1227+ * @mfr_id: manufacturer ID part of the full chip ID array (refers the same
12191228 * memory address as ``id[0]``)
12201229 * @dev_id: device ID part of the full chip ID array (refers the same memory
12211230 * address as ``id[1]``)
include/linux/mtd/spi-nor.h+19−266
@@ -11,23 +11,6 @@ · 10 unmodified lines
1111 #include <linux/mtd/mtd.h>
1212 #include <linux/spi/spi-mem.h>
1313
14−/*
15− * Manufacturer IDs
16− *
17− * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
18− * Sometimes these are the same as CFI IDs, but sometimes they aren't.
19− */
20−#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
21−#define SNOR_MFR_GIGADEVICE 0xc8
22−#define SNOR_MFR_INTEL CFI_MFR_INTEL
23−#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */
24−#define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */
25−#define SNOR_MFR_ISSI CFI_MFR_PMC
26−#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
27−#define SNOR_MFR_SPANSION CFI_MFR_AMD
28−#define SNOR_MFR_SST CFI_MFR_SST
29−#define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
30−
3114 /*
3215 * Note on opcode nomenclature: some opcodes have a format like
3316 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
@@ -128,7 +111,9 @@ · 94 unmodified lines
128111 #define SR_BP0 BIT(2) /* Block protect 0 */
129112 #define SR_BP1 BIT(3) /* Block protect 1 */
130113 #define SR_BP2 BIT(4) /* Block protect 2 */
114+#define SR_BP3 BIT(5) /* Block protect 3 */
131115 #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */
116+#define SR_BP3_BIT6 BIT(6) /* Block protect 3 */
132117 #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */
133118 #define SR_SRWD BIT(7) /* SR write protect */
134119 /* Spansion/Cypress specific status bits */
@@ -137,6 +122,8 @@ · 2 unmodified lines
137122
138123 #define SR1_QUAD_EN_BIT6 BIT(6)
139124
125+#define SR_BP_SHIFT 2
126+
140127 /* Enhanced Volatile Configuration Register bits */
141128 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
142129
@@ -225,110 +212,6 @@ static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto) · 82 unmodified lines
225212 return spi_nor_get_protocol_data_nbits(proto);
226213 }
227214
228−enum spi_nor_option_flags {
229− SNOR_F_USE_FSR = BIT(0),
230− SNOR_F_HAS_SR_TB = BIT(1),
231− SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
232− SNOR_F_READY_XSR_RDY = BIT(3),
233− SNOR_F_USE_CLSR = BIT(4),
234− SNOR_F_BROKEN_RESET = BIT(5),
235− SNOR_F_4B_OPCODES = BIT(6),
236− SNOR_F_HAS_4BAIT = BIT(7),
237− SNOR_F_HAS_LOCK = BIT(8),
238− SNOR_F_HAS_16BIT_SR = BIT(9),
239− SNOR_F_NO_READ_CR = BIT(10),
240− SNOR_F_HAS_SR_TB_BIT6 = BIT(11),
241−
242−};
243−
244−/**
245− * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
246− * @size: the size of the sector/block erased by the erase type.
247− * JEDEC JESD216B imposes erase sizes to be a power of 2.
248− * @size_shift: @size is a power of 2, the shift is stored in
249− * @size_shift.
250− * @size_mask: the size mask based on @size_shift.
251− * @opcode: the SPI command op code to erase the sector/block.
252− * @idx: Erase Type index as sorted in the Basic Flash Parameter
253− * Table. It will be used to synchronize the supported
254− * Erase Types with the ones identified in the SFDP
255− * optional tables.
256− */
257−struct spi_nor_erase_type {
258− u32 size;
259− u32 size_shift;
260− u32 size_mask;
261− u8 opcode;
262− u8 idx;
263−};
264−
265−/**
266− * struct spi_nor_erase_command - Used for non-uniform erases
267− * The structure is used to describe a list of erase commands to be executed
268− * once we validate that the erase can be performed. The elements in the list
269− * are run-length encoded.
270− * @list: for inclusion into the list of erase commands.
271− * @count: how many times the same erase command should be
272− * consecutively used.
273− * @size: the size of the sector/block erased by the command.
274− * @opcode: the SPI command op code to erase the sector/block.
275− */
276−struct spi_nor_erase_command {
277− struct list_head list;
278− u32 count;
279− u32 size;
280− u8 opcode;
281−};
282−
283−/**
284− * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region
285− * @offset: the offset in the data array of erase region start.
286− * LSB bits are used as a bitmask encoding flags to
287− * determine if this region is overlaid, if this region is
288− * the last in the SPI NOR flash memory and to indicate
289− * all the supported erase commands inside this region.
290− * The erase types are sorted in ascending order with the
291− * smallest Erase Type size being at BIT(0).
292− * @size: the size of the region in bytes.
293− */
294−struct spi_nor_erase_region {
295− u64 offset;
296− u64 size;
297−};
298−
299−#define SNOR_ERASE_TYPE_MAX 4
300−#define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0)
301−
302−#define SNOR_LAST_REGION BIT(4)
303−#define SNOR_OVERLAID_REGION BIT(5)
304−
305−#define SNOR_ERASE_FLAGS_MAX 6
306−#define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0)
307−
308−/**
309− * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map
310− * @regions: array of erase regions. The regions are consecutive in
311− * address space. Walking through the regions is done
312− * incrementally.
313− * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform
314− * sector size (legacy implementation).
315− * @erase_type: an array of erase types shared by all the regions.
316− * The erase types are sorted in ascending order, with the
317− * smallest Erase Type size being the first member in the
318− * erase_type array.
319− * @uniform_erase_type: bitmask encoding erase types that can erase the
320− * entire memory. This member is completed at init by
321− * uniform and non-uniform SPI NOR flash memories if they
322− * support at least one erase type that can erase the
323− * entire memory.
324− */
325−struct spi_nor_erase_map {
326− struct spi_nor_erase_region *regions;
327− struct spi_nor_erase_region uniform_region;
328− struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX];
329− u8 uniform_erase_type;
330−};
331−
332215 /**
333216 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
334217 * supported by the SPI controller (bus master).
@@ -404,61 +287,7 @@ struct spi_nor_hwcaps { · 69 unmodified lines
404287 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
405288 SNOR_HWCAPS_PP_MASK)
406289
407−struct spi_nor_read_command {
408− u8 num_mode_clocks;
409− u8 num_wait_states;
410− u8 opcode;
411− enum spi_nor_protocol proto;
412−};
413−
414−struct spi_nor_pp_command {
415− u8 opcode;
416− enum spi_nor_protocol proto;
417−};
418−
419−enum spi_nor_read_command_index {
420− SNOR_CMD_READ,
421− SNOR_CMD_READ_FAST,
422− SNOR_CMD_READ_1_1_1_DTR,
423−
424− /* Dual SPI */
425− SNOR_CMD_READ_1_1_2,
426− SNOR_CMD_READ_1_2_2,
427− SNOR_CMD_READ_2_2_2,
428− SNOR_CMD_READ_1_2_2_DTR,
429−
430− /* Quad SPI */
431− SNOR_CMD_READ_1_1_4,
432− SNOR_CMD_READ_1_4_4,
433− SNOR_CMD_READ_4_4_4,
434− SNOR_CMD_READ_1_4_4_DTR,
435−
436− /* Octal SPI */
437− SNOR_CMD_READ_1_1_8,
438− SNOR_CMD_READ_1_8_8,
439− SNOR_CMD_READ_8_8_8,
440− SNOR_CMD_READ_1_8_8_DTR,
441−
442− SNOR_CMD_READ_MAX
443−};
444−
445−enum spi_nor_pp_command_index {
446− SNOR_CMD_PP,
447−
448− /* Quad SPI */
449− SNOR_CMD_PP_1_1_4,
450− SNOR_CMD_PP_1_4_4,
451− SNOR_CMD_PP_4_4_4,
452−
453− /* Octal SPI */
454− SNOR_CMD_PP_1_1_8,
455− SNOR_CMD_PP_1_8_8,
456− SNOR_CMD_PP_8_8_8,
457−
458− SNOR_CMD_PP_MAX
459−};
460−
461−/* Forward declaration that will be used in 'struct spi_nor_flash_parameter' */
290+/* Forward declaration that is used in 'struct spi_nor_controller_ops' */
462291 struct spi_nor;
463292
464293 /**
@@ -489,68 +318,13 @@ struct spi_nor_controller_ops { · 24 unmodified lines
489318 int (*erase)(struct spi_nor *nor, loff_t offs);
490319 };
491320
492−/**
493− * struct spi_nor_locking_ops - SPI NOR locking methods
494− * @lock: lock a region of the SPI NOR.
495− * @unlock: unlock a region of the SPI NOR.
496− * @is_locked: check if a region of the SPI NOR is completely locked
497− */
498−struct spi_nor_locking_ops {
499− int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
500− int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
501− int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
502−};
503−
504−/**
505− * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings.
506− * Includes legacy flash parameters and settings that can be overwritten
507− * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216
508− * Serial Flash Discoverable Parameters (SFDP) tables.
509− *
510− * @size: the flash memory density in bytes.
511− * @page_size: the page size of the SPI NOR flash memory.
512− * @hwcaps: describes the read and page program hardware
513− * capabilities.
514− * @reads: read capabilities ordered by priority: the higher index
515− * in the array, the higher priority.
516− * @page_programs: page program capabilities ordered by priority: the
517− * higher index in the array, the higher priority.
518− * @erase_map: the erase map parsed from the SFDP Sector Map Parameter
519− * Table.
520− * @quad_enable: enables SPI NOR quad mode.
521− * @set_4byte: puts the SPI NOR in 4 byte addressing mode.
522− * @convert_addr: converts an absolute address into something the flash
523− * will understand. Particularly useful when pagesize is
524− * not a power-of-2.
525− * @setup: configures the SPI NOR memory. Useful for SPI NOR
526− * flashes that have peculiarities to the SPI NOR standard
527− * e.g. different opcodes, specific address calculation,
528− * page size, etc.
529− * @locking_ops: SPI NOR locking methods.
530− */
531−struct spi_nor_flash_parameter {
532− u64 size;
533− u32 page_size;
534−
535− struct spi_nor_hwcaps hwcaps;
536− struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
537− struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
538−
539− struct spi_nor_erase_map erase_map;
540−
541− int (*quad_enable)(struct spi_nor *nor);
542− int (*set_4byte)(struct spi_nor *nor, bool enable);
543− u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
544− int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
545−
546− const struct spi_nor_locking_ops *locking_ops;
547−};
548−
549−/**
550− * struct flash_info - Forward declaration of a structure used internally by
551− * spi_nor_scan()
321+/*
322+ * Forward declarations that are used internally by the core and manufacturer
323+ * drivers.
552324 */
553325 struct flash_info;
326+struct spi_nor_manufacturer;
327+struct spi_nor_flash_parameter;
554328
555329 /**
556330 * struct spi_nor - Structure for defining a the SPI NOR layer
@@ -562,6 +336,7 @@ struct flash_info; · 5 unmodified lines
562336 * layer is not DMA-able
563337 * @bouncebuf_size: size of the bounce buffer
564338 * @info: spi-nor part JDEC MFR id and other info
339+ * @manufacturer: spi-nor manufacturer
565340 * @page_size: the page size of the SPI NOR
566341 * @addr_width: number of address bytes
567342 * @erase_opcode: the opcode for erasing a sector
@@ -578,6 +353,7 @@ struct flash_info; · 10 unmodified lines
578353 * The structure includes legacy flash parameters and
579354 * settings that can be overwritten by the spi_nor_fixups
580355 * hooks, or dynamically when parsing the SFDP tables.
356+ * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes.
581357 * @priv: the private data
582358 */
583359 struct spi_nor {
@@ -588,6 +364,7 @@ struct spi_nor { · 4 unmodified lines
588364 u8 *bouncebuf;
589365 size_t bouncebuf_size;
590366 const struct flash_info *info;
367+ const struct spi_nor_manufacturer *manufacturer;
591368 u32 page_size;
592369 u8 addr_width;
593370 u8 erase_opcode;
@@ -602,40 +379,16 @@ struct spi_nor { · 8 unmodified lines
602379
603380 const struct spi_nor_controller_ops *controller_ops;
604381
605− struct spi_nor_flash_parameter params;
382+ struct spi_nor_flash_parameter *params;
383+
384+ struct {
385+ struct spi_mem_dirmap_desc *rdesc;
386+ struct spi_mem_dirmap_desc *wdesc;
387+ } dirmap;
606388
607389 void *priv;
608390 };
609391
610−static u64 __maybe_unused
611−spi_nor_region_is_last(const struct spi_nor_erase_region *region)
612−{
613− return region->offset & SNOR_LAST_REGION;
614−}
615−
616−static u64 __maybe_unused
617−spi_nor_region_end(const struct spi_nor_erase_region *region)
618−{
619− return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size;
620−}
621−
622−static void __maybe_unused
623−spi_nor_region_mark_end(struct spi_nor_erase_region *region)
624−{
625− region->offset |= SNOR_LAST_REGION;
626−}
627−
628−static void __maybe_unused
629−spi_nor_region_mark_overlay(struct spi_nor_erase_region *region)
630−{
631− region->offset |= SNOR_OVERLAID_REGION;
632−}
633−
634−static bool __maybe_unused spi_nor_has_uniform_erase(const struct spi_nor *nor)
635−{
636− return !!nor->params.erase_map.uniform_erase_type;
637−}
638−
639392 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
640393 struct device_node *np)
641394 {
include/linux/mtd/spinand.h+45−22
@@ -32,9 +32,9 @@ · 31 unmodified lines
3232 SPI_MEM_OP_NO_DUMMY, \
3333 SPI_MEM_OP_NO_DATA)
3434
35−#define SPINAND_READID_OP(ndummy, buf, len) \
35+#define SPINAND_READID_OP(naddr, ndummy, buf, len) \
3636 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
37− SPI_MEM_OP_NO_ADDR, \
37+ SPI_MEM_OP_ADDR(naddr, 0, 1), \
3838 SPI_MEM_OP_DUMMY(ndummy, 1), \
3939 SPI_MEM_OP_DATA_IN(len, buf, 1))
4040
@@ -176,37 +176,46 @@ struct spinand_device; · 135 unmodified lines
176176 * @data: buffer containing the id bytes. Currently 4 bytes large, but can
177177 * be extended if required
178178 * @len: ID length
179− *
180− * struct_spinand_id->data contains all bytes returned after a READ_ID command,
181− * including dummy bytes if the chip does not emit ID bytes right after the
182− * READ_ID command. The responsibility to extract real ID bytes is left to
183− * struct_manufacurer_ops->detect().
184179 */
185180 struct spinand_id {
186181 u8 data[SPINAND_MAX_ID_LEN];
187182 int len;
188183 };
189184
185+enum spinand_readid_method {
186+ SPINAND_READID_METHOD_OPCODE,
187+ SPINAND_READID_METHOD_OPCODE_ADDR,
188+ SPINAND_READID_METHOD_OPCODE_DUMMY,
189+};
190+
191+/**
192+ * struct spinand_devid - SPI NAND device id structure
193+ * @id: device id of current chip
194+ * @len: number of bytes in device id
195+ * @method: method to read chip id
196+ * There are 3 possible variants:
197+ * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
198+ * after read_id opcode.
199+ * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
200+ * read_id opcode + 1-byte address.
201+ * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
202+ * read_id opcode + 1 dummy byte.
203+ */
204+struct spinand_devid {
205+ const u8 *id;
206+ const u8 len;
207+ const enum spinand_readid_method method;
208+};
209+
190210 /**
191211 * struct manufacurer_ops - SPI NAND manufacturer specific operations
192− * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed
193− * the core calls the struct_manufacurer_ops->detect() hook of each
194− * registered manufacturer until one of them return 1. Note that
195− * the first thing to check in this hook is that the manufacturer ID
196− * in struct_spinand_device->id matches the manufacturer whose
197− * ->detect() hook has been called. Should return 1 if there's a
198− * match, 0 if the manufacturer ID does not match and a negative
199− * error code otherwise. When true is returned, the core assumes
200− * that properties of the NAND chip (spinand->base.memorg and
201− * spinand->base.eccreq) have been filled
202212 * @init: initialize a SPI NAND device
203213 * @cleanup: cleanup a SPI NAND device
204214 *
205215 * Each SPI NAND manufacturer driver should implement this interface so that
206− * NAND chips coming from this vendor can be detected and initialized properly.
216+ * NAND chips coming from this vendor can be initialized properly.
207217 */
208218 struct spinand_manufacturer_ops {
209− int (*detect)(struct spinand_device *spinand);
210219 int (*init)(struct spinand_device *spinand);
211220 void (*cleanup)(struct spinand_device *spinand);
212221 };
@@ -215,11 +224,16 @@ struct spinand_manufacturer_ops { · 2 unmodified lines
215224 * struct spinand_manufacturer - SPI NAND manufacturer instance
216225 * @id: manufacturer ID
217226 * @name: manufacturer name
227+ * @devid_len: number of bytes in device ID
228+ * @chips: supported SPI NANDs under current manufacturer
229+ * @nchips: number of SPI NANDs available in chips array
218230 * @ops: manufacturer operations
219231 */
220232 struct spinand_manufacturer {
221233 u8 id;
222234 char *name;
235+ const struct spinand_info *chips;
236+ const size_t nchips;
223237 const struct spinand_manufacturer_ops *ops;
224238 };
225239
@@ -270,6 +284,7 @@ struct spinand_ecc_info { · 44 unmodified lines
270284 };
271285
272286 #define SPINAND_HAS_QE_BIT BIT(0)
287+#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
273288
274289 /**
275290 * struct spinand_info - Structure used to describe SPI NAND chips
@@ -291,7 +306,7 @@ struct spinand_ecc_info { · 15 unmodified lines
291306 */
292307 struct spinand_info {
293308 const char *model;
294− u16 devid;
309+ struct spinand_devid devid;
295310 u32 flags;
296311 struct nand_memory_organization memorg;
297312 struct nand_ecc_req eccreq;
@@ -305,6 +320,13 @@ struct spinand_info { · 7 unmodified lines
305320 unsigned int target);
306321 };
307322
323+#define SPINAND_ID(__method, ...) \
324+ { \
325+ .id = (const u8[]){ __VA_ARGS__ }, \
326+ .len = sizeof((u8[]){ __VA_ARGS__ }), \
327+ .method = __method, \
328+ }
329+
308330 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
309331 { \
310332 .read_cache = __read, \
@@ -451,9 +473,10 @@ static inline void spinand_set_of_node(struct spinand_device *spinand, · 140 unmodified lines
451473 nanddev_set_of_node(&spinand->base, np);
452474 }
453475
454−int spinand_match_and_init(struct spinand_device *dev,
476+int spinand_match_and_init(struct spinand_device *spinand,
455477 const struct spinand_info *table,
456− unsigned int table_size, u16 devid);
478+ unsigned int table_size,
479+ enum spinand_readid_method rdid_method);
457480
458481 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
459482 int spinand_select_target(struct spinand_device *spinand, unsigned int target);