lael-labs/linux

MAINTAINERS+0−2

@@ -7081,9 +7081,7 @@ S: Maintained · 7080 unmodified lines
7081	F: drivers/mmc/host/cqhci*	7081	F: drivers/mmc/host/cqhci*
7082		7082
7083	EMULEX 10Gbps iSCSI - OneConnect DRIVER	7083	EMULEX 10Gbps iSCSI - OneConnect DRIVER
7084	M: Subbu Seetharaman <subbu.seetharaman@broadcom.com>
7085	M: Ketan Mukadam <ketan.mukadam@broadcom.com>	7084	M: Ketan Mukadam <ketan.mukadam@broadcom.com>
7086	M: Jitendra Bhivare <jitendra.bhivare@broadcom.com>
7087	L: linux-scsi@vger.kernel.org	7085	L: linux-scsi@vger.kernel.org
7088	S: Supported	7086	S: Supported
7089	W: http://www.broadcom.com	7087	W: http://www.broadcom.com

block/blk-pm.c+7−15

 /**
  * blk_post_runtime_resume - Post runtime resume processing
  * @q: the queue of the device
- * @err: return value of the device's runtime_resume function
  *
  * Description:
- *    Update the queue's runtime status according to the return value of the
+ *    For historical reasons, this routine merely calls blk_set_runtime_active()
- *    device's runtime_resume function. If the resume was successful, call
+ *    to do the real work of restarting the queue.  It does this regardless of
- *    blk_set_runtime_active() to do the real work of restarting the queue.
+ *    whether the device's runtime-resume succeeded; even if it failed the
+ *    driver or error handler will need to communicate with the device.
  *
  *    This function should be called near the end of the device's
  *    runtime_resume callback.
  */
-void blk_post_runtime_resume(struct request_queue *q, int err)
+void blk_post_runtime_resume(struct request_queue *q)
 {
-	if (!q->dev)
+	blk_set_runtime_active(q);
-		return;
-	if (!err) {
-		blk_set_runtime_active(q);
-	} else {
-		spin_lock_irq(&q->queue_lock);
-		q->rpm_status = RPM_SUSPENDED;
-		spin_unlock_irq(&q->queue_lock);
-	}
 }
 EXPORT_SYMBOL(blk_post_runtime_resume);
  * runtime PM status and re-enable peeking requests from the queue. It
  * should be called before first request is added to the queue.
  *
- * This function is also called by blk_post_runtime_resume() for successful
+ * This function is also called by blk_post_runtime_resume() for
  * runtime resumes.  It does everything necessary to restart the queue.
  */
 void blk_set_runtime_active(struct request_queue *q)

drivers/message/fusion/mptbase.c+2−4

 static int
 mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag)
 {
-	int	 r = 0;
 	/* return if in use */
 	if (CHIPREG_READ32(&ioc->chip->Doorbell)
 	    & MPI_DOORBELL_ACTIVE)
 		 (access_control_value<<12)));
 	/* Wait for IOC to clear Doorbell Status bit */
-	if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
+	if (WaitForDoorbellAck(ioc, 5, sleepFlag) < 0)
 		return -2;
-	}else
+	else
 		return 0;
 }

drivers/scsi/a100u2w.c+0−2

 /**
  *	inia100_queue_lck		-	queue command with host
  *	@cmd: Command block
- *	@done: Completion function
  *
  *	Called by the mid layer to queue a command. Process the command
  *	block, build the host specific scb structures and if there is room
  *	queue the command down to the controller
  */
 static int inia100_queue_lck(struct scsi_cmnd *cmd)
 {
 	struct orc_scb *scb;

drivers/scsi/atp870u.c+0−1

@@ -614,7 +614,6 @@ static irqreturn_t atp870u_intr_handle(int irq, void *dev_id) · 613 unmodified lines
614	/**	614	/**
615	* atp870u_queuecommand_lck - Queue SCSI command	615	* atp870u_queuecommand_lck - Queue SCSI command
616	* @req_p: request block	616	* @req_p: request block
617	* @done: completion function
618	*	617	*
619	* Queue a command to the ATP queue. Called with the host lock held.	618	* Queue a command to the ATP queue. Called with the host lock held.
620	*/	619	*/

drivers/scsi/bfa/bfad_attr.c+1−1

@@ -981,7 +981,7 @@ const struct attribute_group *bfad_im_host_groups[] = { · 980 unmodified lines
981	NULL	981	NULL
982	};	982	};
983		983
984	struct attribute *bfad_im_vport_attrs[] = {	984	static struct attribute *bfad_im_vport_attrs[] = {
985	&dev_attr_serial_number.attr,	985	&dev_attr_serial_number.attr,
986	&dev_attr_model.attr,	986	&dev_attr_model.attr,
987	&dev_attr_model_description.attr,	987	&dev_attr_model_description.attr,

drivers/scsi/ch.c+3−3

@@ -239,7 +239,7 @@ ch_read_element_status(scsi_changer ch, u_int elem, char data) · 238 unmodified lines
239	u_char *buffer;	239	u_char *buffer;
240	int result;	240	int result;
241		241
242	buffer = kmalloc(512, GFP_KERNEL \| GFP_DMA);	242	buffer = kmalloc(512, GFP_KERNEL);
243	if(!buffer)	243	if(!buffer)
244	return -ENOMEM;	244	return -ENOMEM;
245		245
@@ -297,7 +297,7 @@ ch_readconfig(scsi_changer *ch) · 51 unmodified lines
297	int result,id,lun,i;	297	int result,id,lun,i;
298	u_int elem;	298	u_int elem;
299		299
300	buffer = kzalloc(512, GFP_KERNEL \| GFP_DMA);	300	buffer = kzalloc(512, GFP_KERNEL);
301	if (!buffer)	301	if (!buffer)
302	return -ENOMEM;	302	return -ENOMEM;
303		303
@@ -783,7 +783,7 @@ static long ch_ioctl(struct file *file, · 479 unmodified lines
783	return -EINVAL;	783	return -EINVAL;
784	elem = ch->firsts[cge.cge_type] + cge.cge_unit;	784	elem = ch->firsts[cge.cge_type] + cge.cge_unit;
785		785
786	buffer = kmalloc(512, GFP_KERNEL \| GFP_DMA);	786	buffer = kmalloc(512, GFP_KERNEL);
787	if (!buffer)	787	if (!buffer)
788	return -ENOMEM;	788	return -ENOMEM;
789	mutex_lock(&ch->lock);	789	mutex_lock(&ch->lock);

drivers/scsi/dc395x.c+1−2

  * layer, invoke 'done' on completion
  *
  * @cmd: pointer to scsi command object
- * @done: function pointer to be invoked on completion
  *
  * Returns 1 if the adapter (host) is busy, else returns 0. One
  * reason for an adapter to be busy is that the number
  * Locks: struct Scsi_Host::host_lock held on entry (with "irqsave")
  *        and is expected to be held on return.
  *
- **/
+ */
 static int dc395x_queue_command_lck(struct scsi_cmnd *cmd)
 {
 	void (*done)(struct scsi_cmnd *) = scsi_done;

drivers/scsi/elx/efct/efct_driver.c+1−1

@@ -261,7 +261,7 @@ efct_firmware_write(struct efct efct, const u8 buf, size_t buf_len, · 260 unmodified lines
261		261
262	dma.size = FW_WRITE_BUFSIZE;	262	dma.size = FW_WRITE_BUFSIZE;
263	dma.virt = dma_alloc_coherent(&efct->pci->dev,	263	dma.virt = dma_alloc_coherent(&efct->pci->dev,
264	dma.size, &dma.phys, GFP_DMA);	264	dma.size, &dma.phys, GFP_KERNEL);
265	if (!dma.virt)	265	if (!dma.virt)
266	return -ENOMEM;	266	return -ENOMEM;
267		267

drivers/scsi/elx/efct/efct_hw.c+5−5

@@ -516,7 +516,7 @@ efct_hw_setup_io(struct efct_hw *hw) · 515 unmodified lines
516	dma = &hw->xfer_rdy;	516	dma = &hw->xfer_rdy;
517	dma->size = sizeof(struct fcp_txrdy) * hw->config.n_io;	517	dma->size = sizeof(struct fcp_txrdy) * hw->config.n_io;
518	dma->virt = dma_alloc_coherent(&efct->pci->dev,	518	dma->virt = dma_alloc_coherent(&efct->pci->dev,
519	dma->size, &dma->phys, GFP_DMA);	519	dma->size, &dma->phys, GFP_KERNEL);
520	if (!dma->virt)	520	if (!dma->virt)
521	return -ENOMEM;	521	return -ENOMEM;
522	}	522	}
@@ -562,7 +562,7 @@ efct_hw_setup_io(struct efct_hw *hw) · 39 unmodified lines
562	sizeof(struct sli4_sge);	562	sizeof(struct sli4_sge);
563	dma->virt = dma_alloc_coherent(&efct->pci->dev,	563	dma->virt = dma_alloc_coherent(&efct->pci->dev,
564	dma->size, &dma->phys,	564	dma->size, &dma->phys,
565	GFP_DMA);	565	GFP_KERNEL);
566	if (!dma->virt) {	566	if (!dma->virt) {
567	efc_log_err(hw->os, "dma_alloc fail %d\n", i);	567	efc_log_err(hw->os, "dma_alloc fail %d\n", i);
568	memset(&io->def_sgl, 0,	568	memset(&io->def_sgl, 0,
@@ -618,7 +618,7 @@ efct_hw_init_prereg_io(struct efct_hw *hw) · 49 unmodified lines
618	memset(&req, 0, sizeof(struct efc_dma));	618	memset(&req, 0, sizeof(struct efc_dma));
619	req.size = 32 + sgls_per_request * 16;	619	req.size = 32 + sgls_per_request * 16;
620	req.virt = dma_alloc_coherent(&efct->pci->dev, req.size, &req.phys,	620	req.virt = dma_alloc_coherent(&efct->pci->dev, req.size, &req.phys,
621	GFP_DMA);	621	GFP_KERNEL);
622	if (!req.virt) {	622	if (!req.virt) {
623	kfree(sgls);	623	kfree(sgls);
624	return -ENOMEM;	624	return -ENOMEM;
@@ -1063,7 +1063,7 @@ efct_hw_init(struct efct_hw *hw) · 438 unmodified lines
1063	dma = &hw->loop_map;	1063	dma = &hw->loop_map;
1064	dma->size = SLI4_MIN_LOOP_MAP_BYTES;	1064	dma->size = SLI4_MIN_LOOP_MAP_BYTES;
1065	dma->virt = dma_alloc_coherent(&hw->os->pci->dev, dma->size, &dma->phys,	1065	dma->virt = dma_alloc_coherent(&hw->os->pci->dev, dma->size, &dma->phys,
1066	GFP_DMA);	1066	GFP_KERNEL);
1067	if (!dma->virt)	1067	if (!dma->virt)
1068	return -EIO;	1068	return -EIO;
1069		1069
@@ -1192,7 +1192,7 @@ efct_hw_rx_buffer_alloc(struct efct_hw *hw, u32 rqindex, u32 count, · 122 unmodified lines
1192	prq->dma.virt = dma_alloc_coherent(&efct->pci->dev,	1192	prq->dma.virt = dma_alloc_coherent(&efct->pci->dev,
1193	prq->dma.size,	1193	prq->dma.size,
1194	&prq->dma.phys,	1194	&prq->dma.phys,
1195	GFP_DMA);	1195	GFP_KERNEL);
1196	if (!prq->dma.virt) {	1196	if (!prq->dma.virt) {
1197	efc_log_err(hw->os, "DMA allocation failed\n");	1197	efc_log_err(hw->os, "DMA allocation failed\n");
1198	kfree(rq_buf);	1198	kfree(rq_buf);

drivers/scsi/elx/efct/efct_io.c+1−1

@@ -48,7 +48,7 @@ efct_io_pool_create(struct efct *efct, u32 num_sgl) · 47 unmodified lines
48	io->rspbuf.size = SCSI_RSP_BUF_LENGTH;	48	io->rspbuf.size = SCSI_RSP_BUF_LENGTH;
49	io->rspbuf.virt = dma_alloc_coherent(&efct->pci->dev,	49	io->rspbuf.virt = dma_alloc_coherent(&efct->pci->dev,
50	io->rspbuf.size,	50	io->rspbuf.size,
51	&io->rspbuf.phys, GFP_DMA);	51	&io->rspbuf.phys, GFP_KERNEL);
52	if (!io->rspbuf.virt) {	52	if (!io->rspbuf.virt) {
53	efc_log_err(efct, "dma_alloc rspbuf failed\n");	53	efc_log_err(efct, "dma_alloc rspbuf failed\n");
54	efct_io_pool_free(io_pool);	54	efct_io_pool_free(io_pool);

drivers/scsi/elx/libefc/efc_cmds.c+2−2

@@ -179,7 +179,7 @@ efc_nport_alloc_read_sparm64(struct efc efc, struct efc_nport nport) · 178 unmodified lines
179	nport->dma.size = EFC_SPARAM_DMA_SZ;	179	nport->dma.size = EFC_SPARAM_DMA_SZ;
180	nport->dma.virt = dma_alloc_coherent(&efc->pci->dev,	180	nport->dma.virt = dma_alloc_coherent(&efc->pci->dev,
181	nport->dma.size, &nport->dma.phys,	181	nport->dma.size, &nport->dma.phys,
182	GFP_DMA);	182	GFP_KERNEL);
183	if (!nport->dma.virt) {	183	if (!nport->dma.virt) {
184	efc_log_err(efc, "Failed to allocate DMA memory\n");	184	efc_log_err(efc, "Failed to allocate DMA memory\n");
185	efc_nport_free_resources(nport, EFC_EVT_NPORT_ALLOC_FAIL, data);	185	efc_nport_free_resources(nport, EFC_EVT_NPORT_ALLOC_FAIL, data);
@@ -466,7 +466,7 @@ efc_cmd_domain_alloc(struct efc efc, struct efc_domain domain, u32 fcf) · 280 unmodified lines
466	domain->dma.size = EFC_SPARAM_DMA_SZ;	466	domain->dma.size = EFC_SPARAM_DMA_SZ;
467	domain->dma.virt = dma_alloc_coherent(&efc->pci->dev,	467	domain->dma.virt = dma_alloc_coherent(&efc->pci->dev,
468	domain->dma.size,	468	domain->dma.size,
469	&domain->dma.phys, GFP_DMA);	469	&domain->dma.phys, GFP_KERNEL);
470	if (!domain->dma.virt) {	470	if (!domain->dma.virt) {
471	efc_log_err(efc, "Failed to allocate DMA memory\n");	471	efc_log_err(efc, "Failed to allocate DMA memory\n");
472	return -EIO;	472	return -EIO;

drivers/scsi/elx/libefc/efc_els.c+2−2

@@ -71,7 +71,7 @@ efc_els_io_alloc_size(struct efc_node *node, u32 reqlen, u32 rsplen) · 70 unmodified lines
71	/* now allocate DMA for request and response */	71	/* now allocate DMA for request and response */
72	els->io.req.size = reqlen;	72	els->io.req.size = reqlen;
73	els->io.req.virt = dma_alloc_coherent(&efc->pci->dev, els->io.req.size,	73	els->io.req.virt = dma_alloc_coherent(&efc->pci->dev, els->io.req.size,
74	&els->io.req.phys, GFP_DMA);	74	&els->io.req.phys, GFP_KERNEL);
75	if (!els->io.req.virt) {	75	if (!els->io.req.virt) {
76	mempool_free(els, efc->els_io_pool);	76	mempool_free(els, efc->els_io_pool);
77	spin_unlock_irqrestore(&node->els_ios_lock, flags);	77	spin_unlock_irqrestore(&node->els_ios_lock, flags);
@@ -80,7 +80,7 @@ efc_els_io_alloc_size(struct efc_node *node, u32 reqlen, u32 rsplen) · 2 unmodified lines
80		80
81	els->io.rsp.size = rsplen;	81	els->io.rsp.size = rsplen;
82	els->io.rsp.virt = dma_alloc_coherent(&efc->pci->dev, els->io.rsp.size,	82	els->io.rsp.virt = dma_alloc_coherent(&efc->pci->dev, els->io.rsp.size,
83	&els->io.rsp.phys, GFP_DMA);	83	&els->io.rsp.phys, GFP_KERNEL);
84	if (!els->io.rsp.virt) {	84	if (!els->io.rsp.virt) {
85	dma_free_coherent(&efc->pci->dev, els->io.req.size,	85	dma_free_coherent(&efc->pci->dev, els->io.req.size,
86	els->io.req.virt, els->io.req.phys);	86	els->io.req.virt, els->io.req.phys);

drivers/scsi/elx/libefc_sli/sli4.c+7−7

@@ -445,7 +445,7 @@ sli_cmd_rq_create_v2(struct sli4 *sli4, u32 num_rqs, · 444 unmodified lines
445		445
446	dma->size = payload_size;	446	dma->size = payload_size;
447	dma->virt = dma_alloc_coherent(&sli4->pci->dev, dma->size,	447	dma->virt = dma_alloc_coherent(&sli4->pci->dev, dma->size,
448	&dma->phys, GFP_DMA);	448	&dma->phys, GFP_KERNEL);
449	if (!dma->virt)	449	if (!dma->virt)
450	return -EIO;	450	return -EIO;
451		451
@@ -508,7 +508,7 @@ __sli_queue_init(struct sli4 sli4, struct sli4_queue q, u32 qtype, · 56 unmodified lines
508		508
509	q->dma.size = size * n_entries;	509	q->dma.size = size * n_entries;
510	q->dma.virt = dma_alloc_coherent(&sli4->pci->dev, q->dma.size,	510	q->dma.virt = dma_alloc_coherent(&sli4->pci->dev, q->dma.size,
511	&q->dma.phys, GFP_DMA);	511	&q->dma.phys, GFP_KERNEL);
512	if (!q->dma.virt) {	512	if (!q->dma.virt) {
513	memset(&q->dma, 0, sizeof(struct efc_dma));	513	memset(&q->dma, 0, sizeof(struct efc_dma));
514	efc_log_err(sli4, "%s allocation failed\n", SLI4_QNAME[qtype]);	514	efc_log_err(sli4, "%s allocation failed\n", SLI4_QNAME[qtype]);
@@ -849,7 +849,7 @@ static int sli_cmd_cq_set_create(struct sli4 *sli4, · 334 unmodified lines
849		849
850	dma->size = payload_size;	850	dma->size = payload_size;
851	dma->virt = dma_alloc_coherent(&sli4->pci->dev, dma->size,	851	dma->virt = dma_alloc_coherent(&sli4->pci->dev, dma->size,
852	&dma->phys, GFP_DMA);	852	&dma->phys, GFP_KERNEL);
853	if (!dma->virt)	853	if (!dma->virt)
854	return -EIO;	854	return -EIO;
855		855
@@ -4413,7 +4413,7 @@ sli_get_ctrl_attributes(struct sli4 *sli4) · 3557 unmodified lines
4413	psize = sizeof(struct sli4_rsp_cmn_get_cntl_addl_attributes);	4413	psize = sizeof(struct sli4_rsp_cmn_get_cntl_addl_attributes);
4414	data.size = psize;	4414	data.size = psize;
4415	data.virt = dma_alloc_coherent(&sli4->pci->dev, data.size,	4415	data.virt = dma_alloc_coherent(&sli4->pci->dev, data.size,
4416	&data.phys, GFP_DMA);	4416	&data.phys, GFP_KERNEL);
4417	if (!data.virt) {	4417	if (!data.virt) {
4418	memset(&data, 0, sizeof(struct efc_dma));	4418	memset(&data, 0, sizeof(struct efc_dma));
4419	efc_log_err(sli4, "Failed to allocate memory for GET_CNTL_ADDL_ATTR\n");	4419	efc_log_err(sli4, "Failed to allocate memory for GET_CNTL_ADDL_ATTR\n");
@@ -4653,7 +4653,7 @@ sli_setup(struct sli4 sli4, void os, struct pci_dev *pdev, · 233 unmodified lines
4653	*/	4653	*/
4654	sli4->bmbx.size = SLI4_BMBX_SIZE + sizeof(struct sli4_mcqe);	4654	sli4->bmbx.size = SLI4_BMBX_SIZE + sizeof(struct sli4_mcqe);
4655	sli4->bmbx.virt = dma_alloc_coherent(&pdev->dev, sli4->bmbx.size,	4655	sli4->bmbx.virt = dma_alloc_coherent(&pdev->dev, sli4->bmbx.size,
4656	&sli4->bmbx.phys, GFP_DMA);	4656	&sli4->bmbx.phys, GFP_KERNEL);
4657	if (!sli4->bmbx.virt) {	4657	if (!sli4->bmbx.virt) {
4658	memset(&sli4->bmbx, 0, sizeof(struct efc_dma));	4658	memset(&sli4->bmbx, 0, sizeof(struct efc_dma));
4659	efc_log_err(sli4, "bootstrap mailbox allocation failed\n");	4659	efc_log_err(sli4, "bootstrap mailbox allocation failed\n");
@@ -4674,7 +4674,7 @@ sli_setup(struct sli4 sli4, void os, struct pci_dev *pdev, · 14 unmodified lines
4674	sli4->vpd_data.virt = dma_alloc_coherent(&pdev->dev,	4674	sli4->vpd_data.virt = dma_alloc_coherent(&pdev->dev,
4675	sli4->vpd_data.size,	4675	sli4->vpd_data.size,
4676	&sli4->vpd_data.phys,	4676	&sli4->vpd_data.phys,
4677	GFP_DMA);	4677	GFP_KERNEL);
4678	if (!sli4->vpd_data.virt) {	4678	if (!sli4->vpd_data.virt) {
4679	memset(&sli4->vpd_data, 0, sizeof(struct efc_dma));	4679	memset(&sli4->vpd_data, 0, sizeof(struct efc_dma));
4680	/* Note that failure isn't fatal in this specific case */	4680	/* Note that failure isn't fatal in this specific case */
@@ -5070,7 +5070,7 @@ sli_cmd_post_hdr_templates(struct sli4 sli4, void buf, struct efc_dma *dma, · 389 unmodified lines
5070	payload_dma->size = payload_size;	5070	payload_dma->size = payload_size;
5071	payload_dma->virt = dma_alloc_coherent(&sli4->pci->dev,	5071	payload_dma->virt = dma_alloc_coherent(&sli4->pci->dev,
5072	payload_dma->size,	5072	payload_dma->size,
5073	&payload_dma->phys, GFP_DMA);	5073	&payload_dma->phys, GFP_KERNEL);
5074	if (!payload_dma->virt) {	5074	if (!payload_dma->virt) {
5075	memset(payload_dma, 0, sizeof(struct efc_dma));	5075	memset(payload_dma, 0, sizeof(struct efc_dma));
5076	efc_log_err(sli4, "mbox payload memory allocation fail\n");	5076	efc_log_err(sli4, "mbox payload memory allocation fail\n");

drivers/scsi/hisi_sas/hisi_sas.h+6−1

 #define _HISI_SAS_H_
 #include <linux/acpi.h>
-#include <linux/async.h>
 #include <linux/blk-mq.h>
 #include <linux/blk-mq-pci.h>
 #include <linux/clk.h>
 	bool done;
 };
+struct hisi_sas_internal_abort {
+	unsigned int flag;
+	unsigned int tag;
+};
 #define HISI_SAS_RST_WORK_INIT(r, c) \
 	{	.hisi_hba = hisi_hba, \
 		.completion = &c, \
 enum hisi_sas_phy_event {
 	HISI_PHYE_PHY_UP   = 0U,
 	HISI_PHYE_LINK_RESET,
+	HISI_PHYE_PHY_UP_PM,
 	HISI_PHYES_NUM,
 };

drivers/scsi/hisi_sas/hisi_sas_main.c+190−206

@@ -158,7 +158,7 @@ static void hisi_sas_slot_index_clear(struct hisi_hba *hisi_hba, int slot_idx) · 157 unmodified lines
158	{	158	{
159	void *bitmap = hisi_hba->slot_index_tags;	159	void *bitmap = hisi_hba->slot_index_tags;
160		160
161	clear_bit(slot_idx, bitmap);	161	__clear_bit(slot_idx, bitmap);
162	}	162	}
163		163
164	static void hisi_sas_slot_index_free(struct hisi_hba *hisi_hba, int slot_idx)	164	static void hisi_sas_slot_index_free(struct hisi_hba *hisi_hba, int slot_idx)
@@ -175,7 +175,7 @@ static void hisi_sas_slot_index_set(struct hisi_hba *hisi_hba, int slot_idx) · 10 unmodified lines
175	{	175	{
176	void *bitmap = hisi_hba->slot_index_tags;	176	void *bitmap = hisi_hba->slot_index_tags;
177		177
178	set_bit(slot_idx, bitmap);	178	__set_bit(slot_idx, bitmap);
179	}	179	}
180		180
181	static int hisi_sas_slot_index_alloc(struct hisi_hba *hisi_hba,	181	static int hisi_sas_slot_index_alloc(struct hisi_hba *hisi_hba,
@@ -206,14 +206,6 @@ static int hisi_sas_slot_index_alloc(struct hisi_hba *hisi_hba, · 24 unmodified lines
206	return index;	206	return index;
207	}	207	}
208		208
209	static void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba)
210	{
211	int i;
212
213	for (i = 0; i < hisi_hba->slot_index_count; ++i)
214	hisi_sas_slot_index_clear(hisi_hba, i);
215	}
216
217	void hisi_sas_slot_task_free(struct hisi_hba hisi_hba, struct sas_task task,	209	void hisi_sas_slot_task_free(struct hisi_hba hisi_hba, struct sas_task task,
218	struct hisi_sas_slot *slot)	210	struct hisi_sas_slot *slot)
219	{	211	{
@@ -273,11 +265,11 @@ static void hisi_sas_task_prep_ata(struct hisi_hba *hisi_hba, · 53 unmodified lines
273	}	265	}
274		266
275	static void hisi_sas_task_prep_abort(struct hisi_hba *hisi_hba,	267	static void hisi_sas_task_prep_abort(struct hisi_hba *hisi_hba,
276	struct hisi_sas_slot *slot,	268	struct hisi_sas_internal_abort *abort,
277	int device_id, int abort_flag, int tag_to_abort)	269	struct hisi_sas_slot *slot, int device_id)
278	{	270	{
279	hisi_hba->hw->prep_abort(hisi_hba, slot,	271	hisi_hba->hw->prep_abort(hisi_hba, slot,
280	device_id, abort_flag, tag_to_abort);	272	device_id, abort->flag, abort->tag);
281	}	273	}
282		274
283	static void hisi_sas_dma_unmap(struct hisi_hba *hisi_hba,	275	static void hisi_sas_dma_unmap(struct hisi_hba *hisi_hba,
@@ -403,95 +395,20 @@ err_out_dif_dma_unmap: · 119 unmodified lines
403	return rc;	395	return rc;
404	}	396	}
405		397
406	static int hisi_sas_task_prep(struct sas_task *task,	398	static
407	struct hisi_sas_dq **dq_pointer,	399	void hisi_sas_task_deliver(struct hisi_hba *hisi_hba,
408	bool is_tmf, struct hisi_sas_tmf_task *tmf,	400	struct hisi_sas_slot *slot,
409	int *pass)	401	struct hisi_sas_dq *dq,
		402	struct hisi_sas_device *sas_dev,
		403	struct hisi_sas_internal_abort *abort,
		404	struct hisi_sas_tmf_task *tmf)
410	{	405	{
411	struct domain_device *device = task->dev;	406	struct hisi_sas_cmd_hdr *cmd_hdr_base;
412	struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);	407	int dlvry_queue_slot, dlvry_queue;
413	struct hisi_sas_device *sas_dev = device->lldd_dev;	408	struct sas_task *task = slot->task;
414	struct hisi_sas_port *port;
415	struct hisi_sas_slot *slot;
416	struct hisi_sas_cmd_hdr *cmd_hdr_base;
417	struct asd_sas_port *sas_port = device->port;
418	struct device *dev = hisi_hba->dev;
419	int dlvry_queue_slot, dlvry_queue, rc, slot_idx;
420	int n_elem = 0, n_elem_dif = 0, n_elem_req = 0;
421	struct scsi_cmnd *scmd = NULL;
422	struct hisi_sas_dq *dq;
423	unsigned long flags;	409	unsigned long flags;
424	int wr_q_index;	410	int wr_q_index;
425		411
426	if (DEV_IS_GONE(sas_dev)) {
427	if (sas_dev)
428	dev_info(dev, "task prep: device %d not ready\n",
429	sas_dev->device_id);
430	else
431	dev_info(dev, "task prep: device %016llx not ready\n",
432	SAS_ADDR(device->sas_addr));
433
434	return -ECOMM;
435	}
436
437	if (task->uldd_task) {
438	struct ata_queued_cmd *qc;
439
440	if (dev_is_sata(device)) {
441	qc = task->uldd_task;
442	scmd = qc->scsicmd;
443	} else {
444	scmd = task->uldd_task;
445	}
446	}
447
448	if (scmd) {
449	unsigned int dq_index;
450	u32 blk_tag;
451
452	blk_tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd));
453	dq_index = blk_mq_unique_tag_to_hwq(blk_tag);
454	*dq_pointer = dq = &hisi_hba->dq[dq_index];
455	} else {
456	struct Scsi_Host *shost = hisi_hba->shost;
457	struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
458	int queue = qmap->mq_map[raw_smp_processor_id()];
459
460	*dq_pointer = dq = &hisi_hba->dq[queue];
461	}
462
463	port = to_hisi_sas_port(sas_port);
464	if (port && !port->port_attached) {
465	dev_info(dev, "task prep: %s port%d not attach device\n",
466	(dev_is_sata(device)) ?
467	"SATA/STP" : "SAS",
468	device->port->id);
469
470	return -ECOMM;
471	}
472
473	rc = hisi_sas_dma_map(hisi_hba, task, &n_elem,
474	&n_elem_req);
475	if (rc < 0)
476	goto prep_out;
477
478	if (!sas_protocol_ata(task->task_proto)) {
479	rc = hisi_sas_dif_dma_map(hisi_hba, &n_elem_dif, task);
480	if (rc < 0)
481	goto err_out_dma_unmap;
482	}
483
484	if (hisi_hba->hw->slot_index_alloc)
485	rc = hisi_hba->hw->slot_index_alloc(hisi_hba, device);
486	else
487	rc = hisi_sas_slot_index_alloc(hisi_hba, scmd);
488
489	if (rc < 0)
490	goto err_out_dif_dma_unmap;
491
492	slot_idx = rc;
493	slot = &hisi_hba->slot_info[slot_idx];
494
495	spin_lock(&dq->lock);	412	spin_lock(&dq->lock);
496	wr_q_index = dq->wr_point;	413	wr_q_index = dq->wr_point;
497	dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;	414	dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
@@ -505,16 +422,13 @@ static int hisi_sas_task_prep(struct sas_task *task, · 7 unmodified lines
505	dlvry_queue_slot = wr_q_index;	422	dlvry_queue_slot = wr_q_index;
506		423
507	slot->device_id = sas_dev->device_id;	424	slot->device_id = sas_dev->device_id;
508	slot->n_elem = n_elem;
509	slot->n_elem_dif = n_elem_dif;
510	slot->dlvry_queue = dlvry_queue;	425	slot->dlvry_queue = dlvry_queue;
511	slot->dlvry_queue_slot = dlvry_queue_slot;	426	slot->dlvry_queue_slot = dlvry_queue_slot;
512	cmd_hdr_base = hisi_hba->cmd_hdr[dlvry_queue];	427	cmd_hdr_base = hisi_hba->cmd_hdr[dlvry_queue];
513	slot->cmd_hdr = &cmd_hdr_base[dlvry_queue_slot];	428	slot->cmd_hdr = &cmd_hdr_base[dlvry_queue_slot];
514	slot->task = task;	429
515	slot->port = port;
516	slot->tmf = tmf;	430	slot->tmf = tmf;
517	slot->is_internal = is_tmf;	431	slot->is_internal = tmf;
518	task->lldd_task = slot;	432	task->lldd_task = slot;
519		433
520	memset(slot->cmd_hdr, 0, sizeof(struct hisi_sas_cmd_hdr));	434	memset(slot->cmd_hdr, 0, sizeof(struct hisi_sas_cmd_hdr));
@@ -534,8 +448,14 @@ static int hisi_sas_task_prep(struct sas_task *task, · 13 unmodified lines
534	case SAS_PROTOCOL_SATA \| SAS_PROTOCOL_STP:	448	case SAS_PROTOCOL_SATA \| SAS_PROTOCOL_STP:
535	hisi_sas_task_prep_ata(hisi_hba, slot);	449	hisi_sas_task_prep_ata(hisi_hba, slot);
536	break;	450	break;
		451	case SAS_PROTOCOL_NONE:
		452	if (abort) {
		453	hisi_sas_task_prep_abort(hisi_hba, abort, slot, sas_dev->device_id);
		454	break;
		455	}
		456	fallthrough;
537	default:	457	default:
538	dev_err(dev, "task prep: unknown/unsupported proto (0x%x)\n",	458	dev_err(hisi_hba->dev, "task prep: unknown/unsupported proto (0x%x)\n",
539	task->task_proto);	459	task->task_proto);
540	break;	460	break;
541	}	461	}
@@ -544,32 +464,27 @@ static int hisi_sas_task_prep(struct sas_task *task, · 2 unmodified lines
544	task->task_state_flags \|= SAS_TASK_AT_INITIATOR;	464	task->task_state_flags \|= SAS_TASK_AT_INITIATOR;
545	spin_unlock_irqrestore(&task->task_state_lock, flags);	465	spin_unlock_irqrestore(&task->task_state_lock, flags);
546		466
547	++(*pass);
548	WRITE_ONCE(slot->ready, 1);	467	WRITE_ONCE(slot->ready, 1);
549		468
550	return 0;	469	spin_lock(&dq->lock);
551		470	hisi_hba->hw->start_delivery(dq);
552	err_out_dif_dma_unmap:	471	spin_unlock(&dq->lock);
553	if (!sas_protocol_ata(task->task_proto))
554	hisi_sas_dif_dma_unmap(hisi_hba, task, n_elem_dif);
555	err_out_dma_unmap:
556	hisi_sas_dma_unmap(hisi_hba, task, n_elem,
557	n_elem_req);
558	prep_out:
559	dev_err(dev, "task prep: failed[%d]!\n", rc);
560	return rc;
561	}	472	}
562		473
563	static int hisi_sas_task_exec(struct sas_task *task, gfp_t gfp_flags,	474	static int hisi_sas_task_exec(struct sas_task *task, gfp_t gfp_flags,
564	bool is_tmf, struct hisi_sas_tmf_task *tmf)	475	struct hisi_sas_tmf_task *tmf)
565	{	476	{
566	u32 rc;	477	int n_elem = 0, n_elem_dif = 0, n_elem_req = 0;
567	u32 pass = 0;
568	struct hisi_hba *hisi_hba;
569	struct device *dev;
570	struct domain_device *device = task->dev;	478	struct domain_device *device = task->dev;
571	struct asd_sas_port *sas_port = device->port;	479	struct asd_sas_port *sas_port = device->port;
		480	struct hisi_sas_device *sas_dev = device->lldd_dev;
		481	struct scsi_cmnd *scmd = NULL;
572	struct hisi_sas_dq *dq = NULL;	482	struct hisi_sas_dq *dq = NULL;
		483	struct hisi_sas_port *port;
		484	struct hisi_hba *hisi_hba;
		485	struct hisi_sas_slot *slot;
		486	struct device *dev;
		487	int rc;
573		488
574	if (!sas_port) {	489	if (!sas_port) {
575	struct task_status_struct *ts = &task->task_status;	490	struct task_status_struct *ts = &task->task_status;
@@ -596,17 +511,94 @@ static int hisi_sas_task_exec(struct sas_task *task, gfp_t gfp_flags, · 20 unmodified lines
596	up(&hisi_hba->sem);	511	up(&hisi_hba->sem);
597	}	512	}
598		513
599	/* protect task_prep and start_delivery sequence */	514	if (DEV_IS_GONE(sas_dev)) {
600	rc = hisi_sas_task_prep(task, &dq, is_tmf, tmf, &pass);	515	if (sas_dev)
601	if (rc)	516	dev_info(dev, "task prep: device %d not ready\n",
602	dev_err(dev, "task exec: failed[%d]!\n", rc);	517	sas_dev->device_id);
		518	else
		519	dev_info(dev, "task prep: device %016llx not ready\n",
		520	SAS_ADDR(device->sas_addr));
		521
		522	return -ECOMM;
		523	}
		524
		525	if (task->uldd_task) {
		526	struct ata_queued_cmd *qc;
		527
		528	if (dev_is_sata(device)) {
		529	qc = task->uldd_task;
		530	scmd = qc->scsicmd;
		531	} else {
		532	scmd = task->uldd_task;
		533	}
		534	}
603		535
604	if (likely(pass)) {	536	if (scmd) {
605	spin_lock(&dq->lock);	537	unsigned int dq_index;
606	hisi_hba->hw->start_delivery(dq);	538	u32 blk_tag;
607	spin_unlock(&dq->lock);	539
		540	blk_tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd));
		541	dq_index = blk_mq_unique_tag_to_hwq(blk_tag);
		542	dq = &hisi_hba->dq[dq_index];
		543	} else {
		544	struct Scsi_Host *shost = hisi_hba->shost;
		545	struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
		546	int queue = qmap->mq_map[raw_smp_processor_id()];
		547
		548	dq = &hisi_hba->dq[queue];
		549	}
		550
		551	port = to_hisi_sas_port(sas_port);
		552	if (port && !port->port_attached) {
		553	dev_info(dev, "task prep: %s port%d not attach device\n",
		554	(dev_is_sata(device)) ?
		555	"SATA/STP" : "SAS",
		556	device->port->id);
		557
		558	return -ECOMM;
608	}	559	}
609		560
		561	rc = hisi_sas_dma_map(hisi_hba, task, &n_elem,
		562	&n_elem_req);
		563	if (rc < 0)
		564	goto prep_out;
		565
		566	if (!sas_protocol_ata(task->task_proto)) {
		567	rc = hisi_sas_dif_dma_map(hisi_hba, &n_elem_dif, task);
		568	if (rc < 0)
		569	goto err_out_dma_unmap;
		570	}
		571
		572	if (hisi_hba->hw->slot_index_alloc)
		573	rc = hisi_hba->hw->slot_index_alloc(hisi_hba, device);
		574	else
		575	rc = hisi_sas_slot_index_alloc(hisi_hba, scmd);
		576
		577	if (rc < 0)
		578	goto err_out_dif_dma_unmap;
		579
		580	slot = &hisi_hba->slot_info[rc];
		581	slot->n_elem = n_elem;
		582	slot->n_elem_dif = n_elem_dif;
		583	slot->task = task;
		584	slot->port = port;
		585
		586	slot->tmf = tmf;
		587	slot->is_internal = tmf;
		588
		589	/* protect task_prep and start_delivery sequence */
		590	hisi_sas_task_deliver(hisi_hba, slot, dq, sas_dev, NULL, tmf);
		591
		592	return 0;
		593
		594	err_out_dif_dma_unmap:
		595	if (!sas_protocol_ata(task->task_proto))
		596	hisi_sas_dif_dma_unmap(hisi_hba, task, n_elem_dif);
		597	err_out_dma_unmap:
		598	hisi_sas_dma_unmap(hisi_hba, task, n_elem,
		599	n_elem_req);
		600	prep_out:
		601	dev_err(dev, "task exec: failed[%d]!\n", rc);
610	return rc;	602	return rc;
611	}	603	}
612		604
@@ -619,12 +611,6 @@ static void hisi_sas_bytes_dmaed(struct hisi_hba *hisi_hba, int phy_no, · 6 unmodified lines
619	if (!phy->phy_attached)	611	if (!phy->phy_attached)
620	return;	612	return;
621		613
622	if (test_bit(HISI_SAS_PM_BIT, &hisi_hba->flags) &&
623	!sas_phy->suspended) {
624	dev_warn(hisi_hba->dev, "phy%d during suspend filtered out\n", phy_no);
625	return;
626	}
627
628	sas_notify_phy_event(sas_phy, PHYE_OOB_DONE, gfp_flags);	614	sas_notify_phy_event(sas_phy, PHYE_OOB_DONE, gfp_flags);
629		615
630	if (sas_phy->phy) {	616	if (sas_phy->phy) {
@@ -860,10 +846,11 @@ int hisi_sas_scan_finished(struct Scsi_Host *shost, unsigned long time) · 229 unmodified lines
860	}	846	}
861	EXPORT_SYMBOL_GPL(hisi_sas_scan_finished);	847	EXPORT_SYMBOL_GPL(hisi_sas_scan_finished);
862		848
863	static void hisi_sas_phyup_work(struct work_struct *work)	849	static void hisi_sas_phyup_work_common(struct work_struct *work,
		850	enum hisi_sas_phy_event event)
864	{	851	{
865	struct hisi_sas_phy *phy =	852	struct hisi_sas_phy *phy =
866	container_of(work, typeof(*phy), works[HISI_PHYE_PHY_UP]);	853	container_of(work, typeof(*phy), works[event]);
867	struct hisi_hba *hisi_hba = phy->hisi_hba;	854	struct hisi_hba *hisi_hba = phy->hisi_hba;
868	struct asd_sas_phy *sas_phy = &phy->sas_phy;	855	struct asd_sas_phy *sas_phy = &phy->sas_phy;
869	int phy_no = sas_phy->id;	856	int phy_no = sas_phy->id;
@@ -874,6 +861,11 @@ static void hisi_sas_phyup_work(struct work_struct *work) · 4 unmodified lines
874	hisi_sas_bytes_dmaed(hisi_hba, phy_no, GFP_KERNEL);	861	hisi_sas_bytes_dmaed(hisi_hba, phy_no, GFP_KERNEL);
875	}	862	}
876		863
		864	static void hisi_sas_phyup_work(struct work_struct *work)
		865	{
		866	hisi_sas_phyup_work_common(work, HISI_PHYE_PHY_UP);
		867	}
		868
877	static void hisi_sas_linkreset_work(struct work_struct *work)	869	static void hisi_sas_linkreset_work(struct work_struct *work)
878	{	870	{
879	struct hisi_sas_phy *phy =	871	struct hisi_sas_phy *phy =
@@ -883,9 +875,21 @@ static void hisi_sas_linkreset_work(struct work_struct *work) · 3 unmodified lines
883	hisi_sas_control_phy(sas_phy, PHY_FUNC_LINK_RESET, NULL);	875	hisi_sas_control_phy(sas_phy, PHY_FUNC_LINK_RESET, NULL);
884	}	876	}
885		877
		878	static void hisi_sas_phyup_pm_work(struct work_struct *work)
		879	{
		880	struct hisi_sas_phy *phy =
		881	container_of(work, typeof(*phy), works[HISI_PHYE_PHY_UP_PM]);
		882	struct hisi_hba *hisi_hba = phy->hisi_hba;
		883	struct device *dev = hisi_hba->dev;
		884
		885	hisi_sas_phyup_work_common(work, HISI_PHYE_PHY_UP_PM);
		886	pm_runtime_put_sync(dev);
		887	}
		888
886	static const work_func_t hisi_sas_phye_fns[HISI_PHYES_NUM] = {	889	static const work_func_t hisi_sas_phye_fns[HISI_PHYES_NUM] = {
887	[HISI_PHYE_PHY_UP] = hisi_sas_phyup_work,	890	[HISI_PHYE_PHY_UP] = hisi_sas_phyup_work,
888	[HISI_PHYE_LINK_RESET] = hisi_sas_linkreset_work,	891	[HISI_PHYE_LINK_RESET] = hisi_sas_linkreset_work,
		892	[HISI_PHYE_PHY_UP_PM] = hisi_sas_phyup_pm_work,
889	};	893	};
890		894
891	bool hisi_sas_notify_phy_event(struct hisi_sas_phy *phy,	895	bool hisi_sas_notify_phy_event(struct hisi_sas_phy *phy,
@@ -917,10 +921,14 @@ void hisi_sas_phy_oob_ready(struct hisi_hba *hisi_hba, int phy_no) · 25 unmodified lines
917	{	921	{
918	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];	922	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
919	struct device *dev = hisi_hba->dev;	923	struct device *dev = hisi_hba->dev;
		924	unsigned long flags;
920		925
921	dev_dbg(dev, "phy%d OOB ready\n", phy_no);	926	dev_dbg(dev, "phy%d OOB ready\n", phy_no);
922	if (phy->phy_attached)	927	spin_lock_irqsave(&phy->lock, flags);
		928	if (phy->phy_attached) {
		929	spin_unlock_irqrestore(&phy->lock, flags);
923	return;	930	return;
		931	}
924		932
925	if (!timer_pending(&phy->timer)) {	933	if (!timer_pending(&phy->timer)) {
926	if (phy->wait_phyup_cnt < HISI_SAS_WAIT_PHYUP_RETRIES) {	934	if (phy->wait_phyup_cnt < HISI_SAS_WAIT_PHYUP_RETRIES) {
@@ -928,13 +936,17 @@ void hisi_sas_phy_oob_ready(struct hisi_hba *hisi_hba, int phy_no) · 1 unmodified line
928	phy->timer.expires = jiffies +	936	phy->timer.expires = jiffies +
929	HISI_SAS_WAIT_PHYUP_TIMEOUT;	937	HISI_SAS_WAIT_PHYUP_TIMEOUT;
930	add_timer(&phy->timer);	938	add_timer(&phy->timer);
931	} else {	939	spin_unlock_irqrestore(&phy->lock, flags);
932	dev_warn(dev, "phy%d failed to come up %d times, giving up\n",	940	return;
933	phy_no, phy->wait_phyup_cnt);
934	phy->wait_phyup_cnt = 0;
935	}	941	}
		942
		943	dev_warn(dev, "phy%d failed to come up %d times, giving up\n",
		944	phy_no, phy->wait_phyup_cnt);
		945	phy->wait_phyup_cnt = 0;
936	}	946	}
		947	spin_unlock_irqrestore(&phy->lock, flags);
937	}	948	}
		949
938	EXPORT_SYMBOL_GPL(hisi_sas_phy_oob_ready);	950	EXPORT_SYMBOL_GPL(hisi_sas_phy_oob_ready);
939		951
940	static void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int phy_no)	952	static void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int phy_no)
@@ -1105,7 +1117,7 @@ static void hisi_sas_dev_gone(struct domain_device *device) · 164 unmodified lines
1105		1117
1106	static int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags)	1118	static int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags)
1107	{	1119	{
1108	return hisi_sas_task_exec(task, gfp_flags, 0, NULL);	1120	return hisi_sas_task_exec(task, gfp_flags, NULL);
1109	}	1121	}
1110		1122
1111	static int hisi_sas_phy_set_linkrate(struct hisi_hba *hisi_hba, int phy_no,	1123	static int hisi_sas_phy_set_linkrate(struct hisi_hba *hisi_hba, int phy_no,
@@ -1156,6 +1168,7 @@ static int hisi_sas_control_phy(struct asd_sas_phy *sas_phy, enum phy_func func, · 44 unmodified lines
1156	u8 sts = phy->phy_attached;	1168	u8 sts = phy->phy_attached;
1157	int ret = 0;	1169	int ret = 0;
1158		1170
		1171	down(&hisi_hba->sem);
1159	phy->reset_completion = &completion;	1172	phy->reset_completion = &completion;
1160		1173
1161	switch (func) {	1174	switch (func) {
@@ -1199,6 +1212,7 @@ static int hisi_sas_control_phy(struct asd_sas_phy *sas_phy, enum phy_func func, · 37 unmodified lines
1199	out:	1212	out:
1200	phy->reset_completion = NULL;	1213	phy->reset_completion = NULL;
1201		1214
		1215	up(&hisi_hba->sem);
1202	return ret;	1216	return ret;
1203	}	1217	}
1204		1218
@@ -1259,8 +1273,7 @@ static int hisi_sas_exec_internal_tmf_task(struct domain_device *device, · 54 unmodified lines
1259	task->slow_task->timer.expires = jiffies + TASK_TIMEOUT;	1273	task->slow_task->timer.expires = jiffies + TASK_TIMEOUT;
1260	add_timer(&task->slow_task->timer);	1274	add_timer(&task->slow_task->timer);
1261		1275
1262	res = hisi_sas_task_exec(task, GFP_KERNEL, 1, tmf);	1276	res = hisi_sas_task_exec(task, GFP_KERNEL, tmf);
1263
1264	if (res) {	1277	if (res) {
1265	del_timer_sync(&task->slow_task->timer);	1278	del_timer_sync(&task->slow_task->timer);
1266	dev_err(dev, "abort tmf: executing internal task failed: %d\n",	1279	dev_err(dev, "abort tmf: executing internal task failed: %d\n",
@@ -1433,11 +1446,13 @@ static void hisi_sas_refresh_port_id(struct hisi_hba *hisi_hba) · 166 unmodified lines
1433	sas_port = device->port;	1446	sas_port = device->port;
1434	port = to_hisi_sas_port(sas_port);	1447	port = to_hisi_sas_port(sas_port);
1435		1448
		1449	spin_lock(&sas_port->phy_list_lock);
1436	list_for_each_entry(sas_phy, &sas_port->phy_list, port_phy_el)	1450	list_for_each_entry(sas_phy, &sas_port->phy_list, port_phy_el)
1437	if (state & BIT(sas_phy->id)) {	1451	if (state & BIT(sas_phy->id)) {
1438	phy = sas_phy->lldd_phy;	1452	phy = sas_phy->lldd_phy;
1439	break;	1453	break;
1440	}	1454	}
		1455	spin_unlock(&sas_port->phy_list_lock);
1441		1456
1442	if (phy) {	1457	if (phy) {
1443	port->id = phy->port_id;	1458	port->id = phy->port_id;
@@ -1514,22 +1529,25 @@ static void hisi_sas_send_ata_reset_each_phy(struct hisi_hba *hisi_hba, · 70 unmodified lines
1514	struct ata_link *link;	1529	struct ata_link *link;
1515	u8 fis[20] = {0};	1530	u8 fis[20] = {0};
1516	u32 state;	1531	u32 state;
		1532	int i;
1517		1533
1518	state = hisi_hba->hw->get_phys_state(hisi_hba);	1534	state = hisi_hba->hw->get_phys_state(hisi_hba);
1519	list_for_each_entry(sas_phy, &sas_port->phy_list, port_phy_el) {	1535	for (i = 0; i < hisi_hba->n_phy; i++) {
1520	if (!(state & BIT(sas_phy->id)))	1536	if (!(state & BIT(sas_phy->id)))
1521	continue;	1537	continue;
		1538	if (!(sas_port->phy_mask & BIT(i)))
		1539	continue;
1522		1540
1523	ata_for_each_link(link, ap, EDGE) {	1541	ata_for_each_link(link, ap, EDGE) {
1524	int pmp = sata_srst_pmp(link);	1542	int pmp = sata_srst_pmp(link);
1525		1543
1526	tmf_task.phy_id = sas_phy->id;	1544	tmf_task.phy_id = i;
1527	hisi_sas_fill_ata_reset_cmd(link->device, 1, pmp, fis);	1545	hisi_sas_fill_ata_reset_cmd(link->device, 1, pmp, fis);
1528	rc = hisi_sas_exec_internal_tmf_task(device, fis, s,	1546	rc = hisi_sas_exec_internal_tmf_task(device, fis, s,
1529	&tmf_task);	1547	&tmf_task);
1530	if (rc != TMF_RESP_FUNC_COMPLETE) {	1548	if (rc != TMF_RESP_FUNC_COMPLETE) {
1531	dev_err(dev, "phy%d ata reset failed rc=%d\n",	1549	dev_err(dev, "phy%d ata reset failed rc=%d\n",
1532	sas_phy->id, rc);	1550	i, rc);
1533	break;	1551	break;
1534	}	1552	}
1535	}	1553	}
@@ -1581,7 +1599,6 @@ void hisi_sas_controller_reset_prepare(struct hisi_hba *hisi_hba) · 45 unmodified lines
1581	{	1599	{
1582	struct Scsi_Host *shost = hisi_hba->shost;	1600	struct Scsi_Host *shost = hisi_hba->shost;
1583		1601
1584	down(&hisi_hba->sem);
1585	hisi_hba->phy_state = hisi_hba->hw->get_phys_state(hisi_hba);	1602	hisi_hba->phy_state = hisi_hba->hw->get_phys_state(hisi_hba);
1586		1603
1587	scsi_block_requests(shost);	1604	scsi_block_requests(shost);
@@ -1606,9 +1623,9 @@ void hisi_sas_controller_reset_done(struct hisi_hba *hisi_hba) · 18 unmodified lines
1606	if (hisi_hba->reject_stp_links_msk)	1623	if (hisi_hba->reject_stp_links_msk)
1607	hisi_sas_terminate_stp_reject(hisi_hba);	1624	hisi_sas_terminate_stp_reject(hisi_hba);
1608	hisi_sas_reset_init_all_devices(hisi_hba);	1625	hisi_sas_reset_init_all_devices(hisi_hba);
1609	up(&hisi_hba->sem);
1610	scsi_unblock_requests(shost);	1626	scsi_unblock_requests(shost);
1611	clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);	1627	clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
		1628	up(&hisi_hba->sem);
1612		1629
1613	hisi_sas_rescan_topology(hisi_hba, hisi_hba->phy_state);	1630	hisi_sas_rescan_topology(hisi_hba, hisi_hba->phy_state);
1614	}	1631	}
@@ -1619,8 +1636,11 @@ static int hisi_sas_controller_prereset(struct hisi_hba *hisi_hba) · 4 unmodified lines
1619	if (!hisi_hba->hw->soft_reset)	1636	if (!hisi_hba->hw->soft_reset)
1620	return -1;	1637	return -1;
1621		1638
1622	if (test_and_set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))	1639	down(&hisi_hba->sem);
		1640	if (test_and_set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags)) {
		1641	up(&hisi_hba->sem);
1623	return -1;	1642	return -1;
		1643	}
1624		1644
1625	if (hisi_sas_debugfs_enable && hisi_hba->debugfs_itct[0].itct)	1645	if (hisi_sas_debugfs_enable && hisi_hba->debugfs_itct[0].itct)
1626	hisi_hba->hw->debugfs_snapshot_regs(hisi_hba);	1646	hisi_hba->hw->debugfs_snapshot_regs(hisi_hba);
@@ -2021,19 +2041,17 @@ static int hisi_sas_query_task(struct sas_task *task) · 394 unmodified lines
2021		2041
2022	static int	2042	static int
2023	hisi_sas_internal_abort_task_exec(struct hisi_hba *hisi_hba, int device_id,	2043	hisi_sas_internal_abort_task_exec(struct hisi_hba *hisi_hba, int device_id,
2024	struct sas_task *task, int abort_flag,	2044	struct hisi_sas_internal_abort *abort,
2025	int task_tag, struct hisi_sas_dq *dq)	2045	struct sas_task *task,
		2046	struct hisi_sas_dq *dq)
2026	{	2047	{
2027	struct domain_device *device = task->dev;	2048	struct domain_device *device = task->dev;
2028	struct hisi_sas_device *sas_dev = device->lldd_dev;	2049	struct hisi_sas_device *sas_dev = device->lldd_dev;
2029	struct device *dev = hisi_hba->dev;	2050	struct device *dev = hisi_hba->dev;
2030	struct hisi_sas_port *port;	2051	struct hisi_sas_port *port;
2031	struct hisi_sas_slot *slot;
2032	struct asd_sas_port *sas_port = device->port;	2052	struct asd_sas_port *sas_port = device->port;
2033	struct hisi_sas_cmd_hdr *cmd_hdr_base;	2053	struct hisi_sas_slot *slot;
2034	int dlvry_queue_slot, dlvry_queue, n_elem = 0, rc, slot_idx;	2054	int slot_idx;
2035	unsigned long flags;
2036	int wr_q_index;
2037		2055
2038	if (unlikely(test_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags)))	2056	if (unlikely(test_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags)))
2039	return -EINVAL;	2057	return -EINVAL;
@@ -2044,59 +2062,24 @@ hisi_sas_internal_abort_task_exec(struct hisi_hba *hisi_hba, int device_id, · 4 unmodified lines
2044	port = to_hisi_sas_port(sas_port);	2062	port = to_hisi_sas_port(sas_port);
2045		2063
2046	/* simply get a slot and send abort command */	2064	/* simply get a slot and send abort command */
2047	rc = hisi_sas_slot_index_alloc(hisi_hba, NULL);	2065	slot_idx = hisi_sas_slot_index_alloc(hisi_hba, NULL);
2048	if (rc < 0)	2066	if (slot_idx < 0)
2049	goto err_out;	2067	goto err_out;
2050		2068
2051	slot_idx = rc;
2052	slot = &hisi_hba->slot_info[slot_idx];	2069	slot = &hisi_hba->slot_info[slot_idx];
2053		2070	slot->n_elem = 0;
2054	spin_lock(&dq->lock);
2055	wr_q_index = dq->wr_point;
2056	dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
2057	list_add_tail(&slot->delivery, &dq->list);
2058	spin_unlock(&dq->lock);
2059	spin_lock(&sas_dev->lock);
2060	list_add_tail(&slot->entry, &sas_dev->list);
2061	spin_unlock(&sas_dev->lock);
2062
2063	dlvry_queue = dq->id;
2064	dlvry_queue_slot = wr_q_index;
2065
2066	slot->device_id = sas_dev->device_id;
2067	slot->n_elem = n_elem;
2068	slot->dlvry_queue = dlvry_queue;
2069	slot->dlvry_queue_slot = dlvry_queue_slot;
2070	cmd_hdr_base = hisi_hba->cmd_hdr[dlvry_queue];
2071	slot->cmd_hdr = &cmd_hdr_base[dlvry_queue_slot];
2072	slot->task = task;	2071	slot->task = task;
2073	slot->port = port;	2072	slot->port = port;
2074	slot->is_internal = true;	2073	slot->is_internal = true;
2075	task->lldd_task = slot;
2076
2077	memset(slot->cmd_hdr, 0, sizeof(struct hisi_sas_cmd_hdr));
2078	memset(hisi_sas_cmd_hdr_addr_mem(slot), 0, HISI_SAS_COMMAND_TABLE_SZ);
2079	memset(hisi_sas_status_buf_addr_mem(slot), 0,
2080	sizeof(struct hisi_sas_err_record));
2081		2074
2082	hisi_sas_task_prep_abort(hisi_hba, slot, device_id,	2075	hisi_sas_task_deliver(hisi_hba, slot, dq, sas_dev, abort, NULL);
2083	abort_flag, task_tag);
2084
2085	spin_lock_irqsave(&task->task_state_lock, flags);
2086	task->task_state_flags \|= SAS_TASK_AT_INITIATOR;
2087	spin_unlock_irqrestore(&task->task_state_lock, flags);
2088	WRITE_ONCE(slot->ready, 1);
2089	/* send abort command to the chip */
2090	spin_lock(&dq->lock);
2091	hisi_hba->hw->start_delivery(dq);
2092	spin_unlock(&dq->lock);
2093		2076
2094	return 0;	2077	return 0;
2095		2078
2096	err_out:	2079	err_out:
2097	dev_err(dev, "internal abort task prep: failed[%d]!\n", rc);	2080	dev_err(dev, "internal abort task prep: failed[%d]!\n", slot_idx);
2098		2081
2099	return rc;	2082	return slot_idx;
2100	}	2083	}
2101		2084
2102	/**	2085	/**
@@ -2118,9 +2101,12 @@ _hisi_sas_internal_task_abort(struct hisi_hba *hisi_hba, · 15 unmodified lines
2118	{	2101	{
2119	struct sas_task *task;	2102	struct sas_task *task;
2120	struct hisi_sas_device *sas_dev = device->lldd_dev;	2103	struct hisi_sas_device *sas_dev = device->lldd_dev;
		2104	struct hisi_sas_internal_abort abort = {
		2105	.flag = abort_flag,
		2106	.tag = tag,
		2107	};
2121	struct device *dev = hisi_hba->dev;	2108	struct device *dev = hisi_hba->dev;
2122	int res;	2109	int res;
2123
2124	/*	2110	/*
2125	* The interface is not realized means this HW don't support internal	2111	* The interface is not realized means this HW don't support internal
2126	* abort, or don't need to do internal abort. Then here, we return	2112	* abort, or don't need to do internal abort. Then here, we return
@@ -2138,14 +2124,14 @@ _hisi_sas_internal_task_abort(struct hisi_hba *hisi_hba, · 11 unmodified lines
2138	return -ENOMEM;	2124	return -ENOMEM;
2139		2125
2140	task->dev = device;	2126	task->dev = device;
2141	task->task_proto = device->tproto;	2127	task->task_proto = SAS_PROTOCOL_NONE;
2142	task->task_done = hisi_sas_task_done;	2128	task->task_done = hisi_sas_task_done;
2143	task->slow_task->timer.function = hisi_sas_tmf_timedout;	2129	task->slow_task->timer.function = hisi_sas_tmf_timedout;
2144	task->slow_task->timer.expires = jiffies + INTERNAL_ABORT_TIMEOUT;	2130	task->slow_task->timer.expires = jiffies + INTERNAL_ABORT_TIMEOUT;
2145	add_timer(&task->slow_task->timer);	2131	add_timer(&task->slow_task->timer);
2146		2132
2147	res = hisi_sas_internal_abort_task_exec(hisi_hba, sas_dev->device_id,	2133	res = hisi_sas_internal_abort_task_exec(hisi_hba, sas_dev->device_id,
2148	task, abort_flag, tag, dq);	2134	&abort, task, dq);
2149	if (res) {	2135	if (res) {
2150	del_timer_sync(&task->slow_task->timer);	2136	del_timer_sync(&task->slow_task->timer);
2151	dev_err(dev, "internal task abort: executing internal task failed: %d\n",	2137	dev_err(dev, "internal task abort: executing internal task failed: %d\n",
@@ -2516,9 +2502,8 @@ int hisi_sas_alloc(struct hisi_hba *hisi_hba) · 364 unmodified lines
2516	if (!hisi_hba->breakpoint)	2502	if (!hisi_hba->breakpoint)
2517	goto err_out;	2503	goto err_out;
2518		2504
2519	hisi_hba->slot_index_count = max_command_entries;	2505	s = hisi_hba->slot_index_count = max_command_entries;
2520	s = hisi_hba->slot_index_count / BITS_PER_BYTE;	2506	hisi_hba->slot_index_tags = devm_bitmap_zalloc(dev, s, GFP_KERNEL);
2521	hisi_hba->slot_index_tags = devm_kzalloc(dev, s, GFP_KERNEL);
2522	if (!hisi_hba->slot_index_tags)	2507	if (!hisi_hba->slot_index_tags)
2523	goto err_out;	2508	goto err_out;
2524		2509
@@ -2536,7 +2521,6 @@ int hisi_sas_alloc(struct hisi_hba *hisi_hba) · 11 unmodified lines
2536	if (!hisi_hba->sata_breakpoint)	2521	if (!hisi_hba->sata_breakpoint)
2537	goto err_out;	2522	goto err_out;
2538		2523
2539	hisi_sas_slot_index_init(hisi_hba);
2540	hisi_hba->last_slot_index = HISI_SAS_UNRESERVED_IPTT;	2524	hisi_hba->last_slot_index = HISI_SAS_UNRESERVED_IPTT;
2541		2525
2542	hisi_hba->wq = create_singlethread_workqueue(dev_name(dev));	2526	hisi_hba->wq = create_singlethread_workqueue(dev_name(dev));

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c+29−6

@@ -1484,7 +1484,6 @@ static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) · 1483 unmodified lines
1484	struct asd_sas_phy *sas_phy = &phy->sas_phy;	1484	struct asd_sas_phy *sas_phy = &phy->sas_phy;
1485	struct device *dev = hisi_hba->dev;	1485	struct device *dev = hisi_hba->dev;
1486		1486
1487	del_timer(&phy->timer);
1488	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);	1487	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1489		1488
1490	port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);	1489	port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
@@ -1561,9 +1560,18 @@ static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) · 70 unmodified lines
1561	}	1560	}
1562		1561
1563	phy->port_id = port_id;	1562	phy->port_id = port_id;
1564	phy->phy_attached = 1;	1563
1565	hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);	1564	/* Call pm_runtime_put_sync() with pairs in hisi_sas_phyup_pm_work() */
		1565	pm_runtime_get_noresume(dev);
		1566	hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP_PM);
		1567
1566	res = IRQ_HANDLED;	1568	res = IRQ_HANDLED;
		1569
		1570	spin_lock(&phy->lock);
		1571	/* Delete timer and set phy_attached atomically */
		1572	del_timer(&phy->timer);
		1573	phy->phy_attached = 1;
		1574	spin_unlock(&phy->lock);
1567	end:	1575	end:
1568	if (phy->reset_completion)	1576	if (phy->reset_completion)
1569	complete(phy->reset_completion);	1577	complete(phy->reset_completion);
@@ -4775,6 +4783,8 @@ hisi_sas_v3_probe(struct pci_dev pdev, const struct pci_device_id id) · 3205 unmodified lines
4775		4783
4776	scsi_scan_host(shost);	4784	scsi_scan_host(shost);
4777		4785
		4786	pm_runtime_set_autosuspend_delay(dev, 5000);
		4787	pm_runtime_use_autosuspend(dev);
4778	/*	4788	/*
4779	* For the situation that there are ATA disks connected with SAS	4789	* For the situation that there are ATA disks connected with SAS
4780	* controller, it additionally creates ata_port which will affect the	4790	* controller, it additionally creates ata_port which will affect the
@@ -4848,6 +4858,7 @@ static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) · 67 unmodified lines
4848	int rc;	4858	int rc;
4849		4859
4850	dev_info(dev, "FLR prepare\n");	4860	dev_info(dev, "FLR prepare\n");
		4861	down(&hisi_hba->sem);
4851	set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);	4862	set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
4852	hisi_sas_controller_reset_prepare(hisi_hba);	4863	hisi_sas_controller_reset_prepare(hisi_hba);
4853		4864
@@ -4897,6 +4908,8 @@ static int _suspend_v3_hw(struct device *device) · 43 unmodified lines
4897	if (test_and_set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))	4908	if (test_and_set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))
4898	return -1;	4909	return -1;
4899		4910
		4911	dev_warn(dev, "entering suspend state\n");
		4912
4900	scsi_block_requests(shost);	4913	scsi_block_requests(shost);
4901	set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);	4914	set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
4902	flush_workqueue(hisi_hba->wq);	4915	flush_workqueue(hisi_hba->wq);
@@ -4912,11 +4925,11 @@ static int _suspend_v3_hw(struct device *device) · 9 unmodified lines
4912		4925
4913	hisi_sas_init_mem(hisi_hba);	4926	hisi_sas_init_mem(hisi_hba);
4914		4927
4915	dev_warn(dev, "entering suspend state\n");
4916
4917	hisi_sas_release_tasks(hisi_hba);	4928	hisi_sas_release_tasks(hisi_hba);
4918		4929
4919	sas_suspend_ha(sha);	4930	sas_suspend_ha(sha);
		4931
		4932	dev_warn(dev, "end of suspending controller\n");
4920	return 0;	4933	return 0;
4921	}	4934	}
4922		4935
@@ -4943,9 +4956,19 @@ static int _resume_v3_hw(struct device *device) · 20 unmodified lines
4943	return rc;	4956	return rc;
4944	}	4957	}
4945	phys_init_v3_hw(hisi_hba);	4958	phys_init_v3_hw(hisi_hba);
4946	sas_resume_ha(sha);	4959
		4960	/*
		4961	* If a directly-attached disk is removed during suspend, a deadlock
		4962	* may occur, as the PHYE_RESUME_TIMEOUT processing will require the
		4963	* hisi_hba->device to be active, which can only happen when resume
		4964	* completes. So don't wait for the HA event workqueue to drain upon
		4965	* resume.
		4966	*/
		4967	sas_resume_ha_no_sync(sha);
4947	clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);	4968	clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
4948		4969
		4970	dev_warn(dev, "end of resuming controller\n");
		4971
4949	return 0;	4972	return 0;
4950	}	4973	}
4951		4974

drivers/scsi/hosts.c+3−12

 static struct class shost_class = {
 	.name		= "scsi_host",
 	.dev_release	= scsi_host_cls_release,
+	.dev_groups	= scsi_shost_groups,
 };
 /**
 struct Scsi_Host *scsi_host_alloc(struct scsi_host_template *sht, int privsize)
 {
 	struct Scsi_Host *shost;
-	int index, i, j = 0;
+	int index;
 	shost = kzalloc(sizeof(struct Scsi_Host) + privsize, GFP_KERNEL);
 	if (!shost)
 	shost->shost_dev.parent = &shost->shost_gendev;
 	shost->shost_dev.class = &shost_class;
 	dev_set_name(&shost->shost_dev, "host%d", shost->host_no);
-	shost->shost_dev.groups = shost->shost_dev_attr_groups;
+	shost->shost_dev.groups = sht->shost_groups;
-	shost->shost_dev_attr_groups[j++] = &scsi_shost_attr_group;
-	if (sht->shost_groups) {
-		for (i = 0; sht->shost_groups[i] &&
-			     j < ARRAY_SIZE(shost->shost_dev_attr_groups);
-		     i++, j++) {
-			shost->shost_dev_attr_groups[j] =
-				sht->shost_groups[i];
-		}
-	}
-	WARN_ON_ONCE(j >= ARRAY_SIZE(shost->shost_dev_attr_groups));
 	shost->ehandler = kthread_run(scsi_error_handler, shost,
 			"scsi_eh_%d", shost->host_no);

drivers/scsi/hpsa.c+0−2

 	int i, ndevs_to_allocate;
 	int raid_ctlr_position;
 	bool physical_device;
-	DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
 	currentsd = kcalloc(HPSA_MAX_DEVICES, sizeof(*currentsd), GFP_KERNEL);
 	physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
 		dev_err(&h->pdev->dev, "out of memory\n");
 		goto out;
 	}
-	memset(lunzerobits, 0, sizeof(lunzerobits));
 	h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */

drivers/scsi/initio.c+2−3

 /**
  *	i91u_queuecommand_lck	-	Queue a new command if possible
  *	@cmd: SCSI command block from the mid layer
- *	@done: Completion handler
  *
  *	Attempts to queue a new command with the host adapter. Will return
  *	zero if successful or indicate a host busy condition if not (which
  *	will cause the mid layer to call us again later with the command)
  */
 static int i91u_queuecommand_lck(struct scsi_cmnd *cmd)
 {
 	struct initio_host *host = (struct initio_host *) cmd->device->host->hostdata;
 	for (; num_scb >= MAX_TARGETS + 3; num_scb--) {
 		i = num_scb * sizeof(struct scsi_ctrl_blk);
-		if ((scb = kzalloc(i, GFP_DMA)) != NULL)
+		scb = kzalloc(i, GFP_KERNEL);
+		if (scb)
 			break;
 	}

drivers/scsi/libsas/sas_discover.c+0−1

@@ -8,7 +8,6 @@ · 7 unmodified lines
8		8
9	#include <linux/scatterlist.h>	9	#include <linux/scatterlist.h>
10	#include <linux/slab.h>	10	#include <linux/slab.h>
11	#include <linux/async.h>
12	#include <scsi/scsi_host.h>	11	#include <scsi/scsi_host.h>
13	#include <scsi/scsi_eh.h>	12	#include <scsi/scsi_eh.h>
14	#include "sas_internal.h"	13	#include "sas_internal.h"

drivers/scsi/libsas/sas_event.c+63−14

@@ -41,12 +41,25 @@ static int sas_queue_event(int event, struct sas_work *work, · 40 unmodified lines
41	return rc;	41	return rc;
42	}	42	}
43		43
44		44	void sas_queue_deferred_work(struct sas_ha_struct *ha)
45	void __sas_drain_work(struct sas_ha_struct *ha)
46	{	45	{
47	struct sas_work sw, _sw;	46	struct sas_work sw, _sw;
48	int ret;	47	int ret;
49		48
		49	spin_lock_irq(&ha->lock);
		50	list_for_each_entry_safe(sw, _sw, &ha->defer_q, drain_node) {
		51	list_del_init(&sw->drain_node);
		52	ret = sas_queue_work(ha, sw);
		53	if (ret != 1) {
		54	pm_runtime_put(ha->dev);
		55	sas_free_event(to_asd_sas_event(&sw->work));
		56	}
		57	}
		58	spin_unlock_irq(&ha->lock);
		59	}
		60
		61	void __sas_drain_work(struct sas_ha_struct *ha)
		62	{
50	set_bit(SAS_HA_DRAINING, &ha->state);	63	set_bit(SAS_HA_DRAINING, &ha->state);
51	/* flush submitters */	64	/* flush submitters */
52	spin_lock_irq(&ha->lock);	65	spin_lock_irq(&ha->lock);
@@ -55,16 +68,8 @@ void __sas_drain_work(struct sas_ha_struct *ha) · 2 unmodified lines
55	drain_workqueue(ha->event_q);	68	drain_workqueue(ha->event_q);
56	drain_workqueue(ha->disco_q);	69	drain_workqueue(ha->disco_q);
57		70
58	spin_lock_irq(&ha->lock);
59	clear_bit(SAS_HA_DRAINING, &ha->state);	71	clear_bit(SAS_HA_DRAINING, &ha->state);
60	list_for_each_entry_safe(sw, _sw, &ha->defer_q, drain_node) {	72	sas_queue_deferred_work(ha);
61	list_del_init(&sw->drain_node);
62	ret = sas_queue_work(ha, sw);
63	if (ret != 1)
64	sas_free_event(to_asd_sas_event(&sw->work));
65
66	}
67	spin_unlock_irq(&ha->lock);
68	}	73	}
69		74
70	int sas_drain_work(struct sas_ha_struct *ha)	75	int sas_drain_work(struct sas_ha_struct *ha)
@@ -104,11 +109,15 @@ void sas_enable_revalidation(struct sas_ha_struct *ha) · 33 unmodified lines
104	if (!test_and_clear_bit(ev, &d->pending))	109	if (!test_and_clear_bit(ev, &d->pending))
105	continue;	110	continue;
106		111
107	if (list_empty(&port->phy_list))	112	spin_lock(&port->phy_list_lock);
		113	if (list_empty(&port->phy_list)) {
		114	spin_unlock(&port->phy_list_lock);
108	continue;	115	continue;
		116	}
109		117
110	sas_phy = container_of(port->phy_list.next, struct asd_sas_phy,	118	sas_phy = container_of(port->phy_list.next, struct asd_sas_phy,
111	port_phy_el);	119	port_phy_el);
		120	spin_unlock(&port->phy_list_lock);
112	sas_notify_port_event(sas_phy,	121	sas_notify_port_event(sas_phy,
113	PORTE_BROADCAST_RCVD, GFP_KERNEL);	122	PORTE_BROADCAST_RCVD, GFP_KERNEL);
114	}	123	}
@@ -119,19 +128,43 @@ void sas_enable_revalidation(struct sas_ha_struct *ha) · 4 unmodified lines
119	static void sas_port_event_worker(struct work_struct *work)	128	static void sas_port_event_worker(struct work_struct *work)
120	{	129	{
121	struct asd_sas_event *ev = to_asd_sas_event(work);	130	struct asd_sas_event *ev = to_asd_sas_event(work);
		131	struct asd_sas_phy *phy = ev->phy;
		132	struct sas_ha_struct *ha = phy->ha;
122		133
123	sas_port_event_fns[ev->event](work);	134	sas_port_event_fns[ev->event](work);
		135	pm_runtime_put(ha->dev);
124	sas_free_event(ev);	136	sas_free_event(ev);
125	}	137	}
126		138
127	static void sas_phy_event_worker(struct work_struct *work)	139	static void sas_phy_event_worker(struct work_struct *work)
128	{	140	{
129	struct asd_sas_event *ev = to_asd_sas_event(work);	141	struct asd_sas_event *ev = to_asd_sas_event(work);
		142	struct asd_sas_phy *phy = ev->phy;
		143	struct sas_ha_struct *ha = phy->ha;
130		144
131	sas_phy_event_fns[ev->event](work);	145	sas_phy_event_fns[ev->event](work);
		146	pm_runtime_put(ha->dev);
132	sas_free_event(ev);	147	sas_free_event(ev);
133	}	148	}
134		149
		150	/* defer works of new phys during suspend */
		151	static bool sas_defer_event(struct asd_sas_phy phy, struct asd_sas_event ev)
		152	{
		153	struct sas_ha_struct *ha = phy->ha;
		154	unsigned long flags;
		155	bool deferred = false;
		156
		157	spin_lock_irqsave(&ha->lock, flags);
		158	if (test_bit(SAS_HA_RESUMING, &ha->state) && !phy->suspended) {
		159	struct sas_work *sw = &ev->work;
		160
		161	list_add_tail(&sw->drain_node, &ha->defer_q);
		162	deferred = true;
		163	}
		164	spin_unlock_irqrestore(&ha->lock, flags);
		165	return deferred;
		166	}
		167
135	int sas_notify_port_event(struct asd_sas_phy *phy, enum port_event event,	168	int sas_notify_port_event(struct asd_sas_phy *phy, enum port_event event,
136	gfp_t gfp_flags)	169	gfp_t gfp_flags)
137	{	170	{
@@ -145,11 +178,19 @@ int sas_notify_port_event(struct asd_sas_phy *phy, enum port_event event, · 7 unmodified lines
145	if (!ev)	178	if (!ev)
146	return -ENOMEM;	179	return -ENOMEM;
147		180
		181	/* Call pm_runtime_put() with pairs in sas_port_event_worker() */
		182	pm_runtime_get_noresume(ha->dev);
		183
148	INIT_SAS_EVENT(ev, sas_port_event_worker, phy, event);	184	INIT_SAS_EVENT(ev, sas_port_event_worker, phy, event);
149		185
		186	if (sas_defer_event(phy, ev))
		187	return 0;
		188
150	ret = sas_queue_event(event, &ev->work, ha);	189	ret = sas_queue_event(event, &ev->work, ha);
151	if (ret != 1)	190	if (ret != 1) {
		191	pm_runtime_put(ha->dev);
152	sas_free_event(ev);	192	sas_free_event(ev);
		193	}
153		194
154	return ret;	195	return ret;
155	}	196	}
@@ -168,11 +209,19 @@ int sas_notify_phy_event(struct asd_sas_phy *phy, enum phy_event event, · 12 unmodified lines
168	if (!ev)	209	if (!ev)
169	return -ENOMEM;	210	return -ENOMEM;
170		211
		212	/* Call pm_runtime_put() with pairs in sas_phy_event_worker() */
		213	pm_runtime_get_noresume(ha->dev);
		214
171	INIT_SAS_EVENT(ev, sas_phy_event_worker, phy, event);	215	INIT_SAS_EVENT(ev, sas_phy_event_worker, phy, event);
172		216
		217	if (sas_defer_event(phy, ev))
		218	return 0;
		219
173	ret = sas_queue_event(event, &ev->work, ha);	220	ret = sas_queue_event(event, &ev->work, ha);
174	if (ret != 1)	221	if (ret != 1) {
		222	pm_runtime_put(ha->dev);
175	sas_free_event(ev);	223	sas_free_event(ev);
		224	}
176		225
177	return ret;	226	return ret;
178	}	227	}

drivers/scsi/libsas/sas_expander.c+3−0

 	struct sas_task *task = NULL;
 	struct sas_internal *i =
 		to_sas_internal(dev->port->ha->core.shost->transportt);
+	struct sas_ha_struct *ha = dev->port->ha;
+	pm_runtime_get_sync(ha->dev);
 	mutex_lock(&dev->ex_dev.cmd_mutex);
 	for (retry = 0; retry < 3; retry++) {
 		if (test_bit(SAS_DEV_GONE, &dev->state)) {
 		}
 	}
 	mutex_unlock(&dev->ex_dev.cmd_mutex);
+	pm_runtime_put_sync(ha->dev);
 	BUG_ON(retry == 3 && task != NULL);
 	sas_free_task(task);

drivers/scsi/libsas/sas_init.c+47−2

@@ -362,6 +362,7 @@ void sas_prep_resume_ha(struct sas_ha_struct *ha) · 361 unmodified lines
362	int i;	362	int i;
363		363
364	set_bit(SAS_HA_REGISTERED, &ha->state);	364	set_bit(SAS_HA_REGISTERED, &ha->state);
		365	set_bit(SAS_HA_RESUMING, &ha->state);
365		366
366	/* clear out any stale link events/data from the suspension path */	367	/* clear out any stale link events/data from the suspension path */
367	for (i = 0; i < ha->num_phys; i++) {	368	for (i = 0; i < ha->num_phys; i++) {
@@ -387,7 +388,31 @@ static int phys_suspended(struct sas_ha_struct *ha) · 19 unmodified lines
387	return rc;	388	return rc;
388	}	389	}
389		390
390	void sas_resume_ha(struct sas_ha_struct *ha)	391	static void sas_resume_insert_broadcast_ha(struct sas_ha_struct *ha)
		392	{
		393	int i;
		394
		395	for (i = 0; i < ha->num_phys; i++) {
		396	struct asd_sas_port *port = ha->sas_port[i];
		397	struct domain_device *dev = port->port_dev;
		398
		399	if (dev && dev_is_expander(dev->dev_type)) {
		400	struct asd_sas_phy *first_phy;
		401
		402	spin_lock(&port->phy_list_lock);
		403	first_phy = list_first_entry_or_null(
		404	&port->phy_list, struct asd_sas_phy,
		405	port_phy_el);
		406	spin_unlock(&port->phy_list_lock);
		407
		408	if (first_phy)
		409	sas_notify_port_event(first_phy,
		410	PORTE_BROADCAST_RCVD, GFP_KERNEL);
		411	}
		412	}
		413	}
		414
		415	static void _sas_resume_ha(struct sas_ha_struct *ha, bool drain)
391	{	416	{
392	const unsigned long tmo = msecs_to_jiffies(25000);	417	const unsigned long tmo = msecs_to_jiffies(25000);
393	int i;	418	int i;
@@ -417,10 +442,30 @@ void sas_resume_ha(struct sas_ha_struct *ha) · 23 unmodified lines
417	* flush out disks that did not return	442	* flush out disks that did not return
418	*/	443	*/
419	scsi_unblock_requests(ha->core.shost);	444	scsi_unblock_requests(ha->core.shost);
420	sas_drain_work(ha);	445	if (drain)
		446	sas_drain_work(ha);
		447	clear_bit(SAS_HA_RESUMING, &ha->state);
		448
		449	sas_queue_deferred_work(ha);
		450	/* send event PORTE_BROADCAST_RCVD to identify some new inserted
		451	* disks for expander
		452	*/
		453	sas_resume_insert_broadcast_ha(ha);
		454	}
		455
		456	void sas_resume_ha(struct sas_ha_struct *ha)
		457	{
		458	_sas_resume_ha(ha, true);
421	}	459	}
422	EXPORT_SYMBOL(sas_resume_ha);	460	EXPORT_SYMBOL(sas_resume_ha);
423		461
		462	/* A no-sync variant, which does not call sas_drain_ha(). */
		463	void sas_resume_ha_no_sync(struct sas_ha_struct *ha)
		464	{
		465	_sas_resume_ha(ha, false);
		466	}
		467	EXPORT_SYMBOL(sas_resume_ha_no_sync);
		468
424	void sas_suspend_ha(struct sas_ha_struct *ha)	469	void sas_suspend_ha(struct sas_ha_struct *ha)
425	{	470	{
426	int i;	471	int i;

drivers/scsi/libsas/sas_internal.h+2−0

 #include <scsi/scsi_transport_sas.h>
 #include <scsi/libsas.h>
 #include <scsi/sas_ata.h>
+#include <linux/pm_runtime.h>
 #ifdef pr_fmt
 #undef pr_fmt
 void sas_disable_revalidation(struct sas_ha_struct *ha);
 void sas_enable_revalidation(struct sas_ha_struct *ha);
+void sas_queue_deferred_work(struct sas_ha_struct *ha);
 void __sas_drain_work(struct sas_ha_struct *ha);
 void sas_deform_port(struct asd_sas_phy *phy, int gone);

drivers/scsi/libsas/sas_scsi_host.c+4−3

 static void sas_end_task(struct scsi_cmnd *sc, struct sas_task *task)
 {
 	struct task_status_struct *ts = &task->task_status;
-	int hs = 0, stat = 0;
+	enum scsi_host_status hs = DID_OK;
+	enum exec_status stat = SAS_SAM_STAT_GOOD;
 	if (ts->resp == SAS_TASK_UNDELIVERED) {
 		/* transport error */
 		case SAS_ABORTED_TASK:
 			hs = DID_ABORT;
 			break;
-		case SAM_STAT_CHECK_CONDITION:
+		case SAS_SAM_STAT_CHECK_CONDITION:
 			memcpy(sc->sense_buffer, ts->buf,
 			       min(SCSI_SENSE_BUFFERSIZE, ts->buf_valid_size));
-			stat = SAM_STAT_CHECK_CONDITION;
+			stat = SAS_SAM_STAT_CHECK_CONDITION;
 			break;
 		default:
 			stat = ts->stat;

drivers/scsi/lpfc/lpfc.h+47−50

@@ -496,52 +496,50 @@ struct lpfc_cgn_info { · 495 unmodified lines
496	__le32 cgn_alarm_hr[24];	496	__le32 cgn_alarm_hr[24];
497	__le32 cgn_alarm_day[LPFC_MAX_CGN_DAYS];	497	__le32 cgn_alarm_day[LPFC_MAX_CGN_DAYS];
498		498
499	/* Start of congestion statistics */	499	struct_group(cgn_stat,
500	uint8_t cgn_stat_npm; /* Notifications per minute */	500	uint8_t cgn_stat_npm; /* Notifications per minute */
501		501
502	/* Start Time */	502	/* Start Time */
503	uint8_t cgn_stat_month;	503	uint8_t cgn_stat_month;
504	uint8_t cgn_stat_day;	504	uint8_t cgn_stat_day;
505	uint8_t cgn_stat_year;	505	uint8_t cgn_stat_year;
506	uint8_t cgn_stat_hour;	506	uint8_t cgn_stat_hour;
507	uint8_t cgn_stat_minute;	507	uint8_t cgn_stat_minute;
508	uint8_t cgn_pad2[2];	508	uint8_t cgn_pad2[2];
509		509
510	__le32 cgn_notification;	510	__le32 cgn_notification;
511	__le32 cgn_peer_notification;	511	__le32 cgn_peer_notification;
512	__le32 link_integ_notification;	512	__le32 link_integ_notification;
513	__le32 delivery_notification;	513	__le32 delivery_notification;
514		514
515	uint8_t cgn_stat_cgn_month; /* Last congestion notification FPIN */	515	uint8_t cgn_stat_cgn_month; /* Last congestion notification FPIN */
516	uint8_t cgn_stat_cgn_day;	516	uint8_t cgn_stat_cgn_day;
517	uint8_t cgn_stat_cgn_year;	517	uint8_t cgn_stat_cgn_year;
518	uint8_t cgn_stat_cgn_hour;	518	uint8_t cgn_stat_cgn_hour;
519	uint8_t cgn_stat_cgn_min;	519	uint8_t cgn_stat_cgn_min;
520	uint8_t cgn_stat_cgn_sec;	520	uint8_t cgn_stat_cgn_sec;
521		521
522	uint8_t cgn_stat_peer_month; /* Last peer congestion FPIN */	522	uint8_t cgn_stat_peer_month; /* Last peer congestion FPIN */
523	uint8_t cgn_stat_peer_day;	523	uint8_t cgn_stat_peer_day;
524	uint8_t cgn_stat_peer_year;	524	uint8_t cgn_stat_peer_year;
525	uint8_t cgn_stat_peer_hour;	525	uint8_t cgn_stat_peer_hour;
526	uint8_t cgn_stat_peer_min;	526	uint8_t cgn_stat_peer_min;
527	uint8_t cgn_stat_peer_sec;	527	uint8_t cgn_stat_peer_sec;
528		528
529	uint8_t cgn_stat_lnk_month; /* Last link integrity FPIN */	529	uint8_t cgn_stat_lnk_month; /* Last link integrity FPIN */
530	uint8_t cgn_stat_lnk_day;	530	uint8_t cgn_stat_lnk_day;
531	uint8_t cgn_stat_lnk_year;	531	uint8_t cgn_stat_lnk_year;
532	uint8_t cgn_stat_lnk_hour;	532	uint8_t cgn_stat_lnk_hour;
533	uint8_t cgn_stat_lnk_min;	533	uint8_t cgn_stat_lnk_min;
534	uint8_t cgn_stat_lnk_sec;	534	uint8_t cgn_stat_lnk_sec;
535		535
536	uint8_t cgn_stat_del_month; /* Last delivery notification FPIN */	536	uint8_t cgn_stat_del_month; /* Last delivery notification FPIN */
537	uint8_t cgn_stat_del_day;	537	uint8_t cgn_stat_del_day;
538	uint8_t cgn_stat_del_year;	538	uint8_t cgn_stat_del_year;
539	uint8_t cgn_stat_del_hour;	539	uint8_t cgn_stat_del_hour;
540	uint8_t cgn_stat_del_min;	540	uint8_t cgn_stat_del_min;
541	uint8_t cgn_stat_del_sec;	541	uint8_t cgn_stat_del_sec;
542	#define LPFC_CGN_STAT_SIZE 48	542	);
543	#define LPFC_CGN_DATA_SIZE (sizeof(struct lpfc_cgn_info) - \
544	LPFC_CGN_STAT_SIZE - sizeof(uint32_t))
545		543
546	__le32 cgn_info_crc;	544	__le32 cgn_info_crc;
547	#define LPFC_CGN_CRC32_MAGIC_NUMBER 0x1EDC6F41	545	#define LPFC_CGN_CRC32_MAGIC_NUMBER 0x1EDC6F41
@@ -669,8 +667,6 @@ struct lpfc_vport { · 121 unmodified lines
669	struct timer_list els_tmofunc;	667	struct timer_list els_tmofunc;
670	struct timer_list delayed_disc_tmo;	668	struct timer_list delayed_disc_tmo;
671		669
672	int unreg_vpi_cmpl;
673
674	uint8_t load_flag;	670	uint8_t load_flag;
675	#define FC_LOADING 0x1 /* HBA in process of loading drvr */	671	#define FC_LOADING 0x1 /* HBA in process of loading drvr */
676	#define FC_UNLOADING 0x2 /* HBA in process of unloading drvr */	672	#define FC_UNLOADING 0x2 /* HBA in process of unloading drvr */
@@ -1023,7 +1019,6 @@ struct lpfc_hba { · 346 unmodified lines
1023	#define HBA_DEVLOSS_TMO 0x2000 /* HBA in devloss timeout */	1019	#define HBA_DEVLOSS_TMO 0x2000 /* HBA in devloss timeout */
1024	#define HBA_RRQ_ACTIVE 0x4000 /* process the rrq active list */	1020	#define HBA_RRQ_ACTIVE 0x4000 /* process the rrq active list */
1025	#define HBA_IOQ_FLUSH 0x8000 /* FCP/NVME I/O queues being flushed */	1021	#define HBA_IOQ_FLUSH 0x8000 /* FCP/NVME I/O queues being flushed */
1026	#define HBA_FW_DUMP_OP 0x10000 /* Skips fn reset before FW dump */
1027	#define HBA_RECOVERABLE_UE 0x20000 /* Firmware supports recoverable UE */	1022	#define HBA_RECOVERABLE_UE 0x20000 /* Firmware supports recoverable UE */
1028	#define HBA_FORCED_LINK_SPEED 0x40000 /*	1023	#define HBA_FORCED_LINK_SPEED 0x40000 /*
1029	* Firmware supports Forced Link Speed	1024	* Firmware supports Forced Link Speed
@@ -1031,7 +1026,7 @@ struct lpfc_hba { · 1 unmodified line
1031	*/	1026	*/
1032	#define HBA_PCI_ERR 0x80000 /* The PCI slot is offline */	1027	#define HBA_PCI_ERR 0x80000 /* The PCI slot is offline */
1033	#define HBA_FLOGI_ISSUED 0x100000 /* FLOGI was issued */	1028	#define HBA_FLOGI_ISSUED 0x100000 /* FLOGI was issued */
1034	#define HBA_CGN_RSVD1 0x200000 /* Reserved CGN flag */	1029	#define HBA_SHORT_CMF 0x200000 /* shorter CMF timer routine */
1035	#define HBA_CGN_DAY_WRAP 0x400000 /* HBA Congestion info day wraps */	1030	#define HBA_CGN_DAY_WRAP 0x400000 /* HBA Congestion info day wraps */
1036	#define HBA_DEFER_FLOGI 0x800000 /* Defer FLOGI till read_sparm cmpl */	1031	#define HBA_DEFER_FLOGI 0x800000 /* Defer FLOGI till read_sparm cmpl */
1037	#define HBA_SETUP 0x1000000 /* Signifies HBA setup is completed */	1032	#define HBA_SETUP 0x1000000 /* Signifies HBA setup is completed */
@@ -1040,6 +1035,7 @@ struct lpfc_hba { · 2 unmodified lines
1040	#define HBA_HBEAT_TMO 0x8000000 /* HBEAT initiated after timeout */	1035	#define HBA_HBEAT_TMO 0x8000000 /* HBEAT initiated after timeout */
1041	#define HBA_FLOGI_OUTSTANDING 0x10000000 /* FLOGI is outstanding */	1036	#define HBA_FLOGI_OUTSTANDING 0x10000000 /* FLOGI is outstanding */
1042		1037
		1038	struct completion fw_dump_cmpl; / cmpl event tracker for fw_dump */
1043	uint32_t fcp_ring_in_use; /* When polling test if intr-hndlr active*/	1039	uint32_t fcp_ring_in_use; /* When polling test if intr-hndlr active*/
1044	struct lpfc_dmabuf slim2p;	1040	struct lpfc_dmabuf slim2p;
1045		1041
@@ -1604,6 +1600,7 @@ struct lpfc_hba { · 558 unmodified lines
1604	#define LPFC_MAX_RXMONITOR_ENTRY 800	1600	#define LPFC_MAX_RXMONITOR_ENTRY 800
1605	#define LPFC_MAX_RXMONITOR_DUMP 32	1601	#define LPFC_MAX_RXMONITOR_DUMP 32
1606	struct rxtable_entry {	1602	struct rxtable_entry {
		1603	uint64_t cmf_bytes; /* Total no of read bytes for CMF_SYNC_WQE */
1607	uint64_t total_bytes; /* Total no of read bytes requested */	1604	uint64_t total_bytes; /* Total no of read bytes requested */
1608	uint64_t rcv_bytes; /* Total no of read bytes completed */	1605	uint64_t rcv_bytes; /* Total no of read bytes completed */
1609	uint64_t avg_io_size;	1606	uint64_t avg_io_size;

drivers/scsi/lpfc/lpfc_attr.c+40−22

@@ -1709,25 +1709,25 @@ lpfc_sli4_pdev_reg_request(struct lpfc_hba *phba, uint32_t opcode) · 1708 unmodified lines
1709	before_fc_flag = phba->pport->fc_flag;	1709	before_fc_flag = phba->pport->fc_flag;
1710	sriov_nr_virtfn = phba->cfg_sriov_nr_virtfn;	1710	sriov_nr_virtfn = phba->cfg_sriov_nr_virtfn;
1711		1711
1712	/* Disable SR-IOV virtual functions if enabled */	1712	if (opcode == LPFC_FW_DUMP) {
1713	if (phba->cfg_sriov_nr_virtfn) {	1713	init_completion(&online_compl);
1714	pci_disable_sriov(pdev);	1714	phba->fw_dump_cmpl = &online_compl;
1715	phba->cfg_sriov_nr_virtfn = 0;	1715	} else {
1716	}	1716	/* Disable SR-IOV virtual functions if enabled */
		1717	if (phba->cfg_sriov_nr_virtfn) {
		1718	pci_disable_sriov(pdev);
		1719	phba->cfg_sriov_nr_virtfn = 0;
		1720	}
1717		1721
1718	if (opcode == LPFC_FW_DUMP)	1722	status = lpfc_do_offline(phba, LPFC_EVT_OFFLINE);
1719	phba->hba_flag \|= HBA_FW_DUMP_OP;
1720		1723
1721	status = lpfc_do_offline(phba, LPFC_EVT_OFFLINE);	1724	if (status != 0)
		1725	return status;
1722		1726
1723	if (status != 0) {	1727	/* wait for the device to be quiesced before firmware reset */
1724	phba->hba_flag &= ~HBA_FW_DUMP_OP;	1728	msleep(100);
1725	return status;
1726	}	1729	}
1727		1730
1728	/* wait for the device to be quiesced before firmware reset */
1729	msleep(100);
1730
1731	reg_val = readl(phba->sli4_hba.conf_regs_memmap_p +	1731	reg_val = readl(phba->sli4_hba.conf_regs_memmap_p +
1732	LPFC_CTL_PDEV_CTL_OFFSET);	1732	LPFC_CTL_PDEV_CTL_OFFSET);
1733		1733
@@ -1756,24 +1756,42 @@ lpfc_sli4_pdev_reg_request(struct lpfc_hba *phba, uint32_t opcode) · 22 unmodified lines
1756	lpfc_printf_log(phba, KERN_ERR, LOG_SLI,	1756	lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
1757	"3153 Fail to perform the requested "	1757	"3153 Fail to perform the requested "
1758	"access: x%x\n", reg_val);	1758	"access: x%x\n", reg_val);
		1759	if (phba->fw_dump_cmpl)
		1760	phba->fw_dump_cmpl = NULL;
1759	return rc;	1761	return rc;
1760	}	1762	}
1761		1763
1762	/* keep the original port state */	1764	/* keep the original port state */
1763	if (before_fc_flag & FC_OFFLINE_MODE)	1765	if (before_fc_flag & FC_OFFLINE_MODE) {
1764	goto out;	1766	if (phba->fw_dump_cmpl)
1765		1767	phba->fw_dump_cmpl = NULL;
1766	init_completion(&online_compl);
1767	job_posted = lpfc_workq_post_event(phba, &status, &online_compl,
1768	LPFC_EVT_ONLINE);
1769	if (!job_posted)
1770	goto out;	1768	goto out;
		1769	}
1771		1770
1772	wait_for_completion(&online_compl);	1771	/* Firmware dump will trigger an HA_ERATT event, and
		1772	* lpfc_handle_eratt_s4 routine already handles bringing the port back
		1773	* online.
		1774	*/
		1775	if (opcode == LPFC_FW_DUMP) {
		1776	wait_for_completion(phba->fw_dump_cmpl);
		1777	} else {
		1778	init_completion(&online_compl);
		1779	job_posted = lpfc_workq_post_event(phba, &status, &online_compl,
		1780	LPFC_EVT_ONLINE);
		1781	if (!job_posted)
		1782	goto out;
1773		1783
		1784	wait_for_completion(&online_compl);
		1785	}
1774	out:	1786	out:
1775	/* in any case, restore the virtual functions enabled as before */	1787	/* in any case, restore the virtual functions enabled as before */
1776	if (sriov_nr_virtfn) {	1788	if (sriov_nr_virtfn) {
		1789	/* If fw_dump was performed, first disable to clean up */
		1790	if (opcode == LPFC_FW_DUMP) {
		1791	pci_disable_sriov(pdev);
		1792	phba->cfg_sriov_nr_virtfn = 0;
		1793	}
		1794
1777	sriov_err =	1795	sriov_err =
1778	lpfc_sli_probe_sriov_nr_virtfn(phba, sriov_nr_virtfn);	1796	lpfc_sli_probe_sriov_nr_virtfn(phba, sriov_nr_virtfn);
1779	if (!sriov_err)	1797	if (!sriov_err)

drivers/scsi/lpfc/lpfc_debugfs.c+20−7

 		if (len > (LPFC_CGN_BUF_SIZE - LPFC_DEBUG_OUT_LINE_SZ)) {
 			len += scnprintf(buffer + len, LPFC_CGN_BUF_SIZE - len,
 					 "Truncated . . .\n");
-			break;
+			goto out;
 		}
 		len += scnprintf(buffer + len, LPFC_CGN_BUF_SIZE - len,
 				 "%03x: %08x %08x %08x %08x "
 		cnt += 32;
 		ptr += 8;
 	}
+	if (len > (LPFC_CGN_BUF_SIZE - LPFC_DEBUG_OUT_LINE_SZ)) {
+		len += scnprintf(buffer + len, LPFC_CGN_BUF_SIZE - len,
+				 "Truncated . . .\n");
+		goto out;
+	}
+	len += scnprintf(buffer + len, LPFC_CGN_BUF_SIZE - len,
+			 "Parameter Data\n");
+	ptr = (uint32_t *)&phba->cgn_p;
+	len += scnprintf(buffer + len, LPFC_CGN_BUF_SIZE - len,
+			 "%08x %08x %08x %08x\n",
+			 *ptr, *(ptr + 1), *(ptr + 2), *(ptr + 3));
 out:
 	return simple_read_from_buffer(buf, nbytes, ppos, buffer, len);
 }
 	start = tail;
 	len += scnprintf(buffer + len, MAX_DEBUGFS_RX_TABLE_SIZE - len,
-			"        MaxBPI\t Total Data Cmd  Total Data Cmpl "
+			"        MaxBPI    Tot_Data_CMF Tot_Data_Cmd "
-			"  Latency(us)    Avg IO Size\tMax IO Size   IO cnt "
+			"Tot_Data_Cmpl  Lat(us)  Avg_IO  Max_IO "
-			"Info BWutil(ms)\n");
+			"Bsy IO_cnt Info BWutil(ms)\n");
 get_table:
 	for (i = start; i < last; i++) {
 		entry = &phba->rxtable[i];
 		len += scnprintf(buffer + len, MAX_DEBUGFS_RX_TABLE_SIZE - len,
-				"%3d:%12lld  %12lld\t%12lld\t"
+				"%3d:%12lld %12lld %12lld %12lld "
-				"%8lldus\t%8lld\t%10lld "
+				"%7lldus %8lld %7lld "
-				"%8d   %2d %2d(%2d)\n",
+				"%2d   %4d   %2d   %2d(%2d)\n",
 				i, entry->max_bytes_per_interval,
+				entry->cmf_bytes,
 				entry->total_bytes,
 				entry->rcv_bytes,
 				entry->avg_io_latency,
 				entry->avg_io_size,
 				entry->max_read_cnt,
+				entry->cmf_busy,
 				entry->io_cnt,
 				entry->cmf_info,
 				entry->timer_utilization,

drivers/scsi/lpfc/lpfc_debugfs.h+1−1

@@ -282,7 +282,7 @@ struct lpfc_idiag { · 281 unmodified lines
282	void *ptr_private;	282	void *ptr_private;
283	};	283	};
284		284
285	#define MAX_DEBUGFS_RX_TABLE_SIZE (100 * LPFC_MAX_RXMONITOR_ENTRY)	285	#define MAX_DEBUGFS_RX_TABLE_SIZE (128 * LPFC_MAX_RXMONITOR_ENTRY)
286	struct lpfc_rx_monitor_debug {	286	struct lpfc_rx_monitor_debug {
287	char *i_private;	287	char *i_private;
288	char *buffer;	288	char *buffer;

drivers/scsi/lpfc/lpfc_els.c+15−7

 		return 1;
 	}
-	/* This will cause the callback-function lpfc_cmpl_els_cmd to
-	 * trigger the release of node.
-	 */
-	if (!(vport->fc_flag & FC_PT2PT))
-		lpfc_nlp_put(ndlp);
 	return 0;
 }
 lpfc_get_rdp_info(struct lpfc_hba *phba, struct lpfc_rdp_context *rdp_context)
 {
 	LPFC_MBOXQ_t *mbox = NULL;
+	struct lpfc_dmabuf *mp;
 	int rc;
 	mbox = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
 	mbox->mbox_cmpl = lpfc_mbx_cmpl_rdp_page_a0;
 	mbox->ctx_ndlp = (struct lpfc_rdp_context *)rdp_context;
 	rc = lpfc_sli_issue_mbox(phba, mbox, MBX_NOWAIT);
-	if (rc == MBX_NOT_FINISHED)
+	if (rc == MBX_NOT_FINISHED) {
+		mp = (struct lpfc_dmabuf *)mbox->ctx_buf;
+		lpfc_mbuf_free(phba, mp->virt, mp->phys);
 		goto issue_mbox_fail;
+	}
 	return 0;
 		lpfc_can_disctmo(vport);
 	}
+	if (ndlp->save_flags & NLP_WAIT_FOR_LOGO) {
+		/* Wake up lpfc_vport_delete if waiting...*/
+		if (ndlp->logo_waitq)
+			wake_up(ndlp->logo_waitq);
+		spin_lock_irq(&ndlp->lock);
+		ndlp->nlp_flag &= ~(NLP_ISSUE_LOGO | NLP_LOGO_SND);
+		ndlp->save_flags &= ~NLP_WAIT_FOR_LOGO;
+		spin_unlock_irq(&ndlp->lock);
+	}
 	/* Safe to release resources now. */
 	lpfc_els_free_iocb(phba, cmdiocb);
 	lpfc_nlp_put(ndlp);
-	vport->unreg_vpi_cmpl = VPORT_ERROR;
 }
 /**

drivers/scsi/lpfc/lpfc_hbadisc.c+7−3

 	if (phba->pci_dev_grp == LPFC_PCI_DEV_OC)
 		lpfc_sli4_post_async_mbox(phba);
-	if (ha_copy & HA_ERATT)
+	if (ha_copy & HA_ERATT) {
 		/* Handle the error attention event */
 		lpfc_handle_eratt(phba);
+		if (phba->fw_dump_cmpl) {
+			complete(phba->fw_dump_cmpl);
+			phba->fw_dump_cmpl = NULL;
+		}
+	}
 	if (ha_copy & HA_MBATT)
 		lpfc_sli_handle_mb_event(phba);
 	vport->vpi_state &= ~LPFC_VPI_REGISTERED;
 	vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
 	spin_unlock_irq(shost->host_lock);
-	vport->unreg_vpi_cmpl = VPORT_OK;
 	mempool_free(pmb, phba->mbox_mem_pool);
 	lpfc_cleanup_vports_rrqs(vport, NULL);
 	/*
 		lpfc_printf_vlog(vport, KERN_ERR, LOG_TRACE_EVENT,
 				 "1800 Could not issue unreg_vpi\n");
 		mempool_free(mbox, phba->mbox_mem_pool);
-		vport->unreg_vpi_cmpl = VPORT_ERROR;
 		return rc;
 	}
 	return 0;

drivers/scsi/lpfc/lpfc_hw.h+18−11

 };
 typedef struct {
+	struct_group_tagged(MAILBOX_word0, bits,
+		union {
+			struct {
 #ifdef __BIG_ENDIAN_BITFIELD
-	uint16_t mbxStatus;
+				uint16_t mbxStatus;
-	uint8_t mbxCommand;
+				uint8_t mbxCommand;
-	uint8_t mbxReserved:6;
+				uint8_t mbxReserved:6;
-	uint8_t mbxHc:1;
+				uint8_t mbxHc:1;
-	uint8_t mbxOwner:1;	/* Low order bit first word */
+				uint8_t mbxOwner:1;	/* Low order bit first word */
 #else	/*  __LITTLE_ENDIAN_BITFIELD */
-	uint8_t mbxOwner:1;	/* Low order bit first word */
+				uint8_t mbxOwner:1;	/* Low order bit first word */
-	uint8_t mbxHc:1;
+				uint8_t mbxHc:1;
-	uint8_t mbxReserved:6;
+				uint8_t mbxReserved:6;
-	uint8_t mbxCommand;
+				uint8_t mbxCommand;
-	uint16_t mbxStatus;
+				uint16_t mbxStatus;
 #endif
+			};
+			u32 word0;
+		};
+	);
 	MAILVARIANTS un;
 	union sli_var us;
 #define IOERR_ILLEGAL_COMMAND         0x06
 #define IOERR_XCHG_DROPPED            0x07
 #define IOERR_ILLEGAL_FIELD           0x08
-#define IOERR_BAD_CONTINUE            0x09
+#define IOERR_RPI_SUSPENDED           0x09
 #define IOERR_TOO_MANY_BUFFERS        0x0A
 #define IOERR_RCV_BUFFER_WAITING      0x0B
 #define IOERR_NO_CONNECTION           0x0C

drivers/scsi/lpfc/lpfc_init.c+29−12

@@ -5373,8 +5373,10 @@ lpfc_sli4_async_link_evt(struct lpfc_hba *phba, · 5372 unmodified lines
5373	*/	5373	*/
5374	if (!(phba->hba_flag & HBA_FCOE_MODE)) {	5374	if (!(phba->hba_flag & HBA_FCOE_MODE)) {
5375	rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);	5375	rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
5376	if (rc == MBX_NOT_FINISHED)	5376	if (rc == MBX_NOT_FINISHED) {
		5377	lpfc_mbuf_free(phba, mp->virt, mp->phys);
5377	goto out_free_dmabuf;	5378	goto out_free_dmabuf;
		5379	}
5378	return;	5380	return;
5379	}	5381	}
5380	/*	5382	/*
@@ -5925,7 +5927,7 @@ lpfc_cmf_timer(struct hrtimer *timer) · 544 unmodified lines
5925	uint32_t io_cnt;	5927	uint32_t io_cnt;
5926	uint32_t head, tail;	5928	uint32_t head, tail;
5927	uint32_t busy, max_read;	5929	uint32_t busy, max_read;
5928	uint64_t total, rcv, lat, mbpi, extra;	5930	uint64_t total, rcv, lat, mbpi, extra, cnt;
5929	int timer_interval = LPFC_CMF_INTERVAL;	5931	int timer_interval = LPFC_CMF_INTERVAL;
5930	uint32_t ms;	5932	uint32_t ms;
5931	struct lpfc_cgn_stat *cgs;	5933	struct lpfc_cgn_stat *cgs;
@@ -5996,20 +5998,28 @@ lpfc_cmf_timer(struct hrtimer *timer) · 64 unmodified lines
5996		5998
5997	/* Calculate any extra bytes needed to account for the	5999	/* Calculate any extra bytes needed to account for the
5998	* timer accuracy. If we are less than LPFC_CMF_INTERVAL	6000	* timer accuracy. If we are less than LPFC_CMF_INTERVAL
5999	* add an extra 3% slop factor, equal to LPFC_CMF_INTERVAL	6001	* calculate the adjustment needed for total to reflect
6000	* add an extra 2%. The goal is to equalize total with a	6002	* a full LPFC_CMF_INTERVAL.
6001	* time > LPFC_CMF_INTERVAL or <= LPFC_CMF_INTERVAL + 1
6002	*/	6003	*/
6003	if (ms == LPFC_CMF_INTERVAL)	6004	if (ms && ms < LPFC_CMF_INTERVAL) {
6004	extra = div_u64(total, 50);	6005	cnt = div_u64(total, ms); /* bytes per ms */
6005	else if (ms < LPFC_CMF_INTERVAL)	6006	cnt = LPFC_CMF_INTERVAL; / what total should be */
6006	extra = div_u64(total, 33);	6007
		6008	/* If the timeout is scheduled to be shorter,
		6009	* this value may skew the data, so cap it at mbpi.
		6010	*/
		6011	if ((phba->hba_flag & HBA_SHORT_CMF) && cnt > mbpi)
		6012	cnt = mbpi;
		6013
		6014	extra = cnt - total;
		6015	}
6007	lpfc_issue_cmf_sync_wqe(phba, LPFC_CMF_INTERVAL, total + extra);	6016	lpfc_issue_cmf_sync_wqe(phba, LPFC_CMF_INTERVAL, total + extra);
6008	} else {	6017	} else {
6009	/* For Monitor mode or link down we want mbpi	6018	/* For Monitor mode or link down we want mbpi
6010	* to be the full link speed	6019	* to be the full link speed
6011	*/	6020	*/
6012	mbpi = phba->cmf_link_byte_count;	6021	mbpi = phba->cmf_link_byte_count;
		6022	extra = 0;
6013	}	6023	}
6014	phba->cmf_timer_cnt++;	6024	phba->cmf_timer_cnt++;
6015		6025
@@ -6040,6 +6050,7 @@ lpfc_cmf_timer(struct hrtimer *timer) · 24 unmodified lines
6040	LPFC_RXMONITOR_TABLE_IN_USE);	6050	LPFC_RXMONITOR_TABLE_IN_USE);
6041	entry = &phba->rxtable[head];	6051	entry = &phba->rxtable[head];
6042	entry->total_bytes = total;	6052	entry->total_bytes = total;
		6053	entry->cmf_bytes = total + extra;
6043	entry->rcv_bytes = rcv;	6054	entry->rcv_bytes = rcv;
6044	entry->cmf_busy = busy;	6055	entry->cmf_busy = busy;
6045	entry->cmf_info = phba->cmf_active_info;	6056	entry->cmf_info = phba->cmf_active_info;
@@ -6082,6 +6093,8 @@ lpfc_cmf_timer(struct hrtimer *timer) · 36 unmodified lines
6082	/* Each minute save Fabric and Driver congestion information */	6093	/* Each minute save Fabric and Driver congestion information */
6083	lpfc_cgn_save_evt_cnt(phba);	6094	lpfc_cgn_save_evt_cnt(phba);
6084		6095
		6096	phba->hba_flag &= ~HBA_SHORT_CMF;
		6097
6085	/* Since we need to call lpfc_cgn_save_evt_cnt every minute, on the	6098	/* Since we need to call lpfc_cgn_save_evt_cnt every minute, on the
6086	* minute, adjust our next timer interval, if needed, to ensure a	6099	* minute, adjust our next timer interval, if needed, to ensure a
6087	* 1 minute granularity when we get the next timer interrupt.	6100	* 1 minute granularity when we get the next timer interrupt.
@@ -6092,6 +6105,8 @@ lpfc_cmf_timer(struct hrtimer *timer) · 4 unmodified lines
6092	jiffies);	6105	jiffies);
6093	if (timer_interval <= 0)	6106	if (timer_interval <= 0)
6094	timer_interval = LPFC_CMF_INTERVAL;	6107	timer_interval = LPFC_CMF_INTERVAL;
		6108	else
		6109	phba->hba_flag \|= HBA_SHORT_CMF;
6095		6110
6096	/* If we adjust timer_interval, max_bytes_per_interval	6111	/* If we adjust timer_interval, max_bytes_per_interval
6097	* needs to be adjusted as well.	6112	* needs to be adjusted as well.
@@ -6337,8 +6352,10 @@ lpfc_sli4_async_fc_evt(struct lpfc_hba phba, struct lpfc_acqe_fc_la acqe_fc) · 239 unmodified lines
6337	}	6352	}
6338		6353
6339	rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);	6354	rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
6340	if (rc == MBX_NOT_FINISHED)	6355	if (rc == MBX_NOT_FINISHED) {
		6356	lpfc_mbuf_free(phba, mp->virt, mp->phys);
6341	goto out_free_dmabuf;	6357	goto out_free_dmabuf;
		6358	}
6342	return;	6359	return;
6343		6360
6344	out_free_dmabuf:	6361	out_free_dmabuf:
@@ -13464,7 +13481,7 @@ lpfc_init_congestion_buf(struct lpfc_hba *phba) · 7119 unmodified lines
13464	phba->cgn_evt_minute = 0;	13481	phba->cgn_evt_minute = 0;
13465	phba->hba_flag &= ~HBA_CGN_DAY_WRAP;	13482	phba->hba_flag &= ~HBA_CGN_DAY_WRAP;
13466		13483
13467	memset(cp, 0xff, LPFC_CGN_DATA_SIZE);	13484	memset(cp, 0xff, offsetof(struct lpfc_cgn_info, cgn_stat));
13468	cp->cgn_info_size = cpu_to_le16(LPFC_CGN_INFO_SZ);	13485	cp->cgn_info_size = cpu_to_le16(LPFC_CGN_INFO_SZ);
13469	cp->cgn_info_version = LPFC_CGN_INFO_V3;	13486	cp->cgn_info_version = LPFC_CGN_INFO_V3;
13470		13487
@@ -13523,7 +13540,7 @@ lpfc_init_congestion_stat(struct lpfc_hba *phba) · 52 unmodified lines
13523	return;	13540	return;
13524		13541
13525	cp = (struct lpfc_cgn_info *)phba->cgn_i->virt;	13542	cp = (struct lpfc_cgn_info *)phba->cgn_i->virt;
13526	memset(&cp->cgn_stat_npm, 0, LPFC_CGN_STAT_SIZE);	13543	memset(&cp->cgn_stat, 0, sizeof(cp->cgn_stat));
13527		13544
13528	ktime_get_real_ts64(&cmpl_time);	13545	ktime_get_real_ts64(&cmpl_time);
13529	time64_to_tm(cmpl_time.tv_sec, 0, &broken);	13546	time64_to_tm(cmpl_time.tv_sec, 0, &broken);

drivers/scsi/lpfc/lpfc_nportdisc.c+6−0

 {
 	struct lpfc_hba    *phba = vport->phba;
 	struct lpfc_dmabuf *pcmd;
+	struct lpfc_dmabuf *mp;
 	uint64_t nlp_portwwn = 0;
 	uint32_t *lp;
 	IOCB_t *icmd;
 		 * a default RPI.
 		 */
 		if (phba->sli_rev == LPFC_SLI_REV4) {
+			mp = (struct lpfc_dmabuf *)login_mbox->ctx_buf;
+			if (mp) {
+				lpfc_mbuf_free(phba, mp->virt, mp->phys);
+				kfree(mp);
+			}
 			mempool_free(login_mbox, phba->mbox_mem_pool);
 			login_mbox = NULL;
 		} else {

drivers/scsi/lpfc/lpfc_scsi.c+5−3

 		if (lpfc_cmd->result == IOERR_INVALID_RPI ||
 		    lpfc_cmd->result == IOERR_NO_RESOURCES ||
 		    lpfc_cmd->result == IOERR_ABORT_REQUESTED ||
+		    lpfc_cmd->result == IOERR_RPI_SUSPENDED ||
 		    lpfc_cmd->result == IOERR_SLER_CMD_RCV_FAILURE) {
 			cmd->result = DID_REQUEUE << 16;
 			break;
 		lpfc_printf_vlog(vport, KERN_INFO, LOG_FCP,
 				 "9039 Iodone <%d/%llu> cmd x%px, error "
-				 "x%x SNS x%x x%x Data: x%x x%x\n",
+				 "x%x SNS x%x x%x LBA x%llx Data: x%x x%x\n",
 				 cmd->device->id, cmd->device->lun, cmd,
-				 cmd->result, *lp, *(lp + 3), cmd->retries,
+				 cmd->result, *lp, *(lp + 3),
-				 scsi_get_resid(cmd));
+				 (u64)scsi_get_lba(cmd),
+				 cmd->retries, scsi_get_resid(cmd));
 	}
 	lpfc_update_stats(vport, lpfc_cmd);

drivers/scsi/lpfc/lpfc_sli.c+15−23

 {
 	uint32_t __iomem *resp_buf;
 	uint32_t __iomem *mbox_buf;
-	volatile uint32_t mbox;
+	volatile struct MAILBOX_word0 mbox;
 	uint32_t hc_copy, ha_copy, resp_data;
 	int  i;
 	uint8_t hdrtype;
 		phba->pport->stopped = 1;
 	}
-	mbox = 0;
+	mbox.word0 = 0;
-	((MAILBOX_t *)&mbox)->mbxCommand = MBX_KILL_BOARD;
+	mbox.mbxCommand = MBX_KILL_BOARD;
-	((MAILBOX_t *)&mbox)->mbxOwner = OWN_CHIP;
+	mbox.mbxOwner = OWN_CHIP;
 	writel(BARRIER_TEST_PATTERN, (resp_buf + 1));
 	mbox_buf = phba->MBslimaddr;
-	writel(mbox, mbox_buf);
+	writel(mbox.word0, mbox_buf);
 	for (i = 0; i < 50; i++) {
 		if (lpfc_readl((resp_buf + 1), &resp_data))
 			goto clear_errat;
 	}
-	((MAILBOX_t *)&mbox)->mbxOwner = OWN_HOST;
+	mbox.mbxOwner = OWN_HOST;
 	resp_data = 0;
 	for (i = 0; i < 500; i++) {
 		if (lpfc_readl(resp_buf, &resp_data))
 			return;
-		if (resp_data != mbox)
+		if (resp_data != mbox.word0)
 			mdelay(1);
 		else
 			break;
 	phba->fcf.fcf_flag = 0;
 	spin_unlock_irq(&phba->hbalock);
-	/* SLI4 INTF 2: if FW dump is being taken skip INIT_PORT */
-	if (phba->hba_flag & HBA_FW_DUMP_OP) {
-		phba->hba_flag &= ~HBA_FW_DUMP_OP;
-		return rc;
-	}
 	/* Now physically reset the device */
 	lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
 			"0389 Performing PCI function reset!\n");
 static int
 lpfc_sli_brdrestart_s3(struct lpfc_hba *phba)
 {
-	MAILBOX_t *mb;
+	volatile struct MAILBOX_word0 mb;
 	struct lpfc_sli *psli;
-	volatile uint32_t word0;
 	void __iomem *to_slim;
 	uint32_t hba_aer_enabled;
 			(phba->pport) ? phba->pport->port_state : 0,
 			psli->sli_flag);
-	word0 = 0;
+	mb.word0 = 0;
-	mb = (MAILBOX_t *) &word0;
+	mb.mbxCommand = MBX_RESTART;
-	mb->mbxCommand = MBX_RESTART;
+	mb.mbxHc = 1;
-	mb->mbxHc = 1;
 	lpfc_reset_barrier(phba);
 	to_slim = phba->MBslimaddr;
-	writel(*(uint32_t *) mb, to_slim);
+	writel(mb.word0, to_slim);
 	readl(to_slim); /* flush */
 	/* Only skip post after fc_ffinit is completed */
 	if (phba->pport && phba->pport->port_state)
-		word0 = 1;	/* This is really setting up word1 */
+		mb.word0 = 1;	/* This is really setting up word1 */
 	else
-		word0 = 0;	/* This is really setting up word1 */
+		mb.word0 = 0;	/* This is really setting up word1 */
 	to_slim = phba->MBslimaddr + sizeof (uint32_t);
-	writel(*(uint32_t *) mb, to_slim);
+	writel(mb.word0, to_slim);
 	readl(to_slim); /* flush */
 	lpfc_sli_brdreset(phba);

drivers/scsi/lpfc/lpfc_version.h+1−1

@@ -20,7 +20,7 @@ · 19 unmodified lines
20	* included with this package. *	20	* included with this package. *
21	*******************************************************************/	21	*******************************************************************/
22		22
23	#define LPFC_DRIVER_VERSION "14.0.0.3"	23	#define LPFC_DRIVER_VERSION "14.0.0.4"
24	#define LPFC_DRIVER_NAME "lpfc"	24	#define LPFC_DRIVER_NAME "lpfc"
25		25
26	/* Used for SLI 2/3 */	26	/* Used for SLI 2/3 */

drivers/scsi/lpfc/lpfc_vport.c+63−20

@@ -485,23 +485,68 @@ error_out: · 484 unmodified lines
485	return rc;	485	return rc;
486	}	486	}
487		487
		488	static int
		489	lpfc_send_npiv_logo(struct lpfc_vport vport, struct lpfc_nodelist ndlp)
		490	{
		491	int rc;
		492	struct lpfc_hba *phba = vport->phba;
		493
		494	DECLARE_WAIT_QUEUE_HEAD_ONSTACK(waitq);
		495
		496	spin_lock_irq(&ndlp->lock);
		497	if (!(ndlp->save_flags & NLP_WAIT_FOR_LOGO) &&
		498	!ndlp->logo_waitq) {
		499	ndlp->logo_waitq = &waitq;
		500	ndlp->nlp_fcp_info &= ~NLP_FCP_2_DEVICE;
		501	ndlp->nlp_flag \|= NLP_ISSUE_LOGO;
		502	ndlp->save_flags \|= NLP_WAIT_FOR_LOGO;
		503	}
		504	spin_unlock_irq(&ndlp->lock);
		505	rc = lpfc_issue_els_npiv_logo(vport, ndlp);
		506	if (!rc) {
		507	wait_event_timeout(waitq,
		508	(!(ndlp->save_flags & NLP_WAIT_FOR_LOGO)),
		509	msecs_to_jiffies(phba->fc_ratov * 2000));
		510
		511	if (!(ndlp->save_flags & NLP_WAIT_FOR_LOGO))
		512	goto logo_cmpl;
		513	/* LOGO wait failed. Correct status. */
		514	rc = -EINTR;
		515	} else {
		516	rc = -EIO;
		517	}
		518
		519	/* Error - clean up node flags. */
		520	spin_lock_irq(&ndlp->lock);
		521	ndlp->nlp_flag &= ~NLP_ISSUE_LOGO;
		522	ndlp->save_flags &= ~NLP_WAIT_FOR_LOGO;
		523	spin_unlock_irq(&ndlp->lock);
		524
		525	logo_cmpl:
		526	lpfc_printf_vlog(vport, KERN_INFO, LOG_VPORT,
		527	"1824 Issue LOGO completes with status %d\n",
		528	rc);
		529	spin_lock_irq(&ndlp->lock);
		530	ndlp->logo_waitq = NULL;
		531	spin_unlock_irq(&ndlp->lock);
		532	return rc;
		533	}
		534
488	static int	535	static int
489	disable_vport(struct fc_vport *fc_vport)	536	disable_vport(struct fc_vport *fc_vport)
490	{	537	{
491	struct lpfc_vport vport = (struct lpfc_vport **)fc_vport->dd_data;	538	struct lpfc_vport vport = (struct lpfc_vport **)fc_vport->dd_data;
492	struct lpfc_hba *phba = vport->phba;	539	struct lpfc_hba *phba = vport->phba;
493	struct lpfc_nodelist ndlp = NULL, next_ndlp = NULL;	540	struct lpfc_nodelist ndlp = NULL, next_ndlp = NULL;
494	long timeout;
495	struct Scsi_Host *shost = lpfc_shost_from_vport(vport);	541	struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
496		542
		543	/* Can't disable during an outstanding delete. */
		544	if (vport->load_flag & FC_UNLOADING)
		545	return 0;
		546
497	ndlp = lpfc_findnode_did(vport, Fabric_DID);	547	ndlp = lpfc_findnode_did(vport, Fabric_DID);
498	if (ndlp && phba->link_state >= LPFC_LINK_UP) {	548	if (ndlp && phba->link_state >= LPFC_LINK_UP)
499	vport->unreg_vpi_cmpl = VPORT_INVAL;	549	(void)lpfc_send_npiv_logo(vport, ndlp);
500	timeout = msecs_to_jiffies(phba->fc_ratov * 2000);
501	if (!lpfc_issue_els_npiv_logo(vport, ndlp))
502	while (vport->unreg_vpi_cmpl == VPORT_INVAL && timeout)
503	timeout = schedule_timeout(timeout);
504	}
505		550
506	lpfc_sli_host_down(vport);	551	lpfc_sli_host_down(vport);
507		552
@@ -600,7 +645,7 @@ lpfc_vport_delete(struct fc_vport *fc_vport) · 92 unmodified lines
600	struct lpfc_vport vport = (struct lpfc_vport **)fc_vport->dd_data;	645	struct lpfc_vport vport = (struct lpfc_vport **)fc_vport->dd_data;
601	struct Scsi_Host *shost = lpfc_shost_from_vport(vport);	646	struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
602	struct lpfc_hba *phba = vport->phba;	647	struct lpfc_hba *phba = vport->phba;
603	long timeout;	648	int rc;
604		649
605	if (vport->port_type == LPFC_PHYSICAL_PORT) {	650	if (vport->port_type == LPFC_PHYSICAL_PORT) {
606	lpfc_printf_vlog(vport, KERN_ERR, LOG_TRACE_EVENT,	651	lpfc_printf_vlog(vport, KERN_ERR, LOG_TRACE_EVENT,
@@ -665,15 +710,14 @@ lpfc_vport_delete(struct fc_vport *fc_vport) · 58 unmodified lines
665	phba->fc_topology != LPFC_TOPOLOGY_LOOP) {	710	phba->fc_topology != LPFC_TOPOLOGY_LOOP) {
666	if (vport->cfg_enable_da_id) {	711	if (vport->cfg_enable_da_id) {
667	/* Send DA_ID and wait for a completion. */	712	/* Send DA_ID and wait for a completion. */
668	timeout = msecs_to_jiffies(phba->fc_ratov * 2000);	713	rc = lpfc_ns_cmd(vport, SLI_CTNS_DA_ID, 0, 0);
669	if (!lpfc_ns_cmd(vport, SLI_CTNS_DA_ID, 0, 0))	714	if (rc) {
670	while (vport->ct_flags && timeout)
671	timeout = schedule_timeout(timeout);
672	else
673	lpfc_printf_log(vport->phba, KERN_WARNING,	715	lpfc_printf_log(vport->phba, KERN_WARNING,
674	LOG_VPORT,	716	LOG_VPORT,
675	"1829 CT command failed to "	717	"1829 CT command failed to "
676	"delete objects on fabric\n");	718	"delete objects on fabric, "
		719	"rc %d\n", rc);
		720	}
677	}	721	}
678		722
679	/*	723	/*
@@ -688,11 +732,10 @@ lpfc_vport_delete(struct fc_vport *fc_vport) · 8 unmodified lines
688	ndlp = lpfc_findnode_did(vport, Fabric_DID);	732	ndlp = lpfc_findnode_did(vport, Fabric_DID);
689	if (!ndlp)	733	if (!ndlp)
690	goto skip_logo;	734	goto skip_logo;
691	vport->unreg_vpi_cmpl = VPORT_INVAL;	735
692	timeout = msecs_to_jiffies(phba->fc_ratov * 2000);	736	rc = lpfc_send_npiv_logo(vport, ndlp);
693	if (!lpfc_issue_els_npiv_logo(vport, ndlp))	737	if (rc)
694	while (vport->unreg_vpi_cmpl == VPORT_INVAL && timeout)	738	goto skip_logo;
695	timeout = schedule_timeout(timeout);
696	}	739	}
697		740
698	if (!(phba->pport->load_flag & FC_UNLOADING))	741	if (!(phba->pport->load_flag & FC_UNLOADING))

drivers/scsi/megaraid/megaraid_mbox.c+0−1

@@ -1431,7 +1431,6 @@ mbox_post_cmd(adapter_t adapter, scb_t scb) · 1430 unmodified lines
1431	/**	1431	/**
1432	* megaraid_queue_command_lck - generic queue entry point for all LLDs	1432	* megaraid_queue_command_lck - generic queue entry point for all LLDs
1433	* @scp : pointer to the scsi command to be executed	1433	* @scp : pointer to the scsi command to be executed
1434	* @done : callback routine to be called after the cmd has be completed
1435	*	1434	*
1436	* Queue entry point for mailbox based controllers.	1435	* Queue entry point for mailbox based controllers.
1437	*/	1436	*/

drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h+498−105

 #define MPI3_CONFIG_PAGETYPE_IO_UNIT                    (0x00)
 #define MPI3_CONFIG_PAGETYPE_MANUFACTURING              (0x01)
 #define MPI3_CONFIG_PAGETYPE_IOC                        (0x02)
-#define MPI3_CONFIG_PAGETYPE_UEFI_BSD                   (0x03)
+#define MPI3_CONFIG_PAGETYPE_DRIVER                     (0x03)
 #define MPI3_CONFIG_PAGETYPE_SECURITY                   (0x04)
 #define MPI3_CONFIG_PAGETYPE_ENCLOSURE                  (0x11)
 #define MPI3_CONFIG_PAGETYPE_DEVICE                     (0x12)
 #define MPI3_SAS_HWRATE_MIN_RATE_6_0                    (0x0a)
 #define MPI3_SAS_HWRATE_MIN_RATE_12_0                   (0x0b)
 #define MPI3_SAS_HWRATE_MIN_RATE_22_5                   (0x0c)
-#define MPI3_SLOT_INVALID                           (0xffff)
+#define MPI3_SLOT_INVALID                               (0xffff)
-#define MPI3_SLOT_INDEX_INVALID                     (0xffff)
+#define MPI3_SLOT_INDEX_INVALID                         (0xffff)
+#define MPI3_LINK_CHANGE_COUNT_INVALID                   (0xffff)
+#define MPI3_RATE_CHANGE_COUNT_INVALID                   (0xffff)
+#define MPI3_TEMP_SENSOR_LOCATION_INTERNAL              (0x0)
+#define MPI3_TEMP_SENSOR_LOCATION_INLET                 (0x1)
+#define MPI3_TEMP_SENSOR_LOCATION_OUTLET                (0x2)
+#define MPI3_TEMP_SENSOR_LOCATION_DRAM                  (0x3)
+#define MPI3_MFGPAGE_VENDORID_BROADCOM                  (0x1000)
+#define MPI3_MFGPAGE_DEVID_SAS4116                      (0x00a5)
+#define MPI3_MFGPAGE_DEVID_SAS4016                      (0x00a7)
 struct mpi3_man_page0 {
 	struct mpi3_config_page_header         header;
 	u8                                 chip_revision[8];
 	__le32                             reserved98;
 	u8                                 oem;
 	u8                                 sub_oem;
-	__le16                             reserved9e;
+	__le16                             flags;
 	u8                                 board_mfg_day;
 	u8                                 board_mfg_month;
 	__le16                             board_mfg_year;
 };
 #define MPI3_MAN0_PAGEVERSION       (0x00)
+#define MPI3_MAN0_FLAGS_SWITCH_PRESENT                       (0x0002)
+#define MPI3_MAN0_FLAGS_EXPANDER_PRESENT                     (0x0001)
 #define MPI3_MAN1_VPD_SIZE                                   (512)
 struct mpi3_man_page1 {
 	struct mpi3_config_page_header         header;
 #define MPI3_MAN5_PAGEVERSION                                (0x00)
 struct mpi3_man6_gpio_entry {
 	u8         function_code;
-	u8         reserved01;
+	u8         function_flags;
 	__le16     flags;
 	u8         param1;
 	u8         param2;
 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW                            (0x06)
 #define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT                              (0x07)
 #define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE                             (0x08)
-#define MPI3_MAN6_GPIO_FUNCTION_ISTWI_MUX_RESET                               (0x09)
 #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET                                   (0x0a)
 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET                            (0x0b)
 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT                                  (0x0c)
 #define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE                                     (0x10)
 #define MPI3_MAN6_GPIO_FUNCTION_LICENSE                                       (0x11)
 #define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL                                (0x12)
+#define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP                      (0x13)
+#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK               (0x01)
+#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI              (0x00)
+#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID       (0x01)
 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK                        (0xf0)
 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC                     (0x00)
 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT                  (0x10)
 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT             (0x00)
 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE        (0x01)
 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE          (0x02)
-#define MPI3_MAN6_GPIO_ISTWI_MUX_RESET_PARAM2_SPEC_MUX                        (0x00)
-#define MPI3_MAN6_GPIO_ISTWI_MUX_RESET_PARAM2_ALL_MUXES                       (0x01)
 #define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON                            (0x00)
 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK                                   (0x0100)
 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE                              (0x0100)
 	__le32                             reserved0c;
 };
+#define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_HOST_PHY          (0xff)
 #ifndef MPI3_MAN8_PHY_INFO_MAX
 #define MPI3_MAN8_PHY_INFO_MAX                      (1)
 #endif
 };
 enum mpi3_man9_resources {
-	MPI3_MAN9_RSRC_OUTSTANDING_REQS = 0,
+	MPI3_MAN9_RSRC_OUTSTANDING_REQS    = 0,
-	MPI3_MAN9_RSRC_TARGET_CMDS      = 1,
+	MPI3_MAN9_RSRC_TARGET_CMDS         = 1,
-	MPI3_MAN9_RSRC_SAS_TARGETS      = 2,
+	MPI3_MAN9_RSRC_RESERVED02          = 2,
-	MPI3_MAN9_RSRC_PCIE_TARGETS     = 3,
+	MPI3_MAN9_RSRC_NVME                = 3,
-	MPI3_MAN9_RSRC_INITIATORS       = 4,
+	MPI3_MAN9_RSRC_INITIATORS          = 4,
-	MPI3_MAN9_RSRC_VDS              = 5,
+	MPI3_MAN9_RSRC_VDS                 = 5,
-	MPI3_MAN9_RSRC_ENCLOSURES       = 6,
+	MPI3_MAN9_RSRC_ENCLOSURES          = 6,
-	MPI3_MAN9_RSRC_ENCLOSURE_PHYS   = 7,
+	MPI3_MAN9_RSRC_ENCLOSURE_PHYS      = 7,
-	MPI3_MAN9_RSRC_EXPANDERS        = 8,
+	MPI3_MAN9_RSRC_EXPANDERS           = 8,
-	MPI3_MAN9_RSRC_PCIE_SWITCHES    = 9,
+	MPI3_MAN9_RSRC_PCIE_SWITCHES       = 9,
-	MPI3_MAN9_RSRC_PDS              = 10,
+	MPI3_MAN9_RSRC_RESERVED10          = 10,
-	MPI3_MAN9_RSRC_HOST_PDS         = 11,
+	MPI3_MAN9_RSRC_HOST_PD_DRIVES      = 11,
-	MPI3_MAN9_RSRC_ADV_HOST_PDS     = 12,
+	MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES  = 12,
-	MPI3_MAN9_RSRC_RAID_PDS         = 13,
+	MPI3_MAN9_RSRC_RAID_PD_DRIVES      = 13,
+	MPI3_MAN9_RSRC_DRV_DIAG_BUF        = 14,
+	MPI3_MAN9_RSRC_NAMESPACE_COUNT     = 15,
 	MPI3_MAN9_RSRC_NUM_RESOURCES
 };
 #define MPI3_MAN9_MIN_ENCLOSURES            (0)
 #define MPI3_MAN9_MAX_ENCLOSURES            (65535)
 #define MPI3_MAN9_MIN_ENCLOSURE_PHYS        (0)
+#define MPI3_MAN9_MIN_NAMESPACE_COUNT       (1)
 #define MPI3_MAN9_MIN_EXPANDERS             (0)
 #define MPI3_MAN9_MAX_EXPANDERS             (65535)
 #define MPI3_MAN9_MIN_PCIE_SWITCHES         (0)
 struct mpi3_man10_istwi_ctrlr_entry {
 	__le16     slave_address;
 	__le16     flags;
-	__le32     reserved04;
+	u8         scl_low_override;
+	u8         scl_high_override;
+	__le16     reserved06;
 };
+#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK         (0x000c)
+#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100K         (0x0000)
+#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400K         (0x0004)
 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_SLAVE_ENABLED          (0x0002)
 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_MASTER_ENABLED         (0x0001)
 #ifndef MPI3_MAN10_ISTWI_CTRLR_MAX
 	u8         temp_channel[4];
 };
-#define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654         (0x00)
+#define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654                (0x00)
-#define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442         (0x01)
+#define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442                (0x01)
-#define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476         (0x02)
+#define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476                (0x02)
-#define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED      (0x01)
+#define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B                  (0x03)
+#define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK       (0xe0)
+#define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT      (5)
+#define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED             (0x01)
 struct mpi3_man11_seeprom_device_format {
 	u8         size;
 	u8         page_write_size;
 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT                 (4)
 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK            (0x000f)
 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT           (0)
-struct mpi3_man11_bkplane_spec_vpp_format {
+struct mpi3_man11_bkplane_spec_non_ubm_format {
 	__le16     flags;
-	__le16     reserved02;
+	u8         reserved02;
+	u8         type;
 };
-#define MPI3_MAN11_BKPLANE_VPP_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED  (0x0040)
+#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK                    (0xf000)
-#define MPI3_MAN11_BKPLANE_VPP_FLAGS_PRESENCE_DETECT_MASK          (0x0030)
+#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT                   (12)
-#define MPI3_MAN11_BKPLANE_VPP_FLAGS_PRESENCE_DETECT_GPIO          (0x0000)
+#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED  (0x0200)
-#define MPI3_MAN11_BKPLANE_VPP_FLAGS_PRESENCE_DETECT_REG           (0x0010)
+#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK          (0x0030)
-#define MPI3_MAN11_BKPLANE_VPP_FLAGS_POLL_INTERVAL_MASK            (0x000f)
+#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO          (0x0000)
-#define MPI3_MAN11_BKPLANE_VPP_FLAGS_POLL_INTERVAL_SHIFT           (0)
+#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG           (0x0010)
+#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK            (0x000f)
+#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT           (0)
+#define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP                            (0x00)
 union mpi3_man11_bkplane_spec_format {
-	struct mpi3_man11_bkplane_spec_ubm_format     ubm;
+	struct mpi3_man11_bkplane_spec_ubm_format         ubm;
-	struct mpi3_man11_bkplane_spec_vpp_format     vpp;
+	struct mpi3_man11_bkplane_spec_non_ubm_format     non_ubm;
 };
 struct mpi3_man11_bkplane_mgmt_device_format {
 	u8                                        type;
 	u8                                        receptacle_id;
-	__le16                                    reserved02;
+	u8                                        reset_info;
+	u8                                        reserved03;
 	union mpi3_man11_bkplane_spec_format         backplane_mgmt_specific;
 };
 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM            (0x00)
-#define MPI3_MAN11_BKPLANE_MGMT_TYPE_VPP            (0x01)
+#define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM        (0x01)
+#define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK       (0xf0)
+#define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT      (4)
+#define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK        (0x0f)
+#define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT       (0)
 struct mpi3_man11_gas_gauge_device_format {
 	u8         type;
 	u8         reserved01[3];
 };
 #define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD          (0x00)
+struct mpi3_man11_mgmt_ctrlr_device_format {
+	__le32     reserved00;
+	__le32     reserved04;
+};
 union mpi3_man11_device_specific_format {
 	struct mpi3_man11_mux_device_format            mux;
 	struct mpi3_man11_temp_sensor_device_format    temp_sensor;
 	struct mpi3_man11_cable_mgmt_device_format     cable_mgmt;
 	struct mpi3_man11_bkplane_mgmt_device_format   bkplane_mgmt;
 	struct mpi3_man11_gas_gauge_device_format      gas_gauge;
+	struct mpi3_man11_mgmt_ctrlr_device_format     mgmt_controller;
 	__le32                                     words[2];
 };
 #define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT           (0x04)
 #define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT       (0x05)
 #define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE            (0x06)
+#define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER      (0x07)
 #define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT            (0x01)
-#define MPI3_MAN11_ISTWI_FLAGS_BUS_SPEED_MASK         (0x06)
-#define MPI3_MAN11_ISTWI_FLAGS_BUS_SPEED_100KHZ       (0x00)
-#define MPI3_MAN11_ISTWI_FLAGS_BUS_SPEED_400KHZ       (0x02)
 #ifndef MPI3_MAN11_ISTWI_DEVICE_MAX
 #define MPI3_MAN11_ISTWI_DEVICE_MAX             (1)
 #endif
 #define MPI3_MAN14_FLAGS_AUTH_SESSION_REQ                            (0x01)
 #define MPI3_MAN14_FLAGS_AUTH_API_MASK                               (0x0e)
 #define MPI3_MAN14_FLAGS_AUTH_API_NONE                               (0x00)
-#define MPI3_MAN14_FLAGS_AUTH_API_CEREBUS                            (0x02)
+#define MPI3_MAN14_FLAGS_AUTH_API_CERBERUS                           (0x02)
-#define MPI3_MAN14_FLAGS_AUTH_API_DMTF_PMCI                          (0x04)
+#define MPI3_MAN14_FLAGS_AUTH_API_SPDM                               (0x04)
 #ifndef MPI3_MAN15_VERSION_RECORD_MAX
 #define MPI3_MAN15_VERSION_RECORD_MAX      1
 #endif
 	struct mpi3_config_page_header         header;
 	__le32                             flags;
 	u8                                 dmd_io_delay;
-	u8                                 dmd_report_pc_ie;
+	u8                                 dmd_report_pcie;
 	u8                                 dmd_report_sata;
 	u8                                 dmd_report_sas;
 };
 #define MPI3_IOUNIT2_GPIO_SETTING_ON            (0x0001)
 struct mpi3_io_unit3_sensor {
 	__le16             flags;
-	__le16             reserved02;
+	u8                 threshold_margin;
-	__le16             threshold[4];
+	u8                 reserved03;
+	__le16             threshold[3];
+	__le16             reserved0a;
 	__le32             reserved0c;
 	__le32             reserved10;
 	__le32             reserved14;
 };
-#define MPI3_IOUNIT3_SENSOR_FLAGS_T3_ENABLE         (0x0008)
+#define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED           (0x0010)
-#define MPI3_IOUNIT3_SENSOR_FLAGS_T2_ENABLE         (0x0004)
+#define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED          (0x0008)
-#define MPI3_IOUNIT3_SENSOR_FLAGS_T1_ENABLE         (0x0002)
+#define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED        (0x0004)
-#define MPI3_IOUNIT3_SENSOR_FLAGS_T0_ENABLE         (0x0001)
+#define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED       (0x0002)
+#define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED         (0x0001)
 #ifndef MPI3_IO_UNIT3_SENSOR_MAX
-#define MPI3_IO_UNIT3_SENSOR_MAX        (1)
+#define MPI3_IO_UNIT3_SENSOR_MAX                                (1)
 #endif
 struct mpi3_io_unit_page3 {
 	struct mpi3_config_page_header         header;
 	__le32                             reserved08;
 	u8                                 num_sensors;
-	u8                                 polling_interval;
+	u8                                 nominal_poll_interval;
-	__le16                             reserved0e;
+	u8                                 warning_poll_interval;
+	u8                                 reserved0f;
 	struct mpi3_io_unit3_sensor            sensor[MPI3_IO_UNIT3_SENSOR_MAX];
 };
 	__le16             reserved02;
 	u8                 flags;
 	u8                 reserved05[3];
-	__le32             reserved08;
+	__le16             istwi_index;
+	u8                 channel;
+	u8                 reserved0b;
 	__le32             reserved0c;
 };
+#define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK          (0xe0)
+#define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT         (5)
 #define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID        (0x01)
+#define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL    (0xffff)
+#define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED        (0xff)
 #ifndef MPI3_IO_UNIT4_SENSOR_MAX
-#define MPI3_IO_UNIT4_SENSOR_MAX        (1)
+#define MPI3_IO_UNIT4_SENSOR_MAX                                (1)
 #endif
 struct mpi3_io_unit_page4 {
 	struct mpi3_config_page_header         header;
 	struct mpi3_io_unit5_spinup_group      spinup_group_parameters[4];
 	__le32                             reserved18;
 	__le32                             reserved1c;
-	__le32                             reserved20;
+	__le16                             device_shutdown;
-	u8                                 reserved24;
+	__le16                             reserved22;
+	u8                                 pcie_device_wait_time;
 	u8                                 sata_device_wait_time;
 	u8                                 spinup_encl_drive_count;
 	u8                                 spinup_encl_delay;
 };
 #define MPI3_IOUNIT5_PAGEVERSION                           (0x00)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION             (0x00)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED       (0x01)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED     (0x02)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED       (0x02)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER   (0x03)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH     (0x03)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK         (0x0300)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT        (8)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK          (0x00c0)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT         (6)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK         (0x0030)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT        (4)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK         (0x000c)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT        (2)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK          (0x0003)
+#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAA_SSD_SHIFT         (0)
 #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP            (0x02)
 #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE                (0x01)
 #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK                 (0x03)
 };
 #define MPI3_IOC2_PAGEVERSION               (0x00)
-struct mpi3_uefibsd_page0 {
+#define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED               (0x0010)
+#define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED                 (0x0008)
+#define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED                 (0x0004)
+#define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED              (0x0002)
+#define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED                 (0x0001)
+struct mpi3_allowed_cmd_scsi {
+	__le16                             service_action;
+	u8                                 operation_code;
+	u8                                 command_flags;
+};
+struct mpi3_allowed_cmd_ata {
+	u8                                 subcommand;
+	u8                                 reserved01;
+	u8                                 command;
+	u8                                 command_flags;
+};
+struct mpi3_allowed_cmd_nvme {
+	u8                                 reserved00;
+	u8                                 nvme_cmd_flags;
+	u8                                 op_code;
+	u8                                 command_flags;
+};
+#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK     (0x80)
+#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO       (0x00)
+#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN    (0x80)
+#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK        (0x3f)
+#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM         (0x00)
+union mpi3_allowed_cmd {
+	struct mpi3_allowed_cmd_scsi           scsi;
+	struct mpi3_allowed_cmd_ata            ata;
+	struct mpi3_allowed_cmd_nvme           nvme;
+};
+#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED    (0x20)
+#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED      (0x10)
+#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED      (0x08)
+#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED   (0x04)
+#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED      (0x02)
+#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED    (0x01)
+#ifndef MPI3_ALLOWED_CMDS_MAX
+#define MPI3_ALLOWED_CMDS_MAX           (1)
+#endif
+struct mpi3_driver_page0 {
 	struct mpi3_config_page_header         header;
 	__le32                             bsd_options;
 	u8                                 ssu_timeout;
 	__le32                             reserved18;
 };
-#define MPI3_UEFIBSD_PAGEVERSION               (0x00)
+#define MPI3_DRIVER0_PAGEVERSION               (0x00)
-#define MPI3_UEFIBSD_BSDOPTS_REGISTRATION_MASK              (0x00000003)
+#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK              (0x00000003)
-#define MPI3_UEFIBSD_BSDOPTS_REGISTRATION_IOC_AND_DEVS      (0x00000000)
+#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS      (0x00000000)
-#define MPI3_UEFIBSD_BSDOPTS_REGISTRATION_IOC_ONLY          (0x00000001)
+#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY          (0x00000001)
-#define MPI3_UEFIBSD_BSDOPTS_REGISTRATION_NONE              (0x00000002)
+#define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL            (0x00000004)
-#define MPI3_UEFIBSD_BSDOPTS_DIS_HII_CONFIG_UTIL            (0x00000004)
+#define MPI3_DRIVER0_BSDOPTS_EN_ADV_ADAPTER_CONFIG          (0x00000008)
-#define MPI3_UEFIBSD_BSDOPTS_EN_ADV_ADAPTER_CONFIG          (0x00000008)
+struct mpi3_driver_page1 {
+	struct mpi3_config_page_header         header;
+	__le32                             flags;
+	__le32                             reserved0c;
+	__le16                             host_diag_trace_max_size;
+	__le16                             host_diag_trace_min_size;
+	__le16                             host_diag_trace_decrement_size;
+	__le16                             reserved16;
+	__le16                             host_diag_fw_max_size;
+	__le16                             host_diag_fw_min_size;
+	__le16                             host_diag_fw_decrement_size;
+	__le16                             reserved1e;
+	__le16                             host_diag_driver_max_size;
+	__le16                             host_diag_driver_min_size;
+	__le16                             host_diag_driver_decrement_size;
+	__le16                             reserved26;
+};
+#define MPI3_DRIVER1_PAGEVERSION               (0x00)
+#ifndef MPI3_DRIVER2_TRIGGER_MAX
+#define MPI3_DRIVER2_TRIGGER_MAX           (1)
+#endif
+struct mpi3_driver2_trigger_event {
+	u8                                 type;
+	u8                                 flags;
+	u8                                 reserved02;
+	u8                                 event;
+	__le32                             reserved04[3];
+};
+struct mpi3_driver2_trigger_scsi_sense {
+	u8                                 type;
+	u8                                 flags;
+	__le16                             reserved02;
+	u8                                 ascq;
+	u8                                 asc;
+	u8                                 sense_key;
+	u8                                 reserved07;
+	__le32                             reserved08[2];
+};
+#define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL                        (0xff)
+#define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL                         (0xff)
+#define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL                   (0xff)
+struct mpi3_driver2_trigger_reply {
+	u8                                 type;
+	u8                                 flags;
+	__le16                             ioc_status;
+	__le32                             ioc_log_info;
+	__le32                             ioc_log_info_mask;
+	__le32                             reserved0c;
+};
+#define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL                        (0xffff)
+union mpi3_driver2_trigger_element {
+	struct mpi3_driver2_trigger_event             event;
+	struct mpi3_driver2_trigger_scsi_sense        scsi_sense;
+	struct mpi3_driver2_trigger_reply             reply;
+};
+#define MPI3_DRIVER2_TRIGGER_TYPE_EVENT                                       (0x00)
+#define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE                                  (0x01)
+#define MPI3_DRIVER2_TRIGGER_TYPE_REPLY                                       (0x02)
+#define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE                         (0x02)
+#define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE                            (0x01)
+struct mpi3_driver_page2 {
+	struct mpi3_config_page_header         header;
+	__le64                             master_trigger;
+	__le32                             reserved10[3];
+	u8                                 num_triggers;
+	u8                                 reserved1d[3];
+	union mpi3_driver2_trigger_element    trigger[MPI3_DRIVER2_TRIGGER_MAX];
+};
+#define MPI3_DRIVER2_PAGEVERSION               (0x00)
+#define MPI3_DRIVER2_MASTERTRIGGER_DIAG_TRACE_RELEASE                       (0x8000000000000000ULL)
+#define MPI3_DRIVER2_MASTERTRIGGER_DIAG_FW_RELEASE                          (0x4000000000000000ULL)
+#define MPI3_DRIVER2_MASTERTRIGGER_SNAPDUMP                                 (0x2000000000000000ULL)
+#define MPI3_DRIVER2_MASTERTRIGGER_DEVICE_REMOVAL_ENABLED                   (0x0000000000000004ULL)
+#define MPI3_DRIVER2_MASTERTRIGGER_TASK_MANAGEMENT_ENABLED                  (0x0000000000000002ULL)
+struct mpi3_driver_page10 {
+	struct mpi3_config_page_header         header;
+	__le16                             flags;
+	__le16                             reserved0a;
+	u8                                 num_allowed_commands;
+	u8                                 reserved0d[3];
+	union mpi3_allowed_cmd                allowed_command[MPI3_ALLOWED_CMDS_MAX];
+};
+#define MPI3_DRIVER10_PAGEVERSION               (0x00)
+struct mpi3_driver_page20 {
+	struct mpi3_config_page_header         header;
+	__le16                             flags;
+	__le16                             reserved0a;
+	u8                                 num_allowed_commands;
+	u8                                 reserved0d[3];
+	union mpi3_allowed_cmd                allowed_command[MPI3_ALLOWED_CMDS_MAX];
+};
+#define MPI3_DRIVER20_PAGEVERSION               (0x00)
+struct mpi3_driver_page30 {
+	struct mpi3_config_page_header         header;
+	__le16                             flags;
+	__le16                             reserved0a;
+	u8                                 num_allowed_commands;
+	u8                                 reserved0d[3];
+	union mpi3_allowed_cmd                allowed_command[MPI3_ALLOWED_CMDS_MAX];
+};
+#define MPI3_DRIVER30_PAGEVERSION               (0x00)
 union mpi3_security_mac {
 	__le32                             dword[16];
 	__le16                             word[32];
 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID         (0x00)
 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE         (0x01)
 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN        (0x02)
-#define MPI3_SECURITY1_KEY_RECORD_CONSUMER_AUTH_DEV_KEY      (0x03)
+#define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY        (0x03)
 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD     (0x04)
 struct mpi3_security_page1 {
 	struct mpi3_config_page_header         header;
 	struct mpi3_config_page_header         header;
 	__le32                             reserved08;
 	u8                                 num_phys;
-	u8                                 reserved0d[3];
+	u8                                 init_status;
+	__le16                             reserved0e;
 	struct mpi3_sas_io_unit0_phy_data      phy_data[MPI3_SAS_IO_UNIT0_PHY_MAX];
 };
-#define MPI3_SASIOUNIT0_PAGEVERSION                         (0x00)
+#define MPI3_SASIOUNIT0_PAGEVERSION                          (0x00)
-#define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS          (0x08)
+#define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS                 (0x00)
-#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG          (0x01)
+#define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION      (0x01)
-#define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT       (0x40)
+#define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED      (0x02)
-#define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT       (0x20)
+#define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS              (0x04)
-#define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED               (0x08)
+#define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG        (0x05)
+#define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED         (0x06)
+#define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN      (0xf0)
+#define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX      (0xff)
+#define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS           (0x08)
+#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK      (0x03)
+#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1   (0x00)
+#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC   (0x01)
+#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02)
+#define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT        (0x40)
+#define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT        (0x20)
+#define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED                (0x08)
+#define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY                 (0x02)
+#define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY                    (0x01)
 struct mpi3_sas_io_unit1_phy_data {
 	u8                 io_unit_port;
 	u8                 port_flags;
 #define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED     (0x04)
 #define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE   (0x02)
 #define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES   (0x01)
+#ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS
+#define MPI3_SASEXPANDER2_MAX_NUM_PHYS                               (1)
+#endif
+struct mpi3_sasexpander2_phy_element {
+	u8                                 link_change_count;
+	u8                                 reserved01;
+	__le16                             rate_change_count;
+	__le32                             reserved04;
+};
+struct mpi3_sas_expander_page2 {
+	struct mpi3_config_page_header         header;
+	u8                                 num_phys;
+	u8                                 reserved09;
+	__le16                             dev_handle;
+	__le32                             reserved0c;
+	struct mpi3_sasexpander2_phy_element   phy[MPI3_SASEXPANDER2_MAX_NUM_PHYS];
+};
+#define MPI3_SASEXPANDER2_PAGEVERSION                   (0x00)
 struct mpi3_sas_port_page0 {
 	struct mpi3_config_page_header         header;
 	u8                                 port_number;
 #define MPI3_PCIE_NEG_LINK_RATE_8_0                     (0x04)
 #define MPI3_PCIE_NEG_LINK_RATE_16_0                    (0x05)
 #define MPI3_PCIE_NEG_LINK_RATE_32_0                    (0x06)
+#define MPI3_PCIE_ASPM_ENABLE_NONE                      (0x0)
+#define MPI3_PCIE_ASPM_ENABLE_L0S                       (0x1)
+#define MPI3_PCIE_ASPM_ENABLE_L1                        (0x2)
+#define MPI3_PCIE_ASPM_ENABLE_L0S_L1                    (0x3)
+#define MPI3_PCIE_ASPM_SUPPORT_NONE                     (0x0)
+#define MPI3_PCIE_ASPM_SUPPORT_L0S                      (0x1)
+#define MPI3_PCIE_ASPM_SUPPORT_L1                       (0x2)
+#define MPI3_PCIE_ASPM_SUPPORT_L0S_L1                   (0x3)
 struct mpi3_pcie_io_unit0_phy_data {
 	u8         link;
 	u8         link_flags;
 	__le32                             reserved08;
 	u8                                 num_phys;
 	u8                                 init_status;
-	__le16                             reserved0e;
+	u8                                 aspm;
+	u8                                 reserved0f;
 	struct mpi3_pcie_io_unit0_phy_data     phy_data[MPI3_PCIE_IO_UNIT0_PHY_MAX];
 };
 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE       (0x08)
 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START         (0xf0)
 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END           (0xff)
+#define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK            (0xc0)
+#define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT              (6)
+#define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK            (0x30)
+#define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT              (4)
+#define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK           (0x0c)
+#define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT             (2)
+#define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK           (0x03)
+#define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT             (0)
 struct mpi3_pcie_io_unit1_phy_data {
 	u8         link;
 	u8         link_flags;
 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK      (0x00)
 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS                  (0x01)
 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS                  (0x02)
-#define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE               (0x08)
+#define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE                             (0x08)
-#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK                      (0xf0)
+#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK                               (0xf0)
-#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT                     (4)
+#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT                                 (4)
-#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5                       (0x20)
+#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5                                (0x20)
-#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0                       (0x30)
+#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0                                (0x30)
-#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0                       (0x40)
+#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0                                (0x40)
-#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0                      (0x50)
+#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0                               (0x50)
-#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0                      (0x60)
+#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0                               (0x60)
 #ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX
-#define MPI3_PCIE_IO_UNIT1_PHY_MAX          (1)
+#define MPI3_PCIE_IO_UNIT1_PHY_MAX                                           (1)
 #endif
 struct mpi3_pcie_io_unit_page1 {
 	struct mpi3_config_page_header         header;
 	__le32                             reserved0c;
 	u8                                 num_phys;
 	u8                                 reserved11;
-	__le16                             reserved12;
+	u8                                 aspm;
+	u8                                 reserved13;
 	struct mpi3_pcie_io_unit1_phy_data     phy_data[MPI3_PCIE_IO_UNIT1_PHY_MAX];
 };
-#define MPI3_PCIEIOUNIT1_PAGEVERSION                        (0x00)
+#define MPI3_PCIEIOUNIT1_PAGEVERSION                                           (0x00)
+#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE                   (0x80)
+#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE                  (0x40)
+#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK                (0x30)
+#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT               (4)
+#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED  (0x00)
+#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED        (0x10)
+#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED        (0x20)
+#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK                 (0x0f)
+#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5              (0x02)
+#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0              (0x03)
+#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0              (0x04)
+#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0             (0x05)
+#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0             (0x06)
+#define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK                                 (0x0c)
+#define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT                                   (2)
+#define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK                                 (0x03)
+#define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT                                   (0)
 struct mpi3_pcie_io_unit_page2 {
 	struct mpi3_config_page_header         header;
-	__le16                             nv_me_max_queue_depth;
+	__le16                             nvme_max_q_dx1;
-	__le16                             reserved0a;
+	__le16                             nvme_max_q_dx2;
-	u8                                 nv_me_abort_to;
+	u8                                 nvme_abort_to;
 	u8                                 reserved0d;
-	__le16                             reserved0e;
+	__le16                             nvme_max_q_dx4;
 };
 #define MPI3_PCIEIOUNIT2_PAGEVERSION                        (0x00)
+#define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR               (0)
+#define MPI3_PCIEIOUNIT3_ERROR_RECOVERY                     (1)
+#define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG        (2)
+#define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP                     (3)
+#define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP                      (4)
+#define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX                    (5)
+struct mpi3_pcie_io_unit3_error {
+	__le16                             threshold_count;
+	__le16                             reserved02;
+};
+struct mpi3_pcie_io_unit_page3 {
+	struct mpi3_config_page_header         header;
+	u8                                 threshold_window;
+	u8                                 threshold_action;
+	u8                                 escalation_count;
+	u8                                 escalation_action;
+	u8                                 num_errors;
+	u8                                 reserved0d[3];
+	struct mpi3_pcie_io_unit3_error        error[MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX];
+};
+#define MPI3_PCIEIOUNIT3_PAGEVERSION                        (0x00)
+#define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION                   (0x00)
+#define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET                   (0x01)
+#define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY       (0x02)
+#define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS  (0x03)
 struct mpi3_pcie_switch_page0 {
 	struct mpi3_config_page_header     header;
 	u8                             io_unit_port;
 	__le16                         dev_handle;
 	__le16                         parent_dev_handle;
 	u8                             num_ports;
-	u8                             pc_ie_level;
+	u8                             pcie_level;
 	__le16                         reserved12;
 	__le32                         reserved14;
 	__le32                         reserved18;
 struct mpi3_pcie_switch_page1 {
 	struct mpi3_config_page_header     header;
 	u8                             io_unit_port;
-	u8                             reserved09[3];
+	u8                             flags;
+	__le16                         reserved0a;
 	u8                             num_ports;
 	u8                             port_num;
 	__le16                         attached_dev_handle;
 };
 #define MPI3_PCIESWITCH1_PAGEVERSION        (0x00)
+#define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK     (0x0c)
+#define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT    (2)
+#define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK     (0x03)
+#define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT    (0)
+#ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS
+#define MPI3_PCIESWITCH2_MAX_NUM_PORTS                               (1)
+#endif
+struct mpi3_pcieswitch2_port_element {
+	__le16                             link_change_count;
+	__le16                             rate_change_count;
+	__le32                             reserved04;
+};
+struct mpi3_pcie_switch_page2 {
+	struct mpi3_config_page_header         header;
+	u8                                 num_ports;
+	u8                                 reserved09;
+	__le16                             dev_handle;
+	__le32                             reserved0c;
+	struct mpi3_pcieswitch2_port_element   port[MPI3_PCIESWITCH2_MAX_NUM_PORTS];
+};
+#define MPI3_PCIESWITCH2_PAGEVERSION        (0x00)
 struct mpi3_pcie_link_page0 {
 	struct mpi3_config_page_header     header;
 	u8                             link;
 	u8                             reserved09[3];
-	__le32                         correctable_error_count;
+	__le32                         reserved0c;
-	__le16                         n_fatal_error_count;
+	__le32                         receiver_error_count;
-	__le16                         reserved12;
+	__le32                         recovery_count;
-	__le16                         fatal_error_count;
+	__le32                         corr_error_msg_count;
-	__le16                         reserved16;
+	__le32                         non_fatal_error_msg_count;
+	__le32                         fatal_error_msg_count;
+	__le32                         non_fatal_error_count;
+	__le32                         fatal_error_count;
+	__le32                         bad_dllp_count;
+	__le32                         bad_tlp_count;
 };
 #define MPI3_PCIELINK0_PAGEVERSION          (0x00)
 	__le16                             flags;
 	__le16                             enclosure_handle;
 	__le16                             num_slots;
-	__le16                             start_slot;
+	__le16                             reserved16;
 	u8                                 io_unit_port;
 	u8                                 enclosure_level;
 	__le16                             sep_dev_handle;
-	__le32                             reserved1c;
+	u8                                 chassis_slot;
+	u8                                 reserved1d[3];
 };
 #define MPI3_ENCLOSURE0_PAGEVERSION                     (0x00)
 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL             (0x0000)
 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS                 (0x4000)
 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE                (0x8000)
+#define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID            (0x0020)
 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK         (0x0010)
 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND            (0x0000)
 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT              (0x0010)
 	u8         zone_group;
 };
+#define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ (0x0400)
 #define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP          (0x0200)
 #define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP          (0x0100)
 #define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY         (0x0080)
 	__le32     maximum_data_transfer_size;
 	__le32     capabilities;
 	__le16     noiob;
-	u8         nv_me_abort_to;
+	u8         nvme_abort_to;
 	u8         page_size;
 	__le16     shutdown_latency;
-	__le16     reserved16;
+	u8         recovery_info;
+	u8         reserved17;
 };
 #define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP           (0x10)
 #define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP            (0x04)
 #define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP            (0x02)
 #define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP            (0x01)
-#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK             (0x0003)
+#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK             (0x0007)
 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE        (0x0000)
 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE      (0x0001)
 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE    (0x0002)
 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE      (0x0003)
+#define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK             (0x0030)
+#define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT            (4)
+#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK           (0x00c0)
+#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT          (6)
+#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0              (0x0000)
+#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1              (0x0040)
+#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2              (0x0080)
+#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3              (0x00c0)
+#define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED    (0x00000020)
 #define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED            (0x00000010)
 #define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED      (0x00000008)
-#define MPI3_DEVICE0_PCIE_CAP_NVME_SGL_ENABLED              (0x00000004)
+#define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL                (0x00000004)
+#define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP                (0x00000000)
 #define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP           (0x00000002)
 #define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP                      (0x00000001)
+#define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK                     (0x000000c0)
+#define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT                    (6)
+#define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK               (0xe0)
+#define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT            (0x00)
+#define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT             (0x20)
+#define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK               (0x1f)
+#define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS              (0x00)
+#define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1          (0x01)
+#define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS        (0x02)
+#define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION         (0x03)
+#define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ        (0x04)
+#define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ        (0x05)
 struct mpi3_device0_vd_format {
 	u8         vd_state;
 	u8         raid_level;
 };
 #define MPI3_DEVICE0_PAGEVERSION                        (0x00)
+#define MPI3_DEVICE0_PARENT_INVALID                     (0xffff)
+#define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE      (0x0000)
 #define MPI3_DEVICE0_WWID_INVALID                       (0xffffffffffffffff)
 #define MPI3_DEVICE0_PERSISTENTID_INVALID               (0xffff)
 #define MPI3_DEVICE0_IOUNITPORT_INVALID                 (0xff)
 #define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED                         (0x03)
 #define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED                           (0x04)
 #define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY                   (0x05)
+#define MPI3_DEVICE0_ASTATUS_PREPARE                                (0x06)
+#define MPI3_DEVICE0_ASTATUS_SAFE_MODE                              (0x07)
+#define MPI3_DEVICE0_ASTATUS_GENERIC_MAX                            (0x0f)
 #define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN                            (0x10)
 #define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE                  (0x11)
 #define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE              (0x12)
+#define MPI3_DEVICE0_ASTATUS_SAS_MAX                                (0x1f)
 #define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN                            (0x20)
 #define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT               (0x21)
 #define MPI3_DEVICE0_ASTATUS_SIF_DIAG                               (0x22)
 #define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS                  (0x31)
 #define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED                       (0x32)
 #define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED                     (0x33)
+#define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED                     (0x34)
+#define MPI3_DEVICE0_ASTATUS_PCIE_MAX                               (0x3f)
 #define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN                           (0x40)
 #define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT                     (0x41)
 #define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED                (0x42)
 #define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED           (0x47)
 #define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT                      (0x48)
 #define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS               (0x49)
-#define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN                             (0x50)
+#define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER                (0x4a)
+#define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE                   (0x4b)
+#define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE                 (0x4c)
+#define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION                 (0x4d)
+#define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME                   (0x4e)
+#define MPI3_DEVICE0_ASTATUS_NVME_BAR                               (0x4f)
+#define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR                     (0x50)
+#define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS             (0x51)
+#define MPI3_DEVICE0_ASTATUS_NVME_MAX                               (0x5f)
+#define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN                             (0x80)
+#define MPI3_DEVICE0_ASTATUS_VD_MAX                                 (0x8f)
 #define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE        (0x0080)
 #define MPI3_DEVICE0_FLAGS_HIDDEN                       (0x0008)
 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_MASK              (0x0006)
 	struct mpi3_config_page_header         header;
 	__le16                             dev_handle;
 	__le16                             reserved0a;
-	__le32                             reserved0c[12];
+	__le16                             link_change_count;
+	__le16                             rate_change_count;
+	__le16                             tm_count;
+	__le16                             reserved12;
+	__le32                             reserved14[10];
 	u8                                 reserved3c[3];
 	u8                                 device_form;
 	union mpi3_device1_dev_spec_format    device_specific;
 };
 #define MPI3_DEVICE1_PAGEVERSION                            (0x00)
+#define MPI3_DEVICE1_COUNTER_MAX                            (0xfffe)
+#define MPI3_DEVICE1_COUNTER_INVALID                        (0xffff)
 #endif

drivers/scsi/mpi3mr/mpi/mpi30_image.h+58−1

@@ -61,6 +61,8 @@ struct mpi3_component_image_header { · 60 unmodified lines
61	#define MPI3_IMAGE_HEADER_SIGNATURE1_SPD (0x20445053)	61	#define MPI3_IMAGE_HEADER_SIGNATURE1_SPD (0x20445053)
62	#define MPI3_IMAGE_HEADER_SIGNATURE1_GAS_GAUGE (0x20534147)	62	#define MPI3_IMAGE_HEADER_SIGNATURE1_GAS_GAUGE (0x20534147)
63	#define MPI3_IMAGE_HEADER_SIGNATURE1_PBLP (0x504c4250)	63	#define MPI3_IMAGE_HEADER_SIGNATURE1_PBLP (0x504c4250)
		64	#define MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST (0x464e414d)
		65	#define MPI3_IMAGE_HEADER_SIGNATURE1_OEM (0x204d454f)
64	#define MPI3_IMAGE_HEADER_SIGNATURE2_VALUE (0x50584546)	66	#define MPI3_IMAGE_HEADER_SIGNATURE2_VALUE (0x50584546)
65	#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_MASK (0x00000030)	67	#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_MASK (0x00000030)
66	#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_CDI (0x00000000)	68	#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_CDI (0x00000000)
@@ -94,6 +96,61 @@ struct mpi3_component_image_header { · 27 unmodified lines
94	#define MPI3_IMAGE_HEADER_HASH_EXCLUSION_OFFSET (0x5c)	96	#define MPI3_IMAGE_HEADER_HASH_EXCLUSION_OFFSET (0x5c)
95	#define MPI3_IMAGE_HEADER_NEXT_IMAGE_HEADER_OFFSET_OFFSET (0x7c)	97	#define MPI3_IMAGE_HEADER_NEXT_IMAGE_HEADER_OFFSET_OFFSET (0x7c)
96	#define MPI3_IMAGE_HEADER_SIZE (0x100)	98	#define MPI3_IMAGE_HEADER_SIZE (0x100)
		99	#ifndef MPI3_CI_MANIFEST_MPI_MAX
		100	#define MPI3_CI_MANIFEST_MPI_MAX (1)
		101	#endif
		102	struct mpi3_ci_manifest_mpi_comp_image_ref {
		103	__le32 signature1;
		104	__le32 reserved04[3];
		105	struct mpi3_comp_image_version component_image_version;
		106	__le32 component_image_version_string_offset;
		107	__le32 crc;
		108	};
		109
		110	struct mpi3_ci_manifest_mpi {
		111	u8 manifest_type;
		112	u8 reserved01[3];
		113	__le32 reserved04[3];
		114	u8 num_image_references;
		115	u8 release_level;
		116	__le16 reserved12;
		117	__le16 reserved14;
		118	__le16 flags;
		119	__le32 reserved18[2];
		120	__le16 vendor_id;
		121	__le16 device_id;
		122	__le16 subsystem_vendor_id;
		123	__le16 subsystem_id;
		124	__le32 reserved28[2];
		125	union mpi3_version_union package_security_version;
		126	__le32 reserved34;
		127	struct mpi3_comp_image_version package_version;
		128	__le32 package_version_string_offset;
		129	__le32 package_build_date_string_offset;
		130	__le32 package_build_time_string_offset;
		131	__le32 reserved4c;
		132	__le32 diag_authorization_identifier[16];
		133	struct mpi3_ci_manifest_mpi_comp_image_ref component_image_ref[MPI3_CI_MANIFEST_MPI_MAX];
		134	};
		135
		136	#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_DEV (0x00)
		137	#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_PREALPHA (0x10)
		138	#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_ALPHA (0x20)
		139	#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_BETA (0x30)
		140	#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_RC (0x40)
		141	#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_GCA (0x50)
		142	#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_POINT (0x60)
		143	#define MPI3_CI_MANIFEST_MPI_FLAGS_DIAG_AUTHORIZATION (0x01)
		144	#define MPI3_CI_MANIFEST_MPI_SUBSYSTEMID_IGNORED (0xffff)
		145	#define MPI3_CI_MANIFEST_MPI_PKG_VER_STR_OFF_UNSPECIFIED (0x00000000)
		146	#define MPI3_CI_MANIFEST_MPI_PKG_BUILD_DATE_STR_OFF_UNSPECIFIED (0x00000000)
		147	#define MPI3_CI_MANIFEST_MPI_PKG_BUILD_TIME_STR_OFF_UNSPECIFIED (0x00000000)
		148	union mpi3_ci_manifest {
		149	struct mpi3_ci_manifest_mpi mpi;
		150	__le32 dword[1];
		151	};
		152
		153	#define MPI3_CI_MANIFEST_TYPE_MPI (0x00)
97	struct mpi3_extended_image_header {	154	struct mpi3_extended_image_header {
98	u8 image_type;	155	u8 image_type;
99	u8 reserved01[3];	156	u8 reserved01[3];
@@ -161,6 +218,7 @@ struct mpi3_encrypted_hash_entry { · 61 unmodified lines
161	#define MPI3_HASH_ALGORITHM_SIZE_UNUSED (0x00)	218	#define MPI3_HASH_ALGORITHM_SIZE_UNUSED (0x00)
162	#define MPI3_HASH_ALGORITHM_SIZE_SHA256 (0x01)	219	#define MPI3_HASH_ALGORITHM_SIZE_SHA256 (0x01)
163	#define MPI3_HASH_ALGORITHM_SIZE_SHA512 (0x02)	220	#define MPI3_HASH_ALGORITHM_SIZE_SHA512 (0x02)
		221	#define MPI3_HASH_ALGORITHM_SIZE_SHA384 (0x03)
164	#define MPI3_ENCRYPTION_ALGORITHM_UNUSED (0x00)	222	#define MPI3_ENCRYPTION_ALGORITHM_UNUSED (0x00)
165	#define MPI3_ENCRYPTION_ALGORITHM_RSA256 (0x01)	223	#define MPI3_ENCRYPTION_ALGORITHM_RSA256 (0x01)
166	#define MPI3_ENCRYPTION_ALGORITHM_RSA512 (0x02)	224	#define MPI3_ENCRYPTION_ALGORITHM_RSA512 (0x02)
@@ -178,7 +236,6 @@ struct mpi3_encrypted_key_with_hash_entry { · 11 unmodified lines
178	u8 reserved03;	236	u8 reserved03;
179	__le32 reserved04;	237	__le32 reserved04;
180	__le32 public_key[MPI3_PUBLIC_KEY_MAX];	238	__le32 public_key[MPI3_PUBLIC_KEY_MAX];
181	__le32 encrypted_hash[MPI3_ENCRYPTED_HASH_MAX];
182	};	239	};
183		240
184	#ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX	241	#ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX

drivers/scsi/mpi3mr/mpi/mpi30_init.h+12−3

 	__le32             transfer_length;
 };
-union mpi3_scso_io_cdb_union {
+union mpi3_scsi_io_cdb_union {
 	u8                         cdb32[32];
 	struct mpi3_scsi_io_cdb_eedp32 eedp32;
 	struct mpi3_sge_common         sge;
 	__le32                     skip_count;
 	__le32                     data_length;
 	u8                         lun[8];
-	union mpi3_scso_io_cdb_union  cdb;
+	union mpi3_scsi_io_cdb_union  cdb;
 	union mpi3_sge_union          sgl[4];
 };
 #define MPI3_SCSIIO_MSGFLAGS_METASGL_VALID                  (0x80)
+#define MPI3_SCSIIO_MSGFLAGS_DIVERT_TO_FIRMWARE             (0x40)
 #define MPI3_SCSIIO_FLAGS_LARGE_CDB                         (0x60000000)
 #define MPI3_SCSIIO_FLAGS_CDB_16_OR_LESS                    (0x00000000)
 #define MPI3_SCSIIO_FLAGS_CDB_GREATER_THAN_16               (0x20000000)
 	__le32                     reserved18;
 };
-#define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC      (0x80)
+#define MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE                (0x00)
+#define MPI3_SCSITASKMGMT_RSPCODE_INVALID_FRAME              (0x02)
+#define MPI3_SCSITASKMGMT_RSPCODE_TM_FUNCTION_NOT_SUPPORTED  (0x04)
+#define MPI3_SCSITASKMGMT_RSPCODE_TM_FAILED                  (0x05)
+#define MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED               (0x08)
+#define MPI3_SCSITASKMGMT_RSPCODE_TM_INVALID_LUN             (0x09)
+#define MPI3_SCSITASKMGMT_RSPCODE_TM_OVERLAPPED_TAG          (0x0a)
+#define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC           (0x80)
+#define MPI3_SCSITASKMGMT_RSPCODE_TM_NVME_DENIED             (0x81)
 #endif

drivers/scsi/mpi3mr/mpi/mpi30_ioc.h+99−29

 	__le64                   driver_information_address;
 };
-#define MPI3_WHOINIT_NOT_INITIALIZED            (0x00)
+#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK          (0x03)
-#define MPI3_WHOINIT_ROM_BIOS                   (0x02)
+#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED      (0x00)
-#define MPI3_WHOINIT_HOST_DRIVER                (0x03)
+#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED     (0x01)
-#define MPI3_WHOINIT_MANUFACTURER               (0x04)
+#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE        (0x02)
+#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH          (0x03)
+#define MPI3_WHOINIT_NOT_INITIALIZED                     (0x00)
+#define MPI3_WHOINIT_ROM_BIOS                            (0x02)
+#define MPI3_WHOINIT_HOST_DRIVER                         (0x03)
+#define MPI3_WHOINIT_MANUFACTURER                        (0x04)
 struct mpi3_driver_info_layout {
 	__le32             information_length;
 	u8                 driver_signature[12];
 	u8                         sge_modifier_shift;
 	u8                         protocol_flags;
 	__le16                     max_sas_initiators;
-	__le16                     max_sas_targets;
+	__le16                     reserved2a;
 	__le16                     max_sas_expanders;
 	__le16                     max_enclosures;
 	__le16                     min_dev_handle;
 	__le16                     max_dev_handle;
-	__le16                     max_pc_ie_switches;
+	__le16                     max_pcie_switches;
 	__le16                     max_nvme;
-	__le16                     max_pds;
+	__le16                     reserved38;
 	__le16                     max_vds;
 	__le16                     max_host_pds;
-	__le16                     max_advanced_host_pds;
+	__le16                     max_adv_host_pds;
 	__le16                     max_raid_pds;
 	__le16                     max_posted_cmd_buffers;
 	__le32                     flags;
 	__le16                     reserved4e;
 	__le32                     diag_trace_size;
 	__le32                     diag_fw_size;
+	__le32                     diag_driver_size;
+	u8                         max_host_pd_ns_count;
+	u8                         max_adv_host_pd_ns_count;
+	u8                         max_raidpd_ns_count;
+	u8                         reserved5f;
 };
-#define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD             (0x00000010)
+#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK          (0x80000000)
+#define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC               (0x00000000)
+#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC           (0x10000000)
+#define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_CAPABLE       (0x00000100)
+#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_ENABLED       (0x00000080)
+#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_ENABLED          (0x00000040)
+#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_ENABLED      (0x00000020)
+#define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_ENABLED     (0x00000010)
 #define MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE                 (0x00000008)
-#define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_GRAN_MASK      (0x00000001)
+#define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED            (0x00000002)
-#define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_IOC_GRAN       (0x00000000)
+#define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED      (0x00000001)
-#define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_REPLY_Q_GRAN   (0x00000001)
 #define MPI3_IOCFACTS_PID_TYPE_MASK                           (0xf000)
 #define MPI3_IOCFACTS_PID_TYPE_SHIFT                          (12)
 #define MPI3_IOCFACTS_PID_PRODUCT_MASK                        (0x0f00)
 #define MPI3_IOCFACTS_PID_PRODUCT_SHIFT                       (8)
 #define MPI3_IOCFACTS_PID_FAMILY_MASK                         (0x00ff)
 #define MPI3_IOCFACTS_PID_FAMILY_SHIFT                        (0)
+#define MPI3_IOCFACTS_EXCEPT_SECURITY_REKEY                   (0x2000)
+#define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED                     (0x1000)
 #define MPI3_IOCFACTS_EXCEPT_SAFE_MODE                        (0x0800)
 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK                (0x0700)
 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE                (0x0000)
-#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_RAID      (0x0100)
+#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT      (0x0100)
-#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB       (0x0200)
+#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT        (0x0200)
-#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_RAID        (0x0300)
+#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_MGMT  (0x0300)
-#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB         (0x0400)
+#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB       (0x0400)
+#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB         (0x0500)
+#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_OOB   (0x0600)
 #define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED                    (0x0080)
 #define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE           (0x0040)
 #define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL           (0x0020)
 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK          (0x80)
 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED     (0x80)
 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS    (0x00)
+#define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM                  (2)
 struct mpi3_delete_request_queue_request {
 	__le16             host_tag;
 	u8                 ioc_use_only02;
 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK           (0x01)
 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE        (0x00)
 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE         (0x01)
+#define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM                    (2)
 struct mpi3_delete_reply_queue_request {
 	__le16             host_tag;
 	u8                 ioc_use_only02;
 #define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR       (0x19)
 #define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST        (0x20)
 #define MPI3_EVENT_PCIE_ENUMERATION                 (0x22)
+#define MPI3_EVENT_PCIE_ERROR_THRESHOLD             (0x23)
 #define MPI3_EVENT_HARD_RESET_RECEIVED              (0x40)
+#define MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE  (0x50)
 #define MPI3_EVENT_MIN_PRODUCT_SPECIFIC             (0x60)
 #define MPI3_EVENT_MAX_PRODUCT_SPECIFIC             (0x7f)
 #define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
 	__le32             reserved0c;
 };
-#define MPI3_EVENT_TEMP_THRESHOLD_STATUS_THRESHOLD3_EXCEEDED         (0x0008)
+#define MPI3_EVENT_TEMP_THRESHOLD_STATUS_FATAL_THRESHOLD_EXCEEDED     (0x0004)
-#define MPI3_EVENT_TEMP_THRESHOLD_STATUS_THRESHOLD2_EXCEEDED         (0x0004)
+#define MPI3_EVENT_TEMP_THRESHOLD_STATUS_CRITICAL_THRESHOLD_EXCEEDED  (0x0002)
-#define MPI3_EVENT_TEMP_THRESHOLD_STATUS_THRESHOLD1_EXCEEDED         (0x0002)
+#define MPI3_EVENT_TEMP_THRESHOLD_STATUS_WARNING_THRESHOLD_EXCEEDED   (0x0001)
-#define MPI3_EVENT_TEMP_THRESHOLD_STATUS_THRESHOLD0_EXCEEDED         (0x0001)
 struct mpi3_event_data_cable_management {
 	__le32             active_cable_power_requirement;
 	u8                 status;
 #define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED             (0x40000000)
 #define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED               (0x20000000)
 #define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
+#define MPI3_SAS_DISC_STATUS_INVALID_CEI                      (0x00010000)
+#define MPI3_SAS_DISC_STATUS_FECEI_MISMATCH                   (0x00008000)
 #define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT         (0x00004000)
-#define MPI3_SAS_DISC_STATUS_SLOT_COUNT_MISMATCH              (0x00002000)
+#define MPI3_SAS_DISC_STATUS_NECEI_MISMATCH                   (0x00002000)
 #define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS                   (0x00001000)
 #define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE            (0x00000800)
 #define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN                (0x00000400)
 #define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING          (0x02)
 #define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING              (0x03)
 #define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING    (0x04)
+struct mpi3_event_data_pcie_error_threshold {
+	__le64                                 timestamp;
+	u8                                     reason_code;
+	u8                                     port;
+	__le16                                 switch_dev_handle;
+	u8                                     error;
+	u8                                     action;
+	__le16                                 threshold_count;
+	__le16                                 attached_dev_handle;
+	__le16                                 reserved12;
+};
+#define MPI3_EVENT_PCI_ERROR_RC_THRESHOLD_EXCEEDED          (0x00)
+#define MPI3_EVENT_PCI_ERROR_RC_ESCALATION                  (0x01)
 struct mpi3_event_data_sas_init_dev_status_change {
 	u8                 reason_code;
 	u8                 io_unit_port;
 	__le16             reserved02;
 };
+struct mpi3_event_data_diag_buffer_status_change {
+	u8                 type;
+	u8                 reason_code;
+	__le16             reserved02;
+	__le32             reserved04;
+};
+#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED             (0x01)
+#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED               (0x02)
+#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED              (0x03)
 #define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT   (0x0200)
 #define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT       (0x0100)
 #define MPI3_PEL_LOCALE_FLAGS_PCIE                      (0x0080)
 };
 struct mpi3_pel_entry {
+	__le64                             time_stamp;
 	__le32                             sequence_number;
-	__le32                             time_stamp[2];
 	__le16                             log_code;
 	__le16                             arg_type;
 	__le16                             locale;
 	u8                                 class;
-	u8                                 reserved13;
+	u8                                 flags;
 	u8                                 ext_num;
 	u8                                 num_exts;
 	u8                                 arg_data_size;
-	u8                                 fixed_format_size;
+	u8                                 fixed_format_strings_size;
 	__le32                             reserved18[2];
 	__le32                             pel_info[24];
 };
+#define MPI3_PEL_FLAGS_COMPLETE_RESET_NEEDED                  (0x02)
+#define MPI3_PEL_FLAGS_ACK_NEEDED                             (0x01)
 struct mpi3_pel_list {
 	__le32                             log_count;
 	__le32                             reserved04;
 	__le32                             reserved10;
 };
-#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT            (0x01)
+#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK                     (0x03)
+#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE              (0x00)
+#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP              (0x01)
+#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT      (0x02)
 struct mpi3_pel_reply {
 	__le16                             host_tag;
 	u8                                 ioc_use_only02;
 #define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION              (0x02)
 #define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION             (0x03)
 #define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS                     (0x04)
+#define MPI3_CI_DOWNLOAD_ACTION_CANCEL_OFFLINE_ACTIVATION      (0x05)
 struct mpi3_ci_download_reply {
 	__le16                             host_tag;
 	u8                                 ioc_use_only02;
 };
 #define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS                  (0x80)
+#define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED           (0x20)
 #define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING                    (0x10)
 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK                (0x0e)
 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED          (0x00)
 #define MPI3_CTRL_OP_REMOVE_DEVICE                                   (0x10)
 #define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION                     (0x11)
 #define MPI3_CTRL_OP_HIDDEN_ACK                                      (0x12)
+#define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS                           (0x13)
 #define MPI3_CTRL_OP_SAS_SEND_PRIMITIVE                              (0x20)
-#define MPI3_CTRL_OP_SAS_CLEAR_ERROR_LOG                             (0x21)
+#define MPI3_CTRL_OP_SAS_PHY_CONTROL                                 (0x21)
-#define MPI3_CTRL_OP_PCIE_CLEAR_ERROR_LOG                            (0x22)
+#define MPI3_CTRL_OP_READ_INTERNAL_BUS                               (0x23)
+#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS                              (0x24)
+#define MPI3_CTRL_OP_PCIE_LINK_CONTROL                               (0x30)
 #define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX       (0x00)
 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX        (0x00)
 #define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX           (0x00)
 #define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX      (0x00)
 #define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX              (0x00)
+#define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS_PARAM16_DEVHANDLE_INDEX   (0x00)
 #define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM8_PHY_INDEX                  (0x00)
 #define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM8_PRIMSEQ_INDEX              (0x01)
 #define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM32_PRIMITIVE_INDEX           (0x00)
-#define MPI3_CTRL_OP_SAS_CLEAR_ERR_LOG_PARAM8_PHY_INDEX              (0x00)
+#define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_ACTION_INDEX             (0x00)
-#define MPI3_CTRL_OP_PCIE_CLEAR_ERR_LOG_PARAM8_PHY_INDEX             (0x00)
+#define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_PHY_INDEX                (0x01)
+#define MPI3_CTRL_OP_READ_INTERNAL_BUS_PARAM64_ADDRESS_INDEX         (0x00)
+#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM64_ADDRESS_INDEX        (0x00)
+#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM32_VALUE_INDEX          (0x00)
+#define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_ACTION_INDEX           (0x00)
+#define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_LINK_INDEX             (0x01)
 #define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS                         (0x01)
 #define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT                       (0x02)
 #define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME                      (0x03)
 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX   (1)
 #define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX                      (0)
 #define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX                 (0)
+#define MPI3_CTRL_READ_INTERNAL_BUS_VALUE32_VALUE_INDEX                 (0)
 #define MPI3_CTRL_PRIMFLAGS_SINGLE                                   (0x01)
 #define MPI3_CTRL_PRIMFLAGS_TRIPLE                                   (0x03)
 #define MPI3_CTRL_PRIMFLAGS_REDUNDANT                                (0x06)
+#define MPI3_CTRL_ACTION_NOP                                         (0x00)
+#define MPI3_CTRL_ACTION_LINK_RESET                                  (0x01)
+#define MPI3_CTRL_ACTION_HARD_RESET                                  (0x02)
+#define MPI3_CTRL_ACTION_CLEAR_ERROR_LOG                             (0x05)
 struct mpi3_iounit_control_request {
 	__le16                             host_tag;
 	u8                                 ioc_use_only02;

drivers/scsi/mpi3mr/mpi/mpi30_pci.h+44−0

@@ -0,0 +1,44 @@
	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
	2	/*
	3	* Copyright 2016-2021 Broadcom Inc. All rights reserved.
	4	*
	5	*/
	6	#ifndef MPI30_PCI_H
	7	#define MPI30_PCI_H 1
	8	#ifndef MPI3_NVME_ENCAP_CMD_MAX
	9	#define MPI3_NVME_ENCAP_CMD_MAX (1)
	10	#endif
	11	struct mpi3_nvme_encapsulated_request {
	12	__le16 host_tag;
	13	u8 ioc_use_only02;
	14	u8 function;
	15	__le16 ioc_use_only04;
	16	u8 ioc_use_only06;
	17	u8 msg_flags;
	18	__le16 change_count;
	19	__le16 dev_handle;
	20	__le16 encapsulated_command_length;
	21	__le16 flags;
	22	__le32 reserved10[4];
	23	__le32 command[MPI3_NVME_ENCAP_CMD_MAX];
	24	};
	25
	26	#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_MASK (0x0002)
	27	#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_FAIL_ONLY (0x0000)
	28	#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_ALL (0x0002)
	29	#define MPI3_NVME_FLAGS_SUBMISSIONQ_MASK (0x0001)
	30	#define MPI3_NVME_FLAGS_SUBMISSIONQ_IO (0x0000)
	31	#define MPI3_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0001)
	32	struct mpi3_nvme_encapsulated_error_reply {
	33	__le16 host_tag;
	34	u8 ioc_use_only02;
	35	u8 function;
	36	__le16 ioc_use_only04;
	37	u8 ioc_use_only06;
	38	u8 msg_flags;
	39	__le16 ioc_use_only08;
	40	__le16 ioc_status;
	41	__le32 ioc_log_info;
	42	__le32 nvme_completion_entry[4];
	43	};
	44	#endif

drivers/scsi/mpi3mr/mpi/mpi30_sas.h+14−0

@@ -30,4 +30,18 @@ struct mpi3_smp_passthrough_request { · 29 unmodified lines
30	struct mpi3_sge_common request_sge;	30	struct mpi3_sge_common request_sge;
31	struct mpi3_sge_common response_sge;	31	struct mpi3_sge_common response_sge;
32	};	32	};
		33
		34	struct mpi3_smp_passthrough_reply {
		35	__le16 host_tag;
		36	u8 ioc_use_only02;
		37	u8 function;
		38	__le16 ioc_use_only04;
		39	u8 ioc_use_only06;
		40	u8 msg_flags;
		41	__le16 ioc_use_only08;
		42	__le16 ioc_status;
		43	__le32 ioc_log_info;
		44	__le16 response_data_length;
		45	__le16 reserved12;
		46	};
33	#endif	47	#endif

drivers/scsi/mpi3mr/mpi/mpi30_transport.h+19−12

 #define MPI3_VERSION_MAJOR                                              (3)
 #define MPI3_VERSION_MINOR                                              (0)
-#define MPI3_VERSION_UNIT                                               (0)
+#define MPI3_VERSION_UNIT                                               (22)
-#define MPI3_VERSION_DEV                                                (18)
+#define MPI3_VERSION_DEV                                                (0)
 struct mpi3_sysif_oper_queue_indexes {
 	__le16         producer_index;
 	__le16         reserved02;
 #define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET                                 (0x00000004)
 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK                            (0xff000000)
 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT                           (24)
+#define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED                            (0x00000001)
 #define MPI3_SYSIF_IOC_CONFIG_OFFSET                                    (0x00000014)
 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ                           (0x00f00000)
 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT                     (20)
 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK                             (0x0000c000)
 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO                               (0x00000000)
 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL                           (0x00004000)
-#define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN                           (0x00002000)
+#define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ                  (0x00002000)
 #define MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE                                 (0x00000010)
 #define MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC                                (0x00000001)
 #define MPI3_SYSIF_IOC_STATUS_OFFSET                                    (0x0000001c)
 #define MPI3_SYSIF_IOC_STATUS_RESET_HISTORY                             (0x00000010)
 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK                             (0x0000000c)
+#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_SHIFT                            (0x00000002)
 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_NONE                             (0x00000000)
 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS                      (0x00000004)
 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE                         (0x00000008)
 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE                    (0x00000000)
 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE                      (0x40000000)
 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE                       (0xc0000000)
-#define MPI3_SYSIF_COALESCE_CONTROL_VALID                               (0x30000000)
+#define MPI3_SYSIF_COALESCE_CONTROL_VALID                               (0x20000000)
-#define MPI3_SYSIF_COALESCE_CONTROL_QUEUE_ID_MASK                       (0x00ff0000)
+#define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_MASK                       (0x01ff0000)
-#define MPI3_SYSIF_COALESCE_CONTROL_QUEUE_ID_SHIFT                      (16)
+#define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_SHIFT                      (16)
 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_MASK                        (0x0000ff00)
 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_SHIFT                       (8)
 #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_MASK                          (0x000000ff)
 #define MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET                                (0x00001000)
 #define MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET                              (0x00001004)
 #define MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET                                 (0x00001008)
-#define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(n)                            (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((n) - 1) * 8))
+#define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(N)                            (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((N) - 1) * 8))
 #define MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET                               (0x0000100c)
-#define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(n)                          (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((n) - 1) * 8))
+#define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(N)                          (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((N) - 1) * 8))
 #define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET                                (0x00001c04)
 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK                        (0x0000000f)
 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH                       (0x0)
 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK                          (0x00000700)
 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET                      (0x00000000)
 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET                    (0x00000100)
-#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_FLASH_RCVRY_RESET             (0x00000200)
+#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_HOST_CONTROL_BOOT_RESET       (0x00000200)
 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_COMPLETE_RESET                (0x00000300)
 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT                    (0x00000700)
 #define MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS                           (0x00000080)
 #define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET                       (0x0000f001)
 #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS                    (0x0000f002)
 #define MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED                     (0x0000f003)
-#define MPI3_SYSIF_FAULT_CODE_SAFE_MODE_EXIT                            (0x0000f004)
+#define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_NEEDED                         (0x0000f004)
-#define MPI3_SYSIF_FAULT_CODE_FACTORY_RESET                             (0x0000f005)
+#define MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED                      (0x0000f005)
+#define MPI3_SYSIF_FAULT_CODE_TEMP_THRESHOLD_EXCEEDED                   (0x0000f006)
 #define MPI3_SYSIF_FAULT_INFO0_OFFSET                                   (0x00001c14)
 #define MPI3_SYSIF_FAULT_INFO1_OFFSET                                   (0x00001c18)
 #define MPI3_SYSIF_FAULT_INFO2_OFFSET                                   (0x00001c1c)
 #define MPI3_IOCSTATUS_INVALID_STATE                (0x0008)
 #define MPI3_IOCSTATUS_INSUFFICIENT_POWER           (0x000a)
 #define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT         (0x000b)
+#define MPI3_IOCSTATUS_ALLOWED_CMD_BLOCK            (0x000c)
+#define MPI3_IOCSTATUS_SUPERVISOR_ONLY              (0x000d)
 #define MPI3_IOCSTATUS_FAILURE                      (0x001f)
 #define MPI3_IOCSTATUS_CONFIG_INVALID_ACTION        (0x0020)
 #define MPI3_IOCSTATUS_CONFIG_INVALID_TYPE          (0x0021)
 #define MPI3_IOCSTATUS_CI_UNSUPPORTED               (0x00b0)
 #define MPI3_IOCSTATUS_CI_UPDATE_SEQUENCE           (0x00b1)
 #define MPI3_IOCSTATUS_CI_VALIDATION_FAILED         (0x00b2)
-#define MPI3_IOCSTATUS_CI_UPDATE_PENDING            (0x00b3)
+#define MPI3_IOCSTATUS_CI_KEY_UPDATE_PENDING        (0x00b3)
+#define MPI3_IOCSTATUS_CI_KEY_UPDATE_NOT_POSSIBLE   (0x00b4)
 #define MPI3_IOCSTATUS_SECURITY_KEY_REQUIRED        (0x00c0)
+#define MPI3_IOCSTATUS_SECURITY_VIOLATION           (0x00c1)
 #define MPI3_IOCSTATUS_INVALID_QUEUE_ID             (0x0f00)
 #define MPI3_IOCSTATUS_INVALID_QUEUE_SIZE           (0x0f01)
 #define MPI3_IOCSTATUS_INVALID_MSIX_VECTOR          (0x0f02)

drivers/scsi/mpi3mr/mpi3mr.h+86−40

 #include "mpi/mpi30_init.h"
 #include "mpi/mpi30_ioc.h"
 #include "mpi/mpi30_sas.h"
+#include "mpi/mpi30_pci.h"
 #include "mpi3mr_debug.h"
 /* Global list and lock for storing multiple adapters managed by the driver */
 extern struct list_head mrioc_list;
 extern int prot_mask;
-#define MPI3MR_DRIVER_VERSION	"00.255.45.01"
+#define MPI3MR_DRIVER_VERSION	"8.0.0.61.0"
-#define MPI3MR_DRIVER_RELDATE	"12-December-2020"
+#define MPI3MR_DRIVER_RELDATE	"20-December-2021"
 #define MPI3MR_DRIVER_NAME	"mpi3mr"
 #define MPI3MR_DRIVER_LICENSE	"GPL"
 /* Operational queue management definitions */
 #define MPI3MR_OP_REQ_Q_QD		512
-#define MPI3MR_OP_REP_Q_QD		4096
+#define MPI3MR_OP_REP_Q_QD		1024
+#define MPI3MR_OP_REP_Q_QD4K		4096
 #define MPI3MR_OP_REQ_Q_SEG_SIZE	4096
 #define MPI3MR_OP_REP_Q_SEG_SIZE	4096
 #define MPI3MR_MAX_SEG_LIST_SIZE	4096
 #define MPI3MR_HOSTTAG_IOCTLCMDS	2
 #define MPI3MR_HOSTTAG_BLK_TMS		5
-#define MPI3MR_NUM_DEVRMCMD		1
+#define MPI3MR_NUM_DEVRMCMD		16
 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN	(MPI3MR_HOSTTAG_BLK_TMS + 1)
 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX	(MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
 						MPI3MR_NUM_DEVRMCMD - 1)
-#define MPI3MR_INTERNAL_CMDS_RESVD     MPI3MR_HOSTTAG_DEVRMCMD_MAX
+#define MPI3MR_INTERNAL_CMDS_RESVD	MPI3MR_HOSTTAG_DEVRMCMD_MAX
+#define MPI3MR_NUM_EVTACKCMD		4
+#define MPI3MR_HOSTTAG_EVTACKCMD_MIN	(MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1)
+#define MPI3MR_HOSTTAG_EVTACKCMD_MAX	(MPI3MR_HOSTTAG_EVTACKCMD_MIN + \
+					MPI3MR_NUM_EVTACKCMD - 1)
 /* Reduced resource count definition for crash kernel */
 #define MPI3MR_HOST_IOS_KDUMP		128
 /* command/controller interaction timeout definitions in seconds */
-#define MPI3MR_INTADMCMD_TIMEOUT		10
+#define MPI3MR_INTADMCMD_TIMEOUT		60
 #define MPI3MR_PORTENABLE_TIMEOUT		300
-#define MPI3MR_ABORTTM_TIMEOUT			30
+#define MPI3MR_ABORTTM_TIMEOUT			60
-#define MPI3MR_RESETTM_TIMEOUT			30
+#define MPI3MR_RESETTM_TIMEOUT			60
 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT	5
 #define MPI3MR_TSUPDATE_INTERVAL		900
 #define MPI3MR_DEFAULT_SHUTDOWN_TIME		120
 #define	MPI3MR_RAID_ERRREC_RESET_TIMEOUT	180
+#define MPI3MR_PREPARE_FOR_RESET_TIMEOUT	180
+#define MPI3MR_RESET_ACK_TIMEOUT		30
 #define MPI3MR_WATCHDOG_INTERVAL		1000 /* in milli seconds */
 /* Definitions for Event replies and sense buffer allocated per controller */
 #define MPI3MR_NUM_EVT_REPLIES	64
-#define MPI3MR_SENSEBUF_SZ	256
+#define MPI3MR_SENSE_BUF_SZ	256
 #define MPI3MR_SENSEBUF_FACTOR	3
 #define MPI3MR_CHAINBUF_FACTOR	3
 #define MPI3MR_CHAINBUFDIX_FACTOR	2
 /* ResponseCode definitions */
 #define MPI3MR_RI_MASK_RESPCODE		(0x000000FF)
-#define MPI3MR_RSP_TM_COMPLETE		0x00
-#define MPI3MR_RSP_INVALID_FRAME	0x02
-#define MPI3MR_RSP_TM_NOT_SUPPORTED	0x04
-#define MPI3MR_RSP_TM_FAILED		0x05
-#define MPI3MR_RSP_TM_SUCCEEDED		0x08
-#define MPI3MR_RSP_TM_INVALID_LUN	0x09
-#define MPI3MR_RSP_TM_OVERLAPPED_TAG	0x0A
 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \
 			MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
 #define MPI3MR_DEFAULT_MDTS	(128 * 1024)
+#define MPI3MR_DEFAULT_PGSZEXP         (12)
 /* Command retry count definitions */
 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3
 	MRIOC_STATE_UNRECOVERABLE,
 };
-/* Init type definitions */
-enum mpi3mr_init_type {
-	MPI3MR_IT_INIT = 0,
-	MPI3MR_IT_RESET,
-	MPI3MR_IT_RESUME,
-};
-/* Cleanup reason definitions */
-enum mpi3mr_cleanup_reason {
-	MPI3MR_COMPLETE_CLEANUP = 0,
-	MPI3MR_REINIT_FAILURE,
-	MPI3MR_SUSPEND,
-};
 /* Reset reason code definitions*/
 enum mpi3mr_reset_reason {
 	MPI3MR_RESET_FROM_BRINGUP = 1,
 	MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
 	MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
 	MPI3MR_RESET_FROM_SYSFS = 23,
-	MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24
+	MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24,
+	MPI3MR_RESET_FROM_FIRMWARE = 27,
+};
+/* Queue type definitions */
+enum queue_type {
+	MPI3MR_DEFAULT_QUEUE = 0,
+	MPI3MR_POLL_QUEUE,
 };
 /**
 	u16 max_vds;
 	u16 max_hpds;
 	u16 max_advhpds;
-	u16 max_raidpds;
+	u16 max_raid_pds;
 	u16 min_devhandle;
 	u16 max_devhandle;
 	u16 max_op_req_q;
  * @pend_ios: Number of IOs pending in HW for this queue
  * @enable_irq_poll: Flag to indicate polling is enabled
  * @in_use: Queue is handled by poll/ISR
+ * @qtype: Type of queue (types defined in enum queue_type)
  */
 struct op_reply_qinfo {
 	u16 ci;
 	atomic_t pend_ios;
 	bool enable_irq_poll;
 	atomic_t in_use;
+	enum queue_type qtype;
 };
 /**
  * @pgsz: Device page size
  * @abort_to: Timeout for abort TM
  * @reset_to: Timeout for Target/LUN reset TM
+ * @dev_info: Device information bits
  */
 struct tgt_dev_pcie {
 	u32 mdts;
 	u8 pgsz;
 	u8 abort_to;
 	u8 reset_to;
+	u16 dev_info;
 };
 /**
  * @dev_removedelay: Device is waiting to be removed in FW
  * @dev_type: Device type
  * @tgt_dev: Internal target device pointer
+ * @pend_count: Counter to track pending I/Os during error
+ *		handling
  */
 struct mpi3mr_stgt_priv_data {
 	struct scsi_target *starget;
 	u8 dev_removedelay;
 	u8 dev_type;
 	struct mpi3mr_tgt_dev *tgt_dev;
+	u32 pend_count;
 };
 /**
  * @tgt_priv_data: Scsi_target private data pointer
  * @lun_id: LUN ID of the device
  * @ncq_prio_enable: NCQ priority enable for SATA device
+ * @pend_count: Counter to track pending I/Os during error
+ *		handling
  */
 struct mpi3mr_sdev_priv_data {
 	struct mpi3mr_stgt_priv_data *tgt_priv_data;
 	u32 lun_id;
 	u8 ncq_prio_enable;
+	u32 pend_count;
 };
 /**
  * @ready_timeout: Controller ready timeout
  * @intr_info: Interrupt cookie pointer
  * @intr_info_count: Number of interrupt cookies
+ * @is_intr_info_set: Flag to indicate intr info is setup
  * @num_queues: Number of operational queues
  * @num_op_req_q: Number of operational request queues
  * @req_qinfo: Operational request queue info pointer
  * @chain_buf_lock: Chain buffer list lock
  * @host_tm_cmds: Command tracker for task management commands
  * @dev_rmhs_cmds: Command tracker for device removal commands
+ * @evtack_cmds: Command tracker for event ack commands
  * @devrem_bitmap_sz: Device removal bitmap size
  * @devrem_bitmap: Device removal bitmap
  * @dev_handle_bitmap_sz: Device handle bitmap size
  * @removepend_bitmap: Remove pending bitmap
  * @delayed_rmhs_list: Delayed device removal list
+ * @evtack_cmds_bitmap_sz: Event Ack bitmap size
+ * @evtack_cmds_bitmap: Event Ack bitmap
+ * @delayed_evtack_cmds_list: Delayed event acknowledgment list
  * @ts_update_counter: Timestamp update counter
- * @fault_dbg: Fault debug flag
  * @reset_in_progress: Reset in progress flag
  * @unrecoverable: Controller unrecoverable flag
+ * @prev_reset_result: Result of previous reset
  * @reset_mutex: Controller reset mutex
  * @reset_waitq: Controller reset  wait queue
+ * @prepare_for_reset: Prepare for reset event received
+ * @prepare_for_reset_timeout_counter: Prepare for reset timeout
  * @diagsave_timeout: Diagnostic information save timeout
  * @logging_level: Controller debug logging level
  * @flush_io_count: I/O count to flush after reset
  * @driver_info: Driver, Kernel, OS information to firmware
  * @change_count: Topology change count
  * @op_reply_q_offset: Operational reply queue offset with MSIx
+ * @default_qcount: Total Default queues
+ * @active_poll_qcount: Currently active poll queue count
+ * @requested_poll_qcount: User requested poll queue count
  */
 struct mpi3mr_ioc {
 	struct list_head list;
 	struct mpi3mr_intr_info *intr_info;
 	u16 intr_info_count;
+	bool is_intr_info_set;
 	u16 num_queues;
 	u16 num_op_req_q;
 	dma_addr_t reply_buf_dma_max_address;
 	u16 reply_free_qsz;
+	u16 reply_sz;
 	struct dma_pool *reply_free_q_pool;
 	__le64 *reply_free_q;
 	dma_addr_t reply_free_q_dma;
 	struct mpi3mr_drv_cmd host_tm_cmds;
 	struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
+	struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD];
 	u16 devrem_bitmap_sz;
 	void *devrem_bitmap;
 	u16 dev_handle_bitmap_sz;
 	void *removepend_bitmap;
 	struct list_head delayed_rmhs_list;
+	u16 evtack_cmds_bitmap_sz;
+	void *evtack_cmds_bitmap;
+	struct list_head delayed_evtack_cmds_list;
 	u32 ts_update_counter;
-	u8 fault_dbg;
 	u8 reset_in_progress;
 	u8 unrecoverable;
+	int prev_reset_result;
 	struct mutex reset_mutex;
 	wait_queue_head_t reset_waitq;
+	u8 prepare_for_reset;
+	u16 prepare_for_reset_timeout_counter;
 	u16 diagsave_timeout;
 	int logging_level;
 	u16 flush_io_count;
 	struct mpi3_driver_info_layout driver_info;
 	u16 change_count;
 	u16 op_reply_q_offset;
+	u16 default_qcount;
+	u16 active_poll_qcount;
+	u16 requested_poll_qcount;
 };
 /**
 	u8 iou_rc;
 };
+/**
+ * struct delayed_evt_ack_node - Delayed event ack node
+ * @list: list head
+ * @event: MPI3 event ID
+ * @event_ctx: event context
+ */
+struct delayed_evt_ack_node {
+	struct list_head list;
+	u8 event;
+	u32 event_ctx;
+};
 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);
 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);
-int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc, u8 init_type);
+int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc);
-void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc, u8 reason);
+int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume);
+void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc);
 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);
 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
 u16 admin_req_sz, u8 ignore_reset);
 				     u64 sense_buf_dma);
 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc);
+void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc);
 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
 			     struct mpi3_event_notification_reply *event_reply);
 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
 			      u32 reset_reason, u8 snapdump);
-int mpi3mr_diagfault_reset_handler(struct mpi3mr_ioc *mrioc,
-				   u32 reset_reason);
 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);
-int mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
+int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
 			  u32 event_ctx);
 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc);
-void mpi3mr_flush_delayed_rmhs_list(struct mpi3mr_ioc *mrioc);
+void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc);
+void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
+void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc);
+void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
+int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
+	struct op_reply_qinfo *op_reply_q);
+int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
 #endif /*MPI3MR_H_INCLUDED*/

drivers/scsi/mpi3mr/mpi3mr_debug.h+109−24

@@ -14,27 +14,20 @@ · 13 unmodified lines
14	/*	14	/*
15	* debug levels	15	* debug levels
16	*/	16	*/
17	#define MPI3_DEBUG 0x00000001	17
18	#define MPI3_DEBUG_MSG_FRAME 0x00000002	18	#define MPI3_DEBUG_EVENT 0x00000001
19	#define MPI3_DEBUG_SG 0x00000004	19	#define MPI3_DEBUG_EVENT_WORK_TASK 0x00000002
20	#define MPI3_DEBUG_EVENTS 0x00000008	20	#define MPI3_DEBUG_INIT 0x00000004
21	#define MPI3_DEBUG_EVENT_WORK_TASK 0x00000010	21	#define MPI3_DEBUG_EXIT 0x00000008
22	#define MPI3_DEBUG_INIT 0x00000020	22	#define MPI3_DEBUG_TM 0x00000010
23	#define MPI3_DEBUG_EXIT 0x00000040	23	#define MPI3_DEBUG_RESET 0x00000020
24	#define MPI3_DEBUG_FAIL 0x00000080	24	#define MPI3_DEBUG_SCSI_ERROR 0x00000040
25	#define MPI3_DEBUG_TM 0x00000100	25	#define MPI3_DEBUG_REPLY 0x00000080
26	#define MPI3_DEBUG_REPLY 0x00000200	26	#define MPI3_DEBUG_IOCTL_ERROR 0x00008000
27	#define MPI3_DEBUG_HANDSHAKE 0x00000400	27	#define MPI3_DEBUG_IOCTL_INFO 0x00010000
28	#define MPI3_DEBUG_CONFIG 0x00000800	28	#define MPI3_DEBUG_SCSI_INFO 0x00020000
29	#define MPI3_DEBUG_DL 0x00001000	29	#define MPI3_DEBUG 0x01000000
30	#define MPI3_DEBUG_RESET 0x00002000	30	#define MPI3_DEBUG_SG 0x02000000
31	#define MPI3_DEBUG_SCSI 0x00004000
32	#define MPI3_DEBUG_IOCTL 0x00008000
33	#define MPI3_DEBUG_CSMISAS 0x00010000
34	#define MPI3_DEBUG_SAS 0x00020000
35	#define MPI3_DEBUG_TRANSPORT 0x00040000
36	#define MPI3_DEBUG_TASK_SET_FULL 0x00080000
37	#define MPI3_DEBUG_TRIGGER_DIAG 0x00200000
38		31
39		32
40	/*	33	/*
@@ -50,11 +43,103 @@ · 9 unmodified lines
50	#define ioc_info(ioc, fmt, ...) \	43	#define ioc_info(ioc, fmt, ...) \
51	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__)	44	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__)
52		45
		46	#define dprint(ioc, fmt, ...) \
		47	do { \
		48	if (ioc->logging_level & MPI3_DEBUG) \
		49	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__); \
		50	} while (0)
		51
		52	#define dprint_event_th(ioc, fmt, ...) \
		53	do { \
		54	if (ioc->logging_level & MPI3_DEBUG_EVENT) \
		55	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__); \
		56	} while (0)
		57
		58	#define dprint_event_bh(ioc, fmt, ...) \
		59	do { \
		60	if (ioc->logging_level & MPI3_DEBUG_EVENT_WORK_TASK) \
		61	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__); \
		62	} while (0)
		63
		64	#define dprint_init(ioc, fmt, ...) \
		65	do { \
		66	if (ioc->logging_level & MPI3_DEBUG_INIT) \
		67	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__); \
		68	} while (0)
		69
		70	#define dprint_exit(ioc, fmt, ...) \
		71	do { \
		72	if (ioc->logging_level & MPI3_DEBUG_EXIT) \
		73	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__); \
		74	} while (0)
		75
		76	#define dprint_tm(ioc, fmt, ...) \
		77	do { \
		78	if (ioc->logging_level & MPI3_DEBUG_TM) \
		79	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__); \
		80	} while (0)
		81
		82	#define dprint_reply(ioc, fmt, ...) \
		83	do { \
		84	if (ioc->logging_level & MPI3_DEBUG_REPLY) \
		85	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__); \
		86	} while (0)
		87
		88	#define dprint_reset(ioc, fmt, ...) \
		89	do { \
		90	if (ioc->logging_level & MPI3_DEBUG_RESET) \
		91	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__); \
		92	} while (0)
		93
		94	#define dprint_scsi_info(ioc, fmt, ...) \
		95	do { \
		96	if (ioc->logging_level & MPI3_DEBUG_SCSI_INFO) \
		97	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__); \
		98	} while (0)
		99
		100	#define dprint_scsi_err(ioc, fmt, ...) \
		101	do { \
		102	if (ioc->logging_level & MPI3_DEBUG_SCSI_ERROR) \
		103	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__); \
		104	} while (0)
		105
		106	#define dprint_scsi_command(ioc, SCMD, LOG_LEVEL) \
		107	do { \
		108	if (ioc->logging_level & LOG_LEVEL) \
		109	scsi_print_command(SCMD); \
		110	} while (0)
		111
		112
		113	#define dprint_ioctl_info(ioc, fmt, ...) \
		114	do { \
		115	if (ioc->logging_level & MPI3_DEBUG_IOCTL_INFO) \
		116	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__); \
		117	} while (0)
53		118
54	#define dbgprint(IOC, FMT, ...) \	119	#define dprint_ioctl_err(ioc, fmt, ...) \
55	do { \	120	do { \
56	if (IOC->logging_level & MPI3_DEBUG) \	121	if (ioc->logging_level & MPI3_DEBUG_IOCTL_ERROR) \
57	pr_info("%s: " FMT, (IOC)->name, ##__VA_ARGS__); \	122	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__); \
58	} while (0)	123	} while (0)
59		124
60	#endif /* MPT3SAS_DEBUG_H_INCLUDED */	125	#endif /* MPT3SAS_DEBUG_H_INCLUDED */
		126
		127	/**
		128	* dprint_dump_req - print message frame contents
		129	* @req: pointer to message frame
		130	* @sz: number of dwords
		131	*/
		132	static inline void
		133	dprint_dump_req(void *req, int sz)
		134	{
		135	int i;
		136	__le32 mfp = (__le32 )req;
		137
		138	pr_info("request:\n\t");
		139	for (i = 0; i < sz; i++) {
		140	if (i && ((i % 8) == 0))
		141	pr_info("\n\t");
		142	pr_info("%08x ", le32_to_cpu(mfp[i]));
		143	}
		144	pr_info("\n");
		145	}

drivers/scsi/mpi3mr/mpi3mr_fw.c+951−500

@@ -10,6 +10,16 @@ · 9 unmodified lines
10	#include "mpi3mr.h"	10	#include "mpi3mr.h"
11	#include <linux/io-64-nonatomic-lo-hi.h>	11	#include <linux/io-64-nonatomic-lo-hi.h>
12		12
		13	static int
		14	mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason);
		15	static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
		16	static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
		17	struct mpi3_ioc_facts_data *facts_data);
		18
		19	static int poll_queues;
		20	module_param(poll_queues, int, 0444);
		21	MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
		22
13	#if defined(writeq) && defined(CONFIG_64BIT)	23	#if defined(writeq) && defined(CONFIG_64BIT)
14	static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)	24	static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
15	{	25	{
@@ -78,6 +88,7 @@ static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc) · 62 unmodified lines
78	kfree(mrioc->intr_info);	88	kfree(mrioc->intr_info);
79	mrioc->intr_info = NULL;	89	mrioc->intr_info = NULL;
80	mrioc->intr_info_count = 0;	90	mrioc->intr_info_count = 0;
		91	mrioc->is_intr_info_set = false;
81	pci_free_irq_vectors(mrioc->pdev);	92	pci_free_irq_vectors(mrioc->pdev);
82	}	93	}
83		94
@@ -124,8 +135,9 @@ static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc, · 40 unmodified lines
124	u64 reply_dma)	135	u64 reply_dma)
125	{	136	{
126	u32 old_idx = 0;	137	u32 old_idx = 0;
		138	unsigned long flags;
127		139
128	spin_lock(&mrioc->reply_free_queue_lock);	140	spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
129	old_idx = mrioc->reply_free_queue_host_index;	141	old_idx = mrioc->reply_free_queue_host_index;
130	mrioc->reply_free_queue_host_index = (	142	mrioc->reply_free_queue_host_index = (
131	(mrioc->reply_free_queue_host_index ==	143	(mrioc->reply_free_queue_host_index ==
@@ -134,15 +146,16 @@ static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc, · 2 unmodified lines
134	mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);	146	mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
135	writel(mrioc->reply_free_queue_host_index,	147	writel(mrioc->reply_free_queue_host_index,
136	&mrioc->sysif_regs->reply_free_host_index);	148	&mrioc->sysif_regs->reply_free_host_index);
137	spin_unlock(&mrioc->reply_free_queue_lock);	149	spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
138	}	150	}
139		151
140	void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,	152	void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
141	u64 sense_buf_dma)	153	u64 sense_buf_dma)
142	{	154	{
143	u32 old_idx = 0;	155	u32 old_idx = 0;
		156	unsigned long flags;
144		157
145	spin_lock(&mrioc->sbq_lock);	158	spin_lock_irqsave(&mrioc->sbq_lock, flags);
146	old_idx = mrioc->sbq_host_index;	159	old_idx = mrioc->sbq_host_index;
147	mrioc->sbq_host_index = ((mrioc->sbq_host_index ==	160	mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
148	(mrioc->sense_buf_q_sz - 1)) ? 0 :	161	(mrioc->sense_buf_q_sz - 1)) ? 0 :
@@ -150,7 +163,7 @@ void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, · 1 unmodified line
150	mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);	163	mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
151	writel(mrioc->sbq_host_index,	164	writel(mrioc->sbq_host_index,
152	&mrioc->sysif_regs->sense_buffer_free_host_index);	165	&mrioc->sysif_regs->sense_buffer_free_host_index);
153	spin_unlock(&mrioc->sbq_lock);	166	spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
154	}	167	}
155		168
156	static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,	169	static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
@@ -303,6 +316,12 @@ mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag, · 146 unmodified lines
303	return &mrioc->dev_rmhs_cmds[idx];	316	return &mrioc->dev_rmhs_cmds[idx];
304	}	317	}
305		318
		319	if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
		320	host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
		321	idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
		322	return &mrioc->evtack_cmds[idx];
		323	}
		324
306	return NULL;	325	return NULL;
307	}	326	}
308		327
@@ -369,7 +388,7 @@ static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc, · 60 unmodified lines
369	if (def_reply) {	388	if (def_reply) {
370	cmdptr->state \|= MPI3MR_CMD_REPLY_VALID;	389	cmdptr->state \|= MPI3MR_CMD_REPLY_VALID;
371	memcpy((u8 )cmdptr->reply, (u8 )def_reply,	390	memcpy((u8 )cmdptr->reply, (u8 )def_reply,
372	mrioc->facts.reply_sz);	391	mrioc->reply_sz);
373	}	392	}
374	if (cmdptr->is_waiting) {	393	if (cmdptr->is_waiting) {
375	complete(&cmdptr->done);	394	complete(&cmdptr->done);
@@ -446,10 +465,21 @@ mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci) · 70 unmodified lines
446	return reply_desc;	465	return reply_desc;
447	}	466	}
448		467
449	static int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,	468	/**
450	struct mpi3mr_intr_info *intr_info)	469	* mpi3mr_process_op_reply_q - Operational reply queue handler
		470	* @mrioc: Adapter instance reference
		471	* @op_reply_q: Operational reply queue info
		472	*
		473	* Checks the specific operational reply queue and drains the
		474	* reply queue entries until the queue is empty and process the
		475	* individual reply descriptors.
		476	*
		477	* Return: 0 if queue is already processed,or number of reply
		478	* descriptors processed.
		479	*/
		480	int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
		481	struct op_reply_qinfo *op_reply_q)
451	{	482	{
452	struct op_reply_qinfo *op_reply_q = intr_info->op_reply_q;
453	struct op_req_qinfo *op_req_q;	483	struct op_req_qinfo *op_req_q;
454	u32 exp_phase;	484	u32 exp_phase;
455	u32 reply_ci;	485	u32 reply_ci;
@@ -500,7 +530,7 @@ static int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, · 44 unmodified lines
500	* Ensure remaining completion happens from threaded ISR.	530	* Ensure remaining completion happens from threaded ISR.
501	*/	531	*/
502	if (num_op_reply > mrioc->max_host_ios) {	532	if (num_op_reply > mrioc->max_host_ios) {
503	intr_info->op_reply_q->enable_irq_poll = true;	533	op_reply_q->enable_irq_poll = true;
504	break;	534	break;
505	}	535	}
506		536
@@ -515,6 +545,34 @@ static int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, · 8 unmodified lines
515	return num_op_reply;	545	return num_op_reply;
516	}	546	}
517		547
		548	/**
		549	* mpi3mr_blk_mq_poll - Operational reply queue handler
		550	* @shost: SCSI Host reference
		551	* @queue_num: Request queue number (w.r.t OS it is hardware context number)
		552	*
		553	* Checks the specific operational reply queue and drains the
		554	* reply queue entries until the queue is empty and process the
		555	* individual reply descriptors.
		556	*
		557	* Return: 0 if queue is already processed,or number of reply
		558	* descriptors processed.
		559	*/
		560	int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
		561	{
		562	int num_entries = 0;
		563	struct mpi3mr_ioc *mrioc;
		564
		565	mrioc = (struct mpi3mr_ioc *)shost->hostdata;
		566
		567	if ((mrioc->reset_in_progress \|\| mrioc->prepare_for_reset))
		568	return 0;
		569
		570	num_entries = mpi3mr_process_op_reply_q(mrioc,
		571	&mrioc->op_reply_qinfo[queue_num]);
		572
		573	return num_entries;
		574	}
		575
518	static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)	576	static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
519	{	577	{
520	struct mpi3mr_intr_info *intr_info = privdata;	578	struct mpi3mr_intr_info *intr_info = privdata;
@@ -535,7 +593,8 @@ static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata) · 14 unmodified lines
535	if (!midx)	593	if (!midx)
536	num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);	594	num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
537	if (intr_info->op_reply_q)	595	if (intr_info->op_reply_q)
538	num_op_reply = mpi3mr_process_op_reply_q(mrioc, intr_info);	596	num_op_reply = mpi3mr_process_op_reply_q(mrioc,
		597	intr_info->op_reply_q);
539		598
540	if (num_admin_replies \|\| num_op_reply)	599	if (num_admin_replies \|\| num_op_reply)
541	return IRQ_HANDLED;	600	return IRQ_HANDLED;
@@ -606,9 +665,10 @@ static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata) · 64 unmodified lines
606	mpi3mr_process_admin_reply_q(mrioc);	665	mpi3mr_process_admin_reply_q(mrioc);
607	if (intr_info->op_reply_q)	666	if (intr_info->op_reply_q)
608	num_op_reply +=	667	num_op_reply +=
609	mpi3mr_process_op_reply_q(mrioc, intr_info);	668	mpi3mr_process_op_reply_q(mrioc,
		669	intr_info->op_reply_q);
610		670
611	usleep_range(mrioc->irqpoll_sleep, 10 * mrioc->irqpoll_sleep);	671	usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP);
612		672
613	} while (atomic_read(&intr_info->op_reply_q->pend_ios) &&	673	} while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
614	(num_op_reply < mrioc->max_host_ios));	674	(num_op_reply < mrioc->max_host_ios));
@@ -652,6 +712,25 @@ static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index) · 37 unmodified lines
652	return retval;	712	return retval;
653	}	713	}
654		714
		715	static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
		716	{
		717	if (!mrioc->requested_poll_qcount)
		718	return;
		719
		720	/* Reserved for Admin and Default Queue */
		721	if (max_vectors > 2 &&
		722	(mrioc->requested_poll_qcount < max_vectors - 2)) {
		723	ioc_info(mrioc,
		724	"enabled polled queues (%d) msix (%d)\n",
		725	mrioc->requested_poll_qcount, max_vectors);
		726	} else {
		727	ioc_info(mrioc,
		728	"disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
		729	mrioc->requested_poll_qcount, max_vectors);
		730	mrioc->requested_poll_qcount = 0;
		731	}
		732	}
		733
655	/**	734	/**
656	* mpi3mr_setup_isr - Setup ISR for the controller	735	* mpi3mr_setup_isr - Setup ISR for the controller
657	* @mrioc: Adapter instance reference	736	* @mrioc: Adapter instance reference
@@ -664,48 +743,72 @@ static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index) · 6 unmodified lines
664	static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)	743	static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
665	{	744	{
666	unsigned int irq_flags = PCI_IRQ_MSIX;	745	unsigned int irq_flags = PCI_IRQ_MSIX;
667	int max_vectors;	746	int max_vectors, min_vec;
668	int retval;	747	int retval;
669	int i;	748	int i;
670	struct irq_affinity desc = { .pre_vectors = 1};	749	struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 };
		750
		751	if (mrioc->is_intr_info_set)
		752	return 0;
671		753
672	mpi3mr_cleanup_isr(mrioc);	754	mpi3mr_cleanup_isr(mrioc);
673		755
674	if (setup_one \|\| reset_devices)	756	if (setup_one \|\| reset_devices) {
675	max_vectors = 1;	757	max_vectors = 1;
676	else {	758	retval = pci_alloc_irq_vectors(mrioc->pdev,
		759	1, max_vectors, irq_flags);
		760	if (retval < 0) {
		761	ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
		762	retval);
		763	goto out_failed;
		764	}
		765	} else {
677	max_vectors =	766	max_vectors =
678	min_t(int, mrioc->cpu_count + 1, mrioc->msix_count);	767	min_t(int, mrioc->cpu_count + 1 +
		768	mrioc->requested_poll_qcount, mrioc->msix_count);
		769
		770	mpi3mr_calc_poll_queues(mrioc, max_vectors);
679		771
680	ioc_info(mrioc,	772	ioc_info(mrioc,
681	"MSI-X vectors supported: %d, no of cores: %d,",	773	"MSI-X vectors supported: %d, no of cores: %d,",
682	mrioc->msix_count, mrioc->cpu_count);	774	mrioc->msix_count, mrioc->cpu_count);
683	ioc_info(mrioc,	775	ioc_info(mrioc,
684	"MSI-x vectors requested: %d\n", max_vectors);	776	"MSI-x vectors requested: %d poll_queues %d\n",
685	}	777	max_vectors, mrioc->requested_poll_qcount);
		778
		779	desc.post_vectors = mrioc->requested_poll_qcount;
		780	min_vec = desc.pre_vectors + desc.post_vectors;
		781	irq_flags \|= PCI_IRQ_AFFINITY \| PCI_IRQ_ALL_TYPES;
		782
		783	retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
		784	min_vec, max_vectors, irq_flags, &desc);
		785
		786	if (retval < 0) {
		787	ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
		788	retval);
		789	goto out_failed;
		790	}
686		791
687	irq_flags \|= PCI_IRQ_AFFINITY \| PCI_IRQ_ALL_TYPES;
688		792
689	mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
690	retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
691	1, max_vectors, irq_flags, &desc);
692	if (retval < 0) {
693	ioc_err(mrioc, "Cannot alloc irq vectors\n");
694	goto out_failed;
695	}
696	if (retval != max_vectors) {
697	ioc_info(mrioc,
698	"allocated vectors (%d) are less than configured (%d)\n",
699	retval, max_vectors);
700	/*	793	/*
701	* If only one MSI-x is allocated, then MSI-x 0 will be shared	794	* If only one MSI-x is allocated, then MSI-x 0 will be shared
702	* between Admin queue and operational queue	795	* between Admin queue and operational queue
703	*/	796	*/
704	if (retval == 1)	797	if (retval == min_vec)
705	mrioc->op_reply_q_offset = 0;	798	mrioc->op_reply_q_offset = 0;
		799	else if (retval != (max_vectors)) {
		800	ioc_info(mrioc,
		801	"allocated vectors (%d) are less than configured (%d)\n",
		802	retval, max_vectors);
		803	}
706		804
707	max_vectors = retval;	805	max_vectors = retval;
		806	mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
		807
		808	mpi3mr_calc_poll_queues(mrioc, max_vectors);
		809
708	}	810	}
		811
709	mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,	812	mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
710	GFP_KERNEL);	813	GFP_KERNEL);
711	if (!mrioc->intr_info) {	814	if (!mrioc->intr_info) {
@@ -720,6 +823,8 @@ static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one) · 8 unmodified lines
720	goto out_failed;	823	goto out_failed;
721	}	824	}
722	}	825	}
		826	if (reset_devices \|\| !setup_one)
		827	mrioc->is_intr_info_set = true;
723	mrioc->intr_info_count = max_vectors;	828	mrioc->intr_info_count = max_vectors;
724	mpi3mr_ioc_enable_intr(mrioc);	829	mpi3mr_ioc_enable_intr(mrioc);
725	return 0;	830	return 0;
@@ -796,6 +901,7 @@ static const struct { · 70 unmodified lines
796	},	901	},
797	{ MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },	902	{ MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
798	{ MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },	903	{ MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
		904	{ MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronus reset" },
799	};	905	};
800		906
801	/**	907	/**
@@ -860,7 +966,7 @@ static const char *mpi3mr_reset_type_name(u16 reset_type) · 58 unmodified lines
860	*	966	*
861	* Return: Nothing.	967	* Return: Nothing.
862	*/	968	*/
863	static void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)	969	void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
864	{	970	{
865	u32 ioc_status, code, code1, code2, code3;	971	u32 ioc_status, code, code1, code2, code3;
866		972
@@ -958,31 +1064,91 @@ static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc, · 91 unmodified lines
958	ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;	1064	ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
959	writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);	1065	writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
960		1066
961	timeout = mrioc->ready_timeout * 10;	1067	timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
962	do {	1068	do {
963	ioc_status = readl(&mrioc->sysif_regs->ioc_status);	1069	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
964	if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {	1070	if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
965	mpi3mr_clear_reset_history(mrioc);	1071	mpi3mr_clear_reset_history(mrioc);
966	ioc_config =	1072	break;
967	readl(&mrioc->sysif_regs->ioc_configuration);	1073	}
968	if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) \|\|	1074	if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
969	(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) \|\|	1075	mpi3mr_print_fault_info(mrioc);
970	(ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) {	1076	break;
971	retval = 0;
972	break;
973	}
974	}	1077	}
975	msleep(100);	1078	msleep(100);
976	} while (--timeout);	1079	} while (--timeout);
977		1080
978	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
979	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);	1081	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
		1082	if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) \|\|
		1083	(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) \|\|
		1084	(ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
		1085	retval = 0;
980		1086
981	ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",	1087	ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",
982	(!retval) ? "successful" : "failed", ioc_status, ioc_config);	1088	(!retval) ? "successful" : "failed", ioc_status, ioc_config);
983	return retval;	1089	return retval;
984	}	1090	}
985		1091
		1092	/**
		1093	* mpi3mr_revalidate_factsdata - validate IOCFacts parameters
		1094	* during reset/resume
		1095	* @mrioc: Adapter instance reference
		1096	*
		1097	* Return zero if the new IOCFacts parameters value is compatible with
		1098	* older values else return -EPERM
		1099	*/
		1100	static int
		1101	mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
		1102	{
		1103	u16 dev_handle_bitmap_sz;
		1104	void *removepend_bitmap;
		1105
		1106	if (mrioc->facts.reply_sz > mrioc->reply_sz) {
		1107	ioc_err(mrioc,
		1108	"cannot increase reply size from %d to %d\n",
		1109	mrioc->reply_sz, mrioc->facts.reply_sz);
		1110	return -EPERM;
		1111	}
		1112
		1113	if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
		1114	ioc_err(mrioc,
		1115	"cannot reduce number of operational reply queues from %d to %d\n",
		1116	mrioc->num_op_reply_q,
		1117	mrioc->facts.max_op_reply_q);
		1118	return -EPERM;
		1119	}
		1120
		1121	if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
		1122	ioc_err(mrioc,
		1123	"cannot reduce number of operational request queues from %d to %d\n",
		1124	mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
		1125	return -EPERM;
		1126	}
		1127
		1128	dev_handle_bitmap_sz = mrioc->facts.max_devhandle / 8;
		1129	if (mrioc->facts.max_devhandle % 8)
		1130	dev_handle_bitmap_sz++;
		1131	if (dev_handle_bitmap_sz > mrioc->dev_handle_bitmap_sz) {
		1132	removepend_bitmap = krealloc(mrioc->removepend_bitmap,
		1133	dev_handle_bitmap_sz, GFP_KERNEL);
		1134	if (!removepend_bitmap) {
		1135	ioc_err(mrioc,
		1136	"failed to increase removepend_bitmap sz from: %d to %d\n",
		1137	mrioc->dev_handle_bitmap_sz, dev_handle_bitmap_sz);
		1138	return -EPERM;
		1139	}
		1140	memset(removepend_bitmap + mrioc->dev_handle_bitmap_sz, 0,
		1141	dev_handle_bitmap_sz - mrioc->dev_handle_bitmap_sz);
		1142	mrioc->removepend_bitmap = removepend_bitmap;
		1143	ioc_info(mrioc,
		1144	"increased dev_handle_bitmap_sz from %d to %d\n",
		1145	mrioc->dev_handle_bitmap_sz, dev_handle_bitmap_sz);
		1146	mrioc->dev_handle_bitmap_sz = dev_handle_bitmap_sz;
		1147	}
		1148
		1149	return 0;
		1150	}
		1151
986	/**	1152	/**
987	* mpi3mr_bring_ioc_ready - Bring controller to ready state	1153	* mpi3mr_bring_ioc_ready - Bring controller to ready state
988	* @mrioc: Adapter instance reference	1154	* @mrioc: Adapter instance reference
@@ -990,26 +1156,105 @@ static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc, · 1 unmodified line
990	* Set Enable IOC bit in IOC configuration register and wait for	1156	* Set Enable IOC bit in IOC configuration register and wait for
991	* the controller to become ready.	1157	* the controller to become ready.
992	*	1158	*
993	* Return: 0 on success, -1 on failure.	1159	* Return: 0 on success, appropriate error on failure.
994	*/	1160	*/
995	static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)	1161	static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
996	{	1162	{
997	u32 ioc_config, timeout;	1163	u32 ioc_config, ioc_status, timeout;
998	enum mpi3mr_iocstate current_state;	1164	int retval = 0;
		1165	enum mpi3mr_iocstate ioc_state;
		1166	u64 base_info;
		1167
		1168	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
		1169	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
		1170	base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
		1171	ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
		1172	ioc_status, ioc_config, base_info);
		1173
		1174	/The timeout value is in 2sec unit, changing it to seconds/
		1175	mrioc->ready_timeout =
		1176	((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
		1177	MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
		1178
		1179	ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
		1180
		1181	ioc_state = mpi3mr_get_iocstate(mrioc);
		1182	ioc_info(mrioc, "controller is in %s state during detection\n",
		1183	mpi3mr_iocstate_name(ioc_state));
		1184
		1185	if (ioc_state == MRIOC_STATE_BECOMING_READY \|\|
		1186	ioc_state == MRIOC_STATE_RESET_REQUESTED) {
		1187	timeout = mrioc->ready_timeout * 10;
		1188	do {
		1189	msleep(100);
		1190	} while (--timeout);
		1191
		1192	ioc_state = mpi3mr_get_iocstate(mrioc);
		1193	ioc_info(mrioc,
		1194	"controller is in %s state after waiting to reset\n",
		1195	mpi3mr_iocstate_name(ioc_state));
		1196	}
		1197
		1198	if (ioc_state == MRIOC_STATE_READY) {
		1199	ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
		1200	retval = mpi3mr_issue_and_process_mur(mrioc,
		1201	MPI3MR_RESET_FROM_BRINGUP);
		1202	ioc_state = mpi3mr_get_iocstate(mrioc);
		1203	if (retval)
		1204	ioc_err(mrioc,
		1205	"message unit reset failed with error %d current state %s\n",
		1206	retval, mpi3mr_iocstate_name(ioc_state));
		1207	}
		1208	if (ioc_state != MRIOC_STATE_RESET) {
		1209	mpi3mr_print_fault_info(mrioc);
		1210	ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
		1211	retval = mpi3mr_issue_reset(mrioc,
		1212	MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
		1213	MPI3MR_RESET_FROM_BRINGUP);
		1214	if (retval) {
		1215	ioc_err(mrioc,
		1216	"soft reset failed with error %d\n", retval);
		1217	goto out_failed;
		1218	}
		1219	}
		1220	ioc_state = mpi3mr_get_iocstate(mrioc);
		1221	if (ioc_state != MRIOC_STATE_RESET) {
		1222	ioc_err(mrioc,
		1223	"cannot bring controller to reset state, current state: %s\n",
		1224	mpi3mr_iocstate_name(ioc_state));
		1225	goto out_failed;
		1226	}
		1227	mpi3mr_clear_reset_history(mrioc);
		1228	retval = mpi3mr_setup_admin_qpair(mrioc);
		1229	if (retval) {
		1230	ioc_err(mrioc, "failed to setup admin queues: error %d\n",
		1231	retval);
		1232	goto out_failed;
		1233	}
999		1234
		1235	ioc_info(mrioc, "bringing controller to ready state\n");
1000	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);	1236	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1001	ioc_config \|= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;	1237	ioc_config \|= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1002	writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);	1238	writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1003		1239
1004	timeout = mrioc->ready_timeout * 10;	1240	timeout = mrioc->ready_timeout * 10;
1005	do {	1241	do {
1006	current_state = mpi3mr_get_iocstate(mrioc);	1242	ioc_state = mpi3mr_get_iocstate(mrioc);
1007	if (current_state == MRIOC_STATE_READY)	1243	if (ioc_state == MRIOC_STATE_READY) {
		1244	ioc_info(mrioc,
		1245	"successfully transistioned to %s state\n",
		1246	mpi3mr_iocstate_name(ioc_state));
1008	return 0;	1247	return 0;
		1248	}
1009	msleep(100);	1249	msleep(100);
1010	} while (--timeout);	1250	} while (--timeout);
1011		1251
1012	return -1;	1252	out_failed:
		1253	ioc_state = mpi3mr_get_iocstate(mrioc);
		1254	ioc_err(mrioc,
		1255	"failed to bring to ready state, current state: %s\n",
		1256	mpi3mr_iocstate_name(ioc_state));
		1257	return retval;
1013	}	1258	}
1014		1259
1015	/**	1260	/**
@@ -1026,7 +1271,6 @@ static inline bool · 10 unmodified lines
1026	mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)	1271	mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1027	{	1272	{
1028	if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) \|\|	1273	if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) \|\|
1029	(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) \|\|
1030	(ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))	1274	(ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1031	return true;	1275	return true;
1032	return false;	1276	return false;
@@ -1049,8 +1293,10 @@ static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc, · 16 unmodified lines
1049	if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))	1293	if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1050	return false;	1294	return false;
1051	fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;	1295	fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1052	if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET)	1296	if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
		1297	mpi3mr_print_fault_info(mrioc);
1053	return true;	1298	return true;
		1299	}
1054	return false;	1300	return false;
1055	}	1301	}
1056		1302
@@ -1089,26 +1335,36 @@ static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, · 32 unmodified lines
1089	u32 reset_reason)	1335	u32 reset_reason)
1090	{	1336	{
1091	int retval = -1;	1337	int retval = -1;
1092	u8 unlock_retry_count, reset_retry_count = 0;	1338	u8 unlock_retry_count = 0;
1093	u32 host_diagnostic, timeout, ioc_status, ioc_config;	1339	u32 host_diagnostic, ioc_status, ioc_config;
		1340	u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1094		1341
1095	pci_cfg_access_lock(mrioc->pdev);
1096	if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&	1342	if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1097	(reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))	1343	(reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1098	goto out;	1344	return retval;
1099	if (mrioc->unrecoverable)	1345	if (mrioc->unrecoverable)
1100	goto out;	1346	return retval;
1101	retry_reset:	1347	if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1102	unlock_retry_count = 0;	1348	retval = 0;
		1349	return retval;
		1350	}
		1351
		1352	ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
		1353	mpi3mr_reset_type_name(reset_type),
		1354	mpi3mr_reset_rc_name(reset_reason), reset_reason);
		1355
1103	mpi3mr_clear_reset_history(mrioc);	1356	mpi3mr_clear_reset_history(mrioc);
1104	do {	1357	do {
1105	ioc_info(mrioc,	1358	ioc_info(mrioc,
1106	"Write magic sequence to unlock host diag register (retry=%d)\n",	1359	"Write magic sequence to unlock host diag register (retry=%d)\n",
1107	++unlock_retry_count);	1360	++unlock_retry_count);
1108	if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {	1361	if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1109	writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);	1362	ioc_err(mrioc,
		1363	"%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
		1364	mpi3mr_reset_type_name(reset_type),
		1365	host_diagnostic);
1110	mrioc->unrecoverable = 1;	1366	mrioc->unrecoverable = 1;
1111	goto out;	1367	return retval;
1112	}	1368	}
1113		1369
1114	writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,	1370	writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
@@ -1133,31 +1389,26 @@ retry_reset: · 18 unmodified lines
1133	} while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));	1389	} while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1134		1390
1135	writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);	1391	writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1136	ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1137	mpi3mr_reset_type_name(reset_type),
1138	mpi3mr_reset_rc_name(reset_reason), reset_reason);
1139	writel(host_diagnostic \| reset_type,	1392	writel(host_diagnostic \| reset_type,
1140	&mrioc->sysif_regs->host_diagnostic);	1393	&mrioc->sysif_regs->host_diagnostic);
1141	timeout = mrioc->ready_timeout * 10;	1394	switch (reset_type) {
1142	if (reset_type == MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) {	1395	case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1143	do {	1396	do {
1144	ioc_status = readl(&mrioc->sysif_regs->ioc_status);	1397	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1145	if (ioc_status &	1398	ioc_config =
1146	MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {	1399	readl(&mrioc->sysif_regs->ioc_configuration);
		1400	if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
		1401	&& mpi3mr_soft_reset_success(ioc_status, ioc_config)
		1402	) {
1147	mpi3mr_clear_reset_history(mrioc);	1403	mpi3mr_clear_reset_history(mrioc);
1148	ioc_config =	1404	retval = 0;
1149	readl(&mrioc->sysif_regs->ioc_configuration);	1405	break;
1150	if (mpi3mr_soft_reset_success(ioc_status,
1151	ioc_config)) {
1152	retval = 0;
1153	break;
1154	}
1155	}	1406	}
1156	msleep(100);	1407	msleep(100);
1157	} while (--timeout);	1408	} while (--timeout);
1158	writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,	1409	mpi3mr_print_fault_info(mrioc);
1159	&mrioc->sysif_regs->write_sequence);	1410	break;
1160	} else if (reset_type == MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT) {	1411	case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1161	do {	1412	do {
1162	ioc_status = readl(&mrioc->sysif_regs->ioc_status);	1413	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1163	if (mpi3mr_diagfault_success(mrioc, ioc_status)) {	1414	if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
@@ -1166,28 +1417,22 @@ retry_reset: · 2 unmodified lines
1166	}	1417	}
1167	msleep(100);	1418	msleep(100);
1168	} while (--timeout);	1419	} while (--timeout);
1169	mpi3mr_clear_reset_history(mrioc);	1420	break;
1170	writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,	1421	default:
1171	&mrioc->sysif_regs->write_sequence);	1422	break;
1172	}
1173	if (retval && ((++reset_retry_count) < MPI3MR_MAX_RESET_RETRY_COUNT)) {
1174	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1175	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1176	ioc_info(mrioc,
1177	"Base IOC Sts/Config after reset try %d is (0x%x)/(0x%x)\n",
1178	reset_retry_count, ioc_status, ioc_config);
1179	goto retry_reset;
1180	}	1423	}
1181		1424
1182	out:	1425	writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1183	pci_cfg_access_unlock(mrioc->pdev);	1426	&mrioc->sysif_regs->write_sequence);
1184	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1185	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1186		1427
		1428	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
		1429	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1187	ioc_info(mrioc,	1430	ioc_info(mrioc,
1188	"Base IOC Sts/Config after %s reset is (0x%x)/(0x%x)\n",	1431	"ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n",
1189	(!retval) ? "successful" : "failed", ioc_status,	1432	(!retval)?"successful":"failed", ioc_status,
1190	ioc_config);	1433	ioc_config);
		1434	if (retval)
		1435	mrioc->unrecoverable = 1;
1191	return retval;	1436	return retval;
1192	}	1437	}
1193		1438
@@ -1278,7 +1523,7 @@ static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) · 84 unmodified lines
1278	mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;	1523	mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1279	}	1524	}
1280	} else	1525	} else
1281	size = mrioc->req_qinfo[q_idx].num_requests *	1526	size = mrioc->req_qinfo[q_idx].segment_qd *
1282	mrioc->facts.op_req_sz;	1527	mrioc->facts.op_req_sz;
1283		1528
1284	for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {	1529	for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
@@ -1351,10 +1596,11 @@ static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) · 66 unmodified lines
1351	static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)	1596	static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1352	{	1597	{
1353	struct mpi3_delete_reply_queue_request delq_req;	1598	struct mpi3_delete_reply_queue_request delq_req;
		1599	struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1354	int retval = 0;	1600	int retval = 0;
1355	u16 reply_qid = 0, midx;	1601	u16 reply_qid = 0, midx;
1356		1602
1357	reply_qid = mrioc->op_reply_qinfo[qidx].qid;	1603	reply_qid = op_reply_q->qid;
1358		1604
1359	midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);	1605	midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1360		1606
@@ -1364,6 +1610,9 @@ static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) · 3 unmodified lines
1364	goto out;	1610	goto out;
1365	}	1611	}
1366		1612
		1613	(op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
		1614	mrioc->active_poll_qcount--;
		1615
1367	memset(&delq_req, 0, sizeof(delq_req));	1616	memset(&delq_req, 0, sizeof(delq_req));
1368	mutex_lock(&mrioc->init_cmds.mutex);	1617	mutex_lock(&mrioc->init_cmds.mutex);
1369	if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {	1618	if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
@@ -1389,13 +1638,9 @@ static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) · 19 unmodified lines
1389	wait_for_completion_timeout(&mrioc->init_cmds.done,	1638	wait_for_completion_timeout(&mrioc->init_cmds.done,
1390	(MPI3MR_INTADMCMD_TIMEOUT * HZ));	1639	(MPI3MR_INTADMCMD_TIMEOUT * HZ));
1391	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {	1640	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1392	ioc_err(mrioc, "Issue DelRepQ: command timed out\n");	1641	ioc_err(mrioc, "delete reply queue timed out\n");
1393	mpi3mr_set_diagsave(mrioc);	1642	mpi3mr_check_rh_fault_ioc(mrioc,
1394	mpi3mr_issue_reset(mrioc,
1395	MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
1396	MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);	1643	MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1397	mrioc->unrecoverable = 1;
1398
1399	retval = -1;	1644	retval = -1;
1400	goto out_unlock;	1645	goto out_unlock;
1401	}	1646	}
@@ -1565,6 +1810,8 @@ static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) · 163 unmodified lines
1565		1810
1566	reply_qid = qidx + 1;	1811	reply_qid = qidx + 1;
1567	op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;	1812	op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
		1813	if (!mrioc->pdev->revision)
		1814	op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
1568	op_reply_q->ci = 0;	1815	op_reply_q->ci = 0;
1569	op_reply_q->ephase = 1;	1816	op_reply_q->ephase = 1;
1570	atomic_set(&op_reply_q->pend_ios, 0);	1817	atomic_set(&op_reply_q->pend_ios, 0);
@@ -1592,8 +1839,26 @@ static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) · 21 unmodified lines
1592	create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);	1839	create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1593	create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;	1840	create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
1594	create_req.queue_id = cpu_to_le16(reply_qid);	1841	create_req.queue_id = cpu_to_le16(reply_qid);
1595	create_req.flags = MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;	1842
1596	create_req.msix_index = cpu_to_le16(mrioc->intr_info[midx].msix_index);	1843	if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
		1844	op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
		1845	else
		1846	op_reply_q->qtype = MPI3MR_POLL_QUEUE;
		1847
		1848	if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
		1849	create_req.flags =
		1850	MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
		1851	create_req.msix_index =
		1852	cpu_to_le16(mrioc->intr_info[midx].msix_index);
		1853	} else {
		1854	create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
		1855	ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
		1856	reply_qid, midx);
		1857	if (!mrioc->active_poll_qcount)
		1858	disable_irq_nosync(pci_irq_vector(mrioc->pdev,
		1859	mrioc->intr_info_count - 1));
		1860	}
		1861
1597	if (mrioc->enable_segqueue) {	1862	if (mrioc->enable_segqueue) {
1598	create_req.flags \|=	1863	create_req.flags \|=
1599	MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;	1864	MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
@@ -1615,12 +1880,9 @@ static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) · 15 unmodified lines
1615	wait_for_completion_timeout(&mrioc->init_cmds.done,	1880	wait_for_completion_timeout(&mrioc->init_cmds.done,
1616	(MPI3MR_INTADMCMD_TIMEOUT * HZ));	1881	(MPI3MR_INTADMCMD_TIMEOUT * HZ));
1617	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {	1882	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1618	ioc_err(mrioc, "CreateRepQ: command timed out\n");	1883	ioc_err(mrioc, "create reply queue timed out\n");
1619	mpi3mr_set_diagsave(mrioc);	1884	mpi3mr_check_rh_fault_ioc(mrioc,
1620	mpi3mr_issue_reset(mrioc,
1621	MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
1622	MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);	1885	MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
1623	mrioc->unrecoverable = 1;
1624	retval = -1;	1886	retval = -1;
1625	goto out_unlock;	1887	goto out_unlock;
1626	}	1888	}
@@ -1634,7 +1896,11 @@ static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) · 7 unmodified lines
1634	goto out_unlock;	1896	goto out_unlock;
1635	}	1897	}
1636	op_reply_q->qid = reply_qid;	1898	op_reply_q->qid = reply_qid;
1637	mrioc->intr_info[midx].op_reply_q = op_reply_q;	1899	if (midx < mrioc->intr_info_count)
		1900	mrioc->intr_info[midx].op_reply_q = op_reply_q;
		1901
		1902	(op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
		1903	mrioc->active_poll_qcount++;
1638		1904
1639	out_unlock:	1905	out_unlock:
1640	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;	1906	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
@@ -1722,12 +1988,9 @@ static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx, · 81 unmodified lines
1722	wait_for_completion_timeout(&mrioc->init_cmds.done,	1988	wait_for_completion_timeout(&mrioc->init_cmds.done,
1723	(MPI3MR_INTADMCMD_TIMEOUT * HZ));	1989	(MPI3MR_INTADMCMD_TIMEOUT * HZ));
1724	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {	1990	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1725	ioc_err(mrioc, "CreateReqQ: command timed out\n");	1991	ioc_err(mrioc, "create request queue timed out\n");
1726	mpi3mr_set_diagsave(mrioc);	1992	mpi3mr_check_rh_fault_ioc(mrioc,
1727	if (mpi3mr_issue_reset(mrioc,	1993	MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
1728	MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
1729	MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT))
1730	mrioc->unrecoverable = 1;
1731	retval = -1;	1994	retval = -1;
1732	goto out_unlock;	1995	goto out_unlock;
1733	}	1996	}
@@ -1771,8 +2034,13 @@ static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc) · 37 unmodified lines
1771	mrioc->intr_info_count - mrioc->op_reply_q_offset;	2034	mrioc->intr_info_count - mrioc->op_reply_q_offset;
1772	if (!mrioc->num_queues)	2035	if (!mrioc->num_queues)
1773	mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);	2036	mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
1774	num_queues = mrioc->num_queues;	2037	/*
1775	ioc_info(mrioc, "Trying to create %d Operational Q pairs\n",	2038	* During reset set the num_queues to the number of queues
		2039	* that was set before the reset.
		2040	*/
		2041	num_queues = mrioc->num_op_reply_q ?
		2042	mrioc->num_op_reply_q : mrioc->num_queues;
		2043	ioc_info(mrioc, "trying to create %d operational queue pairs\n",
1776	num_queues);	2044	num_queues);
1777		2045
1778	if (!mrioc->req_qinfo) {	2046	if (!mrioc->req_qinfo) {
@@ -1814,8 +2082,10 @@ static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc) · 35 unmodified lines
1814	goto out_failed;	2082	goto out_failed;
1815	}	2083	}
1816	mrioc->num_op_reply_q = mrioc->num_op_req_q = i;	2084	mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
1817	ioc_info(mrioc, "Successfully created %d Operational Q pairs\n",	2085	ioc_info(mrioc,
1818	mrioc->num_op_reply_q);	2086	"successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
		2087	mrioc->num_op_reply_q, mrioc->default_qcount,
		2088	mrioc->active_poll_qcount);
1819		2089
1820	return retval;	2090	return retval;
1821	out_failed:	2091	out_failed:
@@ -1863,7 +2133,7 @@ int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, · 41 unmodified lines
1863	if (mpi3mr_check_req_qfull(op_req_q)) {	2133	if (mpi3mr_check_req_qfull(op_req_q)) {
1864	midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(	2134	midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
1865	reply_qidx, mrioc->op_reply_q_offset);	2135	reply_qidx, mrioc->op_reply_q_offset);
1866	mpi3mr_process_op_reply_q(mrioc, &mrioc->intr_info[midx]);	2136	mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
1867		2137
1868	if (mpi3mr_check_req_qfull(op_req_q)) {	2138	if (mpi3mr_check_req_qfull(op_req_q)) {
1869	retval = -EAGAIN;	2139	retval = -EAGAIN;
@@ -1900,6 +2170,42 @@ out: · 30 unmodified lines
1900	return retval;	2170	return retval;
1901	}	2171	}
1902		2172
		2173	/**
		2174	* mpi3mr_check_rh_fault_ioc - check reset history and fault
		2175	* controller
		2176	* @mrioc: Adapter instance reference
		2177	* @reason_code, reason code for the fault.
		2178	*
		2179	* This routine will save snapdump and fault the controller with
		2180	* the given reason code if it is not already in the fault or
		2181	* not asynchronosuly reset. This will be used to handle
		2182	* initilaization time faults/resets/timeout as in those cases
		2183	* immediate soft reset invocation is not required.
		2184	*
		2185	* Return: None.
		2186	*/
		2187	void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
		2188	{
		2189	u32 ioc_status, host_diagnostic, timeout;
		2190
		2191	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
		2192	if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) \|\|
		2193	(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
		2194	mpi3mr_print_fault_info(mrioc);
		2195	return;
		2196	}
		2197	mpi3mr_set_diagsave(mrioc);
		2198	mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
		2199	reason_code);
		2200	timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
		2201	do {
		2202	host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
		2203	if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
		2204	break;
		2205	msleep(100);
		2206	} while (--timeout);
		2207	}
		2208
1903	/**	2209	/**
1904	* mpi3mr_sync_timestamp - Issue time stamp sync request	2210	* mpi3mr_sync_timestamp - Issue time stamp sync request
1905	* @mrioc: Adapter reference	2211	* @mrioc: Adapter reference
@@ -1945,8 +2251,9 @@ static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc) · 39 unmodified lines
1945	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {	2251	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1946	ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");	2252	ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
1947	mrioc->init_cmds.is_waiting = 0;	2253	mrioc->init_cmds.is_waiting = 0;
1948	mpi3mr_soft_reset_handler(mrioc,	2254	if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
1949	MPI3MR_RESET_FROM_TSU_TIMEOUT, 1);	2255	mpi3mr_soft_reset_handler(mrioc,
		2256	MPI3MR_RESET_FROM_TSU_TIMEOUT, 1);
1950	retval = -1;	2257	retval = -1;
1951	goto out_unlock;	2258	goto out_unlock;
1952	}	2259	}
@@ -1969,65 +2276,166 @@ out: · 16 unmodified lines
1969	}	2276	}
1970		2277
1971	/**	2278	/**
1972	* mpi3mr_watchdog_work - watchdog thread to monitor faults	2279	* mpi3mr_print_pkg_ver - display controller fw package version
1973	* @work: work struct	2280	* @mrioc: Adapter reference
1974	*	2281	*
1975	* Watch dog work periodically executed (1 second interval) to	2282	* Retrieve firmware package version from the component image
1976	* monitor firmware fault and to issue periodic timer sync to	2283	* header of the controller flash and display it.
1977	* the firmware.
1978	*	2284	*
1979	* Return: Nothing.	2285	* Return: 0 on success and non-zero on failure.
1980	*/	2286	*/
1981	static void mpi3mr_watchdog_work(struct work_struct *work)	2287	static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
1982	{	2288	{
1983	struct mpi3mr_ioc *mrioc =	2289	struct mpi3_ci_upload_request ci_upload;
1984	container_of(work, struct mpi3mr_ioc, watchdog_work.work);	2290	int retval = -1;
1985	unsigned long flags;	2291	void *data = NULL;
1986	enum mpi3mr_iocstate ioc_state;	2292	dma_addr_t data_dma;
1987	u32 fault, host_diagnostic;	2293	struct mpi3_ci_manifest_mpi *manifest;
		2294	u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
		2295	u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
		2296
		2297	data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
		2298	GFP_KERNEL);
		2299	if (!data)
		2300	return -ENOMEM;
		2301
		2302	memset(&ci_upload, 0, sizeof(ci_upload));
		2303	mutex_lock(&mrioc->init_cmds.mutex);
		2304	if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
		2305	ioc_err(mrioc, "sending get package version failed due to command in use\n");
		2306	mutex_unlock(&mrioc->init_cmds.mutex);
		2307	goto out;
		2308	}
		2309	mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
		2310	mrioc->init_cmds.is_waiting = 1;
		2311	mrioc->init_cmds.callback = NULL;
		2312	ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
		2313	ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
		2314	ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
		2315	ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
		2316	ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
		2317	ci_upload.segment_size = cpu_to_le32(data_len);
		2318
		2319	mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
		2320	data_dma);
		2321	init_completion(&mrioc->init_cmds.done);
		2322	retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
		2323	sizeof(ci_upload), 1);
		2324	if (retval) {
		2325	ioc_err(mrioc, "posting get package version failed\n");
		2326	goto out_unlock;
		2327	}
		2328	wait_for_completion_timeout(&mrioc->init_cmds.done,
		2329	(MPI3MR_INTADMCMD_TIMEOUT * HZ));
		2330	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
		2331	ioc_err(mrioc, "get package version timed out\n");
		2332	mpi3mr_check_rh_fault_ioc(mrioc,
		2333	MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
		2334	retval = -1;
		2335	goto out_unlock;
		2336	}
		2337	if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
		2338	== MPI3_IOCSTATUS_SUCCESS) {
		2339	manifest = (struct mpi3_ci_manifest_mpi *) data;
		2340	if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
		2341	ioc_info(mrioc,
		2342	"firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
		2343	manifest->package_version.gen_major,
		2344	manifest->package_version.gen_minor,
		2345	manifest->package_version.phase_major,
		2346	manifest->package_version.phase_minor,
		2347	manifest->package_version.customer_id,
		2348	manifest->package_version.build_num);
		2349	}
		2350	}
		2351	retval = 0;
		2352	out_unlock:
		2353	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
		2354	mutex_unlock(&mrioc->init_cmds.mutex);
		2355
		2356	out:
		2357	if (data)
		2358	dma_free_coherent(&mrioc->pdev->dev, data_len, data,
		2359	data_dma);
		2360	return retval;
		2361	}
		2362
		2363	/**
		2364	* mpi3mr_watchdog_work - watchdog thread to monitor faults
		2365	* @work: work struct
		2366	*
		2367	* Watch dog work periodically executed (1 second interval) to
		2368	* monitor firmware fault and to issue periodic timer sync to
		2369	* the firmware.
		2370	*
		2371	* Return: Nothing.
		2372	*/
		2373	static void mpi3mr_watchdog_work(struct work_struct *work)
		2374	{
		2375	struct mpi3mr_ioc *mrioc =
		2376	container_of(work, struct mpi3mr_ioc, watchdog_work.work);
		2377	unsigned long flags;
		2378	enum mpi3mr_iocstate ioc_state;
		2379	u32 fault, host_diagnostic, ioc_status;
		2380	u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
		2381
		2382	if (mrioc->reset_in_progress \|\| mrioc->unrecoverable)
		2383	return;
1988		2384
1989	if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) {	2385	if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) {
1990	mrioc->ts_update_counter = 0;	2386	mrioc->ts_update_counter = 0;
1991	mpi3mr_sync_timestamp(mrioc);	2387	mpi3mr_sync_timestamp(mrioc);
1992	}	2388	}
1993		2389
		2390	if ((mrioc->prepare_for_reset) &&
		2391	((mrioc->prepare_for_reset_timeout_counter++) >=
		2392	MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
		2393	mpi3mr_soft_reset_handler(mrioc,
		2394	MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
		2395	return;
		2396	}
		2397
		2398	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
		2399	if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
		2400	mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
		2401	return;
		2402	}
		2403
1994	/Check for fault state every one second and issue Soft reset/	2404	/Check for fault state every one second and issue Soft reset/
1995	ioc_state = mpi3mr_get_iocstate(mrioc);	2405	ioc_state = mpi3mr_get_iocstate(mrioc);
1996	if (ioc_state == MRIOC_STATE_FAULT) {	2406	if (ioc_state != MRIOC_STATE_FAULT)
1997	fault = readl(&mrioc->sysif_regs->fault) &	2407	goto schedule_work;
1998	MPI3_SYSIF_FAULT_CODE_MASK;
1999	host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2000	if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2001	if (!mrioc->diagsave_timeout) {
2002	mpi3mr_print_fault_info(mrioc);
2003	ioc_warn(mrioc, "Diag save in progress\n");
2004	}
2005	if ((mrioc->diagsave_timeout++) <=
2006	MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2007	goto schedule_work;
2008	} else
2009	mpi3mr_print_fault_info(mrioc);
2010	mrioc->diagsave_timeout = 0;
2011		2408
2012	if (fault == MPI3_SYSIF_FAULT_CODE_FACTORY_RESET) {	2409	fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2013	ioc_info(mrioc,	2410	host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2014	"Factory Reset fault occurred marking controller as unrecoverable"	2411	if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2015	);	2412	if (!mrioc->diagsave_timeout) {
2016	mrioc->unrecoverable = 1;	2413	mpi3mr_print_fault_info(mrioc);
2017	goto out;	2414	ioc_warn(mrioc, "diag save in progress\n");
2018	}	2415	}
		2416	if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
		2417	goto schedule_work;
		2418	}
2019		2419
2020	if ((fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) \|\|	2420	mpi3mr_print_fault_info(mrioc);
2021	(fault == MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS) \|\|	2421	mrioc->diagsave_timeout = 0;
2022	(mrioc->reset_in_progress))	2422
2023	goto out;	2423	switch (fault) {
2024	if (fault == MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET)	2424	case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2025	mpi3mr_soft_reset_handler(mrioc,	2425	ioc_info(mrioc,
2026	MPI3MR_RESET_FROM_CIACTIV_FAULT, 0);	2426	"controller requires system power cycle, marking controller as unrecoverable\n");
2027	else	2427	mrioc->unrecoverable = 1;
2028	mpi3mr_soft_reset_handler(mrioc,	2428	return;
2029	MPI3MR_RESET_FROM_FAULT_WATCH, 0);	2429	case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
		2430	return;
		2431	case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
		2432	reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
		2433	break;
		2434	default:
		2435	break;
2030	}	2436	}
		2437	mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
		2438	return;
2031		2439
2032	schedule_work:	2440	schedule_work:
2033	spin_lock_irqsave(&mrioc->watchdog_lock, flags);	2441	spin_lock_irqsave(&mrioc->watchdog_lock, flags);
@@ -2036,7 +2444,6 @@ schedule_work: · 2 unmodified lines
2036	&mrioc->watchdog_work,	2444	&mrioc->watchdog_work,
2037	msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));	2445	msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2038	spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);	2446	spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2039	out:
2040	return;	2447	return;
2041	}	2448	}
2042		2449
@@ -2096,41 +2503,6 @@ void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc) · 53 unmodified lines
2096	}	2503	}
2097	}	2504	}
2098		2505
2099	/**
2100	* mpi3mr_kill_ioc - Kill the controller
2101	* @mrioc: Adapter instance reference
2102	* @reason: reason for the failure.
2103	*
2104	* If fault debug is enabled, display the fault info else issue
2105	* diag fault and freeze the system for controller debug
2106	* purpose.
2107	*
2108	* Return: Nothing.
2109	*/
2110	static void mpi3mr_kill_ioc(struct mpi3mr_ioc *mrioc, u32 reason)
2111	{
2112	enum mpi3mr_iocstate ioc_state;
2113
2114	if (!mrioc->fault_dbg)
2115	return;
2116
2117	dump_stack();
2118
2119	ioc_state = mpi3mr_get_iocstate(mrioc);
2120	if (ioc_state == MRIOC_STATE_FAULT)
2121	mpi3mr_print_fault_info(mrioc);
2122	else {
2123	ioc_err(mrioc, "Firmware is halted due to the reason %d\n",
2124	reason);
2125	mpi3mr_diagfault_reset_handler(mrioc, reason);
2126	}
2127	if (mrioc->fault_dbg == 2)
2128	for (;;)
2129	;
2130	else
2131	panic("panic in %s\n", __func__);
2132	}
2133
2134	/**	2506	/**
2135	* mpi3mr_setup_admin_qpair - Setup admin queue pair	2507	* mpi3mr_setup_admin_qpair - Setup admin queue pair
2136	* @mrioc: Adapter instance reference	2508	* @mrioc: Adapter instance reference
@@ -2258,12 +2630,9 @@ static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc, · 121 unmodified lines
2258	wait_for_completion_timeout(&mrioc->init_cmds.done,	2630	wait_for_completion_timeout(&mrioc->init_cmds.done,
2259	(MPI3MR_INTADMCMD_TIMEOUT * HZ));	2631	(MPI3MR_INTADMCMD_TIMEOUT * HZ));
2260	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {	2632	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2261	ioc_err(mrioc, "Issue IOCFacts: command timed out\n");	2633	ioc_err(mrioc, "ioc_facts timed out\n");
2262	mpi3mr_set_diagsave(mrioc);	2634	mpi3mr_check_rh_fault_ioc(mrioc,
2263	mpi3mr_issue_reset(mrioc,
2264	MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2265	MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);	2635	MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
2266	mrioc->unrecoverable = 1;
2267	retval = -1;	2636	retval = -1;
2268	goto out_unlock;	2637	goto out_unlock;
2269	}	2638	}
@@ -2277,6 +2646,7 @@ static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc, · 7 unmodified lines
2277	goto out_unlock;	2646	goto out_unlock;
2278	}	2647	}
2279	memcpy(facts_data, (u8 *)data, data_len);	2648	memcpy(facts_data, (u8 *)data, data_len);
		2649	mpi3mr_process_factsdata(mrioc, facts_data);
2280	out_unlock:	2650	out_unlock:
2281	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;	2651	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2282	mutex_unlock(&mrioc->init_cmds.mutex);	2652	mutex_unlock(&mrioc->init_cmds.mutex);
@@ -2374,14 +2744,13 @@ static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, · 91 unmodified lines
2374	mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;	2744	mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
2375	mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);	2745	mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
2376	mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);	2746	mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
2377	mrioc->facts.max_pds = le16_to_cpu(facts_data->max_pds);
2378	mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);	2747	mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
2379	mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);	2748	mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
2380	mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_advanced_host_pds);	2749	mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
2381	mrioc->facts.max_raidpds = le16_to_cpu(facts_data->max_raid_pds);	2750	mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
2382	mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);	2751	mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
2383	mrioc->facts.max_pcie_switches =	2752	mrioc->facts.max_pcie_switches =
2384	le16_to_cpu(facts_data->max_pc_ie_switches);	2753	le16_to_cpu(facts_data->max_pcie_switches);
2385	mrioc->facts.max_sasexpanders =	2754	mrioc->facts.max_sasexpanders =
2386	le16_to_cpu(facts_data->max_sas_expanders);	2755	le16_to_cpu(facts_data->max_sas_expanders);
2387	mrioc->facts.max_sasinitiators =	2756	mrioc->facts.max_sasinitiators =
@@ -2415,22 +2784,15 @@ static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, · 27 unmodified lines
2415	mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,	2784	mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
2416	mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);	2785	mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
2417	ioc_info(mrioc,	2786	ioc_info(mrioc,
2418	"maxreqs(%d), mindh(%d) maxPDs(%d) maxvectors(%d) maxperids(%d)\n",	2787	"maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
2419	mrioc->facts.max_reqs, mrioc->facts.min_devhandle,	2788	mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
2420	mrioc->facts.max_pds, mrioc->facts.max_msix_vectors,	2789	mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
2421	mrioc->facts.max_perids);
2422	ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",	2790	ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
2423	mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,	2791	mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
2424	mrioc->facts.sge_mod_shift);	2792	mrioc->facts.sge_mod_shift);
2425	ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x\n",	2793	ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x\n",
2426	mrioc->facts.dma_mask, (facts_flags &	2794	mrioc->facts.dma_mask, (facts_flags &
2427	MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK));	2795	MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK));
2428
2429	mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
2430
2431	if (reset_devices)
2432	mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
2433	MPI3MR_HOST_IOS_KDUMP);
2434	}	2796	}
2435		2797
2436	/**	2798	/**
@@ -2446,23 +2808,29 @@ static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) · 9 unmodified lines
2446	{	2808	{
2447	int retval = 0;	2809	int retval = 0;
2448	u32 sz, i;	2810	u32 sz, i;
2449	dma_addr_t phy_addr;
2450		2811
2451	if (mrioc->init_cmds.reply)	2812	if (mrioc->init_cmds.reply)
2452	goto post_reply_sbuf;	2813	return retval;
2453		2814
2454	mrioc->init_cmds.reply = kzalloc(mrioc->facts.reply_sz, GFP_KERNEL);	2815	mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2455	if (!mrioc->init_cmds.reply)	2816	if (!mrioc->init_cmds.reply)
2456	goto out_failed;	2817	goto out_failed;
2457		2818
2458	for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {	2819	for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
2459	mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->facts.reply_sz,	2820	mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
2460	GFP_KERNEL);	2821	GFP_KERNEL);
2461	if (!mrioc->dev_rmhs_cmds[i].reply)	2822	if (!mrioc->dev_rmhs_cmds[i].reply)
2462	goto out_failed;	2823	goto out_failed;
2463	}	2824	}
2464		2825
2465	mrioc->host_tm_cmds.reply = kzalloc(mrioc->facts.reply_sz, GFP_KERNEL);	2826	for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
		2827	mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
		2828	GFP_KERNEL);
		2829	if (!mrioc->evtack_cmds[i].reply)
		2830	goto out_failed;
		2831	}
		2832
		2833	mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2466	if (!mrioc->host_tm_cmds.reply)	2834	if (!mrioc->host_tm_cmds.reply)
2467	goto out_failed;	2835	goto out_failed;
2468		2836
@@ -2482,13 +2850,21 @@ static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) · 13 unmodified lines
2482	if (!mrioc->devrem_bitmap)	2850	if (!mrioc->devrem_bitmap)
2483	goto out_failed;	2851	goto out_failed;
2484		2852
		2853	mrioc->evtack_cmds_bitmap_sz = MPI3MR_NUM_EVTACKCMD / 8;
		2854	if (MPI3MR_NUM_EVTACKCMD % 8)
		2855	mrioc->evtack_cmds_bitmap_sz++;
		2856	mrioc->evtack_cmds_bitmap = kzalloc(mrioc->evtack_cmds_bitmap_sz,
		2857	GFP_KERNEL);
		2858	if (!mrioc->evtack_cmds_bitmap)
		2859	goto out_failed;
		2860
2485	mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;	2861	mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
2486	mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;	2862	mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
2487	mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;	2863	mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
2488	mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;	2864	mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
2489		2865
2490	/* reply buffer pool, 16 byte align */	2866	/* reply buffer pool, 16 byte align */
2491	sz = mrioc->num_reply_bufs * mrioc->facts.reply_sz;	2867	sz = mrioc->num_reply_bufs * mrioc->reply_sz;
2492	mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",	2868	mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
2493	&mrioc->pdev->dev, sz, 16, 0);	2869	&mrioc->pdev->dev, sz, 16, 0);
2494	if (!mrioc->reply_buf_pool) {	2870	if (!mrioc->reply_buf_pool) {
@@ -2517,7 +2893,7 @@ static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) · 22 unmodified lines
2517	goto out_failed;	2893	goto out_failed;
2518		2894
2519	/* sense buffer pool, 4 byte align */	2895	/* sense buffer pool, 4 byte align */
2520	sz = mrioc->num_sense_bufs * MPI3MR_SENSEBUF_SZ;	2896	sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
2521	mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",	2897	mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
2522	&mrioc->pdev->dev, sz, 4, 0);	2898	&mrioc->pdev->dev, sz, 4, 0);
2523	if (!mrioc->sense_buf_pool) {	2899	if (!mrioc->sense_buf_pool) {
@@ -2542,21 +2918,42 @@ static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) · 18 unmodified lines
2542	if (!mrioc->sense_buf_q)	2918	if (!mrioc->sense_buf_q)
2543	goto out_failed;	2919	goto out_failed;
2544		2920
2545	post_reply_sbuf:	2921	return retval;
2546	sz = mrioc->num_reply_bufs * mrioc->facts.reply_sz;	2922
		2923	out_failed:
		2924	retval = -1;
		2925	return retval;
		2926	}
		2927
		2928	/**
		2929	* mpimr_initialize_reply_sbuf_queues - initialize reply sense
		2930	* buffers
		2931	* @mrioc: Adapter instance reference
		2932	*
		2933	* Helper function to initialize reply and sense buffers along
		2934	* with some debug prints.
		2935	*
		2936	* Return: None.
		2937	*/
		2938	static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
		2939	{
		2940	u32 sz, i;
		2941	dma_addr_t phy_addr;
		2942
		2943	sz = mrioc->num_reply_bufs * mrioc->reply_sz;
2547	ioc_info(mrioc,	2944	ioc_info(mrioc,
2548	"reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",	2945	"reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
2549	mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->facts.reply_sz,	2946	mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
2550	(sz / 1024), (unsigned long long)mrioc->reply_buf_dma);	2947	(sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
2551	sz = mrioc->reply_free_qsz * 8;	2948	sz = mrioc->reply_free_qsz * 8;
2552	ioc_info(mrioc,	2949	ioc_info(mrioc,
2553	"reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",	2950	"reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
2554	mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),	2951	mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
2555	(unsigned long long)mrioc->reply_free_q_dma);	2952	(unsigned long long)mrioc->reply_free_q_dma);
2556	sz = mrioc->num_sense_bufs * MPI3MR_SENSEBUF_SZ;	2953	sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
2557	ioc_info(mrioc,	2954	ioc_info(mrioc,
2558	"sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",	2955	"sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
2559	mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSEBUF_SZ,	2956	mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
2560	(sz / 1024), (unsigned long long)mrioc->sense_buf_dma);	2957	(sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
2561	sz = mrioc->sense_buf_q_sz * 8;	2958	sz = mrioc->sense_buf_q_sz * 8;
2562	ioc_info(mrioc,	2959	ioc_info(mrioc,
@@ -2566,20 +2963,15 @@ post_reply_sbuf: · 3 unmodified lines
2566		2963
2567	/* initialize Reply buffer Queue */	2964	/* initialize Reply buffer Queue */
2568	for (i = 0, phy_addr = mrioc->reply_buf_dma;	2965	for (i = 0, phy_addr = mrioc->reply_buf_dma;
2569	i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->facts.reply_sz)	2966	i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
2570	mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);	2967	mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
2571	mrioc->reply_free_q[i] = cpu_to_le64(0);	2968	mrioc->reply_free_q[i] = cpu_to_le64(0);
2572		2969
2573	/* initialize Sense Buffer Queue */	2970	/* initialize Sense Buffer Queue */
2574	for (i = 0, phy_addr = mrioc->sense_buf_dma;	2971	for (i = 0, phy_addr = mrioc->sense_buf_dma;
2575	i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSEBUF_SZ)	2972	i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
2576	mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);	2973	mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
2577	mrioc->sense_buf_q[i] = cpu_to_le64(0);	2974	mrioc->sense_buf_q[i] = cpu_to_le64(0);
2578	return retval;
2579
2580	out_failed:
2581	retval = -1;
2582	return retval;
2583	}	2975	}
2584		2976
2585	/**	2977	/**
@@ -2606,6 +2998,8 @@ static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc) · 20 unmodified lines
2606	retval = -1;	2998	retval = -1;
2607	goto out;	2999	goto out;
2608	}	3000	}
		3001	mpimr_initialize_reply_sbuf_queues(mrioc);
		3002
2609	drv_info->information_length = cpu_to_le32(data_len);	3003	drv_info->information_length = cpu_to_le32(data_len);
2610	strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));	3004	strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
2611	strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));	3005	strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
@@ -2639,7 +3033,7 @@ static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc) · 27 unmodified lines
2639	iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);	3033	iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
2640	iocinit_req.reply_free_queue_address =	3034	iocinit_req.reply_free_queue_address =
2641	cpu_to_le64(mrioc->reply_free_q_dma);	3035	cpu_to_le64(mrioc->reply_free_q_dma);
2642	iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSEBUF_SZ);	3036	iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
2643	iocinit_req.sense_buffer_free_queue_depth =	3037	iocinit_req.sense_buffer_free_queue_depth =
2644	cpu_to_le16(mrioc->sense_buf_q_sz);	3038	cpu_to_le16(mrioc->sense_buf_q_sz);
2645	iocinit_req.sense_buffer_free_queue_address =	3039	iocinit_req.sense_buffer_free_queue_address =
@@ -2659,12 +3053,9 @@ static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc) · 13 unmodified lines
2659	wait_for_completion_timeout(&mrioc->init_cmds.done,	3053	wait_for_completion_timeout(&mrioc->init_cmds.done,
2660	(MPI3MR_INTADMCMD_TIMEOUT * HZ));	3054	(MPI3MR_INTADMCMD_TIMEOUT * HZ));
2661	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {	3055	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2662	mpi3mr_set_diagsave(mrioc);	3056	mpi3mr_check_rh_fault_ioc(mrioc,
2663	mpi3mr_issue_reset(mrioc,
2664	MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2665	MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);	3057	MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
2666	mrioc->unrecoverable = 1;	3058	ioc_err(mrioc, "ioc_init timed out\n");
2667	ioc_err(mrioc, "Issue IOCInit: command timed out\n");
2668	retval = -1;	3059	retval = -1;
2669	goto out_unlock;	3060	goto out_unlock;
2670	}	3061	}
@@ -2678,6 +3069,13 @@ static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc) · 7 unmodified lines
2678	goto out_unlock;	3069	goto out_unlock;
2679	}	3070	}
2680		3071
		3072	mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
		3073	writel(mrioc->reply_free_queue_host_index,
		3074	&mrioc->sysif_regs->reply_free_host_index);
		3075
		3076	mrioc->sbq_host_index = mrioc->num_sense_bufs;
		3077	writel(mrioc->sbq_host_index,
		3078	&mrioc->sysif_regs->sense_buffer_free_host_index);
2681	out_unlock:	3079	out_unlock:
2682	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;	3080	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2683	mutex_unlock(&mrioc->init_cmds.mutex);	3081	mutex_unlock(&mrioc->init_cmds.mutex);
@@ -2755,12 +3153,9 @@ static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc) · 71 unmodified lines
2755	wait_for_completion_timeout(&mrioc->init_cmds.done,	3153	wait_for_completion_timeout(&mrioc->init_cmds.done,
2756	(MPI3MR_INTADMCMD_TIMEOUT * HZ));	3154	(MPI3MR_INTADMCMD_TIMEOUT * HZ));
2757	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {	3155	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2758	ioc_err(mrioc, "Issue EvtNotify: command timed out\n");	3156	ioc_err(mrioc, "event notification timed out\n");
2759	mpi3mr_set_diagsave(mrioc);	3157	mpi3mr_check_rh_fault_ioc(mrioc,
2760	mpi3mr_issue_reset(mrioc,
2761	MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2762	MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);	3158	MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
2763	mrioc->unrecoverable = 1;
2764	retval = -1;	3159	retval = -1;
2765	goto out_unlock;	3160	goto out_unlock;
2766	}	3161	}
@@ -2782,17 +3177,17 @@ out: · 15 unmodified lines
2782	}	3177	}
2783		3178
2784	/**	3179	/**
2785	* mpi3mr_send_event_ack - Send event acknowledgment	3180	* mpi3mr_process_event_ack - Process event acknowledgment
2786	* @mrioc: Adapter instance reference	3181	* @mrioc: Adapter instance reference
2787	* @event: MPI3 event ID	3182	* @event: MPI3 event ID
2788	* @event_ctx: Event context	3183	* @event_ctx: event context
2789	*	3184	*
2790	* Send event acknowledgment through admin queue and wait for	3185	* Send event acknowledgment through admin queue and wait for
2791	* it to complete.	3186	* it to complete.
2792	*	3187	*
2793	* Return: 0 on success, non-zero on failures.	3188	* Return: 0 on success, non-zero on failures.
2794	*/	3189	*/
2795	int mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event,	3190	int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
2796	u32 event_ctx)	3191	u32 event_ctx)
2797	{	3192	{
2798	struct mpi3_event_ack_request evtack_req;	3193	struct mpi3_event_ack_request evtack_req;
@@ -2825,8 +3220,9 @@ int mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event, · 26 unmodified lines
2825	(MPI3MR_INTADMCMD_TIMEOUT * HZ));	3220	(MPI3MR_INTADMCMD_TIMEOUT * HZ));
2826	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {	3221	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2827	ioc_err(mrioc, "Issue EvtNotify: command timed out\n");	3222	ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
2828	mpi3mr_soft_reset_handler(mrioc,	3223	if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2829	MPI3MR_RESET_FROM_EVTACK_TIMEOUT, 1);	3224	mpi3mr_soft_reset_handler(mrioc,
		3225	MPI3MR_RESET_FROM_EVTACK_TIMEOUT, 1);
2830	retval = -1;	3226	retval = -1;
2831	goto out_unlock;	3227	goto out_unlock;
2832	}	3228	}
@@ -2863,6 +3259,9 @@ static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc) · 30 unmodified lines
2863	u32 sz, i;	3259	u32 sz, i;
2864	u16 num_chains;	3260	u16 num_chains;
2865		3261
		3262	if (mrioc->chain_sgl_list)
		3263	return retval;
		3264
2866	num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;	3265	num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
2867		3266
2868	if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION	3267	if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
@@ -2966,29 +3365,28 @@ int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async) · 97 unmodified lines
2966	ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");	3365	ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
2967	goto out_unlock;	3366	goto out_unlock;
2968	}	3367	}
2969	if (!async) {	3368	if (async) {
2970	wait_for_completion_timeout(&mrioc->init_cmds.done,	3369	mutex_unlock(&mrioc->init_cmds.mutex);
2971	(pe_timeout * HZ));	3370	goto out;
2972	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2973	ioc_err(mrioc, "Issue PortEnable: command timed out\n");
2974	retval = -1;
2975	mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
2976	mpi3mr_set_diagsave(mrioc);
2977	mpi3mr_issue_reset(mrioc,
2978	MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2979	MPI3MR_RESET_FROM_PE_TIMEOUT);
2980	mrioc->unrecoverable = 1;
2981	goto out_unlock;
2982	}
2983	mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
2984	}	3371	}
		3372
		3373	wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
		3374	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
		3375	ioc_err(mrioc, "port enable timed out\n");
		3376	retval = -1;
		3377	mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
		3378	goto out_unlock;
		3379	}
		3380	mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
		3381
2985	out_unlock:	3382	out_unlock:
		3383	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2986	mutex_unlock(&mrioc->init_cmds.mutex);	3384	mutex_unlock(&mrioc->init_cmds.mutex);
2987	out:	3385	out:
2988	return retval;	3386	return retval;
2989	}	3387	}
2990		3388
2991	/* Protocol type to name mapper structure*/	3389	/* Protocol type to name mapper structure */
2992	static const struct {	3390	static const struct {
2993	u8 protocol;	3391	u8 protocol;
2994	char *name;	3392	char *name;
@@ -3181,6 +3579,10 @@ int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc) · 186 unmodified lines
3181	mrioc->sysif_regs, memap_sz);	3579	mrioc->sysif_regs, memap_sz);
3182	ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",	3580	ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
3183	mrioc->msix_count);	3581	mrioc->msix_count);
		3582
		3583	if (!reset_devices && poll_queues > 0)
		3584	mrioc->requested_poll_qcount = min_t(int, poll_queues,
		3585	mrioc->msix_count - 2);
3184	return retval;	3586	return retval;
3185		3587
3186	out_failed:	3588	out_failed:
@@ -3188,6 +3590,46 @@ out_failed: · 1 unmodified line
3188	return retval;	3590	return retval;
3189	}	3591	}
3190		3592
		3593	/**
		3594	* mpi3mr_enable_events - Enable required events
		3595	* @mrioc: Adapter instance reference
		3596	*
		3597	* This routine unmasks the events required by the driver by
		3598	* sennding appropriate event mask bitmapt through an event
		3599	* notification request.
		3600	*
		3601	* Return: 0 on success and non-zero on failure.
		3602	*/
		3603	static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
		3604	{
		3605	int retval = 0;
		3606	u32 i;
		3607
		3608	for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
		3609	mrioc->event_masks[i] = -1;
		3610
		3611	mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
		3612	mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
		3613	mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
		3614	mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
		3615	mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
		3616	mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
		3617	mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
		3618	mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
		3619	mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
		3620	mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
		3621	mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
		3622	mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
		3623	mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
		3624	mpi3mr_unmask_events(mrioc, MPI3_EVENT_TEMP_THRESHOLD);
		3625
		3626	retval = mpi3mr_issue_event_notification(mrioc);
		3627	if (retval)
		3628	ioc_err(mrioc, "failed to issue event notification %d\n",
		3629	retval);
		3630	return retval;
		3631	}
		3632
3191	/**	3633	/**
3192	* mpi3mr_init_ioc - Initialize the controller	3634	* mpi3mr_init_ioc - Initialize the controller
3193	* @mrioc: Adapter instance reference	3635	* @mrioc: Adapter instance reference
@@ -3204,227 +3646,240 @@ out_failed: · 10 unmodified lines
3204	*	3646	*
3205	* Return: 0 on success and non-zero on failure.	3647	* Return: 0 on success and non-zero on failure.
3206	*/	3648	*/
3207	int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc, u8 init_type)	3649	int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
3208	{	3650	{
3209	int retval = 0;	3651	int retval = 0;
3210	enum mpi3mr_iocstate ioc_state;	3652	u8 retry = 0;
3211	u64 base_info;
3212	u32 timeout;
3213	u32 ioc_status, ioc_config, i;
3214	struct mpi3_ioc_facts_data facts_data;	3653	struct mpi3_ioc_facts_data facts_data;
3215		3654
3216	mrioc->irqpoll_sleep = MPI3MR_IRQ_POLL_SLEEP;	3655	retry_init:
3217	mrioc->change_count = 0;	3656	retval = mpi3mr_bring_ioc_ready(mrioc);
3218	if (init_type == MPI3MR_IT_INIT) {	3657	if (retval) {
3219	mrioc->cpu_count = num_online_cpus();	3658	ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
3220	retval = mpi3mr_setup_resources(mrioc);	3659	retval);
3221	if (retval) {	3660	goto out_failed_noretry;
3222	ioc_err(mrioc, "Failed to setup resources:error %d\n",
3223	retval);
3224	goto out_nocleanup;
3225	}
3226	}	3661	}
3227		3662
3228	ioc_status = readl(&mrioc->sysif_regs->ioc_status);	3663	retval = mpi3mr_setup_isr(mrioc, 1);
3229	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);	3664	if (retval) {
		3665	ioc_err(mrioc, "Failed to setup ISR error %d\n",
		3666	retval);
		3667	goto out_failed_noretry;
		3668	}
3230		3669
3231	ioc_info(mrioc, "SOD status %x configuration %x\n",	3670	retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3232	ioc_status, ioc_config);	3671	if (retval) {
		3672	ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
		3673	retval);
		3674	goto out_failed;
		3675	}
3233		3676
3234	base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);	3677	mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
3235	ioc_info(mrioc, "SOD base_info %llx\n", base_info);
3236		3678
3237	/The timeout value is in 2sec unit, changing it to seconds/	3679	if (reset_devices)
3238	mrioc->ready_timeout =	3680	mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
3239	((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>	3681	MPI3MR_HOST_IOS_KDUMP);
3240	MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
3241		3682
3242	ioc_info(mrioc, "IOC ready timeout %d\n", mrioc->ready_timeout);	3683	mrioc->reply_sz = mrioc->facts.reply_sz;
3243		3684
3244	ioc_state = mpi3mr_get_iocstate(mrioc);	3685	retval = mpi3mr_check_reset_dma_mask(mrioc);
3245	ioc_info(mrioc, "IOC in %s state during detection\n",	3686	if (retval) {
3246	mpi3mr_iocstate_name(ioc_state));	3687	ioc_err(mrioc, "Resetting dma mask failed %d\n",
		3688	retval);
		3689	goto out_failed_noretry;
		3690	}
3247		3691
3248	if (ioc_state == MRIOC_STATE_BECOMING_READY \|\|	3692	mpi3mr_print_ioc_info(mrioc);
3249	ioc_state == MRIOC_STATE_RESET_REQUESTED) {
3250	timeout = mrioc->ready_timeout * 10;
3251	do {
3252	msleep(100);
3253	} while (--timeout);
3254		3693
3255	ioc_state = mpi3mr_get_iocstate(mrioc);	3694	retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
3256	ioc_info(mrioc,	3695	if (retval) {
3257	"IOC in %s state after waiting for reset time\n",	3696	ioc_err(mrioc,
3258	mpi3mr_iocstate_name(ioc_state));	3697	"%s :Failed to allocated reply sense buffers %d\n",
		3698	__func__, retval);
		3699	goto out_failed_noretry;
3259	}	3700	}
3260		3701
3261	if (ioc_state == MRIOC_STATE_READY) {	3702	retval = mpi3mr_alloc_chain_bufs(mrioc);
3262	retval = mpi3mr_issue_and_process_mur(mrioc,	3703	if (retval) {
3263	MPI3MR_RESET_FROM_BRINGUP);	3704	ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
3264	if (retval) {	3705	retval);
3265	ioc_err(mrioc, "Failed to MU reset IOC error %d\n",	3706	goto out_failed_noretry;
3266	retval);
3267	}
3268	ioc_state = mpi3mr_get_iocstate(mrioc);
3269	}	3707	}
3270	if (ioc_state != MRIOC_STATE_RESET) {	3708
3271	mpi3mr_print_fault_info(mrioc);	3709	retval = mpi3mr_issue_iocinit(mrioc);
3272	retval = mpi3mr_issue_reset(mrioc,	3710	if (retval) {
3273	MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,	3711	ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
3274	MPI3MR_RESET_FROM_BRINGUP);	3712	retval);
3275	if (retval) {	3713	goto out_failed;
3276	ioc_err(mrioc,
3277	"%s :Failed to soft reset IOC error %d\n",
3278	__func__, retval);
3279	goto out_failed;
3280	}
3281	}	3714	}
3282	ioc_state = mpi3mr_get_iocstate(mrioc);	3715
3283	if (ioc_state != MRIOC_STATE_RESET) {	3716	retval = mpi3mr_print_pkg_ver(mrioc);
3284	retval = -1;	3717	if (retval) {
3285	ioc_err(mrioc, "Cannot bring IOC to reset state\n");	3718	ioc_err(mrioc, "failed to get package version\n");
3286	goto out_failed;	3719	goto out_failed;
3287	}	3720	}
3288		3721
3289	retval = mpi3mr_setup_admin_qpair(mrioc);	3722	retval = mpi3mr_setup_isr(mrioc, 0);
3290	if (retval) {	3723	if (retval) {
3291	ioc_err(mrioc, "Failed to setup admin Qs: error %d\n",	3724	ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
		3725	retval);
		3726	goto out_failed_noretry;
		3727	}
		3728
		3729	retval = mpi3mr_create_op_queues(mrioc);
		3730	if (retval) {
		3731	ioc_err(mrioc, "Failed to create OpQueues error %d\n",
3292	retval);	3732	retval);
3293	goto out_failed;	3733	goto out_failed;
3294	}	3734	}
3295		3735
3296	retval = mpi3mr_bring_ioc_ready(mrioc);	3736	retval = mpi3mr_enable_events(mrioc);
3297	if (retval) {	3737	if (retval) {
3298	ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",	3738	ioc_err(mrioc, "failed to enable events %d\n",
3299	retval);	3739	retval);
3300	goto out_failed;	3740	goto out_failed;
3301	}	3741	}
3302		3742
3303	if (init_type != MPI3MR_IT_RESET) {	3743	ioc_info(mrioc, "controller initialization completed successfully\n");
		3744	return retval;
		3745	out_failed:
		3746	if (retry < 2) {
		3747	retry++;
		3748	ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
		3749	retry);
		3750	mpi3mr_memset_buffers(mrioc);
		3751	goto retry_init;
		3752	}
		3753	out_failed_noretry:
		3754	ioc_err(mrioc, "controller initialization failed\n");
		3755	mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
		3756	MPI3MR_RESET_FROM_CTLR_CLEANUP);
		3757	mrioc->unrecoverable = 1;
		3758	return retval;
		3759	}
		3760
		3761	/**
		3762	* mpi3mr_reinit_ioc - Re-Initialize the controller
		3763	* @mrioc: Adapter instance reference
		3764	* @is_resume: Called from resume or reset path
		3765	*
		3766	* This the controller re-initialization routine, executed from
		3767	* the soft reset handler or resume callback. Creates
		3768	* operational reply queue pairs, allocate required memory for
		3769	* reply pool, sense buffer pool, issue IOC init request to the
		3770	* firmware, unmask the events and issue port enable to discover
		3771	* SAS/SATA/NVMe devices and RAID volumes.
		3772	*
		3773	* Return: 0 on success and non-zero on failure.
		3774	*/
		3775	int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
		3776	{
		3777	int retval = 0;
		3778	u8 retry = 0;
		3779	struct mpi3_ioc_facts_data facts_data;
		3780
		3781	retry_init:
		3782	dprint_reset(mrioc, "bringing up the controller to ready state\n");
		3783	retval = mpi3mr_bring_ioc_ready(mrioc);
		3784	if (retval) {
		3785	ioc_err(mrioc, "failed to bring to ready state\n");
		3786	goto out_failed_noretry;
		3787	}
		3788
		3789	if (is_resume) {
		3790	dprint_reset(mrioc, "setting up single ISR\n");
3304	retval = mpi3mr_setup_isr(mrioc, 1);	3791	retval = mpi3mr_setup_isr(mrioc, 1);
3305	if (retval) {	3792	if (retval) {
3306	ioc_err(mrioc, "Failed to setup ISR error %d\n",	3793	ioc_err(mrioc, "failed to setup ISR\n");
3307	retval);	3794	goto out_failed_noretry;
3308	goto out_failed;
3309	}	3795	}
3310	} else	3796	} else
3311	mpi3mr_ioc_enable_intr(mrioc);	3797	mpi3mr_ioc_enable_intr(mrioc);
3312		3798
		3799	dprint_reset(mrioc, "getting ioc_facts\n");
3313	retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);	3800	retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3314	if (retval) {	3801	if (retval) {
3315	ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",	3802	ioc_err(mrioc, "failed to get ioc_facts\n");
3316	retval);
3317	goto out_failed;	3803	goto out_failed;
3318	}	3804	}
3319		3805
3320	mpi3mr_process_factsdata(mrioc, &facts_data);	3806	dprint_reset(mrioc, "validating ioc_facts\n");
3321	if (init_type == MPI3MR_IT_INIT) {	3807	retval = mpi3mr_revalidate_factsdata(mrioc);
3322	retval = mpi3mr_check_reset_dma_mask(mrioc);	3808	if (retval) {
3323	if (retval) {	3809	ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
3324	ioc_err(mrioc, "Resetting dma mask failed %d\n",	3810	goto out_failed_noretry;
3325	retval);
3326	goto out_failed;
3327	}
3328	}	3811	}
3329		3812
3330	mpi3mr_print_ioc_info(mrioc);	3813	mpi3mr_print_ioc_info(mrioc);
3331		3814
3332	retval = mpi3mr_alloc_reply_sense_bufs(mrioc);	3815	dprint_reset(mrioc, "sending ioc_init\n");
		3816	retval = mpi3mr_issue_iocinit(mrioc);
3333	if (retval) {	3817	if (retval) {
3334	ioc_err(mrioc,	3818	ioc_err(mrioc, "failed to send ioc_init\n");
3335	"%s :Failed to allocated reply sense buffers %d\n",
3336	__func__, retval);
3337	goto out_failed;	3819	goto out_failed;
3338	}	3820	}
3339		3821
3340	if (init_type == MPI3MR_IT_INIT) {	3822	dprint_reset(mrioc, "getting package version\n");
3341	retval = mpi3mr_alloc_chain_bufs(mrioc);	3823	retval = mpi3mr_print_pkg_ver(mrioc);
3342	if (retval) {
3343	ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
3344	retval);
3345	goto out_failed;
3346	}
3347	}
3348
3349	retval = mpi3mr_issue_iocinit(mrioc);
3350	if (retval) {	3824	if (retval) {
3351	ioc_err(mrioc, "Failed to Issue IOC Init %d\n",	3825	ioc_err(mrioc, "failed to get package version\n");
3352	retval);
3353	goto out_failed;	3826	goto out_failed;
3354	}	3827	}
3355	mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3356	writel(mrioc->reply_free_queue_host_index,
3357	&mrioc->sysif_regs->reply_free_host_index);
3358		3828
3359	mrioc->sbq_host_index = mrioc->num_sense_bufs;	3829	if (is_resume) {
3360	writel(mrioc->sbq_host_index,	3830	dprint_reset(mrioc, "setting up multiple ISR\n");
3361	&mrioc->sysif_regs->sense_buffer_free_host_index);
3362
3363	if (init_type != MPI3MR_IT_RESET) {
3364	retval = mpi3mr_setup_isr(mrioc, 0);	3831	retval = mpi3mr_setup_isr(mrioc, 0);
3365	if (retval) {	3832	if (retval) {
3366	ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",	3833	ioc_err(mrioc, "failed to re-setup ISR\n");
3367	retval);	3834	goto out_failed_noretry;
3368	goto out_failed;
3369	}	3835	}
3370	}	3836	}
3371		3837
		3838	dprint_reset(mrioc, "creating operational queue pairs\n");
3372	retval = mpi3mr_create_op_queues(mrioc);	3839	retval = mpi3mr_create_op_queues(mrioc);
3373	if (retval) {	3840	if (retval) {
3374	ioc_err(mrioc, "Failed to create OpQueues error %d\n",	3841	ioc_err(mrioc, "failed to create operational queue pairs\n");
3375	retval);
3376	goto out_failed;	3842	goto out_failed;
3377	}	3843	}
3378		3844
3379	if ((init_type != MPI3MR_IT_INIT) &&	3845	if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
3380	(mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q)) {
3381	retval = -1;
3382	ioc_err(mrioc,	3846	ioc_err(mrioc,
3383	"Cannot create minimum number of OpQueues expected:%d created:%d\n",	3847	"cannot create minimum number of operatioanl queues expected:%d created:%d\n",
3384	mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);	3848	mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
3385	goto out_failed;	3849	goto out_failed_noretry;
3386	}	3850	}
3387		3851
3388	for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)	3852	dprint_reset(mrioc, "enabling events\n");
3389	mrioc->event_masks[i] = -1;	3853	retval = mpi3mr_enable_events(mrioc);
3390
3391	mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
3392	mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
3393	mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
3394	mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
3395	mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
3396	mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
3397	mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
3398	mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
3399	mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
3400	mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
3401	mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
3402	mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
3403
3404	retval = mpi3mr_issue_event_notification(mrioc);
3405	if (retval) {	3854	if (retval) {
3406	ioc_err(mrioc, "Failed to issue event notification %d\n",	3855	ioc_err(mrioc, "failed to enable events\n");
3407	retval);
3408	goto out_failed;	3856	goto out_failed;
3409	}	3857	}
3410		3858
3411	if (init_type != MPI3MR_IT_INIT) {	3859	ioc_info(mrioc, "sending port enable\n");
3412	ioc_info(mrioc, "Issuing Port Enable\n");	3860	retval = mpi3mr_issue_port_enable(mrioc, 0);
3413	retval = mpi3mr_issue_port_enable(mrioc, 0);	3861	if (retval) {
3414	if (retval) {	3862	ioc_err(mrioc, "failed to issue port enable\n");
3415	ioc_err(mrioc, "Failed to issue port enable %d\n",	3863	goto out_failed;
3416	retval);
3417	goto out_failed;
3418	}
3419	}	3864	}
3420	return retval;
3421		3865
		3866	ioc_info(mrioc, "controller %s completed successfully\n",
		3867	(is_resume)?"resume":"re-initialization");
		3868	return retval;
3422	out_failed:	3869	out_failed:
3423	if (init_type == MPI3MR_IT_INIT)	3870	if (retry < 2) {
3424	mpi3mr_cleanup_ioc(mrioc, MPI3MR_COMPLETE_CLEANUP);	3871	retry++;
3425	else	3872	ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
3426	mpi3mr_cleanup_ioc(mrioc, MPI3MR_REINIT_FAILURE);	3873	(is_resume)?"resume":"re-initialization", retry);
3427	out_nocleanup:	3874	mpi3mr_memset_buffers(mrioc);
		3875	goto retry_init;
		3876	}
		3877	out_failed_noretry:
		3878	ioc_err(mrioc, "controller %s is failed\n",
		3879	(is_resume)?"resume":"re-initialization");
		3880	mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
		3881	MPI3MR_RESET_FROM_CTLR_CLEANUP);
		3882	mrioc->unrecoverable = 1;
3428	return retval;	3883	return retval;
3429	}	3884	}
3430		3885
@@ -3488,17 +3943,29 @@ void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc) · 57 unmodified lines
3488	{	3943	{
3489	u16 i;	3944	u16 i;
3490		3945
3491	memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);	3946	mrioc->change_count = 0;
3492	memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);	3947	mrioc->active_poll_qcount = 0;
3493		3948	mrioc->default_qcount = 0;
3494	memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));	3949	if (mrioc->admin_req_base)
3495	memset(mrioc->host_tm_cmds.reply, 0,	3950	memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
3496	sizeof(*mrioc->host_tm_cmds.reply));	3951	if (mrioc->admin_reply_base)
3497	for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)	3952	memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
3498	memset(mrioc->dev_rmhs_cmds[i].reply, 0,	3953
3499	sizeof(*mrioc->dev_rmhs_cmds[i].reply));	3954	if (mrioc->init_cmds.reply) {
3500	memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz);	3955	memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
3501	memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz);	3956	memset(mrioc->host_tm_cmds.reply, 0,
		3957	sizeof(*mrioc->host_tm_cmds.reply));
		3958	for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
		3959	memset(mrioc->dev_rmhs_cmds[i].reply, 0,
		3960	sizeof(*mrioc->dev_rmhs_cmds[i].reply));
		3961	for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
		3962	memset(mrioc->evtack_cmds[i].reply, 0,
		3963	sizeof(*mrioc->evtack_cmds[i].reply));
		3964	memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz);
		3965	memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz);
		3966	memset(mrioc->evtack_cmds_bitmap, 0,
		3967	mrioc->evtack_cmds_bitmap_sz);
		3968	}
3502		3969
3503	for (i = 0; i < mrioc->num_queues; i++) {	3970	for (i = 0; i < mrioc->num_queues; i++) {
3504	mrioc->op_reply_qinfo[i].qid = 0;	3971	mrioc->op_reply_qinfo[i].qid = 0;
@@ -3527,7 +3994,7 @@ void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc) · 22 unmodified lines
3527	*	3994	*
3528	* Return: Nothing.	3995	* Return: Nothing.
3529	*/	3996	*/
3530	static void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)	3997	void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
3531	{	3998	{
3532	u16 i;	3999	u16 i;
3533	struct mpi3mr_intr_info *intr_info;	4000	struct mpi3mr_intr_info *intr_info;
@@ -3591,12 +4058,20 @@ static void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc) · 57 unmodified lines
3591	kfree(mrioc->host_tm_cmds.reply);	4058	kfree(mrioc->host_tm_cmds.reply);
3592	mrioc->host_tm_cmds.reply = NULL;	4059	mrioc->host_tm_cmds.reply = NULL;
3593		4060
		4061	for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
		4062	kfree(mrioc->evtack_cmds[i].reply);
		4063	mrioc->evtack_cmds[i].reply = NULL;
		4064	}
		4065
3594	kfree(mrioc->removepend_bitmap);	4066	kfree(mrioc->removepend_bitmap);
3595	mrioc->removepend_bitmap = NULL;	4067	mrioc->removepend_bitmap = NULL;
3596		4068
3597	kfree(mrioc->devrem_bitmap);	4069	kfree(mrioc->devrem_bitmap);
3598	mrioc->devrem_bitmap = NULL;	4070	mrioc->devrem_bitmap = NULL;
3599		4071
		4072	kfree(mrioc->evtack_cmds_bitmap);
		4073	mrioc->evtack_cmds_bitmap = NULL;
		4074
3600	kfree(mrioc->chain_bitmap);	4075	kfree(mrioc->chain_bitmap);
3601	mrioc->chain_bitmap = NULL;	4076	mrioc->chain_bitmap = NULL;
3602		4077
@@ -3663,7 +4138,7 @@ static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc) · 60 unmodified lines
3663		4138
3664	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);	4139	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
3665	ioc_config \|= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;	4140	ioc_config \|= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
3666	ioc_config \|= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN;	4141	ioc_config \|= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
3667		4142
3668	writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);	4143	writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
3669		4144
@@ -3699,21 +4174,17 @@ static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc) · 29 unmodified lines
3699	/**	4174	/**
3700	* mpi3mr_cleanup_ioc - Cleanup controller	4175	* mpi3mr_cleanup_ioc - Cleanup controller
3701	* @mrioc: Adapter instance reference	4176	* @mrioc: Adapter instance reference
3702	* @reason: Cleanup reason	4177
3703	*
3704	* controller cleanup handler, Message unit reset or soft reset	4178	* controller cleanup handler, Message unit reset or soft reset
3705	* and shutdown notification is issued to the controller and the	4179	* and shutdown notification is issued to the controller.
3706	* associated memory resources are freed.
3707	*	4180	*
3708	* Return: Nothing.	4181	* Return: Nothing.
3709	*/	4182	*/
3710	void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc, u8 reason)	4183	void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
3711	{	4184	{
3712	enum mpi3mr_iocstate ioc_state;	4185	enum mpi3mr_iocstate ioc_state;
3713		4186
3714	if (reason == MPI3MR_COMPLETE_CLEANUP)	4187	dprint_exit(mrioc, "cleaning up the controller\n");
3715	mpi3mr_stop_watchdog(mrioc);
3716
3717	mpi3mr_ioc_disable_intr(mrioc);	4188	mpi3mr_ioc_disable_intr(mrioc);
3718		4189
3719	ioc_state = mpi3mr_get_iocstate(mrioc);	4190	ioc_state = mpi3mr_get_iocstate(mrioc);
@@ -3725,15 +4196,9 @@ void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc, u8 reason) · 5 unmodified lines
3725	mpi3mr_issue_reset(mrioc,	4196	mpi3mr_issue_reset(mrioc,
3726	MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,	4197	MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
3727	MPI3MR_RESET_FROM_MUR_FAILURE);	4198	MPI3MR_RESET_FROM_MUR_FAILURE);
3728		4199	mpi3mr_issue_ioc_shutdown(mrioc);
3729	if (reason != MPI3MR_REINIT_FAILURE)
3730	mpi3mr_issue_ioc_shutdown(mrioc);
3731	}
3732
3733	if (reason == MPI3MR_COMPLETE_CLEANUP) {
3734	mpi3mr_free_mem(mrioc);
3735	mpi3mr_cleanup_resources(mrioc);
3736	}	4200	}
		4201	dprint_exit(mrioc, "controller cleanup completed\n");
3737	}	4202	}
3738		4203
3739	/**	4204	/**
@@ -3782,41 +4247,11 @@ static void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc) · 42 unmodified lines
3782	cmdptr = &mrioc->dev_rmhs_cmds[i];	4247	cmdptr = &mrioc->dev_rmhs_cmds[i];
3783	mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);	4248	mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
3784	}	4249	}
3785	}
3786
3787	/**
3788	* mpi3mr_diagfault_reset_handler - Diag fault reset handler
3789	* @mrioc: Adapter instance reference
3790	* @reset_reason: Reset reason code
3791	*
3792	* This is an handler for issuing diag fault reset from the
3793	* applications through IOCTL path to stop the execution of the
3794	* controller
3795	*
3796	* Return: 0 on success, non-zero on failure.
3797	*/
3798	int mpi3mr_diagfault_reset_handler(struct mpi3mr_ioc *mrioc,
3799	u32 reset_reason)
3800	{
3801	int retval = 0;
3802
3803	ioc_info(mrioc, "Entry: reason code: %s\n",
3804	mpi3mr_reset_rc_name(reset_reason));
3805	mrioc->reset_in_progress = 1;
3806
3807	mpi3mr_ioc_disable_intr(mrioc);
3808
3809	retval = mpi3mr_issue_reset(mrioc,
3810	MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
3811		4250
3812	if (retval) {	4251	for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
3813	ioc_err(mrioc, "The diag fault reset failed: reason %d\n",	4252	cmdptr = &mrioc->evtack_cmds[i];
3814	reset_reason);	4253	mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
3815	mpi3mr_ioc_enable_intr(mrioc);
3816	}	4254	}
3817	ioc_info(mrioc, "%s\n", ((retval == 0) ? "SUCCESS" : "FAILED"));
3818	mrioc->reset_in_progress = 0;
3819	return retval;
3820	}	4255	}
3821		4256
3822	/**	4257	/**
@@ -3847,34 +4282,44 @@ int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, · 24 unmodified lines
3847	unsigned long flags;	4282	unsigned long flags;
3848	u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;	4283	u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
3849		4284
3850	if (mrioc->fault_dbg) {	4285	/* Block the reset handler until diag save in progress*/
3851	if (snapdump)	4286	dprint_reset(mrioc,
3852	mpi3mr_set_diagsave(mrioc);	4287	"soft_reset_handler: check and block on diagsave_timeout(%d)\n",
3853	mpi3mr_kill_ioc(mrioc, reset_reason);	4288	mrioc->diagsave_timeout);
3854	}	4289	while (mrioc->diagsave_timeout)
3855		4290	ssleep(1);
3856	/*	4291	/*
3857	* Block new resets until the currently executing one is finished and	4292	* Block new resets until the currently executing one is finished and
3858	* return the status of the existing reset for all blocked resets	4293	* return the status of the existing reset for all blocked resets
3859	*/	4294	*/
		4295	dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
3860	if (!mutex_trylock(&mrioc->reset_mutex)) {	4296	if (!mutex_trylock(&mrioc->reset_mutex)) {
3861	ioc_info(mrioc, "Another reset in progress\n");	4297	ioc_info(mrioc,
3862	return -1;	4298	"controller reset triggered by %s is blocked due to another reset in progress\n",
		4299	mpi3mr_reset_rc_name(reset_reason));
		4300	do {
		4301	ssleep(1);
		4302	} while (mrioc->reset_in_progress == 1);
		4303	ioc_info(mrioc,
		4304	"returning previous reset result(%d) for the reset triggered by %s\n",
		4305	mrioc->prev_reset_result,
		4306	mpi3mr_reset_rc_name(reset_reason));
		4307	return mrioc->prev_reset_result;
3863	}	4308	}
		4309	ioc_info(mrioc, "controller reset is triggered by %s\n",
		4310	mpi3mr_reset_rc_name(reset_reason));
		4311
3864	mrioc->reset_in_progress = 1;	4312	mrioc->reset_in_progress = 1;
		4313	mrioc->prev_reset_result = -1;
3865		4314
3866	if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&	4315	if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
		4316	(reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
3867	(reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {	4317	(reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
3868	for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)	4318	for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3869	mrioc->event_masks[i] = -1;	4319	mrioc->event_masks[i] = -1;
3870		4320
3871	retval = mpi3mr_issue_event_notification(mrioc);	4321	dprint_reset(mrioc, "soft_reset_handler: masking events\n");
3872		4322	mpi3mr_issue_event_notification(mrioc);
3873	if (retval) {
3874	ioc_err(mrioc,
3875	"Failed to turn off events prior to reset %d\n",
3876	retval);
3877	}
3878	}	4323	}
3879		4324
3880	mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);	4325	mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
@@ -3904,15 +4349,20 @@ int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, · 23 unmodified lines
3904	goto out;	4349	goto out;
3905	}	4350	}
3906		4351
3907	mpi3mr_flush_delayed_rmhs_list(mrioc);	4352	mpi3mr_flush_delayed_cmd_lists(mrioc);
3908	mpi3mr_flush_drv_cmds(mrioc);	4353	mpi3mr_flush_drv_cmds(mrioc);
3909	memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz);	4354	memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz);
3910	memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz);	4355	memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz);
		4356	memset(mrioc->evtack_cmds_bitmap, 0, mrioc->evtack_cmds_bitmap_sz);
3911	mpi3mr_cleanup_fwevt_list(mrioc);	4357	mpi3mr_cleanup_fwevt_list(mrioc);
3912	mpi3mr_flush_host_io(mrioc);	4358	mpi3mr_flush_host_io(mrioc);
3913	mpi3mr_invalidate_devhandles(mrioc);	4359	mpi3mr_invalidate_devhandles(mrioc);
		4360	if (mrioc->prepare_for_reset) {
		4361	mrioc->prepare_for_reset = 0;
		4362	mrioc->prepare_for_reset_timeout_counter = 0;
		4363	}
3914	mpi3mr_memset_buffers(mrioc);	4364	mpi3mr_memset_buffers(mrioc);
3915	retval = mpi3mr_init_ioc(mrioc, MPI3MR_IT_RESET);	4365	retval = mpi3mr_reinit_ioc(mrioc, 0);
3916	if (retval) {	4366	if (retval) {
3917	pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",	4367	pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
3918	mrioc->name, reset_reason);	4368	mrioc->name, reset_reason);
@@ -3922,8 +4372,8 @@ int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, · 3 unmodified lines
3922		4372
3923	out:	4373	out:
3924	if (!retval) {	4374	if (!retval) {
		4375	mrioc->diagsave_timeout = 0;
3925	mrioc->reset_in_progress = 0;	4376	mrioc->reset_in_progress = 0;
3926	scsi_unblock_requests(mrioc->shost);
3927	mpi3mr_rfresh_tgtdevs(mrioc);	4377	mpi3mr_rfresh_tgtdevs(mrioc);
3928	mrioc->ts_update_counter = 0;	4378	mrioc->ts_update_counter = 0;
3929	spin_lock_irqsave(&mrioc->watchdog_lock, flags);	4379	spin_lock_irqsave(&mrioc->watchdog_lock, flags);
@@ -3939,8 +4389,9 @@ out: · 9 unmodified lines
3939	mrioc->reset_in_progress = 0;	4389	mrioc->reset_in_progress = 0;
3940	retval = -1;	4390	retval = -1;
3941	}	4391	}
3942		4392	mrioc->prev_reset_result = retval;
3943	mutex_unlock(&mrioc->reset_mutex);	4393	mutex_unlock(&mrioc->reset_mutex);
3944	ioc_info(mrioc, "%s\n", ((retval == 0) ? "SUCCESS" : "FAILED"));	4394	ioc_info(mrioc, "controller reset is %s\n",
		4395	((retval == 0) ? "successful" : "failed"));
3945	return retval;	4396	return retval;
3946	}	4397	}

drivers/scsi/mpi3mr/mpi3mr_os.c+642−129

@@ -34,6 +34,9 @@ MODULE_PARM_DESC(logging_level, · 33 unmodified lines
34	" bits for enabling additional logging info (default=0)");	34	" bits for enabling additional logging info (default=0)");
35		35
36	/* Forward declarations*/	36	/* Forward declarations*/
		37	static void mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
		38	struct mpi3mr_drv_cmd *cmdparam, u32 event_ctx);
		39
37	/**	40	/**
38	* mpi3mr_host_tag_for_scmd - Get host tag for a scmd	41	* mpi3mr_host_tag_for_scmd - Get host tag for a scmd
39	* @mrioc: Adapter instance reference	42	* @mrioc: Adapter instance reference
@@ -417,6 +420,74 @@ out: · 377 unmodified lines
417	return(true);	420	return(true);
418	}	421	}
419		422
		423	/**
		424	* mpi3mr_count_dev_pending - Count commands pending for a lun
		425	* @rq: Block request
		426	* @data: SCSI device reference
		427	* @reserved: Unused
		428	*
		429	* This is an iterator function called for each SCSI command in
		430	* a host and if the command is pending in the LLD for the
		431	* specific device(lun) then device specific pending I/O counter
		432	* is updated in the device structure.
		433	*
		434	* Return: true always.
		435	*/
		436
		437	static bool mpi3mr_count_dev_pending(struct request *rq,
		438	void *data, bool reserved)
		439	{
		440	struct scsi_device sdev = (struct scsi_device )data;
		441	struct mpi3mr_sdev_priv_data *sdev_priv_data = sdev->hostdata;
		442	struct scsi_cmnd *scmd = blk_mq_rq_to_pdu(rq);
		443	struct scmd_priv *priv;
		444
		445	if (scmd) {
		446	priv = scsi_cmd_priv(scmd);
		447	if (!priv->in_lld_scope)
		448	goto out;
		449	if (scmd->device == sdev)
		450	sdev_priv_data->pend_count++;
		451	}
		452
		453	out:
		454	return true;
		455	}
		456
		457	/**
		458	* mpi3mr_count_tgt_pending - Count commands pending for target
		459	* @rq: Block request
		460	* @data: SCSI target reference
		461	* @reserved: Unused
		462	*
		463	* This is an iterator function called for each SCSI command in
		464	* a host and if the command is pending in the LLD for the
		465	* specific target then target specific pending I/O counter is
		466	* updated in the target structure.
		467	*
		468	* Return: true always.
		469	*/
		470
		471	static bool mpi3mr_count_tgt_pending(struct request *rq,
		472	void *data, bool reserved)
		473	{
		474	struct scsi_target starget = (struct scsi_target )data;
		475	struct mpi3mr_stgt_priv_data *stgt_priv_data = starget->hostdata;
		476	struct scsi_cmnd *scmd = blk_mq_rq_to_pdu(rq);
		477	struct scmd_priv *priv;
		478
		479	if (scmd) {
		480	priv = scsi_cmd_priv(scmd);
		481	if (!priv->in_lld_scope)
		482	goto out;
		483	if (scmd->device && (scsi_target(scmd->device) == starget))
		484	stgt_priv_data->pend_count++;
		485	}
		486
		487	out:
		488	return true;
		489	}
		490
420	/**	491	/**
421	* mpi3mr_flush_host_io - Flush host I/Os	492	* mpi3mr_flush_host_io - Flush host I/Os
422	* @mrioc: Adapter instance reference	493	* @mrioc: Adapter instance reference
@@ -742,11 +813,18 @@ mpi3mr_update_sdev(struct scsi_device sdev, void data) · 319 unmodified lines
742	switch (tgtdev->dev_type) {	813	switch (tgtdev->dev_type) {
743	case MPI3_DEVICE_DEVFORM_PCIE:	814	case MPI3_DEVICE_DEVFORM_PCIE:
744	/The block layer hw sector size = 512/	815	/The block layer hw sector size = 512/
745	blk_queue_max_hw_sectors(sdev->request_queue,	816	if ((tgtdev->dev_spec.pcie_inf.dev_info &
746	tgtdev->dev_spec.pcie_inf.mdts / 512);	817	MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) ==
747	blk_queue_virt_boundary(sdev->request_queue,	818	MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE) {
748	((1 << tgtdev->dev_spec.pcie_inf.pgsz) - 1));	819	blk_queue_max_hw_sectors(sdev->request_queue,
749		820	tgtdev->dev_spec.pcie_inf.mdts / 512);
		821	if (tgtdev->dev_spec.pcie_inf.pgsz == 0)
		822	blk_queue_virt_boundary(sdev->request_queue,
		823	((1 << MPI3MR_DEFAULT_PGSZEXP) - 1));
		824	else
		825	blk_queue_virt_boundary(sdev->request_queue,
		826	((1 << tgtdev->dev_spec.pcie_inf.pgsz) - 1));
		827	}
750	break;	828	break;
751	default:	829	default:
752	break;	830	break;
@@ -824,6 +902,17 @@ static void mpi3mr_update_tgtdev(struct mpi3mr_ioc *mrioc, · 71 unmodified lines
824	scsi_tgt_priv_data->dev_type = tgtdev->dev_type;	902	scsi_tgt_priv_data->dev_type = tgtdev->dev_type;
825	}	903	}
826		904
		905	switch (dev_pg0->access_status) {
		906	case MPI3_DEVICE0_ASTATUS_NO_ERRORS:
		907	case MPI3_DEVICE0_ASTATUS_PREPARE:
		908	case MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION:
		909	case MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY:
		910	break;
		911	default:
		912	tgtdev->is_hidden = 1;
		913	break;
		914	}
		915
827	switch (tgtdev->dev_type) {	916	switch (tgtdev->dev_type) {
828	case MPI3_DEVICE_DEVFORM_SAS_SATA:	917	case MPI3_DEVICE_DEVFORM_SAS_SATA:
829	{	918	{
@@ -848,6 +937,7 @@ static void mpi3mr_update_tgtdev(struct mpi3mr_ioc *mrioc, · 18 unmodified lines
848	&dev_pg0->device_specific.pcie_format;	937	&dev_pg0->device_specific.pcie_format;
849	u16 dev_info = le16_to_cpu(pcieinf->device_info);	938	u16 dev_info = le16_to_cpu(pcieinf->device_info);
850		939
		940	tgtdev->dev_spec.pcie_inf.dev_info = dev_info;
851	tgtdev->dev_spec.pcie_inf.capb =	941	tgtdev->dev_spec.pcie_inf.capb =
852	le32_to_cpu(pcieinf->capabilities);	942	le32_to_cpu(pcieinf->capabilities);
853	tgtdev->dev_spec.pcie_inf.mdts = MPI3MR_DEFAULT_MDTS;	943	tgtdev->dev_spec.pcie_inf.mdts = MPI3MR_DEFAULT_MDTS;
@@ -858,14 +948,18 @@ static void mpi3mr_update_tgtdev(struct mpi3mr_ioc *mrioc, · 4 unmodified lines
858	le32_to_cpu(pcieinf->maximum_data_transfer_size);	948	le32_to_cpu(pcieinf->maximum_data_transfer_size);
859	tgtdev->dev_spec.pcie_inf.pgsz = pcieinf->page_size;	949	tgtdev->dev_spec.pcie_inf.pgsz = pcieinf->page_size;
860	tgtdev->dev_spec.pcie_inf.reset_to =	950	tgtdev->dev_spec.pcie_inf.reset_to =
861	pcieinf->controller_reset_to;	951	max_t(u8, pcieinf->controller_reset_to,
		952	MPI3MR_INTADMCMD_TIMEOUT);
862	tgtdev->dev_spec.pcie_inf.abort_to =	953	tgtdev->dev_spec.pcie_inf.abort_to =
863	pcieinf->nv_me_abort_to;	954	max_t(u8, pcieinf->nvme_abort_to,
		955	MPI3MR_INTADMCMD_TIMEOUT);
864	}	956	}
865	if (tgtdev->dev_spec.pcie_inf.mdts > (1024 * 1024))	957	if (tgtdev->dev_spec.pcie_inf.mdts > (1024 * 1024))
866	tgtdev->dev_spec.pcie_inf.mdts = (1024 * 1024);	958	tgtdev->dev_spec.pcie_inf.mdts = (1024 * 1024);
867	if ((dev_info & MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) !=	959	if (((dev_info & MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) !=
868	MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE)	960	MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE) &&
		961	((dev_info & MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) !=
		962	MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE))
869	tgtdev->is_hidden = 1;	963	tgtdev->is_hidden = 1;
870	if (!mrioc->shost)	964	if (!mrioc->shost)
871	break;	965	break;
@@ -1313,7 +1407,7 @@ static void mpi3mr_fwevt_bh(struct mpi3mr_ioc *mrioc, · 441 unmodified lines
1313		1407
1314	evt_ack:	1408	evt_ack:
1315	if (fwevt->send_ack)	1409	if (fwevt->send_ack)
1316	mpi3mr_send_event_ack(mrioc, fwevt->event_id,	1410	mpi3mr_process_event_ack(mrioc, fwevt->event_id,
1317	fwevt->evt_ctx);	1411	fwevt->evt_ctx);
1318	out:	1412	out:
1319	/* Put fwevt reference count to neutralize kref_init increment */	1413	/* Put fwevt reference count to neutralize kref_init increment */
@@ -1377,24 +1471,33 @@ static int mpi3mr_create_tgtdev(struct mpi3mr_ioc *mrioc, · 57 unmodified lines
1377	}	1471	}
1378		1472
1379	/**	1473	/**
1380	* mpi3mr_flush_delayed_rmhs_list - Flush pending commands	1474	* mpi3mr_flush_delayed_cmd_lists - Flush pending commands
1381	* @mrioc: Adapter instance reference	1475	* @mrioc: Adapter instance reference
1382	*	1476	*
1383	* Flush pending commands in the delayed removal handshake list	1477	* Flush pending commands in the delayed lists due to a
1384	* due to a controller reset or driver removal as a cleanup.	1478	* controller reset or driver removal as a cleanup.
1385	*	1479	*
1386	* Return: Nothing	1480	* Return: Nothing
1387	*/	1481	*/
1388	void mpi3mr_flush_delayed_rmhs_list(struct mpi3mr_ioc *mrioc)	1482	void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc)
1389	{	1483	{
1390	struct delayed_dev_rmhs_node *_rmhs_node;	1484	struct delayed_dev_rmhs_node *_rmhs_node;
		1485	struct delayed_evt_ack_node *_evtack_node;
1391		1486
		1487	dprint_reset(mrioc, "flushing delayed dev_remove_hs commands\n");
1392	while (!list_empty(&mrioc->delayed_rmhs_list)) {	1488	while (!list_empty(&mrioc->delayed_rmhs_list)) {
1393	_rmhs_node = list_entry(mrioc->delayed_rmhs_list.next,	1489	_rmhs_node = list_entry(mrioc->delayed_rmhs_list.next,
1394	struct delayed_dev_rmhs_node, list);	1490	struct delayed_dev_rmhs_node, list);
1395	list_del(&_rmhs_node->list);	1491	list_del(&_rmhs_node->list);
1396	kfree(_rmhs_node);	1492	kfree(_rmhs_node);
1397	}	1493	}
		1494	dprint_reset(mrioc, "flushing delayed event ack commands\n");
		1495	while (!list_empty(&mrioc->delayed_evtack_cmds_list)) {
		1496	_evtack_node = list_entry(mrioc->delayed_evtack_cmds_list.next,
		1497	struct delayed_evt_ack_node, list);
		1498	list_del(&_evtack_node->list);
		1499	kfree(_evtack_node);
		1500	}
1398	}	1501	}
1399		1502
1400	/**	1503	/**
@@ -1610,6 +1713,141 @@ out_failed: · 209 unmodified lines
1610	clear_bit(cmd_idx, mrioc->devrem_bitmap);	1713	clear_bit(cmd_idx, mrioc->devrem_bitmap);
1611	}	1714	}
1612		1715
		1716	/**
		1717	* mpi3mr_complete_evt_ack - event ack request completion
		1718	* @mrioc: Adapter instance reference
		1719	* @drv_cmd: Internal command tracker
		1720	*
		1721	* This is the completion handler for non blocking event
		1722	* acknowledgment sent to the firmware and this will issue any
		1723	* pending event acknowledgment request.
		1724	*
		1725	* Return: Nothing
		1726	*/
		1727	static void mpi3mr_complete_evt_ack(struct mpi3mr_ioc *mrioc,
		1728	struct mpi3mr_drv_cmd *drv_cmd)
		1729	{
		1730	u16 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
		1731	struct delayed_evt_ack_node *delayed_evtack = NULL;
		1732
		1733	if (drv_cmd->ioc_status != MPI3_IOCSTATUS_SUCCESS) {
		1734	dprint_event_th(mrioc,
		1735	"immediate event ack failed with ioc_status(0x%04x) log_info(0x%08x)\n",
		1736	(drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
		1737	drv_cmd->ioc_loginfo);
		1738	}
		1739
		1740	if (!list_empty(&mrioc->delayed_evtack_cmds_list)) {
		1741	delayed_evtack =
		1742	list_entry(mrioc->delayed_evtack_cmds_list.next,
		1743	struct delayed_evt_ack_node, list);
		1744	mpi3mr_send_event_ack(mrioc, delayed_evtack->event, drv_cmd,
		1745	delayed_evtack->event_ctx);
		1746	list_del(&delayed_evtack->list);
		1747	kfree(delayed_evtack);
		1748	return;
		1749	}
		1750	drv_cmd->state = MPI3MR_CMD_NOTUSED;
		1751	drv_cmd->callback = NULL;
		1752	clear_bit(cmd_idx, mrioc->evtack_cmds_bitmap);
		1753	}
		1754
		1755	/**
		1756	* mpi3mr_send_event_ack - Issue event acknwoledgment request
		1757	* @mrioc: Adapter instance reference
		1758	* @event: MPI3 event id
		1759	* @cmdparam: Internal command tracker
		1760	* @event_ctx: event context
		1761	*
		1762	* Issues event acknowledgment request to the firmware if there
		1763	* is a free command to send the event ack else it to a pend
		1764	* list so that it will be processed on a completion of a prior
		1765	* event acknowledgment .
		1766	*
		1767	* Return: Nothing
		1768	*/
		1769	static void mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
		1770	struct mpi3mr_drv_cmd *cmdparam, u32 event_ctx)
		1771	{
		1772	struct mpi3_event_ack_request evtack_req;
		1773	int retval = 0;
		1774	u8 retrycount = 5;
		1775	u16 cmd_idx = MPI3MR_NUM_EVTACKCMD;
		1776	struct mpi3mr_drv_cmd *drv_cmd = cmdparam;
		1777	struct delayed_evt_ack_node *delayed_evtack = NULL;
		1778
		1779	if (drv_cmd) {
		1780	dprint_event_th(mrioc,
		1781	"sending delayed event ack in the top half for event(0x%02x), event_ctx(0x%08x)\n",
		1782	event, event_ctx);
		1783	goto issue_cmd;
		1784	}
		1785	dprint_event_th(mrioc,
		1786	"sending event ack in the top half for event(0x%02x), event_ctx(0x%08x)\n",
		1787	event, event_ctx);
		1788	do {
		1789	cmd_idx = find_first_zero_bit(mrioc->evtack_cmds_bitmap,
		1790	MPI3MR_NUM_EVTACKCMD);
		1791	if (cmd_idx < MPI3MR_NUM_EVTACKCMD) {
		1792	if (!test_and_set_bit(cmd_idx,
		1793	mrioc->evtack_cmds_bitmap))
		1794	break;
		1795	cmd_idx = MPI3MR_NUM_EVTACKCMD;
		1796	}
		1797	} while (retrycount--);
		1798
		1799	if (cmd_idx >= MPI3MR_NUM_EVTACKCMD) {
		1800	delayed_evtack = kzalloc(sizeof(*delayed_evtack),
		1801	GFP_ATOMIC);
		1802	if (!delayed_evtack)
		1803	return;
		1804	INIT_LIST_HEAD(&delayed_evtack->list);
		1805	delayed_evtack->event = event;
		1806	delayed_evtack->event_ctx = event_ctx;
		1807	list_add_tail(&delayed_evtack->list,
		1808	&mrioc->delayed_evtack_cmds_list);
		1809	dprint_event_th(mrioc,
		1810	"event ack in the top half for event(0x%02x), event_ctx(0x%08x) is postponed\n",
		1811	event, event_ctx);
		1812	return;
		1813	}
		1814	drv_cmd = &mrioc->evtack_cmds[cmd_idx];
		1815
		1816	issue_cmd:
		1817	cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
		1818
		1819	memset(&evtack_req, 0, sizeof(evtack_req));
		1820	if (drv_cmd->state & MPI3MR_CMD_PENDING) {
		1821	dprint_event_th(mrioc,
		1822	"sending event ack failed due to command in use\n");
		1823	goto out;
		1824	}
		1825	drv_cmd->state = MPI3MR_CMD_PENDING;
		1826	drv_cmd->is_waiting = 0;
		1827	drv_cmd->callback = mpi3mr_complete_evt_ack;
		1828	evtack_req.host_tag = cpu_to_le16(drv_cmd->host_tag);
		1829	evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
		1830	evtack_req.event = event;
		1831	evtack_req.event_context = cpu_to_le32(event_ctx);
		1832	retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
		1833	sizeof(evtack_req), 1);
		1834	if (retval) {
		1835	dprint_event_th(mrioc,
		1836	"posting event ack request is failed\n");
		1837	goto out_failed;
		1838	}
		1839
		1840	dprint_event_th(mrioc,
		1841	"event ack in the top half for event(0x%02x), event_ctx(0x%08x) is posted\n",
		1842	event, event_ctx);
		1843	out:
		1844	return;
		1845	out_failed:
		1846	drv_cmd->state = MPI3MR_CMD_NOTUSED;
		1847	drv_cmd->callback = NULL;
		1848	clear_bit(cmd_idx, mrioc->evtack_cmds_bitmap);
		1849	}
		1850
1613	/**	1851	/**
1614	* mpi3mr_pcietopochg_evt_th - PCIETopologyChange evt tophalf	1852	* mpi3mr_pcietopochg_evt_th - PCIETopologyChange evt tophalf
1615	* @mrioc: Adapter instance reference	1853	* @mrioc: Adapter instance reference
@@ -1818,6 +2056,40 @@ out: · 202 unmodified lines
1818	mpi3mr_tgtdev_put(tgtdev);	2056	mpi3mr_tgtdev_put(tgtdev);
1819	}	2057	}
1820		2058
		2059	/**
		2060	* mpi3mr_preparereset_evt_th - Prepare for reset event tophalf
		2061	* @mrioc: Adapter instance reference
		2062	* @event_reply: event data
		2063	*
		2064	* Blocks and unblocks host level I/O based on the reason code
		2065	*
		2066	* Return: Nothing
		2067	*/
		2068	static void mpi3mr_preparereset_evt_th(struct mpi3mr_ioc *mrioc,
		2069	struct mpi3_event_notification_reply *event_reply)
		2070	{
		2071	struct mpi3_event_data_prepare_for_reset *evtdata =
		2072	(struct mpi3_event_data_prepare_for_reset *)event_reply->event_data;
		2073
		2074	if (evtdata->reason_code == MPI3_EVENT_PREPARE_RESET_RC_START) {
		2075	dprint_event_th(mrioc,
		2076	"prepare for reset event top half with rc=start\n");
		2077	if (mrioc->prepare_for_reset)
		2078	return;
		2079	mrioc->prepare_for_reset = 1;
		2080	mrioc->prepare_for_reset_timeout_counter = 0;
		2081	} else if (evtdata->reason_code == MPI3_EVENT_PREPARE_RESET_RC_ABORT) {
		2082	dprint_event_th(mrioc,
		2083	"prepare for reset top half with rc=abort\n");
		2084	mrioc->prepare_for_reset = 0;
		2085	mrioc->prepare_for_reset_timeout_counter = 0;
		2086	}
		2087	if ((event_reply->msg_flags & MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK)
		2088	== MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED)
		2089	mpi3mr_send_event_ack(mrioc, event_reply->event, NULL,
		2090	le32_to_cpu(event_reply->event_context));
		2091	}
		2092
1821	/**	2093	/**
1822	* mpi3mr_energypackchg_evt_th - Energy pack change evt tophalf	2094	* mpi3mr_energypackchg_evt_th - Energy pack change evt tophalf
1823	* @mrioc: Adapter instance reference	2095	* @mrioc: Adapter instance reference
@@ -1847,6 +2119,66 @@ static void mpi3mr_energypackchg_evt_th(struct mpi3mr_ioc *mrioc, · 23 unmodified lines
1847	mrioc->facts.shutdown_timeout = shutdown_timeout;	2119	mrioc->facts.shutdown_timeout = shutdown_timeout;
1848	}	2120	}
1849		2121
		2122	/**
		2123	* mpi3mr_tempthreshold_evt_th - Temp threshold event tophalf
		2124	* @mrioc: Adapter instance reference
		2125	* @event_reply: event data
		2126	*
		2127	* Displays temperature threshold event details and fault code
		2128	* if any is hit due to temperature exceeding threshold.
		2129	*
		2130	* Return: Nothing
		2131	*/
		2132	static void mpi3mr_tempthreshold_evt_th(struct mpi3mr_ioc *mrioc,
		2133	struct mpi3_event_notification_reply *event_reply)
		2134	{
		2135	struct mpi3_event_data_temp_threshold *evtdata =
		2136	(struct mpi3_event_data_temp_threshold *)event_reply->event_data;
		2137
		2138	ioc_err(mrioc, "Temperature threshold levels %s%s%s exceeded for sensor: %d !!! Current temperature in Celsius: %d\n",
		2139	(le16_to_cpu(evtdata->status) & 0x1) ? "Warning " : " ",
		2140	(le16_to_cpu(evtdata->status) & 0x2) ? "Critical " : " ",
		2141	(le16_to_cpu(evtdata->status) & 0x4) ? "Fatal " : " ", evtdata->sensor_num,
		2142	le16_to_cpu(evtdata->current_temperature));
		2143	mpi3mr_print_fault_info(mrioc);
		2144	}
		2145
		2146	/**
		2147	* mpi3mr_cablemgmt_evt_th - Cable management event tophalf
		2148	* @mrioc: Adapter instance reference
		2149	* @event_reply: event data
		2150	*
		2151	* Displays Cable manegemt event details.
		2152	*
		2153	* Return: Nothing
		2154	*/
		2155	static void mpi3mr_cablemgmt_evt_th(struct mpi3mr_ioc *mrioc,
		2156	struct mpi3_event_notification_reply *event_reply)
		2157	{
		2158	struct mpi3_event_data_cable_management *evtdata =
		2159	(struct mpi3_event_data_cable_management *)event_reply->event_data;
		2160
		2161	switch (evtdata->status) {
		2162	case MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER:
		2163	{
		2164	ioc_info(mrioc, "An active cable with receptacle_id %d cannot be powered.\n"
		2165	"Devices connected to this cable are not detected.\n"
		2166	"This cable requires %d mW of power.\n",
		2167	evtdata->receptacle_id,
		2168	le32_to_cpu(evtdata->active_cable_power_requirement));
		2169	break;
		2170	}
		2171	case MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED:
		2172	{
		2173	ioc_info(mrioc, "A cable with receptacle_id %d is not running at optimal speed\n",
		2174	evtdata->receptacle_id);
		2175	break;
		2176	}
		2177	default:
		2178	break;
		2179	}
		2180	}
		2181
1850	/**	2182	/**
1851	* mpi3mr_os_handle_events - Firmware event handler	2183	* mpi3mr_os_handle_events - Firmware event handler
1852	* @mrioc: Adapter instance reference	2184	* @mrioc: Adapter instance reference
@@ -1905,6 +2237,12 @@ void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, · 52 unmodified lines
1905	mpi3mr_pcietopochg_evt_th(mrioc, event_reply);	2237	mpi3mr_pcietopochg_evt_th(mrioc, event_reply);
1906	break;	2238	break;
1907	}	2239	}
		2240	case MPI3_EVENT_PREPARE_FOR_RESET:
		2241	{
		2242	mpi3mr_preparereset_evt_th(mrioc, event_reply);
		2243	ack_req = 0;
		2244	break;
		2245	}
1908	case MPI3_EVENT_DEVICE_INFO_CHANGED:	2246	case MPI3_EVENT_DEVICE_INFO_CHANGED:
1909	{	2247	{
1910	process_evt_bh = 1;	2248	process_evt_bh = 1;
@@ -1915,9 +2253,18 @@ void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, · 4 unmodified lines
1915	mpi3mr_energypackchg_evt_th(mrioc, event_reply);	2253	mpi3mr_energypackchg_evt_th(mrioc, event_reply);
1916	break;	2254	break;
1917	}	2255	}
		2256	case MPI3_EVENT_TEMP_THRESHOLD:
		2257	{
		2258	mpi3mr_tempthreshold_evt_th(mrioc, event_reply);
		2259	break;
		2260	}
		2261	case MPI3_EVENT_CABLE_MGMT:
		2262	{
		2263	mpi3mr_cablemgmt_evt_th(mrioc, event_reply);
		2264	break;
		2265	}
1918	case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:	2266	case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
1919	case MPI3_EVENT_SAS_DISCOVERY:	2267	case MPI3_EVENT_SAS_DISCOVERY:
1920	case MPI3_EVENT_CABLE_MGMT:
1921	case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:	2268	case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
1922	case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:	2269	case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
1923	case MPI3_EVENT_PCIE_ENUMERATION:	2270	case MPI3_EVENT_PCIE_ENUMERATION:
@@ -2520,49 +2867,63 @@ static int mpi3mr_build_sg_scmd(struct mpi3mr_ioc *mrioc, · 596 unmodified lines
2520	}	2867	}
2521		2868
2522	/**	2869	/**
2523	* mpi3mr_print_response_code - print TM response as a string	2870	* mpi3mr_tm_response_name - get TM response as a string
2524	* @mrioc: Adapter instance reference
2525	* @resp_code: TM response code	2871	* @resp_code: TM response code
2526	*	2872	*
2527	* Print TM response code as a readable string.	2873	* Convert known task management response code as a readable
		2874	* string.
2528	*	2875	*
2529	* Return: Nothing.	2876	* Return: response code string.
2530	*/	2877	*/
2531	static void mpi3mr_print_response_code(struct mpi3mr_ioc *mrioc, u8 resp_code)	2878	static const char *mpi3mr_tm_response_name(u8 resp_code)
2532	{	2879	{
2533	char *desc;	2880	char *desc;
2534		2881
2535	switch (resp_code) {	2882	switch (resp_code) {
2536	case MPI3MR_RSP_TM_COMPLETE:	2883	case MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE:
2537	desc = "task management request completed";	2884	desc = "task management request completed";
2538	break;	2885	break;
2539	case MPI3MR_RSP_INVALID_FRAME:	2886	case MPI3_SCSITASKMGMT_RSPCODE_INVALID_FRAME:
2540	desc = "invalid frame";	2887	desc = "invalid frame";
2541	break;	2888	break;
2542	case MPI3MR_RSP_TM_NOT_SUPPORTED:	2889	case MPI3_SCSITASKMGMT_RSPCODE_TM_FUNCTION_NOT_SUPPORTED:
2543	desc = "task management request not supported";	2890	desc = "task management request not supported";
2544	break;	2891	break;
2545	case MPI3MR_RSP_TM_FAILED:	2892	case MPI3_SCSITASKMGMT_RSPCODE_TM_FAILED:
2546	desc = "task management request failed";	2893	desc = "task management request failed";
2547	break;	2894	break;
2548	case MPI3MR_RSP_TM_SUCCEEDED:	2895	case MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED:
2549	desc = "task management request succeeded";	2896	desc = "task management request succeeded";
2550	break;	2897	break;
2551	case MPI3MR_RSP_TM_INVALID_LUN:	2898	case MPI3_SCSITASKMGMT_RSPCODE_TM_INVALID_LUN:
2552	desc = "invalid lun";	2899	desc = "invalid LUN";
2553	break;	2900	break;
2554	case MPI3MR_RSP_TM_OVERLAPPED_TAG:	2901	case MPI3_SCSITASKMGMT_RSPCODE_TM_OVERLAPPED_TAG:
2555	desc = "overlapped tag attempted";	2902	desc = "overlapped tag attempted";
2556	break;	2903	break;
2557	case MPI3MR_RSP_IO_QUEUED_ON_IOC:	2904	case MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC:
2558	desc = "task queued, however not sent to target";	2905	desc = "task queued, however not sent to target";
2559	break;	2906	break;
		2907	case MPI3_SCSITASKMGMT_RSPCODE_TM_NVME_DENIED:
		2908	desc = "task management request denied by NVMe device";
		2909	break;
2560	default:	2910	default:
2561	desc = "unknown";	2911	desc = "unknown";
2562	break;	2912	break;
2563	}	2913	}
2564	ioc_info(mrioc, "%s :response_code(0x%01x): %s\n", __func__,	2914
2565	resp_code, desc);	2915	return desc;
		2916	}
		2917
		2918	inline void mpi3mr_poll_pend_io_completions(struct mpi3mr_ioc *mrioc)
		2919	{
		2920	int i;
		2921	int num_of_reply_queues =
		2922	mrioc->num_op_reply_q + mrioc->op_reply_q_offset;
		2923
		2924	for (i = mrioc->op_reply_q_offset; i < num_of_reply_queues; i++)
		2925	mpi3mr_process_op_reply_q(mrioc,
		2926	mrioc->intr_info[i].op_reply_q);
2566	}	2927	}
2567		2928
2568	/**	2929	/**
@@ -2572,9 +2933,10 @@ static void mpi3mr_print_response_code(struct mpi3mr_ioc *mrioc, u8 resp_code) · 3 unmodified lines
2572	* @handle: Device handle	2933	* @handle: Device handle
2573	* @lun: lun ID	2934	* @lun: lun ID
2574	* @htag: Host tag of the TM request	2935	* @htag: Host tag of the TM request
		2936	* @timeout: TM timeout value
2575	* @drv_cmd: Internal command tracker	2937	* @drv_cmd: Internal command tracker
2576	* @resp_code: Response code place holder	2938	* @resp_code: Response code place holder
2577	* @cmd_priv: SCSI command private data	2939	* @scmd: SCSI command
2578	*	2940	*
2579	* Issues a Task Management Request to the controller for a	2941	* Issues a Task Management Request to the controller for a
2580	* specified target, lun and command and wait for its completion	2942	* specified target, lun and command and wait for its completion
@@ -2586,14 +2948,16 @@ static void mpi3mr_print_response_code(struct mpi3mr_ioc *mrioc, u8 resp_code) · 5 unmodified lines
2586	static int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type,	2948	static int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type,
2587	u16 handle, uint lun, u16 htag, ulong timeout,	2949	u16 handle, uint lun, u16 htag, ulong timeout,
2588	struct mpi3mr_drv_cmd *drv_cmd,	2950	struct mpi3mr_drv_cmd *drv_cmd,
2589	u8 resp_code, struct scmd_priv cmd_priv)	2951	u8 resp_code, struct scsi_cmnd scmd)
2590	{	2952	{
2591	struct mpi3_scsi_task_mgmt_request tm_req;	2953	struct mpi3_scsi_task_mgmt_request tm_req;
2592	struct mpi3_scsi_task_mgmt_reply *tm_reply = NULL;	2954	struct mpi3_scsi_task_mgmt_reply *tm_reply = NULL;
2593	int retval = 0;	2955	int retval = 0;
2594	struct mpi3mr_tgt_dev *tgtdev = NULL;	2956	struct mpi3mr_tgt_dev *tgtdev = NULL;
2595	struct mpi3mr_stgt_priv_data *scsi_tgt_priv_data = NULL;	2957	struct mpi3mr_stgt_priv_data *scsi_tgt_priv_data = NULL;
2596	struct op_req_qinfo *op_req_q = NULL;	2958	struct scmd_priv *cmd_priv = NULL;
		2959	struct scsi_device *sdev = NULL;
		2960	struct mpi3mr_sdev_priv_data *sdev_priv_data = NULL;
2597		2961
2598	ioc_info(mrioc, "%s :Issue TM: TM type (0x%x) for devhandle 0x%04x\n",	2962	ioc_info(mrioc, "%s :Issue TM: TM type (0x%x) for devhandle 0x%04x\n",
2599	__func__, tm_type, handle);	2963	__func__, tm_type, handle);
@@ -2630,16 +2994,21 @@ static int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, · 30 unmodified lines
2630	tm_req.function = MPI3_FUNCTION_SCSI_TASK_MGMT;	2994	tm_req.function = MPI3_FUNCTION_SCSI_TASK_MGMT;
2631		2995
2632	tgtdev = mpi3mr_get_tgtdev_by_handle(mrioc, handle);	2996	tgtdev = mpi3mr_get_tgtdev_by_handle(mrioc, handle);
2633	if (tgtdev && tgtdev->starget && tgtdev->starget->hostdata) {	2997
2634	scsi_tgt_priv_data = (struct mpi3mr_stgt_priv_data *)	2998	if (scmd) {
2635	tgtdev->starget->hostdata;	2999	sdev = scmd->device;
2636	atomic_inc(&scsi_tgt_priv_data->block_io);	3000	sdev_priv_data = sdev->hostdata;
2637	}	3001	scsi_tgt_priv_data = ((sdev_priv_data) ?
2638	if (cmd_priv) {	3002	sdev_priv_data->tgt_priv_data : NULL);
2639	op_req_q = &mrioc->req_qinfo[cmd_priv->req_q_idx];	3003	} else {
2640	tm_req.task_host_tag = cpu_to_le16(cmd_priv->host_tag);	3004	if (tgtdev && tgtdev->starget && tgtdev->starget->hostdata)
2641	tm_req.task_request_queue_id = cpu_to_le16(op_req_q->qid);	3005	scsi_tgt_priv_data = (struct mpi3mr_stgt_priv_data *)
		3006	tgtdev->starget->hostdata;
2642	}	3007	}
		3008
		3009	if (scsi_tgt_priv_data)
		3010	atomic_inc(&scsi_tgt_priv_data->block_io);
		3011
2643	if (tgtdev && (tgtdev->dev_type == MPI3_DEVICE_DEVFORM_PCIE)) {	3012	if (tgtdev && (tgtdev->dev_type == MPI3_DEVICE_DEVFORM_PCIE)) {
2644	if (cmd_priv && tgtdev->dev_spec.pcie_inf.abort_to)	3013	if (cmd_priv && tgtdev->dev_spec.pcie_inf.abort_to)
2645	timeout = tgtdev->dev_spec.pcie_inf.abort_to;	3014	timeout = tgtdev->dev_spec.pcie_inf.abort_to;
@@ -2656,39 +3025,49 @@ static int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, · 10 unmodified lines
2656	wait_for_completion_timeout(&drv_cmd->done, (timeout * HZ));	3025	wait_for_completion_timeout(&drv_cmd->done, (timeout * HZ));
2657		3026
2658	if (!(drv_cmd->state & MPI3MR_CMD_COMPLETE)) {	3027	if (!(drv_cmd->state & MPI3MR_CMD_COMPLETE)) {
2659	ioc_err(mrioc, "%s :Issue TM: command timed out\n", __func__);
2660	drv_cmd->is_waiting = 0;	3028	drv_cmd->is_waiting = 0;
2661	retval = -1;	3029	retval = -1;
2662	mpi3mr_soft_reset_handler(mrioc,	3030	if (!(drv_cmd->state & MPI3MR_CMD_RESET)) {
2663	MPI3MR_RESET_FROM_TM_TIMEOUT, 1);	3031	dprint_tm(mrioc,
		3032	"task management request timed out after %ld seconds\n",
		3033	timeout);
		3034	if (mrioc->logging_level & MPI3_DEBUG_TM)
		3035	dprint_dump_req(&tm_req, sizeof(tm_req)/4);
		3036	mpi3mr_soft_reset_handler(mrioc,
		3037	MPI3MR_RESET_FROM_TM_TIMEOUT, 1);
		3038	}
2664	goto out_unlock;	3039	goto out_unlock;
2665	}	3040	}
2666		3041
2667	if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)	3042	if (!(drv_cmd->state & MPI3MR_CMD_REPLY_VALID)) {
2668	tm_reply = (struct mpi3_scsi_task_mgmt_reply *)drv_cmd->reply;	3043	dprint_tm(mrioc, "invalid task management reply message\n");
2669
2670	if (drv_cmd->ioc_status != MPI3_IOCSTATUS_SUCCESS) {
2671	ioc_err(mrioc,
2672	"%s :Issue TM: handle(0x%04x) Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2673	__func__, handle, drv_cmd->ioc_status,
2674	drv_cmd->ioc_loginfo);
2675	retval = -1;	3044	retval = -1;
2676	goto out_unlock;	3045	goto out_unlock;
2677	}	3046	}
2678		3047
2679	if (!tm_reply) {	3048	tm_reply = (struct mpi3_scsi_task_mgmt_reply *)drv_cmd->reply;
2680	ioc_err(mrioc, "%s :Issue TM: No TM Reply message\n", __func__);	3049
		3050	switch (drv_cmd->ioc_status) {
		3051	case MPI3_IOCSTATUS_SUCCESS:
		3052	*resp_code = le32_to_cpu(tm_reply->response_data) &
		3053	MPI3MR_RI_MASK_RESPCODE;
		3054	break;
		3055	case MPI3_IOCSTATUS_SCSI_IOC_TERMINATED:
		3056	*resp_code = MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE;
		3057	break;
		3058	default:
		3059	dprint_tm(mrioc,
		3060	"task management request to handle(0x%04x) is failed with ioc_status(0x%04x) log_info(0x%08x)\n",
		3061	handle, drv_cmd->ioc_status, drv_cmd->ioc_loginfo);
2681	retval = -1;	3062	retval = -1;
2682	goto out_unlock;	3063	goto out_unlock;
2683	}	3064	}
2684		3065
2685	*resp_code = le32_to_cpu(tm_reply->response_data) &
2686	MPI3MR_RI_MASK_RESPCODE;
2687	switch (*resp_code) {	3066	switch (*resp_code) {
2688	case MPI3MR_RSP_TM_SUCCEEDED:	3067	case MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED:
2689	case MPI3MR_RSP_TM_COMPLETE:	3068	case MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE:
2690	break;	3069	break;
2691	case MPI3MR_RSP_IO_QUEUED_ON_IOC:	3070	case MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC:
2692	if (tm_type != MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK)	3071	if (tm_type != MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK)
2693	retval = -1;	3072	retval = -1;
2694	break;	3073	break;
@@ -2697,14 +3076,37 @@ static int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, · 2 unmodified lines
2697	break;	3076	break;
2698	}	3077	}
2699		3078
2700	ioc_info(mrioc,	3079	dprint_tm(mrioc,
2701	"%s :Issue TM: Completed TM type (0x%x) handle(0x%04x) ",	3080	"task management request type(%d) completed for handle(0x%04x) with ioc_status(0x%04x), log_info(0x%08x), termination_count(%d), response:%s(0x%x)\n",
2702	__func__, tm_type, handle);	3081	tm_type, handle, drv_cmd->ioc_status, drv_cmd->ioc_loginfo,
2703	ioc_info(mrioc,	3082	le32_to_cpu(tm_reply->termination_count),
2704	"with ioc_status(0x%04x), loginfo(0x%08x), term_count(0x%08x)\n",	3083	mpi3mr_tm_response_name(resp_code), resp_code);
2705	drv_cmd->ioc_status, drv_cmd->ioc_loginfo,	3084
2706	le32_to_cpu(tm_reply->termination_count));	3085	if (!retval) {
2707	mpi3mr_print_response_code(mrioc, *resp_code);	3086	mpi3mr_ioc_disable_intr(mrioc);
		3087	mpi3mr_poll_pend_io_completions(mrioc);
		3088	mpi3mr_ioc_enable_intr(mrioc);
		3089	mpi3mr_poll_pend_io_completions(mrioc);
		3090	}
		3091	switch (tm_type) {
		3092	case MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
		3093	if (!scsi_tgt_priv_data)
		3094	break;
		3095	scsi_tgt_priv_data->pend_count = 0;
		3096	blk_mq_tagset_busy_iter(&mrioc->shost->tag_set,
		3097	mpi3mr_count_tgt_pending,
		3098	(void *)scsi_tgt_priv_data->starget);
		3099	break;
		3100	case MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
		3101	if (!sdev_priv_data)
		3102	break;
		3103	sdev_priv_data->pend_count = 0;
		3104	blk_mq_tagset_busy_iter(&mrioc->shost->tag_set,
		3105	mpi3mr_count_dev_pending, (void *)sdev);
		3106	break;
		3107	default:
		3108	break;
		3109	}
2708		3110
2709	out_unlock:	3111	out_unlock:
2710	drv_cmd->state = MPI3MR_CMD_NOTUSED;	3112	drv_cmd->state = MPI3MR_CMD_NOTUSED;
@@ -2713,14 +3115,6 @@ out_unlock: · 2 unmodified lines
2713	atomic_dec_if_positive(&scsi_tgt_priv_data->block_io);	3115	atomic_dec_if_positive(&scsi_tgt_priv_data->block_io);
2714	if (tgtdev)	3116	if (tgtdev)
2715	mpi3mr_tgtdev_put(tgtdev);	3117	mpi3mr_tgtdev_put(tgtdev);
2716	if (!retval) {
2717	/*
2718	* Flush all IRQ handlers by calling synchronize_irq().
2719	* mpi3mr_ioc_disable_intr() takes care of it.
2720	*/
2721	mpi3mr_ioc_disable_intr(mrioc);
2722	mpi3mr_ioc_enable_intr(mrioc);
2723	}
2724	out:	3118	out:
2725	return retval;	3119	return retval;
2726	}	3120	}
@@ -2769,17 +3163,49 @@ static int mpi3mr_bios_param(struct scsi_device *sdev, · 42 unmodified lines
2769	* mpi3mr_map_queues - Map queues callback handler	3163	* mpi3mr_map_queues - Map queues callback handler
2770	* @shost: SCSI host reference	3164	* @shost: SCSI host reference
2771	*	3165	*
2772	* Call the blk_mq_pci_map_queues with from which operational	3166	* Maps default and poll queues.
2773	* queue the mapping has to be done
2774	*	3167	*
2775	* Return: return of blk_mq_pci_map_queues	3168	* Return: return zero.
2776	*/	3169	*/
2777	static int mpi3mr_map_queues(struct Scsi_Host *shost)	3170	static int mpi3mr_map_queues(struct Scsi_Host *shost)
2778	{	3171	{
2779	struct mpi3mr_ioc *mrioc = shost_priv(shost);	3172	struct mpi3mr_ioc *mrioc = shost_priv(shost);
		3173	int i, qoff, offset;
		3174	struct blk_mq_queue_map *map = NULL;
		3175
		3176	offset = mrioc->op_reply_q_offset;
		3177
		3178	for (i = 0, qoff = 0; i < HCTX_MAX_TYPES; i++) {
		3179	map = &shost->tag_set.map[i];
		3180
		3181	map->nr_queues = 0;
		3182
		3183	if (i == HCTX_TYPE_DEFAULT)
		3184	map->nr_queues = mrioc->default_qcount;
		3185	else if (i == HCTX_TYPE_POLL)
		3186	map->nr_queues = mrioc->active_poll_qcount;
		3187
		3188	if (!map->nr_queues) {
		3189	BUG_ON(i == HCTX_TYPE_DEFAULT);
		3190	continue;
		3191	}
		3192
		3193	/*
		3194	* The poll queue(s) doesn't have an IRQ (and hence IRQ
		3195	* affinity), so use the regular blk-mq cpu mapping
		3196	*/
		3197	map->queue_offset = qoff;
		3198	if (i != HCTX_TYPE_POLL)
		3199	blk_mq_pci_map_queues(map, mrioc->pdev, offset);
		3200	else
		3201	blk_mq_map_queues(map);
		3202
		3203	qoff += map->nr_queues;
		3204	offset += map->nr_queues;
		3205	}
		3206
		3207	return 0;
2780		3208
2781	return blk_mq_pci_map_queues(&shost->tag_set.map[HCTX_TYPE_DEFAULT],
2782	mrioc->pdev, mrioc->op_reply_q_offset);
2783	}	3209	}
2784		3210
2785	/**	3211	/**
@@ -2938,6 +3364,13 @@ static int mpi3mr_eh_target_reset(struct scsi_cmnd *scmd) · 152 unmodified lines
2938		3364
2939	stgt_priv_data = sdev_priv_data->tgt_priv_data;	3365	stgt_priv_data = sdev_priv_data->tgt_priv_data;
2940	dev_handle = stgt_priv_data->dev_handle;	3366	dev_handle = stgt_priv_data->dev_handle;
		3367	if (stgt_priv_data->dev_removed) {
		3368	sdev_printk(KERN_INFO, scmd->device,
		3369	"%s:target(handle = 0x%04x) is removed, target reset is not issued\n",
		3370	mrioc->name, dev_handle);
		3371	retval = FAILED;
		3372	goto out;
		3373	}
2941	sdev_printk(KERN_INFO, scmd->device,	3374	sdev_printk(KERN_INFO, scmd->device,
2942	"Target Reset is issued to handle(0x%04x)\n",	3375	"Target Reset is issued to handle(0x%04x)\n",
2943	dev_handle);	3376	dev_handle);
@@ -2945,15 +3378,22 @@ static int mpi3mr_eh_target_reset(struct scsi_cmnd *scmd) · 1 unmodified line
2945	ret = mpi3mr_issue_tm(mrioc,	3378	ret = mpi3mr_issue_tm(mrioc,
2946	MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET, dev_handle,	3379	MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET, dev_handle,
2947	sdev_priv_data->lun_id, MPI3MR_HOSTTAG_BLK_TMS,	3380	sdev_priv_data->lun_id, MPI3MR_HOSTTAG_BLK_TMS,
2948	MPI3MR_RESETTM_TIMEOUT, &mrioc->host_tm_cmds, &resp_code, NULL);	3381	MPI3MR_RESETTM_TIMEOUT, &mrioc->host_tm_cmds, &resp_code, scmd);
2949		3382
2950	if (ret)	3383	if (ret)
2951	goto out;	3384	goto out;
2952		3385
		3386	if (stgt_priv_data->pend_count) {
		3387	sdev_printk(KERN_INFO, scmd->device,
		3388	"%s: target has %d pending commands, target reset is failed\n",
		3389	mrioc->name, sdev_priv_data->pend_count);
		3390	goto out;
		3391	}
		3392
2953	retval = SUCCESS;	3393	retval = SUCCESS;
2954	out:	3394	out:
2955	sdev_printk(KERN_INFO, scmd->device,	3395	sdev_printk(KERN_INFO, scmd->device,
2956	"Target reset is %s for scmd(%p)\n",	3396	"%s: target reset is %s for scmd(%p)\n", mrioc->name,
2957	((retval == SUCCESS) ? "SUCCESS" : "FAILED"), scmd);	3397	((retval == SUCCESS) ? "SUCCESS" : "FAILED"), scmd);
2958		3398
2959	return retval;	3399	return retval;
@@ -2992,21 +3432,34 @@ static int mpi3mr_eh_dev_reset(struct scsi_cmnd *scmd) · 32 unmodified lines
2992		3432
2993	stgt_priv_data = sdev_priv_data->tgt_priv_data;	3433	stgt_priv_data = sdev_priv_data->tgt_priv_data;
2994	dev_handle = stgt_priv_data->dev_handle;	3434	dev_handle = stgt_priv_data->dev_handle;
		3435	if (stgt_priv_data->dev_removed) {
		3436	sdev_printk(KERN_INFO, scmd->device,
		3437	"%s: device(handle = 0x%04x) is removed, device(LUN) reset is not issued\n",
		3438	mrioc->name, dev_handle);
		3439	retval = FAILED;
		3440	goto out;
		3441	}
2995	sdev_printk(KERN_INFO, scmd->device,	3442	sdev_printk(KERN_INFO, scmd->device,
2996	"Device(lun) Reset is issued to handle(0x%04x)\n", dev_handle);	3443	"Device(lun) Reset is issued to handle(0x%04x)\n", dev_handle);
2997		3444
2998	ret = mpi3mr_issue_tm(mrioc,	3445	ret = mpi3mr_issue_tm(mrioc,
2999	MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET, dev_handle,	3446	MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET, dev_handle,
3000	sdev_priv_data->lun_id, MPI3MR_HOSTTAG_BLK_TMS,	3447	sdev_priv_data->lun_id, MPI3MR_HOSTTAG_BLK_TMS,
3001	MPI3MR_RESETTM_TIMEOUT, &mrioc->host_tm_cmds, &resp_code, NULL);	3448	MPI3MR_RESETTM_TIMEOUT, &mrioc->host_tm_cmds, &resp_code, scmd);
3002		3449
3003	if (ret)	3450	if (ret)
3004	goto out;	3451	goto out;
3005		3452
		3453	if (sdev_priv_data->pend_count) {
		3454	sdev_printk(KERN_INFO, scmd->device,
		3455	"%s: device has %d pending commands, device(LUN) reset is failed\n",
		3456	mrioc->name, sdev_priv_data->pend_count);
		3457	goto out;
		3458	}
3006	retval = SUCCESS;	3459	retval = SUCCESS;
3007	out:	3460	out:
3008	sdev_printk(KERN_INFO, scmd->device,	3461	sdev_printk(KERN_INFO, scmd->device,
3009	"Device(lun) reset is %s for scmd(%p)\n",	3462	"%s: device(LUN) reset is %s for scmd(%p)\n", mrioc->name,
3010	((retval == SUCCESS) ? "SUCCESS" : "FAILED"), scmd);	3463	((retval == SUCCESS) ? "SUCCESS" : "FAILED"), scmd);
3011		3464
3012	return retval;	3465	return retval;
@@ -3049,32 +3502,42 @@ static int mpi3mr_scan_finished(struct Scsi_Host *shost, · 36 unmodified lines
3049	{	3502	{
3050	struct mpi3mr_ioc *mrioc = shost_priv(shost);	3503	struct mpi3mr_ioc *mrioc = shost_priv(shost);
3051	u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;	3504	u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
		3505	u32 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
3052		3506
3053	if (time >= (pe_timeout * HZ)) {	3507	if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) \|\|
		3508	(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
		3509	ioc_err(mrioc, "port enable failed due to fault or reset\n");
		3510	mpi3mr_print_fault_info(mrioc);
		3511	mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
		3512	mrioc->scan_started = 0;
3054	mrioc->init_cmds.is_waiting = 0;	3513	mrioc->init_cmds.is_waiting = 0;
3055	mrioc->init_cmds.callback = NULL;	3514	mrioc->init_cmds.callback = NULL;
3056	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;	3515	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3057	ioc_err(mrioc, "%s :port enable request timed out\n", __func__);
3058	mrioc->is_driver_loading = 0;
3059	mpi3mr_soft_reset_handler(mrioc,
3060	MPI3MR_RESET_FROM_PE_TIMEOUT, 1);
3061	}	3516	}
3062		3517
3063	if (mrioc->scan_failed) {	3518	if (time >= (pe_timeout * HZ)) {
3064	ioc_err(mrioc,	3519	ioc_err(mrioc, "port enable failed due to time out\n");
3065	"%s :port enable failed with (ioc_status=0x%08x)\n",	3520	mpi3mr_check_rh_fault_ioc(mrioc,
3066	__func__, mrioc->scan_failed);	3521	MPI3MR_RESET_FROM_PE_TIMEOUT);
3067	mrioc->is_driver_loading = 0;	3522	mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3068	mrioc->stop_drv_processing = 1;	3523	mrioc->scan_started = 0;
3069	return 1;	3524	mrioc->init_cmds.is_waiting = 0;
		3525	mrioc->init_cmds.callback = NULL;
		3526	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3070	}	3527	}
3071		3528
3072	if (mrioc->scan_started)	3529	if (mrioc->scan_started)
3073	return 0;	3530	return 0;
3074	ioc_info(mrioc, "%s :port enable: SUCCESS\n", __func__);	3531
		3532	if (mrioc->scan_failed) {
		3533	ioc_err(mrioc,
		3534	"port enable failed with status=0x%04x\n",
		3535	mrioc->scan_failed);
		3536	} else
		3537	ioc_info(mrioc, "port enable is successfully completed\n");
		3538
3075	mpi3mr_start_watchdog(mrioc);	3539	mpi3mr_start_watchdog(mrioc);
3076	mrioc->is_driver_loading = 0;	3540	mrioc->is_driver_loading = 0;
3077
3078	return 1;	3541	return 1;
3079	}	3542	}
3080		3543
@@ -3189,10 +3652,18 @@ static int mpi3mr_slave_configure(struct scsi_device *sdev) · 108 unmodified lines
3189	switch (tgt_dev->dev_type) {	3652	switch (tgt_dev->dev_type) {
3190	case MPI3_DEVICE_DEVFORM_PCIE:	3653	case MPI3_DEVICE_DEVFORM_PCIE:
3191	/The block layer hw sector size = 512/	3654	/The block layer hw sector size = 512/
3192	blk_queue_max_hw_sectors(sdev->request_queue,	3655	if ((tgt_dev->dev_spec.pcie_inf.dev_info &
3193	tgt_dev->dev_spec.pcie_inf.mdts / 512);	3656	MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) ==
3194	blk_queue_virt_boundary(sdev->request_queue,	3657	MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE) {
3195	((1 << tgt_dev->dev_spec.pcie_inf.pgsz) - 1));	3658	blk_queue_max_hw_sectors(sdev->request_queue,
		3659	tgt_dev->dev_spec.pcie_inf.mdts / 512);
		3660	if (tgt_dev->dev_spec.pcie_inf.pgsz == 0)
		3661	blk_queue_virt_boundary(sdev->request_queue,
		3662	((1 << MPI3MR_DEFAULT_PGSZEXP) - 1));
		3663	else
		3664	blk_queue_virt_boundary(sdev->request_queue,
		3665	((1 << tgt_dev->dev_spec.pcie_inf.pgsz) - 1));
		3666	}
3196	break;	3667	break;
3197	default:	3668	default:
3198	break;	3669	break;
@@ -3312,9 +3783,22 @@ static bool mpi3mr_check_return_unmap(struct mpi3mr_ioc *mrioc, · 113 unmodified lines
3312	struct scsi_cmnd *scmd)	3783	struct scsi_cmnd *scmd)
3313	{	3784	{
3314	unsigned char *buf;	3785	unsigned char *buf;
3315	u16 param_len, desc_len;	3786	u16 param_len, desc_len, trunc_param_len;
3316		3787
3317	param_len = get_unaligned_be16(scmd->cmnd + 7);	3788	trunc_param_len = param_len = get_unaligned_be16(scmd->cmnd + 7);
		3789
		3790	if (mrioc->pdev->revision) {
		3791	if ((param_len > 24) && ((param_len - 8) & 0xF)) {
		3792	trunc_param_len -= (param_len - 8) & 0xF;
		3793	dprint_scsi_command(mrioc, scmd, MPI3_DEBUG_SCSI_ERROR);
		3794	dprint_scsi_err(mrioc,
		3795	"truncating param_len from (%d) to (%d)\n",
		3796	param_len, trunc_param_len);
		3797	put_unaligned_be16(trunc_param_len, scmd->cmnd + 7);
		3798	dprint_scsi_command(mrioc, scmd, MPI3_DEBUG_SCSI_ERROR);
		3799	}
		3800	return false;
		3801	}
3318		3802
3319	if (!param_len) {	3803	if (!param_len) {
3320	ioc_warn(mrioc,	3804	ioc_warn(mrioc,
@@ -3374,12 +3858,12 @@ static bool mpi3mr_check_return_unmap(struct mpi3mr_ioc *mrioc, · 53 unmodified lines
3374	}	3858	}
3375		3859
3376	if (param_len > (desc_len + 8)) {	3860	if (param_len > (desc_len + 8)) {
		3861	trunc_param_len = desc_len + 8;
3377	scsi_print_command(scmd);	3862	scsi_print_command(scmd);
3378	ioc_warn(mrioc,	3863	dprint_scsi_err(mrioc,
3379	"%s: Truncating param_len(%d) to desc_len+8(%d)\n",	3864	"truncating param_len(%d) to desc_len+8(%d)\n",
3380	__func__, param_len, (desc_len + 8));	3865	param_len, trunc_param_len);
3381	param_len = desc_len + 8;	3866	put_unaligned_be16(trunc_param_len, scmd->cmnd + 7);
3382	put_unaligned_be16(param_len, scmd->cmnd + 7);
3383	scsi_print_command(scmd);	3867	scsi_print_command(scmd);
3384	}	3868	}
3385		3869
@@ -3434,6 +3918,7 @@ static int mpi3mr_qcmd(struct Scsi_Host *shost, · 48 unmodified lines
3434	u32 scsiio_flags = 0;	3918	u32 scsiio_flags = 0;
3435	struct request *rq = scsi_cmd_to_rq(scmd);	3919	struct request *rq = scsi_cmd_to_rq(scmd);
3436	int iprio_class;	3920	int iprio_class;
		3921	u8 is_pcie_dev = 0;
3437		3922
3438	sdev_priv_data = scmd->device->hostdata;	3923	sdev_priv_data = scmd->device->hostdata;
3439	if (!sdev_priv_data \|\| !sdev_priv_data->tgt_priv_data) {	3924	if (!sdev_priv_data \|\| !sdev_priv_data->tgt_priv_data) {
@@ -3478,8 +3963,10 @@ static int mpi3mr_qcmd(struct Scsi_Host *shost, · 38 unmodified lines
3478	goto out;	3963	goto out;
3479	}	3964	}
3480		3965
3481	if ((scmd->cmnd[0] == UNMAP) &&	3966	if (stgt_priv_data->dev_type == MPI3_DEVICE_DEVFORM_PCIE)
3482	(stgt_priv_data->dev_type == MPI3_DEVICE_DEVFORM_PCIE) &&	3967	is_pcie_dev = 1;
		3968	if ((scmd->cmnd[0] == UNMAP) && is_pcie_dev &&
		3969	(mrioc->pdev->device == MPI3_MFGPAGE_DEVID_SAS4116) &&
3483	mpi3mr_check_return_unmap(mrioc, scmd))	3970	mpi3mr_check_return_unmap(mrioc, scmd))
3484	goto out;	3971	goto out;
3485		3972
@@ -3559,6 +4046,7 @@ static struct scsi_host_template mpi3mr_driver_template = { · 73 unmodified lines
3559	.eh_host_reset_handler = mpi3mr_eh_host_reset,	4046	.eh_host_reset_handler = mpi3mr_eh_host_reset,
3560	.bios_param = mpi3mr_bios_param,	4047	.bios_param = mpi3mr_bios_param,
3561	.map_queues = mpi3mr_map_queues,	4048	.map_queues = mpi3mr_map_queues,
		4049	.mq_poll = mpi3mr_blk_mq_poll,
3562	.no_write_same = 1,	4050	.no_write_same = 1,
3563	.can_queue = 1,	4051	.can_queue = 1,
3564	.this_id = -1,	4052	.this_id = -1,
@@ -3567,6 +4055,7 @@ static struct scsi_host_template mpi3mr_driver_template = { · 2 unmodified lines
3567	*/	4055	*/
3568	.max_sectors = 2048,	4056	.max_sectors = 2048,
3569	.cmd_per_lun = MPI3MR_MAX_CMDS_LUN,	4057	.cmd_per_lun = MPI3MR_MAX_CMDS_LUN,
		4058	.max_segment_size = 0xffffffff,
3570	.track_queue_depth = 1,	4059	.track_queue_depth = 1,
3571	.cmd_size = sizeof(struct scmd_priv),	4060	.cmd_size = sizeof(struct scmd_priv),
3572	};	4061	};
@@ -3714,6 +4203,7 @@ mpi3mr_probe(struct pci_dev pdev, const struct pci_device_id id) · 141 unmodified lines
3714	INIT_LIST_HEAD(&mrioc->fwevt_list);	4203	INIT_LIST_HEAD(&mrioc->fwevt_list);
3715	INIT_LIST_HEAD(&mrioc->tgtdev_list);	4204	INIT_LIST_HEAD(&mrioc->tgtdev_list);
3716	INIT_LIST_HEAD(&mrioc->delayed_rmhs_list);	4205	INIT_LIST_HEAD(&mrioc->delayed_rmhs_list);
		4206	INIT_LIST_HEAD(&mrioc->delayed_evtack_cmds_list);
3717		4207
3718	mutex_init(&mrioc->reset_mutex);	4208	mutex_init(&mrioc->reset_mutex);
3719	mpi3mr_init_drv_cmd(&mrioc->init_cmds, MPI3MR_HOSTTAG_INITCMDS);	4209	mpi3mr_init_drv_cmd(&mrioc->init_cmds, MPI3MR_HOSTTAG_INITCMDS);
@@ -3772,21 +4262,29 @@ mpi3mr_probe(struct pci_dev pdev, const struct pci_device_id id) · 52 unmodified lines
3772	ioc_err(mrioc, "failure at %s:%d/%s()!\n",	4262	ioc_err(mrioc, "failure at %s:%d/%s()!\n",
3773	__FILE__, __LINE__, __func__);	4263	__FILE__, __LINE__, __func__);
3774	retval = -ENODEV;	4264	retval = -ENODEV;
3775	goto out_fwevtthread_failed;	4265	goto fwevtthread_failed;
3776	}	4266	}
3777		4267
3778	mrioc->is_driver_loading = 1;	4268	mrioc->is_driver_loading = 1;
3779	if (mpi3mr_init_ioc(mrioc, MPI3MR_IT_INIT)) {	4269	mrioc->cpu_count = num_online_cpus();
3780	ioc_err(mrioc, "failure at %s:%d/%s()!\n",	4270	if (mpi3mr_setup_resources(mrioc)) {
3781	__FILE__, __LINE__, __func__);	4271	ioc_err(mrioc, "setup resources failed\n");
3782	retval = -ENODEV;	4272	retval = -ENODEV;
3783	goto out_iocinit_failed;	4273	goto resource_alloc_failed;
		4274	}
		4275	if (mpi3mr_init_ioc(mrioc)) {
		4276	ioc_err(mrioc, "initializing IOC failed\n");
		4277	retval = -ENODEV;
		4278	goto init_ioc_failed;
3784	}	4279	}
3785		4280
3786	shost->nr_hw_queues = mrioc->num_op_reply_q;	4281	shost->nr_hw_queues = mrioc->num_op_reply_q;
		4282	if (mrioc->active_poll_qcount)
		4283	shost->nr_maps = 3;
		4284
3787	shost->can_queue = mrioc->max_host_ios;	4285	shost->can_queue = mrioc->max_host_ios;
3788	shost->sg_tablesize = MPI3MR_SG_DEPTH;	4286	shost->sg_tablesize = MPI3MR_SG_DEPTH;
3789	shost->max_id = mrioc->facts.max_perids;	4287	shost->max_id = mrioc->facts.max_perids + 1;
3790		4288
3791	retval = scsi_add_host(shost, &pdev->dev);	4289	retval = scsi_add_host(shost, &pdev->dev);
3792	if (retval) {	4290	if (retval) {
@@ -3799,10 +4297,14 @@ mpi3mr_probe(struct pci_dev pdev, const struct pci_device_id id) · 6 unmodified lines
3799	return retval;	4297	return retval;
3800		4298
3801	addhost_failed:	4299	addhost_failed:
3802	mpi3mr_cleanup_ioc(mrioc, MPI3MR_COMPLETE_CLEANUP);	4300	mpi3mr_stop_watchdog(mrioc);
3803	out_iocinit_failed:	4301	mpi3mr_cleanup_ioc(mrioc);
		4302	init_ioc_failed:
		4303	mpi3mr_free_mem(mrioc);
		4304	mpi3mr_cleanup_resources(mrioc);
		4305	resource_alloc_failed:
3804	destroy_workqueue(mrioc->fwevt_worker_thread);	4306	destroy_workqueue(mrioc->fwevt_worker_thread);
3805	out_fwevtthread_failed:	4307	fwevtthread_failed:
3806	spin_lock(&mrioc_list_lock);	4308	spin_lock(&mrioc_list_lock);
3807	list_del(&mrioc->list);	4309	list_del(&mrioc->list);
3808	spin_unlock(&mrioc_list_lock);	4310	spin_unlock(&mrioc_list_lock);
@@ -3815,6 +4317,7 @@ shost_failed: · 6 unmodified lines
3815	* mpi3mr_remove - PCI remove callback	4317	* mpi3mr_remove - PCI remove callback
3816	* @pdev: PCI device instance	4318	* @pdev: PCI device instance
3817	*	4319	*
		4320	* Cleanup the IOC by issuing MUR and shutdown notification.
3818	* Free up all memory and resources associated with the	4321	* Free up all memory and resources associated with the
3819	* controllerand target devices, unregister the shost.	4322	* controllerand target devices, unregister the shost.
3820	*	4323	*
@@ -3851,7 +4354,10 @@ static void mpi3mr_remove(struct pci_dev *pdev) · 30 unmodified lines
3851	mpi3mr_tgtdev_del_from_list(mrioc, tgtdev);	4354	mpi3mr_tgtdev_del_from_list(mrioc, tgtdev);
3852	mpi3mr_tgtdev_put(tgtdev);	4355	mpi3mr_tgtdev_put(tgtdev);
3853	}	4356	}
3854	mpi3mr_cleanup_ioc(mrioc, MPI3MR_COMPLETE_CLEANUP);	4357	mpi3mr_stop_watchdog(mrioc);
		4358	mpi3mr_cleanup_ioc(mrioc);
		4359	mpi3mr_free_mem(mrioc);
		4360	mpi3mr_cleanup_resources(mrioc);
3855		4361
3856	spin_lock(&mrioc_list_lock);	4362	spin_lock(&mrioc_list_lock);
3857	list_del(&mrioc->list);	4363	list_del(&mrioc->list);
@@ -3891,7 +4397,10 @@ static void mpi3mr_shutdown(struct pci_dev *pdev) · 33 unmodified lines
3891	spin_unlock_irqrestore(&mrioc->fwevt_lock, flags);	4397	spin_unlock_irqrestore(&mrioc->fwevt_lock, flags);
3892	if (wq)	4398	if (wq)
3893	destroy_workqueue(wq);	4399	destroy_workqueue(wq);
3894	mpi3mr_cleanup_ioc(mrioc, MPI3MR_COMPLETE_CLEANUP);	4400
		4401	mpi3mr_stop_watchdog(mrioc);
		4402	mpi3mr_cleanup_ioc(mrioc);
		4403	mpi3mr_cleanup_resources(mrioc);
3895	}	4404	}
3896		4405
3897	#ifdef CONFIG_PM	4406	#ifdef CONFIG_PM
@@ -3921,7 +4430,7 @@ static int mpi3mr_suspend(struct pci_dev *pdev, pm_message_t state) · 23 unmodified lines
3921	mpi3mr_cleanup_fwevt_list(mrioc);	4430	mpi3mr_cleanup_fwevt_list(mrioc);
3922	scsi_block_requests(shost);	4431	scsi_block_requests(shost);
3923	mpi3mr_stop_watchdog(mrioc);	4432	mpi3mr_stop_watchdog(mrioc);
3924	mpi3mr_cleanup_ioc(mrioc, MPI3MR_SUSPEND);	4433	mpi3mr_cleanup_ioc(mrioc);
3925		4434
3926	device_state = pci_choose_state(pdev, state);	4435	device_state = pci_choose_state(pdev, state);
3927	ioc_info(mrioc, "pdev=0x%p, slot=%s, entering operating state [D%d]\n",	4436	ioc_info(mrioc, "pdev=0x%p, slot=%s, entering operating state [D%d]\n",
@@ -3970,7 +4479,11 @@ static int mpi3mr_resume(struct pci_dev *pdev) · 42 unmodified lines
3970		4479
3971	mrioc->stop_drv_processing = 0;	4480	mrioc->stop_drv_processing = 0;
3972	mpi3mr_memset_buffers(mrioc);	4481	mpi3mr_memset_buffers(mrioc);
3973	mpi3mr_init_ioc(mrioc, MPI3MR_IT_RESUME);	4482	r = mpi3mr_reinit_ioc(mrioc, 1);
		4483	if (r) {
		4484	ioc_err(mrioc, "resuming controller failed[%d]\n", r);
		4485	return r;
		4486	}
3974	scsi_unblock_requests(shost);	4487	scsi_unblock_requests(shost);
3975	mpi3mr_start_watchdog(mrioc);	4488	mpi3mr_start_watchdog(mrioc);
3976		4489
@@ -3980,8 +4493,8 @@ static int mpi3mr_resume(struct pci_dev *pdev) · 3 unmodified lines
3980		4493
3981	static const struct pci_device_id mpi3mr_pci_id_table[] = {	4494	static const struct pci_device_id mpi3mr_pci_id_table[] = {
3982	{	4495	{
3983	PCI_DEVICE_SUB(PCI_VENDOR_ID_LSI_LOGIC, 0x00A5,	4496	PCI_DEVICE_SUB(MPI3_MFGPAGE_VENDORID_BROADCOM,
3984	PCI_ANY_ID, PCI_ANY_ID)	4497	MPI3_MFGPAGE_DEVID_SAS4116, PCI_ANY_ID, PCI_ANY_ID)
3985	},	4498	},
3986	{ 0 }	4499	{ 0 }
3987	};	4500	};

drivers/scsi/mvsas/mv_sas.c+5−0

 	while (sha->sas_port[i]) {
 		if (sha->sas_port[i] == dev->port) {
+			spin_lock(&sha->sas_port[i]->phy_list_lock);
 			phy =  container_of(sha->sas_port[i]->phy_list.next,
 				struct asd_sas_phy, port_phy_el);
+			spin_unlock(&sha->sas_port[i]->phy_list_lock);
 			j = 0;
 			while (sha->sas_phy[j]) {
 				if (sha->sas_phy[j] == phy)
 	while (sha->sas_port[i]) {
 		if (sha->sas_port[i] == dev->port) {
 			struct asd_sas_phy *phy;
+			spin_lock(&sha->sas_port[i]->phy_list_lock);
 			list_for_each_entry(phy,
 				&sha->sas_port[i]->phy_list, port_phy_el) {
 				j = 0;
 				num++;
 				n++;
 			}
+			spin_unlock(&sha->sas_port[i]->phy_list_lock);
 			break;
 		}
 		i++;

drivers/scsi/myrb.c+1−1

@@ -1674,7 +1674,7 @@ static int myrb_pdev_slave_alloc(struct scsi_device *sdev) · 1673 unmodified lines
1674	if (sdev->id > MYRB_MAX_TARGETS)	1674	if (sdev->id > MYRB_MAX_TARGETS)
1675	return -ENXIO;	1675	return -ENXIO;
1676		1676
1677	pdev_info = kzalloc(sizeof(*pdev_info), GFP_KERNEL\|GFP_DMA);	1677	pdev_info = kzalloc(sizeof(*pdev_info), GFP_KERNEL);
1678	if (!pdev_info)	1678	if (!pdev_info)
1679	return -ENOMEM;	1679	return -ENOMEM;
1680		1680

drivers/scsi/myrs.c+4−6

 		cs->fwstat_buf = NULL;
 		goto out_free;
 	}
-	cs->ctlr_info = kzalloc(sizeof(struct myrs_ctlr_info),
+	cs->ctlr_info = kzalloc(sizeof(struct myrs_ctlr_info), GFP_KERNEL);
-				GFP_KERNEL | GFP_DMA);
 	if (!cs->ctlr_info)
 		goto out_free;
-	cs->event_buf = kzalloc(sizeof(struct myrs_event),
+	cs->event_buf = kzalloc(sizeof(struct myrs_event), GFP_KERNEL);
-				GFP_KERNEL | GFP_DMA);
 	if (!cs->event_buf)
 		goto out_free;
 		ldev_num = myrs_translate_ldev(cs, sdev);
-		ldev_info = kzalloc(sizeof(*ldev_info), GFP_KERNEL|GFP_DMA);
+		ldev_info = kzalloc(sizeof(*ldev_info), GFP_KERNEL);
 		if (!ldev_info)
 			return -ENOMEM;
 	} else {
 		struct myrs_pdev_info *pdev_info;
-		pdev_info = kzalloc(sizeof(*pdev_info), GFP_KERNEL|GFP_DMA);
+		pdev_info = kzalloc(sizeof(*pdev_info), GFP_KERNEL);
 		if (!pdev_info)
 			return -ENOMEM;

drivers/scsi/pm8001/Makefile+5−2

@@ -6,9 +6,12 @@ · 5 unmodified lines
6		6
7		7
8	obj-$(CONFIG_SCSI_PM8001) += pm80xx.o	8	obj-$(CONFIG_SCSI_PM8001) += pm80xx.o
		9
		10	CFLAGS_pm80xx_tracepoints.o := -I$(src)
		11
9	pm80xx-y += pm8001_init.o \	12	pm80xx-y += pm8001_init.o \
10	pm8001_sas.o \	13	pm8001_sas.o \
11	pm8001_ctl.o \	14	pm8001_ctl.o \
12	pm8001_hwi.o \	15	pm8001_hwi.o \
13	pm80xx_hwi.o	16	pm80xx_hwi.o \
14		17	pm80xx_tracepoints.o

drivers/scsi/pm8001/pm8001_ctl.c+12−12

 static DEVICE_ATTR(update_fw, S_IRUGO|S_IWUSR|S_IWGRP,
 	pm8001_show_update_fw, pm8001_store_update_fw);
-/**
- * ctl_mpi_state_show - controller MPI state check
- * @cdev: pointer to embedded class device
- * @buf: the buffer returned
- *
- * A sysfs 'read-only' shost attribute.
- */
 static const char *const mpiStateText[] = {
 	"MPI is not initialized",
 	"MPI is successfully initialized",
 	"MPI initialization failed with error in [31:16]"
 };
+/**
+ * ctl_mpi_state_show - controller MPI state check
+ * @cdev: pointer to embedded class device
+ * @attr: device attribute (unused)
+ * @buf: the buffer returned
+ *
+ * A sysfs 'read-only' shost attribute.
+ */
 static ssize_t ctl_mpi_state_show(struct device *cdev,
 		struct device_attribute *attr, char *buf)
 {
 /**
  * ctl_hmi_error_show - controller MPI initialization fails
  * @cdev: pointer to embedded class device
+ * @attr: device attribute (unused)
  * @buf: the buffer returned
  *
  * A sysfs 'read-only' shost attribute.
  */
 static ssize_t ctl_hmi_error_show(struct device *cdev,
 		struct device_attribute *attr, char *buf)
 {
 /**
  * ctl_raae_count_show - controller raae count check
  * @cdev: pointer to embedded class device
+ * @attr: device attribute (unused)
  * @buf: the buffer returned
  *
  * A sysfs 'read-only' shost attribute.
  */
 static ssize_t ctl_raae_count_show(struct device *cdev,
 		struct device_attribute *attr, char *buf)
 {
 /**
  * ctl_iop0_count_show - controller iop0 count check
  * @cdev: pointer to embedded class device
+ * @attr: device attribute (unused)
  * @buf: the buffer returned
  *
  * A sysfs 'read-only' shost attribute.
  */
 static ssize_t ctl_iop0_count_show(struct device *cdev,
 		struct device_attribute *attr, char *buf)
 {
 /**
  * ctl_iop1_count_show - controller iop1 count check
  * @cdev: pointer to embedded class device
+ * @attr: device attribute (unused)
  * @buf: the buffer returned
  *
  * A sysfs 'read-only' shost attribute.
  */
 static ssize_t ctl_iop1_count_show(struct device *cdev,
 		struct device_attribute *attr, char *buf)
 {

drivers/scsi/pm8001/pm8001_hwi.c+12−21

  #include "pm8001_hwi.h"
  #include "pm8001_chips.h"
  #include "pm8001_ctl.h"
+ #include "pm80xx_tracepoints.h"
 /**
  * read_main_config_table - read the configure table and save it.
 	unsigned long flags;
 	int q_index = circularQ - pm8001_ha->inbnd_q_tbl;
 	int rv;
+	u32 htag = le32_to_cpu(*(__le32 *)payload);
+	trace_pm80xx_mpi_build_cmd(pm8001_ha->id, opCode, htag, q_index,
+		circularQ->producer_idx, le32_to_cpu(circularQ->consumer_index));
+	if (WARN_ON(q_index >= pm8001_ha->max_q_num))
+		return -EINVAL;
-	WARN_ON(q_index >= PM8001_MAX_INB_NUM);
 	spin_lock_irqsave(&circularQ->iq_lock, flags);
 	rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
 			&pMessage);
 	psataPayload = (struct sata_completion_resp *)(piomb + 4);
 	status = le32_to_cpu(psataPayload->status);
+	param = le32_to_cpu(psataPayload->param);
 	tag = le32_to_cpu(psataPayload->tag);
 	if (!tag) {
 		pm8001_dbg(pm8001_ha, FAIL, "tag null\n");
 		return;
 	}
 	ccb = &pm8001_ha->ccb_info[tag];
-	param = le32_to_cpu(psataPayload->param);
+	t = ccb->task;
-	if (ccb) {
+	pm8001_dev = ccb->device;
-		t = ccb->task;
-		pm8001_dev = ccb->device;
-	} else {
-		pm8001_dbg(pm8001_ha, FAIL, "ccb null\n");
-		return;
-	}
 	if (t) {
 		if (t->dev && (t->dev->lldd_dev))
 	}
 	ts = &t->task_status;
-	if (!ts) {
-		pm8001_dbg(pm8001_ha, FAIL, "ts null\n");
-		return;
-	}
 	if (status)
 		pm8001_dbg(pm8001_ha, IOERR,
 	u32 dev_id = le32_to_cpu(psataPayload->device_id);
 	unsigned long flags;
-	ccb = &pm8001_ha->ccb_info[tag];
-	if (ccb) {
-		t = ccb->task;
-		pm8001_dev = ccb->device;
-	} else {
-		pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n");
-	}
 	if (event)
 		pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);

drivers/scsi/pm8001/pm8001_init.c+2−2

@@ -179,7 +179,7 @@ static void pm8001_free(struct pm8001_hba_info *pm8001_ha) · 178 unmodified lines
179	}	179	}
180	PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);	180	PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
181	flush_workqueue(pm8001_wq);	181	flush_workqueue(pm8001_wq);
182	kfree(pm8001_ha->tags);	182	bitmap_free(pm8001_ha->tags);
183	kfree(pm8001_ha);	183	kfree(pm8001_ha);
184	}	184	}
185		185
@@ -1192,7 +1192,7 @@ pm8001_init_ccb_tag(struct pm8001_hba_info pm8001_ha, struct Scsi_Host shost, · 1006 unmodified lines
1192	can_queue = ccb_count - PM8001_RESERVE_SLOT;	1192	can_queue = ccb_count - PM8001_RESERVE_SLOT;
1193	shost->can_queue = can_queue;	1193	shost->can_queue = can_queue;
1194		1194
1195	pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL);	1195	pm8001_ha->tags = bitmap_zalloc(ccb_count, GFP_KERNEL);
1196	if (!pm8001_ha->tags)	1196	if (!pm8001_ha->tags)
1197	goto err_out;	1197	goto err_out;
1198		1198

drivers/scsi/pm8001/pm8001_sas.c+16−0

 #include <linux/slab.h>
 #include "pm8001_sas.h"
+#include "pm80xx_tracepoints.h"
 /**
  * pm8001_find_tag - from sas task to find out  tag that belongs to this task
 void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
 	struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx)
 {
+	struct ata_queued_cmd *qc;
+	struct pm8001_device *pm8001_dev;
 	if (!ccb->task)
 		return;
 	if (!sas_protocol_ata(task->task_proto))
 		/* do nothing */
 		break;
 	}
+	if (sas_protocol_ata(task->task_proto)) {
+		// For SCSI/ATA commands uldd_task points to ata_queued_cmd
+		qc = task->uldd_task;
+		pm8001_dev = ccb->device;
+		trace_pm80xx_request_complete(pm8001_ha->id,
+			pm8001_dev ? pm8001_dev->attached_phy : PM8001_MAX_PHYS,
+			ccb_idx, 0 /* ctlr_opcode not known */,
+			qc ? qc->tf.command : 0, // ata opcode
+			pm8001_dev ? atomic_read(&pm8001_dev->running_req) : -1);
+	}
 	task->lldd_task = NULL;
 	ccb->task = NULL;
 	ccb->ccb_tag = 0xFFFFFFFF;

drivers/scsi/pm8001/pm80xx_hwi.c+16−22

  #include "pm80xx_hwi.h"
  #include "pm8001_chips.h"
  #include "pm8001_ctl.h"
+#include "pm80xx_tracepoints.h"
 #define SMP_DIRECT 1
 #define SMP_INDIRECT 2
 	psataPayload = (struct sata_completion_resp *)(piomb + 4);
 	status = le32_to_cpu(psataPayload->status);
+	param = le32_to_cpu(psataPayload->param);
 	tag = le32_to_cpu(psataPayload->tag);
 	if (!tag) {
 		pm8001_dbg(pm8001_ha, FAIL, "tag null\n");
 		return;
 	}
 	ccb = &pm8001_ha->ccb_info[tag];
-	param = le32_to_cpu(psataPayload->param);
+	t = ccb->task;
-	if (ccb) {
+	pm8001_dev = ccb->device;
-		t = ccb->task;
-		pm8001_dev = ccb->device;
-	} else {
-		pm8001_dbg(pm8001_ha, FAIL, "ccb null\n");
-		return;
-	}
 	if (t) {
 		if (t->dev && (t->dev->lldd_dev))
 	}
 	ts = &t->task_status;
-	if (!ts) {
-		pm8001_dbg(pm8001_ha, FAIL, "ts null\n");
-		return;
-	}
 	if (status != IO_SUCCESS) {
 		pm8001_dbg(pm8001_ha, FAIL,
 	u32 dev_id = le32_to_cpu(psataPayload->device_id);
 	unsigned long flags;
-	ccb = &pm8001_ha->ccb_info[tag];
-	if (ccb) {
-		t = ccb->task;
-		pm8001_dev = ccb->device;
-	} else {
-		pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n");
-		return;
-	}
 	if (event)
 		pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
 		return;
 	}
+	ccb = &pm8001_ha->ccb_info[tag];
+	t = ccb->task;
+	pm8001_dev = ccb->device;
 	if (unlikely(!t || !t->lldd_task || !t->dev)) {
 		pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
 		return;
 	u32 status =
 		le32_to_cpu(pPayload->status);
 	u32 phy_id =
-		le32_to_cpu(pPayload->phyid);
+		le32_to_cpu(pPayload->phyid) & 0xFF;
 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
 	pm8001_dbg(pm8001_ha, INIT,
 	struct sas_task *task = ccb->task;
 	struct domain_device *dev = task->dev;
 	struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
+	struct ata_queued_cmd *qc = task->uldd_task;
 	u32 tag = ccb->ccb_tag;
 	int ret;
 	u32 q_index, cpu_id;
 			}
 		}
 	}
+	trace_pm80xx_request_issue(pm8001_ha->id,
+				ccb->device ? ccb->device->attached_phy : PM8001_MAX_PHYS,
+				ccb->ccb_tag, opc,
+				qc ? qc->tf.command : 0, // ata opcode
+				ccb->device ? atomic_read(&ccb->device->running_req) : 0);
 	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
 			&sata_cmd, sizeof(sata_cmd), q_index);
 	return ret;

drivers/scsi/pm8001/pm80xx_tracepoints.c+10−0

@@ -0,0 +1,10 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Trace events in pm8001 driver.
	4	*
	5	* Copyright 2020 Google LLC
	6	* Author: Akshat Jain <akshatzen@google.com>
	7	*/
	8
	9	#define CREATE_TRACE_POINTS
	10	#include "pm80xx_tracepoints.h"

drivers/scsi/pm8001/pm80xx_tracepoints.h+113−0

@@ -0,0 +1,113 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Trace events in pm8001 driver.
	4	*
	5	* Copyright 2020 Google LLC
	6	* Author: Akshat Jain <akshatzen@google.com>
	7	*/
	8
	9	#undef TRACE_SYSTEM
	10	#define TRACE_SYSTEM pm80xx
	11
	12	#if !defined(_TRACE_PM80XX_H) \|\| defined(TRACE_HEADER_MULTI_READ)
	13	#define _TRACE_PM80XX_H
	14
	15	#include <linux/tracepoint.h>
	16	#include "pm8001_sas.h"
	17
	18	TRACE_EVENT(pm80xx_request_issue,
	19	TP_PROTO(u32 id, u32 phy_id, u32 htag, u32 ctlr_opcode,
	20	u16 ata_opcode, int running_req),
	21
	22	TP_ARGS(id, phy_id, htag, ctlr_opcode, ata_opcode, running_req),
	23
	24	TP_STRUCT__entry(
	25	__field(u32, id)
	26	__field(u32, phy_id)
	27	__field(u32, htag)
	28	__field(u32, ctlr_opcode)
	29	__field(u16, ata_opcode)
	30	__field(int, running_req)
	31	),
	32
	33	TP_fast_assign(
	34	__entry->id = id;
	35	__entry->phy_id = phy_id;
	36	__entry->htag = htag;
	37	__entry->ctlr_opcode = ctlr_opcode;
	38	__entry->ata_opcode = ata_opcode;
	39	__entry->running_req = running_req;
	40	),
	41
	42	TP_printk("ctlr_id = %u phy_id = %u htag = %#x, ctlr_opcode = %#x ata_opcode = %#x running_req = %d",
	43	__entry->id, __entry->phy_id, __entry->htag,
	44	__entry->ctlr_opcode, __entry->ata_opcode,
	45	__entry->running_req)
	46	);
	47
	48	TRACE_EVENT(pm80xx_request_complete,
	49	TP_PROTO(u32 id, u32 phy_id, u32 htag, u32 ctlr_opcode,
	50	u16 ata_opcode, int running_req),
	51
	52	TP_ARGS(id, phy_id, htag, ctlr_opcode, ata_opcode, running_req),
	53
	54	TP_STRUCT__entry(
	55	__field(u32, id)
	56	__field(u32, phy_id)
	57	__field(u32, htag)
	58	__field(u32, ctlr_opcode)
	59	__field(u16, ata_opcode)
	60	__field(int, running_req)
	61	),
	62
	63	TP_fast_assign(
	64	__entry->id = id;
	65	__entry->phy_id = phy_id;
	66	__entry->htag = htag;
	67	__entry->ctlr_opcode = ctlr_opcode;
	68	__entry->ata_opcode = ata_opcode;
	69	__entry->running_req = running_req;
	70	),
	71
	72	TP_printk("ctlr_id = %u phy_id = %u htag = %#x, ctlr_opcode = %#x ata_opcode = %#x running_req = %d",
	73	__entry->id, __entry->phy_id, __entry->htag,
	74	__entry->ctlr_opcode, __entry->ata_opcode,
	75	__entry->running_req)
	76	);
	77
	78	TRACE_EVENT(pm80xx_mpi_build_cmd,
	79	TP_PROTO(u32 id, u32 opc, u32 htag, u32 qi, u32 pi, u32 ci),
	80
	81	TP_ARGS(id, opc, htag, qi, pi, ci),
	82
	83	TP_STRUCT__entry(
	84	__field(u32, id)
	85	__field(u32, opc)
	86	__field(u32, htag)
	87	__field(u32, qi)
	88	__field(u32, pi)
	89	__field(u32, ci)
	90	),
	91
	92	TP_fast_assign(
	93	__entry->id = id;
	94	__entry->opc = opc;
	95	__entry->htag = htag;
	96	__entry->qi = qi;
	97	__entry->pi = pi;
	98	__entry->ci = ci;
	99	),
	100
	101	TP_printk("ctlr_id = %u opc = %#x htag = %#x QI = %u PI = %u CI = %u",
	102	__entry->id, __entry->opc, __entry->htag, __entry->qi,
	103	__entry->pi, __entry->ci)
	104	);
	105
	106	#endif /* _TRACE_PM80XX_H_ */
	107
	108	#undef TRACE_INCLUDE_PATH
	109	#undef TRACE_INCLUDE_FILE
	110	#define TRACE_INCLUDE_PATH .
	111	#define TRACE_INCLUDE_FILE pm80xx_tracepoints
	112
	113	#include <trace/define_trace.h>

drivers/scsi/pmcraid.c+2−3

 		return NULL;
 	sglist->order = order;
-	sgl_alloc_order(buflen, order, false,
+	sgl_alloc_order(buflen, order, false, GFP_KERNEL | __GFP_ZERO,
-			GFP_KERNEL | GFP_DMA | __GFP_ZERO, &sglist->num_sg);
+			&sglist->num_sg);
 	return sglist;
 }
 /**
  * pmcraid_queuecommand_lck - Queue a mid-layer request
  * @scsi_cmd: scsi command struct
- * @done: done function
  *
  * This function queues a request generated by the mid-layer. Midlayer calls
  * this routine within host->lock. Some of the functions called by queuecommand

drivers/scsi/qedi/qedi_main.c+2−6

 	int i;
 	struct scsi_bd *pbl;
 	u64 *list;
-	dma_addr_t page;
 	/* Alloc dma memory for BDQ buffers */
 	for (i = 0; i < QEDI_BDQ_NUM; i++) {
 	qedi->bdq_pbl_list_num_entries = qedi->bdq_pbl_mem_size /
 					 QEDI_PAGE_SIZE;
 	list = (u64 *)qedi->bdq_pbl_list;
-	page = qedi->bdq_pbl_list_dma;
 	for (i = 0; i < qedi->bdq_pbl_list_num_entries; i++) {
 		*list = qedi->bdq_pbl_dma;
 		list++;
-		page += QEDI_PAGE_SIZE;
 	}
 	return 0;
 		rc = snprintf(buf, ip_len, fmt, gw);
 		break;
 	case ISCSI_BOOT_ETH_FLAGS:
-		rc = snprintf(buf, 3, "%hhd\n",
+		rc = snprintf(buf, 3, "%d\n", (char)SYSFS_FLAG_FW_SEL_BOOT);
-			      SYSFS_FLAG_FW_SEL_BOOT);
 		break;
 	case ISCSI_BOOT_ETH_INDEX:
 		rc = snprintf(buf, 3, "0\n");
 			     mchap_secret);
 		break;
 	case ISCSI_BOOT_TGT_FLAGS:
-		rc = snprintf(buf, 3, "%hhd\n", SYSFS_FLAG_FW_SEL_BOOT);
+		rc = snprintf(buf, 3, "%d\n", (char)SYSFS_FLAG_FW_SEL_BOOT);
 		break;
 	case ISCSI_BOOT_TGT_NIC_ASSOC:
 		rc = snprintf(buf, 3, "0\n");

drivers/scsi/qla2xxx/qla_attr.c+6−0

 static inline void
 qla2x00_set_rport_loss_tmo(struct fc_rport *rport, uint32_t timeout)
 {
+	fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
 	rport->dev_loss_tmo = timeout ? timeout : 1;
+	if (IS_ENABLED(CONFIG_NVME_FC) && fcport && fcport->nvme_remote_port)
+		nvme_fc_set_remoteport_devloss(fcport->nvme_remote_port,
+					       rport->dev_loss_tmo);
 }
 static void

drivers/scsi/qla2xxx/qla_init.c+3−7

 	qla2x00_dfs_create_rport(vha, fcport);
-	if (NVME_TARGET(vha->hw, fcport)) {
-		qla_nvme_register_remote(vha, fcport);
-		qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE);
-		qla2x00_set_fcport_state(fcport, FCS_ONLINE);
-		return;
-	}
 	qla24xx_update_fcport_fcp_prio(vha, fcport);
 	switch (vha->host->active_mode) {
 		break;
 	}
+	if (NVME_TARGET(vha->hw, fcport))
+		qla_nvme_register_remote(vha, fcport);
 	qla2x00_set_fcport_state(fcport, FCS_ONLINE);
 	if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) {

drivers/scsi/qla2xxx/qla_nvme.c+4−1

 	req.port_name = wwn_to_u64(fcport->port_name);
 	req.node_name = wwn_to_u64(fcport->node_name);
 	req.port_role = 0;
-	req.dev_loss_tmo = 0;
+	req.dev_loss_tmo = fcport->dev_loss_tmo;
 	if (fcport->nvme_prli_service_param & NVME_PRLI_SP_INITIATOR)
 		req.port_role = FC_PORT_ROLE_NVME_INITIATOR;
 		return ret;
 	}
+	nvme_fc_set_remoteport_devloss(fcport->nvme_remote_port,
+				       fcport->dev_loss_tmo);
 	if (fcport->nvme_prli_service_param & NVME_PRLI_SP_SLER)
 		ql_log(ql_log_info, vha, 0x212a,
 		       "PortID:%06x Supports SLER\n", req.port_id);

drivers/scsi/qla4xxx/ql4_os.c+2−2

@@ -5734,7 +5734,7 @@ static ssize_t qla4xxx_show_boot_eth_info(void data, int type, char buf) · 5733 unmodified lines
5734		5734
5735	switch (type) {	5735	switch (type) {
5736	case ISCSI_BOOT_ETH_FLAGS:	5736	case ISCSI_BOOT_ETH_FLAGS:
5737	rc = sprintf(str, "%d\n", SYSFS_FLAG_FW_SEL_BOOT);	5737	rc = sprintf(str, "%d\n", (char)SYSFS_FLAG_FW_SEL_BOOT);
5738	break;	5738	break;
5739	case ISCSI_BOOT_ETH_INDEX:	5739	case ISCSI_BOOT_ETH_INDEX:
5740	rc = sprintf(str, "0\n");	5740	rc = sprintf(str, "0\n");
@@ -5843,7 +5843,7 @@ qla4xxx_show_boot_tgt_info(struct ql4_boot_session_info *boot_sess, int type, · 102 unmodified lines
5843	(char *)&boot_conn->chap.intr_secret);	5843	(char *)&boot_conn->chap.intr_secret);
5844	break;	5844	break;
5845	case ISCSI_BOOT_TGT_FLAGS:	5845	case ISCSI_BOOT_TGT_FLAGS:
5846	rc = sprintf(str, "%d\n", SYSFS_FLAG_FW_SEL_BOOT);	5846	rc = sprintf(str, "%d\n", (char)SYSFS_FLAG_FW_SEL_BOOT);
5847	break;	5847	break;
5848	case ISCSI_BOOT_TGT_NIC_ASSOC:	5848	case ISCSI_BOOT_TGT_NIC_ASSOC:
5849	rc = sprintf(str, "0\n");	5849	rc = sprintf(str, "0\n");

drivers/scsi/scsi.c+2−3

 #include <linux/notifier.h>
 #include <linux/cpu.h>
 #include <linux/mutex.h>
-#include <linux/async.h>
 #include <asm/unaligned.h>
 #include <scsi/scsi.h>
 /*
- * 1024 is big enough for saturating the fast scsi LUN now
+ * 1024 is big enough for saturating fast SCSI LUNs.
  */
 int scsi_device_max_queue_depth(struct scsi_device *sdev)
 {
-	return max_t(int, sdev->host->can_queue, 1024);
+	return min_t(int, sdev->host->can_queue, 1024);
 }
 /**

drivers/scsi/scsi_debugfs.c+1−0

@@ -9,6 +9,7 @@ · 8 unmodified lines
9	static const char *const scsi_cmd_flags[] = {	9	static const char *const scsi_cmd_flags[] = {
10	SCSI_CMD_FLAG_NAME(TAGGED),	10	SCSI_CMD_FLAG_NAME(TAGGED),
11	SCSI_CMD_FLAG_NAME(INITIALIZED),	11	SCSI_CMD_FLAG_NAME(INITIALIZED),
		12	SCSI_CMD_FLAG_NAME(LAST),
12	};	13	};
13	#undef SCSI_CMD_FLAG_NAME	14	#undef SCSI_CMD_FLAG_NAME
14		15

drivers/scsi/scsi_error.c+57−55

@@ -133,23 +133,6 @@ static bool scsi_eh_should_retry_cmd(struct scsi_cmnd *cmd) · 132 unmodified lines
133	return true;	133	return true;
134	}	134	}
135		135
136	static void scsi_eh_complete_abort(struct scsi_cmnd scmd, struct Scsi_Host shost)
137	{
138	unsigned long flags;
139
140	spin_lock_irqsave(shost->host_lock, flags);
141	list_del_init(&scmd->eh_entry);
142	/*
143	* If the abort succeeds, and there is no further
144	* EH action, clear the ->last_reset time.
145	*/
146	if (list_empty(&shost->eh_abort_list) &&
147	list_empty(&shost->eh_cmd_q))
148	if (shost->eh_deadline != -1)
149	shost->last_reset = 0;
150	spin_unlock_irqrestore(shost->host_lock, flags);
151	}
152
153	/**	136	/**
154	* scmd_eh_abort_handler - Handle command aborts	137	* scmd_eh_abort_handler - Handle command aborts
155	* @work: command to be aborted.	138	* @work: command to be aborted.
@@ -166,54 +149,72 @@ scmd_eh_abort_handler(struct work_struct *work) · 10 unmodified lines
166	struct scsi_cmnd *scmd =	149	struct scsi_cmnd *scmd =
167	container_of(work, struct scsi_cmnd, abort_work.work);	150	container_of(work, struct scsi_cmnd, abort_work.work);
168	struct scsi_device *sdev = scmd->device;	151	struct scsi_device *sdev = scmd->device;
		152	struct Scsi_Host *shost = sdev->host;
169	enum scsi_disposition rtn;	153	enum scsi_disposition rtn;
170	unsigned long flags;	154	unsigned long flags;
171		155
172	if (scsi_host_eh_past_deadline(sdev->host)) {	156	if (scsi_host_eh_past_deadline(shost)) {
173	SCSI_LOG_ERROR_RECOVERY(3,	157	SCSI_LOG_ERROR_RECOVERY(3,
174	scmd_printk(KERN_INFO, scmd,	158	scmd_printk(KERN_INFO, scmd,
175	"eh timeout, not aborting\n"));	159	"eh timeout, not aborting\n"));
176	} else {	160	goto out;
177	SCSI_LOG_ERROR_RECOVERY(3,	161	}
		162
		163	SCSI_LOG_ERROR_RECOVERY(3,
178	scmd_printk(KERN_INFO, scmd,	164	scmd_printk(KERN_INFO, scmd,
179	"aborting command\n"));	165	"aborting command\n"));
180	rtn = scsi_try_to_abort_cmd(sdev->host->hostt, scmd);	166	rtn = scsi_try_to_abort_cmd(shost->hostt, scmd);
181	if (rtn == SUCCESS) {	167	if (rtn != SUCCESS) {
182	set_host_byte(scmd, DID_TIME_OUT);	168	SCSI_LOG_ERROR_RECOVERY(3,
183	if (scsi_host_eh_past_deadline(sdev->host)) {	169	scmd_printk(KERN_INFO, scmd,
184	SCSI_LOG_ERROR_RECOVERY(3,	170	"cmd abort %s\n",
185	scmd_printk(KERN_INFO, scmd,	171	(rtn == FAST_IO_FAIL) ?
186	"eh timeout, not retrying "	172	"not send" : "failed"));
187	"aborted command\n"));	173	goto out;
188	} else if (!scsi_noretry_cmd(scmd) &&	174	}
189	scsi_cmd_retry_allowed(scmd) &&	175	set_host_byte(scmd, DID_TIME_OUT);
190	scsi_eh_should_retry_cmd(scmd)) {	176	if (scsi_host_eh_past_deadline(shost)) {
191	SCSI_LOG_ERROR_RECOVERY(3,	177	SCSI_LOG_ERROR_RECOVERY(3,
192	scmd_printk(KERN_WARNING, scmd,	178	scmd_printk(KERN_INFO, scmd,
193	"retry aborted command\n"));	179	"eh timeout, not retrying "
194	scsi_eh_complete_abort(scmd, sdev->host);	180	"aborted command\n"));
195	scsi_queue_insert(scmd, SCSI_MLQUEUE_EH_RETRY);	181	goto out;
196	return;
197	} else {
198	SCSI_LOG_ERROR_RECOVERY(3,
199	scmd_printk(KERN_WARNING, scmd,
200	"finish aborted command\n"));
201	scsi_eh_complete_abort(scmd, sdev->host);
202	scsi_finish_command(scmd);
203	return;
204	}
205	} else {
206	SCSI_LOG_ERROR_RECOVERY(3,
207	scmd_printk(KERN_INFO, scmd,
208	"cmd abort %s\n",
209	(rtn == FAST_IO_FAIL) ?
210	"not send" : "failed"));
211	}
212	}	182	}
213		183
214	spin_lock_irqsave(sdev->host->host_lock, flags);	184	spin_lock_irqsave(shost->host_lock, flags);
215	list_del_init(&scmd->eh_entry);	185	list_del_init(&scmd->eh_entry);
216	spin_unlock_irqrestore(sdev->host->host_lock, flags);	186
		187	/*
		188	* If the abort succeeds, and there is no further
		189	* EH action, clear the ->last_reset time.
		190	*/
		191	if (list_empty(&shost->eh_abort_list) &&
		192	list_empty(&shost->eh_cmd_q))
		193	if (shost->eh_deadline != -1)
		194	shost->last_reset = 0;
		195
		196	spin_unlock_irqrestore(shost->host_lock, flags);
		197
		198	if (!scsi_noretry_cmd(scmd) &&
		199	scsi_cmd_retry_allowed(scmd) &&
		200	scsi_eh_should_retry_cmd(scmd)) {
		201	SCSI_LOG_ERROR_RECOVERY(3,
		202	scmd_printk(KERN_WARNING, scmd,
		203	"retry aborted command\n"));
		204	scsi_queue_insert(scmd, SCSI_MLQUEUE_EH_RETRY);
		205	} else {
		206	SCSI_LOG_ERROR_RECOVERY(3,
		207	scmd_printk(KERN_WARNING, scmd,
		208	"finish aborted command\n"));
		209	scsi_finish_command(scmd);
		210	}
		211	return;
		212
		213	out:
		214	spin_lock_irqsave(shost->host_lock, flags);
		215	list_del_init(&scmd->eh_entry);
		216	spin_unlock_irqrestore(shost->host_lock, flags);
		217
217	scsi_eh_scmd_add(scmd);	218	scsi_eh_scmd_add(scmd);
218	}	219	}
219		220
@@ -1429,7 +1430,8 @@ static int scsi_eh_try_stu(struct scsi_cmnd *scmd) · 1209 unmodified lines
1429	enum scsi_disposition rtn = NEEDS_RETRY;	1430	enum scsi_disposition rtn = NEEDS_RETRY;
1430		1431
1431	for (i = 0; rtn == NEEDS_RETRY && i < 2; i++)	1432	for (i = 0; rtn == NEEDS_RETRY && i < 2; i++)
1432	rtn = scsi_send_eh_cmnd(scmd, stu_command, 6, scmd->device->request_queue->rq_timeout, 0);	1433	rtn = scsi_send_eh_cmnd(scmd, stu_command, 6,
		1434	scmd->device->eh_timeout, 0);
1433		1435
1434	if (rtn == SUCCESS)	1436	if (rtn == SUCCESS)
1435	return 0;	1437	return 0;

drivers/scsi/scsi_pm.c+1−2

 #include <linux/pm_runtime.h>
 #include <linux/export.h>
-#include <linux/async.h>
 #include <linux/blk-pm.h>
 #include <scsi/scsi.h>
 	blk_pre_runtime_resume(sdev->request_queue);
 	if (pm && pm->runtime_resume)
 		err = pm->runtime_resume(dev);
-	blk_post_runtime_resume(sdev->request_queue, err);
+	blk_post_runtime_resume(sdev->request_queue);
 	return err;
 }

drivers/scsi/scsi_priv.h+1−2

 #define _SCSI_PRIV_H
 #include <linux/device.h>
-#include <linux/async.h>
 #include <scsi/scsi_device.h>
 #include <linux/sbitmap.h>
 extern void __scsi_remove_device(struct scsi_device *);
 extern struct bus_type scsi_bus_type;
-extern const struct attribute_group scsi_shost_attr_group;
+extern const struct attribute_group *scsi_shost_groups[];
 /* scsi_netlink.c */
 #ifdef CONFIG_SCSI_NETLINK

drivers/scsi/scsi_scan.c+2−2

@@ -97,7 +97,7 @@ MODULE_PARM_DESC(max_luns, · 96 unmodified lines
97	#define SCSI_SCAN_TYPE_DEFAULT "sync"	97	#define SCSI_SCAN_TYPE_DEFAULT "sync"
98	#endif	98	#endif
99		99
100	char scsi_scan_type[7] = SCSI_SCAN_TYPE_DEFAULT;	100	static char scsi_scan_type[7] = SCSI_SCAN_TYPE_DEFAULT;
101		101
102	module_param_string(scan, scsi_scan_type, sizeof(scsi_scan_type),	102	module_param_string(scan, scsi_scan_type, sizeof(scsi_scan_type),
103	S_IRUGO\|S_IWUSR);	103	S_IRUGO\|S_IWUSR);
@@ -122,7 +122,7 @@ struct async_scan_data { · 18 unmodified lines
122	struct completion prev_finished;	122	struct completion prev_finished;
123	};	123	};
124		124
125	/**	125	/*
126	* scsi_enable_async_suspend - Enable async suspend and resume	126	* scsi_enable_async_suspend - Enable async suspend and resume
127	*/	127	*/
128	void scsi_enable_async_suspend(struct device *dev)	128	void scsi_enable_async_suspend(struct device *dev)

drivers/scsi/scsi_sysfs.c+6−1

 	NULL
 };
-const struct attribute_group scsi_shost_attr_group = {
+static const struct attribute_group scsi_shost_attr_group = {
 	.attrs =	scsi_sysfs_shost_attrs,
 };
+const struct attribute_group *scsi_shost_groups[] = {
+	&scsi_shost_attr_group,
+	NULL
+};
 static void scsi_device_cls_release(struct device *class_dev)
 {
 	struct scsi_device *sdev;

drivers/scsi/sd.c+0−1

@@ -51,7 +51,6 @@ · 50 unmodified lines
51	#include <linux/major.h>	51	#include <linux/major.h>
52	#include <linux/mutex.h>	52	#include <linux/mutex.h>
53	#include <linux/string_helpers.h>	53	#include <linux/string_helpers.h>
54	#include <linux/async.h>
55	#include <linux/slab.h>	54	#include <linux/slab.h>
56	#include <linux/sed-opal.h>	55	#include <linux/sed-opal.h>
57	#include <linux/pm_runtime.h>	56	#include <linux/pm_runtime.h>

drivers/scsi/sd_zbc.c+3−3

 	zone.len = logical_to_sectors(sdp, get_unaligned_be64(&buf[8]));
 	zone.capacity = zone.len;
 	zone.start = logical_to_sectors(sdp, get_unaligned_be64(&buf[16]));
-	zone.wp = logical_to_sectors(sdp, get_unaligned_be64(&buf[24]));
+	if (zone.cond == ZBC_ZONE_COND_FULL)
-	if (zone.type != ZBC_ZONE_TYPE_CONV &&
-	    zone.cond == ZBC_ZONE_COND_FULL)
 		zone.wp = zone.start + zone.len;
+	else
+		zone.wp = logical_to_sectors(sdp, get_unaligned_be64(&buf[24]));
 	ret = cb(&zone, idx, data);
 	if (ret)

drivers/scsi/snic/snic_disc.c+1−1

@@ -100,7 +100,7 @@ snic_queue_report_tgt_req(struct snic *snic) · 99 unmodified lines
100	SNIC_BUG_ON(ntgts == 0);	100	SNIC_BUG_ON(ntgts == 0);
101	buf_len = ntgts * sizeof(struct snic_tgt_id) + SNIC_SG_DESC_ALIGN;	101	buf_len = ntgts * sizeof(struct snic_tgt_id) + SNIC_SG_DESC_ALIGN;
102		102
103	buf = kzalloc(buf_len, GFP_KERNEL\|GFP_DMA);	103	buf = kzalloc(buf_len, GFP_KERNEL);
104	if (!buf) {	104	if (!buf) {
105	snic_req_free(snic, rqi);	105	snic_req_free(snic, rqi);
106	SNIC_HOST_ERR(snic->shost, "Resp Buf Alloc Failed.\n");	106	SNIC_HOST_ERR(snic->shost, "Resp Buf Alloc Failed.\n");

drivers/scsi/sr.c+1−1

@@ -855,7 +855,7 @@ static void get_capabilities(struct scsi_cd *cd) · 854 unmodified lines
855		855
856		856
857	/* allocate transfer buffer */	857	/* allocate transfer buffer */
858	buffer = kmalloc(512, GFP_KERNEL \| GFP_DMA);	858	buffer = kmalloc(512, GFP_KERNEL);
859	if (!buffer) {	859	if (!buffer) {
860	sr_printk(KERN_ERR, cd, "out of memory.\n");	860	sr_printk(KERN_ERR, cd, "out of memory.\n");
861	return;	861	return;

drivers/scsi/sr_vendor.c+2−2

@@ -131,7 +131,7 @@ int sr_set_blocklength(Scsi_CD *cd, int blocklength) · 130 unmodified lines
131	if (cd->vendor == VENDOR_TOSHIBA)	131	if (cd->vendor == VENDOR_TOSHIBA)
132	density = (blocklength > 2048) ? 0x81 : 0x83;	132	density = (blocklength > 2048) ? 0x81 : 0x83;
133		133
134	buffer = kmalloc(512, GFP_KERNEL \| GFP_DMA);	134	buffer = kmalloc(512, GFP_KERNEL);
135	if (!buffer)	135	if (!buffer)
136	return -ENOMEM;	136	return -ENOMEM;
137		137
@@ -179,7 +179,7 @@ int sr_cd_check(struct cdrom_device_info *cdi) · 41 unmodified lines
179	if (cd->cdi.mask & CDC_MULTI_SESSION)	179	if (cd->cdi.mask & CDC_MULTI_SESSION)
180	return 0;	180	return 0;
181		181
182	buffer = kmalloc(512, GFP_KERNEL \| GFP_DMA);	182	buffer = kmalloc(512, GFP_KERNEL);
183	if (!buffer)	183	if (!buffer)
184	return -ENOMEM;	184	return -ENOMEM;
185		185

drivers/scsi/ufs/Kconfig+8−7

 	  However, do not compile this as a module if your root file system
 	  (the one containing the directory /) is located on a UFS device.
+if SCSI_UFSHCD
 config SCSI_UFSHCD_PCI
 	tristate "PCI bus based UFS Controller support"
-	depends on SCSI_UFSHCD && PCI
+	depends on PCI
 	help
 	  This selects the PCI UFS Host Controller Interface. Select this if
 	  you have UFS Host Controller with PCI Interface.
 config SCSI_UFSHCD_PLATFORM
 	tristate "Platform bus based UFS Controller support"
-	depends on SCSI_UFSHCD
 	depends on HAS_IOMEM
 	help
 	  This selects the UFS host controller support. Select this if
 config SCSI_UFS_BSG
 	bool "Universal Flash Storage BSG device node"
-	depends on SCSI_UFSHCD
 	select BLK_DEV_BSGLIB
 	help
 	  Universal Flash Storage (UFS) is SCSI transport specification for
 config SCSI_UFS_CRYPTO
 	bool "UFS Crypto Engine Support"
-	depends on SCSI_UFSHCD && BLK_INLINE_ENCRYPTION
+	depends on BLK_INLINE_ENCRYPTION
 	help
 	  Enable Crypto Engine Support in UFS.
 	  Enabling this makes it possible for the kernel to use the crypto
 config SCSI_UFS_HPB
 	bool "Support UFS Host Performance Booster"
-	depends on SCSI_UFSHCD
 	help
 	  The UFS HPB feature improves random read performance. It caches
 	  L2P (logical to physical) map of UFS to host DRAM. The driver uses HPB
 config SCSI_UFS_FAULT_INJECTION
 	bool "UFS Fault Injection Support"
-	depends on SCSI_UFSHCD && FAULT_INJECTION
+	depends on FAULT_INJECTION
 	help
 	  Enable fault injection support in the UFS driver. This makes it easier
 	  to test the UFS error handler and abort handler.
 config SCSI_UFS_HWMON
-	bool "UFS  Temperature Notification"
+	bool "UFS Temperature Notification"
 	depends on SCSI_UFSHCD=HWMON || HWMON=y
 	help
 	  This provides support for UFS hardware monitoring. If enabled,
 	  a hardware monitoring device will be created for the UFS device.
 	  If unsure, say N.
+endif

drivers/scsi/ufs/tc-dwc-g210-pci.c+0−1

@@ -110,7 +110,6 @@ tc_dwc_g210_pci_probe(struct pci_dev pdev, const struct pci_device_id id) · 109 unmodified lines
110	return err;	110	return err;
111	}	111	}
112		112
113	pci_set_drvdata(pdev, hba);
114	pm_runtime_put_noidle(&pdev->dev);	113	pm_runtime_put_noidle(&pdev->dev);
115	pm_runtime_allow(&pdev->dev);	114	pm_runtime_allow(&pdev->dev);
116		115

drivers/scsi/ufs/ufs-exynos.c+2−2

@@ -853,14 +853,14 @@ static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba, · 852 unmodified lines
853	}	853	}
854		854
855	static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba,	855	static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba,
856	int tag, bool op)	856	int tag, bool is_scsi_cmd)
857	{	857	{
858	struct exynos_ufs *ufs = ufshcd_get_variant(hba);	858	struct exynos_ufs *ufs = ufshcd_get_variant(hba);
859	u32 type;	859	u32 type;
860		860
861	type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);	861	type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);
862		862
863	if (op)	863	if (is_scsi_cmd)
864	hci_writel(ufs, type \| (1 << tag), HCI_UTRL_NEXUS_TYPE);	864	hci_writel(ufs, type \| (1 << tag), HCI_UTRL_NEXUS_TYPE);
865	else	865	else
866	hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE);	866	hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE);

drivers/scsi/ufs/ufs-hisi.c+7−1

 	return ret;
 }
+static int ufs_hisi_suspend_prepare(struct device *dev)
+{
+	/* RPM and SPM are different. Refer ufs_hisi_suspend() */
+	return __ufshcd_suspend_prepare(dev, false);
+}
 static int ufs_hisi_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
 	enum ufs_notify_change_status status)
 {
 static const struct dev_pm_ops ufs_hisi_pm_ops = {
 	SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
 	SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
-	.prepare	 = ufshcd_suspend_prepare,
+	.prepare	 = ufs_hisi_suspend_prepare,
 	.complete	 = ufshcd_resume_complete,
 };

drivers/scsi/ufs/ufshcd-pci.c+0−2

@@ -538,8 +538,6 @@ ufshcd_pci_probe(struct pci_dev pdev, const struct pci_device_id id) · 537 unmodified lines
538	return err;	538	return err;
539	}	539	}
540		540
541	pci_set_drvdata(pdev, hba);
542
543	hba->vops = (struct ufs_hba_variant_ops *)id->driver_data;	541	hba->vops = (struct ufs_hba_variant_ops *)id->driver_data;
544		542
545	err = ufshcd_init(hba, mmio_base, pdev->irq);	543	err = ufshcd_init(hba, mmio_base, pdev->irq);

drivers/scsi/ufs/ufshcd-pltfrm.c+0−2

@@ -361,8 +361,6 @@ int ufshcd_pltfrm_init(struct platform_device *pdev, · 360 unmodified lines
361	goto dealloc_host;	361	goto dealloc_host;
362	}	362	}
363		363
364	platform_set_drvdata(pdev, hba);
365
366	pm_runtime_set_active(&pdev->dev);	364	pm_runtime_set_active(&pdev->dev);
367	pm_runtime_enable(&pdev->dev);	365	pm_runtime_enable(&pdev->dev);
368		366

drivers/scsi/ufs/ufshcd.c+206−141

@@ -128,8 +128,9 @@ EXPORT_SYMBOL_GPL(ufshcd_dump_regs); · 127 unmodified lines
128	enum {	128	enum {
129	UFSHCD_MAX_CHANNEL = 0,	129	UFSHCD_MAX_CHANNEL = 0,
130	UFSHCD_MAX_ID = 1,	130	UFSHCD_MAX_ID = 1,
131	UFSHCD_CMD_PER_LUN = 32,	131	UFSHCD_NUM_RESERVED = 1,
132	UFSHCD_CAN_QUEUE = 32,	132	UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED,
		133	UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED,
133	};	134	};
134		135
135	static const char *const ufshcd_state_name[] = {	136	static const char *const ufshcd_state_name[] = {
@@ -1069,13 +1070,32 @@ static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, · 933 unmodified lines
1069	return false;	1070	return false;
1070	}	1071	}
1071		1072
		1073	/*
		1074	* Determine the number of pending commands by counting the bits in the SCSI
		1075	* device budget maps. This approach has been selected because a bit is set in
		1076	* the budget map before scsi_host_queue_ready() checks the host_self_blocked
		1077	* flag. The host_self_blocked flag can be modified by calling
		1078	* scsi_block_requests() or scsi_unblock_requests().
		1079	*/
		1080	static u32 ufshcd_pending_cmds(struct ufs_hba *hba)
		1081	{
		1082	struct scsi_device *sdev;
		1083	u32 pending = 0;
		1084
		1085	lockdep_assert_held(hba->host->host_lock);
		1086	__shost_for_each_device(sdev, hba->host)
		1087	pending += sbitmap_weight(&sdev->budget_map);
		1088
		1089	return pending;
		1090	}
		1091
1072	static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,	1092	static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1073	u64 wait_timeout_us)	1093	u64 wait_timeout_us)
1074	{	1094	{
1075	unsigned long flags;	1095	unsigned long flags;
1076	int ret = 0;	1096	int ret = 0;
1077	u32 tm_doorbell;	1097	u32 tm_doorbell;
1078	u32 tr_doorbell;	1098	u32 tr_pending;
1079	bool timeout = false, do_last_check = false;	1099	bool timeout = false, do_last_check = false;
1080	ktime_t start;	1100	ktime_t start;
1081		1101
@@ -1093,8 +1113,8 @@ static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, · 11 unmodified lines
1093	}	1113	}
1094		1114
1095	tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);	1115	tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1096	tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);	1116	tr_pending = ufshcd_pending_cmds(hba);
1097	if (!tm_doorbell && !tr_doorbell) {	1117	if (!tm_doorbell && !tr_pending) {
1098	timeout = false;	1118	timeout = false;
1099	break;	1119	break;
1100	} else if (do_last_check) {	1120	} else if (do_last_check) {
@@ -1114,12 +1134,12 @@ static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, · 13 unmodified lines
1114	do_last_check = true;	1134	do_last_check = true;
1115	}	1135	}
1116	spin_lock_irqsave(hba->host->host_lock, flags);	1136	spin_lock_irqsave(hba->host->host_lock, flags);
1117	} while (tm_doorbell \|\| tr_doorbell);	1137	} while (tm_doorbell \|\| tr_pending);
1118		1138
1119	if (timeout) {	1139	if (timeout) {
1120	dev_err(hba->dev,	1140	dev_err(hba->dev,
1121	"%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",	1141	"%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1122	__func__, tm_doorbell, tr_doorbell);	1142	__func__, tm_doorbell, tr_pending);
1123	ret = -EBUSY;	1143	ret = -EBUSY;
1124	}	1144	}
1125	out:	1145	out:
@@ -1352,25 +1372,6 @@ out: · 226 unmodified lines
1352	return ret;	1372	return ret;
1353	}	1373	}
1354		1374
1355	static bool ufshcd_is_busy(struct request req, void priv, bool reserved)
1356	{
1357	int *busy = priv;
1358
1359	WARN_ON_ONCE(reserved);
1360	(*busy)++;
1361	return false;
1362	}
1363
1364	/* Whether or not any tag is in use by a request that is in progress. */
1365	static bool ufshcd_any_tag_in_use(struct ufs_hba *hba)
1366	{
1367	struct request_queue *q = hba->cmd_queue;
1368	int busy = 0;
1369
1370	blk_mq_tagset_busy_iter(q->tag_set, ufshcd_is_busy, &busy);
1371	return busy;
1372	}
1373
1374	static int ufshcd_devfreq_get_dev_status(struct device *dev,	1375	static int ufshcd_devfreq_get_dev_status(struct device *dev,
1375	struct devfreq_dev_status *stat)	1376	struct devfreq_dev_status *stat)
1376	{	1377	{
@@ -1666,7 +1667,8 @@ int ufshcd_hold(struct ufs_hba *hba, bool async) · 289 unmodified lines
1666	bool flush_result;	1667	bool flush_result;
1667	unsigned long flags;	1668	unsigned long flags;
1668		1669
1669	if (!ufshcd_is_clkgating_allowed(hba))	1670	if (!ufshcd_is_clkgating_allowed(hba) \|\|
		1671	!hba->clk_gating.is_initialized)
1670	goto out;	1672	goto out;
1671	spin_lock_irqsave(hba->host->host_lock, flags);	1673	spin_lock_irqsave(hba->host->host_lock, flags);
1672	hba->clk_gating.active_reqs++;	1674	hba->clk_gating.active_reqs++;
@@ -1769,7 +1771,7 @@ static void ufshcd_gate_work(struct work_struct *work) · 96 unmodified lines
1769		1771
1770	if (hba->clk_gating.active_reqs	1772	if (hba->clk_gating.active_reqs
1771	\|\| hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL	1773	\|\| hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1772	\|\| ufshcd_any_tag_in_use(hba) \|\| hba->outstanding_tasks	1774	\|\| hba->outstanding_reqs \|\| hba->outstanding_tasks
1773	\|\| hba->active_uic_cmd \|\| hba->uic_async_done)	1775	\|\| hba->active_uic_cmd \|\| hba->uic_async_done)
1774	goto rel_lock;	1776	goto rel_lock;
1775		1777
@@ -1826,7 +1828,7 @@ static void __ufshcd_release(struct ufs_hba *hba) · 50 unmodified lines
1826		1828
1827	if (hba->clk_gating.active_reqs \|\| hba->clk_gating.is_suspended \|\|	1829	if (hba->clk_gating.active_reqs \|\| hba->clk_gating.is_suspended \|\|
1828	hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL \|\|	1830	hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL \|\|
1829	hba->outstanding_tasks \|\|	1831	hba->outstanding_tasks \|\| !hba->clk_gating.is_initialized \|\|
1830	hba->active_uic_cmd \|\| hba->uic_async_done \|\|	1832	hba->active_uic_cmd \|\| hba->uic_async_done \|\|
1831	hba->clk_gating.state == CLKS_OFF)	1833	hba->clk_gating.state == CLKS_OFF)
1832	return;	1834	return;
@@ -1961,11 +1963,15 @@ static void ufshcd_exit_clk_gating(struct ufs_hba *hba) · 128 unmodified lines
1961	{	1963	{
1962	if (!hba->clk_gating.is_initialized)	1964	if (!hba->clk_gating.is_initialized)
1963	return;	1965	return;
		1966
1964	ufshcd_remove_clk_gating_sysfs(hba);	1967	ufshcd_remove_clk_gating_sysfs(hba);
1965	cancel_work_sync(&hba->clk_gating.ungate_work);	1968
1966	cancel_delayed_work_sync(&hba->clk_gating.gate_work);	1969	/* Ungate the clock if necessary. */
1967	destroy_workqueue(hba->clk_gating.clk_gating_workq);	1970	ufshcd_hold(hba, false);
1968	hba->clk_gating.is_initialized = false;	1971	hba->clk_gating.is_initialized = false;
		1972	ufshcd_release(hba);
		1973
		1974	destroy_workqueue(hba->clk_gating.clk_gating_workq);
1969	}	1975	}
1970		1976
1971	/* Must be called with host lock acquired */	1977	/* Must be called with host lock acquired */
@@ -2189,6 +2195,7 @@ static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) · 217 unmodified lines
2189	hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;	2195	hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2190	hba->nutmrs =	2196	hba->nutmrs =
2191	((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;	2197	((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
		2198	hba->reserved_slot = hba->nutrs - 1;
2192		2199
2193	/* Read crypto capabilities */	2200	/* Read crypto capabilities */
2194	err = ufshcd_hba_init_crypto_capabilities(hba);	2201	err = ufshcd_hba_init_crypto_capabilities(hba);
@@ -2650,17 +2657,42 @@ static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) · 455 unmodified lines
2650	return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) \| SCSI_W_LUN_BASE;	2657	return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) \| SCSI_W_LUN_BASE;
2651	}	2658	}
2652		2659
2653	static inline bool is_rpmb_wlun(struct scsi_device *sdev)
2654	{
2655	return sdev->lun == ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN);
2656	}
2657
2658	static inline bool is_device_wlun(struct scsi_device *sdev)	2660	static inline bool is_device_wlun(struct scsi_device *sdev)
2659	{	2661	{
2660	return sdev->lun ==	2662	return sdev->lun ==
2661	ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);	2663	ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2662	}	2664	}
2663		2665
		2666	/*
		2667	* Associate the UFS controller queue with the default and poll HCTX types.
		2668	* Initialize the mq_map[] arrays.
		2669	*/
		2670	static int ufshcd_map_queues(struct Scsi_Host *shost)
		2671	{
		2672	int i, ret;
		2673
		2674	for (i = 0; i < shost->nr_maps; i++) {
		2675	struct blk_mq_queue_map *map = &shost->tag_set.map[i];
		2676
		2677	switch (i) {
		2678	case HCTX_TYPE_DEFAULT:
		2679	case HCTX_TYPE_POLL:
		2680	map->nr_queues = 1;
		2681	break;
		2682	case HCTX_TYPE_READ:
		2683	map->nr_queues = 0;
		2684	break;
		2685	default:
		2686	WARN_ON_ONCE(true);
		2687	}
		2688	map->queue_offset = 0;
		2689	ret = blk_mq_map_queues(map);
		2690	WARN_ON_ONCE(ret);
		2691	}
		2692
		2693	return 0;
		2694	}
		2695
2664	static void ufshcd_init_lrb(struct ufs_hba hba, struct ufshcd_lrb lrb, int i)	2696	static void ufshcd_init_lrb(struct ufs_hba hba, struct ufshcd_lrb lrb, int i)
2665	{	2697	{
2666	struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;	2698	struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;
@@ -2696,10 +2728,13 @@ static int ufshcd_queuecommand(struct Scsi_Host host, struct scsi_cmnd cmd) · 29 unmodified lines
2696	struct ufshcd_lrb *lrbp;	2728	struct ufshcd_lrb *lrbp;
2697	int err = 0;	2729	int err = 0;
2698		2730
2699	WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);	2731	WARN_ONCE(tag < 0 \|\| tag >= hba->nutrs, "Invalid tag %d\n", tag);
2700		2732
2701	if (!down_read_trylock(&hba->clk_scaling_lock))	2733	/*
2702	return SCSI_MLQUEUE_HOST_BUSY;	2734	* Allows the UFS error handler to wait for prior ufshcd_queuecommand()
		2735	* calls.
		2736	*/
		2737	rcu_read_lock();
2703		2738
2704	switch (hba->ufshcd_state) {	2739	switch (hba->ufshcd_state) {
2705	case UFSHCD_STATE_OPERATIONAL:	2740	case UFSHCD_STATE_OPERATIONAL:
@@ -2779,8 +2814,9 @@ static int ufshcd_queuecommand(struct Scsi_Host host, struct scsi_cmnd cmd) · 73 unmodified lines
2779	}	2814	}
2780		2815
2781	ufshcd_send_command(hba, tag);	2816	ufshcd_send_command(hba, tag);
		2817
2782	out:	2818	out:
2783	up_read(&hba->clk_scaling_lock);	2819	rcu_read_unlock();
2784		2820
2785	if (ufs_trigger_eh()) {	2821	if (ufs_trigger_eh()) {
2786	unsigned long flags;	2822	unsigned long flags;
@@ -2936,30 +2972,15 @@ static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, · 149 unmodified lines
2936	static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,	2972	static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2937	enum dev_cmd_type cmd_type, int timeout)	2973	enum dev_cmd_type cmd_type, int timeout)
2938	{	2974	{
2939	struct request_queue *q = hba->cmd_queue;
2940	DECLARE_COMPLETION_ONSTACK(wait);	2975	DECLARE_COMPLETION_ONSTACK(wait);
2941	struct request *req;	2976	const u32 tag = hba->reserved_slot;
2942	struct ufshcd_lrb *lrbp;	2977	struct ufshcd_lrb *lrbp;
2943	int err;	2978	int err;
2944	int tag;
2945		2979
2946	down_read(&hba->clk_scaling_lock);	2980	/* Protects use of hba->reserved_slot. */
		2981	lockdep_assert_held(&hba->dev_cmd.lock);
2947		2982
2948	/*	2983	down_read(&hba->clk_scaling_lock);
2949	* Get free slot, sleep if slots are unavailable.
2950	* Even though we use wait_event() which sleeps indefinitely,
2951	* the maximum wait time is bounded by SCSI request timeout.
2952	*/
2953	req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0);
2954	if (IS_ERR(req)) {
2955	err = PTR_ERR(req);
2956	goto out_unlock;
2957	}
2958	tag = req->tag;
2959	WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
2960	/* Set the timeout such that the SCSI error handler is not activated. */
2961	req->timeout = msecs_to_jiffies(2 * timeout);
2962	blk_mq_start_request(req);
2963		2984
2964	lrbp = &hba->lrb[tag];	2985	lrbp = &hba->lrb[tag];
2965	WARN_ON(lrbp->cmd);	2986	WARN_ON(lrbp->cmd);
@@ -2977,8 +2998,6 @@ static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, · 11 unmodified lines
2977	(struct utp_upiu_req *)lrbp->ucd_rsp_ptr);	2998	(struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
2978		2999
2979	out:	3000	out:
2980	blk_mq_free_request(req);
2981	out_unlock:
2982	up_read(&hba->clk_scaling_lock);	3001	up_read(&hba->clk_scaling_lock);
2983	return err;	3002	return err;
2984	}	3003	}
@@ -4960,11 +4979,7 @@ static int ufshcd_slave_alloc(struct scsi_device *sdev) · 1975 unmodified lines
4960	*/	4979	*/
4961	static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)	4980	static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4962	{	4981	{
4963	struct ufs_hba *hba = shost_priv(sdev->host);	4982	return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue));
4964
4965	if (depth > hba->nutrs)
4966	depth = hba->nutrs;
4967	return scsi_change_queue_depth(sdev, depth);
4968	}	4983	}
4969		4984
4970	static void ufshcd_hpb_destroy(struct ufs_hba hba, struct scsi_device sdev)	4985	static void ufshcd_hpb_destroy(struct ufs_hba hba, struct scsi_device sdev)
@@ -5256,6 +5271,18 @@ static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) · 285 unmodified lines
5256	return retval;	5271	return retval;
5257	}	5272	}
5258		5273
		5274	/* Release the resources allocated for processing a SCSI command. */
		5275	static void ufshcd_release_scsi_cmd(struct ufs_hba *hba,
		5276	struct ufshcd_lrb *lrbp)
		5277	{
		5278	struct scsi_cmnd *cmd = lrbp->cmd;
		5279
		5280	scsi_dma_unmap(cmd);
		5281	lrbp->cmd = NULL; /* Mark the command as completed. */
		5282	ufshcd_release(hba);
		5283	ufshcd_clk_scaling_update_busy(hba);
		5284	}
		5285
5259	/**	5286	/**
5260	* __ufshcd_transfer_req_compl - handle SCSI and query command completion	5287	* __ufshcd_transfer_req_compl - handle SCSI and query command completion
5261	* @hba: per adapter instance	5288	* @hba: per adapter instance
@@ -5266,9 +5293,7 @@ static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, · 4 unmodified lines
5266	{	5293	{
5267	struct ufshcd_lrb *lrbp;	5294	struct ufshcd_lrb *lrbp;
5268	struct scsi_cmnd *cmd;	5295	struct scsi_cmnd *cmd;
5269	int result;
5270	int index;	5296	int index;
5271	bool update_scaling = false;
5272		5297
5273	for_each_set_bit(index, &completed_reqs, hba->nutrs) {	5298	for_each_set_bit(index, &completed_reqs, hba->nutrs) {
5274	lrbp = &hba->lrb[index];	5299	lrbp = &hba->lrb[index];
@@ -5278,29 +5303,47 @@ static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, · 3 unmodified lines
5278	if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))	5303	if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5279	ufshcd_update_monitor(hba, lrbp);	5304	ufshcd_update_monitor(hba, lrbp);
5280	ufshcd_add_command_trace(hba, index, UFS_CMD_COMP);	5305	ufshcd_add_command_trace(hba, index, UFS_CMD_COMP);
5281	result = ufshcd_transfer_rsp_status(hba, lrbp);	5306	cmd->result = ufshcd_transfer_rsp_status(hba, lrbp);
5282	scsi_dma_unmap(cmd);	5307	ufshcd_release_scsi_cmd(hba, lrbp);
5283	cmd->result = result;
5284	/* Mark completed command as NULL in LRB */
5285	lrbp->cmd = NULL;
5286	/* Do not touch lrbp after scsi done */	5308	/* Do not touch lrbp after scsi done */
5287	scsi_done(cmd);	5309	scsi_done(cmd);
5288	ufshcd_release(hba);
5289	update_scaling = true;
5290	} else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE \|\|	5310	} else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE \|\|
5291	lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {	5311	lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
5292	if (hba->dev_cmd.complete) {	5312	if (hba->dev_cmd.complete) {
5293	ufshcd_add_command_trace(hba, index,	5313	ufshcd_add_command_trace(hba, index,
5294	UFS_DEV_COMP);	5314	UFS_DEV_COMP);
5295	complete(hba->dev_cmd.complete);	5315	complete(hba->dev_cmd.complete);
5296	update_scaling = true;	5316	ufshcd_clk_scaling_update_busy(hba);
5297	}	5317	}
5298	}	5318	}
5299	if (update_scaling)
5300	ufshcd_clk_scaling_update_busy(hba);
5301	}	5319	}
5302	}	5320	}
5303		5321
		5322	/*
		5323	* Returns > 0 if one or more commands have been completed or 0 if no
		5324	* requests have been completed.
		5325	*/
		5326	static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num)
		5327	{
		5328	struct ufs_hba *hba = shost_priv(shost);
		5329	unsigned long completed_reqs, flags;
		5330	u32 tr_doorbell;
		5331
		5332	spin_lock_irqsave(&hba->outstanding_lock, flags);
		5333	tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
		5334	completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
		5335	WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
		5336	"completed: %#lx; outstanding: %#lx\n", completed_reqs,
		5337	hba->outstanding_reqs);
		5338	hba->outstanding_reqs &= ~completed_reqs;
		5339	spin_unlock_irqrestore(&hba->outstanding_lock, flags);
		5340
		5341	if (completed_reqs)
		5342	__ufshcd_transfer_req_compl(hba, completed_reqs);
		5343
		5344	return completed_reqs;
		5345	}
		5346
5304	/**	5347	/**
5305	* ufshcd_transfer_req_compl - handle SCSI and query command completion	5348	* ufshcd_transfer_req_compl - handle SCSI and query command completion
5306	* @hba: per adapter instance	5349	* @hba: per adapter instance
@@ -5311,9 +5354,6 @@ static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, · 4 unmodified lines
5311	*/	5354	*/
5312	static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)	5355	static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
5313	{	5356	{
5314	unsigned long completed_reqs, flags;
5315	u32 tr_doorbell;
5316
5317	/* Resetting interrupt aggregation counters first and reading the	5357	/* Resetting interrupt aggregation counters first and reading the
5318	* DOOR_BELL afterward allows us to handle all the completed requests.	5358	* DOOR_BELL afterward allows us to handle all the completed requests.
5319	* In order to prevent other interrupts starvation the DB is read once	5359	* In order to prevent other interrupts starvation the DB is read once
@@ -5328,21 +5368,13 @@ static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) · 8 unmodified lines
5328	if (ufs_fail_completion())	5368	if (ufs_fail_completion())
5329	return IRQ_HANDLED;	5369	return IRQ_HANDLED;
5330		5370
5331	spin_lock_irqsave(&hba->outstanding_lock, flags);	5371	/*
5332	tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);	5372	* Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we
5333	completed_reqs = ~tr_doorbell & hba->outstanding_reqs;	5373	* do not want polling to trigger spurious interrupt complaints.
5334	WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,	5374	*/
5335	"completed: %#lx; outstanding: %#lx\n", completed_reqs,	5375	ufshcd_poll(hba->host, 0);
5336	hba->outstanding_reqs);
5337	hba->outstanding_reqs &= ~completed_reqs;
5338	spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5339		5376
5340	if (completed_reqs) {	5377	return IRQ_HANDLED;
5341	__ufshcd_transfer_req_compl(hba, completed_reqs);
5342	return IRQ_HANDLED;
5343	} else {
5344	return IRQ_NONE;
5345	}
5346	}	5378	}
5347		5379
5348	int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)	5380	int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
@@ -5986,8 +6018,7 @@ static void ufshcd_err_handling_prepare(struct ufs_hba *hba) · 637 unmodified lines
5986	}	6018	}
5987	ufshcd_scsi_block_requests(hba);	6019	ufshcd_scsi_block_requests(hba);
5988	/* Drain ufshcd_queuecommand() */	6020	/* Drain ufshcd_queuecommand() */
5989	down_write(&hba->clk_scaling_lock);	6021	synchronize_rcu();
5990	up_write(&hba->clk_scaling_lock);
5991	cancel_work_sync(&hba->eeh_work);	6022	cancel_work_sync(&hba->eeh_work);
5992	}	6023	}
5993		6024
@@ -6594,6 +6625,8 @@ static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, · 600 unmodified lines
6594	spin_lock_irqsave(host->host_lock, flags);	6625	spin_lock_irqsave(host->host_lock, flags);
6595		6626
6596	task_tag = req->tag;	6627	task_tag = req->tag;
		6628	WARN_ONCE(task_tag < 0 \|\| task_tag >= hba->nutmrs, "Invalid tag %d\n",
		6629	task_tag);
6597	hba->tmf_rqs[req->tag] = req;	6630	hba->tmf_rqs[req->tag] = req;
6598	treq->upiu_req.req_header.dword_0 \|= cpu_to_be32(task_tag);	6631	treq->upiu_req.req_header.dword_0 \|= cpu_to_be32(task_tag);
6599		6632
@@ -6711,28 +6744,16 @@ static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, · 111 unmodified lines
6711	enum dev_cmd_type cmd_type,	6744	enum dev_cmd_type cmd_type,
6712	enum query_opcode desc_op)	6745	enum query_opcode desc_op)
6713	{	6746	{
6714	struct request_queue *q = hba->cmd_queue;
6715	DECLARE_COMPLETION_ONSTACK(wait);	6747	DECLARE_COMPLETION_ONSTACK(wait);
6716	struct request *req;	6748	const u32 tag = hba->reserved_slot;
6717	struct ufshcd_lrb *lrbp;	6749	struct ufshcd_lrb *lrbp;
6718	int err = 0;	6750	int err = 0;
6719	int tag;
6720	u8 upiu_flags;	6751	u8 upiu_flags;
6721		6752
6722	down_read(&hba->clk_scaling_lock);	6753	/* Protects use of hba->reserved_slot. */
6723		6754	lockdep_assert_held(&hba->dev_cmd.lock);
6724	req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0);
6725	if (IS_ERR(req)) {
6726	err = PTR_ERR(req);
6727	goto out_unlock;
6728	}
6729	tag = req->tag;
6730	WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
6731		6755
6732	if (unlikely(test_bit(tag, &hba->outstanding_reqs))) {	6756	down_read(&hba->clk_scaling_lock);
6733	err = -EBUSY;
6734	goto out;
6735	}
6736		6757
6737	lrbp = &hba->lrb[tag];	6758	lrbp = &hba->lrb[tag];
6738	WARN_ON(lrbp->cmd);	6759	WARN_ON(lrbp->cmd);
@@ -6801,9 +6822,6 @@ static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, · 62 unmodified lines
6801	ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,	6822	ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
6802	(struct utp_upiu_req *)lrbp->ucd_rsp_ptr);	6823	(struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
6803		6824
6804	out:
6805	blk_mq_free_request(req);
6806	out_unlock:
6807	up_read(&hba->clk_scaling_lock);	6825	up_read(&hba->clk_scaling_lock);
6808	return err;	6826	return err;
6809	}	6827	}
@@ -7033,6 +7051,7 @@ static int ufshcd_abort(struct scsi_cmnd *cmd) · 223 unmodified lines
7033	struct ufshcd_lrb *lrbp = &hba->lrb[tag];	7051	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7034	unsigned long flags;	7052	unsigned long flags;
7035	int err = FAILED;	7053	int err = FAILED;
		7054	bool outstanding;
7036	u32 reg;	7055	u32 reg;
7037		7056
7038	WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);	7057	WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
@@ -7110,7 +7129,17 @@ static int ufshcd_abort(struct scsi_cmnd *cmd) · 71 unmodified lines
7110	goto release;	7129	goto release;
7111	}	7130	}
7112		7131
7113	lrbp->cmd = NULL;	7132	/*
		7133	* Clear the corresponding bit from outstanding_reqs since the command
		7134	* has been aborted successfully.
		7135	*/
		7136	spin_lock_irqsave(&hba->outstanding_lock, flags);
		7137	outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs);
		7138	spin_unlock_irqrestore(&hba->outstanding_lock, flags);
		7139
		7140	if (outstanding)
		7141	ufshcd_release_scsi_cmd(hba, lrbp);
		7142
7114	err = SUCCESS;	7143	err = SUCCESS;
7115		7144
7116	release:	7145	release:
@@ -7412,7 +7441,7 @@ static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) · 295 unmodified lines
7412	static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)	7441	static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7413	{	7442	{
7414	int ret = 0;	7443	int ret = 0;
7415	struct scsi_device *sdev_boot;	7444	struct scsi_device sdev_boot, sdev_rpmb;
7416		7445
7417	hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,	7446	hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
7418	ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);	7447	ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
@@ -7423,14 +7452,14 @@ static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) · 4 unmodified lines
7423	}	7452	}
7424	scsi_device_put(hba->sdev_ufs_device);	7453	scsi_device_put(hba->sdev_ufs_device);
7425		7454
7426	hba->sdev_rpmb = __scsi_add_device(hba->host, 0, 0,	7455	sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
7427	ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);	7456	ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7428	if (IS_ERR(hba->sdev_rpmb)) {	7457	if (IS_ERR(sdev_rpmb)) {
7429	ret = PTR_ERR(hba->sdev_rpmb);	7458	ret = PTR_ERR(sdev_rpmb);
7430	goto remove_sdev_ufs_device;	7459	goto remove_sdev_ufs_device;
7431	}	7460	}
7432	ufshcd_blk_pm_runtime_init(hba->sdev_rpmb);	7461	ufshcd_blk_pm_runtime_init(sdev_rpmb);
7433	scsi_device_put(hba->sdev_rpmb);	7462	scsi_device_put(sdev_rpmb);
7434		7463
7435	sdev_boot = __scsi_add_device(hba->host, 0, 0,	7464	sdev_boot = __scsi_add_device(hba->host, 0, 0,
7436	ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);	7465	ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
@@ -8156,7 +8185,9 @@ static struct scsi_host_template ufshcd_driver_template = { · 719 unmodified lines
8156	.module = THIS_MODULE,	8185	.module = THIS_MODULE,
8157	.name = UFSHCD,	8186	.name = UFSHCD,
8158	.proc_name = UFSHCD,	8187	.proc_name = UFSHCD,
		8188	.map_queues = ufshcd_map_queues,
8159	.queuecommand = ufshcd_queuecommand,	8189	.queuecommand = ufshcd_queuecommand,
		8190	.mq_poll = ufshcd_poll,
8160	.slave_alloc = ufshcd_slave_alloc,	8191	.slave_alloc = ufshcd_slave_alloc,
8161	.slave_configure = ufshcd_slave_configure,	8192	.slave_configure = ufshcd_slave_configure,
8162	.slave_destroy = ufshcd_slave_destroy,	8193	.slave_destroy = ufshcd_slave_destroy,
@@ -9384,7 +9415,6 @@ void ufshcd_remove(struct ufs_hba *hba) · 1221 unmodified lines
9384	ufs_sysfs_remove_nodes(hba->dev);	9415	ufs_sysfs_remove_nodes(hba->dev);
9385	blk_cleanup_queue(hba->tmf_queue);	9416	blk_cleanup_queue(hba->tmf_queue);
9386	blk_mq_free_tag_set(&hba->tmf_tag_set);	9417	blk_mq_free_tag_set(&hba->tmf_tag_set);
9387	blk_cleanup_queue(hba->cmd_queue);
9388	scsi_remove_host(hba->host);	9418	scsi_remove_host(hba->host);
9389	/* disable interrupts */	9419	/* disable interrupts */
9390	ufshcd_disable_intr(hba, hba->intr_mask);	9420	ufshcd_disable_intr(hba, hba->intr_mask);
@@ -9445,6 +9475,7 @@ int ufshcd_alloc_host(struct device dev, struct ufs_hba *hba_handle) · 54 unmodified lines
9445	err = -ENOMEM;	9475	err = -ENOMEM;
9446	goto out_error;	9476	goto out_error;
9447	}	9477	}
		9478	host->nr_maps = HCTX_TYPE_POLL + 1;
9448	hba = shost_priv(host);	9479	hba = shost_priv(host);
9449	hba->host = host;	9480	hba->host = host;
9450	hba->dev = dev;	9481	hba->dev = dev;
@@ -9486,6 +9517,13 @@ int ufshcd_init(struct ufs_hba hba, void __iomem mmio_base, unsigned int irq) · 35 unmodified lines
9486	struct device *dev = hba->dev;	9517	struct device *dev = hba->dev;
9487	char eh_wq_name[sizeof("ufs_eh_wq_00")];	9518	char eh_wq_name[sizeof("ufs_eh_wq_00")];
9488		9519
		9520	/*
		9521	* dev_set_drvdata() must be called before any callbacks are registered
		9522	* that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon,
		9523	* sysfs).
		9524	*/
		9525	dev_set_drvdata(dev, hba);
		9526
9489	if (!mmio_base) {	9527	if (!mmio_base) {
9490	dev_err(hba->dev,	9528	dev_err(hba->dev,
9491	"Invalid memory reference for mmio_base is NULL\n");	9529	"Invalid memory reference for mmio_base is NULL\n");
@@ -9528,8 +9566,8 @@ int ufshcd_init(struct ufs_hba hba, void __iomem mmio_base, unsigned int irq) · 36 unmodified lines
9528	/* Configure LRB */	9566	/* Configure LRB */
9529	ufshcd_host_memory_configure(hba);	9567	ufshcd_host_memory_configure(hba);
9530		9568
9531	host->can_queue = hba->nutrs;	9569	host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
9532	host->cmd_per_lun = hba->nutrs;	9570	host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED;
9533	host->max_id = UFSHCD_MAX_ID;	9571	host->max_id = UFSHCD_MAX_ID;
9534	host->max_lun = UFS_MAX_LUNS;	9572	host->max_lun = UFS_MAX_LUNS;
9535	host->max_channel = UFSHCD_MAX_CHANNEL;	9573	host->max_channel = UFSHCD_MAX_CHANNEL;
@@ -9597,12 +9635,6 @@ int ufshcd_init(struct ufs_hba hba, void __iomem mmio_base, unsigned int irq) · 61 unmodified lines
9597	goto out_disable;	9635	goto out_disable;
9598	}	9636	}
9599		9637
9600	hba->cmd_queue = blk_mq_init_queue(&hba->host->tag_set);
9601	if (IS_ERR(hba->cmd_queue)) {
9602	err = PTR_ERR(hba->cmd_queue);
9603	goto out_remove_scsi_host;
9604	}
9605
9606	hba->tmf_tag_set = (struct blk_mq_tag_set) {	9638	hba->tmf_tag_set = (struct blk_mq_tag_set) {
9607	.nr_hw_queues = 1,	9639	.nr_hw_queues = 1,
9608	.queue_depth = hba->nutmrs,	9640	.queue_depth = hba->nutmrs,
@@ -9611,7 +9643,7 @@ int ufshcd_init(struct ufs_hba hba, void __iomem mmio_base, unsigned int irq) · 2 unmodified lines
9611	};	9643	};
9612	err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);	9644	err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
9613	if (err < 0)	9645	if (err < 0)
9614	goto free_cmd_queue;	9646	goto out_remove_scsi_host;
9615	hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);	9647	hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
9616	if (IS_ERR(hba->tmf_queue)) {	9648	if (IS_ERR(hba->tmf_queue)) {
9617	err = PTR_ERR(hba->tmf_queue);	9649	err = PTR_ERR(hba->tmf_queue);
@@ -9680,8 +9712,6 @@ free_tmf_queue: · 62 unmodified lines
9680	blk_cleanup_queue(hba->tmf_queue);	9712	blk_cleanup_queue(hba->tmf_queue);
9681	free_tmf_tag_set:	9713	free_tmf_tag_set:
9682	blk_mq_free_tag_set(&hba->tmf_tag_set);	9714	blk_mq_free_tag_set(&hba->tmf_tag_set);
9683	free_cmd_queue:
9684	blk_cleanup_queue(hba->cmd_queue);
9685	out_remove_scsi_host:	9715	out_remove_scsi_host:
9686	scsi_remove_host(hba->host);	9716	scsi_remove_host(hba->host);
9687	out_disable:	9717	out_disable:
@@ -9703,7 +9733,27 @@ void ufshcd_resume_complete(struct device *dev) · 15 unmodified lines
9703	}	9733	}
9704	EXPORT_SYMBOL_GPL(ufshcd_resume_complete);	9734	EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
9705		9735
9706	int ufshcd_suspend_prepare(struct device *dev)	9736	static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba)
		9737	{
		9738	struct device *dev = &hba->sdev_ufs_device->sdev_gendev;
		9739	enum ufs_dev_pwr_mode dev_pwr_mode;
		9740	enum uic_link_state link_state;
		9741	unsigned long flags;
		9742	bool res;
		9743
		9744	spin_lock_irqsave(&dev->power.lock, flags);
		9745	dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl);
		9746	link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl);
		9747	res = pm_runtime_suspended(dev) &&
		9748	hba->curr_dev_pwr_mode == dev_pwr_mode &&
		9749	hba->uic_link_state == link_state &&
		9750	!hba->dev_info.b_rpm_dev_flush_capable;
		9751	spin_unlock_irqrestore(&dev->power.lock, flags);
		9752
		9753	return res;
		9754	}
		9755
		9756	int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm)
9707	{	9757	{
9708	struct ufs_hba *hba = dev_get_drvdata(dev);	9758	struct ufs_hba *hba = dev_get_drvdata(dev);
9709	int ret;	9759	int ret;
@@ -9715,15 +9765,30 @@ int ufshcd_suspend_prepare(struct device *dev) · 5 unmodified lines
9715	* Refer ufshcd_resume_complete()	9765	* Refer ufshcd_resume_complete()
9716	*/	9766	*/
9717	if (hba->sdev_ufs_device) {	9767	if (hba->sdev_ufs_device) {
9718	ret = ufshcd_rpm_get_sync(hba);	9768	/* Prevent runtime suspend */
9719	if (ret < 0 && ret != -EACCES) {	9769	ufshcd_rpm_get_noresume(hba);
9720	ufshcd_rpm_put(hba);	9770	/*
9721	return ret;	9771	* Check if already runtime suspended in same state as system
		9772	* suspend would be.
		9773	*/
		9774	if (!rpm_ok_for_spm \|\| !ufshcd_rpm_ok_for_spm(hba)) {
		9775	/* RPM state is not ok for SPM, so runtime resume */
		9776	ret = ufshcd_rpm_resume(hba);
		9777	if (ret < 0 && ret != -EACCES) {
		9778	ufshcd_rpm_put(hba);
		9779	return ret;
		9780	}
9722	}	9781	}
9723	hba->complete_put = true;	9782	hba->complete_put = true;
9724	}	9783	}
9725	return 0;	9784	return 0;
9726	}	9785	}
		9786	EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare);
		9787
		9788	int ufshcd_suspend_prepare(struct device *dev)
		9789	{
		9790	return __ufshcd_suspend_prepare(dev, true);
		9791	}
9727	EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);	9792	EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
9728		9793
9729	#ifdef CONFIG_PM_SLEEP	9794	#ifdef CONFIG_PM_SLEEP

drivers/scsi/ufs/ufshcd.h+16−4

 					enum ufs_notify_change_status status,
 					struct ufs_pa_layer_attr *,
 					struct ufs_pa_layer_attr *);
-	void	(*setup_xfer_req)(struct ufs_hba *, int, bool);
+	void	(*setup_xfer_req)(struct ufs_hba *hba, int tag,
+				  bool is_scsi_cmd);
 	void	(*setup_task_mgmt)(struct ufs_hba *, int, u8);
 	void    (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
 					enum ufs_notify_change_status);
  * @host: Scsi_Host instance of the driver
  * @dev: device handle
  * @lrb: local reference block
- * @cmd_queue: Used to allocate command tags from hba->host->tag_set.
  * @outstanding_tasks: Bits representing outstanding task requests
  * @outstanding_lock: Protects @outstanding_reqs.
  * @outstanding_reqs: Bits representing outstanding transfer requests
  * @capabilities: UFS Controller Capabilities
  * @nutrs: Transfer Request Queue depth supported by controller
  * @nutmrs: Task Management Queue depth supported by controller
+ * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock.
  * @ufs_version: UFS Version to which controller complies
  * @vops: pointer to variant specific operations
  * @priv: pointer to variant specific private data
  * @clk_list_head: UFS host controller clocks list node head
  * @pwr_info: holds current power mode
  * @max_pwr_info: keeps the device max valid pwm
+ * @clk_scaling_lock: used to serialize device commands and clock scaling
  * @desc_size: descriptor sizes reported by device
  * @urgent_bkops_lvl: keeps track of urgent bkops level for device
  * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
 	struct Scsi_Host *host;
 	struct device *dev;
-	struct request_queue *cmd_queue;
 	/*
 	 * This field is to keep a reference to "scsi_device" corresponding to
 	 * "UFS device" W-LU.
 	 */
 	struct scsi_device *sdev_ufs_device;
-	struct scsi_device *sdev_rpmb;
 #ifdef CONFIG_SCSI_UFS_HWMON
 	struct device *hwmon_device;
 	u32 capabilities;
 	int nutrs;
 	int nutmrs;
+	u32 reserved_slot;
 	u32 ufs_version;
 	const struct ufs_hba_variant_ops *vops;
 	struct ufs_hba_variant_params *vps;
 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable);
 int ufshcd_suspend_prepare(struct device *dev);
+int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm);
 void ufshcd_resume_complete(struct device *dev);
 /* Wrapper functions for safely calling variant operations */
 	return pm_runtime_put_sync(&hba->sdev_ufs_device->sdev_gendev);
 }
+static inline void ufshcd_rpm_get_noresume(struct ufs_hba *hba)
+{
+	pm_runtime_get_noresume(&hba->sdev_ufs_device->sdev_gendev);
+}
+static inline int ufshcd_rpm_resume(struct ufs_hba *hba)
+{
+	return pm_runtime_resume(&hba->sdev_ufs_device->sdev_gendev);
+}
 static inline int ufshcd_rpm_put(struct ufs_hba *hba)
 {
 	return pm_runtime_put(&hba->sdev_ufs_device->sdev_gendev);

drivers/scsi/ufs/ufshpb.c+0−1

@@ -10,7 +10,6 @@ · 9 unmodified lines
10	*/	10	*/
11		11
12	#include <asm/unaligned.h>	12	#include <asm/unaligned.h>
13	#include <linux/async.h>
14		13
15	#include "ufshcd.h"	14	#include "ufshcd.h"
16	#include "ufshpb.h"	15	#include "ufshpb.h"

include/linux/blk-pm.h+1−1

@@ -14,7 +14,7 @@ extern void blk_pm_runtime_init(struct request_queue q, struct device dev); · 13 unmodified lines
14	extern int blk_pre_runtime_suspend(struct request_queue *q);	14	extern int blk_pre_runtime_suspend(struct request_queue *q);
15	extern void blk_post_runtime_suspend(struct request_queue *q, int err);	15	extern void blk_post_runtime_suspend(struct request_queue *q, int err);
16	extern void blk_pre_runtime_resume(struct request_queue *q);	16	extern void blk_pre_runtime_resume(struct request_queue *q);
17	extern void blk_post_runtime_resume(struct request_queue *q, int err);	17	extern void blk_post_runtime_resume(struct request_queue *q);
18	extern void blk_set_runtime_active(struct request_queue *q);	18	extern void blk_set_runtime_active(struct request_queue *q);
19	#else	19	#else
20	static inline void blk_pm_runtime_init(struct request_queue *q,	20	static inline void blk_pm_runtime_init(struct request_queue *q,

include/scsi/libsas.h+2−0

 	SAS_HA_DRAINING,
 	SAS_HA_ATA_EH_ACTIVE,
 	SAS_HA_FROZEN,
+	SAS_HA_RESUMING,
 };
 struct sas_ha_struct {
 extern int sas_unregister_ha(struct sas_ha_struct *);
 extern void sas_prep_resume_ha(struct sas_ha_struct *sas_ha);
 extern void sas_resume_ha(struct sas_ha_struct *sas_ha);
+extern void sas_resume_ha_no_sync(struct sas_ha_struct *sas_ha);
 extern void sas_suspend_ha(struct sas_ha_struct *sas_ha);
 int sas_set_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates);

include/scsi/scsi_host.h+0−6

 	/* ldm bits */
 	struct device		shost_gendev, shost_dev;
-	/*
-	 * The array size 3 provides space for one attribute group defined by
-	 * the SCSI core, one attribute group defined by the SCSI LLD and one
-	 * terminating NULL pointer.
-	 */
-	const struct attribute_group *shost_dev_attr_groups[3];
 	/*
 	 * Points to the transport data (if any) which is allocated