lael-labs/linux

Documentation/ABI/testing/sysfs-bus-pci+4−7

 Contact:	Neil Horman <nhorman@tuxdriver.com>
 Description:
 		The /sys/devices/.../msi_irqs directory contains a variable set
-		of sub-directories, with each sub-directory being named after a
+		of files, with each file being named after a corresponding msi
-		corresponding msi irq vector allocated to that device.  Each
+		irq vector allocated to that device.
-		numbered sub-directory N contains attributes of that irq.
-		Note that this directory is not created for device drivers which
-		do not support msi irqs
-What:		/sys/bus/pci/devices/.../msi_irqs/<N>/mode
+What:		/sys/bus/pci/devices/.../msi_irqs/<N>
 Date:		September 2011
 Contact:	Neil Horman <nhorman@tuxdriver.com>
 Description:
 		This attribute indicates the mode that the irq vector named by
-		the parent directory is in (msi vs. msix)
+		the file is in (msi vs. msix)
 What:		/sys/bus/pci/devices/.../remove
 Date:		January 2009

Documentation/PCI/00-INDEX+2−2

 	- this file
 MSI-HOWTO.txt
 	- the Message Signaled Interrupts (MSI) Driver Guide HOWTO and FAQ.
-PCI-DMA-mapping.txt
-	- info for PCI drivers using DMA portably across all platforms
 PCIEBUS-HOWTO.txt
 	- a guide describing the PCI Express Port Bus driver
 pci-error-recovery.txt
 	- info on PCI error recovery
+pci-iov-howto.txt
+	- the PCI Express I/O Virtualization HOWTO
 pci.txt
 	- info on the PCI subsystem for device driver authors
 pcieaer-howto.txt

Documentation/PCI/MSI-HOWTO.txt+210−98

@@ -82,93 +82,111 @@ Most of the hard work is done for the driver in the PCI layer. It simply · 81 unmodified lines
82	has to request that the PCI layer set up the MSI capability for this	82	has to request that the PCI layer set up the MSI capability for this
83	device.	83	device.
84		84
85	4.2.1 pci_enable_msi	85	4.2.1 pci_enable_msi_range
86		86
87	int pci_enable_msi(struct pci_dev *dev)	87	int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
88		88
89	A successful call allocates ONE interrupt to the device, regardless	89	This function allows a device driver to request any number of MSI
90	of how many MSIs the device supports. The device is switched from	90	interrupts within specified range from 'minvec' to 'maxvec'.
91	pin-based interrupt mode to MSI mode. The dev->irq number is changed
92	to a new number which represents the message signaled interrupt;
93	consequently, this function should be called before the driver calls
94	request_irq(), because an MSI is delivered via a vector that is
95	different from the vector of a pin-based interrupt.
96		91
97	4.2.2 pci_enable_msi_block	92	If this function returns a positive number it indicates the number of
		93	MSI interrupts that have been successfully allocated. In this case
		94	the device is switched from pin-based interrupt mode to MSI mode and
		95	updates dev->irq to be the lowest of the new interrupts assigned to it.
		96	The other interrupts assigned to the device are in the range dev->irq
		97	to dev->irq + returned value - 1. Device driver can use the returned
		98	number of successfully allocated MSI interrupts to further allocate
		99	and initialize device resources.
98		100
99	int pci_enable_msi_block(struct pci_dev *dev, int count)	101	If this function returns a negative number, it indicates an error and
		102	the driver should not attempt to request any more MSI interrupts for
		103	this device.
100		104
101	This variation on the above call allows a device driver to request multiple	105	This function should be called before the driver calls request_irq(),
102	MSIs. The MSI specification only allows interrupts to be allocated in	106	because MSI interrupts are delivered via vectors that are different
103	powers of two, up to a maximum of 2^5 (32).	107	from the vector of a pin-based interrupt.
104		108
105	If this function returns 0, it has succeeded in allocating at least as many	109	It is ideal if drivers can cope with a variable number of MSI interrupts;
106	interrupts as the driver requested (it may have allocated more in order	110	there are many reasons why the platform may not be able to provide the
107	to satisfy the power-of-two requirement). In this case, the function	111	exact number that a driver asks for.
108	enables MSI on this device and updates dev->irq to be the lowest of
109	the new interrupts assigned to it. The other interrupts assigned to
110	the device are in the range dev->irq to dev->irq + count - 1.
111		112
112	If this function returns a negative number, it indicates an error and	113	There could be devices that can not operate with just any number of MSI
113	the driver should not attempt to request any more MSI interrupts for	114	interrupts within a range. See chapter 4.3.1.3 to get the idea how to
114	this device. If this function returns a positive number, it is	115	handle such devices for MSI-X - the same logic applies to MSI.
115	less than 'count' and indicates the number of interrupts that could have
116	been allocated. In neither case is the irq value updated or the device
117	switched into MSI mode.
118
119	The device driver must decide what action to take if
120	pci_enable_msi_block() returns a value less than the number requested.
121	For instance, the driver could still make use of fewer interrupts;
122	in this case the driver should call pci_enable_msi_block()
123	again. Note that it is not guaranteed to succeed, even when the
124	'count' has been reduced to the value returned from a previous call to
125	pci_enable_msi_block(). This is because there are multiple constraints
126	on the number of vectors that can be allocated; pci_enable_msi_block()
127	returns as soon as it finds any constraint that doesn't allow the
128	call to succeed.
129
130	4.2.3 pci_enable_msi_block_auto
131
132	int pci_enable_msi_block_auto(struct pci_dev dev, unsigned int count)
133
134	This variation on pci_enable_msi() call allows a device driver to request
135	the maximum possible number of MSIs. The MSI specification only allows
136	interrupts to be allocated in powers of two, up to a maximum of 2^5 (32).
137
138	If this function returns a positive number, it indicates that it has
139	succeeded and the returned value is the number of allocated interrupts. In
140	this case, the function enables MSI on this device and updates dev->irq to
141	be the lowest of the new interrupts assigned to it. The other interrupts
142	assigned to the device are in the range dev->irq to dev->irq + returned
143	value - 1.
144		116
145	If this function returns a negative number, it indicates an error and	117	4.2.1.1 Maximum possible number of MSI interrupts
146	the driver should not attempt to request any more MSI interrupts for	118
147	this device.	119	The typical usage of MSI interrupts is to allocate as many vectors as
		120	possible, likely up to the limit returned by pci_msi_vec_count() function:
		121
		122	static int foo_driver_enable_msi(struct pci_dev *pdev, int nvec)
		123	{
		124	return pci_enable_msi_range(pdev, 1, nvec);
		125	}
		126
		127	Note the value of 'minvec' parameter is 1. As 'minvec' is inclusive,
		128	the value of 0 would be meaningless and could result in error.
148		129
149	If the device driver needs to know the number of interrupts the device	130	Some devices have a minimal limit on number of MSI interrupts.
150	supports it can pass the pointer count where that number is stored. The	131	In this case the function could look like this:
151	device driver must decide what action to take if pci_enable_msi_block_auto()
152	succeeds, but returns a value less than the number of interrupts supported.
153	If the device driver does not need to know the number of interrupts
154	supported, it can set the pointer count to NULL.
155		132
156	4.2.4 pci_disable_msi	133	static int foo_driver_enable_msi(struct pci_dev *pdev, int nvec)
		134	{
		135	return pci_enable_msi_range(pdev, FOO_DRIVER_MINIMUM_NVEC, nvec);
		136	}
		137
		138	4.2.1.2 Exact number of MSI interrupts
		139
		140	If a driver is unable or unwilling to deal with a variable number of MSI
		141	interrupts it could request a particular number of interrupts by passing
		142	that number to pci_enable_msi_range() function as both 'minvec' and 'maxvec'
		143	parameters:
		144
		145	static int foo_driver_enable_msi(struct pci_dev *pdev, int nvec)
		146	{
		147	return pci_enable_msi_range(pdev, nvec, nvec);
		148	}
		149
		150	4.2.1.3 Single MSI mode
		151
		152	The most notorious example of the request type described above is
		153	enabling the single MSI mode for a device. It could be done by passing
		154	two 1s as 'minvec' and 'maxvec':
		155
		156	static int foo_driver_enable_single_msi(struct pci_dev *pdev)
		157	{
		158	return pci_enable_msi_range(pdev, 1, 1);
		159	}
		160
		161	4.2.2 pci_disable_msi
157		162
158	void pci_disable_msi(struct pci_dev *dev)	163	void pci_disable_msi(struct pci_dev *dev)
159		164
160	This function should be used to undo the effect of pci_enable_msi() or	165	This function should be used to undo the effect of pci_enable_msi_range().
161	pci_enable_msi_block() or pci_enable_msi_block_auto(). Calling it restores	166	Calling it restores dev->irq to the pin-based interrupt number and frees
162	dev->irq to the pin-based interrupt number and frees the previously	167	the previously allocated MSIs. The interrupts may subsequently be assigned
163	allocated message signaled interrupt(s). The interrupt may subsequently be	168	to another device, so drivers should not cache the value of dev->irq.
164	assigned to another device, so drivers should not cache the value of
165	dev->irq.
166		169
167	Before calling this function, a device driver must always call free_irq()	170	Before calling this function, a device driver must always call free_irq()
168	on any interrupt for which it previously called request_irq().	171	on any interrupt for which it previously called request_irq().
169	Failure to do so results in a BUG_ON(), leaving the device with	172	Failure to do so results in a BUG_ON(), leaving the device with
170	MSI enabled and thus leaking its vector.	173	MSI enabled and thus leaking its vector.
171		174
		175	4.2.3 pci_msi_vec_count
		176
		177	int pci_msi_vec_count(struct pci_dev *dev)
		178
		179	This function could be used to retrieve the number of MSI vectors the
		180	device requested (via the Multiple Message Capable register). The MSI
		181	specification only allows the returned value to be a power of two,
		182	up to a maximum of 2^5 (32).
		183
		184	If this function returns a negative number, it indicates the device is
		185	not capable of sending MSIs.
		186
		187	If this function returns a positive number, it indicates the maximum
		188	number of MSI interrupt vectors that could be allocated.
		189
172	4.3 Using MSI-X	190	4.3 Using MSI-X
173		191
174	The MSI-X capability is much more flexible than the MSI capability.	192	The MSI-X capability is much more flexible than the MSI capability.
@@ -188,26 +206,31 @@ in each element of the array to indicate for which entries the kernel · 13 unmodified lines
188	should assign interrupts; it is invalid to fill in two entries with the	206	should assign interrupts; it is invalid to fill in two entries with the
189	same number.	207	same number.
190		208
191	4.3.1 pci_enable_msix	209	4.3.1 pci_enable_msix_range
192		210
193	int pci_enable_msix(struct pci_dev dev, struct msix_entry entries, int nvec)	211	int pci_enable_msix_range(struct pci_dev dev, struct msix_entry entries,
		212	int minvec, int maxvec)
194		213
195	Calling this function asks the PCI subsystem to allocate 'nvec' MSIs.	214	Calling this function asks the PCI subsystem to allocate any number of
		215	MSI-X interrupts within specified range from 'minvec' to 'maxvec'.
196	The 'entries' argument is a pointer to an array of msix_entry structs	216	The 'entries' argument is a pointer to an array of msix_entry structs
197	which should be at least 'nvec' entries in size. On success, the	217	which should be at least 'maxvec' entries in size.
198	device is switched into MSI-X mode and the function returns 0.	218
199	The 'vector' member in each entry is populated with the interrupt number;	219	On success, the device is switched into MSI-X mode and the function
		220	returns the number of MSI-X interrupts that have been successfully
		221	allocated. In this case the 'vector' member in entries numbered from
		222	0 to the returned value - 1 is populated with the interrupt number;
200	the driver should then call request_irq() for each 'vector' that it	223	the driver should then call request_irq() for each 'vector' that it
201	decides to use. The device driver is responsible for keeping track of the	224	decides to use. The device driver is responsible for keeping track of the
202	interrupts assigned to the MSI-X vectors so it can free them again later.	225	interrupts assigned to the MSI-X vectors so it can free them again later.
		226	Device driver can use the returned number of successfully allocated MSI-X
		227	interrupts to further allocate and initialize device resources.
203		228
204	If this function returns a negative number, it indicates an error and	229	If this function returns a negative number, it indicates an error and
205	the driver should not attempt to allocate any more MSI-X interrupts for	230	the driver should not attempt to allocate any more MSI-X interrupts for
206	this device. If it returns a positive number, it indicates the maximum	231	this device.
207	number of interrupt vectors that could have been allocated. See example
208	below.
209		232
210	This function, in contrast with pci_enable_msi(), does not adjust	233	This function, in contrast with pci_enable_msi_range(), does not adjust
211	dev->irq. The device will not generate interrupts for this interrupt	234	dev->irq. The device will not generate interrupts for this interrupt
212	number once MSI-X is enabled.	235	number once MSI-X is enabled.
213		236
@@ -218,28 +241,103 @@ It is ideal if drivers can cope with a variable number of MSI-X interrupts; · 4 unmodified lines
218	there are many reasons why the platform may not be able to provide the	241	there are many reasons why the platform may not be able to provide the
219	exact number that a driver asks for.	242	exact number that a driver asks for.
220		243
221	A request loop to achieve that might look like:	244	There could be devices that can not operate with just any number of MSI-X
		245	interrupts within a range. E.g., an network adapter might need let's say
		246	four vectors per each queue it provides. Therefore, a number of MSI-X
		247	interrupts allocated should be a multiple of four. In this case interface
		248	pci_enable_msix_range() can not be used alone to request MSI-X interrupts
		249	(since it can allocate any number within the range, without any notion of
		250	the multiple of four) and the device driver should master a custom logic
		251	to request the required number of MSI-X interrupts.
		252
		253	4.3.1.1 Maximum possible number of MSI-X interrupts
		254
		255	The typical usage of MSI-X interrupts is to allocate as many vectors as
		256	possible, likely up to the limit returned by pci_msix_vec_count() function:
222		257
223	static int foo_driver_enable_msix(struct foo_adapter *adapter, int nvec)	258	static int foo_driver_enable_msix(struct foo_adapter *adapter, int nvec)
224	{	259	{
225	while (nvec >= FOO_DRIVER_MINIMUM_NVEC) {	260	return pci_enable_msi_range(adapter->pdev, adapter->msix_entries,
226	rc = pci_enable_msix(adapter->pdev,	261	1, nvec);
227	adapter->msix_entries, nvec);	262	}
228	if (rc > 0)	263
229	nvec = rc;	264	Note the value of 'minvec' parameter is 1. As 'minvec' is inclusive,
230	else	265	the value of 0 would be meaningless and could result in error.
231	return rc;	266
		267	Some devices have a minimal limit on number of MSI-X interrupts.
		268	In this case the function could look like this:
		269
		270	static int foo_driver_enable_msix(struct foo_adapter *adapter, int nvec)
		271	{
		272	return pci_enable_msi_range(adapter->pdev, adapter->msix_entries,
		273	FOO_DRIVER_MINIMUM_NVEC, nvec);
		274	}
		275
		276	4.3.1.2 Exact number of MSI-X interrupts
		277
		278	If a driver is unable or unwilling to deal with a variable number of MSI-X
		279	interrupts it could request a particular number of interrupts by passing
		280	that number to pci_enable_msix_range() function as both 'minvec' and 'maxvec'
		281	parameters:
		282
		283	static int foo_driver_enable_msix(struct foo_adapter *adapter, int nvec)
		284	{
		285	return pci_enable_msi_range(adapter->pdev, adapter->msix_entries,
		286	nvec, nvec);
		287	}
		288
		289	4.3.1.3 Specific requirements to the number of MSI-X interrupts
		290
		291	As noted above, there could be devices that can not operate with just any
		292	number of MSI-X interrupts within a range. E.g., let's assume a device that
		293	is only capable sending the number of MSI-X interrupts which is a power of
		294	two. A routine that enables MSI-X mode for such device might look like this:
		295
		296	/*
		297	* Assume 'minvec' and 'maxvec' are non-zero
		298	*/
		299	static int foo_driver_enable_msix(struct foo_adapter *adapter,
		300	int minvec, int maxvec)
		301	{
		302	int rc;
		303
		304	minvec = roundup_pow_of_two(minvec);
		305	maxvec = rounddown_pow_of_two(maxvec);
		306
		307	if (minvec > maxvec)
		308	return -ERANGE;
		309
		310	retry:
		311	rc = pci_enable_msix_range(adapter->pdev, adapter->msix_entries,
		312	maxvec, maxvec);
		313	/*
		314	* -ENOSPC is the only error code allowed to be analized
		315	*/
		316	if (rc == -ENOSPC) {
		317	if (maxvec == 1)
		318	return -ENOSPC;
		319
		320	maxvec /= 2;
		321
		322	if (minvec > maxvec)
		323	return -ENOSPC;
		324
		325	goto retry;
232	}	326	}
233		327
234	return -ENOSPC;	328	return rc;
235	}	329	}
236		330
		331	Note how pci_enable_msix_range() return value is analized for a fallback -
		332	any error code other than -ENOSPC indicates a fatal error and should not
		333	be retried.
		334
237	4.3.2 pci_disable_msix	335	4.3.2 pci_disable_msix
238		336
239	void pci_disable_msix(struct pci_dev *dev)	337	void pci_disable_msix(struct pci_dev *dev)
240		338
241	This function should be used to undo the effect of pci_enable_msix(). It frees	339	This function should be used to undo the effect of pci_enable_msix_range().
242	the previously allocated message signaled interrupts. The interrupts may	340	It frees the previously allocated MSI-X interrupts. The interrupts may
243	subsequently be assigned to another device, so drivers should not cache	341	subsequently be assigned to another device, so drivers should not cache
244	the value of the 'vector' elements over a call to pci_disable_msix().	342	the value of the 'vector' elements over a call to pci_disable_msix().
245		343
@@ -255,18 +353,32 @@ MSI-X Table. This address is mapped by the PCI subsystem, and should not · 9 unmodified lines
255	be accessed directly by the device driver. If the driver wishes to	353	be accessed directly by the device driver. If the driver wishes to
256	mask or unmask an interrupt, it should call disable_irq() / enable_irq().	354	mask or unmask an interrupt, it should call disable_irq() / enable_irq().
257		355
		356	4.3.4 pci_msix_vec_count
		357
		358	int pci_msix_vec_count(struct pci_dev *dev)
		359
		360	This function could be used to retrieve number of entries in the device
		361	MSI-X table.
		362
		363	If this function returns a negative number, it indicates the device is
		364	not capable of sending MSI-Xs.
		365
		366	If this function returns a positive number, it indicates the maximum
		367	number of MSI-X interrupt vectors that could be allocated.
		368
258	4.4 Handling devices implementing both MSI and MSI-X capabilities	369	4.4 Handling devices implementing both MSI and MSI-X capabilities
259		370
260	If a device implements both MSI and MSI-X capabilities, it can	371	If a device implements both MSI and MSI-X capabilities, it can
261	run in either MSI mode or MSI-X mode, but not both simultaneously.	372	run in either MSI mode or MSI-X mode, but not both simultaneously.
262	This is a requirement of the PCI spec, and it is enforced by the	373	This is a requirement of the PCI spec, and it is enforced by the
263	PCI layer. Calling pci_enable_msi() when MSI-X is already enabled or	374	PCI layer. Calling pci_enable_msi_range() when MSI-X is already
264	pci_enable_msix() when MSI is already enabled results in an error.	375	enabled or pci_enable_msix_range() when MSI is already enabled
265	If a device driver wishes to switch between MSI and MSI-X at runtime,	376	results in an error. If a device driver wishes to switch between MSI
266	it must first quiesce the device, then switch it back to pin-interrupt	377	and MSI-X at runtime, it must first quiesce the device, then switch
267	mode, before calling pci_enable_msi() or pci_enable_msix() and resuming	378	it back to pin-interrupt mode, before calling pci_enable_msi_range()
268	operation. This is not expected to be a common operation but may be	379	or pci_enable_msix_range() and resuming operation. This is not expected
269	useful for debugging or testing during development.	380	to be a common operation but may be useful for debugging or testing
		381	during development.
270		382
271	4.5 Considerations when using MSIs	383	4.5 Considerations when using MSIs
272		384
@@ -381,5 +493,5 @@ or disabled (0). If 0 is found in any of the msi_bus files belonging · 108 unmodified lines
381	to bridges between the PCI root and the device, MSIs are disabled.	493	to bridges between the PCI root and the device, MSIs are disabled.
382		494
383	It is also worth checking the device driver to see whether it supports MSIs.	495	It is also worth checking the device driver to see whether it supports MSIs.
384	For example, it may contain calls to pci_enable_msi(), pci_enable_msix() or	496	For example, it may contain calls to pci_enable_msi_range() or
385	pci_enable_msi_block().	497	pci_enable_msix_range().

Documentation/PCI/pci.txt+4−2

@@ -123,8 +123,10 @@ initialization with a pointer to a structure describing the driver · 122 unmodified lines
123		123
124		124
125	The ID table is an array of struct pci_device_id entries ending with an	125	The ID table is an array of struct pci_device_id entries ending with an
126	all-zero entry; use of the macro DEFINE_PCI_DEVICE_TABLE is the preferred	126	all-zero entry. Definitions with static const are generally preferred.
127	method of declaring the table. Each entry consists of:	127	Use of the deprecated macro DEFINE_PCI_DEVICE_TABLE should be avoided.
		128
		129	Each entry consists of:
128		130
129	vendor,device Vendor and device ID to match (or PCI_ANY_ID)	131	vendor,device Vendor and device ID to match (or PCI_ANY_ID)
130		132

Documentation/devicetree/bindings/pci/designware-pcie.txt+2−0

@@ -19,6 +19,8 @@ Required properties: · 18 unmodified lines
19	to define the mapping of the PCIe interface to interrupt	19	to define the mapping of the PCIe interface to interrupt
20	numbers.	20	numbers.
21	- num-lanes: number of lanes to use	21	- num-lanes: number of lanes to use
		22
		23	Optional properties:
22	- reset-gpio: gpio pin number of power good signal	24	- reset-gpio: gpio pin number of power good signal
23		25
24	Optional properties for fsl,imx6q-pcie	26	Optional properties for fsl,imx6q-pcie

arch/alpha/kernel/pci-sysfs.c+2−2

@@ -83,7 +83,7 @@ static int pci_mmap_resource(struct kobject *kobj, · 82 unmodified lines
83	if (iomem_is_exclusive(res->start))	83	if (iomem_is_exclusive(res->start))
84	return -EINVAL;	84	return -EINVAL;
85		85
86	pcibios_resource_to_bus(pdev, &bar, res);	86	pcibios_resource_to_bus(pdev->bus, &bar, res);
87	vma->vm_pgoff += bar.start >> (PAGE_SHIFT - (sparse ? 5 : 0));	87	vma->vm_pgoff += bar.start >> (PAGE_SHIFT - (sparse ? 5 : 0));
88	mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io;	88	mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io;
89		89
@@ -139,7 +139,7 @@ static int sparse_mem_mmap_fits(struct pci_dev *pdev, int num) · 49 unmodified lines
139	long dense_offset;	139	long dense_offset;
140	unsigned long sparse_size;	140	unsigned long sparse_size;
141		141
142	pcibios_resource_to_bus(pdev, &bar, &pdev->resource[num]);	142	pcibios_resource_to_bus(pdev->bus, &bar, &pdev->resource[num]);
143		143
144	/* All core logic chips have 4G sparse address space, except	144	/* All core logic chips have 4G sparse address space, except
145	CIA which has 16G (see xxx_SPARSE_MEM and xxx_DENSE_MEM	145	CIA which has 16G (see xxx_SPARSE_MEM and xxx_DENSE_MEM

arch/alpha/kernel/pci_iommu.c+1−1

@@ -325,7 +325,7 @@ pci_map_single_1(struct pci_dev pdev, void cpu_addr, size_t size, · 324 unmodified lines
325	/* Helper for generic DMA-mapping functions. */	325	/* Helper for generic DMA-mapping functions. */
326	static struct pci_dev alpha_gendev_to_pci(struct device dev)	326	static struct pci_dev alpha_gendev_to_pci(struct device dev)
327	{	327	{
328	if (dev && dev->bus == &pci_bus_type)	328	if (dev && dev_is_pci(dev))
329	return to_pci_dev(dev);	329	return to_pci_dev(dev);
330		330
331	/* Assume that non-PCI devices asking for DMA are either ISA or EISA,	331	/* Assume that non-PCI devices asking for DMA are either ISA or EISA,

arch/arm/common/it8152.c+2−2

@@ -257,7 +257,7 @@ static int it8152_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t s · 256 unmodified lines
257	*/	257	*/
258	static int it8152_pci_platform_notify(struct device *dev)	258	static int it8152_pci_platform_notify(struct device *dev)
259	{	259	{
260	if (dev->bus == &pci_bus_type) {	260	if (dev_is_pci(dev)) {
261	if (dev->dma_mask)	261	if (dev->dma_mask)
262	*dev->dma_mask = (SZ_64M - 1) \| PHYS_OFFSET;	262	*dev->dma_mask = (SZ_64M - 1) \| PHYS_OFFSET;
263	dev->coherent_dma_mask = (SZ_64M - 1) \| PHYS_OFFSET;	263	dev->coherent_dma_mask = (SZ_64M - 1) \| PHYS_OFFSET;
@@ -268,7 +268,7 @@ static int it8152_pci_platform_notify(struct device *dev) · 4 unmodified lines
268		268
269	static int it8152_pci_platform_notify_remove(struct device *dev)	269	static int it8152_pci_platform_notify_remove(struct device *dev)
270	{	270	{
271	if (dev->bus == &pci_bus_type)	271	if (dev_is_pci(dev))
272	dmabounce_unregister_dev(dev);	272	dmabounce_unregister_dev(dev);
273		273
274	return 0;	274	return 0;

arch/arm/mach-ixp4xx/common-pci.c+3−3

@@ -326,7 +326,7 @@ static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t s · 325 unmodified lines
326	*/	326	*/
327	static int ixp4xx_pci_platform_notify(struct device *dev)	327	static int ixp4xx_pci_platform_notify(struct device *dev)
328	{	328	{
329	if(dev->bus == &pci_bus_type) {	329	if (dev_is_pci(dev)) {
330	*dev->dma_mask = SZ_64M - 1;	330	*dev->dma_mask = SZ_64M - 1;
331	dev->coherent_dma_mask = SZ_64M - 1;	331	dev->coherent_dma_mask = SZ_64M - 1;
332	dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);	332	dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
@@ -336,9 +336,9 @@ static int ixp4xx_pci_platform_notify(struct device *dev) · 3 unmodified lines
336		336
337	static int ixp4xx_pci_platform_notify_remove(struct device *dev)	337	static int ixp4xx_pci_platform_notify_remove(struct device *dev)
338	{	338	{
339	if(dev->bus == &pci_bus_type) {	339	if (dev_is_pci(dev))
340	dmabounce_unregister_dev(dev);	340	dmabounce_unregister_dev(dev);
341	}	341
342	return 0;	342	return 0;
343	}	343	}
344		344

arch/ia64/hp/common/sba_iommu.c+1−1

@@ -255,7 +255,7 @@ static u64 prefetch_spill_page; · 254 unmodified lines
255	#endif	255	#endif
256		256
257	#ifdef CONFIG_PCI	257	#ifdef CONFIG_PCI
258	# define GET_IOC(dev) (((dev)->bus == &pci_bus_type) \	258	# define GET_IOC(dev) ((dev_is_pci(dev)) \
259	? ((struct ioc *) PCI_CONTROLLER(to_pci_dev(dev))->iommu) : NULL)	259	? ((struct ioc *) PCI_CONTROLLER(to_pci_dev(dev))->iommu) : NULL)
260	#else	260	#else
261	# define GET_IOC(dev) NULL	261	# define GET_IOC(dev) NULL

arch/ia64/sn/pci/pci_dma.c+12−12

@@ -34,7 +34,7 @@ · 33 unmodified lines
34	*/	34	*/
35	static int sn_dma_supported(struct device *dev, u64 mask)	35	static int sn_dma_supported(struct device *dev, u64 mask)
36	{	36	{
37	BUG_ON(dev->bus != &pci_bus_type);	37	BUG_ON(!dev_is_pci(dev));
38		38
39	if (mask < 0x7fffffff)	39	if (mask < 0x7fffffff)
40	return 0;	40	return 0;
@@ -50,7 +50,7 @@ static int sn_dma_supported(struct device *dev, u64 mask) · 9 unmodified lines
50	*/	50	*/
51	int sn_dma_set_mask(struct device *dev, u64 dma_mask)	51	int sn_dma_set_mask(struct device *dev, u64 dma_mask)
52	{	52	{
53	BUG_ON(dev->bus != &pci_bus_type);	53	BUG_ON(!dev_is_pci(dev));
54		54
55	if (!sn_dma_supported(dev, dma_mask))	55	if (!sn_dma_supported(dev, dma_mask))
56	return 0;	56	return 0;
@@ -85,7 +85,7 @@ static void sn_dma_alloc_coherent(struct device dev, size_t size, · 28 unmodified lines
85	struct pci_dev *pdev = to_pci_dev(dev);	85	struct pci_dev *pdev = to_pci_dev(dev);
86	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);	86	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
87		87
88	BUG_ON(dev->bus != &pci_bus_type);	88	BUG_ON(!dev_is_pci(dev));
89		89
90	/*	90	/*
91	* Allocate the memory.	91	* Allocate the memory.
@@ -143,7 +143,7 @@ static void sn_dma_free_coherent(struct device dev, size_t size, void cpu_addr · 51 unmodified lines
143	struct pci_dev *pdev = to_pci_dev(dev);	143	struct pci_dev *pdev = to_pci_dev(dev);
144	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);	144	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
145		145
146	BUG_ON(dev->bus != &pci_bus_type);	146	BUG_ON(!dev_is_pci(dev));
147		147
148	provider->dma_unmap(pdev, dma_handle, 0);	148	provider->dma_unmap(pdev, dma_handle, 0);
149	free_pages((unsigned long)cpu_addr, get_order(size));	149	free_pages((unsigned long)cpu_addr, get_order(size));
@@ -187,7 +187,7 @@ static dma_addr_t sn_dma_map_page(struct device dev, struct page page, · 37 unmodified lines
187		187
188	dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs);	188	dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs);
189		189
190	BUG_ON(dev->bus != &pci_bus_type);	190	BUG_ON(!dev_is_pci(dev));
191		191
192	phys_addr = __pa(cpu_addr);	192	phys_addr = __pa(cpu_addr);
193	if (dmabarr)	193	if (dmabarr)
@@ -223,7 +223,7 @@ static void sn_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, · 29 unmodified lines
223	struct pci_dev *pdev = to_pci_dev(dev);	223	struct pci_dev *pdev = to_pci_dev(dev);
224	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);	224	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
225		225
226	BUG_ON(dev->bus != &pci_bus_type);	226	BUG_ON(!dev_is_pci(dev));
227		227
228	provider->dma_unmap(pdev, dma_addr, dir);	228	provider->dma_unmap(pdev, dma_addr, dir);
229	}	229	}
@@ -247,7 +247,7 @@ static void sn_dma_unmap_sg(struct device dev, struct scatterlist sgl, · 17 unmodified lines
247	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);	247	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
248	struct scatterlist *sg;	248	struct scatterlist *sg;
249		249
250	BUG_ON(dev->bus != &pci_bus_type);	250	BUG_ON(!dev_is_pci(dev));
251		251
252	for_each_sg(sgl, sg, nhwentries, i) {	252	for_each_sg(sgl, sg, nhwentries, i) {
253	provider->dma_unmap(pdev, sg->dma_address, dir);	253	provider->dma_unmap(pdev, sg->dma_address, dir);
@@ -284,7 +284,7 @@ static int sn_dma_map_sg(struct device dev, struct scatterlist sgl, · 30 unmodified lines
284		284
285	dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs);	285	dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs);
286		286
287	BUG_ON(dev->bus != &pci_bus_type);	287	BUG_ON(!dev_is_pci(dev));
288		288
289	/*	289	/*
290	* Setup a DMA address for each entry in the scatterlist.	290	* Setup a DMA address for each entry in the scatterlist.
@@ -323,26 +323,26 @@ static int sn_dma_map_sg(struct device dev, struct scatterlist sgl, · 32 unmodified lines
323	static void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,	323	static void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
324	size_t size, enum dma_data_direction dir)	324	size_t size, enum dma_data_direction dir)
325	{	325	{
326	BUG_ON(dev->bus != &pci_bus_type);	326	BUG_ON(!dev_is_pci(dev));
327	}	327	}
328		328
329	static void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,	329	static void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
330	size_t size,	330	size_t size,
331	enum dma_data_direction dir)	331	enum dma_data_direction dir)
332	{	332	{
333	BUG_ON(dev->bus != &pci_bus_type);	333	BUG_ON(!dev_is_pci(dev));
334	}	334	}
335		335
336	static void sn_dma_sync_sg_for_cpu(struct device dev, struct scatterlist sg,	336	static void sn_dma_sync_sg_for_cpu(struct device dev, struct scatterlist sg,
337	int nelems, enum dma_data_direction dir)	337	int nelems, enum dma_data_direction dir)
338	{	338	{
339	BUG_ON(dev->bus != &pci_bus_type);	339	BUG_ON(!dev_is_pci(dev));
340	}	340	}
341		341
342	static void sn_dma_sync_sg_for_device(struct device dev, struct scatterlist sg,	342	static void sn_dma_sync_sg_for_device(struct device dev, struct scatterlist sg,
343	int nelems, enum dma_data_direction dir)	343	int nelems, enum dma_data_direction dir)
344	{	344	{
345	BUG_ON(dev->bus != &pci_bus_type);	345	BUG_ON(!dev_is_pci(dev));
346	}	346	}
347		347
348	static int sn_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)	348	static int sn_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)

arch/parisc/kernel/drivers.c+5−17

 	return NULL;
 }
-#ifdef CONFIG_PCI
-static inline int is_pci_dev(struct device *dev)
-{
-	return dev->bus == &pci_bus_type;
-}
-#else
-static inline int is_pci_dev(struct device *dev)
-{
-	return 0;
-}
-#endif
 /*
  * get_node_path fills in @path with the firmware path to the device.
  * Note that if @node is a parisc device, we don't fill in the 'mod' field.
 	int i = 5;
 	memset(&path->bc, -1, 6);
-	if (is_pci_dev(dev)) {
+	if (dev_is_pci(dev)) {
 		unsigned int devfn = to_pci_dev(dev)->devfn;
 		path->mod = PCI_FUNC(devfn);
 		path->bc[i--] = PCI_SLOT(devfn);
 	}
 	while (dev != &root) {
-		if (is_pci_dev(dev)) {
+		if (dev_is_pci(dev)) {
 			unsigned int devfn = to_pci_dev(dev)->devfn;
 			path->bc[i--] = PCI_SLOT(devfn) | (PCI_FUNC(devfn)<< 5);
 		} else if (dev->bus == &parisc_bus_type) {
 		if (dev->bus == &parisc_bus_type) {
 			if (match_parisc_device(dev, d->index, d->modpath))
 				d->dev = dev;
-		} else if (is_pci_dev(dev)) {
+		} else if (dev_is_pci(dev)) {
 			if (match_pci_device(dev, d->index, d->modpath))
 				d->dev = dev;
 		} else if (dev->bus == NULL) {
 		if (!parent)
 			return NULL;
 	}
-	if (is_pci_dev(parent)) /* pci devices already parse MOD */
+	if (dev_is_pci(parent)) /* pci devices already parse MOD */
 		return parent;
 	else
 		return parse_tree_node(parent, 6, modpath);
 		padev = to_parisc_device(dev);
 		get_node_path(dev->parent, path);
 		path->mod = padev->hw_path;
-	} else if (is_pci_dev(dev)) {
+	} else if (dev_is_pci(dev)) {
 		get_node_path(dev, path);
 	}
 }

arch/powerpc/kernel/eeh_driver.c+16−3

 	edev->mode |= EEH_DEV_DISCONNECTED;
 	(*removed)++;
+	pci_lock_rescan_remove();
 	pci_stop_and_remove_bus_device(dev);
+	pci_unlock_rescan_remove();
 	return NULL;
 }
 	 * into pcibios_add_pci_devices().
 	 */
 	eeh_pe_state_mark(pe, EEH_PE_KEEP);
-	if (bus)
+	if (bus) {
+		pci_lock_rescan_remove();
 		pcibios_remove_pci_devices(bus);
-	else if (frozen_bus)
+		pci_unlock_rescan_remove();
+	} else if (frozen_bus) {
 		eeh_pe_dev_traverse(pe, eeh_rmv_device, &removed);
+	}
 	/* Reset the pci controller. (Asserts RST#; resets config space).
 	 * Reconfigure bridges and devices. Don't try to bring the system
 	if (rc)
 		return rc;
+	pci_lock_rescan_remove();
 	/* Restore PE */
 	eeh_ops->configure_bridge(pe);
 	eeh_pe_restore_bars(pe);
 	pe->tstamp = tstamp;
 	pe->freeze_count = cnt;
+	pci_unlock_rescan_remove();
 	return 0;
 }
 	eeh_pe_dev_traverse(pe, eeh_report_failure, NULL);
 	/* Shut down the device drivers for good. */
-	if (frozen_bus)
+	if (frozen_bus) {
+		pci_lock_rescan_remove();
 		pcibios_remove_pci_devices(frozen_bus);
+		pci_unlock_rescan_remove();
+	}
 }
 static void eeh_handle_special_event(void)
 	if (rc == 2 || rc == 1)
 		eeh_handle_normal_event(pe);
 	else {
+		pci_lock_rescan_remove();
 		list_for_each_entry_safe(hose, tmp,
 			&hose_list, list_node) {
 			phb_pe = eeh_phb_pe_get(hose);
 			eeh_pe_dev_traverse(pe, eeh_report_failure, NULL);
 			pcibios_remove_pci_devices(bus);
 		}
+		pci_unlock_rescan_remove();
 	}
 }

arch/powerpc/kernel/pci-common.c+2−2

@@ -835,7 +835,7 @@ static void pcibios_fixup_resources(struct pci_dev *dev) · 834 unmodified lines
835	* at 0 as unset as well, except if PCI_PROBE_ONLY is also set	835	* at 0 as unset as well, except if PCI_PROBE_ONLY is also set
836	* since in that case, we don't want to re-assign anything	836	* since in that case, we don't want to re-assign anything
837	*/	837	*/
838	pcibios_resource_to_bus(dev, &reg, res);	838	pcibios_resource_to_bus(dev->bus, &reg, res);
839	if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) \|\|	839	if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) \|\|
840	(reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {	840	(reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
841	/* Only print message if not re-assigning */	841	/* Only print message if not re-assigning */
@@ -886,7 +886,7 @@ static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, · 44 unmodified lines
886		886
887	/* Job is a bit different between memory and IO */	887	/* Job is a bit different between memory and IO */
888	if (res->flags & IORESOURCE_MEM) {	888	if (res->flags & IORESOURCE_MEM) {
889	pcibios_resource_to_bus(dev, &region, res);	889	pcibios_resource_to_bus(dev->bus, &region, res);
890		890
891	/* If the BAR is non-0 then it's probably been initialized */	891	/* If the BAR is non-0 then it's probably been initialized */
892	if (region.start != 0)	892	if (region.start != 0)

arch/powerpc/kernel/pci_of_scan.c+2−2

@@ -111,7 +111,7 @@ static void of_pci_parse_addrs(struct device_node node, struct pci_dev dev) · 110 unmodified lines
111	res->name = pci_name(dev);	111	res->name = pci_name(dev);
112	region.start = base;	112	region.start = base;
113	region.end = base + size - 1;	113	region.end = base + size - 1;
114	pcibios_bus_to_resource(dev, res, &region);	114	pcibios_bus_to_resource(dev->bus, res, &region);
115	}	115	}
116	}	116	}
117		117
@@ -280,7 +280,7 @@ void of_scan_pci_bridge(struct pci_dev *dev) · 162 unmodified lines
280	res->flags = flags;	280	res->flags = flags;
281	region.start = of_read_number(&ranges[1], 2);	281	region.start = of_read_number(&ranges[1], 2);
282	region.end = region.start + size - 1;	282	region.end = region.start + size - 1;
283	pcibios_bus_to_resource(dev, res, &region);	283	pcibios_bus_to_resource(dev->bus, res, &region);
284	}	284	}
285	sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),	285	sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
286	bus->number);	286	bus->number);

arch/s390/pci/pci.c+2−2

@@ -407,8 +407,8 @@ int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) · 406 unmodified lines
407	struct msi_msg msg;	407	struct msi_msg msg;
408	int rc;	408	int rc;
409		409
410	if (type != PCI_CAP_ID_MSIX && type != PCI_CAP_ID_MSI)	410	if (type == PCI_CAP_ID_MSI && nvec > 1)
411	return -EINVAL;	411	return 1;
412	msi_vecs = min(nvec, ZPCI_MSI_VEC_MAX);	412	msi_vecs = min(nvec, ZPCI_MSI_VEC_MAX);
413	msi_vecs = min_t(unsigned int, msi_vecs, CONFIG_PCI_NR_MSI);	413	msi_vecs = min_t(unsigned int, msi_vecs, CONFIG_PCI_NR_MSI);
414		414

arch/sparc/kernel/pci.c+3−3

@@ -392,7 +392,7 @@ static void apb_fake_ranges(struct pci_dev *dev, · 391 unmodified lines
392	res->flags = IORESOURCE_IO;	392	res->flags = IORESOURCE_IO;
393	region.start = (first << 21);	393	region.start = (first << 21);
394	region.end = (last << 21) + ((1 << 21) - 1);	394	region.end = (last << 21) + ((1 << 21) - 1);
395	pcibios_bus_to_resource(dev, res, &region);	395	pcibios_bus_to_resource(dev->bus, res, &region);
396		396
397	pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);	397	pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
398	apb_calc_first_last(map, &first, &last);	398	apb_calc_first_last(map, &first, &last);
@@ -400,7 +400,7 @@ static void apb_fake_ranges(struct pci_dev *dev, · 1 unmodified line
400	res->flags = IORESOURCE_MEM;	400	res->flags = IORESOURCE_MEM;
401	region.start = (first << 29);	401	region.start = (first << 29);
402	region.end = (last << 29) + ((1 << 29) - 1);	402	region.end = (last << 29) + ((1 << 29) - 1);
403	pcibios_bus_to_resource(dev, res, &region);	403	pcibios_bus_to_resource(dev->bus, res, &region);
404	}	404	}
405		405
406	static void pci_of_scan_bus(struct pci_pbm_info *pbm,	406	static void pci_of_scan_bus(struct pci_pbm_info *pbm,
@@ -491,7 +491,7 @@ static void of_scan_pci_bridge(struct pci_pbm_info *pbm, · 84 unmodified lines
491	res->flags = flags;	491	res->flags = flags;
492	region.start = GET_64BIT(ranges, 1);	492	region.start = GET_64BIT(ranges, 1);
493	region.end = region.start + size - 1;	493	region.end = region.start + size - 1;
494	pcibios_bus_to_resource(dev, res, &region);	494	pcibios_bus_to_resource(dev->bus, res, &region);
495	}	495	}
496	after_ranges:	496	after_ranges:
497	sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),	497	sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),

arch/x86/include/asm/pci.h+1−2

 struct msi_desc;
 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
 void native_teardown_msi_irq(unsigned int irq);
-void native_restore_msi_irqs(struct pci_dev *dev, int irq);
+void native_restore_msi_irqs(struct pci_dev *dev);
 int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
 		  unsigned int irq_base, unsigned int irq_offset);
 #else
 /* generic pci stuff */
 #include <asm-generic/pci.h>
-#define PCIBIOS_MAX_MEM_32 0xffffffff
 #ifdef CONFIG_NUMA
 /* Returns the node based on pci bus */

arch/x86/include/asm/x86_init.h+1−1

@@ -181,7 +181,7 @@ struct x86_msi_ops { · 180 unmodified lines
181	u8 hpet_id);	181	u8 hpet_id);
182	void (*teardown_msi_irq)(unsigned int irq);	182	void (*teardown_msi_irq)(unsigned int irq);
183	void (teardown_msi_irqs)(struct pci_dev dev);	183	void (teardown_msi_irqs)(struct pci_dev dev);
184	void (restore_msi_irqs)(struct pci_dev dev, int irq);	184	void (restore_msi_irqs)(struct pci_dev dev);
185	int (*setup_hpet_msi)(unsigned int irq, unsigned int id);	185	int (*setup_hpet_msi)(unsigned int irq, unsigned int id);
186	u32 (msi_mask_irq)(struct msi_desc desc, u32 mask, u32 flag);	186	u32 (msi_mask_irq)(struct msi_desc desc, u32 mask, u32 flag);
187	u32 (msix_mask_irq)(struct msi_desc desc, u32 flag);	187	u32 (msix_mask_irq)(struct msi_desc desc, u32 flag);

arch/x86/kernel/acpi/boot.c+1−3

@@ -1034,9 +1034,7 @@ static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger, · 1033 unmodified lines
1034		1034
1035	if (!acpi_ioapic)	1035	if (!acpi_ioapic)
1036	return 0;	1036	return 0;
1037	if (!dev)	1037	if (!dev \|\| !dev_is_pci(dev))
1038	return 0;
1039	if (dev->bus != &pci_bus_type)
1040	return 0;	1038	return 0;
1041		1039
1042	pdev = to_pci_dev(dev);	1040	pdev = to_pci_dev(dev);

arch/x86/kernel/x86_init.c+2−2

@@ -136,9 +136,9 @@ void arch_teardown_msi_irq(unsigned int irq) · 135 unmodified lines
136	x86_msi.teardown_msi_irq(irq);	136	x86_msi.teardown_msi_irq(irq);
137	}	137	}
138		138
139	void arch_restore_msi_irqs(struct pci_dev *dev, int irq)	139	void arch_restore_msi_irqs(struct pci_dev *dev)
140	{	140	{
141	x86_msi.restore_msi_irqs(dev, irq);	141	x86_msi.restore_msi_irqs(dev);
142	}	142	}
143	u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)	143	u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
144	{	144	{

arch/x86/pci/xen.c+1−1

@@ -337,7 +337,7 @@ out: · 336 unmodified lines
337	return ret;	337	return ret;
338	}	338	}
339		339
340	static void xen_initdom_restore_msi_irqs(struct pci_dev *dev, int irq)	340	static void xen_initdom_restore_msi_irqs(struct pci_dev *dev)
341	{	341	{
342	int ret = 0;	342	int ret = 0;
343		343

drivers/acpi/pci_root.c+6−0

 		pci_assign_unassigned_root_bus_resources(root->bus);
 	}
+	pci_lock_rescan_remove();
 	pci_bus_add_devices(root->bus);
+	pci_unlock_rescan_remove();
 	return 1;
 end:
 {
 	struct acpi_pci_root *root = acpi_driver_data(device);
+	pci_lock_rescan_remove();
 	pci_stop_root_bus(root->bus);
 	device_set_run_wake(root->bus->bridge, false);
 	pci_remove_root_bus(root->bus);
+	pci_unlock_rescan_remove();
 	kfree(root);
 }

drivers/ata/ahci.c+35−21

@@ -1148,26 +1148,40 @@ static inline void ahci_gtf_filter_workaround(struct ata_host *host) · 1147 unmodified lines
1148	{}	1148	{}
1149	#endif	1149	#endif
1150		1150
1151	static int ahci_init_interrupts(struct pci_dev pdev, struct ahci_host_priv hpriv)	1151	static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
		1152	struct ahci_host_priv *hpriv)
1152	{	1153	{
1153	int rc;	1154	int rc, nvec;
1154	unsigned int maxvec;
1155		1155
1156	if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {	1156	if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1157	rc = pci_enable_msi_block_auto(pdev, &maxvec);	1157	goto intx;
1158	if (rc > 0) {	1158
1159	if ((rc == maxvec) \|\| (rc == 1))	1159	rc = pci_msi_vec_count(pdev);
1160	return rc;	1160	if (rc < 0)
1161	/*	1161	goto intx;
1162	* Assume that advantage of multipe MSIs is negated,	1162
1163	* so fallback to single MSI mode to save resources	1163	/*
1164	*/	1164	* If number of MSIs is less than number of ports then Sharing Last
1165	pci_disable_msi(pdev);	1165	* Message mode could be enforced. In this case assume that advantage
1166	if (!pci_enable_msi(pdev))	1166	* of multipe MSIs is negated and use single MSI mode instead.
1167	return 1;	1167	*/
1168	}	1168	if (rc < n_ports)
1169	}	1169	goto single_msi;
		1170
		1171	nvec = rc;
		1172	rc = pci_enable_msi_block(pdev, nvec);
		1173	if (rc)
		1174	goto intx;
1170		1175
		1176	return nvec;
		1177
		1178	single_msi:
		1179	rc = pci_enable_msi(pdev);
		1180	if (rc)
		1181	goto intx;
		1182	return 1;
		1183
		1184	intx:
1171	pci_intx(pdev, 1);	1185	pci_intx(pdev, 1);
1172	return 0;	1186	return 0;
1173	}	1187	}
@@ -1328,10 +1342,6 @@ static int ahci_init_one(struct pci_dev pdev, const struct pci_device_id ent) · 154 unmodified lines
1328		1342
1329	hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];	1343	hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1330		1344
1331	n_msis = ahci_init_interrupts(pdev, hpriv);
1332	if (n_msis > 1)
1333	hpriv->flags \|= AHCI_HFLAG_MULTI_MSI;
1334
1335	/* save initial config */	1345	/* save initial config */
1336	ahci_pci_save_initial_config(pdev, hpriv);	1346	ahci_pci_save_initial_config(pdev, hpriv);
1337		1347
@@ -1386,6 +1396,10 @@ static int ahci_init_one(struct pci_dev pdev, const struct pci_device_id ent) · 48 unmodified lines
1386	*/	1396	*/
1387	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));	1397	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1388		1398
		1399	n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
		1400	if (n_msis > 1)
		1401	hpriv->flags \|= AHCI_HFLAG_MULTI_MSI;
		1402
1389	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);	1403	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1390	if (!host)	1404	if (!host)
1391	return -ENOMEM;	1405	return -ENOMEM;

drivers/char/agp/agp.h+1−0

@@ -239,6 +239,7 @@ long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg); · 238 unmodified lines
239		239
240	/* Chipset independent registers (from AGP Spec) */	240	/* Chipset independent registers (from AGP Spec) */
241	#define AGP_APBASE 0x10	241	#define AGP_APBASE 0x10
		242	#define AGP_APERTURE_BAR 0
242		243
243	#define AGPSTAT 0x4	244	#define AGPSTAT 0x4
244	#define AGPCMD 0x8	245	#define AGPCMD 0x8

drivers/char/agp/ali-agp.c+2−2

@@ -85,8 +85,8 @@ static int ali_configure(void) · 84 unmodified lines
85	pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) \| 0x00000010));	85	pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) \| 0x00000010));
86		86
87	/* address to map to */	87	/* address to map to */
88	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);	88	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
89	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);	89	AGP_APERTURE_BAR);
90		90
91	#if 0	91	#if 0
92	if (agp_bridge->type == ALI_M1541) {	92	if (agp_bridge->type == ALI_M1541) {

drivers/char/agp/amd-k7-agp.c+5−7

 #include <linux/slab.h>
 #include "agp.h"
-#define AMD_MMBASE	0x14
+#define AMD_MMBASE_BAR	1
 #define AMD_APSIZE	0xac
 #define AMD_MODECNTL	0xb0
 #define AMD_MODECNTL2	0xb2
 	unsigned long __iomem *cur_gatt;
 	unsigned long addr;
 	int retval;
-	u32 temp;
 	int i;
 	value = A_SIZE_LVL2(agp_bridge->current_size);
 	 * used to program the agp master not the cpu
 	 */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);
-	addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 	agp_bridge->gart_bus_addr = addr;
 	/* Calculate the agp offset */
 static int amd_irongate_configure(void)
 {
 	struct aper_size_info_lvl2 *current_size;
+	phys_addr_t reg;
 	u32 temp;
 	u16 enable_reg;
 	if (!amd_irongate_private.registers) {
 		/* Get the memory mapped registers */
-		pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
+		reg = pci_resource_start(agp_bridge->dev, AMD_MMBASE_BAR);
-		temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+		amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096);
-		amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
 		if (!amd_irongate_private.registers)
 			return -ENOMEM;
 	}

drivers/char/agp/amd64-agp.c+1−4

  */
 static int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, u16 cap)
 {
-	u32 aper_low, aper_hi;
 	u64 aper, nb_aper;
 	int order = 0;
 	u32 nb_order, nb_base;
 		apsize |= 0xf00;
 	order = 7 - hweight16(apsize);
-	pci_read_config_dword(agp, 0x10, &aper_low);
+	aper = pci_bus_address(agp, AGP_APERTURE_BAR);
-	pci_read_config_dword(agp, 0x14, &aper_hi);
-	aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
 	/*
 	 * On some sick chips APSIZE is 0. This means it wants 4G

drivers/char/agp/ati-agp.c+10−11

 #include <asm/agp.h>
 #include "agp.h"
-#define ATI_GART_MMBASE_ADDR	0x14
+#define ATI_GART_MMBASE_BAR	1
 #define ATI_RS100_APSIZE	0xac
 #define ATI_RS100_IG_AGPMODE	0xb0
 #define ATI_RS300_APSIZE	0xf8
 static int ati_configure(void)
 {
+	phys_addr_t reg;
 	u32 temp;
 	/* Get the memory mapped registers */
-	pci_read_config_dword(agp_bridge->dev, ATI_GART_MMBASE_ADDR, &temp);
+	reg = pci_resource_start(agp_bridge->dev, ATI_GART_MMBASE_BAR);
-	temp = (temp & 0xfffff000);
+	ati_generic_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096);
-	ati_generic_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
 	if (!ati_generic_private.registers)
 		return -ENOMEM;
 	else
 		pci_write_config_dword(agp_bridge->dev, ATI_RS300_IG_AGPMODE, 0x20000);
-	/* address to map too */
+	/* address to map to */
 	/*
-	pci_read_config_dword(agp_bridge.dev, AGP_APBASE, &temp);
+	agp_bridge.gart_bus_addr = pci_bus_address(agp_bridge.dev,
-	agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+						   AGP_APERTURE_BAR);
 	printk(KERN_INFO PFX "IGP320 gart_bus_addr: %x\n", agp_bridge.gart_bus_addr);
 	*/
 	writel(0x60000, ati_generic_private.registers+ATI_GART_FEATURE_ID);
 	readl(ati_generic_private.registers+ATI_GART_FEATURE_ID);	/* PCI Posting.*/
 	/* SIGNALED_SYSTEM_ERROR @ NB_STATUS */
-	pci_read_config_dword(agp_bridge->dev, 4, &temp);
+	pci_read_config_dword(agp_bridge->dev, PCI_COMMAND, &temp);
-	pci_write_config_dword(agp_bridge->dev, 4, temp | (1<<14));
+	pci_write_config_dword(agp_bridge->dev, PCI_COMMAND, temp | (1<<14));
 	/* Write out the address of the gatt table */
 	writel(agp_bridge->gatt_bus_addr, ati_generic_private.registers+ATI_GART_BASE);
 	 * This is a bus address even on the alpha, b/c its
 	 * used to program the agp master not the cpu
 	 */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);
-	addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 	agp_bridge->gart_bus_addr = addr;
 	/* Calculate the agp offset */

drivers/char/agp/efficeon-agp.c+2−3

 static int efficeon_configure(void)
 {
-	u32 temp;
 	u16 temp2;
 	struct aper_size_info_lvl2 *current_size;
 			      current_size->size_value);
 	/* address to map to */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
-	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+						    AGP_APERTURE_BAR);
 	/* agpctrl */
 	pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);

drivers/char/agp/generic.c+2−2

@@ -1396,8 +1396,8 @@ int agp3_generic_configure(void) · 1395 unmodified lines
1396		1396
1397	current_size = A_SIZE_16(agp_bridge->current_size);	1397	current_size = A_SIZE_16(agp_bridge->current_size);
1398		1398
1399	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);	1399	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
1400	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);	1400	AGP_APERTURE_BAR);
1401		1401
1402	/* set aperture size */	1402	/* set aperture size */
1403	pci_write_config_word(agp_bridge->dev, agp_bridge->capndx+AGPAPSIZE, current_size->size_value);	1403	pci_write_config_word(agp_bridge->dev, agp_bridge->capndx+AGPAPSIZE, current_size->size_value);

drivers/char/agp/intel-agp.c+20−28

 static int intel_configure(void)
 {
-	u32 temp;
 	u16 temp2;
 	struct aper_size_info_16 *current_size;
 	pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 	/* address to map to */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
-	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+						    AGP_APERTURE_BAR);
 	/* attbase - aperture base */
 	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
 static int intel_815_configure(void)
 {
-	u32 temp, addr;
+	u32 addr;
 	u8 temp2;
 	struct aper_size_info_8 *current_size;
 			current_size->size_value);
 	/* address to map to */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
-	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+						    AGP_APERTURE_BAR);
 	pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
 	addr &= INTEL_815_ATTBASE_MASK;
 static int intel_820_configure(void)
 {
-	u32 temp;
 	u8 temp2;
 	struct aper_size_info_8 *current_size;
 	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 	/* address to map to */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
-	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+						    AGP_APERTURE_BAR);
 	/* attbase - aperture base */
 	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
 static int intel_840_configure(void)
 {
-	u32 temp;
 	u16 temp2;
 	struct aper_size_info_8 *current_size;
 	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 	/* address to map to */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
-	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+						    AGP_APERTURE_BAR);
 	/* attbase - aperture base */
 	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
 static int intel_845_configure(void)
 {
-	u32 temp;
 	u8 temp2;
 	struct aper_size_info_8 *current_size;
 				       agp_bridge->apbase_config);
 	} else {
 		/* address to map to */
-		pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+		agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
-		agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+							    AGP_APERTURE_BAR);
-		agp_bridge->apbase_config = temp;
+		agp_bridge->apbase_config = agp_bridge->gart_bus_addr;
 	}
 	/* attbase - aperture base */
 static int intel_850_configure(void)
 {
-	u32 temp;
 	u16 temp2;
 	struct aper_size_info_8 *current_size;
 	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 	/* address to map to */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
-	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+						    AGP_APERTURE_BAR);
 	/* attbase - aperture base */
 	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
 static int intel_860_configure(void)
 {
-	u32 temp;
 	u16 temp2;
 	struct aper_size_info_8 *current_size;
 	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 	/* address to map to */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
-	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+						    AGP_APERTURE_BAR);
 	/* attbase - aperture base */
 	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
 static int intel_830mp_configure(void)
 {
-	u32 temp;
 	u16 temp2;
 	struct aper_size_info_8 *current_size;
 	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 	/* address to map to */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
-	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+						    AGP_APERTURE_BAR);
 	/* attbase - aperture base */
 	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
 static int intel_7505_configure(void)
 {
-	u32 temp;
 	u16 temp2;
 	struct aper_size_info_8 *current_size;
 	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 	/* address to map to */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
-	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+						    AGP_APERTURE_BAR);
 	/* attbase - aperture base */
 	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);

drivers/char/agp/intel-agp.h+5−5

@@ -55,8 +55,8 @@ · 54 unmodified lines
55	#define INTEL_I860_ERRSTS 0xc8	55	#define INTEL_I860_ERRSTS 0xc8
56		56
57	/* Intel i810 registers */	57	/* Intel i810 registers */
58	#define I810_GMADDR 0x10	58	#define I810_GMADR_BAR 0
59	#define I810_MMADDR 0x14	59	#define I810_MMADR_BAR 1
60	#define I810_PTE_BASE 0x10000	60	#define I810_PTE_BASE 0x10000
61	#define I810_PTE_MAIN_UNCACHED 0x00000000	61	#define I810_PTE_MAIN_UNCACHED 0x00000000
62	#define I810_PTE_LOCAL 0x00000002	62	#define I810_PTE_LOCAL 0x00000002
@@ -113,9 +113,9 @@ · 50 unmodified lines
113	#define INTEL_I850_ERRSTS 0xc8	113	#define INTEL_I850_ERRSTS 0xc8
114		114
115	/* intel 915G registers */	115	/* intel 915G registers */
116	#define I915_GMADDR 0x18	116	#define I915_GMADR_BAR 2
117	#define I915_MMADDR 0x10	117	#define I915_MMADR_BAR 0
118	#define I915_PTEADDR 0x1C	118	#define I915_PTE_BAR 3
119	#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)	119	#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
120	#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)	120	#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
121	#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)	121	#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)

drivers/char/agp/intel-gtt.c+19−28

 	struct pci_dev *pcidev;	/* device one */
 	struct pci_dev *bridge_dev;
 	u8 __iomem *registers;
-	phys_addr_t gtt_bus_addr;
+	phys_addr_t gtt_phys_addr;
 	u32 PGETBL_save;
 	u32 __iomem *gtt;		/* I915G */
 	bool clear_fake_agp; /* on first access via agp, fill with scratch */
 #define I810_GTT_ORDER 4
 static int i810_setup(void)
 {
-	u32 reg_addr;
+	phys_addr_t reg_addr;
 	char *gtt_table;
 	/* i81x does not preallocate the gtt. It's always 64kb in size. */
 		return -ENOMEM;
 	intel_private.i81x_gtt_table = gtt_table;
-	pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
+	reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
-	reg_addr &= 0xfff80000;
 	intel_private.registers = ioremap(reg_addr, KB(64));
 	if (!intel_private.registers)
 	writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
 	       intel_private.registers+I810_PGETBL_CTL);
-	intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
+	intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
 	if ((readl(intel_private.registers+I810_DRAM_CTL)
 		& I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 static int intel_gtt_init(void)
 {
-	u32 gma_addr;
 	u32 gtt_map_size;
-	int ret;
+	int ret, bar;
 	ret = intel_private.driver->setup();
 	if (ret != 0)
 	intel_private.gtt = NULL;
 	if (intel_gtt_can_wc())
-		intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
+		intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr,
 					       gtt_map_size);
 	if (intel_private.gtt == NULL)
-		intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
+		intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
 					    gtt_map_size);
 	if (intel_private.gtt == NULL) {
 		intel_private.driver->cleanup();
 	}
 	if (INTEL_GTT_GEN <= 2)
-		pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
+		bar = I810_GMADR_BAR;
-				      &gma_addr);
 	else
-		pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
+		bar = I915_GMADR_BAR;
-				      &gma_addr);
-	intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
+	intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
 	return 0;
 }
 static int i830_setup(void)
 {
-	u32 reg_addr;
+	phys_addr_t reg_addr;
-	pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
+	reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
-	reg_addr &= 0xfff80000;
 	intel_private.registers = ioremap(reg_addr, KB(64));
 	if (!intel_private.registers)
 		return -ENOMEM;
-	intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
+	intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
 	return 0;
 }
 static int i9xx_setup(void)
 {
-	u32 reg_addr, gtt_addr;
+	phys_addr_t reg_addr;
 	int size = KB(512);
-	pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
+	reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
-	reg_addr &= 0xfff80000;
 	intel_private.registers = ioremap(reg_addr, size);
 	if (!intel_private.registers)
 	switch (INTEL_GTT_GEN) {
 	case 3:
-		pci_read_config_dword(intel_private.pcidev,
+		intel_private.gtt_phys_addr =
-				      I915_PTEADDR, &gtt_addr);
+			pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
-		intel_private.gtt_bus_addr = gtt_addr;
 		break;
 	case 5:
-		intel_private.gtt_bus_addr = reg_addr + MB(2);
+		intel_private.gtt_phys_addr = reg_addr + MB(2);
 		break;
 	default:
-		intel_private.gtt_bus_addr = reg_addr + KB(512);
+		intel_private.gtt_phys_addr = reg_addr + KB(512);
 		break;
 	}

drivers/char/agp/nvidia-agp.c+5−4

 {
 	int i, rc, num_dirs;
 	u32 apbase, aplimit;
+	phys_addr_t apbase_phys;
 	struct aper_size_info_8 *current_size;
 	u32 temp;
 	pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
 		current_size->size_value);
-    /* address to map to */
+	/* address to map to */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &apbase);
+	apbase = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);
-	apbase &= PCI_BASE_ADDRESS_MEM_MASK;
 	agp_bridge->gart_bus_addr = apbase;
 	aplimit = apbase + (current_size->size * 1024 * 1024) - 1;
 	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase);
 	pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp | 0x100);
 	/* map aperture */
+	apbase_phys = pci_resource_start(agp_bridge->dev, AGP_APERTURE_BAR);
 	nvidia_private.aperture =
-		(volatile u32 __iomem *) ioremap(apbase, 33 * PAGE_SIZE);
+		(volatile u32 __iomem *) ioremap(apbase_phys, 33 * PAGE_SIZE);
 	if (!nvidia_private.aperture)
 		return -ENOMEM;

drivers/char/agp/sis-agp.c+2−3

 static int sis_configure(void)
 {
-	u32 temp;
 	struct aper_size_info_8 *current_size;
 	current_size = A_SIZE_8(agp_bridge->current_size);
 	pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05);
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
-	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+						    AGP_APERTURE_BAR);
 	pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE,
 			       agp_bridge->gatt_bus_addr);
 	pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,

drivers/char/agp/via-agp.c+6−7

 static int via_configure(void)
 {
-	u32 temp;
 	struct aper_size_info_8 *current_size;
 	current_size = A_SIZE_8(agp_bridge->current_size);
 	/* aperture size */
 	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
 			      current_size->size_value);
-	/* address to map too */
+	/* address to map to */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
-	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+						    AGP_APERTURE_BAR);
 	/* GART control register */
 	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
 	current_size = A_SIZE_16(agp_bridge->current_size);
-	/* address to map too */
+	/* address to map to */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
-	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+						    AGP_APERTURE_BAR);
 	/* attbase - aperture GATT base */
 	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,

drivers/eisa/eisa-bus.c+18−13

 static int __init eisa_register_device(struct eisa_device *edev)
 {
 	int rc = device_register(&edev->dev);
-	if (rc)
+	if (rc) {
+		put_device(&edev->dev);
 		return rc;
+	}
 	rc = device_create_file(&edev->dev, &dev_attr_signature);
 	if (rc)
 		}
 		if (slot) {
+			edev->res[i].name  = NULL;
 			edev->res[i].start = SLOT_ADDRESS(root, slot)
 					     + (i * 0x400);
 			edev->res[i].end   = edev->res[i].start + 0xff;
 			edev->res[i].flags = IORESOURCE_IO;
 		} else {
+			edev->res[i].name  = NULL;
 			edev->res[i].start = SLOT_ADDRESS(root, slot)
 					     + EISA_VENDOR_ID_OFFSET;
 			edev->res[i].end   = edev->res[i].start + 3;
 			edev->res[i].flags = IORESOURCE_IO | IORESOURCE_BUSY;
 		}
-		dev_printk(KERN_DEBUG, &edev->dev, "%pR\n", &edev->res[i]);
 		if (request_resource(root->res, &edev->res[i]))
 			goto failed;
 	}
 		return -ENOMEM;
 	}
-	if (eisa_init_device(root, edev, 0)) {
+	if (eisa_request_resources(root, edev, 0)) {
+		dev_warn(root->dev,
+		         "EISA: Cannot allocate resource for mainboard\n");
 		kfree(edev);
 		if (!root->force_probe)
-			return -ENODEV;
+			return -EBUSY;
 		goto force_probe;
 	}
-	if (eisa_request_resources(root, edev, 0)) {
+	if (eisa_init_device(root, edev, 0)) {
-		dev_warn(root->dev,
+		eisa_release_resources(edev);
-		         "EISA: Cannot allocate resource for mainboard\n");
 		kfree(edev);
 		if (!root->force_probe)
-			return -EBUSY;
+			return -ENODEV;
 		goto force_probe;
 	}
 			continue;
 		}
-		if (eisa_init_device(root, edev, i)) {
-			kfree(edev);
-			continue;
-		}
 		if (eisa_request_resources(root, edev, i)) {
 			dev_warn(root->dev,
 			         "Cannot allocate resource for EISA slot %d\n",
 			continue;
 		}
+		if (eisa_init_device(root, edev, i)) {
+			eisa_release_resources(edev);
+			kfree(edev);
+			continue;
+		}
 		if (edev->state == (EISA_CONFIG_ENABLED | EISA_CONFIG_FORCED))
 			enabled_str = " (forced enabled)";
 		else if (edev->state == EISA_CONFIG_FORCED)

drivers/gpu/drm/i915/i915_gem_gtt.c+3−3

@@ -1265,14 +1265,14 @@ static int ggtt_probe_common(struct drm_device *dev, · 1264 unmodified lines
1265	size_t gtt_size)	1265	size_t gtt_size)
1266	{	1266	{
1267	struct drm_i915_private *dev_priv = dev->dev_private;	1267	struct drm_i915_private *dev_priv = dev->dev_private;
1268	phys_addr_t gtt_bus_addr;	1268	phys_addr_t gtt_phys_addr;
1269	int ret;	1269	int ret;
1270		1270
1271	/* For Modern GENs the PTEs and register space are split in the BAR */	1271	/* For Modern GENs the PTEs and register space are split in the BAR */
1272	gtt_bus_addr = pci_resource_start(dev->pdev, 0) +	1272	gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1273	(pci_resource_len(dev->pdev, 0) / 2);	1273	(pci_resource_len(dev->pdev, 0) / 2);
1274		1274
1275	dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);	1275	dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1276	if (!dev_priv->gtt.gsm) {	1276	if (!dev_priv->gtt.gsm) {
1277	DRM_ERROR("Failed to map the gtt page table\n");	1277	DRM_ERROR("Failed to map the gtt page table\n");
1278	return -ENOMEM;	1278	return -ENOMEM;

drivers/message/fusion/mptbase.c+1−1

@@ -346,7 +346,7 @@ static int mpt_remove_dead_ioc_func(void *arg) · 345 unmodified lines
346	if ((pdev == NULL))	346	if ((pdev == NULL))
347	return -1;	347	return -1;
348		348
349	pci_stop_and_remove_bus_device(pdev);	349	pci_stop_and_remove_bus_device_locked(pdev);
350	return 0;	350	return 0;
351	}	351	}
352		352

drivers/pci/Kconfig+2−1

 	  If unsure, say N.
 config PCI_IOAPIC
-	tristate "PCI IO-APIC hotplug support" if X86
+	bool "PCI IO-APIC hotplug support" if X86
 	depends on PCI
 	depends on ACPI
+	depends on X86_IO_APIC
 	default !X86
 config PCI_LABEL

drivers/pci/Makefile+1−1

@@ -4,7 +4,7 @@ · 3 unmodified lines
4		4
5	obj-y += access.o bus.o probe.o host-bridge.o remove.o pci.o \	5	obj-y += access.o bus.o probe.o host-bridge.o remove.o pci.o \
6	pci-driver.o search.o pci-sysfs.o rom.o setup-res.o \	6	pci-driver.o search.o pci-sysfs.o rom.o setup-res.o \
7	irq.o vpd.o setup-bus.o	7	irq.o vpd.o setup-bus.o vc.o
8	obj-$(CONFIG_PROC_FS) += proc.o	8	obj-$(CONFIG_PROC_FS) += proc.o
9	obj-$(CONFIG_SYSFS) += slot.o	9	obj-$(CONFIG_SYSFS) += slot.o
10		10

drivers/pci/access.c+0−24

@@ -380,30 +380,6 @@ int pci_vpd_pci22_init(struct pci_dev *dev) · 379 unmodified lines
380	return 0;	380	return 0;
381	}	381	}
382		382
383	/**
384	* pci_vpd_truncate - Set available Vital Product Data size
385	* @dev: pci device struct
386	* @size: available memory in bytes
387	*
388	* Adjust size of available VPD area.
389	*/
390	int pci_vpd_truncate(struct pci_dev *dev, size_t size)
391	{
392	if (!dev->vpd)
393	return -EINVAL;
394
395	/* limited by the access method */
396	if (size > dev->vpd->len)
397	return -EINVAL;
398
399	dev->vpd->len = size;
400	if (dev->vpd->attr)
401	dev->vpd->attr->size = size;
402
403	return 0;
404	}
405	EXPORT_SYMBOL(pci_vpd_truncate);
406
407	/**	383	/**
408	* pci_cfg_access_lock - Lock PCI config reads/writes	384	* pci_cfg_access_lock - Lock PCI config reads/writes
409	* @dev: pci device struct	385	* @dev: pci device struct

drivers/pci/ats.c+0−82

@@ -234,27 +234,6 @@ void pci_disable_pri(struct pci_dev *pdev) · 233 unmodified lines
234	}	234	}
235	EXPORT_SYMBOL_GPL(pci_disable_pri);	235	EXPORT_SYMBOL_GPL(pci_disable_pri);
236		236
237	/**
238	* pci_pri_enabled - Checks if PRI capability is enabled
239	* @pdev: PCI device structure
240	*
241	* Returns true if PRI is enabled on the device, false otherwise
242	*/
243	bool pci_pri_enabled(struct pci_dev *pdev)
244	{
245	u16 control;
246	int pos;
247
248	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
249	if (!pos)
250	return false;
251
252	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
253
254	return (control & PCI_PRI_CTRL_ENABLE) ? true : false;
255	}
256	EXPORT_SYMBOL_GPL(pci_pri_enabled);
257
258	/**	237	/**
259	* pci_reset_pri - Resets device's PRI state	238	* pci_reset_pri - Resets device's PRI state
260	* @pdev: PCI device structure	239	* @pdev: PCI device structure
@@ -282,67 +261,6 @@ int pci_reset_pri(struct pci_dev *pdev) · 21 unmodified lines
282	return 0;	261	return 0;
283	}	262	}
284	EXPORT_SYMBOL_GPL(pci_reset_pri);	263	EXPORT_SYMBOL_GPL(pci_reset_pri);
285
286	/**
287	* pci_pri_stopped - Checks whether the PRI capability is stopped
288	* @pdev: PCI device structure
289	*
290	* Returns true if the PRI capability on the device is disabled and the
291	* device has no outstanding PRI requests, false otherwise. The device
292	* indicates this via the STOPPED bit in the status register of the
293	* capability.
294	* The device internal state can be cleared by resetting the PRI state
295	* with pci_reset_pri(). This can force the capability into the STOPPED
296	* state.
297	*/
298	bool pci_pri_stopped(struct pci_dev *pdev)
299	{
300	u16 control, status;
301	int pos;
302
303	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
304	if (!pos)
305	return true;
306
307	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
308	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
309
310	if (control & PCI_PRI_CTRL_ENABLE)
311	return false;
312
313	return (status & PCI_PRI_STATUS_STOPPED) ? true : false;
314	}
315	EXPORT_SYMBOL_GPL(pci_pri_stopped);
316
317	/**
318	* pci_pri_status - Request PRI status of a device
319	* @pdev: PCI device structure
320	*
321	* Returns negative value on failure, status on success. The status can
322	* be checked against status-bits. Supported bits are currently:
323	* PCI_PRI_STATUS_RF: Response failure
324	* PCI_PRI_STATUS_UPRGI: Unexpected Page Request Group Index
325	* PCI_PRI_STATUS_STOPPED: PRI has stopped
326	*/
327	int pci_pri_status(struct pci_dev *pdev)
328	{
329	u16 status, control;
330	int pos;
331
332	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
333	if (!pos)
334	return -EINVAL;
335
336	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
337	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
338
339	/* Stopped bit is undefined when enable == 1, so clear it */
340	if (control & PCI_PRI_CTRL_ENABLE)
341	status &= ~PCI_PRI_STATUS_STOPPED;
342
343	return status;
344	}
345	EXPORT_SYMBOL_GPL(pci_pri_status);
346	#endif /* CONFIG_PCI_PRI */	264	#endif /* CONFIG_PCI_PRI */
347		265
348	#ifdef CONFIG_PCI_PASID	266	#ifdef CONFIG_PCI_PASID

drivers/pci/bus.c+103−30

@@ -98,41 +98,54 @@ void pci_bus_remove_resources(struct pci_bus *bus) · 97 unmodified lines
98	}	98	}
99	}	99	}
100		100
101	/**	101	static struct pci_bus_region pci_32_bit = {0, 0xffffffffULL};
102	* pci_bus_alloc_resource - allocate a resource from a parent bus	102	#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
103	* @bus: PCI bus	103	static struct pci_bus_region pci_64_bit = {0,
104	* @res: resource to allocate	104	(dma_addr_t) 0xffffffffffffffffULL};
105	* @size: size of resource to allocate	105	static struct pci_bus_region pci_high = {(dma_addr_t) 0x100000000ULL,
106	* @align: alignment of resource to allocate	106	(dma_addr_t) 0xffffffffffffffffULL};
107	* @min: minimum /proc/iomem address to allocate	107	#endif
108	* @type_mask: IORESOURCE_* type flags	108
109	* @alignf: resource alignment function	109	/*
110	* @alignf_data: data argument for resource alignment function	110	* @res contains CPU addresses. Clip it so the corresponding bus addresses
111	*	111	* on @bus are entirely within @region. This is used to control the bus
112	* Given the PCI bus a device resides on, the size, minimum address,	112	* addresses of resources we allocate, e.g., we may need a resource that
113	* alignment and type, try to find an acceptable resource allocation	113	* can be mapped by a 32-bit BAR.
114	* for a specific device resource.
115	*/	114	*/
116	int	115	static void pci_clip_resource_to_region(struct pci_bus *bus,
117	pci_bus_alloc_resource(struct pci_bus bus, struct resource res,	116	struct resource *res,
		117	struct pci_bus_region *region)
		118	{
		119	struct pci_bus_region r;
		120
		121	pcibios_resource_to_bus(bus, &r, res);
		122	if (r.start < region->start)
		123	r.start = region->start;
		124	if (r.end > region->end)
		125	r.end = region->end;
		126
		127	if (r.end < r.start)
		128	res->end = res->start - 1;
		129	else
		130	pcibios_bus_to_resource(bus, res, &r);
		131	}
		132
		133	static int pci_bus_alloc_from_region(struct pci_bus bus, struct resource res,
118	resource_size_t size, resource_size_t align,	134	resource_size_t size, resource_size_t align,
119	resource_size_t min, unsigned int type_mask,	135	resource_size_t min, unsigned int type_mask,
120	resource_size_t (alignf)(void ,	136	resource_size_t (alignf)(void ,
121	const struct resource *,	137	const struct resource *,
122	resource_size_t,	138	resource_size_t,
123	resource_size_t),	139	resource_size_t),
124	void *alignf_data)	140	void *alignf_data,
		141	struct pci_bus_region *region)
125	{	142	{
126	int i, ret = -ENOMEM;	143	int i, ret;
127	struct resource *r;	144	struct resource *r, avail;
128	resource_size_t max = -1;	145	resource_size_t max;
129		146
130	type_mask \|= IORESOURCE_IO \| IORESOURCE_MEM;	147	type_mask \|= IORESOURCE_IO \| IORESOURCE_MEM;
131		148
132	/* don't allocate too high if the pref mem doesn't support 64bit*/
133	if (!(res->flags & IORESOURCE_MEM_64))
134	max = PCIBIOS_MAX_MEM_32;
135
136	pci_bus_for_each_resource(bus, r, i) {	149	pci_bus_for_each_resource(bus, r, i) {
137	if (!r)	150	if (!r)
138	continue;	151	continue;
@@ -147,15 +160,74 @@ pci_bus_alloc_resource(struct pci_bus bus, struct resource res, · 8 unmodified lines
147	!(res->flags & IORESOURCE_PREFETCH))	160	!(res->flags & IORESOURCE_PREFETCH))
148	continue;	161	continue;
149		162
		163	avail = *r;
		164	pci_clip_resource_to_region(bus, &avail, region);
		165	if (!resource_size(&avail))
		166	continue;
		167
		168	/*
		169	* "min" is typically PCIBIOS_MIN_IO or PCIBIOS_MIN_MEM to
		170	* protect badly documented motherboard resources, but if
		171	* this is an already-configured bridge window, its start
		172	* overrides "min".
		173	*/
		174	if (avail.start)
		175	min = avail.start;
		176
		177	max = avail.end;
		178
150	/* Ok, try it out.. */	179	/* Ok, try it out.. */
151	ret = allocate_resource(r, res, size,	180	ret = allocate_resource(r, res, size, min, max,
152	r->start ? : min,	181	align, alignf, alignf_data);
153	max, align,
154	alignf, alignf_data);
155	if (ret == 0)	182	if (ret == 0)
156	break;	183	return 0;
157	}	184	}
158	return ret;	185	return -ENOMEM;
		186	}
		187
		188	/**
		189	* pci_bus_alloc_resource - allocate a resource from a parent bus
		190	* @bus: PCI bus
		191	* @res: resource to allocate
		192	* @size: size of resource to allocate
		193	* @align: alignment of resource to allocate
		194	* @min: minimum /proc/iomem address to allocate
		195	* @type_mask: IORESOURCE_* type flags
		196	* @alignf: resource alignment function
		197	* @alignf_data: data argument for resource alignment function
		198	*
		199	* Given the PCI bus a device resides on, the size, minimum address,
		200	* alignment and type, try to find an acceptable resource allocation
		201	* for a specific device resource.
		202	*/
		203	int pci_bus_alloc_resource(struct pci_bus bus, struct resource res,
		204	resource_size_t size, resource_size_t align,
		205	resource_size_t min, unsigned int type_mask,
		206	resource_size_t (alignf)(void ,
		207	const struct resource *,
		208	resource_size_t,
		209	resource_size_t),
		210	void *alignf_data)
		211	{
		212	#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
		213	int rc;
		214
		215	if (res->flags & IORESOURCE_MEM_64) {
		216	rc = pci_bus_alloc_from_region(bus, res, size, align, min,
		217	type_mask, alignf, alignf_data,
		218	&pci_high);
		219	if (rc == 0)
		220	return 0;
		221
		222	return pci_bus_alloc_from_region(bus, res, size, align, min,
		223	type_mask, alignf, alignf_data,
		224	&pci_64_bit);
		225	}
		226	#endif
		227
		228	return pci_bus_alloc_from_region(bus, res, size, align, min,
		229	type_mask, alignf, alignf_data,
		230	&pci_32_bit);
159	}	231	}
160		232
161	void __weak pcibios_resource_survey_bus(struct pci_bus *bus) { }	233	void __weak pcibios_resource_survey_bus(struct pci_bus *bus) { }
@@ -176,6 +248,7 @@ int pci_bus_add_device(struct pci_dev *dev) · 14 unmodified lines
176	*/	248	*/
177	pci_fixup_device(pci_fixup_final, dev);	249	pci_fixup_device(pci_fixup_final, dev);
178	pci_create_sysfs_dev_files(dev);	250	pci_create_sysfs_dev_files(dev);
		251	pci_proc_attach_device(dev);
179		252
180	dev->match_driver = true;	253	dev->match_driver = true;
181	retval = device_attach(&dev->dev);	254	retval = device_attach(&dev->dev);

drivers/pci/host-bridge.c+8−11

 #include "pci.h"
-static struct pci_bus *find_pci_root_bus(struct pci_dev *dev)
+static struct pci_bus *find_pci_root_bus(struct pci_bus *bus)
 {
-	struct pci_bus *bus;
-	bus = dev->bus;
 	while (bus->parent)
 		bus = bus->parent;
 	return bus;
 }
-static struct pci_host_bridge *find_pci_host_bridge(struct pci_dev *dev)
+static struct pci_host_bridge *find_pci_host_bridge(struct pci_bus *bus)
 {
-	struct pci_bus *bus = find_pci_root_bus(dev);
+	struct pci_bus *root_bus = find_pci_root_bus(bus);
-	return to_pci_host_bridge(bus->bridge);
+	return to_pci_host_bridge(root_bus->bridge);
 }
 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
 	return res1->start <= res2->start && res1->end >= res2->end;
 }
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
+void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
 			     struct resource *res)
 {
-	struct pci_host_bridge *bridge = find_pci_host_bridge(dev);
+	struct pci_host_bridge *bridge = find_pci_host_bridge(bus);
 	struct pci_host_bridge_window *window;
 	resource_size_t offset = 0;
 	return region1->start <= region2->start && region1->end >= region2->end;
 }
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
 			     struct pci_bus_region *region)
 {
-	struct pci_host_bridge *bridge = find_pci_host_bridge(dev);
+	struct pci_host_bridge *bridge = find_pci_host_bridge(bus);
 	struct pci_host_bridge_window *window;
 	resource_size_t offset = 0;

drivers/pci/host/pci-exynos.c+3−2

 	int ret;
 	exynos_pcie_sideband_dbi_r_mode(pp, true);
-	ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
+	ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
 	exynos_pcie_sideband_dbi_r_mode(pp, false);
 	return ret;
 }
 	int ret;
 	exynos_pcie_sideband_dbi_w_mode(pp, true);
-	ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val);
+	ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),
+			where, size, val);
 	exynos_pcie_sideband_dbi_w_mode(pp, false);
 	return ret;
 }

drivers/pci/host/pci-imx6.c+145−80

@@ -44,10 +44,18 @@ struct imx6_pcie { · 43 unmodified lines
44	void __iomem *mem_base;	44	void __iomem *mem_base;
45	};	45	};
46		46
		47	/* PCIe Root Complex registers (memory-mapped) */
		48	#define PCIE_RC_LCR 0x7c
		49	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
		50	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
		51	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
		52
47	/* PCIe Port Logic registers (memory-mapped) */	53	/* PCIe Port Logic registers (memory-mapped) */
48	#define PL_OFFSET 0x700	54	#define PL_OFFSET 0x700
49	#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)	55	#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
50	#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)	56	#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
		57	#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
		58	#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
51		59
52	#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)	60	#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
53	#define PCIE_PHY_CTRL_DATA_LOC 0	61	#define PCIE_PHY_CTRL_DATA_LOC 0
@@ -59,6 +67,9 @@ struct imx6_pcie { · 5 unmodified lines
59	#define PCIE_PHY_STAT (PL_OFFSET + 0x110)	67	#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
60	#define PCIE_PHY_STAT_ACK_LOC 16	68	#define PCIE_PHY_STAT_ACK_LOC 16
61		69
		70	#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
		71	#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
		72
62	/* PHY registers (not memory-mapped) */	73	/* PHY registers (not memory-mapped) */
63	#define PCIE_PHY_RX_ASIC_OUT 0x100D	74	#define PCIE_PHY_RX_ASIC_OUT 0x100D
64		75
@@ -209,15 +220,9 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp) · 144 unmodified lines
209		220
210	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,	221	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
211	IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);	222	IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
212	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
213	IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
214	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,	223	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
215	IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);	224	IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
216		225
217	gpio_set_value(imx6_pcie->reset_gpio, 0);
218	msleep(100);
219	gpio_set_value(imx6_pcie->reset_gpio, 1);
220
221	return 0;	226	return 0;
222	}	227	}
223		228
@@ -261,6 +266,12 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) · 37 unmodified lines
261	/* allow the clocks to stabilize */	266	/* allow the clocks to stabilize */
262	usleep_range(200, 500);	267	usleep_range(200, 500);
263		268
		269	/* Some boards don't have PCIe reset GPIO. */
		270	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
		271	gpio_set_value(imx6_pcie->reset_gpio, 0);
		272	msleep(100);
		273	gpio_set_value(imx6_pcie->reset_gpio, 1);
		274	}
264	return 0;	275	return 0;
265		276
266	err_pcie_axi:	277	err_pcie_axi:
@@ -299,11 +310,90 @@ static void imx6_pcie_init_phy(struct pcie_port *pp) · 32 unmodified lines
299	IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);	310	IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
300	}	311	}
301		312
302	static void imx6_pcie_host_init(struct pcie_port *pp)	313	static int imx6_pcie_wait_for_link(struct pcie_port *pp)
		314	{
		315	int count = 200;
		316
		317	while (!dw_pcie_link_up(pp)) {
		318	usleep_range(100, 1000);
		319	if (--count)
		320	continue;
		321
		322	dev_err(pp->dev, "phy link never came up\n");
		323	dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
		324	readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
		325	readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
		326	return -EINVAL;
		327	}
		328
		329	return 0;
		330	}
		331
		332	static int imx6_pcie_start_link(struct pcie_port *pp)
303	{	333	{
304	int count = 0;
305	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);	334	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
		335	uint32_t tmp;
		336	int ret, count;
306		337
		338	/*
		339	* Force Gen1 operation when starting the link. In case the link is
		340	* started in Gen2 mode, there is a possibility the devices on the
		341	* bus will not be detected at all. This happens with PCIe switches.
		342	*/
		343	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
		344	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
		345	tmp \|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
		346	writel(tmp, pp->dbi_base + PCIE_RC_LCR);
		347
		348	/* Start LTSSM. */
		349	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
		350	IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
		351
		352	ret = imx6_pcie_wait_for_link(pp);
		353	if (ret)
		354	return ret;
		355
		356	/* Allow Gen2 mode after the link is up. */
		357	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
		358	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
		359	tmp \|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
		360	writel(tmp, pp->dbi_base + PCIE_RC_LCR);
		361
		362	/*
		363	* Start Directed Speed Change so the best possible speed both link
		364	* partners support can be negotiated.
		365	*/
		366	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
		367	tmp \|= PORT_LOGIC_SPEED_CHANGE;
		368	writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
		369
		370	count = 200;
		371	while (count--) {
		372	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
		373	/* Test if the speed change finished. */
		374	if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
		375	break;
		376	usleep_range(100, 1000);
		377	}
		378
		379	/* Make sure link training is finished as well! */
		380	if (count)
		381	ret = imx6_pcie_wait_for_link(pp);
		382	else
		383	ret = -EINVAL;
		384
		385	if (ret) {
		386	dev_err(pp->dev, "Failed to bring link up!\n");
		387	} else {
		388	tmp = readl(pp->dbi_base + 0x80);
		389	dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
		390	}
		391
		392	return ret;
		393	}
		394
		395	static void imx6_pcie_host_init(struct pcie_port *pp)
		396	{
307	imx6_pcie_assert_core_reset(pp);	397	imx6_pcie_assert_core_reset(pp);
308		398
309	imx6_pcie_init_phy(pp);	399	imx6_pcie_init_phy(pp);
@@ -312,33 +402,41 @@ static void imx6_pcie_host_init(struct pcie_port *pp) · 2 unmodified lines
312		402
313	dw_pcie_setup_rc(pp);	403	dw_pcie_setup_rc(pp);
314		404
315	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,	405	imx6_pcie_start_link(pp);
316	IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);	406	}
317		407
318	while (!dw_pcie_link_up(pp)) {	408	static void imx6_pcie_reset_phy(struct pcie_port *pp)
319	usleep_range(100, 1000);	409	{
320	count++;	410	uint32_t temp;
321	if (count >= 200) {	411
322	dev_err(pp->dev, "phy link never came up\n");	412	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
323	dev_dbg(pp->dev,	413	temp \|= (PHY_RX_OVRD_IN_LO_RX_DATA_EN \|
324	"DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",	414	PHY_RX_OVRD_IN_LO_RX_PLL_EN);
325	readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),	415	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
326	readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));	416
327	break;	417	usleep_range(2000, 3000);
328	}
329	}
330		418
331	return;	419	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
		420	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN \|
		421	PHY_RX_OVRD_IN_LO_RX_PLL_EN);
		422	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
332	}	423	}
333		424
334	static int imx6_pcie_link_up(struct pcie_port *pp)	425	static int imx6_pcie_link_up(struct pcie_port *pp)
335	{	426	{
336	u32 rc, ltssm, rx_valid, temp;	427	u32 rc, ltssm, rx_valid;
337		428
338	/* link is debug bit 36, debug register 1 starts at bit 32 */	429	/*
339	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));	430	* Test if the PHY reports that the link is up and also that
340	if (rc)	431	* the link training finished. It might happen that the PHY
341	return -EAGAIN;	432	* reports the link is already up, but the link training bit
		433	* is still set, so make sure to check the training is done
		434	* as well here.
		435	*/
		436	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
		437	if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&
		438	!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
		439	return 1;
342		440
343	/*	441	/*
344	* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.	442	* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
@@ -358,21 +456,7 @@ static int imx6_pcie_link_up(struct pcie_port *pp) · 13 unmodified lines
358		456
359	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");	457	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
360		458
361	pcie_phy_read(pp->dbi_base,	459	imx6_pcie_reset_phy(pp);
362	PHY_RX_OVRD_IN_LO, &temp);
363	temp \|= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
364	\| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
365	pcie_phy_write(pp->dbi_base,
366	PHY_RX_OVRD_IN_LO, temp);
367
368	usleep_range(2000, 3000);
369
370	pcie_phy_read(pp->dbi_base,
371	PHY_RX_OVRD_IN_LO, &temp);
372	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
373	\| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
374	pcie_phy_write(pp->dbi_base,
375	PHY_RX_OVRD_IN_LO, temp);
376		460
377	return 0;	461	return 0;
378	}	462	}
@@ -426,30 +510,19 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) · 47 unmodified lines
426	"imprecise external abort");	510	"imprecise external abort");
427		511
428	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);	512	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
429	if (!dbi_base) {
430	dev_err(&pdev->dev, "dbi_base memory resource not found\n");
431	return -ENODEV;
432	}
433
434	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);	513	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
435	if (IS_ERR(pp->dbi_base)) {	514	if (IS_ERR(pp->dbi_base))
436	ret = PTR_ERR(pp->dbi_base);	515	return PTR_ERR(pp->dbi_base);
437	goto err;
438	}
439		516
440	/* Fetch GPIOs */	517	/* Fetch GPIOs */
441	imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);	518	imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
442	if (!gpio_is_valid(imx6_pcie->reset_gpio)) {	519	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
443	dev_err(&pdev->dev, "no reset-gpio defined\n");	520	ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
444	ret = -ENODEV;	521	GPIOF_OUT_INIT_LOW, "PCIe reset");
445	}	522	if (ret) {
446	ret = devm_gpio_request_one(&pdev->dev,	523	dev_err(&pdev->dev, "unable to get reset gpio\n");
447	imx6_pcie->reset_gpio,	524	return ret;
448	GPIOF_OUT_INIT_LOW,	525	}
449	"PCIe reset");
450	if (ret) {
451	dev_err(&pdev->dev, "unable to get reset gpio\n");
452	goto err;
453	}	526	}
454		527
455	imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);	528	imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
@@ -460,7 +533,7 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) · 4 unmodified lines
460	"PCIe power enable");	533	"PCIe power enable");
461	if (ret) {	534	if (ret) {
462	dev_err(&pdev->dev, "unable to get power-on gpio\n");	535	dev_err(&pdev->dev, "unable to get power-on gpio\n");
463	goto err;	536	return ret;
464	}	537	}
465	}	538	}
466		539
@@ -472,7 +545,7 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) · 5 unmodified lines
472	"PCIe wake up");	545	"PCIe wake up");
473	if (ret) {	546	if (ret) {
474	dev_err(&pdev->dev, "unable to get wake-up gpio\n");	547	dev_err(&pdev->dev, "unable to get wake-up gpio\n");
475	goto err;	548	return ret;
476	}	549	}
477	}	550	}
478		551
@@ -484,7 +557,7 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) · 5 unmodified lines
484	"PCIe disable endpoint");	557	"PCIe disable endpoint");
485	if (ret) {	558	if (ret) {
486	dev_err(&pdev->dev, "unable to get disable-ep gpio\n");	559	dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
487	goto err;	560	return ret;
488	}	561	}
489	}	562	}
490		563
@@ -493,32 +566,28 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) · 2 unmodified lines
493	if (IS_ERR(imx6_pcie->lvds_gate)) {	566	if (IS_ERR(imx6_pcie->lvds_gate)) {
494	dev_err(&pdev->dev,	567	dev_err(&pdev->dev,
495	"lvds_gate clock select missing or invalid\n");	568	"lvds_gate clock select missing or invalid\n");
496	ret = PTR_ERR(imx6_pcie->lvds_gate);	569	return PTR_ERR(imx6_pcie->lvds_gate);
497	goto err;
498	}	570	}
499		571
500	imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");	572	imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
501	if (IS_ERR(imx6_pcie->sata_ref_100m)) {	573	if (IS_ERR(imx6_pcie->sata_ref_100m)) {
502	dev_err(&pdev->dev,	574	dev_err(&pdev->dev,
503	"sata_ref_100m clock source missing or invalid\n");	575	"sata_ref_100m clock source missing or invalid\n");
504	ret = PTR_ERR(imx6_pcie->sata_ref_100m);	576	return PTR_ERR(imx6_pcie->sata_ref_100m);
505	goto err;
506	}	577	}
507		578
508	imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");	579	imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
509	if (IS_ERR(imx6_pcie->pcie_ref_125m)) {	580	if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
510	dev_err(&pdev->dev,	581	dev_err(&pdev->dev,
511	"pcie_ref_125m clock source missing or invalid\n");	582	"pcie_ref_125m clock source missing or invalid\n");
512	ret = PTR_ERR(imx6_pcie->pcie_ref_125m);	583	return PTR_ERR(imx6_pcie->pcie_ref_125m);
513	goto err;
514	}	584	}
515		585
516	imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");	586	imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
517	if (IS_ERR(imx6_pcie->pcie_axi)) {	587	if (IS_ERR(imx6_pcie->pcie_axi)) {
518	dev_err(&pdev->dev,	588	dev_err(&pdev->dev,
519	"pcie_axi clock source missing or invalid\n");	589	"pcie_axi clock source missing or invalid\n");
520	ret = PTR_ERR(imx6_pcie->pcie_axi);	590	return PTR_ERR(imx6_pcie->pcie_axi);
521	goto err;
522	}	591	}
523		592
524	/* Grab GPR config register range */	593	/* Grab GPR config register range */
@@ -526,19 +595,15 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) · 1 unmodified line
526	syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");	595	syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
527	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {	596	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
528	dev_err(&pdev->dev, "unable to find iomuxc registers\n");	597	dev_err(&pdev->dev, "unable to find iomuxc registers\n");
529	ret = PTR_ERR(imx6_pcie->iomuxc_gpr);	598	return PTR_ERR(imx6_pcie->iomuxc_gpr);
530	goto err;
531	}	599	}
532		600
533	ret = imx6_add_pcie_port(pp, pdev);	601	ret = imx6_add_pcie_port(pp, pdev);
534	if (ret < 0)	602	if (ret < 0)
535	goto err;	603	return ret;
536		604
537	platform_set_drvdata(pdev, imx6_pcie);	605	platform_set_drvdata(pdev, imx6_pcie);
538	return 0;	606	return 0;
539
540	err:
541	return ret;
542	}	607	}
543		608
544	static const struct of_device_id imx6_pcie_of_match[] = {	609	static const struct of_device_id imx6_pcie_of_match[] = {

drivers/pci/host/pci-mvebu.c+62−37

 	return readl(port->base + reg);
 }
+static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
+{
+	return port->io_target != -1 && port->io_attr != -1;
+}
 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
 {
 	return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
 	/* Are the new iobase/iolimit values invalid? */
 	if (port->bridge.iolimit < port->bridge.iobase ||
-	    port->bridge.iolimitupper < port->bridge.iobaseupper) {
+	    port->bridge.iolimitupper < port->bridge.iobaseupper ||
+	    !(port->bridge.command & PCI_COMMAND_IO)) {
 		/* If a window was configured, remove it */
 		if (port->iowin_base) {
 		return;
 	}
+	if (!mvebu_has_ioport(port)) {
+		dev_WARN(&port->pcie->pdev->dev,
+			 "Attempt to set IO when IO is disabled\n");
+		return;
+	}
 	/*
 	 * We read the PCI-to-PCI bridge emulated registers, and
 	 * calculate the base address and size of the address decoding
 	mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
 					  port->iowin_base, port->iowin_size,
 					  iobase);
-	pci_ioremap_io(iobase, port->iowin_base);
 }
 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
 {
 	/* Are the new membase/memlimit values invalid? */
-	if (port->bridge.memlimit < port->bridge.membase) {
+	if (port->bridge.memlimit < port->bridge.membase ||
+	    !(port->bridge.command & PCI_COMMAND_MEMORY)) {
 		/* If a window was configured, remove it */
 		if (port->memwin_base) {
 		break;
 	case PCI_IO_BASE:
-		*value = (bridge->secondary_status << 16 |
+		if (!mvebu_has_ioport(port))
-			  bridge->iolimit          <<  8 |
+			*value = bridge->secondary_status << 16;
-			  bridge->iobase);
+		else
+			*value = (bridge->secondary_status << 16 |
+				  bridge->iolimit          <<  8 |
+				  bridge->iobase);
 		break;
 	case PCI_MEMORY_BASE:
 	switch (where & ~3) {
 	case PCI_COMMAND:
+	{
+		u32 old = bridge->command;
+		if (!mvebu_has_ioport(port))
+			value &= ~PCI_COMMAND_IO;
 		bridge->command = value & 0xffff;
+		if ((old ^ bridge->command) & PCI_COMMAND_IO)
+			mvebu_pcie_handle_iobase_change(port);
+		if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
+			mvebu_pcie_handle_membase_change(port);
 		break;
+	}
 	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
 		bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
 		 */
 		bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
 		bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
-		bridge->secondary_status = value >> 16;
 		mvebu_pcie_handle_iobase_change(port);
 		break;
 	struct mvebu_pcie *pcie = sys_to_pcie(sys);
 	int i;
-	pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
+	if (resource_size(&pcie->realio) != 0)
+		pci_add_resource_offset(&sys->resources, &pcie->realio,
+					sys->io_offset);
 	pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
 	pci_add_resource(&sys->resources, &pcie->busn);
 	 * aligned on their size
 	 */
 	if (res->flags & IORESOURCE_IO)
-		return round_up(start, max((resource_size_t)SZ_64K, size));
+		return round_up(start, max_t(resource_size_t, SZ_64K, size));
 	else if (res->flags & IORESOURCE_MEM)
-		return round_up(start, max((resource_size_t)SZ_1M, size));
+		return round_up(start, max_t(resource_size_t, SZ_1M, size));
 	else
 		return start;
 }
 #define DT_CPUADDR_TO_ATTR(cpuaddr)   (((cpuaddr) >> 48) & 0xFF)
 static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
-			      unsigned long type, int *tgt, int *attr)
+			      unsigned long type,
+			      unsigned int *tgt,
+			      unsigned int *attr)
 {
 	const int na = 3, ns = 2;
 	const __be32 *range;
 	int rlen, nranges, rangesz, pna, i;
+	*tgt = -1;
+	*attr = -1;
 	range = of_get_property(np, "ranges", &rlen);
 	if (!range)
 		return -EINVAL;
 	}
 	mvebu_mbus_get_pcie_io_aperture(&pcie->io);
-	if (resource_size(&pcie->io) == 0) {
-		dev_err(&pdev->dev, "invalid I/O aperture size\n");
-		return -EINVAL;
-	}
-	pcie->realio.flags = pcie->io.flags;
+	if (resource_size(&pcie->io) != 0) {
-	pcie->realio.start = PCIBIOS_MIN_IO;
+		pcie->realio.flags = pcie->io.flags;
-	pcie->realio.end = min_t(resource_size_t,
+		pcie->realio.start = PCIBIOS_MIN_IO;
-				  IO_SPACE_LIMIT,
+		pcie->realio.end = min_t(resource_size_t,
-				  resource_size(&pcie->io));
+					 IO_SPACE_LIMIT,
+					 resource_size(&pcie->io));
+	} else
+		pcie->realio = pcie->io;
 	/* Get the bus range */
 	ret = of_pci_parse_bus_range(np, &pcie->busn);
 			continue;
 		}
-		ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
+		if (resource_size(&pcie->io) != 0)
-					 &port->io_target, &port->io_attr);
+			mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
-		if (ret < 0) {
+					   &port->io_target, &port->io_attr);
-			dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for io window\n",
+		else {
-				port->port, port->lane);
+			port->io_target = -1;
-			continue;
+			port->io_attr = -1;
 		}
 		port->reset_gpio = of_get_named_gpio_flags(child,
 		mvebu_pcie_set_local_dev_nr(port, 1);
-		port->clk = of_clk_get_by_name(child, NULL);
-		if (IS_ERR(port->clk)) {
-			dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
-			       port->port, port->lane);
-			iounmap(port->base);
-			continue;
-		}
 		port->dn = child;
 		spin_lock_init(&port->conf_lock);
 		mvebu_sw_pci_bridge_init(port);
 	}
 	pcie->nports = i;
+	for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K)
+		pci_ioremap_io(i, pcie->io.start + i);
 	mvebu_pcie_msi_enable(pcie);
 	mvebu_pcie_enable(pcie);
 	.driver = {
 		.owner = THIS_MODULE,
 		.name = "mvebu-pcie",
-		.of_match_table =
+		.of_match_table = mvebu_pcie_of_match_table,
-		   of_match_ptr(mvebu_pcie_of_match_table),
 		/* driver unloading/unbinding currently not supported */
 		.suppress_bind_attrs = true,
 	},

drivers/pci/host/pci-rcar-gen2.c+9−3

 #include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/slab.h>
 /* AHB-PCI Bridge PCI communication registers */
 #define RCAR_PCI_NR_CONTROLLERS		3
 struct rcar_pci_priv {
+	struct device *dev;
 	void __iomem *reg;
 	struct resource io_res;
 	struct resource mem_res;
 	void __iomem *reg = priv->reg;
 	u32 val;
+	pm_runtime_enable(priv->dev);
+	pm_runtime_get_sync(priv->dev);
 	val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
-	pr_info("PCI: bus%u revision %x\n", sys->busnr, val);
+	dev_info(priv->dev, "PCI: bus%u revision %x\n", sys->busnr, val);
 	/* Disable Direct Power Down State and assert reset */
 	val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
 	cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	reg = devm_ioremap_resource(&pdev->dev, cfg_res);
-	if (!reg)
+	if (IS_ERR(reg))
-		return -ENODEV;
+		return PTR_ERR(reg);
 	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 	if (!mem_res || !mem_res->start)
 	priv->irq = platform_get_irq(pdev, 0);
 	priv->reg = reg;
+	priv->dev = &pdev->dev;
 	return rcar_pci_add_controller(priv);
 }

drivers/pci/host/pci-tegra.c+1−1

@@ -805,7 +805,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) · 804 unmodified lines
805	afi_writel(pcie, value, AFI_PCIE_CONFIG);	805	afi_writel(pcie, value, AFI_PCIE_CONFIG);
806		806
807	value = afi_readl(pcie, AFI_FUSE);	807	value = afi_readl(pcie, AFI_FUSE);
808	value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;	808	value \|= AFI_FUSE_PCIE_T0_GEN2_DIS;
809	afi_writel(pcie, value, AFI_FUSE);	809	afi_writel(pcie, value, AFI_FUSE);
810		810
811	/* initialize internal PHY, enable up to 16 PCIE lanes */	811	/* initialize internal PHY, enable up to 16 PCIE lanes */

drivers/pci/host/pcie-designware.c+59−32

 	return sys->private_data;
 }
-int cfg_read(void __iomem *addr, int where, int size, u32 *val)
+int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
 {
 	*val = readl(addr);
 	return PCIBIOS_SUCCESSFUL;
 }
-int cfg_write(void __iomem *addr, int where, int size, u32 val)
+int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
 {
 	if (size == 4)
 		writel(val, addr);
 	if (pp->ops->rd_own_conf)
 		ret = pp->ops->rd_own_conf(pp, where, size, val);
 	else
-		ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
+		ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
+				size, val);
 	return ret;
 }
 	if (pp->ops->wr_own_conf)
 		ret = pp->ops->wr_own_conf(pp, where, size, val);
 	else
-		ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
+		ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
-				val);
+				size, val);
 	return ret;
 }
 			while ((pos = find_next_bit(&val, 32, pos)) != 32) {
 				irq = irq_find_mapping(pp->irq_domain,
 						i * 32 + pos);
+				dw_pcie_wr_own_conf(pp,
+						PCIE_MSI_INTR0_STATUS + i * 12,
+						4, 1 << pos);
 				generic_handle_irq(irq);
 				pos++;
 			}
 		}
-		dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, val);
 	}
 }
 	return 0;
 }
+static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
+			    unsigned int nvec, unsigned int pos)
+{
+	unsigned int i, res, bit, val;
+	for (i = 0; i < nvec; i++) {
+		irq_set_msi_desc_off(irq_base, i, NULL);
+		clear_bit(pos + i, pp->msi_irq_in_use);
+		/* Disable corresponding interrupt on MSI controller */
+		res = ((pos + i) / 32) * 12;
+		bit = (pos + i) % 32;
+		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
+		val &= ~(1 << bit);
+		dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
+	}
+}
 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
 {
 	int res, bit, irq, pos0, pos1, i;
 	if (!irq)
 		goto no_valid_irq;
-	i = 0;
+	/*
-	while (i < no_irqs) {
+	 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
+	 * descs so there is no need to allocate descs here. We can therefore
+	 * assume that if irq_find_mapping above returns non-zero, then the
+	 * descs are also successfully allocated.
+	 */
+	for (i = 0; i < no_irqs; i++) {
+		if (irq_set_msi_desc_off(irq, i, desc) != 0) {
+			clear_irq_range(pp, irq, i, pos0);
+			goto no_valid_irq;
+		}
 		set_bit(pos0 + i, pp->msi_irq_in_use);
-		irq_alloc_descs((irq + i), (irq + i), 1, 0);
-		irq_set_msi_desc(irq + i, desc);
 		/*Enable corresponding interrupt in MSI interrupt controller */
 		res = ((pos0 + i) / 32) * 12;
 		bit = (pos0 + i) % 32;
 		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
 		val |= 1 << bit;
 		dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
-		i++;
 	}
 	*pos = pos0;
 static void clear_irq(unsigned int irq)
 {
-	int res, bit, val, pos;
+	unsigned int pos, nvec;
 	struct irq_desc *desc;
 	struct msi_desc *msi;
 	struct pcie_port *pp;
 		return;
 	}
+	/* undo what was done in assign_irq */
 	pos = data->hwirq;
+	nvec = 1 << msi->msi_attrib.multiple;
-	irq_free_desc(irq);
+	clear_irq_range(pp, irq, nvec, pos);
-	clear_bit(pos, pp->msi_irq_in_use);
-	/* Disable corresponding interrupt on MSI interrupt controller */
+	/* all irqs cleared; reset attributes */
-	res = (pos / 32) * 12;
+	msi->irq = 0;
-	bit = pos % 32;
+	msi->msi_attrib.multiple = 0;
-	dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
-	val &= ~(1 << bit);
-	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
 }
 static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
 	if (irq < 0)
 		return irq;
-	msg_ctr &= ~PCI_MSI_FLAGS_QSIZE;
+	/*
-	msg_ctr |= msgvec << 4;
+	 * write_msi_msg() will update PCI_MSI_FLAGS so there is
-	pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
+	 * no need to explicitly call pci_write_config_word().
-				msg_ctr);
+	 */
 	desc->msi_attrib.multiple = msgvec;
 	msg.address_lo = virt_to_phys((void *)pp->msi_data);
 					   + global_io_offset);
 			pp->config.io_size = resource_size(&pp->io);
 			pp->config.io_bus_addr = range.pci_addr;
+			pp->io_base = range.cpu_addr;
 		}
 		if (restype == IORESOURCE_MEM) {
 			of_pci_range_to_resource(&range, np, &pp->mem);
 	pp->cfg0_base = pp->cfg.start;
 	pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
-	pp->io_base = pp->io.start;
 	pp->mem_base = pp->mem.start;
 	pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
 	if (bus->parent->number == pp->root_bus_nr) {
 		dw_pcie_prog_viewport_cfg0(pp, busdev);
-		ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
+		ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
+				val);
 		dw_pcie_prog_viewport_mem_outbound(pp);
 	} else {
 		dw_pcie_prog_viewport_cfg1(pp, busdev);
-		ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
+		ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
+				val);
 		dw_pcie_prog_viewport_io_outbound(pp);
 	}
 	if (bus->parent->number == pp->root_bus_nr) {
 		dw_pcie_prog_viewport_cfg0(pp, busdev);
-		ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
+		ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
+				val);
 		dw_pcie_prog_viewport_mem_outbound(pp);
 	} else {
 		dw_pcie_prog_viewport_cfg1(pp, busdev);
-		ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
+		ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
+				val);
 		dw_pcie_prog_viewport_io_outbound(pp);
 	}
 	return ret;
 }
 static int dw_pcie_valid_config(struct pcie_port *pp,
 				struct pci_bus *bus, int dev)
 {
 	if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
 		sys->io_offset = global_io_offset - pp->config.io_bus_addr;
-		pci_ioremap_io(sys->io_offset, pp->io.start);
+		pci_ioremap_io(global_io_offset, pp->io_base);
 		global_io_offset += SZ_64K;
 		pci_add_resource_offset(&sys->resources, &pp->io,
 					sys->io_offset);

drivers/pci/host/pcie-designware.h+2−2

@@ -66,8 +66,8 @@ struct pcie_host_ops { · 65 unmodified lines
66	void (host_init)(struct pcie_port pp);	66	void (host_init)(struct pcie_port pp);
67	};	67	};
68		68
69	int cfg_read(void __iomem addr, int where, int size, u32 val);	69	int dw_pcie_cfg_read(void __iomem addr, int where, int size, u32 val);
70	int cfg_write(void __iomem *addr, int where, int size, u32 val);	70	int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
71	void dw_handle_msi_irq(struct pcie_port *pp);	71	void dw_handle_msi_irq(struct pcie_port *pp);
72	void dw_pcie_msi_init(struct pcie_port *pp);	72	void dw_pcie_msi_init(struct pcie_port *pp);
73	int dw_pcie_link_up(struct pcie_port *pp);	73	int dw_pcie_link_up(struct pcie_port *pp);

drivers/pci/hotplug/acpiphp.h+4−1

 	/* PCI-to-PCI bridge device */
 	struct pci_dev *pci_dev;
+	bool is_going_away;
 };
 /* slot flags */
 #define SLOT_ENABLED		(0x00000001)
+#define SLOT_IS_GOING_AWAY	(0x00000002)
 /* function flags */
 typedef int (*acpiphp_callback)(struct acpiphp_slot *slot, void *data);
 int acpiphp_enable_slot(struct acpiphp_slot *slot);
-int acpiphp_disable_and_eject_slot(struct acpiphp_slot *slot);
+int acpiphp_disable_slot(struct acpiphp_slot *slot);
 u8 acpiphp_get_power_status(struct acpiphp_slot *slot);
 u8 acpiphp_get_attention_status(struct acpiphp_slot *slot);
 u8 acpiphp_get_latch_status(struct acpiphp_slot *slot);

drivers/pci/hotplug/acpiphp_core.c+1−1

@@ -156,7 +156,7 @@ static int disable_slot(struct hotplug_slot *hotplug_slot) · 155 unmodified lines
156	pr_debug("%s - physical_slot = %s\n", __func__, slot_name(slot));	156	pr_debug("%s - physical_slot = %s\n", __func__, slot_name(slot));
157		157
158	/* disable the specified slot */	158	/* disable the specified slot */
159	return acpiphp_disable_and_eject_slot(slot->acpi_slot);	159	return acpiphp_disable_slot(slot->acpi_slot);
160	}	160	}
161		161
162		162

drivers/pci/hotplug/acpiphp_glue.c+38−5

@@ -432,6 +432,7 @@ static void cleanup_bridge(struct acpiphp_bridge *bridge) · 431 unmodified lines
432	pr_err("failed to remove notify handler\n");	432	pr_err("failed to remove notify handler\n");
433	}	433	}
434	}	434	}
		435	slot->flags \|= SLOT_IS_GOING_AWAY;
435	if (slot->slot)	436	if (slot->slot)
436	acpiphp_unregister_hotplug_slot(slot);	437	acpiphp_unregister_hotplug_slot(slot);
437	}	438	}
@@ -439,6 +440,8 @@ static void cleanup_bridge(struct acpiphp_bridge *bridge) · 1 unmodified line
439	mutex_lock(&bridge_mutex);	440	mutex_lock(&bridge_mutex);
440	list_del(&bridge->list);	441	list_del(&bridge->list);
441	mutex_unlock(&bridge_mutex);	442	mutex_unlock(&bridge_mutex);
		443
		444	bridge->is_going_away = true;
442	}	445	}
443		446
444	/**	447	/**
@@ -757,6 +760,10 @@ static void acpiphp_check_bridge(struct acpiphp_bridge *bridge) · 312 unmodified lines
757	{	760	{
758	struct acpiphp_slot *slot;	761	struct acpiphp_slot *slot;
759		762
		763	/* Bail out if the bridge is going away. */
		764	if (bridge->is_going_away)
		765	return;
		766
760	list_for_each_entry(slot, &bridge->slots, node) {	767	list_for_each_entry(slot, &bridge->slots, node) {
761	struct pci_bus *bus = slot->bus;	768	struct pci_bus *bus = slot->bus;
762	struct pci_dev dev, tmp;	769	struct pci_dev dev, tmp;
@@ -827,6 +834,8 @@ void acpiphp_check_host_bridge(acpi_handle handle) · 64 unmodified lines
827	}	834	}
828	}	835	}
829		836
		837	static int acpiphp_disable_and_eject_slot(struct acpiphp_slot *slot);
		838
830	static void hotplug_event(acpi_handle handle, u32 type, void *data)	839	static void hotplug_event(acpi_handle handle, u32 type, void *data)
831	{	840	{
832	struct acpiphp_context *context = data;	841	struct acpiphp_context *context = data;
@@ -856,6 +865,9 @@ static void hotplug_event(acpi_handle handle, u32 type, void *data) · 23 unmodified lines
856	} else {	865	} else {
857	struct acpiphp_slot *slot = func->slot;	866	struct acpiphp_slot *slot = func->slot;
858		867
		868	if (slot->flags & SLOT_IS_GOING_AWAY)
		869	break;
		870
859	mutex_lock(&slot->crit_sect);	871	mutex_lock(&slot->crit_sect);
860	enable_slot(slot);	872	enable_slot(slot);
861	mutex_unlock(&slot->crit_sect);	873	mutex_unlock(&slot->crit_sect);
@@ -871,6 +883,9 @@ static void hotplug_event(acpi_handle handle, u32 type, void *data) · 9 unmodified lines
871	struct acpiphp_slot *slot = func->slot;	883	struct acpiphp_slot *slot = func->slot;
872	int ret;	884	int ret;
873		885
		886	if (slot->flags & SLOT_IS_GOING_AWAY)
		887	break;
		888
874	/*	889	/*
875	* Check if anything has changed in the slot and rescan	890	* Check if anything has changed in the slot and rescan
876	* from the parent if that's the case.	891	* from the parent if that's the case.
@@ -900,9 +915,11 @@ static void hotplug_event_work(void *data, u32 type) · 23 unmodified lines
900	acpi_handle handle = context->handle;	915	acpi_handle handle = context->handle;
901		916
902	acpi_scan_lock_acquire();	917	acpi_scan_lock_acquire();
		918	pci_lock_rescan_remove();
903		919
904	hotplug_event(handle, type, context);	920	hotplug_event(handle, type, context);
905		921
		922	pci_unlock_rescan_remove();
906	acpi_scan_lock_release();	923	acpi_scan_lock_release();
907	acpi_evaluate_hotplug_ost(handle, type, ACPI_OST_SC_SUCCESS, NULL);	924	acpi_evaluate_hotplug_ost(handle, type, ACPI_OST_SC_SUCCESS, NULL);
908	put_bridge(context->func.parent);	925	put_bridge(context->func.parent);
@@ -1070,12 +1087,19 @@ void acpiphp_remove_slots(struct pci_bus *bus) · 161 unmodified lines
1070	*/	1087	*/
1071	int acpiphp_enable_slot(struct acpiphp_slot *slot)	1088	int acpiphp_enable_slot(struct acpiphp_slot *slot)
1072	{	1089	{
		1090	pci_lock_rescan_remove();
		1091
		1092	if (slot->flags & SLOT_IS_GOING_AWAY)
		1093	return -ENODEV;
		1094
1073	mutex_lock(&slot->crit_sect);	1095	mutex_lock(&slot->crit_sect);
1074	/* configure all functions */	1096	/* configure all functions */
1075	if (!(slot->flags & SLOT_ENABLED))	1097	if (!(slot->flags & SLOT_ENABLED))
1076	enable_slot(slot);	1098	enable_slot(slot);
1077		1099
1078	mutex_unlock(&slot->crit_sect);	1100	mutex_unlock(&slot->crit_sect);
		1101
		1102	pci_unlock_rescan_remove();
1079	return 0;	1103	return 0;
1080	}	1104	}
1081		1105
@@ -1083,10 +1107,12 @@ int acpiphp_enable_slot(struct acpiphp_slot *slot) · 1 unmodified line
1083	* acpiphp_disable_and_eject_slot - power off and eject slot	1107	* acpiphp_disable_and_eject_slot - power off and eject slot
1084	* @slot: ACPI PHP slot	1108	* @slot: ACPI PHP slot
1085	*/	1109	*/
1086	int acpiphp_disable_and_eject_slot(struct acpiphp_slot *slot)	1110	static int acpiphp_disable_and_eject_slot(struct acpiphp_slot *slot)
1087	{	1111	{
1088	struct acpiphp_func *func;	1112	struct acpiphp_func *func;
1089	int retval = 0;	1113
		1114	if (slot->flags & SLOT_IS_GOING_AWAY)
		1115	return -ENODEV;
1090		1116
1091	mutex_lock(&slot->crit_sect);	1117	mutex_lock(&slot->crit_sect);
1092		1118
@@ -1104,9 +1130,18 @@ int acpiphp_disable_and_eject_slot(struct acpiphp_slot *slot) · 11 unmodified lines
1104	}	1130	}
1105		1131
1106	mutex_unlock(&slot->crit_sect);	1132	mutex_unlock(&slot->crit_sect);
1107	return retval;	1133	return 0;
1108	}	1134	}
1109		1135
		1136	int acpiphp_disable_slot(struct acpiphp_slot *slot)
		1137	{
		1138	int ret;
		1139
		1140	pci_lock_rescan_remove();
		1141	ret = acpiphp_disable_and_eject_slot(slot);
		1142	pci_unlock_rescan_remove();
		1143	return ret;
		1144	}
1110		1145
1111	/*	1146	/*
1112	* slot enabled: 1	1147	* slot enabled: 1
@@ -1117,7 +1152,6 @@ u8 acpiphp_get_power_status(struct acpiphp_slot *slot) · 4 unmodified lines
1117	return (slot->flags & SLOT_ENABLED);	1152	return (slot->flags & SLOT_ENABLED);
1118	}	1153	}
1119		1154
1120
1121	/*	1155	/*
1122	* latch open: 1	1156	* latch open: 1
1123	* latch closed: 0	1157	* latch closed: 0
@@ -1127,7 +1161,6 @@ u8 acpiphp_get_latch_status(struct acpiphp_slot *slot) · 3 unmodified lines
1127	return !(get_slot_status(slot) & ACPI_STA_DEVICE_UI);	1161	return !(get_slot_status(slot) & ACPI_STA_DEVICE_UI);
1128	}	1162	}
1129		1163
1130
1131	/*	1164	/*
1132	* adapter presence : 1	1165	* adapter presence : 1
1133	* absence : 0	1166	* absence : 0

drivers/pci/hotplug/cpci_hotplug_pci.c+12−2

 {
 	struct pci_dev *dev;
 	struct pci_bus *parent;
+	int ret = 0;
 	dbg("%s - enter", __func__);
+	pci_lock_rescan_remove();
 	if (slot->dev == NULL) {
 		dbg("pci_dev null, finding %02x:%02x:%x",
 		    slot->bus->number, PCI_SLOT(slot->devfn), PCI_FUNC(slot->devfn));
 		slot->dev = pci_get_slot(slot->bus, slot->devfn);
 		if (slot->dev == NULL) {
 			err("Could not find PCI device for slot %02x", slot->number);
-			return -ENODEV;
+			ret = -ENODEV;
+			goto out;
 		}
 	}
 	parent = slot->dev->bus;
 	pci_bus_add_devices(parent);
+ out:
+	pci_unlock_rescan_remove();
 	dbg("%s - exit", __func__);
-	return 0;
+	return ret;
 }
 int cpci_unconfigure_slot(struct slot* slot)
 		return -ENODEV;
 	}
+	pci_lock_rescan_remove();
 	list_for_each_entry_safe(dev, temp, &slot->bus->devices, bus_list) {
 		if (PCI_SLOT(dev->devfn) != PCI_SLOT(slot->devfn))
 			continue;
 	pci_dev_put(slot->dev);
 	slot->dev = NULL;
+	pci_unlock_rescan_remove();
 	dbg("%s - exit", __func__);
 	return 0;
 }

drivers/pci/hotplug/cpqphp_pci.c+7−1

 	struct pci_bus *child;
 	int num;
+	pci_lock_rescan_remove();
 	if (func->pci_dev == NULL)
 		func->pci_dev = pci_get_bus_and_slot(func->bus,PCI_DEVFN(func->device, func->function));
 		func->pci_dev = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, func->function));
 		if (func->pci_dev == NULL) {
 			dbg("ERROR: pci_dev still null\n");
-			return 0;
+			goto out;
 		}
 	}
 	pci_dev_put(func->pci_dev);
+ out:
+	pci_unlock_rescan_remove();
 	return 0;
 }
 	dbg("%s: bus/dev/func = %x/%x/%x\n", __func__, func->bus, func->device, func->function);
+	pci_lock_rescan_remove();
 	for (j=0; j<8 ; j++) {
 		struct pci_dev* temp = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, j));
 		if (temp) {
 			pci_stop_and_remove_bus_device(temp);
 		}
 	}
+	pci_unlock_rescan_remove();
 	return 0;
 }

drivers/pci/hotplug/ibmphp_core.c+11−2

 					func->device, func->function);
 	debug("func->device << 3 | 0x0  = %x\n", func->device << 3 | 0x0);
+	pci_lock_rescan_remove();
 	for (j = 0; j < 0x08; j++) {
 		temp = pci_get_bus_and_slot(func->busno, (func->device << 3) | j);
 		if (temp) {
 			pci_dev_put(temp);
 		}
 	}
 	pci_dev_put(func->dev);
+	pci_unlock_rescan_remove();
 }
 /*
 	int flag = 0;	/* this is to make sure we don't double scan the bus,
 					for bridged devices primarily */
+	pci_lock_rescan_remove();
 	if (!(bus_structure_fixup(func->busno)))
 		flag = 1;
 	if (func->dev == NULL)
 	if (func->dev == NULL) {
 		struct pci_bus *bus = pci_find_bus(0, func->busno);
 		if (!bus)
-			return 0;
+			goto out;
 		num = pci_scan_slot(bus,
 				PCI_DEVFN(func->device, func->function));
 				PCI_DEVFN(func->device, func->function));
 		if (func->dev == NULL) {
 			err("ERROR... : pci_dev still NULL\n");
-			return 0;
+			goto out;
 		}
 	}
 	if (!(flag) && (func->dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
 			pci_bus_add_devices(child);
 	}
+ out:
+	pci_unlock_rescan_remove();
 	return 0;
 }

drivers/pci/hotplug/pciehp.h+7−8

 extern bool pciehp_poll_mode;
 extern int pciehp_poll_time;
 extern bool pciehp_debug;
-extern bool pciehp_force;
 #define dbg(format, arg...)						\
 do {									\
 int pcie_init_notification(struct controller *ctrl);
 int pciehp_enable_slot(struct slot *p_slot);
 int pciehp_disable_slot(struct slot *p_slot);
-int pcie_enable_notification(struct controller *ctrl);
+void pcie_enable_notification(struct controller *ctrl);
 int pciehp_power_on_slot(struct slot *slot);
-int pciehp_power_off_slot(struct slot *slot);
+void pciehp_power_off_slot(struct slot *slot);
-int pciehp_get_power_status(struct slot *slot, u8 *status);
+void pciehp_get_power_status(struct slot *slot, u8 *status);
-int pciehp_get_attention_status(struct slot *slot, u8 *status);
+void pciehp_get_attention_status(struct slot *slot, u8 *status);
-int pciehp_set_attention_status(struct slot *slot, u8 status);
+void pciehp_set_attention_status(struct slot *slot, u8 status);
-int pciehp_get_latch_status(struct slot *slot, u8 *status);
+void pciehp_get_latch_status(struct slot *slot, u8 *status);
-int pciehp_get_adapter_status(struct slot *slot, u8 *status);
+void pciehp_get_adapter_status(struct slot *slot, u8 *status);
 int pciehp_query_power_fault(struct slot *slot);
 void pciehp_green_led_on(struct slot *slot);
 void pciehp_green_led_off(struct slot *slot);

drivers/pci/hotplug/pciehp_core.c+11−6

 bool pciehp_debug;
 bool pciehp_poll_mode;
 int pciehp_poll_time;
-bool pciehp_force;
+static bool pciehp_force;
 #define DRIVER_VERSION	"0.4"
 #define DRIVER_AUTHOR	"Dan Zink <dan.zink@compaq.com>, Greg Kroah-Hartman <greg@kroah.com>, Dely Sy <dely.l.sy@intel.com>"
 	ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
 		  __func__, slot_name(slot));
-	return pciehp_set_attention_status(slot, status);
+	pciehp_set_attention_status(slot, status);
+	return 0;
 }
 	ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
 		  __func__, slot_name(slot));
-	return pciehp_get_power_status(slot, value);
+	pciehp_get_power_status(slot, value);
+	return 0;
 }
 static int get_attention_status(struct hotplug_slot *hotplug_slot, u8 *value)
 	ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
 		  __func__, slot_name(slot));
-	return pciehp_get_attention_status(slot, value);
+	pciehp_get_attention_status(slot, value);
+	return 0;
 }
 static int get_latch_status(struct hotplug_slot *hotplug_slot, u8 *value)
 	ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
 		 __func__, slot_name(slot));
-	return pciehp_get_latch_status(slot, value);
+	pciehp_get_latch_status(slot, value);
+	return 0;
 }
 static int get_adapter_status(struct hotplug_slot *hotplug_slot, u8 *value)
 	ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
 		 __func__, slot_name(slot));
-	return pciehp_get_adapter_status(slot, value);
+	pciehp_get_adapter_status(slot, value);
+	return 0;
 }
 static int reset_slot(struct hotplug_slot *hotplug_slot, int probe)

drivers/pci/hotplug/pciehp_ctrl.c+30−60

@@ -158,11 +158,8 @@ static void set_slot_off(struct controller ctrl, struct slot pslot) · 157 unmodified lines
158	{	158	{
159	/* turn off slot, turn on Amber LED, turn off Green LED if supported*/	159	/* turn off slot, turn on Amber LED, turn off Green LED if supported*/
160	if (POWER_CTRL(ctrl)) {	160	if (POWER_CTRL(ctrl)) {
161	if (pciehp_power_off_slot(pslot)) {	161	pciehp_power_off_slot(pslot);
162	ctrl_err(ctrl,	162
163	"Issue of Slot Power Off command failed\n");
164	return;
165	}
166	/*	163	/*
167	* After turning power off, we must wait for at least 1 second	164	* After turning power off, we must wait for at least 1 second
168	* before taking any action that relies on power having been	165	* before taking any action that relies on power having been
@@ -171,16 +168,8 @@ static void set_slot_off(struct controller ctrl, struct slot pslot) · 2 unmodified lines
171	msleep(1000);	168	msleep(1000);
172	}	169	}
173		170
174	if (PWR_LED(ctrl))	171	pciehp_green_led_off(pslot);
175	pciehp_green_led_off(pslot);	172	pciehp_set_attention_status(pslot, 1);
176
177	if (ATTN_LED(ctrl)) {
178	if (pciehp_set_attention_status(pslot, 1)) {
179	ctrl_err(ctrl,
180	"Issue of Set Attention Led command failed\n");
181	return;
182	}
183	}
184	}	173	}
185		174
186	/**	175	/**
@@ -203,8 +192,7 @@ static int board_added(struct slot *p_slot) · 16 unmodified lines
203	return retval;	192	return retval;
204	}	193	}
205		194
206	if (PWR_LED(ctrl))	195	pciehp_green_led_blink(p_slot);
207	pciehp_green_led_blink(p_slot);
208		196
209	/* Check link training status */	197	/* Check link training status */
210	retval = pciehp_check_link_status(ctrl);	198	retval = pciehp_check_link_status(ctrl);
@@ -227,9 +215,7 @@ static int board_added(struct slot *p_slot) · 16 unmodified lines
227	goto err_exit;	215	goto err_exit;
228	}	216	}
229		217
230	if (PWR_LED(ctrl))	218	pciehp_green_led_on(p_slot);
231	pciehp_green_led_on(p_slot);
232
233	return 0;	219	return 0;
234		220
235	err_exit:	221	err_exit:
@@ -243,7 +229,7 @@ err_exit: · 7 unmodified lines
243	*/	229	*/
244	static int remove_board(struct slot *p_slot)	230	static int remove_board(struct slot *p_slot)
245	{	231	{
246	int retval = 0;	232	int retval;
247	struct controller *ctrl = p_slot->ctrl;	233	struct controller *ctrl = p_slot->ctrl;
248		234
249	retval = pciehp_unconfigure_device(p_slot);	235	retval = pciehp_unconfigure_device(p_slot);
@@ -251,13 +237,8 @@ static int remove_board(struct slot *p_slot) · 1 unmodified line
251	return retval;	237	return retval;
252		238
253	if (POWER_CTRL(ctrl)) {	239	if (POWER_CTRL(ctrl)) {
254	/* power off slot */	240	pciehp_power_off_slot(p_slot);
255	retval = pciehp_power_off_slot(p_slot);	241
256	if (retval) {
257	ctrl_err(ctrl,
258	"Issue of Slot Disable command failed\n");
259	return retval;
260	}
261	/*	242	/*
262	* After turning power off, we must wait for at least 1 second	243	* After turning power off, we must wait for at least 1 second
263	* before taking any action that relies on power having been	244	* before taking any action that relies on power having been
@@ -267,9 +248,7 @@ static int remove_board(struct slot *p_slot) · 3 unmodified lines
267	}	248	}
268		249
269	/* turn off Green LED */	250	/* turn off Green LED */
270	if (PWR_LED(ctrl))	251	pciehp_green_led_off(p_slot);
271	pciehp_green_led_off(p_slot);
272
273	return 0;	252	return 0;
274	}	253	}
275		254
@@ -305,7 +284,7 @@ static void pciehp_power_thread(struct work_struct *work) · 29 unmodified lines
305	break;	284	break;
306	case POWERON_STATE:	285	case POWERON_STATE:
307	mutex_unlock(&p_slot->lock);	286	mutex_unlock(&p_slot->lock);
308	if (pciehp_enable_slot(p_slot) && PWR_LED(p_slot->ctrl))	287	if (pciehp_enable_slot(p_slot))
309	pciehp_green_led_off(p_slot);	288	pciehp_green_led_off(p_slot);
310	mutex_lock(&p_slot->lock);	289	mutex_lock(&p_slot->lock);
311	p_slot->state = STATIC_STATE;	290	p_slot->state = STATIC_STATE;
@@ -372,11 +351,8 @@ static void handle_button_press_event(struct slot *p_slot) · 60 unmodified lines
372	"press.\n", slot_name(p_slot));	351	"press.\n", slot_name(p_slot));
373	}	352	}
374	/* blink green LED and turn off amber */	353	/* blink green LED and turn off amber */
375	if (PWR_LED(ctrl))	354	pciehp_green_led_blink(p_slot);
376	pciehp_green_led_blink(p_slot);	355	pciehp_set_attention_status(p_slot, 0);
377	if (ATTN_LED(ctrl))
378	pciehp_set_attention_status(p_slot, 0);
379
380	queue_delayed_work(p_slot->wq, &p_slot->work, 5*HZ);	356	queue_delayed_work(p_slot->wq, &p_slot->work, 5*HZ);
381	break;	357	break;
382	case BLINKINGOFF_STATE:	358	case BLINKINGOFF_STATE:
@@ -389,14 +365,11 @@ static void handle_button_press_event(struct slot *p_slot) · 6 unmodified lines
389	ctrl_info(ctrl, "Button cancel on Slot(%s)\n", slot_name(p_slot));	365	ctrl_info(ctrl, "Button cancel on Slot(%s)\n", slot_name(p_slot));
390	cancel_delayed_work(&p_slot->work);	366	cancel_delayed_work(&p_slot->work);
391	if (p_slot->state == BLINKINGOFF_STATE) {	367	if (p_slot->state == BLINKINGOFF_STATE) {
392	if (PWR_LED(ctrl))	368	pciehp_green_led_on(p_slot);
393	pciehp_green_led_on(p_slot);
394	} else {	369	} else {
395	if (PWR_LED(ctrl))	370	pciehp_green_led_off(p_slot);
396	pciehp_green_led_off(p_slot);
397	}	371	}
398	if (ATTN_LED(ctrl))	372	pciehp_set_attention_status(p_slot, 0);
399	pciehp_set_attention_status(p_slot, 0);
400	ctrl_info(ctrl, "PCI slot #%s - action canceled "	373	ctrl_info(ctrl, "PCI slot #%s - action canceled "
401	"due to button press\n", slot_name(p_slot));	374	"due to button press\n", slot_name(p_slot));
402	p_slot->state = STATIC_STATE;	375	p_slot->state = STATIC_STATE;
@@ -456,10 +429,8 @@ static void interrupt_event_handler(struct work_struct *work) · 53 unmodified lines
456	case INT_POWER_FAULT:	429	case INT_POWER_FAULT:
457	if (!POWER_CTRL(ctrl))	430	if (!POWER_CTRL(ctrl))
458	break;	431	break;
459	if (ATTN_LED(ctrl))	432	pciehp_set_attention_status(p_slot, 1);
460	pciehp_set_attention_status(p_slot, 1);	433	pciehp_green_led_off(p_slot);
461	if (PWR_LED(ctrl))
462	pciehp_green_led_off(p_slot);
463	break;	434	break;
464	case INT_PRESENCE_ON:	435	case INT_PRESENCE_ON:
465	case INT_PRESENCE_OFF:	436	case INT_PRESENCE_OFF:
@@ -482,14 +453,14 @@ int pciehp_enable_slot(struct slot *p_slot) · 16 unmodified lines
482	int rc;	453	int rc;
483	struct controller *ctrl = p_slot->ctrl;	454	struct controller *ctrl = p_slot->ctrl;
484		455
485	rc = pciehp_get_adapter_status(p_slot, &getstatus);	456	pciehp_get_adapter_status(p_slot, &getstatus);
486	if (rc \|\| !getstatus) {	457	if (!getstatus) {
487	ctrl_info(ctrl, "No adapter on slot(%s)\n", slot_name(p_slot));	458	ctrl_info(ctrl, "No adapter on slot(%s)\n", slot_name(p_slot));
488	return -ENODEV;	459	return -ENODEV;
489	}	460	}
490	if (MRL_SENS(p_slot->ctrl)) {	461	if (MRL_SENS(p_slot->ctrl)) {
491	rc = pciehp_get_latch_status(p_slot, &getstatus);	462	pciehp_get_latch_status(p_slot, &getstatus);
492	if (rc \|\| getstatus) {	463	if (getstatus) {
493	ctrl_info(ctrl, "Latch open on slot(%s)\n",	464	ctrl_info(ctrl, "Latch open on slot(%s)\n",
494	slot_name(p_slot));	465	slot_name(p_slot));
495	return -ENODEV;	466	return -ENODEV;
@@ -497,8 +468,8 @@ int pciehp_enable_slot(struct slot *p_slot) · 1 unmodified line
497	}	468	}
498		469
499	if (POWER_CTRL(p_slot->ctrl)) {	470	if (POWER_CTRL(p_slot->ctrl)) {
500	rc = pciehp_get_power_status(p_slot, &getstatus);	471	pciehp_get_power_status(p_slot, &getstatus);
501	if (rc \|\| getstatus) {	472	if (getstatus) {
502	ctrl_info(ctrl, "Already enabled on slot(%s)\n",	473	ctrl_info(ctrl, "Already enabled on slot(%s)\n",
503	slot_name(p_slot));	474	slot_name(p_slot));
504	return -EINVAL;	475	return -EINVAL;
@@ -518,15 +489,14 @@ int pciehp_enable_slot(struct slot *p_slot) · 13 unmodified lines
518	int pciehp_disable_slot(struct slot *p_slot)	489	int pciehp_disable_slot(struct slot *p_slot)
519	{	490	{
520	u8 getstatus = 0;	491	u8 getstatus = 0;
521	int ret = 0;
522	struct controller *ctrl = p_slot->ctrl;	492	struct controller *ctrl = p_slot->ctrl;
523		493
524	if (!p_slot->ctrl)	494	if (!p_slot->ctrl)
525	return 1;	495	return 1;
526		496
527	if (!HP_SUPR_RM(p_slot->ctrl)) {	497	if (!HP_SUPR_RM(p_slot->ctrl)) {
528	ret = pciehp_get_adapter_status(p_slot, &getstatus);	498	pciehp_get_adapter_status(p_slot, &getstatus);
529	if (ret \|\| !getstatus) {	499	if (!getstatus) {
530	ctrl_info(ctrl, "No adapter on slot(%s)\n",	500	ctrl_info(ctrl, "No adapter on slot(%s)\n",
531	slot_name(p_slot));	501	slot_name(p_slot));
532	return -ENODEV;	502	return -ENODEV;
@@ -534,8 +504,8 @@ int pciehp_disable_slot(struct slot *p_slot) · 1 unmodified line
534	}	504	}
535		505
536	if (MRL_SENS(p_slot->ctrl)) {	506	if (MRL_SENS(p_slot->ctrl)) {
537	ret = pciehp_get_latch_status(p_slot, &getstatus);	507	pciehp_get_latch_status(p_slot, &getstatus);
538	if (ret \|\| getstatus) {	508	if (getstatus) {
539	ctrl_info(ctrl, "Latch open on slot(%s)\n",	509	ctrl_info(ctrl, "Latch open on slot(%s)\n",
540	slot_name(p_slot));	510	slot_name(p_slot));
541	return -ENODEV;	511	return -ENODEV;
@@ -543,8 +513,8 @@ int pciehp_disable_slot(struct slot *p_slot) · 1 unmodified line
543	}	513	}
544		514
545	if (POWER_CTRL(p_slot->ctrl)) {	515	if (POWER_CTRL(p_slot->ctrl)) {
546	ret = pciehp_get_power_status(p_slot, &getstatus);	516	pciehp_get_power_status(p_slot, &getstatus);
547	if (ret \|\| !getstatus) {	517	if (!getstatus) {
548	ctrl_info(ctrl, "Already disabled on slot(%s)\n",	518	ctrl_info(ctrl, "Already disabled on slot(%s)\n",
549	slot_name(p_slot));	519	slot_name(p_slot));
550	return -EINVAL;	520	return -EINVAL;

drivers/pci/hotplug/pciehp_hpc.c+128−252

@@ -41,34 +41,11 @@ · 40 unmodified lines
41	#include "../pci.h"	41	#include "../pci.h"
42	#include "pciehp.h"	42	#include "pciehp.h"
43		43
44	static inline int pciehp_readw(struct controller ctrl, int reg, u16 value)	44	static inline struct pci_dev ctrl_dev(struct controller ctrl)
45	{	45	{
46	struct pci_dev *dev = ctrl->pcie->port;	46	return ctrl->pcie->port;
47	return pcie_capability_read_word(dev, reg, value);
48	}	47	}
49		48
50	static inline int pciehp_readl(struct controller ctrl, int reg, u32 value)
51	{
52	struct pci_dev *dev = ctrl->pcie->port;
53	return pcie_capability_read_dword(dev, reg, value);
54	}
55
56	static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
57	{
58	struct pci_dev *dev = ctrl->pcie->port;
59	return pcie_capability_write_word(dev, reg, value);
60	}
61
62	static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
63	{
64	struct pci_dev *dev = ctrl->pcie->port;
65	return pcie_capability_write_dword(dev, reg, value);
66	}
67
68	/* Power Control Command */
69	#define POWER_ON 0
70	#define POWER_OFF PCI_EXP_SLTCTL_PCC
71
72	static irqreturn_t pcie_isr(int irq, void *dev_id);	49	static irqreturn_t pcie_isr(int irq, void *dev_id);
73	static void start_int_poll_timer(struct controller *ctrl, int sec);	50	static void start_int_poll_timer(struct controller *ctrl, int sec);
74		51
@@ -129,20 +106,23 @@ static inline void pciehp_free_irq(struct controller *ctrl) · 54 unmodified lines
129		106
130	static int pcie_poll_cmd(struct controller *ctrl)	107	static int pcie_poll_cmd(struct controller *ctrl)
131	{	108	{
		109	struct pci_dev *pdev = ctrl_dev(ctrl);
132	u16 slot_status;	110	u16 slot_status;
133	int err, timeout = 1000;	111	int timeout = 1000;
134		112
135	err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);	113	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
136	if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {	114	if (slot_status & PCI_EXP_SLTSTA_CC) {
137	pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);	115	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
		116	PCI_EXP_SLTSTA_CC);
138	return 1;	117	return 1;
139	}	118	}
140	while (timeout > 0) {	119	while (timeout > 0) {
141	msleep(10);	120	msleep(10);
142	timeout -= 10;	121	timeout -= 10;
143	err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);	122	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
144	if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {	123	if (slot_status & PCI_EXP_SLTSTA_CC) {
145	pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);	124	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
		125	PCI_EXP_SLTSTA_CC);
146	return 1;	126	return 1;
147	}	127	}
148	}	128	}
@@ -169,21 +149,15 @@ static void pcie_wait_cmd(struct controller *ctrl, int poll) · 20 unmodified lines
169	* @cmd: command value written to slot control register	149	* @cmd: command value written to slot control register
170	* @mask: bitmask of slot control register to be modified	150	* @mask: bitmask of slot control register to be modified
171	*/	151	*/
172	static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)	152	static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
173	{	153	{
174	int retval = 0;	154	struct pci_dev *pdev = ctrl_dev(ctrl);
175	u16 slot_status;	155	u16 slot_status;
176	u16 slot_ctrl;	156	u16 slot_ctrl;
177		157
178	mutex_lock(&ctrl->ctrl_lock);	158	mutex_lock(&ctrl->ctrl_lock);
179		159
180	retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);	160	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
181	if (retval) {
182	ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
183	__func__);
184	goto out;
185	}
186
187	if (slot_status & PCI_EXP_SLTSTA_CC) {	161	if (slot_status & PCI_EXP_SLTSTA_CC) {
188	if (!ctrl->no_cmd_complete) {	162	if (!ctrl->no_cmd_complete) {
189	/*	163	/*
@@ -207,24 +181,17 @@ static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) · 17 unmodified lines
207	}	181	}
208	}	182	}
209		183
210	retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);	184	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
211	if (retval) {
212	ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
213	goto out;
214	}
215
216	slot_ctrl &= ~mask;	185	slot_ctrl &= ~mask;
217	slot_ctrl \|= (cmd & mask);	186	slot_ctrl \|= (cmd & mask);
218	ctrl->cmd_busy = 1;	187	ctrl->cmd_busy = 1;
219	smp_mb();	188	smp_mb();
220	retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);	189	pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
221	if (retval)
222	ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
223		190
224	/*	191	/*
225	* Wait for command completion.	192	* Wait for command completion.
226	*/	193	*/
227	if (!retval && !ctrl->no_cmd_complete) {	194	if (!ctrl->no_cmd_complete) {
228	int poll = 0;	195	int poll = 0;
229	/*	196	/*
230	* if hotplug interrupt is not enabled or command	197	* if hotplug interrupt is not enabled or command
@@ -236,19 +203,16 @@ static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) · 5 unmodified lines
236	poll = 1;	203	poll = 1;
237	pcie_wait_cmd(ctrl, poll);	204	pcie_wait_cmd(ctrl, poll);
238	}	205	}
239	out:
240	mutex_unlock(&ctrl->ctrl_lock);	206	mutex_unlock(&ctrl->ctrl_lock);
241	return retval;
242	}	207	}
243		208
244	static bool check_link_active(struct controller *ctrl)	209	static bool check_link_active(struct controller *ctrl)
245	{	210	{
246	bool ret = false;	211	struct pci_dev *pdev = ctrl_dev(ctrl);
247	u16 lnk_status;	212	u16 lnk_status;
		213	bool ret;
248		214
249	if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status))	215	pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
250	return ret;
251
252	ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);	216	ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
253		217
254	if (ret)	218	if (ret)
@@ -311,9 +275,9 @@ static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) · 56 unmodified lines
311		275
312	int pciehp_check_link_status(struct controller *ctrl)	276	int pciehp_check_link_status(struct controller *ctrl)
313	{	277	{
		278	struct pci_dev *pdev = ctrl_dev(ctrl);
		279	bool found;
314	u16 lnk_status;	280	u16 lnk_status;
315	int retval = 0;
316	bool found = false;
317		281
318	/*	282	/*
319	* Data Link Layer Link Active Reporting must be capable for	283	* Data Link Layer Link Active Reporting must be capable for
@@ -330,52 +294,37 @@ int pciehp_check_link_status(struct controller *ctrl) · 10 unmodified lines
330	found = pci_bus_check_dev(ctrl->pcie->port->subordinate,	294	found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
331	PCI_DEVFN(0, 0));	295	PCI_DEVFN(0, 0));
332		296
333	retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);	297	pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
334	if (retval) {
335	ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
336	return retval;
337	}
338
339	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);	298	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
340	if ((lnk_status & PCI_EXP_LNKSTA_LT) \|\|	299	if ((lnk_status & PCI_EXP_LNKSTA_LT) \|\|
341	!(lnk_status & PCI_EXP_LNKSTA_NLW)) {	300	!(lnk_status & PCI_EXP_LNKSTA_NLW)) {
342	ctrl_err(ctrl, "Link Training Error occurs \n");	301	ctrl_err(ctrl, "Link Training Error occurs \n");
343	retval = -1;	302	return -1;
344	return retval;
345	}	303	}
346		304
347	pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);	305	pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
348		306
349	if (!found && !retval)	307	if (!found)
350	retval = -1;	308	return -1;
351		309
352	return retval;	310	return 0;
353	}	311	}
354		312
355	static int __pciehp_link_set(struct controller *ctrl, bool enable)	313	static int __pciehp_link_set(struct controller *ctrl, bool enable)
356	{	314	{
		315	struct pci_dev *pdev = ctrl_dev(ctrl);
357	u16 lnk_ctrl;	316	u16 lnk_ctrl;
358	int retval = 0;
359		317
360	retval = pciehp_readw(ctrl, PCI_EXP_LNKCTL, &lnk_ctrl);	318	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
361	if (retval) {
362	ctrl_err(ctrl, "Cannot read LNKCTRL register\n");
363	return retval;
364	}
365		319
366	if (enable)	320	if (enable)
367	lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;	321	lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
368	else	322	else
369	lnk_ctrl \|= PCI_EXP_LNKCTL_LD;	323	lnk_ctrl \|= PCI_EXP_LNKCTL_LD;
370		324
371	retval = pciehp_writew(ctrl, PCI_EXP_LNKCTL, lnk_ctrl);	325	pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
372	if (retval) {
373	ctrl_err(ctrl, "Cannot write LNKCTRL register\n");
374	return retval;
375	}
376	ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);	326	ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
377		327	return 0;
378	return retval;
379	}	328	}
380		329
381	static int pciehp_link_enable(struct controller *ctrl)	330	static int pciehp_link_enable(struct controller *ctrl)
@@ -388,223 +337,165 @@ static int pciehp_link_disable(struct controller *ctrl) · 6 unmodified lines
388	return __pciehp_link_set(ctrl, false);	337	return __pciehp_link_set(ctrl, false);
389	}	338	}
390		339
391	int pciehp_get_attention_status(struct slot slot, u8 status)	340	void pciehp_get_attention_status(struct slot slot, u8 status)
392	{	341	{
393	struct controller *ctrl = slot->ctrl;	342	struct controller *ctrl = slot->ctrl;
		343	struct pci_dev *pdev = ctrl_dev(ctrl);
394	u16 slot_ctrl;	344	u16 slot_ctrl;
395	u8 atten_led_state;
396	int retval = 0;
397
398	retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
399	if (retval) {
400	ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
401	return retval;
402	}
403		345
		346	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
404	ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,	347	ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
405	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);	348	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
406		349
407	atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;	350	switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
408		351	case PCI_EXP_SLTCTL_ATTN_IND_ON:
409	switch (atten_led_state) {
410	case 0:
411	status = 0xFF; / Reserved */
412	break;
413	case 1:
414	status = 1; / On */	352	status = 1; / On */
415	break;	353	break;
416	case 2:	354	case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
417	status = 2; / Blink */	355	status = 2; / Blink */
418	break;	356	break;
419	case 3:	357	case PCI_EXP_SLTCTL_ATTN_IND_OFF:
420	status = 0; / Off */	358	status = 0; / Off */
421	break;	359	break;
422	default:	360	default:
423	*status = 0xFF;	361	*status = 0xFF;
424	break;	362	break;
425	}	363	}
426
427	return 0;
428	}	364	}
429		365
430	int pciehp_get_power_status(struct slot slot, u8 status)	366	void pciehp_get_power_status(struct slot slot, u8 status)
431	{	367	{
432	struct controller *ctrl = slot->ctrl;	368	struct controller *ctrl = slot->ctrl;
		369	struct pci_dev *pdev = ctrl_dev(ctrl);
433	u16 slot_ctrl;	370	u16 slot_ctrl;
434	u8 pwr_state;
435	int retval = 0;
436		371
437	retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);	372	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
438	if (retval) {
439	ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
440	return retval;
441	}
442	ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,	373	ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
443	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);	374	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
444		375
445	pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;	376	switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
446		377	case PCI_EXP_SLTCTL_PWR_ON:
447	switch (pwr_state) {	378	status = 1; / On */
448	case 0:
449	*status = 1;
450	break;	379	break;
451	case 1:	380	case PCI_EXP_SLTCTL_PWR_OFF:
452	*status = 0;	381	status = 0; / Off */
453	break;	382	break;
454	default:	383	default:
455	*status = 0xFF;	384	*status = 0xFF;
456	break;	385	break;
457	}	386	}
458
459	return retval;
460	}	387	}
461		388
462	int pciehp_get_latch_status(struct slot slot, u8 status)	389	void pciehp_get_latch_status(struct slot slot, u8 status)
463	{	390	{
464	struct controller *ctrl = slot->ctrl;	391	struct pci_dev *pdev = ctrl_dev(slot->ctrl);
465	u16 slot_status;	392	u16 slot_status;
466	int retval;
467		393
468	retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);	394	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
469	if (retval) {
470	ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
471	__func__);
472	return retval;
473	}
474	*status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);	395	*status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
475	return 0;
476	}	396	}
477		397
478	int pciehp_get_adapter_status(struct slot slot, u8 status)	398	void pciehp_get_adapter_status(struct slot slot, u8 status)
479	{	399	{
480	struct controller *ctrl = slot->ctrl;	400	struct pci_dev *pdev = ctrl_dev(slot->ctrl);
481	u16 slot_status;	401	u16 slot_status;
482	int retval;
483		402
484	retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);	403	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
485	if (retval) {
486	ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
487	__func__);
488	return retval;
489	}
490	*status = !!(slot_status & PCI_EXP_SLTSTA_PDS);	404	*status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
491	return 0;
492	}	405	}
493		406
494	int pciehp_query_power_fault(struct slot *slot)	407	int pciehp_query_power_fault(struct slot *slot)
495	{	408	{
496	struct controller *ctrl = slot->ctrl;	409	struct pci_dev *pdev = ctrl_dev(slot->ctrl);
497	u16 slot_status;	410	u16 slot_status;
498	int retval;
499		411
500	retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);	412	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
501	if (retval) {
502	ctrl_err(ctrl, "Cannot check for power fault\n");
503	return retval;
504	}
505	return !!(slot_status & PCI_EXP_SLTSTA_PFD);	413	return !!(slot_status & PCI_EXP_SLTSTA_PFD);
506	}	414	}
507		415
508	int pciehp_set_attention_status(struct slot *slot, u8 value)	416	void pciehp_set_attention_status(struct slot *slot, u8 value)
509	{	417	{
510	struct controller *ctrl = slot->ctrl;	418	struct controller *ctrl = slot->ctrl;
511	u16 slot_cmd;	419	u16 slot_cmd;
512	u16 cmd_mask;
513		420
514	cmd_mask = PCI_EXP_SLTCTL_AIC;	421	if (!ATTN_LED(ctrl))
		422	return;
		423
515	switch (value) {	424	switch (value) {
516	case 0 : /* turn off */	425	case 0 : /* turn off */
517	slot_cmd = 0x00C0;	426	slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
518	break;	427	break;
519	case 1: /* turn on */	428	case 1: /* turn on */
520	slot_cmd = 0x0040;	429	slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
521	break;	430	break;
522	case 2: /* turn blink */	431	case 2: /* turn blink */
523	slot_cmd = 0x0080;	432	slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
524	break;	433	break;
525	default:	434	default:
526	return -EINVAL;	435	return;
527	}	436	}
528	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,	437	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
529	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);	438	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
530	return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);	439	pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
531	}	440	}
532		441
533	void pciehp_green_led_on(struct slot *slot)	442	void pciehp_green_led_on(struct slot *slot)
534	{	443	{
535	struct controller *ctrl = slot->ctrl;	444	struct controller *ctrl = slot->ctrl;
536	u16 slot_cmd;
537	u16 cmd_mask;
538		445
539	slot_cmd = 0x0100;	446	if (!PWR_LED(ctrl))
540	cmd_mask = PCI_EXP_SLTCTL_PIC;	447	return;
541	pcie_write_cmd(ctrl, slot_cmd, cmd_mask);	448
		449	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC);
542	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,	450	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
543	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);	451	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
		452	PCI_EXP_SLTCTL_PWR_IND_ON);
544	}	453	}
545		454
546	void pciehp_green_led_off(struct slot *slot)	455	void pciehp_green_led_off(struct slot *slot)
547	{	456	{
548	struct controller *ctrl = slot->ctrl;	457	struct controller *ctrl = slot->ctrl;
549	u16 slot_cmd;
550	u16 cmd_mask;
551		458
552	slot_cmd = 0x0300;	459	if (!PWR_LED(ctrl))
553	cmd_mask = PCI_EXP_SLTCTL_PIC;	460	return;
554	pcie_write_cmd(ctrl, slot_cmd, cmd_mask);	461
		462	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC);
555	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,	463	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
556	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);	464	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
		465	PCI_EXP_SLTCTL_PWR_IND_OFF);
557	}	466	}
558		467
559	void pciehp_green_led_blink(struct slot *slot)	468	void pciehp_green_led_blink(struct slot *slot)
560	{	469	{
561	struct controller *ctrl = slot->ctrl;	470	struct controller *ctrl = slot->ctrl;
562	u16 slot_cmd;
563	u16 cmd_mask;
564		471
565	slot_cmd = 0x0200;	472	if (!PWR_LED(ctrl))
566	cmd_mask = PCI_EXP_SLTCTL_PIC;	473	return;
567	pcie_write_cmd(ctrl, slot_cmd, cmd_mask);	474
		475	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC);
568	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,	476	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
569	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);	477	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
		478	PCI_EXP_SLTCTL_PWR_IND_BLINK);
570	}	479	}
571		480
572	int pciehp_power_on_slot(struct slot * slot)	481	int pciehp_power_on_slot(struct slot * slot)
573	{	482	{
574	struct controller *ctrl = slot->ctrl;	483	struct controller *ctrl = slot->ctrl;
575	u16 slot_cmd;	484	struct pci_dev *pdev = ctrl_dev(ctrl);
576	u16 cmd_mask;
577	u16 slot_status;	485	u16 slot_status;
578	int retval = 0;	486	int retval;
579		487
580	/* Clear sticky power-fault bit from previous power failures */	488	/* Clear sticky power-fault bit from previous power failures */
581	retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);	489	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
582	if (retval) {	490	if (slot_status & PCI_EXP_SLTSTA_PFD)
583	ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",	491	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
584	__func__);	492	PCI_EXP_SLTSTA_PFD);
585	return retval;
586	}
587	slot_status &= PCI_EXP_SLTSTA_PFD;
588	if (slot_status) {
589	retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
590	if (retval) {
591	ctrl_err(ctrl,
592	"%s: Cannot write to SLOTSTATUS register\n",
593	__func__);
594	return retval;
595	}
596	}
597	ctrl->power_fault_detected = 0;	493	ctrl->power_fault_detected = 0;
598		494
599	slot_cmd = POWER_ON;	495	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
600	cmd_mask = PCI_EXP_SLTCTL_PCC;
601	retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
602	if (retval) {
603	ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
604	return retval;
605	}
606	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,	496	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
607	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);	497	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
		498	PCI_EXP_SLTCTL_PWR_ON);
608		499
609	retval = pciehp_link_enable(ctrl);	500	retval = pciehp_link_enable(ctrl);
610	if (retval)	501	if (retval)
@@ -613,12 +504,9 @@ int pciehp_power_on_slot(struct slot * slot) · 2 unmodified lines
613	return retval;	504	return retval;
614	}	505	}
615		506
616	int pciehp_power_off_slot(struct slot * slot)	507	void pciehp_power_off_slot(struct slot * slot)
617	{	508	{
618	struct controller *ctrl = slot->ctrl;	509	struct controller *ctrl = slot->ctrl;
619	u16 slot_cmd;
620	u16 cmd_mask;
621	int retval;
622		510
623	/* Disable the link at first */	511	/* Disable the link at first */
624	pciehp_link_disable(ctrl);	512	pciehp_link_disable(ctrl);
@@ -628,21 +516,16 @@ int pciehp_power_off_slot(struct slot * slot) · 3 unmodified lines
628	else	516	else
629	msleep(1000);	517	msleep(1000);
630		518
631	slot_cmd = POWER_OFF;	519	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
632	cmd_mask = PCI_EXP_SLTCTL_PCC;
633	retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
634	if (retval) {
635	ctrl_err(ctrl, "Write command failed!\n");
636	return retval;
637	}
638	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,	520	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
639	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);	521	pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
640	return 0;	522	PCI_EXP_SLTCTL_PWR_OFF);
641	}	523	}
642		524
643	static irqreturn_t pcie_isr(int irq, void *dev_id)	525	static irqreturn_t pcie_isr(int irq, void *dev_id)
644	{	526	{
645	struct controller ctrl = (struct controller )dev_id;	527	struct controller ctrl = (struct controller )dev_id;
		528	struct pci_dev *pdev = ctrl_dev(ctrl);
646	struct slot *slot = ctrl->slot;	529	struct slot *slot = ctrl->slot;
647	u16 detected, intr_loc;	530	u16 detected, intr_loc;
648		531
@@ -653,11 +536,7 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) · 4 unmodified lines
653	*/	536	*/
654	intr_loc = 0;	537	intr_loc = 0;
655	do {	538	do {
656	if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {	539	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
657	ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
658	__func__);
659	return IRQ_NONE;
660	}
661		540
662	detected &= (PCI_EXP_SLTSTA_ABP \| PCI_EXP_SLTSTA_PFD \|	541	detected &= (PCI_EXP_SLTSTA_ABP \| PCI_EXP_SLTSTA_PFD \|
663	PCI_EXP_SLTSTA_MRLSC \| PCI_EXP_SLTSTA_PDC \|	542	PCI_EXP_SLTSTA_MRLSC \| PCI_EXP_SLTSTA_PDC \|
@@ -666,11 +545,9 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) · 2 unmodified lines
666	intr_loc \|= detected;	545	intr_loc \|= detected;
667	if (!intr_loc)	546	if (!intr_loc)
668	return IRQ_NONE;	547	return IRQ_NONE;
669	if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {	548	if (detected)
670	ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",	549	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
671	__func__);	550	intr_loc);
672	return IRQ_NONE;
673	}
674	} while (detected);	551	} while (detected);
675		552
676	ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);	553	ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
@@ -705,7 +582,7 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) · 28 unmodified lines
705	return IRQ_HANDLED;	582	return IRQ_HANDLED;
706	}	583	}
707		584
708	int pcie_enable_notification(struct controller *ctrl)	585	void pcie_enable_notification(struct controller *ctrl)
709	{	586	{
710	u16 cmd, mask;	587	u16 cmd, mask;
711		588
@@ -731,22 +608,18 @@ int pcie_enable_notification(struct controller *ctrl) · 19 unmodified lines
731	PCI_EXP_SLTCTL_MRLSCE \| PCI_EXP_SLTCTL_PFDE \|	608	PCI_EXP_SLTCTL_MRLSCE \| PCI_EXP_SLTCTL_PFDE \|
732	PCI_EXP_SLTCTL_HPIE \| PCI_EXP_SLTCTL_CCIE);	609	PCI_EXP_SLTCTL_HPIE \| PCI_EXP_SLTCTL_CCIE);
733		610
734	if (pcie_write_cmd(ctrl, cmd, mask)) {	611	pcie_write_cmd(ctrl, cmd, mask);
735	ctrl_err(ctrl, "Cannot enable software notification\n");
736	return -1;
737	}
738	return 0;
739	}	612	}
740		613
741	static void pcie_disable_notification(struct controller *ctrl)	614	static void pcie_disable_notification(struct controller *ctrl)
742	{	615	{
743	u16 mask;	616	u16 mask;
		617
744	mask = (PCI_EXP_SLTCTL_PDCE \| PCI_EXP_SLTCTL_ABPE \|	618	mask = (PCI_EXP_SLTCTL_PDCE \| PCI_EXP_SLTCTL_ABPE \|
745	PCI_EXP_SLTCTL_MRLSCE \| PCI_EXP_SLTCTL_PFDE \|	619	PCI_EXP_SLTCTL_MRLSCE \| PCI_EXP_SLTCTL_PFDE \|
746	PCI_EXP_SLTCTL_HPIE \| PCI_EXP_SLTCTL_CCIE \|	620	PCI_EXP_SLTCTL_HPIE \| PCI_EXP_SLTCTL_CCIE \|
747	PCI_EXP_SLTCTL_DLLSCE);	621	PCI_EXP_SLTCTL_DLLSCE);
748	if (pcie_write_cmd(ctrl, 0, mask))	622	pcie_write_cmd(ctrl, 0, mask);
749	ctrl_warn(ctrl, "Cannot disable software notification\n");
750	}	623	}
751		624
752	/*	625	/*
@@ -758,6 +631,7 @@ static void pcie_disable_notification(struct controller *ctrl) · 5 unmodified lines
758	int pciehp_reset_slot(struct slot *slot, int probe)	631	int pciehp_reset_slot(struct slot *slot, int probe)
759	{	632	{
760	struct controller *ctrl = slot->ctrl;	633	struct controller *ctrl = slot->ctrl;
		634	struct pci_dev *pdev = ctrl_dev(ctrl);
761		635
762	if (probe)	636	if (probe)
763	return 0;	637	return 0;
@@ -771,7 +645,8 @@ int pciehp_reset_slot(struct slot *slot, int probe) · 7 unmodified lines
771	pci_reset_bridge_secondary_bus(ctrl->pcie->port);	645	pci_reset_bridge_secondary_bus(ctrl->pcie->port);
772		646
773	if (HP_SUPR_RM(ctrl)) {	647	if (HP_SUPR_RM(ctrl)) {
774	pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_PDC);	648	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
		649	PCI_EXP_SLTSTA_PDC);
775	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE);	650	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE);
776	if (pciehp_poll_mode)	651	if (pciehp_poll_mode)
777	int_poll_timeout(ctrl->poll_timer.data);	652	int_poll_timeout(ctrl->poll_timer.data);
@@ -784,10 +659,7 @@ int pcie_init_notification(struct controller *ctrl) · 6 unmodified lines
784	{	659	{
785	if (pciehp_request_irq(ctrl))	660	if (pciehp_request_irq(ctrl))
786	return -1;	661	return -1;
787	if (pcie_enable_notification(ctrl)) {	662	pcie_enable_notification(ctrl);
788	pciehp_free_irq(ctrl);
789	return -1;
790	}
791	ctrl->notification_enabled = 1;	663	ctrl->notification_enabled = 1;
792	return 0;	664	return 0;
793	}	665	}
@@ -875,12 +747,14 @@ static inline void dbg_ctrl(struct controller *ctrl) · 81 unmodified lines
875	EMI(ctrl) ? "yes" : "no");	747	EMI(ctrl) ? "yes" : "no");
876	ctrl_info(ctrl, " Command Completed : %3s\n",	748	ctrl_info(ctrl, " Command Completed : %3s\n",
877	NO_CMD_CMPL(ctrl) ? "no" : "yes");	749	NO_CMD_CMPL(ctrl) ? "no" : "yes");
878	pciehp_readw(ctrl, PCI_EXP_SLTSTA, &reg16);	750	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
879	ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);	751	ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
880	pciehp_readw(ctrl, PCI_EXP_SLTCTL, &reg16);	752	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
881	ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);	753	ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
882	}	754	}
883		755
		756	#define FLAG(x,y) (((x) & (y)) ? '+' : '-')
		757
884	struct controller pcie_init(struct pcie_device dev)	758	struct controller pcie_init(struct pcie_device dev)
885	{	759	{
886	struct controller *ctrl;	760	struct controller *ctrl;
@@ -893,11 +767,7 @@ struct controller pcie_init(struct pcie_device dev) · 6 unmodified lines
893	goto abort;	767	goto abort;
894	}	768	}
895	ctrl->pcie = dev;	769	ctrl->pcie = dev;
896	if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {	770	pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
897	ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
898	goto abort_ctrl;
899	}
900
901	ctrl->slot_cap = slot_cap;	771	ctrl->slot_cap = slot_cap;
902	mutex_init(&ctrl->ctrl_lock);	772	mutex_init(&ctrl->ctrl_lock);
903	init_waitqueue_head(&ctrl->queue);	773	init_waitqueue_head(&ctrl->queue);
@@ -913,25 +783,31 @@ struct controller pcie_init(struct pcie_device dev) · 9 unmodified lines
913	ctrl->no_cmd_complete = 1;	783	ctrl->no_cmd_complete = 1;
914		784
915	/* Check if Data Link Layer Link Active Reporting is implemented */	785	/* Check if Data Link Layer Link Active Reporting is implemented */
916	if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {	786	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
917	ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
918	goto abort_ctrl;
919	}
920	if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {	787	if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
921	ctrl_dbg(ctrl, "Link Active Reporting supported\n");	788	ctrl_dbg(ctrl, "Link Active Reporting supported\n");
922	ctrl->link_active_reporting = 1;	789	ctrl->link_active_reporting = 1;
923	}	790	}
924		791
925	/* Clear all remaining event bits in Slot Status register */	792	/* Clear all remaining event bits in Slot Status register */
926	if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))	793	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
927	goto abort_ctrl;	794	PCI_EXP_SLTSTA_ABP \| PCI_EXP_SLTSTA_PFD \|
		795	PCI_EXP_SLTSTA_MRLSC \| PCI_EXP_SLTSTA_PDC \|
		796	PCI_EXP_SLTSTA_CC);
928		797
929	/* Disable software notification */	798	/* Disable software notification */
930	pcie_disable_notification(ctrl);	799	pcie_disable_notification(ctrl);
931		800
932	ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",	801	ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n",
933	pdev->vendor, pdev->device, pdev->subsystem_vendor,	802	(slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
934	pdev->subsystem_device);	803	FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
		804	FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
		805	FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
		806	FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
		807	FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
		808	FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
		809	FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
		810	FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
935		811
936	if (pcie_init_slot(ctrl))	812	if (pcie_init_slot(ctrl))
937	goto abort_ctrl;	813	goto abort_ctrl;

drivers/pci/hotplug/pciehp_pci.c+15−8

@@ -39,22 +39,26 @@ int pciehp_configure_device(struct slot *p_slot) · 38 unmodified lines
39	struct pci_dev *dev;	39	struct pci_dev *dev;
40	struct pci_dev *bridge = p_slot->ctrl->pcie->port;	40	struct pci_dev *bridge = p_slot->ctrl->pcie->port;
41	struct pci_bus *parent = bridge->subordinate;	41	struct pci_bus *parent = bridge->subordinate;
42	int num;	42	int num, ret = 0;
43	struct controller *ctrl = p_slot->ctrl;	43	struct controller *ctrl = p_slot->ctrl;
44		44
		45	pci_lock_rescan_remove();
		46
45	dev = pci_get_slot(parent, PCI_DEVFN(0, 0));	47	dev = pci_get_slot(parent, PCI_DEVFN(0, 0));
46	if (dev) {	48	if (dev) {
47	ctrl_err(ctrl, "Device %s already exists "	49	ctrl_err(ctrl, "Device %s already exists "
48	"at %04x:%02x:00, cannot hot-add\n", pci_name(dev),	50	"at %04x:%02x:00, cannot hot-add\n", pci_name(dev),
49	pci_domain_nr(parent), parent->number);	51	pci_domain_nr(parent), parent->number);
50	pci_dev_put(dev);	52	pci_dev_put(dev);
51	return -EINVAL;	53	ret = -EINVAL;
		54	goto out;
52	}	55	}
53		56
54	num = pci_scan_slot(parent, PCI_DEVFN(0, 0));	57	num = pci_scan_slot(parent, PCI_DEVFN(0, 0));
55	if (num == 0) {	58	if (num == 0) {
56	ctrl_err(ctrl, "No new device found\n");	59	ctrl_err(ctrl, "No new device found\n");
57	return -ENODEV;	60	ret = -ENODEV;
		61	goto out;
58	}	62	}
59		63
60	list_for_each_entry(dev, &parent->devices, bus_list)	64	list_for_each_entry(dev, &parent->devices, bus_list)
@@ -73,12 +77,14 @@ int pciehp_configure_device(struct slot *p_slot) · 12 unmodified lines
73		77
74	pci_bus_add_devices(parent);	78	pci_bus_add_devices(parent);
75		79
76	return 0;	80	out:
		81	pci_unlock_rescan_remove();
		82	return ret;
77	}	83	}
78		84
79	int pciehp_unconfigure_device(struct slot *p_slot)	85	int pciehp_unconfigure_device(struct slot *p_slot)
80	{	86	{
81	int ret, rc = 0;	87	int rc = 0;
82	u8 bctl = 0;	88	u8 bctl = 0;
83	u8 presence = 0;	89	u8 presence = 0;
84	struct pci_dev dev, temp;	90	struct pci_dev dev, temp;
@@ -88,9 +94,9 @@ int pciehp_unconfigure_device(struct slot *p_slot) · 3 unmodified lines
88		94
89	ctrl_dbg(ctrl, "%s: domain:bus:dev = %04x:%02x:00\n",	95	ctrl_dbg(ctrl, "%s: domain:bus:dev = %04x:%02x:00\n",
90	__func__, pci_domain_nr(parent), parent->number);	96	__func__, pci_domain_nr(parent), parent->number);
91	ret = pciehp_get_adapter_status(p_slot, &presence);	97	pciehp_get_adapter_status(p_slot, &presence);
92	if (ret)	98
93	presence = 0;	99	pci_lock_rescan_remove();
94		100
95	/*	101	/*
96	* Stopping an SR-IOV PF device removes all the associated VFs,	102	* Stopping an SR-IOV PF device removes all the associated VFs,
@@ -126,5 +132,6 @@ int pciehp_unconfigure_device(struct slot *p_slot) · 29 unmodified lines
126	pci_dev_put(dev);	132	pci_dev_put(dev);
127	}	133	}
128		134
		135	pci_unlock_rescan_remove();
129	return rc;	136	return rc;
130	}	137	}

drivers/pci/hotplug/rpadlpar_core.c+14−5

 {
 	struct pci_bus *bus;
 	struct slot *slot;
+	int ret = 0;
+	pci_lock_rescan_remove();
 	bus = pcibios_find_pci_bus(dn);
-	if (!bus)
+	if (!bus) {
-		return -EINVAL;
+		ret = -EINVAL;
+		goto out;
+	}
 	pr_debug("PCI: Removing PCI slot below EADS bridge %s\n",
 		 bus->self ? pci_name(bus->self) : "<!PHB!>");
 			printk(KERN_ERR
 				"%s: unable to remove hotplug slot %s\n",
 				__func__, drc_name);
-			return -EIO;
+			ret = -EIO;
+			goto out;
 		}
 	}
 	if (pcibios_unmap_io_space(bus)) {
 		printk(KERN_ERR "%s: failed to unmap bus range\n",
 			__func__);
-		return -ERANGE;
+		ret = -ERANGE;
+		goto out;
 	}
 	/* Remove the EADS bridge device itself */
 	pr_debug("PCI: Now removing bridge device %s\n", pci_name(bus->self));
 	pci_stop_and_remove_bus_device(bus->self);
-	return 0;
+ out:
+	pci_unlock_rescan_remove();
+	return ret;
 }
 /**

drivers/pci/hotplug/rpaphp_core.c+4−0

 		return retval;
 	if (state == PRESENT) {
+		pci_lock_rescan_remove();
 		pcibios_add_pci_devices(slot->bus);
+		pci_unlock_rescan_remove();
 		slot->state = CONFIGURED;
 	} else if (state == EMPTY) {
 		slot->state = EMPTY;
 	if (slot->state == NOT_CONFIGURED)
 		return -EINVAL;
+	pci_lock_rescan_remove();
 	pcibios_remove_pci_devices(slot->bus);
+	pci_unlock_rescan_remove();
 	vm_unmap_aliases();
 	slot->state = NOT_CONFIGURED;

drivers/pci/hotplug/s390_pci_hpc.c+3−1

 		goto out_deconfigure;
 	pci_scan_slot(slot->zdev->bus, ZPCI_DEVFN);
+	pci_lock_rescan_remove();
 	pci_bus_add_devices(slot->zdev->bus);
+	pci_unlock_rescan_remove();
 	return rc;
 		return -EIO;
 	if (slot->zdev->pdev)
-		pci_stop_and_remove_bus_device(slot->zdev->pdev);
+		pci_stop_and_remove_bus_device_locked(slot->zdev->pdev);
 	rc = zpci_disable_device(slot->zdev);
 	if (rc)

drivers/pci/hotplug/sgi_hotplug.c+5−0

 		acpi_scan_lock_release();
 	}
+	pci_lock_rescan_remove();
 	/* Call the driver for the new device */
 	pci_bus_add_devices(slot->pci_bus);
 	/* Call the drivers for the new devices subordinate to PPB */
 	if (new_ppb)
 		pci_bus_add_devices(new_bus);
+	pci_unlock_rescan_remove();
 	mutex_unlock(&sn_hotplug_mutex);
 	if (rc == 0)
 		acpi_scan_lock_release();
 	}
+	pci_lock_rescan_remove();
 	/* Free the SN resources assigned to the Linux device.*/
 	list_for_each_entry_safe(dev, temp, &slot->pci_bus->devices, bus_list) {
 		if (PCI_SLOT(dev->devfn) != slot->device_num + 1)
 		pci_stop_and_remove_bus_device(dev);
 		pci_dev_put(dev);
 	}
+	pci_unlock_rescan_remove();
 	/* Remove the SSDT for the slot from the ACPI namespace */
 	if (SN_ACPI_BASE_SUPPORT() && ssdt_id) {

drivers/pci/hotplug/shpchp_pci.c+14−4

 	struct controller *ctrl = p_slot->ctrl;
 	struct pci_dev *bridge = ctrl->pci_dev;
 	struct pci_bus *parent = bridge->subordinate;
-	int num;
+	int num, ret = 0;
+	pci_lock_rescan_remove();
 	dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, 0));
 	if (dev) {
 			 "at %04x:%02x:%02x, cannot hot-add\n", pci_name(dev),
 			 pci_domain_nr(parent), p_slot->bus, p_slot->device);
 		pci_dev_put(dev);
-		return -EINVAL;
+		ret = -EINVAL;
+		goto out;
 	}
 	num = pci_scan_slot(parent, PCI_DEVFN(p_slot->device, 0));
 	if (num == 0) {
 		ctrl_err(ctrl, "No new device found\n");
-		return -ENODEV;
+		ret = -ENODEV;
+		goto out;
 	}
 	list_for_each_entry(dev, &parent->devices, bus_list) {
 	pci_bus_add_devices(parent);
-	return 0;
+ out:
+	pci_unlock_rescan_remove();
+	return ret;
 }
 int shpchp_unconfigure_device(struct slot *p_slot)
 	ctrl_dbg(ctrl, "%s: domain:bus:dev = %04x:%02x:%02x\n",
 		 __func__, pci_domain_nr(parent), p_slot->bus, p_slot->device);
+	pci_lock_rescan_remove();
 	list_for_each_entry_safe(dev, temp, &parent->devices, bus_list) {
 		if (PCI_SLOT(dev->devfn) != p_slot->device)
 			continue;
 		pci_stop_and_remove_bus_device(dev);
 		pci_dev_put(dev);
 	}
+	pci_unlock_rescan_remove();
 	return rc;
 }

drivers/pci/ioapic.c+5−1

 	.remove		= ioapic_remove,
 };
-module_pci_driver(ioapic_driver);
+static int __init ioapic_init(void)
+{
+	return pci_register_driver(&ioapic_driver);
+}
+module_init(ioapic_init);
 MODULE_LICENSE("GPL");

drivers/pci/iov.c+2−0

 	virtfn->dev.parent = dev->dev.parent;
 	virtfn->physfn = pci_dev_get(dev);
 	virtfn->is_virtfn = 1;
+	virtfn->multifunction = 0;
 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 		res = dev->resource + PCI_IOV_RESOURCES + i;
 found:
 	pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, ctrl);
+	pci_write_config_word(dev, pos + PCI_SRIOV_NUM_VF, 0);
 	pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
 	pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride);
 	if (!offset || (total > 1 && !stride))

drivers/pci/msi.c+227−121

@@ -116,7 +116,7 @@ void __weak arch_teardown_msi_irqs(struct pci_dev *dev) · 115 unmodified lines
116	return default_teardown_msi_irqs(dev);	116	return default_teardown_msi_irqs(dev);
117	}	117	}
118		118
119	void default_restore_msi_irqs(struct pci_dev *dev, int irq)	119	static void default_restore_msi_irq(struct pci_dev *dev, int irq)
120	{	120	{
121	struct msi_desc *entry;	121	struct msi_desc *entry;
122		122
@@ -134,9 +134,9 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq) · 11 unmodified lines
134	write_msi_msg(irq, &entry->msg);	134	write_msi_msg(irq, &entry->msg);
135	}	135	}
136		136
137	void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq)	137	void __weak arch_restore_msi_irqs(struct pci_dev *dev)
138	{	138	{
139	return default_restore_msi_irqs(dev, irq);	139	return default_restore_msi_irqs(dev);
140	}	140	}
141		141
142	static void msi_set_enable(struct pci_dev *dev, int enable)	142	static void msi_set_enable(struct pci_dev *dev, int enable)
@@ -262,6 +262,15 @@ void unmask_msi_irq(struct irq_data *data) · 119 unmodified lines
262	msi_set_mask_bit(data, 0);	262	msi_set_mask_bit(data, 0);
263	}	263	}
264		264
		265	void default_restore_msi_irqs(struct pci_dev *dev)
		266	{
		267	struct msi_desc *entry;
		268
		269	list_for_each_entry(entry, &dev->msi_list, list) {
		270	default_restore_msi_irq(dev, entry->irq);
		271	}
		272	}
		273
265	void __read_msi_msg(struct msi_desc entry, struct msi_msg msg)	274	void __read_msi_msg(struct msi_desc entry, struct msi_msg msg)
266	{	275	{
267	BUG_ON(entry->dev->current_state != PCI_D0);	276	BUG_ON(entry->dev->current_state != PCI_D0);
@@ -363,6 +372,9 @@ void write_msi_msg(unsigned int irq, struct msi_msg *msg) · 95 unmodified lines
363	static void free_msi_irqs(struct pci_dev *dev)	372	static void free_msi_irqs(struct pci_dev *dev)
364	{	373	{
365	struct msi_desc entry, tmp;	374	struct msi_desc entry, tmp;
		375	struct attribute **msi_attrs;
		376	struct device_attribute *dev_attr;
		377	int count = 0;
366		378
367	list_for_each_entry(entry, &dev->msi_list, list) {	379	list_for_each_entry(entry, &dev->msi_list, list) {
368	int i, nvec;	380	int i, nvec;
@@ -398,6 +410,22 @@ static void free_msi_irqs(struct pci_dev *dev) · 29 unmodified lines
398	list_del(&entry->list);	410	list_del(&entry->list);
399	kfree(entry);	411	kfree(entry);
400	}	412	}
		413
		414	if (dev->msi_irq_groups) {
		415	sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
		416	msi_attrs = dev->msi_irq_groups[0]->attrs;
		417	list_for_each_entry(entry, &dev->msi_list, list) {
		418	dev_attr = container_of(msi_attrs[count],
		419	struct device_attribute, attr);
		420	kfree(dev_attr->attr.name);
		421	kfree(dev_attr);
		422	++count;
		423	}
		424	kfree(msi_attrs);
		425	kfree(dev->msi_irq_groups[0]);
		426	kfree(dev->msi_irq_groups);
		427	dev->msi_irq_groups = NULL;
		428	}
401	}	429	}
402		430
403	static struct msi_desc alloc_msi_entry(struct pci_dev dev)	431	static struct msi_desc alloc_msi_entry(struct pci_dev dev)
@@ -430,7 +458,7 @@ static void __pci_restore_msi_state(struct pci_dev *dev) · 26 unmodified lines
430		458
431	pci_intx_for_msi(dev, 0);	459	pci_intx_for_msi(dev, 0);
432	msi_set_enable(dev, 0);	460	msi_set_enable(dev, 0);
433	arch_restore_msi_irqs(dev, dev->irq);	461	arch_restore_msi_irqs(dev);
434		462
435	pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);	463	pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
436	msi_mask_irq(entry, msi_capable_mask(control), entry->masked);	464	msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
@@ -455,8 +483,8 @@ static void __pci_restore_msix_state(struct pci_dev *dev) · 18 unmodified lines
455	control \|= PCI_MSIX_FLAGS_ENABLE \| PCI_MSIX_FLAGS_MASKALL;	483	control \|= PCI_MSIX_FLAGS_ENABLE \| PCI_MSIX_FLAGS_MASKALL;
456	pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);	484	pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
457		485
		486	arch_restore_msi_irqs(dev);
458	list_for_each_entry(entry, &dev->msi_list, list) {	487	list_for_each_entry(entry, &dev->msi_list, list) {
459	arch_restore_msi_irqs(dev, entry->irq);
460	msix_mask_irq(entry, entry->masked);	488	msix_mask_irq(entry, entry->masked);
461	}	489	}
462		490
@@ -471,94 +499,95 @@ void pci_restore_msi_state(struct pci_dev *dev) · 8 unmodified lines
471	}	499	}
472	EXPORT_SYMBOL_GPL(pci_restore_msi_state);	500	EXPORT_SYMBOL_GPL(pci_restore_msi_state);
473		501
474		502	static ssize_t msi_mode_show(struct device dev, struct device_attribute attr,
475	#define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr)
476	#define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj)
477
478	struct msi_attribute {
479	struct attribute attr;
480	ssize_t (show)(struct msi_desc entry, struct msi_attribute *attr,
481	char *buf);
482	ssize_t (store)(struct msi_desc entry, struct msi_attribute *attr,
483	const char *buf, size_t count);
484	};
485
486	static ssize_t show_msi_mode(struct msi_desc entry, struct msi_attribute atr,
487	char *buf)	503	char *buf)
488	{	504	{
489	return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi");	505	struct pci_dev *pdev = to_pci_dev(dev);
490	}	506	struct msi_desc *entry;
491		507	unsigned long irq;
492	static ssize_t msi_irq_attr_show(struct kobject *kobj,	508	int retval;
493	struct attribute attr, char buf)
494	{
495	struct msi_attribute *attribute = to_msi_attr(attr);
496	struct msi_desc *entry = to_msi_desc(kobj);
497
498	if (!attribute->show)
499	return -EIO;
500
501	return attribute->show(entry, attribute, buf);
502	}
503
504	static const struct sysfs_ops msi_irq_sysfs_ops = {
505	.show = msi_irq_attr_show,
506	};
507
508	static struct msi_attribute mode_attribute =
509	__ATTR(mode, S_IRUGO, show_msi_mode, NULL);
510
511		509
512	static struct attribute *msi_irq_default_attrs[] = {	510	retval = kstrtoul(attr->attr.name, 10, &irq);
513	&mode_attribute.attr,	511	if (retval)
514	NULL	512	return retval;
515	};
516		513
517	static void msi_kobj_release(struct kobject *kobj)	514	list_for_each_entry(entry, &pdev->msi_list, list) {
518	{	515	if (entry->irq == irq) {
519	struct msi_desc *entry = to_msi_desc(kobj);	516	return sprintf(buf, "%s\n",
520		517	entry->msi_attrib.is_msix ? "msix" : "msi");
521	pci_dev_put(entry->dev);	518	}
		519	}
		520	return -ENODEV;
522	}	521	}
523		522
524	static struct kobj_type msi_irq_ktype = {
525	.release = msi_kobj_release,
526	.sysfs_ops = &msi_irq_sysfs_ops,
527	.default_attrs = msi_irq_default_attrs,
528	};
529
530	static int populate_msi_sysfs(struct pci_dev *pdev)	523	static int populate_msi_sysfs(struct pci_dev *pdev)
531	{	524	{
		525	struct attribute **msi_attrs;
		526	struct attribute *msi_attr;
		527	struct device_attribute *msi_dev_attr;
		528	struct attribute_group *msi_irq_group;
		529	const struct attribute_group **msi_irq_groups;
532	struct msi_desc *entry;	530	struct msi_desc *entry;
533	struct kobject *kobj;	531	int ret = -ENOMEM;
534	int ret;	532	int num_msi = 0;
535	int count = 0;	533	int count = 0;
536		534
537	pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj);	535	/* Determine how many msi entries we have */
538	if (!pdev->msi_kset)	536	list_for_each_entry(entry, &pdev->msi_list, list) {
539	return -ENOMEM;	537	++num_msi;
		538	}
		539	if (!num_msi)
		540	return 0;
540		541
		542	/* Dynamically create the MSI attributes for the PCI device */
		543	msi_attrs = kzalloc(sizeof(void ) (num_msi + 1), GFP_KERNEL);
		544	if (!msi_attrs)
		545	return -ENOMEM;
541	list_for_each_entry(entry, &pdev->msi_list, list) {	546	list_for_each_entry(entry, &pdev->msi_list, list) {
542	kobj = &entry->kobj;	547	char *name = kmalloc(20, GFP_KERNEL);
543	kobj->kset = pdev->msi_kset;	548	msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
544	pci_dev_get(pdev);	549	if (!msi_dev_attr)
545	ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL,	550	goto error_attrs;
546	"%u", entry->irq);	551	sprintf(name, "%d", entry->irq);
547	if (ret)	552	sysfs_attr_init(&msi_dev_attr->attr);
548	goto out_unroll;	553	msi_dev_attr->attr.name = name;
549		554	msi_dev_attr->attr.mode = S_IRUGO;
550	count++;	555	msi_dev_attr->show = msi_mode_show;
		556	msi_attrs[count] = &msi_dev_attr->attr;
		557	++count;
551	}	558	}
552		559
		560	msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
		561	if (!msi_irq_group)
		562	goto error_attrs;
		563	msi_irq_group->name = "msi_irqs";
		564	msi_irq_group->attrs = msi_attrs;
		565
		566	msi_irq_groups = kzalloc(sizeof(void ) 2, GFP_KERNEL);
		567	if (!msi_irq_groups)
		568	goto error_irq_group;
		569	msi_irq_groups[0] = msi_irq_group;
		570
		571	ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
		572	if (ret)
		573	goto error_irq_groups;
		574	pdev->msi_irq_groups = msi_irq_groups;
		575
553	return 0;	576	return 0;
554		577
555	out_unroll:	578	error_irq_groups:
556	list_for_each_entry(entry, &pdev->msi_list, list) {	579	kfree(msi_irq_groups);
557	if (!count)	580	error_irq_group:
558	break;	581	kfree(msi_irq_group);
559	kobject_del(&entry->kobj);	582	error_attrs:
560	kobject_put(&entry->kobj);	583	count = 0;
561	count--;	584	msi_attr = msi_attrs[count];
		585	while (msi_attr) {
		586	msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
		587	kfree(msi_attr->name);
		588	kfree(msi_dev_attr);
		589	++count;
		590	msi_attr = msi_attrs[count];
562	}	591	}
563	return ret;	592	return ret;
564	}	593	}
@@ -729,7 +758,7 @@ static int msix_capability_init(struct pci_dev *dev, · 164 unmodified lines
729		758
730	ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);	759	ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
731	if (ret)	760	if (ret)
732	goto error;	761	goto out_avail;
733		762
734	/*	763	/*
735	* Some devices require MSI-X to be enabled before we can touch the	764	* Some devices require MSI-X to be enabled before we can touch the
@@ -742,10 +771,8 @@ static int msix_capability_init(struct pci_dev *dev, · 6 unmodified lines
742	msix_program_entries(dev, entries);	771	msix_program_entries(dev, entries);
743		772
744	ret = populate_msi_sysfs(dev);	773	ret = populate_msi_sysfs(dev);
745	if (ret) {	774	if (ret)
746	ret = 0;	775	goto out_free;
747	goto error;
748	}
749		776
750	/* Set MSI-X enabled bits and unmask the function */	777	/* Set MSI-X enabled bits and unmask the function */
751	pci_intx_for_msi(dev, 0);	778	pci_intx_for_msi(dev, 0);
@@ -756,7 +783,7 @@ static int msix_capability_init(struct pci_dev *dev, · 4 unmodified lines
756		783
757	return 0;	784	return 0;
758		785
759	error:	786	out_avail:
760	if (ret < 0) {	787	if (ret < 0) {
761	/*	788	/*
762	* If we had some success, report the number of irqs	789	* If we had some success, report the number of irqs
@@ -773,6 +800,7 @@ error: · 10 unmodified lines
773	ret = avail;	800	ret = avail;
774	}	801	}
775		802
		803	out_free:
776	free_msi_irqs(dev);	804	free_msi_irqs(dev);
777		805
778	return ret;	806	return ret;
@@ -823,6 +851,31 @@ static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) · 44 unmodified lines
823	return 0;	851	return 0;
824	}	852	}
825		853
		854	/**
		855	* pci_msi_vec_count - Return the number of MSI vectors a device can send
		856	* @dev: device to report about
		857	*
		858	* This function returns the number of MSI vectors a device requested via
		859	* Multiple Message Capable register. It returns a negative errno if the
		860	* device is not capable sending MSI interrupts. Otherwise, the call succeeds
		861	* and returns a power of two, up to a maximum of 2^5 (32), according to the
		862	* MSI specification.
		863	**/
		864	int pci_msi_vec_count(struct pci_dev *dev)
		865	{
		866	int ret;
		867	u16 msgctl;
		868
		869	if (!dev->msi_cap)
		870	return -EINVAL;
		871
		872	pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
		873	ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
		874
		875	return ret;
		876	}
		877	EXPORT_SYMBOL(pci_msi_vec_count);
		878
826	/**	879	/**
827	* pci_enable_msi_block - configure device's MSI capability structure	880	* pci_enable_msi_block - configure device's MSI capability structure
828	* @dev: device to configure	881	* @dev: device to configure
@@ -836,16 +889,16 @@ static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) · 7 unmodified lines
836	* updates the @dev's irq member to the lowest new interrupt number; the	889	* updates the @dev's irq member to the lowest new interrupt number; the
837	* other interrupt numbers allocated to this device are consecutive.	890	* other interrupt numbers allocated to this device are consecutive.
838	*/	891	*/
839	int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)	892	int pci_enable_msi_block(struct pci_dev *dev, int nvec)
840	{	893	{
841	int status, maxvec;	894	int status, maxvec;
842	u16 msgctl;
843		895
844	if (!dev->msi_cap \|\| dev->current_state != PCI_D0)	896	if (dev->current_state != PCI_D0)
845	return -EINVAL;	897	return -EINVAL;
846		898
847	pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);	899	maxvec = pci_msi_vec_count(dev);
848	maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);	900	if (maxvec < 0)
		901	return maxvec;
849	if (nvec > maxvec)	902	if (nvec > maxvec)
850	return maxvec;	903	return maxvec;
851		904
@@ -867,31 +920,6 @@ int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) · 15 unmodified lines
867	}	920	}
868	EXPORT_SYMBOL(pci_enable_msi_block);	921	EXPORT_SYMBOL(pci_enable_msi_block);
869		922
870	int pci_enable_msi_block_auto(struct pci_dev dev, unsigned int maxvec)
871	{
872	int ret, nvec;
873	u16 msgctl;
874
875	if (!dev->msi_cap \|\| dev->current_state != PCI_D0)
876	return -EINVAL;
877
878	pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
879	ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
880
881	if (maxvec)
882	*maxvec = ret;
883
884	do {
885	nvec = ret;
886	ret = pci_enable_msi_block(dev, nvec);
887	} while (ret > 0);
888
889	if (ret < 0)
890	return ret;
891	return nvec;
892	}
893	EXPORT_SYMBOL(pci_enable_msi_block_auto);
894
895	void pci_msi_shutdown(struct pci_dev *dev)	923	void pci_msi_shutdown(struct pci_dev *dev)
896	{	924	{
897	struct msi_desc *desc;	925	struct msi_desc *desc;
@@ -925,25 +953,29 @@ void pci_disable_msi(struct pci_dev *dev) · 27 unmodified lines
925		953
926	pci_msi_shutdown(dev);	954	pci_msi_shutdown(dev);
927	free_msi_irqs(dev);	955	free_msi_irqs(dev);
928	kset_unregister(dev->msi_kset);
929	dev->msi_kset = NULL;
930	}	956	}
931	EXPORT_SYMBOL(pci_disable_msi);	957	EXPORT_SYMBOL(pci_disable_msi);
932		958
933	/**	959	/**
934	* pci_msix_table_size - return the number of device's MSI-X table entries	960	* pci_msix_vec_count - return the number of device's MSI-X table entries
935	* @dev: pointer to the pci_dev data structure of MSI-X device function	961	* @dev: pointer to the pci_dev data structure of MSI-X device function
936	*/	962
937	int pci_msix_table_size(struct pci_dev *dev)	963	* This function returns the number of device's MSI-X table entries and
		964	* therefore the number of MSI-X vectors device is capable of sending.
		965	* It returns a negative errno if the device is not capable of sending MSI-X
		966	* interrupts.
		967	**/
		968	int pci_msix_vec_count(struct pci_dev *dev)
938	{	969	{
939	u16 control;	970	u16 control;
940		971
941	if (!dev->msix_cap)	972	if (!dev->msix_cap)
942	return 0;	973	return -EINVAL;
943		974
944	pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);	975	pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
945	return msix_table_size(control);	976	return msix_table_size(control);
946	}	977	}
		978	EXPORT_SYMBOL(pci_msix_vec_count);
947		979
948	/**	980	/**
949	* pci_enable_msix - configure device's MSI-X capability structure	981	* pci_enable_msix - configure device's MSI-X capability structure
@@ -972,7 +1004,9 @@ int pci_enable_msix(struct pci_dev dev, struct msix_entry entries, int nvec) · 22 unmodified lines
972	if (status)	1004	if (status)
973	return status;	1005	return status;
974		1006
975	nr_entries = pci_msix_table_size(dev);	1007	nr_entries = pci_msix_vec_count(dev);
		1008	if (nr_entries < 0)
		1009	return nr_entries;
976	if (nvec > nr_entries)	1010	if (nvec > nr_entries)
977	return nr_entries;	1011	return nr_entries;
978		1012
@@ -1023,8 +1057,6 @@ void pci_disable_msix(struct pci_dev *dev) · 44 unmodified lines
1023		1057
1024	pci_msix_shutdown(dev);	1058	pci_msix_shutdown(dev);
1025	free_msi_irqs(dev);	1059	free_msi_irqs(dev);
1026	kset_unregister(dev->msi_kset);
1027	dev->msi_kset = NULL;
1028	}	1060	}
1029	EXPORT_SYMBOL(pci_disable_msix);	1061	EXPORT_SYMBOL(pci_disable_msix);
1030		1062
@@ -1079,3 +1111,77 @@ void pci_msi_init_pci_dev(struct pci_dev *dev) · 48 unmodified lines
1079	if (dev->msix_cap)	1111	if (dev->msix_cap)
1080	msix_set_enable(dev, 0);	1112	msix_set_enable(dev, 0);
1081	}	1113	}
		1114
		1115	/**
		1116	* pci_enable_msi_range - configure device's MSI capability structure
		1117	* @dev: device to configure
		1118	* @minvec: minimal number of interrupts to configure
		1119	* @maxvec: maximum number of interrupts to configure
		1120	*
		1121	* This function tries to allocate a maximum possible number of interrupts in a
		1122	* range between @minvec and @maxvec. It returns a negative errno if an error
		1123	* occurs. If it succeeds, it returns the actual number of interrupts allocated
		1124	* and updates the @dev's irq member to the lowest new interrupt number;
		1125	* the other interrupt numbers allocated to this device are consecutive.
		1126	**/
		1127	int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
		1128	{
		1129	int nvec = maxvec;
		1130	int rc;
		1131
		1132	if (maxvec < minvec)
		1133	return -ERANGE;
		1134
		1135	do {
		1136	rc = pci_enable_msi_block(dev, nvec);
		1137	if (rc < 0) {
		1138	return rc;
		1139	} else if (rc > 0) {
		1140	if (rc < minvec)
		1141	return -ENOSPC;
		1142	nvec = rc;
		1143	}
		1144	} while (rc);
		1145
		1146	return nvec;
		1147	}
		1148	EXPORT_SYMBOL(pci_enable_msi_range);
		1149
		1150	/**
		1151	* pci_enable_msix_range - configure device's MSI-X capability structure
		1152	* @dev: pointer to the pci_dev data structure of MSI-X device function
		1153	* @entries: pointer to an array of MSI-X entries
		1154	* @minvec: minimum number of MSI-X irqs requested
		1155	* @maxvec: maximum number of MSI-X irqs requested
		1156	*
		1157	* Setup the MSI-X capability structure of device function with a maximum
		1158	* possible number of interrupts in the range between @minvec and @maxvec
		1159	* upon its software driver call to request for MSI-X mode enabled on its
		1160	* hardware device function. It returns a negative errno if an error occurs.
		1161	* If it succeeds, it returns the actual number of interrupts allocated and
		1162	* indicates the successful configuration of MSI-X capability structure
		1163	* with new allocated MSI-X interrupts.
		1164	**/
		1165	int pci_enable_msix_range(struct pci_dev dev, struct msix_entry entries,
		1166	int minvec, int maxvec)
		1167	{
		1168	int nvec = maxvec;
		1169	int rc;
		1170
		1171	if (maxvec < minvec)
		1172	return -ERANGE;
		1173
		1174	do {
		1175	rc = pci_enable_msix(dev, entries, nvec);
		1176	if (rc < 0) {
		1177	return rc;
		1178	} else if (rc > 0) {
		1179	if (rc < minvec)
		1180	return -ENOSPC;
		1181	nvec = rc;
		1182	}
		1183	} while (rc);
		1184
		1185	return nvec;
		1186	}
		1187	EXPORT_SYMBOL(pci_enable_msix_range);

drivers/pci/pci-acpi.c+1−1

@@ -361,7 +361,7 @@ static void pci_acpi_cleanup(struct device *dev) · 360 unmodified lines
361		361
362	static bool pci_acpi_bus_match(struct device *dev)	362	static bool pci_acpi_bus_match(struct device *dev)
363	{	363	{
364	return dev->bus == &pci_bus_type;	364	return dev_is_pci(dev);
365	}	365	}
366		366
367	static struct acpi_bus_type acpi_pci_bus = {	367	static struct acpi_bus_type acpi_pci_bus = {

drivers/pci/pci-label.c+25−32

@@ -34,21 +34,7 @@ · 33 unmodified lines
34		34
35	#define DEVICE_LABEL_DSM 0x07	35	#define DEVICE_LABEL_DSM 0x07
36		36
37	#ifndef CONFIG_DMI	37	#ifdef CONFIG_DMI
38
39	static inline int
40	pci_create_smbiosname_file(struct pci_dev *pdev)
41	{
42	return -1;
43	}
44
45	static inline void
46	pci_remove_smbiosname_file(struct pci_dev *pdev)
47	{
48	}
49
50	#else
51
52	enum smbios_attr_enum {	38	enum smbios_attr_enum {
53	SMBIOS_ATTR_NONE = 0,	39	SMBIOS_ATTR_NONE = 0,
54	SMBIOS_ATTR_LABEL_SHOW,	40	SMBIOS_ATTR_LABEL_SHOW,
@@ -156,31 +142,20 @@ pci_remove_smbiosname_file(struct pci_dev *pdev) · 101 unmodified lines
156	{	142	{
157	sysfs_remove_group(&pdev->dev.kobj, &smbios_attr_group);	143	sysfs_remove_group(&pdev->dev.kobj, &smbios_attr_group);
158	}	144	}
159		145	#else
160	#endif
161
162	#ifndef CONFIG_ACPI
163
164	static inline int
165	pci_create_acpi_index_label_files(struct pci_dev *pdev)
166	{
167	return -1;
168	}
169
170	static inline int	146	static inline int
171	pci_remove_acpi_index_label_files(struct pci_dev *pdev)	147	pci_create_smbiosname_file(struct pci_dev *pdev)
172	{	148	{
173	return -1;	149	return -1;
174	}	150	}
175		151
176	static inline bool	152	static inline void
177	device_has_dsm(struct device *dev)	153	pci_remove_smbiosname_file(struct pci_dev *pdev)
178	{	154	{
179	return false;
180	}	155	}
		156	#endif
181		157
182	#else	158	#ifdef CONFIG_ACPI
183
184	static const char device_label_dsm_uuid[] = {	159	static const char device_label_dsm_uuid[] = {
185	0xD0, 0x37, 0xC9, 0xE5, 0x53, 0x35, 0x7A, 0x4D,	160	0xD0, 0x37, 0xC9, 0xE5, 0x53, 0x35, 0x7A, 0x4D,
186	0x91, 0x17, 0xEA, 0x4D, 0x19, 0xC3, 0x43, 0x4D	161	0x91, 0x17, 0xEA, 0x4D, 0x19, 0xC3, 0x43, 0x4D
@@ -364,6 +339,24 @@ pci_remove_acpi_index_label_files(struct pci_dev *pdev) · 177 unmodified lines
364	sysfs_remove_group(&pdev->dev.kobj, &acpi_attr_group);	339	sysfs_remove_group(&pdev->dev.kobj, &acpi_attr_group);
365	return 0;	340	return 0;
366	}	341	}
		342	#else
		343	static inline int
		344	pci_create_acpi_index_label_files(struct pci_dev *pdev)
		345	{
		346	return -1;
		347	}
		348
		349	static inline int
		350	pci_remove_acpi_index_label_files(struct pci_dev *pdev)
		351	{
		352	return -1;
		353	}
		354
		355	static inline bool
		356	device_has_dsm(struct device *dev)
		357	{
		358	return false;
		359	}
367	#endif	360	#endif
368		361
369	void pci_create_firmware_label_files(struct pci_dev *pdev)	362	void pci_create_firmware_label_files(struct pci_dev *pdev)

drivers/pci/pci-sysfs.c+7−12

 }
 static DEVICE_ATTR_RW(msi_bus);
-static DEFINE_MUTEX(pci_remove_rescan_mutex);
 static ssize_t bus_rescan_store(struct bus_type *bus, const char *buf,
 				size_t count)
 {
 		return -EINVAL;
 	if (val) {
-		mutex_lock(&pci_remove_rescan_mutex);
+		pci_lock_rescan_remove();
 		while ((b = pci_find_next_bus(b)) != NULL)
 			pci_rescan_bus(b);
-		mutex_unlock(&pci_remove_rescan_mutex);
+		pci_unlock_rescan_remove();
 	}
 	return count;
 }
 		return -EINVAL;
 	if (val) {
-		mutex_lock(&pci_remove_rescan_mutex);
+		pci_lock_rescan_remove();
 		pci_rescan_bus(pdev->bus);
-		mutex_unlock(&pci_remove_rescan_mutex);
+		pci_unlock_rescan_remove();
 	}
 	return count;
 }
 static void remove_callback(struct device *dev)
 {
-	struct pci_dev *pdev = to_pci_dev(dev);
+	pci_stop_and_remove_bus_device_locked(to_pci_dev(dev));
-	mutex_lock(&pci_remove_rescan_mutex);
-	pci_stop_and_remove_bus_device(pdev);
-	mutex_unlock(&pci_remove_rescan_mutex);
 }
 static ssize_t
 		return -EINVAL;
 	if (val) {
-		mutex_lock(&pci_remove_rescan_mutex);
+		pci_lock_rescan_remove();
 		if (!pci_is_root_bus(bus) && list_empty(&bus->devices))
 			pci_rescan_bus_bridge_resize(bus->self);
 		else
 			pci_rescan_bus(bus);
-		mutex_unlock(&pci_remove_rescan_mutex);
+		pci_unlock_rescan_remove();
 	}
 	return count;
 }

drivers/pci/pci.c+252−293

 	return best;
 }
+/**
+ * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
+ * @dev: the PCI device to operate on
+ * @pos: config space offset of status word
+ * @mask: mask of bit(s) to care about in status word
+ *
+ * Return 1 when mask bit(s) in status word clear, 0 otherwise.
+ */
+int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
+{
+	int i;
+	/* Wait for Transaction Pending bit clean */
+	for (i = 0; i < 4; i++) {
+		u16 status;
+		if (i)
+			msleep((1 << (i - 1)) * 100);
+		pci_read_config_word(dev, pos, &status);
+		if (!(status & mask))
+			return 1;
+	}
+	return 0;
+}
 /**
  * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
  * @dev: PCI device to have its BARs restored
 	return error;
 }
+/**
+ * pci_wakeup - Wake up a PCI device
+ * @pci_dev: Device to handle.
+ * @ign: ignored parameter
+ */
+static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
+{
+	pci_wakeup_event(pci_dev);
+	pm_request_resume(&pci_dev->dev);
+	return 0;
+}
+/**
+ * pci_wakeup_bus - Walk given bus and wake up devices on it
+ * @bus: Top bus of the subtree to walk.
+ */
+static void pci_wakeup_bus(struct pci_bus *bus)
+{
+	if (bus)
+		pci_walk_bus(bus, pci_wakeup, NULL);
+}
 /**
  * __pci_start_power_transition - Start power transition of a PCI device
  * @dev: PCI device to handle.
 #define PCI_EXP_SAVE_REGS	7
-static struct pci_cap_saved_state *pci_find_saved_cap(
+static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
-	struct pci_dev *pci_dev, char cap)
+						       u16 cap, bool extended)
 {
 	struct pci_cap_saved_state *tmp;
 	hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
-		if (tmp->cap.cap_nr == cap)
+		if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
 			return tmp;
 	}
 	return NULL;
 }
+struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
+{
+	return _pci_find_saved_cap(dev, cap, false);
+}
+struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
+{
+	return _pci_find_saved_cap(dev, cap, true);
+}
 static int pci_save_pcie_state(struct pci_dev *dev)
 {
 	int i = 0;
 		return i;
 	if ((i = pci_save_pcix_state(dev)) != 0)
 		return i;
+	if ((i = pci_save_vc_state(dev)) != 0)
+		return i;
 	return 0;
 }
 	/* PCI Express register must be restored first */
 	pci_restore_pcie_state(dev);
 	pci_restore_ats_state(dev);
+	pci_restore_vc_state(dev);
 	pci_restore_config_space(dev);
  * @dev: PCI device that we're dealing with
  * @state: Saved state returned from pci_store_saved_state()
  */
-int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
+static int pci_load_saved_state(struct pci_dev *dev,
+				struct pci_saved_state *state)
 {
 	struct pci_cap_saved_data *cap;
 	while (cap->size) {
 		struct pci_cap_saved_state *tmp;
-		tmp = pci_find_saved_cap(dev, cap->cap_nr);
+		tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
 		if (!tmp || tmp->cap.size != cap->size)
 			return -EINVAL;
 	dev->state_saved = true;
 	return 0;
 }
-EXPORT_SYMBOL_GPL(pci_load_saved_state);
 /**
  * pci_load_and_free_saved_state - Reload the save state pointed to by state,
 		pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
 }
-/**
- * pci_wakeup - Wake up a PCI device
- * @pci_dev: Device to handle.
- * @ign: ignored parameter
- */
-static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
-{
-	pci_wakeup_event(pci_dev);
-	pm_request_resume(&pci_dev->dev);
-	return 0;
-}
-/**
- * pci_wakeup_bus - Walk given bus and wake up devices on it
- * @bus: Top bus of the subtree to walk.
- */
-void pci_wakeup_bus(struct pci_bus *bus)
-{
-	if (bus)
-		pci_walk_bus(bus, pci_wakeup, NULL);
-}
 /**
  * pci_pme_capable - check the capability of PCI device to generate PME#
  * If the platform can't manage @dev, return the deepest state from which it
  * can generate wake events, based on any available PME info.
  */
-pci_power_t pci_target_state(struct pci_dev *dev)
+static pci_power_t pci_target_state(struct pci_dev *dev)
 {
 	pci_power_t target_state = PCI_D3hot;
 }
 /**
- * pci_add_cap_save_buffer - allocate buffer for saving given capability registers
+ * _pci_add_cap_save_buffer - allocate buffer for saving given
+ *                            capability registers
  * @dev: the PCI device
  * @cap: the capability to allocate the buffer for
+ * @extended: Standard or Extended capability ID
  * @size: requested size of the buffer
  */
-static int pci_add_cap_save_buffer(
+static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
-	struct pci_dev *dev, char cap, unsigned int size)
+				    bool extended, unsigned int size)
 {
 	int pos;
 	struct pci_cap_saved_state *save_state;
-	pos = pci_find_capability(dev, cap);
+	if (extended)
+		pos = pci_find_ext_capability(dev, cap);
+	else
+		pos = pci_find_capability(dev, cap);
 	if (pos <= 0)
 		return 0;
 		return -ENOMEM;
 	save_state->cap.cap_nr = cap;
+	save_state->cap.cap_extended = extended;
 	save_state->cap.size = size;
 	pci_add_saved_cap(dev, save_state);
 	return 0;
 }
+int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
+{
+	return _pci_add_cap_save_buffer(dev, cap, false, size);
+}
+int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
+{
+	return _pci_add_cap_save_buffer(dev, cap, true, size);
+}
 /**
  * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
  * @dev: the PCI device
 	if (error)
 		dev_err(&dev->dev,
 			"unable to preallocate PCI-X save buffer\n");
+	pci_allocate_vc_save_buffers(dev);
 }
 void pci_free_cap_save_buffers(struct pci_dev *dev)
 	}
 }
-/**
- * pci_enable_ido - enable ID-based Ordering on a device
- * @dev: the PCI device
- * @type: which types of IDO to enable
- *
- * Enable ID-based ordering on @dev.  @type can contain the bits
- * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
- * which types of transactions are allowed to be re-ordered.
- */
-void pci_enable_ido(struct pci_dev *dev, unsigned long type)
-{
-	u16 ctrl = 0;
-	if (type & PCI_EXP_IDO_REQUEST)
-		ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
-	if (type & PCI_EXP_IDO_COMPLETION)
-		ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
-	if (ctrl)
-		pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
-}
-EXPORT_SYMBOL(pci_enable_ido);
-/**
- * pci_disable_ido - disable ID-based ordering on a device
- * @dev: the PCI device
- * @type: which types of IDO to disable
- */
-void pci_disable_ido(struct pci_dev *dev, unsigned long type)
-{
-	u16 ctrl = 0;
-	if (type & PCI_EXP_IDO_REQUEST)
-		ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
-	if (type & PCI_EXP_IDO_COMPLETION)
-		ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
-	if (ctrl)
-		pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
-}
-EXPORT_SYMBOL(pci_disable_ido);
-/**
- * pci_enable_obff - enable optimized buffer flush/fill
- * @dev: PCI device
- * @type: type of signaling to use
- *
- * Try to enable @type OBFF signaling on @dev.  It will try using WAKE#
- * signaling if possible, falling back to message signaling only if
- * WAKE# isn't supported.  @type should indicate whether the PCIe link
- * be brought out of L0s or L1 to send the message.  It should be either
- * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
- *
- * If your device can benefit from receiving all messages, even at the
- * power cost of bringing the link back up from a low power state, use
- * %PCI_EXP_OBFF_SIGNAL_ALWAYS.  Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
- * preferred type).
- *
- * RETURNS:
- * Zero on success, appropriate error number on failure.
- */
-int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
-{
-	u32 cap;
-	u16 ctrl;
-	int ret;
-	pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
-	if (!(cap & PCI_EXP_DEVCAP2_OBFF_MASK))
-		return -ENOTSUPP; /* no OBFF support at all */
-	/* Make sure the topology supports OBFF as well */
-	if (dev->bus->self) {
-		ret = pci_enable_obff(dev->bus->self, type);
-		if (ret)
-			return ret;
-	}
-	pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
-	if (cap & PCI_EXP_DEVCAP2_OBFF_WAKE)
-		ctrl |= PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
-	else {
-		switch (type) {
-		case PCI_EXP_OBFF_SIGNAL_L0:
-			if (!(ctrl & PCI_EXP_DEVCTL2_OBFF_WAKE_EN))
-				ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGA_EN;
-			break;
-		case PCI_EXP_OBFF_SIGNAL_ALWAYS:
-			ctrl &= ~PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
-			ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGB_EN;
-			break;
-		default:
-			WARN(1, "bad OBFF signal type\n");
-			return -ENOTSUPP;
-		}
-	}
-	pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
-	return 0;
-}
-EXPORT_SYMBOL(pci_enable_obff);
-/**
- * pci_disable_obff - disable optimized buffer flush/fill
- * @dev: PCI device
- *
- * Disable OBFF on @dev.
- */
-void pci_disable_obff(struct pci_dev *dev)
-{
-	pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
-				   PCI_EXP_DEVCTL2_OBFF_WAKE_EN);
-}
-EXPORT_SYMBOL(pci_disable_obff);
-/**
- * pci_ltr_supported - check whether a device supports LTR
- * @dev: PCI device
- *
- * RETURNS:
- * True if @dev supports latency tolerance reporting, false otherwise.
- */
-static bool pci_ltr_supported(struct pci_dev *dev)
-{
-	u32 cap;
-	pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
-	return cap & PCI_EXP_DEVCAP2_LTR;
-}
-/**
- * pci_enable_ltr - enable latency tolerance reporting
- * @dev: PCI device
- *
- * Enable LTR on @dev if possible, which means enabling it first on
- * upstream ports.
- *
- * RETURNS:
- * Zero on success, errno on failure.
- */
-int pci_enable_ltr(struct pci_dev *dev)
-{
-	int ret;
-	/* Only primary function can enable/disable LTR */
-	if (PCI_FUNC(dev->devfn) != 0)
-		return -EINVAL;
-	if (!pci_ltr_supported(dev))
-		return -ENOTSUPP;
-	/* Enable upstream ports first */
-	if (dev->bus->self) {
-		ret = pci_enable_ltr(dev->bus->self);
-		if (ret)
-			return ret;
-	}
-	return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
-					PCI_EXP_DEVCTL2_LTR_EN);
-}
-EXPORT_SYMBOL(pci_enable_ltr);
-/**
- * pci_disable_ltr - disable latency tolerance reporting
- * @dev: PCI device
- */
-void pci_disable_ltr(struct pci_dev *dev)
-{
-	/* Only primary function can enable/disable LTR */
-	if (PCI_FUNC(dev->devfn) != 0)
-		return;
-	if (!pci_ltr_supported(dev))
-		return;
-	pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
-				   PCI_EXP_DEVCTL2_LTR_EN);
-}
-EXPORT_SYMBOL(pci_disable_ltr);
-static int __pci_ltr_scale(int *val)
-{
-	int scale = 0;
-	while (*val > 1023) {
-		*val = (*val + 31) / 32;
-		scale++;
-	}
-	return scale;
-}
-/**
- * pci_set_ltr - set LTR latency values
- * @dev: PCI device
- * @snoop_lat_ns: snoop latency in nanoseconds
- * @nosnoop_lat_ns: nosnoop latency in nanoseconds
- *
- * Figure out the scale and set the LTR values accordingly.
- */
-int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
-{
-	int pos, ret, snoop_scale, nosnoop_scale;
-	u16 val;
-	if (!pci_ltr_supported(dev))
-		return -ENOTSUPP;
-	snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
-	nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
-	if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
-	    nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
-		return -EINVAL;
-	if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
-	    (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
-		return -EINVAL;
-	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
-	if (!pos)
-		return -ENOTSUPP;
-	val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
-	ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
-	if (ret != 4)
-		return -EIO;
-	val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
-	ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
-	if (ret != 4)
-		return -EIO;
-	return 0;
-}
-EXPORT_SYMBOL(pci_set_ltr);
 static int pci_acs_enable;
 /**
 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
 /**
- * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
+ * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
  * @dev: the PCI device to operate on
  *
  * Check if the device dev has its INTx line asserted, unmask it if not
  */
 int pci_wait_for_pending_transaction(struct pci_dev *dev)
 {
-	int i;
+	if (!pci_is_pcie(dev))
-	u16 status;
+		return 1;
-	/* Wait for Transaction Pending bit clean */
-	for (i = 0; i < 4; i++) {
-		if (i)
-			msleep((1 << (i - 1)) * 100);
-		pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
-		if (!(status & PCI_EXP_DEVSTA_TRPND))
-			return 1;
-	}
-	return 0;
+	return pci_wait_for_pending(dev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_TRPND);
 }
 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
 static int pci_af_flr(struct pci_dev *dev, int probe)
 {
-	int i;
 	int pos;
 	u8 cap;
-	u8 status;
 	pos = pci_find_capability(dev, PCI_CAP_ID_AF);
 	if (!pos)
 		return 0;
 	/* Wait for Transaction Pending bit clean */
-	for (i = 0; i < 4; i++) {
+	if (pci_wait_for_pending(dev, PCI_AF_STATUS, PCI_AF_STATUS_TP))
-		if (i)
+		goto clear;
-			msleep((1 << (i - 1)) * 100);
-		pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
-		if (!(status & PCI_AF_STATUS_TP))
-			goto clear;
-	}
 	dev_err(&dev->dev, "transaction is not cleared; "
 			"proceeding with reset anyway\n");
 	device_lock(&dev->dev);
 }
+/* Return 1 on successful lock, 0 on contention */
+static int pci_dev_trylock(struct pci_dev *dev)
+{
+	if (pci_cfg_access_trylock(dev)) {
+		if (device_trylock(&dev->dev))
+			return 1;
+		pci_cfg_access_unlock(dev);
+	}
+	return 0;
+}
 static void pci_dev_unlock(struct pci_dev *dev)
 {
 	device_unlock(&dev->dev);
 }
 EXPORT_SYMBOL_GPL(pci_reset_function);
+/**
+ * pci_try_reset_function - quiesce and reset a PCI device function
+ * @dev: PCI device to reset
+ *
+ * Same as above, except return -EAGAIN if unable to lock device.
+ */
+int pci_try_reset_function(struct pci_dev *dev)
+{
+	int rc;
+	rc = pci_dev_reset(dev, 1);
+	if (rc)
+		return rc;
+	pci_dev_save_and_disable(dev);
+	if (pci_dev_trylock(dev)) {
+		rc = __pci_dev_reset(dev, 0);
+		pci_dev_unlock(dev);
+	} else
+		rc = -EAGAIN;
+	pci_dev_restore(dev);
+	return rc;
+}
+EXPORT_SYMBOL_GPL(pci_try_reset_function);
 /* Lock devices from the top of the tree down */
 static void pci_bus_lock(struct pci_bus *bus)
 {
 	}
 }
+/* Return 1 on successful lock, 0 on contention */
+static int pci_bus_trylock(struct pci_bus *bus)
+{
+	struct pci_dev *dev;
+	list_for_each_entry(dev, &bus->devices, bus_list) {
+		if (!pci_dev_trylock(dev))
+			goto unlock;
+		if (dev->subordinate) {
+			if (!pci_bus_trylock(dev->subordinate)) {
+				pci_dev_unlock(dev);
+				goto unlock;
+			}
+		}
+	}
+	return 1;
+unlock:
+	list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
+		if (dev->subordinate)
+			pci_bus_unlock(dev->subordinate);
+		pci_dev_unlock(dev);
+	}
+	return 0;
+}
 /* Lock devices from the top of the tree down */
 static void pci_slot_lock(struct pci_slot *slot)
 {
 	}
 }
+/* Return 1 on successful lock, 0 on contention */
+static int pci_slot_trylock(struct pci_slot *slot)
+{
+	struct pci_dev *dev;
+	list_for_each_entry(dev, &slot->bus->devices, bus_list) {
+		if (!dev->slot || dev->slot != slot)
+			continue;
+		if (!pci_dev_trylock(dev))
+			goto unlock;
+		if (dev->subordinate) {
+			if (!pci_bus_trylock(dev->subordinate)) {
+				pci_dev_unlock(dev);
+				goto unlock;
+			}
+		}
+	}
+	return 1;
+unlock:
+	list_for_each_entry_continue_reverse(dev,
+					     &slot->bus->devices, bus_list) {
+		if (!dev->slot || dev->slot != slot)
+			continue;
+		if (dev->subordinate)
+			pci_bus_unlock(dev->subordinate);
+		pci_dev_unlock(dev);
+	}
+	return 0;
+}
 /* Save and disable devices from the top of the tree down */
 static void pci_bus_save_and_disable(struct pci_bus *bus)
 {
 }
 EXPORT_SYMBOL_GPL(pci_reset_slot);
+/**
+ * pci_try_reset_slot - Try to reset a PCI slot
+ * @slot: PCI slot to reset
+ *
+ * Same as above except return -EAGAIN if the slot cannot be locked
+ */
+int pci_try_reset_slot(struct pci_slot *slot)
+{
+	int rc;
+	rc = pci_slot_reset(slot, 1);
+	if (rc)
+		return rc;
+	pci_slot_save_and_disable(slot);
+	if (pci_slot_trylock(slot)) {
+		might_sleep();
+		rc = pci_reset_hotplug_slot(slot->hotplug, 0);
+		pci_slot_unlock(slot);
+	} else
+		rc = -EAGAIN;
+	pci_slot_restore(slot);
+	return rc;
+}
+EXPORT_SYMBOL_GPL(pci_try_reset_slot);
 static int pci_bus_reset(struct pci_bus *bus, int probe)
 {
 	if (!bus->self)
 }
 EXPORT_SYMBOL_GPL(pci_reset_bus);
+/**
+ * pci_try_reset_bus - Try to reset a PCI bus
+ * @bus: top level PCI bus to reset
+ *
+ * Same as above except return -EAGAIN if the bus cannot be locked
+ */
+int pci_try_reset_bus(struct pci_bus *bus)
+{
+	int rc;
+	rc = pci_bus_reset(bus, 1);
+	if (rc)
+		return rc;
+	pci_bus_save_and_disable(bus);
+	if (pci_bus_trylock(bus)) {
+		might_sleep();
+		pci_reset_bridge_secondary_bus(bus->self);
+		pci_bus_unlock(bus);
+	} else
+		rc = -EAGAIN;
+	pci_bus_restore(bus);
+	return rc;
+}
+EXPORT_SYMBOL_GPL(pci_try_reset_bus);
 /**
  * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
  * @dev: PCI device to query
 EXPORT_SYMBOL(pci_pme_capable);
 EXPORT_SYMBOL(pci_pme_active);
 EXPORT_SYMBOL(pci_wake_from_d3);
-EXPORT_SYMBOL(pci_target_state);
 EXPORT_SYMBOL(pci_prepare_to_sleep);
 EXPORT_SYMBOL(pci_back_from_sleep);
 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);

drivers/pci/pci.h+0−2

 #define PCI_CFG_SPACE_SIZE	256
 #define PCI_CFG_SPACE_EXP_SIZE	4096
-extern const unsigned char pcix_bus_speed[];
 extern const unsigned char pcie_link_speed[];
 /* Functions internal to the PCI core code */
 void pci_disable_enabled_device(struct pci_dev *dev);
 int pci_finish_runtime_suspend(struct pci_dev *dev);
 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
-void pci_wakeup_bus(struct pci_bus *bus);
 void pci_config_pm_runtime_get(struct pci_dev *dev);
 void pci_config_pm_runtime_put(struct pci_dev *dev);
 void pci_pm_init(struct pci_dev *dev);

drivers/pci/pcie/aer/aerdrv_acpi.c+33−23

 static inline int hest_match_pci(struct acpi_hest_aer_common *p,
 				 struct pci_dev *pci)
 {
-	return	(0           == pci_domain_nr(pci->bus) &&
+	return   ACPI_HEST_SEGMENT(p->bus) == pci_domain_nr(pci->bus) &&
-		 p->bus      == pci->bus->number &&
+		 ACPI_HEST_BUS(p->bus)     == pci->bus->number &&
-		 p->device   == PCI_SLOT(pci->devfn) &&
+		 p->device                 == PCI_SLOT(pci->devfn) &&
-		 p->function == PCI_FUNC(pci->devfn));
+		 p->function               == PCI_FUNC(pci->devfn);
 }
 static inline bool hest_match_type(struct acpi_hest_header *hest_hdr,
 	int firmware_first;
 };
+static int hest_source_is_pcie_aer(struct acpi_hest_header *hest_hdr)
+{
+	if (hest_hdr->type == ACPI_HEST_TYPE_AER_ROOT_PORT ||
+	    hest_hdr->type == ACPI_HEST_TYPE_AER_ENDPOINT ||
+	    hest_hdr->type == ACPI_HEST_TYPE_AER_BRIDGE)
+		return 1;
+	return 0;
+}
 static int aer_hest_parse(struct acpi_hest_header *hest_hdr, void *data)
 {
 	struct aer_hest_parse_info *info = data;
 	struct acpi_hest_aer_common *p;
 	int ff;
+	if (!hest_source_is_pcie_aer(hest_hdr))
+		return 0;
 	p = (struct acpi_hest_aer_common *)(hest_hdr + 1);
 	ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
+	/*
+	 * If no specific device is supplied, determine whether
+	 * FIRMWARE_FIRST is set for *any* PCIe device.
+	 */
+	if (!info->pci_dev) {
+		info->firmware_first |= ff;
+		return 0;
+	}
+	/* Otherwise, check the specific device */
 	if (p->flags & ACPI_HEST_GLOBAL) {
 		if (hest_match_type(hest_hdr, info->pci_dev))
 			info->firmware_first = ff;
 static bool aer_firmware_first;
-static int aer_hest_parse_aff(struct acpi_hest_header *hest_hdr, void *data)
-{
-	struct acpi_hest_aer_common *p;
-	if (aer_firmware_first)
-		return 0;
-	switch (hest_hdr->type) {
-	case ACPI_HEST_TYPE_AER_ROOT_PORT:
-	case ACPI_HEST_TYPE_AER_ENDPOINT:
-	case ACPI_HEST_TYPE_AER_BRIDGE:
-		p = (struct acpi_hest_aer_common *)(hest_hdr + 1);
-		aer_firmware_first = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
-	default:
-		return 0;
-	}
-}
 /**
  * aer_acpi_firmware_first - Check if APEI should control AER.
  */
 bool aer_acpi_firmware_first(void)
 {
 	static bool parsed = false;
+	struct aer_hest_parse_info info = {
+		.pci_dev	= NULL,	/* Check all PCIe devices */
+		.firmware_first	= 0,
+	};
 	if (!parsed) {
-		apei_hest_parse(aer_hest_parse_aff, NULL);
+		apei_hest_parse(aer_hest_parse, &info);
+		aer_firmware_first = info.firmware_first;
 		parsed = true;
 	}
 	return aer_firmware_first;

drivers/pci/pcie/aer/aerdrv_errprint.c+48−47

@@ -124,6 +124,21 @@ static const char *aer_agent_string[] = { · 123 unmodified lines
124	"Transmitter ID"	124	"Transmitter ID"
125	};	125	};
126		126
		127	static void __print_tlp_header(struct pci_dev *dev,
		128	struct aer_header_log_regs *t)
		129	{
		130	unsigned char tlp = (unsigned char )&t;
		131
		132	dev_err(&dev->dev, " TLP Header:"
		133	" %02x%02x%02x%02x %02x%02x%02x%02x"
		134	" %02x%02x%02x%02x %02x%02x%02x%02x\n",
		135	(tlp + 3), (tlp + 2), (tlp + 1), tlp,
		136	(tlp + 7), (tlp + 6), (tlp + 5), (tlp + 4),
		137	(tlp + 11), (tlp + 10), *(tlp + 9),
		138	(tlp + 8), (tlp + 15), *(tlp + 14),
		139	(tlp + 13), (tlp + 12));
		140	}
		141
127	static void __aer_print_error(struct pci_dev *dev,	142	static void __aer_print_error(struct pci_dev *dev,
128	struct aer_err_info *info)	143	struct aer_err_info *info)
129	{	144	{
@@ -153,48 +168,39 @@ static void __aer_print_error(struct pci_dev *dev, · 23 unmodified lines
153		168
154	void aer_print_error(struct pci_dev dev, struct aer_err_info info)	169	void aer_print_error(struct pci_dev dev, struct aer_err_info info)
155	{	170	{
		171	int layer, agent;
156	int id = ((dev->bus->number << 8) \| dev->devfn);	172	int id = ((dev->bus->number << 8) \| dev->devfn);
157		173
158	if (info->status == 0) {	174	if (!info->status) {
159	dev_err(&dev->dev,	175	dev_err(&dev->dev,
160	"PCIe Bus Error: severity=%s, type=Unaccessible, "	176	"PCIe Bus Error: severity=%s, type=Unaccessible, "
161	"id=%04x(Unregistered Agent ID)\n",	177	"id=%04x(Unregistered Agent ID)\n",
162	aer_error_severity_string[info->severity], id);	178	aer_error_severity_string[info->severity], id);
163	} else {	179	goto out;
164	int layer, agent;	180	}
165		181
166	layer = AER_GET_LAYER_ERROR(info->severity, info->status);	182	layer = AER_GET_LAYER_ERROR(info->severity, info->status);
167	agent = AER_GET_AGENT(info->severity, info->status);	183	agent = AER_GET_AGENT(info->severity, info->status);
168		184
169	dev_err(&dev->dev,	185	dev_err(&dev->dev,
170	"PCIe Bus Error: severity=%s, type=%s, id=%04x(%s)\n",	186	"PCIe Bus Error: severity=%s, type=%s, id=%04x(%s)\n",
171	aer_error_severity_string[info->severity],	187	aer_error_severity_string[info->severity],
172	aer_error_layer[layer], id, aer_agent_string[agent]);	188	aer_error_layer[layer], id, aer_agent_string[agent]);
173		189
174	dev_err(&dev->dev,	190	dev_err(&dev->dev,
175	" device [%04x:%04x] error status/mask=%08x/%08x\n",	191	" device [%04x:%04x] error status/mask=%08x/%08x\n",
176	dev->vendor, dev->device,	192	dev->vendor, dev->device,
177	info->status, info->mask);	193	info->status, info->mask);
178		194
179	__aer_print_error(dev, info);	195	__aer_print_error(dev, info);
180
181	if (info->tlp_header_valid) {
182	unsigned char tlp = (unsigned char ) &info->tlp;
183	dev_err(&dev->dev, " TLP Header:"
184	" %02x%02x%02x%02x %02x%02x%02x%02x"
185	" %02x%02x%02x%02x %02x%02x%02x%02x\n",
186	(tlp + 3), (tlp + 2), (tlp + 1), tlp,
187	(tlp + 7), (tlp + 6), (tlp + 5), (tlp + 4),
188	(tlp + 11), (tlp + 10), *(tlp + 9),
189	(tlp + 8), (tlp + 15), *(tlp + 14),
190	(tlp + 13), (tlp + 12));
191	}
192	}
193		196
		197	if (info->tlp_header_valid)
		198	__print_tlp_header(dev, &info->tlp);
		199
		200	out:
194	if (info->id && info->error_dev_num > 1 && info->id == id)	201	if (info->id && info->error_dev_num > 1 && info->id == id)
195	dev_err(&dev->dev,	202	dev_err(&dev->dev, " Error of this Agent(%04x) is reported first\n", id);
196	" Error of this Agent(%04x) is reported first\n",	203
197	id);
198	trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),	204	trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
199	info->severity);	205	info->severity);
200	}	206	}
@@ -228,6 +234,7 @@ void cper_print_aer(struct pci_dev *dev, int cper_severity, · 27 unmodified lines
228	const char **status_strs;	234	const char **status_strs;
229		235
230	aer_severity = cper_severity_to_aer(cper_severity);	236	aer_severity = cper_severity_to_aer(cper_severity);
		237
231	if (aer_severity == AER_CORRECTABLE) {	238	if (aer_severity == AER_CORRECTABLE) {
232	status = aer->cor_status;	239	status = aer->cor_status;
233	mask = aer->cor_mask;	240	mask = aer->cor_mask;
@@ -240,28 +247,22 @@ void cper_print_aer(struct pci_dev *dev, int cper_severity, · 6 unmodified lines
240	status_strs_size = ARRAY_SIZE(aer_uncorrectable_error_string);	247	status_strs_size = ARRAY_SIZE(aer_uncorrectable_error_string);
241	tlp_header_valid = status & AER_LOG_TLP_MASKS;	248	tlp_header_valid = status & AER_LOG_TLP_MASKS;
242	}	249	}
		250
243	layer = AER_GET_LAYER_ERROR(aer_severity, status);	251	layer = AER_GET_LAYER_ERROR(aer_severity, status);
244	agent = AER_GET_AGENT(aer_severity, status);	252	agent = AER_GET_AGENT(aer_severity, status);
245	dev_err(&dev->dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n",	253
246	status, mask);	254	dev_err(&dev->dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
247	cper_print_bits("", status, status_strs, status_strs_size);	255	cper_print_bits("", status, status_strs, status_strs_size);
248	dev_err(&dev->dev, "aer_layer=%s, aer_agent=%s\n",	256	dev_err(&dev->dev, "aer_layer=%s, aer_agent=%s\n",
249	aer_error_layer[layer], aer_agent_string[agent]);	257	aer_error_layer[layer], aer_agent_string[agent]);
		258
250	if (aer_severity != AER_CORRECTABLE)	259	if (aer_severity != AER_CORRECTABLE)
251	dev_err(&dev->dev, "aer_uncor_severity: 0x%08x\n",	260	dev_err(&dev->dev, "aer_uncor_severity: 0x%08x\n",
252	aer->uncor_severity);	261	aer->uncor_severity);
253	if (tlp_header_valid) {	262
254	const unsigned char *tlp;	263	if (tlp_header_valid)
255	tlp = (const unsigned char *)&aer->header_log;	264	__print_tlp_header(dev, &aer->header_log);
256	dev_err(&dev->dev, "aer_tlp_header:"	265
257	" %02x%02x%02x%02x %02x%02x%02x%02x"
258	" %02x%02x%02x%02x %02x%02x%02x%02x\n",
259	(tlp + 3), (tlp + 2), (tlp + 1), tlp,
260	(tlp + 7), (tlp + 6), (tlp + 5), (tlp + 4),
261	(tlp + 11), (tlp + 10), *(tlp + 9),
262	(tlp + 8), (tlp + 15), *(tlp + 14),
263	(tlp + 13), (tlp + 12));
264	}
265	trace_aer_event(dev_name(&dev->dev), (status & ~mask),	266	trace_aer_event(dev_name(&dev->dev), (status & ~mask),
266	aer_severity);	267	aer_severity);
267	}	268	}

drivers/pci/pcie/aspm.c+0−12

@@ -984,18 +984,6 @@ void pcie_no_aspm(void) · 983 unmodified lines
984	}	984	}
985	}	985	}
986		986
987	/**
988	* pcie_aspm_enabled - is PCIe ASPM enabled?
989	*
990	* Returns true if ASPM has not been disabled by the command-line option
991	* pcie_aspm=off.
992	**/
993	int pcie_aspm_enabled(void)
994	{
995	return !aspm_disabled;
996	}
997	EXPORT_SYMBOL(pcie_aspm_enabled);
998
999	bool pcie_aspm_support_enabled(void)	987	bool pcie_aspm_support_enabled(void)
1000	{	988	{
1001	return aspm_support_enabled;	989	return aspm_support_enabled;

drivers/pci/pcie/portdrv_core.c+18−18

@@ -79,9 +79,10 @@ static int pcie_port_enable_msix(struct pci_dev dev, int vectors, int mask) · 78 unmodified lines
79	u16 reg16;	79	u16 reg16;
80	u32 reg32;	80	u32 reg32;
81		81
82	nr_entries = pci_msix_table_size(dev);	82	nr_entries = pci_msix_vec_count(dev);
83	if (!nr_entries)	83	if (nr_entries < 0)
84	return -EINVAL;	84	return nr_entries;
		85	BUG_ON(!nr_entries);
85	if (nr_entries > PCIE_PORT_MAX_MSIX_ENTRIES)	86	if (nr_entries > PCIE_PORT_MAX_MSIX_ENTRIES)
86	nr_entries = PCIE_PORT_MAX_MSIX_ENTRIES;	87	nr_entries = PCIE_PORT_MAX_MSIX_ENTRIES;
87		88
@@ -344,11 +345,12 @@ static int pcie_device_init(struct pci_dev *pdev, int service, int irq) · 256 unmodified lines
344	device_enable_async_suspend(device);	345	device_enable_async_suspend(device);
345		346
346	retval = device_register(device);	347	retval = device_register(device);
347	if (retval)	348	if (retval) {
348	kfree(pcie);	349	put_device(device);
349	else	350	return retval;
350	get_device(device);	351	}
351	return retval;	352
		353	return 0;
352	}	354	}
353		355
354	/**	356	/**
@@ -454,10 +456,8 @@ int pcie_port_device_resume(struct device *dev) · 99 unmodified lines
454		456
455	static int remove_iter(struct device dev, void data)	457	static int remove_iter(struct device dev, void data)
456	{	458	{
457	if (dev->bus == &pcie_port_bus_type) {	459	if (dev->bus == &pcie_port_bus_type)
458	put_device(dev);
459	device_unregister(dev);	460	device_unregister(dev);
460	}
461	return 0;	461	return 0;
462	}	462	}
463		463
@@ -498,12 +498,12 @@ static int pcie_port_probe_service(struct device *dev) · 34 unmodified lines
498		498
499	pciedev = to_pcie_device(dev);	499	pciedev = to_pcie_device(dev);
500	status = driver->probe(pciedev);	500	status = driver->probe(pciedev);
501	if (!status) {	501	if (status)
502	dev_printk(KERN_DEBUG, dev, "service driver %s loaded\n",	502	return status;
503	driver->name);	503
504	get_device(dev);	504	dev_printk(KERN_DEBUG, dev, "service driver %s loaded\n", driver->name);
505	}	505	get_device(dev);
506	return status;	506	return 0;
507	}	507	}
508		508
509	/**	509	/**
@@ -554,7 +554,7 @@ int pcie_port_service_register(struct pcie_port_service_driver *new) · 44 unmodified lines
554	if (pcie_ports_disabled)	554	if (pcie_ports_disabled)
555	return -ENODEV;	555	return -ENODEV;
556		556
557	new->driver.name = (char *)new->name;	557	new->driver.name = new->name;
558	new->driver.bus = &pcie_port_bus_type;	558	new->driver.bus = &pcie_port_bus_type;
559	new->driver.probe = pcie_port_probe_service;	559	new->driver.probe = pcie_port_probe_service;
560	new->driver.remove = pcie_port_remove_service;	560	new->driver.remove = pcie_port_remove_service;

drivers/pci/probe.c+102−74

 #define CARDBUS_LATENCY_TIMER	176	/* secondary latency timer */
 #define CARDBUS_RESERVE_BUSNR	3
-struct resource busn_resource = {
+static struct resource busn_resource = {
 	.name	= "PCI busn",
 	.start	= 0,
 	.end	= 255,
 		region.end = l + sz;
 	}
-	pcibios_bus_to_resource(dev, res, &region);
+	pcibios_bus_to_resource(dev->bus, res, &region);
-	pcibios_resource_to_bus(dev, &inverted_region, res);
+	pcibios_resource_to_bus(dev->bus, &inverted_region, res);
 	/*
 	 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
 		res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
 		region.start = base;
 		region.end = limit + io_granularity - 1;
-		pcibios_bus_to_resource(dev, res, &region);
+		pcibios_bus_to_resource(dev->bus, res, &region);
 		dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
 	}
 }
 		res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
 		region.start = base;
 		region.end = limit + 0xfffff;
-		pcibios_bus_to_resource(dev, res, &region);
+		pcibios_bus_to_resource(dev->bus, res, &region);
 		dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
 	}
 }
 			res->flags |= IORESOURCE_MEM_64;
 		region.start = base;
 		region.end = limit + 0xfffff;
-		pcibios_bus_to_resource(dev, res, &region);
+		pcibios_bus_to_resource(dev->bus, res, &region);
 		dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
 	}
 }
 	return bridge;
 }
-const unsigned char pcix_bus_speed[] = {
+static const unsigned char pcix_bus_speed[] = {
 	PCI_SPEED_UNKNOWN,		/* 0 */
 	PCI_SPEED_66MHz_PCIX,		/* 1 */
 	PCI_SPEED_100MHz_PCIX,		/* 2 */
 		pdev->is_hotplug_bridge = 1;
 }
+/**
+ * pci_cfg_space_size - get the configuration space size of the PCI device.
+ * @dev: PCI device
+ *
+ * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
+ * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
+ * access it.  Maybe we don't have a way to generate extended config space
+ * accesses, or the device is behind a reverse Express bridge.  So we try
+ * reading the dword at 0x100 which must either be 0 or a valid extended
+ * capability header.
+ */
+static int pci_cfg_space_size_ext(struct pci_dev *dev)
+{
+	u32 status;
+	int pos = PCI_CFG_SPACE_SIZE;
+	if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
+		goto fail;
+	if (status == 0xffffffff)
+		goto fail;
+	return PCI_CFG_SPACE_EXP_SIZE;
+ fail:
+	return PCI_CFG_SPACE_SIZE;
+}
+int pci_cfg_space_size(struct pci_dev *dev)
+{
+	int pos;
+	u32 status;
+	u16 class;
+	class = dev->class >> 8;
+	if (class == PCI_CLASS_BRIDGE_HOST)
+		return pci_cfg_space_size_ext(dev);
+	if (!pci_is_pcie(dev)) {
+		pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
+		if (!pos)
+			goto fail;
+		pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
+		if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
+			goto fail;
+	}
+	return pci_cfg_space_size_ext(dev);
+ fail:
+	return PCI_CFG_SPACE_SIZE;
+}
 #define LEGACY_IO_RESOURCE	(IORESOURCE_IO | IORESOURCE_PCI_FIXED)
 /**
 				region.end = 0x1F7;
 				res = &dev->resource[0];
 				res->flags = LEGACY_IO_RESOURCE;
-				pcibios_bus_to_resource(dev, res, &region);
+				pcibios_bus_to_resource(dev->bus, res, &region);
 				region.start = 0x3F6;
 				region.end = 0x3F6;
 				res = &dev->resource[1];
 				res->flags = LEGACY_IO_RESOURCE;
-				pcibios_bus_to_resource(dev, res, &region);
+				pcibios_bus_to_resource(dev->bus, res, &region);
 			}
 			if ((progif & 4) == 0) {
 				region.start = 0x170;
 				region.end = 0x177;
 				res = &dev->resource[2];
 				res->flags = LEGACY_IO_RESOURCE;
-				pcibios_bus_to_resource(dev, res, &region);
+				pcibios_bus_to_resource(dev->bus, res, &region);
 				region.start = 0x376;
 				region.end = 0x376;
 				res = &dev->resource[3];
 				res->flags = LEGACY_IO_RESOURCE;
-				pcibios_bus_to_resource(dev, res, &region);
+				pcibios_bus_to_resource(dev->bus, res, &region);
 			}
 		}
 		break;
 	pci_free_cap_save_buffers(dev);
 }
+static void pci_free_resources(struct pci_dev *dev)
+{
+	int i;
+	pci_cleanup_rom(dev);
+	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
+		struct resource *res = dev->resource + i;
+		if (res->parent)
+			release_resource(res);
+	}
+}
 /**
  * pci_release_dev - free a pci device structure when all users of it are finished.
  * @dev: device that's been disconnected
  */
 static void pci_release_dev(struct device *dev)
 {
-	struct pci_dev *pci_dev;
+	struct pci_dev *pci_dev = to_pci_dev(dev);
+	down_write(&pci_bus_sem);
+	list_del(&pci_dev->bus_list);
+	up_write(&pci_bus_sem);
+	pci_free_resources(pci_dev);
-	pci_dev = to_pci_dev(dev);
 	pci_release_capabilities(pci_dev);
 	pci_release_of_node(pci_dev);
 	pcibios_release_device(pci_dev);
 	kfree(pci_dev);
 }
-/**
- * pci_cfg_space_size - get the configuration space size of the PCI device.
- * @dev: PCI device
- *
- * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
- * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
- * access it.  Maybe we don't have a way to generate extended config space
- * accesses, or the device is behind a reverse Express bridge.  So we try
- * reading the dword at 0x100 which must either be 0 or a valid extended
- * capability header.
- */
-int pci_cfg_space_size_ext(struct pci_dev *dev)
-{
-	u32 status;
-	int pos = PCI_CFG_SPACE_SIZE;
-	if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
-		goto fail;
-	if (status == 0xffffffff)
-		goto fail;
-	return PCI_CFG_SPACE_EXP_SIZE;
- fail:
-	return PCI_CFG_SPACE_SIZE;
-}
-int pci_cfg_space_size(struct pci_dev *dev)
-{
-	int pos;
-	u32 status;
-	u16 class;
-	class = dev->class >> 8;
-	if (class == PCI_CLASS_BRIDGE_HOST)
-		return pci_cfg_space_size_ext(dev);
-	if (!pci_is_pcie(dev)) {
-		pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
-		if (!pos)
-			goto fail;
-		pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
-		if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
-			goto fail;
-	}
-	return pci_cfg_space_size_ext(dev);
- fail:
-	return PCI_CFG_SPACE_SIZE;
-}
 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
 {
 	struct pci_dev *dev;
 }
 EXPORT_SYMBOL(pci_alloc_dev);
-struct pci_dev *alloc_pci_dev(void)
-{
-	return pci_alloc_dev(NULL);
-}
-EXPORT_SYMBOL(alloc_pci_dev);
 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
 				 int crs_timeout)
 {
 	dev->match_driver = false;
 	ret = device_add(&dev->dev);
 	WARN_ON(ret < 0);
-	pci_proc_attach_device(dev);
 }
 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
 EXPORT_SYMBOL(pci_scan_bridge);
 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
+/*
+ * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
+ * routines should always be executed under this mutex.
+ */
+static DEFINE_MUTEX(pci_rescan_remove_lock);
+void pci_lock_rescan_remove(void)
+{
+	mutex_lock(&pci_rescan_remove_lock);
+}
+EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
+void pci_unlock_rescan_remove(void)
+{
+	mutex_unlock(&pci_rescan_remove_lock);
+}
+EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
 {
 	const struct pci_dev *a = to_pci_dev(d_a);

drivers/pci/quirks.c+1−1

@@ -339,7 +339,7 @@ static void quirk_io_region(struct pci_dev *dev, int port, · 338 unmodified lines
339	/* Convert from PCI bus to resource space */	339	/* Convert from PCI bus to resource space */
340	bus_region.start = region;	340	bus_region.start = region;
341	bus_region.end = region + size - 1;	341	bus_region.end = region + size - 1;
342	pcibios_bus_to_resource(dev, res, &bus_region);	342	pcibios_bus_to_resource(dev->bus, res, &bus_region);
343		343
344	if (!pci_claim_resource(dev, nr))	344	if (!pci_claim_resource(dev, nr))
345	dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);	345	dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);

drivers/pci/remove.c+13−21

 #include <linux/pci-aspm.h>
 #include "pci.h"
-static void pci_free_resources(struct pci_dev *dev)
-{
-	int i;
-	msi_remove_pci_irq_vectors(dev);
-	pci_cleanup_rom(dev);
-	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-		struct resource *res = dev->resource + i;
-		if (res->parent)
-			release_resource(res);
-	}
-}
 static void pci_stop_dev(struct pci_dev *dev)
 {
 	pci_pme_active(dev, false);
 static void pci_destroy_dev(struct pci_dev *dev)
 {
-	device_del(&dev->dev);
+	if (!dev->dev.kobj.parent)
+		return;
-	down_write(&pci_bus_sem);
+	device_del(&dev->dev);
-	list_del(&dev->bus_list);
-	up_write(&pci_bus_sem);
-	pci_free_resources(dev);
 	put_device(&dev->dev);
 }
 }
 EXPORT_SYMBOL(pci_stop_and_remove_bus_device);
+void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev)
+{
+	pci_lock_rescan_remove();
+	pci_stop_and_remove_bus_device(dev);
+	pci_unlock_rescan_remove();
+}
+EXPORT_SYMBOL_GPL(pci_stop_and_remove_bus_device_locked);
 void pci_stop_root_bus(struct pci_bus *bus)
 {
 	struct pci_dev *child, *tmp;
 		pci_stop_bus_device(child);
 	/* stop the host bridge */
-	device_del(&host_bridge->dev);
+	device_release_driver(&host_bridge->dev);
 }
 void pci_remove_root_bus(struct pci_bus *bus)
 	host_bridge->bus = NULL;
 	/* remove the host bridge */
-	put_device(&host_bridge->dev);
+	device_unregister(&host_bridge->dev);
 }

drivers/pci/rom.c+1−1

@@ -31,7 +31,7 @@ int pci_enable_rom(struct pci_dev *pdev) · 30 unmodified lines
31	if (!res->flags)	31	if (!res->flags)
32	return -1;	32	return -1;
33		33
34	pcibios_resource_to_bus(pdev, &region, res);	34	pcibios_resource_to_bus(pdev->bus, &region, res);
35	pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);	35	pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
36	rom_addr &= ~PCI_ROM_ADDRESS_MASK;	36	rom_addr &= ~PCI_ROM_ADDRESS_MASK;
37	rom_addr \|= region.start \| PCI_ROM_ADDRESS_ENABLE;	37	rom_addr \|= region.start \| PCI_ROM_ADDRESS_ENABLE;

drivers/pci/setup-bus.c+17−15

 		 &bus->busn_res);
 	res = bus->resource[0];
-	pcibios_resource_to_bus(bridge, &region, res);
+	pcibios_resource_to_bus(bridge->bus, &region, res);
 	if (res->flags & IORESOURCE_IO) {
 		/*
 		 * The IO resource is allocated a range twice as large as it
 	}
 	res = bus->resource[1];
-	pcibios_resource_to_bus(bridge, &region, res);
+	pcibios_resource_to_bus(bridge->bus, &region, res);
 	if (res->flags & IORESOURCE_IO) {
 		dev_info(&bridge->dev, "  bridge window %pR\n", res);
 		pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
 	}
 	res = bus->resource[2];
-	pcibios_resource_to_bus(bridge, &region, res);
+	pcibios_resource_to_bus(bridge->bus, &region, res);
 	if (res->flags & IORESOURCE_MEM) {
 		dev_info(&bridge->dev, "  bridge window %pR\n", res);
 		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
 	}
 	res = bus->resource[3];
-	pcibios_resource_to_bus(bridge, &region, res);
+	pcibios_resource_to_bus(bridge->bus, &region, res);
 	if (res->flags & IORESOURCE_MEM) {
 		dev_info(&bridge->dev, "  bridge window %pR\n", res);
 		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
 	struct pci_bus_region region;
 	unsigned long io_mask;
 	u8 io_base_lo, io_limit_lo;
-	u32 l, io_upper16;
+	u16 l;
+	u32 io_upper16;
 	io_mask = PCI_IO_RANGE_MASK;
 	if (bridge->io_window_1k)
 	/* Set up the top and bottom of the PCI I/O segment for this bus. */
 	res = bus->resource[0];
-	pcibios_resource_to_bus(bridge, &region, res);
+	pcibios_resource_to_bus(bridge->bus, &region, res);
 	if (res->flags & IORESOURCE_IO) {
-		pci_read_config_dword(bridge, PCI_IO_BASE, &l);
+		pci_read_config_word(bridge, PCI_IO_BASE, &l);
-		l &= 0xffff0000;
 		io_base_lo = (region.start >> 8) & io_mask;
 		io_limit_lo = (region.end >> 8) & io_mask;
-		l |= ((u32) io_limit_lo << 8) | io_base_lo;
+		l = ((u16) io_limit_lo << 8) | io_base_lo;
 		/* Set up upper 16 bits of I/O base/limit. */
 		io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
 		dev_info(&bridge->dev, "  bridge window %pR\n", res);
 	/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
 	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
 	/* Update lower 16 bits of I/O base/limit. */
-	pci_write_config_dword(bridge, PCI_IO_BASE, l);
+	pci_write_config_word(bridge, PCI_IO_BASE, l);
 	/* Update upper 16 bits of I/O base/limit. */
 	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
 }
 	/* Set up the top and bottom of the PCI Memory segment for this bus. */
 	res = bus->resource[1];
-	pcibios_resource_to_bus(bridge, &region, res);
+	pcibios_resource_to_bus(bridge->bus, &region, res);
 	if (res->flags & IORESOURCE_MEM) {
 		l = (region.start >> 16) & 0xfff0;
 		l |= region.end & 0xfff00000;
 	/* Set up PREF base/limit. */
 	bu = lu = 0;
 	res = bus->resource[2];
-	pcibios_resource_to_bus(bridge, &region, res);
+	pcibios_resource_to_bus(bridge->bus, &region, res);
 	if (res->flags & IORESOURCE_PREFETCH) {
 		l = (region.start >> 16) & 0xfff0;
 		l |= region.end & 0xfff00000;
 	pci_read_config_word(bridge, PCI_IO_BASE, &io);
 	if (!io) {
-		pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
+		pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
 		pci_read_config_word(bridge, PCI_IO_BASE, &io);
 		pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
 	}
 	if (io)
 		b_res[0].flags |= IORESOURCE_IO;
 	/*  DECchip 21050 pass 2 errata: the bridge may miss an address
 	    disconnect boundary by one PCI data phase.
 	    Workaround: do not use prefetching on this device. */
 	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
 		return;
 	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
 	if (!pmem) {
 		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
-					       0xfff0fff0);
+					       0xffe0fff0);
 		pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
 		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
 	}
 		if (!r->flags)
 			continue;
-		pcibios_resource_to_bus(dev, &region, r);
+		pcibios_resource_to_bus(dev->bus, &region, r);
 		if (!region.start) {
 			*unassigned = true;
 			return 1; /* return early from pci_walk_bus() */

drivers/pci/setup-res.c+1−1

@@ -52,7 +52,7 @@ void pci_update_resource(struct pci_dev *dev, int resno) · 51 unmodified lines
52	if (res->flags & IORESOURCE_PCI_FIXED)	52	if (res->flags & IORESOURCE_PCI_FIXED)
53	return;	53	return;
54		54
55	pcibios_resource_to_bus(dev, &region, res);	55	pcibios_resource_to_bus(dev->bus, &region, res);
56		56
57	new = region.start \| (res->flags & PCI_REGION_FLAG_MASK);	57	new = region.start \| (res->flags & PCI_REGION_FLAG_MASK);
58	if (res->flags & IORESOURCE_IO)	58	if (res->flags & IORESOURCE_IO)

drivers/pci/slot.c+0−26

@@ -319,32 +319,6 @@ err: · 318 unmodified lines
319	}	319	}
320	EXPORT_SYMBOL_GPL(pci_create_slot);	320	EXPORT_SYMBOL_GPL(pci_create_slot);
321		321
322	/**
323	* pci_renumber_slot - update %struct pci_slot -> number
324	* @slot: &struct pci_slot to update
325	* @slot_nr: new number for slot
326	*
327	* The primary purpose of this interface is to allow callers who earlier
328	* created a placeholder slot in pci_create_slot() by passing a -1 as
329	* slot_nr, to update their %struct pci_slot with the correct @slot_nr.
330	*/
331	void pci_renumber_slot(struct pci_slot *slot, int slot_nr)
332	{
333	struct pci_slot *tmp;
334
335	down_write(&pci_bus_sem);
336
337	list_for_each_entry(tmp, &slot->bus->slots, list) {
338	WARN_ON(tmp->number == slot_nr);
339	goto out;
340	}
341
342	slot->number = slot_nr;
343	out:
344	up_write(&pci_bus_sem);
345	}
346	EXPORT_SYMBOL_GPL(pci_renumber_slot);
347
348	/**	322	/**
349	* pci_destroy_slot - decrement refcount for physical PCI slot	323	* pci_destroy_slot - decrement refcount for physical PCI slot
350	* @slot: struct pci_slot to decrement	324	* @slot: struct pci_slot to decrement

drivers/pci/vc.c+434−0

@@ -0,0 +1,434 @@
	1	/*
	2	* PCI Virtual Channel support
	3	*
	4	* Copyright (C) 2013 Red Hat, Inc. All rights reserved.
	5	* Author: Alex Williamson <alex.williamson@redhat.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/device.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/pci.h>
	16	#include <linux/pci_regs.h>
	17	#include <linux/types.h>
	18
	19	/**
	20	* pci_vc_save_restore_dwords - Save or restore a series of dwords
	21	* @dev: device
	22	* @pos: starting config space position
	23	* @buf: buffer to save to or restore from
	24	* @dwords: number of dwords to save/restore
	25	* @save: whether to save or restore
	26	*/
	27	static void pci_vc_save_restore_dwords(struct pci_dev *dev, int pos,
	28	u32 *buf, int dwords, bool save)
	29	{
	30	int i;
	31
	32	for (i = 0; i < dwords; i++, buf++) {
	33	if (save)
	34	pci_read_config_dword(dev, pos + (i * 4), buf);
	35	else
	36	pci_write_config_dword(dev, pos + (i * 4), *buf);
	37	}
	38	}
	39
	40	/**
	41	* pci_vc_load_arb_table - load and wait for VC arbitration table
	42	* @dev: device
	43	* @pos: starting position of VC capability (VC/VC9/MFVC)
	44	*
	45	* Set Load VC Arbitration Table bit requesting hardware to apply the VC
	46	* Arbitration Table (previously loaded). When the VC Arbitration Table
	47	* Status clears, hardware has latched the table into VC arbitration logic.
	48	*/
	49	static void pci_vc_load_arb_table(struct pci_dev *dev, int pos)
	50	{
	51	u16 ctrl;
	52
	53	pci_read_config_word(dev, pos + PCI_VC_PORT_CTRL, &ctrl);
	54	pci_write_config_word(dev, pos + PCI_VC_PORT_CTRL,
	55	ctrl \| PCI_VC_PORT_CTRL_LOAD_TABLE);
	56	if (pci_wait_for_pending(dev, pos + PCI_VC_PORT_STATUS,
	57	PCI_VC_PORT_STATUS_TABLE))
	58	return;
	59
	60	dev_err(&dev->dev, "VC arbitration table failed to load\n");
	61	}
	62
	63	/**
	64	* pci_vc_load_port_arb_table - Load and wait for VC port arbitration table
	65	* @dev: device
	66	* @pos: starting position of VC capability (VC/VC9/MFVC)
	67	* @res: VC resource number, ie. VCn (0-7)
	68	*
	69	* Set Load Port Arbitration Table bit requesting hardware to apply the Port
	70	* Arbitration Table (previously loaded). When the Port Arbitration Table
	71	* Status clears, hardware has latched the table into port arbitration logic.
	72	*/
	73	static void pci_vc_load_port_arb_table(struct pci_dev *dev, int pos, int res)
	74	{
	75	int ctrl_pos, status_pos;
	76	u32 ctrl;
	77
	78	ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF);
	79	status_pos = pos + PCI_VC_RES_STATUS + (res * PCI_CAP_VC_PER_VC_SIZEOF);
	80
	81	pci_read_config_dword(dev, ctrl_pos, &ctrl);
	82	pci_write_config_dword(dev, ctrl_pos,
	83	ctrl \| PCI_VC_RES_CTRL_LOAD_TABLE);
	84
	85	if (pci_wait_for_pending(dev, status_pos, PCI_VC_RES_STATUS_TABLE))
	86	return;
	87
	88	dev_err(&dev->dev, "VC%d port arbitration table failed to load\n", res);
	89	}
	90
	91	/**
	92	* pci_vc_enable - Enable virtual channel
	93	* @dev: device
	94	* @pos: starting position of VC capability (VC/VC9/MFVC)
	95	* @res: VC res number, ie. VCn (0-7)
	96	*
	97	* A VC is enabled by setting the enable bit in matching resource control
	98	* registers on both sides of a link. We therefore need to find the opposite
	99	* end of the link. To keep this simple we enable from the downstream device.
	100	* RC devices do not have an upstream device, nor does it seem that VC9 do
	101	* (spec is unclear). Once we find the upstream device, match the VC ID to
	102	* get the correct resource, disable and enable on both ends.
	103	*/
	104	static void pci_vc_enable(struct pci_dev *dev, int pos, int res)
	105	{
	106	int ctrl_pos, status_pos, id, pos2, evcc, i, ctrl_pos2, status_pos2;
	107	u32 ctrl, header, cap1, ctrl2;
	108	struct pci_dev *link = NULL;
	109
	110	/* Enable VCs from the downstream device */
	111	if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT \|\|
	112	pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM)
	113	return;
	114
	115	ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF);
	116	status_pos = pos + PCI_VC_RES_STATUS + (res * PCI_CAP_VC_PER_VC_SIZEOF);
	117
	118	pci_read_config_dword(dev, ctrl_pos, &ctrl);
	119	id = ctrl & PCI_VC_RES_CTRL_ID;
	120
	121	pci_read_config_dword(dev, pos, &header);
	122
	123	/* If there is no opposite end of the link, skip to enable */
	124	if (PCI_EXT_CAP_ID(header) == PCI_EXT_CAP_ID_VC9 \|\|
	125	pci_is_root_bus(dev->bus))
	126	goto enable;
	127
	128	pos2 = pci_find_ext_capability(dev->bus->self, PCI_EXT_CAP_ID_VC);
	129	if (!pos2)
	130	goto enable;
	131
	132	pci_read_config_dword(dev->bus->self, pos2 + PCI_VC_PORT_CAP1, &cap1);
	133	evcc = cap1 & PCI_VC_CAP1_EVCC;
	134
	135	/* VC0 is hardwired enabled, so we can start with 1 */
	136	for (i = 1; i < evcc + 1; i++) {
	137	ctrl_pos2 = pos2 + PCI_VC_RES_CTRL +
	138	(i * PCI_CAP_VC_PER_VC_SIZEOF);
	139	status_pos2 = pos2 + PCI_VC_RES_STATUS +
	140	(i * PCI_CAP_VC_PER_VC_SIZEOF);
	141	pci_read_config_dword(dev->bus->self, ctrl_pos2, &ctrl2);
	142	if ((ctrl2 & PCI_VC_RES_CTRL_ID) == id) {
	143	link = dev->bus->self;
	144	break;
	145	}
	146	}
	147
	148	if (!link)
	149	goto enable;
	150
	151	/* Disable if enabled */
	152	if (ctrl2 & PCI_VC_RES_CTRL_ENABLE) {
	153	ctrl2 &= ~PCI_VC_RES_CTRL_ENABLE;
	154	pci_write_config_dword(link, ctrl_pos2, ctrl2);
	155	}
	156
	157	/* Enable on both ends */
	158	ctrl2 \|= PCI_VC_RES_CTRL_ENABLE;
	159	pci_write_config_dword(link, ctrl_pos2, ctrl2);
	160	enable:
	161	ctrl \|= PCI_VC_RES_CTRL_ENABLE;
	162	pci_write_config_dword(dev, ctrl_pos, ctrl);
	163
	164	if (!pci_wait_for_pending(dev, status_pos, PCI_VC_RES_STATUS_NEGO))
	165	dev_err(&dev->dev, "VC%d negotiation stuck pending\n", id);
	166
	167	if (link && !pci_wait_for_pending(link, status_pos2,
	168	PCI_VC_RES_STATUS_NEGO))
	169	dev_err(&link->dev, "VC%d negotiation stuck pending\n", id);
	170	}
	171
	172	/**
	173	* pci_vc_do_save_buffer - Size, save, or restore VC state
	174	* @dev: device
	175	* @pos: starting position of VC capability (VC/VC9/MFVC)
	176	* @save_state: buffer for save/restore
	177	* @name: for error message
	178	* @save: if provided a buffer, this indicates what to do with it
	179	*
	180	* Walking Virtual Channel config space to size, save, or restore it
	181	* is complicated, so we do it all from one function to reduce code and
	182	* guarantee ordering matches in the buffer. When called with NULL
	183	* @save_state, return the size of the necessary save buffer. When called
	184	* with a non-NULL @save_state, @save determines whether we save to the
	185	* buffer or restore from it.
	186	*/
	187	static int pci_vc_do_save_buffer(struct pci_dev *dev, int pos,
	188	struct pci_cap_saved_state *save_state,
	189	bool save)
	190	{
	191	u32 cap1;
	192	char evcc, lpevcc, parb_size;
	193	int i, len = 0;
	194	u8 buf = save_state ? (u8 )save_state->cap.data : NULL;
	195
	196	/* Sanity check buffer size for save/restore */
	197	if (buf && save_state->cap.size !=
	198	pci_vc_do_save_buffer(dev, pos, NULL, save)) {
	199	dev_err(&dev->dev,
	200	"VC save buffer size does not match @0x%x\n", pos);
	201	return -ENOMEM;
	202	}
	203
	204	pci_read_config_dword(dev, pos + PCI_VC_PORT_CAP1, &cap1);
	205	/* Extended VC Count (not counting VC0) */
	206	evcc = cap1 & PCI_VC_CAP1_EVCC;
	207	/* Low Priority Extended VC Count (not counting VC0) */
	208	lpevcc = (cap1 & PCI_VC_CAP1_LPEVCC) >> 4;
	209	/* Port Arbitration Table Entry Size (bits) */
	210	parb_size = 1 << ((cap1 & PCI_VC_CAP1_ARB_SIZE) >> 10);
	211
	212	/*
	213	* Port VC Control Register contains VC Arbitration Select, which
	214	* cannot be modified when more than one LPVC is in operation. We
	215	* therefore save/restore it first, as only VC0 should be enabled
	216	* after device reset.
	217	*/
	218	if (buf) {
	219	if (save)
	220	pci_read_config_word(dev, pos + PCI_VC_PORT_CTRL,
	221	(u16 *)buf);
	222	else
	223	pci_write_config_word(dev, pos + PCI_VC_PORT_CTRL,
	224	(u16 )buf);
	225	buf += 2;
	226	}
	227	len += 2;
	228
	229	/*
	230	* If we have any Low Priority VCs and a VC Arbitration Table Offset
	231	* in Port VC Capability Register 2 then save/restore it next.
	232	*/
	233	if (lpevcc) {
	234	u32 cap2;
	235	int vcarb_offset;
	236
	237	pci_read_config_dword(dev, pos + PCI_VC_PORT_CAP2, &cap2);
	238	vcarb_offset = ((cap2 & PCI_VC_CAP2_ARB_OFF) >> 24) * 16;
	239
	240	if (vcarb_offset) {
	241	int size, vcarb_phases = 0;
	242
	243	if (cap2 & PCI_VC_CAP2_128_PHASE)
	244	vcarb_phases = 128;
	245	else if (cap2 & PCI_VC_CAP2_64_PHASE)
	246	vcarb_phases = 64;
	247	else if (cap2 & PCI_VC_CAP2_32_PHASE)
	248	vcarb_phases = 32;
	249
	250	/* Fixed 4 bits per phase per lpevcc (plus VC0) */
	251	size = ((lpevcc + 1) * vcarb_phases * 4) / 8;
	252
	253	if (size && buf) {
	254	pci_vc_save_restore_dwords(dev,
	255	pos + vcarb_offset,
	256	(u32 *)buf,
	257	size / 4, save);
	258	/*
	259	* On restore, we need to signal hardware to
	260	* re-load the VC Arbitration Table.
	261	*/
	262	if (!save)
	263	pci_vc_load_arb_table(dev, pos);
	264
	265	buf += size;
	266	}
	267	len += size;
	268	}
	269	}
	270
	271	/*
	272	* In addition to each VC Resource Control Register, we may have a
	273	* Port Arbitration Table attached to each VC. The Port Arbitration
	274	* Table Offset in each VC Resource Capability Register tells us if
	275	* it exists. The entry size is global from the Port VC Capability
	276	* Register1 above. The number of phases is determined per VC.
	277	*/
	278	for (i = 0; i < evcc + 1; i++) {
	279	u32 cap;
	280	int parb_offset;
	281
	282	pci_read_config_dword(dev, pos + PCI_VC_RES_CAP +
	283	(i * PCI_CAP_VC_PER_VC_SIZEOF), &cap);
	284	parb_offset = ((cap & PCI_VC_RES_CAP_ARB_OFF) >> 24) * 16;
	285	if (parb_offset) {
	286	int size, parb_phases = 0;
	287
	288	if (cap & PCI_VC_RES_CAP_256_PHASE)
	289	parb_phases = 256;
	290	else if (cap & (PCI_VC_RES_CAP_128_PHASE \|
	291	PCI_VC_RES_CAP_128_PHASE_TB))
	292	parb_phases = 128;
	293	else if (cap & PCI_VC_RES_CAP_64_PHASE)
	294	parb_phases = 64;
	295	else if (cap & PCI_VC_RES_CAP_32_PHASE)
	296	parb_phases = 32;
	297
	298	size = (parb_size * parb_phases) / 8;
	299
	300	if (size && buf) {
	301	pci_vc_save_restore_dwords(dev,
	302	pos + parb_offset,
	303	(u32 *)buf,
	304	size / 4, save);
	305	buf += size;
	306	}
	307	len += size;
	308	}
	309
	310	/* VC Resource Control Register */
	311	if (buf) {
	312	int ctrl_pos = pos + PCI_VC_RES_CTRL +
	313	(i * PCI_CAP_VC_PER_VC_SIZEOF);
	314	if (save)
	315	pci_read_config_dword(dev, ctrl_pos,
	316	(u32 *)buf);
	317	else {
	318	u32 tmp, ctrl = (u32 )buf;
	319	/*
	320	* For an FLR case, the VC config may remain.
	321	* Preserve enable bit, restore the rest.
	322	*/
	323	pci_read_config_dword(dev, ctrl_pos, &tmp);
	324	tmp &= PCI_VC_RES_CTRL_ENABLE;
	325	tmp \|= ctrl & ~PCI_VC_RES_CTRL_ENABLE;
	326	pci_write_config_dword(dev, ctrl_pos, tmp);
	327	/* Load port arbitration table if used */
	328	if (ctrl & PCI_VC_RES_CTRL_ARB_SELECT)
	329	pci_vc_load_port_arb_table(dev, pos, i);
	330	/* Re-enable if needed */
	331	if ((ctrl ^ tmp) & PCI_VC_RES_CTRL_ENABLE)
	332	pci_vc_enable(dev, pos, i);
	333	}
	334	buf += 4;
	335	}
	336	len += 4;
	337	}
	338
	339	return buf ? 0 : len;
	340	}
	341
	342	static struct {
	343	u16 id;
	344	const char *name;
	345	} vc_caps[] = { { PCI_EXT_CAP_ID_MFVC, "MFVC" },
	346	{ PCI_EXT_CAP_ID_VC, "VC" },
	347	{ PCI_EXT_CAP_ID_VC9, "VC9" } };
	348
	349	/**
	350	* pci_save_vc_state - Save VC state to pre-allocate save buffer
	351	* @dev: device
	352	*
	353	* For each type of VC capability, VC/VC9/MFVC, find the capability and
	354	* save it to the pre-allocated save buffer.
	355	*/
	356	int pci_save_vc_state(struct pci_dev *dev)
	357	{
	358	int i;
	359
	360	for (i = 0; i < ARRAY_SIZE(vc_caps); i++) {
	361	int pos, ret;
	362	struct pci_cap_saved_state *save_state;
	363
	364	pos = pci_find_ext_capability(dev, vc_caps[i].id);
	365	if (!pos)
	366	continue;
	367
	368	save_state = pci_find_saved_ext_cap(dev, vc_caps[i].id);
	369	if (!save_state) {
	370	dev_err(&dev->dev, "%s buffer not found in %s\n",
	371	vc_caps[i].name, __func__);
	372	return -ENOMEM;
	373	}
	374
	375	ret = pci_vc_do_save_buffer(dev, pos, save_state, true);
	376	if (ret) {
	377	dev_err(&dev->dev, "%s save unsuccessful %s\n",
	378	vc_caps[i].name, __func__);
	379	return ret;
	380	}
	381	}
	382
	383	return 0;
	384	}
	385
	386	/**
	387	* pci_restore_vc_state - Restore VC state from save buffer
	388	* @dev: device
	389	*
	390	* For each type of VC capability, VC/VC9/MFVC, find the capability and
	391	* restore it from the previously saved buffer.
	392	*/
	393	void pci_restore_vc_state(struct pci_dev *dev)
	394	{
	395	int i;
	396
	397	for (i = 0; i < ARRAY_SIZE(vc_caps); i++) {
	398	int pos;
	399	struct pci_cap_saved_state *save_state;
	400
	401	pos = pci_find_ext_capability(dev, vc_caps[i].id);
	402	save_state = pci_find_saved_ext_cap(dev, vc_caps[i].id);
	403	if (!save_state \|\| !pos)
	404	continue;
	405
	406	pci_vc_do_save_buffer(dev, pos, save_state, false);
	407	}
	408	}
	409
	410	/**
	411	* pci_allocate_vc_save_buffers - Allocate save buffers for VC caps
	412	* @dev: device
	413	*
	414	* For each type of VC capability, VC/VC9/MFVC, find the capability, size
	415	* it, and allocate a buffer for save/restore.
	416	*/
	417
	418	void pci_allocate_vc_save_buffers(struct pci_dev *dev)
	419	{
	420	int i;
	421
	422	for (i = 0; i < ARRAY_SIZE(vc_caps); i++) {
	423	int len, pos = pci_find_ext_capability(dev, vc_caps[i].id);
	424
	425	if (!pos)
	426	continue;
	427
	428	len = pci_vc_do_save_buffer(dev, pos, NULL, false);
	429	if (pci_add_ext_cap_save_buffer(dev, vc_caps[i].id, len))
	430	dev_err(&dev->dev,
	431	"unable to preallocate %s save buffer\n",
	432	vc_caps[i].name);
	433	}
	434	}

drivers/pci/xen-pcifront.c+8−0

 	}
 	pcifront_init_sd(sd, domain, bus, pdev);
+	pci_lock_rescan_remove();
 	b = pci_scan_bus_parented(&pdev->xdev->dev, bus,
 				  &pcifront_bus_ops, sd);
 	if (!b) {
 		dev_err(&pdev->xdev->dev,
 			"Error creating PCI Frontend Bus!\n");
 		err = -ENOMEM;
+		pci_unlock_rescan_remove();
 		goto err_out;
 	}
 	/* Create SysFS and notify udev of the devices. Aka: "going live" */
 	pci_bus_add_devices(b);
+	pci_unlock_rescan_remove();
 	return err;
 err_out:
 	dev_dbg(&pdev->xdev->dev, "cleaning up root buses\n");
+	pci_lock_rescan_remove();
 	list_for_each_entry_safe(bus_entry, t, &pdev->root_buses, list) {
 		list_del(&bus_entry->list);
 		kfree(bus_entry);
 	}
+	pci_unlock_rescan_remove();
 }
 static pci_ers_result_t pcifront_common_process(int cmd,
 				domain, bus, slot, func);
 			continue;
 		}
+		pci_lock_rescan_remove();
 		pci_stop_and_remove_bus_device(pci_dev);
 		pci_dev_put(pci_dev);
+		pci_unlock_rescan_remove();
 		dev_dbg(&pdev->xdev->dev,
 			"PCI device %04x:%02x:%02x.%d removed.\n",

drivers/pcmcia/cardbus.c+7−0

 	struct pci_dev *dev;
 	unsigned int max, pass;
+	pci_lock_rescan_remove();
 	s->functions = pci_scan_slot(bus, PCI_DEVFN(0, 0));
 	pci_fixup_cardbus(bus);
 	pci_bus_add_devices(bus);
+	pci_unlock_rescan_remove();
 	return 0;
 }
 	if (!bus)
 		return;
+	pci_lock_rescan_remove();
 	list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list)
 		pci_stop_and_remove_bus_device(dev);
+	pci_unlock_rescan_remove();
 }

drivers/pcmcia/i82092.c+1−1

@@ -608,7 +608,7 @@ static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_ · 607 unmodified lines
608		608
609	enter("i82092aa_set_mem_map");	609	enter("i82092aa_set_mem_map");
610		610
611	pcibios_resource_to_bus(sock_info->dev, &region, mem->res);	611	pcibios_resource_to_bus(sock_info->dev->bus, &region, mem->res);
612		612
613	map = mem->map;	613	map = mem->map;
614	if (map > 4) {	614	if (map > 4) {

drivers/pcmcia/yenta_socket.c+3−3

@@ -445,7 +445,7 @@ static int yenta_set_mem_map(struct pcmcia_socket sock, struct pccard_mem_map · 444 unmodified lines
445	unsigned int start, stop, card_start;	445	unsigned int start, stop, card_start;
446	unsigned short word;	446	unsigned short word;
447		447
448	pcibios_resource_to_bus(socket->dev, &region, mem->res);	448	pcibios_resource_to_bus(socket->dev->bus, &region, mem->res);
449		449
450	map = mem->map;	450	map = mem->map;
451	start = region.start;	451	start = region.start;
@@ -709,7 +709,7 @@ static int yenta_allocate_res(struct yenta_socket *socket, int nr, unsigned type · 257 unmodified lines
709	region.start = config_readl(socket, addr_start) & mask;	709	region.start = config_readl(socket, addr_start) & mask;
710	region.end = config_readl(socket, addr_end) \| ~mask;	710	region.end = config_readl(socket, addr_end) \| ~mask;
711	if (region.start && region.end > region.start && !override_bios) {	711	if (region.start && region.end > region.start && !override_bios) {
712	pcibios_bus_to_resource(dev, res, &region);	712	pcibios_bus_to_resource(dev->bus, res, &region);
713	if (pci_claim_resource(dev, PCI_BRIDGE_RESOURCES + nr) == 0)	713	if (pci_claim_resource(dev, PCI_BRIDGE_RESOURCES + nr) == 0)
714	return 0;	714	return 0;
715	dev_printk(KERN_INFO, &dev->dev,	715	dev_printk(KERN_INFO, &dev->dev,
@@ -1033,7 +1033,7 @@ static void yenta_config_init(struct yenta_socket *socket) · 317 unmodified lines
1033	struct pci_dev *dev = socket->dev;	1033	struct pci_dev *dev = socket->dev;
1034	struct pci_bus_region region;	1034	struct pci_bus_region region;
1035		1035
1036	pcibios_resource_to_bus(socket->dev, &region, &dev->resource[0]);	1036	pcibios_resource_to_bus(socket->dev->bus, &region, &dev->resource[0]);
1037		1037
1038	config_writel(socket, CB_LEGACY_MODE_BASE, 0);	1038	config_writel(socket, CB_LEGACY_MODE_BASE, 0);
1039	config_writel(socket, PCI_BASE_ADDRESS_0, region.start);	1039	config_writel(socket, PCI_BASE_ADDRESS_0, region.start);

drivers/platform/x86/asus-wmi.c+2−0

 	mutex_unlock(&asus->wmi_lock);
 	mutex_lock(&asus->hotplug_lock);
+	pci_lock_rescan_remove();
 	if (asus->wlan.rfkill)
 		rfkill_set_sw_state(asus->wlan.rfkill, blocked);
 	}
 out_unlock:
+	pci_unlock_rescan_remove();
 	mutex_unlock(&asus->hotplug_lock);
 }

drivers/platform/x86/eeepc-laptop.c+2−0

 		rfkill_set_sw_state(eeepc->wlan_rfkill, blocked);
 	mutex_lock(&eeepc->hotplug_lock);
+	pci_lock_rescan_remove();
 	if (eeepc->hotplug_slot) {
 		port = acpi_get_pci_dev(handle);
 	}
 out_unlock:
+	pci_unlock_rescan_remove();
 	mutex_unlock(&eeepc->hotplug_lock);
 }

drivers/scsi/mpt2sas/mpt2sas_base.c+1−1

@@ -128,7 +128,7 @@ static int mpt2sas_remove_dead_ioc_func(void *arg) · 127 unmodified lines
128	pdev = ioc->pdev;	128	pdev = ioc->pdev;
129	if ((pdev == NULL))	129	if ((pdev == NULL))
130	return -1;	130	return -1;
131	pci_stop_and_remove_bus_device(pdev);	131	pci_stop_and_remove_bus_device_locked(pdev);
132	return 0;	132	return 0;
133	}	133	}
134		134

drivers/scsi/mpt3sas/mpt3sas_base.c+1−1

@@ -131,7 +131,7 @@ static int mpt3sas_remove_dead_ioc_func(void *arg) · 130 unmodified lines
131	pdev = ioc->pdev;	131	pdev = ioc->pdev;
132	if ((pdev == NULL))	132	if ((pdev == NULL))
133	return -1;	133	return -1;
134	pci_stop_and_remove_bus_device(pdev);	134	pci_stop_and_remove_bus_device_locked(pdev);
135	return 0;	135	return 0;
136	}	136	}
137		137

drivers/scsi/sym53c8xx_2/sym_glue.c+3−2

 	struct pci_bus_region bus_addr;
 	int i = 2;
-	pcibios_resource_to_bus(pdev, &bus_addr, &pdev->resource[1]);
+	pcibios_resource_to_bus(pdev->bus, &bus_addr, &pdev->resource[1]);
 	device->mmio_base = bus_addr.start;
 	if (device->chip.features & FE_RAM) {
 		 */
 		if (!pdev->resource[i].flags)
 			i++;
-		pcibios_resource_to_bus(pdev, &bus_addr, &pdev->resource[i]);
+		pcibios_resource_to_bus(pdev->bus, &bus_addr,
+					&pdev->resource[i]);
 		device->ram_base = bus_addr.start;
 	}

drivers/vfio/pci/vfio_pci.c+9−20

@@ -139,25 +139,14 @@ static void vfio_pci_disable(struct vfio_pci_device *vdev) · 138 unmodified lines
139	pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);	139	pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
140		140
141	/*	141	/*
142	* Careful, device_lock may already be held. This is the case if	142	* Try to reset the device. The success of this is dependent on
143	* a driver unbind is blocked. Try to get the locks ourselves to	143	* being able to lock the device, which is not always possible.
144	* prevent a deadlock.
145	*/	144	*/
146	if (vdev->reset_works) {	145	if (vdev->reset_works) {
147	bool reset_done = false;	146	int ret = pci_try_reset_function(pdev);
148		147	if (ret)
149	if (pci_cfg_access_trylock(pdev)) {	148	pr_warn("%s: Failed to reset device %s (%d)\n",
150	if (device_trylock(&pdev->dev)) {	149	__func__, dev_name(&pdev->dev), ret);
151	__pci_reset_function_locked(pdev);
152	reset_done = true;
153	device_unlock(&pdev->dev);
154	}
155	pci_cfg_access_unlock(pdev);
156	}
157
158	if (!reset_done)
159	pr_warn("%s: Unable to acquire locks for reset of %s\n",
160	__func__, dev_name(&pdev->dev));
161	}	150	}
162		151
163	pci_restore_state(pdev);	152	pci_restore_state(pdev);
@@ -514,7 +503,7 @@ static long vfio_pci_ioctl(void *device_data, · 350 unmodified lines
514		503
515	} else if (cmd == VFIO_DEVICE_RESET) {	504	} else if (cmd == VFIO_DEVICE_RESET) {
516	return vdev->reset_works ?	505	return vdev->reset_works ?
517	pci_reset_function(vdev->pdev) : -EINVAL;	506	pci_try_reset_function(vdev->pdev) : -EINVAL;
518		507
519	} else if (cmd == VFIO_DEVICE_GET_PCI_HOT_RESET_INFO) {	508	} else if (cmd == VFIO_DEVICE_GET_PCI_HOT_RESET_INFO) {
520	struct vfio_pci_hot_reset_info hdr;	509	struct vfio_pci_hot_reset_info hdr;
@@ -684,8 +673,8 @@ reset_info_exit: · 163 unmodified lines
684	&info, slot);	673	&info, slot);
685	if (!ret)	674	if (!ret)
686	/* User has access, do the reset */	675	/* User has access, do the reset */
687	ret = slot ? pci_reset_slot(vdev->pdev->slot) :	676	ret = slot ? pci_try_reset_slot(vdev->pdev->slot) :
688	pci_reset_bus(vdev->pdev->bus);	677	pci_try_reset_bus(vdev->pdev->bus);
689		678
690	hot_reset_release:	679	hot_reset_release:
691	for (i--; i >= 0; i--)	680	for (i--; i >= 0; i--)

drivers/vfio/pci/vfio_pci_config.c+6−6

@@ -975,20 +975,20 @@ static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos) · 974 unmodified lines
975	int ret, evcc, phases, vc_arb;	975	int ret, evcc, phases, vc_arb;
976	int len = PCI_CAP_VC_BASE_SIZEOF;	976	int len = PCI_CAP_VC_BASE_SIZEOF;
977		977
978	ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_REG1, &tmp);	978	ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp);
979	if (ret)	979	if (ret)
980	return pcibios_err_to_errno(ret);	980	return pcibios_err_to_errno(ret);
981		981
982	evcc = tmp & PCI_VC_REG1_EVCC; /* extended vc count */	982	evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */
983	ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_REG2, &tmp);	983	ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp);
984	if (ret)	984	if (ret)
985	return pcibios_err_to_errno(ret);	985	return pcibios_err_to_errno(ret);
986		986
987	if (tmp & PCI_VC_REG2_128_PHASE)	987	if (tmp & PCI_VC_CAP2_128_PHASE)
988	phases = 128;	988	phases = 128;
989	else if (tmp & PCI_VC_REG2_64_PHASE)	989	else if (tmp & PCI_VC_CAP2_64_PHASE)
990	phases = 64;	990	phases = 64;
991	else if (tmp & PCI_VC_REG2_32_PHASE)	991	else if (tmp & PCI_VC_CAP2_32_PHASE)
992	phases = 32;	992	phases = 32;
993	else	993	else
994	phases = 0;	994	phases = 0;

drivers/video/arkfb.c+1−1

@@ -1014,7 +1014,7 @@ static int ark_pci_probe(struct pci_dev dev, const struct pci_device_id id) · 1013 unmodified lines
1014		1014
1015	vga_res.flags = IORESOURCE_IO;	1015	vga_res.flags = IORESOURCE_IO;
1016		1016
1017	pcibios_bus_to_resource(dev, &vga_res, &bus_reg);	1017	pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
1018		1018
1019	par->state.vgabase = (void __iomem *) vga_res.start;	1019	par->state.vgabase = (void __iomem *) vga_res.start;
1020		1020

drivers/video/s3fb.c+1−1

@@ -1180,7 +1180,7 @@ static int s3_pci_probe(struct pci_dev dev, const struct pci_device_id id) · 1179 unmodified lines
1180		1180
1181	vga_res.flags = IORESOURCE_IO;	1181	vga_res.flags = IORESOURCE_IO;
1182		1182
1183	pcibios_bus_to_resource(dev, &vga_res, &bus_reg);	1183	pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
1184		1184
1185	par->state.vgabase = (void __iomem *) vga_res.start;	1185	par->state.vgabase = (void __iomem *) vga_res.start;
1186		1186

drivers/video/vt8623fb.c+1−1

@@ -729,7 +729,7 @@ static int vt8623_pci_probe(struct pci_dev dev, const struct pci_device_id id) · 728 unmodified lines
729		729
730	vga_res.flags = IORESOURCE_IO;	730	vga_res.flags = IORESOURCE_IO;
731		731
732	pcibios_bus_to_resource(dev, &vga_res, &bus_reg);	732	pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
733		733
734	par->state.vgabase = (void __iomem *) vga_res.start;	734	par->state.vgabase = (void __iomem *) vga_res.start;
735		735

include/acpi/actbl1.h+9−1

 	u8 enabled;
 	u32 records_to_preallocate;
 	u32 max_sections_per_record;
-	u32 bus;
+	u32 bus;		/* Bus and Segment numbers */
 	u16 device;
 	u16 function;
 	u16 device_control;
 #define ACPI_HEST_FIRMWARE_FIRST        (1)
 #define ACPI_HEST_GLOBAL                (1<<1)
+/*
+ * Macros to access the bus/segment numbers in Bus field above:
+ *  Bus number is encoded in bits 7:0
+ *  Segment number is encoded in bits 23:8
+ */
+#define ACPI_HEST_BUS(bus)              ((bus) & 0xFF)
+#define ACPI_HEST_SEGMENT(bus)          (((bus) >> 8) & 0xFFFF)
 /* Hardware Error Notification */
 struct acpi_hest_notify {

include/linux/msi.h+2−2

@@ -60,10 +60,10 @@ void arch_teardown_msi_irq(unsigned int irq); · 59 unmodified lines
60	int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);	60	int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
61	void arch_teardown_msi_irqs(struct pci_dev *dev);	61	void arch_teardown_msi_irqs(struct pci_dev *dev);
62	int arch_msi_check_device(struct pci_dev* dev, int nvec, int type);	62	int arch_msi_check_device(struct pci_dev* dev, int nvec, int type);
63	void arch_restore_msi_irqs(struct pci_dev *dev, int irq);	63	void arch_restore_msi_irqs(struct pci_dev *dev);
64		64
65	void default_teardown_msi_irqs(struct pci_dev *dev);	65	void default_teardown_msi_irqs(struct pci_dev *dev);
66	void default_restore_msi_irqs(struct pci_dev *dev, int irq);	66	void default_restore_msi_irqs(struct pci_dev *dev);
67	u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);	67	u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
68	u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag);	68	u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag);
69		69

include/linux/pci-ats.h+0−17

 int pci_enable_pri(struct pci_dev *pdev, u32 reqs);
 void pci_disable_pri(struct pci_dev *pdev);
-bool pci_pri_enabled(struct pci_dev *pdev);
 int pci_reset_pri(struct pci_dev *pdev);
-bool pci_pri_stopped(struct pci_dev *pdev);
-int pci_pri_status(struct pci_dev *pdev);
 #else /* CONFIG_PCI_PRI */
 {
 }
-static inline bool pci_pri_enabled(struct pci_dev *pdev)
-{
-	return false;
-}
 static inline int pci_reset_pri(struct pci_dev *pdev)
 {
 	return -ENODEV;
 }
-static inline bool pci_pri_stopped(struct pci_dev *pdev)
-{
-	return true;
-}
-static inline int pci_pri_status(struct pci_dev *pdev)
-{
-	return -ENODEV;
-}
 #endif /* CONFIG_PCI_PRI */
 #ifdef CONFIG_PCI_PASID

include/linux/pci.h+107−245

@@ -224,7 +224,8 @@ enum pci_bus_speed { · 223 unmodified lines
224	};	224	};
225		225
226	struct pci_cap_saved_data {	226	struct pci_cap_saved_data {
227	char cap_nr;	227	u16 cap_nr;
		228	bool cap_extended;
228	unsigned int size;	229	unsigned int size;
229	u32 data[0];	230	u32 data[0];
230	};	231	};
@@ -351,7 +352,7 @@ struct pci_dev { · 120 unmodified lines
351	struct bin_attribute res_attr_wc[DEVICE_COUNT_RESOURCE]; / sysfs file for WC mapping of resources */	352	struct bin_attribute res_attr_wc[DEVICE_COUNT_RESOURCE]; / sysfs file for WC mapping of resources */
352	#ifdef CONFIG_PCI_MSI	353	#ifdef CONFIG_PCI_MSI
353	struct list_head msi_list;	354	struct list_head msi_list;
354	struct kset *msi_kset;	355	const struct attribute_group **msi_irq_groups;
355	#endif	356	#endif
356	struct pci_vpd *vpd;	357	struct pci_vpd *vpd;
357	#ifdef CONFIG_PCI_ATS	358	#ifdef CONFIG_PCI_ATS
@@ -375,7 +376,6 @@ static inline struct pci_dev pci_physfn(struct pci_dev dev) · 17 unmodified lines
375	}	376	}
376		377
377	struct pci_dev pci_alloc_dev(struct pci_bus bus);	378	struct pci_dev pci_alloc_dev(struct pci_bus bus);
378	struct pci_dev * __deprecated alloc_pci_dev(void);
379		379
380	#define to_pci_dev(n) container_of(n, struct pci_dev, dev)	380	#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
381	#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)	381	#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
@@ -385,8 +385,6 @@ static inline int pci_channel_offline(struct pci_dev *pdev) · 3 unmodified lines
385	return (pdev->error_state != pci_channel_io_normal);	385	return (pdev->error_state != pci_channel_io_normal);
386	}	386	}
387		387
388	extern struct resource busn_resource;
389
390	struct pci_host_bridge_window {	388	struct pci_host_bridge_window {
391	struct list_head list;	389	struct list_head list;
392	struct resource res; / host bridge aperture (CPU address) */	390	struct resource res; / host bridge aperture (CPU address) */
@@ -551,8 +549,8 @@ int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, · 158 unmodified lines
551	int reg, int len, u32 val);	549	int reg, int len, u32 val);
552		550
553	struct pci_bus_region {	551	struct pci_bus_region {
554	resource_size_t start;	552	dma_addr_t start;
555	resource_size_t end;	553	dma_addr_t end;
556	};	554	};
557		555
558	struct pci_dynids {	556	struct pci_dynids {
@@ -634,8 +632,7 @@ struct pci_driver { · 75 unmodified lines
634	* DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table	632	* DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
635	* @_table: device table name	633	* @_table: device table name
636	*	634	*
637	* This macro is used to create a struct pci_device_id array (a device table)	635	* This macro is deprecated and should not be used in new code.
638	* in a generic manner.
639	*/	636	*/
640	#define DEFINE_PCI_DEVICE_TABLE(_table) \	637	#define DEFINE_PCI_DEVICE_TABLE(_table) \
641	const struct pci_device_id _table[]	638	const struct pci_device_id _table[]
@@ -737,9 +734,9 @@ void pci_fixup_cardbus(struct pci_bus *); · 95 unmodified lines
737		734
738	/* Generic PCI functions used internally */	735	/* Generic PCI functions used internally */
739		736
740	void pcibios_resource_to_bus(struct pci_dev dev, struct pci_bus_region region,	737	void pcibios_resource_to_bus(struct pci_bus bus, struct pci_bus_region region,
741	struct resource *res);	738	struct resource *res);
742	void pcibios_bus_to_resource(struct pci_dev dev, struct resource res,	739	void pcibios_bus_to_resource(struct pci_bus bus, struct resource res,
743	struct pci_bus_region *region);	740	struct pci_bus_region *region);
744	void pcibios_scan_specific_bus(int busn);	741	void pcibios_scan_specific_bus(int busn);
745	struct pci_bus *pci_find_bus(int domain, int busnr);	742	struct pci_bus *pci_find_bus(int domain, int busnr);
@@ -763,7 +760,6 @@ struct pci_slot pci_create_slot(struct pci_bus parent, int slot_nr, · 17 unmodified lines
763	const char *name,	760	const char *name,
764	struct hotplug_slot *hotplug);	761	struct hotplug_slot *hotplug);
765	void pci_destroy_slot(struct pci_slot *slot);	762	void pci_destroy_slot(struct pci_slot *slot);
766	void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
767	int pci_scan_slot(struct pci_bus *bus, int devfn);	763	int pci_scan_slot(struct pci_bus *bus, int devfn);
768	struct pci_dev pci_scan_single_device(struct pci_bus bus, int devfn);	764	struct pci_dev pci_scan_single_device(struct pci_bus bus, int devfn);
769	void pci_device_add(struct pci_dev dev, struct pci_bus bus);	765	void pci_device_add(struct pci_dev dev, struct pci_bus bus);
@@ -779,6 +775,7 @@ struct pci_dev pci_dev_get(struct pci_dev dev); · 9 unmodified lines
779	void pci_dev_put(struct pci_dev *dev);	775	void pci_dev_put(struct pci_dev *dev);
780	void pci_remove_bus(struct pci_bus *b);	776	void pci_remove_bus(struct pci_bus *b);
781	void pci_stop_and_remove_bus_device(struct pci_dev *dev);	777	void pci_stop_and_remove_bus_device(struct pci_dev *dev);
		778	void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
782	void pci_stop_root_bus(struct pci_bus *bus);	779	void pci_stop_root_bus(struct pci_bus *bus);
783	void pci_remove_root_bus(struct pci_bus *bus);	780	void pci_remove_root_bus(struct pci_bus *bus);
784	void pci_setup_cardbus(struct pci_bus *bus);	781	void pci_setup_cardbus(struct pci_bus *bus);
@@ -938,6 +935,7 @@ bool pci_check_and_unmask_intx(struct pci_dev *dev); · 153 unmodified lines
938	void pci_msi_off(struct pci_dev *dev);	935	void pci_msi_off(struct pci_dev *dev);
939	int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);	936	int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
940	int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);	937	int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
		938	int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
941	int pci_wait_for_pending_transaction(struct pci_dev *dev);	939	int pci_wait_for_pending_transaction(struct pci_dev *dev);
942	int pcix_get_max_mmrbc(struct pci_dev *dev);	940	int pcix_get_max_mmrbc(struct pci_dev *dev);
943	int pcix_get_mmrbc(struct pci_dev *dev);	941	int pcix_get_mmrbc(struct pci_dev *dev);
@@ -951,10 +949,13 @@ int pcie_get_minimum_link(struct pci_dev dev, enum pci_bus_speed speed, · 7 unmodified lines
951	int __pci_reset_function(struct pci_dev *dev);	949	int __pci_reset_function(struct pci_dev *dev);
952	int __pci_reset_function_locked(struct pci_dev *dev);	950	int __pci_reset_function_locked(struct pci_dev *dev);
953	int pci_reset_function(struct pci_dev *dev);	951	int pci_reset_function(struct pci_dev *dev);
		952	int pci_try_reset_function(struct pci_dev *dev);
954	int pci_probe_reset_slot(struct pci_slot *slot);	953	int pci_probe_reset_slot(struct pci_slot *slot);
955	int pci_reset_slot(struct pci_slot *slot);	954	int pci_reset_slot(struct pci_slot *slot);
		955	int pci_try_reset_slot(struct pci_slot *slot);
956	int pci_probe_reset_bus(struct pci_bus *bus);	956	int pci_probe_reset_bus(struct pci_bus *bus);
957	int pci_reset_bus(struct pci_bus *bus);	957	int pci_reset_bus(struct pci_bus *bus);
		958	int pci_try_reset_bus(struct pci_bus *bus);
958	void pci_reset_bridge_secondary_bus(struct pci_dev *dev);	959	void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
959	void pci_update_resource(struct pci_dev *dev, int resno);	960	void pci_update_resource(struct pci_dev *dev, int resno);
960	int __must_check pci_assign_resource(struct pci_dev *dev, int i);	961	int __must_check pci_assign_resource(struct pci_dev *dev, int i);
@@ -974,9 +975,14 @@ void __iomem __must_check pci_platform_rom(struct pci_dev pdev, size_t *size); · 13 unmodified lines
974	int pci_save_state(struct pci_dev *dev);	975	int pci_save_state(struct pci_dev *dev);
975	void pci_restore_state(struct pci_dev *dev);	976	void pci_restore_state(struct pci_dev *dev);
976	struct pci_saved_state pci_store_saved_state(struct pci_dev dev);	977	struct pci_saved_state pci_store_saved_state(struct pci_dev dev);
977	int pci_load_saved_state(struct pci_dev dev, struct pci_saved_state state);
978	int pci_load_and_free_saved_state(struct pci_dev *dev,	978	int pci_load_and_free_saved_state(struct pci_dev *dev,
979	struct pci_saved_state **state);	979	struct pci_saved_state **state);
		980	struct pci_cap_saved_state pci_find_saved_cap(struct pci_dev dev, char cap);
		981	struct pci_cap_saved_state pci_find_saved_ext_cap(struct pci_dev dev,
		982	u16 cap);
		983	int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
		984	int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
		985	u16 cap, unsigned int size);
980	int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);	986	int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
981	int pci_set_power_state(struct pci_dev *dev, pci_power_t state);	987	int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
982	pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);	988	pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
@@ -985,7 +991,6 @@ void pci_pme_active(struct pci_dev *dev, bool enable); · 2 unmodified lines
985	int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,	991	int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
986	bool runtime, bool enable);	992	bool runtime, bool enable);
987	int pci_wake_from_d3(struct pci_dev *dev, bool enable);	993	int pci_wake_from_d3(struct pci_dev *dev, bool enable);
988	pci_power_t pci_target_state(struct pci_dev *dev);
989	int pci_prepare_to_sleep(struct pci_dev *dev);	994	int pci_prepare_to_sleep(struct pci_dev *dev);
990	int pci_back_from_sleep(struct pci_dev *dev);	995	int pci_back_from_sleep(struct pci_dev *dev);
991	bool pci_dev_run_wake(struct pci_dev *dev);	996	bool pci_dev_run_wake(struct pci_dev *dev);
@@ -998,21 +1003,10 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, · 6 unmodified lines
998	return __pci_enable_wake(dev, state, false, enable);	1003	return __pci_enable_wake(dev, state, false, enable);
999	}	1004	}
1000		1005
1001	#define PCI_EXP_IDO_REQUEST (1<<0)	1006	/* PCI Virtual Channel */
1002	#define PCI_EXP_IDO_COMPLETION (1<<1)	1007	int pci_save_vc_state(struct pci_dev *dev);
1003	void pci_enable_ido(struct pci_dev *dev, unsigned long type);	1008	void pci_restore_vc_state(struct pci_dev *dev);
1004	void pci_disable_ido(struct pci_dev *dev, unsigned long type);	1009	void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1005
1006	enum pci_obff_signal_type {
1007	PCI_EXP_OBFF_SIGNAL_L0 = 0,
1008	PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
1009	};
1010	int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
1011	void pci_disable_obff(struct pci_dev *dev);
1012
1013	int pci_enable_ltr(struct pci_dev *dev);
1014	void pci_disable_ltr(struct pci_dev *dev);
1015	int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
1016		1010
1017	/* For use by arch with custom probe code */	1011	/* For use by arch with custom probe code */
1018	void set_pcie_port_type(struct pci_dev *pdev);	1012	void set_pcie_port_type(struct pci_dev *pdev);
@@ -1022,11 +1016,12 @@ void set_pcie_hotplug_bridge(struct pci_dev *pdev); · 3 unmodified lines
1022	int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);	1016	int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1023	unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);	1017	unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1024	unsigned int pci_rescan_bus(struct pci_bus *bus);	1018	unsigned int pci_rescan_bus(struct pci_bus *bus);
		1019	void pci_lock_rescan_remove(void);
		1020	void pci_unlock_rescan_remove(void);
1025		1021
1026	/* Vital product data routines */	1022	/* Vital product data routines */
1027	ssize_t pci_read_vpd(struct pci_dev dev, loff_t pos, size_t count, void buf);	1023	ssize_t pci_read_vpd(struct pci_dev dev, loff_t pos, size_t count, void buf);
1028	ssize_t pci_write_vpd(struct pci_dev dev, loff_t pos, size_t count, const void buf);	1024	ssize_t pci_write_vpd(struct pci_dev dev, loff_t pos, size_t count, const void buf);
1029	int pci_vpd_truncate(struct pci_dev *dev, size_t size);
1030		1025
1031	/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */	1026	/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1032	resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);	1027	resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
@@ -1078,6 +1073,14 @@ int __must_check pci_bus_alloc_resource(struct pci_bus *bus, · 45 unmodified lines
1078	resource_size_t),	1073	resource_size_t),
1079	void *alignf_data);	1074	void *alignf_data);
1080		1075
		1076	static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
		1077	{
		1078	struct pci_bus_region region;
		1079
		1080	pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
		1081	return region.start;
		1082	}
		1083
1081	/* Proper probing supporting hot-pluggable devices */	1084	/* Proper probing supporting hot-pluggable devices */
1082	int __must_check __pci_register_driver(struct pci_driver , struct module ,	1085	int __must_check __pci_register_driver(struct pci_driver , struct module ,
1083	const char *mod_name);	1086	const char *mod_name);
@@ -1115,7 +1118,6 @@ int pci_scan_bridge(struct pci_bus bus, struct pci_dev dev, int max, · 31 unmodified lines
1115		1118
1116	void pci_walk_bus(struct pci_bus top, int (cb)(struct pci_dev , void ),	1119	void pci_walk_bus(struct pci_bus top, int (cb)(struct pci_dev , void ),
1117	void *userdata);	1120	void *userdata);
1118	int pci_cfg_space_size_ext(struct pci_dev *dev);
1119	int pci_cfg_space_size(struct pci_dev *dev);	1121	int pci_cfg_space_size(struct pci_dev *dev);
1120	unsigned char pci_bus_max_busnr(struct pci_bus *bus);	1122	unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1121	void pci_setup_bridge(struct pci_bus *bus);	1123	void pci_setup_bridge(struct pci_bus *bus);
@@ -1154,59 +1156,42 @@ struct msix_entry { · 32 unmodified lines
1154	};	1156	};
1155		1157
1156		1158
1157	#ifndef CONFIG_PCI_MSI	1159	#ifdef CONFIG_PCI_MSI
1158	static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)	1160	int pci_msi_vec_count(struct pci_dev *dev);
1159	{	1161	int pci_enable_msi_block(struct pci_dev *dev, int nvec);
1160	return -1;
1161	}
1162
1163	static inline int
1164	pci_enable_msi_block_auto(struct pci_dev dev, unsigned int maxvec)
1165	{
1166	return -1;
1167	}
1168
1169	static inline void pci_msi_shutdown(struct pci_dev *dev)
1170	{ }
1171	static inline void pci_disable_msi(struct pci_dev *dev)
1172	{ }
1173
1174	static inline int pci_msix_table_size(struct pci_dev *dev)
1175	{
1176	return 0;
1177	}
1178	static inline int pci_enable_msix(struct pci_dev *dev,
1179	struct msix_entry *entries, int nvec)
1180	{
1181	return -1;
1182	}
1183
1184	static inline void pci_msix_shutdown(struct pci_dev *dev)
1185	{ }
1186	static inline void pci_disable_msix(struct pci_dev *dev)
1187	{ }
1188
1189	static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1190	{ }
1191
1192	static inline void pci_restore_msi_state(struct pci_dev *dev)
1193	{ }
1194	static inline int pci_msi_enabled(void)
1195	{
1196	return 0;
1197	}
1198	#else
1199	int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1200	int pci_enable_msi_block_auto(struct pci_dev dev, unsigned int maxvec);
1201	void pci_msi_shutdown(struct pci_dev *dev);	1162	void pci_msi_shutdown(struct pci_dev *dev);
1202	void pci_disable_msi(struct pci_dev *dev);	1163	void pci_disable_msi(struct pci_dev *dev);
1203	int pci_msix_table_size(struct pci_dev *dev);	1164	int pci_msix_vec_count(struct pci_dev *dev);
1204	int pci_enable_msix(struct pci_dev dev, struct msix_entry entries, int nvec);	1165	int pci_enable_msix(struct pci_dev dev, struct msix_entry entries, int nvec);
1205	void pci_msix_shutdown(struct pci_dev *dev);	1166	void pci_msix_shutdown(struct pci_dev *dev);
1206	void pci_disable_msix(struct pci_dev *dev);	1167	void pci_disable_msix(struct pci_dev *dev);
1207	void msi_remove_pci_irq_vectors(struct pci_dev *dev);	1168	void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1208	void pci_restore_msi_state(struct pci_dev *dev);	1169	void pci_restore_msi_state(struct pci_dev *dev);
1209	int pci_msi_enabled(void);	1170	int pci_msi_enabled(void);
		1171	int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
		1172	int pci_enable_msix_range(struct pci_dev dev, struct msix_entry entries,
		1173	int minvec, int maxvec);
		1174	#else
		1175	static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
		1176	static inline int pci_enable_msi_block(struct pci_dev *dev, int nvec)
		1177	{ return -ENOSYS; }
		1178	static inline void pci_msi_shutdown(struct pci_dev *dev) { }
		1179	static inline void pci_disable_msi(struct pci_dev *dev) { }
		1180	static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
		1181	static inline int pci_enable_msix(struct pci_dev *dev,
		1182	struct msix_entry *entries, int nvec)
		1183	{ return -ENOSYS; }
		1184	static inline void pci_msix_shutdown(struct pci_dev *dev) { }
		1185	static inline void pci_disable_msix(struct pci_dev *dev) { }
		1186	static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) { }
		1187	static inline void pci_restore_msi_state(struct pci_dev *dev) { }
		1188	static inline int pci_msi_enabled(void) { return 0; }
		1189	static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
		1190	int maxvec)
		1191	{ return -ENOSYS; }
		1192	static inline int pci_enable_msix_range(struct pci_dev *dev,
		1193	struct msix_entry *entries, int minvec, int maxvec)
		1194	{ return -ENOSYS; }
1210	#endif	1195	#endif
1211		1196
1212	#ifdef CONFIG_PCIEPORTBUS	1197	#ifdef CONFIG_PCIEPORTBUS
@@ -1217,12 +1202,10 @@ extern bool pcie_ports_auto; · 4 unmodified lines
1217	#define pcie_ports_auto false	1202	#define pcie_ports_auto false
1218	#endif	1203	#endif
1219		1204
1220	#ifndef CONFIG_PCIEASPM	1205	#ifdef CONFIG_PCIEASPM
1221	static inline int pcie_aspm_enabled(void) { return 0; }
1222	static inline bool pcie_aspm_support_enabled(void) { return false; }
1223	#else
1224	int pcie_aspm_enabled(void);
1225	bool pcie_aspm_support_enabled(void);	1206	bool pcie_aspm_support_enabled(void);
		1207	#else
		1208	static inline bool pcie_aspm_support_enabled(void) { return false; }
1226	#endif	1209	#endif
1227		1210
1228	#ifdef CONFIG_PCIEAER	1211	#ifdef CONFIG_PCIEAER
@@ -1233,15 +1216,12 @@ static inline void pci_no_aer(void) { } · 4 unmodified lines
1233	static inline bool pci_aer_available(void) { return false; }	1216	static inline bool pci_aer_available(void) { return false; }
1234	#endif	1217	#endif
1235		1218
1236	#ifndef CONFIG_PCIE_ECRC	1219	#ifdef CONFIG_PCIE_ECRC
1237	static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1238	{
1239	return;
1240	}
1241	static inline void pcie_ecrc_get_policy(char *str) {};
1242	#else
1243	void pcie_set_ecrc_checking(struct pci_dev *dev);	1220	void pcie_set_ecrc_checking(struct pci_dev *dev);
1244	void pcie_ecrc_get_policy(char *str);	1221	void pcie_ecrc_get_policy(char *str);
		1222	#else
		1223	static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
		1224	static inline void pcie_ecrc_get_policy(char *str) { }
1245	#endif	1225	#endif
1246		1226
1247	#define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)	1227	#define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
@@ -1265,15 +1245,8 @@ void pci_cfg_access_unlock(struct pci_dev *dev); · 17 unmodified lines
1265	extern int pci_domains_supported;	1245	extern int pci_domains_supported;
1266	#else	1246	#else
1267	enum { pci_domains_supported = 0 };	1247	enum { pci_domains_supported = 0 };
1268	static inline int pci_domain_nr(struct pci_bus *bus)	1248	static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1269	{	1249	static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1270	return 0;
1271	}
1272
1273	static inline int pci_proc_domain(struct pci_bus *bus)
1274	{
1275	return 0;
1276	}
1277	#endif /* CONFIG_PCI_DOMAINS */	1250	#endif /* CONFIG_PCI_DOMAINS */
1278		1251
1279	/* some architectures require additional setup to direct VGA traffic */	1252	/* some architectures require additional setup to direct VGA traffic */
@@ -1302,180 +1275,88 @@ _PCI_NOP_ALL(write,) · 22 unmodified lines
1302	static inline struct pci_dev *pci_get_device(unsigned int vendor,	1275	static inline struct pci_dev *pci_get_device(unsigned int vendor,
1303	unsigned int device,	1276	unsigned int device,
1304	struct pci_dev *from)	1277	struct pci_dev *from)
1305	{	1278	{ return NULL; }
1306	return NULL;
1307	}
1308		1279
1309	static inline struct pci_dev *pci_get_subsys(unsigned int vendor,	1280	static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1310	unsigned int device,	1281	unsigned int device,
1311	unsigned int ss_vendor,	1282	unsigned int ss_vendor,
1312	unsigned int ss_device,	1283	unsigned int ss_device,
1313	struct pci_dev *from)	1284	struct pci_dev *from)
1314	{	1285	{ return NULL; }
1315	return NULL;
1316	}
1317		1286
1318	static inline struct pci_dev *pci_get_class(unsigned int class,	1287	static inline struct pci_dev *pci_get_class(unsigned int class,
1319	struct pci_dev *from)	1288	struct pci_dev *from)
1320	{	1289	{ return NULL; }
1321	return NULL;
1322	}
1323		1290
1324	#define pci_dev_present(ids) (0)	1291	#define pci_dev_present(ids) (0)
1325	#define no_pci_devices() (1)	1292	#define no_pci_devices() (1)
1326	#define pci_dev_put(dev) do { } while (0)	1293	#define pci_dev_put(dev) do { } while (0)
1327		1294
1328	static inline void pci_set_master(struct pci_dev *dev)	1295	static inline void pci_set_master(struct pci_dev *dev) { }
1329	{ }	1296	static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1330		1297	static inline void pci_disable_device(struct pci_dev *dev) { }
1331	static inline int pci_enable_device(struct pci_dev *dev)
1332	{
1333	return -EIO;
1334	}
1335
1336	static inline void pci_disable_device(struct pci_dev *dev)
1337	{ }
1338
1339	static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)	1298	static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1340	{	1299	{ return -EIO; }
1341	return -EIO;
1342	}
1343
1344	static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)	1300	static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1345	{	1301	{ return -EIO; }
1346	return -EIO;
1347	}
1348
1349	static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,	1302	static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1350	unsigned int size)	1303	unsigned int size)
1351	{	1304	{ return -EIO; }
1352	return -EIO;
1353	}
1354
1355	static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,	1305	static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1356	unsigned long mask)	1306	unsigned long mask)
1357	{	1307	{ return -EIO; }
1358	return -EIO;
1359	}
1360
1361	static inline int pci_assign_resource(struct pci_dev *dev, int i)	1308	static inline int pci_assign_resource(struct pci_dev *dev, int i)
1362	{	1309	{ return -EBUSY; }
1363	return -EBUSY;
1364	}
1365
1366	static inline int __pci_register_driver(struct pci_driver *drv,	1310	static inline int __pci_register_driver(struct pci_driver *drv,
1367	struct module *owner)	1311	struct module *owner)
1368	{	1312	{ return 0; }
1369	return 0;
1370	}
1371
1372	static inline int pci_register_driver(struct pci_driver *drv)	1313	static inline int pci_register_driver(struct pci_driver *drv)
1373	{	1314	{ return 0; }
1374	return 0;	1315	static inline void pci_unregister_driver(struct pci_driver *drv) { }
1375	}
1376
1377	static inline void pci_unregister_driver(struct pci_driver *drv)
1378	{ }
1379
1380	static inline int pci_find_capability(struct pci_dev *dev, int cap)	1316	static inline int pci_find_capability(struct pci_dev *dev, int cap)
1381	{	1317	{ return 0; }
1382	return 0;
1383	}
1384
1385	static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,	1318	static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1386	int cap)	1319	int cap)
1387	{	1320	{ return 0; }
1388	return 0;
1389	}
1390
1391	static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)	1321	static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1392	{	1322	{ return 0; }
1393	return 0;
1394	}
1395		1323
1396	/* Power management related routines */	1324	/* Power management related routines */
1397	static inline int pci_save_state(struct pci_dev *dev)	1325	static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1398	{	1326	static inline void pci_restore_state(struct pci_dev *dev) { }
1399	return 0;
1400	}
1401
1402	static inline void pci_restore_state(struct pci_dev *dev)
1403	{ }
1404
1405	static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)	1327	static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1406	{	1328	{ return 0; }
1407	return 0;
1408	}
1409
1410	static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)	1329	static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1411	{	1330	{ return 0; }
1412	return 0;
1413	}
1414
1415	static inline pci_power_t pci_choose_state(struct pci_dev *dev,	1331	static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1416	pm_message_t state)	1332	pm_message_t state)
1417	{	1333	{ return PCI_D0; }
1418	return PCI_D0;
1419	}
1420
1421	static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,	1334	static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1422	int enable)	1335	int enable)
1423	{	1336	{ return 0; }
1424	return 0;
1425	}
1426
1427	static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1428	{
1429	}
1430
1431	static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1432	{
1433	}
1434
1435	static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1436	{
1437	return 0;
1438	}
1439
1440	static inline void pci_disable_obff(struct pci_dev *dev)
1441	{
1442	}
1443		1337
1444	static inline int pci_request_regions(struct pci_dev dev, const char res_name)	1338	static inline int pci_request_regions(struct pci_dev dev, const char res_name)
1445	{	1339	{ return -EIO; }
1446	return -EIO;	1340	static inline void pci_release_regions(struct pci_dev *dev) { }
1447	}
1448
1449	static inline void pci_release_regions(struct pci_dev *dev)
1450	{ }
1451		1341
1452	#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)	1342	#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1453		1343
1454	static inline void pci_block_cfg_access(struct pci_dev *dev)	1344	static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1455	{ }
1456
1457	static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)	1345	static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1458	{ return 0; }	1346	{ return 0; }
1459		1347	static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1460	static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1461	{ }
1462		1348
1463	static inline struct pci_bus pci_find_next_bus(const struct pci_bus from)	1349	static inline struct pci_bus pci_find_next_bus(const struct pci_bus from)
1464	{ return NULL; }	1350	{ return NULL; }
1465
1466	static inline struct pci_dev pci_get_slot(struct pci_bus bus,	1351	static inline struct pci_dev pci_get_slot(struct pci_bus bus,
1467	unsigned int devfn)	1352	unsigned int devfn)
1468	{ return NULL; }	1353	{ return NULL; }
1469
1470	static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,	1354	static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1471	unsigned int devfn)	1355	unsigned int devfn)
1472	{ return NULL; }	1356	{ return NULL; }
1473		1357
1474	static inline int pci_domain_nr(struct pci_bus *bus)	1358	static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1475	{ return 0; }	1359	static inline struct pci_dev pci_dev_get(struct pci_dev dev) { return NULL; }
1476
1477	static inline struct pci_dev pci_dev_get(struct pci_dev dev)
1478	{ return NULL; }
1479		1360
1480	#define dev_is_pci(d) (false)	1361	#define dev_is_pci(d) (false)
1481	#define dev_is_pf(d) (false)	1362	#define dev_is_pf(d) (false)
@@ -1486,10 +1367,6 @@ static inline struct pci_dev pci_dev_get(struct pci_dev dev) · 4 unmodified lines
1486		1367
1487	#include <asm/pci.h>	1368	#include <asm/pci.h>
1488		1369
1489	#ifndef PCIBIOS_MAX_MEM_32
1490	#define PCIBIOS_MAX_MEM_32 (-1)
1491	#endif
1492
1493	/* these helpers provide future and backwards compatibility	1370	/* these helpers provide future and backwards compatibility
1494	* for accessing popular PCI BAR info */	1371	* for accessing popular PCI BAR info */
1495	#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)	1372	#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
@@ -1635,7 +1512,7 @@ struct pci_dev pci_get_dma_source(struct pci_dev dev); · 139 unmodified lines
1635	int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);	1512	int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1636	#else	1513	#else
1637	static inline void pci_fixup_device(enum pci_fixup_pass pass,	1514	static inline void pci_fixup_device(enum pci_fixup_pass pass,
1638	struct pci_dev *dev) {}	1515	struct pci_dev *dev) { }
1639	static inline struct pci_dev pci_get_dma_source(struct pci_dev dev)	1516	static inline struct pci_dev pci_get_dma_source(struct pci_dev dev)
1640	{	1517	{
1641	return pci_dev_get(dev);	1518	return pci_dev_get(dev);
@@ -1707,32 +1584,17 @@ int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); · 65 unmodified lines
1707	int pci_sriov_get_totalvfs(struct pci_dev *dev);	1584	int pci_sriov_get_totalvfs(struct pci_dev *dev);
1708	#else	1585	#else
1709	static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)	1586	static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1710	{	1587	{ return -ENODEV; }
1711	return -ENODEV;	1588	static inline void pci_disable_sriov(struct pci_dev *dev) { }
1712	}
1713	static inline void pci_disable_sriov(struct pci_dev *dev)
1714	{
1715	}
1716	static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)	1589	static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1717	{	1590	{ return IRQ_NONE; }
1718	return IRQ_NONE;	1591	static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1719	}
1720	static inline int pci_num_vf(struct pci_dev *dev)
1721	{
1722	return 0;
1723	}
1724	static inline int pci_vfs_assigned(struct pci_dev *dev)	1592	static inline int pci_vfs_assigned(struct pci_dev *dev)
1725	{	1593	{ return 0; }
1726	return 0;
1727	}
1728	static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)	1594	static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1729	{	1595	{ return 0; }
1730	return 0;
1731	}
1732	static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)	1596	static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1733	{	1597	{ return 0; }
1734	return 0;
1735	}
1736	#endif	1598	#endif
1737		1599
1738	#if defined(CONFIG_HOTPLUG_PCI) \|\| defined(CONFIG_HOTPLUG_PCI_MODULE)	1600	#if defined(CONFIG_HOTPLUG_PCI) \|\| defined(CONFIG_HOTPLUG_PCI_MODULE)

include/uapi/linux/pci_regs.h+31−6

 #define  PCI_EXP_SLTCTL_CCIE	0x0010	/* Command Completed Interrupt Enable */
 #define  PCI_EXP_SLTCTL_HPIE	0x0020	/* Hot-Plug Interrupt Enable */
 #define  PCI_EXP_SLTCTL_AIC	0x00c0	/* Attention Indicator Control */
+#define  PCI_EXP_SLTCTL_ATTN_IND_ON    0x0040 /* Attention Indicator on */
+#define  PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */
+#define  PCI_EXP_SLTCTL_ATTN_IND_OFF   0x00c0 /* Attention Indicator off */
 #define  PCI_EXP_SLTCTL_PIC	0x0300	/* Power Indicator Control */
+#define  PCI_EXP_SLTCTL_PWR_IND_ON     0x0100 /* Power Indicator on */
+#define  PCI_EXP_SLTCTL_PWR_IND_BLINK  0x0200 /* Power Indicator blinking */
+#define  PCI_EXP_SLTCTL_PWR_IND_OFF    0x0300 /* Power Indicator off */
 #define  PCI_EXP_SLTCTL_PCC	0x0400	/* Power Controller Control */
+#define  PCI_EXP_SLTCTL_PWR_ON         0x0000 /* Power On */
+#define  PCI_EXP_SLTCTL_PWR_OFF        0x0400 /* Power Off */
 #define  PCI_EXP_SLTCTL_EIC	0x0800	/* Electromechanical Interlock Control */
 #define  PCI_EXP_SLTCTL_DLLSCE	0x1000	/* Data Link Layer State Changed Enable */
 #define PCI_EXP_SLTSTA		26	/* Slot Status */
 #define PCI_ERR_ROOT_ERR_SRC	52	/* Error Source Identification */
 /* Virtual Channel */
-#define PCI_VC_PORT_REG1	4
+#define PCI_VC_PORT_CAP1	4
-#define  PCI_VC_REG1_EVCC	0x7	/* extended VC count */
+#define  PCI_VC_CAP1_EVCC	0x00000007	/* extended VC count */
-#define PCI_VC_PORT_REG2	8
+#define  PCI_VC_CAP1_LPEVCC	0x00000070	/* low prio extended VC count */
-#define  PCI_VC_REG2_32_PHASE	0x2
+#define  PCI_VC_CAP1_ARB_SIZE	0x00000c00
-#define  PCI_VC_REG2_64_PHASE	0x4
+#define PCI_VC_PORT_CAP2	8
-#define  PCI_VC_REG2_128_PHASE	0x8
+#define  PCI_VC_CAP2_32_PHASE		0x00000002
+#define  PCI_VC_CAP2_64_PHASE		0x00000004
+#define  PCI_VC_CAP2_128_PHASE		0x00000008
+#define  PCI_VC_CAP2_ARB_OFF		0xff000000
 #define PCI_VC_PORT_CTRL	12
+#define  PCI_VC_PORT_CTRL_LOAD_TABLE	0x00000001
 #define PCI_VC_PORT_STATUS	14
+#define  PCI_VC_PORT_STATUS_TABLE	0x00000001
 #define PCI_VC_RES_CAP		16
+#define  PCI_VC_RES_CAP_32_PHASE	0x00000002
+#define  PCI_VC_RES_CAP_64_PHASE	0x00000004
+#define  PCI_VC_RES_CAP_128_PHASE	0x00000008
+#define  PCI_VC_RES_CAP_128_PHASE_TB	0x00000010
+#define  PCI_VC_RES_CAP_256_PHASE	0x00000020
+#define  PCI_VC_RES_CAP_ARB_OFF		0xff000000
 #define PCI_VC_RES_CTRL		20
+#define  PCI_VC_RES_CTRL_LOAD_TABLE	0x00010000
+#define  PCI_VC_RES_CTRL_ARB_SELECT	0x000e0000
+#define  PCI_VC_RES_CTRL_ID		0x07000000
+#define  PCI_VC_RES_CTRL_ENABLE		0x80000000
 #define PCI_VC_RES_STATUS	26
+#define  PCI_VC_RES_STATUS_TABLE	0x00000001
+#define  PCI_VC_RES_STATUS_NEGO		0x00000002
 #define PCI_CAP_VC_BASE_SIZEOF		0x10
 #define PCI_CAP_VC_PER_VC_SIZEOF	0x0C

scripts/checkpatch.pl+7−4

 				$herecurr);
                }
-# check for declarations of struct pci_device_id
+# check for uses of DEFINE_PCI_DEVICE_TABLE
-		if ($line =~ /\bstruct\s+pci_device_id\s+\w+\s*\[\s*\]\s*\=\s*\{/) {
+		if ($line =~ /\bDEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=/) {
-			WARN("DEFINE_PCI_DEVICE_TABLE",
+			if (WARN("DEFINE_PCI_DEVICE_TABLE",
-			     "Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id\n" . $herecurr);
+				 "Prefer struct pci_device_id over deprecated DEFINE_PCI_DEVICE_TABLE\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/\b(?:static\s+|)DEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=\s*/static const struct pci_device_id $1\[\] = /;
+			}
 		}
 # check for new typedefs, only function parameters and sparse annotations