Pull PCI updates from Bjorn Helgaas: "PCI changes for the v3.14 merge window: Resource management - Change pci_bus_region addresses to dma_addr_t (Bjorn Helgaas) - Support 64-bit AGP BARs (Bjorn Helgaas, Yinghai Lu) - Add pci_bus_address() to get bus address of a BAR (Bjorn Helgaas) - Use pci_resource_start() for CPU address of AGP BARs (Bjorn Helgaas) - Enforce bus address limits in resource allocation (Yinghai Lu) - Allocate 64-bit BARs above 4G when possible (Yinghai Lu) - Convert pcibios_resource_to_bus() to take pci_bus, not pci_dev (Yinghai Lu) PCI device hotplug - Major rescan/remove locking update (Rafael J. Wysocki) - Make ioapic builtin only (not modular) (Yinghai Lu) - Fix release/free issues (Yinghai Lu) - Clean up pciehp (Bjorn Helgaas) - Announce pciehp slot info during enumeration (Bjorn Helgaas) MSI - Add pci_msi_vec_count(), pci_msix_vec_count() (Alexander Gordeev) - Add pci_enable_msi_range(), pci_enable_msix_range() (Alexander Gordeev) - Deprecate "tri-state" interfaces: fail/success/fail+info (Alexander Gordeev) - Export MSI mode using attributes, not kobjects (Greg Kroah-Hartman) - Drop "irq" param from *_restore_msi_irqs() (DuanZhenzhong) SR-IOV - Clear NumVFs when disabling SR-IOV in sriov_init() (ethan.zhao) Virtualization - Add support for save/restore of extended capabilities (Alex Williamson) - Add Virtual Channel to save/restore support (Alex Williamson) - Never treat a VF as a multifunction device (Alex Williamson) - Add pci_try_reset_function(), et al (Alex Williamson) AER - Ignore non-PCIe error sources (Betty Dall) - Support ACPI HEST error sources for domains other than 0 (Betty Dall) - Consolidate HEST error source parsers (Bjorn Helgaas) - Add a TLP header print helper (Borislav Petkov) Freescale i.MX6 - Remove unnecessary code (Fabio Estevam) - Make reset-gpio optional (Marek Vasut) - Report "link up" only after link training completes (Marek Vasut) - Start link in Gen1 before negotiating for Gen2 mode (Marek Vasut) - Fix PCIe startup code (Richard Zhu) Marvell MVEBU - Remove duplicate of_clk_get_by_name() call (Andrew Lunn) - Drop writes to bridge Secondary Status register (Jason Gunthorpe) - Obey bridge PCI_COMMAND_MEM and PCI_COMMAND_IO bits (Jason Gunthorpe) - Support a bridge with no IO port window (Jason Gunthorpe) - Use max_t() instead of max(resource_size_t,) (Jingoo Han) - Remove redundant of_match_ptr (Sachin Kamat) - Call pci_ioremap_io() at startup instead of dynamically (Thomas Petazzoni) NVIDIA Tegra - Disable Gen2 for Tegra20 and Tegra30 (Eric Brower) Renesas R-Car - Add runtime PM support (Valentine Barshak) - Fix rcar_pci_probe() return value check (Wei Yongjun) Synopsys DesignWare - Fix crash in dw_msi_teardown_irq() (Bjørn Erik Nilsen) - Remove redundant call to pci_write_config_word() (Bjørn Erik Nilsen) - Fix missing MSI IRQs (Harro Haan) - Add dw_pcie prefix before cfg_read/write (Pratyush Anand) - Fix I/O transfers by using CPU (not realio) address (Pratyush Anand) - Whitespace cleanup (Jingoo Han) EISA - Call put_device() if device_register() fails (Levente Kurusa) - Revert EISA initialization breakage ((Bjorn Helgaas) Miscellaneous - Remove unused code, including PCIe 3.0 interfaces (Stephen Hemminger) - Prevent bus conflicts while checking for bridge apertures (Bjorn Helgaas) - Stop clearing bridge Secondary Status when setting up I/O aperture (Bjorn Helgaas) - Use dev_is_pci() to identify PCI devices (Yijing Wang) - Deprecate DEFINE_PCI_DEVICE_TABLE (Joe Perches) - Update documentation 00-INDEX (Erik Ekman)" * tag 'pci-v3.14-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (119 commits) Revert "EISA: Initialize device before its resources" Revert "EISA: Log device resources in dmesg" vfio-pci: Use pci "try" reset interface PCI: Check parent kobject in pci_destroy_dev() xen/pcifront: Use global PCI rescan-remove locking powerpc/eeh: Use global PCI rescan-remove locking PCI: Fix pci_check_and_unmask_intx() comment typos PCI: Add pci_try_reset_function(), pci_try_reset_slot(), pci_try_reset_bus() MPT / PCI: Use pci_stop_and_remove_bus_device_locked() platform / x86: Use global PCI rescan-remove locking PCI: hotplug: Use global PCI rescan-remove locking pcmcia: Use global PCI rescan-remove locking ACPI / hotplug / PCI: Use global PCI rescan-remove locking ACPI / PCI: Use global PCI rescan-remove locking in PCI root hotplug PCI: Add global pci_lock_rescan_remove() PCI: Cleanup pci.h whitespace PCI: Reorder so actual code comes before stubs PCI/AER: Support ACPI HEST AER error sources for PCI domains other than 0 ACPICA: Add helper macros to extract bus/segment numbers from HEST table. PCI: Make local functions static ...
Showing the changes to include/uapi/linux (1 of 109 files). Show all
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| @@ -518,8 +518,16 @@ · 517 unmodified lines | |||
| 518 | #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ | 518 | #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ |
| 519 | #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ | 519 | #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ |
| 520 | #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ | 520 | #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ |
| 521 | #define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 /* Attention Indicator on */ | ||
| 522 | #define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */ | ||
| 523 | #define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 /* Attention Indicator off */ | ||
| 521 | #define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */ | 524 | #define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */ |
| 525 | #define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 /* Power Indicator on */ | ||
| 526 | #define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 /* Power Indicator blinking */ | ||
| 527 | #define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 /* Power Indicator off */ | ||
| 522 | #define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */ | 528 | #define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */ |
| 529 | #define PCI_EXP_SLTCTL_PWR_ON 0x0000 /* Power On */ | ||
| 530 | #define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */ | ||
| 523 | #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ | 531 | #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ |
| 524 | #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ | 532 | #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ |
| 525 | #define PCI_EXP_SLTSTA 26 /* Slot Status */ | 533 | #define PCI_EXP_SLTSTA 26 /* Slot Status */ |
| @@ -677,17 +685,34 @@ · 151 unmodified lines | |||
| 677 | #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ | 685 | #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ |
| 678 | 686 | ||
| 679 | /* Virtual Channel */ | 687 | /* Virtual Channel */ |
| 680 | #define PCI_VC_PORT_REG1 4 | 688 | #define PCI_VC_PORT_CAP1 4 |
| 681 | #define PCI_VC_REG1_EVCC 0x7 /* extended VC count */ | 689 | #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ |
| 682 | #define PCI_VC_PORT_REG2 8 | 690 | #define PCI_VC_CAP1_LPEVCC 0x00000070 /* low prio extended VC count */ |
| 683 | #define PCI_VC_REG2_32_PHASE 0x2 | 691 | #define PCI_VC_CAP1_ARB_SIZE 0x00000c00 |
| 684 | #define PCI_VC_REG2_64_PHASE 0x4 | 692 | #define PCI_VC_PORT_CAP2 8 |
| 685 | #define PCI_VC_REG2_128_PHASE 0x8 | 693 | #define PCI_VC_CAP2_32_PHASE 0x00000002 |
| 694 | #define PCI_VC_CAP2_64_PHASE 0x00000004 | ||
| 695 | #define PCI_VC_CAP2_128_PHASE 0x00000008 | ||
| 696 | #define PCI_VC_CAP2_ARB_OFF 0xff000000 | ||
| 686 | #define PCI_VC_PORT_CTRL 12 | 697 | #define PCI_VC_PORT_CTRL 12 |
| 698 | #define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 | ||
| 687 | #define PCI_VC_PORT_STATUS 14 | 699 | #define PCI_VC_PORT_STATUS 14 |
| 700 | #define PCI_VC_PORT_STATUS_TABLE 0x00000001 | ||
| 688 | #define PCI_VC_RES_CAP 16 | 701 | #define PCI_VC_RES_CAP 16 |
| 702 | #define PCI_VC_RES_CAP_32_PHASE 0x00000002 | ||
| 703 | #define PCI_VC_RES_CAP_64_PHASE 0x00000004 | ||
| 704 | #define PCI_VC_RES_CAP_128_PHASE 0x00000008 | ||
| 705 | #define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 | ||
| 706 | #define PCI_VC_RES_CAP_256_PHASE 0x00000020 | ||
| 707 | #define PCI_VC_RES_CAP_ARB_OFF 0xff000000 | ||
| 689 | #define PCI_VC_RES_CTRL 20 | 708 | #define PCI_VC_RES_CTRL 20 |
| 709 | #define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 | ||
| 710 | #define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 | ||
| 711 | #define PCI_VC_RES_CTRL_ID 0x07000000 | ||
| 712 | #define PCI_VC_RES_CTRL_ENABLE 0x80000000 | ||
| 690 | #define PCI_VC_RES_STATUS 26 | 713 | #define PCI_VC_RES_STATUS 26 |
| 714 | #define PCI_VC_RES_STATUS_TABLE 0x00000001 | ||
| 715 | #define PCI_VC_RES_STATUS_NEGO 0x00000002 | ||
| 691 | #define PCI_CAP_VC_BASE_SIZEOF 0x10 | 716 | #define PCI_CAP_VC_BASE_SIZEOF 0x10 |
| 692 | #define PCI_CAP_VC_PER_VC_SIZEOF 0x0C | 717 | #define PCI_CAP_VC_PER_VC_SIZEOF 0x0C |
| 693 | 718 | ||