In order to get the GSC Support merged on drm-intel-gt-next in a clean fashion we needed this ATS-M patch to avoid conflict in i915_pci.c: commit 412c942bdfae ("drm/i915/ats-m: add ATS-M platform info") -- Fixing a silent conflict on drivers/gpu/drm/i915/gt/intel_gt_gmch.c: - if (!intel_vtd_active(i915)) + if (!i915_vtd_active(i915))
Showing the changes to include/uapi (1 of 150 files). Show all
Unified · Split
| @@ -572,6 +572,53 @@ extern "C" { · 571 unmodified lines | ||
| 572 | 572 | */ |
| 573 | 573 | #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) |
| 574 | 574 | |
| 575 | +/* | |
| 576 | + * Intel Tile 4 layout | |
| 577 | + * | |
| 578 | + * This is a tiled layout using 4KB tiles in a row-major layout. It has the same | |
| 579 | + * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It | |
| 580 | + * only differs from Tile Y at the 256B granularity in between. At this | |
| 581 | + * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape | |
| 582 | + * of 64B x 8 rows. | |
| 583 | + */ | |
| 584 | +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) | |
| 585 | + | |
| 586 | +/* | |
| 587 | + * Intel color control surfaces (CCS) for DG2 render compression. | |
| 588 | + * | |
| 589 | + * The main surface is Tile 4 and at plane index 0. The CCS data is stored | |
| 590 | + * outside of the GEM object in a reserved memory area dedicated for the | |
| 591 | + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The | |
| 592 | + * main surface pitch is required to be a multiple of four Tile 4 widths. | |
| 593 | + */ | |
| 594 | +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10) | |
| 595 | + | |
| 596 | +/* | |
| 597 | + * Intel color control surfaces (CCS) for DG2 media compression. | |
| 598 | + * | |
| 599 | + * The main surface is Tile 4 and at plane index 0. For semi-planar formats | |
| 600 | + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices | |
| 601 | + * 0 and 1, respectively. The CCS for all planes are stored outside of the | |
| 602 | + * GEM object in a reserved memory area dedicated for the storage of the | |
| 603 | + * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface | |
| 604 | + * pitch is required to be a multiple of four Tile 4 widths. | |
| 605 | + */ | |
| 606 | +#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) | |
| 607 | + | |
| 608 | +/* | |
| 609 | + * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression. | |
| 610 | + * | |
| 611 | + * The main surface is Tile 4 and at plane index 0. The CCS data is stored | |
| 612 | + * outside of the GEM object in a reserved memory area dedicated for the | |
| 613 | + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The | |
| 614 | + * main surface pitch is required to be a multiple of four Tile 4 widths. The | |
| 615 | + * clear color is stored at plane index 1 and the pitch should be ignored. The | |
| 616 | + * format of the 256 bits of clear color data matches the one used for the | |
| 617 | + * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description | |
| 618 | + * for details. | |
| 619 | + */ | |
| 620 | +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) | |
| 621 | + | |
| 575 | 622 | /* |
| 576 | 623 | * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks |
| 577 | 624 | * |