History

Merge drm/drm-next into drm-intel-next-queued

Backmerge to get dfce90259d74 ("Backmerge i915 security patches from commit 'ea0b163b13ff' into drm-next") and thus 100d46bd72ec ("Merge Intel Gen8/Gen9 graphics fixes from Jon Bloomfield.").

Jani Nikula committed 7 years ago

Commit e205cee2 parents 1cdc233 17cc5132089 files · +46862 −22417Browse files

Unified · Split

2089 files
  1. .mailmap +7 −1
  2. CREDITS +4 −0
  3. Documentation/admin-guide/cgroup-v2.rst +14 −6
  4. Documentation/admin-guide/kernel-parameters.txt +4 −0
  5. Documentation/arm64/memory.rst +8 −1
  6. Documentation/arm64/silicon-errata.rst +8 −1
  7. Documentation/core-api/index.rst +1 −0
  8. Documentation/core-api/memory-allocation.rst +4 −0
  9. Documentation/core-api/symbol-namespaces.rst +0 −0
  10. Documentation/dev-tools/kasan.rst +3 −0
  11. Documentation/dev-tools/kselftest.rst +16 −0
  12. Documentation/devicetree/bindings/arm/rockchip.yaml +2 −2
  13. Documentation/devicetree/bindings/display/arm,malidp.txt +3 −0
  14. Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt +1 −0
  15. Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt +1 −0
  16. Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +17 −13
  17. Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +2 −2
  18. Documentation/devicetree/bindings/display/renesas,du.txt +2 −0
  19. Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +5 −1
  20. Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt +5 −2
  21. Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml +3 −6
  22. Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +42 −44
  23. Documentation/devicetree/bindings/regulator/fixed-regulator.yaml +2 −2
  24. Documentation/devicetree/bindings/riscv/cpus.yaml +13 −16
  25. Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +2 −0
  26. Documentation/devicetree/bindings/usb/amlogic,dwc3.txt +2 −2
  27. Documentation/devicetree/bindings/usb/generic-ehci.yaml +6 −1
  28. Documentation/devicetree/bindings/usb/generic-ohci.yaml +6 −1
  29. Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt +2 −2
  30. Documentation/devicetree/bindings/usb/mediatek,mtu3.txt +2 −2
  31. Documentation/devicetree/bindings/usb/usb-hcd.yaml +5 −0
  32. Documentation/devicetree/bindings/usb/usb-uhci.txt +1 −1
  33. Documentation/devicetree/bindings/usb/usb-xhci.txt +2 −2
  34. Documentation/driver-api/dma-buf.rst +3 −3
  35. Documentation/gpu/amdgpu.rst +60 −5
  36. Documentation/gpu/drm-kms-helpers.rst +0 −3
  37. Documentation/gpu/todo.rst +104 −23
  38. Documentation/hwmon/index.rst +1 −0
  39. Documentation/hwmon/inspur-ipsps1.rst +1 −1
  40. Documentation/hwmon/k10temp.rst +17 −1
  41. Documentation/networking/device_drivers/intel/e100.rst +7 −7
  42. Documentation/networking/device_drivers/intel/e1000.rst +6 −6
  43. Documentation/networking/device_drivers/intel/e1000e.rst +7 −7
  44. Documentation/networking/device_drivers/intel/fm10k.rst +5 −5
  45. Documentation/networking/device_drivers/intel/i40e.rst +4 −4
  46. Documentation/networking/device_drivers/intel/iavf.rst +4 −4
  47. Documentation/networking/device_drivers/intel/ice.rst +3 −3
  48. Documentation/networking/device_drivers/intel/igb.rst +6 −6
  49. Documentation/networking/device_drivers/intel/igbvf.rst +3 −3
  50. Documentation/networking/device_drivers/intel/ixgbe.rst +5 −5
  51. Documentation/networking/device_drivers/intel/ixgbevf.rst +3 −3
  52. Documentation/networking/device_drivers/pensando/ionic.rst +6 −4
  53. Documentation/networking/ip-sysctl.txt +7 −4
  54. Documentation/networking/net_dim.txt +18 −18
  55. Documentation/networking/tls-offload.rst +4 −0
  56. Documentation/process/coding-style.rst +1 −1
  57. Documentation/process/deprecated.rst +23 −10
  58. Documentation/usb/rio.rst +0 −109
  59. MAINTAINERS +35 −29
  60. Makefile +6 −7
  61. arch/arc/boot/dts/hsdk.dts +23 −0
  62. arch/arc/configs/hsdk_defconfig +6 −0
  63. arch/arc/kernel/perf_event.c +2 −2
  64. arch/arm/boot/dts/am3874-iceboard.dts +1 −8
  65. arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +1 −0
  66. arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi +8 −0
  67. arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi +4 −0
  68. arch/arm/boot/dts/imx6-logicpd-som.dtsi +4 −0
  69. arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +8 −0
  70. arch/arm/boot/dts/imx7s.dtsi +4 −4
  71. arch/arm/boot/dts/logicpd-torpedo-som.dtsi +4 −0
  72. arch/arm/boot/dts/mt7629-rfb.dts +12 −1
  73. arch/arm/boot/dts/mt7629.dtsi +0 −2
  74. arch/arm/boot/dts/omap4-droid4-xt894.dts +1 −1
  75. arch/arm/boot/dts/omap4-panda-common.dtsi +1 −1
  76. arch/arm/boot/dts/omap4-sdp.dts +1 −1
  77. arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi +1 −1
  78. arch/arm/boot/dts/omap5-board-common.dtsi +1 −1
  79. arch/arm/boot/dts/omap54xx-clocks.dtsi +1 −1
  80. arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +4 −4
  81. arch/arm/boot/dts/stm32mp157c-ev1.dts +2 −11
  82. arch/arm/boot/dts/stm32mp157c.dtsi +2 −2
  83. arch/arm/boot/dts/sun4i-a10.dtsi +4 −0
  84. arch/arm/boot/dts/sun5i.dtsi +2 −0
  85. arch/arm/boot/dts/sun6i-a31.dtsi +4 −0
  86. arch/arm/boot/dts/sun7i-a20.dtsi +6 −3
  87. arch/arm/boot/dts/sun8i-a23-a33.dtsi +2 −0
  88. arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +1 −0
  89. arch/arm/boot/dts/sun8i-a83t.dtsi +3 −0
  90. arch/arm/boot/dts/sun8i-r40.dtsi +4 −0
  91. arch/arm/boot/dts/sun9i-a80.dtsi +5 −0
  92. arch/arm/boot/dts/sunxi-h3-h5.dtsi +6 −0
  93. arch/arm/boot/dts/vf610-zii-scu4-aib.dts +2 −0
  94. arch/arm/configs/badge4_defconfig +0 −1
  95. arch/arm/configs/corgi_defconfig +0 −1
  96. arch/arm/configs/davinci_all_defconfig +1 −0
  97. arch/arm/configs/imx_v6_v7_defconfig +1 −0
  98. arch/arm/configs/omap2plus_defconfig +6 −6
  99. arch/arm/configs/pxa_defconfig +0 −1
  100. arch/arm/configs/s3c2410_defconfig +0 −1
  101. arch/arm/configs/spitz_defconfig +0 −1
  102. arch/arm/crypto/Kconfig +1 −0
  103. arch/arm/crypto/aes-ce-core.S +1 −0
  104. arch/arm/include/asm/domain.h +4 −4
  105. arch/arm/include/asm/uaccess.h +2 −2
  106. arch/arm/kernel/head-common.S +3 −2
  107. arch/arm/kernel/head-nommu.S +2 −0
  108. arch/arm/mach-davinci/dm365.c +2 −2
  109. arch/arm/mach-omap2/pdata-quirks.c +11 −0
  110. arch/arm/mach-sunxi/mc_smp.c +5 −1
  111. arch/arm/mm/alignment.c +49 −21
  112. arch/arm/mm/proc-v7m.S +2 −4
  113. arch/arm64/Kconfig +30 −2
  114. arch/arm64/Makefile +0 −16
  115. arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +9 −0
  116. arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +2 −0
  117. arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +6 −0
  118. arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +2 −9
  119. arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +2 −0
  120. arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi +3 −2
  121. arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +1 −2
  122. arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +1 −1
  123. arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +18 −18
  124. arch/arm64/boot/dts/freescale/imx8mm.dtsi +6 −6
  125. arch/arm64/boot/dts/freescale/imx8mn.dtsi +6 −6
  126. arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +3 −3
  127. arch/arm64/boot/dts/freescale/imx8mq.dtsi +2 −2
  128. arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +7 −6
  129. arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +1 −1
  130. arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts +2 −2
  131. arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts +5 −7
  132. arch/arm64/include/asm/asm-uaccess.h +3 −4
  133. arch/arm64/include/asm/atomic_lse.h +4 −2
  134. arch/arm64/include/asm/cpucaps.h +3 −1
  135. arch/arm64/include/asm/cputype.h +2 −0
  136. arch/arm64/include/asm/memory.h +8 −2
  137. arch/arm64/include/asm/pgtable-prot.h +8 −7
  138. arch/arm64/include/asm/pgtable.h +0 −20
  139. arch/arm64/include/asm/sysreg.h +1 −1
  140. arch/arm64/include/asm/vdso/compat_barrier.h +1 −1
  141. arch/arm64/include/asm/vdso/vsyscall.h +0 −7
  142. arch/arm64/include/asm/vdso_datapage.h +0 −33
  143. arch/arm64/kernel/armv8_deprecated.c +5 −0
  144. arch/arm64/kernel/cpu_errata.c +88 −13
  145. arch/arm64/kernel/cpufeature.c +11 −5
  146. arch/arm64/kernel/entry.S +6 −3
  147. arch/arm64/kernel/ftrace.c +9 −3
  148. arch/arm64/kernel/hibernate.c +8 −1
  149. arch/arm64/kernel/process.c +33 −17
  150. arch/arm64/kernel/vdso32/Makefile +28 −16
  151. arch/arm64/kvm/hyp/switch.c +67 −2
  152. arch/arm64/kvm/sys_regs.c +4 −0
  153. arch/arm64/mm/fault.c +16 −3
  154. arch/mips/bcm63xx/prom.c +1 −1
  155. arch/mips/configs/mtx1_defconfig +0 −1
  156. arch/mips/configs/rm200_defconfig +0 −1
  157. arch/mips/fw/sni/sniprom.c +1 −1
  158. arch/mips/include/asm/bmips.h +5 −5
  159. arch/mips/include/asm/cmpxchg.h +5 −4
  160. arch/mips/include/asm/vdso/gettimeofday.h +3 −1
  161. arch/mips/include/asm/vdso/vsyscall.h +0 −7
  162. arch/mips/include/uapi/asm/hwcap.h +11 −0
  163. arch/mips/kernel/cpu-probe.c +33 −0
  164. arch/mips/kernel/smp-bmips.c +4 −4
  165. arch/mips/loongson64/Platform +4 −0
  166. arch/mips/mm/tlbex.c +15 −8
  167. arch/mips/vdso/Makefile +1 −0
  168. arch/parisc/include/asm/cache.h +1 −1
  169. arch/parisc/include/asm/ldcw.h +1 −1
  170. arch/parisc/kernel/entry.S +1 −1
  171. arch/parisc/mm/ioremap.c +7 −5
  172. arch/powerpc/include/asm/book3s/32/kup.h +1 −0
  173. arch/powerpc/include/asm/book3s/64/tlbflush-radix.h +4 −0
  174. arch/powerpc/include/asm/elf.h +3 −0
  175. arch/powerpc/kernel/prom_init.c +13 −0
  176. arch/powerpc/kernel/prom_init_check.sh +2 −1
  177. arch/powerpc/kvm/book3s_hv_rmhandlers.S +1 −0
  178. arch/powerpc/kvm/book3s_xive.c +16 −8
  179. arch/powerpc/kvm/book3s_xive.h +12 −0
  180. arch/powerpc/kvm/book3s_xive_native.c +4 −2
  181. arch/powerpc/net/bpf_jit_comp64.c +13 −0
  182. arch/powerpc/platforms/cell/spufs/inode.c +1 −0
  183. arch/powerpc/platforms/powernv/eeh-powernv.c +1 −1
  184. arch/powerpc/platforms/powernv/smp.c +37 −16
  185. arch/powerpc/platforms/pseries/lpar.c +3 −0
  186. arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts +1 −0
  187. arch/riscv/include/asm/bug.h +3 −13
  188. arch/riscv/include/asm/io.h +7 −0
  189. arch/riscv/include/asm/irq.h +3 −0
  190. arch/riscv/include/asm/pgtable.h +14 −14
  191. arch/riscv/include/asm/switch_to.h +1 −0
  192. arch/riscv/include/asm/tlbflush.h +0 −4
  193. arch/riscv/kernel/cpufeature.c +1 −0
  194. arch/riscv/kernel/entry.S +1 −2
  195. arch/riscv/kernel/head.h +21 −0
  196. arch/riscv/kernel/irq.c +1 −1
  197. arch/riscv/kernel/module-sections.c +1 −0
  198. arch/riscv/kernel/process.c +2 −0
  199. arch/riscv/kernel/ptrace.c +2 −2
  200. arch/riscv/kernel/reset.c +1 −0
  201. arch/riscv/kernel/setup.c +2 −0
  202. arch/riscv/kernel/signal.c +4 −4
  203. arch/riscv/kernel/smp.c +2 −0
  204. arch/riscv/kernel/smpboot.c +4 −1
  205. arch/riscv/kernel/syscall_table.c +1 −0
  206. arch/riscv/kernel/time.c +1 −0
  207. arch/riscv/kernel/traps.c +9 −22
  208. arch/riscv/kernel/vdso.c +2 −1
  209. arch/riscv/mm/context.c +1 −0
  210. arch/riscv/mm/fault.c +2 −0
  211. arch/riscv/mm/init.c +4 −3
  212. arch/riscv/mm/sifive_l2_cache.c +1 −1
  213. arch/s390/boot/startup.c +11 −3
  214. arch/s390/include/asm/uaccess.h +2 −2
  215. arch/s390/include/asm/unwind.h +1 −0
  216. arch/s390/kernel/idle.c +22 −7
  217. arch/s390/kernel/machine_kexec_reloc.c +1 −0
  218. arch/s390/kernel/unwind_bc.c +13 −5
  219. arch/s390/mm/cmm.c +6 −6
  220. arch/sparc/Kconfig +0 −1
  221. arch/um/drivers/ubd_kern.c +6 −2
  222. arch/x86/boot/compressed/acpi.c +24 −24
  223. arch/x86/boot/compressed/eboot.c +3 −1
  224. arch/x86/boot/compressed/misc.c +19 −6
  225. arch/x86/events/amd/core.c +17 −13
  226. arch/x86/events/amd/ibs.c +5 −3
  227. arch/x86/events/intel/core.c +4 −0
  228. arch/x86/events/intel/cstate.c +32 −12
  229. arch/x86/events/intel/pt.c +1 −1
  230. arch/x86/events/intel/uncore.c +38 −6
  231. arch/x86/events/intel/uncore.h +0 −12
  232. arch/x86/events/msr.c +7 −0
  233. arch/x86/hyperv/hv_apic.c +15 −5
  234. arch/x86/include/asm/cpu_entry_area.h +1 −1
  235. arch/x86/include/asm/intel-family.h +3 −0
  236. arch/x86/include/asm/kvm_host.h +1 −1
  237. arch/x86/include/asm/mwait.h +1 −1
  238. arch/x86/include/asm/pti.h +1 −1
  239. arch/x86/include/asm/uaccess.h +23 −0
  240. arch/x86/include/asm/vmware.h +9 −5
  241. arch/x86/kernel/apic/apic.c +15 −13
  242. arch/x86/kernel/apic/x2apic_cluster.c +2 −1
  243. arch/x86/kernel/cpu/mshyperv.c +4 −0
  244. arch/x86/kernel/cpu/resctrl/ctrlmondata.c +4 −0
  245. arch/x86/kernel/cpu/vmware.c +1 −1
  246. arch/x86/kernel/dumpstack_64.c +7 −0
  247. arch/x86/kernel/head64.c +20 −2
  248. arch/x86/kernel/process.h +1 −1
  249. arch/x86/kernel/tsc.c +3 −0
  250. arch/x86/kvm/cpuid.c +1 −1
  251. arch/x86/kvm/lapic.c +0 −5
  252. arch/x86/kvm/lapic.h +5 −0
  253. arch/x86/kvm/svm.c +11 −5
  254. arch/x86/kvm/vmx/nested.c +36 −28
  255. arch/x86/kvm/vmx/nested.h +12 −1
  256. arch/x86/kvm/vmx/vmx.c +3 −23
  257. arch/x86/kvm/x86.c +10 −9
  258. arch/x86/lib/delay.c +2 −2
  259. arch/x86/platform/efi/efi.c +0 −3
  260. arch/x86/xen/enlighten.c +25 −3
  261. arch/x86/xen/enlighten_pv.c +8 −0
  262. arch/xtensa/boot/dts/virt.dts +1 −1
  263. arch/xtensa/include/asm/bitops.h +1 −1
  264. arch/xtensa/include/asm/uaccess.h +53 −41
  265. arch/xtensa/kernel/xtensa_ksyms.c +0 −7
  266. block/blk-cgroup.c +59 −23
  267. block/blk-iocost.c +2 −2
  268. block/blk-rq-qos.c +9 −5
  269. block/blk-rq-qos.h +7 −10
  270. block/blk-wbt.c +4 −2
  271. block/elevator.c +2 −1
  272. drivers/acpi/cppc_acpi.c +1 −1
  273. drivers/acpi/hmat/hmat.c +1 −1
  274. drivers/acpi/nfit/core.c +1 −1
  275. drivers/acpi/processor_driver.c +4 −5
  276. drivers/acpi/processor_perflib.c +25 −15
  277. drivers/acpi/processor_thermal.c +26 −16
  278. drivers/acpi/sleep.c +0 −13
  279. drivers/amba/bus.c +11 −3
  280. drivers/android/binder.c +3 −8
  281. drivers/android/binder_alloc.c +5 −3
  282. drivers/android/binder_internal.h +1 −1
  283. drivers/ata/ahci.c +3 −1
  284. drivers/ata/libahci_platform.c +14 −24
  285. drivers/ata/libata-scsi.c +0 −21
  286. drivers/base/core.c +3 −0
  287. drivers/base/memory.c +3 −0
  288. drivers/base/platform.c +39 −7
  289. drivers/base/power/qos.c +2 −68
  290. drivers/block/drbd/drbd_main.c +0 −1
  291. drivers/block/nbd.c +35 −8
  292. drivers/block/null_blk_zoned.c +1 −2
  293. drivers/block/rbd.c +6 −3
  294. drivers/block/zram/zram_drv.c +3 −2
  295. drivers/bus/ti-sysc.c +14 −4
  296. drivers/clk/at91/clk-main.c +4 −1
  297. drivers/clk/at91/sam9x60.c +1 −0
  298. drivers/clk/at91/sckc.c +16 −4
  299. drivers/clk/clk-ast2600.c +4 −3
  300. drivers/clk/imx/clk-imx8mm.c +1 −1
  301. drivers/clk/imx/clk-imx8mn.c +1 −1
  302. drivers/clk/meson/g12a.c +11 −2
  303. drivers/clk/meson/gxbb.c +1 −0
  304. drivers/clk/samsung/clk-exynos5420.c +25 −2
  305. drivers/clk/samsung/clk-exynos5433.c +12 −2
  306. drivers/clk/sunxi-ng/ccu-sun9i-a80.c +1 −1
  307. drivers/clk/sunxi/clk-sunxi.c +2 −2
  308. drivers/clk/ti/clk-dra7-atl.c +0 −6
  309. drivers/clk/ti/clkctrl.c +3 −2
  310. drivers/clocksource/sh_mtu2.c +11 −5
  311. drivers/clocksource/timer-mediatek.c +2 −8
  312. drivers/cpufreq/cpufreq.c +29 −43
  313. drivers/cpufreq/intel_pstate.c +16 −18
  314. drivers/cpufreq/ppc_cbe_cpufreq_pmi.c +7 −8
  315. drivers/cpuidle/cpuidle-haltpoll.c +4 −0
  316. drivers/crypto/chelsio/chtls/chtls_cm.c +1 −1
  317. drivers/crypto/chelsio/chtls/chtls_io.c +1 −1
  318. drivers/dma-buf/dma-buf.c +95 −25
  319. drivers/dma/imx-sdma.c +8 −0
  320. drivers/dma/qcom/bam_dma.c +19 −0
  321. drivers/dma/sprd-dma.c +25 −2
  322. drivers/dma/tegra210-adma.c +7 −0
  323. drivers/dma/ti/cppi41.c +20 −1
  324. drivers/dma/xilinx/xilinx_dma.c +9 −1
  325. drivers/edac/ghes_edac.c +4 −0
  326. drivers/firmware/dmi_scan.c +1 −1
  327. drivers/firmware/efi/Kconfig +1 −0
  328. drivers/firmware/efi/cper.c +1 −1
  329. drivers/firmware/efi/efi.c +4 −1
  330. drivers/firmware/efi/libstub/Makefile +1 −0
  331. drivers/firmware/efi/libstub/arm32-stub.c +13 −3
  332. drivers/firmware/efi/libstub/efi-stub-helper.c +10 −14
  333. drivers/firmware/efi/rci2-table.c +1 −1
  334. drivers/firmware/efi/test/efi_test.c +8 −0
  335. drivers/firmware/efi/tpm.c +20 −7
  336. drivers/firmware/google/vpd_decode.c +1 −1
  337. drivers/gpio/gpio-eic-sprd.c +4 −3
  338. drivers/gpio/gpio-intel-mid.c +6 −3
  339. drivers/gpio/gpio-lynxpoint.c +6 −4
  340. drivers/gpio/gpio-max77620.c +3 −3
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  1131. drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h +5 −2
  1132. drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h +19 −0
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  1138. drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.h +2 −1
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  1141. drivers/net/ethernet/broadcom/genet/bcmmii.c +41 −3
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  1144. drivers/net/ethernet/cavium/octeon/octeon_mgmt.c +1 −1
  1145. drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c +16 −12
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  1148. drivers/net/ethernet/faraday/ftgmac100.c +12 −13
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  1158. drivers/net/ethernet/hisilicon/hip04_eth.c +9 −7
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  1165. drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.h +1 −1
  1166. drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +37 −2
  1167. drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +2 −1
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  1548. fs/fuse/file.c +8 −6
  1549. fs/fuse/fuse_i.h +4 −0
  1550. fs/fuse/inode.c +4 −0
  1551. fs/fuse/virtio_fs.c +113 −56
  1552. fs/gfs2/ops_fstype.c +14 −7
  1553. fs/io_uring.c +210 −150
  1554. fs/libfs.c +72 −68
  1555. fs/nfs/delegation.c +11 −1
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  1560. fs/ocfs2/aops.c +23 −2
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  1563. fs/ocfs2/journal.c +2 −1
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  1566. fs/proc/meminfo.c +2 −2
  1567. fs/proc/page.c +16 −12
  1568. fs/readdir.c +4 −44
  1569. fs/super.c +4 −1
  1570. fs/tracefs/inode.c +5 −41
  1571. fs/xfs/libxfs/xfs_ag.c +2 −3
  1572. fs/xfs/libxfs/xfs_attr_leaf.c +3 −18
  1573. fs/xfs/libxfs/xfs_bmap.c +4 −2
  1574. fs/xfs/libxfs/xfs_bmap.h +2 −1
  1575. fs/xfs/libxfs/xfs_dir2_block.c +1 −1
  1576. fs/xfs/libxfs/xfs_fs.h +4 −4
  1577. fs/xfs/scrub/refcount.c +1 −2
  1578. fs/xfs/xfs_bmap_util.c +3 −1
  1579. fs/xfs/xfs_buf.c +11 −1
  1580. fs/xfs/xfs_log.c +1 −1
  1581. fs/xfs/xfs_log_recover.c +1 −1
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  1584. include/drm/amd_asic_type.h +29 −27
  1585. include/drm/bridge/dw_hdmi.h +1 −0
  1586. include/drm/drmP.h +0 −103
  1587. include/drm/drm_dp_helper.h +63 −18
  1588. include/drm/drm_dp_mst_helper.h +137 −23
  1589. include/drm/drm_edid.h +4 −1
  1590. include/drm/drm_fb_helper.h +0 −1
  1591. include/drm/drm_gem.h +15 −0
  1592. include/drm/drm_gem_shmem_helper.h +14 −29
  1593. include/drm/drm_gem_ttm_helper.h +2 −0
  1594. include/drm/drm_gem_vram_helper.h +25 −25
  1595. include/drm/drm_os_linux.h +0 −55
  1596. include/drm/drm_plane.h +25 −6
  1597. include/drm/drm_self_refresh_helper.h +2 −1
  1598. include/drm/drm_simple_kms_helper.h +1 −1
  1599. include/drm/gpu_scheduler.h +3 −0
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  1601. include/drm/ttm/ttm_bo_driver.h +5 −21
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  1603. include/drm/ttm/ttm_memory.h +0 −1
  1604. include/drm/ttm/ttm_page_alloc.h +1 −1
  1605. include/linux/bitmap.h +2 −1
  1606. include/linux/bpf.h +2 −2
  1607. include/linux/compiler_attributes.h +17 −0
  1608. include/linux/cpufreq.h +5 −2
  1609. include/linux/device_cgroup.h +4 −15
  1610. include/linux/dma-buf.h +57 −6
  1611. include/linux/dynamic_debug.h +6 −0
  1612. include/linux/efi.h +16 −2
  1613. include/linux/export.h +8 −12
  1614. include/linux/filter.h +0 −1
  1615. include/linux/gfp.h +23 −0
  1616. include/linux/gpio/driver.h +8 −0
  1617. include/linux/host1x.h +18 −8
  1618. include/linux/hwmon.h +1 −1
  1619. include/linux/idr.h +1 −1
  1620. include/linux/if_macvlan.h +0 −1
  1621. include/linux/if_team.h +1 −0
  1622. include/linux/if_vlan.h +0 −11
  1623. include/linux/leds.h +2 −3
  1624. include/linux/memcontrol.h +29 −0
  1625. include/linux/micrel_phy.h +1 −1
  1626. include/linux/mlx5/mlx5_ifc.h +1 −2
  1627. include/linux/mm.h +0 −5
  1628. include/linux/mm_types.h +5 −0
  1629. include/linux/netdevice.h +27 −34
  1630. include/linux/page-flags.h +18 −2
  1631. include/linux/page_ext.h +9 −1
  1632. include/linux/perf_event.h +1 −1
  1633. include/linux/platform_data/dma-imx-sdma.h +3 −0
  1634. include/linux/platform_device.h +2 −0
  1635. include/linux/pm_qos.h +44 −12
  1636. include/linux/radix-tree.h +0 −18
  1637. include/linux/reset-controller.h +2 −2
  1638. include/linux/reset.h +1 −1
  1639. include/linux/sched.h +1 −0
  1640. include/linux/security.h +1 −0
  1641. include/linux/skbuff.h +29 −12
  1642. include/linux/skmsg.h +6 −3
  1643. include/linux/slab.h +4 −0
  1644. include/linux/socket.h +1 −1
  1645. include/linux/string.h +20 −1
  1646. include/linux/sunrpc/bc_xprt.h +5 −0
  1647. include/linux/sunrpc/xprtsock.h +1 −0
  1648. include/linux/sysfs.h +2 −2
  1649. include/linux/tcp.h +3 −3
  1650. include/linux/tpm_eventlog.h +12 −4
  1651. include/linux/uaccess.h +4 −2
  1652. include/linux/virtio_vsock.h +0 −1
  1653. include/linux/xarray.h +2 −2
  1654. include/net/bonding.h +2 −3
  1655. include/net/busy_poll.h +3 −3
  1656. include/net/cfg80211.h +8 −0
  1657. include/net/flow_dissector.h +2 −1
  1658. include/net/fq.h +1 −1
  1659. include/net/fq_impl.h +4 −4
  1660. include/net/hwbm.h +7 −3
  1661. include/net/ip.h +2 −2
  1662. include/net/ip_vs.h +1 −0
  1663. include/net/llc_conn.h +1 −1
  1664. include/net/neighbour.h +2 −2
  1665. include/net/net_namespace.h +18 −9
  1666. include/net/netfilter/nf_tables.h +2 −1
  1667. include/net/request_sock.h +2 −2
  1668. include/net/sch_generic.h +4 −0
  1669. include/net/sctp/sctp.h +5 −0
  1670. include/net/sock.h +34 −18
  1671. include/net/tcp.h +6 −4
  1672. include/net/tls.h +5 −0
  1673. include/net/vxlan.h +1 −0
  1674. include/rdma/ib_verbs.h +1 −1
  1675. include/scsi/scsi_eh.h +1 −0
  1676. include/sound/hda_register.h +3 −0
  1677. include/sound/simple_card_utils.h +4 −4
  1678. include/trace/events/btrfs.h +2 −1
  1679. include/trace/events/rxrpc.h +9 −9
  1680. include/trace/events/sock.h +2 −2
  1681. include/uapi/drm/amdgpu_drm.h +2 −0
  1682. include/uapi/drm/drm.h +2 −1
  1683. include/uapi/drm/drm_fourcc.h +1 −1
  1684. include/uapi/drm/exynos_drm.h +1 −1
  1685. include/uapi/drm/omap_drm.h +9 −9
  1686. include/uapi/linux/can.h +1 −1
  1687. include/uapi/linux/can/bcm.h +1 −1
  1688. include/uapi/linux/can/error.h +1 −1
  1689. include/uapi/linux/can/gw.h +1 −1
  1690. include/uapi/linux/can/j1939.h +1 −1
  1691. include/uapi/linux/can/netlink.h +1 −1
  1692. include/uapi/linux/can/raw.h +1 −1
  1693. include/uapi/linux/can/vxcan.h +1 −1
  1694. include/uapi/linux/fuse.h +37 −0
  1695. include/uapi/linux/nvme_ioctl.h +1 −0
  1696. include/uapi/linux/sched.h +4 −0
  1697. include/uapi/linux/serial_core.h +1 −1
  1698. kernel/bpf/cgroup.c +2 −2
  1699. kernel/bpf/core.c +1 −1
  1700. kernel/bpf/devmap.c +32 −1
  1701. kernel/bpf/syscall.c +25 −13
  1702. kernel/cgroup/cpuset.c +2 −1
  1703. kernel/events/core.c +42 −11
  1704. kernel/events/uprobes.c +11 −2
  1705. kernel/fork.c +34 −3
  1706. kernel/freezer.c +0 −6
  1707. kernel/gen_kheaders.sh +7 −4
  1708. kernel/irq/irqdomain.c +1 −1
  1709. kernel/kthread.c +3 −3
  1710. kernel/panic.c +1 −0
  1711. kernel/power/main.c +1 −0
  1712. kernel/power/qos.c +240 −0
  1713. kernel/sched/core.c +16 −7
  1714. kernel/sched/cputime.c +3 −3
  1715. kernel/sched/deadline.c +20 −20
  1716. kernel/sched/fair.c +34 −17
  1717. kernel/sched/idle.c +8 −1
  1718. kernel/sched/rt.c +19 −18
  1719. kernel/sched/sched.h +27 −3
  1720. kernel/sched/stop_task.c +11 −7
  1721. kernel/sched/topology.c +9 −2
  1722. kernel/stacktrace.c +4 −2
  1723. kernel/stop_machine.c +6 −4
  1724. kernel/sysctl.c +2 −2
  1725. kernel/time/hrtimer.c +4 −4
  1726. kernel/time/posix-cpu-timers.c +3 −3
  1727. kernel/time/sched_clock.c +2 −0
  1728. kernel/time/vsyscall.c +3 −6
  1729. kernel/trace/ftrace.c +43 −12
  1730. kernel/trace/trace.c +87 −52
  1731. kernel/trace/trace.h +2 −0
  1732. kernel/trace/trace_dynevent.c +4 −0
  1733. kernel/trace/trace_event_perf.c +4 −0
  1734. kernel/trace/trace_events.c +17 −18
  1735. kernel/trace/trace_events_hist.c +14 −1
  1736. kernel/trace/trace_events_trigger.c +7 −1
  1737. kernel/trace/trace_hwlat.c +3 −1
  1738. kernel/trace/trace_kprobe.c +11 −1
  1739. kernel/trace/trace_printk.c +7 −0
  1740. kernel/trace/trace_stack.c +8 −0
  1741. kernel/trace/trace_stat.c +5 −1
  1742. kernel/trace/trace_uprobe.c +11 −0
  1743. lib/Kconfig +0 −1
  1744. lib/dump_stack.c +6 −1
  1745. lib/generic-radix-tree.c +26 −6
  1746. lib/idr.c +11 −20
  1747. lib/radix-tree.c +1 −1
  1748. lib/string.c +0 −21
  1749. lib/test_meminit.c +27 −0
  1750. lib/test_user_copy.c +28 −9
  1751. lib/test_xarray.c +24 −0
  1752. lib/vdso/Kconfig +0 −9
  1753. lib/vdso/gettimeofday.c +5 −4
  1754. lib/xarray.c +4 −0
  1755. mm/backing-dev.c +2 −2
  1756. mm/compaction.c +4 −3
  1757. mm/filemap.c +1 −0
  1758. mm/gup.c +8 −6
  1759. mm/huge_memory.c +7 −2
  1760. mm/hugetlb.c +2 −3
  1761. mm/init-mm.c +1 −0
  1762. mm/khugepaged.c +4 −3
  1763. mm/kmemleak.c +21 −9
  1764. mm/memblock.c +3 −3
  1765. mm/memcontrol.c +33 −13
  1766. mm/memory-failure.c +21 −15
  1767. mm/memory_hotplug.c +20 −54
  1768. mm/memremap.c +7 −6
  1769. mm/mmu_notifier.c +1 −1
  1770. mm/page_alloc.c +20 −11
  1771. mm/page_ext.c +9 −14
  1772. mm/page_owner.c +23 −37
  1773. mm/rmap.c +1 −0
  1774. mm/shmem.c +6 −0
  1775. mm/shuffle.c +1 −1
  1776. mm/slab.c +3 −0
  1777. mm/slab.h +2 −2
  1778. mm/slab_common.c +21 −7
  1779. mm/slob.c +47 −15
  1780. mm/slub.c +38 −11
  1781. mm/sparse.c +1 −1
  1782. mm/truncate.c +12 −0
  1783. mm/vmpressure.c +11 −9
  1784. mm/vmscan.c +72 −14
  1785. mm/vmstat.c +21 −4
  1786. mm/z3fold.c +8 −2
  1787. net/8021q/vlan.c +0 −1
  1788. net/8021q/vlan_dev.c +0 −33
  1789. net/atm/common.c +1 −1
  1790. net/batman-adv/bat_iv_ogm.c +52 −9
  1791. net/batman-adv/bat_v_ogm.c +33 −8
  1792. net/batman-adv/hard-interface.c +2 −0
  1793. net/batman-adv/soft-interface.c +0 −32
  1794. net/batman-adv/types.h +7 −0
  1795. net/bluetooth/6lowpan.c +0 −8
  1796. net/bluetooth/af_bluetooth.c +2 −2
  1797. net/bridge/br_device.c +0 −8
  1798. net/bridge/netfilter/ebt_dnat.c +15 −4
  1799. net/bridge/netfilter/nf_conntrack_bridge.c +4 −1
  1800. net/caif/caif_socket.c +1 −1
  1801. net/can/j1939/socket.c +7 −2
  1802. net/can/j1939/transport.c +19 −1
  1803. net/core/datagram.c +5 −5
  1804. net/core/dev.c +467 −156
  1805. net/core/dev_addr_lists.c +6 −6
  1806. net/core/ethtool.c +3 −1
  1807. net/core/filter.c +5 −3
  1808. net/core/flow_dissector.c +16 −22
  1809. net/core/lwt_bpf.c +6 −1
  1810. net/core/net_namespace.c +15 −8
  1811. net/core/request_sock.c +1 −1
  1812. net/core/rtnetlink.c +9 −8
  1813. net/core/skbuff.c +13 −10
  1814. net/core/skmsg.c +15 −5
  1815. net/core/sock.c +21 −17
  1816. net/dccp/ipv4.c +2 −2
  1817. net/decnet/af_decnet.c +1 −1
  1818. net/dsa/dsa2.c +1 −1
  1819. net/dsa/master.c +0 −5
  1820. net/dsa/slave.c +0 −12
  1821. net/ieee802154/6lowpan/core.c +0 −8
  1822. net/ipv4/datagram.c +1 −1
  1823. net/ipv4/fib_frontend.c +1 −1
  1824. net/ipv4/fib_semantics.c +1 −1
  1825. net/ipv4/inet_connection_sock.c +3 −3
  1826. net/ipv4/inet_diag.c +1 −1
  1827. net/ipv4/inet_hashtables.c +1 −1
  1828. net/ipv4/ip_gre.c +2 −2
  1829. net/ipv4/ip_output.c +9 −5
  1830. net/ipv4/route.c +7 −4
  1831. net/ipv4/tcp.c +47 −32
  1832. net/ipv4/tcp_diag.c +3 −2
  1833. net/ipv4/tcp_fastopen.c +1 −1
  1834. net/ipv4/tcp_input.c +22 −15
  1835. net/ipv4/tcp_ipv4.c +20 −16
  1836. net/ipv4/tcp_minisocks.c +11 −6
  1837. net/ipv4/tcp_output.c +16 −16
  1838. net/ipv4/tcp_timer.c +6 −5
  1839. net/ipv4/udp.c +20 −9
  1840. net/ipv6/addrconf_core.c +1 −0
  1841. net/ipv6/inet6_hashtables.c +1 −1
  1842. net/ipv6/ip6_gre.c +3 −2
  1843. net/ipv6/ip6_output.c +3 −0
  1844. net/ipv6/netfilter.c +3 −0
  1845. net/ipv6/route.c +10 −3
  1846. net/ipv6/tcp_ipv6.c +10 −8
  1847. net/ipv6/udp.c +1 −1
  1848. net/l2tp/l2tp_eth.c +0 −1
  1849. net/llc/af_llc.c +20 −14
  1850. net/llc/llc_c_ac.c +6 −2
  1851. net/llc/llc_conn.c +18 −51
  1852. net/llc/llc_if.c +8 −4
  1853. net/llc/llc_s_ac.c +9 −3
  1854. net/llc/llc_sap.c +8 −15
  1855. net/mac80211/main.c +1 −1
  1856. net/mac80211/mlme.c +3 −2
  1857. net/mac80211/rx.c +10 −1
  1858. net/mac80211/scan.c +28 −2
  1859. net/mac80211/sta_info.c +2 −1
  1860. net/netfilter/ipset/ip_set_core.c +33 −16
  1861. net/netfilter/ipset/ip_set_hash_ipmac.c +1 −1
  1862. net/netfilter/ipset/ip_set_hash_net.c +1 −0
  1863. net/netfilter/ipset/ip_set_hash_netnet.c +1 −0
  1864. net/netfilter/ipvs/ip_vs_app.c +10 −2
  1865. net/netfilter/ipvs/ip_vs_ctl.c +11 −18
  1866. net/netfilter/ipvs/ip_vs_pe.c +2 −1
  1867. net/netfilter/ipvs/ip_vs_sched.c +2 −1
  1868. net/netfilter/ipvs/ip_vs_sync.c +10 −3
  1869. net/netfilter/nf_conntrack_core.c +2 −2
  1870. net/netfilter/nf_flow_table_core.c +2 −1
  1871. net/netfilter/nf_tables_api.c +3 −4
  1872. net/netfilter/nf_tables_offload.c +3 −2
  1873. net/netfilter/nft_bitwise.c +3 −2
  1874. net/netfilter/nft_cmp.c +1 −1
  1875. net/netfilter/nft_payload.c +38 −0
  1876. net/netrom/af_netrom.c +0 −23
  1877. net/nfc/llcp_sock.c +2 −2
  1878. net/nfc/netlink.c +0 −2
  1879. net/openvswitch/actions.c +3 −2
  1880. net/openvswitch/datapath.c +11 −9
  1881. net/openvswitch/vport-internal_dev.c +4 −7
  1882. net/phonet/socket.c +2 −2
  1883. net/rose/af_rose.c +0 −23
  1884. net/rxrpc/ar-internal.h +2 −0
  1885. net/rxrpc/call_accept.c +3 −2
  1886. net/rxrpc/call_object.c +20 −14
  1887. net/rxrpc/conn_client.c +7 −2
  1888. net/rxrpc/conn_object.c +7 −6
  1889. net/rxrpc/conn_service.c +1 −1
  1890. net/rxrpc/peer_event.c +9 −2
  1891. net/rxrpc/peer_object.c +10 −6
  1892. net/rxrpc/recvmsg.c +16 −8
  1893. net/rxrpc/sendmsg.c +2 −1
  1894. net/sched/act_api.c +13 −10
  1895. net/sched/act_mirred.c +5 −1
  1896. net/sched/act_mpls.c +8 −4
  1897. net/sched/cls_api.c +112 −7
  1898. net/sched/cls_bpf.c +6 −2
  1899. net/sched/em_meta.c +2 −2
  1900. net/sched/sch_api.c +1 −2
  1901. net/sched/sch_etf.c +1 −1
  1902. net/sched/sch_generic.c +8 −11
  1903. net/sched/sch_hhf.c +4 −4
  1904. net/sched/sch_netem.c +8 −3
  1905. net/sched/sch_sfb.c +7 −6
  1906. net/sched/sch_sfq.c +8 −6
  1907. net/sched/sch_taprio.c +8 −3
  1908. net/sctp/diag.c +1 −1
  1909. net/sctp/input.c +11 −5
  1910. net/sctp/sm_make_chunk.c +6 −6
  1911. net/sctp/socket.c +6 −6
  1912. net/smc/af_smc.c +10 −3
  1913. net/smc/smc_core.c +5 −2
  1914. net/smc/smc_pnet.c +1 −3
  1915. net/smc/smc_rx.c +21 −8
  1916. net/sunrpc/backchannel_rqst.c +4 −3
  1917. net/sunrpc/xprt.c +5 −0
  1918. net/sunrpc/xprtrdma/backchannel.c +2 −0
  1919. net/sunrpc/xprtsock.c +8 −9
  1920. net/tipc/socket.c +6 −6
  1921. net/tls/tls_device.c +9 −1
  1922. net/tls/tls_main.c +2 −0
  1923. net/tls/tls_sw.c +10 −20
  1924. net/unix/af_unix.c +3 −3
  1925. net/vmw_vsock/af_vsock.c +1 −1
  1926. net/vmw_vsock/virtio_transport_common.c +19 −6
  1927. net/wireless/chan.c +5 −0
  1928. net/wireless/nl80211.c +2 −2
  1929. net/wireless/reg.c +1 −0
  1930. net/wireless/reg.h +0 −8
  1931. net/wireless/scan.c +13 −10
  1932. net/wireless/util.c +2 −1
  1933. net/wireless/wext-sme.c +6 −2
  1934. net/x25/x25_dev.c +1 −1
  1935. net/xdp/xdp_umem.c +6 −0
  1936. net/xdp/xsk.c +27 −15
  1937. samples/bpf/Makefile +1 −0
  1938. samples/bpf/asm_goto_workaround.h +12 −1
  1939. samples/bpf/task_fd_query_user.c +1 −0
  1940. scripts/coccinelle/api/devm_platform_ioremap_resource.cocci +0 −60
  1941. scripts/coccinelle/misc/add_namespace.cocci +2 −0
  1942. scripts/gdb/linux/dmesg.py +12 −4
  1943. scripts/gdb/linux/symbols.py +9 −2
  1944. scripts/gdb/linux/utils.py +13 −12
  1945. scripts/mod/modpost.c +41 −19
  1946. scripts/mod/modpost.h +1 −0
  1947. scripts/nsdeps +5 −5
  1948. scripts/recordmcount.h +1 −4
  1949. scripts/setlocalversion +1 −1
  1950. security/device_cgroup.c +13 −2
  1951. security/lockdown/lockdown.c +1 −0
  1952. security/selinux/ss/services.c +8 −1
  1953. sound/core/compress_offload.c +1 −1
  1954. sound/core/timer.c +20 −10
  1955. sound/firewire/bebob/bebob_focusrite.c +3 −0
  1956. sound/firewire/bebob/bebob_stream.c +1 −2
  1957. sound/hda/ext/hdac_ext_controller.c +5 −0
  1958. sound/hda/hdac_controller.c +0 −2
  1959. sound/pci/hda/hda_intel.c +7 −1
  1960. sound/pci/hda/patch_ca0132.c +1 −1
  1961. sound/pci/hda/patch_hdmi.c +21 −4
  1962. sound/pci/hda/patch_realtek.c +46 −3
  1963. sound/soc/codecs/hdac_hda.c +1 −1
  1964. sound/soc/codecs/hdmi-codec.c +5 −7
  1965. sound/soc/codecs/max98373.c +14 −10
  1966. sound/soc/codecs/msm8916-wcd-analog.c +2 −2
  1967. sound/soc/codecs/msm8916-wcd-digital.c +22 −0
  1968. sound/soc/codecs/rt5651.c +3 −0
  1969. sound/soc/codecs/rt5682.c +10 −2
  1970. sound/soc/codecs/wm8994.c +26 −17
  1971. sound/soc/codecs/wm_adsp.c +7 −3
  1972. sound/soc/intel/boards/sof_rt5682.c +56 −4
  1973. sound/soc/kirkwood/kirkwood-i2s.c +6 −5
  1974. sound/soc/rockchip/rockchip_i2s.c +1 −1
  1975. sound/soc/rockchip/rockchip_max98090.c +5 −2
  1976. sound/soc/samsung/arndale_rt5631.c +30 −4
  1977. sound/soc/sh/rcar/core.c +1 −0
  1978. sound/soc/sh/rcar/dma.c +2 −2
  1979. sound/soc/soc-pcm.c +12 −5
  1980. sound/soc/soc-topology.c +1 −1
  1981. sound/soc/sof/control.c +18 −8
  1982. sound/soc/sof/debug.c +4 −2
  1983. sound/soc/sof/intel/Kconfig +10 −0
  1984. sound/soc/sof/intel/bdw.c +7 −0
  1985. sound/soc/sof/intel/byt.c +6 −0
  1986. sound/soc/sof/intel/hda-ctrl.c +4 −8
  1987. sound/soc/sof/intel/hda-loader.c +1 −0
  1988. sound/soc/sof/intel/hda-stream.c +38 −7
  1989. sound/soc/sof/intel/hda.c +7 −0
  1990. sound/soc/sof/intel/hda.h +4 −1
  1991. sound/soc/sof/ipc.c +3 −1
  1992. sound/soc/sof/loader.c +2 −2
  1993. sound/soc/sof/pcm.c +24 −11
  1994. sound/soc/sof/topology.c +9 −6
  1995. sound/soc/stm/stm32_sai_sub.c +22 −11
  1996. sound/soc/ti/sdma-pcm.c +1 −1
  1997. sound/usb/pcm.c +3 −0
  1998. sound/usb/quirks.c +1 −0
  1999. sound/usb/validate.c +1 −1
  2000. tools/arch/arm/include/uapi/asm/kvm.h +3 −1
  2001. tools/arch/arm64/include/uapi/asm/kvm.h +3 −1
  2002. tools/arch/s390/include/uapi/asm/kvm.h +6 −0
  2003. tools/arch/x86/include/uapi/asm/svm.h +1 −0
  2004. tools/arch/x86/include/uapi/asm/vmx.h +7 −1
  2005. tools/bpf/Makefile +5 −1
  2006. tools/gpio/Makefile +5 −1
  2007. tools/include/uapi/asm-generic/mman-common.h +3 −0
  2008. tools/include/uapi/drm/i915_drm.h +1 −0
  2009. tools/include/uapi/linux/fs.h +4 −51
  2010. tools/include/uapi/linux/fscrypt.h +181 −0
  2011. tools/include/uapi/linux/kvm.h +5 −0
  2012. tools/include/uapi/linux/sched.h +28 −2
  2013. tools/include/uapi/linux/usbdevice_fs.h +4 −0
  2014. tools/lib/bpf/Makefile +23 −10
  2015. tools/lib/bpf/libbpf_internal.h +16 −0
  2016. tools/lib/bpf/xsk.c +2 −2
  2017. tools/lib/subcmd/Makefile +7 −1
  2018. tools/perf/Documentation/asciidoc.conf +3 −0
  2019. tools/perf/Documentation/jitdump-specification.txt +2 −2
  2020. tools/perf/arch/arm/annotate/instructions.c +2 −2
  2021. tools/perf/arch/arm64/annotate/instructions.c +2 −2
  2022. tools/perf/arch/powerpc/util/header.c +2 −1
  2023. tools/perf/arch/s390/annotate/instructions.c +4 −2
  2024. tools/perf/arch/s390/util/header.c +5 −4
  2025. tools/perf/arch/x86/annotate/instructions.c +4 −2
  2026. tools/perf/arch/x86/util/header.c +2 −1
  2027. tools/perf/builtin-c2c.c +9 −5
  2028. tools/perf/builtin-kmem.c +1 −0
  2029. tools/perf/builtin-kvm.c +4 −3
  2030. tools/perf/builtin-script.c +5 −1
  2031. tools/perf/check-headers.sh +1 −0
  2032. tools/perf/jvmti/Build +5 −1
  2033. tools/perf/perf-sys.h +4 −2
  2034. tools/perf/pmu-events/arch/s390/cf_z15/basic.json +0 −0
  2035. tools/perf/pmu-events/arch/s390/cf_z15/crypto.json +0 −0
  2036. tools/perf/pmu-events/arch/s390/cf_z15/crypto6.json +0 −0
  2037. tools/perf/pmu-events/arch/s390/cf_z15/extended.json +0 −0
  2038. tools/perf/pmu-events/arch/s390/cf_z15/transaction.json +7 −0
  2039. tools/perf/pmu-events/arch/s390/mapfile.csv +1 −1
  2040. tools/perf/pmu-events/jevents.c +6 −6
  2041. tools/perf/tests/perf-hooks.c +1 −2
  2042. tools/perf/util/annotate.c +26 −9
  2043. tools/perf/util/annotate.h +4 −0
  2044. tools/perf/util/copyfile.c +5 −3
  2045. tools/perf/util/evlist.c +1 −1
  2046. tools/perf/util/evsel.c +2 −1
  2047. tools/perf/util/header.c +3 −1
  2048. tools/perf/util/hist.c +1 −1
  2049. tools/perf/util/jitdump.c +3 −3
  2050. tools/perf/util/llvm-utils.c +3 −3
  2051. tools/perf/util/map.c +3 −0
  2052. tools/perf/util/python.c +6 −0
  2053. tools/perf/util/scripting-engines/trace-event-perl.c +6 −2
  2054. tools/perf/util/scripting-engines/trace-event-python.c +7 −2
  2055. tools/perf/util/trace-event-parse.c +0 −31
  2056. tools/perf/util/trace-event.h +0 −2
  2057. tools/perf/util/util.c +4 −2
  2058. tools/testing/selftests/Makefile +17 −2
  2059. tools/testing/selftests/bpf/prog_tests/sockopt_inherit.c +1 −1
  2060. tools/testing/selftests/bpf/prog_tests/tcp_rtt.c +2 −1
  2061. tools/testing/selftests/bpf/test_flow_dissector.sh +3 −0
  2062. tools/testing/selftests/bpf/test_lwt_ip_encap.sh +3 −3
  2063. tools/testing/selftests/bpf/test_offload.py +5 −0
  2064. tools/testing/selftests/bpf/test_sysctl.c +7 −1
  2065. tools/testing/selftests/bpf/test_tc_edt.sh +1 −1
  2066. tools/testing/selftests/kselftest/runner.sh +33 −3
  2067. tools/testing/selftests/kselftest_install.sh +2 −2
  2068. tools/testing/selftests/kvm/.gitignore +2 −0
  2069. tools/testing/selftests/kvm/include/x86_64/vmx.h +2 −0
  2070. tools/testing/selftests/kvm/lib/x86_64/vmx.c +10 −0
  2071. tools/testing/selftests/kvm/x86_64/sync_regs_test.c +11 −10
  2072. tools/testing/selftests/kvm/x86_64/vmx_close_while_nested_test.c +1 −5
  2073. tools/testing/selftests/kvm/x86_64/vmx_dirty_log_test.c +2 −0
  2074. tools/testing/selftests/kvm/x86_64/vmx_set_nested_state_test.c +2 −11
  2075. tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c +1 −5
  2076. tools/testing/selftests/net/fib_tests.sh +21 −0
  2077. tools/testing/selftests/net/l2tp.sh +0 −0
  2078. tools/testing/selftests/net/reuseport_dualstack.c +2 −1
  2079. tools/testing/selftests/net/tls.c +108 −0
  2080. tools/testing/selftests/powerpc/mm/tlbie_test.c +1 −1
  2081. tools/testing/selftests/rtc/settings +1 −0
  2082. tools/testing/selftests/vm/gup_benchmark.c +2 −2
  2083. tools/testing/selftests/watchdog/watchdog-test.c +26 −1
  2084. tools/usb/usbip/libsrc/usbip_device_driver.c +4 −2
  2085. tools/virtio/crypto/hash.h +0 −0
  2086. tools/virtio/linux/dma-mapping.h +2 −0
  2087. tools/virtio/xen/xen.h +6 −0
  2088. virt/kvm/arm/pmu.c +35 −13
  2089. virt/kvm/kvm_main.c +42 −35
.mailmap+7−1
@@ -108,6 +108,10 @@ Jason Gunthorpe <jgg@ziepe.ca> <jgg@mellanox.com> · 107 unmodified lines
108108 Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com>
109109 Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com>
110110 <javier@osg.samsung.com> <javier.martinez@collabora.co.uk>
111+Jayachandran C <c.jayachandran@gmail.com> <jayachandranc@netlogicmicro.com>
112+Jayachandran C <c.jayachandran@gmail.com> <jchandra@broadcom.com>
113+Jayachandran C <c.jayachandran@gmail.com> <jchandra@digeo.com>
114+Jayachandran C <c.jayachandran@gmail.com> <jnair@caviumnetworks.com>
111115 Jean Tourrilhes <jt@hpl.hp.com>
112116 <jean-philippe@linaro.org> <jean-philippe.brucker@arm.com>
113117 Jeff Garzik <jgarzik@pretzel.yyz.us>
@@ -196,7 +200,8 @@ Oleksij Rempel <linux@rempel-privat.de> <o.rempel@pengutronix.de> · 82 unmodified lines
196200 Oleksij Rempel <linux@rempel-privat.de> <ore@pengutronix.de>
197201 Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>
198202 Patrick Mochel <mochel@digitalimplant.org>
199−Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
203+Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
204+Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
200205 Peter A Jonsson <pj@ludd.ltu.se>
201206 Peter Oruba <peter@oruba.de>
202207 Peter Oruba <peter.oruba@amd.com>
@@ -229,6 +234,7 @@ Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com> · 26 unmodified lines
229234 Shuah Khan <shuah@kernel.org> <shuah.khan@hp.com>
230235 Shuah Khan <shuah@kernel.org> <shuahkh@osg.samsung.com>
231236 Shuah Khan <shuah@kernel.org> <shuah.kh@samsung.com>
237+Simon Arlott <simon@octiron.net> <simon@fire.lp0.eu>
232238 Simon Kelley <simon@thekelleys.org.uk>
233239 Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
234240 Stephen Hemminger <shemminger@osdl.org>
CREDITS+4−0
@@ -1637,6 +1637,10 @@ S: Panoramastrasse 18 · 1636 unmodified lines
16371637 S: D-69126 Heidelberg
16381638 S: Germany
16391639
1640+N: Simon Horman
1641+M: horms@verge.net.au
1642+D: Renesas ARM/ARM64 SoC maintainer
1643+
16401644 N: Christopher Horn
16411645 E: chorn@warwick.net
16421646 D: Miscellaneous sysctl hacks
Documentation/admin-guide/cgroup-v2.rst+14−6
@@ -615,8 +615,8 @@ on an IO device and is an example of this type. · 614 unmodified lines
615615 Protections
616616 -----------
617617
618−A cgroup is protected to be allocated upto the configured amount of
619−the resource if the usages of all its ancestors are under their
618+A cgroup is protected upto the configured amount of the resource
619+as long as the usages of all its ancestors are under their
620620 protected levels. Protections can be hard guarantees or best effort
621621 soft boundaries. Protections can also be over-committed in which case
622622 only upto the amount available to the parent is protected among
@@ -1096,7 +1096,10 @@ PAGE_SIZE multiple when read back. · 473 unmodified lines
10961096 is within its effective min boundary, the cgroup's memory
10971097 won't be reclaimed under any conditions. If there is no
10981098 unprotected reclaimable memory available, OOM killer
1099− is invoked.
1099+ is invoked. Above the effective min boundary (or
1100+ effective low boundary if it is higher), pages are reclaimed
1101+ proportionally to the overage, reducing reclaim pressure for
1102+ smaller overages.
11001103
11011104 Effective min boundary is limited by memory.min values of
11021105 all ancestor cgroups. If there is memory.min overcommitment
@@ -1118,7 +1121,10 @@ PAGE_SIZE multiple when read back. · 15 unmodified lines
11181121 Best-effort memory protection. If the memory usage of a
11191122 cgroup is within its effective low boundary, the cgroup's
11201123 memory won't be reclaimed unless memory can be reclaimed
1121− from unprotected cgroups.
1124+ from unprotected cgroups. Above the effective low boundary (or
1125+ effective min boundary if it is higher), pages are reclaimed
1126+ proportionally to the overage, reducing reclaim pressure for
1127+ smaller overages.
11221128
11231129 Effective low boundary is limited by memory.low values of
11241130 all ancestor cgroups. If there is memory.low overcommitment
@@ -2482,8 +2488,10 @@ system performance due to overreclaim, to the point where the feature · 1357 unmodified lines
24822488 becomes self-defeating.
24832489
24842490 The memory.low boundary on the other hand is a top-down allocated
2485−reserve. A cgroup enjoys reclaim protection when it's within its low,
2486−which makes delegation of subtrees possible.
2491+reserve. A cgroup enjoys reclaim protection when it's within its
2492+effective low, which makes delegation of subtrees possible. It also
2493+enjoys having reclaim pressure proportional to its overage when
2494+above its effective low.
24872495
24882496 The original high boundary, the hard limit, is defined as a strict
24892497 limit that can not budge, even if the OOM killer has to be called.
Documentation/admin-guide/kernel-parameters.txt+4−0
@@ -5302,6 +5302,10 @@ · 5301 unmodified lines
53025302 the unplug protocol
53035303 never -- do not unplug even if version check succeeds
53045304
5305+ xen_legacy_crash [X86,XEN]
5306+ Crash from Xen panic notifier, without executing late
5307+ panic() code such as dumping handler.
5308+
53055309 xen_nopvspin [X86,XEN]
53065310 Disables the ticketlock slowpath using Xen PV
53075311 optimizations.
Documentation/arm64/memory.rst+8−1
@@ -154,11 +154,18 @@ return virtual addresses to userspace from a 48-bit range. · 153 unmodified lines
154154
155155 Software can "opt-in" to receiving VAs from a 52-bit space by
156156 specifying an mmap hint parameter that is larger than 48-bit.
157+
157158 For example:
158− maybe_high_address = mmap(~0UL, size, prot, flags,...);
159+
160+.. code-block:: c
161+
162+ maybe_high_address = mmap(~0UL, size, prot, flags,...);
159163
160164 It is also possible to build a debug kernel that returns addresses
161165 from a 52-bit space by enabling the following kernel config options:
166+
167+.. code-block:: sh
168+
162169 CONFIG_EXPERT=y && CONFIG_ARM64_FORCE_52BIT=y
163170
164171 Note that this option is only intended for debugging applications
Documentation/arm64/silicon-errata.rst+8−1
@@ -91,6 +91,11 @@ stable kernels. · 90 unmodified lines
9191 | ARM | MMU-500 | #841119,826419 | N/A |
9292 +----------------+-----------------+-----------------+-----------------------------+
9393 +----------------+-----------------+-----------------+-----------------------------+
94+| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_845719 |
95++----------------+-----------------+-----------------+-----------------------------+
96+| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_843419 |
97++----------------+-----------------+-----------------+-----------------------------+
98++----------------+-----------------+-----------------+-----------------------------+
9499 | Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 |
95100 +----------------+-----------------+-----------------+-----------------------------+
96101 | Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
@@ -107,6 +112,8 @@ stable kernels. · 10 unmodified lines
107112 +----------------+-----------------+-----------------+-----------------------------+
108113 | Cavium | ThunderX2 SMMUv3| #126 | N/A |
109114 +----------------+-----------------+-----------------+-----------------------------+
115+| Cavium | ThunderX2 Core | #219 | CAVIUM_TX2_ERRATUM_219 |
116++----------------+-----------------+-----------------+-----------------------------+
110117 +----------------+-----------------+-----------------+-----------------------------+
111118 | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
112119 +----------------+-----------------+-----------------+-----------------------------+
@@ -124,7 +131,7 @@ stable kernels. · 11 unmodified lines
124131 +----------------+-----------------+-----------------+-----------------------------+
125132 | Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
126133 +----------------+-----------------+-----------------+-----------------------------+
127−| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
134+| Qualcomm Tech. | Kryo/Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
128135 +----------------+-----------------+-----------------+-----------------------------+
129136 | Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 |
130137 +----------------+-----------------+-----------------+-----------------------------+
Documentation/core-api/index.rst+1−0
@@ -38,6 +38,7 @@ Core utilities · 37 unmodified lines
3838 protection-keys
3939 ../RCU/index
4040 gcc-plugins
41+ symbol-namespaces
4142
4243
4344 Interfaces for kernel debugging
Documentation/core-api/memory-allocation.rst+4−0
@@ -98,6 +98,10 @@ limited. The actual limit depends on the hardware and the kernel · 97 unmodified lines
9898 configuration, but it is a good practice to use `kmalloc` for objects
9999 smaller than page size.
100100
101+The address of a chunk allocated with `kmalloc` is aligned to at least
102+ARCH_KMALLOC_MINALIGN bytes. For sizes which are a power of two, the
103+alignment is also guaranteed to be at least the respective size.
104+
101105 For large allocations you can use :c:func:`vmalloc` and
102106 :c:func:`vzalloc`, or directly request pages from the page
103107 allocator. The memory allocated by `vmalloc` and related functions is
Documentation/core-api/symbol-namespaces.rstrenamed from Documentation/kbuild/namespaces.rst+0−0

File renamed without changes.

Documentation/dev-tools/kasan.rst+3−0
@@ -41,6 +41,9 @@ smaller binary while the latter is 1.1 - 2 times faster. · 40 unmodified lines
4141 Both KASAN modes work with both SLUB and SLAB memory allocators.
4242 For better bug detection and nicer reporting, enable CONFIG_STACKTRACE.
4343
44+To augment reports with last allocation and freeing stack of the physical page,
45+it is recommended to enable also CONFIG_PAGE_OWNER and boot with page_owner=on.
46+
4447 To disable instrumentation for specific files or directories, add a line
4548 similar to the following to the respective kernel Makefile:
4649
Documentation/dev-tools/kselftest.rst+16−0
@@ -89,6 +89,22 @@ To build, save output files in a separate directory with KBUILD_OUTPUT :: · 88 unmodified lines
8989
9090 $ export KBUILD_OUTPUT=/tmp/kselftest; make TARGETS="size timers" kselftest
9191
92+Additionally you can use the "SKIP_TARGETS" variable on the make command
93+line to specify one or more targets to exclude from the TARGETS list.
94+
95+To run all tests but a single subsystem::
96+
97+ $ make -C tools/testing/selftests SKIP_TARGETS=ptrace run_tests
98+
99+You can specify multiple tests to skip::
100+
101+ $ make SKIP_TARGETS="size timers" kselftest
102+
103+You can also specify a restricted list of tests to run together with a
104+dedicated skiplist::
105+
106+ $ make TARGETS="bpf breakpoints size timers" SKIP_TARGETS=bpf kselftest
107+
92108 See the top-level tools/testing/selftests/Makefile for the list of all
93109 possible targets.
94110
Documentation/devicetree/bindings/arm/rockchip.yaml+2−2
@@ -496,12 +496,12 @@ properties: · 495 unmodified lines
496496
497497 - description: Theobroma Systems RK3368-uQ7 with Haikou baseboard
498498 items:
499− - const: tsd,rk3368-uq7-haikou
499+ - const: tsd,rk3368-lion-haikou
500500 - const: rockchip,rk3368
501501
502502 - description: Theobroma Systems RK3399-Q7 with Haikou baseboard
503503 items:
504− - const: tsd,rk3399-q7-haikou
504+ - const: tsd,rk3399-puma-haikou
505505 - const: rockchip,rk3399
506506
507507 - description: Tronsmart Orion R68 Meta
Documentation/devicetree/bindings/display/arm,malidp.txt+3−0
@@ -37,6 +37,8 @@ Optional properties: · 36 unmodified lines
3737 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
3838 to be used for the framebuffer; if not present, the framebuffer may
3939 be located anywhere in memory.
40+ - arm,malidp-arqos-high-level: integer of u32 value describing the ARQoS
41+ levels of DP500's QoS signaling.
4042
4143
4244 Example:
@@ -54,6 +56,7 @@ Example: · 11 unmodified lines
5456 clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
5557 clock-names = "pxlclk", "mclk", "aclk", "pclk";
5658 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
59+ arm,malidp-arqos-high-level = <0xd000d000>;
5760 port {
5861 dp0_output: endpoint {
5962 remote-endpoint = <&tda998x_2_input>;
Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt+1−0
@@ -13,6 +13,7 @@ Required properties: · 12 unmodified lines
1313
1414 - compatible : Shall contain one or more of
1515 - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
16+ - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
1617 - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
1718 - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
1819 - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt+1−0
@@ -10,6 +10,7 @@ Required properties: · 9 unmodified lines
1010 - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
1111 - "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders
1212 - "renesas,r8a774a1-lvds" for R8A774A1 (RZ/G2M) compatible LVDS encoders
13+ - "renesas,r8a774b1-lvds" for R8A774B1 (RZ/G2N) compatible LVDS encoders
1314 - "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders
1415 - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
1516 - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt+17−13
@@ -27,19 +27,22 @@ Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt. · 26 unmodified lines
2727
2828 Required properties (all function blocks):
2929 - compatible: "mediatek,<chip>-disp-<function>", one of
30− "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31− "mediatek,<chip>-disp-rdma" - read DMA / line buffer
32− "mediatek,<chip>-disp-wdma" - write DMA
33− "mediatek,<chip>-disp-color" - color processor
34− "mediatek,<chip>-disp-aal" - adaptive ambient light controller
35− "mediatek,<chip>-disp-gamma" - gamma correction
36− "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
37− "mediatek,<chip>-disp-split" - split stream to two encoders
38− "mediatek,<chip>-disp-ufoe" - data compression engine
39− "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
40− "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
41− "mediatek,<chip>-disp-mutex" - display mutex
42− "mediatek,<chip>-disp-od" - overdrive
30+ "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31+ "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32+ "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33+ "mediatek,<chip>-disp-wdma" - write DMA
34+ "mediatek,<chip>-disp-ccorr" - color correction
35+ "mediatek,<chip>-disp-color" - color processor
36+ "mediatek,<chip>-disp-dither" - dither
37+ "mediatek,<chip>-disp-aal" - adaptive ambient light controller
38+ "mediatek,<chip>-disp-gamma" - gamma correction
39+ "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
40+ "mediatek,<chip>-disp-split" - split stream to two encoders
41+ "mediatek,<chip>-disp-ufoe" - data compression engine
42+ "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
43+ "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
44+ "mediatek,<chip>-disp-mutex" - display mutex
45+ "mediatek,<chip>-disp-od" - overdrive
4346 the supported chips are mt2701, mt2712 and mt8173.
4447 - reg: Physical base address and length of the function block register space
4548 - interrupts: The interrupt signal from the function block (required, except for
@@ -49,6 +52,7 @@ Required properties (all function blocks): · 3 unmodified lines
4952 For most function blocks this is just a single clock input. Only the DSI and
5053 DPI controller nodes have multiple clock inputs. These are documented in
5154 mediatek,dsi.txt and mediatek,dpi.txt, respectively.
55+ An exception is that the mt8183 mutex is always free running with no clocks property.
5256
5357 Required properties (DMA function blocks):
5458 - compatible: Should be one of
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt+2−2
@@ -7,7 +7,7 @@ channel output. · 6 unmodified lines
77
88 Required properties:
99 - compatible: "mediatek,<chip>-dsi"
10− the supported chips are mt2701 and mt8173.
10+ the supported chips are mt2701, mt8173 and mt8183.
1111 - reg: Physical base address and length of the controller's registers
1212 - interrupts: The interrupt signal from the function block.
1313 - clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. · 12 unmodified lines
2626
2727 Required properties:
2828 - compatible: "mediatek,<chip>-mipi-tx"
29− the supported chips are mt2701 and mt8173.
29+ the supported chips are mt2701, mt8173 and mt8183.
3030 - reg: Physical base address and length of the controller's registers
3131 - clocks: PLL reference clock
3232 - clock-output-names: name of the output clock line to the DSI encoder
Documentation/devicetree/bindings/display/renesas,du.txt+2−0
@@ -8,6 +8,7 @@ Required Properties: · 7 unmodified lines
88 - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
99 - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU
1010 - "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU
11+ - "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU
1112 - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU
1213 - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
1314 - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
@@ -60,6 +61,7 @@ corresponding to each DU output. · 46 unmodified lines
6061 R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
6162 R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 -
6263 R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 -
64+ R8A774B1 (RZ/G2N) DPAD 0 HDMI 0 LVDS 0 -
6365 R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 -
6466 R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
6567 R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt+5−1
@@ -20,6 +20,10 @@ Required properties: · 19 unmodified lines
2020 "rockchip,rk3228-vop";
2121 "rockchip,rk3328-vop";
2222
23+- reg: Must contain one entry corresponding to the base address and length
24+ of the register space. Can optionally contain a second entry
25+ corresponding to the CRTC gamma LUT address.
26+
2327 - interrupts: should contain a list of all VOP IP block interrupts in the
2428 order: VSYNC, LCD_SYSTEM. The interrupt specifier
2529 format depends on the interrupt controller used.
@@ -48,7 +52,7 @@ Example: · 22 unmodified lines
4852 SoC specific DT entry:
4953 vopb: vopb@ff930000 {
5054 compatible = "rockchip,rk3288-vop";
51− reg = <0xff930000 0x19c>;
55+ reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
5256 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
5357 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
5458 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt+5−2
@@ -1,8 +1,11 @@
11 * Advanced Interrupt Controller (AIC)
22
33 Required properties:
4−- compatible: Should be "atmel,<chip>-aic"
5− <chip> can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4"
4+- compatible: Should be:
5+ - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
6+ "sama5d3" or "sama5d4"
7+ - "microchip,<chip>-aic" where <chip> can be "sam9x60"
8+
69 - interrupt-controller: Identifies the node as an interrupt controller.
710 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
811 The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml+3−6
@@ -1,7 +1,7 @@
11 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
22 %YAML 1.2
33 ---
4−$id: http://devicetree.org/schemas/arm/allwinner,sun4i-a10-csi.yaml#
4+$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
55 $schema: http://devicetree.org/meta-schemas/core.yaml#
66
77 title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings
@@ -27,14 +27,12 @@ properties: · 19 unmodified lines
2727 clocks:
2828 items:
2929 - description: The CSI interface clock
30− - description: The CSI module clock
3130 - description: The CSI ISP clock
3231 - description: The CSI DRAM clock
3332
3433 clock-names:
3534 items:
3635 - const: bus
37− - const: mod
3836 - const: isp
3937 - const: ram
4038
@@ -89,9 +87,8 @@ examples: · 48 unmodified lines
8987 compatible = "allwinner,sun7i-a20-csi0";
9088 reg = <0x01c09000 0x1000>;
9189 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
92− clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
93− <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
94− clock-names = "bus", "mod", "isp", "ram";
90+ clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
91+ clock-names = "bus", "isp", "ram";
9592 resets = <&ccu RST_CSI0>;
9693
9794 port {
Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml+42−44
@@ -33,13 +33,13 @@ patternProperties: · 32 unmodified lines
3333 allOf:
3434 - $ref: "/schemas/types.yaml#/definitions/string"
3535 - enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
36− ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI,
37− ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1,
38− GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2,
39− GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12,
40− I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7,
41− I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC,
42− LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2,
36+ ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC,
37+ ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0,
38+ GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
39+ GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11,
40+ I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6,
41+ I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
42+ LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2,
4343 MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2,
4444 NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3,
4545 NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1,
@@ -48,47 +48,45 @@ patternProperties: · 2 unmodified lines
4848 PWM8, PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3,
4949 RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12,
5050 SALT13, SALT14, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5,
51− SALT6, SALT7, SALT8, SALT9, SD1, SD2, SD3, SD3DAT4, SD3DAT5,
52− SD3DAT6, SD3DAT7, SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO,
53− SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1,
54− SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
55− TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5,
56− TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1,
57− TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13, UART6, UART7,
58− UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
59− WDTRST4, ]
51+ SALT6, SALT7, SALT8, SALT9, SD1, SD2, SGPM1, SGPS1, SIOONCTRL,
52+ SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
53+ SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1,
54+ TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
55+ TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
56+ THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13,
57+ UART6, UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
58+ WDTRST3, WDTRST4, ]
6059 groups:
6160 allOf:
6261 - $ref: "/schemas/types.yaml#/definitions/string"
6362 - enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
64− ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI,
65− ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWQSPID, FWSPIWP, GPIT0,
66− GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
67− GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1,
68− I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3,
69− I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6,
70− JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
71− MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3,
72− MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
73− NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1,
74− NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE,
75− PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0, PWM12G1,
76− PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2, PWM3,
77− PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
78− QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3,
79− RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1,
80− SALT11G0, SALT11G1, SALT12G0, SALT12G1, SALT13G0, SALT13G1,
81− SALT14G0, SALT14G1, SALT15G0, SALT15G1, SALT16G0, SALT16G1,
82− SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9G0,
83− SALT9G1, SD1, SD2, SD3, SD3DAT4, SD3DAT5, SD3DAT6, SD3DAT7,
84− SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD,
85− SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
86− SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13,
87− TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8,
88− TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4,
89− UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
90− UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
91− WDTRST4, ]
63+ ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1,
64+ EMMCG4, EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID,
65+ FWQSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5,
66+ GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5, GPIU6,
67+ GPIU7, HVI3C3, HVI3C4, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14,
68+ I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9,
69+ I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD,
70+ LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3, MACLINK4,
71+ MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1,
72+ NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
73+ NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
74+ OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1,
75+ PWM12G0, PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0,
76+ PWM15G1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1,
77+ PWM9G0, PWM9G1, QSPI1, QSPI2, RGMII1, RGMII2, RGMII3, RGMII4,
78+ RMII1, RMII2, RMII3, RMII4, RXD1, RXD2, RXD3, RXD4, SALT1,
79+ SALT10G0, SALT10G1, SALT11G0, SALT11G1, SALT12G0, SALT12G1,
80+ SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, SALT15G1,
81+ SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7,
82+ SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPS1, SIOONCTRL,
83+ SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
84+ SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1,
85+ TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
86+ TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
87+ THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0,
88+ UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, VB,
89+ VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]
9290
9391 required:
9492 - compatible
Documentation/devicetree/bindings/regulator/fixed-regulator.yaml+2−2
@@ -30,8 +30,8 @@ if: · 29 unmodified lines
3030 properties:
3131 compatible:
3232 enum:
33− - const: regulator-fixed
34− - const: regulator-fixed-clock
33+ - regulator-fixed
34+ - regulator-fixed-clock
3535
3636 regulator-name: true
3737
Documentation/devicetree/bindings/riscv/cpus.yaml+13−16
@@ -24,15 +24,17 @@ description: | · 23 unmodified lines
2424
2525 properties:
2626 compatible:
27− items:
28− - enum:
29− - sifive,rocket0
30− - sifive,e5
31− - sifive,e51
32− - sifive,u54-mc
33− - sifive,u54
34− - sifive,u5
35− - const: riscv
27+ oneOf:
28+ - items:
29+ - enum:
30+ - sifive,rocket0
31+ - sifive,e5
32+ - sifive,e51
33+ - sifive,u54-mc
34+ - sifive,u54
35+ - sifive,u5
36+ - const: riscv
37+ - const: riscv # Simulator only
3638 description:
3739 Identifies that the hart uses the RISC-V instruction set
3840 and identifies the type of the hart.
@@ -66,12 +68,8 @@ properties: · 27 unmodified lines
6668 insensitive, letters in the riscv,isa string must be all
6769 lowercase to simplify parsing.
6870
69− timebase-frequency:
70− type: integer
71− minimum: 1
72− description:
73− Specifies the clock frequency of the system timer in Hz.
74− This value is common to all harts on a single system image.
71+ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
72+ timebase-frequency: false
7573
7674 interrupt-controller:
7775 type: object
@@ -93,7 +91,6 @@ properties: · 15 unmodified lines
9391
9492 required:
9593 - riscv,isa
96− - timebase-frequency
9794 - interrupt-controller
9895
9996 examples:
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt+2−0
@@ -26,6 +26,8 @@ Required properties: · 25 unmodified lines
2626 - "renesas,hscif-r8a77470" for R8A77470 (RZ/G1C) HSCIF compatible UART.
2727 - "renesas,scif-r8a774a1" for R8A774A1 (RZ/G2M) SCIF compatible UART.
2828 - "renesas,hscif-r8a774a1" for R8A774A1 (RZ/G2M) HSCIF compatible UART.
29+ - "renesas,scif-r8a774b1" for R8A774B1 (RZ/G2N) SCIF compatible UART.
30+ - "renesas,hscif-r8a774b1" for R8A774B1 (RZ/G2N) HSCIF compatible UART.
2931 - "renesas,scif-r8a774c0" for R8A774C0 (RZ/G2E) SCIF compatible UART.
3032 - "renesas,hscif-r8a774c0" for R8A774C0 (RZ/G2E) HSCIF compatible UART.
3133 - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART.
Documentation/devicetree/bindings/usb/amlogic,dwc3.txt+2−2
@@ -85,8 +85,8 @@ A child node must exist to represent the core DWC2 IP block. The name of · 84 unmodified lines
8585 the node is not important. The content of the node is defined in dwc2.txt.
8686
8787 PHY documentation is provided in the following places:
88−- Documentation/devicetree/bindings/phy/meson-g12a-usb2-phy.txt
89−- Documentation/devicetree/bindings/phy/meson-g12a-usb3-pcie-phy.txt
88+- Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml
89+- Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml
9090
9191 Example device nodes:
9292 usb: usb@ffe09000 {
Documentation/devicetree/bindings/usb/generic-ehci.yaml+6−1
@@ -63,7 +63,11 @@ properties: · 62 unmodified lines
6363 description:
6464 Set this flag to force EHCI reset after resume.
6565
66− phys: true
66+ phys:
67+ description: PHY specifier for the USB PHY
68+
69+ phy-names:
70+ const: usb
6771
6872 required:
6973 - compatible
@@ -89,6 +93,7 @@ examples: · 19 unmodified lines
8993 interrupts = <39>;
9094 clocks = <&ahb_gates 1>;
9195 phys = <&usbphy 1>;
96+ phy-names = "usb";
9297 };
9398
9499 ...
Documentation/devicetree/bindings/usb/generic-ohci.yaml+6−1
@@ -67,7 +67,11 @@ properties: · 66 unmodified lines
6767 description:
6868 Overrides the detected port count
6969
70− phys: true
70+ phys:
71+ description: PHY specifier for the USB PHY
72+
73+ phy-names:
74+ const: usb
7175
7276 required:
7377 - compatible
@@ -84,6 +88,7 @@ examples: · 10 unmodified lines
8488 interrupts = <64>;
8589 clocks = <&usb_clk 6>, <&ahb_gates 2>;
8690 phys = <&usbphy 1>;
91+ phy-names = "usb";
8792 };
8893
8994 ...
Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt+2−2
@@ -33,7 +33,7 @@ Required properties: · 32 unmodified lines
3333 "dma_ck": dma_bus clock for data transfer by DMA,
3434 "xhci_ck": controller clock
3535
36− - phys : see usb-hcd.txt in the current directory
36+ - phys : see usb-hcd.yaml in the current directory
3737
3838 Optional properties:
3939 - wakeup-source : enable USB remote wakeup;
@@ -53,7 +53,7 @@ Optional properties: · 13 unmodified lines
5353 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
5454 - imod-interval-ns: default interrupt moderation interval is 5000ns
5555
56−additionally the properties from usb-hcd.txt (in the current directory) are
56+additionally the properties from usb-hcd.yaml (in the current directory) are
5757 supported.
5858
5959 Example:
Documentation/devicetree/bindings/usb/mediatek,mtu3.txt+2−2
@@ -17,7 +17,7 @@ Required properties: · 16 unmodified lines
1717 - clock-names : must contain "sys_ck" for clock of controller,
1818 the following clocks are optional:
1919 "ref_ck", "mcu_ck" and "dma_ck";
20− - phys : see usb-hcd.txt in the current directory
20+ - phys : see usb-hcd.yaml in the current directory
2121 - dr_mode : should be one of "host", "peripheral" or "otg",
2222 refer to usb/generic.txt
2323
@@ -60,7 +60,7 @@ Optional properties: · 36 unmodified lines
6060 - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
6161 bit1 for u3port1, ... etc;
6262
63−additionally the properties from usb-hcd.txt (in the current directory) are
63+additionally the properties from usb-hcd.yaml (in the current directory) are
6464 supported.
6565
6666 Sub-nodes:
Documentation/devicetree/bindings/usb/usb-hcd.yaml+5−0
@@ -18,8 +18,13 @@ properties: · 17 unmodified lines
1818 description:
1919 List of all the USB PHYs on this HCD
2020
21+ phy-names:
22+ description:
23+ Name specifier for the USB PHY
24+
2125 examples:
2226 - |
2327 usb {
2428 phys = <&usb2_phy1>, <&usb3_phy1>;
29+ phy-names = "usb";
2530 };
Documentation/devicetree/bindings/usb/usb-uhci.txt+1−1
@@ -6,7 +6,7 @@ Required properties: · 5 unmodified lines
66 - reg : Should contain 1 register ranges(address and length)
77 - interrupts : UHCI controller interrupt
88
9−additionally the properties from usb-hcd.txt (in the current directory) are
9+additionally the properties from usb-hcd.yaml (in the current directory) are
1010 supported.
1111
1212 Example:
Documentation/devicetree/bindings/usb/usb-xhci.txt+2−2
@@ -41,9 +41,9 @@ Optional properties: · 40 unmodified lines
4141 - usb3-lpm-capable: determines if platform is USB3 LPM capable
4242 - quirk-broken-port-ped: set if the controller has broken port disable mechanism
4343 - imod-interval-ns: default interrupt moderation interval is 5000ns
44− - phys : see usb-hcd.txt in the current directory
44+ - phys : see usb-hcd.yaml in the current directory
4545
46−additionally the properties from usb-hcd.txt (in the current directory) are
46+additionally the properties from usb-hcd.yaml (in the current directory) are
4747 supported.
4848
4949
Documentation/driver-api/dma-buf.rst+3−3
@@ -118,13 +118,13 @@ Kernel Functions and Structures Reference · 117 unmodified lines
118118 Reservation Objects
119119 -------------------
120120
121−.. kernel-doc:: drivers/dma-buf/reservation.c
121+.. kernel-doc:: drivers/dma-buf/dma-resv.c
122122 :doc: Reservation Object Overview
123123
124−.. kernel-doc:: drivers/dma-buf/reservation.c
124+.. kernel-doc:: drivers/dma-buf/dma-resv.c
125125 :export:
126126
127−.. kernel-doc:: include/linux/reservation.h
127+.. kernel-doc:: include/linux/dma-resv.h
128128 :internal:
129129
130130 DMA Fences
Documentation/gpu/amdgpu.rst+60−5
@@ -79,16 +79,71 @@ AMDGPU XGMI Support · 78 unmodified lines
7979 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
8080 :internal:
8181
82−AMDGPU RAS debugfs control interface
83−====================================
82+AMDGPU RAS Support
83+==================
84+
85+The AMDGPU RAS interfaces are exposed via sysfs (for informational queries) and
86+debugfs (for error injection).
87+
88+RAS debugfs/sysfs Control and Error Injection Interfaces
89+--------------------------------------------------------
8490
8591 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
8692 :doc: AMDGPU RAS debugfs control interface
8793
94+RAS Reboot Behavior for Unrecoverable Errors
95+--------------------------------------------------------
96+
97+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
98+ :doc: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
99+
100+RAS Error Count sysfs Interface
101+-------------------------------
102+
103+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
104+ :doc: AMDGPU RAS sysfs Error Count Interface
105+
106+RAS EEPROM debugfs Interface
107+----------------------------
108+
109+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
110+ :doc: AMDGPU RAS debugfs EEPROM table reset interface
111+
112+RAS VRAM Bad Pages sysfs Interface
113+----------------------------------
114+
115+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
116+ :doc: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
88117
89118 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
90119 :internal:
91120
121+Sample Code
122+-----------
123+Sample code for testing error injection can be found here:
124+https://cgit.freedesktop.org/mesa/drm/tree/tests/amdgpu/ras_tests.c
125+
126+This is part of the libdrm amdgpu unit tests which cover several areas of the GPU.
127+There are four sets of tests:
128+
129+RAS Basic Test
130+
131+The test verifies the RAS feature enabled status and makes sure the necessary sysfs and debugfs files
132+are present.
133+
134+RAS Query Test
135+
136+This test checks the RAS availability and enablement status for each supported IP block as well as
137+the error counts.
138+
139+RAS Inject Test
140+
141+This test injects errors for each IP.
142+
143+RAS Disable Test
144+
145+This test tests disabling of RAS features for each IP block.
146+
92147
93148 GPU Power/Thermal Controls and Monitoring
94149 =========================================
@@ -130,11 +185,11 @@ pp_od_clk_voltage · 35 unmodified lines
130185 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
131186 :doc: pp_od_clk_voltage
132187
133−pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
134−~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
188+pp_dpm_*
189+~~~~~~~~
135190
136191 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
137− :doc: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
192+ :doc: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
138193
139194 pp_power_profile_mode
140195 ~~~~~~~~~~~~~~~~~~~~~
Documentation/gpu/drm-kms-helpers.rst+0−3
@@ -77,9 +77,6 @@ Atomic State Reset and Initialization · 76 unmodified lines
7777 Atomic State Helper Reference
7878 -----------------------------
7979
80−.. kernel-doc:: include/drm/drm_atomic_state_helper.h
81− :internal:
82−
8380 .. kernel-doc:: drivers/gpu/drm/drm_atomic_state_helper.c
8481 :export:
8582
Documentation/gpu/todo.rst+104−23
@@ -7,6 +7,22 @@ TODO list · 6 unmodified lines
77 This section contains a list of smaller janitorial tasks in the kernel DRM
88 graphics subsystem useful as newbie projects. Or for slow rainy days.
99
10+Difficulty
11+----------
12+
13+To make it easier task are categorized into different levels:
14+
15+Starter: Good tasks to get started with the DRM subsystem.
16+
17+Intermediate: Tasks which need some experience with working in the DRM
18+subsystem, or some specific GPU/display graphics knowledge. For debugging issue
19+it's good to have the relevant hardware (or a virtual driver set up) available
20+for testing.
21+
22+Advanced: Tricky tasks that need fairly good understanding of the DRM subsystem
23+and graphics topics. Generally need the relevant hardware for development and
24+testing.
25+
1026 Subsystem-wide refactorings
1127 ===========================
1228
@@ -20,6 +36,8 @@ implementations), and then remove it. · 7 unmodified lines
2036
2137 Contact: Daniel Vetter, respective driver maintainers
2238
39+Level: Intermediate
40+
2341 Convert existing KMS drivers to atomic modesetting
2442 --------------------------------------------------
2543
@@ -38,6 +56,8 @@ do by directly using the new atomic helper driver callbacks. · 12 unmodified lines
3856
3957 Contact: Daniel Vetter, respective driver maintainers
4058
59+Level: Advanced
60+
4161 Clean up the clipped coordination confusion around planes
4262 ---------------------------------------------------------
4363
@@ -50,6 +70,8 @@ helpers. · 6 unmodified lines
5070
5171 Contact: Ville Syrjälä, Daniel Vetter, driver maintainers
5272
73+Level: Advanced
74+
5375 Convert early atomic drivers to async commit helpers
5476 ----------------------------------------------------
5577
@@ -63,6 +85,8 @@ events for atomic commits correctly. But fixing these bugs is good anyway. · 7 unmodified lines
6385
6486 Contact: Daniel Vetter, respective driver maintainers
6587
88+Level: Advanced
89+
6690 Fallout from atomic KMS
6791 -----------------------
6892
@@ -91,6 +115,8 @@ interfaces to fix these issues: · 22 unmodified lines
91115
92116 Contact: Daniel Vetter
93117
118+Level: Intermediate
119+
94120 Get rid of dev->struct_mutex from GEM drivers
95121 ---------------------------------------------
96122
@@ -114,6 +140,8 @@ fine-grained per-buffer object and per-context lockings scheme. Currently only t · 17 unmodified lines
114140
115141 Contact: Daniel Vetter, respective driver maintainers
116142
143+Level: Advanced
144+
117145 Convert instances of dev_info/dev_err/dev_warn to their DRM_DEV_* equivalent
118146 ----------------------------------------------------------------------------
119147
@@ -129,6 +157,8 @@ are better. · 9 unmodified lines
129157
130158 Contact: Sean Paul, Maintainer of the driver you plan to convert
131159
160+Level: Starter
161+
132162 Convert drivers to use simple modeset suspend/resume
133163 ----------------------------------------------------
134164
@@ -139,6 +169,8 @@ of the atomic suspend/resume code in older atomic modeset drivers. · 4 unmodified lines
139169
140170 Contact: Maintainer of the driver you plan to convert
141171
172+Level: Intermediate
173+
142174 Convert drivers to use drm_fb_helper_fbdev_setup/teardown()
143175 -----------------------------------------------------------
144176
@@ -157,6 +189,8 @@ probably use drm_fb_helper_fbdev_teardown(). · 12 unmodified lines
157189
158190 Contact: Maintainer of the driver you plan to convert
159191
192+Level: Intermediate
193+
160194 Clean up mmap forwarding
161195 ------------------------
162196
@@ -166,14 +200,16 @@ There's drm_gem_prime_mmap() for this now, but still needs to be rolled out. · 3 unmodified lines
166200
167201 Contact: Daniel Vetter
168202
203+Level: Intermediate
204+
169205 Generic fbdev defio support
170206 ---------------------------
171207
172208 The defio support code in the fbdev core has some very specific requirements,
173−which means drivers need to have a special framebuffer for fbdev. Which prevents
174−us from using the generic fbdev emulation code everywhere. The main issue is
175−that it uses some fields in struct page itself, which breaks shmem gem objects
176−(and other things).
209+which means drivers need to have a special framebuffer for fbdev. The main
210+issue is that it uses some fields in struct page itself, which breaks shmem
211+gem objects (and other things). To support defio, affected drivers require
212+the use of a shadow buffer, which may add CPU and memory overhead.
177213
178214 Possible solution would be to write our own defio mmap code in the drm fbdev
179215 emulation. It would need to fully wrap the existing mmap ops, forwarding
@@ -196,6 +232,8 @@ Might be good to also have some igt testcases for this. · 16 unmodified lines
196232
197233 Contact: Daniel Vetter, Noralf Tronnes
198234
235+Level: Advanced
236+
199237 idr_init_base()
200238 ---------------
201239
@@ -206,6 +244,8 @@ efficient. · 4 unmodified lines
206244
207245 Contact: Daniel Vetter
208246
247+Level: Starter
248+
209249 struct drm_gem_object_funcs
210250 ---------------------------
211251
@@ -216,6 +256,8 @@ We also need a 2nd version of the CMA define that doesn't require the · 4 unmodified lines
216256 vmapping to be present (different hook for prime importing). Plus this needs to
217257 be rolled out to all drivers using their own implementations, too.
218258
259+Level: Intermediate
260+
219261 Use DRM_MODESET_LOCK_ALL_* helpers instead of boilerplate
220262 ---------------------------------------------------------
221263
@@ -231,6 +273,8 @@ As a reference, take a look at the conversions already completed in drm core. · 9 unmodified lines
231273
232274 Contact: Sean Paul, respective driver maintainers
233275
276+Level: Starter
277+
234278 Rename CMA helpers to DMA helpers
235279 ---------------------------------
236280
@@ -241,6 +285,9 @@ no one knows what that means) since underneath they just use dma_alloc_coherent. · 4 unmodified lines
241285
242286 Contact: Laurent Pinchart, Daniel Vetter
243287
288+Level: Intermediate (mostly because it is a huge tasks without good partial
289+milestones, not technically itself that challenging)
290+
244291 Convert direct mode.vrefresh accesses to use drm_mode_vrefresh()
245292 ----------------------------------------------------------------
246293
@@ -259,6 +306,8 @@ drm_display_mode to avoid future use. · 12 unmodified lines
259306
260307 Contact: Sean Paul
261308
309+Level: Starter
310+
262311 Remove drm_display_mode.hsync
263312 -----------------------------
264313
@@ -269,6 +318,8 @@ it to use drm_mode_hsync() instead. · 4 unmodified lines
269318
270319 Contact: Sean Paul
271320
321+Level: Starter
322+
272323 drm_fb_helper tasks
273324 -------------------
274325
@@ -284,6 +335,8 @@ drm_fb_helper tasks · 9 unmodified lines
284335 removed: drm_fb_helper_single_add_all_connectors(),
285336 drm_fb_helper_add_one_connector() and drm_fb_helper_remove_one_connector().
286337
338+Level: Intermediate
339+
287340 connector register/unregister fixes
288341 -----------------------------------
289342
@@ -296,21 +349,11 @@ connector register/unregister fixes · 6 unmodified lines
296349 drm_dp_aux_init, and moving the actual registering into a late_register
297350 callback as recommended in the kerneldoc.
298351
352+Level: Intermediate
353+
299354 Core refactorings
300355 =================
301356
302−Clean up the DRM header mess
303−----------------------------
304−
305−The DRM subsystem originally had only one huge global header, ``drmP.h``. This
306−is now split up, but many source files still include it. The remaining part of
307−the cleanup work here is to replace any ``#include <drm/drmP.h>`` by only the
308−headers needed (and fixing up any missing pre-declarations in the headers).
309−
310−In the end no .c file should need to include ``drmP.h`` anymore.
311−
312−Contact: Daniel Vetter
313−
314357 Make panic handling work
315358 ------------------------
316359
@@ -350,6 +393,8 @@ This is a really varied tasks with lots of little bits and pieces: · 33 unmodified lines
350393
351394 Contact: Daniel Vetter
352395
396+Level: Advanced
397+
353398 Clean up the debugfs support
354399 ----------------------------
355400
@@ -379,6 +424,8 @@ There's a bunch of issues with it: · 23 unmodified lines
379424
380425 Contact: Daniel Vetter
381426
427+Level: Intermediate
428+
382429 KMS cleanups
383430 ------------
384431
@@ -394,6 +441,8 @@ Some of these date from the very introduction of KMS in 2008 ... · 9 unmodified lines
394441 end, for which we could add drm_*_cleanup_kfree(). And then there's the (for
395442 historical reasons) misnamed drm_primary_helper_destroy() function.
396443
444+Level: Intermediate
445+
397446 Better Testing
398447 ==============
399448
@@ -402,6 +451,8 @@ Enable trinity for DRM · 2 unmodified lines
402451
403452 And fix up the fallout. Should be really interesting ...
404453
454+Level: Advanced
455+
405456 Make KMS tests in i-g-t generic
406457 -------------------------------
407458
@@ -415,6 +466,8 @@ converting things over. For modeset tests we also first need a bit of · 7 unmodified lines
415466 infrastructure to use dumb buffers for untiled buffers, to be able to run all
416467 the non-i915 specific modeset tests.
417468
469+Level: Advanced
470+
418471 Extend virtual test driver (VKMS)
419472 ---------------------------------
420473
@@ -424,6 +477,8 @@ fit the available time. · 3 unmodified lines
424477
425478 Contact: Daniel Vetter
426479
480+Level: See details
481+
427482 Backlight Refactoring
428483 ---------------------
429484
@@ -437,6 +492,8 @@ Plan to fix this: · 7 unmodified lines
437492
438493 Contact: Daniel Vetter
439494
495+Level: Intermediate
496+
440497 Driver Specific
441498 ===============
442499
@@ -450,13 +507,6 @@ See drivers/gpu/drm/amd/display/TODO for tasks. · 7 unmodified lines
450507
451508 Contact: Harry Wentland, Alex Deucher
452509
453−i915
454−----
455−
456−- Our early/late pm callbacks could be removed in favour of using
457− device_link_add to model the dependency between i915 and snd_had. See
458− https://dri.freedesktop.org/docs/drm/driver-api/device_link.html
459−
460510 Bootsplash
461511 ==========
462512
@@ -472,5 +522,36 @@ for fbdev. · 9 unmodified lines
472522
473523 Contact: Sam Ravnborg
474524
525+Level: Advanced
526+
475527 Outside DRM
476528 ===========
529+
530+Convert fbdev drivers to DRM
531+----------------------------
532+
533+There are plenty of fbdev drivers for older hardware. Some hwardware has
534+become obsolete, but some still provides good(-enough) framebuffers. The
535+drivers that are still useful should be converted to DRM and afterwards
536+removed from fbdev.
537+
538+Very simple fbdev drivers can best be converted by starting with a new
539+DRM driver. Simple KMS helpers and SHMEM should be able to handle any
540+existing hardware. The new driver's call-back functions are filled from
541+existing fbdev code.
542+
543+More complex fbdev drivers can be refactored step-by-step into a DRM
544+driver with the help of the DRM fbconv helpers. [1] These helpers provide
545+the transition layer between the DRM core infrastructure and the fbdev
546+driver interface. Create a new DRM driver on top of the fbconv helpers,
547+copy over the fbdev driver, and hook it up to the DRM code. Examples for
548+several fbdev drivers are available at [1] and a tutorial of this process
549+available at [2]. The result is a primitive DRM driver that can run X11
550+and Weston.
551+
552+ - [1] https://gitlab.freedesktop.org/tzimmermann/linux/tree/fbconv
553+ - [2] https://gitlab.freedesktop.org/tzimmermann/linux/blob/fbconv/drivers/gpu/drm/drm_fbconv_helper.c
554+
555+Contact: Thomas Zimmermann <tzimmermann@suse.de>
556+
557+Level: Advanced
Documentation/hwmon/index.rst+1−0
@@ -7,6 +7,7 @@ Linux Hardware Monitoring · 6 unmodified lines
77
88 hwmon-kernel-api
99 pmbus-core
10+ inspur-ipsps1
1011 submitting-patches
1112 sysfs-interface
1213 userspace-tools
Documentation/hwmon/inspur-ipsps1.rst+1−1
@@ -1,5 +1,5 @@
11 Kernel driver inspur-ipsps1
2−=======================
2+===========================
33
44 Supported chips:
55
Documentation/hwmon/k10temp.rst+17−1
@@ -21,10 +21,17 @@ Supported chips: · 20 unmodified lines
2121
2222 * AMD Family 14h processors: "Brazos" (C/E/G/Z-Series)
2323
24−* AMD Family 15h processors: "Bulldozer" (FX-Series), "Trinity", "Kaveri", "Carrizo"
24+* AMD Family 15h processors: "Bulldozer" (FX-Series), "Trinity", "Kaveri",
25+ "Carrizo", "Stoney Ridge", "Bristol Ridge"
2526
2627 * AMD Family 16h processors: "Kabini", "Mullins"
2728
29+* AMD Family 17h processors: "Zen", "Zen 2"
30+
31+* AMD Family 18h processors: "Hygon Dhyana"
32+
33+* AMD Family 19h processors: "Zen 3"
34+
2835 Prefix: 'k10temp'
2936
3037 Addresses scanned: PCI space
@@ -110,3 +117,12 @@ The maximum value for Tctl is available in the file temp1_max. · 79 unmodified lines
110117 If the BIOS has enabled hardware temperature control, the threshold at
111118 which the processor will throttle itself to avoid damage is available in
112119 temp1_crit and temp1_crit_hyst.
120+
121+On some AMD CPUs, there is a difference between the die temperature (Tdie) and
122+the reported temperature (Tctl). Tdie is the real measured temperature, and
123+Tctl is used for fan control. While Tctl is always available as temp1_input,
124+the driver exports Tdie temperature as temp2_input for those CPUs which support
125+it.
126+
127+Models from 17h family report relative temperature, the driver aims to
128+compensate and report the real temperature.
Documentation/networking/device_drivers/intel/e100.rst+7−7
@@ -1,8 +1,8 @@
11 .. SPDX-License-Identifier: GPL-2.0+
22
3−==============================================================
4−Linux* Base Driver for the Intel(R) PRO/100 Family of Adapters
5−==============================================================
3+=============================================================
4+Linux Base Driver for the Intel(R) PRO/100 Family of Adapters
5+=============================================================
66
77 June 1, 2018
88
@@ -21,7 +21,7 @@ Contents · 12 unmodified lines
2121 In This Release
2222 ===============
2323
24−This file describes the Linux* Base Driver for the Intel(R) PRO/100 Family of
24+This file describes the Linux Base Driver for the Intel(R) PRO/100 Family of
2525 Adapters. This driver includes support for Itanium(R)2-based systems.
2626
2727 For questions related to hardware requirements, refer to the documentation
@@ -138,9 +138,9 @@ version 1.6 or later is required for this functionality. · 110 unmodified lines
138138 The latest release of ethtool can be found from
139139 https://www.kernel.org/pub/software/network/ethtool/
140140
141−Enabling Wake on LAN* (WoL)
142−---------------------------
143−WoL is provided through the ethtool* utility. For instructions on
141+Enabling Wake on LAN (WoL)
142+--------------------------
143+WoL is provided through the ethtool utility. For instructions on
144144 enabling WoL with ethtool, refer to the ethtool man page. WoL will be
145145 enabled on the system during the next shut down or reboot. For this
146146 driver version, in order to enable WoL, the e100 driver must be loaded
Documentation/networking/device_drivers/intel/e1000.rst+6−6
@@ -1,8 +1,8 @@
11 .. SPDX-License-Identifier: GPL-2.0+
22
3−===========================================================
4−Linux* Base Driver for Intel(R) Ethernet Network Connection
5−===========================================================
3+==========================================================
4+Linux Base Driver for Intel(R) Ethernet Network Connection
5+==========================================================
66
77 Intel Gigabit Linux driver.
88 Copyright(c) 1999 - 2013 Intel Corporation.
@@ -438,10 +438,10 @@ ethtool · 429 unmodified lines
438438 The latest release of ethtool can be found from
439439 https://www.kernel.org/pub/software/network/ethtool/
440440
441−Enabling Wake on LAN* (WoL)
442−---------------------------
441+Enabling Wake on LAN (WoL)
442+--------------------------
443443
444− WoL is configured through the ethtool* utility.
444+ WoL is configured through the ethtool utility.
445445
446446 WoL will be enabled on the system during the next shut down or reboot.
447447 For this driver version, in order to enable WoL, the e1000 driver must be
Documentation/networking/device_drivers/intel/e1000e.rst+7−7
@@ -1,8 +1,8 @@
11 .. SPDX-License-Identifier: GPL-2.0+
22
3−======================================================
4−Linux* Driver for Intel(R) Ethernet Network Connection
5−======================================================
3+=====================================================
4+Linux Driver for Intel(R) Ethernet Network Connection
5+=====================================================
66
77 Intel Gigabit Linux driver.
88 Copyright(c) 2008-2018 Intel Corporation.
@@ -338,7 +338,7 @@ and higher cannot be forced. Use the autonegotiation advertising setting to · 329 unmodified lines
338338 manually set devices for 1 Gbps and higher.
339339
340340 Speed, duplex, and autonegotiation advertising are configured through the
341−ethtool* utility.
341+ethtool utility.
342342
343343 Caution: Only experienced network administrators should force speed and duplex
344344 or change autonegotiation advertising manually. The settings at the switch must
@@ -351,9 +351,9 @@ will not attempt to auto-negotiate with its link partner since those adapters · 6 unmodified lines
351351 operate only in full duplex and only at their native speed.
352352
353353
354−Enabling Wake on LAN* (WoL)
355−---------------------------
356−WoL is configured through the ethtool* utility.
354+Enabling Wake on LAN (WoL)
355+--------------------------
356+WoL is configured through the ethtool utility.
357357
358358 WoL will be enabled on the system during the next shut down or reboot. For
359359 this driver version, in order to enable WoL, the e1000e driver must be loaded
Documentation/networking/device_drivers/intel/fm10k.rst+5−5
@@ -1,8 +1,8 @@
11 .. SPDX-License-Identifier: GPL-2.0+
22
3−==============================================================
4−Linux* Base Driver for Intel(R) Ethernet Multi-host Controller
5−==============================================================
3+=============================================================
4+Linux Base Driver for Intel(R) Ethernet Multi-host Controller
5+=============================================================
66
77 August 20, 2018
88 Copyright(c) 2015-2018 Intel Corporation.
@@ -120,8 +120,8 @@ rx-flow-hash tcp4|udp4|ah4|esp4|sctp4|tcp6|udp6|ah6|esp6|sctp6 m|v|t|s|d|f|n|r · 111 unmodified lines
120120 Known Issues/Troubleshooting
121121 ============================
122122
123−Enabling SR-IOV in a 64-bit Microsoft* Windows Server* 2012/R2 guest OS under Linux KVM
124−---------------------------------------------------------------------------------------
123+Enabling SR-IOV in a 64-bit Microsoft Windows Server 2012/R2 guest OS under Linux KVM
124+-------------------------------------------------------------------------------------
125125 KVM Hypervisor/VMM supports direct assignment of a PCIe device to a VM. This
126126 includes traditional PCIe devices, as well as SR-IOV-capable devices based on
127127 the Intel Ethernet Controller XL710.
Documentation/networking/device_drivers/intel/i40e.rst+4−4
@@ -1,8 +1,8 @@
11 .. SPDX-License-Identifier: GPL-2.0+
22
3−==================================================================
4−Linux* Base Driver for the Intel(R) Ethernet Controller 700 Series
5−==================================================================
3+=================================================================
4+Linux Base Driver for the Intel(R) Ethernet Controller 700 Series
5+=================================================================
66
77 Intel 40 Gigabit Linux driver.
88 Copyright(c) 1999-2018 Intel Corporation.
@@ -384,7 +384,7 @@ NOTE: You cannot set the speed for devices based on the Intel(R) Ethernet · 375 unmodified lines
384384 Network Adapter XXV710 based devices.
385385
386386 Speed, duplex, and autonegotiation advertising are configured through the
387−ethtool* utility.
387+ethtool utility.
388388
389389 Caution: Only experienced network administrators should force speed and duplex
390390 or change autonegotiation advertising manually. The settings at the switch must
Documentation/networking/device_drivers/intel/iavf.rst+4−4
@@ -1,8 +1,8 @@
11 .. SPDX-License-Identifier: GPL-2.0+
22
3−==================================================================
4−Linux* Base Driver for Intel(R) Ethernet Adaptive Virtual Function
5−==================================================================
3+=================================================================
4+Linux Base Driver for Intel(R) Ethernet Adaptive Virtual Function
5+=================================================================
66
77 Intel Ethernet Adaptive Virtual Function Linux driver.
88 Copyright(c) 2013-2018 Intel Corporation.
@@ -19,7 +19,7 @@ Contents · 10 unmodified lines
1919 Overview
2020 ========
2121
22−This file describes the iavf Linux* Base Driver. This driver was formerly
22+This file describes the iavf Linux Base Driver. This driver was formerly
2323 called i40evf.
2424
2525 The iavf driver supports the below mentioned virtual function devices and
Documentation/networking/device_drivers/intel/ice.rst+3−3
@@ -1,8 +1,8 @@
11 .. SPDX-License-Identifier: GPL-2.0+
22
3−===================================================================
4−Linux* Base Driver for the Intel(R) Ethernet Connection E800 Series
5−===================================================================
3+==================================================================
4+Linux Base Driver for the Intel(R) Ethernet Connection E800 Series
5+==================================================================
66
77 Intel ice Linux driver.
88 Copyright(c) 2018 Intel Corporation.
Documentation/networking/device_drivers/intel/igb.rst+6−6
@@ -1,8 +1,8 @@
11 .. SPDX-License-Identifier: GPL-2.0+
22
3−===========================================================
4−Linux* Base Driver for Intel(R) Ethernet Network Connection
5−===========================================================
3+==========================================================
4+Linux Base Driver for Intel(R) Ethernet Network Connection
5+==========================================================
66
77 Intel Gigabit Linux driver.
88 Copyright(c) 1999-2018 Intel Corporation.
@@ -129,9 +129,9 @@ version is required for this functionality. Download it at: · 120 unmodified lines
129129 https://www.kernel.org/pub/software/network/ethtool/
130130
131131
132−Enabling Wake on LAN* (WoL)
133−---------------------------
134−WoL is configured through the ethtool* utility.
132+Enabling Wake on LAN (WoL)
133+--------------------------
134+WoL is configured through the ethtool utility.
135135
136136 WoL will be enabled on the system during the next shut down or reboot. For
137137 this driver version, in order to enable WoL, the igb driver must be loaded
Documentation/networking/device_drivers/intel/igbvf.rst+3−3
@@ -1,8 +1,8 @@
11 .. SPDX-License-Identifier: GPL-2.0+
22
3−============================================================
4−Linux* Base Virtual Function Driver for Intel(R) 1G Ethernet
5−============================================================
3+===========================================================
4+Linux Base Virtual Function Driver for Intel(R) 1G Ethernet
5+===========================================================
66
77 Intel Gigabit Virtual Function Linux driver.
88 Copyright(c) 1999-2018 Intel Corporation.
Documentation/networking/device_drivers/intel/ixgbe.rst+5−5
@@ -1,8 +1,8 @@
11 .. SPDX-License-Identifier: GPL-2.0+
22
3−=============================================================================
4−Linux* Base Driver for the Intel(R) Ethernet 10 Gigabit PCI Express Adapters
5−=============================================================================
3+===========================================================================
4+Linux Base Driver for the Intel(R) Ethernet 10 Gigabit PCI Express Adapters
5+===========================================================================
66
77 Intel 10 Gigabit Linux driver.
88 Copyright(c) 1999-2018 Intel Corporation.
@@ -519,8 +519,8 @@ The offload is also supported for ixgbe's VFs, but the VF must be set as · 510 unmodified lines
519519 Known Issues/Troubleshooting
520520 ============================
521521
522−Enabling SR-IOV in a 64-bit Microsoft* Windows Server* 2012/R2 guest OS
523−-----------------------------------------------------------------------
522+Enabling SR-IOV in a 64-bit Microsoft Windows Server 2012/R2 guest OS
523+---------------------------------------------------------------------
524524 Linux KVM Hypervisor/VMM supports direct assignment of a PCIe device to a VM.
525525 This includes traditional PCIe devices, as well as SR-IOV-capable devices based
526526 on the Intel Ethernet Controller XL710.
Documentation/networking/device_drivers/intel/ixgbevf.rst+3−3
@@ -1,8 +1,8 @@
11 .. SPDX-License-Identifier: GPL-2.0+
22
3−=============================================================
4−Linux* Base Virtual Function Driver for Intel(R) 10G Ethernet
5−=============================================================
3+============================================================
4+Linux Base Virtual Function Driver for Intel(R) 10G Ethernet
5+============================================================
66
77 Intel 10 Gigabit Virtual Function Linux driver.
88 Copyright(c) 1999-2018 Intel Corporation.
Documentation/networking/device_drivers/pensando/ionic.rst+6−4
@@ -1,8 +1,8 @@
11 .. SPDX-License-Identifier: GPL-2.0+
22
3−==========================================================
4−Linux* Driver for the Pensando(R) Ethernet adapter family
5−==========================================================
3+========================================================
4+Linux Driver for the Pensando(R) Ethernet adapter family
5+========================================================
66
77 Pensando Linux Ethernet driver.
88 Copyright(c) 2019 Pensando Systems, Inc
@@ -36,8 +36,10 @@ Support · 27 unmodified lines
3636 =======
3737 For general Linux networking support, please use the netdev mailing
3838 list, which is monitored by Pensando personnel::
39+
3940 netdev@vger.kernel.org
4041
4142 For more specific support needs, please use the Pensando driver support
4243 email::
43− drivers@pensando.io
44+
45+ drivers@pensando.io
Documentation/networking/ip-sysctl.txt+7−4
@@ -207,8 +207,8 @@ TCP variables: · 206 unmodified lines
207207
208208 somaxconn - INTEGER
209209 Limit of socket listen() backlog, known in userspace as SOMAXCONN.
210− Defaults to 128. See also tcp_max_syn_backlog for additional tuning
211− for TCP sockets.
210+ Defaults to 4096. (Was 128 before linux-5.4)
211+ See also tcp_max_syn_backlog for additional tuning for TCP sockets.
212212
213213 tcp_abort_on_overflow - BOOLEAN
214214 If listening service is too slow to accept new connections,
@@ -408,11 +408,14 @@ tcp_max_orphans - INTEGER · 193 unmodified lines
408408 up to ~64K of unswappable memory.
409409
410410 tcp_max_syn_backlog - INTEGER
411− Maximal number of remembered connection requests, which have not
412− received an acknowledgment from connecting client.
411+ Maximal number of remembered connection requests (SYN_RECV),
412+ which have not received an acknowledgment from connecting client.
413+ This is a per-listener limit.
413414 The minimal value is 128 for low memory machines, and it will
414415 increase in proportion to the memory of machine.
415416 If server suffers from overload, try increasing this number.
417+ Remember to also check /proc/sys/net/core/somaxconn
418+ A SYN_RECV request socket consumes about 304 bytes of memory.
416419
417420 tcp_max_tw_buckets - INTEGER
418421 Maximal number of timewait sockets held by system simultaneously.
Documentation/networking/net_dim.txt+18−18
@@ -92,16 +92,16 @@ under some conditions. · 91 unmodified lines
9292 Part III: Registering a Network Device to DIM
9393 ==============================================
9494
95−Net DIM API exposes the main function net_dim(struct net_dim *dim,
96−struct net_dim_sample end_sample). This function is the entry point to the Net
95+Net DIM API exposes the main function net_dim(struct dim *dim,
96+struct dim_sample end_sample). This function is the entry point to the Net
9797 DIM algorithm and has to be called every time the driver would like to check if
9898 it should change interrupt moderation parameters. The driver should provide two
99−data structures: struct net_dim and struct net_dim_sample. Struct net_dim
99+data structures: struct dim and struct dim_sample. Struct dim
100100 describes the state of DIM for a specific object (RX queue, TX queue,
101101 other queues, etc.). This includes the current selected profile, previous data
102102 samples, the callback function provided by the driver and more.
103−Struct net_dim_sample describes a data sample, which will be compared to the
104−data sample stored in struct net_dim in order to decide on the algorithm's next
103+Struct dim_sample describes a data sample, which will be compared to the
104+data sample stored in struct dim in order to decide on the algorithm's next
105105 step. The sample should include bytes, packets and interrupts, measured by
106106 the driver.
107107
@@ -110,9 +110,9 @@ main net_dim() function. The recommended method is to call net_dim() on each · 2 unmodified lines
110110 interrupt. Since Net DIM has a built-in moderation and it might decide to skip
111111 iterations under certain conditions, there is no need to moderate the net_dim()
112112 calls as well. As mentioned above, the driver needs to provide an object of type
113−struct net_dim to the net_dim() function call. It is advised for each entity
114−using Net DIM to hold a struct net_dim as part of its data structure and use it
115−as the main Net DIM API object. The struct net_dim_sample should hold the latest
113+struct dim to the net_dim() function call. It is advised for each entity
114+using Net DIM to hold a struct dim as part of its data structure and use it
115+as the main Net DIM API object. The struct dim_sample should hold the latest
116116 bytes, packets and interrupts count. No need to perform any calculations, just
117117 include the raw data.
118118
@@ -132,19 +132,19 @@ usage is not complete but it should make the outline of the usage clear. · 13 unmodified lines
132132
133133 my_driver.c:
134134
135−#include <linux/net_dim.h>
135+#include <linux/dim.h>
136136
137137 /* Callback for net DIM to schedule on a decision to change moderation */
138138 void my_driver_do_dim_work(struct work_struct *work)
139139 {
140− /* Get struct net_dim from struct work_struct */
141− struct net_dim *dim = container_of(work, struct net_dim,
142− work);
140+ /* Get struct dim from struct work_struct */
141+ struct dim *dim = container_of(work, struct dim,
142+ work);
143143 /* Do interrupt moderation related stuff */
144144 ...
145145
146146 /* Signal net DIM work is done and it should move to next iteration */
147− dim->state = NET_DIM_START_MEASURE;
147+ dim->state = DIM_START_MEASURE;
148148 }
149149
150150 /* My driver's interrupt handler */
@@ -152,13 +152,13 @@ int my_driver_handle_interrupt(struct my_driver_entity *my_entity, ...) · 1 unmodified line
152152 {
153153 ...
154154 /* A struct to hold current measured data */
155− struct net_dim_sample dim_sample;
155+ struct dim_sample dim_sample;
156156 ...
157157 /* Initiate data sample struct with current data */
158− net_dim_sample(my_entity->events,
159− my_entity->packets,
160− my_entity->bytes,
161− &dim_sample);
158+ dim_update_sample(my_entity->events,
159+ my_entity->packets,
160+ my_entity->bytes,
161+ &dim_sample);
162162 /* Call net DIM */
163163 net_dim(&my_entity->dim, dim_sample);
164164 ...
Documentation/networking/tls-offload.rst+4−0
@@ -436,6 +436,10 @@ by the driver: · 435 unmodified lines
436436 encryption.
437437 * ``tx_tls_ooo`` - number of TX packets which were part of a TLS stream
438438 but did not arrive in the expected order.
439+ * ``tx_tls_skip_no_sync_data`` - number of TX packets which were part of
440+ a TLS stream and arrived out-of-order, but skipped the HW offload routine
441+ and went to the regular transmit flow as they were retransmissions of the
442+ connection handshake.
439443 * ``tx_tls_drop_no_sync_data`` - number of TX packets which were part of
440444 a TLS stream dropped, because they arrived out of order and associated
441445 record could not be found.
Documentation/process/coding-style.rst+1−1
@@ -56,7 +56,7 @@ instead of ``double-indenting`` the ``case`` labels. E.g.: · 55 unmodified lines
5656 case 'K':
5757 case 'k':
5858 mem <<= 10;
59− /* fall through */
59+ fallthrough;
6060 default:
6161 break;
6262 }
Documentation/process/deprecated.rst+23−10
@@ -122,14 +122,27 @@ memory adjacent to the stack (when built without `CONFIG_VMAP_STACK=y`) · 121 unmodified lines
122122
123123 Implicit switch case fall-through
124124 ---------------------------------
125−The C language allows switch cases to "fall through" when
126−a "break" statement is missing at the end of a case. This,
127−however, introduces ambiguity in the code, as it's not always
128−clear if the missing break is intentional or a bug. As there
129−have been a long list of flaws `due to missing "break" statements
125+The C language allows switch cases to "fall-through" when a "break" statement
126+is missing at the end of a case. This, however, introduces ambiguity in the
127+code, as it's not always clear if the missing break is intentional or a bug.
128+
129+As there have been a long list of flaws `due to missing "break" statements
130130 <https://cwe.mitre.org/data/definitions/484.html>`_, we no longer allow
131−"implicit fall-through". In order to identify an intentional fall-through
132−case, we have adopted the marking used by static analyzers: a comment
133−saying `/* Fall through */`. Once the C++17 `__attribute__((fallthrough))`
134−is more widely handled by C compilers, static analyzers, and IDEs, we can
135−switch to using that instead.
131+"implicit fall-through".
132+
133+In order to identify intentional fall-through cases, we have adopted a
134+pseudo-keyword macro 'fallthrough' which expands to gcc's extension
135+__attribute__((__fallthrough__)). `Statement Attributes
136+<https://gcc.gnu.org/onlinedocs/gcc/Statement-Attributes.html>`_
137+
138+When the C17/C18 [[fallthrough]] syntax is more commonly supported by
139+C compilers, static analyzers, and IDEs, we can switch to using that syntax
140+for the macro pseudo-keyword.
141+
142+All switch/case blocks must end in one of:
143+
144+ break;
145+ fallthrough;
146+ continue;
147+ goto <label>;
148+ return [expression];
Documentation/usb/rio.rst+0−109
@@ -1,109 +0,0 @@
1−============
2−Diamonds Rio
3−============
4−
5−Copyright (C) 1999, 2000 Bruce Tenison
6−
7−Portions Copyright (C) 1999, 2000 David Nelson
8−
9−Thanks to David Nelson for guidance and the usage of the scanner.txt
10−and scanner.c files to model our driver and this informative file.
11−
12−Mar. 2, 2000
13−
14−Changes
15−=======
16−
17−- Initial Revision
18−
19−
20−Overview
21−========
22−
23−This README will address issues regarding how to configure the kernel
24−to access a RIO 500 mp3 player.
25−Before I explain how to use this to access the Rio500 please be warned:
26−
27−.. warning::
28−
29− Please note that this software is still under development. The authors
30− are in no way responsible for any damage that may occur, no matter how
31− inconsequential.
32−
33−It seems that the Rio has a problem when sending .mp3 with low batteries.
34−I suggest when the batteries are low and you want to transfer stuff that you
35−replace it with a fresh one. In my case, what happened is I lost two 16kb
36−blocks (they are no longer usable to store information to it). But I don't
37−know if that's normal or not; it could simply be a problem with the flash
38−memory.
39−
40−In an extreme case, I left my Rio playing overnight and the batteries wore
41−down to nothing and appear to have corrupted the flash memory. My RIO
42−needed to be replaced as a result. Diamond tech support is aware of the
43−problem. Do NOT allow your batteries to wear down to nothing before
44−changing them. It appears RIO 500 firmware does not handle low battery
45−power well at all.
46−
47−On systems with OHCI controllers, the kernel OHCI code appears to have
48−power on problems with some chipsets. If you are having problems
49−connecting to your RIO 500, try turning it on first and then plugging it
50−into the USB cable.
51−
52−Contact Information
53−-------------------
54−
55− The main page for the project is hosted at sourceforge.net in the following
56− URL: <http://rio500.sourceforge.net>. You can also go to the project's
57− sourceforge home page at: <http://sourceforge.net/projects/rio500/>.
58− There is also a mailing list: rio500-users@lists.sourceforge.net
59−
60−Authors
61−-------
62−
63−Most of the code was written by Cesar Miquel <miquel@df.uba.ar>. Keith
64−Clayton <kclayton@jps.net> is incharge of the PPC port and making sure
65−things work there. Bruce Tenison <btenison@dibbs.net> is adding support
66−for .fon files and also does testing. The program will mostly sure be
67−re-written and Pete Ikusz along with the rest will re-design it. I would
68−also like to thank Tri Nguyen <tmn_3022000@hotmail.com> who provided use
69−with some important information regarding the communication with the Rio.
70−
71−Additional Information and userspace tools
72−
73− http://rio500.sourceforge.net/
74−
75−
76−Requirements
77−============
78−
79−A host with a USB port running a Linux kernel with RIO 500 support enabled.
80−
81−The driver is a module called rio500, which should be automatically loaded
82−as you plug in your device. If that fails you can manually load it with
83−
84− modprobe rio500
85−
86−Udev should automatically create a device node as soon as plug in your device.
87−If that fails, you can manually add a device for the USB rio500::
88−
89− mknod /dev/usb/rio500 c 180 64
90−
91−In that case, set appropriate permissions for /dev/usb/rio500 (don't forget
92−about group and world permissions). Both read and write permissions are
93−required for proper operation.
94−
95−That's it. The Rio500 Utils at: http://rio500.sourceforge.net should
96−be able to access the rio500.
97−
98−Limits
99−======
100−
101−You can use only a single rio500 device at a time with your computer.
102−
103−Bugs
104−====
105−
106−If you encounter any problems feel free to drop me an email.
107−
108−Bruce Tenison
109−btenison@dibbs.net
MAINTAINERS+35−29
@@ -1251,6 +1251,7 @@ F: Documentation/devicetree/bindings/display/arm,hdlcd.txt · 1250 unmodified lines
12511251 ARM KOMEDA DRM-KMS DRIVER
12521252 M: James (Qian) Wang <james.qian.wang@arm.com>
12531253 M: Liviu Dudau <liviu.dudau@arm.com>
1254+M: Mihail Atanassov <mihail.atanassov@arm.com>
12541255 L: Mali DP Maintainers <malidp@foss.arm.com>
12551256 S: Supported
12561257 T: git git://anongit.freedesktop.org/drm/drm-misc
@@ -2167,12 +2168,10 @@ F: arch/arm64/boot/dts/realtek/ · 910 unmodified lines
21672168 F: Documentation/devicetree/bindings/arm/realtek.yaml
21682169
21692170 ARM/RENESAS ARM64 ARCHITECTURE
2170−M: Simon Horman <horms@verge.net.au>
21712171 M: Geert Uytterhoeven <geert+renesas@glider.be>
21722172 M: Magnus Damm <magnus.damm@gmail.com>
21732173 L: linux-renesas-soc@vger.kernel.org
21742174 Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/
2175−T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
21762175 T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
21772176 S: Supported
21782177 F: arch/arm64/boot/dts/renesas/
@@ -2284,12 +2283,10 @@ S: Maintained · 105 unmodified lines
22842283 F: drivers/media/platform/s5p-mfc/
22852284
22862285 ARM/SHMOBILE ARM ARCHITECTURE
2287−M: Simon Horman <horms@verge.net.au>
22882286 M: Geert Uytterhoeven <geert+renesas@glider.be>
22892287 M: Magnus Damm <magnus.damm@gmail.com>
22902288 L: linux-renesas-soc@vger.kernel.org
22912289 Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/
2292−T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
22932290 T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
22942291 S: Supported
22952292 F: arch/arm/boot/dts/emev2*
@@ -2329,11 +2326,13 @@ F: drivers/edac/altera_edac. · 33 unmodified lines
23292326
23302327 ARM/SPREADTRUM SoC SUPPORT
23312328 M: Orson Zhai <orsonzhai@gmail.com>
2332−M: Baolin Wang <baolin.wang@linaro.org>
2329+M: Baolin Wang <baolin.wang7@gmail.com>
23332330 M: Chunyan Zhang <zhang.lyra@gmail.com>
23342331 S: Maintained
23352332 F: arch/arm64/boot/dts/sprd
23362333 N: sprd
2334+N: sc27xx
2335+N: sc2731
23372336
23382337 ARM/STI ARCHITECTURE
23392338 M: Patrice Chotard <patrice.chotard@st.com>
@@ -3057,6 +3056,7 @@ M: Daniel Borkmann <daniel@iogearbox.net> · 717 unmodified lines
30573056 R: Martin KaFai Lau <kafai@fb.com>
30583057 R: Song Liu <songliubraving@fb.com>
30593058 R: Yonghong Song <yhs@fb.com>
3059+R: Andrii Nakryiko <andriin@fb.com>
30603060 L: netdev@vger.kernel.org
30613061 L: bpf@vger.kernel.org
30623062 T: git git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git
@@ -3102,7 +3102,7 @@ S: Supported · 39 unmodified lines
31023102 F: arch/arm64/net/
31033103
31043104 BPF JIT for MIPS (32-BIT AND 64-BIT)
3105−M: Paul Burton <paul.burton@mips.com>
3105+M: Paul Burton <paulburton@kernel.org>
31063106 L: netdev@vger.kernel.org
31073107 L: bpf@vger.kernel.org
31083108 S: Maintained
@@ -3189,7 +3189,7 @@ N: bcm216* · 80 unmodified lines
31893189 N: kona
31903190 F: arch/arm/mach-bcm/
31913191
3192−BROADCOM BCM2835 ARM ARCHITECTURE
3192+BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
31933193 M: Eric Anholt <eric@anholt.net>
31943194 M: Stefan Wahren <wahrenst@gmx.net>
31953195 L: bcm-kernel-feedback-list@broadcom.com
@@ -3197,6 +3197,7 @@ L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers) · 1 unmodified line
31973197 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
31983198 T: git git://github.com/anholt/linux
31993199 S: Maintained
3200+N: bcm2711
32003201 N: bcm2835
32013202 F: drivers/staging/vc04_services
32023203
@@ -3243,8 +3244,6 @@ S: Maintained · 40 unmodified lines
32433244 F: drivers/usb/gadget/udc/bcm63xx_udc.*
32443245
32453246 BROADCOM BCM7XXX ARM ARCHITECTURE
3246−M: Brian Norris <computersforpeace@gmail.com>
3247−M: Gregory Fong <gregory.0xf0@gmail.com>
32483247 M: Florian Fainelli <f.fainelli@gmail.com>
32493248 M: bcm-kernel-feedback-list@broadcom.com
32503249 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -3742,7 +3741,6 @@ F: drivers/crypto/cavium/cpt/ · 491 unmodified lines
37423741
37433742 CAVIUM THUNDERX2 ARM64 SOC
37443743 M: Robert Richter <rrichter@cavium.com>
3745−M: Jayachandran C <jnair@caviumnetworks.com>
37463744 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
37473745 S: Maintained
37483746 F: arch/arm64/boot/dts/cavium/thunder2-99xx*
@@ -8017,7 +8015,7 @@ S: Maintained · 4268 unmodified lines
80178015 F: drivers/usb/atm/ueagle-atm.c
80188016
80198017 IMGTEC ASCII LCD DRIVER
8020−M: Paul Burton <paul.burton@mips.com>
8018+M: Paul Burton <paulburton@kernel.org>
80218019 S: Maintained
80228020 F: Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt
80238021 F: drivers/auxdisplay/img-ascii-lcd.c
@@ -9138,7 +9136,7 @@ F: drivers/auxdisplay/ks0108.c · 1114 unmodified lines
91389136 F: include/linux/ks0108.h
91399137
91409138 L3MDEV
9141−M: David Ahern <dsa@cumulusnetworks.com>
9139+M: David Ahern <dsahern@kernel.org>
91429140 L: netdev@vger.kernel.org
91439141 S: Maintained
91449142 F: net/l3mdev
@@ -9199,6 +9197,7 @@ M: Pavel Machek <pavel@ucw.cz> · 54 unmodified lines
91999197 R: Dan Murphy <dmurphy@ti.com>
92009198 L: linux-leds@vger.kernel.org
92019199 T: git git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds.git
9200+T: git git://git.kernel.org/pub/scm/linux/kernel/git/pavel/linux-leds.git
92029201 S: Maintained
92039202 F: Documentation/devicetree/bindings/leds/
92049203 F: drivers/leds/
@@ -10270,7 +10269,7 @@ MEDIATEK ETHERNET DRIVER · 1065 unmodified lines
1027010269 M: Felix Fietkau <nbd@openwrt.org>
1027110270 M: John Crispin <john@phrozen.org>
1027210271 M: Sean Wang <sean.wang@mediatek.com>
10273−M: Nelson Chang <nelson.chang@mediatek.com>
10272+M: Mark Lee <Mark-MC.Lee@mediatek.com>
1027410273 L: netdev@vger.kernel.org
1027510274 S: Maintained
1027610275 F: drivers/net/ethernet/mediatek/
@@ -10533,8 +10532,12 @@ F: mm/memblock.c · 256 unmodified lines
1053310532 F: Documentation/core-api/boot-time-mm.rst
1053410533
1053510534 MEMORY MANAGEMENT
10535+M: Andrew Morton <akpm@linux-foundation.org>
1053610536 L: linux-mm@kvack.org
1053710537 W: http://www.linux-mm.org
10538+T: quilt https://ozlabs.org/~akpm/mmotm/
10539+T: quilt https://ozlabs.org/~akpm/mmots/
10540+T: git git://github.com/hnaz/linux-mm.git
1053810541 S: Maintained
1053910542 F: include/linux/mm.h
1054010543 F: include/linux/gfp.h
@@ -10843,7 +10846,7 @@ F: drivers/usb/image/microtek.* · 302 unmodified lines
1084310846
1084410847 MIPS
1084510848 M: Ralf Baechle <ralf@linux-mips.org>
10846−M: Paul Burton <paul.burton@mips.com>
10849+M: Paul Burton <paulburton@kernel.org>
1084710850 M: James Hogan <jhogan@kernel.org>
1084810851 L: linux-mips@vger.kernel.org
1084910852 W: http://www.linux-mips.org/
@@ -10857,7 +10860,7 @@ F: arch/mips/ · 7 unmodified lines
1085710860 F: drivers/platform/mips/
1085810861
1085910862 MIPS BOSTON DEVELOPMENT BOARD
10860−M: Paul Burton <paul.burton@mips.com>
10863+M: Paul Burton <paulburton@kernel.org>
1086110864 L: linux-mips@vger.kernel.org
1086210865 S: Maintained
1086310866 F: Documentation/devicetree/bindings/clock/img,boston-clock.txt
@@ -10867,7 +10870,7 @@ F: drivers/clk/imgtec/clk-boston.c · 3 unmodified lines
1086710870 F: include/dt-bindings/clock/boston-clock.h
1086810871
1086910872 MIPS GENERIC PLATFORM
10870−M: Paul Burton <paul.burton@mips.com>
10873+M: Paul Burton <paulburton@kernel.org>
1087110874 L: linux-mips@vger.kernel.org
1087210875 S: Supported
1087310876 F: Documentation/devicetree/bindings/power/mti,mips-cpc.txt
@@ -11422,7 +11425,6 @@ F: include/trace/events/tcp.h · 548 unmodified lines
1142211425 NETWORKING [TLS]
1142311426 M: Boris Pismenny <borisp@mellanox.com>
1142411427 M: Aviad Yehezkel <aviadye@mellanox.com>
11425−M: Dave Watson <davejwatson@fb.com>
1142611428 M: John Fastabend <john.fastabend@gmail.com>
1142711429 M: Daniel Borkmann <daniel@iogearbox.net>
1142811430 M: Jakub Kicinski <jakub.kicinski@netronome.com>
@@ -11559,6 +11561,7 @@ NSDEPS · 130 unmodified lines
1155911561 M: Matthias Maennich <maennich@google.com>
1156011562 S: Maintained
1156111563 F: scripts/nsdeps
11564+F: Documentation/core-api/symbol-namespaces.rst
1156211565
1156311566 NTB AMD DRIVER
1156411567 M: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
@@ -12326,12 +12329,15 @@ F: arch/parisc/ · 761 unmodified lines
1232612329 F: Documentation/parisc/
1232712330 F: drivers/parisc/
1232812331 F: drivers/char/agp/parisc-agp.c
12332+F: drivers/input/misc/hp_sdc_rtc.c
1232912333 F: drivers/input/serio/gscps2.c
12334+F: drivers/input/serio/hp_sdc*
1233012335 F: drivers/parport/parport_gsc.*
1233112336 F: drivers/tty/serial/8250/8250_gsc.c
1233212337 F: drivers/video/fbdev/sti*
1233312338 F: drivers/video/console/sti*
1233412339 F: drivers/video/logo/logo_parisc*
12340+F: include/linux/hp_sdc.h
1233512341
1233612342 PARMAN
1233712343 M: Jiri Pirko <jiri@mellanox.com>
@@ -13375,7 +13381,7 @@ S: Maintained · 1037 unmodified lines
1337513381 F: drivers/scsi/qla1280.[ch]
1337613382
1337713383 QLOGIC QLA2XXX FC-SCSI DRIVER
13378−M: qla2xxx-upstream@qlogic.com
13384+M: hmadhani@marvell.com
1337913385 L: linux-scsi@vger.kernel.org
1338013386 S: Supported
1338113387 F: Documentation/scsi/LICENSE.qla2xxx
@@ -13916,7 +13922,7 @@ F: drivers/mtd/nand/raw/r852.h · 534 unmodified lines
1391613922
1391713923 RISC-V ARCHITECTURE
1391813924 M: Paul Walmsley <paul.walmsley@sifive.com>
13919−M: Palmer Dabbelt <palmer@sifive.com>
13925+M: Palmer Dabbelt <palmer@dabbelt.com>
1392013926 M: Albert Ou <aou@eecs.berkeley.edu>
1392113927 L: linux-riscv@lists.infradead.org
1392213928 T: git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
@@ -14793,7 +14799,7 @@ F: drivers/media/usb/siano/ · 870 unmodified lines
1479314799 F: drivers/media/mmc/siano/
1479414800
1479514801 SIFIVE DRIVERS
14796−M: Palmer Dabbelt <palmer@sifive.com>
14802+M: Palmer Dabbelt <palmer@dabbelt.com>
1479714803 M: Paul Walmsley <paul.walmsley@sifive.com>
1479814804 L: linux-riscv@lists.infradead.org
1479914805 T: git git://github.com/sifive/riscv-linux.git
@@ -14803,7 +14809,7 @@ N: sifive · 3 unmodified lines
1480314809
1480414810 SIFIVE FU540 SYSTEM-ON-CHIP
1480514811 M: Paul Walmsley <paul.walmsley@sifive.com>
14806−M: Palmer Dabbelt <palmer@sifive.com>
14812+M: Palmer Dabbelt <palmer@dabbelt.com>
1480714813 L: linux-riscv@lists.infradead.org
1480814814 T: git git://git.kernel.org/pub/scm/linux/kernel/git/pjw/sifive.git
1480914815 S: Supported
@@ -16778,13 +16784,6 @@ W: http://www.linux-usb.org/usbnet · 1968 unmodified lines
1677816784 S: Maintained
1677916785 F: drivers/net/usb/dm9601.c
1678016786
16781−USB DIAMOND RIO500 DRIVER
16782−M: Cesar Miquel <miquel@df.uba.ar>
16783−L: rio500-users@lists.sourceforge.net
16784−W: http://rio500.sourceforge.net
16785−S: Maintained
16786−F: drivers/usb/misc/rio500*
16787−
1678816787 USB EHCI DRIVER
1678916788 M: Alan Stern <stern@rowland.harvard.edu>
1679016789 L: linux-usb@vger.kernel.org
@@ -17352,6 +17351,12 @@ F: include/linux/vbox_utils.h · 561 unmodified lines
1735217351 F: include/uapi/linux/vbox*.h
1735317352 F: drivers/virt/vboxguest/
1735417353
17354+VIRTUAL BOX SHARED FOLDER VFS DRIVER:
17355+M: Hans de Goede <hdegoede@redhat.com>
17356+L: linux-fsdevel@vger.kernel.org
17357+S: Maintained
17358+F: drivers/staging/vboxsf/*
17359+
1735517360 VIRTUAL SERIO DEVICE DRIVER
1735617361 M: Stephen Chandler Paul <thatslyude@gmail.com>
1735717362 S: Maintained
@@ -17451,7 +17456,7 @@ F: include/linux/regulator/ · 93 unmodified lines
1745117456 K: regulator_get_optional
1745217457
1745317458 VRF
17454−M: David Ahern <dsa@cumulusnetworks.com>
17459+M: David Ahern <dsahern@kernel.org>
1745517460 M: Shrijeet Mukherjee <shrijeet@gmail.com>
1745617461 L: netdev@vger.kernel.org
1745717462 S: Maintained
@@ -18052,6 +18057,7 @@ F: Documentation/vm/zsmalloc.rst · 594 unmodified lines
1805218057 ZSWAP COMPRESSED SWAP CACHING
1805318058 M: Seth Jennings <sjenning@redhat.com>
1805418059 M: Dan Streetman <ddstreet@ieee.org>
18060+M: Vitaly Wool <vitaly.wool@konsulko.com>
1805518061 L: linux-mm@kvack.org
1805618062 S: Maintained
1805718063 F: mm/zswap.c
Makefile+6−7
@@ -2,8 +2,8 @@ · 1 unmodified line
22 VERSION = 5
33 PATCHLEVEL = 4
44 SUBLEVEL = 0
5−EXTRAVERSION = -rc2
6−NAME = Nesting Opossum
5+EXTRAVERSION = -rc7
6+NAME = Kleptomaniac Octopus
77
88 # *DOCUMENTATION*
99 # To see a list of typical targets execute "make help"
@@ -599,7 +599,7 @@ endif · 589 unmodified lines
599599 # in addition to whatever we do anyway.
600600 # Just "make" or "make all" shall build modules as well
601601
602−ifneq ($(filter all _all modules,$(MAKECMDGOALS)),)
602+ifneq ($(filter all _all modules nsdeps,$(MAKECMDGOALS)),)
603603 KBUILD_MODULES := 1
604604 endif
605605
@@ -1037,7 +1037,7 @@ export KBUILD_VMLINUX_OBJS := $(head-y) $(init-y) $(core-y) $(libs-y2) \ · 431 unmodified lines
10371037 export KBUILD_VMLINUX_LIBS := $(libs-y1)
10381038 export KBUILD_LDS := arch/$(SRCARCH)/kernel/vmlinux.lds
10391039 export LDFLAGS_vmlinux
1040−# used by scripts/package/Makefile
1040+# used by scripts/Makefile.package
10411041 export KBUILD_ALLDIRS := $(sort $(filter-out arch/%,$(vmlinux-alldirs)) LICENSES arch include scripts tools)
10421042
10431043 vmlinux-deps := $(KBUILD_LDS) $(KBUILD_VMLINUX_OBJS) $(KBUILD_VMLINUX_LIBS)
@@ -1217,9 +1217,8 @@ PHONY += kselftest · 173 unmodified lines
12171217 kselftest:
12181218 $(Q)$(MAKE) -C $(srctree)/tools/testing/selftests run_tests
12191219
1220−PHONY += kselftest-clean
1221−kselftest-clean:
1222− $(Q)$(MAKE) -C $(srctree)/tools/testing/selftests clean
1220+kselftest-%: FORCE
1221+ $(Q)$(MAKE) -C $(srctree)/tools/testing/selftests $*
12231222
12241223 PHONY += kselftest-merge
12251224 kselftest-merge:
arch/arc/boot/dts/hsdk.dts+23−0
@@ -65,6 +65,14 @@ · 64 unmodified lines
6565 clock-frequency = <33333333>;
6666 };
6767
68+ reg_5v0: regulator-5v0 {
69+ compatible = "regulator-fixed";
70+
71+ regulator-name = "5v0-supply";
72+ regulator-min-microvolt = <5000000>;
73+ regulator-max-microvolt = <5000000>;
74+ };
75+
6876 cpu_intc: cpu-interrupt-controller {
6977 compatible = "snps,archs-intc";
7078 interrupt-controller;
@@ -264,6 +272,21 @@ · 193 unmodified lines
264272 clocks = <&input_clk>;
265273 cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
266274 <&creg_gpio 1 GPIO_ACTIVE_LOW>;
275+
276+ spi-flash@0 {
277+ compatible = "sst26wf016b", "jedec,spi-nor";
278+ reg = <0>;
279+ #address-cells = <1>;
280+ #size-cells = <1>;
281+ spi-max-frequency = <4000000>;
282+ };
283+
284+ adc@1 {
285+ compatible = "ti,adc108s102";
286+ reg = <1>;
287+ vref-supply = <&reg_5v0>;
288+ spi-max-frequency = <1000000>;
289+ };
267290 };
268291
269292 creg_gpio: gpio@14b0 {
arch/arc/configs/hsdk_defconfig+6−0
@@ -32,6 +32,8 @@ CONFIG_INET=y · 31 unmodified lines
3232 CONFIG_DEVTMPFS=y
3333 # CONFIG_STANDALONE is not set
3434 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
35+CONFIG_MTD=y
36+CONFIG_MTD_SPI_NOR=y
3537 CONFIG_SCSI=y
3638 CONFIG_BLK_DEV_SD=y
3739 CONFIG_NETDEVICES=y
@@ -55,6 +57,8 @@ CONFIG_GPIO_SYSFS=y · 17 unmodified lines
5557 CONFIG_GPIO_DWAPB=y
5658 CONFIG_GPIO_SNPS_CREG=y
5759 # CONFIG_HWMON is not set
60+CONFIG_REGULATOR=y
61+CONFIG_REGULATOR_FIXED_VOLTAGE=y
5862 CONFIG_DRM=y
5963 # CONFIG_DRM_FBDEV_EMULATION is not set
6064 CONFIG_DRM_UDL=y
@@ -72,6 +76,8 @@ CONFIG_MMC_SDHCI_PLTFM=y · 11 unmodified lines
7276 CONFIG_MMC_DW=y
7377 CONFIG_DMADEVICES=y
7478 CONFIG_DW_AXI_DMAC=y
79+CONFIG_IIO=y
80+CONFIG_TI_ADC108S102=y
7581 CONFIG_EXT3_FS=y
7682 CONFIG_VFAT_FS=y
7783 CONFIG_TMPFS=y
arch/arc/kernel/perf_event.c+2−2
@@ -614,8 +614,8 @@ static int arc_pmu_device_probe(struct platform_device *pdev) · 613 unmodified lines
614614 /* loop thru all available h/w condition indexes */
615615 for (i = 0; i < cc_bcr.c; i++) {
616616 write_aux_reg(ARC_REG_CC_INDEX, i);
617− cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0);
618− cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1);
617+ cc_name.indiv.word0 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME0));
618+ cc_name.indiv.word1 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME1));
619619
620620 arc_pmu_map_hw_event(i, cc_name.str);
621621 arc_pmu_add_raw_event_attr(i, cc_name.str);
arch/arm/boot/dts/am3874-iceboard.dts+1−8
@@ -111,13 +111,13 @@ · 110 unmodified lines
111111 reg = <0x70>;
112112 #address-cells = <1>;
113113 #size-cells = <0>;
114+ i2c-mux-idle-disconnect;
114115
115116 i2c@0 {
116117 /* FMC A */
117118 #address-cells = <1>;
118119 #size-cells = <0>;
119120 reg = <0>;
120− i2c-mux-idle-disconnect;
121121 };
122122
123123 i2c@1 {
@@ -125,7 +125,6 @@ · 1 unmodified line
125125 #address-cells = <1>;
126126 #size-cells = <0>;
127127 reg = <1>;
128− i2c-mux-idle-disconnect;
129128 };
130129
131130 i2c@2 {
@@ -133,7 +132,6 @@ · 1 unmodified line
133132 #address-cells = <1>;
134133 #size-cells = <0>;
135134 reg = <2>;
136− i2c-mux-idle-disconnect;
137135 };
138136
139137 i2c@3 {
@@ -141,7 +139,6 @@ · 1 unmodified line
141139 #address-cells = <1>;
142140 #size-cells = <0>;
143141 reg = <3>;
144− i2c-mux-idle-disconnect;
145142 };
146143
147144 i2c@4 {
@@ -149,14 +146,12 @@ · 1 unmodified line
149146 #address-cells = <1>;
150147 #size-cells = <0>;
151148 reg = <4>;
152− i2c-mux-idle-disconnect;
153149 };
154150
155151 i2c@5 {
156152 #address-cells = <1>;
157153 #size-cells = <0>;
158154 reg = <5>;
159− i2c-mux-idle-disconnect;
160155
161156 ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; };
162157 ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; };
@@ -182,14 +177,12 @@ · 19 unmodified lines
182177 #address-cells = <1>;
183178 #size-cells = <0>;
184179 reg = <6>;
185− i2c-mux-idle-disconnect;
186180 };
187181
188182 i2c@7 {
189183 #address-cells = <1>;
190184 #size-cells = <0>;
191185 reg = <7>;
192− i2c-mux-idle-disconnect;
193186
194187 u41: pca9575@20 {
195188 compatible = "nxp,pca9575";
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts+1−0
@@ -113,6 +113,7 @@ · 112 unmodified lines
113113 #address-cells = <1>;
114114 #size-cells = <0>;
115115 pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
116+ bus-width = <4>;
116117 mmc-pwrseq = <&wifi_pwrseq>;
117118 non-removable;
118119 status = "okay";
arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi+8−0
@@ -9,6 +9,14 @@ · 8 unmodified lines
99 reg = <0 0x40000000>;
1010 };
1111
12+ leds {
13+ /*
14+ * Since there is no upstream GPIO driver yet,
15+ * remove the incomplete node.
16+ */
17+ /delete-node/ act;
18+ };
19+
1220 reg_3v3: fixed-regulator {
1321 compatible = "regulator-fixed";
1422 regulator-name = "3V3";
arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi+4−0
@@ -328,6 +328,10 @@ · 327 unmodified lines
328328 pinctrl-0 = <&pinctrl_pwm3>;
329329 };
330330
331+&snvs_pwrkey {
332+ status = "okay";
333+};
334+
331335 &ssi2 {
332336 status = "okay";
333337 };
arch/arm/boot/dts/imx6-logicpd-som.dtsi+4−0
@@ -207,6 +207,10 @@ · 206 unmodified lines
207207 vin-supply = <&sw1c_reg>;
208208 };
209209
210+&snvs_poweroff {
211+ status = "okay";
212+};
213+
210214 &iomuxc {
211215 pinctrl-names = "default";
212216 pinctrl-0 = <&pinctrl_hog>;
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi+8−0
@@ -230,6 +230,8 @@ · 229 unmodified lines
230230 accelerometer@1c {
231231 compatible = "fsl,mma8451";
232232 reg = <0x1c>;
233+ pinctrl-names = "default";
234+ pinctrl-0 = <&pinctrl_mma8451_int>;
233235 interrupt-parent = <&gpio6>;
234236 interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
235237 };
@@ -628,6 +630,12 @@ · 392 unmodified lines
628630 >;
629631 };
630632
633+ pinctrl_mma8451_int: mma8451intgrp {
634+ fsl,pins = <
635+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1
636+ >;
637+ };
638+
631639 pinctrl_pwm3: pwm1grp {
632640 fsl,pins = <
633641 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
arch/arm/boot/dts/imx7s.dtsi+4−4
@@ -448,7 +448,7 @@ · 447 unmodified lines
448448 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
449449 reg = <0x302d0000 0x10000>;
450450 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
451− clocks = <&clks IMX7D_CLK_DUMMY>,
451+ clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
452452 <&clks IMX7D_GPT1_ROOT_CLK>;
453453 clock-names = "ipg", "per";
454454 };
@@ -457,7 +457,7 @@ · 2 unmodified lines
457457 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
458458 reg = <0x302e0000 0x10000>;
459459 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
460− clocks = <&clks IMX7D_CLK_DUMMY>,
460+ clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
461461 <&clks IMX7D_GPT2_ROOT_CLK>;
462462 clock-names = "ipg", "per";
463463 status = "disabled";
@@ -467,7 +467,7 @@ · 3 unmodified lines
467467 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
468468 reg = <0x302f0000 0x10000>;
469469 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
470− clocks = <&clks IMX7D_CLK_DUMMY>,
470+ clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
471471 <&clks IMX7D_GPT3_ROOT_CLK>;
472472 clock-names = "ipg", "per";
473473 status = "disabled";
@@ -477,7 +477,7 @@ · 3 unmodified lines
477477 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
478478 reg = <0x30300000 0x10000>;
479479 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
480− clocks = <&clks IMX7D_CLK_DUMMY>,
480+ clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
481481 <&clks IMX7D_GPT4_ROOT_CLK>;
482482 clock-names = "ipg", "per";
483483 status = "disabled";
arch/arm/boot/dts/logicpd-torpedo-som.dtsi+4−0
@@ -192,3 +192,7 @@ · 191 unmodified lines
192192 &twl_gpio {
193193 ti,use-leds;
194194 };
195+
196+&twl_keypad {
197+ status = "disabled";
198+};
arch/arm/boot/dts/mt7629-rfb.dts+12−1
@@ -66,9 +66,21 @@ · 65 unmodified lines
6666 pinctrl-1 = <&ephy_leds_pins>;
6767 status = "okay";
6868
69+ gmac0: mac@0 {
70+ compatible = "mediatek,eth-mac";
71+ reg = <0>;
72+ phy-mode = "2500base-x";
73+ fixed-link {
74+ speed = <2500>;
75+ full-duplex;
76+ pause;
77+ };
78+ };
79+
6980 gmac1: mac@1 {
7081 compatible = "mediatek,eth-mac";
7182 reg = <1>;
83+ phy-mode = "gmii";
7284 phy-handle = <&phy0>;
7385 };
7486
@@ -78,7 +90,6 @@ · 3 unmodified lines
7890
7991 phy0: ethernet-phy@0 {
8092 reg = <0>;
81− phy-mode = "gmii";
8293 };
8394 };
8495 };
arch/arm/boot/dts/mt7629.dtsi+0−2
@@ -468,14 +468,12 @@ · 467 unmodified lines
468468 compatible = "mediatek,mt7629-sgmiisys", "syscon";
469469 reg = <0x1b128000 0x3000>;
470470 #clock-cells = <1>;
471− mediatek,physpeed = "2500";
472471 };
473472
474473 sgmiisys1: syscon@1b130000 {
475474 compatible = "mediatek,mt7629-sgmiisys", "syscon";
476475 reg = <0x1b130000 0x3000>;
477476 #clock-cells = <1>;
478− mediatek,physpeed = "2500";
479477 };
480478 };
481479 };
arch/arm/boot/dts/omap4-droid4-xt894.dts+1−1
@@ -369,7 +369,7 @@ · 368 unmodified lines
369369 compatible = "ti,wl1285", "ti,wl1283";
370370 reg = <2>;
371371 /* gpio_100 with gpmc_wait2 pad as wakeirq */
372− interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>,
372+ interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>,
373373 <&omap4_pmx_core 0x4e>;
374374 interrupt-names = "irq", "wakeup";
375375 ref-clock-frequency = <26000000>;
arch/arm/boot/dts/omap4-panda-common.dtsi+1−1
@@ -474,7 +474,7 @@ · 473 unmodified lines
474474 compatible = "ti,wl1271";
475475 reg = <2>;
476476 /* gpio_53 with gpmc_ncs3 pad as wakeup */
477− interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_RISING>,
477+ interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>,
478478 <&omap4_pmx_core 0x3a>;
479479 interrupt-names = "irq", "wakeup";
480480 ref-clock-frequency = <38400000>;
arch/arm/boot/dts/omap4-sdp.dts+1−1
@@ -512,7 +512,7 @@ · 511 unmodified lines
512512 compatible = "ti,wl1281";
513513 reg = <2>;
514514 interrupt-parent = <&gpio1>;
515− interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */
515+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
516516 ref-clock-frequency = <26000000>;
517517 tcxo-clock-frequency = <26000000>;
518518 };
arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi+1−1
@@ -69,7 +69,7 @@ · 68 unmodified lines
6969 compatible = "ti,wl1271";
7070 reg = <2>;
7171 interrupt-parent = <&gpio2>;
72− interrupts = <9 IRQ_TYPE_EDGE_RISING>; /* gpio 41 */
72+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */
7373 ref-clock-frequency = <38400000>;
7474 };
7575 };
arch/arm/boot/dts/omap5-board-common.dtsi+1−1
@@ -362,7 +362,7 @@ · 361 unmodified lines
362362 pinctrl-names = "default";
363363 pinctrl-0 = <&wlcore_irq_pin>;
364364 interrupt-parent = <&gpio1>;
365− interrupts = <14 IRQ_TYPE_EDGE_RISING>; /* gpio 14 */
365+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
366366 ref-clock-frequency = <26000000>;
367367 };
368368 };
arch/arm/boot/dts/omap54xx-clocks.dtsi+1−1
@@ -1146,7 +1146,7 @@ · 1145 unmodified lines
11461146 };
11471147 };
11481148
1149− gpu_cm: clock-controller@1500 {
1149+ gpu_cm: gpu_cm@1500 {
11501150 compatible = "ti,omap4-cm";
11511151 reg = <0x1500 0x100>;
11521152 #address-cells = <1>;
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi+4−4
@@ -609,13 +609,13 @@ · 608 unmodified lines
609609 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
610610 bias-disable;
611611 drive-push-pull;
612− slew-rate = <3>;
612+ slew-rate = <1>;
613613 };
614614 pins2 {
615615 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
616616 bias-pull-up;
617617 drive-push-pull;
618− slew-rate = <3>;
618+ slew-rate = <1>;
619619 };
620620 };
621621
@@ -637,13 +637,13 @@ · 15 unmodified lines
637637 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
638638 bias-disable;
639639 drive-push-pull;
640− slew-rate = <3>;
640+ slew-rate = <1>;
641641 };
642642 pins2 {
643643 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
644644 bias-pull-up;
645645 drive-push-pull;
646− slew-rate = <3>;
646+ slew-rate = <1>;
647647 };
648648 };
649649
arch/arm/boot/dts/stm32mp157c-ev1.dts+2−11
@@ -183,14 +183,12 @@ · 182 unmodified lines
183183
184184 ov5640: camera@3c {
185185 compatible = "ovti,ov5640";
186− pinctrl-names = "default";
187− pinctrl-0 = <&ov5640_pins>;
188186 reg = <0x3c>;
189187 clocks = <&clk_ext_camera>;
190188 clock-names = "xclk";
191189 DOVDD-supply = <&v2v8>;
192− powerdown-gpios = <&stmfx_pinctrl 18 GPIO_ACTIVE_HIGH>;
193− reset-gpios = <&stmfx_pinctrl 19 GPIO_ACTIVE_LOW>;
190+ powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
191+ reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
194192 rotation = <180>;
195193 status = "okay";
196194
@@ -223,15 +221,8 @@ · 26 unmodified lines
223221
224222 joystick_pins: joystick {
225223 pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
226− drive-push-pull;
227224 bias-pull-down;
228225 };
229−
230− ov5640_pins: camera {
231− pins = "agpio2", "agpio3"; /* stmfx pins 18 & 19 */
232− drive-push-pull;
233− output-low;
234− };
235226 };
236227 };
237228 };
arch/arm/boot/dts/stm32mp157c.dtsi+2−2
@@ -932,7 +932,7 @@ · 931 unmodified lines
932932 interrupt-names = "int0", "int1";
933933 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
934934 clock-names = "hclk", "cclk";
935− bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
935+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
936936 status = "disabled";
937937 };
938938
@@ -945,7 +945,7 @@ · 6 unmodified lines
945945 interrupt-names = "int0", "int1";
946946 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
947947 clock-names = "hclk", "cclk";
948− bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
948+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
949949 status = "disabled";
950950 };
951951
arch/arm/boot/dts/sun4i-a10.dtsi+4−0
@@ -520,6 +520,7 @@ · 519 unmodified lines
520520 interrupts = <39>;
521521 clocks = <&ccu CLK_AHB_EHCI0>;
522522 phys = <&usbphy 1>;
523+ phy-names = "usb";
523524 status = "disabled";
524525 };
525526
@@ -529,6 +530,7 @@ · 3 unmodified lines
529530 interrupts = <64>;
530531 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
531532 phys = <&usbphy 1>;
533+ phy-names = "usb";
532534 status = "disabled";
533535 };
534536
@@ -608,6 +610,7 @@ · 73 unmodified lines
608610 interrupts = <40>;
609611 clocks = <&ccu CLK_AHB_EHCI1>;
610612 phys = <&usbphy 2>;
613+ phy-names = "usb";
611614 status = "disabled";
612615 };
613616
@@ -617,6 +620,7 @@ · 3 unmodified lines
617620 interrupts = <65>;
618621 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
619622 phys = <&usbphy 2>;
623+ phy-names = "usb";
620624 status = "disabled";
621625 };
622626
arch/arm/boot/dts/sun5i.dtsi+2−0
@@ -391,6 +391,7 @@ · 390 unmodified lines
391391 interrupts = <39>;
392392 clocks = <&ccu CLK_AHB_EHCI>;
393393 phys = <&usbphy 1>;
394+ phy-names = "usb";
394395 status = "disabled";
395396 };
396397
@@ -400,6 +401,7 @@ · 3 unmodified lines
400401 interrupts = <40>;
401402 clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
402403 phys = <&usbphy 1>;
404+ phy-names = "usb";
403405 status = "disabled";
404406 };
405407
arch/arm/boot/dts/sun6i-a31.dtsi+4−0
@@ -545,6 +545,7 @@ · 544 unmodified lines
545545 clocks = <&ccu CLK_AHB1_EHCI0>;
546546 resets = <&ccu RST_AHB1_EHCI0>;
547547 phys = <&usbphy 1>;
548+ phy-names = "usb";
548549 status = "disabled";
549550 };
550551
@@ -555,6 +556,7 @@ · 4 unmodified lines
555556 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
556557 resets = <&ccu RST_AHB1_OHCI0>;
557558 phys = <&usbphy 1>;
559+ phy-names = "usb";
558560 status = "disabled";
559561 };
560562
@@ -565,6 +567,7 @@ · 4 unmodified lines
565567 clocks = <&ccu CLK_AHB1_EHCI1>;
566568 resets = <&ccu RST_AHB1_EHCI1>;
567569 phys = <&usbphy 2>;
570+ phy-names = "usb";
568571 status = "disabled";
569572 };
570573
@@ -575,6 +578,7 @@ · 4 unmodified lines
575578 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
576579 resets = <&ccu RST_AHB1_OHCI1>;
577580 phys = <&usbphy 2>;
581+ phy-names = "usb";
578582 status = "disabled";
579583 };
580584
arch/arm/boot/dts/sun7i-a20.dtsi+6−3
@@ -380,9 +380,8 @@ · 379 unmodified lines
380380 compatible = "allwinner,sun7i-a20-csi0";
381381 reg = <0x01c09000 0x1000>;
382382 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
383− clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
384− <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
385− clock-names = "bus", "mod", "isp", "ram";
383+ clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
384+ clock-names = "bus", "isp", "ram";
386385 resets = <&ccu RST_CSI0>;
387386 status = "disabled";
388387 };
@@ -623,6 +622,7 @@ · 234 unmodified lines
623622 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
624623 clocks = <&ccu CLK_AHB_EHCI0>;
625624 phys = <&usbphy 1>;
625+ phy-names = "usb";
626626 status = "disabled";
627627 };
628628
@@ -632,6 +632,7 @@ · 3 unmodified lines
632632 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
633633 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
634634 phys = <&usbphy 1>;
635+ phy-names = "usb";
635636 status = "disabled";
636637 };
637638
@@ -714,6 +715,7 @@ · 76 unmodified lines
714715 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
715716 clocks = <&ccu CLK_AHB_EHCI1>;
716717 phys = <&usbphy 2>;
718+ phy-names = "usb";
717719 status = "disabled";
718720 };
719721
@@ -723,6 +725,7 @@ · 3 unmodified lines
723725 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
724726 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
725727 phys = <&usbphy 2>;
728+ phy-names = "usb";
726729 status = "disabled";
727730 };
728731
arch/arm/boot/dts/sun8i-a23-a33.dtsi+2−0
@@ -307,6 +307,7 @@ · 306 unmodified lines
307307 clocks = <&ccu CLK_BUS_EHCI>;
308308 resets = <&ccu RST_BUS_EHCI>;
309309 phys = <&usbphy 1>;
310+ phy-names = "usb";
310311 status = "disabled";
311312 };
312313
@@ -317,6 +318,7 @@ · 4 unmodified lines
317318 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
318319 resets = <&ccu RST_BUS_OHCI>;
319320 phys = <&usbphy 1>;
321+ phy-names = "usb";
320322 status = "disabled";
321323 };
322324
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts+1−0
@@ -192,6 +192,7 @@ · 191 unmodified lines
192192 vqmmc-supply = <&reg_dldo1>;
193193 non-removable;
194194 wakeup-source;
195+ keep-power-in-suspend;
195196 status = "okay";
196197
197198 brcmf: wifi@1 {
arch/arm/boot/dts/sun8i-a83t.dtsi+3−0
@@ -632,6 +632,7 @@ · 631 unmodified lines
632632 clocks = <&ccu CLK_BUS_EHCI0>;
633633 resets = <&ccu RST_BUS_EHCI0>;
634634 phys = <&usbphy 1>;
635+ phy-names = "usb";
635636 status = "disabled";
636637 };
637638
@@ -643,6 +644,7 @@ · 5 unmodified lines
643644 clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
644645 resets = <&ccu RST_BUS_OHCI0>;
645646 phys = <&usbphy 1>;
647+ phy-names = "usb";
646648 status = "disabled";
647649 };
648650
@@ -654,6 +656,7 @@ · 5 unmodified lines
654656 clocks = <&ccu CLK_BUS_EHCI1>;
655657 resets = <&ccu RST_BUS_EHCI1>;
656658 phys = <&usbphy 2>;
659+ phy-names = "usb";
657660 status = "disabled";
658661 };
659662
arch/arm/boot/dts/sun8i-r40.dtsi+4−0
@@ -273,6 +273,7 @@ · 272 unmodified lines
273273 clocks = <&ccu CLK_BUS_EHCI1>;
274274 resets = <&ccu RST_BUS_EHCI1>;
275275 phys = <&usbphy 1>;
276+ phy-names = "usb";
276277 status = "disabled";
277278 };
278279
@@ -284,6 +285,7 @@ · 5 unmodified lines
284285 <&ccu CLK_USB_OHCI1>;
285286 resets = <&ccu RST_BUS_OHCI1>;
286287 phys = <&usbphy 1>;
288+ phy-names = "usb";
287289 status = "disabled";
288290 };
289291
@@ -294,6 +296,7 @@ · 4 unmodified lines
294296 clocks = <&ccu CLK_BUS_EHCI2>;
295297 resets = <&ccu RST_BUS_EHCI2>;
296298 phys = <&usbphy 2>;
299+ phy-names = "usb";
297300 status = "disabled";
298301 };
299302
@@ -305,6 +308,7 @@ · 5 unmodified lines
305308 <&ccu CLK_USB_OHCI2>;
306309 resets = <&ccu RST_BUS_OHCI2>;
307310 phys = <&usbphy 2>;
311+ phy-names = "usb";
308312 status = "disabled";
309313 };
310314
arch/arm/boot/dts/sun9i-a80.dtsi+5−0
@@ -346,6 +346,7 @@ · 345 unmodified lines
346346 clocks = <&usb_clocks CLK_BUS_HCI0>;
347347 resets = <&usb_clocks RST_USB0_HCI>;
348348 phys = <&usbphy1>;
349+ phy-names = "usb";
349350 status = "disabled";
350351 };
351352
@@ -357,6 +358,7 @@ · 5 unmodified lines
357358 <&usb_clocks CLK_USB_OHCI0>;
358359 resets = <&usb_clocks RST_USB0_HCI>;
359360 phys = <&usbphy1>;
361+ phy-names = "usb";
360362 status = "disabled";
361363 };
362364
@@ -378,6 +380,7 @@ · 15 unmodified lines
378380 clocks = <&usb_clocks CLK_BUS_HCI1>;
379381 resets = <&usb_clocks RST_USB1_HCI>;
380382 phys = <&usbphy2>;
383+ phy-names = "usb";
381384 status = "disabled";
382385 };
383386
@@ -407,6 +410,7 @@ · 23 unmodified lines
407410 clocks = <&usb_clocks CLK_BUS_HCI2>;
408411 resets = <&usb_clocks RST_USB2_HCI>;
409412 phys = <&usbphy3>;
413+ phy-names = "usb";
410414 status = "disabled";
411415 };
412416
@@ -418,6 +422,7 @@ · 5 unmodified lines
418422 <&usb_clocks CLK_USB_OHCI2>;
419423 resets = <&usb_clocks RST_USB2_HCI>;
420424 phys = <&usbphy3>;
425+ phy-names = "usb";
421426 status = "disabled";
422427 };
423428
arch/arm/boot/dts/sunxi-h3-h5.dtsi+6−0
@@ -304,6 +304,7 @@ · 303 unmodified lines
304304 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
305305 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
306306 phys = <&usbphy 1>;
307+ phy-names = "usb";
307308 status = "disabled";
308309 };
309310
@@ -315,6 +316,7 @@ · 5 unmodified lines
315316 <&ccu CLK_USB_OHCI1>;
316317 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
317318 phys = <&usbphy 1>;
319+ phy-names = "usb";
318320 status = "disabled";
319321 };
320322
@@ -325,6 +327,7 @@ · 4 unmodified lines
325327 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
326328 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
327329 phys = <&usbphy 2>;
330+ phy-names = "usb";
328331 status = "disabled";
329332 };
330333
@@ -336,6 +339,7 @@ · 5 unmodified lines
336339 <&ccu CLK_USB_OHCI2>;
337340 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
338341 phys = <&usbphy 2>;
342+ phy-names = "usb";
339343 status = "disabled";
340344 };
341345
@@ -346,6 +350,7 @@ · 4 unmodified lines
346350 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
347351 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
348352 phys = <&usbphy 3>;
353+ phy-names = "usb";
349354 status = "disabled";
350355 };
351356
@@ -357,6 +362,7 @@ · 5 unmodified lines
357362 <&ccu CLK_USB_OHCI3>;
358363 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
359364 phys = <&usbphy 3>;
365+ phy-names = "usb";
360366 status = "disabled";
361367 };
362368
arch/arm/boot/dts/vf610-zii-scu4-aib.dts+2−0
@@ -602,6 +602,7 @@ · 601 unmodified lines
602602 #address-cells = <1>;
603603 #size-cells = <0>;
604604 reg = <0x70>;
605+ i2c-mux-idle-disconnect;
605606
606607 sff0_i2c: i2c@1 {
607608 #address-cells = <1>;
@@ -640,6 +641,7 @@ · 32 unmodified lines
640641 reg = <0x71>;
641642 #address-cells = <1>;
642643 #size-cells = <0>;
644+ i2c-mux-idle-disconnect;
643645
644646 sff5_i2c: i2c@1 {
645647 #address-cells = <1>;
arch/arm/configs/badge4_defconfig+0−1
@@ -91,7 +91,6 @@ CONFIG_USB_SERIAL_PL2303=m · 90 unmodified lines
9191 CONFIG_USB_SERIAL_CYBERJACK=m
9292 CONFIG_USB_SERIAL_XIRCOM=m
9393 CONFIG_USB_SERIAL_OMNINET=m
94−CONFIG_USB_RIO500=m
9594 CONFIG_EXT2_FS=m
9695 CONFIG_EXT3_FS=m
9796 CONFIG_MSDOS_FS=y
arch/arm/configs/corgi_defconfig+0−1
@@ -195,7 +195,6 @@ CONFIG_USB_SERIAL_XIRCOM=m · 194 unmodified lines
195195 CONFIG_USB_SERIAL_OMNINET=m
196196 CONFIG_USB_EMI62=m
197197 CONFIG_USB_EMI26=m
198−CONFIG_USB_RIO500=m
199198 CONFIG_USB_LEGOTOWER=m
200199 CONFIG_USB_LCD=m
201200 CONFIG_USB_CYTHERM=m
arch/arm/configs/davinci_all_defconfig+1−0
@@ -167,6 +167,7 @@ CONFIG_FB=y · 166 unmodified lines
167167 CONFIG_FIRMWARE_EDID=y
168168 CONFIG_FB_DA8XX=y
169169 CONFIG_BACKLIGHT_PWM=m
170+CONFIG_BACKLIGHT_GPIO=m
170171 CONFIG_FRAMEBUFFER_CONSOLE=y
171172 CONFIG_LOGO=y
172173 CONFIG_SOUND=m
arch/arm/configs/imx_v6_v7_defconfig+1−0
@@ -276,6 +276,7 @@ CONFIG_VIDEO_OV5640=m · 275 unmodified lines
276276 CONFIG_VIDEO_OV5645=m
277277 CONFIG_IMX_IPUV3_CORE=y
278278 CONFIG_DRM=y
279+CONFIG_DRM_MSM=y
279280 CONFIG_DRM_PANEL_LVDS=y
280281 CONFIG_DRM_PANEL_SIMPLE=y
281282 CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
arch/arm/configs/omap2plus_defconfig+6−6
@@ -356,15 +356,15 @@ CONFIG_DRM_OMAP_CONNECTOR_HDMI=m · 355 unmodified lines
356356 CONFIG_DRM_OMAP_CONNECTOR_ANALOG_TV=m
357357 CONFIG_DRM_OMAP_PANEL_DPI=m
358358 CONFIG_DRM_OMAP_PANEL_DSI_CM=m
359−CONFIG_DRM_OMAP_PANEL_SONY_ACX565AKM=m
360−CONFIG_DRM_OMAP_PANEL_LGPHILIPS_LB035Q02=m
361−CONFIG_DRM_OMAP_PANEL_SHARP_LS037V7DW01=m
362−CONFIG_DRM_OMAP_PANEL_TPO_TD028TTEC1=m
363−CONFIG_DRM_OMAP_PANEL_TPO_TD043MTEA1=m
364−CONFIG_DRM_OMAP_PANEL_NEC_NL8048HL11=m
365359 CONFIG_DRM_TILCDC=m
366360 CONFIG_DRM_PANEL_SIMPLE=m
367361 CONFIG_DRM_TI_TFP410=m
362+CONFIG_DRM_PANEL_LG_LB035Q02=m
363+CONFIG_DRM_PANEL_NEC_NL8048HL11=m
364+CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
365+CONFIG_DRM_PANEL_SONY_ACX565AKM=m
366+CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
367+CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
368368 CONFIG_FB=y
369369 CONFIG_FIRMWARE_EDID=y
370370 CONFIG_FB_MODE_HELPERS=y
arch/arm/configs/pxa_defconfig+0−1
@@ -581,7 +581,6 @@ CONFIG_USB_SERIAL_XIRCOM=m · 580 unmodified lines
581581 CONFIG_USB_SERIAL_OMNINET=m
582582 CONFIG_USB_EMI62=m
583583 CONFIG_USB_EMI26=m
584−CONFIG_USB_RIO500=m
585584 CONFIG_USB_LEGOTOWER=m
586585 CONFIG_USB_LCD=m
587586 CONFIG_USB_CYTHERM=m
arch/arm/configs/s3c2410_defconfig+0−1
@@ -327,7 +327,6 @@ CONFIG_USB_EMI62=m · 326 unmodified lines
327327 CONFIG_USB_EMI26=m
328328 CONFIG_USB_ADUTUX=m
329329 CONFIG_USB_SEVSEG=m
330−CONFIG_USB_RIO500=m
331330 CONFIG_USB_LEGOTOWER=m
332331 CONFIG_USB_LCD=m
333332 CONFIG_USB_CYPRESS_CY7C63=m
arch/arm/configs/spitz_defconfig+0−1
@@ -189,7 +189,6 @@ CONFIG_USB_SERIAL_XIRCOM=m · 188 unmodified lines
189189 CONFIG_USB_SERIAL_OMNINET=m
190190 CONFIG_USB_EMI62=m
191191 CONFIG_USB_EMI26=m
192−CONFIG_USB_RIO500=m
193192 CONFIG_USB_LEGOTOWER=m
194193 CONFIG_USB_LCD=m
195194 CONFIG_USB_CYTHERM=m
arch/arm/crypto/Kconfig+1−0
@@ -98,6 +98,7 @@ config CRYPTO_AES_ARM_CE · 97 unmodified lines
9898 tristate "Accelerated AES using ARMv8 Crypto Extensions"
9999 depends on KERNEL_MODE_NEON
100100 select CRYPTO_BLKCIPHER
101+ select CRYPTO_LIB_AES
101102 select CRYPTO_SIMD
102103 help
103104 Use an implementation of AES in CBC, CTR and XTS modes that uses
arch/arm/crypto/aes-ce-core.S+1−0
@@ -9,6 +9,7 @@ · 8 unmodified lines
99 #include <asm/assembler.h>
1010
1111 .text
12+ .arch armv8-a
1213 .fpu crypto-neon-fp-armv8
1314 .align 3
1415
arch/arm/include/asm/domain.h+4−4
@@ -82,7 +82,7 @@ · 81 unmodified lines
8282 #ifndef __ASSEMBLY__
8383
8484 #ifdef CONFIG_CPU_CP15_MMU
85−static inline unsigned int get_domain(void)
85+static __always_inline unsigned int get_domain(void)
8686 {
8787 unsigned int domain;
8888
@@ -94,7 +94,7 @@ static inline unsigned int get_domain(void) · 5 unmodified lines
9494 return domain;
9595 }
9696
97−static inline void set_domain(unsigned val)
97+static __always_inline void set_domain(unsigned int val)
9898 {
9999 asm volatile(
100100 "mcr p15, 0, %0, c3, c0 @ set domain"
@@ -102,12 +102,12 @@ static inline void set_domain(unsigned val) · 1 unmodified line
102102 isb();
103103 }
104104 #else
105−static inline unsigned int get_domain(void)
105+static __always_inline unsigned int get_domain(void)
106106 {
107107 return 0;
108108 }
109109
110−static inline void set_domain(unsigned val)
110+static __always_inline void set_domain(unsigned int val)
111111 {
112112 }
113113 #endif
arch/arm/include/asm/uaccess.h+2−2
@@ -22,7 +22,7 @@ · 21 unmodified lines
2222 * perform such accesses (eg, via list poison values) which could then
2323 * be exploited for priviledge escalation.
2424 */
25−static inline unsigned int uaccess_save_and_enable(void)
25+static __always_inline unsigned int uaccess_save_and_enable(void)
2626 {
2727 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
2828 unsigned int old_domain = get_domain();
@@ -37,7 +37,7 @@ static inline unsigned int uaccess_save_and_enable(void) · 8 unmodified lines
3737 #endif
3838 }
3939
40−static inline void uaccess_restore(unsigned int flags)
40+static __always_inline void uaccess_restore(unsigned int flags)
4141 {
4242 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
4343 /* Restore the user access mask */
arch/arm/kernel/head-common.S+3−2
@@ -68,7 +68,7 @@ ENDPROC(__vet_atags) · 67 unmodified lines
6868 * The following fragment of code is executed with the MMU on in MMU mode,
6969 * and uses absolute addresses; this is not position independent.
7070 *
71− * r0 = cp#15 control register
71+ * r0 = cp#15 control register (exc_ret for M-class)
7272 * r1 = machine ID
7373 * r2 = atags/dtb pointer
7474 * r9 = processor ID
@@ -137,7 +137,8 @@ __mmap_switched_data: · 62 unmodified lines
137137 #ifdef CONFIG_CPU_CP15
138138 .long cr_alignment @ r3
139139 #else
140− .long 0 @ r3
140+M_CLASS(.long exc_ret) @ r3
141+AR_CLASS(.long 0) @ r3
141142 #endif
142143 .size __mmap_switched_data, . - __mmap_switched_data
143144
arch/arm/kernel/head-nommu.S+2−0
@@ -201,6 +201,8 @@ M_CLASS(streq r3, [r12, #PMSAv8_MAIR1]) · 200 unmodified lines
201201 bic r0, r0, #V7M_SCB_CCR_IC
202202 #endif
203203 str r0, [r12, V7M_SCB_CCR]
204+ /* Pass exc_ret to __mmap_switched */
205+ mov r0, r10
204206 #endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */
205207 ret lr
206208 ENDPROC(__after_proc_init)
arch/arm/mach-davinci/dm365.c+2−2
@@ -462,8 +462,8 @@ static s8 dm365_queue_priority_mapping[][2] = { · 461 unmodified lines
462462 };
463463
464464 static const struct dma_slave_map dm365_edma_map[] = {
465− { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
466− { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
465+ { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
466+ { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
467467 { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
468468 { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
469469 { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
arch/arm/mach-omap2/pdata-quirks.c+11−0
@@ -89,6 +89,13 @@ static struct iommu_platform_data omap3_iommu_pdata = { · 88 unmodified lines
8989 .reset_name = "mmu",
9090 .assert_reset = omap_device_assert_hardreset,
9191 .deassert_reset = omap_device_deassert_hardreset,
92+ .device_enable = omap_device_enable,
93+ .device_idle = omap_device_idle,
94+};
95+
96+static struct iommu_platform_data omap3_iommu_isp_pdata = {
97+ .device_enable = omap_device_enable,
98+ .device_idle = omap_device_idle,
9299 };
93100
94101 static int omap3_sbc_t3730_twl_callback(struct device *dev,
@@ -424,6 +431,8 @@ static struct iommu_platform_data omap4_iommu_pdata = { · 329 unmodified lines
424431 .reset_name = "mmu_cache",
425432 .assert_reset = omap_device_assert_hardreset,
426433 .deassert_reset = omap_device_deassert_hardreset,
434+ .device_enable = omap_device_enable,
435+ .device_idle = omap_device_idle,
427436 };
428437 #endif
429438
@@ -617,6 +626,8 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = { · 187 unmodified lines
617626 #ifdef CONFIG_ARCH_OMAP3
618627 OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu",
619628 &omap3_iommu_pdata),
629+ OF_DEV_AUXDATA("ti,omap2-iommu", 0x480bd400, "480bd400.mmu",
630+ &omap3_iommu_isp_pdata),
620631 OF_DEV_AUXDATA("ti,omap3-smartreflex-core", 0x480cb000,
621632 "480cb000.smartreflex", &omap_sr_pdata[OMAP_SR_CORE]),
622633 OF_DEV_AUXDATA("ti,omap3-smartreflex-mpu-iva", 0x480c9000,
arch/arm/mach-sunxi/mc_smp.c+5−1
@@ -481,14 +481,18 @@ static void sunxi_mc_smp_cpu_die(unsigned int l_cpu) · 480 unmodified lines
481481 static int sunxi_cpu_powerdown(unsigned int cpu, unsigned int cluster)
482482 {
483483 u32 reg;
484+ int gating_bit = cpu;
484485
485486 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
486487 if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
487488 return -EINVAL;
488489
490+ if (is_a83t && cpu == 0)
491+ gating_bit = 4;
492+
489493 /* gate processor power */
490494 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
491− reg |= PRCM_PWROFF_GATING_REG_CORE(cpu);
495+ reg |= PRCM_PWROFF_GATING_REG_CORE(gating_bit);
492496 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
493497 udelay(20);
494498
arch/arm/mm/alignment.c+49−21
@@ -324,7 +324,7 @@ union offset_union { · 323 unmodified lines
324324 __put32_unaligned_check("strbt", val, addr)
325325
326326 static void
327−do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
327+do_alignment_finish_ldst(unsigned long addr, u32 instr, struct pt_regs *regs, union offset_union offset)
328328 {
329329 if (!LDST_U_BIT(instr))
330330 offset.un = -offset.un;
@@ -337,7 +337,7 @@ do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs · 6 unmodified lines
337337 }
338338
339339 static int
340−do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
340+do_alignment_ldrhstrh(unsigned long addr, u32 instr, struct pt_regs *regs)
341341 {
342342 unsigned int rd = RD_BITS(instr);
343343
@@ -386,8 +386,7 @@ do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *r · 42 unmodified lines
386386 }
387387
388388 static int
389−do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
390− struct pt_regs *regs)
389+do_alignment_ldrdstrd(unsigned long addr, u32 instr, struct pt_regs *regs)
391390 {
392391 unsigned int rd = RD_BITS(instr);
393392 unsigned int rd2;
@@ -449,7 +448,7 @@ do_alignment_ldrdstrd(unsigned long addr, unsigned long instr, · 55 unmodified lines
449448 }
450449
451450 static int
452−do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
451+do_alignment_ldrstr(unsigned long addr, u32 instr, struct pt_regs *regs)
453452 {
454453 unsigned int rd = RD_BITS(instr);
455454
@@ -498,7 +497,7 @@ do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *reg · 42 unmodified lines
498497 * PU = 10 A B
499498 */
500499 static int
501−do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
500+do_alignment_ldmstm(unsigned long addr, u32 instr, struct pt_regs *regs)
502501 {
503502 unsigned int rd, rn, correction, nr_regs, regbits;
504503 unsigned long eaddr, newaddr;
@@ -539,7 +538,7 @@ do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *reg · 34 unmodified lines
539538 * processor for us.
540539 */
541540 if (addr != eaddr) {
542− pr_err("LDMSTM: PC = %08lx, instr = %08lx, "
541+ pr_err("LDMSTM: PC = %08lx, instr = %08x, "
543542 "addr = %08lx, eaddr = %08lx\n",
544543 instruction_pointer(regs), instr, addr, eaddr);
545544 show_regs(regs);
@@ -716,10 +715,10 @@ thumb2arm(u16 tinstr) · 170 unmodified lines
716715 * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
717716 */
718717 static void *
719−do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
718+do_alignment_t32_to_handler(u32 *pinstr, struct pt_regs *regs,
720719 union offset_union *poffset)
721720 {
722− unsigned long instr = *pinstr;
721+ u32 instr = *pinstr;
723722 u16 tinst1 = (instr >> 16) & 0xffff;
724723 u16 tinst2 = instr & 0xffff;
725724
@@ -767,17 +766,48 @@ do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs, · 41 unmodified lines
767766 return NULL;
768767 }
769768
769+static int alignment_get_arm(struct pt_regs *regs, u32 *ip, u32 *inst)
770+{
771+ u32 instr = 0;
772+ int fault;
773+
774+ if (user_mode(regs))
775+ fault = get_user(instr, ip);
776+ else
777+ fault = probe_kernel_address(ip, instr);
778+
779+ *inst = __mem_to_opcode_arm(instr);
780+
781+ return fault;
782+}
783+
784+static int alignment_get_thumb(struct pt_regs *regs, u16 *ip, u16 *inst)
785+{
786+ u16 instr = 0;
787+ int fault;
788+
789+ if (user_mode(regs))
790+ fault = get_user(instr, ip);
791+ else
792+ fault = probe_kernel_address(ip, instr);
793+
794+ *inst = __mem_to_opcode_thumb16(instr);
795+
796+ return fault;
797+}
798+
770799 static int
771800 do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
772801 {
773802 union offset_union uninitialized_var(offset);
774− unsigned long instr = 0, instrptr;
775− int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
803+ unsigned long instrptr;
804+ int (*handler)(unsigned long addr, u32 instr, struct pt_regs *regs);
776805 unsigned int type;
777− unsigned int fault;
806+ u32 instr = 0;
778807 u16 tinstr = 0;
779808 int isize = 4;
780809 int thumb2_32b = 0;
810+ int fault;
781811
782812 if (interrupts_enabled(regs))
783813 local_irq_enable();
@@ -786,15 +816,14 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) · 2 unmodified lines
786816
787817 if (thumb_mode(regs)) {
788818 u16 *ptr = (u16 *)(instrptr & ~1);
789− fault = probe_kernel_address(ptr, tinstr);
790− tinstr = __mem_to_opcode_thumb16(tinstr);
819+
820+ fault = alignment_get_thumb(regs, ptr, &tinstr);
791821 if (!fault) {
792822 if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
793823 IS_T32(tinstr)) {
794824 /* Thumb-2 32-bit */
795− u16 tinst2 = 0;
796− fault = probe_kernel_address(ptr + 1, tinst2);
797− tinst2 = __mem_to_opcode_thumb16(tinst2);
825+ u16 tinst2;
826+ fault = alignment_get_thumb(regs, ptr + 1, &tinst2);
798827 instr = __opcode_thumb32_compose(tinstr, tinst2);
799828 thumb2_32b = 1;
800829 } else {
@@ -803,8 +832,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) · 2 unmodified lines
803832 }
804833 }
805834 } else {
806− fault = probe_kernel_address((void *)instrptr, instr);
807− instr = __mem_to_opcode_arm(instr);
835+ fault = alignment_get_arm(regs, (void *)instrptr, &instr);
808836 }
809837
810838 if (fault) {
@@ -926,7 +954,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) · 115 unmodified lines
926954 * Oops, we didn't handle the instruction.
927955 */
928956 pr_err("Alignment trap: not handling instruction "
929− "%0*lx at [<%08lx>]\n",
957+ "%0*x at [<%08lx>]\n",
930958 isize << 1,
931959 isize == 2 ? tinstr : instr, instrptr);
932960 ai_skipped += 1;
@@ -936,7 +964,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) · 3 unmodified lines
936964 ai_user += 1;
937965
938966 if (ai_usermode & UM_WARN)
939− printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
967+ printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*x "
940968 "Address=0x%08lx FSR 0x%03x\n", current->comm,
941969 task_pid_nr(current), instrptr,
942970 isize << 1,
arch/arm/mm/proc-v7m.S+2−4
@@ -132,13 +132,11 @@ __v7m_setup_cont: · 131 unmodified lines
132132 dsb
133133 mov r6, lr @ save LR
134134 ldr sp, =init_thread_union + THREAD_START_SP
135− stmia sp, {r0-r3, r12}
136135 cpsie i
137136 svc #0
138137 1: cpsid i
139− ldr r0, =exc_ret
140− orr lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK
141− str lr, [r0]
138+ /* Calculate exc_ret */
139+ orr r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
142140 ldmia sp, {r0-r3, r12}
143141 str r5, [r12, #11 * 4] @ restore the original SVC vector entry
144142 mov lr, r6 @ restore LR
arch/arm64/Kconfig+30−2
@@ -110,7 +110,6 @@ config ARM64 · 109 unmodified lines
110110 select GENERIC_STRNLEN_USER
111111 select GENERIC_TIME_VSYSCALL
112112 select GENERIC_GETTIMEOFDAY
113− select GENERIC_COMPAT_VDSO if (!CPU_BIG_ENDIAN && COMPAT)
114113 select HANDLE_DOMAIN_IRQ
115114 select HARDIRQS_SW_RESEND
116115 select HAVE_PCI
@@ -617,6 +616,23 @@ config CAVIUM_ERRATUM_30115 · 500 unmodified lines
617616
618617 If unsure, say Y.
619618
619+config CAVIUM_TX2_ERRATUM_219
620+ bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
621+ default y
622+ help
623+ On Cavium ThunderX2, a load, store or prefetch instruction between a
624+ TTBR update and the corresponding context synchronizing operation can
625+ cause a spurious Data Abort to be delivered to any hardware thread in
626+ the CPU core.
627+
628+ Work around the issue by avoiding the problematic code sequence and
629+ trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
630+ trap handler performs the corresponding register access, skips the
631+ instruction and ensures context synchronization by virtue of the
632+ exception return.
633+
634+ If unsure, say Y.
635+
620636 config QCOM_FALKOR_ERRATUM_1003
621637 bool "Falkor E1003: Incorrect translation due to ASID change"
622638 default y
@@ -1159,7 +1175,7 @@ menuconfig COMPAT · 536 unmodified lines
11591175 if COMPAT
11601176
11611177 config KUSER_HELPERS
1162− bool "Enable kuser helpers page for 32 bit applications"
1178+ bool "Enable kuser helpers page for 32-bit applications"
11631179 default y
11641180 help
11651181 Warning: disabling this option may break 32-bit user programs.
@@ -1185,6 +1201,18 @@ config KUSER_HELPERS · 19 unmodified lines
11851201 Say N here only if you are absolutely certain that you do not
11861202 need these helpers; otherwise, the safe option is to say Y.
11871203
1204+config COMPAT_VDSO
1205+ bool "Enable vDSO for 32-bit applications"
1206+ depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1207+ select GENERIC_COMPAT_VDSO
1208+ default y
1209+ help
1210+ Place in the process address space of 32-bit applications an
1211+ ELF shared object providing fast implementations of gettimeofday
1212+ and clock_gettime.
1213+
1214+ You must have a 32-bit build of glibc 2.22 or later for programs
1215+ to seamlessly take advantage of this.
11881216
11891217 menuconfig ARMV8_DEPRECATED
11901218 bool "Emulate deprecated/obsolete ARMv8 instructions"
arch/arm64/Makefile+0−16
@@ -53,22 +53,6 @@ $(warning Detected assembler with broken .inst; disassembly will be unreliable) · 52 unmodified lines
5353 endif
5454 endif
5555
56−ifeq ($(CONFIG_GENERIC_COMPAT_VDSO), y)
57− CROSS_COMPILE_COMPAT ?= $(CONFIG_CROSS_COMPILE_COMPAT_VDSO:"%"=%)
58−
59− ifeq ($(CONFIG_CC_IS_CLANG), y)
60− $(warning CROSS_COMPILE_COMPAT is clang, the compat vDSO will not be built)
61− else ifeq ($(strip $(CROSS_COMPILE_COMPAT)),)
62− $(warning CROSS_COMPILE_COMPAT not defined or empty, the compat vDSO will not be built)
63− else ifeq ($(shell which $(CROSS_COMPILE_COMPAT)gcc 2> /dev/null),)
64− $(error $(CROSS_COMPILE_COMPAT)gcc not found, check CROSS_COMPILE_COMPAT)
65− else
66− export CROSS_COMPILE_COMPAT
67− export CONFIG_COMPAT_VDSO := y
68− compat_vdso := -DCONFIG_COMPAT_VDSO=1
69− endif
70−endif
71−
7256 KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) $(brokengasinst) \
7357 $(compat_vdso) $(cc_has_k_constraint)
7458 KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts+9−0
@@ -63,3 +63,12 @@ · 62 unmodified lines
6363 reg = <1>;
6464 };
6565 };
66+
67+&reg_dc1sw {
68+ /*
69+ * Ethernet PHY needs 30ms to properly power up and some more
70+ * to initialize. 100ms should be plenty of time to finish
71+ * whole process.
72+ */
73+ regulator-enable-ramp-delay = <100000>;
74+};
arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts+2−0
@@ -104,6 +104,7 @@ · 103 unmodified lines
104104
105105 &ehci0 {
106106 phys = <&usbphy 0>;
107+ phy-names = "usb";
107108 status = "okay";
108109 };
109110
@@ -150,6 +151,7 @@ · 40 unmodified lines
150151
151152 &ohci0 {
152153 phys = <&usbphy 0>;
154+ phy-names = "usb";
153155 status = "okay";
154156 };
155157
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts+6−0
@@ -159,6 +159,12 @@ · 158 unmodified lines
159159 };
160160
161161 &reg_dc1sw {
162+ /*
163+ * Ethernet PHY needs 30ms to properly power up and some more
164+ * to initialize. 100ms should be plenty of time to finish
165+ * whole process.
166+ */
167+ regulator-enable-ramp-delay = <100000>;
162168 regulator-name = "vcc-phy";
163169 };
164170
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi+2−9
@@ -142,15 +142,6 @@ · 141 unmodified lines
142142 clock-output-names = "ext-osc32k";
143143 };
144144
145− pmu {
146− compatible = "arm,cortex-a53-pmu";
147− interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
148− <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
149− <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
150− <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
151− interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
152− };
153−
154145 psci {
155146 compatible = "arm,psci-0.2";
156147 method = "smc";
@@ -553,6 +544,7 @@ · 396 unmodified lines
553544 resets = <&ccu RST_BUS_OHCI1>,
554545 <&ccu RST_BUS_EHCI1>;
555546 phys = <&usbphy 1>;
547+ phy-names = "usb";
556548 status = "disabled";
557549 };
558550
@@ -564,6 +556,7 @@ · 5 unmodified lines
564556 <&ccu CLK_USB_OHCI1>;
565557 resets = <&ccu RST_BUS_OHCI1>;
566558 phys = <&usbphy 1>;
559+ phy-names = "usb";
567560 status = "disabled";
568561 };
569562
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi+2−0
@@ -547,6 +547,7 @@ · 546 unmodified lines
547547 resets = <&ccu RST_BUS_OHCI3>,
548548 <&ccu RST_BUS_EHCI3>;
549549 phys = <&usb2phy 3>;
550+ phy-names = "usb";
550551 status = "disabled";
551552 };
552553
@@ -558,6 +559,7 @@ · 5 unmodified lines
558559 <&ccu CLK_USB_OHCI3>;
559560 resets = <&ccu RST_BUS_OHCI3>;
560561 phys = <&usb2phy 3>;
562+ phy-names = "usb";
561563 status = "disabled";
562564 };
563565
arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi+3−2
@@ -42,13 +42,14 @@ · 41 unmodified lines
4242
4343 pinmux: pinmux@14029c {
4444 compatible = "pinctrl-single";
45− reg = <0x0014029c 0x250>;
45+ reg = <0x0014029c 0x26c>;
4646 #address-cells = <1>;
4747 #size-cells = <1>;
4848 pinctrl-single,register-width = <32>;
4949 pinctrl-single,function-mask = <0xf>;
5050 pinctrl-single,gpio-range = <
51− &range 0 154 MODE_GPIO
51+ &range 0 91 MODE_GPIO
52+ &range 95 60 MODE_GPIO
5253 >;
5354 range: gpio-range {
5455 #pinctrl-single,gpio-range-cells = <3>;
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi+1−2
@@ -464,8 +464,7 @@ · 463 unmodified lines
464464 <&pinmux 108 16 27>,
465465 <&pinmux 135 77 6>,
466466 <&pinmux 141 67 4>,
467− <&pinmux 145 149 6>,
468− <&pinmux 151 91 4>;
467+ <&pinmux 145 149 6>;
469468 };
470469
471470 i2c1: i2c@e0000 {
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts+1−1
@@ -127,7 +127,7 @@ · 126 unmodified lines
127127 status = "okay";
128128
129129 i2c-mux@77 {
130− compatible = "nxp,pca9847";
130+ compatible = "nxp,pca9547";
131131 reg = <0x77>;
132132 #address-cells = <1>;
133133 #size-cells = <0>;
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi+18−18
@@ -33,7 +33,7 @@ · 32 unmodified lines
3333 i-cache-line-size = <64>;
3434 i-cache-sets = <192>;
3535 next-level-cache = <&cluster0_l2>;
36− cpu-idle-states = <&cpu_pw20>;
36+ cpu-idle-states = <&cpu_pw15>;
3737 };
3838
3939 cpu@1 {
@@ -49,7 +49,7 @@ · 9 unmodified lines
4949 i-cache-line-size = <64>;
5050 i-cache-sets = <192>;
5151 next-level-cache = <&cluster0_l2>;
52− cpu-idle-states = <&cpu_pw20>;
52+ cpu-idle-states = <&cpu_pw15>;
5353 };
5454
5555 cpu@100 {
@@ -65,7 +65,7 @@ · 9 unmodified lines
6565 i-cache-line-size = <64>;
6666 i-cache-sets = <192>;
6767 next-level-cache = <&cluster1_l2>;
68− cpu-idle-states = <&cpu_pw20>;
68+ cpu-idle-states = <&cpu_pw15>;
6969 };
7070
7171 cpu@101 {
@@ -81,7 +81,7 @@ · 9 unmodified lines
8181 i-cache-line-size = <64>;
8282 i-cache-sets = <192>;
8383 next-level-cache = <&cluster1_l2>;
84− cpu-idle-states = <&cpu_pw20>;
84+ cpu-idle-states = <&cpu_pw15>;
8585 };
8686
8787 cpu@200 {
@@ -97,7 +97,7 @@ · 9 unmodified lines
9797 i-cache-line-size = <64>;
9898 i-cache-sets = <192>;
9999 next-level-cache = <&cluster2_l2>;
100− cpu-idle-states = <&cpu_pw20>;
100+ cpu-idle-states = <&cpu_pw15>;
101101 };
102102
103103 cpu@201 {
@@ -113,7 +113,7 @@ · 9 unmodified lines
113113 i-cache-line-size = <64>;
114114 i-cache-sets = <192>;
115115 next-level-cache = <&cluster2_l2>;
116− cpu-idle-states = <&cpu_pw20>;
116+ cpu-idle-states = <&cpu_pw15>;
117117 };
118118
119119 cpu@300 {
@@ -129,7 +129,7 @@ · 9 unmodified lines
129129 i-cache-line-size = <64>;
130130 i-cache-sets = <192>;
131131 next-level-cache = <&cluster3_l2>;
132− cpu-idle-states = <&cpu_pw20>;
132+ cpu-idle-states = <&cpu_pw15>;
133133 };
134134
135135 cpu@301 {
@@ -145,7 +145,7 @@ · 9 unmodified lines
145145 i-cache-line-size = <64>;
146146 i-cache-sets = <192>;
147147 next-level-cache = <&cluster3_l2>;
148− cpu-idle-states = <&cpu_pw20>;
148+ cpu-idle-states = <&cpu_pw15>;
149149 };
150150
151151 cpu@400 {
@@ -161,7 +161,7 @@ · 9 unmodified lines
161161 i-cache-line-size = <64>;
162162 i-cache-sets = <192>;
163163 next-level-cache = <&cluster4_l2>;
164− cpu-idle-states = <&cpu_pw20>;
164+ cpu-idle-states = <&cpu_pw15>;
165165 };
166166
167167 cpu@401 {
@@ -177,7 +177,7 @@ · 9 unmodified lines
177177 i-cache-line-size = <64>;
178178 i-cache-sets = <192>;
179179 next-level-cache = <&cluster4_l2>;
180− cpu-idle-states = <&cpu_pw20>;
180+ cpu-idle-states = <&cpu_pw15>;
181181 };
182182
183183 cpu@500 {
@@ -193,7 +193,7 @@ · 9 unmodified lines
193193 i-cache-line-size = <64>;
194194 i-cache-sets = <192>;
195195 next-level-cache = <&cluster5_l2>;
196− cpu-idle-states = <&cpu_pw20>;
196+ cpu-idle-states = <&cpu_pw15>;
197197 };
198198
199199 cpu@501 {
@@ -209,7 +209,7 @@ · 9 unmodified lines
209209 i-cache-line-size = <64>;
210210 i-cache-sets = <192>;
211211 next-level-cache = <&cluster5_l2>;
212− cpu-idle-states = <&cpu_pw20>;
212+ cpu-idle-states = <&cpu_pw15>;
213213 };
214214
215215 cpu@600 {
@@ -225,7 +225,7 @@ · 9 unmodified lines
225225 i-cache-line-size = <64>;
226226 i-cache-sets = <192>;
227227 next-level-cache = <&cluster6_l2>;
228− cpu-idle-states = <&cpu_pw20>;
228+ cpu-idle-states = <&cpu_pw15>;
229229 };
230230
231231 cpu@601 {
@@ -241,7 +241,7 @@ · 9 unmodified lines
241241 i-cache-line-size = <64>;
242242 i-cache-sets = <192>;
243243 next-level-cache = <&cluster6_l2>;
244− cpu-idle-states = <&cpu_pw20>;
244+ cpu-idle-states = <&cpu_pw15>;
245245 };
246246
247247 cpu@700 {
@@ -257,7 +257,7 @@ · 9 unmodified lines
257257 i-cache-line-size = <64>;
258258 i-cache-sets = <192>;
259259 next-level-cache = <&cluster7_l2>;
260− cpu-idle-states = <&cpu_pw20>;
260+ cpu-idle-states = <&cpu_pw15>;
261261 };
262262
263263 cpu@701 {
@@ -273,7 +273,7 @@ · 9 unmodified lines
273273 i-cache-line-size = <64>;
274274 i-cache-sets = <192>;
275275 next-level-cache = <&cluster7_l2>;
276− cpu-idle-states = <&cpu_pw20>;
276+ cpu-idle-states = <&cpu_pw15>;
277277 };
278278
279279 cluster0_l2: l2-cache0 {
@@ -340,9 +340,9 @@ · 60 unmodified lines
340340 cache-level = <2>;
341341 };
342342
343− cpu_pw20: cpu-pw20 {
343+ cpu_pw15: cpu-pw15 {
344344 compatible = "arm,idle-state";
345− idle-state-name = "PW20";
345+ idle-state-name = "PW15";
346346 arm,psci-suspend-param = <0x0>;
347347 entry-latency-us = <2000>;
348348 exit-latency-us = <2000>;
arch/arm64/boot/dts/freescale/imx8mm.dtsi+6−6
@@ -394,7 +394,7 @@ · 393 unmodified lines
394394 };
395395
396396 sdma2: dma-controller@302c0000 {
397− compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
397+ compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
398398 reg = <0x302c0000 0x10000>;
399399 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
400400 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
@@ -405,7 +405,7 @@ · 4 unmodified lines
405405 };
406406
407407 sdma3: dma-controller@302b0000 {
408− compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
408+ compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
409409 reg = <0x302b0000 0x10000>;
410410 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
411411 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
@@ -694,7 +694,7 @@ · 282 unmodified lines
694694 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
695695 reg = <0x30b40000 0x10000>;
696696 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
697− clocks = <&clk IMX8MM_CLK_DUMMY>,
697+ clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
698698 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
699699 <&clk IMX8MM_CLK_USDHC1_ROOT>;
700700 clock-names = "ipg", "ahb", "per";
@@ -710,7 +710,7 @@ · 9 unmodified lines
710710 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
711711 reg = <0x30b50000 0x10000>;
712712 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
713− clocks = <&clk IMX8MM_CLK_DUMMY>,
713+ clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
714714 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
715715 <&clk IMX8MM_CLK_USDHC2_ROOT>;
716716 clock-names = "ipg", "ahb", "per";
@@ -724,7 +724,7 @@ · 7 unmodified lines
724724 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
725725 reg = <0x30b60000 0x10000>;
726726 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
727− clocks = <&clk IMX8MM_CLK_DUMMY>,
727+ clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
728728 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
729729 <&clk IMX8MM_CLK_USDHC3_ROOT>;
730730 clock-names = "ipg", "ahb", "per";
@@ -737,7 +737,7 @@ · 6 unmodified lines
737737 };
738738
739739 sdma1: dma-controller@30bd0000 {
740− compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
740+ compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
741741 reg = <0x30bd0000 0x10000>;
742742 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
743743 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
arch/arm64/boot/dts/freescale/imx8mn.dtsi+6−6
@@ -288,7 +288,7 @@ · 287 unmodified lines
288288 };
289289
290290 sdma3: dma-controller@302b0000 {
291− compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
291+ compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
292292 reg = <0x302b0000 0x10000>;
293293 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
294294 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
@@ -299,7 +299,7 @@ · 4 unmodified lines
299299 };
300300
301301 sdma2: dma-controller@302c0000 {
302− compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
302+ compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
303303 reg = <0x302c0000 0x10000>;
304304 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
305305 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
@@ -569,7 +569,7 @@ · 263 unmodified lines
569569 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
570570 reg = <0x30b40000 0x10000>;
571571 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
572− clocks = <&clk IMX8MN_CLK_DUMMY>,
572+ clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
573573 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
574574 <&clk IMX8MN_CLK_USDHC1_ROOT>;
575575 clock-names = "ipg", "ahb", "per";
@@ -585,7 +585,7 @@ · 9 unmodified lines
585585 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
586586 reg = <0x30b50000 0x10000>;
587587 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
588− clocks = <&clk IMX8MN_CLK_DUMMY>,
588+ clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
589589 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
590590 <&clk IMX8MN_CLK_USDHC2_ROOT>;
591591 clock-names = "ipg", "ahb", "per";
@@ -599,7 +599,7 @@ · 7 unmodified lines
599599 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
600600 reg = <0x30b60000 0x10000>;
601601 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
602− clocks = <&clk IMX8MN_CLK_DUMMY>,
602+ clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
603603 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
604604 <&clk IMX8MN_CLK_USDHC3_ROOT>;
605605 clock-names = "ipg", "ahb", "per";
@@ -612,7 +612,7 @@ · 6 unmodified lines
612612 };
613613
614614 sdma1: dma-controller@30bd0000 {
615− compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
615+ compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
616616 reg = <0x30bd0000 0x10000>;
617617 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
618618 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi+3−3
@@ -88,9 +88,9 @@ · 87 unmodified lines
8888 regulator-name = "0V9_ARM";
8989 regulator-min-microvolt = <900000>;
9090 regulator-max-microvolt = <1000000>;
91− gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
92− states = <1000000 0x0
93− 900000 0x1>;
91+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
92+ states = <1000000 0x1
93+ 900000 0x0>;
9494 regulator-always-on;
9595 };
9696 };
arch/arm64/boot/dts/freescale/imx8mq.dtsi+2−2
@@ -850,7 +850,7 @@ · 849 unmodified lines
850850 "fsl,imx7d-usdhc";
851851 reg = <0x30b40000 0x10000>;
852852 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
853− clocks = <&clk IMX8MQ_CLK_DUMMY>,
853+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
854854 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
855855 <&clk IMX8MQ_CLK_USDHC1_ROOT>;
856856 clock-names = "ipg", "ahb", "per";
@@ -867,7 +867,7 @@ · 10 unmodified lines
867867 "fsl,imx7d-usdhc";
868868 reg = <0x30b50000 0x10000>;
869869 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
870− clocks = <&clk IMX8MQ_CLK_DUMMY>,
870+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
871871 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
872872 <&clk IMX8MQ_CLK_USDHC2_ROOT>;
873873 clock-names = "ipg", "ahb", "per";
arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts+7−6
@@ -60,11 +60,6 @@ · 59 unmodified lines
6060 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
6161 };
6262
63− usb3_phy: usb3-phy {
64− compatible = "usb-nop-xceiv";
65− vcc-supply = <&exp_usb3_vbus>;
66− };
67−
6863 vsdc_reg: vsdc-reg {
6964 compatible = "regulator-gpio";
7065 regulator-name = "vsdc";
@@ -255,10 +250,16 @@ · 184 unmodified lines
255250 status = "okay";
256251 };
257252
253+&comphy2 {
254+ connector {
255+ compatible = "usb-a-connector";
256+ phy-supply = <&exp_usb3_vbus>;
257+ };
258+};
259+
258260 &usb3 {
259261 status = "okay";
260262 phys = <&comphy2 0>;
261− usb-phy = <&usb3_phy>;
262263 };
263264
264265 &mdio {
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts+1−1
@@ -44,7 +44,7 @@ · 43 unmodified lines
4444 power-supply = <&pp3300_disp>;
4545
4646 panel-timing {
47− clock-frequency = <266604720>;
47+ clock-frequency = <266666667>;
4848 hactive = <2400>;
4949 hfront-porch = <48>;
5050 hback-porch = <84>;
arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts+2−2
@@ -644,7 +644,7 @@ · 643 unmodified lines
644644 status = "okay";
645645
646646 u2phy0_host: host-port {
647− phy-supply = <&vcc5v0_host>;
647+ phy-supply = <&vcc5v0_typec>;
648648 status = "okay";
649649 };
650650
@@ -712,7 +712,7 @@ · 61 unmodified lines
712712
713713 &usbdrd_dwc3_0 {
714714 status = "okay";
715− dr_mode = "otg";
715+ dr_mode = "host";
716716 };
717717
718718 &usbdrd3_1 {
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts+5−7
@@ -173,7 +173,7 @@ · 172 unmodified lines
173173 regulator-always-on;
174174 regulator-boot-on;
175175 regulator-min-microvolt = <800000>;
176− regulator-max-microvolt = <1400000>;
176+ regulator-max-microvolt = <1700000>;
177177 vin-supply = <&vcc5v0_sys>;
178178 };
179179 };
@@ -247,8 +247,8 @@ · 67 unmodified lines
247247 rk808: pmic@1b {
248248 compatible = "rockchip,rk808";
249249 reg = <0x1b>;
250− interrupt-parent = <&gpio1>;
251− interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
250+ interrupt-parent = <&gpio3>;
251+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
252252 #clock-cells = <1>;
253253 clock-output-names = "xin32k", "rk808-clkout2";
254254 pinctrl-names = "default";
@@ -574,7 +574,7 @@ · 319 unmodified lines
574574
575575 pmic {
576576 pmic_int_l: pmic-int-l {
577− rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
577+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
578578 };
579579
580580 vsel1_gpio: vsel1-gpio {
@@ -624,7 +624,6 @@ · 43 unmodified lines
624624
625625 &sdmmc {
626626 bus-width = <4>;
627− cap-mmc-highspeed;
628627 cap-sd-highspeed;
629628 cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
630629 disable-wp;
@@ -636,8 +635,7 @@ · 5 unmodified lines
636635
637636 &sdhci {
638637 bus-width = <8>;
639− mmc-hs400-1_8v;
640− mmc-hs400-enhanced-strobe;
638+ mmc-hs200-1_8v;
641639 non-removable;
642640 status = "okay";
643641 };
arch/arm64/include/asm/asm-uaccess.h+3−4
@@ -78,10 +78,9 @@ alternative_else_nop_endif · 77 unmodified lines
7878 /*
7979 * Remove the address tag from a virtual address, if present.
8080 */
81− .macro clear_address_tag, dst, addr
82− tst \addr, #(1 << 55)
83− bic \dst, \addr, #(0xff << 56)
84− csel \dst, \dst, \addr, eq
81+ .macro untagged_addr, dst, addr
82+ sbfx \dst, \addr, #0, #56
83+ and \dst, \dst, \addr
8584 .endm
8685
8786 #endif
arch/arm64/include/asm/atomic_lse.h+4−2
@@ -321,7 +321,8 @@ static inline s64 __lse_atomic64_dec_if_positive(atomic64_t *v) · 320 unmodified lines
321321 }
322322
323323 #define __CMPXCHG_CASE(w, sfx, name, sz, mb, cl...) \
324−static inline u##sz __lse__cmpxchg_case_##name##sz(volatile void *ptr, \
324+static __always_inline u##sz \
325+__lse__cmpxchg_case_##name##sz(volatile void *ptr, \
325326 u##sz old, \
326327 u##sz new) \
327328 { \
@@ -362,7 +363,8 @@ __CMPXCHG_CASE(x, , mb_, 64, al, "memory") · 34 unmodified lines
362363 #undef __CMPXCHG_CASE
363364
364365 #define __CMPXCHG_DBL(name, mb, cl...) \
365−static inline long __lse__cmpxchg_double##name(unsigned long old1, \
366+static __always_inline long \
367+__lse__cmpxchg_double##name(unsigned long old1, \
366368 unsigned long old2, \
367369 unsigned long new1, \
368370 unsigned long new2, \
arch/arm64/include/asm/cpucaps.h+3−1
@@ -52,7 +52,9 @@ · 51 unmodified lines
5252 #define ARM64_HAS_IRQ_PRIO_MASKING 42
5353 #define ARM64_HAS_DCPODP 43
5454 #define ARM64_WORKAROUND_1463225 44
55+#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45
56+#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46
5557
56−#define ARM64_NCAPS 45
58+#define ARM64_NCAPS 47
5759
5860 #endif /* __ASM_CPUCAPS_H */
arch/arm64/include/asm/cputype.h+2−0
@@ -79,6 +79,7 @@ · 78 unmodified lines
7979 #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
8080 #define CAVIUM_CPU_PART_THUNDERX2 0x0AF
8181
82+#define BRCM_CPU_PART_BRAHMA_B53 0x100
8283 #define BRCM_CPU_PART_VULCAN 0x516
8384
8485 #define QCOM_CPU_PART_FALKOR_V1 0x800
@@ -105,6 +106,7 @@ · 20 unmodified lines
105106 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
106107 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
107108 #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
109+#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
108110 #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
109111 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
110112 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
arch/arm64/include/asm/memory.h+8−2
@@ -215,12 +215,18 @@ static inline unsigned long kaslr_offset(void) · 214 unmodified lines
215215 * up with a tagged userland pointer. Clear the tag to get a sane pointer to
216216 * pass on to access_ok(), for instance.
217217 */
218−#define untagged_addr(addr) \
218+#define __untagged_addr(addr) \
219219 ((__force __typeof__(addr))sign_extend64((__force u64)(addr), 55))
220220
221+#define untagged_addr(addr) ({ \
222+ u64 __addr = (__force u64)addr; \
223+ __addr &= __untagged_addr(__addr); \
224+ (__force __typeof__(addr))__addr; \
225+})
226+
221227 #ifdef CONFIG_KASAN_SW_TAGS
222228 #define __tag_shifted(tag) ((u64)(tag) << 56)
223−#define __tag_reset(addr) untagged_addr(addr)
229+#define __tag_reset(addr) __untagged_addr(addr)
224230 #define __tag_get(addr) (__u8)((u64)(addr) >> 56)
225231 #else
226232 #define __tag_shifted(tag) 0UL
arch/arm64/include/asm/pgtable-prot.h+8−7
@@ -32,11 +32,11 @@ · 31 unmodified lines
3232 #define PROT_DEFAULT (_PROT_DEFAULT | PTE_MAYBE_NG)
3333 #define PROT_SECT_DEFAULT (_PROT_SECT_DEFAULT | PMD_MAYBE_NG)
3434
35−#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
36−#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
37−#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
38−#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
39−#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
35+#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
36+#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
37+#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
38+#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
39+#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
4040
4141 #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
4242 #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
@@ -80,8 +80,9 @@ · 37 unmodified lines
8080 #define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_S2_XN)
8181
8282 #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
83−#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
84−#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
83+/* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
84+#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
85+#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
8586 #define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
8687 #define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
8788 #define PAGE_EXECONLY __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
arch/arm64/include/asm/pgtable.h+0−20
@@ -283,23 +283,6 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, · 282 unmodified lines
283283 set_pte(ptep, pte);
284284 }
285285
286−#define __HAVE_ARCH_PTE_SAME
287−static inline int pte_same(pte_t pte_a, pte_t pte_b)
288−{
289− pteval_t lhs, rhs;
290−
291− lhs = pte_val(pte_a);
292− rhs = pte_val(pte_b);
293−
294− if (pte_present(pte_a))
295− lhs &= ~PTE_RDONLY;
296−
297− if (pte_present(pte_b))
298− rhs &= ~PTE_RDONLY;
299−
300− return (lhs == rhs);
301−}
302−
303286 /*
304287 * Huge pte definitions.
305288 */
@@ -876,9 +859,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, · 570 unmodified lines
876859
877860 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
878861
879−#define kc_vaddr_to_offset(v) ((v) & ~PAGE_END)
880−#define kc_offset_to_vaddr(o) ((o) | PAGE_END)
881−
882862 #ifdef CONFIG_ARM64_PA_BITS_52
883863 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
884864 #else
arch/arm64/include/asm/sysreg.h+1−1
@@ -212,7 +212,7 @@ · 211 unmodified lines
212212 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
213213 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
214214
215−#define SYS_PAR_EL1_F BIT(1)
215+#define SYS_PAR_EL1_F BIT(0)
216216 #define SYS_PAR_EL1_FST GENMASK(6, 1)
217217
218218 /*** Statistical Profiling Extension ***/
arch/arm64/include/asm/vdso/compat_barrier.h+1−1
@@ -20,7 +20,7 @@ · 19 unmodified lines
2020
2121 #define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")
2222
23−#if __LINUX_ARM_ARCH__ >= 8
23+#if __LINUX_ARM_ARCH__ >= 8 && defined(CONFIG_AS_DMB_ISHLD)
2424 #define aarch32_smp_mb() dmb(ish)
2525 #define aarch32_smp_rmb() dmb(ishld)
2626 #define aarch32_smp_wmb() dmb(ishst)
arch/arm64/include/asm/vdso/vsyscall.h+0−7
@@ -30,13 +30,6 @@ int __arm64_get_clock_mode(struct timekeeper *tk) · 29 unmodified lines
3030 }
3131 #define __arch_get_clock_mode __arm64_get_clock_mode
3232
33−static __always_inline
34−int __arm64_use_vsyscall(struct vdso_data *vdata)
35−{
36− return !vdata[CS_HRES_COARSE].clock_mode;
37−}
38−#define __arch_use_vsyscall __arm64_use_vsyscall
39−
4033 static __always_inline
4134 void __arm64_update_vsyscall(struct vdso_data *vdata, struct timekeeper *tk)
4235 {
arch/arm64/include/asm/vdso_datapage.h+0−33
@@ -1,33 +0,0 @@
1−/* SPDX-License-Identifier: GPL-2.0-only */
2−/*
3− * Copyright (C) 2012 ARM Limited
4− */
5−#ifndef __ASM_VDSO_DATAPAGE_H
6−#define __ASM_VDSO_DATAPAGE_H
7−
8−#ifndef __ASSEMBLY__
9−
10−struct vdso_data {
11− __u64 cs_cycle_last; /* Timebase at clocksource init */
12− __u64 raw_time_sec; /* Raw time */
13− __u64 raw_time_nsec;
14− __u64 xtime_clock_sec; /* Kernel time */
15− __u64 xtime_clock_nsec;
16− __u64 xtime_coarse_sec; /* Coarse time */
17− __u64 xtime_coarse_nsec;
18− __u64 wtm_clock_sec; /* Wall to monotonic time */
19− __u64 wtm_clock_nsec;
20− __u32 tb_seq_count; /* Timebase sequence counter */
21− /* cs_* members must be adjacent and in this order (ldp accesses) */
22− __u32 cs_mono_mult; /* NTP-adjusted clocksource multiplier */
23− __u32 cs_shift; /* Clocksource shift (mono = raw) */
24− __u32 cs_raw_mult; /* Raw clocksource multiplier */
25− __u32 tz_minuteswest; /* Whacky timezone stuff */
26− __u32 tz_dsttime;
27− __u32 use_syscall;
28− __u32 hrtimer_res;
29−};
30−
31−#endif /* !__ASSEMBLY__ */
32−
33−#endif /* __ASM_VDSO_DATAPAGE_H */
arch/arm64/kernel/armv8_deprecated.c+5−0
@@ -174,6 +174,9 @@ static void __init register_insn_emulation(struct insn_emulation_ops *ops) · 173 unmodified lines
174174 struct insn_emulation *insn;
175175
176176 insn = kzalloc(sizeof(*insn), GFP_KERNEL);
177+ if (!insn)
178+ return;
179+
177180 insn->ops = ops;
178181 insn->min = INSN_UNDEF;
179182
@@ -233,6 +236,8 @@ static void __init register_insn_emulation_sysctl(void) · 53 unmodified lines
233236
234237 insns_sysctl = kcalloc(nr_insn_emulated + 1, sizeof(*sysctl),
235238 GFP_KERNEL);
239+ if (!insns_sysctl)
240+ return;
236241
237242 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
238243 list_for_each_entry(insn, &insn_emulation, node) {
arch/arm64/kernel/cpu_errata.c+88−13
@@ -12,6 +12,7 @@ · 11 unmodified lines
1212 #include <asm/cpu.h>
1313 #include <asm/cputype.h>
1414 #include <asm/cpufeature.h>
15+#include <asm/smp_plat.h>
1516
1617 static bool __maybe_unused
1718 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
@@ -128,8 +129,8 @@ static void install_bp_hardening_cb(bp_hardening_cb_t fn, · 110 unmodified lines
128129 int cpu, slot = -1;
129130
130131 /*
131− * enable_smccc_arch_workaround_1() passes NULL for the hyp_vecs
132− * start/end if we're a guest. Skip the hyp-vectors work.
132+ * detect_harden_bp_fw() passes NULL for the hyp_vecs start/end if
133+ * we're a guest. Skip the hyp-vectors work.
133134 */
134135 if (!hyp_vecs_start) {
135136 __this_cpu_write(bp_hardening_data.fn, fn);
@@ -488,6 +489,7 @@ static const struct midr_range arm64_ssb_cpus[] = { · 352 unmodified lines
488489 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
489490 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
490491 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
492+ MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
491493 {},
492494 };
493495
@@ -572,6 +574,7 @@ static const struct midr_range spectre_v2_safe_list[] = { · 78 unmodified lines
572574 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
573575 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
574576 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
577+ MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
575578 { /* sentinel */ }
576579 };
577580
@@ -623,6 +626,30 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) · 45 unmodified lines
623626 return (need_wa > 0);
624627 }
625628
629+static const __maybe_unused struct midr_range tx2_family_cpus[] = {
630+ MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
631+ MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
632+ {},
633+};
634+
635+static bool __maybe_unused
636+needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
637+ int scope)
638+{
639+ int i;
640+
641+ if (!is_affected_midr_range_list(entry, scope) ||
642+ !is_hyp_mode_available())
643+ return false;
644+
645+ for_each_possible_cpu(i) {
646+ if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
647+ return true;
648+ }
649+
650+ return false;
651+}
652+
626653 #ifdef CONFIG_HARDEN_EL2_VECTORS
627654
628655 static const struct midr_range arm64_harden_el2_vectors[] = {
@@ -634,17 +661,23 @@ static const struct midr_range arm64_harden_el2_vectors[] = { · 5 unmodified lines
634661 #endif
635662
636663 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
637−
638−static const struct midr_range arm64_repeat_tlbi_cpus[] = {
664+static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
639665 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
640− MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0, 0, 0, 0),
666+ {
667+ ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
668+ },
669+ {
670+ .midr_range.model = MIDR_QCOM_KRYO,
671+ .matches = is_kryo_midr,
672+ },
641673 #endif
642674 #ifdef CONFIG_ARM64_ERRATUM_1286807
643− MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
675+ {
676+ ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
677+ },
644678 #endif
645679 {},
646680 };
647−
648681 #endif
649682
650683 #ifdef CONFIG_CAVIUM_ERRATUM_27456
@@ -712,6 +745,33 @@ static const struct midr_range erratum_1418040_list[] = { · 61 unmodified lines
712745 };
713746 #endif
714747
748+#ifdef CONFIG_ARM64_ERRATUM_845719
749+static const struct midr_range erratum_845719_list[] = {
750+ /* Cortex-A53 r0p[01234] */
751+ MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
752+ /* Brahma-B53 r0p[0] */
753+ MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
754+ {},
755+};
756+#endif
757+
758+#ifdef CONFIG_ARM64_ERRATUM_843419
759+static const struct arm64_cpu_capabilities erratum_843419_list[] = {
760+ {
761+ /* Cortex-A53 r0p[01234] */
762+ .matches = is_affected_midr_range,
763+ ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
764+ MIDR_FIXED(0x4, BIT(8)),
765+ },
766+ {
767+ /* Brahma-B53 r0p[0] */
768+ .matches = is_affected_midr_range,
769+ ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
770+ },
771+ {},
772+};
773+#endif
774+
715775 const struct arm64_cpu_capabilities arm64_errata[] = {
716776 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
717777 {
@@ -743,19 +803,18 @@ const struct arm64_cpu_capabilities arm64_errata[] = { · 25 unmodified lines
743803 #endif
744804 #ifdef CONFIG_ARM64_ERRATUM_843419
745805 {
746− /* Cortex-A53 r0p[01234] */
747806 .desc = "ARM erratum 843419",
748807 .capability = ARM64_WORKAROUND_843419,
749− ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
750− MIDR_FIXED(0x4, BIT(8)),
808+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
809+ .matches = cpucap_multi_entry_cap_matches,
810+ .match_list = erratum_843419_list,
751811 },
752812 #endif
753813 #ifdef CONFIG_ARM64_ERRATUM_845719
754814 {
755− /* Cortex-A53 r0p[01234] */
756815 .desc = "ARM erratum 845719",
757816 .capability = ARM64_WORKAROUND_845719,
758− ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
817+ ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
759818 },
760819 #endif
761820 #ifdef CONFIG_CAVIUM_ERRATUM_23154
@@ -791,6 +850,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { · 29 unmodified lines
791850 {
792851 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
793852 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
853+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
794854 .matches = cpucap_multi_entry_cap_matches,
795855 .match_list = qcom_erratum_1003_list,
796856 },
@@ -799,7 +859,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = { · 2 unmodified lines
799859 {
800860 .desc = "Qualcomm erratum 1009, ARM erratum 1286807",
801861 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
802− ERRATA_MIDR_RANGE_LIST(arm64_repeat_tlbi_cpus),
862+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
863+ .matches = cpucap_multi_entry_cap_matches,
864+ .match_list = arm64_repeat_tlbi_list,
803865 },
804866 #endif
805867 #ifdef CONFIG_ARM64_ERRATUM_858921
@@ -851,6 +913,19 @@ const struct arm64_cpu_capabilities arm64_errata[] = { · 45 unmodified lines
851913 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
852914 .matches = has_cortex_a76_erratum_1463225,
853915 },
916+#endif
917+#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
918+ {
919+ .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
920+ .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
921+ ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
922+ .matches = needs_tx2_tvm_workaround,
923+ },
924+ {
925+ .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
926+ .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
927+ ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
928+ },
854929 #endif
855930 {
856931 }
arch/arm64/kernel/cpufeature.c+11−5
@@ -136,6 +136,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { · 135 unmodified lines
136136
137137 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
138138 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
139+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
139140 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
140141 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
141142 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
@@ -175,11 +176,16 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { · 33 unmodified lines
175176 };
176177
177178 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
178− ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
179− ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
180− ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
181− ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
182− ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
179+ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
180+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
181+ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
182+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
183+ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
184+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
185+ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
186+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
187+ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
188+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
183189 ARM64_FTR_END,
184190 };
185191
arch/arm64/kernel/entry.S+6−3
@@ -604,7 +604,7 @@ el1_da: · 603 unmodified lines
604604 */
605605 mrs x3, far_el1
606606 inherit_daif pstate=x23, tmp=x2
607− clear_address_tag x0, x3
607+ untagged_addr x0, x3
608608 mov x2, sp // struct pt_regs
609609 bl do_mem_abort
610610
@@ -680,7 +680,7 @@ alternative_if ARM64_HAS_IRQ_PRIO_MASKING · 69 unmodified lines
680680 orr x24, x24, x0
681681 alternative_else_nop_endif
682682 cbnz x24, 1f // preempt count != 0 || NMI return path
683− bl preempt_schedule_irq // irq en/disable is done inside
683+ bl arm64_preempt_schedule_irq // irq en/disable is done inside
684684 1:
685685 #endif
686686
@@ -775,6 +775,7 @@ el0_sync_compat: · 88 unmodified lines
775775 b.ge el0_dbg
776776 b el0_inv
777777 el0_svc_compat:
778+ gic_prio_kentry_setup tmp=x1
778779 mov x0, sp
779780 bl el0_svc_compat_handler
780781 b ret_to_user
@@ -807,7 +808,7 @@ el0_da: · 26 unmodified lines
807808 mrs x26, far_el1
808809 ct_user_exit_irqoff
809810 enable_daif
810− clear_address_tag x0, x26
811+ untagged_addr x0, x26
811812 mov x1, x25
812813 mov x2, sp
813814 bl do_mem_abort
@@ -1070,7 +1071,9 @@ alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 · 256 unmodified lines
10701071 #else
10711072 ldr x30, =vectors
10721073 #endif
1074+alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM
10731075 prfm plil1strm, [x30, #(1b - tramp_vectors)]
1076+alternative_else_nop_endif
10741077 msr vbar_el1, x30
10751078 add x30, x30, #(1b - tramp_vectors)
10761079 isb
arch/arm64/kernel/ftrace.c+9−3
@@ -121,10 +121,16 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) · 120 unmodified lines
121121
122122 /*
123123 * Ensure updated trampoline is visible to instruction
124− * fetch before we patch in the branch.
124+ * fetch before we patch in the branch. Although the
125+ * architecture doesn't require an IPI in this case,
126+ * Neoverse-N1 erratum #1542419 does require one
127+ * if the TLB maintenance in module_enable_ro() is
128+ * skipped due to rodata_enabled. It doesn't seem worth
129+ * it to make it conditional given that this is
130+ * certainly not a fast-path.
125131 */
126− __flush_icache_range((unsigned long)&dst[0],
127− (unsigned long)&dst[1]);
132+ flush_icache_range((unsigned long)&dst[0],
133+ (unsigned long)&dst[1]);
128134 }
129135 addr = (unsigned long)dst;
130136 #else /* CONFIG_ARM64_MODULE_PLTS */
arch/arm64/kernel/hibernate.c+8−1
@@ -201,6 +201,7 @@ static int create_safe_exec_page(void *src_start, size_t length, · 200 unmodified lines
201201 gfp_t mask)
202202 {
203203 int rc = 0;
204+ pgd_t *trans_pgd;
204205 pgd_t *pgdp;
205206 pud_t *pudp;
206207 pmd_t *pmdp;
@@ -215,7 +216,13 @@ static int create_safe_exec_page(void *src_start, size_t length, · 8 unmodified lines
215216 memcpy((void *)dst, src_start, length);
216217 __flush_icache_range(dst, dst + length);
217218
218− pgdp = pgd_offset_raw(allocator(mask), dst_addr);
219+ trans_pgd = allocator(mask);
220+ if (!trans_pgd) {
221+ rc = -ENOMEM;
222+ goto out;
223+ }
224+
225+ pgdp = pgd_offset_raw(trans_pgd, dst_addr);
219226 if (pgd_none(READ_ONCE(*pgdp))) {
220227 pudp = allocator(mask);
221228 if (!pudp) {
arch/arm64/kernel/process.c+33−17
@@ -17,6 +17,7 @@ · 16 unmodified lines
1717 #include <linux/sched/task.h>
1818 #include <linux/sched/task_stack.h>
1919 #include <linux/kernel.h>
20+#include <linux/lockdep.h>
2021 #include <linux/mm.h>
2122 #include <linux/stddef.h>
2223 #include <linux/sysctl.h>
@@ -44,6 +45,7 @@ · 21 unmodified lines
4445 #include <asm/alternative.h>
4546 #include <asm/arch_gicv3.h>
4647 #include <asm/compat.h>
48+#include <asm/cpufeature.h>
4749 #include <asm/cacheflush.h>
4850 #include <asm/exec.h>
4951 #include <asm/fpsimd.h>
@@ -332,22 +334,27 @@ void arch_release_task_struct(struct task_struct *tsk) · 282 unmodified lines
332334 fpsimd_release_task(tsk);
333335 }
334336
335−/*
336− * src and dst may temporarily have aliased sve_state after task_struct
337− * is copied. We cannot fix this properly here, because src may have
338− * live SVE state and dst's thread_info may not exist yet, so tweaking
339− * either src's or dst's TIF_SVE is not safe.
340− *
341− * The unaliasing is done in copy_thread() instead. This works because
342− * dst is not schedulable or traceable until both of these functions
343− * have been called.
344− */
345337 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
346338 {
347339 if (current->mm)
348340 fpsimd_preserve_current_state();
349341 *dst = *src;
350342
343+ /* We rely on the above assignment to initialize dst's thread_flags: */
344+ BUILD_BUG_ON(!IS_ENABLED(CONFIG_THREAD_INFO_IN_TASK));
345+
346+ /*
347+ * Detach src's sve_state (if any) from dst so that it does not
348+ * get erroneously used or freed prematurely. dst's sve_state
349+ * will be allocated on demand later on if dst uses SVE.
350+ * For consistency, also clear TIF_SVE here: this could be done
351+ * later in copy_process(), but to avoid tripping up future
352+ * maintainers it is best not to leave TIF_SVE and sve_state in
353+ * an inconsistent state, even temporarily.
354+ */
355+ dst->thread.sve_state = NULL;
356+ clear_tsk_thread_flag(dst, TIF_SVE);
357+
351358 return 0;
352359 }
353360
@@ -360,13 +367,6 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start, · 6 unmodified lines
360367
361368 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
362369
363− /*
364− * Unalias p->thread.sve_state (if any) from the parent task
365− * and disable discard SVE state for p:
366− */
367− clear_tsk_thread_flag(p, TIF_SVE);
368− p->thread.sve_state = NULL;
369−
370370 /*
371371 * In case p was allocated the same task_struct pointer as some
372372 * other recently-exited task, make sure p is disassociated from
@@ -633,3 +633,19 @@ static int __init tagged_addr_init(void) · 260 unmodified lines
633633
634634 core_initcall(tagged_addr_init);
635635 #endif /* CONFIG_ARM64_TAGGED_ADDR_ABI */
636+
637+asmlinkage void __sched arm64_preempt_schedule_irq(void)
638+{
639+ lockdep_assert_irqs_disabled();
640+
641+ /*
642+ * Preempting a task from an IRQ means we leave copies of PSTATE
643+ * on the stack. cpufeature's enable calls may modify PSTATE, but
644+ * resuming one of these preempted tasks would undo those changes.
645+ *
646+ * Only allow a task to be preempted once cpufeatures have been
647+ * enabled.
648+ */
649+ if (static_branch_likely(&arm64_const_caps_ready))
650+ preempt_schedule_irq();
651+}
arch/arm64/kernel/vdso32/Makefile+28−16
@@ -8,15 +8,21 @@ · 7 unmodified lines
88 ARCH_REL_TYPE_ABS := R_ARM_JUMP_SLOT|R_ARM_GLOB_DAT|R_ARM_ABS32
99 include $(srctree)/lib/vdso/Makefile
1010
11−COMPATCC := $(CROSS_COMPILE_COMPAT)gcc
11+# Same as cc-*option, but using CC_COMPAT instead of CC
12+ifeq ($(CONFIG_CC_IS_CLANG), y)
13+CC_COMPAT ?= $(CC)
14+else
15+CC_COMPAT ?= $(CROSS_COMPILE_COMPAT)gcc
16+endif
1217
13−# Same as cc-*option, but using COMPATCC instead of CC
1418 cc32-option = $(call try-run,\
15− $(COMPATCC) $(1) -c -x c /dev/null -o "$$TMP",$(1),$(2))
19+ $(CC_COMPAT) $(1) -c -x c /dev/null -o "$$TMP",$(1),$(2))
1620 cc32-disable-warning = $(call try-run,\
17− $(COMPATCC) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1)))
21+ $(CC_COMPAT) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1)))
1822 cc32-ldoption = $(call try-run,\
19− $(COMPATCC) $(1) -nostdlib -x c /dev/null -o "$$TMP",$(1),$(2))
23+ $(CC_COMPAT) $(1) -nostdlib -x c /dev/null -o "$$TMP",$(1),$(2))
24+cc32-as-instr = $(call try-run,\
25+ printf "%b\n" "$(1)" | $(CC_COMPAT) $(VDSO_AFLAGS) -c -x assembler -o "$$TMP" -,$(2),$(3))
2026
2127 # We cannot use the global flags to compile the vDSO files, the main reason
2228 # being that the 32-bit compiler may be older than the main (64-bit) compiler
@@ -25,22 +31,21 @@ cc32-ldoption = $(call try-run,\ · 2 unmodified lines
2531 # arm64 one.
2632 # As a result we set our own flags here.
2733
28−# From top-level Makefile
29−# NOSTDINC_FLAGS
30−VDSO_CPPFLAGS := -nostdinc -isystem $(shell $(COMPATCC) -print-file-name=include)
34+# KBUILD_CPPFLAGS and NOSTDINC_FLAGS from top-level Makefile
35+VDSO_CPPFLAGS := -D__KERNEL__ -nostdinc -isystem $(shell $(CC_COMPAT) -print-file-name=include)
3136 VDSO_CPPFLAGS += $(LINUXINCLUDE)
32−VDSO_CPPFLAGS += $(KBUILD_CPPFLAGS)
3337
3438 # Common C and assembly flags
3539 # From top-level Makefile
3640 VDSO_CAFLAGS := $(VDSO_CPPFLAGS)
41+ifneq ($(shell $(CC_COMPAT) --version 2>&1 | head -n 1 | grep clang),)
42+VDSO_CAFLAGS += --target=$(notdir $(CROSS_COMPILE_COMPAT:%-=%))
43+endif
44+
3745 VDSO_CAFLAGS += $(call cc32-option,-fno-PIE)
3846 ifdef CONFIG_DEBUG_INFO
3947 VDSO_CAFLAGS += -g
4048 endif
41−ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-goto.sh $(COMPATCC)), y)
42−VDSO_CAFLAGS += -DCC_HAVE_ASM_GOTO
43−endif
4449
4550 # From arm Makefile
4651 VDSO_CAFLAGS += $(call cc32-option,-fno-dwarf2-cfi-asm)
@@ -55,6 +60,7 @@ endif · 8 unmodified lines
5560 VDSO_CAFLAGS += -fPIC -fno-builtin -fno-stack-protector
5661 VDSO_CAFLAGS += -DDISABLE_BRANCH_PROFILING
5762
63+
5864 # Try to compile for ARMv8. If the compiler is too old and doesn't support it,
5965 # fall back to v7. There is no easy way to check for what architecture the code
6066 # is being compiled, so define a macro specifying that (see arch/arm/Makefile).
@@ -91,6 +97,12 @@ VDSO_CFLAGS += -Wno-int-to-pointer-cast · 30 unmodified lines
9197 VDSO_AFLAGS := $(VDSO_CAFLAGS)
9298 VDSO_AFLAGS += -D__ASSEMBLY__
9399
100+# Check for binutils support for dmb ishld
101+dmbinstr := $(call cc32-as-instr,dmb ishld,-DCONFIG_AS_DMB_ISHLD=1)
102+
103+VDSO_CFLAGS += $(dmbinstr)
104+VDSO_AFLAGS += $(dmbinstr)
105+
94106 VDSO_LDFLAGS := $(VDSO_CPPFLAGS)
95107 # From arm vDSO Makefile
96108 VDSO_LDFLAGS += -Wl,-Bsymbolic -Wl,--no-undefined -Wl,-soname=linux-vdso.so.1
@@ -159,14 +171,14 @@ quiet_cmd_vdsold_and_vdso_check = LD32 $@ · 62 unmodified lines
159171 cmd_vdsold_and_vdso_check = $(cmd_vdsold); $(cmd_vdso_check)
160172
161173 quiet_cmd_vdsold = LD32 $@
162− cmd_vdsold = $(COMPATCC) -Wp,-MD,$(depfile) $(VDSO_LDFLAGS) \
174+ cmd_vdsold = $(CC_COMPAT) -Wp,-MD,$(depfile) $(VDSO_LDFLAGS) \
163175 -Wl,-T $(filter %.lds,$^) $(filter %.o,$^) -o $@
164176 quiet_cmd_vdsocc = CC32 $@
165− cmd_vdsocc = $(COMPATCC) -Wp,-MD,$(depfile) $(VDSO_CFLAGS) -c -o $@ $<
177+ cmd_vdsocc = $(CC_COMPAT) -Wp,-MD,$(depfile) $(VDSO_CFLAGS) -c -o $@ $<
166178 quiet_cmd_vdsocc_gettimeofday = CC32 $@
167− cmd_vdsocc_gettimeofday = $(COMPATCC) -Wp,-MD,$(depfile) $(VDSO_CFLAGS) $(VDSO_CFLAGS_gettimeofday_o) -c -o $@ $<
179+ cmd_vdsocc_gettimeofday = $(CC_COMPAT) -Wp,-MD,$(depfile) $(VDSO_CFLAGS) $(VDSO_CFLAGS_gettimeofday_o) -c -o $@ $<
168180 quiet_cmd_vdsoas = AS32 $@
169− cmd_vdsoas = $(COMPATCC) -Wp,-MD,$(depfile) $(VDSO_AFLAGS) -c -o $@ $<
181+ cmd_vdsoas = $(CC_COMPAT) -Wp,-MD,$(depfile) $(VDSO_AFLAGS) -c -o $@ $<
170182
171183 quiet_cmd_vdsomunge = MUNGE $@
172184 cmd_vdsomunge = $(obj)/$(munge) $< $@
arch/arm64/kvm/hyp/switch.c+67−2
@@ -124,6 +124,9 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu) · 123 unmodified lines
124124 {
125125 u64 hcr = vcpu->arch.hcr_el2;
126126
127+ if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
128+ hcr |= HCR_TVM;
129+
127130 write_sysreg(hcr, hcr_el2);
128131
129132 if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
@@ -174,8 +177,10 @@ static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu) · 44 unmodified lines
174177 * the crucial bit is "On taking a vSError interrupt,
175178 * HCR_EL2.VSE is cleared to 0."
176179 */
177− if (vcpu->arch.hcr_el2 & HCR_VSE)
178− vcpu->arch.hcr_el2 = read_sysreg(hcr_el2);
180+ if (vcpu->arch.hcr_el2 & HCR_VSE) {
181+ vcpu->arch.hcr_el2 &= ~HCR_VSE;
182+ vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE;
183+ }
179184
180185 if (has_vhe())
181186 deactivate_traps_vhe();
@@ -380,6 +385,61 @@ static bool __hyp_text __hyp_handle_fpsimd(struct kvm_vcpu *vcpu) · 198 unmodified lines
380385 return true;
381386 }
382387
388+static bool __hyp_text handle_tx2_tvm(struct kvm_vcpu *vcpu)
389+{
390+ u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_hsr(vcpu));
391+ int rt = kvm_vcpu_sys_get_rt(vcpu);
392+ u64 val = vcpu_get_reg(vcpu, rt);
393+
394+ /*
395+ * The normal sysreg handling code expects to see the traps,
396+ * let's not do anything here.
397+ */
398+ if (vcpu->arch.hcr_el2 & HCR_TVM)
399+ return false;
400+
401+ switch (sysreg) {
402+ case SYS_SCTLR_EL1:
403+ write_sysreg_el1(val, SYS_SCTLR);
404+ break;
405+ case SYS_TTBR0_EL1:
406+ write_sysreg_el1(val, SYS_TTBR0);
407+ break;
408+ case SYS_TTBR1_EL1:
409+ write_sysreg_el1(val, SYS_TTBR1);
410+ break;
411+ case SYS_TCR_EL1:
412+ write_sysreg_el1(val, SYS_TCR);
413+ break;
414+ case SYS_ESR_EL1:
415+ write_sysreg_el1(val, SYS_ESR);
416+ break;
417+ case SYS_FAR_EL1:
418+ write_sysreg_el1(val, SYS_FAR);
419+ break;
420+ case SYS_AFSR0_EL1:
421+ write_sysreg_el1(val, SYS_AFSR0);
422+ break;
423+ case SYS_AFSR1_EL1:
424+ write_sysreg_el1(val, SYS_AFSR1);
425+ break;
426+ case SYS_MAIR_EL1:
427+ write_sysreg_el1(val, SYS_MAIR);
428+ break;
429+ case SYS_AMAIR_EL1:
430+ write_sysreg_el1(val, SYS_AMAIR);
431+ break;
432+ case SYS_CONTEXTIDR_EL1:
433+ write_sysreg_el1(val, SYS_CONTEXTIDR);
434+ break;
435+ default:
436+ return false;
437+ }
438+
439+ __kvm_skip_instr(vcpu);
440+ return true;
441+}
442+
383443 /*
384444 * Return true when we were able to fixup the guest exit and should return to
385445 * the guest, false when we should restore the host state and return to the
@@ -399,6 +459,11 @@ static bool __hyp_text fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) · 13 unmodified lines
399459 if (*exit_code != ARM_EXCEPTION_TRAP)
400460 goto exit;
401461
462+ if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
463+ kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 &&
464+ handle_tx2_tvm(vcpu))
465+ return true;
466+
402467 /*
403468 * We trap the first access to the FP/SIMD to save the host context
404469 * and restore the guest context lazily.
arch/arm64/kvm/sys_regs.c+4−0
@@ -632,6 +632,8 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) · 631 unmodified lines
632632 */
633633 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
634634 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
635+ if (!system_supports_32bit_el0())
636+ val |= ARMV8_PMU_PMCR_LC;
635637 __vcpu_sys_reg(vcpu, r->reg) = val;
636638 }
637639
@@ -682,6 +684,8 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, · 44 unmodified lines
682684 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
683685 val &= ~ARMV8_PMU_PMCR_MASK;
684686 val |= p->regval & ARMV8_PMU_PMCR_MASK;
687+ if (!system_supports_32bit_el0())
688+ val |= ARMV8_PMU_PMCR_LC;
685689 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
686690 kvm_pmu_handle_pmcr(vcpu, val);
687691 kvm_vcpu_pmu_restore_guest(vcpu);
arch/arm64/mm/fault.c+16−3
@@ -113,6 +113,15 @@ static inline bool is_ttbr1_addr(unsigned long addr) · 112 unmodified lines
113113 return arch_kasan_reset_tag(addr) >= PAGE_OFFSET;
114114 }
115115
116+static inline unsigned long mm_to_pgd_phys(struct mm_struct *mm)
117+{
118+ /* Either init_pg_dir or swapper_pg_dir */
119+ if (mm == &init_mm)
120+ return __pa_symbol(mm->pgd);
121+
122+ return (unsigned long)virt_to_phys(mm->pgd);
123+}
124+
116125 /*
117126 * Dump out the page tables associated with 'addr' in the currently active mm.
118127 */
@@ -141,7 +150,7 @@ static void show_pte(unsigned long addr) · 22 unmodified lines
141150
142151 pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n",
143152 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K,
144− vabits_actual, (unsigned long)virt_to_phys(mm->pgd));
153+ vabits_actual, mm_to_pgd_phys(mm));
145154 pgdp = pgd_offset(mm, addr);
146155 pgd = READ_ONCE(*pgdp);
147156 pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd));
@@ -259,14 +268,18 @@ static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr, · 111 unmodified lines
259268 par = read_sysreg(par_el1);
260269 local_irq_restore(flags);
261270
271+ /*
272+ * If we now have a valid translation, treat the translation fault as
273+ * spurious.
274+ */
262275 if (!(par & SYS_PAR_EL1_F))
263− return false;
276+ return true;
264277
265278 /*
266279 * If we got a different type of fault from the AT instruction,
267280 * treat the translation fault as spurious.
268281 */
269− dfsc = FIELD_PREP(SYS_PAR_EL1_FST, par);
282+ dfsc = FIELD_GET(SYS_PAR_EL1_FST, par);
270283 return (dfsc & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT;
271284 }
272285
arch/mips/bcm63xx/prom.c+1−1
@@ -84,7 +84,7 @@ void __init prom_init(void) · 83 unmodified lines
8484 * Here we will start up CPU1 in the background and ask it to
8585 * reconfigure itself then go back to sleep.
8686 */
87− memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
87+ memcpy((void *)0xa0000200, bmips_smp_movevec, 0x20);
8888 __sync();
8989 set_c0_cause(C_SW0);
9090 cpumask_set_cpu(1, &bmips_booted_mask);
arch/mips/configs/mtx1_defconfig+0−1
@@ -571,7 +571,6 @@ CONFIG_USB_SERIAL_OMNINET=m · 570 unmodified lines
571571 CONFIG_USB_EMI62=m
572572 CONFIG_USB_EMI26=m
573573 CONFIG_USB_ADUTUX=m
574−CONFIG_USB_RIO500=m
575574 CONFIG_USB_LEGOTOWER=m
576575 CONFIG_USB_LCD=m
577576 CONFIG_USB_CYPRESS_CY7C63=m
arch/mips/configs/rm200_defconfig+0−1
@@ -314,7 +314,6 @@ CONFIG_USB_SERIAL_SAFE_PADDED=y · 313 unmodified lines
314314 CONFIG_USB_SERIAL_CYBERJACK=m
315315 CONFIG_USB_SERIAL_XIRCOM=m
316316 CONFIG_USB_SERIAL_OMNINET=m
317−CONFIG_USB_RIO500=m
318317 CONFIG_USB_LEGOTOWER=m
319318 CONFIG_USB_LCD=m
320319 CONFIG_USB_CYTHERM=m
arch/mips/fw/sni/sniprom.c+1−1
@@ -43,7 +43,7 @@ · 42 unmodified lines
4343
4444 /* O32 stack has to be 8-byte aligned. */
4545 static u64 o32_stk[4096];
46−#define O32_STK &o32_stk[sizeof(o32_stk)]
46+#define O32_STK (&o32_stk[ARRAY_SIZE(o32_stk)])
4747
4848 #define __PROM_O32(fun, arg) fun arg __asm__(#fun); \
4949 __asm__(#fun " = call_o32")
arch/mips/include/asm/bmips.h+5−5
@@ -75,11 +75,11 @@ static inline int register_bmips_smp_ops(void) · 74 unmodified lines
7575 #endif
7676 }
7777
78−extern char bmips_reset_nmi_vec;
79−extern char bmips_reset_nmi_vec_end;
80−extern char bmips_smp_movevec;
81−extern char bmips_smp_int_vec;
82−extern char bmips_smp_int_vec_end;
78+extern char bmips_reset_nmi_vec[];
79+extern char bmips_reset_nmi_vec_end[];
80+extern char bmips_smp_movevec[];
81+extern char bmips_smp_int_vec[];
82+extern char bmips_smp_int_vec_end[];
8383
8484 extern int bmips_smp_enabled;
8585 extern int bmips_cpu_offset;
arch/mips/include/asm/cmpxchg.h+5−4
@@ -77,8 +77,8 @@ extern unsigned long __xchg_called_with_bad_pointer(void) · 76 unmodified lines
7777 extern unsigned long __xchg_small(volatile void *ptr, unsigned long val,
7878 unsigned int size);
7979
80−static inline unsigned long __xchg(volatile void *ptr, unsigned long x,
81− int size)
80+static __always_inline
81+unsigned long __xchg(volatile void *ptr, unsigned long x, int size)
8282 {
8383 switch (size) {
8484 case 1:
@@ -153,8 +153,9 @@ static inline unsigned long __xchg(volatile void *ptr, unsigned long x, · 68 unmodified lines
153153 extern unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old,
154154 unsigned long new, unsigned int size);
155155
156−static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
157− unsigned long new, unsigned int size)
156+static __always_inline
157+unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
158+ unsigned long new, unsigned int size)
158159 {
159160 switch (size) {
160161 case 1:
arch/mips/include/asm/vdso/gettimeofday.h+3−1
@@ -24,6 +24,8 @@ · 23 unmodified lines
2424
2525 #define VDSO_HAS_CLOCK_GETRES 1
2626
27+#define __VDSO_USE_SYSCALL ULLONG_MAX
28+
2729 #ifdef CONFIG_MIPS_CLOCK_VSYSCALL
2830
2931 static __always_inline long gettimeofday_fallback(
@@ -205,7 +207,7 @@ static __always_inline u64 __arch_get_hw_counter(s32 clock_mode) · 175 unmodified lines
205207 break;
206208 #endif
207209 default:
208− cycle_now = 0;
210+ cycle_now = __VDSO_USE_SYSCALL;
209211 break;
210212 }
211213
arch/mips/include/asm/vdso/vsyscall.h+0−7
@@ -28,13 +28,6 @@ int __mips_get_clock_mode(struct timekeeper *tk) · 27 unmodified lines
2828 }
2929 #define __arch_get_clock_mode __mips_get_clock_mode
3030
31−static __always_inline
32−int __mips_use_vsyscall(struct vdso_data *vdata)
33−{
34− return (vdata[CS_HRES_COARSE].clock_mode != VDSO_CLOCK_NONE);
35−}
36−#define __arch_use_vsyscall __mips_use_vsyscall
37−
3831 /* The asm-generic header needs to be included after the definitions above */
3932 #include <asm-generic/vdso/vsyscall.h>
4033
arch/mips/include/uapi/asm/hwcap.h+11−0
@@ -6,5 +6,16 @@ · 5 unmodified lines
66 #define HWCAP_MIPS_R6 (1 << 0)
77 #define HWCAP_MIPS_MSA (1 << 1)
88 #define HWCAP_MIPS_CRC32 (1 << 2)
9+#define HWCAP_MIPS_MIPS16 (1 << 3)
10+#define HWCAP_MIPS_MDMX (1 << 4)
11+#define HWCAP_MIPS_MIPS3D (1 << 5)
12+#define HWCAP_MIPS_SMARTMIPS (1 << 6)
13+#define HWCAP_MIPS_DSP (1 << 7)
14+#define HWCAP_MIPS_DSP2 (1 << 8)
15+#define HWCAP_MIPS_DSP3 (1 << 9)
16+#define HWCAP_MIPS_MIPS16E2 (1 << 10)
17+#define HWCAP_LOONGSON_MMI (1 << 11)
18+#define HWCAP_LOONGSON_EXT (1 << 12)
19+#define HWCAP_LOONGSON_EXT2 (1 << 13)
920
1021 #endif /* _UAPI_ASM_HWCAP_H */
arch/mips/kernel/cpu-probe.c+33−0
@@ -2180,6 +2180,39 @@ void cpu_probe(void) · 2179 unmodified lines
21802180 elf_hwcap |= HWCAP_MIPS_MSA;
21812181 }
21822182
2183+ if (cpu_has_mips16)
2184+ elf_hwcap |= HWCAP_MIPS_MIPS16;
2185+
2186+ if (cpu_has_mdmx)
2187+ elf_hwcap |= HWCAP_MIPS_MDMX;
2188+
2189+ if (cpu_has_mips3d)
2190+ elf_hwcap |= HWCAP_MIPS_MIPS3D;
2191+
2192+ if (cpu_has_smartmips)
2193+ elf_hwcap |= HWCAP_MIPS_SMARTMIPS;
2194+
2195+ if (cpu_has_dsp)
2196+ elf_hwcap |= HWCAP_MIPS_DSP;
2197+
2198+ if (cpu_has_dsp2)
2199+ elf_hwcap |= HWCAP_MIPS_DSP2;
2200+
2201+ if (cpu_has_dsp3)
2202+ elf_hwcap |= HWCAP_MIPS_DSP3;
2203+
2204+ if (cpu_has_mips16e2)
2205+ elf_hwcap |= HWCAP_MIPS_MIPS16E2;
2206+
2207+ if (cpu_has_loongson_mmi)
2208+ elf_hwcap |= HWCAP_LOONGSON_MMI;
2209+
2210+ if (cpu_has_loongson_ext)
2211+ elf_hwcap |= HWCAP_LOONGSON_EXT;
2212+
2213+ if (cpu_has_loongson_ext2)
2214+ elf_hwcap |= HWCAP_LOONGSON_EXT2;
2215+
21832216 if (cpu_has_vz)
21842217 cpu_probe_vz(c);
21852218
arch/mips/kernel/smp-bmips.c+4−4
@@ -464,10 +464,10 @@ static void bmips_wr_vec(unsigned long dst, char *start, char *end) · 463 unmodified lines
464464
465465 static inline void bmips_nmi_handler_setup(void)
466466 {
467− bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
468− &bmips_reset_nmi_vec_end);
469− bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
470− &bmips_smp_int_vec_end);
467+ bmips_wr_vec(BMIPS_NMI_RESET_VEC, bmips_reset_nmi_vec,
468+ bmips_reset_nmi_vec_end);
469+ bmips_wr_vec(BMIPS_WARM_RESTART_VEC, bmips_smp_int_vec,
470+ bmips_smp_int_vec_end);
471471 }
472472
473473 struct reset_vec_info {
arch/mips/loongson64/Platform+4−0
@@ -66,6 +66,10 @@ else · 65 unmodified lines
6666 $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
6767 endif
6868
69+# Some -march= flags enable MMI instructions, and GCC complains about that
70+# support being enabled alongside -msoft-float. Thus explicitly disable MMI.
71+cflags-y += $(call cc-option,-mno-loongson-mmi)
72+
6973 #
7074 # Loongson Machines' Support
7175 #
arch/mips/mm/tlbex.c+15−8
@@ -653,6 +653,13 @@ static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, · 652 unmodified lines
653653 int restore_scratch)
654654 {
655655 if (restore_scratch) {
656+ /*
657+ * Ensure the MFC0 below observes the value written to the
658+ * KScratch register by the prior MTC0.
659+ */
660+ if (scratch_reg >= 0)
661+ uasm_i_ehb(p);
662+
656663 /* Reset default page size */
657664 if (PM_DEFAULT_MASK >> 16) {
658665 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
@@ -667,12 +674,10 @@ static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, · 8 unmodified lines
667674 uasm_i_mtc0(p, 0, C0_PAGEMASK);
668675 uasm_il_b(p, r, lid);
669676 }
670− if (scratch_reg >= 0) {
671− uasm_i_ehb(p);
677+ if (scratch_reg >= 0)
672678 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
673− } else {
679+ else
674680 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
675− }
676681 } else {
677682 /* Reset default page size */
678683 if (PM_DEFAULT_MASK >> 16) {
@@ -921,6 +926,10 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, · 242 unmodified lines
921926 }
922927 if (mode != not_refill && check_for_high_segbits) {
923928 uasm_l_large_segbits_fault(l, *p);
929+
930+ if (mode == refill_scratch && scratch_reg >= 0)
931+ uasm_i_ehb(p);
932+
924933 /*
925934 * We get here if we are an xsseg address, or if we are
926935 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
@@ -939,12 +948,10 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, · 12 unmodified lines
939948 uasm_i_jr(p, ptr);
940949
941950 if (mode == refill_scratch) {
942− if (scratch_reg >= 0) {
943− uasm_i_ehb(p);
951+ if (scratch_reg >= 0)
944952 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
945− } else {
953+ else
946954 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
947− }
948955 } else {
949956 uasm_i_nop(p);
950957 }
arch/mips/vdso/Makefile+1−0
@@ -15,6 +15,7 @@ ccflags-vdso := \ · 14 unmodified lines
1515 $(filter -mmicromips,$(KBUILD_CFLAGS)) \
1616 $(filter -march=%,$(KBUILD_CFLAGS)) \
1717 $(filter -m%-float,$(KBUILD_CFLAGS)) \
18+ $(filter -mno-loongson-%,$(KBUILD_CFLAGS)) \
1819 -D__VDSO__
1920
2021 ifdef CONFIG_CC_IS_CLANG
arch/parisc/include/asm/cache.h+1−1
@@ -22,7 +22,7 @@ · 21 unmodified lines
2222
2323 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
2424
25−#define __read_mostly __attribute__((__section__(".data..read_mostly")))
25+#define __read_mostly __section(.data..read_mostly)
2626
2727 void parisc_cache_init(void); /* initializes cache-flushing */
2828 void disable_sr_hashing_asm(int); /* low level support for above */
arch/parisc/include/asm/ldcw.h+1−1
@@ -52,7 +52,7 @@ · 51 unmodified lines
5252 })
5353
5454 #ifdef CONFIG_SMP
55−# define __lock_aligned __attribute__((__section__(".data..lock_aligned")))
55+# define __lock_aligned __section(.data..lock_aligned)
5656 #endif
5757
5858 #endif /* __PARISC_LDCW_H */
arch/parisc/kernel/entry.S+1−1
@@ -2125,7 +2125,7 @@ ftrace_regs_caller: · 2124 unmodified lines
21252125 copy %rp, %r26
21262126 LDREG -FTRACE_FRAME_SIZE-PT_SZ_ALGN(%sp), %r25
21272127 ldo -8(%r25), %r25
2128− copy %r3, %arg2
2128+ ldo -FTRACE_FRAME_SIZE(%r1), %arg2
21292129 b,l ftrace_function_trampoline, %rp
21302130 copy %r1, %arg3 /* struct pt_regs */
21312131
arch/parisc/mm/ioremap.c+7−5
@@ -3,7 +3,7 @@ · 2 unmodified lines
33 * arch/parisc/mm/ioremap.c
44 *
55 * (C) Copyright 1995 1996 Linus Torvalds
6− * (C) Copyright 2001-2006 Helge Deller <deller@gmx.de>
6+ * (C) Copyright 2001-2019 Helge Deller <deller@gmx.de>
77 * (C) Copyright 2005 Kyle McMartin <kyle@parisc-linux.org>
88 */
99
@@ -84,7 +84,7 @@ void __iomem * __ioremap(unsigned long phys_addr, unsigned long size, unsigned l · 74 unmodified lines
8484 addr = (void __iomem *) area->addr;
8585 if (ioremap_page_range((unsigned long)addr, (unsigned long)addr + size,
8686 phys_addr, pgprot)) {
87− vfree(addr);
87+ vunmap(addr);
8888 return NULL;
8989 }
9090
@@ -92,9 +92,11 @@ void __iomem * __ioremap(unsigned long phys_addr, unsigned long size, unsigned l · 1 unmodified line
9292 }
9393 EXPORT_SYMBOL(__ioremap);
9494
95−void iounmap(const volatile void __iomem *addr)
95+void iounmap(const volatile void __iomem *io_addr)
9696 {
97− if (addr > high_memory)
98− return vfree((void *) (PAGE_MASK & (unsigned long __force) addr));
97+ unsigned long addr = (unsigned long)io_addr & PAGE_MASK;
98+
99+ if (is_vmalloc_addr((void *)addr))
100+ vunmap((void *)addr);
99101 }
100102 EXPORT_SYMBOL(iounmap);
arch/powerpc/include/asm/book3s/32/kup.h+1−0
@@ -91,6 +91,7 @@ · 90 unmodified lines
9191
9292 static inline void kuap_update_sr(u32 sr, u32 addr, u32 end)
9393 {
94+ addr &= 0xf0000000; /* align addr to start of segment */
9495 barrier(); /* make sure thread.kuap is updated before playing with SRs */
9596 while (addr < end) {
9697 mtsrin(sr, addr);
arch/powerpc/include/asm/book3s/64/tlbflush-radix.h+4−0
@@ -35,6 +35,10 @@ static inline void radix__flush_all_lpid(unsigned int lpid) · 34 unmodified lines
3535 {
3636 WARN_ON(1);
3737 }
38+static inline void radix__flush_all_lpid_guest(unsigned int lpid)
39+{
40+ WARN_ON(1);
41+}
3842 #endif
3943
4044 extern void radix__flush_hugetlb_tlb_range(struct vm_area_struct *vma,
arch/powerpc/include/asm/elf.h+3−0
@@ -175,4 +175,7 @@ do { \ · 174 unmodified lines
175175 ARCH_DLINFO_CACHE_GEOMETRY; \
176176 } while (0)
177177
178+/* Relocate the kernel image to @final_address */
179+void relocate(unsigned long final_address);
180+
178181 #endif /* _ASM_POWERPC_ELF_H */
arch/powerpc/kernel/prom_init.c+13−0
@@ -3249,7 +3249,20 @@ static void setup_secure_guest(unsigned long kbase, unsigned long fdt) · 3248 unmodified lines
32493249 /* Switch to secure mode. */
32503250 prom_printf("Switching to secure mode.\n");
32513251
3252+ /*
3253+ * The ultravisor will do an integrity check of the kernel image but we
3254+ * relocated it so the check will fail. Restore the original image by
3255+ * relocating it back to the kernel virtual base address.
3256+ */
3257+ if (IS_ENABLED(CONFIG_RELOCATABLE))
3258+ relocate(KERNELBASE);
3259+
32523260 ret = enter_secure_mode(kbase, fdt);
3261+
3262+ /* Relocate the kernel again. */
3263+ if (IS_ENABLED(CONFIG_RELOCATABLE))
3264+ relocate(kbase);
3265+
32533266 if (ret != U_SUCCESS) {
32543267 prom_printf("Returned %d from switching to secure mode.\n", ret);
32553268 prom_rtas_os_term("Switch to secure mode failed.\n");
arch/powerpc/kernel/prom_init_check.sh+2−1
@@ -26,7 +26,8 @@ _end enter_prom $MEM_FUNCS reloc_offset __secondary_hold · 25 unmodified lines
2626 __secondary_hold_acknowledge __secondary_hold_spinloop __start
2727 logo_linux_clut224 btext_prepare_BAT
2828 reloc_got2 kernstart_addr memstart_addr linux_banner _stext
29−__prom_init_toc_start __prom_init_toc_end btext_setup_display TOC."
29+__prom_init_toc_start __prom_init_toc_end btext_setup_display TOC.
30+relocate"
3031
3132 NM="$1"
3233 OBJ="$2"
arch/powerpc/kvm/book3s_hv_rmhandlers.S+1−0
@@ -1921,6 +1921,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) · 1920 unmodified lines
19211921 mtspr SPRN_PCR, r6
19221922 18:
19231923 /* Signal secondary CPUs to continue */
1924+ li r0, 0
19241925 stb r0,VCORE_IN_GUEST(r5)
19251926 19: lis r8,0x7fff /* MAX_INT@h */
19261927 mtspr SPRN_HDEC,r8
arch/powerpc/kvm/book3s_xive.c+16−8
@@ -1217,6 +1217,7 @@ int kvmppc_xive_connect_vcpu(struct kvm_device *dev, · 1216 unmodified lines
12171217 struct kvmppc_xive *xive = dev->private;
12181218 struct kvmppc_xive_vcpu *xc;
12191219 int i, r = -EBUSY;
1220+ u32 vp_id;
12201221
12211222 pr_devel("connect_vcpu(cpu=%d)\n", cpu);
12221223
@@ -1228,25 +1229,32 @@ int kvmppc_xive_connect_vcpu(struct kvm_device *dev, · 5 unmodified lines
12281229 return -EPERM;
12291230 if (vcpu->arch.irq_type != KVMPPC_IRQ_DEFAULT)
12301231 return -EBUSY;
1231− if (kvmppc_xive_find_server(vcpu->kvm, cpu)) {
1232− pr_devel("Duplicate !\n");
1233− return -EEXIST;
1234− }
12351232 if (cpu >= (KVM_MAX_VCPUS * vcpu->kvm->arch.emul_smt_mode)) {
12361233 pr_devel("Out of bounds !\n");
12371234 return -EINVAL;
12381235 }
1239− xc = kzalloc(sizeof(*xc), GFP_KERNEL);
1240− if (!xc)
1241− return -ENOMEM;
12421236
12431237 /* We need to synchronize with queue provisioning */
12441238 mutex_lock(&xive->lock);
1239+
1240+ vp_id = kvmppc_xive_vp(xive, cpu);
1241+ if (kvmppc_xive_vp_in_use(xive->kvm, vp_id)) {
1242+ pr_devel("Duplicate !\n");
1243+ r = -EEXIST;
1244+ goto bail;
1245+ }
1246+
1247+ xc = kzalloc(sizeof(*xc), GFP_KERNEL);
1248+ if (!xc) {
1249+ r = -ENOMEM;
1250+ goto bail;
1251+ }
1252+
12451253 vcpu->arch.xive_vcpu = xc;
12461254 xc->xive = xive;
12471255 xc->vcpu = vcpu;
12481256 xc->server_num = cpu;
1249− xc->vp_id = kvmppc_xive_vp(xive, cpu);
1257+ xc->vp_id = vp_id;
12501258 xc->mfrr = 0xff;
12511259 xc->valid = true;
12521260
arch/powerpc/kvm/book3s_xive.h+12−0
@@ -220,6 +220,18 @@ static inline u32 kvmppc_xive_vp(struct kvmppc_xive *xive, u32 server) · 219 unmodified lines
220220 return xive->vp_base + kvmppc_pack_vcpu_id(xive->kvm, server);
221221 }
222222
223+static inline bool kvmppc_xive_vp_in_use(struct kvm *kvm, u32 vp_id)
224+{
225+ struct kvm_vcpu *vcpu = NULL;
226+ int i;
227+
228+ kvm_for_each_vcpu(i, vcpu, kvm) {
229+ if (vcpu->arch.xive_vcpu && vp_id == vcpu->arch.xive_vcpu->vp_id)
230+ return true;
231+ }
232+ return false;
233+}
234+
223235 /*
224236 * Mapping between guest priorities and host priorities
225237 * is as follow.
arch/powerpc/kvm/book3s_xive_native.c+4−2
@@ -106,6 +106,7 @@ int kvmppc_xive_native_connect_vcpu(struct kvm_device *dev, · 105 unmodified lines
106106 struct kvmppc_xive *xive = dev->private;
107107 struct kvmppc_xive_vcpu *xc = NULL;
108108 int rc;
109+ u32 vp_id;
109110
110111 pr_devel("native_connect_vcpu(server=%d)\n", server_num);
111112
@@ -124,7 +125,8 @@ int kvmppc_xive_native_connect_vcpu(struct kvm_device *dev, · 12 unmodified lines
124125
125126 mutex_lock(&xive->lock);
126127
127− if (kvmppc_xive_find_server(vcpu->kvm, server_num)) {
128+ vp_id = kvmppc_xive_vp(xive, server_num);
129+ if (kvmppc_xive_vp_in_use(xive->kvm, vp_id)) {
128130 pr_devel("Duplicate !\n");
129131 rc = -EEXIST;
130132 goto bail;
@@ -141,7 +143,7 @@ int kvmppc_xive_native_connect_vcpu(struct kvm_device *dev, · 10 unmodified lines
141143 xc->vcpu = vcpu;
142144 xc->server_num = server_num;
143145
144− xc->vp_id = kvmppc_xive_vp(xive, server_num);
146+ xc->vp_id = vp_id;
145147 xc->valid = true;
146148 vcpu->arch.irq_type = KVMPPC_IRQ_XIVE;
147149
arch/powerpc/net/bpf_jit_comp64.c+13−0
@@ -1141,6 +1141,19 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp) · 1140 unmodified lines
11411141 goto out_addrs;
11421142 }
11431143
1144+ /*
1145+ * If we have seen a tail call, we need a second pass.
1146+ * This is because bpf_jit_emit_common_epilogue() is called
1147+ * from bpf_jit_emit_tail_call() with a not yet stable ctx->seen.
1148+ */
1149+ if (cgctx.seen & SEEN_TAILCALL) {
1150+ cgctx.idx = 0;
1151+ if (bpf_jit_build_body(fp, 0, &cgctx, addrs, false)) {
1152+ fp = org_fp;
1153+ goto out_addrs;
1154+ }
1155+ }
1156+
11441157 /*
11451158 * Pretend to build prologue, given the features we've seen. This will
11461159 * update ctgtx.idx as it pretends to output instructions, then we can
arch/powerpc/platforms/cell/spufs/inode.c+1−0
@@ -761,6 +761,7 @@ static int spufs_init_fs_context(struct fs_context *fc) · 760 unmodified lines
761761 ctx->gid = current_gid();
762762 ctx->mode = 0755;
763763
764+ fc->fs_private = ctx;
764765 fc->s_fs_info = sbi;
765766 fc->ops = &spufs_context_ops;
766767 return 0;
arch/powerpc/platforms/powernv/eeh-powernv.c+1−1
@@ -42,7 +42,7 @@ void pnv_pcibios_bus_add_device(struct pci_dev *pdev) · 41 unmodified lines
4242 {
4343 struct pci_dn *pdn = pci_get_pdn(pdev);
4444
45− if (eeh_has_flag(EEH_FORCE_DISABLED))
45+ if (!pdn || eeh_has_flag(EEH_FORCE_DISABLED))
4646 return;
4747
4848 dev_dbg(&pdev->dev, "EEH: Setting up device\n");
arch/powerpc/platforms/powernv/smp.c+37−16
@@ -146,20 +146,25 @@ static int pnv_smp_cpu_disable(void) · 145 unmodified lines
146146 return 0;
147147 }
148148
149+static void pnv_flush_interrupts(void)
150+{
151+ if (cpu_has_feature(CPU_FTR_ARCH_300)) {
152+ if (xive_enabled())
153+ xive_flush_interrupt();
154+ else
155+ icp_opal_flush_interrupt();
156+ } else {
157+ icp_native_flush_interrupt();
158+ }
159+}
160+
149161 static void pnv_smp_cpu_kill_self(void)
150162 {
163+ unsigned long srr1, unexpected_mask, wmask;
151164 unsigned int cpu;
152− unsigned long srr1, wmask;
153165 u64 lpcr_val;
154166
155167 /* Standard hot unplug procedure */
156− /*
157− * This hard disables local interurpts, ensuring we have no lazy
158− * irqs pending.
159− */
160− WARN_ON(irqs_disabled());
161− hard_irq_disable();
162− WARN_ON(lazy_irq_pending());
163168
164169 idle_task_exit();
165170 current->active_mm = NULL; /* for sanity */
@@ -172,6 +177,27 @@ static void pnv_smp_cpu_kill_self(void) · 6 unmodified lines
172177 if (cpu_has_feature(CPU_FTR_ARCH_207S))
173178 wmask = SRR1_WAKEMASK_P8;
174179
180+ /*
181+ * This turns the irq soft-disabled state we're called with, into a
182+ * hard-disabled state with pending irq_happened interrupts cleared.
183+ *
184+ * PACA_IRQ_DEC - Decrementer should be ignored.
185+ * PACA_IRQ_HMI - Can be ignored, processing is done in real mode.
186+ * PACA_IRQ_DBELL, EE, PMI - Unexpected.
187+ */
188+ hard_irq_disable();
189+ if (generic_check_cpu_restart(cpu))
190+ goto out;
191+
192+ unexpected_mask = ~(PACA_IRQ_DEC | PACA_IRQ_HMI | PACA_IRQ_HARD_DIS);
193+ if (local_paca->irq_happened & unexpected_mask) {
194+ if (local_paca->irq_happened & PACA_IRQ_EE)
195+ pnv_flush_interrupts();
196+ DBG("CPU%d Unexpected exit while offline irq_happened=%lx!\n",
197+ cpu, local_paca->irq_happened);
198+ }
199+ local_paca->irq_happened = PACA_IRQ_HARD_DIS;
200+
175201 /*
176202 * We don't want to take decrementer interrupts while we are
177203 * offline, so clear LPCR:PECE1. We keep PECE2 (and
@@ -197,6 +223,7 @@ static void pnv_smp_cpu_kill_self(void) · 19 unmodified lines
197223
198224 srr1 = pnv_cpu_offline(cpu);
199225
226+ WARN_ON_ONCE(!irqs_disabled());
200227 WARN_ON(lazy_irq_pending());
201228
202229 /*
@@ -212,13 +239,7 @@ static void pnv_smp_cpu_kill_self(void) · 9 unmodified lines
212239 */
213240 if (((srr1 & wmask) == SRR1_WAKEEE) ||
214241 ((srr1 & wmask) == SRR1_WAKEHVI)) {
215− if (cpu_has_feature(CPU_FTR_ARCH_300)) {
216− if (xive_enabled())
217− xive_flush_interrupt();
218− else
219− icp_opal_flush_interrupt();
220− } else
221− icp_native_flush_interrupt();
242+ pnv_flush_interrupts();
222243 } else if ((srr1 & wmask) == SRR1_WAKEHDBELL) {
223244 unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER);
224245 asm volatile(PPC_MSGCLR(%0) : : "r" (msg));
@@ -266,7 +287,7 @@ static void pnv_smp_cpu_kill_self(void) · 41 unmodified lines
266287 */
267288 lpcr_val = mfspr(SPRN_LPCR) | (u64)LPCR_PECE1;
268289 pnv_program_cpu_hotplug_lpcr(cpu, lpcr_val);
269−
290+out:
270291 DBG("CPU%d coming online...\n", cpu);
271292 }
272293
arch/powerpc/platforms/pseries/lpar.c+3−0
@@ -1419,6 +1419,9 @@ void __init pseries_lpar_read_hblkrm_characteristics(void) · 1418 unmodified lines
14191419 unsigned char local_buffer[SPLPAR_TLB_BIC_MAXLENGTH];
14201420 int call_status, len, idx, bpsize;
14211421
1422+ if (!firmware_has_feature(FW_FEATURE_BLOCK_REMOVE))
1423+ return;
1424+
14221425 spin_lock(&rtas_data_buf_lock);
14231426 memset(rtas_data_buf, 0, RTAS_DATA_BUF_SIZE);
14241427 call_status = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1,
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts+1−0
@@ -13,6 +13,7 @@ · 12 unmodified lines
1313 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
1414
1515 chosen {
16+ stdout-path = "serial0";
1617 };
1718
1819 cpus {
arch/riscv/include/asm/bug.h+3−13
@@ -12,7 +12,6 @@ · 11 unmodified lines
1212
1313 #include <asm/asm.h>
1414
15−#ifdef CONFIG_GENERIC_BUG
1615 #define __INSN_LENGTH_MASK _UL(0x3)
1716 #define __INSN_LENGTH_32 _UL(0x3)
1817 #define __COMPRESSED_INSN_MASK _UL(0xffff)
@@ -20,7 +19,6 @@ · 1 unmodified line
2019 #define __BUG_INSN_32 _UL(0x00100073) /* ebreak */
2120 #define __BUG_INSN_16 _UL(0x9002) /* c.ebreak */
2221
23−#ifndef __ASSEMBLY__
2422 typedef u32 bug_insn_t;
2523
2624 #ifdef CONFIG_GENERIC_BUG_RELATIVE_POINTERS
@@ -43,6 +41,7 @@ typedef u32 bug_insn_t; · 16 unmodified lines
4341 RISCV_SHORT " %2"
4442 #endif
4543
44+#ifdef CONFIG_GENERIC_BUG
4645 #define __BUG_FLAGS(flags) \
4746 do { \
4847 __asm__ __volatile__ ( \
@@ -58,14 +57,10 @@ do { \ · 9 unmodified lines
5857 "i" (flags), \
5958 "i" (sizeof(struct bug_entry))); \
6059 } while (0)
61−
62−#endif /* !__ASSEMBLY__ */
6360 #else /* CONFIG_GENERIC_BUG */
64−#ifndef __ASSEMBLY__
6561 #define __BUG_FLAGS(flags) do { \
6662 __asm__ __volatile__ ("ebreak\n"); \
6763 } while (0)
68−#endif /* !__ASSEMBLY__ */
6964 #endif /* CONFIG_GENERIC_BUG */
7065
7166 #define BUG() do { \
@@ -79,15 +74,10 @@ do { \ · 7 unmodified lines
7974
8075 #include <asm-generic/bug.h>
8176
82−#ifndef __ASSEMBLY__
83−
8477 struct pt_regs;
8578 struct task_struct;
8679
87−extern void die(struct pt_regs *regs, const char *str);
88−extern void do_trap(struct pt_regs *regs, int signo, int code,
89− unsigned long addr);
90−
91−#endif /* !__ASSEMBLY__ */
80+void die(struct pt_regs *regs, const char *str);
81+void do_trap(struct pt_regs *regs, int signo, int code, unsigned long addr);
9282
9383 #endif /* _ASM_RISCV_BUG_H */
arch/riscv/include/asm/io.h+7−0
@@ -13,6 +13,7 @@ · 12 unmodified lines
1313
1414 #include <linux/types.h>
1515 #include <asm/mmiowb.h>
16+#include <asm/pgtable.h>
1617
1718 extern void __iomem *ioremap(phys_addr_t offset, unsigned long size);
1819
@@ -161,6 +162,12 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) · 142 unmodified lines
161162 #define writeq(v,c) ({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); })
162163 #endif
163164
165+/*
166+ * I/O port access constants.
167+ */
168+#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
169+#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
170+
164171 /*
165172 * Emulation routines for the port-mapped IO space used by some PCI drivers.
166173 * These are defined as being "fully synchronous", but also "not guaranteed to
arch/riscv/include/asm/irq.h+3−0
@@ -7,6 +7,9 @@ · 6 unmodified lines
77 #ifndef _ASM_RISCV_IRQ_H
88 #define _ASM_RISCV_IRQ_H
99
10+#include <linux/interrupt.h>
11+#include <linux/linkage.h>
12+
1013 #define NR_IRQS 0
1114
1215 void riscv_timer_interrupt(void);
arch/riscv/include/asm/pgtable.h+14−14
@@ -7,6 +7,7 @@ · 6 unmodified lines
77 #define _ASM_RISCV_PGTABLE_H
88
99 #include <linux/mmzone.h>
10+#include <linux/sizes.h>
1011
1112 #include <asm/pgtable-bits.h>
1213
@@ -86,14 +87,7 @@ extern pgd_t swapper_pg_dir[]; · 73 unmodified lines
8687 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1)
8788 #define VMALLOC_END (PAGE_OFFSET - 1)
8889 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE)
89−
90−#define FIXADDR_TOP VMALLOC_START
91−#ifdef CONFIG_64BIT
92−#define FIXADDR_SIZE PMD_SIZE
93−#else
94−#define FIXADDR_SIZE PGDIR_SIZE
95−#endif
96−#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
90+#define PCI_IO_SIZE SZ_16M
9791
9892 /*
9993 * Roughly size the vmemmap space to be large enough to fit enough
@@ -108,6 +102,17 @@ extern pgd_t swapper_pg_dir[]; · 8 unmodified lines
108102
109103 #define vmemmap ((struct page *)VMEMMAP_START)
110104
105+#define PCI_IO_END VMEMMAP_START
106+#define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE)
107+#define FIXADDR_TOP PCI_IO_START
108+
109+#ifdef CONFIG_64BIT
110+#define FIXADDR_SIZE PMD_SIZE
111+#else
112+#define FIXADDR_SIZE PGDIR_SIZE
113+#endif
114+#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
115+
111116 /*
112117 * ZERO_PAGE is a global shared page that is always zero,
113118 * used for zero-mapped memory areas, etc.
@@ -184,10 +189,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) · 70 unmodified lines
184189 return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
185190 }
186191
187−static inline pte_t mk_pte(struct page *page, pgprot_t prot)
188−{
189− return pfn_pte(page_to_pfn(page), prot);
190−}
192+#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
191193
192194 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
193195
@@ -428,9 +430,7 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, · 234 unmodified lines
428430 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
429431 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
430432
431−#ifdef CONFIG_FLATMEM
432433 #define kern_addr_valid(addr) (1) /* FIXME */
433−#endif
434434
435435 extern void *dtb_early_va;
436436 extern void setup_bootmem(void);
arch/riscv/include/asm/switch_to.h+1−0
@@ -6,6 +6,7 @@ · 5 unmodified lines
66 #ifndef _ASM_RISCV_SWITCH_TO_H
77 #define _ASM_RISCV_SWITCH_TO_H
88
9+#include <linux/sched/task_stack.h>
910 #include <asm/processor.h>
1011 #include <asm/ptrace.h>
1112 #include <asm/csr.h>
arch/riscv/include/asm/tlbflush.h+0−4
@@ -10,10 +10,6 @@ · 9 unmodified lines
1010 #include <linux/mm_types.h>
1111 #include <asm/smp.h>
1212
13−/*
14− * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction
15− * cache as well, so a 'fence.i' is not necessary.
16− */
1713 static inline void local_flush_tlb_all(void)
1814 {
1915 __asm__ __volatile__ ("sfence.vma" : : : "memory");
arch/riscv/kernel/cpufeature.c+1−0
@@ -10,6 +10,7 @@ · 9 unmodified lines
1010 #include <asm/processor.h>
1111 #include <asm/hwcap.h>
1212 #include <asm/smp.h>
13+#include <asm/switch_to.h>
1314
1415 unsigned long elf_hwcap __read_mostly;
1516 #ifdef CONFIG_FPU
arch/riscv/kernel/entry.S+1−2
@@ -273,12 +273,11 @@ restore_all: · 272 unmodified lines
273273 resume_kernel:
274274 REG_L s0, TASK_TI_PREEMPT_COUNT(tp)
275275 bnez s0, restore_all
276−need_resched:
277276 REG_L s0, TASK_TI_FLAGS(tp)
278277 andi s0, s0, _TIF_NEED_RESCHED
279278 beqz s0, restore_all
280279 call preempt_schedule_irq
281− j need_resched
280+ j restore_all
282281 #endif
283282
284283 work_pending:
arch/riscv/kernel/head.h+21−0
@@ -0,0 +1,21 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (C) 2019 SiFive, Inc.
4+ */
5+#ifndef __ASM_HEAD_H
6+#define __ASM_HEAD_H
7+
8+#include <linux/linkage.h>
9+#include <linux/init.h>
10+
11+extern atomic_t hart_lottery;
12+
13+asmlinkage void do_page_fault(struct pt_regs *regs);
14+asmlinkage void __init setup_vm(uintptr_t dtb_pa);
15+
16+extern void *__cpu_up_stack_pointer[];
17+extern void *__cpu_up_task_pointer[];
18+
19+void __init parse_dtb(void);
20+
21+#endif /* __ASM_HEAD_H */
arch/riscv/kernel/irq.c+1−1
@@ -24,7 +24,7 @@ int arch_show_interrupts(struct seq_file *p, int prec) · 23 unmodified lines
2424 return 0;
2525 }
2626
27−asmlinkage void __irq_entry do_IRQ(struct pt_regs *regs)
27+asmlinkage __visible void __irq_entry do_IRQ(struct pt_regs *regs)
2828 {
2929 struct pt_regs *old_regs = set_irq_regs(regs);
3030
arch/riscv/kernel/module-sections.c+1−0
@@ -8,6 +8,7 @@ · 7 unmodified lines
88 #include <linux/elf.h>
99 #include <linux/kernel.h>
1010 #include <linux/module.h>
11+#include <linux/moduleloader.h>
1112
1213 unsigned long module_emit_got_entry(struct module *mod, unsigned long val)
1314 {
arch/riscv/kernel/process.c+2−0
@@ -7,6 +7,7 @@ · 6 unmodified lines
77 * Copyright (C) 2017 SiFive
88 */
99
10+#include <linux/cpu.h>
1011 #include <linux/kernel.h>
1112 #include <linux/sched.h>
1213 #include <linux/sched/task_stack.h>
@@ -19,6 +20,7 @@ · 6 unmodified lines
1920 #include <asm/csr.h>
2021 #include <asm/string.h>
2122 #include <asm/switch_to.h>
23+#include <asm/thread_info.h>
2224
2325 extern asmlinkage void ret_from_fork(void);
2426 extern asmlinkage void ret_from_kernel_thread(void);
arch/riscv/kernel/ptrace.c+2−2
@@ -148,7 +148,7 @@ long arch_ptrace(struct task_struct *child, long request, · 147 unmodified lines
148148 * Allows PTRACE_SYSCALL to work. These are called from entry.S in
149149 * {handle,ret_from}_syscall.
150150 */
151−void do_syscall_trace_enter(struct pt_regs *regs)
151+__visible void do_syscall_trace_enter(struct pt_regs *regs)
152152 {
153153 if (test_thread_flag(TIF_SYSCALL_TRACE))
154154 if (tracehook_report_syscall_entry(regs))
@@ -162,7 +162,7 @@ void do_syscall_trace_enter(struct pt_regs *regs) · 7 unmodified lines
162162 audit_syscall_entry(regs->a7, regs->a0, regs->a1, regs->a2, regs->a3);
163163 }
164164
165−void do_syscall_trace_exit(struct pt_regs *regs)
165+__visible void do_syscall_trace_exit(struct pt_regs *regs)
166166 {
167167 audit_syscall_exit(regs);
168168
arch/riscv/kernel/reset.c+1−0
@@ -4,6 +4,7 @@ · 3 unmodified lines
44 */
55
66 #include <linux/reboot.h>
7+#include <linux/pm.h>
78 #include <asm/sbi.h>
89
910 static void default_power_off(void)
arch/riscv/kernel/setup.c+2−0
@@ -24,6 +24,8 @@ · 23 unmodified lines
2424 #include <asm/tlbflush.h>
2525 #include <asm/thread_info.h>
2626
27+#include "head.h"
28+
2729 #ifdef CONFIG_DUMMY_CONSOLE
2830 struct screen_info screen_info = {
2931 .orig_video_lines = 30,
arch/riscv/kernel/signal.c+4−4
@@ -26,7 +26,7 @@ struct rt_sigframe { · 25 unmodified lines
2626
2727 #ifdef CONFIG_FPU
2828 static long restore_fp_state(struct pt_regs *regs,
29− union __riscv_fp_state *sc_fpregs)
29+ union __riscv_fp_state __user *sc_fpregs)
3030 {
3131 long err;
3232 struct __riscv_d_ext_state __user *state = &sc_fpregs->d;
@@ -53,7 +53,7 @@ static long restore_fp_state(struct pt_regs *regs, · 20 unmodified lines
5353 }
5454
5555 static long save_fp_state(struct pt_regs *regs,
56− union __riscv_fp_state *sc_fpregs)
56+ union __riscv_fp_state __user *sc_fpregs)
5757 {
5858 long err;
5959 struct __riscv_d_ext_state __user *state = &sc_fpregs->d;
@@ -292,8 +292,8 @@ static void do_signal(struct pt_regs *regs) · 232 unmodified lines
292292 * notification of userspace execution resumption
293293 * - triggered by the _TIF_WORK_MASK flags
294294 */
295−asmlinkage void do_notify_resume(struct pt_regs *regs,
296− unsigned long thread_info_flags)
295+asmlinkage __visible void do_notify_resume(struct pt_regs *regs,
296+ unsigned long thread_info_flags)
297297 {
298298 /* Handle pending signal delivery */
299299 if (thread_info_flags & _TIF_SIGPENDING)
arch/riscv/kernel/smp.c+2−0
@@ -8,7 +8,9 @@ · 7 unmodified lines
88 * Copyright (C) 2017 SiFive
99 */
1010
11+#include <linux/cpu.h>
1112 #include <linux/interrupt.h>
13+#include <linux/profile.h>
1214 #include <linux/smp.h>
1315 #include <linux/sched.h>
1416 #include <linux/seq_file.h>
arch/riscv/kernel/smpboot.c+4−1
@@ -29,6 +29,9 @@ · 28 unmodified lines
2929 #include <asm/tlbflush.h>
3030 #include <asm/sections.h>
3131 #include <asm/sbi.h>
32+#include <asm/smp.h>
33+
34+#include "head.h"
3235
3336 void *__cpu_up_stack_pointer[NR_CPUS];
3437 void *__cpu_up_task_pointer[NR_CPUS];
@@ -130,7 +133,7 @@ void __init smp_cpus_done(unsigned int max_cpus) · 95 unmodified lines
130133 /*
131134 * C entry point for a secondary processor.
132135 */
133−asmlinkage void __init smp_callin(void)
136+asmlinkage __visible void __init smp_callin(void)
134137 {
135138 struct mm_struct *mm = &init_mm;
136139
arch/riscv/kernel/syscall_table.c+1−0
@@ -8,6 +8,7 @@ · 7 unmodified lines
88 #include <linux/syscalls.h>
99 #include <asm-generic/syscalls.h>
1010 #include <asm/vdso.h>
11+#include <asm/syscall.h>
1112
1213 #undef __SYSCALL
1314 #define __SYSCALL(nr, call) [nr] = (call),
arch/riscv/kernel/time.c+1−0
@@ -7,6 +7,7 @@ · 6 unmodified lines
77 #include <linux/clocksource.h>
88 #include <linux/delay.h>
99 #include <asm/sbi.h>
10+#include <asm/processor.h>
1011
1112 unsigned long riscv_timebase;
1213 EXPORT_SYMBOL_GPL(riscv_timebase);
arch/riscv/kernel/traps.c+9−22
@@ -3,6 +3,7 @@ · 2 unmodified lines
33 * Copyright (C) 2012 Regents of the University of California
44 */
55
6+#include <linux/cpu.h>
67 #include <linux/kernel.h>
78 #include <linux/init.h>
89 #include <linux/sched.h>
@@ -83,7 +84,7 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code, · 74 unmodified lines
8384 }
8485
8586 #define DO_ERROR_INFO(name, signo, code, str) \
86−asmlinkage void name(struct pt_regs *regs) \
87+asmlinkage __visible void name(struct pt_regs *regs) \
8788 { \
8889 do_trap_error(regs, signo, code, regs->sepc, "Oops - " str); \
8990 }
@@ -111,7 +112,6 @@ DO_ERROR_INFO(do_trap_ecall_s, · 21 unmodified lines
111112 DO_ERROR_INFO(do_trap_ecall_m,
112113 SIGILL, ILL_ILLTRP, "environment call from M-mode");
113114
114−#ifdef CONFIG_GENERIC_BUG
115115 static inline unsigned long get_break_insn_length(unsigned long pc)
116116 {
117117 bug_insn_t insn;
@@ -120,28 +120,15 @@ static inline unsigned long get_break_insn_length(unsigned long pc) · 2 unmodified lines
120120 return 0;
121121 return (((insn & __INSN_LENGTH_MASK) == __INSN_LENGTH_32) ? 4UL : 2UL);
122122 }
123−#endif /* CONFIG_GENERIC_BUG */
124123
125−asmlinkage void do_trap_break(struct pt_regs *regs)
124+asmlinkage __visible void do_trap_break(struct pt_regs *regs)
126125 {
127−#ifdef CONFIG_GENERIC_BUG
128− if (!user_mode(regs)) {
129− enum bug_trap_type type;
130−
131− type = report_bug(regs->sepc, regs);
132− switch (type) {
133− case BUG_TRAP_TYPE_NONE:
134− break;
135− case BUG_TRAP_TYPE_WARN:
136− regs->sepc += get_break_insn_length(regs->sepc);
137− break;
138− case BUG_TRAP_TYPE_BUG:
139− die(regs, "Kernel BUG");
140− }
141− }
142−#endif /* CONFIG_GENERIC_BUG */
143−
144− force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)(regs->sepc));
126+ if (user_mode(regs))
127+ force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->sepc);
128+ else if (report_bug(regs->sepc, regs) == BUG_TRAP_TYPE_WARN)
129+ regs->sepc += get_break_insn_length(regs->sepc);
130+ else
131+ die(regs, "Kernel BUG");
145132 }
146133
147134 #ifdef CONFIG_GENERIC_BUG
arch/riscv/kernel/vdso.c+2−1
@@ -6,6 +6,7 @@ · 5 unmodified lines
66 * Copyright (C) 2015 Regents of the University of California
77 */
88
9+#include <linux/elf.h>
910 #include <linux/mm.h>
1011 #include <linux/slab.h>
1112 #include <linux/binfmts.h>
@@ -25,7 +26,7 @@ static union { · 13 unmodified lines
2526 struct vdso_data data;
2627 u8 page[PAGE_SIZE];
2728 } vdso_data_store __page_aligned_data;
28−struct vdso_data *vdso_data = &vdso_data_store.data;
29+static struct vdso_data *vdso_data = &vdso_data_store.data;
2930
3031 static int __init vdso_init(void)
3132 {
arch/riscv/mm/context.c+1−0
@@ -7,6 +7,7 @@ · 6 unmodified lines
77 #include <linux/mm.h>
88 #include <asm/tlbflush.h>
99 #include <asm/cacheflush.h>
10+#include <asm/mmu_context.h>
1011
1112 /*
1213 * When necessary, performs a deferred icache flush for the given MM context,
arch/riscv/mm/fault.c+2−0
@@ -18,6 +18,8 @@ · 17 unmodified lines
1818 #include <asm/ptrace.h>
1919 #include <asm/tlbflush.h>
2020
21+#include "../kernel/head.h"
22+
2123 /*
2224 * This routine handles page faults. It determines the address and the
2325 * problem, and then passes it off to one of the appropriate routines.
arch/riscv/mm/init.c+4−3
@@ -19,6 +19,8 @@ · 18 unmodified lines
1919 #include <asm/pgtable.h>
2020 #include <asm/io.h>
2121
22+#include "../kernel/head.h"
23+
2224 unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]
2325 __page_aligned_bss;
2426 EXPORT_SYMBOL(empty_zero_page);
@@ -337,8 +339,7 @@ static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size) · 312 unmodified lines
337339 */
338340
339341 #ifndef __riscv_cmodel_medany
340−#error "setup_vm() is called from head.S before relocate so it should "
341− "not use absolute addressing."
342+#error "setup_vm() is called from head.S before relocate so it should not use absolute addressing."
342343 #endif
343344
344345 asmlinkage void __init setup_vm(uintptr_t dtb_pa)
@@ -458,7 +459,7 @@ void __init paging_init(void) · 113 unmodified lines
458459 zone_sizes_init();
459460 }
460461
461−#ifdef CONFIG_SPARSEMEM
462+#ifdef CONFIG_SPARSEMEM_VMEMMAP
462463 int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node,
463464 struct vmem_altmap *altmap)
464465 {
arch/riscv/mm/sifive_l2_cache.c+1−1
@@ -142,7 +142,7 @@ static irqreturn_t l2_int_handler(int irq, void *device) · 141 unmodified lines
142142 return IRQ_HANDLED;
143143 }
144144
145−int __init sifive_l2_init(void)
145+static int __init sifive_l2_init(void)
146146 {
147147 struct device_node *np;
148148 struct resource res;
arch/s390/boot/startup.c+11−3
@@ -101,10 +101,18 @@ static void handle_relocs(unsigned long offset) · 100 unmodified lines
101101 dynsym = (Elf64_Sym *) vmlinux.dynsym_start;
102102 for (rela = rela_start; rela < rela_end; rela++) {
103103 loc = rela->r_offset + offset;
104− val = rela->r_addend + offset;
104+ val = rela->r_addend;
105105 r_sym = ELF64_R_SYM(rela->r_info);
106− if (r_sym)
107− val += dynsym[r_sym].st_value;
106+ if (r_sym) {
107+ if (dynsym[r_sym].st_shndx != SHN_UNDEF)
108+ val += dynsym[r_sym].st_value + offset;
109+ } else {
110+ /*
111+ * 0 == undefined symbol table index (STN_UNDEF),
112+ * used for R_390_RELATIVE, only add KASLR offset
113+ */
114+ val += offset;
115+ }
108116 r_type = ELF64_R_TYPE(rela->r_info);
109117 rc = arch_kexec_do_relocs(r_type, (void *) loc, val, 0);
110118 if (rc)
arch/s390/include/asm/uaccess.h+2−2
@@ -83,7 +83,7 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n); · 82 unmodified lines
8383 __rc; \
8484 })
8585
86−static inline int __put_user_fn(void *x, void __user *ptr, unsigned long size)
86+static __always_inline int __put_user_fn(void *x, void __user *ptr, unsigned long size)
8787 {
8888 unsigned long spec = 0x010000UL;
8989 int rc;
@@ -113,7 +113,7 @@ static inline int __put_user_fn(void *x, void __user *ptr, unsigned long size) · 23 unmodified lines
113113 return rc;
114114 }
115115
116−static inline int __get_user_fn(void *x, const void __user *ptr, unsigned long size)
116+static __always_inline int __get_user_fn(void *x, const void __user *ptr, unsigned long size)
117117 {
118118 unsigned long spec = 0x01UL;
119119 int rc;
arch/s390/include/asm/unwind.h+1−0
@@ -35,6 +35,7 @@ struct unwind_state { · 34 unmodified lines
3535 struct task_struct *task;
3636 struct pt_regs *regs;
3737 unsigned long sp, ip;
38+ bool reuse_sp;
3839 int graph_idx;
3940 bool reliable;
4041 bool error;
arch/s390/kernel/idle.c+22−7
@@ -69,18 +69,26 @@ DEVICE_ATTR(idle_count, 0444, show_idle_count, NULL); · 68 unmodified lines
6969 static ssize_t show_idle_time(struct device *dev,
7070 struct device_attribute *attr, char *buf)
7171 {
72+ unsigned long long now, idle_time, idle_enter, idle_exit, in_idle;
7273 struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id);
73− unsigned long long now, idle_time, idle_enter, idle_exit;
7474 unsigned int seq;
7575
7676 do {
77− now = get_tod_clock();
7877 seq = read_seqcount_begin(&idle->seqcount);
7978 idle_time = READ_ONCE(idle->idle_time);
8079 idle_enter = READ_ONCE(idle->clock_idle_enter);
8180 idle_exit = READ_ONCE(idle->clock_idle_exit);
8281 } while (read_seqcount_retry(&idle->seqcount, seq));
83− idle_time += idle_enter ? ((idle_exit ? : now) - idle_enter) : 0;
82+ in_idle = 0;
83+ now = get_tod_clock();
84+ if (idle_enter) {
85+ if (idle_exit) {
86+ in_idle = idle_exit - idle_enter;
87+ } else if (now > idle_enter) {
88+ in_idle = now - idle_enter;
89+ }
90+ }
91+ idle_time += in_idle;
8492 return sprintf(buf, "%llu\n", idle_time >> 12);
8593 }
8694 DEVICE_ATTR(idle_time_us, 0444, show_idle_time, NULL);
@@ -88,17 +96,24 @@ DEVICE_ATTR(idle_time_us, 0444, show_idle_time, NULL); · 1 unmodified line
8896 u64 arch_cpu_idle_time(int cpu)
8997 {
9098 struct s390_idle_data *idle = &per_cpu(s390_idle, cpu);
91− unsigned long long now, idle_enter, idle_exit;
99+ unsigned long long now, idle_enter, idle_exit, in_idle;
92100 unsigned int seq;
93101
94102 do {
95− now = get_tod_clock();
96103 seq = read_seqcount_begin(&idle->seqcount);
97104 idle_enter = READ_ONCE(idle->clock_idle_enter);
98105 idle_exit = READ_ONCE(idle->clock_idle_exit);
99106 } while (read_seqcount_retry(&idle->seqcount, seq));
100−
101− return cputime_to_nsecs(idle_enter ? ((idle_exit ?: now) - idle_enter) : 0);
107+ in_idle = 0;
108+ now = get_tod_clock();
109+ if (idle_enter) {
110+ if (idle_exit) {
111+ in_idle = idle_exit - idle_enter;
112+ } else if (now > idle_enter) {
113+ in_idle = now - idle_enter;
114+ }
115+ }
116+ return cputime_to_nsecs(in_idle);
102117 }
103118
104119 void arch_cpu_idle_enter(void)
arch/s390/kernel/machine_kexec_reloc.c+1−0
@@ -27,6 +27,7 @@ int arch_kexec_do_relocs(int r_type, void *loc, unsigned long val, · 26 unmodified lines
2727 *(u32 *)loc = val;
2828 break;
2929 case R_390_64: /* Direct 64 bit. */
30+ case R_390_GLOB_DAT:
3031 *(u64 *)loc = val;
3132 break;
3233 case R_390_PC16: /* PC relative 16 bit. */
arch/s390/kernel/unwind_bc.c+13−5
@@ -46,10 +46,15 @@ bool unwind_next_frame(struct unwind_state *state) · 45 unmodified lines
4646
4747 regs = state->regs;
4848 if (unlikely(regs)) {
49− sp = READ_ONCE_NOCHECK(regs->gprs[15]);
50− if (unlikely(outside_of_stack(state, sp))) {
51− if (!update_stack_info(state, sp))
52− goto out_err;
49+ if (state->reuse_sp) {
50+ sp = state->sp;
51+ state->reuse_sp = false;
52+ } else {
53+ sp = READ_ONCE_NOCHECK(regs->gprs[15]);
54+ if (unlikely(outside_of_stack(state, sp))) {
55+ if (!update_stack_info(state, sp))
56+ goto out_err;
57+ }
5358 }
5459 sf = (struct stack_frame *) sp;
5560 ip = READ_ONCE_NOCHECK(sf->gprs[8]);
@@ -107,9 +112,9 @@ void __unwind_start(struct unwind_state *state, struct task_struct *task, · 51 unmodified lines
107112 {
108113 struct stack_info *info = &state->stack_info;
109114 unsigned long *mask = &state->stack_mask;
115+ bool reliable, reuse_sp;
110116 struct stack_frame *sf;
111117 unsigned long ip;
112− bool reliable;
113118
114119 memset(state, 0, sizeof(*state));
115120 state->task = task;
@@ -134,10 +139,12 @@ void __unwind_start(struct unwind_state *state, struct task_struct *task, · 18 unmodified lines
134139 if (regs) {
135140 ip = READ_ONCE_NOCHECK(regs->psw.addr);
136141 reliable = true;
142+ reuse_sp = true;
137143 } else {
138144 sf = (struct stack_frame *) sp;
139145 ip = READ_ONCE_NOCHECK(sf->gprs[8]);
140146 reliable = false;
147+ reuse_sp = false;
141148 }
142149
143150 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
@@ -151,5 +158,6 @@ void __unwind_start(struct unwind_state *state, struct task_struct *task, · 7 unmodified lines
151158 state->sp = sp;
152159 state->ip = ip;
153160 state->reliable = reliable;
161+ state->reuse_sp = reuse_sp;
154162 }
155163 EXPORT_SYMBOL_GPL(__unwind_start);
arch/s390/mm/cmm.c+6−6
@@ -298,16 +298,16 @@ static int cmm_timeout_handler(struct ctl_table *ctl, int write, · 297 unmodified lines
298298 }
299299
300300 if (write) {
301− len = *lenp;
302− if (copy_from_user(buf, buffer,
303− len > sizeof(buf) ? sizeof(buf) : len))
301+ len = min(*lenp, sizeof(buf));
302+ if (copy_from_user(buf, buffer, len))
304303 return -EFAULT;
305− buf[sizeof(buf) - 1] = '\0';
304+ buf[len - 1] = '\0';
306305 cmm_skip_blanks(buf, &p);
307306 nr = simple_strtoul(p, &p, 0);
308307 cmm_skip_blanks(p, &p);
309308 seconds = simple_strtoul(p, &p, 0);
310309 cmm_set_timeout(nr, seconds);
310+ *ppos += *lenp;
311311 } else {
312312 len = sprintf(buf, "%ld %ld\n",
313313 cmm_timeout_pages, cmm_timeout_seconds);
@@ -315,9 +315,9 @@ static int cmm_timeout_handler(struct ctl_table *ctl, int write, · 1 unmodified line
315315 len = *lenp;
316316 if (copy_to_user(buffer, buf, len))
317317 return -EFAULT;
318+ *lenp = len;
319+ *ppos += len;
318320 }
319− *lenp = len;
320− *ppos += len;
321321 return 0;
322322 }
323323
arch/sparc/Kconfig+0−1
@@ -29,7 +29,6 @@ config SPARC · 28 unmodified lines
2929 select RTC_DRV_M48T59
3030 select RTC_SYSTOHC
3131 select HAVE_ARCH_JUMP_LABEL if SPARC64
32− select HAVE_FAST_GUP if SPARC64
3332 select GENERIC_IRQ_SHOW
3433 select ARCH_WANT_IPC_PARSE_VERSION
3534 select GENERIC_PCI_IOMAP
arch/um/drivers/ubd_kern.c+6−2
@@ -1403,8 +1403,12 @@ static blk_status_t ubd_queue_rq(struct blk_mq_hw_ctx *hctx, · 1402 unmodified lines
14031403
14041404 spin_unlock_irq(&ubd_dev->lock);
14051405
1406− if (ret < 0)
1407− blk_mq_requeue_request(req, true);
1406+ if (ret < 0) {
1407+ if (ret == -ENOMEM)
1408+ res = BLK_STS_RESOURCE;
1409+ else
1410+ res = BLK_STS_DEV_RESOURCE;
1411+ }
14081412
14091413 return res;
14101414 }
arch/x86/boot/compressed/acpi.c+24−24
@@ -20,30 +20,6 @@ · 19 unmodified lines
2020 */
2121 struct mem_vector immovable_mem[MAX_NUMNODES*2];
2222
23−/*
24− * Max length of 64-bit hex address string is 19, prefix "0x" + 16 hex
25− * digits, and '\0' for termination.
26− */
27−#define MAX_ADDR_LEN 19
28−
29−static acpi_physical_address get_cmdline_acpi_rsdp(void)
30−{
31− acpi_physical_address addr = 0;
32−
33−#ifdef CONFIG_KEXEC
34− char val[MAX_ADDR_LEN] = { };
35− int ret;
36−
37− ret = cmdline_find_option("acpi_rsdp", val, MAX_ADDR_LEN);
38− if (ret < 0)
39− return 0;
40−
41− if (kstrtoull(val, 16, &addr))
42− return 0;
43−#endif
44− return addr;
45−}
46−
4723 /*
4824 * Search EFI system tables for RSDP. If both ACPI_20_TABLE_GUID and
4925 * ACPI_TABLE_GUID are found, take the former, which has more features.
@@ -298,6 +274,30 @@ acpi_physical_address get_rsdp_addr(void) · 248 unmodified lines
298274 }
299275
300276 #if defined(CONFIG_RANDOMIZE_BASE) && defined(CONFIG_MEMORY_HOTREMOVE)
277+/*
278+ * Max length of 64-bit hex address string is 19, prefix "0x" + 16 hex
279+ * digits, and '\0' for termination.
280+ */
281+#define MAX_ADDR_LEN 19
282+
283+static acpi_physical_address get_cmdline_acpi_rsdp(void)
284+{
285+ acpi_physical_address addr = 0;
286+
287+#ifdef CONFIG_KEXEC
288+ char val[MAX_ADDR_LEN] = { };
289+ int ret;
290+
291+ ret = cmdline_find_option("acpi_rsdp", val, MAX_ADDR_LEN);
292+ if (ret < 0)
293+ return 0;
294+
295+ if (kstrtoull(val, 16, &addr))
296+ return 0;
297+#endif
298+ return addr;
299+}
300+
301301 /* Compute SRAT address from RSDP. */
302302 static unsigned long get_acpi_srat_table(void)
303303 {
arch/x86/boot/compressed/eboot.c+3−1
@@ -13,6 +13,7 @@ · 12 unmodified lines
1313 #include <asm/e820/types.h>
1414 #include <asm/setup.h>
1515 #include <asm/desc.h>
16+#include <asm/boot.h>
1617
1718 #include "../string.h"
1819 #include "eboot.h"
@@ -813,7 +814,8 @@ efi_main(struct efi_config *c, struct boot_params *boot_params) · 794 unmodified lines
813814 status = efi_relocate_kernel(sys_table, &bzimage_addr,
814815 hdr->init_size, hdr->init_size,
815816 hdr->pref_address,
816− hdr->kernel_alignment);
817+ hdr->kernel_alignment,
818+ LOAD_PHYSICAL_ADDR);
817819 if (status != EFI_SUCCESS) {
818820 efi_printk(sys_table, "efi_relocate_kernel() failed!\n");
819821 goto fail;
arch/x86/boot/compressed/misc.c+19−6
@@ -345,6 +345,7 @@ asmlinkage __visible void *extract_kernel(void *rmode, memptr heap, · 344 unmodified lines
345345 {
346346 const unsigned long kernel_total_size = VO__end - VO__text;
347347 unsigned long virt_addr = LOAD_PHYSICAL_ADDR;
348+ unsigned long needed_size;
348349
349350 /* Retain x86 boot parameters pointer passed from startup_32/64. */
350351 boot_params = rmode;
@@ -379,26 +380,38 @@ asmlinkage __visible void *extract_kernel(void *rmode, memptr heap, · 28 unmodified lines
379380 free_mem_ptr = heap; /* Heap */
380381 free_mem_end_ptr = heap + BOOT_HEAP_SIZE;
381382
383+ /*
384+ * The memory hole needed for the kernel is the larger of either
385+ * the entire decompressed kernel plus relocation table, or the
386+ * entire decompressed kernel plus .bss and .brk sections.
387+ *
388+ * On X86_64, the memory is mapped with PMD pages. Round the
389+ * size up so that the full extent of PMD pages mapped is
390+ * included in the check against the valid memory table
391+ * entries. This ensures the full mapped area is usable RAM
392+ * and doesn't include any reserved areas.
393+ */
394+ needed_size = max(output_len, kernel_total_size);
395+#ifdef CONFIG_X86_64
396+ needed_size = ALIGN(needed_size, MIN_KERNEL_ALIGN);
397+#endif
398+
382399 /* Report initial kernel position details. */
383400 debug_putaddr(input_data);
384401 debug_putaddr(input_len);
385402 debug_putaddr(output);
386403 debug_putaddr(output_len);
387404 debug_putaddr(kernel_total_size);
405+ debug_putaddr(needed_size);
388406
389407 #ifdef CONFIG_X86_64
390408 /* Report address of 32-bit trampoline */
391409 debug_putaddr(trampoline_32bit);
392410 #endif
393411
394− /*
395− * The memory hole needed for the kernel is the larger of either
396− * the entire decompressed kernel plus relocation table, or the
397− * entire decompressed kernel plus .bss and .brk sections.
398− */
399412 choose_random_location((unsigned long)input_data, input_len,
400413 (unsigned long *)&output,
401− max(output_len, kernel_total_size),
414+ needed_size,
402415 &virt_addr);
403416
404417 /* Validate memory location choices. */
arch/x86/events/amd/core.c+17−13
@@ -5,12 +5,14 @@ · 4 unmodified lines
55 #include <linux/init.h>
66 #include <linux/slab.h>
77 #include <linux/delay.h>
8+#include <linux/jiffies.h>
89 #include <asm/apicdef.h>
910 #include <asm/nmi.h>
1011
1112 #include "../perf_event.h"
1213
13−static DEFINE_PER_CPU(unsigned int, perf_nmi_counter);
14+static DEFINE_PER_CPU(unsigned long, perf_nmi_tstamp);
15+static unsigned long perf_nmi_window;
1416
1517 static __initconst const u64 amd_hw_cache_event_ids
1618 [PERF_COUNT_HW_CACHE_MAX]
@@ -641,11 +643,12 @@ static void amd_pmu_disable_event(struct perf_event *event) · 624 unmodified lines
641643 * handler when multiple PMCs are active or PMC overflow while handling some
642644 * other source of an NMI.
643645 *
644− * Attempt to mitigate this by using the number of active PMCs to determine
645− * whether to return NMI_HANDLED if the perf NMI handler did not handle/reset
646− * any PMCs. The per-CPU perf_nmi_counter variable is set to a minimum of the
647− * number of active PMCs or 2. The value of 2 is used in case an NMI does not
648− * arrive at the LAPIC in time to be collapsed into an already pending NMI.
646+ * Attempt to mitigate this by creating an NMI window in which un-handled NMIs
647+ * received during this window will be claimed. This prevents extending the
648+ * window past when it is possible that latent NMIs should be received. The
649+ * per-CPU perf_nmi_tstamp will be set to the window end time whenever perf has
650+ * handled a counter. When an un-handled NMI is received, it will be claimed
651+ * only if arriving within that window.
649652 */
650653 static int amd_pmu_handle_irq(struct pt_regs *regs)
651654 {
@@ -663,21 +666,19 @@ static int amd_pmu_handle_irq(struct pt_regs *regs) · 11 unmodified lines
663666 handled = x86_pmu_handle_irq(regs);
664667
665668 /*
666− * If a counter was handled, record the number of possible remaining
667− * NMIs that can occur.
669+ * If a counter was handled, record a timestamp such that un-handled
670+ * NMIs will be claimed if arriving within that window.
668671 */
669672 if (handled) {
670− this_cpu_write(perf_nmi_counter,
671− min_t(unsigned int, 2, active));
673+ this_cpu_write(perf_nmi_tstamp,
674+ jiffies + perf_nmi_window);
672675
673676 return handled;
674677 }
675678
676− if (!this_cpu_read(perf_nmi_counter))
679+ if (time_after(jiffies, this_cpu_read(perf_nmi_tstamp)))
677680 return NMI_DONE;
678681
679− this_cpu_dec(perf_nmi_counter);
680−
681682 return NMI_HANDLED;
682683 }
683684
@@ -909,6 +910,9 @@ static int __init amd_core_pmu_init(void) · 225 unmodified lines
909910 if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
910911 return 0;
911912
913+ /* Avoid calulating the value each time in the NMI handler */
914+ perf_nmi_window = msecs_to_jiffies(100);
915+
912916 switch (boot_cpu_data.x86) {
913917 case 0x15:
914918 pr_cont("Fam15h ");
arch/x86/events/amd/ibs.c+5−3
@@ -377,7 +377,8 @@ static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs, · 376 unmodified lines
377377 struct hw_perf_event *hwc, u64 config)
378378 {
379379 config &= ~perf_ibs->cnt_mask;
380− wrmsrl(hwc->config_base, config);
380+ if (boot_cpu_data.x86 == 0x10)
381+ wrmsrl(hwc->config_base, config);
381382 config &= ~perf_ibs->enable_mask;
382383 wrmsrl(hwc->config_base, config);
383384 }
@@ -553,7 +554,8 @@ static struct perf_ibs perf_ibs_op = { · 169 unmodified lines
553554 },
554555 .msr = MSR_AMD64_IBSOPCTL,
555556 .config_mask = IBS_OP_CONFIG_MASK,
556− .cnt_mask = IBS_OP_MAX_CNT,
557+ .cnt_mask = IBS_OP_MAX_CNT | IBS_OP_CUR_CNT |
558+ IBS_OP_CUR_CNT_RAND,
557559 .enable_mask = IBS_OP_ENABLE,
558560 .valid_mask = IBS_OP_VAL,
559561 .max_period = IBS_OP_MAX_CNT << 4,
@@ -614,7 +616,7 @@ fail: · 54 unmodified lines
614616 if (event->attr.sample_type & PERF_SAMPLE_RAW)
615617 offset_max = perf_ibs->offset_max;
616618 else if (check_rip)
617− offset_max = 2;
619+ offset_max = 3;
618620 else
619621 offset_max = 1;
620622 do {
arch/x86/events/intel/core.c+4−0
@@ -4983,6 +4983,8 @@ __init int intel_pmu_init(void) · 4982 unmodified lines
49834983 case INTEL_FAM6_SKYLAKE:
49844984 case INTEL_FAM6_KABYLAKE_L:
49854985 case INTEL_FAM6_KABYLAKE:
4986+ case INTEL_FAM6_COMETLAKE_L:
4987+ case INTEL_FAM6_COMETLAKE:
49864988 x86_add_quirk(intel_pebs_isolation_quirk);
49874989 x86_pmu.late_ack = true;
49884990 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
@@ -5031,6 +5033,8 @@ __init int intel_pmu_init(void) · 42 unmodified lines
50315033 /* fall through */
50325034 case INTEL_FAM6_ICELAKE_L:
50335035 case INTEL_FAM6_ICELAKE:
5036+ case INTEL_FAM6_TIGERLAKE_L:
5037+ case INTEL_FAM6_TIGERLAKE:
50345038 x86_pmu.late_ack = true;
50355039 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
50365040 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
arch/x86/events/intel/cstate.c+32−12
@@ -45,46 +45,49 @@ · 44 unmodified lines
4545 * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
4646 * perf code: 0x01
4747 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
48− CNL
48+ * CNL,KBL,CML
4949 * Scope: Core
5050 * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
5151 * perf code: 0x02
5252 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
53− * SKL,KNL,GLM,CNL
53+ * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL
5454 * Scope: Core
5555 * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
5656 * perf code: 0x03
57− * Available model: SNB,IVB,HSW,BDW,SKL,CNL
57+ * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
58+ * ICL,TGL
5859 * Scope: Core
5960 * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
6061 * perf code: 0x00
61− * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
62+ * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
63+ * KBL,CML,ICL,TGL
6264 * Scope: Package (physical package)
6365 * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
6466 * perf code: 0x01
6567 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
66− * GLM,CNL
68+ * GLM,CNL,KBL,CML,ICL,TGL
6769 * Scope: Package (physical package)
6870 * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
6971 * perf code: 0x02
7072 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
71− * SKL,KNL,GLM,CNL
73+ * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL
7274 * Scope: Package (physical package)
7375 * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
7476 * perf code: 0x03
75− * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
77+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
78+ * KBL,CML,ICL,TGL
7679 * Scope: Package (physical package)
7780 * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
7881 * perf code: 0x04
79− * Available model: HSW ULT,KBL,CNL
82+ * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL
8083 * Scope: Package (physical package)
8184 * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
8285 * perf code: 0x05
83− * Available model: HSW ULT,KBL,CNL
86+ * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL
8487 * Scope: Package (physical package)
8588 * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
8689 * perf code: 0x06
87− * Available model: HSW ULT,KBL,GLM,CNL
90+ * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL
8891 * Scope: Package (physical package)
8992 *
9093 */
@@ -544,6 +547,19 @@ static const struct cstate_model cnl_cstates __initconst = { · 453 unmodified lines
544547 BIT(PERF_CSTATE_PKG_C10_RES),
545548 };
546549
550+static const struct cstate_model icl_cstates __initconst = {
551+ .core_events = BIT(PERF_CSTATE_CORE_C6_RES) |
552+ BIT(PERF_CSTATE_CORE_C7_RES),
553+
554+ .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
555+ BIT(PERF_CSTATE_PKG_C3_RES) |
556+ BIT(PERF_CSTATE_PKG_C6_RES) |
557+ BIT(PERF_CSTATE_PKG_C7_RES) |
558+ BIT(PERF_CSTATE_PKG_C8_RES) |
559+ BIT(PERF_CSTATE_PKG_C9_RES) |
560+ BIT(PERF_CSTATE_PKG_C10_RES),
561+};
562+
547563 static const struct cstate_model slm_cstates __initconst = {
548564 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
549565 BIT(PERF_CSTATE_CORE_C6_RES),
@@ -614,6 +630,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { · 64 unmodified lines
614630
615631 X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_L, hswult_cstates),
616632 X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE, hswult_cstates),
633+ X86_CSTATES_MODEL(INTEL_FAM6_COMETLAKE_L, hswult_cstates),
634+ X86_CSTATES_MODEL(INTEL_FAM6_COMETLAKE, hswult_cstates),
617635
618636 X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_L, cnl_cstates),
619637
@@ -625,8 +643,10 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { · 5 unmodified lines
625643
626644 X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),
627645
628− X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, snb_cstates),
629− X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, snb_cstates),
646+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates),
647+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, icl_cstates),
648+ X86_CSTATES_MODEL(INTEL_FAM6_TIGERLAKE_L, icl_cstates),
649+ X86_CSTATES_MODEL(INTEL_FAM6_TIGERLAKE, icl_cstates),
630650 { },
631651 };
632652 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
arch/x86/events/intel/pt.c+1−1
@@ -627,7 +627,7 @@ static struct topa *topa_alloc(int cpu, gfp_t gfp) · 626 unmodified lines
627627 * link as the 2nd entry in the table
628628 */
629629 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) {
630− TOPA_ENTRY(&tp->topa, 1)->base = page_to_phys(p);
630+ TOPA_ENTRY(&tp->topa, 1)->base = page_to_phys(p) >> TOPA_SHIFT;
631631 TOPA_ENTRY(&tp->topa, 1)->end = 1;
632632 }
633633
arch/x86/events/intel/uncore.c+38−6
@@ -502,10 +502,8 @@ void uncore_pmu_event_start(struct perf_event *event, int flags) · 501 unmodified lines
502502 local64_set(&event->hw.prev_count, uncore_read_counter(box, event));
503503 uncore_enable_event(box, event);
504504
505− if (box->n_active == 1) {
506− uncore_enable_box(box);
505+ if (box->n_active == 1)
507506 uncore_pmu_start_hrtimer(box);
508− }
509507 }
510508
511509 void uncore_pmu_event_stop(struct perf_event *event, int flags)
@@ -529,10 +527,8 @@ void uncore_pmu_event_stop(struct perf_event *event, int flags) · 17 unmodified lines
529527 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
530528 hwc->state |= PERF_HES_STOPPED;
531529
532− if (box->n_active == 0) {
533− uncore_disable_box(box);
530+ if (box->n_active == 0)
534531 uncore_pmu_cancel_hrtimer(box);
535− }
536532 }
537533
538534 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
@@ -778,6 +774,40 @@ static int uncore_pmu_event_init(struct perf_event *event) · 239 unmodified lines
778774 return ret;
779775 }
780776
777+static void uncore_pmu_enable(struct pmu *pmu)
778+{
779+ struct intel_uncore_pmu *uncore_pmu;
780+ struct intel_uncore_box *box;
781+
782+ uncore_pmu = container_of(pmu, struct intel_uncore_pmu, pmu);
783+ if (!uncore_pmu)
784+ return;
785+
786+ box = uncore_pmu_to_box(uncore_pmu, smp_processor_id());
787+ if (!box)
788+ return;
789+
790+ if (uncore_pmu->type->ops->enable_box)
791+ uncore_pmu->type->ops->enable_box(box);
792+}
793+
794+static void uncore_pmu_disable(struct pmu *pmu)
795+{
796+ struct intel_uncore_pmu *uncore_pmu;
797+ struct intel_uncore_box *box;
798+
799+ uncore_pmu = container_of(pmu, struct intel_uncore_pmu, pmu);
800+ if (!uncore_pmu)
801+ return;
802+
803+ box = uncore_pmu_to_box(uncore_pmu, smp_processor_id());
804+ if (!box)
805+ return;
806+
807+ if (uncore_pmu->type->ops->disable_box)
808+ uncore_pmu->type->ops->disable_box(box);
809+}
810+
781811 static ssize_t uncore_get_attr_cpumask(struct device *dev,
782812 struct device_attribute *attr, char *buf)
783813 {
@@ -803,6 +833,8 @@ static int uncore_pmu_register(struct intel_uncore_pmu *pmu) · 19 unmodified lines
803833 pmu->pmu = (struct pmu) {
804834 .attr_groups = pmu->type->attr_groups,
805835 .task_ctx_nr = perf_invalid_context,
836+ .pmu_enable = uncore_pmu_enable,
837+ .pmu_disable = uncore_pmu_disable,
806838 .event_init = uncore_pmu_event_init,
807839 .add = uncore_pmu_event_add,
808840 .del = uncore_pmu_event_del,
arch/x86/events/intel/uncore.h+0−12
@@ -441,18 +441,6 @@ static inline int uncore_freerunning_hw_config(struct intel_uncore_box *box, · 440 unmodified lines
441441 return -EINVAL;
442442 }
443443
444−static inline void uncore_disable_box(struct intel_uncore_box *box)
445−{
446− if (box->pmu->type->ops->disable_box)
447− box->pmu->type->ops->disable_box(box);
448−}
449−
450−static inline void uncore_enable_box(struct intel_uncore_box *box)
451−{
452− if (box->pmu->type->ops->enable_box)
453− box->pmu->type->ops->enable_box(box);
454−}
455−
456444 static inline void uncore_disable_event(struct intel_uncore_box *box,
457445 struct perf_event *event)
458446 {
arch/x86/events/msr.c+7−0
@@ -89,7 +89,14 @@ static bool test_intel(int idx, void *data) · 88 unmodified lines
8989 case INTEL_FAM6_SKYLAKE_X:
9090 case INTEL_FAM6_KABYLAKE_L:
9191 case INTEL_FAM6_KABYLAKE:
92+ case INTEL_FAM6_COMETLAKE_L:
93+ case INTEL_FAM6_COMETLAKE:
9294 case INTEL_FAM6_ICELAKE_L:
95+ case INTEL_FAM6_ICELAKE:
96+ case INTEL_FAM6_ICELAKE_X:
97+ case INTEL_FAM6_ICELAKE_D:
98+ case INTEL_FAM6_TIGERLAKE_L:
99+ case INTEL_FAM6_TIGERLAKE:
93100 if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
94101 return true;
95102 break;
arch/x86/hyperv/hv_apic.c+15−5
@@ -260,11 +260,21 @@ void __init hv_apic_init(void) · 259 unmodified lines
260260 }
261261
262262 if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
263− pr_info("Hyper-V: Using MSR based APIC access\n");
263+ pr_info("Hyper-V: Using enlightened APIC (%s mode)",
264+ x2apic_enabled() ? "x2apic" : "xapic");
265+ /*
266+ * With x2apic, architectural x2apic MSRs are equivalent to the
267+ * respective synthetic MSRs, so there's no need to override
268+ * the apic accessors. The only exception is
269+ * hv_apic_eoi_write, because it benefits from lazy EOI when
270+ * available, but it works for both xapic and x2apic modes.
271+ */
264272 apic_set_eoi_write(hv_apic_eoi_write);
265− apic->read = hv_apic_read;
266− apic->write = hv_apic_write;
267− apic->icr_write = hv_apic_icr_write;
268− apic->icr_read = hv_apic_icr_read;
273+ if (!x2apic_enabled()) {
274+ apic->read = hv_apic_read;
275+ apic->write = hv_apic_write;
276+ apic->icr_write = hv_apic_icr_write;
277+ apic->icr_read = hv_apic_icr_read;
278+ }
269279 }
270280 }
arch/x86/include/asm/cpu_entry_area.h+1−1
@@ -1,4 +1,4 @@
1−// SPDX-License-Identifier: GPL-2.0
1+/* SPDX-License-Identifier: GPL-2.0 */
22
33 #ifndef _ASM_X86_CPU_ENTRY_AREA_H
44 #define _ASM_X86_CPU_ENTRY_AREA_H
arch/x86/include/asm/intel-family.h+3−0
@@ -83,6 +83,9 @@ · 82 unmodified lines
8383 #define INTEL_FAM6_TIGERLAKE_L 0x8C
8484 #define INTEL_FAM6_TIGERLAKE 0x8D
8585
86+#define INTEL_FAM6_COMETLAKE 0xA5
87+#define INTEL_FAM6_COMETLAKE_L 0xA6
88+
8689 /* "Small Core" Processors (Atom) */
8790
8891 #define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
arch/x86/include/asm/kvm_host.h+1−1
@@ -1189,7 +1189,7 @@ struct kvm_x86_ops { · 1188 unmodified lines
11891189 int (*set_nested_state)(struct kvm_vcpu *vcpu,
11901190 struct kvm_nested_state __user *user_kvm_nested_state,
11911191 struct kvm_nested_state *kvm_state);
1192− void (*get_vmcs12_pages)(struct kvm_vcpu *vcpu);
1192+ bool (*get_vmcs12_pages)(struct kvm_vcpu *vcpu);
11931193
11941194 int (*smi_allowed)(struct kvm_vcpu *vcpu);
11951195 int (*pre_enter_smm)(struct kvm_vcpu *vcpu, char *smstate);
arch/x86/include/asm/mwait.h+1−1
@@ -21,7 +21,7 @@ · 20 unmodified lines
2121 #define MWAIT_ECX_INTERRUPT_BREAK 0x1
2222 #define MWAITX_ECX_TIMER_ENABLE BIT(1)
2323 #define MWAITX_MAX_LOOPS ((u32)-1)
24−#define MWAITX_DISABLE_CSTATES 0xf
24+#define MWAITX_DISABLE_CSTATES 0xf0
2525
2626 static inline void __monitor(const void *eax, unsigned long ecx,
2727 unsigned long edx)
arch/x86/include/asm/pti.h+1−1
@@ -1,4 +1,4 @@
1−// SPDX-License-Identifier: GPL-2.0
1+/* SPDX-License-Identifier: GPL-2.0 */
22 #ifndef _ASM_X86_PTI_H
33 #define _ASM_X86_PTI_H
44 #ifndef __ASSEMBLY__
arch/x86/include/asm/uaccess.h+23−0
@@ -734,5 +734,28 @@ do { \ · 733 unmodified lines
734734 if (unlikely(__gu_err)) goto err_label; \
735735 } while (0)
736736
737+/*
738+ * We want the unsafe accessors to always be inlined and use
739+ * the error labels - thus the macro games.
740+ */
741+#define unsafe_copy_loop(dst, src, len, type, label) \
742+ while (len >= sizeof(type)) { \
743+ unsafe_put_user(*(type *)src,(type __user *)dst,label); \
744+ dst += sizeof(type); \
745+ src += sizeof(type); \
746+ len -= sizeof(type); \
747+ }
748+
749+#define unsafe_copy_to_user(_dst,_src,_len,label) \
750+do { \
751+ char __user *__ucu_dst = (_dst); \
752+ const char *__ucu_src = (_src); \
753+ size_t __ucu_len = (_len); \
754+ unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \
755+ unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \
756+ unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \
757+ unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \
758+} while (0)
759+
737760 #endif /* _ASM_X86_UACCESS_H */
738761
arch/x86/include/asm/vmware.h+9−5
@@ -4,6 +4,7 @@ · 3 unmodified lines
44
55 #include <asm/cpufeatures.h>
66 #include <asm/alternative.h>
7+#include <linux/stringify.h>
78
89 /*
910 * The hypercall definitions differ in the low word of the %edx argument
@@ -20,8 +21,8 @@ · 10 unmodified lines
2021 */
2122
2223 /* Old port-based version */
23−#define VMWARE_HYPERVISOR_PORT "0x5658"
24−#define VMWARE_HYPERVISOR_PORT_HB "0x5659"
24+#define VMWARE_HYPERVISOR_PORT 0x5658
25+#define VMWARE_HYPERVISOR_PORT_HB 0x5659
2526
2627 /* Current vmcall / vmmcall version */
2728 #define VMWARE_HYPERVISOR_HB BIT(0)
@@ -29,7 +30,8 @@ · 1 unmodified line
2930
3031 /* The low bandwidth call. The low word of edx is presumed clear. */
3132 #define VMWARE_HYPERCALL \
32− ALTERNATIVE_2("movw $" VMWARE_HYPERVISOR_PORT ", %%dx; inl (%%dx)", \
33+ ALTERNATIVE_2("movw $" __stringify(VMWARE_HYPERVISOR_PORT) ", %%dx; " \
34+ "inl (%%dx), %%eax", \
3335 "vmcall", X86_FEATURE_VMCALL, \
3436 "vmmcall", X86_FEATURE_VMW_VMMCALL)
3537
@@ -38,7 +40,8 @@ · 2 unmodified lines
3840 * HB and OUT bits set.
3941 */
4042 #define VMWARE_HYPERCALL_HB_OUT \
41− ALTERNATIVE_2("movw $" VMWARE_HYPERVISOR_PORT_HB ", %%dx; rep outsb", \
43+ ALTERNATIVE_2("movw $" __stringify(VMWARE_HYPERVISOR_PORT_HB) ", %%dx; " \
44+ "rep outsb", \
4245 "vmcall", X86_FEATURE_VMCALL, \
4346 "vmmcall", X86_FEATURE_VMW_VMMCALL)
4447
@@ -47,7 +50,8 @@ · 2 unmodified lines
4750 * HB bit set.
4851 */
4952 #define VMWARE_HYPERCALL_HB_IN \
50− ALTERNATIVE_2("movw $" VMWARE_HYPERVISOR_PORT_HB ", %%dx; rep insb", \
53+ ALTERNATIVE_2("movw $" __stringify(VMWARE_HYPERVISOR_PORT_HB) ", %%dx; " \
54+ "rep insb", \
5155 "vmcall", X86_FEATURE_VMCALL, \
5256 "vmmcall", X86_FEATURE_VMW_VMMCALL)
5357 #endif
arch/x86/kernel/apic/apic.c+15−13
@@ -1586,9 +1586,6 @@ static void setup_local_APIC(void) · 1585 unmodified lines
15861586 {
15871587 int cpu = smp_processor_id();
15881588 unsigned int value;
1589−#ifdef CONFIG_X86_32
1590− int logical_apicid, ldr_apicid;
1591−#endif
15921589
15931590 if (disable_apic) {
15941591 disable_ioapic_support();
@@ -1626,16 +1623,21 @@ static void setup_local_APIC(void) · 31 unmodified lines
16261623 apic->init_apic_ldr();
16271624
16281625 #ifdef CONFIG_X86_32
1629− /*
1630− * APIC LDR is initialized. If logical_apicid mapping was
1631− * initialized during get_smp_config(), make sure it matches the
1632− * actual value.
1633− */
1634− logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1635− ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1636− WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid);
1637− /* always use the value from LDR */
1638− early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1626+ if (apic->dest_logical) {
1627+ int logical_apicid, ldr_apicid;
1628+
1629+ /*
1630+ * APIC LDR is initialized. If logical_apicid mapping was
1631+ * initialized during get_smp_config(), make sure it matches
1632+ * the actual value.
1633+ */
1634+ logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1635+ ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1636+ if (logical_apicid != BAD_APICID)
1637+ WARN_ON(logical_apicid != ldr_apicid);
1638+ /* Always use the value from LDR. */
1639+ early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1640+ }
16391641 #endif
16401642
16411643 /*
arch/x86/kernel/apic/x2apic_cluster.c+2−1
@@ -156,7 +156,8 @@ static int x2apic_dead_cpu(unsigned int dead_cpu) · 155 unmodified lines
156156 {
157157 struct cluster_mask *cmsk = per_cpu(cluster_masks, dead_cpu);
158158
159− cpumask_clear_cpu(dead_cpu, &cmsk->mask);
159+ if (cmsk)
160+ cpumask_clear_cpu(dead_cpu, &cmsk->mask);
160161 free_cpumask_var(per_cpu(ipi_mask, dead_cpu));
161162 return 0;
162163 }
arch/x86/kernel/cpu/mshyperv.c+4−0
@@ -216,6 +216,10 @@ static void __init ms_hyperv_init_platform(void) · 215 unmodified lines
216216 int hv_host_info_ecx;
217217 int hv_host_info_edx;
218218
219+#ifdef CONFIG_PARAVIRT
220+ pv_info.name = "Hyper-V";
221+#endif
222+
219223 /*
220224 * Extract the features and hints
221225 */
arch/x86/kernel/cpu/resctrl/ctrlmondata.c+4−0
@@ -522,6 +522,10 @@ int rdtgroup_mondata_show(struct seq_file *m, void *arg) · 521 unmodified lines
522522 int ret = 0;
523523
524524 rdtgrp = rdtgroup_kn_lock_live(of->kn);
525+ if (!rdtgrp) {
526+ ret = -ENOENT;
527+ goto out;
528+ }
525529
526530 md.priv = of->kn->priv;
527531 resid = md.u.rid;
arch/x86/kernel/cpu/vmware.c+1−1
@@ -49,7 +49,7 @@ · 48 unmodified lines
4949 #define VMWARE_CMD_VCPU_RESERVED 31
5050
5151 #define VMWARE_PORT(cmd, eax, ebx, ecx, edx) \
52− __asm__("inl (%%dx)" : \
52+ __asm__("inl (%%dx), %%eax" : \
5353 "=a"(eax), "=c"(ecx), "=d"(edx), "=b"(ebx) : \
5454 "a"(VMWARE_HYPERVISOR_MAGIC), \
5555 "c"(VMWARE_CMD_##cmd), \
arch/x86/kernel/dumpstack_64.c+7−0
@@ -94,6 +94,13 @@ static bool in_exception_stack(unsigned long *stack, struct stack_info *info) · 93 unmodified lines
9494 BUILD_BUG_ON(N_EXCEPTION_STACKS != 6);
9595
9696 begin = (unsigned long)__this_cpu_read(cea_exception_stacks);
97+ /*
98+ * Handle the case where stack trace is collected _before_
99+ * cea_exception_stacks had been initialized.
100+ */
101+ if (!begin)
102+ return false;
103+
97104 end = begin + sizeof(struct cea_exception_stacks);
98105 /* Bail if @stack is outside the exception stack area. */
99106 if (stk < begin || stk >= end)
arch/x86/kernel/head64.c+20−2
@@ -222,13 +222,31 @@ unsigned long __head __startup_64(unsigned long physaddr, · 221 unmodified lines
222222 * we might write invalid pmds, when the kernel is relocated
223223 * cleanup_highmap() fixes this up along with the mappings
224224 * beyond _end.
225+ *
226+ * Only the region occupied by the kernel image has so far
227+ * been checked against the table of usable memory regions
228+ * provided by the firmware, so invalidate pages outside that
229+ * region. A page table entry that maps to a reserved area of
230+ * memory would allow processor speculation into that area,
231+ * and on some hardware (particularly the UV platform) even
232+ * speculative access to some reserved areas is caught as an
233+ * error, causing the BIOS to halt the system.
225234 */
226235
227236 pmd = fixup_pointer(level2_kernel_pgt, physaddr);
228− for (i = 0; i < PTRS_PER_PMD; i++) {
237+
238+ /* invalidate pages before the kernel image */
239+ for (i = 0; i < pmd_index((unsigned long)_text); i++)
240+ pmd[i] &= ~_PAGE_PRESENT;
241+
242+ /* fixup pages that are part of the kernel image */
243+ for (; i <= pmd_index((unsigned long)_end); i++)
229244 if (pmd[i] & _PAGE_PRESENT)
230245 pmd[i] += load_delta;
231− }
246+
247+ /* invalidate pages after the kernel image */
248+ for (; i < PTRS_PER_PMD; i++)
249+ pmd[i] &= ~_PAGE_PRESENT;
232250
233251 /*
234252 * Fixup phys_base - remove the memory encryption mask to obtain
arch/x86/kernel/process.h+1−1
@@ -1,4 +1,4 @@
1−// SPDX-License-Identifier: GPL-2.0
1+/* SPDX-License-Identifier: GPL-2.0 */
22 //
33 // Code shared between 32 and 64 bit
44
arch/x86/kernel/tsc.c+3−0
@@ -1505,6 +1505,9 @@ void __init tsc_init(void) · 1504 unmodified lines
15051505 return;
15061506 }
15071507
1508+ if (tsc_clocksource_reliable || no_tsc_watchdog)
1509+ clocksource_tsc_early.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1510+
15081511 clocksource_register_khz(&clocksource_tsc_early, tsc_khz);
15091512 detect_art();
15101513 }
arch/x86/kvm/cpuid.c+1−1
@@ -363,7 +363,7 @@ static inline void do_cpuid_7_mask(struct kvm_cpuid_entry2 *entry, int index) · 362 unmodified lines
363363
364364 /* cpuid 7.0.ecx*/
365365 const u32 kvm_cpuid_7_0_ecx_x86_features =
366− F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ |
366+ F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
367367 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
368368 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
369369 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/;
arch/x86/kvm/lapic.c+0−5
@@ -111,11 +111,6 @@ static inline int apic_enabled(struct kvm_lapic *apic) · 110 unmodified lines
111111 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
112112 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
113113
114−static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
115−{
116− return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
117−}
118−
119114 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
120115 {
121116 return apic->vcpu->vcpu_id;
arch/x86/kvm/lapic.h+5−0
@@ -242,4 +242,9 @@ static inline enum lapic_mode kvm_apic_mode(u64 apic_base) · 241 unmodified lines
242242 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
243243 }
244244
245+static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
246+{
247+ return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
248+}
249+
245250 #endif
arch/x86/kvm/svm.c+11−5
@@ -734,8 +734,14 @@ static int get_npt_level(struct kvm_vcpu *vcpu) · 733 unmodified lines
734734 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
735735 {
736736 vcpu->arch.efer = efer;
737− if (!npt_enabled && !(efer & EFER_LMA))
738− efer &= ~EFER_LME;
737+
738+ if (!npt_enabled) {
739+ /* Shadow paging assumes NX to be available. */
740+ efer |= EFER_NX;
741+
742+ if (!(efer & EFER_LMA))
743+ efer &= ~EFER_LME;
744+ }
739745
740746 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
741747 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
@@ -4591,6 +4597,7 @@ static int avic_handle_ldr_update(struct kvm_vcpu *vcpu) · 3849 unmodified lines
45914597 int ret = 0;
45924598 struct vcpu_svm *svm = to_svm(vcpu);
45934599 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4600+ u32 id = kvm_xapic_id(vcpu->arch.apic);
45944601
45954602 if (ldr == svm->ldr_reg)
45964603 return 0;
@@ -4598,7 +4605,7 @@ static int avic_handle_ldr_update(struct kvm_vcpu *vcpu) · 1 unmodified line
45984605 avic_invalidate_logical_id_entry(vcpu);
45994606
46004607 if (ldr)
4601− ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr);
4608+ ret = avic_ldr_write(vcpu, id, ldr);
46024609
46034610 if (!ret)
46044611 svm->ldr_reg = ldr;
@@ -4610,8 +4617,7 @@ static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu) · 5 unmodified lines
46104617 {
46114618 u64 *old, *new;
46124619 struct vcpu_svm *svm = to_svm(vcpu);
4613− u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4614− u32 id = (apic_id_reg >> 24) & 0xff;
4620+ u32 id = kvm_xapic_id(vcpu->arch.apic);
46154621
46164622 if (vcpu->vcpu_id == id)
46174623 return 0;
arch/x86/kvm/vmx/nested.c+36−28
@@ -2917,7 +2917,7 @@ static int nested_vmx_check_vmentry_hw(struct kvm_vcpu *vcpu) · 2916 unmodified lines
29172917 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
29182918 struct vmcs12 *vmcs12);
29192919
2920−static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
2920+static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
29212921 {
29222922 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
29232923 struct vcpu_vmx *vmx = to_vmx(vcpu);
@@ -2937,19 +2937,18 @@ static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu) · 13 unmodified lines
29372937 vmx->nested.apic_access_page = NULL;
29382938 }
29392939 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
2940− /*
2941− * If translation failed, no matter: This feature asks
2942− * to exit when accessing the given address, and if it
2943− * can never be accessed, this feature won't do
2944− * anything anyway.
2945− */
29462940 if (!is_error_page(page)) {
29472941 vmx->nested.apic_access_page = page;
29482942 hpa = page_to_phys(vmx->nested.apic_access_page);
29492943 vmcs_write64(APIC_ACCESS_ADDR, hpa);
29502944 } else {
2951− secondary_exec_controls_clearbit(vmx,
2952− SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
2945+ pr_debug_ratelimited("%s: no backing 'struct page' for APIC-access address in vmcs12\n",
2946+ __func__);
2947+ vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2948+ vcpu->run->internal.suberror =
2949+ KVM_INTERNAL_ERROR_EMULATION;
2950+ vcpu->run->internal.ndata = 0;
2951+ return false;
29532952 }
29542953 }
29552954
@@ -2994,6 +2993,7 @@ static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu) · 38 unmodified lines
29942993 exec_controls_setbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
29952994 else
29962995 exec_controls_clearbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
2996+ return true;
29972997 }
29982998
29992999 /*
@@ -3032,13 +3032,15 @@ static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, · 32 unmodified lines
30323032 /*
30333033 * If from_vmentry is false, this is being called from state restore (either RSM
30343034 * or KVM_SET_NESTED_STATE). Otherwise it's called from vmlaunch/vmresume.
3035−+ *
3036−+ * Returns:
3037−+ * 0 - success, i.e. proceed with actual VMEnter
3038−+ * 1 - consistency check VMExit
3039−+ * -1 - consistency check VMFail
3035+ *
3036+ * Returns:
3037+ * NVMX_ENTRY_SUCCESS: Entered VMX non-root mode
3038+ * NVMX_ENTRY_VMFAIL: Consistency check VMFail
3039+ * NVMX_ENTRY_VMEXIT: Consistency check VMExit
3040+ * NVMX_ENTRY_KVM_INTERNAL_ERROR: KVM internal error
30403041 */
3041−int nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
3042+enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
3043+ bool from_vmentry)
30423044 {
30433045 struct vcpu_vmx *vmx = to_vmx(vcpu);
30443046 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
@@ -3081,11 +3083,12 @@ int nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry) · 36 unmodified lines
30813083 prepare_vmcs02_early(vmx, vmcs12);
30823084
30833085 if (from_vmentry) {
3084− nested_get_vmcs12_pages(vcpu);
3086+ if (unlikely(!nested_get_vmcs12_pages(vcpu)))
3087+ return NVMX_VMENTRY_KVM_INTERNAL_ERROR;
30853088
30863089 if (nested_vmx_check_vmentry_hw(vcpu)) {
30873090 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3088− return -1;
3091+ return NVMX_VMENTRY_VMFAIL;
30893092 }
30903093
30913094 if (nested_vmx_check_guest_state(vcpu, vmcs12, &exit_qual))
@@ -3149,7 +3152,7 @@ int nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry) · 57 unmodified lines
31493152 * returned as far as L1 is concerned. It will only return (and set
31503153 * the success flag) when L2 exits (see nested_vmx_vmexit()).
31513154 */
3152− return 0;
3155+ return NVMX_VMENTRY_SUCCESS;
31533156
31543157 /*
31553158 * A failed consistency check that leads to a VMExit during L1's
@@ -3165,14 +3168,14 @@ vmentry_fail_vmexit: · 9 unmodified lines
31653168 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
31663169
31673170 if (!from_vmentry)
3168− return 1;
3171+ return NVMX_VMENTRY_VMEXIT;
31693172
31703173 load_vmcs12_host_state(vcpu, vmcs12);
31713174 vmcs12->vm_exit_reason = exit_reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
31723175 vmcs12->exit_qualification = exit_qual;
31733176 if (enable_shadow_vmcs || vmx->nested.hv_evmcs)
31743177 vmx->nested.need_vmcs12_to_shadow_sync = true;
3175− return 1;
3178+ return NVMX_VMENTRY_VMEXIT;
31763179 }
31773180
31783181 /*
@@ -3182,9 +3185,9 @@ vmentry_fail_vmexit: · 3 unmodified lines
31823185 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
31833186 {
31843187 struct vmcs12 *vmcs12;
3188+ enum nvmx_vmentry_status status;
31853189 struct vcpu_vmx *vmx = to_vmx(vcpu);
31863190 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
3187− int ret;
31883191
31893192 if (!nested_vmx_check_permission(vcpu))
31903193 return 1;
@@ -3244,13 +3247,9 @@ static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) · 53 unmodified lines
32443247 * the nested entry.
32453248 */
32463249 vmx->nested.nested_run_pending = 1;
3247− ret = nested_vmx_enter_non_root_mode(vcpu, true);
3248− vmx->nested.nested_run_pending = !ret;
3249− if (ret > 0)
3250− return 1;
3251− else if (ret)
3252− return nested_vmx_failValid(vcpu,
3253− VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3250+ status = nested_vmx_enter_non_root_mode(vcpu, true);
3251+ if (unlikely(status != NVMX_VMENTRY_SUCCESS))
3252+ goto vmentry_failed;
32543253
32553254 /* Hide L1D cache contents from the nested guest. */
32563255 vmx->vcpu.arch.l1tf_flush_l1d = true;
@@ -3281,6 +3280,15 @@ static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) · 24 unmodified lines
32813280 return kvm_vcpu_halt(vcpu);
32823281 }
32833282 return 1;
3283+
3284+vmentry_failed:
3285+ vmx->nested.nested_run_pending = 0;
3286+ if (status == NVMX_VMENTRY_KVM_INTERNAL_ERROR)
3287+ return 0;
3288+ if (status == NVMX_VMENTRY_VMEXIT)
3289+ return 1;
3290+ WARN_ON_ONCE(status != NVMX_VMENTRY_VMFAIL);
3291+ return nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
32843292 }
32853293
32863294 /*
arch/x86/kvm/vmx/nested.h+12−1
@@ -6,6 +6,16 @@ · 5 unmodified lines
66 #include "vmcs12.h"
77 #include "vmx.h"
88
9+/*
10+ * Status returned by nested_vmx_enter_non_root_mode():
11+ */
12+enum nvmx_vmentry_status {
13+ NVMX_VMENTRY_SUCCESS, /* Entered VMX non-root mode */
14+ NVMX_VMENTRY_VMFAIL, /* Consistency check VMFail */
15+ NVMX_VMENTRY_VMEXIT, /* Consistency check VMExit */
16+ NVMX_VMENTRY_KVM_INTERNAL_ERROR,/* KVM internal error */
17+};
18+
919 void vmx_leave_nested(struct kvm_vcpu *vcpu);
1020 void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps,
1121 bool apicv);
@@ -13,7 +23,8 @@ void nested_vmx_hardware_unsetup(void); · 1 unmodified line
1323 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *));
1424 void nested_vmx_vcpu_setup(void);
1525 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu);
16−int nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry);
26+enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
27+ bool from_vmentry);
1728 bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason);
1829 void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1930 u32 exit_intr_info, unsigned long exit_qualification);
arch/x86/kvm/vmx/vmx.c+3−23
@@ -969,17 +969,9 @@ static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) · 968 unmodified lines
969969 u64 guest_efer = vmx->vcpu.arch.efer;
970970 u64 ignore_bits = 0;
971971
972− if (!enable_ept) {
973− /*
974− * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
975− * host CPUID is more efficient than testing guest CPUID
976− * or CR4. Host SMEP is anyway a requirement for guest SMEP.
977− */
978− if (boot_cpu_has(X86_FEATURE_SMEP))
979− guest_efer |= EFER_NX;
980− else if (!(guest_efer & EFER_NX))
981− ignore_bits |= EFER_NX;
982− }
972+ /* Shadow paging assumes NX to be available. */
973+ if (!enable_ept)
974+ guest_efer |= EFER_NX;
983975
984976 /*
985977 * LMA and LME handled by hardware; SCE meaningless outside long mode.
@@ -5543,14 +5535,6 @@ static int handle_encls(struct kvm_vcpu *vcpu) · 4557 unmodified lines
55435535 return 1;
55445536 }
55455537
5546−static int handle_unexpected_vmexit(struct kvm_vcpu *vcpu)
5547−{
5548− kvm_skip_emulated_instruction(vcpu);
5549− WARN_ONCE(1, "Unexpected VM-Exit Reason = 0x%x",
5550− vmcs_read32(VM_EXIT_REASON));
5551− return 1;
5552−}
5553−
55545538 /*
55555539 * The exit handlers return 1 if the exit was handled fully and guest execution
55565540 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
@@ -5602,15 +5586,11 @@ static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { · 45 unmodified lines
56025586 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
56035587 [EXIT_REASON_RDRAND] = handle_invalid_op,
56045588 [EXIT_REASON_RDSEED] = handle_invalid_op,
5605− [EXIT_REASON_XSAVES] = handle_unexpected_vmexit,
5606− [EXIT_REASON_XRSTORS] = handle_unexpected_vmexit,
56075589 [EXIT_REASON_PML_FULL] = handle_pml_full,
56085590 [EXIT_REASON_INVPCID] = handle_invpcid,
56095591 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
56105592 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
56115593 [EXIT_REASON_ENCLS] = handle_encls,
5612− [EXIT_REASON_UMWAIT] = handle_unexpected_vmexit,
5613− [EXIT_REASON_TPAUSE] = handle_unexpected_vmexit,
56145594 };
56155595
56165596 static const int kvm_vmx_max_exit_handlers =
arch/x86/kvm/x86.c+10−9
@@ -360,8 +360,7 @@ EXPORT_SYMBOL_GPL(kvm_set_apic_base); · 359 unmodified lines
360360 asmlinkage __visible void kvm_spurious_fault(void)
361361 {
362362 /* Fault while not rebooting. We want the trace. */
363− if (!kvm_rebooting)
364− BUG();
363+ BUG_ON(!kvm_rebooting);
365364 }
366365 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
367366
@@ -2537,6 +2536,7 @@ static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) · 2169 unmodified lines
25372536 static void kvmclock_reset(struct kvm_vcpu *vcpu)
25382537 {
25392538 vcpu->arch.pv_time_enabled = false;
2539+ vcpu->arch.time = 0;
25402540 }
25412541
25422542 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
@@ -2702,8 +2702,6 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) · 159 unmodified lines
27022702 case MSR_KVM_SYSTEM_TIME: {
27032703 struct kvm_arch *ka = &vcpu->kvm->arch;
27042704
2705− kvmclock_reset(vcpu);
2706−
27072705 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
27082706 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
27092707
@@ -2717,14 +2715,13 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) · 7 unmodified lines
27172715 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
27182716
27192717 /* we verify if the enable bit is set... */
2718+ vcpu->arch.pv_time_enabled = false;
27202719 if (!(data & 1))
27212720 break;
27222721
2723− if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2722+ if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
27242723 &vcpu->arch.pv_time, data & ~1ULL,
27252724 sizeof(struct pvclock_vcpu_time_info)))
2726− vcpu->arch.pv_time_enabled = false;
2727− else
27282725 vcpu->arch.pv_time_enabled = true;
27292726
27302727 break;
@@ -7941,8 +7938,12 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) · 5210 unmodified lines
79417938 bool req_immediate_exit = false;
79427939
79437940 if (kvm_request_pending(vcpu)) {
7944− if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7945− kvm_x86_ops->get_vmcs12_pages(vcpu);
7941+ if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
7942+ if (unlikely(!kvm_x86_ops->get_vmcs12_pages(vcpu))) {
7943+ r = 0;
7944+ goto out;
7945+ }
7946+ }
79467947 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
79477948 kvm_mmu_unload(vcpu);
79487949 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
arch/x86/lib/delay.c+2−2
@@ -113,8 +113,8 @@ static void delay_mwaitx(unsigned long __loops) · 112 unmodified lines
113113 __monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0);
114114
115115 /*
116− * AMD, like Intel, supports the EAX hint and EAX=0xf
117− * means, do not enter any deep C-state and we use it
116+ * AMD, like Intel's MWAIT version, supports the EAX hint and
117+ * EAX=0xf0 means, do not enter any deep C-state and we use it
118118 * here in delay() to minimize wakeup latency.
119119 */
120120 __mwaitx(MWAITX_DISABLE_CSTATES, delay, MWAITX_ECX_TIMER_ENABLE);
arch/x86/platform/efi/efi.c+0−3
@@ -917,9 +917,6 @@ static void __init kexec_enter_virtual_mode(void) · 916 unmodified lines
917917
918918 if (efi_enabled(EFI_OLD_MEMMAP) && (__supported_pte_mask & _PAGE_NX))
919919 runtime_code_page_mkexec();
920−
921− /* clean DUMMY object */
922− efi_delete_dummy_variable();
923920 #endif
924921 }
925922
arch/x86/xen/enlighten.c+25−3
@@ -269,19 +269,41 @@ void xen_reboot(int reason) · 268 unmodified lines
269269 BUG();
270270 }
271271
272+static int reboot_reason = SHUTDOWN_reboot;
273+static bool xen_legacy_crash;
272274 void xen_emergency_restart(void)
273275 {
274− xen_reboot(SHUTDOWN_reboot);
276+ xen_reboot(reboot_reason);
275277 }
276278
277279 static int
278280 xen_panic_event(struct notifier_block *this, unsigned long event, void *ptr)
279281 {
280− if (!kexec_crash_loaded())
281− xen_reboot(SHUTDOWN_crash);
282+ if (!kexec_crash_loaded()) {
283+ if (xen_legacy_crash)
284+ xen_reboot(SHUTDOWN_crash);
285+
286+ reboot_reason = SHUTDOWN_crash;
287+
288+ /*
289+ * If panic_timeout==0 then we are supposed to wait forever.
290+ * However, to preserve original dom0 behavior we have to drop
291+ * into hypervisor. (domU behavior is controlled by its
292+ * config file)
293+ */
294+ if (panic_timeout == 0)
295+ panic_timeout = -1;
296+ }
282297 return NOTIFY_DONE;
283298 }
284299
300+static int __init parse_xen_legacy_crash(char *arg)
301+{
302+ xen_legacy_crash = true;
303+ return 0;
304+}
305+early_param("xen_legacy_crash", parse_xen_legacy_crash);
306+
285307 static struct notifier_block xen_panic_block = {
286308 .notifier_call = xen_panic_event,
287309 .priority = INT_MIN
arch/x86/xen/enlighten_pv.c+8−0
@@ -117,6 +117,14 @@ static void __init xen_banner(void) · 116 unmodified lines
117117 printk(KERN_INFO "Xen version: %d.%d%s%s\n",
118118 version >> 16, version & 0xffff, extra.extraversion,
119119 xen_feature(XENFEAT_mmu_pt_update_preserve_ad) ? " (preserve-AD)" : "");
120+
121+#ifdef CONFIG_X86_32
122+ pr_warn("WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! WARNING!\n"
123+ "Support for running as 32-bit PV-guest under Xen will soon be removed\n"
124+ "from the Linux kernel!\n"
125+ "Please use either a 64-bit kernel or switch to HVM or PVH mode!\n"
126+ "WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! WARNING!\n");
127+#endif
120128 }
121129
122130 static void __init xen_pv_init_platform(void)
arch/xtensa/boot/dts/virt.dts+1−1
@@ -56,7 +56,7 @@ · 55 unmodified lines
5656 reg = <0xf0100000 0x03f00000>;
5757
5858 // BUS_ADDRESS(3) CPU_PHYSICAL(1) SIZE(2)
59− ranges = <0x01000000 0x0 0xf0000000 0xf0000000 0x0 0x00010000>,
59+ ranges = <0x01000000 0x0 0x00000000 0xf0000000 0x0 0x00010000>,
6060 <0x02000000 0x0 0xf4000000 0xf4000000 0x0 0x08000000>;
6161
6262 // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(2)
arch/xtensa/include/asm/bitops.h+1−1
@@ -148,7 +148,7 @@ static inline void change_bit(unsigned int bit, volatile unsigned long *p) · 147 unmodified lines
148148 " getex %0\n"
149149 " beqz %0, 1b\n"
150150 : "=&a" (tmp)
151− : "a" (~mask), "a" (p)
151+ : "a" (mask), "a" (p)
152152 : "memory");
153153 }
154154
arch/xtensa/include/asm/uaccess.h+53−41
@@ -100,7 +100,7 @@ do { \ · 99 unmodified lines
100100 case 4: __put_user_asm(x, ptr, retval, 4, "s32i", __cb); break; \
101101 case 8: { \
102102 __typeof__(*ptr) __v64 = x; \
103− retval = __copy_to_user(ptr, &__v64, 8); \
103+ retval = __copy_to_user(ptr, &__v64, 8) ? -EFAULT : 0; \
104104 break; \
105105 } \
106106 default: __put_user_bad(); \
@@ -132,14 +132,14 @@ do { \ · 25 unmodified lines
132132 #define __check_align_1 ""
133133
134134 #define __check_align_2 \
135− " _bbci.l %3, 0, 1f \n" \
136− " movi %0, %4 \n" \
135+ " _bbci.l %[addr], 0, 1f \n" \
136+ " movi %[err], %[efault] \n" \
137137 " _j 2f \n"
138138
139139 #define __check_align_4 \
140− " _bbsi.l %3, 0, 0f \n" \
141− " _bbci.l %3, 1, 1f \n" \
142− "0: movi %0, %4 \n" \
140+ " _bbsi.l %[addr], 0, 0f \n" \
141+ " _bbci.l %[addr], 1, 1f \n" \
142+ "0: movi %[err], %[efault] \n" \
143143 " _j 2f \n"
144144
145145
@@ -151,40 +151,40 @@ do { \ · 5 unmodified lines
151151 * WARNING: If you modify this macro at all, verify that the
152152 * __check_align_* macros still work.
153153 */
154−#define __put_user_asm(x, addr, err, align, insn, cb) \
154+#define __put_user_asm(x_, addr_, err_, align, insn, cb)\
155155 __asm__ __volatile__( \
156156 __check_align_##align \
157− "1: "insn" %2, %3, 0 \n" \
157+ "1: "insn" %[x], %[addr], 0 \n" \
158158 "2: \n" \
159159 " .section .fixup,\"ax\" \n" \
160160 " .align 4 \n" \
161161 " .literal_position \n" \
162162 "5: \n" \
163− " movi %1, 2b \n" \
164− " movi %0, %4 \n" \
165− " jx %1 \n" \
163+ " movi %[tmp], 2b \n" \
164+ " movi %[err], %[efault] \n" \
165+ " jx %[tmp] \n" \
166166 " .previous \n" \
167167 " .section __ex_table,\"a\" \n" \
168168 " .long 1b, 5b \n" \
169169 " .previous" \
170− :"=r" (err), "=r" (cb) \
171− :"r" ((int)(x)), "r" (addr), "i" (-EFAULT), "0" (err))
170+ :[err] "+r"(err_), [tmp] "=r"(cb) \
171+ :[x] "r"(x_), [addr] "r"(addr_), [efault] "i"(-EFAULT))
172172
173173 #define __get_user_nocheck(x, ptr, size) \
174174 ({ \
175− long __gu_err, __gu_val; \
176− __get_user_size(__gu_val, (ptr), (size), __gu_err); \
177− (x) = (__force __typeof__(*(ptr)))__gu_val; \
175+ long __gu_err; \
176+ __get_user_size((x), (ptr), (size), __gu_err); \
178177 __gu_err; \
179178 })
180179
181180 #define __get_user_check(x, ptr, size) \
182181 ({ \
183− long __gu_err = -EFAULT, __gu_val = 0; \
182+ long __gu_err = -EFAULT; \
184183 const __typeof__(*(ptr)) *__gu_addr = (ptr); \
185− if (access_ok(__gu_addr, size)) \
186− __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
187− (x) = (__force __typeof__(*(ptr)))__gu_val; \
184+ if (access_ok(__gu_addr, size)) \
185+ __get_user_size((x), __gu_addr, (size), __gu_err); \
186+ else \
187+ (x) = 0; \
188188 __gu_err; \
189189 })
190190
@@ -198,8 +198,17 @@ do { \ · 7 unmodified lines
198198 case 1: __get_user_asm(x, ptr, retval, 1, "l8ui", __cb); break;\
199199 case 2: __get_user_asm(x, ptr, retval, 2, "l16ui", __cb); break;\
200200 case 4: __get_user_asm(x, ptr, retval, 4, "l32i", __cb); break;\
201− case 8: retval = __copy_from_user(&x, ptr, 8); break; \
202− default: (x) = __get_user_bad(); \
201+ case 8: { \
202+ u64 __x; \
203+ if (unlikely(__copy_from_user(&__x, ptr, 8))) { \
204+ retval = -EFAULT; \
205+ (x) = 0; \
206+ } else { \
207+ (x) = *(__force __typeof__((ptr)))&__x; \
208+ } \
209+ break; \
210+ } \
211+ default: (x) = 0; __get_user_bad(); \
203212 } \
204213 } while (0)
205214
@@ -208,25 +217,28 @@ do { \ · 2 unmodified lines
208217 * WARNING: If you modify this macro at all, verify that the
209218 * __check_align_* macros still work.
210219 */
211−#define __get_user_asm(x, addr, err, align, insn, cb) \
212−__asm__ __volatile__( \
213− __check_align_##align \
214− "1: "insn" %2, %3, 0 \n" \
215− "2: \n" \
216− " .section .fixup,\"ax\" \n" \
217− " .align 4 \n" \
218− " .literal_position \n" \
219− "5: \n" \
220− " movi %1, 2b \n" \
221− " movi %2, 0 \n" \
222− " movi %0, %4 \n" \
223− " jx %1 \n" \
224− " .previous \n" \
225− " .section __ex_table,\"a\" \n" \
226− " .long 1b, 5b \n" \
227− " .previous" \
228− :"=r" (err), "=r" (cb), "=r" (x) \
229− :"r" (addr), "i" (-EFAULT), "0" (err))
220+#define __get_user_asm(x_, addr_, err_, align, insn, cb) \
221+do { \
222+ u32 __x = 0; \
223+ __asm__ __volatile__( \
224+ __check_align_##align \
225+ "1: "insn" %[x], %[addr], 0 \n" \
226+ "2: \n" \
227+ " .section .fixup,\"ax\" \n" \
228+ " .align 4 \n" \
229+ " .literal_position \n" \
230+ "5: \n" \
231+ " movi %[tmp], 2b \n" \
232+ " movi %[err], %[efault] \n" \
233+ " jx %[tmp] \n" \
234+ " .previous \n" \
235+ " .section __ex_table,\"a\" \n" \
236+ " .long 1b, 5b \n" \
237+ " .previous" \
238+ :[err] "+r"(err_), [tmp] "=r"(cb), [x] "+r"(__x) \
239+ :[addr] "r"(addr_), [efault] "i"(-EFAULT)); \
240+ (x_) = (__force __typeof__(*(addr_)))__x; \
241+} while (0)
230242
231243
232244 /*
arch/xtensa/kernel/xtensa_ksyms.c+0−7
@@ -119,13 +119,6 @@ EXPORT_SYMBOL(__invalidate_icache_range); · 118 unmodified lines
119119 // FIXME EXPORT_SYMBOL(screen_info);
120120 #endif
121121
122−EXPORT_SYMBOL(outsb);
123−EXPORT_SYMBOL(outsw);
124−EXPORT_SYMBOL(outsl);
125−EXPORT_SYMBOL(insb);
126−EXPORT_SYMBOL(insw);
127−EXPORT_SYMBOL(insl);
128−
129122 extern long common_exception_return;
130123 EXPORT_SYMBOL(common_exception_return);
131124
block/blk-cgroup.c+59−23
@@ -934,9 +934,14 @@ static int blkcg_print_stat(struct seq_file *sf, void *v) · 933 unmodified lines
934934 int i;
935935 bool has_stats = false;
936936
937+ spin_lock_irq(&blkg->q->queue_lock);
938+
939+ if (!blkg->online)
940+ goto skip;
941+
937942 dname = blkg_dev_name(blkg);
938943 if (!dname)
939− continue;
944+ goto skip;
940945
941946 /*
942947 * Hooray string manipulation, count is the size written NOT
@@ -946,8 +951,6 @@ static int blkcg_print_stat(struct seq_file *sf, void *v) · 3 unmodified lines
946951 */
947952 off += scnprintf(buf+off, size-off, "%s ", dname);
948953
949− spin_lock_irq(&blkg->q->queue_lock);
950−
951954 blkg_rwstat_recursive_sum(blkg, NULL,
952955 offsetof(struct blkcg_gq, stat_bytes), &rwstat);
953956 rbytes = rwstat.cnt[BLKG_RWSTAT_READ];
@@ -960,8 +963,6 @@ static int blkcg_print_stat(struct seq_file *sf, void *v) · 6 unmodified lines
960963 wios = rwstat.cnt[BLKG_RWSTAT_WRITE];
961964 dios = rwstat.cnt[BLKG_RWSTAT_DISCARD];
962965
963− spin_unlock_irq(&blkg->q->queue_lock);
964−
965966 if (rbytes || wbytes || rios || wios) {
966967 has_stats = true;
967968 off += scnprintf(buf+off, size-off,
@@ -999,6 +1000,8 @@ static int blkcg_print_stat(struct seq_file *sf, void *v) · 31 unmodified lines
9991000 seq_commit(sf, -1);
10001001 }
10011002 }
1003+ skip:
1004+ spin_unlock_irq(&blkg->q->queue_lock);
10021005 }
10031006
10041007 rcu_read_unlock();
@@ -1362,7 +1365,7 @@ int blkcg_activate_policy(struct request_queue *q, · 357 unmodified lines
13621365 const struct blkcg_policy *pol)
13631366 {
13641367 struct blkg_policy_data *pd_prealloc = NULL;
1365− struct blkcg_gq *blkg;
1368+ struct blkcg_gq *blkg, *pinned_blkg = NULL;
13661369 int ret;
13671370
13681371 if (blkcg_policy_enabled(q, pol))
@@ -1370,49 +1373,82 @@ int blkcg_activate_policy(struct request_queue *q, · 1 unmodified line
13701373
13711374 if (queue_is_mq(q))
13721375 blk_mq_freeze_queue(q);
1373−pd_prealloc:
1374− if (!pd_prealloc) {
1375− pd_prealloc = pol->pd_alloc_fn(GFP_KERNEL, q, &blkcg_root);
1376− if (!pd_prealloc) {
1377− ret = -ENOMEM;
1378− goto out_bypass_end;
1379− }
1380− }
1381−
1376+retry:
13821377 spin_lock_irq(&q->queue_lock);
13831378
1384− /* blkg_list is pushed at the head, reverse walk to init parents first */
1379+ /* blkg_list is pushed at the head, reverse walk to allocate parents first */
13851380 list_for_each_entry_reverse(blkg, &q->blkg_list, q_node) {
13861381 struct blkg_policy_data *pd;
13871382
13881383 if (blkg->pd[pol->plid])
13891384 continue;
13901385
1391− pd = pol->pd_alloc_fn(GFP_NOWAIT | __GFP_NOWARN, q, &blkcg_root);
1392− if (!pd)
1393− swap(pd, pd_prealloc);
1386+ /* If prealloc matches, use it; otherwise try GFP_NOWAIT */
1387+ if (blkg == pinned_blkg) {
1388+ pd = pd_prealloc;
1389+ pd_prealloc = NULL;
1390+ } else {
1391+ pd = pol->pd_alloc_fn(GFP_NOWAIT | __GFP_NOWARN, q,
1392+ blkg->blkcg);
1393+ }
1394+
13941395 if (!pd) {
1396+ /*
1397+ * GFP_NOWAIT failed. Free the existing one and
1398+ * prealloc for @blkg w/ GFP_KERNEL.
1399+ */
1400+ if (pinned_blkg)
1401+ blkg_put(pinned_blkg);
1402+ blkg_get(blkg);
1403+ pinned_blkg = blkg;
1404+
13951405 spin_unlock_irq(&q->queue_lock);
1396− goto pd_prealloc;
1406+
1407+ if (pd_prealloc)
1408+ pol->pd_free_fn(pd_prealloc);
1409+ pd_prealloc = pol->pd_alloc_fn(GFP_KERNEL, q,
1410+ blkg->blkcg);
1411+ if (pd_prealloc)
1412+ goto retry;
1413+ else
1414+ goto enomem;
13971415 }
13981416
13991417 blkg->pd[pol->plid] = pd;
14001418 pd->blkg = blkg;
14011419 pd->plid = pol->plid;
1402− if (pol->pd_init_fn)
1403− pol->pd_init_fn(pd);
14041420 }
14051421
1422+ /* all allocated, init in the same order */
1423+ if (pol->pd_init_fn)
1424+ list_for_each_entry_reverse(blkg, &q->blkg_list, q_node)
1425+ pol->pd_init_fn(blkg->pd[pol->plid]);
1426+
14061427 __set_bit(pol->plid, q->blkcg_pols);
14071428 ret = 0;
14081429
14091430 spin_unlock_irq(&q->queue_lock);
1410−out_bypass_end:
1431+out:
14111432 if (queue_is_mq(q))
14121433 blk_mq_unfreeze_queue(q);
1434+ if (pinned_blkg)
1435+ blkg_put(pinned_blkg);
14131436 if (pd_prealloc)
14141437 pol->pd_free_fn(pd_prealloc);
14151438 return ret;
1439+
1440+enomem:
1441+ /* alloc failed, nothing's initialized yet, free everything */
1442+ spin_lock_irq(&q->queue_lock);
1443+ list_for_each_entry(blkg, &q->blkg_list, q_node) {
1444+ if (blkg->pd[pol->plid]) {
1445+ pol->pd_free_fn(blkg->pd[pol->plid]);
1446+ blkg->pd[pol->plid] = NULL;
1447+ }
1448+ }
1449+ spin_unlock_irq(&q->queue_lock);
1450+ ret = -ENOMEM;
1451+ goto out;
14161452 }
14171453 EXPORT_SYMBOL_GPL(blkcg_activate_policy);
14181454
block/blk-iocost.c+2−2
@@ -2110,10 +2110,10 @@ static ssize_t ioc_weight_write(struct kernfs_open_file *of, char *buf, · 2109 unmodified lines
21102110 goto einval;
21112111 }
21122112
2113− spin_lock_irq(&iocg->ioc->lock);
2113+ spin_lock(&iocg->ioc->lock);
21142114 iocg->cfg_weight = v;
21152115 weight_updated(iocg);
2116− spin_unlock_irq(&iocg->ioc->lock);
2116+ spin_unlock(&iocg->ioc->lock);
21172117
21182118 blkg_conf_finish(&ctx);
21192119 return nbytes;
block/blk-rq-qos.c+9−5
@@ -160,24 +160,27 @@ bool rq_depth_calc_max_depth(struct rq_depth *rqd) · 159 unmodified lines
160160 return ret;
161161 }
162162
163−void rq_depth_scale_up(struct rq_depth *rqd)
163+/* Returns true on success and false if scaling up wasn't possible */
164+bool rq_depth_scale_up(struct rq_depth *rqd)
164165 {
165166 /*
166167 * Hit max in previous round, stop here
167168 */
168169 if (rqd->scaled_max)
169− return;
170+ return false;
170171
171172 rqd->scale_step--;
172173
173174 rqd->scaled_max = rq_depth_calc_max_depth(rqd);
175+ return true;
174176 }
175177
176178 /*
177179 * Scale rwb down. If 'hard_throttle' is set, do it quicker, since we
178− * had a latency violation.
180+ * had a latency violation. Returns true on success and returns false if
181+ * scaling down wasn't possible.
179182 */
180−void rq_depth_scale_down(struct rq_depth *rqd, bool hard_throttle)
183+bool rq_depth_scale_down(struct rq_depth *rqd, bool hard_throttle)
181184 {
182185 /*
183186 * Stop scaling down when we've hit the limit. This also prevents
@@ -185,7 +188,7 @@ void rq_depth_scale_down(struct rq_depth *rqd, bool hard_throttle) · 1 unmodified line
185188 * keep up.
186189 */
187190 if (rqd->max_depth == 1)
188− return;
191+ return false;
189192
190193 if (rqd->scale_step < 0 && hard_throttle)
191194 rqd->scale_step = 0;
@@ -194,6 +197,7 @@ void rq_depth_scale_down(struct rq_depth *rqd, bool hard_throttle) · 2 unmodified lines
194197
195198 rqd->scaled_max = false;
196199 rq_depth_calc_max_depth(rqd);
200+ return true;
197201 }
198202
199203 struct rq_qos_wait_data {
block/blk-rq-qos.h+7−10
@@ -108,16 +108,13 @@ static inline void rq_qos_add(struct request_queue *q, struct rq_qos *rqos) · 107 unmodified lines
108108
109109 static inline void rq_qos_del(struct request_queue *q, struct rq_qos *rqos)
110110 {
111− struct rq_qos *cur, *prev = NULL;
112− for (cur = q->rq_qos; cur; cur = cur->next) {
113− if (cur == rqos) {
114− if (prev)
115− prev->next = rqos->next;
116− else
117− q->rq_qos = cur;
111+ struct rq_qos **cur;
112+
113+ for (cur = &q->rq_qos; *cur; cur = &(*cur)->next) {
114+ if (*cur == rqos) {
115+ *cur = rqos->next;
118116 break;
119117 }
120− prev = cur;
121118 }
122119
123120 blk_mq_debugfs_unregister_rqos(rqos);
@@ -130,8 +127,8 @@ void rq_qos_wait(struct rq_wait *rqw, void *private_data, · 6 unmodified lines
130127 acquire_inflight_cb_t *acquire_inflight_cb,
131128 cleanup_cb_t *cleanup_cb);
132129 bool rq_wait_inc_below(struct rq_wait *rq_wait, unsigned int limit);
133−void rq_depth_scale_up(struct rq_depth *rqd);
134−void rq_depth_scale_down(struct rq_depth *rqd, bool hard_throttle);
130+bool rq_depth_scale_up(struct rq_depth *rqd);
131+bool rq_depth_scale_down(struct rq_depth *rqd, bool hard_throttle);
135132 bool rq_depth_calc_max_depth(struct rq_depth *rqd);
136133
137134 void __rq_qos_cleanup(struct rq_qos *rqos, struct bio *bio);
block/blk-wbt.c+4−2
@@ -308,7 +308,8 @@ static void calc_wb_limits(struct rq_wb *rwb) · 307 unmodified lines
308308
309309 static void scale_up(struct rq_wb *rwb)
310310 {
311− rq_depth_scale_up(&rwb->rq_depth);
311+ if (!rq_depth_scale_up(&rwb->rq_depth))
312+ return;
312313 calc_wb_limits(rwb);
313314 rwb->unknown_cnt = 0;
314315 rwb_wake_all(rwb);
@@ -317,7 +318,8 @@ static void scale_up(struct rq_wb *rwb) · 2 unmodified lines
317318
318319 static void scale_down(struct rq_wb *rwb, bool hard_throttle)
319320 {
320− rq_depth_scale_down(&rwb->rq_depth, hard_throttle);
321+ if (!rq_depth_scale_down(&rwb->rq_depth, hard_throttle))
322+ return;
321323 calc_wb_limits(rwb);
322324 rwb->unknown_cnt = 0;
323325 rwb_trace_step(rwb, "scale down");
block/elevator.c+2−1
@@ -616,7 +616,8 @@ out: · 615 unmodified lines
616616
617617 static inline bool elv_support_iosched(struct request_queue *q)
618618 {
619− if (q->tag_set && (q->tag_set->flags & BLK_MQ_F_NO_SCHED))
619+ if (!q->mq_ops ||
620+ (q->tag_set && (q->tag_set->flags & BLK_MQ_F_NO_SCHED)))
620621 return false;
621622 return true;
622623 }
drivers/acpi/cppc_acpi.c+1−1
@@ -905,8 +905,8 @@ void acpi_cppc_processor_exit(struct acpi_processor *pr) · 904 unmodified lines
905905 pcc_data[pcc_ss_id]->refcount--;
906906 if (!pcc_data[pcc_ss_id]->refcount) {
907907 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
908− pcc_data[pcc_ss_id]->pcc_channel_acquired = 0;
909908 kfree(pcc_data[pcc_ss_id]);
909+ pcc_data[pcc_ss_id] = NULL;
910910 }
911911 }
912912 }
drivers/acpi/hmat/hmat.c+1−1
@@ -403,7 +403,7 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade · 402 unmodified lines
403403 pr_info("HMAT: Memory Flags:%04x Processor Domain:%d Memory Domain:%d\n",
404404 p->flags, p->processor_PD, p->memory_PD);
405405
406− if (p->flags & ACPI_HMAT_MEMORY_PD_VALID) {
406+ if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
407407 target = find_mem_target(p->memory_PD);
408408 if (!target) {
409409 pr_debug("HMAT: Memory Domain missing from SRAT\n");
drivers/acpi/nfit/core.c+1−1
@@ -1322,7 +1322,7 @@ static ssize_t scrub_show(struct device *dev, · 1321 unmodified lines
13221322 nfit_device_lock(dev);
13231323 nd_desc = dev_get_drvdata(dev);
13241324 if (!nd_desc) {
1325− device_unlock(dev);
1325+ nfit_device_unlock(dev);
13261326 return rc;
13271327 }
13281328 acpi_desc = to_acpi_desc(nd_desc);
drivers/acpi/processor_driver.c+4−5
@@ -290,14 +290,13 @@ static int acpi_processor_notifier(struct notifier_block *nb, · 289 unmodified lines
290290 unsigned long event, void *data)
291291 {
292292 struct cpufreq_policy *policy = data;
293− int cpu = policy->cpu;
294293
295294 if (event == CPUFREQ_CREATE_POLICY) {
296− acpi_thermal_cpufreq_init(cpu);
297− acpi_processor_ppc_init(cpu);
295+ acpi_thermal_cpufreq_init(policy);
296+ acpi_processor_ppc_init(policy);
298297 } else if (event == CPUFREQ_REMOVE_POLICY) {
299− acpi_processor_ppc_exit(cpu);
300− acpi_thermal_cpufreq_exit(cpu);
298+ acpi_processor_ppc_exit(policy);
299+ acpi_thermal_cpufreq_exit(policy);
301300 }
302301
303302 return 0;
drivers/acpi/processor_perflib.c+25−15
@@ -81,10 +81,10 @@ static int acpi_processor_get_platform_limit(struct acpi_processor *pr) · 80 unmodified lines
8181 pr->performance_platform_limit = (int)ppc;
8282
8383 if (ppc >= pr->performance->state_count ||
84− unlikely(!dev_pm_qos_request_active(&pr->perflib_req)))
84+ unlikely(!freq_qos_request_active(&pr->perflib_req)))
8585 return 0;
8686
87− ret = dev_pm_qos_update_request(&pr->perflib_req,
87+ ret = freq_qos_update_request(&pr->perflib_req,
8888 pr->performance->states[ppc].core_frequency * 1000);
8989 if (ret < 0) {
9090 pr_warn("Failed to update perflib freq constraint: CPU%d (%d)\n",
@@ -157,26 +157,36 @@ void acpi_processor_ignore_ppc_init(void) · 66 unmodified lines
157157 ignore_ppc = 0;
158158 }
159159
160−void acpi_processor_ppc_init(int cpu)
160+void acpi_processor_ppc_init(struct cpufreq_policy *policy)
161161 {
162− struct acpi_processor *pr = per_cpu(processors, cpu);
163− int ret;
162+ unsigned int cpu;
164163
165− ret = dev_pm_qos_add_request(get_cpu_device(cpu),
166− &pr->perflib_req, DEV_PM_QOS_MAX_FREQUENCY,
167− INT_MAX);
168− if (ret < 0) {
169− pr_err("Failed to add freq constraint for CPU%d (%d)\n", cpu,
170− ret);
171− return;
164+ for_each_cpu(cpu, policy->related_cpus) {
165+ struct acpi_processor *pr = per_cpu(processors, cpu);
166+ int ret;
167+
168+ if (!pr)
169+ continue;
170+
171+ ret = freq_qos_add_request(&policy->constraints,
172+ &pr->perflib_req,
173+ FREQ_QOS_MAX, INT_MAX);
174+ if (ret < 0)
175+ pr_err("Failed to add freq constraint for CPU%d (%d)\n",
176+ cpu, ret);
172177 }
173178 }
174179
175−void acpi_processor_ppc_exit(int cpu)
180+void acpi_processor_ppc_exit(struct cpufreq_policy *policy)
176181 {
177− struct acpi_processor *pr = per_cpu(processors, cpu);
182+ unsigned int cpu;
178183
179− dev_pm_qos_remove_request(&pr->perflib_req);
184+ for_each_cpu(cpu, policy->related_cpus) {
185+ struct acpi_processor *pr = per_cpu(processors, cpu);
186+
187+ if (pr)
188+ freq_qos_remove_request(&pr->perflib_req);
189+ }
180190 }
181191
182192 static int acpi_processor_get_performance_control(struct acpi_processor *pr)
drivers/acpi/processor_thermal.c+26−16
@@ -105,7 +105,7 @@ static int cpufreq_set_cur_state(unsigned int cpu, int state) · 104 unmodified lines
105105
106106 pr = per_cpu(processors, i);
107107
108− if (unlikely(!dev_pm_qos_request_active(&pr->thermal_req)))
108+ if (unlikely(!freq_qos_request_active(&pr->thermal_req)))
109109 continue;
110110
111111 policy = cpufreq_cpu_get(i);
@@ -116,7 +116,7 @@ static int cpufreq_set_cur_state(unsigned int cpu, int state) · 4 unmodified lines
116116
117117 cpufreq_cpu_put(policy);
118118
119− ret = dev_pm_qos_update_request(&pr->thermal_req, max_freq);
119+ ret = freq_qos_update_request(&pr->thermal_req, max_freq);
120120 if (ret < 0) {
121121 pr_warn("Failed to update thermal freq constraint: CPU%d (%d)\n",
122122 pr->id, ret);
@@ -125,26 +125,36 @@ static int cpufreq_set_cur_state(unsigned int cpu, int state) · 2 unmodified lines
125125 return 0;
126126 }
127127
128−void acpi_thermal_cpufreq_init(int cpu)
128+void acpi_thermal_cpufreq_init(struct cpufreq_policy *policy)
129129 {
130− struct acpi_processor *pr = per_cpu(processors, cpu);
131− int ret;
132−
133− ret = dev_pm_qos_add_request(get_cpu_device(cpu),
134− &pr->thermal_req, DEV_PM_QOS_MAX_FREQUENCY,
135− INT_MAX);
136− if (ret < 0) {
137− pr_err("Failed to add freq constraint for CPU%d (%d)\n", cpu,
138− ret);
139− return;
130+ unsigned int cpu;
131+
132+ for_each_cpu(cpu, policy->related_cpus) {
133+ struct acpi_processor *pr = per_cpu(processors, cpu);
134+ int ret;
135+
136+ if (!pr)
137+ continue;
138+
139+ ret = freq_qos_add_request(&policy->constraints,
140+ &pr->thermal_req,
141+ FREQ_QOS_MAX, INT_MAX);
142+ if (ret < 0)
143+ pr_err("Failed to add freq constraint for CPU%d (%d)\n",
144+ cpu, ret);
140145 }
141146 }
142147
143−void acpi_thermal_cpufreq_exit(int cpu)
148+void acpi_thermal_cpufreq_exit(struct cpufreq_policy *policy)
144149 {
145− struct acpi_processor *pr = per_cpu(processors, cpu);
150+ unsigned int cpu;
151+
152+ for_each_cpu(cpu, policy->related_cpus) {
153+ struct acpi_processor *pr = per_cpu(processors, policy->cpu);
146154
147− dev_pm_qos_remove_request(&pr->thermal_req);
155+ if (pr)
156+ freq_qos_remove_request(&pr->thermal_req);
157+ }
148158 }
149159 #else /* ! CONFIG_CPU_FREQ */
150160 static int cpufreq_get_max_state(unsigned int cpu)
drivers/acpi/sleep.c+0−13
@@ -361,19 +361,6 @@ static const struct dmi_system_id acpisleep_dmi_table[] __initconst = { · 360 unmodified lines
361361 DMI_MATCH(DMI_PRODUCT_NAME, "80E3"),
362362 },
363363 },
364− /*
365− * https://bugzilla.kernel.org/show_bug.cgi?id=196907
366− * Some Dell XPS13 9360 cannot do suspend-to-idle using the Low Power
367− * S0 Idle firmware interface.
368− */
369− {
370− .callback = init_default_s3,
371− .ident = "Dell XPS13 9360",
372− .matches = {
373− DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
374− DMI_MATCH(DMI_PRODUCT_NAME, "XPS 13 9360"),
375− },
376− },
377364 /*
378365 * ThinkPad X1 Tablet(2016) cannot do suspend-to-idle using
379366 * the Low Power S0 Idle firmware interface (see
drivers/amba/bus.c+11−3
@@ -409,9 +409,11 @@ static int amba_device_try_add(struct amba_device *dev, struct resource *parent) · 408 unmodified lines
409409 */
410410 rstc = of_reset_control_array_get_optional_shared(dev->dev.of_node);
411411 if (IS_ERR(rstc)) {
412− if (PTR_ERR(rstc) != -EPROBE_DEFER)
413− dev_err(&dev->dev, "Can't get amba reset!\n");
414− return PTR_ERR(rstc);
412+ ret = PTR_ERR(rstc);
413+ if (ret != -EPROBE_DEFER)
414+ dev_err(&dev->dev, "can't get reset: %d\n",
415+ ret);
416+ goto err_reset;
415417 }
416418 reset_control_deassert(rstc);
417419 reset_control_put(rstc);
@@ -472,6 +474,12 @@ static int amba_device_try_add(struct amba_device *dev, struct resource *parent) · 54 unmodified lines
472474 release_resource(&dev->res);
473475 err_out:
474476 return ret;
477+
478+ err_reset:
479+ amba_put_disable_pclk(dev);
480+ iounmap(tmp);
481+ dev_pm_domain_detach(&dev->dev, true);
482+ goto err_release;
475483 }
476484
477485 /*
drivers/android/binder.c+3−8
@@ -57,6 +57,7 @@ · 56 unmodified lines
5757 #include <linux/sched/signal.h>
5858 #include <linux/sched/mm.h>
5959 #include <linux/seq_file.h>
60+#include <linux/string.h>
6061 #include <linux/uaccess.h>
6162 #include <linux/pid_namespace.h>
6263 #include <linux/security.h>
@@ -66,6 +67,7 @@ · 3 unmodified lines
6667 #include <linux/task_work.h>
6768
6869 #include <uapi/linux/android/binder.h>
70+#include <uapi/linux/android/binderfs.h>
6971
7072 #include <asm/cacheflush.h>
7173
@@ -95,10 +97,6 @@ DEFINE_SHOW_ATTRIBUTE(proc); · 23 unmodified lines
9597 #define SZ_1K 0x400
9698 #endif
9799
98−#ifndef SZ_4M
99−#define SZ_4M 0x400000
100−#endif
101−
102100 #define FORBIDDEN_MMAP_FLAGS (VM_WRITE)
103101
104102 enum {
@@ -2876,7 +2874,7 @@ static void binder_transaction(struct binder_proc *proc, · 2771 unmodified lines
28762874 e->target_handle = tr->target.handle;
28772875 e->data_size = tr->data_size;
28782876 e->offsets_size = tr->offsets_size;
2879− e->context_name = proc->context->name;
2877+ strscpy(e->context_name, proc->context->name, BINDERFS_MAX_NAME);
28802878
28812879 if (reply) {
28822880 binder_inner_proc_lock(proc);
@@ -5175,9 +5173,6 @@ static int binder_mmap(struct file *filp, struct vm_area_struct *vma) · 2292 unmodified lines
51755173 if (proc->tsk != current->group_leader)
51765174 return -EINVAL;
51775175
5178− if ((vma->vm_end - vma->vm_start) > SZ_4M)
5179− vma->vm_end = vma->vm_start + SZ_4M;
5180−
51815176 binder_debug(BINDER_DEBUG_OPEN_CLOSE,
51825177 "%s: %d %lx-%lx (%ld K) vma %lx pagep %lx\n",
51835178 __func__, proc->pid, vma->vm_start, vma->vm_end,
drivers/android/binder_alloc.c+5−3
@@ -22,6 +22,7 @@ · 21 unmodified lines
2222 #include <asm/cacheflush.h>
2323 #include <linux/uaccess.h>
2424 #include <linux/highmem.h>
25+#include <linux/sizes.h>
2526 #include "binder_alloc.h"
2627 #include "binder_trace.h"
2728
@@ -156,7 +157,7 @@ static struct binder_buffer *binder_alloc_prepare_to_free_locked( · 128 unmodified lines
156157 }
157158
158159 /**
159− * binder_alloc_buffer_lookup() - get buffer given user ptr
160+ * binder_alloc_prepare_to_free() - get buffer given user ptr
160161 * @alloc: binder_alloc for this proc
161162 * @user_ptr: User pointer to buffer data
162163 *
@@ -689,7 +690,9 @@ int binder_alloc_mmap_handler(struct binder_alloc *alloc, · 526 unmodified lines
689690 alloc->buffer = (void __user *)vma->vm_start;
690691 mutex_unlock(&binder_alloc_mmap_lock);
691692
692− alloc->pages = kcalloc((vma->vm_end - vma->vm_start) / PAGE_SIZE,
693+ alloc->buffer_size = min_t(unsigned long, vma->vm_end - vma->vm_start,
694+ SZ_4M);
695+ alloc->pages = kcalloc(alloc->buffer_size / PAGE_SIZE,
693696 sizeof(alloc->pages[0]),
694697 GFP_KERNEL);
695698 if (alloc->pages == NULL) {
@@ -697,7 +700,6 @@ int binder_alloc_mmap_handler(struct binder_alloc *alloc, · 1 unmodified line
697700 failure_string = "alloc page array";
698701 goto err_alloc_pages_failed;
699702 }
700− alloc->buffer_size = vma->vm_end - vma->vm_start;
701703
702704 buffer = kzalloc(sizeof(*buffer), GFP_KERNEL);
703705 if (!buffer) {
drivers/android/binder_internal.h+1−1
@@ -130,7 +130,7 @@ struct binder_transaction_log_entry { · 129 unmodified lines
130130 int return_error_line;
131131 uint32_t return_error;
132132 uint32_t return_error_param;
133− const char *context_name;
133+ char context_name[BINDERFS_MAX_NAME + 1];
134134 };
135135
136136 struct binder_transaction_log {
drivers/ata/ahci.c+3−1
@@ -1600,7 +1600,9 @@ static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hp · 1599 unmodified lines
16001600 */
16011601 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
16021602 return;
1603− if (((enum board_ids) id->driver_data) < board_ahci_pcs7)
1603+
1604+ /* Skip applying the quirk on Denverton and beyond */
1605+ if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
16041606 return;
16051607
16061608 /*
drivers/ata/libahci_platform.c+14−24
@@ -153,17 +153,13 @@ int ahci_platform_enable_regulators(struct ahci_host_priv *hpriv) · 152 unmodified lines
153153 {
154154 int rc, i;
155155
156− if (hpriv->ahci_regulator) {
157− rc = regulator_enable(hpriv->ahci_regulator);
158− if (rc)
159− return rc;
160− }
156+ rc = regulator_enable(hpriv->ahci_regulator);
157+ if (rc)
158+ return rc;
161159
162− if (hpriv->phy_regulator) {
163− rc = regulator_enable(hpriv->phy_regulator);
164− if (rc)
165− goto disable_ahci_pwrs;
166− }
160+ rc = regulator_enable(hpriv->phy_regulator);
161+ if (rc)
162+ goto disable_ahci_pwrs;
167163
168164 for (i = 0; i < hpriv->nports; i++) {
169165 if (!hpriv->target_pwrs[i])
@@ -181,11 +177,9 @@ disable_target_pwrs: · 11 unmodified lines
181177 if (hpriv->target_pwrs[i])
182178 regulator_disable(hpriv->target_pwrs[i]);
183179
184− if (hpriv->phy_regulator)
185− regulator_disable(hpriv->phy_regulator);
180+ regulator_disable(hpriv->phy_regulator);
186181 disable_ahci_pwrs:
187− if (hpriv->ahci_regulator)
188− regulator_disable(hpriv->ahci_regulator);
182+ regulator_disable(hpriv->ahci_regulator);
189183 return rc;
190184 }
191185 EXPORT_SYMBOL_GPL(ahci_platform_enable_regulators);
@@ -207,10 +201,8 @@ void ahci_platform_disable_regulators(struct ahci_host_priv *hpriv) · 15 unmodified lines
207201 regulator_disable(hpriv->target_pwrs[i]);
208202 }
209203
210− if (hpriv->ahci_regulator)
211− regulator_disable(hpriv->ahci_regulator);
212− if (hpriv->phy_regulator)
213− regulator_disable(hpriv->phy_regulator);
204+ regulator_disable(hpriv->ahci_regulator);
205+ regulator_disable(hpriv->phy_regulator);
214206 }
215207 EXPORT_SYMBOL_GPL(ahci_platform_disable_regulators);
216208 /**
@@ -359,7 +351,7 @@ static int ahci_platform_get_regulator(struct ahci_host_priv *hpriv, u32 port, · 142 unmodified lines
359351 struct regulator *target_pwr;
360352 int rc = 0;
361353
362− target_pwr = regulator_get_optional(dev, "target");
354+ target_pwr = regulator_get(dev, "target");
363355
364356 if (!IS_ERR(target_pwr))
365357 hpriv->target_pwrs[port] = target_pwr;
@@ -436,16 +428,14 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev, · 70 unmodified lines
436428 hpriv->clks[i] = clk;
437429 }
438430
439− hpriv->ahci_regulator = devm_regulator_get_optional(dev, "ahci");
431+ hpriv->ahci_regulator = devm_regulator_get(dev, "ahci");
440432 if (IS_ERR(hpriv->ahci_regulator)) {
441433 rc = PTR_ERR(hpriv->ahci_regulator);
442− if (rc == -EPROBE_DEFER)
434+ if (rc != 0)
443435 goto err_out;
444− rc = 0;
445− hpriv->ahci_regulator = NULL;
446436 }
447437
448− hpriv->phy_regulator = devm_regulator_get_optional(dev, "phy");
438+ hpriv->phy_regulator = devm_regulator_get(dev, "phy");
449439 if (IS_ERR(hpriv->phy_regulator)) {
450440 rc = PTR_ERR(hpriv->phy_regulator);
451441 if (rc == -EPROBE_DEFER)
drivers/ata/libata-scsi.c+0−21
@@ -4791,27 +4791,6 @@ void ata_scsi_hotplug(struct work_struct *work) · 4790 unmodified lines
47914791 return;
47924792 }
47934793
4794− /*
4795− * XXX - UGLY HACK
4796− *
4797− * The block layer suspend/resume path is fundamentally broken due
4798− * to freezable kthreads and workqueue and may deadlock if a block
4799− * device gets removed while resume is in progress. I don't know
4800− * what the solution is short of removing freezable kthreads and
4801− * workqueues altogether.
4802− *
4803− * The following is an ugly hack to avoid kicking off device
4804− * removal while freezer is active. This is a joke but does avoid
4805− * this particular deadlock scenario.
4806− *
4807− * https://bugzilla.kernel.org/show_bug.cgi?id=62801
4808− * http://marc.info/?l=linux-kernel&m=138695698516487
4809− */
4810−#ifdef CONFIG_FREEZER
4811− while (pm_freezing)
4812− msleep(10);
4813−#endif
4814−
48154794 DPRINTK("ENTER\n");
48164795 mutex_lock(&ap->scsi_scan_mutex);
48174796
drivers/base/core.c+3−0
@@ -9,6 +9,7 @@ · 8 unmodified lines
99 */
1010
1111 #include <linux/acpi.h>
12+#include <linux/cpufreq.h>
1213 #include <linux/device.h>
1314 #include <linux/err.h>
1415 #include <linux/fwnode.h>
@@ -3179,6 +3180,8 @@ void device_shutdown(void) · 3164 unmodified lines
31793180 wait_for_device_probe();
31803181 device_block_probing();
31813182
3183+ cpufreq_suspend();
3184+
31823185 spin_lock(&devices_kset->list_lock);
31833186 /*
31843187 * Walk the devices list backward, shutting down each in turn.
drivers/base/memory.c+3−0
@@ -540,6 +540,9 @@ static ssize_t soft_offline_page_store(struct device *dev, · 539 unmodified lines
540540 pfn >>= PAGE_SHIFT;
541541 if (!pfn_valid(pfn))
542542 return -ENXIO;
543+ /* Only online pages can be soft-offlined (esp., not ZONE_DEVICE). */
544+ if (!pfn_to_online_page(pfn))
545+ return -EIO;
543546 ret = soft_offline_page(pfn_to_page(pfn), 0);
544547 return ret == 0 ? count : ret;
545548 }
drivers/base/platform.c+39−7
@@ -241,12 +241,8 @@ struct resource *platform_get_resource_byname(struct platform_device *dev, · 240 unmodified lines
241241 }
242242 EXPORT_SYMBOL_GPL(platform_get_resource_byname);
243243
244−/**
245− * platform_get_irq_byname - get an IRQ for a device by name
246− * @dev: platform device
247− * @name: IRQ name
248− */
249−int platform_get_irq_byname(struct platform_device *dev, const char *name)
244+static int __platform_get_irq_byname(struct platform_device *dev,
245+ const char *name)
250246 {
251247 struct resource *r;
252248
@@ -262,11 +258,47 @@ int platform_get_irq_byname(struct platform_device *dev, const char *name) · 9 unmodified lines
262258 if (r)
263259 return r->start;
264260
265− dev_err(&dev->dev, "IRQ %s not found\n", name);
266261 return -ENXIO;
267262 }
263+
264+/**
265+ * platform_get_irq_byname - get an IRQ for a device by name
266+ * @dev: platform device
267+ * @name: IRQ name
268+ *
269+ * Get an IRQ like platform_get_irq(), but then by name rather then by index.
270+ *
271+ * Return: IRQ number on success, negative error number on failure.
272+ */
273+int platform_get_irq_byname(struct platform_device *dev, const char *name)
274+{
275+ int ret;
276+
277+ ret = __platform_get_irq_byname(dev, name);
278+ if (ret < 0 && ret != -EPROBE_DEFER)
279+ dev_err(&dev->dev, "IRQ %s not found\n", name);
280+
281+ return ret;
282+}
268283 EXPORT_SYMBOL_GPL(platform_get_irq_byname);
269284
285+/**
286+ * platform_get_irq_byname_optional - get an optional IRQ for a device by name
287+ * @dev: platform device
288+ * @name: IRQ name
289+ *
290+ * Get an optional IRQ by name like platform_get_irq_byname(). Except that it
291+ * does not print an error message if an IRQ can not be obtained.
292+ *
293+ * Return: IRQ number on success, negative error number on failure.
294+ */
295+int platform_get_irq_byname_optional(struct platform_device *dev,
296+ const char *name)
297+{
298+ return __platform_get_irq_byname(dev, name);
299+}
300+EXPORT_SYMBOL_GPL(platform_get_irq_byname_optional);
301+
270302 /**
271303 * platform_add_devices - add a numbers of platform devices
272304 * @devs: array of platform devices to add
drivers/base/power/qos.c+2−68
@@ -115,20 +115,10 @@ s32 dev_pm_qos_read_value(struct device *dev, enum dev_pm_qos_req_type type) · 114 unmodified lines
115115
116116 spin_lock_irqsave(&dev->power.lock, flags);
117117
118− switch (type) {
119− case DEV_PM_QOS_RESUME_LATENCY:
118+ if (type == DEV_PM_QOS_RESUME_LATENCY) {
120119 ret = IS_ERR_OR_NULL(qos) ? PM_QOS_RESUME_LATENCY_NO_CONSTRAINT
121120 : pm_qos_read_value(&qos->resume_latency);
122− break;
123− case DEV_PM_QOS_MIN_FREQUENCY:
124− ret = IS_ERR_OR_NULL(qos) ? PM_QOS_MIN_FREQUENCY_DEFAULT_VALUE
125− : pm_qos_read_value(&qos->min_frequency);
126− break;
127− case DEV_PM_QOS_MAX_FREQUENCY:
128− ret = IS_ERR_OR_NULL(qos) ? PM_QOS_MAX_FREQUENCY_DEFAULT_VALUE
129− : pm_qos_read_value(&qos->max_frequency);
130− break;
131− default:
121+ } else {
132122 WARN_ON(1);
133123 ret = 0;
134124 }
@@ -169,14 +159,6 @@ static int apply_constraint(struct dev_pm_qos_request *req, · 34 unmodified lines
169159 req->dev->power.set_latency_tolerance(req->dev, value);
170160 }
171161 break;
172− case DEV_PM_QOS_MIN_FREQUENCY:
173− ret = pm_qos_update_target(&qos->min_frequency,
174− &req->data.pnode, action, value);
175− break;
176− case DEV_PM_QOS_MAX_FREQUENCY:
177− ret = pm_qos_update_target(&qos->max_frequency,
178− &req->data.pnode, action, value);
179− break;
180162 case DEV_PM_QOS_FLAGS:
181163 ret = pm_qos_update_flags(&qos->flags, &req->data.flr,
182164 action, value);
@@ -227,24 +209,6 @@ static int dev_pm_qos_constraints_allocate(struct device *dev) · 44 unmodified lines
227209 c->no_constraint_value = PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT;
228210 c->type = PM_QOS_MIN;
229211
230− c = &qos->min_frequency;
231− plist_head_init(&c->list);
232− c->target_value = PM_QOS_MIN_FREQUENCY_DEFAULT_VALUE;
233− c->default_value = PM_QOS_MIN_FREQUENCY_DEFAULT_VALUE;
234− c->no_constraint_value = PM_QOS_MIN_FREQUENCY_DEFAULT_VALUE;
235− c->type = PM_QOS_MAX;
236− c->notifiers = ++n;
237− BLOCKING_INIT_NOTIFIER_HEAD(n);
238−
239− c = &qos->max_frequency;
240− plist_head_init(&c->list);
241− c->target_value = PM_QOS_MAX_FREQUENCY_DEFAULT_VALUE;
242− c->default_value = PM_QOS_MAX_FREQUENCY_DEFAULT_VALUE;
243− c->no_constraint_value = PM_QOS_MAX_FREQUENCY_DEFAULT_VALUE;
244− c->type = PM_QOS_MIN;
245− c->notifiers = ++n;
246− BLOCKING_INIT_NOTIFIER_HEAD(n);
247−
248212 INIT_LIST_HEAD(&qos->flags.list);
249213
250214 spin_lock_irq(&dev->power.lock);
@@ -305,18 +269,6 @@ void dev_pm_qos_constraints_destroy(struct device *dev) · 54 unmodified lines
305269 memset(req, 0, sizeof(*req));
306270 }
307271
308− c = &qos->min_frequency;
309− plist_for_each_entry_safe(req, tmp, &c->list, data.pnode) {
310− apply_constraint(req, PM_QOS_REMOVE_REQ, PM_QOS_MIN_FREQUENCY_DEFAULT_VALUE);
311− memset(req, 0, sizeof(*req));
312− }
313−
314− c = &qos->max_frequency;
315− plist_for_each_entry_safe(req, tmp, &c->list, data.pnode) {
316− apply_constraint(req, PM_QOS_REMOVE_REQ, PM_QOS_MAX_FREQUENCY_DEFAULT_VALUE);
317− memset(req, 0, sizeof(*req));
318− }
319−
320272 f = &qos->flags;
321273 list_for_each_entry_safe(req, tmp, &f->list, data.flr.node) {
322274 apply_constraint(req, PM_QOS_REMOVE_REQ, PM_QOS_DEFAULT_VALUE);
@@ -428,8 +380,6 @@ static int __dev_pm_qos_update_request(struct dev_pm_qos_request *req, · 105 unmodified lines
428380 switch(req->type) {
429381 case DEV_PM_QOS_RESUME_LATENCY:
430382 case DEV_PM_QOS_LATENCY_TOLERANCE:
431− case DEV_PM_QOS_MIN_FREQUENCY:
432− case DEV_PM_QOS_MAX_FREQUENCY:
433383 curr_value = req->data.pnode.prio;
434384 break;
435385 case DEV_PM_QOS_FLAGS:
@@ -557,14 +507,6 @@ int dev_pm_qos_add_notifier(struct device *dev, struct notifier_block *notifier, · 121 unmodified lines
557507 ret = blocking_notifier_chain_register(dev->power.qos->resume_latency.notifiers,
558508 notifier);
559509 break;
560− case DEV_PM_QOS_MIN_FREQUENCY:
561− ret = blocking_notifier_chain_register(dev->power.qos->min_frequency.notifiers,
562− notifier);
563− break;
564− case DEV_PM_QOS_MAX_FREQUENCY:
565− ret = blocking_notifier_chain_register(dev->power.qos->max_frequency.notifiers,
566− notifier);
567− break;
568510 default:
569511 WARN_ON(1);
570512 ret = -EINVAL;
@@ -604,14 +546,6 @@ int dev_pm_qos_remove_notifier(struct device *dev, · 33 unmodified lines
604546 ret = blocking_notifier_chain_unregister(dev->power.qos->resume_latency.notifiers,
605547 notifier);
606548 break;
607− case DEV_PM_QOS_MIN_FREQUENCY:
608− ret = blocking_notifier_chain_unregister(dev->power.qos->min_frequency.notifiers,
609− notifier);
610− break;
611− case DEV_PM_QOS_MAX_FREQUENCY:
612− ret = blocking_notifier_chain_unregister(dev->power.qos->max_frequency.notifiers,
613− notifier);
614− break;
615549 default:
616550 WARN_ON(1);
617551 ret = -EINVAL;
drivers/block/drbd/drbd_main.c+0−1
@@ -786,7 +786,6 @@ int __drbd_send_protocol(struct drbd_connection *connection, enum drbd_packet cm · 785 unmodified lines
786786
787787 if (nc->tentative && connection->agreed_pro_version < 92) {
788788 rcu_read_unlock();
789− mutex_unlock(&sock->mutex);
790789 drbd_err(connection, "--dry-run is not supported by peer");
791790 return -EOPNOTSUPP;
792791 }
drivers/block/nbd.c+35−8
@@ -248,8 +248,8 @@ static void nbd_put(struct nbd_device *nbd) · 247 unmodified lines
248248 if (refcount_dec_and_mutex_lock(&nbd->refs,
249249 &nbd_index_mutex)) {
250250 idr_remove(&nbd_index_idr, nbd->index);
251− mutex_unlock(&nbd_index_mutex);
252251 nbd_dev_remove(nbd);
252+ mutex_unlock(&nbd_index_mutex);
253253 }
254254 }
255255
@@ -385,17 +385,16 @@ static enum blk_eh_timer_return nbd_xmit_timeout(struct request *req, · 129 unmodified lines
385385 struct nbd_device *nbd = cmd->nbd;
386386 struct nbd_config *config;
387387
388+ if (!mutex_trylock(&cmd->lock))
389+ return BLK_EH_RESET_TIMER;
390+
388391 if (!refcount_inc_not_zero(&nbd->config_refs)) {
389392 cmd->status = BLK_STS_TIMEOUT;
393+ mutex_unlock(&cmd->lock);
390394 goto done;
391395 }
392396 config = nbd->config;
393397
394− if (!mutex_trylock(&cmd->lock)) {
395− nbd_config_put(nbd);
396− return BLK_EH_RESET_TIMER;
397− }
398−
399398 if (config->num_connections > 1) {
400399 dev_err_ratelimited(nbd_to_dev(nbd),
401400 "Connection timed out, retrying (%d/%d alive)\n",
@@ -711,6 +710,12 @@ static struct nbd_cmd *nbd_read_stat(struct nbd_device *nbd, int index) · 309 unmodified lines
711710 ret = -ENOENT;
712711 goto out;
713712 }
713+ if (cmd->status != BLK_STS_OK) {
714+ dev_err(disk_to_dev(nbd->disk), "Command already handled %p\n",
715+ req);
716+ ret = -ENOENT;
717+ goto out;
718+ }
714719 if (test_bit(NBD_CMD_REQUEUED, &cmd->flags)) {
715720 dev_err(disk_to_dev(nbd->disk), "Raced with timeout on req %p\n",
716721 req);
@@ -792,7 +797,10 @@ static bool nbd_clear_req(struct request *req, void *data, bool reserved) · 75 unmodified lines
792797 {
793798 struct nbd_cmd *cmd = blk_mq_rq_to_pdu(req);
794799
800+ mutex_lock(&cmd->lock);
795801 cmd->status = BLK_STS_IOERR;
802+ mutex_unlock(&cmd->lock);
803+
796804 blk_mq_complete_request(req);
797805 return true;
798806 }
@@ -972,6 +980,25 @@ static blk_status_t nbd_queue_rq(struct blk_mq_hw_ctx *hctx, · 173 unmodified lines
972980 return ret;
973981 }
974982
983+static struct socket *nbd_get_socket(struct nbd_device *nbd, unsigned long fd,
984+ int *err)
985+{
986+ struct socket *sock;
987+
988+ *err = 0;
989+ sock = sockfd_lookup(fd, err);
990+ if (!sock)
991+ return NULL;
992+
993+ if (sock->ops->shutdown == sock_no_shutdown) {
994+ dev_err(disk_to_dev(nbd->disk), "Unsupported socket: shutdown callout must be supported.\n");
995+ *err = -EINVAL;
996+ return NULL;
997+ }
998+
999+ return sock;
1000+}
1001+
9751002 static int nbd_add_socket(struct nbd_device *nbd, unsigned long arg,
9761003 bool netlink)
9771004 {
@@ -981,7 +1008,7 @@ static int nbd_add_socket(struct nbd_device *nbd, unsigned long arg, · 3 unmodified lines
9811008 struct nbd_sock *nsock;
9821009 int err;
9831010
984− sock = sockfd_lookup(arg, &err);
1011+ sock = nbd_get_socket(nbd, arg, &err);
9851012 if (!sock)
9861013 return err;
9871014
@@ -1033,7 +1060,7 @@ static int nbd_reconnect_socket(struct nbd_device *nbd, unsigned long arg) · 45 unmodified lines
10331060 int i;
10341061 int err;
10351062
1036− sock = sockfd_lookup(arg, &err);
1063+ sock = nbd_get_socket(nbd, arg, &err);
10371064 if (!sock)
10381065 return err;
10391066
drivers/block/null_blk_zoned.c+1−2
@@ -142,8 +142,7 @@ static blk_status_t null_zone_reset(struct nullb_cmd *cmd, sector_t sector) · 141 unmodified lines
142142 zone->wp = zone->start;
143143 break;
144144 default:
145− cmd->error = BLK_STS_NOTSUPP;
146− break;
145+ return BLK_STS_NOTSUPP;
147146 }
148147 return BLK_STS_OK;
149148 }
drivers/block/rbd.c+6−3
@@ -6639,10 +6639,13 @@ static int rbd_add_acquire_lock(struct rbd_device *rbd_dev) · 6638 unmodified lines
66396639 queue_delayed_work(rbd_dev->task_wq, &rbd_dev->lock_dwork, 0);
66406640 ret = wait_for_completion_killable_timeout(&rbd_dev->acquire_wait,
66416641 ceph_timeout_jiffies(rbd_dev->opts->lock_timeout));
6642− if (ret > 0)
6642+ if (ret > 0) {
66436643 ret = rbd_dev->acquire_err;
6644− else if (!ret)
6645− ret = -ETIMEDOUT;
6644+ } else {
6645+ cancel_delayed_work_sync(&rbd_dev->lock_dwork);
6646+ if (!ret)
6647+ ret = -ETIMEDOUT;
6648+ }
66466649
66476650 if (ret) {
66486651 rbd_warn(rbd_dev, "failed to acquire exclusive lock: %ld", ret);
drivers/block/zram/zram_drv.c+3−2
@@ -413,13 +413,14 @@ static void reset_bdev(struct zram *zram) · 412 unmodified lines
413413 static ssize_t backing_dev_show(struct device *dev,
414414 struct device_attribute *attr, char *buf)
415415 {
416+ struct file *file;
416417 struct zram *zram = dev_to_zram(dev);
417− struct file *file = zram->backing_dev;
418418 char *p;
419419 ssize_t ret;
420420
421421 down_read(&zram->init_lock);
422− if (!zram->backing_dev) {
422+ file = zram->backing_dev;
423+ if (!file) {
423424 memcpy(buf, "none\n", 5);
424425 up_read(&zram->init_lock);
425426 return 5;
drivers/bus/ti-sysc.c+14−4
@@ -74,6 +74,7 @@ static const char * const clock_names[SYSC_MAX_CLOCKS] = { · 73 unmodified lines
7474 * @clk_disable_quirk: module specific clock disable quirk
7575 * @reset_done_quirk: module specific reset done quirk
7676 * @module_enable_quirk: module specific enable quirk
77+ * @module_disable_quirk: module specific disable quirk
7778 */
7879 struct sysc {
7980 struct device *dev;
@@ -100,6 +101,7 @@ struct sysc { · 20 unmodified lines
100101 void (*clk_disable_quirk)(struct sysc *sysc);
101102 void (*reset_done_quirk)(struct sysc *sysc);
102103 void (*module_enable_quirk)(struct sysc *sysc);
104+ void (*module_disable_quirk)(struct sysc *sysc);
103105 };
104106
105107 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
@@ -959,6 +961,9 @@ static int sysc_disable_module(struct device *dev) · 853 unmodified lines
959961 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
960962 return 0;
961963
964+ if (ddata->module_disable_quirk)
965+ ddata->module_disable_quirk(ddata);
966+
962967 regbits = ddata->cap->regbits;
963968 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
964969
@@ -1248,6 +1253,9 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { · 283 unmodified lines
12481253 SYSC_MODULE_QUIRK_SGX),
12491254 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
12501255 SYSC_MODULE_QUIRK_WDT),
1256+ /* Watchdog on am3 and am4 */
1257+ SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1258+ SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
12511259
12521260 #ifdef DEBUG
12531261 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
@@ -1440,14 +1448,14 @@ static void sysc_reset_done_quirk_wdt(struct sysc *ddata) · 186 unmodified lines
14401448 !(val & 0x10), 100,
14411449 MAX_MODULE_SOFTRESET_WAIT);
14421450 if (error)
1443− dev_warn(ddata->dev, "wdt disable spr failed\n");
1451+ dev_warn(ddata->dev, "wdt disable step1 failed\n");
14441452
1445− sysc_write(ddata, wps, 0x5555);
1453+ sysc_write(ddata, spr, 0x5555);
14461454 error = readl_poll_timeout(ddata->module_va + wps, val,
14471455 !(val & 0x10), 100,
14481456 MAX_MODULE_SOFTRESET_WAIT);
14491457 if (error)
1450− dev_warn(ddata->dev, "wdt disable wps failed\n");
1458+ dev_warn(ddata->dev, "wdt disable step2 failed\n");
14511459 }
14521460
14531461 static void sysc_init_module_quirks(struct sysc *ddata)
@@ -1471,8 +1479,10 @@ static void sysc_init_module_quirks(struct sysc *ddata) · 17 unmodified lines
14711479 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
14721480 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
14731481
1474− if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT)
1482+ if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
14751483 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
1484+ ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1485+ }
14761486 }
14771487
14781488 static int sysc_clockdomain_init(struct sysc *ddata)
drivers/clk/at91/clk-main.c+4−1
@@ -297,7 +297,10 @@ static int clk_main_probe_frequency(struct regmap *regmap) · 296 unmodified lines
297297 regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
298298 if (mcfr & AT91_PMC_MAINRDY)
299299 return 0;
300− usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
300+ if (system_state < SYSTEM_RUNNING)
301+ udelay(MAINF_LOOP_MIN_WAIT);
302+ else
303+ usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
301304 } while (time_before(prep_time, timeout));
302305
303306 return -ETIMEDOUT;
drivers/clk/at91/sam9x60.c+1−0
@@ -43,6 +43,7 @@ static const struct clk_pll_characteristics upll_characteristics = { · 42 unmodified lines
4343 };
4444
4545 static const struct clk_programmable_layout sam9x60_programmable_layout = {
46+ .pres_mask = 0xff,
4647 .pres_shift = 8,
4748 .css_mask = 0x1f,
4849 .have_slck_mck = 0,
drivers/clk/at91/sckc.c+16−4
@@ -76,7 +76,10 @@ static int clk_slow_osc_prepare(struct clk_hw *hw) · 75 unmodified lines
7676
7777 writel(tmp | osc->bits->cr_osc32en, sckcr);
7878
79− usleep_range(osc->startup_usec, osc->startup_usec + 1);
79+ if (system_state < SYSTEM_RUNNING)
80+ udelay(osc->startup_usec);
81+ else
82+ usleep_range(osc->startup_usec, osc->startup_usec + 1);
8083
8184 return 0;
8285 }
@@ -187,7 +190,10 @@ static int clk_slow_rc_osc_prepare(struct clk_hw *hw) · 104 unmodified lines
187190
188191 writel(readl(sckcr) | osc->bits->cr_rcen, sckcr);
189192
190− usleep_range(osc->startup_usec, osc->startup_usec + 1);
193+ if (system_state < SYSTEM_RUNNING)
194+ udelay(osc->startup_usec);
195+ else
196+ usleep_range(osc->startup_usec, osc->startup_usec + 1);
191197
192198 return 0;
193199 }
@@ -288,7 +294,10 @@ static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index) · 94 unmodified lines
288294
289295 writel(tmp, sckcr);
290296
291− usleep_range(SLOWCK_SW_TIME_USEC, SLOWCK_SW_TIME_USEC + 1);
297+ if (system_state < SYSTEM_RUNNING)
298+ udelay(SLOWCK_SW_TIME_USEC);
299+ else
300+ usleep_range(SLOWCK_SW_TIME_USEC, SLOWCK_SW_TIME_USEC + 1);
292301
293302 return 0;
294303 }
@@ -533,7 +542,10 @@ static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw) · 238 unmodified lines
533542 return 0;
534543 }
535544
536− usleep_range(osc->startup_usec, osc->startup_usec + 1);
545+ if (system_state < SYSTEM_RUNNING)
546+ udelay(osc->startup_usec);
547+ else
548+ usleep_range(osc->startup_usec, osc->startup_usec + 1);
537549 osc->prepared = true;
538550
539551 return 0;
drivers/clk/clk-ast2600.c+4−3
@@ -266,10 +266,11 @@ static int aspeed_g6_clk_enable(struct clk_hw *hw) · 265 unmodified lines
266266
267267 /* Enable clock */
268268 if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
269− regmap_write(gate->map, get_clock_reg(gate), clk);
270− } else {
271− /* Use set to clear register */
269+ /* Clock is clear to enable, so use set to clear register */
272270 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
271+ } else {
272+ /* Clock is set to enable, so use write to set register */
273+ regmap_write(gate->map, get_clock_reg(gate), clk);
273274 }
274275
275276 if (gate->reset_idx >= 0) {
drivers/clk/imx/clk-imx8mm.c+1−1
@@ -638,7 +638,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) · 637 unmodified lines
638638 clks[IMX8MM_CLK_A53_DIV],
639639 clks[IMX8MM_CLK_A53_SRC],
640640 clks[IMX8MM_ARM_PLL_OUT],
641− clks[IMX8MM_CLK_24M]);
641+ clks[IMX8MM_SYS_PLL1_800M]);
642642
643643 imx_check_clocks(clks, ARRAY_SIZE(clks));
644644
drivers/clk/imx/clk-imx8mn.c+1−1
@@ -610,7 +610,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) · 609 unmodified lines
610610 clks[IMX8MN_CLK_A53_DIV],
611611 clks[IMX8MN_CLK_A53_SRC],
612612 clks[IMX8MN_ARM_PLL_OUT],
613− clks[IMX8MN_CLK_24M]);
613+ clks[IMX8MN_SYS_PLL1_800M]);
614614
615615 imx_check_clocks(clks, ARRAY_SIZE(clks));
616616
drivers/clk/meson/g12a.c+11−2
@@ -343,6 +343,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = { · 342 unmodified lines
343343 .offset = HHI_SYS_CPU_CLK_CNTL0,
344344 .mask = 0x3,
345345 .shift = 0,
346+ .flags = CLK_MUX_ROUND_CLOSEST,
346347 },
347348 .hw.init = &(struct clk_init_data){
348349 .name = "cpu_clk_dyn0_sel",
@@ -353,8 +354,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = { · 4 unmodified lines
353354 { .hw = &g12a_fclk_div3.hw },
354355 },
355356 .num_parents = 3,
356− /* This sub-tree is used a parking clock */
357− .flags = CLK_SET_RATE_NO_REPARENT,
357+ .flags = CLK_SET_RATE_PARENT,
358358 },
359359 };
360360
@@ -410,6 +410,7 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = { · 49 unmodified lines
410410 .offset = HHI_SYS_CPU_CLK_CNTL0,
411411 .mask = 0x1,
412412 .shift = 2,
413+ .flags = CLK_MUX_ROUND_CLOSEST,
413414 },
414415 .hw.init = &(struct clk_init_data){
415416 .name = "cpu_clk_dyn0",
@@ -466,6 +467,7 @@ static struct clk_regmap g12a_cpu_clk_dyn = { · 50 unmodified lines
466467 .offset = HHI_SYS_CPU_CLK_CNTL0,
467468 .mask = 0x1,
468469 .shift = 10,
470+ .flags = CLK_MUX_ROUND_CLOSEST,
469471 },
470472 .hw.init = &(struct clk_init_data){
471473 .name = "cpu_clk_dyn",
@@ -485,6 +487,7 @@ static struct clk_regmap g12a_cpu_clk = { · 13 unmodified lines
485487 .offset = HHI_SYS_CPU_CLK_CNTL0,
486488 .mask = 0x1,
487489 .shift = 11,
490+ .flags = CLK_MUX_ROUND_CLOSEST,
488491 },
489492 .hw.init = &(struct clk_init_data){
490493 .name = "cpu_clk",
@@ -504,6 +507,7 @@ static struct clk_regmap g12b_cpu_clk = { · 13 unmodified lines
504507 .offset = HHI_SYS_CPU_CLK_CNTL0,
505508 .mask = 0x1,
506509 .shift = 11,
510+ .flags = CLK_MUX_ROUND_CLOSEST,
507511 },
508512 .hw.init = &(struct clk_init_data){
509513 .name = "cpu_clk",
@@ -523,6 +527,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = { · 13 unmodified lines
523527 .offset = HHI_SYS_CPUB_CLK_CNTL,
524528 .mask = 0x3,
525529 .shift = 0,
530+ .flags = CLK_MUX_ROUND_CLOSEST,
526531 },
527532 .hw.init = &(struct clk_init_data){
528533 .name = "cpub_clk_dyn0_sel",
@@ -533,6 +538,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = { · 4 unmodified lines
533538 { .hw = &g12a_fclk_div3.hw },
534539 },
535540 .num_parents = 3,
541+ .flags = CLK_SET_RATE_PARENT,
536542 },
537543 };
538544
@@ -567,6 +573,7 @@ static struct clk_regmap g12b_cpub_clk_postmux0 = { · 28 unmodified lines
567573 .offset = HHI_SYS_CPUB_CLK_CNTL,
568574 .mask = 0x1,
569575 .shift = 2,
576+ .flags = CLK_MUX_ROUND_CLOSEST,
570577 },
571578 .hw.init = &(struct clk_init_data){
572579 .name = "cpub_clk_dyn0",
@@ -644,6 +651,7 @@ static struct clk_regmap g12b_cpub_clk_dyn = { · 71 unmodified lines
644651 .offset = HHI_SYS_CPUB_CLK_CNTL,
645652 .mask = 0x1,
646653 .shift = 10,
654+ .flags = CLK_MUX_ROUND_CLOSEST,
647655 },
648656 .hw.init = &(struct clk_init_data){
649657 .name = "cpub_clk_dyn",
@@ -663,6 +671,7 @@ static struct clk_regmap g12b_cpub_clk = { · 13 unmodified lines
663671 .offset = HHI_SYS_CPUB_CLK_CNTL,
664672 .mask = 0x1,
665673 .shift = 11,
674+ .flags = CLK_MUX_ROUND_CLOSEST,
666675 },
667676 .hw.init = &(struct clk_init_data){
668677 .name = "cpub_clk",
drivers/clk/meson/gxbb.c+1−0
@@ -935,6 +935,7 @@ static struct clk_regmap gxbb_sar_adc_clk_div = { · 934 unmodified lines
935935 &gxbb_sar_adc_clk_sel.hw
936936 },
937937 .num_parents = 1,
938+ .flags = CLK_SET_RATE_PARENT,
938939 },
939940 };
940941
drivers/clk/samsung/clk-exynos5420.c+25−2
@@ -165,12 +165,18 @@ static const unsigned long exynos5x_clk_regs[] __initconst = { · 164 unmodified lines
165165 GATE_BUS_CPU,
166166 GATE_SCLK_CPU,
167167 CLKOUT_CMU_CPU,
168+ CPLL_CON0,
169+ DPLL_CON0,
168170 EPLL_CON0,
169171 EPLL_CON1,
170172 EPLL_CON2,
171173 RPLL_CON0,
172174 RPLL_CON1,
173175 RPLL_CON2,
176+ IPLL_CON0,
177+ SPLL_CON0,
178+ VPLL_CON0,
179+ MPLL_CON0,
174180 SRC_TOP0,
175181 SRC_TOP1,
176182 SRC_TOP2,
@@ -1172,8 +1178,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { · 995 unmodified lines
11721178 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
11731179 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
11741180
1175− GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1176−
11771181 /* CDREX */
11781182 GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
11791183 GATE_BUS_CDREX0, 0, 0, 0),
@@ -1248,6 +1252,15 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { · 68 unmodified lines
12481252 { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */
12491253 };
12501254
1255+static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
1256+ GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1257+};
1258+
1259+static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = {
1260+ { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */
1261+ { SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */
1262+};
1263+
12511264 static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
12521265 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
12531266 };
@@ -1320,6 +1333,14 @@ static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = { · 66 unmodified lines
13201333 .pd_name = "GSC",
13211334 };
13221335
1336+static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = {
1337+ .gate_clks = exynos5x_g3d_gate_clks,
1338+ .nr_gate_clks = ARRAY_SIZE(exynos5x_g3d_gate_clks),
1339+ .suspend_regs = exynos5x_g3d_suspend_regs,
1340+ .nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs),
1341+ .pd_name = "G3D",
1342+};
1343+
13231344 static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {
13241345 .div_clks = exynos5x_mfc_div_clks,
13251346 .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
@@ -1351,6 +1372,7 @@ static const struct exynos5_subcmu_info exynos5800_mau_subcmu = { · 25 unmodified lines
13511372 static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
13521373 &exynos5x_disp_subcmu,
13531374 &exynos5x_gsc_subcmu,
1375+ &exynos5x_g3d_subcmu,
13541376 &exynos5x_mfc_subcmu,
13551377 &exynos5x_mscl_subcmu,
13561378 };
@@ -1358,6 +1380,7 @@ static const struct exynos5_subcmu_info *exynos5x_subcmus[] = { · 1 unmodified line
13581380 static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
13591381 &exynos5x_disp_subcmu,
13601382 &exynos5x_gsc_subcmu,
1383+ &exynos5x_g3d_subcmu,
13611384 &exynos5x_mfc_subcmu,
13621385 &exynos5x_mscl_subcmu,
13631386 &exynos5800_mau_subcmu,
drivers/clk/samsung/clk-exynos5433.c+12−2
@@ -13,6 +13,7 @@ · 12 unmodified lines
1313 #include <linux/of_device.h>
1414 #include <linux/platform_device.h>
1515 #include <linux/pm_runtime.h>
16+#include <linux/slab.h>
1617
1718 #include <dt-bindings/clock/exynos5433.h>
1819
@@ -5584,6 +5585,8 @@ static int __init exynos5433_cmu_probe(struct platform_device *pdev) · 5565 unmodified lines
55845585
55855586 data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs,
55865587 info->nr_clk_regs);
5588+ if (!data->clk_save)
5589+ return -ENOMEM;
55875590 data->nr_clk_save = info->nr_clk_regs;
55885591 data->clk_suspend = info->suspend_regs;
55895592 data->nr_clk_suspend = info->nr_suspend_regs;
@@ -5592,12 +5595,19 @@ static int __init exynos5433_cmu_probe(struct platform_device *pdev) · 2 unmodified lines
55925595 if (data->nr_pclks > 0) {
55935596 data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
55945597 data->nr_pclks, GFP_KERNEL);
5595−
5598+ if (!data->pclks) {
5599+ kfree(data->clk_save);
5600+ return -ENOMEM;
5601+ }
55965602 for (i = 0; i < data->nr_pclks; i++) {
55975603 struct clk *clk = of_clk_get(dev->of_node, i);
55985604
5599− if (IS_ERR(clk))
5605+ if (IS_ERR(clk)) {
5606+ kfree(data->clk_save);
5607+ while (--i >= 0)
5608+ clk_put(data->pclks[i]);
56005609 return PTR_ERR(clk);
5610+ }
56015611 data->pclks[i] = clk;
56025612 }
56035613 }
drivers/clk/sunxi-ng/ccu-sun9i-a80.c+1−1
@@ -1224,7 +1224,7 @@ static int sun9i_a80_ccu_probe(struct platform_device *pdev) · 1223 unmodified lines
12241224
12251225 /* Enforce d1 = 0, d2 = 0 for Audio PLL */
12261226 val = readl(reg + SUN9I_A80_PLL_AUDIO_REG);
1227− val &= (BIT(16) & BIT(18));
1227+ val &= ~(BIT(16) | BIT(18));
12281228 writel(val, reg + SUN9I_A80_PLL_AUDIO_REG);
12291229
12301230 /* Enforce P = 1 for both CPU cluster PLLs */
drivers/clk/sunxi/clk-sunxi.c+2−2
@@ -1080,8 +1080,8 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node, · 1079 unmodified lines
10801080 rate_hw, rate_ops,
10811081 gate_hw, &clk_gate_ops,
10821082 clkflags |
1083− data->div[i].critical ?
1084− CLK_IS_CRITICAL : 0);
1083+ (data->div[i].critical ?
1084+ CLK_IS_CRITICAL : 0));
10851085
10861086 WARN_ON(IS_ERR(clk_data->clks[i]));
10871087 }
drivers/clk/ti/clk-dra7-atl.c+0−6
@@ -174,7 +174,6 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) · 173 unmodified lines
174174 struct clk_init_data init = { NULL };
175175 const char **parent_names = NULL;
176176 struct clk *clk;
177− int ret;
178177
179178 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
180179 if (!clk_hw) {
@@ -207,11 +206,6 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) · 26 unmodified lines
207206 clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
208207
209208 if (!IS_ERR(clk)) {
210− ret = ti_clk_add_alias(NULL, clk, node->name);
211− if (ret) {
212− clk_unregister(clk);
213− goto cleanup;
214− }
215209 of_clk_add_provider(node, of_clk_src_simple_get, clk);
216210 kfree(parent_names);
217211 return;
drivers/clk/ti/clkctrl.c+3−2
@@ -100,11 +100,12 @@ static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout) · 99 unmodified lines
100100 * can be from a timer that requires pm_runtime access, which
101101 * will eventually bring us here with timekeeping_suspended,
102102 * during both suspend entry and resume paths. This happens
103− * at least on am43xx platform.
103+ * at least on am43xx platform. Account for flakeyness
104+ * with udelay() by multiplying the timeout value by 2.
104105 */
105106 if (unlikely(_early_timeout || timekeeping_suspended)) {
106107 if (time->cycles++ < timeout) {
107− udelay(1);
108+ udelay(1 * 2);
108109 return false;
109110 }
110111 } else {
drivers/clocksource/sh_mtu2.c+11−5
@@ -328,12 +328,13 @@ static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name) · 327 unmodified lines
328328 return 0;
329329 }
330330
331+static const unsigned int sh_mtu2_channel_offsets[] = {
332+ 0x300, 0x380, 0x000,
333+};
334+
331335 static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index,
332336 struct sh_mtu2_device *mtu)
333337 {
334− static const unsigned int channel_offsets[] = {
335− 0x300, 0x380, 0x000,
336− };
337338 char name[6];
338339 int irq;
339340 int ret;
@@ -356,7 +357,7 @@ static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index, · 16 unmodified lines
356357 return ret;
357358 }
358359
359− ch->base = mtu->mapbase + channel_offsets[index];
360+ ch->base = mtu->mapbase + sh_mtu2_channel_offsets[index];
360361 ch->index = index;
361362
362363 return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev));
@@ -408,7 +409,12 @@ static int sh_mtu2_setup(struct sh_mtu2_device *mtu, · 45 unmodified lines
408409 }
409410
410411 /* Allocate and setup the channels. */
411− mtu->num_channels = 3;
412+ ret = platform_irq_count(pdev);
413+ if (ret < 0)
414+ goto err_unmap;
415+
416+ mtu->num_channels = min_t(unsigned int, ret,
417+ ARRAY_SIZE(sh_mtu2_channel_offsets));
412418
413419 mtu->channels = kcalloc(mtu->num_channels, sizeof(*mtu->channels),
414420 GFP_KERNEL);
drivers/clocksource/timer-mediatek.c+2−8
@@ -268,15 +268,12 @@ static int __init mtk_syst_init(struct device_node *node) · 267 unmodified lines
268268
269269 ret = timer_of_init(node, &to);
270270 if (ret)
271− goto err;
271+ return ret;
272272
273273 clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
274274 TIMER_SYNC_TICKS, 0xffffffff);
275275
276276 return 0;
277−err:
278− timer_of_cleanup(&to);
279− return ret;
280277 }
281278
282279 static int __init mtk_gpt_init(struct device_node *node)
@@ -293,7 +290,7 @@ static int __init mtk_gpt_init(struct device_node *node) · 10 unmodified lines
293290
294291 ret = timer_of_init(node, &to);
295292 if (ret)
296− goto err;
293+ return ret;
297294
298295 /* Configure clock source */
299296 mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
@@ -311,9 +308,6 @@ static int __init mtk_gpt_init(struct device_node *node) · 11 unmodified lines
311308 mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);
312309
313310 return 0;
314−err:
315− timer_of_cleanup(&to);
316− return ret;
317311 }
318312 TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
319313 TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);
drivers/cpufreq/cpufreq.c+29−43
@@ -720,7 +720,7 @@ static ssize_t store_##file_name \ · 719 unmodified lines
720720 if (ret != 1) \
721721 return -EINVAL; \
722722 \
723− ret = dev_pm_qos_update_request(policy->object##_freq_req, val);\
723+ ret = freq_qos_update_request(policy->object##_freq_req, val);\
724724 return ret >= 0 ? count : ret; \
725725 }
726726
@@ -1202,19 +1202,21 @@ static struct cpufreq_policy *cpufreq_policy_alloc(unsigned int cpu) · 475 unmodified lines
12021202 goto err_free_real_cpus;
12031203 }
12041204
1205+ freq_constraints_init(&policy->constraints);
1206+
12051207 policy->nb_min.notifier_call = cpufreq_notifier_min;
12061208 policy->nb_max.notifier_call = cpufreq_notifier_max;
12071209
1208− ret = dev_pm_qos_add_notifier(dev, &policy->nb_min,
1209− DEV_PM_QOS_MIN_FREQUENCY);
1210+ ret = freq_qos_add_notifier(&policy->constraints, FREQ_QOS_MIN,
1211+ &policy->nb_min);
12101212 if (ret) {
12111213 dev_err(dev, "Failed to register MIN QoS notifier: %d (%*pbl)\n",
12121214 ret, cpumask_pr_args(policy->cpus));
12131215 goto err_kobj_remove;
12141216 }
12151217
1216− ret = dev_pm_qos_add_notifier(dev, &policy->nb_max,
1217− DEV_PM_QOS_MAX_FREQUENCY);
1218+ ret = freq_qos_add_notifier(&policy->constraints, FREQ_QOS_MAX,
1219+ &policy->nb_max);
12181220 if (ret) {
12191221 dev_err(dev, "Failed to register MAX QoS notifier: %d (%*pbl)\n",
12201222 ret, cpumask_pr_args(policy->cpus));
@@ -1232,8 +1234,8 @@ static struct cpufreq_policy *cpufreq_policy_alloc(unsigned int cpu) · 11 unmodified lines
12321234 return policy;
12331235
12341236 err_min_qos_notifier:
1235− dev_pm_qos_remove_notifier(dev, &policy->nb_min,
1236− DEV_PM_QOS_MIN_FREQUENCY);
1237+ freq_qos_remove_notifier(&policy->constraints, FREQ_QOS_MIN,
1238+ &policy->nb_min);
12371239 err_kobj_remove:
12381240 cpufreq_policy_put_kobj(policy);
12391241 err_free_real_cpus:
@@ -1250,7 +1252,6 @@ err_free_policy: · 10 unmodified lines
12501252
12511253 static void cpufreq_policy_free(struct cpufreq_policy *policy)
12521254 {
1253− struct device *dev = get_cpu_device(policy->cpu);
12541255 unsigned long flags;
12551256 int cpu;
12561257
@@ -1262,10 +1263,13 @@ static void cpufreq_policy_free(struct cpufreq_policy *policy) · 5 unmodified lines
12621263 per_cpu(cpufreq_cpu_data, cpu) = NULL;
12631264 write_unlock_irqrestore(&cpufreq_driver_lock, flags);
12641265
1265− dev_pm_qos_remove_notifier(dev, &policy->nb_max,
1266− DEV_PM_QOS_MAX_FREQUENCY);
1267− dev_pm_qos_remove_notifier(dev, &policy->nb_min,
1268− DEV_PM_QOS_MIN_FREQUENCY);
1266+ freq_qos_remove_notifier(&policy->constraints, FREQ_QOS_MAX,
1267+ &policy->nb_max);
1268+ freq_qos_remove_notifier(&policy->constraints, FREQ_QOS_MIN,
1269+ &policy->nb_min);
1270+
1271+ /* Cancel any pending policy->update work before freeing the policy. */
1272+ cancel_work_sync(&policy->update);
12691273
12701274 if (policy->max_freq_req) {
12711275 /*
@@ -1274,10 +1278,10 @@ static void cpufreq_policy_free(struct cpufreq_policy *policy) · 2 unmodified lines
12741278 */
12751279 blocking_notifier_call_chain(&cpufreq_policy_notifier_list,
12761280 CPUFREQ_REMOVE_POLICY, policy);
1277− dev_pm_qos_remove_request(policy->max_freq_req);
1281+ freq_qos_remove_request(policy->max_freq_req);
12781282 }
12791283
1280− dev_pm_qos_remove_request(policy->min_freq_req);
1284+ freq_qos_remove_request(policy->min_freq_req);
12811285 kfree(policy->min_freq_req);
12821286
12831287 cpufreq_policy_put_kobj(policy);
@@ -1357,8 +1361,6 @@ static int cpufreq_online(unsigned int cpu) · 73 unmodified lines
13571361 cpumask_and(policy->cpus, policy->cpus, cpu_online_mask);
13581362
13591363 if (new_policy) {
1360− struct device *dev = get_cpu_device(cpu);
1361−
13621364 for_each_cpu(j, policy->related_cpus) {
13631365 per_cpu(cpufreq_cpu_data, j) = policy;
13641366 add_cpu_dev_symlink(policy, j);
@@ -1369,36 +1371,31 @@ static int cpufreq_online(unsigned int cpu) · 4 unmodified lines
13691371 if (!policy->min_freq_req)
13701372 goto out_destroy_policy;
13711373
1372− ret = dev_pm_qos_add_request(dev, policy->min_freq_req,
1373− DEV_PM_QOS_MIN_FREQUENCY,
1374− policy->min);
1374+ ret = freq_qos_add_request(&policy->constraints,
1375+ policy->min_freq_req, FREQ_QOS_MIN,
1376+ policy->min);
13751377 if (ret < 0) {
13761378 /*
1377− * So we don't call dev_pm_qos_remove_request() for an
1379+ * So we don't call freq_qos_remove_request() for an
13781380 * uninitialized request.
13791381 */
13801382 kfree(policy->min_freq_req);
13811383 policy->min_freq_req = NULL;
1382−
1383− dev_err(dev, "Failed to add min-freq constraint (%d)\n",
1384− ret);
13851384 goto out_destroy_policy;
13861385 }
13871386
13881387 /*
13891388 * This must be initialized right here to avoid calling
1390− * dev_pm_qos_remove_request() on uninitialized request in case
1389+ * freq_qos_remove_request() on uninitialized request in case
13911390 * of errors.
13921391 */
13931392 policy->max_freq_req = policy->min_freq_req + 1;
13941393
1395− ret = dev_pm_qos_add_request(dev, policy->max_freq_req,
1396− DEV_PM_QOS_MAX_FREQUENCY,
1397− policy->max);
1394+ ret = freq_qos_add_request(&policy->constraints,
1395+ policy->max_freq_req, FREQ_QOS_MAX,
1396+ policy->max);
13981397 if (ret < 0) {
13991398 policy->max_freq_req = NULL;
1400− dev_err(dev, "Failed to add max-freq constraint (%d)\n",
1401− ret);
14021399 goto out_destroy_policy;
14031400 }
14041401
@@ -2374,7 +2371,6 @@ int cpufreq_set_policy(struct cpufreq_policy *policy, · 969 unmodified lines
23742371 struct cpufreq_policy *new_policy)
23752372 {
23762373 struct cpufreq_governor *old_gov;
2377− struct device *cpu_dev = get_cpu_device(policy->cpu);
23782374 int ret;
23792375
23802376 pr_debug("setting new policy for CPU %u: %u - %u kHz\n",
@@ -2386,8 +2382,8 @@ int cpufreq_set_policy(struct cpufreq_policy *policy, · 5 unmodified lines
23862382 * PM QoS framework collects all the requests from users and provide us
23872383 * the final aggregated value here.
23882384 */
2389− new_policy->min = dev_pm_qos_read_value(cpu_dev, DEV_PM_QOS_MIN_FREQUENCY);
2390− new_policy->max = dev_pm_qos_read_value(cpu_dev, DEV_PM_QOS_MAX_FREQUENCY);
2385+ new_policy->min = freq_qos_read_value(&policy->constraints, FREQ_QOS_MIN);
2386+ new_policy->max = freq_qos_read_value(&policy->constraints, FREQ_QOS_MAX);
23912387
23922388 /* verify the cpu speed can be set within this limit */
23932389 ret = cpufreq_driver->verify(new_policy);
@@ -2518,7 +2514,7 @@ static int cpufreq_boost_set_sw(int state) · 124 unmodified lines
25182514 break;
25192515 }
25202516
2521− ret = dev_pm_qos_update_request(policy->max_freq_req, policy->max);
2517+ ret = freq_qos_update_request(policy->max_freq_req, policy->max);
25222518 if (ret < 0)
25232519 break;
25242520 }
@@ -2737,14 +2733,6 @@ int cpufreq_unregister_driver(struct cpufreq_driver *driver) · 212 unmodified lines
27372733 }
27382734 EXPORT_SYMBOL_GPL(cpufreq_unregister_driver);
27392735
2740−/*
2741− * Stop cpufreq at shutdown to make sure it isn't holding any locks
2742− * or mutexes when secondary CPUs are halted.
2743− */
2744−static struct syscore_ops cpufreq_syscore_ops = {
2745− .shutdown = cpufreq_suspend,
2746−};
2747−
27482736 struct kobject *cpufreq_global_kobject;
27492737 EXPORT_SYMBOL(cpufreq_global_kobject);
27502738
@@ -2756,8 +2744,6 @@ static int __init cpufreq_core_init(void) · 5 unmodified lines
27562744 cpufreq_global_kobject = kobject_create_and_add("cpufreq", &cpu_subsys.dev_root->kobj);
27572745 BUG_ON(!cpufreq_global_kobject);
27582746
2759− register_syscore_ops(&cpufreq_syscore_ops);
2760−
27612747 return 0;
27622748 }
27632749 module_param(off, int, 0444);
drivers/cpufreq/intel_pstate.c+16−18
@@ -847,11 +847,9 @@ static void intel_pstate_hwp_force_min_perf(int cpu) · 846 unmodified lines
847847 value |= HWP_MAX_PERF(min_perf);
848848 value |= HWP_MIN_PERF(min_perf);
849849
850− /* Set EPP/EPB to min */
850+ /* Set EPP to min */
851851 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
852852 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
853− else
854− intel_pstate_set_epb(cpu, HWP_EPP_BALANCE_POWERSAVE);
855853
856854 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
857855 }
@@ -1088,10 +1086,10 @@ static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, · 230 unmodified lines
10881086
10891087 static struct cpufreq_driver intel_pstate;
10901088
1091−static void update_qos_request(enum dev_pm_qos_req_type type)
1089+static void update_qos_request(enum freq_qos_req_type type)
10921090 {
10931091 int max_state, turbo_max, freq, i, perf_pct;
1094− struct dev_pm_qos_request *req;
1092+ struct freq_qos_request *req;
10951093 struct cpufreq_policy *policy;
10961094
10971095 for_each_possible_cpu(i) {
@@ -1112,7 +1110,7 @@ static void update_qos_request(enum dev_pm_qos_req_type type) · 14 unmodified lines
11121110 else
11131111 turbo_max = cpu->pstate.turbo_pstate;
11141112
1115− if (type == DEV_PM_QOS_MIN_FREQUENCY) {
1113+ if (type == FREQ_QOS_MIN) {
11161114 perf_pct = global.min_perf_pct;
11171115 } else {
11181116 req++;
@@ -1122,7 +1120,7 @@ static void update_qos_request(enum dev_pm_qos_req_type type) · 3 unmodified lines
11221120 freq = DIV_ROUND_UP(turbo_max * perf_pct, 100);
11231121 freq *= cpu->pstate.scaling;
11241122
1125− if (dev_pm_qos_update_request(req, freq) < 0)
1123+ if (freq_qos_update_request(req, freq) < 0)
11261124 pr_warn("Failed to update freq constraint: CPU%d\n", i);
11271125 }
11281126 }
@@ -1153,7 +1151,7 @@ static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, · 24 unmodified lines
11531151 if (intel_pstate_driver == &intel_pstate)
11541152 intel_pstate_update_policies();
11551153 else
1156− update_qos_request(DEV_PM_QOS_MAX_FREQUENCY);
1154+ update_qos_request(FREQ_QOS_MAX);
11571155
11581156 mutex_unlock(&intel_pstate_driver_lock);
11591157
@@ -1187,7 +1185,7 @@ static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, · 27 unmodified lines
11871185 if (intel_pstate_driver == &intel_pstate)
11881186 intel_pstate_update_policies();
11891187 else
1190− update_qos_request(DEV_PM_QOS_MIN_FREQUENCY);
1188+ update_qos_request(FREQ_QOS_MIN);
11911189
11921190 mutex_unlock(&intel_pstate_driver_lock);
11931191
@@ -2381,7 +2379,7 @@ static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, · 1187 unmodified lines
23812379 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
23822380 {
23832381 int max_state, turbo_max, min_freq, max_freq, ret;
2384− struct dev_pm_qos_request *req;
2382+ struct freq_qos_request *req;
23852383 struct cpudata *cpu;
23862384 struct device *dev;
23872385
@@ -2416,15 +2414,15 @@ static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) · 28 unmodified lines
24162414 max_freq = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
24172415 max_freq *= cpu->pstate.scaling;
24182416
2419− ret = dev_pm_qos_add_request(dev, req, DEV_PM_QOS_MIN_FREQUENCY,
2420− min_freq);
2417+ ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
2418+ min_freq);
24212419 if (ret < 0) {
24222420 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
24232421 goto free_req;
24242422 }
24252423
2426− ret = dev_pm_qos_add_request(dev, req + 1, DEV_PM_QOS_MAX_FREQUENCY,
2427− max_freq);
2424+ ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
2425+ max_freq);
24282426 if (ret < 0) {
24292427 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
24302428 goto remove_min_req;
@@ -2435,7 +2433,7 @@ static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) · 4 unmodified lines
24352433 return 0;
24362434
24372435 remove_min_req:
2438− dev_pm_qos_remove_request(req);
2436+ freq_qos_remove_request(req);
24392437 free_req:
24402438 kfree(req);
24412439 pstate_exit:
@@ -2446,12 +2444,12 @@ pstate_exit: · 4 unmodified lines
24462444
24472445 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
24482446 {
2449− struct dev_pm_qos_request *req;
2447+ struct freq_qos_request *req;
24502448
24512449 req = policy->driver_data;
24522450
2453− dev_pm_qos_remove_request(req + 1);
2454− dev_pm_qos_remove_request(req);
2451+ freq_qos_remove_request(req + 1);
2452+ freq_qos_remove_request(req);
24552453 kfree(req);
24562454
24572455 return intel_pstate_cpu_exit(policy);
drivers/cpufreq/ppc_cbe_cpufreq_pmi.c+7−8
@@ -65,7 +65,7 @@ EXPORT_SYMBOL_GPL(cbe_cpufreq_set_pmode_pmi); · 64 unmodified lines
6565 static void cbe_cpufreq_handle_pmi(pmi_message_t pmi_msg)
6666 {
6767 struct cpufreq_policy *policy;
68− struct dev_pm_qos_request *req;
68+ struct freq_qos_request *req;
6969 u8 node, slow_mode;
7070 int cpu, ret;
7171
@@ -86,7 +86,7 @@ static void cbe_cpufreq_handle_pmi(pmi_message_t pmi_msg) · 14 unmodified lines
8686
8787 req = policy->driver_data;
8888
89− ret = dev_pm_qos_update_request(req,
89+ ret = freq_qos_update_request(req,
9090 policy->freq_table[slow_mode].frequency);
9191 if (ret < 0)
9292 pr_warn("Failed to update freq constraint: %d\n", ret);
@@ -103,7 +103,7 @@ static struct pmi_handler cbe_pmi_handler = { · 10 unmodified lines
103103
104104 void cbe_cpufreq_pmi_policy_init(struct cpufreq_policy *policy)
105105 {
106− struct dev_pm_qos_request *req;
106+ struct freq_qos_request *req;
107107 int ret;
108108
109109 if (!cbe_cpufreq_has_pmi)
@@ -113,9 +113,8 @@ void cbe_cpufreq_pmi_policy_init(struct cpufreq_policy *policy) · 3 unmodified lines
113113 if (!req)
114114 return;
115115
116− ret = dev_pm_qos_add_request(get_cpu_device(policy->cpu), req,
117− DEV_PM_QOS_MAX_FREQUENCY,
118− policy->freq_table[0].frequency);
116+ ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MAX,
117+ policy->freq_table[0].frequency);
119118 if (ret < 0) {
120119 pr_err("Failed to add freq constraint (%d)\n", ret);
121120 kfree(req);
@@ -128,10 +127,10 @@ EXPORT_SYMBOL_GPL(cbe_cpufreq_pmi_policy_init); · 6 unmodified lines
128127
129128 void cbe_cpufreq_pmi_policy_exit(struct cpufreq_policy *policy)
130129 {
131− struct dev_pm_qos_request *req = policy->driver_data;
130+ struct freq_qos_request *req = policy->driver_data;
132131
133132 if (cbe_cpufreq_has_pmi) {
134− dev_pm_qos_remove_request(req);
133+ freq_qos_remove_request(req);
135134 kfree(req);
136135 }
137136 }
drivers/cpuidle/cpuidle-haltpoll.c+4−0
@@ -95,6 +95,10 @@ static int __init haltpoll_init(void) · 94 unmodified lines
9595 int ret;
9696 struct cpuidle_driver *drv = &haltpoll_driver;
9797
98+ /* Do not load haltpoll if idle= is passed */
99+ if (boot_option_idle_override != IDLE_NO_OVERRIDE)
100+ return -ENODEV;
101+
98102 cpuidle_poll_state_init(drv);
99103
100104 if (!kvm_para_available() ||
drivers/crypto/chelsio/chtls/chtls_cm.c+1−1
@@ -1297,7 +1297,7 @@ static void make_established(struct sock *sk, u32 snd_isn, unsigned int opt) · 1296 unmodified lines
12971297 tp->write_seq = snd_isn;
12981298 tp->snd_nxt = snd_isn;
12991299 tp->snd_una = snd_isn;
1300− inet_sk(sk)->inet_id = tp->write_seq ^ jiffies;
1300+ inet_sk(sk)->inet_id = prandom_u32();
13011301 assign_rxopt(sk, opt);
13021302
13031303 if (tp->rcv_wnd > (RCV_BUFSIZ_M << 10))
drivers/crypto/chelsio/chtls/chtls_io.c+1−1
@@ -1702,7 +1702,7 @@ int chtls_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, · 1701 unmodified lines
17021702 return peekmsg(sk, msg, len, nonblock, flags);
17031703
17041704 if (sk_can_busy_loop(sk) &&
1705− skb_queue_empty(&sk->sk_receive_queue) &&
1705+ skb_queue_empty_lockless(&sk->sk_receive_queue) &&
17061706 sk->sk_state == TCP_ESTABLISHED)
17071707 sk_busy_loop(sk, nonblock);
17081708
drivers/dma-buf/dma-buf.c+95−25
@@ -45,10 +45,10 @@ static char *dmabuffs_dname(struct dentry *dentry, char *buffer, int buflen) · 44 unmodified lines
4545 size_t ret = 0;
4646
4747 dmabuf = dentry->d_fsdata;
48− mutex_lock(&dmabuf->lock);
48+ dma_resv_lock(dmabuf->resv, NULL);
4949 if (dmabuf->name)
5050 ret = strlcpy(name, dmabuf->name, DMA_BUF_NAME_LEN);
51− mutex_unlock(&dmabuf->lock);
51+ dma_resv_unlock(dmabuf->resv);
5252
5353 return dynamic_dname(dentry, buffer, buflen, "/%s:%s",
5454 dentry->d_name.name, ret > 0 ? name : "");
@@ -334,7 +334,7 @@ static long dma_buf_set_name(struct dma_buf *dmabuf, const char __user *buf) · 279 unmodified lines
334334 if (IS_ERR(name))
335335 return PTR_ERR(name);
336336
337− mutex_lock(&dmabuf->lock);
337+ dma_resv_lock(dmabuf->resv, NULL);
338338 if (!list_empty(&dmabuf->attachments)) {
339339 ret = -EBUSY;
340340 kfree(name);
@@ -344,7 +344,7 @@ static long dma_buf_set_name(struct dma_buf *dmabuf, const char __user *buf) · 3 unmodified lines
344344 dmabuf->name = name;
345345
346346 out_unlock:
347− mutex_unlock(&dmabuf->lock);
347+ dma_resv_unlock(dmabuf->resv);
348348 return ret;
349349 }
350350
@@ -403,10 +403,10 @@ static void dma_buf_show_fdinfo(struct seq_file *m, struct file *file) · 52 unmodified lines
403403 /* Don't count the temporary reference taken inside procfs seq_show */
404404 seq_printf(m, "count:\t%ld\n", file_count(dmabuf->file) - 1);
405405 seq_printf(m, "exp_name:\t%s\n", dmabuf->exp_name);
406− mutex_lock(&dmabuf->lock);
406+ dma_resv_lock(dmabuf->resv, NULL);
407407 if (dmabuf->name)
408408 seq_printf(m, "name:\t%s\n", dmabuf->name);
409− mutex_unlock(&dmabuf->lock);
409+ dma_resv_unlock(dmabuf->resv);
410410 }
411411
412412 static const struct file_operations dma_buf_fops = {
@@ -525,6 +525,10 @@ struct dma_buf *dma_buf_export(const struct dma_buf_export_info *exp_info) · 112 unmodified lines
525525 return ERR_PTR(-EINVAL);
526526 }
527527
528+ if (WARN_ON(exp_info->ops->cache_sgt_mapping &&
529+ exp_info->ops->dynamic_mapping))
530+ return ERR_PTR(-EINVAL);
531+
528532 if (!try_module_get(exp_info->owner))
529533 return ERR_PTR(-ENOENT);
530534
@@ -645,10 +649,11 @@ void dma_buf_put(struct dma_buf *dmabuf) · 114 unmodified lines
645649 EXPORT_SYMBOL_GPL(dma_buf_put);
646650
647651 /**
648− * dma_buf_attach - Add the device to dma_buf's attachments list; optionally,
652+ * dma_buf_dynamic_attach - Add the device to dma_buf's attachments list; optionally,
649653 * calls attach() of dma_buf_ops to allow device-specific attach functionality
650− * @dmabuf: [in] buffer to attach device to.
651− * @dev: [in] device to be attached.
654+ * @dmabuf: [in] buffer to attach device to.
655+ * @dev: [in] device to be attached.
656+ * @dynamic_mapping: [in] calling convention for map/unmap
652657 *
653658 * Returns struct dma_buf_attachment pointer for this attachment. Attachments
654659 * must be cleaned up by calling dma_buf_detach().
@@ -662,8 +667,9 @@ EXPORT_SYMBOL_GPL(dma_buf_put); · 7 unmodified lines
662667 * accessible to @dev, and cannot be moved to a more suitable place. This is
663668 * indicated with the error code -EBUSY.
664669 */
665−struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,
666− struct device *dev)
670+struct dma_buf_attachment *
671+dma_buf_dynamic_attach(struct dma_buf *dmabuf, struct device *dev,
672+ bool dynamic_mapping)
667673 {
668674 struct dma_buf_attachment *attach;
669675 int ret;
@@ -677,25 +683,69 @@ struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf, · 7 unmodified lines
677683
678684 attach->dev = dev;
679685 attach->dmabuf = dmabuf;
680−
681− mutex_lock(&dmabuf->lock);
686+ attach->dynamic_mapping = dynamic_mapping;
682687
683688 if (dmabuf->ops->attach) {
684689 ret = dmabuf->ops->attach(dmabuf, attach);
685690 if (ret)
686691 goto err_attach;
687692 }
693+ dma_resv_lock(dmabuf->resv, NULL);
688694 list_add(&attach->node, &dmabuf->attachments);
695+ dma_resv_unlock(dmabuf->resv);
689696
690− mutex_unlock(&dmabuf->lock);
697+ /* When either the importer or the exporter can't handle dynamic
698+ * mappings we cache the mapping here to avoid issues with the
699+ * reservation object lock.
700+ */
701+ if (dma_buf_attachment_is_dynamic(attach) !=
702+ dma_buf_is_dynamic(dmabuf)) {
703+ struct sg_table *sgt;
704+
705+ if (dma_buf_is_dynamic(attach->dmabuf))
706+ dma_resv_lock(attach->dmabuf->resv, NULL);
707+
708+ sgt = dmabuf->ops->map_dma_buf(attach, DMA_BIDIRECTIONAL);
709+ if (!sgt)
710+ sgt = ERR_PTR(-ENOMEM);
711+ if (IS_ERR(sgt)) {
712+ ret = PTR_ERR(sgt);
713+ goto err_unlock;
714+ }
715+ if (dma_buf_is_dynamic(attach->dmabuf))
716+ dma_resv_unlock(attach->dmabuf->resv);
717+ attach->sgt = sgt;
718+ attach->dir = DMA_BIDIRECTIONAL;
719+ }
691720
692721 return attach;
693722
694723 err_attach:
695724 kfree(attach);
696− mutex_unlock(&dmabuf->lock);
725+ return ERR_PTR(ret);
726+
727+err_unlock:
728+ if (dma_buf_is_dynamic(attach->dmabuf))
729+ dma_resv_unlock(attach->dmabuf->resv);
730+
731+ dma_buf_detach(dmabuf, attach);
697732 return ERR_PTR(ret);
698733 }
734+EXPORT_SYMBOL_GPL(dma_buf_dynamic_attach);
735+
736+/**
737+ * dma_buf_attach - Wrapper for dma_buf_dynamic_attach
738+ * @dmabuf: [in] buffer to attach device to.
739+ * @dev: [in] device to be attached.
740+ *
741+ * Wrapper to call dma_buf_dynamic_attach() for drivers which still use a static
742+ * mapping.
743+ */
744+struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,
745+ struct device *dev)
746+{
747+ return dma_buf_dynamic_attach(dmabuf, dev, false);
748+}
699749 EXPORT_SYMBOL_GPL(dma_buf_attach);
700750
701751 /**
@@ -711,15 +761,22 @@ void dma_buf_detach(struct dma_buf *dmabuf, struct dma_buf_attachment *attach) · 9 unmodified lines
711761 if (WARN_ON(!dmabuf || !attach))
712762 return;
713763
714− if (attach->sgt)
764+ if (attach->sgt) {
765+ if (dma_buf_is_dynamic(attach->dmabuf))
766+ dma_resv_lock(attach->dmabuf->resv, NULL);
767+
715768 dmabuf->ops->unmap_dma_buf(attach, attach->sgt, attach->dir);
716769
717− mutex_lock(&dmabuf->lock);
770+ if (dma_buf_is_dynamic(attach->dmabuf))
771+ dma_resv_unlock(attach->dmabuf->resv);
772+ }
773+
774+ dma_resv_lock(dmabuf->resv, NULL);
718775 list_del(&attach->node);
776+ dma_resv_unlock(dmabuf->resv);
719777 if (dmabuf->ops->detach)
720778 dmabuf->ops->detach(dmabuf, attach);
721779
722− mutex_unlock(&dmabuf->lock);
723780 kfree(attach);
724781 }
725782 EXPORT_SYMBOL_GPL(dma_buf_detach);
@@ -749,6 +806,9 @@ struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *attach, · 23 unmodified lines
749806 if (WARN_ON(!attach || !attach->dmabuf))
750807 return ERR_PTR(-EINVAL);
751808
809+ if (dma_buf_attachment_is_dynamic(attach))
810+ dma_resv_assert_held(attach->dmabuf->resv);
811+
752812 if (attach->sgt) {
753813 /*
754814 * Two mappings with different directions for the same
@@ -761,6 +821,9 @@ struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *attach, · 6 unmodified lines
761821 return attach->sgt;
762822 }
763823
824+ if (dma_buf_is_dynamic(attach->dmabuf))
825+ dma_resv_assert_held(attach->dmabuf->resv);
826+
764827 sg_table = attach->dmabuf->ops->map_dma_buf(attach, direction);
765828 if (!sg_table)
766829 sg_table = ERR_PTR(-ENOMEM);
@@ -793,9 +856,15 @@ void dma_buf_unmap_attachment(struct dma_buf_attachment *attach, · 26 unmodified lines
793856 if (WARN_ON(!attach || !attach->dmabuf || !sg_table))
794857 return;
795858
859+ if (dma_buf_attachment_is_dynamic(attach))
860+ dma_resv_assert_held(attach->dmabuf->resv);
861+
796862 if (attach->sgt == sg_table)
797863 return;
798864
865+ if (dma_buf_is_dynamic(attach->dmabuf))
866+ dma_resv_assert_held(attach->dmabuf->resv);
867+
799868 attach->dmabuf->ops->unmap_dma_buf(attach, sg_table, direction);
800869 }
801870 EXPORT_SYMBOL_GPL(dma_buf_unmap_attachment);
@@ -1171,13 +1240,10 @@ static int dma_buf_debug_show(struct seq_file *s, void *unused) · 369 unmodified lines
11711240 "size", "flags", "mode", "count", "ino");
11721241
11731242 list_for_each_entry(buf_obj, &db_list.head, list_node) {
1174− ret = mutex_lock_interruptible(&buf_obj->lock);
11751243
1176− if (ret) {
1177− seq_puts(s,
1178− "\tERROR locking buffer object: skipping\n");
1179− continue;
1180− }
1244+ ret = dma_resv_lock_interruptible(buf_obj->resv, NULL);
1245+ if (ret)
1246+ goto error_unlock;
11811247
11821248 seq_printf(s, "%08zu\t%08x\t%08x\t%08ld\t%s\t%08lu\t%s\n",
11831249 buf_obj->size,
@@ -1223,19 +1289,23 @@ static int dma_buf_debug_show(struct seq_file *s, void *unused) · 39 unmodified lines
12231289 seq_printf(s, "\t%s\n", dev_name(attach_obj->dev));
12241290 attach_count++;
12251291 }
1292+ dma_resv_unlock(buf_obj->resv);
12261293
12271294 seq_printf(s, "Total %d devices attached\n\n",
12281295 attach_count);
12291296
12301297 count++;
12311298 size += buf_obj->size;
1232− mutex_unlock(&buf_obj->lock);
12331299 }
12341300
12351301 seq_printf(s, "\nTotal %d objects, %zu bytes\n", count, size);
12361302
12371303 mutex_unlock(&db_list.lock);
12381304 return 0;
1305+
1306+error_unlock:
1307+ mutex_unlock(&db_list.lock);
1308+ return ret;
12391309 }
12401310
12411311 DEFINE_SHOW_ATTRIBUTE(dma_buf_debug);
drivers/dma/imx-sdma.c+8−0
@@ -1707,6 +1707,14 @@ static void sdma_add_scripts(struct sdma_engine *sdma, · 1706 unmodified lines
17071707 if (!sdma->script_number)
17081708 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
17091709
1710+ if (sdma->script_number > sizeof(struct sdma_script_start_addrs)
1711+ / sizeof(s32)) {
1712+ dev_err(sdma->dev,
1713+ "SDMA script number %d not match with firmware.\n",
1714+ sdma->script_number);
1715+ return;
1716+ }
1717+
17101718 for (i = 0; i < sdma->script_number; i++)
17111719 if (addr_arr[i] > 0)
17121720 saddr_arr[i] = addr_arr[i];
drivers/dma/qcom/bam_dma.c+19−0
@@ -694,6 +694,25 @@ static int bam_dma_terminate_all(struct dma_chan *chan) · 693 unmodified lines
694694
695695 /* remove all transactions, including active transaction */
696696 spin_lock_irqsave(&bchan->vc.lock, flag);
697+ /*
698+ * If we have transactions queued, then some might be committed to the
699+ * hardware in the desc fifo. The only way to reset the desc fifo is
700+ * to do a hardware reset (either by pipe or the entire block).
701+ * bam_chan_init_hw() will trigger a pipe reset, and also reinit the
702+ * pipe. If the pipe is left disabled (default state after pipe reset)
703+ * and is accessed by a connected hardware engine, a fatal error in
704+ * the BAM will occur. There is a small window where this could happen
705+ * with bam_chan_init_hw(), but it is assumed that the caller has
706+ * stopped activity on any attached hardware engine. Make sure to do
707+ * this first so that the BAM hardware doesn't cause memory corruption
708+ * by accessing freed resources.
709+ */
710+ if (!list_empty(&bchan->desc_list)) {
711+ async_desc = list_first_entry(&bchan->desc_list,
712+ struct bam_async_desc, desc_node);
713+ bam_chan_init_hw(bchan, async_desc->dir);
714+ }
715+
697716 list_for_each_entry_safe(async_desc, tmp,
698717 &bchan->desc_list, desc_node) {
699718 list_add(&async_desc->vd.node, &bchan->vc.desc_issued);
drivers/dma/sprd-dma.c+25−2
@@ -134,6 +134,10 @@ · 133 unmodified lines
134134 #define SPRD_DMA_SRC_TRSF_STEP_OFFSET 0
135135 #define SPRD_DMA_TRSF_STEP_MASK GENMASK(15, 0)
136136
137+/* SPRD DMA_SRC_BLK_STEP register definition */
138+#define SPRD_DMA_LLIST_HIGH_MASK GENMASK(31, 28)
139+#define SPRD_DMA_LLIST_HIGH_SHIFT 28
140+
137141 /* define DMA channel mode & trigger mode mask */
138142 #define SPRD_DMA_CHN_MODE_MASK GENMASK(7, 0)
139143 #define SPRD_DMA_TRG_MODE_MASK GENMASK(7, 0)
@@ -208,6 +212,7 @@ struct sprd_dma_dev { · 68 unmodified lines
208212 struct sprd_dma_chn channels[0];
209213 };
210214
215+static void sprd_dma_free_desc(struct virt_dma_desc *vd);
211216 static bool sprd_dma_filter_fn(struct dma_chan *chan, void *param);
212217 static struct of_dma_filter_info sprd_dma_info = {
213218 .filter_fn = sprd_dma_filter_fn,
@@ -609,12 +614,19 @@ static int sprd_dma_alloc_chan_resources(struct dma_chan *chan) · 395 unmodified lines
609614 static void sprd_dma_free_chan_resources(struct dma_chan *chan)
610615 {
611616 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
617+ struct virt_dma_desc *cur_vd = NULL;
612618 unsigned long flags;
613619
614620 spin_lock_irqsave(&schan->vc.lock, flags);
621+ if (schan->cur_desc)
622+ cur_vd = &schan->cur_desc->vd;
623+
615624 sprd_dma_stop(schan);
616625 spin_unlock_irqrestore(&schan->vc.lock, flags);
617626
627+ if (cur_vd)
628+ sprd_dma_free_desc(cur_vd);
629+
618630 vchan_free_chan_resources(&schan->vc);
619631 pm_runtime_put(chan->device->dev);
620632 }
@@ -717,6 +729,7 @@ static int sprd_dma_fill_desc(struct dma_chan *chan, · 96 unmodified lines
717729 u32 int_mode = flags & SPRD_DMA_INT_MASK;
718730 int src_datawidth, dst_datawidth, src_step, dst_step;
719731 u32 temp, fix_mode = 0, fix_en = 0;
732+ phys_addr_t llist_ptr;
720733
721734 if (dir == DMA_MEM_TO_DEV) {
722735 src_step = sprd_dma_get_step(slave_cfg->src_addr_width);
@@ -814,13 +827,16 @@ static int sprd_dma_fill_desc(struct dma_chan *chan, · 91 unmodified lines
814827 * Set the link-list pointer point to next link-list
815828 * configuration's physical address.
816829 */
817− hw->llist_ptr = schan->linklist.phy_addr + temp;
830+ llist_ptr = schan->linklist.phy_addr + temp;
831+ hw->llist_ptr = lower_32_bits(llist_ptr);
832+ hw->src_blk_step = (upper_32_bits(llist_ptr) << SPRD_DMA_LLIST_HIGH_SHIFT) &
833+ SPRD_DMA_LLIST_HIGH_MASK;
818834 } else {
819835 hw->llist_ptr = 0;
836+ hw->src_blk_step = 0;
820837 }
821838
822839 hw->frg_step = 0;
823− hw->src_blk_step = 0;
824840 hw->des_blk_step = 0;
825841 return 0;
826842 }
@@ -1023,15 +1039,22 @@ static int sprd_dma_resume(struct dma_chan *chan) · 196 unmodified lines
10231039 static int sprd_dma_terminate_all(struct dma_chan *chan)
10241040 {
10251041 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
1042+ struct virt_dma_desc *cur_vd = NULL;
10261043 unsigned long flags;
10271044 LIST_HEAD(head);
10281045
10291046 spin_lock_irqsave(&schan->vc.lock, flags);
1047+ if (schan->cur_desc)
1048+ cur_vd = &schan->cur_desc->vd;
1049+
10301050 sprd_dma_stop(schan);
10311051
10321052 vchan_get_all_descriptors(&schan->vc, &head);
10331053 spin_unlock_irqrestore(&schan->vc.lock, flags);
10341054
1055+ if (cur_vd)
1056+ sprd_dma_free_desc(cur_vd);
1057+
10351058 vchan_dma_desc_free_list(&schan->vc, &head);
10361059 return 0;
10371060 }
drivers/dma/tegra210-adma.c+7−0
@@ -40,6 +40,7 @@ · 39 unmodified lines
4040 #define ADMA_CH_CONFIG_MAX_BURST_SIZE 16
4141 #define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0xf)
4242 #define ADMA_CH_CONFIG_MAX_BUFS 8
43+#define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) (reqs << 4)
4344
4445 #define ADMA_CH_FIFO_CTRL 0x2c
4546 #define TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0xf) << 8)
@@ -77,6 +78,7 @@ struct tegra_adma; · 31 unmodified lines
7778 * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
7879 * @ch_req_rx_shift: Register offset for AHUB receive channel select.
7980 * @ch_base_offset: Register offset of DMA channel registers.
81+ * @has_outstanding_reqs: If DMA channel can have outstanding requests.
8082 * @ch_fifo_ctrl: Default value for channel FIFO CTRL register.
8183 * @ch_req_mask: Mask for Tx or Rx channel select.
8284 * @ch_req_max: Maximum number of Tx or Rx channels available.
@@ -95,6 +97,7 @@ struct tegra_adma_chip_data { · 12 unmodified lines
9597 unsigned int ch_req_max;
9698 unsigned int ch_reg_size;
9799 unsigned int nr_channels;
100+ bool has_outstanding_reqs;
98101 };
99102
100103 /*
@@ -594,6 +597,8 @@ static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc, · 493 unmodified lines
594597 ADMA_CH_CTRL_FLOWCTRL_EN;
595598 ch_regs->config |= cdata->adma_get_burst_config(burst_size);
596599 ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
600+ if (cdata->has_outstanding_reqs)
601+ ch_regs->config |= TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8);
597602 ch_regs->fifo_ctrl = cdata->ch_fifo_ctrl;
598603 ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
599604
@@ -778,6 +783,7 @@ static const struct tegra_adma_chip_data tegra210_chip_data = { · 178 unmodified lines
778783 .ch_req_tx_shift = 28,
779784 .ch_req_rx_shift = 24,
780785 .ch_base_offset = 0,
786+ .has_outstanding_reqs = false,
781787 .ch_fifo_ctrl = TEGRA210_FIFO_CTRL_DEFAULT,
782788 .ch_req_mask = 0xf,
783789 .ch_req_max = 10,
@@ -792,6 +798,7 @@ static const struct tegra_adma_chip_data tegra186_chip_data = { · 8 unmodified lines
792798 .ch_req_tx_shift = 27,
793799 .ch_req_rx_shift = 22,
794800 .ch_base_offset = 0x10000,
801+ .has_outstanding_reqs = true,
795802 .ch_fifo_ctrl = TEGRA186_FIFO_CTRL_DEFAULT,
796803 .ch_req_mask = 0x1f,
797804 .ch_req_max = 20,
drivers/dma/ti/cppi41.c+20−1
@@ -586,9 +586,22 @@ static struct dma_async_tx_descriptor *cppi41_dma_prep_slave_sg( · 585 unmodified lines
586586 enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
587587 {
588588 struct cppi41_channel *c = to_cpp41_chan(chan);
589+ struct dma_async_tx_descriptor *txd = NULL;
590+ struct cppi41_dd *cdd = c->cdd;
589591 struct cppi41_desc *d;
590592 struct scatterlist *sg;
591593 unsigned int i;
594+ int error;
595+
596+ error = pm_runtime_get(cdd->ddev.dev);
597+ if (error < 0) {
598+ pm_runtime_put_noidle(cdd->ddev.dev);
599+
600+ return NULL;
601+ }
602+
603+ if (cdd->is_suspended)
604+ goto err_out_not_ready;
592605
593606 d = c->desc;
594607 for_each_sg(sgl, sg, sg_len, i) {
@@ -611,7 +624,13 @@ static struct dma_async_tx_descriptor *cppi41_dma_prep_slave_sg( · 16 unmodified lines
611624 d++;
612625 }
613626
614− return &c->txd;
627+ txd = &c->txd;
628+
629+err_out_not_ready:
630+ pm_runtime_mark_last_busy(cdd->ddev.dev);
631+ pm_runtime_put_autosuspend(cdd->ddev.dev);
632+
633+ return txd;
615634 }
616635
617636 static void cppi41_compute_td_desc(struct cppi41_desc *d)
drivers/dma/xilinx/xilinx_dma.c+9−1
@@ -68,6 +68,9 @@ · 67 unmodified lines
6868 #define XILINX_DMA_DMACR_CIRC_EN BIT(1)
6969 #define XILINX_DMA_DMACR_RUNSTOP BIT(0)
7070 #define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5)
71+#define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24)
72+#define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16)
73+#define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8)
7174
7275 #define XILINX_DMA_REG_DMASR 0x0004
7376 #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15)
@@ -1354,7 +1357,8 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) · 1280 unmodified lines
13541357 node);
13551358 hw = &segment->hw;
13561359
1357− xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr);
1360+ xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR,
1361+ xilinx_prep_dma_addr_t(hw->buf_addr));
13581362
13591363 /* Start the transfer */
13601364 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
@@ -2117,8 +2121,10 @@ int xilinx_vdma_channel_set_config(struct dma_chan *dchan, · 756 unmodified lines
21172121 chan->config.gen_lock = cfg->gen_lock;
21182122 chan->config.master = cfg->master;
21192123
2124+ dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;
21202125 if (cfg->gen_lock && chan->genlock) {
21212126 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
2127+ dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;
21222128 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
21232129 }
21242130
@@ -2134,11 +2140,13 @@ int xilinx_vdma_channel_set_config(struct dma_chan *dchan, · 9 unmodified lines
21342140 chan->config.delay = cfg->delay;
21352141
21362142 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
2143+ dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;
21372144 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
21382145 chan->config.coalesc = cfg->coalesc;
21392146 }
21402147
21412148 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
2149+ dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;
21422150 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
21432151 chan->config.delay = cfg->delay;
21442152 }
drivers/edac/ghes_edac.c+4−0
@@ -553,7 +553,11 @@ void ghes_edac_unregister(struct ghes *ghes) · 552 unmodified lines
553553 if (!ghes_pvt)
554554 return;
555555
556+ if (atomic_dec_return(&ghes_init))
557+ return;
558+
556559 mci = ghes_pvt->mci;
560+ ghes_pvt = NULL;
557561 edac_mc_del_mc(mci->pdev);
558562 edac_mc_free(mci);
559563 }
drivers/firmware/dmi_scan.c+1−1
@@ -408,7 +408,7 @@ static void __init save_mem_devices(const struct dmi_header *dm, void *v) · 407 unmodified lines
408408 bytes = ~0ull;
409409 else if (size & 0x8000)
410410 bytes = (u64)(size & 0x7fff) << 10;
411− else if (size != 0x7fff)
411+ else if (size != 0x7fff || dm->length < 0x20)
412412 bytes = (u64)size << 20;
413413 else
414414 bytes = (u64)get_unaligned((u32 *)&d[0x1C]) << 20;
drivers/firmware/efi/Kconfig+1−0
@@ -182,6 +182,7 @@ config RESET_ATTACK_MITIGATION · 181 unmodified lines
182182
183183 config EFI_RCI2_TABLE
184184 bool "EFI Runtime Configuration Interface Table Version 2 Support"
185+ depends on X86 || COMPILE_TEST
185186 help
186187 Displays the content of the Runtime Configuration Interface
187188 Table version 2 on Dell EMC PowerEdge systems as a binary
drivers/firmware/efi/cper.c+1−1
@@ -381,7 +381,7 @@ static void cper_print_pcie(const char *pfx, const struct cper_sec_pcie *pcie, · 380 unmodified lines
381381 printk("%s""vendor_id: 0x%04x, device_id: 0x%04x\n", pfx,
382382 pcie->device_id.vendor_id, pcie->device_id.device_id);
383383 p = pcie->device_id.class_code;
384− printk("%s""class_code: %02x%02x%02x\n", pfx, p[0], p[1], p[2]);
384+ printk("%s""class_code: %02x%02x%02x\n", pfx, p[2], p[1], p[0]);
385385 }
386386 if (pcie->validation_bits & CPER_PCIE_VALID_SERIAL_NUMBER)
387387 printk("%s""serial number: 0x%04x, 0x%04x\n", pfx,
drivers/firmware/efi/efi.c+4−1
@@ -267,6 +267,9 @@ static __init int efivar_ssdt_load(void) · 266 unmodified lines
267267 void *data;
268268 int ret;
269269
270+ if (!efivar_ssdt[0])
271+ return 0;
272+
270273 ret = efivar_init(efivar_ssdt_iter, &entries, true, &entries);
271274
272275 list_for_each_entry_safe(entry, aux, &entries, list) {
@@ -551,7 +554,7 @@ int __init efi_config_parse_tables(void *config_tables, int count, int sz, · 278 unmodified lines
551554 sizeof(*seed) + size);
552555 if (seed != NULL) {
553556 pr_notice("seeding entropy pool\n");
554− add_device_randomness(seed->bits, seed->size);
557+ add_bootloader_randomness(seed->bits, seed->size);
555558 early_memunmap(seed, sizeof(*seed) + size);
556559 } else {
557560 pr_err("Could not map UEFI random seed!\n");
drivers/firmware/efi/libstub/Makefile+1−0
@@ -52,6 +52,7 @@ lib-$(CONFIG_EFI_ARMSTUB) += arm-stub.o fdt.o string.o random.o \ · 51 unmodified lines
5252
5353 lib-$(CONFIG_ARM) += arm32-stub.o
5454 lib-$(CONFIG_ARM64) += arm64-stub.o
55+CFLAGS_arm32-stub.o := -DTEXT_OFFSET=$(TEXT_OFFSET)
5556 CFLAGS_arm64-stub.o := -DTEXT_OFFSET=$(TEXT_OFFSET)
5657
5758 #
drivers/firmware/efi/libstub/arm32-stub.c+13−3
@@ -195,6 +195,7 @@ efi_status_t handle_kernel_image(efi_system_table_t *sys_table, · 194 unmodified lines
195195 unsigned long dram_base,
196196 efi_loaded_image_t *image)
197197 {
198+ unsigned long kernel_base;
198199 efi_status_t status;
199200
200201 /*
@@ -204,9 +205,18 @@ efi_status_t handle_kernel_image(efi_system_table_t *sys_table, · 3 unmodified lines
204205 * loaded. These assumptions are made by the decompressor,
205206 * before any memory map is available.
206207 */
207− dram_base = round_up(dram_base, SZ_128M);
208+ kernel_base = round_up(dram_base, SZ_128M);
208209
209− status = reserve_kernel_base(sys_table, dram_base, reserve_addr,
210+ /*
211+ * Note that some platforms (notably, the Raspberry Pi 2) put
212+ * spin-tables and other pieces of firmware at the base of RAM,
213+ * abusing the fact that the window of TEXT_OFFSET bytes at the
214+ * base of the kernel image is only partially used at the moment.
215+ * (Up to 5 pages are used for the swapper page tables)
216+ */
217+ kernel_base += TEXT_OFFSET - 5 * PAGE_SIZE;
218+
219+ status = reserve_kernel_base(sys_table, kernel_base, reserve_addr,
210220 reserve_size);
211221 if (status != EFI_SUCCESS) {
212222 pr_efi_err(sys_table, "Unable to allocate memory for uncompressed kernel.\n");
@@ -220,7 +230,7 @@ efi_status_t handle_kernel_image(efi_system_table_t *sys_table, · 7 unmodified lines
220230 *image_size = image->image_size;
221231 status = efi_relocate_kernel(sys_table, image_addr, *image_size,
222232 *image_size,
223− dram_base + MAX_UNCOMP_KERNEL_SIZE, 0);
233+ kernel_base + MAX_UNCOMP_KERNEL_SIZE, 0, 0);
224234 if (status != EFI_SUCCESS) {
225235 pr_efi_err(sys_table, "Failed to relocate kernel.\n");
226236 efi_free(sys_table, *reserve_size, *reserve_addr);
drivers/firmware/efi/libstub/efi-stub-helper.c+10−14
@@ -260,11 +260,11 @@ fail: · 259 unmodified lines
260260 }
261261
262262 /*
263− * Allocate at the lowest possible address.
263+ * Allocate at the lowest possible address that is not below 'min'.
264264 */
265−efi_status_t efi_low_alloc(efi_system_table_t *sys_table_arg,
266− unsigned long size, unsigned long align,
267− unsigned long *addr)
265+efi_status_t efi_low_alloc_above(efi_system_table_t *sys_table_arg,
266+ unsigned long size, unsigned long align,
267+ unsigned long *addr, unsigned long min)
268268 {
269269 unsigned long map_size, desc_size, buff_size;
270270 efi_memory_desc_t *map;
@@ -311,13 +311,8 @@ efi_status_t efi_low_alloc(efi_system_table_t *sys_table_arg, · 40 unmodified lines
311311 start = desc->phys_addr;
312312 end = start + desc->num_pages * EFI_PAGE_SIZE;
313313
314− /*
315− * Don't allocate at 0x0. It will confuse code that
316− * checks pointers against NULL. Skip the first 8
317− * bytes so we start at a nice even number.
318− */
319− if (start == 0x0)
320− start += 8;
314+ if (start < min)
315+ start = min;
321316
322317 start = round_up(start, align);
323318 if ((start + size) > end)
@@ -698,7 +693,8 @@ efi_status_t efi_relocate_kernel(efi_system_table_t *sys_table_arg, · 374 unmodified lines
698693 unsigned long image_size,
699694 unsigned long alloc_size,
700695 unsigned long preferred_addr,
701− unsigned long alignment)
696+ unsigned long alignment,
697+ unsigned long min_addr)
702698 {
703699 unsigned long cur_image_addr;
704700 unsigned long new_addr = 0;
@@ -731,8 +727,8 @@ efi_status_t efi_relocate_kernel(efi_system_table_t *sys_table_arg, · 26 unmodified lines
731727 * possible.
732728 */
733729 if (status != EFI_SUCCESS) {
734− status = efi_low_alloc(sys_table_arg, alloc_size, alignment,
735− &new_addr);
730+ status = efi_low_alloc_above(sys_table_arg, alloc_size,
731+ alignment, &new_addr, min_addr);
736732 }
737733 if (status != EFI_SUCCESS) {
738734 pr_efi_err(sys_table_arg, "Failed to allocate usable memory for kernel.\n");
drivers/firmware/efi/rci2-table.c+1−1
@@ -76,7 +76,7 @@ static u16 checksum(void) · 75 unmodified lines
7676 return chksum;
7777 }
7878
79−int __init efi_rci2_sysfs_init(void)
79+static int __init efi_rci2_sysfs_init(void)
8080 {
8181 struct kobject *tables_kobj;
8282 int ret = -ENOMEM;
drivers/firmware/efi/test/efi_test.c+8−0
@@ -14,6 +14,7 @@ · 13 unmodified lines
1414 #include <linux/init.h>
1515 #include <linux/proc_fs.h>
1616 #include <linux/efi.h>
17+#include <linux/security.h>
1718 #include <linux/slab.h>
1819 #include <linux/uaccess.h>
1920
@@ -717,6 +718,13 @@ static long efi_test_ioctl(struct file *file, unsigned int cmd, · 697 unmodified lines
717718
718719 static int efi_test_open(struct inode *inode, struct file *file)
719720 {
721+ int ret = security_locked_down(LOCKDOWN_EFI_TEST);
722+
723+ if (ret)
724+ return ret;
725+
726+ if (!capable(CAP_SYS_ADMIN))
727+ return -EACCES;
720728 /*
721729 * nothing special to do here
722730 * We do accept multiple open files at the same time as we
drivers/firmware/efi/tpm.c+20−7
@@ -40,7 +40,7 @@ int __init efi_tpm_eventlog_init(void) · 39 unmodified lines
4040 {
4141 struct linux_efi_tpm_eventlog *log_tbl;
4242 struct efi_tcg2_final_events_table *final_tbl;
43− unsigned int tbl_size;
43+ int tbl_size;
4444 int ret = 0;
4545
4646 if (efi.tpm_log == EFI_INVALID_TABLE_ADDR) {
@@ -75,16 +75,29 @@ int __init efi_tpm_eventlog_init(void) · 28 unmodified lines
7575 goto out;
7676 }
7777
78− tbl_size = tpm2_calc_event_log_size((void *)efi.tpm_final_log
79− + sizeof(final_tbl->version)
80− + sizeof(final_tbl->nr_events),
81− final_tbl->nr_events,
82− log_tbl->log);
78+ tbl_size = 0;
79+ if (final_tbl->nr_events != 0) {
80+ void *events = (void *)efi.tpm_final_log
81+ + sizeof(final_tbl->version)
82+ + sizeof(final_tbl->nr_events);
83+
84+ tbl_size = tpm2_calc_event_log_size(events,
85+ final_tbl->nr_events,
86+ log_tbl->log);
87+ }
88+
89+ if (tbl_size < 0) {
90+ pr_err(FW_BUG "Failed to parse event in TPM Final Events Log\n");
91+ ret = -EINVAL;
92+ goto out_calc;
93+ }
94+
8395 memblock_reserve((unsigned long)final_tbl,
8496 tbl_size + sizeof(*final_tbl));
85− early_memunmap(final_tbl, sizeof(*final_tbl));
8697 efi_tpm_final_log_size = tbl_size;
8798
99+out_calc:
100+ early_memunmap(final_tbl, sizeof(*final_tbl));
88101 out:
89102 early_memunmap(log_tbl, sizeof(*log_tbl));
90103 return ret;
drivers/firmware/google/vpd_decode.c+1−1
@@ -52,7 +52,7 @@ static int vpd_decode_entry(const u32 max_len, const u8 *input_buf, · 51 unmodified lines
5252 if (max_len - consumed < *entry_len)
5353 return VPD_FAIL;
5454
55− consumed += decoded_len;
55+ consumed += *entry_len;
5656 *_consumed = consumed;
5757 return VPD_OK;
5858 }
drivers/gpio/gpio-eic-sprd.c+4−3
@@ -530,11 +530,12 @@ static void sprd_eic_handle_one_type(struct gpio_chip *chip) · 529 unmodified lines
530530 }
531531
532532 for_each_set_bit(n, &reg, SPRD_EIC_PER_BANK_NR) {
533− girq = irq_find_mapping(chip->irq.domain,
534− bank * SPRD_EIC_PER_BANK_NR + n);
533+ u32 offset = bank * SPRD_EIC_PER_BANK_NR + n;
534+
535+ girq = irq_find_mapping(chip->irq.domain, offset);
535536
536537 generic_handle_irq(girq);
537− sprd_eic_toggle_trigger(chip, girq, n);
538+ sprd_eic_toggle_trigger(chip, girq, offset);
538539 }
539540 }
540541 }
drivers/gpio/gpio-intel-mid.c+6−3
@@ -293,8 +293,9 @@ static void intel_mid_irq_handler(struct irq_desc *desc) · 292 unmodified lines
293293 chip->irq_eoi(data);
294294 }
295295
296−static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
296+static int intel_mid_irq_init_hw(struct gpio_chip *chip)
297297 {
298+ struct intel_mid_gpio *priv = gpiochip_get_data(chip);
298299 void __iomem *reg;
299300 unsigned base;
300301
@@ -309,6 +310,8 @@ static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv) · 8 unmodified lines
309310 reg = gpio_reg(&priv->chip, base, GEDR);
310311 writel(~0, reg);
311312 }
313+
314+ return 0;
312315 }
313316
314317 static int __maybe_unused intel_gpio_runtime_idle(struct device *dev)
@@ -372,6 +375,7 @@ static int intel_gpio_probe(struct pci_dev *pdev, · 57 unmodified lines
372375
373376 girq = &priv->chip.irq;
374377 girq->chip = &intel_mid_irqchip;
378+ girq->init_hw = intel_mid_irq_init_hw;
375379 girq->parent_handler = intel_mid_irq_handler;
376380 girq->num_parents = 1;
377381 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
@@ -384,9 +388,8 @@ static int intel_gpio_probe(struct pci_dev *pdev, · 6 unmodified lines
384388 girq->default_type = IRQ_TYPE_NONE;
385389 girq->handler = handle_simple_irq;
386390
387− intel_mid_irq_init_hw(priv);
388−
389391 pci_set_drvdata(pdev, priv);
392+
390393 retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
391394 if (retval) {
392395 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
drivers/gpio/gpio-lynxpoint.c+6−4
@@ -294,8 +294,9 @@ static struct irq_chip lp_irqchip = { · 293 unmodified lines
294294 .flags = IRQCHIP_SKIP_SET_WAKE,
295295 };
296296
297−static void lp_gpio_irq_init_hw(struct lp_gpio *lg)
297+static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
298298 {
299+ struct lp_gpio *lg = gpiochip_get_data(chip);
299300 unsigned long reg;
300301 unsigned base;
301302
@@ -307,6 +308,8 @@ static void lp_gpio_irq_init_hw(struct lp_gpio *lg) · 5 unmodified lines
307308 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
308309 outl(0xffffffff, reg);
309310 }
311+
312+ return 0;
310313 }
311314
312315 static int lp_gpio_probe(struct platform_device *pdev)
@@ -364,6 +367,7 @@ static int lp_gpio_probe(struct platform_device *pdev) · 51 unmodified lines
364367
365368 girq = &gc->irq;
366369 girq->chip = &lp_irqchip;
370+ girq->init_hw = lp_gpio_irq_init_hw;
367371 girq->parent_handler = lp_gpio_irq_handler;
368372 girq->num_parents = 1;
369373 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
@@ -373,9 +377,7 @@ static int lp_gpio_probe(struct platform_device *pdev) · 3 unmodified lines
373377 return -ENOMEM;
374378 girq->parents[0] = (unsigned)irq_rc->start;
375379 girq->default_type = IRQ_TYPE_NONE;
376− girq->handler = handle_simple_irq;
377−
378− lp_gpio_irq_init_hw(lg);
380+ girq->handler = handle_bad_irq;
379381 }
380382
381383 ret = devm_gpiochip_add_data(dev, gc, lg);
drivers/gpio/gpio-max77620.c+3−3
@@ -192,13 +192,13 @@ static int max77620_gpio_set_debounce(struct max77620_gpio *mgpio, · 191 unmodified lines
192192 case 0:
193193 val = MAX77620_CNFG_GPIO_DBNC_None;
194194 break;
195− case 1 ... 8:
195+ case 1000 ... 8000:
196196 val = MAX77620_CNFG_GPIO_DBNC_8ms;
197197 break;
198− case 9 ... 16:
198+ case 9000 ... 16000:
199199 val = MAX77620_CNFG_GPIO_DBNC_16ms;
200200 break;
201− case 17 ... 32:
201+ case 17000 ... 32000:
202202 val = MAX77620_CNFG_GPIO_DBNC_32ms;
203203 break;
204204 default:
drivers/gpio/gpio-merrifield.c+12−16
@@ -397,7 +397,6 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id · 396 unmodified lines
397397 {
398398 const struct mrfld_gpio_pinrange *range;
399399 const char *pinctrl_dev_name;
400− struct gpio_irq_chip *girq;
401400 struct mrfld_gpio *priv;
402401 u32 gpio_base, irq_base;
403402 void __iomem *base;
@@ -445,21 +444,6 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id · 41 unmodified lines
445444
446445 raw_spin_lock_init(&priv->lock);
447446
448− girq = &priv->chip.irq;
449− girq->chip = &mrfld_irqchip;
450− girq->parent_handler = mrfld_irq_handler;
451− girq->num_parents = 1;
452− girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
453− sizeof(*girq->parents),
454− GFP_KERNEL);
455− if (!girq->parents)
456− return -ENOMEM;
457− girq->parents[0] = pdev->irq;
458− girq->default_type = IRQ_TYPE_NONE;
459− girq->handler = handle_bad_irq;
460−
461− mrfld_irq_init_hw(priv);
462−
463447 pci_set_drvdata(pdev, priv);
464448 retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
465449 if (retval) {
@@ -481,6 +465,18 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id · 15 unmodified lines
481465 }
482466 }
483467
468+ retval = gpiochip_irqchip_add(&priv->chip, &mrfld_irqchip, irq_base,
469+ handle_bad_irq, IRQ_TYPE_NONE);
470+ if (retval) {
471+ dev_err(&pdev->dev, "could not connect irqchip to gpiochip\n");
472+ return retval;
473+ }
474+
475+ mrfld_irq_init_hw(priv);
476+
477+ gpiochip_set_chained_irqchip(&priv->chip, &mrfld_irqchip, pdev->irq,
478+ mrfld_irq_handler);
479+
484480 return 0;
485481 }
486482
drivers/gpio/gpiolib-of.c+1−1
@@ -317,7 +317,7 @@ struct gpio_desc *gpiod_get_from_of_node(struct device_node *node, · 316 unmodified lines
317317 transitory = flags & OF_GPIO_TRANSITORY;
318318
319319 ret = gpiod_request(desc, label);
320− if (ret == -EBUSY && (flags & GPIOD_FLAGS_BIT_NONEXCLUSIVE))
320+ if (ret == -EBUSY && (dflags & GPIOD_FLAGS_BIT_NONEXCLUSIVE))
321321 return desc;
322322 if (ret)
323323 return ERR_PTR(ret);
drivers/gpio/gpiolib.c+40−9
@@ -86,6 +86,7 @@ static int gpiochip_add_irqchip(struct gpio_chip *gpiochip, · 85 unmodified lines
8686 struct lock_class_key *lock_key,
8787 struct lock_class_key *request_key);
8888 static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip);
89+static int gpiochip_irqchip_init_hw(struct gpio_chip *gpiochip);
8990 static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip);
9091 static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip);
9192
@@ -1406,6 +1407,10 @@ int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data, · 1314 unmodified lines
14061407
14071408 machine_gpiochip_add(chip);
14081409
1410+ ret = gpiochip_irqchip_init_hw(chip);
1411+ if (ret)
1412+ goto err_remove_acpi_chip;
1413+
14091414 ret = gpiochip_irqchip_init_valid_mask(chip);
14101415 if (ret)
14111416 goto err_remove_acpi_chip;
@@ -1622,6 +1627,16 @@ static struct gpio_chip *find_chip_by_name(const char *name) · 210 unmodified lines
16221627 * The following is irqchip helper code for gpiochips.
16231628 */
16241629
1630+static int gpiochip_irqchip_init_hw(struct gpio_chip *gc)
1631+{
1632+ struct gpio_irq_chip *girq = &gc->irq;
1633+
1634+ if (!girq->init_hw)
1635+ return 0;
1636+
1637+ return girq->init_hw(gc);
1638+}
1639+
16251640 static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gc)
16261641 {
16271642 struct gpio_irq_chip *girq = &gc->irq;
@@ -2446,8 +2461,13 @@ static inline int gpiochip_add_irqchip(struct gpio_chip *gpiochip, · 818 unmodified lines
24462461 {
24472462 return 0;
24482463 }
2449−
24502464 static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip) {}
2465+
2466+static inline int gpiochip_irqchip_init_hw(struct gpio_chip *gpiochip)
2467+{
2468+ return 0;
2469+}
2470+
24512471 static inline int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip)
24522472 {
24532473 return 0;
@@ -3070,8 +3090,10 @@ int gpiod_direction_output(struct gpio_desc *desc, int value) · 616 unmodified lines
30703090 if (!ret)
30713091 goto set_output_value;
30723092 /* Emulate open drain by not actively driving the line high */
3073− if (value)
3074− return gpiod_direction_input(desc);
3093+ if (value) {
3094+ ret = gpiod_direction_input(desc);
3095+ goto set_output_flag;
3096+ }
30753097 }
30763098 else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags)) {
30773099 ret = gpio_set_config(gc, gpio_chip_hwgpio(desc),
@@ -3079,8 +3101,10 @@ int gpiod_direction_output(struct gpio_desc *desc, int value) · 1 unmodified line
30793101 if (!ret)
30803102 goto set_output_value;
30813103 /* Emulate open source by not actively driving the line low */
3082− if (!value)
3083− return gpiod_direction_input(desc);
3104+ if (!value) {
3105+ ret = gpiod_direction_input(desc);
3106+ goto set_output_flag;
3107+ }
30843108 } else {
30853109 gpio_set_config(gc, gpio_chip_hwgpio(desc),
30863110 PIN_CONFIG_DRIVE_PUSH_PULL);
@@ -3088,6 +3112,17 @@ int gpiod_direction_output(struct gpio_desc *desc, int value) · 1 unmodified line
30883112
30893113 set_output_value:
30903114 return gpiod_direction_output_raw_commit(desc, value);
3115+
3116+set_output_flag:
3117+ /*
3118+ * When emulating open-source or open-drain functionalities by not
3119+ * actively driving the line (setting mode to input) we still need to
3120+ * set the IS_OUT flag or otherwise we won't be able to set the line
3121+ * value anymore.
3122+ */
3123+ if (ret == 0)
3124+ set_bit(FLAG_IS_OUT, &desc->flags);
3125+ return ret;
30913126 }
30923127 EXPORT_SYMBOL_GPL(gpiod_direction_output);
30933128
@@ -3448,8 +3483,6 @@ static void gpio_set_open_drain_value_commit(struct gpio_desc *desc, bool value) · 354 unmodified lines
34483483
34493484 if (value) {
34503485 ret = chip->direction_input(chip, offset);
3451− if (!ret)
3452− clear_bit(FLAG_IS_OUT, &desc->flags);
34533486 } else {
34543487 ret = chip->direction_output(chip, offset, 0);
34553488 if (!ret)
@@ -3479,8 +3512,6 @@ static void gpio_set_open_source_value_commit(struct gpio_desc *desc, bool value · 23 unmodified lines
34793512 set_bit(FLAG_IS_OUT, &desc->flags);
34803513 } else {
34813514 ret = chip->direction_input(chip, offset);
3482− if (!ret)
3483− clear_bit(FLAG_IS_OUT, &desc->flags);
34843515 }
34853516 trace_gpio_direction(desc_to_gpio(desc), !value, ret);
34863517 if (ret < 0)
drivers/gpu/drm/Kconfig+25−3
@@ -97,6 +97,20 @@ config DRM_KMS_FB_HELPER · 96 unmodified lines
9797 help
9898 FBDEV helpers for KMS drivers.
9999
100+config DRM_DEBUG_DP_MST_TOPOLOGY_REFS
101+ bool "Enable refcount backtrace history in the DP MST helpers"
102+ select STACKDEPOT
103+ depends on DRM_KMS_HELPER
104+ depends on DEBUG_KERNEL
105+ depends on EXPERT
106+ help
107+ Enables debug tracing for topology refs in DRM's DP MST helpers. A
108+ history of each topology reference/dereference will be printed to the
109+ kernel log once a port or branch device's topology refcount reaches 0.
110+
111+ This has the potential to use a lot of memory and print some very
112+ large kernel messages. If in doubt, say "N".
113+
100114 config DRM_FBDEV_EMULATION
101115 bool "Enable legacy fbdev support for your modesetting driver"
102116 depends on DRM
@@ -169,6 +183,13 @@ config DRM_TTM · 66 unmodified lines
169183 GPU memory types. Will be enabled automatically if a device driver
170184 uses it.
171185
186+config DRM_TTM_DMA_PAGE_POOL
187+ bool
188+ depends on DRM_TTM && (SWIOTLB || INTEL_IOMMU)
189+ default y
190+ help
191+ Choose this if you need the TTM dma page pool
192+
172193 config DRM_VRAM_HELPER
173194 tristate
174195 depends on DRM
@@ -236,9 +257,9 @@ config DRM_AMDGPU · 61 unmodified lines
236257 tristate "AMD GPU"
237258 depends on DRM && PCI && MMU
238259 select FW_LOADER
239− select DRM_KMS_HELPER
260+ select DRM_KMS_HELPER
240261 select DRM_SCHED
241− select DRM_TTM
262+ select DRM_TTM
242263 select POWER_SUPPLY
243264 select HWMON
244265 select BACKLIGHT_CLASS_DEVICE
@@ -267,6 +288,7 @@ config DRM_VKMS · 22 unmodified lines
267288 tristate "Virtual KMS (EXPERIMENTAL)"
268289 depends on DRM
269290 select DRM_KMS_HELPER
291+ select CRC32
270292 default n
271293 help
272294 Virtual Kernel Mode-Setting (VKMS) is used for testing or for
@@ -407,7 +429,7 @@ config DRM_R128 · 134 unmodified lines
407429
408430 config DRM_I810
409431 tristate "Intel I810"
410− # !PREEMPT because of missing ioctl locking
432+ # !PREEMPTION because of missing ioctl locking
411433 depends on DRM && AGP && AGP_INTEL && (!PREEMPTION || BROKEN)
412434 help
413435 Choose this option if you have an Intel I810 graphics card. If M is
drivers/gpu/drm/amd/amdgpu/Makefile+5−4
@@ -53,8 +53,9 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ · 52 unmodified lines
5353 amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
5454 amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
5555 amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
56− amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
57− amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o smu_v11_0_i2c.o
56+ amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
57+ amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
58+ amdgpu_umc.o smu_v11_0_i2c.o
5859
5960 amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
6061
@@ -67,7 +68,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce · 6 unmodified lines
6768 amdgpu-y += \
6869 vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
6970 vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
70− arct_reg_init.o navi12_reg_init.o
71+ arct_reg_init.o navi12_reg_init.o mxgpu_nv.o
7172
7273 # add DF block
7374 amdgpu-y += \
@@ -83,7 +84,7 @@ amdgpu-y += \ · 9 unmodified lines
8384
8485 # add UMC block
8586 amdgpu-y += \
86− umc_v6_1.o
87+ umc_v6_1.o umc_v6_0.o
8788
8889 # add IH block
8990 amdgpu-y += \
drivers/gpu/drm/amd/amdgpu/amdgpu.h+33−69
@@ -73,6 +73,7 @@ · 72 unmodified lines
7373 #include "amdgpu_gmc.h"
7474 #include "amdgpu_gfx.h"
7575 #include "amdgpu_sdma.h"
76+#include "amdgpu_nbio.h"
7677 #include "amdgpu_dm.h"
7778 #include "amdgpu_virt.h"
7879 #include "amdgpu_csa.h"
@@ -106,6 +107,8 @@ struct amdgpu_mgpu_info · 27 unmodified lines
106107 uint32_t num_apu;
107108 };
108109
110+#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
111+
109112 /*
110113 * Modules parameters.
111114 */
@@ -122,6 +125,7 @@ extern int amdgpu_disp_priority; · 10 unmodified lines
122125 extern int amdgpu_hw_i2c;
123126 extern int amdgpu_pcie_gen2;
124127 extern int amdgpu_msi;
128+extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
125129 extern int amdgpu_dpm;
126130 extern int amdgpu_fw_load_type;
127131 extern int amdgpu_aspm;
@@ -135,6 +139,7 @@ extern int amdgpu_vm_fragment_size; · 7 unmodified lines
135139 extern int amdgpu_vm_fault_stop;
136140 extern int amdgpu_vm_debug;
137141 extern int amdgpu_vm_update_mode;
142+extern int amdgpu_exp_hw_support;
138143 extern int amdgpu_dc;
139144 extern int amdgpu_sched_jobs;
140145 extern int amdgpu_sched_hw_submission;
@@ -146,11 +151,7 @@ extern uint amdgpu_sdma_phase_quantum; · 5 unmodified lines
146151 extern char *amdgpu_disable_cu;
147152 extern char *amdgpu_virtual_display;
148153 extern uint amdgpu_pp_feature_mask;
149−extern int amdgpu_ngg;
150−extern int amdgpu_prim_buf_per_se;
151−extern int amdgpu_pos_buf_per_se;
152−extern int amdgpu_cntl_sb_buf_per_se;
153−extern int amdgpu_param_buf_per_se;
154+extern uint amdgpu_force_long_training;
154155 extern int amdgpu_job_hang_limit;
155156 extern int amdgpu_lbpw;
156157 extern int amdgpu_compute_multipipe;
@@ -167,6 +168,12 @@ extern int amdgpu_mcbp; · 10 unmodified lines
167168 extern int amdgpu_discovery;
168169 extern int amdgpu_mes;
169170 extern int amdgpu_noretry;
171+extern int amdgpu_force_asic_type;
172+#ifdef CONFIG_HSA_AMD
173+extern int sched_policy;
174+#else
175+static const int sched_policy = KFD_SCHED_POLICY_HWS;
176+#endif
170177
171178 #ifdef CONFIG_DRM_AMDGPU_SI
172179 extern int amdgpu_si_support;
@@ -283,6 +290,9 @@ struct amdgpu_ip_block_version { · 110 unmodified lines
283290 const struct amd_ip_funcs *funcs;
284291 };
285292
293+#define HW_REV(_Major, _Minor, _Rev) \
294+ ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
295+
286296 struct amdgpu_ip_block {
287297 struct amdgpu_ip_block_status status;
288298 const struct amdgpu_ip_block_version *version;
@@ -425,7 +435,6 @@ struct amdgpu_fpriv { · 136 unmodified lines
425435 };
426436
427437 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
428−int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev);
429438
430439 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
431440 unsigned size, struct amdgpu_ib *ib);
@@ -477,7 +486,6 @@ struct amdgpu_cs_parser { · 45 unmodified lines
477486 uint64_t bytes_moved_vis_threshold;
478487 uint64_t bytes_moved;
479488 uint64_t bytes_moved_vis;
480− struct amdgpu_bo_list_entry *evictable;
481489
482490 /* user fence */
483491 struct amdgpu_bo_list_entry uf_entry;
@@ -624,6 +632,11 @@ struct amdgpu_fw_vram_usage { · 140 unmodified lines
624632 u64 size;
625633 struct amdgpu_bo *reserved_bo;
626634 void *va;
635+
636+ /* Offset on the top of VRAM, used as c2p write buffer.
637+ */
638+ u64 mem_train_fb_loc;
639+ bool mem_train_support;
627640 };
628641
629642 /*
@@ -644,71 +657,14 @@ typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); · 14 unmodified lines
644657 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
645658 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
646659
647−
648−/*
649− * amdgpu nbio functions
650− *
651− */
652−struct nbio_hdp_flush_reg {
653− u32 ref_and_mask_cp0;
654− u32 ref_and_mask_cp1;
655− u32 ref_and_mask_cp2;
656− u32 ref_and_mask_cp3;
657− u32 ref_and_mask_cp4;
658− u32 ref_and_mask_cp5;
659− u32 ref_and_mask_cp6;
660− u32 ref_and_mask_cp7;
661− u32 ref_and_mask_cp8;
662− u32 ref_and_mask_cp9;
663− u32 ref_and_mask_sdma0;
664− u32 ref_and_mask_sdma1;
665− u32 ref_and_mask_sdma2;
666− u32 ref_and_mask_sdma3;
667− u32 ref_and_mask_sdma4;
668− u32 ref_and_mask_sdma5;
669− u32 ref_and_mask_sdma6;
670− u32 ref_and_mask_sdma7;
671−};
672−
673660 struct amdgpu_mmio_remap {
674661 u32 reg_offset;
675662 resource_size_t bus_addr;
676663 };
677664
678−struct amdgpu_nbio_funcs {
679− const struct nbio_hdp_flush_reg *hdp_flush_reg;
680− u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
681− u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
682− u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
683− u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
684− u32 (*get_rev_id)(struct amdgpu_device *adev);
685− void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
686− void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
687− u32 (*get_memsize)(struct amdgpu_device *adev);
688− void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
689− bool use_doorbell, int doorbell_index, int doorbell_size);
690− void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
691− int doorbell_index, int instance);
692− void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
693− bool enable);
694− void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
695− bool enable);
696− void (*ih_doorbell_range)(struct amdgpu_device *adev,
697− bool use_doorbell, int doorbell_index);
698− void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
699− bool enable);
700− void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
701− bool enable);
702− void (*get_clockgating_state)(struct amdgpu_device *adev,
703− u32 *flags);
704− void (*ih_control)(struct amdgpu_device *adev);
705− void (*init_registers)(struct amdgpu_device *adev);
706− void (*detect_hw_virt)(struct amdgpu_device *adev);
707− void (*remap_hdp_registers)(struct amdgpu_device *adev);
708−};
709−
710665 struct amdgpu_df_funcs {
711666 void (*sw_init)(struct amdgpu_device *adev);
667+ void (*sw_fini)(struct amdgpu_device *adev);
712668 void (*enable_broadcast_mode)(struct amdgpu_device *adev,
713669 bool enable);
714670 u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
@@ -813,6 +769,7 @@ struct amdgpu_device { · 98 unmodified lines
813769 uint8_t *bios;
814770 uint32_t bios_size;
815771 struct amdgpu_bo *stolen_vga_memory;
772+ struct amdgpu_bo *discovery_memory;
816773 uint32_t bios_scratch_reg_offset;
817774 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
818775
@@ -921,6 +878,12 @@ struct amdgpu_device { · 102 unmodified lines
921878 u32 cg_flags;
922879 u32 pg_flags;
923880
881+ /* nbio */
882+ struct amdgpu_nbio nbio;
883+
884+ /* mmhub */
885+ struct amdgpu_mmhub mmhub;
886+
924887 /* gfx */
925888 struct amdgpu_gfx gfx;
926889
@@ -974,9 +937,7 @@ struct amdgpu_device { · 47 unmodified lines
974937 /* soc15 register offset based on ip, instance and segment */
975938 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
976939
977− const struct amdgpu_nbio_funcs *nbio_funcs;
978940 const struct amdgpu_df_funcs *df_funcs;
979− const struct amdgpu_mmhub_funcs *mmhub_funcs;
980941
981942 /* delayed work_func for deferring clockgating during resume */
982943 struct delayed_work delayed_init_work;
@@ -1009,8 +970,6 @@ struct amdgpu_device { · 26 unmodified lines
1009970 int asic_reset_res;
1010971 struct work_struct xgmi_reset_work;
1011972
1012− bool in_baco_reset;
1013−
1014973 long gfx_timeout;
1015974 long sdma_timeout;
1016975 long video_timeout;
@@ -1018,6 +977,9 @@ struct amdgpu_device { · 1 unmodified line
1018977
1019978 uint64_t unique_id;
1020979 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
980+
981+ /* device pstate */
982+ int pstate;
1021983 };
1022984
1023985 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
@@ -1032,6 +994,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 8 unmodified lines
1032994 void amdgpu_device_fini(struct amdgpu_device *adev);
1033995 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1034996
997+void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
998+ uint32_t *buf, size_t size, bool write);
1035999 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
10361000 uint32_t acc_flags);
10371001 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c+5−72
@@ -63,45 +63,10 @@ void amdgpu_amdkfd_fini(void) · 62 unmodified lines
6363
6464 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
6565 {
66− const struct kfd2kgd_calls *kfd2kgd;
67−
68− switch (adev->asic_type) {
69−#ifdef CONFIG_DRM_AMDGPU_CIK
70− case CHIP_KAVERI:
71− case CHIP_HAWAII:
72− kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
73− break;
74−#endif
75− case CHIP_CARRIZO:
76− case CHIP_TONGA:
77− case CHIP_FIJI:
78− case CHIP_POLARIS10:
79− case CHIP_POLARIS11:
80− case CHIP_POLARIS12:
81− case CHIP_VEGAM:
82− kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
83− break;
84− case CHIP_VEGA10:
85− case CHIP_VEGA12:
86− case CHIP_VEGA20:
87− case CHIP_RAVEN:
88− kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
89− break;
90− case CHIP_ARCTURUS:
91− kfd2kgd = amdgpu_amdkfd_arcturus_get_functions();
92− break;
93− case CHIP_NAVI10:
94− case CHIP_NAVI14:
95− case CHIP_NAVI12:
96− kfd2kgd = amdgpu_amdkfd_gfx_10_0_get_functions();
97− break;
98− default:
99− dev_info(adev->dev, "kfd not supported on this ASIC\n");
100− return;
101− }
66+ bool vf = amdgpu_sriov_vf(adev);
10267
10368 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
104− adev->pdev, kfd2kgd);
69+ adev->pdev, adev->asic_type, vf);
10570
10671 if (adev->kfd.dev)
10772 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
@@ -165,14 +130,6 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) · 57 unmodified lines
165130 adev->gfx.mec.queue_bitmap,
166131 KGD_MAX_QUEUES);
167132
168− /* remove the KIQ bit as well */
169− if (adev->gfx.kiq.ring.sched.ready)
170− clear_bit(amdgpu_gfx_mec_queue_to_bit(adev,
171− adev->gfx.kiq.ring.me - 1,
172− adev->gfx.kiq.ring.pipe,
173− adev->gfx.kiq.ring.queue),
174− gpu_resources.queue_bitmap);
175−
176133 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
177134 * nbits is not compile time constant
178135 */
@@ -202,7 +159,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) · 23 unmodified lines
202159 adev->doorbell_index.last_non_cp;
203160 }
204161
205− kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
162+ kgd2kfd_device_init(adev->kfd.dev, adev->ddev, &gpu_resources);
206163 }
207164 }
208165
@@ -709,38 +666,14 @@ int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) · 500 unmodified lines
709666 return 0;
710667 }
711668
712−struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
713−{
714− return NULL;
715−}
716−
717−struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
718−{
719− return NULL;
720−}
721−
722−struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
723−{
724− return NULL;
725−}
726−
727−struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void)
728−{
729− return NULL;
730−}
731−
732−struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void)
733−{
734− return NULL;
735−}
736−
737669 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
738− const struct kfd2kgd_calls *f2g)
670+ unsigned int asic_type, bool vf)
739671 {
740672 return NULL;
741673 }
742674
743675 bool kgd2kfd_device_init(struct kfd_dev *kfd,
676+ struct drm_device *ddev,
744677 const struct kgd2kfd_shared_resources *gpu_resources)
745678 {
746679 return false;
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h+11−8
@@ -57,7 +57,7 @@ struct kgd_mem { · 56 unmodified lines
5757 unsigned int mapped_to_gpu_memory;
5858 uint64_t va;
5959
60− uint32_t mapping_flags;
60+ uint32_t alloc_flags;
6161
6262 atomic_t invalid;
6363 struct amdkfd_process_info *process_info;
@@ -137,12 +137,6 @@ int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, · 73 unmodified lines
137137 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle);
138138 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd);
139139
140−struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void);
141−struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void);
142−struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void);
143−struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void);
144−struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void);
145−
146140 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
147141
148142 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);
@@ -179,10 +173,17 @@ uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd); · 30 unmodified lines
179173 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd);
180174 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src);
181175
176+/* Read user wptr from a specified user address space with page fault
177+ * disabled. The memory must be pinned and mapped to the hardware when
178+ * this is called in hqd_load functions, so it should never fault in
179+ * the first place. This resolves a circular lock dependency involving
180+ * four locks, including the DQM lock and mmap_sem.
181+ */
182182 #define read_user_wptr(mmptr, wptr, dst) \
183183 ({ \
184184 bool valid = false; \
185185 if ((mmptr) && (wptr)) { \
186+ pagefault_disable(); \
186187 if ((mmptr) == current->mm) { \
187188 valid = !get_user((dst), (wptr)); \
188189 } else if (current->mm == NULL) { \
@@ -190,6 +191,7 @@ uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *s · 1 unmodified line
190191 valid = !get_user((dst), (wptr)); \
191192 unuse_mm(mmptr); \
192193 } \
194+ pagefault_enable(); \
193195 } \
194196 valid; \
195197 })
@@ -240,8 +242,9 @@ void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo); · 44 unmodified lines
240242 int kgd2kfd_init(void);
241243 void kgd2kfd_exit(void);
242244 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
243− const struct kfd2kgd_calls *f2g);
245+ unsigned int asic_type, bool vf);
244246 bool kgd2kfd_device_init(struct kfd_dev *kfd,
247+ struct drm_device *ddev,
245248 const struct kgd2kfd_shared_resources *gpu_resources);
246249 void kgd2kfd_device_exit(struct kfd_dev *kfd);
247250 void kgd2kfd_suspend(struct kfd_dev *kfd);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c+54−93
@@ -19,10 +19,6 @@ · 18 unmodified lines
1919 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2020 * OTHER DEALINGS IN THE SOFTWARE.
2121 */
22−
23−#undef pr_fmt
24−#define pr_fmt(fmt) "kfd2kgd: " fmt
25−
2622 #include <linux/module.h>
2723 #include <linux/fdtable.h>
2824 #include <linux/uaccess.h>
@@ -69,11 +65,11 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) · 40 unmodified lines
6965 return (struct v9_sdma_mqd *)mqd;
7066 }
7167
72−static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
68+static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
7369 unsigned int engine_id,
7470 unsigned int queue_id)
7571 {
76− uint32_t base[8] = {
72+ uint32_t sdma_engine_reg_base[8] = {
7773 SOC15_REG_OFFSET(SDMA0, 0,
7874 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
7975 SOC15_REG_OFFSET(SDMA1, 0,
@@ -91,111 +87,82 @@ static uint32_t get_sdma_base_addr(struct amdgpu_device *adev, · 11 unmodified lines
9187 SOC15_REG_OFFSET(SDMA7, 0,
9288 mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
9389 };
94− uint32_t retval;
9590
96− retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
97− mmSDMA0_RLC0_RB_CNTL);
91+ uint32_t retval = sdma_engine_reg_base[engine_id]
92+ + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
9893
99− pr_debug("sdma base address: 0x%x\n", retval);
94+ pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
95+ queue_id, retval);
10096
10197 return retval;
10298 }
10399
104−static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
105− u32 instance, u32 offset)
106−{
107− switch (instance) {
108− case 0:
109− return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
110− case 1:
111− return (adev->reg_offset[SDMA1_HWIP][0][1] + offset);
112− case 2:
113− return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
114− case 3:
115− return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
116− case 4:
117− return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
118− case 5:
119− return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
120− case 6:
121− return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
122− case 7:
123− return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
124− default:
125− break;
126− }
127− return 0;
128−}
129−
130100 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
131101 uint32_t __user *wptr, struct mm_struct *mm)
132102 {
133103 struct amdgpu_device *adev = get_amdgpu_device(kgd);
134104 struct v9_sdma_mqd *m;
135− uint32_t sdma_base_addr, sdmax_gfx_context_cntl;
105+ uint32_t sdma_rlc_reg_offset;
136106 unsigned long end_jiffies;
137107 uint32_t data;
138108 uint64_t data64;
139109 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
140110
141111 m = get_sdma_mqd(mqd);
142− sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
112+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
143113 m->sdma_queue_id);
144− sdmax_gfx_context_cntl = sdma_v4_0_get_reg_offset(adev,
145− m->sdma_engine_id, mmSDMA0_GFX_CONTEXT_CNTL);
146114
147− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
115+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
148116 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
149117
150118 end_jiffies = msecs_to_jiffies(2000) + jiffies;
151119 while (true) {
152− data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
120+ data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
153121 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
154122 break;
155− if (time_after(jiffies, end_jiffies))
123+ if (time_after(jiffies, end_jiffies)) {
124+ pr_err("SDMA RLC not idle in %s\n", __func__);
156125 return -ETIME;
126+ }
157127 usleep_range(500, 1000);
158128 }
159− data = RREG32(sdmax_gfx_context_cntl);
160− data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
161− RESUME_CTX, 0);
162− WREG32(sdmax_gfx_context_cntl, data);
163129
164− WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
130+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
165131 m->sdmax_rlcx_doorbell_offset);
166132
167133 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
168134 ENABLE, 1);
169− WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
170− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
171− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
135+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
136+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
137+ m->sdmax_rlcx_rb_rptr);
138+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
172139 m->sdmax_rlcx_rb_rptr_hi);
173140
174− WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
141+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
175142 if (read_user_wptr(mm, wptr64, data64)) {
176− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
143+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
177144 lower_32_bits(data64));
178− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
145+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
179146 upper_32_bits(data64));
180147 } else {
181− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
148+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
182149 m->sdmax_rlcx_rb_rptr);
183− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
150+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
184151 m->sdmax_rlcx_rb_rptr_hi);
185152 }
186− WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
153+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
187154
188− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
189− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
155+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
156+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
190157 m->sdmax_rlcx_rb_base_hi);
191− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
158+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
192159 m->sdmax_rlcx_rb_rptr_addr_lo);
193− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
160+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
194161 m->sdmax_rlcx_rb_rptr_addr_hi);
195162
196163 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
197164 RB_ENABLE, 1);
198− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
165+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
199166
200167 return 0;
201168 }
@@ -205,7 +172,8 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, · 3 unmodified lines
205172 uint32_t (**dump)[2], uint32_t *n_regs)
206173 {
207174 struct amdgpu_device *adev = get_amdgpu_device(kgd);
208− uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
175+ uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
176+ engine_id, queue_id);
209177 uint32_t i = 0, reg;
210178 #undef HQD_N_REGS
211179 #define HQD_N_REGS (19+6+7+10)
@@ -215,15 +183,15 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, · 3 unmodified lines
215183 return -ENOMEM;
216184
217185 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
218− DUMP_REG(sdma_base_addr + reg);
186+ DUMP_REG(sdma_rlc_reg_offset + reg);
219187 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
220− DUMP_REG(sdma_base_addr + reg);
188+ DUMP_REG(sdma_rlc_reg_offset + reg);
221189 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
222190 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
223− DUMP_REG(sdma_base_addr + reg);
191+ DUMP_REG(sdma_rlc_reg_offset + reg);
224192 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
225193 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
226− DUMP_REG(sdma_base_addr + reg);
194+ DUMP_REG(sdma_rlc_reg_offset + reg);
227195
228196 WARN_ON_ONCE(i != HQD_N_REGS);
229197 *n_regs = i;
@@ -235,14 +203,14 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) · 5 unmodified lines
235203 {
236204 struct amdgpu_device *adev = get_amdgpu_device(kgd);
237205 struct v9_sdma_mqd *m;
238− uint32_t sdma_base_addr;
206+ uint32_t sdma_rlc_reg_offset;
239207 uint32_t sdma_rlc_rb_cntl;
240208
241209 m = get_sdma_mqd(mqd);
242− sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
210+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
243211 m->sdma_queue_id);
244212
245− sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
213+ sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
246214
247215 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
248216 return true;
@@ -255,40 +223,42 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, · 6 unmodified lines
255223 {
256224 struct amdgpu_device *adev = get_amdgpu_device(kgd);
257225 struct v9_sdma_mqd *m;
258− uint32_t sdma_base_addr;
226+ uint32_t sdma_rlc_reg_offset;
259227 uint32_t temp;
260228 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
261229
262230 m = get_sdma_mqd(mqd);
263− sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
231+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
264232 m->sdma_queue_id);
265233
266− temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
234+ temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
267235 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
268− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
236+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
269237
270238 while (true) {
271− temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
239+ temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
272240 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
273241 break;
274− if (time_after(jiffies, end_jiffies))
242+ if (time_after(jiffies, end_jiffies)) {
243+ pr_err("SDMA RLC not idle in %s\n", __func__);
275244 return -ETIME;
245+ }
276246 usleep_range(500, 1000);
277247 }
278248
279− WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
280− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
281− RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
249+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
250+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
251+ RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
282252 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
283253
284− m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
254+ m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
285255 m->sdmax_rlcx_rb_rptr_hi =
286− RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI);
256+ RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
287257
288258 return 0;
289259 }
290260
291−static const struct kfd2kgd_calls kfd2kgd = {
261+const struct kfd2kgd_calls arcturus_kfd2kgd = {
292262 .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
293263 .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
294264 .init_interrupts = kgd_gfx_v9_init_interrupts,
@@ -304,20 +274,11 @@ static const struct kfd2kgd_calls kfd2kgd = { · 9 unmodified lines
304274 .address_watch_execute = kgd_gfx_v9_address_watch_execute,
305275 .wave_control_execute = kgd_gfx_v9_wave_control_execute,
306276 .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
307− .get_atc_vmid_pasid_mapping_pasid =
308− kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid,
309− .get_atc_vmid_pasid_mapping_valid =
310− kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid,
311− .set_scratch_backing_va = kgd_gfx_v9_set_scratch_backing_va,
277+ .get_atc_vmid_pasid_mapping_info =
278+ kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
312279 .get_tile_config = kgd_gfx_v9_get_tile_config,
313280 .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
314281 .invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
315282 .invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid,
316283 .get_hive_id = amdgpu_amdkfd_get_hive_id,
317284 };
318−
319−struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void)
320−{
321− return (struct kfd2kgd_calls *)&kfd2kgd;
322−}
323−
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c+94−195
@@ -19,18 +19,9 @@ · 18 unmodified lines
1919 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2020 * OTHER DEALINGS IN THE SOFTWARE.
2121 */
22−#undef pr_fmt
23−#define pr_fmt(fmt) "kfd2kgd: " fmt
24−
25−#include <linux/module.h>
26−#include <linux/fdtable.h>
27−#include <linux/uaccess.h>
28−#include <linux/firmware.h>
2922 #include <linux/mmu_context.h>
3023 #include "amdgpu.h"
3124 #include "amdgpu_amdkfd.h"
32−#include "amdgpu_ucode.h"
33−#include "soc15_hw_ip.h"
3425 #include "gc/gc_10_1_0_offset.h"
3526 #include "gc/gc_10_1_0_sh_mask.h"
3627 #include "navi10_enum.h"
@@ -42,6 +33,7 @@ · 5 unmodified lines
4233 #include "v10_structs.h"
4334 #include "nv.h"
4435 #include "nvd.h"
36+#include "gfxhub_v2_0.h"
4537
4638 enum hqd_dequeue_request_type {
4739 NO_ACTION = 0,
@@ -50,63 +42,6 @@ enum hqd_dequeue_request_type { · 2 unmodified lines
5042 SAVE_WAVES
5143 };
5244
53−/*
54− * Register access functions
55− */
56−
57−static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
58− uint32_t sh_mem_config,
59− uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
60− uint32_t sh_mem_bases);
61−static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
62− unsigned int vmid);
63−static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
64−static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
65− uint32_t queue_id, uint32_t __user *wptr,
66− uint32_t wptr_shift, uint32_t wptr_mask,
67− struct mm_struct *mm);
68−static int kgd_hqd_dump(struct kgd_dev *kgd,
69− uint32_t pipe_id, uint32_t queue_id,
70− uint32_t (**dump)[2], uint32_t *n_regs);
71−static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
72− uint32_t __user *wptr, struct mm_struct *mm);
73−static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
74− uint32_t engine_id, uint32_t queue_id,
75− uint32_t (**dump)[2], uint32_t *n_regs);
76−static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
77− uint32_t pipe_id, uint32_t queue_id);
78−static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
79−static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
80− enum kfd_preempt_type reset_type,
81− unsigned int utimeout, uint32_t pipe_id,
82− uint32_t queue_id);
83−static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
84− unsigned int utimeout);
85−#if 0
86−static uint32_t get_watch_base_addr(struct amdgpu_device *adev);
87−#endif
88−static int kgd_address_watch_disable(struct kgd_dev *kgd);
89−static int kgd_address_watch_execute(struct kgd_dev *kgd,
90− unsigned int watch_point_id,
91− uint32_t cntl_val,
92− uint32_t addr_hi,
93− uint32_t addr_lo);
94−static int kgd_wave_control_execute(struct kgd_dev *kgd,
95− uint32_t gfx_index_val,
96− uint32_t sq_cmd);
97−static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
98− unsigned int watch_point_id,
99− unsigned int reg_offset);
100−
101−static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
102− uint8_t vmid);
103−static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
104− uint8_t vmid);
105−static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
106− uint64_t page_table_base);
107−static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
108−static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
109−
11045 /* Because of REG_GET_FIELD() being used, we put this function in the
11146 * asic specific file.
11247 */
@@ -139,37 +74,6 @@ static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, · 26 unmodified lines
13974 return 0;
14075 }
14176
142−static const struct kfd2kgd_calls kfd2kgd = {
143− .program_sh_mem_settings = kgd_program_sh_mem_settings,
144− .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
145− .init_interrupts = kgd_init_interrupts,
146− .hqd_load = kgd_hqd_load,
147− .hqd_sdma_load = kgd_hqd_sdma_load,
148− .hqd_dump = kgd_hqd_dump,
149− .hqd_sdma_dump = kgd_hqd_sdma_dump,
150− .hqd_is_occupied = kgd_hqd_is_occupied,
151− .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
152− .hqd_destroy = kgd_hqd_destroy,
153− .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
154− .address_watch_disable = kgd_address_watch_disable,
155− .address_watch_execute = kgd_address_watch_execute,
156− .wave_control_execute = kgd_wave_control_execute,
157− .address_watch_get_offset = kgd_address_watch_get_offset,
158− .get_atc_vmid_pasid_mapping_pasid =
159− get_atc_vmid_pasid_mapping_pasid,
160− .get_atc_vmid_pasid_mapping_valid =
161− get_atc_vmid_pasid_mapping_valid,
162− .invalidate_tlbs = invalidate_tlbs,
163− .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
164− .set_vm_context_page_table_base = set_vm_context_page_table_base,
165− .get_tile_config = amdgpu_amdkfd_get_tile_config,
166−};
167−
168−struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions()
169−{
170− return (struct kfd2kgd_calls *)&kfd2kgd;
171−}
172−
17377 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
17478 {
17579 return (struct amdgpu_device *)kgd;
@@ -250,11 +154,6 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, · 74 unmodified lines
250154 ATC_VMID0_PASID_MAPPING__VALID_MASK;
251155
252156 pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping);
253− /*
254− * need to do this twice, once for gfx and once for mmhub
255− * for ATC add 16 to VMID for mmhub, for IH different registers.
256− * ATC_VMID0..15 registers are separate from ATC_VMID16..31.
257− */
258157
259158 pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid);
260159 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
@@ -306,11 +205,11 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) · 45 unmodified lines
306205 return 0;
307206 }
308207
309−static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
208+static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
310209 unsigned int engine_id,
311210 unsigned int queue_id)
312211 {
313− uint32_t base[2] = {
212+ uint32_t sdma_engine_reg_base[2] = {
314213 SOC15_REG_OFFSET(SDMA0, 0,
315214 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
316215 /* On gfx10, mmSDMA1_xxx registers are defined NOT based
@@ -322,12 +221,12 @@ static uint32_t get_sdma_base_addr(struct amdgpu_device *adev, · 5 unmodified lines
322221 SOC15_REG_OFFSET(SDMA1, 0,
323222 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL
324223 };
325− uint32_t retval;
326224
327− retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
328− mmSDMA0_RLC0_RB_CNTL);
225+ uint32_t retval = sdma_engine_reg_base[engine_id]
226+ + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
329227
330− pr_debug("sdma base address: 0x%x\n", retval);
228+ pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
229+ queue_id, retval);
331230
332231 return retval;
333232 }
@@ -488,72 +387,67 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, · 154 unmodified lines
488387 {
489388 struct amdgpu_device *adev = get_amdgpu_device(kgd);
490389 struct v10_sdma_mqd *m;
491− uint32_t sdma_base_addr, sdmax_gfx_context_cntl;
390+ uint32_t sdma_rlc_reg_offset;
492391 unsigned long end_jiffies;
493392 uint32_t data;
494393 uint64_t data64;
495394 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
496395
497396 m = get_sdma_mqd(mqd);
498− sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
397+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
499398 m->sdma_queue_id);
500− pr_debug("sdma load base addr %x for engine %d, queue %d\n", sdma_base_addr, m->sdma_engine_id, m->sdma_queue_id);
501− sdmax_gfx_context_cntl = m->sdma_engine_id ?
502− SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) :
503− SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL);
504399
505− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
400+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
506401 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
507402
508403 end_jiffies = msecs_to_jiffies(2000) + jiffies;
509404 while (true) {
510− data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
405+ data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
511406 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
512407 break;
513− if (time_after(jiffies, end_jiffies))
408+ if (time_after(jiffies, end_jiffies)) {
409+ pr_err("SDMA RLC not idle in %s\n", __func__);
514410 return -ETIME;
411+ }
515412 usleep_range(500, 1000);
516413 }
517− data = RREG32(sdmax_gfx_context_cntl);
518− data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
519− RESUME_CTX, 0);
520− WREG32(sdmax_gfx_context_cntl, data);
521414
522− WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
415+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
523416 m->sdmax_rlcx_doorbell_offset);
524417
525418 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
526419 ENABLE, 1);
527− WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
528− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
529− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
420+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
421+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
422+ m->sdmax_rlcx_rb_rptr);
423+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
530424 m->sdmax_rlcx_rb_rptr_hi);
531425
532− WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
426+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
533427 if (read_user_wptr(mm, wptr64, data64)) {
534− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
428+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
535429 lower_32_bits(data64));
536− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
430+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
537431 upper_32_bits(data64));
538432 } else {
539− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
433+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
540434 m->sdmax_rlcx_rb_rptr);
541− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
435+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
542436 m->sdmax_rlcx_rb_rptr_hi);
543437 }
544− WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
438+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
545439
546− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
547− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
440+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
441+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
548442 m->sdmax_rlcx_rb_base_hi);
549− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
443+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
550444 m->sdmax_rlcx_rb_rptr_addr_lo);
551− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
445+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
552446 m->sdmax_rlcx_rb_rptr_addr_hi);
553447
554448 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
555449 RB_ENABLE, 1);
556− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
450+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
557451
558452 return 0;
559453 }
@@ -563,28 +457,26 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, · 3 unmodified lines
563457 uint32_t (**dump)[2], uint32_t *n_regs)
564458 {
565459 struct amdgpu_device *adev = get_amdgpu_device(kgd);
566− uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
460+ uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
461+ engine_id, queue_id);
567462 uint32_t i = 0, reg;
568463 #undef HQD_N_REGS
569464 #define HQD_N_REGS (19+6+7+10)
570465
571− pr_debug("sdma dump engine id %d queue_id %d\n", engine_id, queue_id);
572− pr_debug("sdma base addr %x\n", sdma_base_addr);
573−
574466 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
575467 if (*dump == NULL)
576468 return -ENOMEM;
577469
578470 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
579− DUMP_REG(sdma_base_addr + reg);
471+ DUMP_REG(sdma_rlc_reg_offset + reg);
580472 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
581− DUMP_REG(sdma_base_addr + reg);
473+ DUMP_REG(sdma_rlc_reg_offset + reg);
582474 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
583475 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
584− DUMP_REG(sdma_base_addr + reg);
476+ DUMP_REG(sdma_rlc_reg_offset + reg);
585477 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
586478 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
587− DUMP_REG(sdma_base_addr + reg);
479+ DUMP_REG(sdma_rlc_reg_offset + reg);
588480
589481 WARN_ON_ONCE(i != HQD_N_REGS);
590482 *n_regs = i;
@@ -618,14 +510,14 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) · 27 unmodified lines
618510 {
619511 struct amdgpu_device *adev = get_amdgpu_device(kgd);
620512 struct v10_sdma_mqd *m;
621− uint32_t sdma_base_addr;
513+ uint32_t sdma_rlc_reg_offset;
622514 uint32_t sdma_rlc_rb_cntl;
623515
624516 m = get_sdma_mqd(mqd);
625− sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
517+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
626518 m->sdma_queue_id);
627519
628− sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
520+ sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
629521
630522 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
631523 return true;
@@ -746,59 +638,52 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, · 114 unmodified lines
746638 {
747639 struct amdgpu_device *adev = get_amdgpu_device(kgd);
748640 struct v10_sdma_mqd *m;
749− uint32_t sdma_base_addr;
641+ uint32_t sdma_rlc_reg_offset;
750642 uint32_t temp;
751643 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
752644
753645 m = get_sdma_mqd(mqd);
754− sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
646+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
755647 m->sdma_queue_id);
756648
757− temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
649+ temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
758650 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
759− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
651+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
760652
761653 while (true) {
762− temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
654+ temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
763655 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
764656 break;
765− if (time_after(jiffies, end_jiffies))
657+ if (time_after(jiffies, end_jiffies)) {
658+ pr_err("SDMA RLC not idle in %s\n", __func__);
766659 return -ETIME;
660+ }
767661 usleep_range(500, 1000);
768662 }
769663
770− WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
771− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
772− RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
664+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
665+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
666+ RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
773667 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
774668
775− m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
669+ m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
776670 m->sdmax_rlcx_rb_rptr_hi =
777− RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI);
671+ RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
778672
779673 return 0;
780674 }
781675
782−static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
783− uint8_t vmid)
676+static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
677+ uint8_t vmid, uint16_t *p_pasid)
784678 {
785− uint32_t reg;
679+ uint32_t value;
786680 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
787681
788− reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
682+ value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
789683 + vmid);
790− return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
791−}
792−
793−static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
794− uint8_t vmid)
795−{
796− uint32_t reg;
797− struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
684+ *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
798685
799− reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
800− + vmid);
801− return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
686+ return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
802687 }
803688
804689 static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid)
@@ -830,6 +715,8 @@ static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) · 25 unmodified lines
830715 {
831716 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
832717 int vmid;
718+ uint16_t queried_pasid;
719+ bool ret;
833720 struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
834721
835722 if (amdgpu_emu_mode == 0 && ring->sched.ready)
@@ -838,13 +725,13 @@ static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) · 2 unmodified lines
838725 for (vmid = 0; vmid < 16; vmid++) {
839726 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
840727 continue;
841− if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
842− if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
843− == pasid) {
844− amdgpu_gmc_flush_gpu_tlb(adev, vmid,
845− AMDGPU_GFXHUB_0, 0);
846− break;
847− }
728+
729+ ret = get_atc_vmid_pasid_mapping_info(kgd, vmid,
730+ &queried_pasid);
731+ if (ret && queried_pasid == pasid) {
732+ amdgpu_gmc_flush_gpu_tlb(adev, vmid,
733+ AMDGPU_GFXHUB_0, 0);
734+ break;
848735 }
849736 }
850737
@@ -914,7 +801,6 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, · 63 unmodified lines
914801 uint64_t page_table_base)
915802 {
916803 struct amdgpu_device *adev = get_amdgpu_device(kgd);
917− uint64_t base = page_table_base | AMDGPU_PTE_VALID;
918804
919805 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
920806 pr_err("trying to set page table base for wrong VMID %u\n",
@@ -922,18 +808,31 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, · 1 unmodified line
922808 return;
923809 }
924810
925− /* TODO: take advantage of per-process address space size. For
926− * now, all processes share the same address space size, like
927− * on GFX8 and older.
928− */
929− WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0);
930− WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0);
931−
932− WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2),
933− lower_32_bits(adev->vm_manager.max_pfn - 1));
934− WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2),
935− upper_32_bits(adev->vm_manager.max_pfn - 1));
936−
937− WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base));
938− WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base));
811+ /* SDMA is on gfxhub as well for Navi1* series */
812+ gfxhub_v2_0_setup_vm_pt_regs(adev, vmid, page_table_base);
939813 }
814+
815+const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
816+ .program_sh_mem_settings = kgd_program_sh_mem_settings,
817+ .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
818+ .init_interrupts = kgd_init_interrupts,
819+ .hqd_load = kgd_hqd_load,
820+ .hqd_sdma_load = kgd_hqd_sdma_load,
821+ .hqd_dump = kgd_hqd_dump,
822+ .hqd_sdma_dump = kgd_hqd_sdma_dump,
823+ .hqd_is_occupied = kgd_hqd_is_occupied,
824+ .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
825+ .hqd_destroy = kgd_hqd_destroy,
826+ .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
827+ .address_watch_disable = kgd_address_watch_disable,
828+ .address_watch_execute = kgd_address_watch_execute,
829+ .wave_control_execute = kgd_wave_control_execute,
830+ .address_watch_get_offset = kgd_address_watch_get_offset,
831+ .get_atc_vmid_pasid_mapping_info =
832+ get_atc_vmid_pasid_mapping_info,
833+ .get_tile_config = amdgpu_amdkfd_get_tile_config,
834+ .set_vm_context_page_table_base = set_vm_context_page_table_base,
835+ .invalidate_tlbs = invalidate_tlbs,
836+ .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
837+ .get_hive_id = amdgpu_amdkfd_get_hive_id,
838+};
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c+67−147
@@ -20,8 +20,6 @@ · 19 unmodified lines
2020 * OTHER DEALINGS IN THE SOFTWARE.
2121 */
2222
23−#include <linux/fdtable.h>
24−#include <linux/uaccess.h>
2523 #include <linux/mmu_context.h>
2624
2725 #include "amdgpu.h"
@@ -86,65 +84,6 @@ union TCP_WATCH_CNTL_BITS { · 58 unmodified lines
8684 float f32All;
8785 };
8886
89−/*
90− * Register access functions
91− */
92−
93−static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
94− uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
95− uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
96−
97−static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
98− unsigned int vmid);
99−
100−static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
101−static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
102− uint32_t queue_id, uint32_t __user *wptr,
103− uint32_t wptr_shift, uint32_t wptr_mask,
104− struct mm_struct *mm);
105−static int kgd_hqd_dump(struct kgd_dev *kgd,
106− uint32_t pipe_id, uint32_t queue_id,
107− uint32_t (**dump)[2], uint32_t *n_regs);
108−static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
109− uint32_t __user *wptr, struct mm_struct *mm);
110−static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
111− uint32_t engine_id, uint32_t queue_id,
112− uint32_t (**dump)[2], uint32_t *n_regs);
113−static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
114− uint32_t pipe_id, uint32_t queue_id);
115−
116−static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
117− enum kfd_preempt_type reset_type,
118− unsigned int utimeout, uint32_t pipe_id,
119− uint32_t queue_id);
120−static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
121−static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
122− unsigned int utimeout);
123−static int kgd_address_watch_disable(struct kgd_dev *kgd);
124−static int kgd_address_watch_execute(struct kgd_dev *kgd,
125− unsigned int watch_point_id,
126− uint32_t cntl_val,
127− uint32_t addr_hi,
128− uint32_t addr_lo);
129−static int kgd_wave_control_execute(struct kgd_dev *kgd,
130− uint32_t gfx_index_val,
131− uint32_t sq_cmd);
132−static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
133− unsigned int watch_point_id,
134− unsigned int reg_offset);
135−
136−static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
137−static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
138− uint8_t vmid);
139−
140−static void set_scratch_backing_va(struct kgd_dev *kgd,
141− uint64_t va, uint32_t vmid);
142−static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
143− uint64_t page_table_base);
144−static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
145−static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
146−static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd);
147−
14887 /* Because of REG_GET_FIELD() being used, we put this function in the
14988 * asic specific file.
15089 */
@@ -170,37 +109,6 @@ static int get_tile_config(struct kgd_dev *kgd, · 19 unmodified lines
170109 return 0;
171110 }
172111
173−static const struct kfd2kgd_calls kfd2kgd = {
174− .program_sh_mem_settings = kgd_program_sh_mem_settings,
175− .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
176− .init_interrupts = kgd_init_interrupts,
177− .hqd_load = kgd_hqd_load,
178− .hqd_sdma_load = kgd_hqd_sdma_load,
179− .hqd_dump = kgd_hqd_dump,
180− .hqd_sdma_dump = kgd_hqd_sdma_dump,
181− .hqd_is_occupied = kgd_hqd_is_occupied,
182− .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
183− .hqd_destroy = kgd_hqd_destroy,
184− .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
185− .address_watch_disable = kgd_address_watch_disable,
186− .address_watch_execute = kgd_address_watch_execute,
187− .wave_control_execute = kgd_wave_control_execute,
188− .address_watch_get_offset = kgd_address_watch_get_offset,
189− .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
190− .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
191− .set_scratch_backing_va = set_scratch_backing_va,
192− .get_tile_config = get_tile_config,
193− .set_vm_context_page_table_base = set_vm_context_page_table_base,
194− .invalidate_tlbs = invalidate_tlbs,
195− .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
196− .read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
197−};
198−
199−struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
200−{
201− return (struct kfd2kgd_calls *)&kfd2kgd;
202−}
203−
204112 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
205113 {
206114 return (struct amdgpu_device *)kgd;
@@ -303,14 +211,15 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) · 96 unmodified lines
303211 return 0;
304212 }
305213
306−static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
214+static inline uint32_t get_sdma_rlc_reg_offset(struct cik_sdma_rlc_registers *m)
307215 {
308216 uint32_t retval;
309217
310218 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
311219 m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
312220
313− pr_debug("sdma base address: 0x%x\n", retval);
221+ pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n",
222+ m->sdma_engine_id, m->sdma_queue_id, retval);
314223
315224 return retval;
316225 }
@@ -413,60 +322,52 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, · 96 unmodified lines
413322 struct amdgpu_device *adev = get_amdgpu_device(kgd);
414323 struct cik_sdma_rlc_registers *m;
415324 unsigned long end_jiffies;
416− uint32_t sdma_base_addr;
325+ uint32_t sdma_rlc_reg_offset;
417326 uint32_t data;
418327
419328 m = get_sdma_mqd(mqd);
420− sdma_base_addr = get_sdma_base_addr(m);
329+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
421330
422− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
331+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
423332 m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
424333
425334 end_jiffies = msecs_to_jiffies(2000) + jiffies;
426335 while (true) {
427− data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
336+ data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
428337 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
429338 break;
430− if (time_after(jiffies, end_jiffies))
339+ if (time_after(jiffies, end_jiffies)) {
340+ pr_err("SDMA RLC not idle in %s\n", __func__);
431341 return -ETIME;
342+ }
432343 usleep_range(500, 1000);
433344 }
434− if (m->sdma_engine_id) {
435− data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
436− data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
437− RESUME_CTX, 0);
438− WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
439− } else {
440− data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
441− data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
442− RESUME_CTX, 0);
443− WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
444− }
445345
446346 data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
447347 ENABLE, 1);
448− WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
449− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr);
348+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
349+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
350+ m->sdma_rlc_rb_rptr);
450351
451352 if (read_user_wptr(mm, wptr, data))
452− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
353+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
453354 else
454− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
355+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
455356 m->sdma_rlc_rb_rptr);
456357
457− WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
358+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
458359 m->sdma_rlc_virtual_addr);
459− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
460− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
360+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
361+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
461362 m->sdma_rlc_rb_base_hi);
462− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
363+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
463364 m->sdma_rlc_rb_rptr_addr_lo);
464− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
365+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
465366 m->sdma_rlc_rb_rptr_addr_hi);
466367
467368 data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
468369 RB_ENABLE, 1);
469− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
370+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
470371
471372 return 0;
472373 }
@@ -524,13 +425,13 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) · 51 unmodified lines
524425 {
525426 struct amdgpu_device *adev = get_amdgpu_device(kgd);
526427 struct cik_sdma_rlc_registers *m;
527− uint32_t sdma_base_addr;
428+ uint32_t sdma_rlc_reg_offset;
528429 uint32_t sdma_rlc_rb_cntl;
529430
530431 m = get_sdma_mqd(mqd);
531− sdma_base_addr = get_sdma_base_addr(m);
432+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
532433
533− sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
434+ sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
534435
535436 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
536437 return true;
@@ -645,32 +546,34 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, · 108 unmodified lines
645546 {
646547 struct amdgpu_device *adev = get_amdgpu_device(kgd);
647548 struct cik_sdma_rlc_registers *m;
648− uint32_t sdma_base_addr;
549+ uint32_t sdma_rlc_reg_offset;
649550 uint32_t temp;
650551 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
651552
652553 m = get_sdma_mqd(mqd);
653− sdma_base_addr = get_sdma_base_addr(m);
554+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
654555
655− temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
556+ temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
656557 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
657− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
558+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
658559
659560 while (true) {
660− temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
561+ temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
661562 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
662563 break;
663− if (time_after(jiffies, end_jiffies))
564+ if (time_after(jiffies, end_jiffies)) {
565+ pr_err("SDMA RLC not idle in %s\n", __func__);
664566 return -ETIME;
567+ }
665568 usleep_range(500, 1000);
666569 }
667570
668− WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
669− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
670− RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
571+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
572+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
573+ RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
671574 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
672575
673− m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
576+ m->sdma_rlc_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
674577
675578 return 0;
676579 }
@@ -758,24 +661,16 @@ static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, · 81 unmodified lines
758661 return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
759662 }
760663
761−static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
762− uint8_t vmid)
664+static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
665+ uint8_t vmid, uint16_t *p_pasid)
763666 {
764− uint32_t reg;
667+ uint32_t value;
765668 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
766669
767− reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
768− return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
769−}
770−
771−static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
772− uint8_t vmid)
773−{
774− uint32_t reg;
775− struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
670+ value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
671+ *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
776672
777− reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
778− return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
673+ return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
779674 }
780675
781676 static void set_scratch_backing_va(struct kgd_dev *kgd,
@@ -855,3 +750,28 @@ static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd) · 73 unmodified lines
855750
856751 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
857752 }
753+
754+const struct kfd2kgd_calls gfx_v7_kfd2kgd = {
755+ .program_sh_mem_settings = kgd_program_sh_mem_settings,
756+ .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
757+ .init_interrupts = kgd_init_interrupts,
758+ .hqd_load = kgd_hqd_load,
759+ .hqd_sdma_load = kgd_hqd_sdma_load,
760+ .hqd_dump = kgd_hqd_dump,
761+ .hqd_sdma_dump = kgd_hqd_sdma_dump,
762+ .hqd_is_occupied = kgd_hqd_is_occupied,
763+ .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
764+ .hqd_destroy = kgd_hqd_destroy,
765+ .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
766+ .address_watch_disable = kgd_address_watch_disable,
767+ .address_watch_execute = kgd_address_watch_execute,
768+ .wave_control_execute = kgd_wave_control_execute,
769+ .address_watch_get_offset = kgd_address_watch_get_offset,
770+ .get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,
771+ .set_scratch_backing_va = set_scratch_backing_va,
772+ .get_tile_config = get_tile_config,
773+ .set_vm_context_page_table_base = set_vm_context_page_table_base,
774+ .invalidate_tlbs = invalidate_tlbs,
775+ .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
776+ .read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
777+};
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c+68−146
@@ -20,9 +20,6 @@ · 19 unmodified lines
2020 * OTHER DEALINGS IN THE SOFTWARE.
2121 */
2222
23−#include <linux/module.h>
24−#include <linux/fdtable.h>
25−#include <linux/uaccess.h>
2623 #include <linux/mmu_context.h>
2724
2825 #include "amdgpu.h"
@@ -44,62 +41,6 @@ enum hqd_dequeue_request_type { · 15 unmodified lines
4441 RESET_WAVES
4542 };
4643
47−/*
48− * Register access functions
49− */
50−
51−static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
52− uint32_t sh_mem_config,
53− uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
54− uint32_t sh_mem_bases);
55−static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
56− unsigned int vmid);
57−static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
58−static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
59− uint32_t queue_id, uint32_t __user *wptr,
60− uint32_t wptr_shift, uint32_t wptr_mask,
61− struct mm_struct *mm);
62−static int kgd_hqd_dump(struct kgd_dev *kgd,
63− uint32_t pipe_id, uint32_t queue_id,
64− uint32_t (**dump)[2], uint32_t *n_regs);
65−static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
66− uint32_t __user *wptr, struct mm_struct *mm);
67−static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
68− uint32_t engine_id, uint32_t queue_id,
69− uint32_t (**dump)[2], uint32_t *n_regs);
70−static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
71− uint32_t pipe_id, uint32_t queue_id);
72−static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
73−static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
74− enum kfd_preempt_type reset_type,
75− unsigned int utimeout, uint32_t pipe_id,
76− uint32_t queue_id);
77−static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
78− unsigned int utimeout);
79−static int kgd_address_watch_disable(struct kgd_dev *kgd);
80−static int kgd_address_watch_execute(struct kgd_dev *kgd,
81− unsigned int watch_point_id,
82− uint32_t cntl_val,
83− uint32_t addr_hi,
84− uint32_t addr_lo);
85−static int kgd_wave_control_execute(struct kgd_dev *kgd,
86− uint32_t gfx_index_val,
87− uint32_t sq_cmd);
88−static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
89− unsigned int watch_point_id,
90− unsigned int reg_offset);
91−
92−static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
93− uint8_t vmid);
94−static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
95− uint8_t vmid);
96−static void set_scratch_backing_va(struct kgd_dev *kgd,
97− uint64_t va, uint32_t vmid);
98−static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
99− uint64_t page_table_base);
100−static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
101−static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
102−
10344 /* Because of REG_GET_FIELD() being used, we put this function in the
10445 * asic specific file.
10546 */
@@ -125,38 +66,6 @@ static int get_tile_config(struct kgd_dev *kgd, · 19 unmodified lines
12566 return 0;
12667 }
12768
128−static const struct kfd2kgd_calls kfd2kgd = {
129− .program_sh_mem_settings = kgd_program_sh_mem_settings,
130− .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
131− .init_interrupts = kgd_init_interrupts,
132− .hqd_load = kgd_hqd_load,
133− .hqd_sdma_load = kgd_hqd_sdma_load,
134− .hqd_dump = kgd_hqd_dump,
135− .hqd_sdma_dump = kgd_hqd_sdma_dump,
136− .hqd_is_occupied = kgd_hqd_is_occupied,
137− .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
138− .hqd_destroy = kgd_hqd_destroy,
139− .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
140− .address_watch_disable = kgd_address_watch_disable,
141− .address_watch_execute = kgd_address_watch_execute,
142− .wave_control_execute = kgd_wave_control_execute,
143− .address_watch_get_offset = kgd_address_watch_get_offset,
144− .get_atc_vmid_pasid_mapping_pasid =
145− get_atc_vmid_pasid_mapping_pasid,
146− .get_atc_vmid_pasid_mapping_valid =
147− get_atc_vmid_pasid_mapping_valid,
148− .set_scratch_backing_va = set_scratch_backing_va,
149− .get_tile_config = get_tile_config,
150− .set_vm_context_page_table_base = set_vm_context_page_table_base,
151− .invalidate_tlbs = invalidate_tlbs,
152− .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
153−};
154−
155−struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
156−{
157− return (struct kfd2kgd_calls *)&kfd2kgd;
158−}
159−
16069 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
16170 {
16271 return (struct amdgpu_device *)kgd;
@@ -260,13 +169,15 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) · 97 unmodified lines
260169 return 0;
261170 }
262171
263−static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m)
172+static inline uint32_t get_sdma_rlc_reg_offset(struct vi_sdma_mqd *m)
264173 {
265174 uint32_t retval;
266175
267176 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
268177 m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
269− pr_debug("sdma base address: 0x%x\n", retval);
178+
179+ pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n",
180+ m->sdma_engine_id, m->sdma_queue_id, retval);
270181
271182 return retval;
272183 }
@@ -398,59 +309,51 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, · 125 unmodified lines
398309 struct amdgpu_device *adev = get_amdgpu_device(kgd);
399310 struct vi_sdma_mqd *m;
400311 unsigned long end_jiffies;
401− uint32_t sdma_base_addr;
312+ uint32_t sdma_rlc_reg_offset;
402313 uint32_t data;
403314
404315 m = get_sdma_mqd(mqd);
405− sdma_base_addr = get_sdma_base_addr(m);
406− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
316+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
317+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
407318 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
408319
409320 end_jiffies = msecs_to_jiffies(2000) + jiffies;
410321 while (true) {
411− data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
322+ data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
412323 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
413324 break;
414− if (time_after(jiffies, end_jiffies))
325+ if (time_after(jiffies, end_jiffies)) {
326+ pr_err("SDMA RLC not idle in %s\n", __func__);
415327 return -ETIME;
328+ }
416329 usleep_range(500, 1000);
417330 }
418− if (m->sdma_engine_id) {
419− data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
420− data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
421− RESUME_CTX, 0);
422− WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
423− } else {
424− data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
425− data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
426− RESUME_CTX, 0);
427− WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
428− }
429331
430332 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
431333 ENABLE, 1);
432− WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
433− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
334+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
335+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
336+ m->sdmax_rlcx_rb_rptr);
434337
435338 if (read_user_wptr(mm, wptr, data))
436− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
339+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
437340 else
438− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
341+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
439342 m->sdmax_rlcx_rb_rptr);
440343
441− WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
344+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
442345 m->sdmax_rlcx_virtual_addr);
443− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
444− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
346+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
347+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
445348 m->sdmax_rlcx_rb_base_hi);
446− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
349+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
447350 m->sdmax_rlcx_rb_rptr_addr_lo);
448− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
351+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
449352 m->sdmax_rlcx_rb_rptr_addr_hi);
450353
451354 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
452355 RB_ENABLE, 1);
453− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
356+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
454357
455358 return 0;
456359 }
@@ -517,13 +420,13 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) · 60 unmodified lines
517420 {
518421 struct amdgpu_device *adev = get_amdgpu_device(kgd);
519422 struct vi_sdma_mqd *m;
520− uint32_t sdma_base_addr;
423+ uint32_t sdma_rlc_reg_offset;
521424 uint32_t sdma_rlc_rb_cntl;
522425
523426 m = get_sdma_mqd(mqd);
524− sdma_base_addr = get_sdma_base_addr(m);
427+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
525428
526− sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
429+ sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
527430
528431 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
529432 return true;
@@ -641,54 +544,48 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, · 111 unmodified lines
641544 {
642545 struct amdgpu_device *adev = get_amdgpu_device(kgd);
643546 struct vi_sdma_mqd *m;
644− uint32_t sdma_base_addr;
547+ uint32_t sdma_rlc_reg_offset;
645548 uint32_t temp;
646549 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
647550
648551 m = get_sdma_mqd(mqd);
649− sdma_base_addr = get_sdma_base_addr(m);
552+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
650553
651− temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
554+ temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
652555 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
653− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
556+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
654557
655558 while (true) {
656− temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
559+ temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
657560 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
658561 break;
659− if (time_after(jiffies, end_jiffies))
562+ if (time_after(jiffies, end_jiffies)) {
563+ pr_err("SDMA RLC not idle in %s\n", __func__);
660564 return -ETIME;
565+ }
661566 usleep_range(500, 1000);
662567 }
663568
664− WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
665− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
666− RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
569+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
570+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
571+ RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
667572 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
668573
669− m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
574+ m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
670575
671576 return 0;
672577 }
673578
674−static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
675− uint8_t vmid)
579+static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
580+ uint8_t vmid, uint16_t *p_pasid)
676581 {
677− uint32_t reg;
582+ uint32_t value;
678583 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
679584
680− reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
681− return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
682−}
585+ value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
586+ *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
683587
684−static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
685− uint8_t vmid)
686−{
687− uint32_t reg;
688− struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
689−
690− reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
691− return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
588+ return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
692589 }
693590
694591 static int kgd_address_watch_disable(struct kgd_dev *kgd)
@@ -798,3 +695,28 @@ static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) · 103 unmodified lines
798695 RREG32(mmVM_INVALIDATE_RESPONSE);
799696 return 0;
800697 }
698+
699+const struct kfd2kgd_calls gfx_v8_kfd2kgd = {
700+ .program_sh_mem_settings = kgd_program_sh_mem_settings,
701+ .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
702+ .init_interrupts = kgd_init_interrupts,
703+ .hqd_load = kgd_hqd_load,
704+ .hqd_sdma_load = kgd_hqd_sdma_load,
705+ .hqd_dump = kgd_hqd_dump,
706+ .hqd_sdma_dump = kgd_hqd_sdma_dump,
707+ .hqd_is_occupied = kgd_hqd_is_occupied,
708+ .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
709+ .hqd_destroy = kgd_hqd_destroy,
710+ .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
711+ .address_watch_disable = kgd_address_watch_disable,
712+ .address_watch_execute = kgd_address_watch_execute,
713+ .wave_control_execute = kgd_wave_control_execute,
714+ .address_watch_get_offset = kgd_address_watch_get_offset,
715+ .get_atc_vmid_pasid_mapping_info =
716+ get_atc_vmid_pasid_mapping_info,
717+ .set_scratch_backing_va = set_scratch_backing_va,
718+ .get_tile_config = get_tile_config,
719+ .set_vm_context_page_table_base = set_vm_context_page_table_base,
720+ .invalidate_tlbs = invalidate_tlbs,
721+ .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
722+};
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c+70−106
@@ -19,17 +19,10 @@ · 18 unmodified lines
1919 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2020 * OTHER DEALINGS IN THE SOFTWARE.
2121 */
22−
23−#define pr_fmt(fmt) "kfd2kgd: " fmt
24−
25−#include <linux/module.h>
26−#include <linux/fdtable.h>
27−#include <linux/uaccess.h>
2822 #include <linux/mmu_context.h>
2923
3024 #include "amdgpu.h"
3125 #include "amdgpu_amdkfd.h"
32−#include "soc15_hw_ip.h"
3326 #include "gc/gc_9_0_offset.h"
3427 #include "gc/gc_9_0_sh_mask.h"
3528 #include "vega10_enum.h"
@@ -50,9 +43,6 @@ · 14 unmodified lines
5043 #include "gmc_v9_0.h"
5144
5245
53−#define V9_PIPE_PER_MEC (4)
54−#define V9_QUEUES_PER_PIPE_MEC (8)
55−
5646 enum hqd_dequeue_request_type {
5747 NO_ACTION = 0,
5848 DRAIN_PIPE,
@@ -226,22 +216,21 @@ int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) · 167 unmodified lines
226216 return 0;
227217 }
228218
229−static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
219+static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
230220 unsigned int engine_id,
231221 unsigned int queue_id)
232222 {
233− uint32_t base[2] = {
223+ uint32_t sdma_engine_reg_base[2] = {
234224 SOC15_REG_OFFSET(SDMA0, 0,
235225 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
236226 SOC15_REG_OFFSET(SDMA1, 0,
237227 mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL
238228 };
239− uint32_t retval;
229+ uint32_t retval = sdma_engine_reg_base[engine_id]
230+ + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
240231
241− retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
242− mmSDMA0_RLC0_RB_CNTL);
243−
244− pr_debug("sdma base address: 0x%x\n", retval);
232+ pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
233+ queue_id, retval);
245234
246235 return retval;
247236 }
@@ -388,71 +377,67 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, · 140 unmodified lines
388377 {
389378 struct amdgpu_device *adev = get_amdgpu_device(kgd);
390379 struct v9_sdma_mqd *m;
391− uint32_t sdma_base_addr, sdmax_gfx_context_cntl;
380+ uint32_t sdma_rlc_reg_offset;
392381 unsigned long end_jiffies;
393382 uint32_t data;
394383 uint64_t data64;
395384 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
396385
397386 m = get_sdma_mqd(mqd);
398− sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
387+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
399388 m->sdma_queue_id);
400− sdmax_gfx_context_cntl = m->sdma_engine_id ?
401− SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) :
402− SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL);
403389
404− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
390+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
405391 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
406392
407393 end_jiffies = msecs_to_jiffies(2000) + jiffies;
408394 while (true) {
409− data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
395+ data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
410396 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
411397 break;
412− if (time_after(jiffies, end_jiffies))
398+ if (time_after(jiffies, end_jiffies)) {
399+ pr_err("SDMA RLC not idle in %s\n", __func__);
413400 return -ETIME;
401+ }
414402 usleep_range(500, 1000);
415403 }
416− data = RREG32(sdmax_gfx_context_cntl);
417− data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
418− RESUME_CTX, 0);
419− WREG32(sdmax_gfx_context_cntl, data);
420404
421− WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
405+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
422406 m->sdmax_rlcx_doorbell_offset);
423407
424408 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
425409 ENABLE, 1);
426− WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
427− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
428− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
410+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
411+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
412+ m->sdmax_rlcx_rb_rptr);
413+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
429414 m->sdmax_rlcx_rb_rptr_hi);
430415
431− WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
416+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
432417 if (read_user_wptr(mm, wptr64, data64)) {
433− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
418+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
434419 lower_32_bits(data64));
435− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
420+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
436421 upper_32_bits(data64));
437422 } else {
438− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
423+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
439424 m->sdmax_rlcx_rb_rptr);
440− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
425+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
441426 m->sdmax_rlcx_rb_rptr_hi);
442427 }
443− WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
428+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
444429
445− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
446− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
430+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
431+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
447432 m->sdmax_rlcx_rb_base_hi);
448− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
433+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
449434 m->sdmax_rlcx_rb_rptr_addr_lo);
450− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
435+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
451436 m->sdmax_rlcx_rb_rptr_addr_hi);
452437
453438 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
454439 RB_ENABLE, 1);
455− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
440+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
456441
457442 return 0;
458443 }
@@ -462,7 +447,8 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, · 3 unmodified lines
462447 uint32_t (**dump)[2], uint32_t *n_regs)
463448 {
464449 struct amdgpu_device *adev = get_amdgpu_device(kgd);
465− uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
450+ uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
451+ engine_id, queue_id);
466452 uint32_t i = 0, reg;
467453 #undef HQD_N_REGS
468454 #define HQD_N_REGS (19+6+7+10)
@@ -472,15 +458,15 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, · 3 unmodified lines
472458 return -ENOMEM;
473459
474460 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
475− DUMP_REG(sdma_base_addr + reg);
461+ DUMP_REG(sdma_rlc_reg_offset + reg);
476462 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
477− DUMP_REG(sdma_base_addr + reg);
463+ DUMP_REG(sdma_rlc_reg_offset + reg);
478464 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
479465 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
480− DUMP_REG(sdma_base_addr + reg);
466+ DUMP_REG(sdma_rlc_reg_offset + reg);
481467 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
482468 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
483− DUMP_REG(sdma_base_addr + reg);
469+ DUMP_REG(sdma_rlc_reg_offset + reg);
484470
485471 WARN_ON_ONCE(i != HQD_N_REGS);
486472 *n_regs = i;
@@ -514,14 +500,14 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) · 27 unmodified lines
514500 {
515501 struct amdgpu_device *adev = get_amdgpu_device(kgd);
516502 struct v9_sdma_mqd *m;
517− uint32_t sdma_base_addr;
503+ uint32_t sdma_rlc_reg_offset;
518504 uint32_t sdma_rlc_rb_cntl;
519505
520506 m = get_sdma_mqd(mqd);
521− sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
507+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
522508 m->sdma_queue_id);
523509
524− sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
510+ sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
525511
526512 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
527513 return true;
@@ -584,59 +570,52 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, · 56 unmodified lines
584570 {
585571 struct amdgpu_device *adev = get_amdgpu_device(kgd);
586572 struct v9_sdma_mqd *m;
587− uint32_t sdma_base_addr;
573+ uint32_t sdma_rlc_reg_offset;
588574 uint32_t temp;
589575 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
590576
591577 m = get_sdma_mqd(mqd);
592− sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
578+ sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
593579 m->sdma_queue_id);
594580
595− temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
581+ temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
596582 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
597− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
583+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
598584
599585 while (true) {
600− temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
586+ temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
601587 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
602588 break;
603− if (time_after(jiffies, end_jiffies))
589+ if (time_after(jiffies, end_jiffies)) {
590+ pr_err("SDMA RLC not idle in %s\n", __func__);
604591 return -ETIME;
592+ }
605593 usleep_range(500, 1000);
606594 }
607595
608− WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
609− WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
610− RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
596+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
597+ WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
598+ RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
611599 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
612600
613− m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
601+ m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
614602 m->sdmax_rlcx_rb_rptr_hi =
615− RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI);
603+ RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
616604
617605 return 0;
618606 }
619607
620−bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
621− uint8_t vmid)
608+bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
609+ uint8_t vmid, uint16_t *p_pasid)
622610 {
623− uint32_t reg;
611+ uint32_t value;
624612 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
625613
626− reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
614+ value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
627615 + vmid);
628− return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
629−}
630−
631−uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
632− uint8_t vmid)
633−{
634− uint32_t reg;
635− struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
616+ *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
636617
637− reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
638− + vmid);
639− return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
618+ return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
640619 }
641620
642621 static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid,
@@ -671,6 +650,8 @@ int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) · 28 unmodified lines
671650 {
672651 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
673652 int vmid, i;
653+ uint16_t queried_pasid;
654+ bool ret;
674655 struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
675656 uint32_t flush_type = 0;
676657
@@ -686,14 +667,14 @@ int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) · 9 unmodified lines
686667 for (vmid = 0; vmid < 16; vmid++) {
687668 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
688669 continue;
689− if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
690− if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
691− == pasid) {
692− for (i = 0; i < adev->num_vmhubs; i++)
693− amdgpu_gmc_flush_gpu_tlb(adev, vmid,
694− i, flush_type);
695− break;
696− }
670+
671+ ret = kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(kgd, vmid,
672+ &queried_pasid);
673+ if (ret && queried_pasid == pasid) {
674+ for (i = 0; i < adev->num_vmhubs; i++)
675+ amdgpu_gmc_flush_gpu_tlb(adev, vmid,
676+ i, flush_type);
677+ break;
697678 }
698679 }
699680
@@ -777,15 +758,6 @@ uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd, · 77 unmodified lines
777758 return 0;
778759 }
779760
780−void kgd_gfx_v9_set_scratch_backing_va(struct kgd_dev *kgd,
781− uint64_t va, uint32_t vmid)
782−{
783− /* No longer needed on GFXv9. The scratch base address is
784− * passed to the shader by the CP. It's the user mode driver's
785− * responsibility.
786− */
787−}
788−
789761 void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
790762 uint64_t page_table_base)
791763 {
@@ -811,7 +783,7 @@ void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmi · 19 unmodified lines
811783 gfxhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
812784 }
813785
814−static const struct kfd2kgd_calls kfd2kgd = {
786+const struct kfd2kgd_calls gfx_v9_kfd2kgd = {
815787 .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
816788 .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
817789 .init_interrupts = kgd_gfx_v9_init_interrupts,
@@ -827,19 +799,11 @@ static const struct kfd2kgd_calls kfd2kgd = { · 9 unmodified lines
827799 .address_watch_execute = kgd_gfx_v9_address_watch_execute,
828800 .wave_control_execute = kgd_gfx_v9_wave_control_execute,
829801 .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
830− .get_atc_vmid_pasid_mapping_pasid =
831− kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid,
832− .get_atc_vmid_pasid_mapping_valid =
833− kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid,
834− .set_scratch_backing_va = kgd_gfx_v9_set_scratch_backing_va,
802+ .get_atc_vmid_pasid_mapping_info =
803+ kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
835804 .get_tile_config = kgd_gfx_v9_get_tile_config,
836805 .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
837806 .invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
838807 .invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid,
839808 .get_hive_id = amdgpu_amdkfd_get_hive_id,
840809 };
841−
842−struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
843−{
844− return (struct kfd2kgd_calls *)&kfd2kgd;
845−}
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h+2−6
@@ -55,14 +55,10 @@ uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd, · 54 unmodified lines
5555 unsigned int watch_point_id,
5656 unsigned int reg_offset);
5757
58−bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
59− uint8_t vmid);
60−uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
61− uint8_t vmid);
58+bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
59+ uint8_t vmid, uint16_t *p_pasid);
6260 void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
6361 uint64_t page_table_base);
64−void kgd_gfx_v9_set_scratch_backing_va(struct kgd_dev *kgd,
65− uint64_t va, uint32_t vmid);
6662 int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
6763 int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
6864 int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c+45−41
@@ -19,9 +19,6 @@ · 18 unmodified lines
1919 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2020 * OTHER DEALINGS IN THE SOFTWARE.
2121 */
22−
23−#define pr_fmt(fmt) "kfd2kgd: " fmt
24−
2522 #include <linux/dma-buf.h>
2623 #include <linux/list.h>
2724 #include <linux/pagemap.h>
@@ -33,11 +30,6 @@ · 5 unmodified lines
3330 #include "amdgpu_amdkfd.h"
3431 #include "amdgpu_dma_buf.h"
3532
36−/* Special VM and GART address alignment needed for VI pre-Fiji due to
37− * a HW bug.
38− */
39−#define VI_BO_SIZE_ALIGN (0x8000)
40−
4133 /* BO flag to indicate a KFD userptr BO */
4234 #define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63)
4335
@@ -349,13 +341,46 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync) · 305 unmodified lines
349341 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
350342 int ret;
351343
352− ret = amdgpu_vm_update_directories(adev, vm);
344+ ret = amdgpu_vm_update_pdes(adev, vm, false);
353345 if (ret)
354346 return ret;
355347
356348 return amdgpu_sync_fence(NULL, sync, vm->last_update, false);
357349 }
358350
351+static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
352+{
353+ struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
354+ bool coherent = mem->alloc_flags & ALLOC_MEM_FLAGS_COHERENT;
355+ uint32_t mapping_flags;
356+
357+ mapping_flags = AMDGPU_VM_PAGE_READABLE;
358+ if (mem->alloc_flags & ALLOC_MEM_FLAGS_WRITABLE)
359+ mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
360+ if (mem->alloc_flags & ALLOC_MEM_FLAGS_EXECUTABLE)
361+ mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
362+
363+ switch (adev->asic_type) {
364+ case CHIP_ARCTURUS:
365+ if (mem->alloc_flags & ALLOC_MEM_FLAGS_VRAM) {
366+ if (bo_adev == adev)
367+ mapping_flags |= coherent ?
368+ AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
369+ else
370+ mapping_flags |= AMDGPU_VM_MTYPE_UC;
371+ } else {
372+ mapping_flags |= coherent ?
373+ AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
374+ }
375+ break;
376+ default:
377+ mapping_flags |= coherent ?
378+ AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
379+ }
380+
381+ return amdgpu_gem_va_map_flags(adev, mapping_flags);
382+}
383+
359384 /* add_bo_to_vm - Add a BO to a VM
360385 *
361386 * Everything that needs to bo done only once when a BO is first added
@@ -404,8 +429,7 @@ static int add_bo_to_vm(struct amdgpu_device *adev, struct kgd_mem *mem, · 42 unmodified lines
404429 }
405430
406431 bo_va_entry->va = va;
407− bo_va_entry->pte_flags = amdgpu_gmc_get_pte_flags(adev,
408− mem->mapping_flags);
432+ bo_va_entry->pte_flags = get_pte_flags(adev, mem);
409433 bo_va_entry->kgd_dev = (void *)adev;
410434 list_add(&bo_va_entry->bo_list, list_bo_va);
411435
@@ -586,7 +610,7 @@ static int reserve_bo_and_vm(struct kgd_mem *mem, · 174 unmodified lines
586610 amdgpu_vm_get_pd_bo(vm, &ctx->list, &ctx->vm_pd[0]);
587611
588612 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
589− false, &ctx->duplicates, true);
613+ false, &ctx->duplicates);
590614 if (!ret)
591615 ctx->reserved = true;
592616 else {
@@ -659,7 +683,7 @@ static int reserve_bo_and_cond_vms(struct kgd_mem *mem, · 66 unmodified lines
659683 }
660684
661685 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
662− false, &ctx->duplicates, true);
686+ false, &ctx->duplicates);
663687 if (!ret)
664688 ctx->reserved = true;
665689 else
@@ -1079,10 +1103,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( · 413 unmodified lines
10791103 uint64_t user_addr = 0;
10801104 struct amdgpu_bo *bo;
10811105 struct amdgpu_bo_param bp;
1082− int byte_align;
10831106 u32 domain, alloc_domain;
10841107 u64 alloc_flags;
1085− uint32_t mapping_flags;
10861108 int ret;
10871109
10881110 /*
@@ -1135,25 +1157,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( · 46 unmodified lines
11351157 if ((*mem)->aql_queue)
11361158 size = size >> 1;
11371159
1138− /* Workaround for TLB bug on older VI chips */
1139− byte_align = (adev->family == AMDGPU_FAMILY_VI &&
1140− adev->asic_type != CHIP_FIJI &&
1141− adev->asic_type != CHIP_POLARIS10 &&
1142− adev->asic_type != CHIP_POLARIS11 &&
1143− adev->asic_type != CHIP_POLARIS12 &&
1144− adev->asic_type != CHIP_VEGAM) ?
1145− VI_BO_SIZE_ALIGN : 1;
1146−
1147− mapping_flags = AMDGPU_VM_PAGE_READABLE;
1148− if (flags & ALLOC_MEM_FLAGS_WRITABLE)
1149− mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
1150− if (flags & ALLOC_MEM_FLAGS_EXECUTABLE)
1151− mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
1152− if (flags & ALLOC_MEM_FLAGS_COHERENT)
1153− mapping_flags |= AMDGPU_VM_MTYPE_UC;
1154− else
1155− mapping_flags |= AMDGPU_VM_MTYPE_NC;
1156− (*mem)->mapping_flags = mapping_flags;
1160+ (*mem)->alloc_flags = flags;
11571161
11581162 amdgpu_sync_create(&(*mem)->sync);
11591163
@@ -1168,7 +1172,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( · 8 unmodified lines
11681172
11691173 memset(&bp, 0, sizeof(bp));
11701174 bp.size = size;
1171− bp.byte_align = byte_align;
1175+ bp.byte_align = 1;
11721176 bp.domain = alloc_domain;
11731177 bp.flags = alloc_flags;
11741178 bp.type = bo_type;
@@ -1626,9 +1630,10 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, · 451 unmodified lines
16261630
16271631 INIT_LIST_HEAD(&(*mem)->bo_va_list);
16281632 mutex_init(&(*mem)->lock);
1629− (*mem)->mapping_flags =
1630− AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
1631− AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_NC;
1633+ (*mem)->alloc_flags =
1634+ ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
1635+ ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT) |
1636+ ALLOC_MEM_FLAGS_WRITABLE | ALLOC_MEM_FLAGS_EXECUTABLE;
16321637
16331638 (*mem)->bo = amdgpu_bo_ref(bo);
16341639 (*mem)->va = va;
@@ -1797,8 +1802,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) · 162 unmodified lines
17971802 }
17981803
17991804 /* Reserve all BOs and page tables for validation */
1800− ret = ttm_eu_reserve_buffers(&ticket, &resv_list, false, &duplicates,
1801− true);
1805+ ret = ttm_eu_reserve_buffers(&ticket, &resv_list, false, &duplicates);
18021806 WARN(!list_empty(&duplicates), "Duplicates should be empty");
18031807 if (ret)
18041808 goto out_free;
@@ -1996,7 +2000,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef) · 191 unmodified lines
19962000 }
19972001
19982002 ret = ttm_eu_reserve_buffers(&ctx.ticket, &ctx.list,
1999− false, &duplicate_save, true);
2003+ false, &duplicate_save);
20002004 if (ret) {
20012005 pr_debug("Memory eviction: TTM Reserve Failed. Try again\n");
20022006 goto ttm_reserve_fail;
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c+5−0
@@ -2038,6 +2038,11 @@ int amdgpu_atombios_init(struct amdgpu_device *adev) · 2037 unmodified lines
20382038 if (adev->is_atom_fw) {
20392039 amdgpu_atomfirmware_scratch_regs_init(adev);
20402040 amdgpu_atomfirmware_allocate_fb_scratch(adev);
2041+ ret = amdgpu_atomfirmware_get_mem_train_fb_loc(adev);
2042+ if (ret) {
2043+ DRM_ERROR("Failed to get mem train fb location.\n");
2044+ return ret;
2045+ }
20412046 } else {
20422047 amdgpu_atombios_scratch_regs_init(adev);
20432048 amdgpu_atombios_allocate_fb_scratch(adev);
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c+204−70
@@ -27,6 +27,7 @@ · 26 unmodified lines
2727 #include "amdgpu_atomfirmware.h"
2828 #include "atom.h"
2929 #include "atombios.h"
30+#include "soc15_hw_ip.h"
3031
3132 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
3233 {
@@ -120,65 +121,14 @@ union vram_info { · 87 unmodified lines
120121 struct atom_vram_info_header_v2_3 v23;
121122 struct atom_vram_info_header_v2_4 v24;
122123 };
123−/*
124− * Return vram width from integrated system info table, if available,
125− * or 0 if not.
126− */
127−int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
128−{
129− struct amdgpu_mode_info *mode_info = &adev->mode_info;
130− int index;
131− u16 data_offset, size;
132− union igp_info *igp_info;
133− union vram_info *vram_info;
134− u32 mem_channel_number;
135− u32 mem_channel_width;
136− u8 frev, crev;
137−
138− if (adev->flags & AMD_IS_APU)
139− index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
140− integratedsysteminfo);
141− else
142− index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
143− vram_info);
144124
145− /* get any igp specific overrides */
146− if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
147− &frev, &crev, &data_offset)) {
148− if (adev->flags & AMD_IS_APU) {
149− igp_info = (union igp_info *)
150− (mode_info->atom_context->bios + data_offset);
151− switch (crev) {
152− case 11:
153− mem_channel_number = igp_info->v11.umachannelnumber;
154− /* channel width is 64 */
155− return mem_channel_number * 64;
156− default:
157− return 0;
158− }
159− } else {
160− vram_info = (union vram_info *)
161− (mode_info->atom_context->bios + data_offset);
162− switch (crev) {
163− case 3:
164− mem_channel_number = vram_info->v23.vram_module[0].channel_num;
165− mem_channel_width = vram_info->v23.vram_module[0].channel_width;
166− return mem_channel_number * (1 << mem_channel_width);
167− case 4:
168− mem_channel_number = vram_info->v24.vram_module[0].channel_num;
169− mem_channel_width = vram_info->v24.vram_module[0].channel_width;
170− return mem_channel_number * (1 << mem_channel_width);
171− default:
172− return 0;
173− }
174− }
175− }
176−
177− return 0;
178−}
125+union vram_module {
126+ struct atom_vram_module_v9 v9;
127+ struct atom_vram_module_v10 v10;
128+};
179129
180−static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev,
181− int atom_mem_type)
130+static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
131+ int atom_mem_type)
182132 {
183133 int vram_type;
184134
@@ -219,19 +169,25 @@ static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev, · 34 unmodified lines
219169
220170 return vram_type;
221171 }
222−/*
223− * Return vram type from either integrated system info table
224− * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
225− */
226−int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
172+
173+
174+int
175+amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
176+ int *vram_width, int *vram_type,
177+ int *vram_vendor)
227178 {
228179 struct amdgpu_mode_info *mode_info = &adev->mode_info;
229− int index;
180+ int index, i = 0;
230181 u16 data_offset, size;
231182 union igp_info *igp_info;
232183 union vram_info *vram_info;
184+ union vram_module *vram_module;
233185 u8 frev, crev;
234186 u8 mem_type;
187+ u8 mem_vendor;
188+ u32 mem_channel_number;
189+ u32 mem_channel_width;
190+ u32 module_id;
235191
236192 if (adev->flags & AMD_IS_APU)
237193 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
@@ -239,6 +195,7 @@ int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev) · 1 unmodified line
239195 else
240196 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
241197 vram_info);
198+
242199 if (amdgpu_atom_parse_data_header(mode_info->atom_context,
243200 index, &size,
244201 &frev, &crev, &data_offset)) {
@@ -247,25 +204,67 @@ int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev) · 2 unmodified lines
247204 (mode_info->atom_context->bios + data_offset);
248205 switch (crev) {
249206 case 11:
207+ mem_channel_number = igp_info->v11.umachannelnumber;
208+ /* channel width is 64 */
209+ if (vram_width)
210+ *vram_width = mem_channel_number * 64;
250211 mem_type = igp_info->v11.memorytype;
251− return convert_atom_mem_type_to_vram_type(adev, mem_type);
212+ if (vram_type)
213+ *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
214+ break;
252215 default:
253− return 0;
216+ return -EINVAL;
254217 }
255218 } else {
256219 vram_info = (union vram_info *)
257220 (mode_info->atom_context->bios + data_offset);
221+ module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
258222 switch (crev) {
259223 case 3:
260− mem_type = vram_info->v23.vram_module[0].memory_type;
261− return convert_atom_mem_type_to_vram_type(adev, mem_type);
224+ if (module_id > vram_info->v23.vram_module_num)
225+ module_id = 0;
226+ vram_module = (union vram_module *)vram_info->v23.vram_module;
227+ while (i < module_id) {
228+ vram_module = (union vram_module *)
229+ ((u8 *)vram_module + vram_module->v9.vram_module_size);
230+ i++;
231+ }
232+ mem_type = vram_module->v9.memory_type;
233+ if (vram_type)
234+ *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
235+ mem_channel_number = vram_module->v9.channel_num;
236+ mem_channel_width = vram_module->v9.channel_width;
237+ if (vram_width)
238+ *vram_width = mem_channel_number * (1 << mem_channel_width);
239+ mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
240+ if (vram_vendor)
241+ *vram_vendor = mem_vendor;
242+ break;
262243 case 4:
263− mem_type = vram_info->v24.vram_module[0].memory_type;
264− return convert_atom_mem_type_to_vram_type(adev, mem_type);
244+ if (module_id > vram_info->v24.vram_module_num)
245+ module_id = 0;
246+ vram_module = (union vram_module *)vram_info->v24.vram_module;
247+ while (i < module_id) {
248+ vram_module = (union vram_module *)
249+ ((u8 *)vram_module + vram_module->v10.vram_module_size);
250+ i++;
251+ }
252+ mem_type = vram_module->v10.memory_type;
253+ if (vram_type)
254+ *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
255+ mem_channel_number = vram_module->v10.channel_num;
256+ mem_channel_width = vram_module->v10.channel_width;
257+ if (vram_width)
258+ *vram_width = mem_channel_number * (1 << mem_channel_width);
259+ mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
260+ if (vram_vendor)
261+ *vram_vendor = mem_vendor;
262+ break;
265263 default:
266− return 0;
264+ return -EINVAL;
267265 }
268266 }
267+
269268 }
270269
271270 return 0;
@@ -464,3 +463,138 @@ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev) · 192 unmodified lines
464463 }
465464 return -EINVAL;
466465 }
466+
467+/*
468+ * Check if VBIOS supports GDDR6 training data save/restore
469+ */
470+static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
471+{
472+ uint16_t data_offset;
473+ int index;
474+
475+ index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
476+ firmwareinfo);
477+ if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
478+ NULL, NULL, &data_offset)) {
479+ struct atom_firmware_info_v3_1 *firmware_info =
480+ (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
481+ data_offset);
482+
483+ DRM_DEBUG("atom firmware capability:0x%08x.\n",
484+ le32_to_cpu(firmware_info->firmware_capability));
485+
486+ if (le32_to_cpu(firmware_info->firmware_capability) &
487+ ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING)
488+ return true;
489+ }
490+
491+ return false;
492+}
493+
494+static int gddr6_mem_train_support(struct amdgpu_device *adev)
495+{
496+ int ret;
497+ uint32_t major, minor, revision, hw_v;
498+
499+ if (gddr6_mem_train_vbios_support(adev)) {
500+ amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision);
501+ hw_v = HW_REV(major, minor, revision);
502+ /*
503+ * treat 0 revision as a special case since register for MP0 and MMHUB is missing
504+ * for some Navi10 A0, preventing driver from discovering the hwip information since
505+ * none of the functions will be initialized, it should not cause any problems
506+ */
507+ switch (hw_v) {
508+ case HW_REV(11, 0, 0):
509+ case HW_REV(11, 0, 5):
510+ ret = 1;
511+ break;
512+ default:
513+ DRM_ERROR("memory training vbios supports but psp hw(%08x)"
514+ " doesn't support!\n", hw_v);
515+ ret = -1;
516+ break;
517+ }
518+ } else {
519+ ret = 0;
520+ hw_v = -1;
521+ }
522+
523+
524+ DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret);
525+ return ret;
526+}
527+
528+int amdgpu_atomfirmware_get_mem_train_fb_loc(struct amdgpu_device *adev)
529+{
530+ struct atom_context *ctx = adev->mode_info.atom_context;
531+ unsigned char *bios = ctx->bios;
532+ struct vram_reserve_block *reserved_block;
533+ int index, block_number;
534+ uint8_t frev, crev;
535+ uint16_t data_offset, size;
536+ uint32_t start_address_in_kb;
537+ uint64_t offset;
538+ int ret;
539+
540+ adev->fw_vram_usage.mem_train_support = false;
541+
542+ if (adev->asic_type != CHIP_NAVI10 &&
543+ adev->asic_type != CHIP_NAVI14)
544+ return 0;
545+
546+ if (amdgpu_sriov_vf(adev))
547+ return 0;
548+
549+ ret = gddr6_mem_train_support(adev);
550+ if (ret == -1)
551+ return -EINVAL;
552+ else if (ret == 0)
553+ return 0;
554+
555+ index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
556+ vram_usagebyfirmware);
557+ ret = amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev,
558+ &data_offset);
559+ if (ret == 0) {
560+ DRM_ERROR("parse data header failed.\n");
561+ return -EINVAL;
562+ }
563+
564+ DRM_DEBUG("atom firmware common table header size:0x%04x, frev:0x%02x,"
565+ " crev:0x%02x, data_offset:0x%04x.\n", size, frev, crev, data_offset);
566+ /* only support 2.1+ */
567+ if (((uint16_t)frev << 8 | crev) < 0x0201) {
568+ DRM_ERROR("frev:0x%02x, crev:0x%02x < 2.1 !\n", frev, crev);
569+ return -EINVAL;
570+ }
571+
572+ reserved_block = (struct vram_reserve_block *)
573+ (bios + data_offset + sizeof(struct atom_common_table_header));
574+ block_number = ((unsigned int)size - sizeof(struct atom_common_table_header))
575+ / sizeof(struct vram_reserve_block);
576+ reserved_block += (block_number > 0) ? block_number-1 : 0;
577+ DRM_DEBUG("block_number:0x%04x, last block: 0x%08xkb sz, %dkb fw, %dkb drv.\n",
578+ block_number,
579+ le32_to_cpu(reserved_block->start_address_in_kb),
580+ le16_to_cpu(reserved_block->used_by_firmware_in_kb),
581+ le16_to_cpu(reserved_block->used_by_driver_in_kb));
582+ if (reserved_block->used_by_firmware_in_kb > 0) {
583+ start_address_in_kb = le32_to_cpu(reserved_block->start_address_in_kb);
584+ offset = (uint64_t)start_address_in_kb * ONE_KiB;
585+ if ((offset & (ONE_MiB - 1)) < (4 * ONE_KiB + 1) ) {
586+ offset -= ONE_MiB;
587+ }
588+
589+ offset &= ~(ONE_MiB - 1);
590+ adev->fw_vram_usage.mem_train_fb_loc = offset;
591+ adev->fw_vram_usage.mem_train_support = true;
592+ DRM_DEBUG("mem_train_fb_loc:0x%09llx.\n", offset);
593+ ret = 0;
594+ } else {
595+ DRM_ERROR("used_by_firmware_in_kb is 0!\n");
596+ ret = -EINVAL;
597+ }
598+
599+ return ret;
600+}
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h+3−2
@@ -29,8 +29,9 @@ · 28 unmodified lines
2929 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev);
3030 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
3131 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
32−int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);
33−int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev);
32+int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
33+ int *vram_width, int *vram_type, int *vram_vendor);
34+int amdgpu_atomfirmware_get_mem_train_fb_loc(struct amdgpu_device *adev);
3435 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
3536 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
3637 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev);
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c+1−11
@@ -613,17 +613,7 @@ static bool amdgpu_atpx_detect(void) · 612 unmodified lines
613613 bool d3_supported = false;
614614 struct pci_dev *parent_pdev;
615615
616− while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
617− vga_count++;
618−
619− has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
620−
621− parent_pdev = pci_upstream_bridge(pdev);
622− d3_supported |= parent_pdev && parent_pdev->bridge_d3;
623− amdgpu_atpx_get_quirks(pdev);
624− }
625−
626− while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
616+ while ((pdev = pci_get_class(PCI_BASE_CLASS_DISPLAY << 16, pdev)) != NULL) {
627617 vga_count++;
628618
629619 has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c+2−4
@@ -33,7 +33,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size, · 32 unmodified lines
3333 {
3434 unsigned long start_jiffies;
3535 unsigned long end_jiffies;
36− struct dma_fence *fence = NULL;
36+ struct dma_fence *fence;
3737 int i, r;
3838
3939 start_jiffies = jiffies;
@@ -44,16 +44,14 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size, · 4 unmodified lines
4444 if (r)
4545 goto exit_do_move;
4646 r = dma_fence_wait(fence, false);
47+ dma_fence_put(fence);
4748 if (r)
4849 goto exit_do_move;
49− dma_fence_put(fence);
5050 }
5151 end_jiffies = jiffies;
5252 r = jiffies_to_msecs(end_jiffies - start_jiffies);
5353
5454 exit_do_move:
55− if (fence)
56− dma_fence_put(fence);
5755 return r;
5856 }
5957
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c+13−8
@@ -140,7 +140,12 @@ int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp, · 139 unmodified lines
140140 return 0;
141141
142142 error_free:
143− while (i--) {
143+ for (i = 0; i < last_entry; ++i) {
144+ struct amdgpu_bo *bo = ttm_to_amdgpu_bo(array[i].tv.bo);
145+
146+ amdgpu_bo_unref(&bo);
147+ }
148+ for (i = first_userptr; i < num_entries; ++i) {
144149 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(array[i].tv.bo);
145150
146151 amdgpu_bo_unref(&bo);
@@ -270,7 +275,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, · 123 unmodified lines
270275
271276 r = amdgpu_bo_create_list_entry_array(&args->in, &info);
272277 if (r)
273− goto error_free;
278+ return r;
274279
275280 switch (args->in.operation) {
276281 case AMDGPU_BO_LIST_OP_CREATE:
@@ -283,8 +288,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, · 6 unmodified lines
283288 r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, GFP_KERNEL);
284289 mutex_unlock(&fpriv->bo_list_lock);
285290 if (r < 0) {
286− amdgpu_bo_list_put(list);
287− return r;
291+ goto error_put_list;
288292 }
289293
290294 handle = r;
@@ -306,9 +310,8 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, · 15 unmodified lines
306310 mutex_unlock(&fpriv->bo_list_lock);
307311
308312 if (IS_ERR(old)) {
309− amdgpu_bo_list_put(list);
310313 r = PTR_ERR(old);
311− goto error_free;
314+ goto error_put_list;
312315 }
313316
314317 amdgpu_bo_list_put(old);
@@ -325,8 +328,10 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, · 10 unmodified lines
325328
326329 return 0;
327330
331+error_put_list:
332+ amdgpu_bo_list_put(list);
333+
328334 error_free:
329− if (info)
330− kvfree(info);
335+ kvfree(info);
331336 return r;
332337 }
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c+11−2
@@ -1019,8 +1019,12 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) · 1018 unmodified lines
10191019 */
10201020 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
10211021 struct drm_connector *list_connector;
1022+ struct drm_connector_list_iter iter;
10221023 struct amdgpu_connector *list_amdgpu_connector;
1023− list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1024+
1025+ drm_connector_list_iter_begin(dev, &iter);
1026+ drm_for_each_connector_iter(list_connector,
1027+ &iter) {
10241028 if (connector == list_connector)
10251029 continue;
10261030 list_amdgpu_connector = to_amdgpu_connector(list_connector);
@@ -1037,6 +1041,7 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) · 10 unmodified lines
10371041 }
10381042 }
10391043 }
1044+ drm_connector_list_iter_end(&iter);
10401045 }
10411046 }
10421047 }
@@ -1494,6 +1499,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, · 451 unmodified lines
14941499 {
14951500 struct drm_device *dev = adev->ddev;
14961501 struct drm_connector *connector;
1502+ struct drm_connector_list_iter iter;
14971503 struct amdgpu_connector *amdgpu_connector;
14981504 struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
14991505 struct drm_encoder *encoder;
@@ -1508,10 +1514,12 @@ amdgpu_connector_add(struct amdgpu_device *adev, · 8 unmodified lines
15081514 return;
15091515
15101516 /* see if we already added it */
1511− list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1517+ drm_connector_list_iter_begin(dev, &iter);
1518+ drm_for_each_connector_iter(connector, &iter) {
15121519 amdgpu_connector = to_amdgpu_connector(connector);
15131520 if (amdgpu_connector->connector_id == connector_id) {
15141521 amdgpu_connector->devices |= supported_device;
1522+ drm_connector_list_iter_end(&iter);
15151523 return;
15161524 }
15171525 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
@@ -1526,6 +1534,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, · 8 unmodified lines
15261534 }
15271535 }
15281536 }
1537+ drm_connector_list_iter_end(&iter);
15291538
15301539 /* check if it's a dp bridge */
15311540 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c+9−78
@@ -35,6 +35,7 @@ · 34 unmodified lines
3535 #include "amdgpu_trace.h"
3636 #include "amdgpu_gmc.h"
3737 #include "amdgpu_gem.h"
38+#include "amdgpu_ras.h"
3839
3940 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
4041 struct drm_amdgpu_cs_chunk_fence *data,
@@ -449,75 +450,12 @@ retry: · 408 unmodified lines
449450 return r;
450451 }
451452
452−/* Last resort, try to evict something from the current working set */
453−static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
454− struct amdgpu_bo *validated)
455−{
456− uint32_t domain = validated->allowed_domains;
457− struct ttm_operation_ctx ctx = { true, false };
458− int r;
459−
460− if (!p->evictable)
461− return false;
462−
463− for (;&p->evictable->tv.head != &p->validated;
464− p->evictable = list_prev_entry(p->evictable, tv.head)) {
465−
466− struct amdgpu_bo_list_entry *candidate = p->evictable;
467− struct amdgpu_bo *bo = ttm_to_amdgpu_bo(candidate->tv.bo);
468− struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
469− bool update_bytes_moved_vis;
470− uint32_t other;
471−
472− /* If we reached our current BO we can forget it */
473− if (bo == validated)
474− break;
475−
476− /* We can't move pinned BOs here */
477− if (bo->pin_count)
478− continue;
479−
480− other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
481−
482− /* Check if this BO is in one of the domains we need space for */
483− if (!(other & domain))
484− continue;
485−
486− /* Check if we can move this BO somewhere else */
487− other = bo->allowed_domains & ~domain;
488− if (!other)
489− continue;
490−
491− /* Good we can try to move this BO somewhere else */
492− update_bytes_moved_vis =
493− !amdgpu_gmc_vram_full_visible(&adev->gmc) &&
494− amdgpu_bo_in_cpu_visible_vram(bo);
495− amdgpu_bo_placement_from_domain(bo, other);
496− r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
497− p->bytes_moved += ctx.bytes_moved;
498− if (update_bytes_moved_vis)
499− p->bytes_moved_vis += ctx.bytes_moved;
500−
501− if (unlikely(r))
502− break;
503−
504− p->evictable = list_prev_entry(p->evictable, tv.head);
505− list_move(&candidate->tv.head, &p->validated);
506−
507− return true;
508− }
509−
510− return false;
511−}
512−
513453 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
514454 {
515455 struct amdgpu_cs_parser *p = param;
516456 int r;
517457
518− do {
519− r = amdgpu_cs_bo_validate(p, bo);
520− } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
458+ r = amdgpu_cs_bo_validate(p, bo);
521459 if (r)
522460 return r;
523461
@@ -536,7 +474,6 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, · 12 unmodified lines
536474
537475 list_for_each_entry(lobj, validated, tv.head) {
538476 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
539− bool binding_userptr = false;
540477 struct mm_struct *usermm;
541478
542479 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
@@ -553,20 +490,14 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, · 10 unmodified lines
553490
554491 amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
555492 lobj->user_pages);
556− binding_userptr = true;
557493 }
558494
559− if (p->evictable == lobj)
560− p->evictable = NULL;
561−
562495 r = amdgpu_cs_validate(p, bo);
563496 if (r)
564497 return r;
565498
566− if (binding_userptr) {
567− kvfree(lobj->user_pages);
568− lobj->user_pages = NULL;
569− }
499+ kvfree(lobj->user_pages);
500+ lobj->user_pages = NULL;
570501 }
571502 return 0;
572503 }
@@ -650,7 +581,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, · 77 unmodified lines
650581 }
651582
652583 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
653− &duplicates, false);
584+ &duplicates);
654585 if (unlikely(r != 0)) {
655586 if (r != -ERESTARTSYS)
656587 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
@@ -661,9 +592,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, · 4 unmodified lines
661592 &p->bytes_moved_vis_threshold);
662593 p->bytes_moved = 0;
663594 p->bytes_moved_vis = 0;
664− p->evictable = list_last_entry(&p->validated,
665− struct amdgpu_bo_list_entry,
666− tv.head);
667595
668596 r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
669597 amdgpu_cs_validate, p);
@@ -915,7 +843,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) · 245 unmodified lines
915843 if (r)
916844 return r;
917845
918− r = amdgpu_vm_update_directories(adev, vm);
846+ r = amdgpu_vm_update_pdes(adev, vm, false);
919847 if (r)
920848 return r;
921849
@@ -1359,6 +1287,9 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) · 437 unmodified lines
13591287 bool reserved_buffers = false;
13601288 int i, r;
13611289
1290+ if (amdgpu_ras_intr_triggered())
1291+ return -EHWPOISON;
1292+
13621293 if (!adev->accel_working)
13631294 return -EBUSY;
13641295
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c+1−1
@@ -80,7 +80,7 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 79 unmodified lines
8080 list_add(&csa_tv.head, &list);
8181 amdgpu_vm_get_pd_bo(vm, &list, &pd);
8282
83− r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL, false);
83+ r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
8484 if (r) {
8585 DRM_ERROR("failed to reserve CSA,PD BOs: err=%d\n", r);
8686 return r;
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c+4−1
@@ -604,8 +604,11 @@ void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr) · 603 unmodified lines
604604 continue;
605605 }
606606
607− for (i = 0; i < num_entities; i++)
607+ for (i = 0; i < num_entities; i++) {
608+ mutex_lock(&ctx->adev->lock_reset);
608609 drm_sched_entity_fini(&ctx->entities[0][i].entity);
610+ mutex_unlock(&ctx->adev->lock_reset);
611+ }
609612 }
610613 }
611614
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c+14−6
@@ -859,6 +859,9 @@ static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) · 858 unmodified lines
859859 struct amdgpu_device *adev = dev->dev_private;
860860 int r = 0, i;
861861
862+ /* Avoid accidently unparking the sched thread during GPU reset */
863+ mutex_lock(&adev->lock_reset);
864+
862865 /* hold on the scheduler */
863866 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
864867 struct amdgpu_ring *ring = adev->rings[i];
@@ -884,6 +887,8 @@ static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) · 19 unmodified lines
884887 kthread_unpark(ring->sched.thread);
885888 }
886889
890+ mutex_unlock(&adev->lock_reset);
891+
887892 return 0;
888893 }
889894
@@ -1036,6 +1041,9 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) · 146 unmodified lines
10361041 if (!fences)
10371042 return -ENOMEM;
10381043
1044+ /* Avoid accidently unparking the sched thread during GPU reset */
1045+ mutex_lock(&adev->lock_reset);
1046+
10391047 /* stop the scheduler */
10401048 kthread_park(ring->sched.thread);
10411049
@@ -1075,10 +1083,11 @@ failure: · 33 unmodified lines
10751083 /* restart the scheduler */
10761084 kthread_unpark(ring->sched.thread);
10771085
1086+ mutex_unlock(&adev->lock_reset);
1087+
10781088 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
10791089
1080− if (fences)
1081− kfree(fences);
1090+ kfree(fences);
10821091
10831092 return 0;
10841093 }
@@ -1090,8 +1099,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) · 5 unmodified lines
10901099 {
10911100 adev->debugfs_preempt =
10921101 debugfs_create_file("amdgpu_preempt_ib", 0600,
1093− adev->ddev->primary->debugfs_root,
1094− (void *)adev, &fops_ib_preempt);
1102+ adev->ddev->primary->debugfs_root, adev,
1103+ &fops_ib_preempt);
10951104 if (!(adev->debugfs_preempt)) {
10961105 DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
10971106 return -EIO;
@@ -1103,8 +1112,7 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) · 5 unmodified lines
11031112
11041113 void amdgpu_debugfs_preempt_cleanup(struct amdgpu_device *adev)
11051114 {
1106− if (adev->debugfs_preempt)
1107− debugfs_remove(adev->debugfs_preempt);
1115+ debugfs_remove(adev->debugfs_preempt);
11081116 }
11091117
11101118 #else
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+255−55
@@ -65,6 +65,8 @@ · 64 unmodified lines
6565 #include "amdgpu_ras.h"
6666 #include "amdgpu_pmu.h"
6767
68+#include <linux/suspend.h>
69+
6870 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
6971 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
7072 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
@@ -78,7 +80,7 @@ MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); · 7 unmodified lines
7880
7981 #define AMDGPU_RESUME_MS 2000
8082
81−static const char *amdgpu_asic_name[] = {
83+const char *amdgpu_asic_name[] = {
8284 "TAHITI",
8385 "PITCAIRN",
8486 "VERDE",
@@ -151,6 +153,36 @@ bool amdgpu_device_is_px(struct drm_device *dev) · 66 unmodified lines
151153 return false;
152154 }
153155
156+/**
157+ * VRAM access helper functions.
158+ *
159+ * amdgpu_device_vram_access - read/write a buffer in vram
160+ *
161+ * @adev: amdgpu_device pointer
162+ * @pos: offset of the buffer in vram
163+ * @buf: virtual address of the buffer in system memory
164+ * @size: read/write size, sizeof(@buf) must > @size
165+ * @write: true - write to vram, otherwise - read from vram
166+ */
167+void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
168+ uint32_t *buf, size_t size, bool write)
169+{
170+ uint64_t last;
171+ unsigned long flags;
172+
173+ last = size - 4;
174+ for (last += pos; pos <= last; pos += 4) {
175+ spin_lock_irqsave(&adev->mmio_idx_lock, flags);
176+ WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
177+ WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
178+ if (write)
179+ WREG32_NO_KIQ(mmMM_DATA, *buf++);
180+ else
181+ *buf++ = RREG32_NO_KIQ(mmMM_DATA);
182+ spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
183+ }
184+}
185+
154186 /*
155187 * MMIO register access helper functions.
156188 */
@@ -1023,12 +1055,6 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev) · 866 unmodified lines
10231055
10241056 amdgpu_device_check_block_size(adev);
10251057
1026− ret = amdgpu_device_get_job_timeout_settings(adev);
1027− if (ret) {
1028− dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
1029− return ret;
1030− }
1031−
10321058 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
10331059
10341060 return ret;
@@ -1469,6 +1495,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) · 434 unmodified lines
14691495 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
14701496 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
14711497
1498+ if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
1499+ goto parse_soc_bounding_box;
1500+
14721501 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
14731502 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
14741503 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
@@ -1496,7 +1525,13 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) · 21 unmodified lines
14961525 adev->gfx.config.num_packer_per_sc =
14971526 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
14981527 }
1528+
1529+parse_soc_bounding_box:
14991530 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
1531+ /*
1532+ * soc bounding box info is not integrated in disocovery table,
1533+ * we always need to parse it from gpu info firmware.
1534+ */
15001535 if (hdr->version_minor == 2) {
15011536 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
15021537 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
@@ -1613,6 +1648,9 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) · 110 unmodified lines
16131648 if (r)
16141649 return r;
16151650
1651+ if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
1652+ amdgpu_discovery_get_gfx_info(adev);
1653+
16161654 amdgpu_amdkfd_device_probe(adev);
16171655
16181656 if (amdgpu_sriov_vf(adev)) {
@@ -1622,7 +1660,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) · 3 unmodified lines
16221660 }
16231661
16241662 adev->pm.pp_feature = amdgpu_pp_feature_mask;
1625− if (amdgpu_sriov_vf(adev))
1663+ if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
16261664 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
16271665
16281666 for (i = 0; i < adev->num_ip_blocks; i++) {
@@ -1839,6 +1877,19 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) · 210 unmodified lines
18391877 if (r)
18401878 goto init_failed;
18411879
1880+ /*
1881+ * retired pages will be loaded from eeprom and reserved here,
1882+ * it should be called after amdgpu_device_ip_hw_init_phase2 since
1883+ * for some ASICs the RAS EEPROM code relies on SMU fully functioning
1884+ * for I2C communication which only true at this point.
1885+ * recovery_init may fail, but it can free all resources allocated by
1886+ * itself and its failure should not stop amdgpu init process.
1887+ *
1888+ * Note: theoretically, this should be called before all vram allocations
1889+ * to protect retired page from abusing
1890+ */
1891+ amdgpu_ras_recovery_init(adev);
1892+
18421893 if (adev->gmc.xgmi.num_physical_nodes > 1)
18431894 amdgpu_xgmi_add_device(adev);
18441895 amdgpu_amdkfd_device_init(adev);
@@ -2006,6 +2057,7 @@ out: · 161 unmodified lines
20062057 */
20072058 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
20082059 {
2060+ struct amdgpu_gpu_instance *gpu_instance;
20092061 int i = 0, r;
20102062
20112063 for (i = 0; i < adev->num_ip_blocks; i++) {
@@ -2031,8 +2083,39 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) · 19 unmodified lines
20312083 if (r)
20322084 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
20332085
2034− /* set to low pstate by default */
2035− amdgpu_xgmi_set_pstate(adev, 0);
2086+
2087+ if (adev->gmc.xgmi.num_physical_nodes > 1) {
2088+ mutex_lock(&mgpu_info.mutex);
2089+
2090+ /*
2091+ * Reset device p-state to low as this was booted with high.
2092+ *
2093+ * This should be performed only after all devices from the same
2094+ * hive get initialized.
2095+ *
2096+ * However, it's unknown how many device in the hive in advance.
2097+ * As this is counted one by one during devices initializations.
2098+ *
2099+ * So, we wait for all XGMI interlinked devices initialized.
2100+ * This may bring some delays as those devices may come from
2101+ * different hives. But that should be OK.
2102+ */
2103+ if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2104+ for (i = 0; i < mgpu_info.num_gpu; i++) {
2105+ gpu_instance = &(mgpu_info.gpu_ins[i]);
2106+ if (gpu_instance->adev->flags & AMD_IS_APU)
2107+ continue;
2108+
2109+ r = amdgpu_xgmi_set_pstate(gpu_instance->adev, 0);
2110+ if (r) {
2111+ DRM_ERROR("pstate setting failed (%d).\n", r);
2112+ break;
2113+ }
2114+ }
2115+ }
2116+
2117+ mutex_unlock(&mgpu_info.mutex);
2118+ }
20362119
20372120 return 0;
20382121 }
@@ -2220,6 +2303,12 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) · 181 unmodified lines
22202303 /* displays are handled in phase1 */
22212304 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
22222305 continue;
2306+ /* PSP lost connection when err_event_athub occurs */
2307+ if (amdgpu_ras_intr_triggered() &&
2308+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2309+ adev->ip_blocks[i].status.hw = false;
2310+ continue;
2311+ }
22232312 /* XXX handle errors */
22242313 r = adev->ip_blocks[i].version->funcs->suspend(adev);
22252314 /* XXX handle errors */
@@ -2231,17 +2320,17 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) · 5 unmodified lines
22312320 /* handle putting the SMC in the appropriate state */
22322321 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
22332322 if (is_support_sw_smu(adev)) {
2234− /* todo */
2323+ r = smu_set_mp1_state(&adev->smu, adev->mp1_state);
22352324 } else if (adev->powerplay.pp_funcs &&
22362325 adev->powerplay.pp_funcs->set_mp1_state) {
22372326 r = adev->powerplay.pp_funcs->set_mp1_state(
22382327 adev->powerplay.pp_handle,
22392328 adev->mp1_state);
2240− if (r) {
2241− DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2242− adev->mp1_state, r);
2243− return r;
2244− }
2329+ }
2330+ if (r) {
2331+ DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2332+ adev->mp1_state, r);
2333+ return r;
22452334 }
22462335 }
22472336
@@ -2556,6 +2645,73 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) · 308 unmodified lines
25562645 adev->asic_reset_res, adev->ddev->unique);
25572646 }
25582647
2648+static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
2649+{
2650+ char *input = amdgpu_lockup_timeout;
2651+ char *timeout_setting = NULL;
2652+ int index = 0;
2653+ long timeout;
2654+ int ret = 0;
2655+
2656+ /*
2657+ * By default timeout for non compute jobs is 10000.
2658+ * And there is no timeout enforced on compute jobs.
2659+ * In SR-IOV or passthrough mode, timeout for compute
2660+ * jobs are 10000 by default.
2661+ */
2662+ adev->gfx_timeout = msecs_to_jiffies(10000);
2663+ adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
2664+ if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
2665+ adev->compute_timeout = adev->gfx_timeout;
2666+ else
2667+ adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
2668+
2669+ if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
2670+ while ((timeout_setting = strsep(&input, ",")) &&
2671+ strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
2672+ ret = kstrtol(timeout_setting, 0, &timeout);
2673+ if (ret)
2674+ return ret;
2675+
2676+ if (timeout == 0) {
2677+ index++;
2678+ continue;
2679+ } else if (timeout < 0) {
2680+ timeout = MAX_SCHEDULE_TIMEOUT;
2681+ } else {
2682+ timeout = msecs_to_jiffies(timeout);
2683+ }
2684+
2685+ switch (index++) {
2686+ case 0:
2687+ adev->gfx_timeout = timeout;
2688+ break;
2689+ case 1:
2690+ adev->compute_timeout = timeout;
2691+ break;
2692+ case 2:
2693+ adev->sdma_timeout = timeout;
2694+ break;
2695+ case 3:
2696+ adev->video_timeout = timeout;
2697+ break;
2698+ default:
2699+ break;
2700+ }
2701+ }
2702+ /*
2703+ * There is only one value specified and
2704+ * it should apply to all non-compute jobs.
2705+ */
2706+ if (index == 1) {
2707+ adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
2708+ if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
2709+ adev->compute_timeout = adev->gfx_timeout;
2710+ }
2711+ }
2712+
2713+ return ret;
2714+}
25592715
25602716 /**
25612717 * amdgpu_device_init - initialize the driver
@@ -2583,7 +2739,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 21 unmodified lines
25832739 adev->ddev = ddev;
25842740 adev->pdev = pdev;
25852741 adev->flags = flags;
2586− adev->asic_type = flags & AMD_ASIC_MASK;
2742+
2743+ if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
2744+ adev->asic_type = amdgpu_force_asic_type;
2745+ else
2746+ adev->asic_type = flags & AMD_ASIC_MASK;
2747+
25872748 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
25882749 if (amdgpu_emu_mode == 1)
25892750 adev->usec_timeout *= 2;
@@ -2726,6 +2887,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 136 unmodified lines
27262887 if (r)
27272888 return r;
27282889
2890+ r = amdgpu_device_get_job_timeout_settings(adev);
2891+ if (r) {
2892+ dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
2893+ return r;
2894+ }
2895+
27292896 /* doorbell bar mapping and doorbell index init*/
27302897 amdgpu_device_doorbell_init(adev);
27312898
@@ -2885,6 +3052,13 @@ fence_driver_init: · 153 unmodified lines
28853052 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
28863053 }
28873054
3055+ /*
3056+ * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3057+ * Otherwise the mgpu fan boost feature will be skipped due to the
3058+ * gpu instance is counted less.
3059+ */
3060+ amdgpu_register_gpu_instance(adev);
3061+
28883062 /* enable clockgating, etc. after ib tests, etc. since some blocks require
28893063 * explicit gating rather than handling it automatically.
28903064 */
@@ -3007,6 +3181,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) · 116 unmodified lines
30073181 struct amdgpu_device *adev;
30083182 struct drm_crtc *crtc;
30093183 struct drm_connector *connector;
3184+ struct drm_connector_list_iter iter;
30103185 int r;
30113186
30123187 if (dev == NULL || dev->dev_private == NULL) {
@@ -3029,9 +3204,11 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) · 16 unmodified lines
30293204 if (!amdgpu_device_has_dc_support(adev)) {
30303205 /* turn off display hw */
30313206 drm_modeset_lock_all(dev);
3032− list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3033− drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
3034− }
3207+ drm_connector_list_iter_begin(dev, &iter);
3208+ drm_for_each_connector_iter(connector, &iter)
3209+ drm_helper_connector_dpms(connector,
3210+ DRM_MODE_DPMS_OFF);
3211+ drm_connector_list_iter_end(&iter);
30353212 drm_modeset_unlock_all(dev);
30363213 /* unpin the front buffers and cursors */
30373214 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
@@ -3082,15 +3259,11 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) · 44 unmodified lines
30823259 */
30833260 amdgpu_bo_evict_vram(adev);
30843261
3085− pci_save_state(dev->pdev);
30863262 if (suspend) {
3263+ pci_save_state(dev->pdev);
30873264 /* Shut down the device */
30883265 pci_disable_device(dev->pdev);
30893266 pci_set_power_state(dev->pdev, PCI_D3hot);
3090− } else {
3091− r = amdgpu_asic_reset(adev);
3092− if (r)
3093− DRM_ERROR("amdgpu asic reset failed\n");
30943267 }
30953268
30963269 return 0;
@@ -3110,6 +3283,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) · 13 unmodified lines
31103283 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
31113284 {
31123285 struct drm_connector *connector;
3286+ struct drm_connector_list_iter iter;
31133287 struct amdgpu_device *adev = dev->dev_private;
31143288 struct drm_crtc *crtc;
31153289 int r = 0;
@@ -3180,9 +3354,13 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) · 64 unmodified lines
31803354
31813355 /* turn on display hw */
31823356 drm_modeset_lock_all(dev);
3183− list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3184− drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
3185− }
3357+
3358+ drm_connector_list_iter_begin(dev, &iter);
3359+ drm_for_each_connector_iter(connector, &iter)
3360+ drm_helper_connector_dpms(connector,
3361+ DRM_MODE_DPMS_ON);
3362+ drm_connector_list_iter_end(&iter);
3363+
31863364 drm_modeset_unlock_all(dev);
31873365 }
31883366 amdgpu_fbdev_set_suspend(adev, 0);
@@ -3628,11 +3806,6 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, · 439 unmodified lines
36283806 break;
36293807 }
36303808 }
3631−
3632− list_for_each_entry(tmp_adev, device_list_handle,
3633− gmc.xgmi.head) {
3634− amdgpu_ras_reserve_bad_pages(tmp_adev);
3635− }
36363809 }
36373810 }
36383811
@@ -3736,25 +3909,18 @@ static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock) · 97 unmodified lines
37363909 adev->mp1_state = PP_MP1_STATE_NONE;
37373910 break;
37383911 }
3739− /* Block kfd: SRIOV would do it separately */
3740− if (!amdgpu_sriov_vf(adev))
3741− amdgpu_amdkfd_pre_reset(adev);
37423912
37433913 return true;
37443914 }
37453915
37463916 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
37473917 {
3748− /*unlock kfd: SRIOV would do it separately */
3749− if (!amdgpu_sriov_vf(adev))
3750− amdgpu_amdkfd_post_reset(adev);
37513918 amdgpu_vf_error_trans_all(adev);
37523919 adev->mp1_state = PP_MP1_STATE_NONE;
37533920 adev->in_gpu_reset = 0;
37543921 mutex_unlock(&adev->lock_reset);
37553922 }
37563923
3757−
37583924 /**
37593925 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
37603926 *
@@ -3774,11 +3940,24 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 13 unmodified lines
37743940 struct amdgpu_hive_info *hive = NULL;
37753941 struct amdgpu_device *tmp_adev = NULL;
37763942 int i, r = 0;
3943+ bool in_ras_intr = amdgpu_ras_intr_triggered();
3944+
3945+ /*
3946+ * Flush RAM to disk so that after reboot
3947+ * the user can read log and see why the system rebooted.
3948+ */
3949+ if (in_ras_intr && amdgpu_ras_get_context(adev)->reboot) {
3950+
3951+ DRM_WARN("Emergency reboot.");
3952+
3953+ ksys_sync_helper();
3954+ emergency_restart();
3955+ }
37773956
37783957 need_full_reset = job_signaled = false;
37793958 INIT_LIST_HEAD(&device_list);
37803959
3781− dev_info(adev->dev, "GPU reset begin!\n");
3960+ dev_info(adev->dev, "GPU %s begin!\n", in_ras_intr ? "jobs stop":"reset");
37823961
37833962 cancel_delayed_work_sync(&adev->delayed_init_work);
37843963
@@ -3805,9 +3984,16 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 20 unmodified lines
38053984 return 0;
38063985 }
38073986
3987+ /* Block kfd: SRIOV would do it separately */
3988+ if (!amdgpu_sriov_vf(adev))
3989+ amdgpu_amdkfd_pre_reset(adev);
3990+
38083991 /* Build list of devices to reset */
38093992 if (adev->gmc.xgmi.num_physical_nodes > 1) {
38103993 if (!hive) {
3994+ /*unlock kfd: SRIOV would do it separately */
3995+ if (!amdgpu_sriov_vf(adev))
3996+ amdgpu_amdkfd_post_reset(adev);
38113997 amdgpu_device_unlock_adev(adev);
38123998 return -ENODEV;
38133999 }
@@ -3823,17 +4009,22 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 9 unmodified lines
38234009 device_list_handle = &device_list;
38244010 }
38254011
3826− /*
3827− * Mark these ASICs to be reseted as untracked first
3828− * And add them back after reset completed
3829− */
3830− list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head)
3831− amdgpu_unregister_gpu_instance(tmp_adev);
3832−
38334012 /* block all schedulers and reset given job's ring */
38344013 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4014+ if (tmp_adev != adev) {
4015+ amdgpu_device_lock_adev(tmp_adev, false);
4016+ if (!amdgpu_sriov_vf(tmp_adev))
4017+ amdgpu_amdkfd_pre_reset(tmp_adev);
4018+ }
4019+
4020+ /*
4021+ * Mark these ASICs to be reseted as untracked first
4022+ * And add them back after reset completed
4023+ */
4024+ amdgpu_unregister_gpu_instance(tmp_adev);
4025+
38354026 /* disable ras on ALL IPs */
3836− if (amdgpu_device_ip_need_full_reset(tmp_adev))
4027+ if (!in_ras_intr && amdgpu_device_ip_need_full_reset(tmp_adev))
38374028 amdgpu_ras_suspend(tmp_adev);
38384029
38394030 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
@@ -3843,10 +4034,16 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 3 unmodified lines
38434034 continue;
38444035
38454036 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
4037+
4038+ if (in_ras_intr)
4039+ amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
38464040 }
38474041 }
38484042
38494043
4044+ if (in_ras_intr)
4045+ goto skip_sched_resume;
4046+
38504047 /*
38514048 * Must check guilty signal here since after this point all old
38524049 * HW fences are force signaled.
@@ -3857,9 +4054,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 4 unmodified lines
38574054 dma_fence_is_signaled(job->base.s_fence->parent))
38584055 job_signaled = true;
38594056
3860− if (!amdgpu_device_ip_need_full_reset(adev))
3861− device_list_handle = &device_list;
3862−
38634057 if (job_signaled) {
38644058 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
38654059 goto skip_hw_reset;
@@ -3881,7 +4075,6 @@ retry: /* Rest of adevs pre asic reset from XGMI hive. */ · 15 unmodified lines
38814075 if (tmp_adev == adev)
38824076 continue;
38834077
3884− amdgpu_device_lock_adev(tmp_adev, false);
38854078 r = amdgpu_device_pre_asic_reset(tmp_adev,
38864079 NULL,
38874080 &need_full_reset);
@@ -3909,6 +4102,7 @@ skip_hw_reset: · 21 unmodified lines
39094102
39104103 /* Post ASIC reset for all devs .*/
39114104 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4105+
39124106 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
39134107 struct amdgpu_ring *ring = tmp_adev->rings[i];
39144108
@@ -3930,12 +4124,18 @@ skip_hw_reset: · 15 unmodified lines
39304124
39314125 if (r) {
39324126 /* bad news, how to tell it to userspace ? */
3933− dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
4127+ dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
39344128 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
39354129 } else {
3936− dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter));
4130+ dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
39374131 }
4132+ }
39384133
4134+skip_sched_resume:
4135+ list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4136+ /*unlock kfd: SRIOV would do it separately */
4137+ if (!in_ras_intr && !amdgpu_sriov_vf(tmp_adev))
4138+ amdgpu_amdkfd_post_reset(tmp_adev);
39394139 amdgpu_device_unlock_adev(tmp_adev);
39404140 }
39414141
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c+6−14
@@ -134,20 +134,10 @@ static int hw_id_map[MAX_HWIP] = { · 133 unmodified lines
134134
135135 static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary)
136136 {
137− uint32_t *p = (uint32_t *)binary;
138137 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
139− uint64_t pos = vram_size - BINARY_MAX_SIZE;
140− unsigned long flags;
141−
142− while (pos < vram_size) {
143− spin_lock_irqsave(&adev->mmio_idx_lock, flags);
144− WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
145− WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
146− *p++ = RREG32_NO_KIQ(mmMM_DATA);
147− spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
148− pos += 4;
149− }
138+ uint64_t pos = vram_size - DISCOVERY_TMR_SIZE;
150139
140+ amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, DISCOVERY_TMR_SIZE, false);
151141 return 0;
152142 }
153143
@@ -179,7 +169,7 @@ int amdgpu_discovery_init(struct amdgpu_device *adev) · 25 unmodified lines
179169 uint16_t checksum;
180170 int r;
181171
182− adev->discovery = kzalloc(BINARY_MAX_SIZE, GFP_KERNEL);
172+ adev->discovery = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL);
183173 if (!adev->discovery)
184174 return -ENOMEM;
185175
@@ -333,7 +323,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) · 147 unmodified lines
333323 }
334324
335325 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
336− int *major, int *minor)
326+ int *major, int *minor, int *revision)
337327 {
338328 struct binary_header *bhdr;
339329 struct ip_discovery_header *ihdr;
@@ -369,6 +359,8 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, · 29 unmodified lines
369359 *major = ip->major;
370360 if (minor)
371361 *minor = ip->minor;
362+ if (revision)
363+ *revision = ip->revision;
372364 return 0;
373365 }
374366 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h+3−1
@@ -24,11 +24,13 @@ · 23 unmodified lines
2424 #ifndef __AMDGPU_DISCOVERY__
2525 #define __AMDGPU_DISCOVERY__
2626
27+#define DISCOVERY_TMR_SIZE (64 << 10)
28+
2729 int amdgpu_discovery_init(struct amdgpu_device *adev);
2830 void amdgpu_discovery_fini(struct amdgpu_device *adev);
2931 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
3032 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
31− int *major, int *minor);
33+ int *major, int *minor, int *revision);
3234 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);
3335
3436 #endif /* __AMDGPU_DISCOVERY__ */
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c+4−1
@@ -370,11 +370,13 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) · 369 unmodified lines
370370 struct amdgpu_connector *amdgpu_connector;
371371 struct drm_encoder *encoder;
372372 struct amdgpu_encoder *amdgpu_encoder;
373+ struct drm_connector_list_iter iter;
373374 uint32_t devices;
374375 int i = 0;
375376
377+ drm_connector_list_iter_begin(dev, &iter);
376378 DRM_INFO("AMDGPU Display Connectors\n");
377− list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
379+ drm_for_each_connector_iter(connector, &iter) {
378380 amdgpu_connector = to_amdgpu_connector(connector);
379381 DRM_INFO("Connector %d:\n", i);
380382 DRM_INFO(" %s\n", connector->name);
@@ -438,6 +440,7 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) · 57 unmodified lines
438440 }
439441 i++;
440442 }
443+ drm_connector_list_iter_end(&iter);
441444 }
442445
443446 /**
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c+121−95
@@ -34,26 +34,11 @@ · 33 unmodified lines
3434 #include "amdgpu.h"
3535 #include "amdgpu_display.h"
3636 #include "amdgpu_gem.h"
37+#include "amdgpu_dma_buf.h"
3738 #include <drm/amdgpu_drm.h>
3839 #include <linux/dma-buf.h>
3940 #include <linux/dma-fence-array.h>
4041
41−/**
42− * amdgpu_gem_prime_get_sg_table - &drm_driver.gem_prime_get_sg_table
43− * implementation
44− * @obj: GEM buffer object (BO)
45− *
46− * Returns:
47− * A scatter/gather table for the pinned pages of the BO's memory.
48− */
49−struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj)
50−{
51− struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
52− int npages = bo->tbo.num_pages;
53−
54− return drm_prime_pages_to_sg(bo->tbo.ttm->pages, npages);
55−}
56−
5742 /**
5843 * amdgpu_gem_prime_vmap - &dma_buf_ops.vmap implementation
5944 * @obj: GEM BO
@@ -179,92 +164,126 @@ err_fences_put: · 119 unmodified lines
179164 }
180165
181166 /**
182− * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation
183− * @dma_buf: Shared DMA buffer
167+ * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
168+ *
169+ * @dmabuf: DMA-buf where we attach to
170+ * @attach: attachment to add
171+ *
172+ * Add the attachment as user to the exported DMA-buf.
173+ */
174+static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
175+ struct dma_buf_attachment *attach)
176+{
177+ struct drm_gem_object *obj = dmabuf->priv;
178+ struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
179+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
180+ int r;
181+
182+ if (attach->dev->driver == adev->dev->driver)
183+ return 0;
184+
185+ r = amdgpu_bo_reserve(bo, false);
186+ if (unlikely(r != 0))
187+ return r;
188+
189+ /*
190+ * We only create shared fences for internal use, but importers
191+ * of the dmabuf rely on exclusive fences for implicitly
192+ * tracking write hazards. As any of the current fences may
193+ * correspond to a write, we need to convert all existing
194+ * fences on the reservation object into a single exclusive
195+ * fence.
196+ */
197+ r = __dma_resv_make_exclusive(bo->tbo.base.resv);
198+ if (r)
199+ return r;
200+
201+ bo->prime_shared_count++;
202+ amdgpu_bo_unreserve(bo);
203+ return 0;
204+}
205+
206+/**
207+ * amdgpu_dma_buf_detach - &dma_buf_ops.detach implementation
208+ *
209+ * @dmabuf: DMA-buf where we remove the attachment from
210+ * @attach: the attachment to remove
211+ *
212+ * Called when an attachment is removed from the DMA-buf.
213+ */
214+static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,
215+ struct dma_buf_attachment *attach)
216+{
217+ struct drm_gem_object *obj = dmabuf->priv;
218+ struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
219+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
220+
221+ if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count)
222+ bo->prime_shared_count--;
223+}
224+
225+/**
226+ * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
184227 * @attach: DMA-buf attachment
228+ * @dir: DMA direction
185229 *
186230 * Makes sure that the shared DMA buffer can be accessed by the target device.
187231 * For now, simply pins it to the GTT domain, where it should be accessible by
188232 * all DMA devices.
189233 *
190234 * Returns:
191− * 0 on success or a negative error code on failure.
235+ * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
236+ * code.
192237 */
193−static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf,
194− struct dma_buf_attachment *attach)
238+static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
239+ enum dma_data_direction dir)
195240 {
241+ struct dma_buf *dma_buf = attach->dmabuf;
196242 struct drm_gem_object *obj = dma_buf->priv;
197243 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
198− struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
244+ struct sg_table *sgt;
199245 long r;
200246
201− r = drm_gem_map_attach(dma_buf, attach);
202− if (r)
203− return r;
204−
205− r = amdgpu_bo_reserve(bo, false);
206− if (unlikely(r != 0))
207− goto error_detach;
208−
209−
210− if (attach->dev->driver != adev->dev->driver) {
211− /*
212− * We only create shared fences for internal use, but importers
213− * of the dmabuf rely on exclusive fences for implicitly
214− * tracking write hazards. As any of the current fences may
215− * correspond to a write, we need to convert all existing
216− * fences on the reservation object into a single exclusive
217− * fence.
218− */
219− r = __dma_resv_make_exclusive(bo->tbo.base.resv);
220− if (r)
221− goto error_unreserve;
222− }
223−
224− /* pin buffer into GTT */
225247 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
226248 if (r)
227− goto error_unreserve;
249+ return ERR_PTR(r);
228250
229− if (attach->dev->driver != adev->dev->driver)
230− bo->prime_shared_count++;
251+ sgt = drm_prime_pages_to_sg(bo->tbo.ttm->pages, bo->tbo.num_pages);
252+ if (IS_ERR(sgt))
253+ return sgt;
231254
232−error_unreserve:
233− amdgpu_bo_unreserve(bo);
255+ if (!dma_map_sg_attrs(attach->dev, sgt->sgl, sgt->nents, dir,
256+ DMA_ATTR_SKIP_CPU_SYNC))
257+ goto error_free;
234258
235−error_detach:
236− if (r)
237− drm_gem_map_detach(dma_buf, attach);
238− return r;
259+ return sgt;
260+
261+error_free:
262+ sg_free_table(sgt);
263+ kfree(sgt);
264+ return ERR_PTR(-ENOMEM);
239265 }
240266
241267 /**
242− * amdgpu_dma_buf_map_detach - &dma_buf_ops.detach implementation
243− * @dma_buf: Shared DMA buffer
268+ * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
244269 * @attach: DMA-buf attachment
270+ * @sgt: sg_table to unmap
271+ * @dir: DMA direction
245272 *
246273 * This is called when a shared DMA buffer no longer needs to be accessible by
247274 * another device. For now, simply unpins the buffer from GTT.
248275 */
249−static void amdgpu_dma_buf_map_detach(struct dma_buf *dma_buf,
250− struct dma_buf_attachment *attach)
276+static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
277+ struct sg_table *sgt,
278+ enum dma_data_direction dir)
251279 {
252− struct drm_gem_object *obj = dma_buf->priv;
280+ struct drm_gem_object *obj = attach->dmabuf->priv;
253281 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
254− struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
255− int ret = 0;
256−
257− ret = amdgpu_bo_reserve(bo, true);
258− if (unlikely(ret != 0))
259− goto error;
260282
283+ dma_unmap_sg(attach->dev, sgt->sgl, sgt->nents, dir);
284+ sg_free_table(sgt);
285+ kfree(sgt);
261286 amdgpu_bo_unpin(bo);
262− if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count)
263− bo->prime_shared_count--;
264− amdgpu_bo_unreserve(bo);
265−
266−error:
267− drm_gem_map_detach(dma_buf, attach);
268287 }
269288
270289 /**
@@ -308,10 +327,11 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, · 37 unmodified lines
308327 }
309328
310329 const struct dma_buf_ops amdgpu_dmabuf_ops = {
311− .attach = amdgpu_dma_buf_map_attach,
312− .detach = amdgpu_dma_buf_map_detach,
313− .map_dma_buf = drm_gem_map_dma_buf,
314− .unmap_dma_buf = drm_gem_unmap_dma_buf,
330+ .dynamic_mapping = true,
331+ .attach = amdgpu_dma_buf_attach,
332+ .detach = amdgpu_dma_buf_detach,
333+ .map_dma_buf = amdgpu_dma_buf_map,
334+ .unmap_dma_buf = amdgpu_dma_buf_unmap,
315335 .release = drm_gem_dmabuf_release,
316336 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
317337 .mmap = drm_gem_dmabuf_mmap,
@@ -321,7 +341,6 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { · 3 unmodified lines
321341
322342 /**
323343 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
324− * @dev: DRM device
325344 * @gobj: GEM BO
326345 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
327346 *
@@ -350,31 +369,28 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, · 22 unmodified lines
350369 }
351370
352371 /**
353− * amdgpu_gem_prime_import_sg_table - &drm_driver.gem_prime_import_sg_table
354− * implementation
372+ * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
373+ *
355374 * @dev: DRM device
356− * @attach: DMA-buf attachment
357− * @sg: Scatter/gather table
375+ * @dma_buf: DMA-buf
358376 *
359− * Imports shared DMA buffer memory exported by another device.
377+ * Creates an empty SG BO for DMA-buf import.
360378 *
361379 * Returns:
362380 * A new GEM BO of the given DRM device, representing the memory
363381 * described by the given DMA-buf attachment and scatter/gather table.
364382 */
365−struct drm_gem_object *
366−amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
367− struct dma_buf_attachment *attach,
368− struct sg_table *sg)
383+static struct drm_gem_object *
384+amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
369385 {
370− struct dma_resv *resv = attach->dmabuf->resv;
386+ struct dma_resv *resv = dma_buf->resv;
371387 struct amdgpu_device *adev = dev->dev_private;
372388 struct amdgpu_bo *bo;
373389 struct amdgpu_bo_param bp;
374390 int ret;
375391
376392 memset(&bp, 0, sizeof(bp));
377− bp.size = attach->dmabuf->size;
393+ bp.size = dma_buf->size;
378394 bp.byte_align = PAGE_SIZE;
379395 bp.domain = AMDGPU_GEM_DOMAIN_CPU;
380396 bp.flags = 0;
@@ -385,11 +401,9 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, · 4 unmodified lines
385401 if (ret)
386402 goto error;
387403
388− bo->tbo.sg = sg;
389− bo->tbo.ttm->sg = sg;
390404 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
391405 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
392− if (attach->dmabuf->ops != &amdgpu_dmabuf_ops)
406+ if (dma_buf->ops != &amdgpu_dmabuf_ops)
393407 bo->prime_shared_count = 1;
394408
395409 dma_resv_unlock(resv);
@@ -405,15 +419,15 @@ error: · 9 unmodified lines
405419 * @dev: DRM device
406420 * @dma_buf: Shared DMA buffer
407421 *
408− * The main work is done by the &drm_gem_prime_import helper, which in turn
409− * uses &amdgpu_gem_prime_import_sg_table.
422+ * Import a dma_buf into a the driver and potentially create a new GEM object.
410423 *
411424 * Returns:
412425 * GEM BO representing the shared DMA buffer for the given device.
413426 */
414427 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
415− struct dma_buf *dma_buf)
428+ struct dma_buf *dma_buf)
416429 {
430+ struct dma_buf_attachment *attach;
417431 struct drm_gem_object *obj;
418432
419433 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
@@ -428,5 +442,17 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, · 8 unmodified lines
428442 }
429443 }
430444
431− return drm_gem_prime_import(dev, dma_buf);
445+ obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
446+ if (IS_ERR(obj))
447+ return obj;
448+
449+ attach = dma_buf_dynamic_attach(dma_buf, dev->dev, true);
450+ if (IS_ERR(attach)) {
451+ drm_gem_object_put(obj);
452+ return ERR_CAST(attach);
453+ }
454+
455+ get_dma_buf(dma_buf);
456+ obj->import_attach = attach;
457+ return obj;
432458 }
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h+0−5
@@ -25,11 +25,6 @@ · 24 unmodified lines
2525
2626 #include <drm/drm_gem.h>
2727
28−struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
29−struct drm_gem_object *
30−amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
31− struct dma_buf_attachment *attach,
32− struct sg_table *sg);
3328 struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
3429 int flags);
3530 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c+4−2
@@ -911,7 +911,8 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) · 910 unmodified lines
911911 if (is_support_sw_smu(adev)) {
912912 ret = smu_get_dpm_freq_range(&adev->smu, SMU_GFXCLK,
913913 low ? &clk_freq : NULL,
914− !low ? &clk_freq : NULL);
914+ !low ? &clk_freq : NULL,
915+ true);
915916 if (ret)
916917 return 0;
917918 return clk_freq * 100;
@@ -928,7 +929,8 @@ int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) · 10 unmodified lines
928929 if (is_support_sw_smu(adev)) {
929930 ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK,
930931 low ? &clk_freq : NULL,
931− !low ? &clk_freq : NULL);
932+ !low ? &clk_freq : NULL,
933+ true);
932934 if (ret)
933935 return 0;
934936 return clk_freq * 100;
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h+0−6
@@ -298,12 +298,6 @@ enum amdgpu_pcie_gen { · 297 unmodified lines
298298 #define amdgpu_dpm_get_current_power_state(adev) \
299299 ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
300300
301−#define amdgpu_smu_get_current_power_state(adev) \
302− ((adev)->smu.ppt_funcs->get_current_power_state(&((adev)->smu)))
303−
304−#define amdgpu_smu_set_power_state(adev) \
305− ((adev)->smu.ppt_funcs->set_power_state(&((adev)->smu)))
306−
307301 #define amdgpu_dpm_get_pp_num_states(adev, data) \
308302 ((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
309303
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+87−116
@@ -43,6 +43,8 @@ · 42 unmodified lines
4343
4444 #include "amdgpu_amdkfd.h"
4545
46+#include "amdgpu_ras.h"
47+
4648 /*
4749 * KMS wrapper.
4850 * - 3.0.0 - initial driver
@@ -82,13 +84,12 @@ · 33 unmodified lines
8284 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
8385 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
8486 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
87+ * - 3.36.0 - Allow reading more status registers on si/cik
8588 */
8689 #define KMS_DRIVER_MAJOR 3
87−#define KMS_DRIVER_MINOR 35
90+#define KMS_DRIVER_MINOR 36
8891 #define KMS_DRIVER_PATCHLEVEL 0
8992
90−#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
91−
9293 int amdgpu_vram_limit = 0;
9394 int amdgpu_vis_vram_limit = 0;
9495 int amdgpu_gart_size = -1; /* auto */
@@ -101,7 +102,7 @@ int amdgpu_disp_priority = 0; · 6 unmodified lines
101102 int amdgpu_hw_i2c = 0;
102103 int amdgpu_pcie_gen2 = -1;
103104 int amdgpu_msi = -1;
104−char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH];
105+char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
105106 int amdgpu_dpm = -1;
106107 int amdgpu_fw_load_type = -1;
107108 int amdgpu_aspm = -1;
@@ -128,11 +129,7 @@ char *amdgpu_disable_cu = NULL; · 20 unmodified lines
128129 char *amdgpu_virtual_display = NULL;
129130 /* OverDrive(bit 14) disabled by default*/
130131 uint amdgpu_pp_feature_mask = 0xffffbfff;
131−int amdgpu_ngg = 0;
132−int amdgpu_prim_buf_per_se = 0;
133−int amdgpu_pos_buf_per_se = 0;
134−int amdgpu_cntl_sb_buf_per_se = 0;
135−int amdgpu_param_buf_per_se = 0;
132+uint amdgpu_force_long_training = 0;
136133 int amdgpu_job_hang_limit = 0;
137134 int amdgpu_lbpw = -1;
138135 int amdgpu_compute_multipipe = -1;
@@ -146,12 +143,13 @@ int amdgpu_mcbp = 0; · 7 unmodified lines
146143 int amdgpu_discovery = -1;
147144 int amdgpu_mes = 0;
148145 int amdgpu_noretry = 1;
146+int amdgpu_force_asic_type = -1;
149147
150148 struct amdgpu_mgpu_info mgpu_info = {
151149 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
152150 };
153151 int amdgpu_ras_enable = -1;
154−uint amdgpu_ras_mask = 0xfffffffb;
152+uint amdgpu_ras_mask = 0xffffffff;
155153
156154 /**
157155 * DOC: vramlimit (int)
@@ -244,16 +242,21 @@ module_param_named(msi, amdgpu_msi, int, 0444); · 86 unmodified lines
244242 *
245243 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
246244 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
247− * to default timeout.
248− * - With one value specified, the setting will apply to all non-compute jobs.
249− * - With multiple values specified, the first one will be for GFX. The second one is for Compute.
250− * And the third and fourth ones are for SDMA and Video.
245+ * to the default timeout.
246+ *
247+ * - With one value specified, the setting will apply to all non-compute jobs.
248+ * - With multiple values specified, the first one will be for GFX.
249+ * The second one is for Compute. The third and fourth ones are
250+ * for SDMA and Video.
251+ *
251252 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
252253 * jobs is 10000. And there is no timeout enforced on compute jobs.
253254 */
254−MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and infinity timeout for compute jobs."
255+MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; "
256+ "for passthrough or sriov, 10000 for all jobs."
255257 " 0: keep default value. negative: infinity timeout), "
256− "format is [Non-Compute] or [GFX,Compute,SDMA,Video]");
258+ "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
259+ "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
257260 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
258261
259262 /**
@@ -391,6 +394,14 @@ module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); · 131 unmodified lines
391394 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
392395 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
393396
397+/**
398+ * DOC: forcelongtraining (uint)
399+ * Force long memory training in resume.
400+ * The default is zero, indicates short training in resume.
401+ */
402+MODULE_PARM_DESC(forcelongtraining, "force memory long training");
403+module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
404+
394405 /**
395406 * DOC: pcie_gen_cap (uint)
396407 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
@@ -448,42 +459,6 @@ MODULE_PARM_DESC(virtual_display, · 51 unmodified lines
448459 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
449460 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
450461
451−/**
452− * DOC: ngg (int)
453− * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled).
454− */
455−MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
456−module_param_named(ngg, amdgpu_ngg, int, 0444);
457−
458−/**
459− * DOC: prim_buf_per_se (int)
460− * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
461− */
462−MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
463−module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
464−
465−/**
466− * DOC: pos_buf_per_se (int)
467− * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
468− */
469−MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
470−module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
471−
472−/**
473− * DOC: cntl_sb_buf_per_se (int)
474− * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx).
475− */
476−MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
477−module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
478−
479−/**
480− * DOC: param_buf_per_se (int)
481− * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte.
482− * The default is 0 (depending on gfx).
483− */
484−MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)");
485−module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
486−
487462 /**
488463 * DOC: job_hang_limit (int)
489464 * Set how much time allow a job hang and not drop it. The default is 0.
@@ -616,6 +591,16 @@ MODULE_PARM_DESC(noretry, · 126 unmodified lines
616591 "Disable retry faults (0 = retry enabled, 1 = retry disabled (default))");
617592 module_param_named(noretry, amdgpu_noretry, int, 0644);
618593
594+/**
595+ * DOC: force_asic_type (int)
596+ * A non negative value used to specify the asic type for all supported GPUs.
597+ */
598+MODULE_PARM_DESC(force_asic_type,
599+ "A non negative value used to specify the asic type for all supported GPUs");
600+module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
601+
602+
603+
619604 #ifdef CONFIG_HSA_AMD
620605 /**
621606 * DOC: sched_policy (int)
@@ -1016,12 +1001,14 @@ static const struct pci_device_id pciidlist[] = { · 394 unmodified lines
10161001 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
10171002 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
10181003 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
1004+ {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
10191005
10201006 /* Renoir */
10211007 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
10221008
10231009 /* Navi12 */
10241010 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
1011+ {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
10251012
10261013 {0, 0, 0}
10271014 };
@@ -1048,6 +1035,41 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, · 20 unmodified lines
10481035 return -ENODEV;
10491036 }
10501037
1038+#ifdef CONFIG_DRM_AMDGPU_SI
1039+ if (!amdgpu_si_support) {
1040+ switch (flags & AMD_ASIC_MASK) {
1041+ case CHIP_TAHITI:
1042+ case CHIP_PITCAIRN:
1043+ case CHIP_VERDE:
1044+ case CHIP_OLAND:
1045+ case CHIP_HAINAN:
1046+ dev_info(&pdev->dev,
1047+ "SI support provided by radeon.\n");
1048+ dev_info(&pdev->dev,
1049+ "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
1050+ );
1051+ return -ENODEV;
1052+ }
1053+ }
1054+#endif
1055+#ifdef CONFIG_DRM_AMDGPU_CIK
1056+ if (!amdgpu_cik_support) {
1057+ switch (flags & AMD_ASIC_MASK) {
1058+ case CHIP_KAVERI:
1059+ case CHIP_BONAIRE:
1060+ case CHIP_HAWAII:
1061+ case CHIP_KABINI:
1062+ case CHIP_MULLINS:
1063+ dev_info(&pdev->dev,
1064+ "CIK support provided by radeon.\n");
1065+ dev_info(&pdev->dev,
1066+ "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
1067+ );
1068+ return -ENODEV;
1069+ }
1070+ }
1071+#endif
1072+
10511073 /* Get rid of things like offb */
10521074 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb");
10531075 if (ret)
@@ -1092,7 +1114,10 @@ amdgpu_pci_remove(struct pci_dev *pdev) · 38 unmodified lines
10921114 {
10931115 struct drm_device *dev = pci_get_drvdata(pdev);
10941116
1095− DRM_ERROR("Device removal is currently not supported outside of fbcon\n");
1117+#ifdef MODULE
1118+ if (THIS_MODULE->state != MODULE_STATE_GOING)
1119+#endif
1120+ DRM_ERROR("Hotplug removal is not supported\n");
10961121 drm_dev_unplug(dev);
10971122 drm_dev_put(dev);
10981123 pci_disable_device(pdev);
@@ -1105,6 +1130,9 @@ amdgpu_pci_shutdown(struct pci_dev *pdev) · 6 unmodified lines
11051130 struct drm_device *dev = pci_get_drvdata(pdev);
11061131 struct amdgpu_device *adev = dev->dev_private;
11071132
1133+ if (amdgpu_ras_intr_triggered())
1134+ return;
1135+
11081136 /* if we are running in a VM, make sure the device
11091137 * torn down properly on reboot/shutdown.
11101138 * unfortunately we can't detect certain
@@ -1139,8 +1167,13 @@ static int amdgpu_pmops_resume(struct device *dev) · 28 unmodified lines
11391167 static int amdgpu_pmops_freeze(struct device *dev)
11401168 {
11411169 struct drm_device *drm_dev = dev_get_drvdata(dev);
1170+ struct amdgpu_device *adev = drm_dev->dev_private;
1171+ int r;
11421172
1143− return amdgpu_device_suspend(drm_dev, false, true);
1173+ r = amdgpu_device_suspend(drm_dev, false, true);
1174+ if (r)
1175+ return r;
1176+ return amdgpu_asic_reset(adev);
11441177 }
11451178
11461179 static int amdgpu_pmops_thaw(struct device *dev)
@@ -1312,66 +1345,6 @@ int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) · 165 unmodified lines
13121345 return 0;
13131346 }
13141347
1315−int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
1316−{
1317− char *input = amdgpu_lockup_timeout;
1318− char *timeout_setting = NULL;
1319− int index = 0;
1320− long timeout;
1321− int ret = 0;
1322−
1323− /*
1324− * By default timeout for non compute jobs is 10000.
1325− * And there is no timeout enforced on compute jobs.
1326− */
1327− adev->gfx_timeout = msecs_to_jiffies(10000);
1328− adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
1329− adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
1330−
1331− if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
1332− while ((timeout_setting = strsep(&input, ",")) &&
1333− strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
1334− ret = kstrtol(timeout_setting, 0, &timeout);
1335− if (ret)
1336− return ret;
1337−
1338− if (timeout == 0) {
1339− index++;
1340− continue;
1341− } else if (timeout < 0) {
1342− timeout = MAX_SCHEDULE_TIMEOUT;
1343− } else {
1344− timeout = msecs_to_jiffies(timeout);
1345− }
1346−
1347− switch (index++) {
1348− case 0:
1349− adev->gfx_timeout = timeout;
1350− break;
1351− case 1:
1352− adev->compute_timeout = timeout;
1353− break;
1354− case 2:
1355− adev->sdma_timeout = timeout;
1356− break;
1357− case 3:
1358− adev->video_timeout = timeout;
1359− break;
1360− default:
1361− break;
1362− }
1363− }
1364− /*
1365− * There is only one value specified and
1366− * it should apply to all non-compute jobs.
1367− */
1368− if (index == 1)
1369− adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
1370− }
1371−
1372− return ret;
1373−}
1374−
13751348 static bool
13761349 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
13771350 bool in_vblank_irq, int *vpos, int *hpos,
@@ -1410,8 +1383,6 @@ static struct drm_driver kms_driver = { · 32 unmodified lines
14101383 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
14111384 .gem_prime_export = amdgpu_gem_prime_export,
14121385 .gem_prime_import = amdgpu_gem_prime_import,
1413− .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
1414− .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
14151386 .gem_prime_vmap = amdgpu_gem_prime_vmap,
14161387 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
14171388 .gem_prime_mmap = amdgpu_gem_prime_mmap,
drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c+28−12
@@ -37,12 +37,14 @@ amdgpu_link_encoder_connector(struct drm_device *dev) · 36 unmodified lines
3737 {
3838 struct amdgpu_device *adev = dev->dev_private;
3939 struct drm_connector *connector;
40+ struct drm_connector_list_iter iter;
4041 struct amdgpu_connector *amdgpu_connector;
4142 struct drm_encoder *encoder;
4243 struct amdgpu_encoder *amdgpu_encoder;
4344
45+ drm_connector_list_iter_begin(dev, &iter);
4446 /* walk the list and link encoders to connectors */
45− list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
47+ drm_for_each_connector_iter(connector, &iter) {
4648 amdgpu_connector = to_amdgpu_connector(connector);
4749 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4850 amdgpu_encoder = to_amdgpu_encoder(encoder);
@@ -55,6 +57,7 @@ amdgpu_link_encoder_connector(struct drm_device *dev) · 6 unmodified lines
5557 }
5658 }
5759 }
60+ drm_connector_list_iter_end(&iter);
5861 }
5962
6063 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder)
@@ -62,8 +65,10 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) · 1 unmodified line
6265 struct drm_device *dev = encoder->dev;
6366 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6467 struct drm_connector *connector;
68+ struct drm_connector_list_iter iter;
6569
66− list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
70+ drm_connector_list_iter_begin(dev, &iter);
71+ drm_for_each_connector_iter(connector, &iter) {
6772 if (connector->encoder == encoder) {
6873 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
6974 amdgpu_encoder->active_device = amdgpu_encoder->devices & amdgpu_connector->devices;
@@ -72,6 +77,7 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) · 2 unmodified lines
7277 amdgpu_connector->devices, encoder->encoder_type);
7378 }
7479 }
80+ drm_connector_list_iter_end(&iter);
7581 }
7682
7783 struct drm_connector *
@@ -79,15 +85,20 @@ amdgpu_get_connector_for_encoder(struct drm_encoder *encoder) · 1 unmodified line
7985 {
8086 struct drm_device *dev = encoder->dev;
8187 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
82− struct drm_connector *connector;
88+ struct drm_connector *connector, *found = NULL;
89+ struct drm_connector_list_iter iter;
8390 struct amdgpu_connector *amdgpu_connector;
8491
85− list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
92+ drm_connector_list_iter_begin(dev, &iter);
93+ drm_for_each_connector_iter(connector, &iter) {
8694 amdgpu_connector = to_amdgpu_connector(connector);
87− if (amdgpu_encoder->active_device & amdgpu_connector->devices)
88− return connector;
95+ if (amdgpu_encoder->active_device & amdgpu_connector->devices) {
96+ found = connector;
97+ break;
98+ }
8999 }
90− return NULL;
100+ drm_connector_list_iter_end(&iter);
101+ return found;
91102 }
92103
93104 struct drm_connector *
@@ -95,15 +106,20 @@ amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder) · 1 unmodified line
95106 {
96107 struct drm_device *dev = encoder->dev;
97108 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
98− struct drm_connector *connector;
109+ struct drm_connector *connector, *found = NULL;
110+ struct drm_connector_list_iter iter;
99111 struct amdgpu_connector *amdgpu_connector;
100112
101− list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
113+ drm_connector_list_iter_begin(dev, &iter);
114+ drm_for_each_connector_iter(connector, &iter) {
102115 amdgpu_connector = to_amdgpu_connector(connector);
103− if (amdgpu_encoder->devices & amdgpu_connector->devices)
104− return connector;
116+ if (amdgpu_encoder->devices & amdgpu_connector->devices) {
117+ found = connector;
118+ break;
119+ }
105120 }
106− return NULL;
121+ drm_connector_list_iter_end(&iter);
122+ return found;
107123 }
108124
109125 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder)
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c+1−12
@@ -462,18 +462,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, · 461 unmodified lines
462462 timeout = adev->gfx_timeout;
463463 break;
464464 case AMDGPU_RING_TYPE_COMPUTE:
465− /*
466− * For non-sriov case, no timeout enforce
467− * on compute ring by default. Unless user
468− * specifies a timeout for compute ring.
469− *
470− * For sriov case, always use the timeout
471− * as gfx ring
472− */
473− if (!amdgpu_sriov_vf(ring->adev))
474− timeout = adev->compute_timeout;
475− else
476− timeout = adev->gfx_timeout;
465+ timeout = adev->compute_timeout;
477466 break;
478467 case AMDGPU_RING_TYPE_SDMA:
479468 timeout = adev->sdma_timeout;
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c+1−1
@@ -71,7 +71,7 @@ · 70 unmodified lines
7171 */
7272 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
7373 {
74− struct page *dummy_page = adev->mman.bdev.glob->dummy_read_page;
74+ struct page *dummy_page = ttm_bo_glob.dummy_read_page;
7575
7676 if (adev->dummy_page_addr)
7777 return 0;
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c+33−5
@@ -175,7 +175,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, · 174 unmodified lines
175175
176176 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
177177
178− r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates, false);
178+ r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
179179 if (r) {
180180 dev_err(adev->dev, "leaking bo va because "
181181 "we fail to reserve bo (%d)\n", r);
@@ -527,13 +527,41 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, · 345 unmodified lines
527527 goto error;
528528 }
529529
530− r = amdgpu_vm_update_directories(adev, vm);
530+ r = amdgpu_vm_update_pdes(adev, vm, false);
531531
532532 error:
533533 if (r && r != -ERESTARTSYS)
534534 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
535535 }
536536
537+/**
538+ * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags
539+ *
540+ * @adev: amdgpu_device pointer
541+ * @flags: GEM UAPI flags
542+ *
543+ * Returns the GEM UAPI flags mapped into hardware for the ASIC.
544+ */
545+uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
546+{
547+ uint64_t pte_flag = 0;
548+
549+ if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
550+ pte_flag |= AMDGPU_PTE_EXECUTABLE;
551+ if (flags & AMDGPU_VM_PAGE_READABLE)
552+ pte_flag |= AMDGPU_PTE_READABLE;
553+ if (flags & AMDGPU_VM_PAGE_WRITEABLE)
554+ pte_flag |= AMDGPU_PTE_WRITEABLE;
555+ if (flags & AMDGPU_VM_PAGE_PRT)
556+ pte_flag |= AMDGPU_PTE_PRT;
557+
558+ if (adev->gmc.gmc_funcs->map_mtype)
559+ pte_flag |= amdgpu_gmc_map_mtype(adev,
560+ flags & AMDGPU_VM_MTYPE_MASK);
561+
562+ return pte_flag;
563+}
564+
537565 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
538566 struct drm_file *filp)
539567 {
@@ -613,7 +641,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, · 73 unmodified lines
613641
614642 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
615643
616− r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates, false);
644+ r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
617645 if (r)
618646 goto error_unref;
619647
@@ -631,7 +659,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, · 11 unmodified lines
631659
632660 switch (args->operation) {
633661 case AMDGPU_VA_OP_MAP:
634− va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
662+ va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
635663 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
636664 args->offset_in_bo, args->map_size,
637665 va_flags);
@@ -646,7 +674,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, · 8 unmodified lines
646674 args->map_size);
647675 break;
648676 case AMDGPU_VA_OP_REPLACE:
649− va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
677+ va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
650678 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
651679 args->offset_in_bo, args->map_size,
652680 va_flags);
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h+1−0
@@ -67,6 +67,7 @@ int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, · 66 unmodified lines
6767 struct drm_file *filp);
6868 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
6969 struct drm_file *filp);
70+uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags);
7071 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
7172 struct drm_file *filp);
7273 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c+102−5
@@ -26,6 +26,7 @@ · 25 unmodified lines
2626 #include "amdgpu.h"
2727 #include "amdgpu_gfx.h"
2828 #include "amdgpu_rlc.h"
29+#include "amdgpu_ras.h"
2930
3031 /* delay 0.1 second to enable gfx off feature */
3132 #define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100)
@@ -231,12 +232,10 @@ void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) · 199 unmodified lines
231232
232233 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
233234 {
234− int i, queue, pipe, me;
235+ int i, queue, me;
235236
236237 for (i = 0; i < AMDGPU_MAX_GFX_QUEUES; ++i) {
237238 queue = i % adev->gfx.me.num_queue_per_pipe;
238− pipe = (i / adev->gfx.me.num_queue_per_pipe)
239− % adev->gfx.me.num_pipe_per_me;
240239 me = (i / adev->gfx.me.num_queue_per_pipe)
241240 / adev->gfx.me.num_pipe_per_me;
242241
@@ -320,8 +319,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, · 77 unmodified lines
320319 return r;
321320 }
322321
323−void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
324− struct amdgpu_irq_src *irq)
322+void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
325323 {
326324 amdgpu_device_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
327325 amdgpu_ring_fini(ring);
@@ -569,3 +567,102 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) · 241 unmodified lines
569567
570568 mutex_unlock(&adev->gfx.gfx_off_mutex);
571569 }
570+
571+int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev)
572+{
573+ int r;
574+ struct ras_fs_if fs_info = {
575+ .sysfs_name = "gfx_err_count",
576+ .debugfs_name = "gfx_err_inject",
577+ };
578+ struct ras_ih_if ih_info = {
579+ .cb = amdgpu_gfx_process_ras_data_cb,
580+ };
581+
582+ if (!adev->gfx.ras_if) {
583+ adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
584+ if (!adev->gfx.ras_if)
585+ return -ENOMEM;
586+ adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
587+ adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
588+ adev->gfx.ras_if->sub_block_index = 0;
589+ strcpy(adev->gfx.ras_if->name, "gfx");
590+ }
591+ fs_info.head = ih_info.head = *adev->gfx.ras_if;
592+
593+ r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
594+ &fs_info, &ih_info);
595+ if (r)
596+ goto free;
597+
598+ if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
599+ r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
600+ if (r)
601+ goto late_fini;
602+ } else {
603+ /* free gfx ras_if if ras is not supported */
604+ r = 0;
605+ goto free;
606+ }
607+
608+ return 0;
609+late_fini:
610+ amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
611+free:
612+ kfree(adev->gfx.ras_if);
613+ adev->gfx.ras_if = NULL;
614+ return r;
615+}
616+
617+void amdgpu_gfx_ras_fini(struct amdgpu_device *adev)
618+{
619+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
620+ adev->gfx.ras_if) {
621+ struct ras_common_if *ras_if = adev->gfx.ras_if;
622+ struct ras_ih_if ih_info = {
623+ .head = *ras_if,
624+ .cb = amdgpu_gfx_process_ras_data_cb,
625+ };
626+
627+ amdgpu_ras_late_fini(adev, ras_if, &ih_info);
628+ kfree(ras_if);
629+ }
630+}
631+
632+int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
633+ void *err_data,
634+ struct amdgpu_iv_entry *entry)
635+{
636+ /* TODO ue will trigger an interrupt.
637+ *
638+ * When “Full RAS” is enabled, the per-IP interrupt sources should
639+ * be disabled and the driver should only look for the aggregated
640+ * interrupt via sync flood
641+ */
642+ if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
643+ kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
644+ if (adev->gfx.funcs->query_ras_error_count)
645+ adev->gfx.funcs->query_ras_error_count(adev, err_data);
646+ amdgpu_ras_reset_gpu(adev, 0);
647+ }
648+ return AMDGPU_RAS_SUCCESS;
649+}
650+
651+int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
652+ struct amdgpu_irq_src *source,
653+ struct amdgpu_iv_entry *entry)
654+{
655+ struct ras_common_if *ras_if = adev->gfx.ras_if;
656+ struct ras_dispatch_if ih_data = {
657+ .entry = entry,
658+ };
659+
660+ if (!ras_if)
661+ return 0;
662+
663+ ih_data.head = *ras_if;
664+
665+ DRM_ERROR("CP ECC ERROR IRQ\n");
666+ amdgpu_ras_interrupt_dispatch(adev, &ih_data);
667+ return 0;
668+}
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h+10−28
@@ -201,28 +201,6 @@ struct amdgpu_gfx_funcs { · 200 unmodified lines
201201 int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
202202 };
203203
204−struct amdgpu_ngg_buf {
205− struct amdgpu_bo *bo;
206− uint64_t gpu_addr;
207− uint32_t size;
208− uint32_t bo_size;
209−};
210−
211−enum {
212− NGG_PRIM = 0,
213− NGG_POS,
214− NGG_CNTL,
215− NGG_PARAM,
216− NGG_BUF_MAX
217−};
218−
219−struct amdgpu_ngg {
220− struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
221− uint32_t gds_reserve_addr;
222− uint32_t gds_reserve_size;
223− bool init;
224−};
225−
226204 struct sq_work {
227205 struct work_struct work;
228206 unsigned ih_data;
@@ -289,6 +267,7 @@ struct amdgpu_gfx { · 60 unmodified lines
289267 uint32_t mec2_feature_version;
290268 bool mec_fw_write_wait;
291269 bool me_fw_write_wait;
270+ bool cp_fw_write_wait;
292271 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
293272 unsigned num_gfx_rings;
294273 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
@@ -311,9 +290,6 @@ struct amdgpu_gfx { · 16 unmodified lines
311290 uint32_t grbm_soft_reset;
312291 uint32_t srbm_soft_reset;
313292
314− /* NGG */
315− struct amdgpu_ngg ngg;
316−
317293 /* gfx off */
318294 bool gfx_off_state; /* true: enabled, false: disabled */
319295 struct mutex gfx_off_mutex;
@@ -355,8 +331,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, · 35 unmodified lines
355331 struct amdgpu_ring *ring,
356332 struct amdgpu_irq_src *irq);
357333
358−void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
359− struct amdgpu_irq_src *irq);
334+void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
360335
361336 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
362337 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
@@ -384,5 +359,12 @@ void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, · 21 unmodified lines
384359 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
385360 int pipe, int queue);
386361 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
387−
362+int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
363+void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
364+int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
365+ void *err_data,
366+ struct amdgpu_iv_entry *entry);
367+int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
368+ struct amdgpu_irq_src *source,
369+ struct amdgpu_iv_entry *entry);
388370 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c+28−0
@@ -27,6 +27,8 @@ · 26 unmodified lines
2727 #include <linux/io-64-nonatomic-lo-hi.h>
2828
2929 #include "amdgpu.h"
30+#include "amdgpu_ras.h"
31+#include "amdgpu_xgmi.h"
3032
3133 /**
3234 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
@@ -305,3 +307,29 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, · 272 unmodified lines
305307 gmc->fault_hash[hash].idx = gmc->last_fault++;
306308 return false;
307309 }
310+
311+int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
312+{
313+ int r;
314+
315+ if (adev->umc.funcs && adev->umc.funcs->ras_late_init) {
316+ r = adev->umc.funcs->ras_late_init(adev);
317+ if (r)
318+ return r;
319+ }
320+
321+ if (adev->mmhub.funcs && adev->mmhub.funcs->ras_late_init) {
322+ r = adev->mmhub.funcs->ras_late_init(adev);
323+ if (r)
324+ return r;
325+ }
326+
327+ return amdgpu_xgmi_ras_late_init(adev);
328+}
329+
330+void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
331+{
332+ amdgpu_umc_ras_fini(adev);
333+ amdgpu_mmhub_ras_fini(adev);
334+ amdgpu_xgmi_ras_fini(adev);
335+}
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h+42−6
@@ -99,12 +99,15 @@ struct amdgpu_gmc_funcs { · 98 unmodified lines
9999 unsigned pasid);
100100 /* enable/disable PRT support */
101101 void (*set_prt)(struct amdgpu_device *adev, bool enable);
102− /* set pte flags based per asic */
103− uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
104− uint32_t flags);
102+ /* map mtype to hardware flags */
103+ uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags);
105104 /* get the pde for a given mc addr */
106105 void (*get_vm_pde)(struct amdgpu_device *adev, int level,
107106 u64 *dst, u64 *flags);
107+ /* get the pte flags to use for a BO VA mapping */
108+ void (*get_vm_pte)(struct amdgpu_device *adev,
109+ struct amdgpu_bo_va_mapping *mapping,
110+ uint64_t *flags);
108111 };
109112
110113 struct amdgpu_xgmi {
@@ -120,21 +123,52 @@ struct amdgpu_xgmi { · 9 unmodified lines
120123 /* gpu list in the same hive */
121124 struct list_head head;
122125 bool supported;
126+ struct ras_common_if *ras_if;
123127 };
124128
125129 struct amdgpu_gmc {
130+ /* FB's physical address in MMIO space (for CPU to
131+ * map FB). This is different compared to the agp/
132+ * gart/vram_start/end field as the later is from
133+ * GPU's view and aper_base is from CPU's view.
134+ */
126135 resource_size_t aper_size;
127136 resource_size_t aper_base;
128137 /* for some chips with <= 32MB we need to lie
129138 * about vram size near mc fb location */
130139 u64 mc_vram_size;
131140 u64 visible_vram_size;
141+ /* AGP aperture start and end in MC address space
142+ * Driver find a hole in the MC address space
143+ * to place AGP by setting MC_VM_AGP_BOT/TOP registers
144+ * Under VMID0, logical address == MC address. AGP
145+ * aperture maps to physical bus or IOVA addressed.
146+ * AGP aperture is used to simulate FB in ZFB case.
147+ * AGP aperture is also used for page table in system
148+ * memory (mainly for APU).
149+ *
150+ */
132151 u64 agp_size;
133152 u64 agp_start;
134153 u64 agp_end;
154+ /* GART aperture start and end in MC address space
155+ * Driver find a hole in the MC address space
156+ * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR
157+ * registers
158+ * Under VMID0, logical address inside GART aperture will
159+ * be translated through gpuvm gart page table to access
160+ * paged system memory
161+ */
135162 u64 gart_size;
136163 u64 gart_start;
137164 u64 gart_end;
165+ /* Frame buffer aperture of this GPU device. Different from
166+ * fb_start (see below), this only covers the local GPU device.
167+ * Driver get fb_start from MC_VM_FB_LOCATION_BASE (set by vbios)
168+ * and calculate vram_start of this local device by adding an
169+ * offset inside the XGMI hive.
170+ * Under VMID0, logical address == MC address
171+ */
138172 u64 vram_start;
139173 u64 vram_end;
140174 /* FB region , it's same as local vram region in single GPU, in XGMI
@@ -153,6 +187,7 @@ struct amdgpu_gmc { · 12 unmodified lines
153187 uint32_t fw_version;
154188 struct amdgpu_irq_src vm_fault;
155189 uint32_t vram_type;
190+ uint8_t vram_vendor;
156191 uint32_t srbm_soft_reset;
157192 bool prt_warning;
158193 uint64_t stolen_size;
@@ -177,15 +212,14 @@ struct amdgpu_gmc { · 18 unmodified lines
177212
178213 struct amdgpu_xgmi xgmi;
179214 struct amdgpu_irq_src ecc_irq;
180− struct ras_common_if *umc_ras_if;
181− struct ras_common_if *mmhub_ras_if;
182215 };
183216
184217 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
185218 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
186219 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
220+#define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
187221 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
188−#define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
222+#define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags))
189223
190224 /**
191225 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
@@ -230,5 +264,7 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev, · 38 unmodified lines
230264 struct amdgpu_gmc *mc);
231265 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
232266 uint16_t pasid, uint64_t timestamp);
267+int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev);
268+void amdgpu_gmc_ras_fini(struct amdgpu_device *adev);
233269
234270 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c+3−3
@@ -282,7 +282,7 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm, · 281 unmodified lines
282282 !dma_fence_is_later(updates, (*id)->flushed_updates))
283283 updates = NULL;
284284
285− if ((*id)->owner != vm->entity.fence_context ||
285+ if ((*id)->owner != vm->direct.fence_context ||
286286 job->vm_pd_addr != (*id)->pd_gpu_addr ||
287287 updates || !(*id)->last_flush ||
288288 ((*id)->last_flush->context != fence_context &&
@@ -349,7 +349,7 @@ static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm, · 60 unmodified lines
349349 struct dma_fence *flushed;
350350
351351 /* Check all the prerequisites to using this VMID */
352− if ((*id)->owner != vm->entity.fence_context)
352+ if ((*id)->owner != vm->direct.fence_context)
353353 continue;
354354
355355 if ((*id)->pd_gpu_addr != job->vm_pd_addr)
@@ -449,7 +449,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring, · 93 unmodified lines
449449 }
450450
451451 id->pd_gpu_addr = job->vm_pd_addr;
452− id->owner = vm->entity.fence_context;
452+ id->owner = vm->direct.fence_context;
453453
454454 if (job->vm_needs_flush) {
455455 dma_fence_put(id->last_flush);
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c+34−7
@@ -87,10 +87,13 @@ static void amdgpu_hotplug_work_func(struct work_struct *work) · 86 unmodified lines
8787 struct drm_device *dev = adev->ddev;
8888 struct drm_mode_config *mode_config = &dev->mode_config;
8989 struct drm_connector *connector;
90+ struct drm_connector_list_iter iter;
9091
9192 mutex_lock(&mode_config->mutex);
92− list_for_each_entry(connector, &mode_config->connector_list, head)
93+ drm_connector_list_iter_begin(dev, &iter);
94+ drm_for_each_connector_iter(connector, &iter)
9395 amdgpu_connector_hotplug(connector);
96+ drm_connector_list_iter_end(&iter);
9497 mutex_unlock(&mode_config->mutex);
9598 /* Just fire off a uevent and let userspace tell us what to do */
9699 drm_helper_hpd_irq_event(dev);
@@ -153,6 +156,20 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg) · 56 unmodified lines
153156 ret = amdgpu_ih_process(adev, &adev->irq.ih);
154157 if (ret == IRQ_HANDLED)
155158 pm_runtime_mark_last_busy(dev->dev);
159+
160+ /* For the hardware that cannot enable bif ring for both ras_controller_irq
161+ * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
162+ * register to check whether the interrupt is triggered or not, and properly
163+ * ack the interrupt if it is there
164+ */
165+ if (adev->nbio.funcs &&
166+ adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
167+ adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
168+
169+ if (adev->nbio.funcs &&
170+ adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
171+ adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
172+
156173 return ret;
157174 }
158175
@@ -228,10 +245,19 @@ int amdgpu_irq_init(struct amdgpu_device *adev) · 69 unmodified lines
228245 adev->irq.msi_enabled = false;
229246
230247 if (amdgpu_msi_ok(adev)) {
231− int ret = pci_enable_msi(adev->pdev);
232− if (!ret) {
248+ int nvec = pci_msix_vec_count(adev->pdev);
249+ unsigned int flags;
250+
251+ if (nvec <= 0) {
252+ flags = PCI_IRQ_MSI;
253+ } else {
254+ flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
255+ }
256+ /* we only need one vector */
257+ nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
258+ if (nvec > 0) {
233259 adev->irq.msi_enabled = true;
234− dev_dbg(adev->dev, "amdgpu: using MSI.\n");
260+ dev_dbg(adev->dev, "amdgpu: using MSI/MSI-X.\n");
235261 }
236262 }
237263
@@ -254,7 +280,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev) · 16 unmodified lines
254280 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
255281
256282 adev->irq.installed = true;
257− r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
283+ /* Use vector 0 for MSI-X */
284+ r = drm_irq_install(adev->ddev, pci_irq_vector(adev->pdev, 0));
258285 if (r) {
259286 adev->irq.installed = false;
260287 if (!amdgpu_device_has_dc_support(adev))
@@ -284,7 +311,7 @@ void amdgpu_irq_fini(struct amdgpu_device *adev) · 23 unmodified lines
284311 drm_irq_uninstall(adev->ddev);
285312 adev->irq.installed = false;
286313 if (adev->irq.msi_enabled)
287− pci_disable_msi(adev->pdev);
314+ pci_free_irq_vectors(adev->pdev);
288315 if (!amdgpu_device_has_dc_support(adev))
289316 flush_work(&adev->hotplug_work);
290317 }
@@ -369,7 +396,7 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev, · 78 unmodified lines
369396 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
370397 *
371398 * @adev: amdgpu device pointer
372− * @entry: interrupt vector pointer
399+ * @ih: interrupt ring instance
373400 *
374401 * Dispatches IRQ to IP blocks.
375402 */
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c+41−1
@@ -218,7 +218,7 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) · 217 unmodified lines
218218 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
219219 struct dma_fence *fence = NULL, *finished;
220220 struct amdgpu_job *job;
221− int r;
221+ int r = 0;
222222
223223 job = to_amdgpu_job(sched_job);
224224 finished = &job->base.s_fence->finished;
@@ -243,9 +243,49 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) · 18 unmodified lines
243243 job->fence = dma_fence_get(fence);
244244
245245 amdgpu_job_free_resources(job);
246+
247+ fence = r ? ERR_PTR(r) : fence;
246248 return fence;
247249 }
248250
251+#define to_drm_sched_job(sched_job) \
252+ container_of((sched_job), struct drm_sched_job, queue_node)
253+
254+void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)
255+{
256+ struct drm_sched_job *s_job;
257+ struct drm_sched_entity *s_entity = NULL;
258+ int i;
259+
260+ /* Signal all jobs not yet scheduled */
261+ for (i = DRM_SCHED_PRIORITY_MAX - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) {
262+ struct drm_sched_rq *rq = &sched->sched_rq[i];
263+
264+ if (!rq)
265+ continue;
266+
267+ spin_lock(&rq->lock);
268+ list_for_each_entry(s_entity, &rq->entities, list) {
269+ while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) {
270+ struct drm_sched_fence *s_fence = s_job->s_fence;
271+
272+ dma_fence_signal(&s_fence->scheduled);
273+ dma_fence_set_error(&s_fence->finished, -EHWPOISON);
274+ dma_fence_signal(&s_fence->finished);
275+ }
276+ }
277+ spin_unlock(&rq->lock);
278+ }
279+
280+ /* Signal all jobs already scheduled to HW */
281+ list_for_each_entry(s_job, &sched->ring_mirror_list, node) {
282+ struct drm_sched_fence *s_fence = s_job->s_fence;
283+
284+ dma_fence_set_error(&s_fence->finished, -EHWPOISON);
285+ dma_fence_signal(&s_fence->finished);
286+ }
287+}
288+
249289 const struct drm_sched_backend_ops amdgpu_sched_ops = {
250290 .dependency = amdgpu_job_dependency,
251291 .run_job = amdgpu_job_run,
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h+3−0
@@ -76,4 +76,7 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity, · 75 unmodified lines
7676 void *owner, struct dma_fence **f);
7777 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
7878 struct dma_fence **fence);
79+
80+void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched);
81+
7982 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c+18−53
@@ -144,41 +144,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) · 143 unmodified lines
144144 struct amdgpu_device *adev;
145145 int r, acpi_status;
146146
147−#ifdef CONFIG_DRM_AMDGPU_SI
148− if (!amdgpu_si_support) {
149− switch (flags & AMD_ASIC_MASK) {
150− case CHIP_TAHITI:
151− case CHIP_PITCAIRN:
152− case CHIP_VERDE:
153− case CHIP_OLAND:
154− case CHIP_HAINAN:
155− dev_info(dev->dev,
156− "SI support provided by radeon.\n");
157− dev_info(dev->dev,
158− "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
159− );
160− return -ENODEV;
161− }
162− }
163−#endif
164−#ifdef CONFIG_DRM_AMDGPU_CIK
165− if (!amdgpu_cik_support) {
166− switch (flags & AMD_ASIC_MASK) {
167− case CHIP_KAVERI:
168− case CHIP_BONAIRE:
169− case CHIP_HAWAII:
170− case CHIP_KABINI:
171− case CHIP_MULLINS:
172− dev_info(dev->dev,
173− "CIK support provided by radeon.\n");
174− dev_info(dev->dev,
175− "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
176− );
177− return -ENODEV;
178− }
179− }
180−#endif
181−
182147 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
183148 if (adev == NULL) {
184149 return -ENOMEM;
@@ -225,7 +190,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) · 40 unmodified lines
225190 pm_runtime_put_autosuspend(dev->dev);
226191 }
227192
228− amdgpu_register_gpu_instance(adev);
229193 out:
230194 if (r) {
231195 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
@@ -619,9 +583,12 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file · 387 unmodified lines
619583 struct drm_amdgpu_info_vram_gtt vram_gtt;
620584
621585 vram_gtt.vram_size = adev->gmc.real_vram_size -
622− atomic64_read(&adev->vram_pin_size);
623− vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
624− atomic64_read(&adev->visible_pin_size);
586+ atomic64_read(&adev->vram_pin_size) -
587+ AMDGPU_VM_RESERVED_VRAM;
588+ vram_gtt.vram_cpu_accessible_size =
589+ min(adev->gmc.visible_vram_size -
590+ atomic64_read(&adev->visible_pin_size),
591+ vram_gtt.vram_size);
625592 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
626593 vram_gtt.gtt_size *= PAGE_SIZE;
627594 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
@@ -634,15 +601,18 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file · 6 unmodified lines
634601 memset(&mem, 0, sizeof(mem));
635602 mem.vram.total_heap_size = adev->gmc.real_vram_size;
636603 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
637− atomic64_read(&adev->vram_pin_size);
604+ atomic64_read(&adev->vram_pin_size) -
605+ AMDGPU_VM_RESERVED_VRAM;
638606 mem.vram.heap_usage =
639607 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
640608 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
641609
642610 mem.cpu_accessible_vram.total_heap_size =
643611 adev->gmc.visible_vram_size;
644− mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
645− atomic64_read(&adev->visible_pin_size);
612+ mem.cpu_accessible_vram.usable_heap_size =
613+ min(adev->gmc.visible_vram_size -
614+ atomic64_read(&adev->visible_pin_size),
615+ mem.vram.usable_heap_size);
646616 mem.cpu_accessible_vram.heap_usage =
647617 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
648618 mem.cpu_accessible_vram.max_allocation =
@@ -764,17 +734,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file · 115 unmodified lines
764734 dev_info.vce_harvest_config = adev->vce.harvest_config;
765735 dev_info.gc_double_offchip_lds_buf =
766736 adev->gfx.config.double_offchip_lds_buf;
767−
768− if (amdgpu_ngg) {
769− dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
770− dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
771− dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
772− dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
773− dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
774− dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
775− dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
776− dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
777− }
778737 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
779738 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
780739 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
@@ -1003,6 +962,12 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) · 222 unmodified lines
1003962 /* Ensure IB tests are run on ring */
1004963 flush_delayed_work(&adev->delayed_init_work);
1005964
965+
966+ if (amdgpu_ras_intr_triggered()) {
967+ DRM_ERROR("RAS Intr triggered, device disabled!!");
968+ return -EHWPOISON;
969+ }
970+
1006971 file_priv->driver_priv = NULL;
1007972
1008973 r = pm_runtime_get_sync(dev->dev);
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c+70−0
@@ -0,0 +1,70 @@
1+/*
2+ * Copyright 2019 Advanced Micro Devices, Inc.
3+ *
4+ * Permission is hereby granted, free of charge, to any person obtaining a
5+ * copy of this software and associated documentation files (the "Software"),
6+ * to deal in the Software without restriction, including without limitation
7+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+ * and/or sell copies of the Software, and to permit persons to whom the
9+ * Software is furnished to do so, subject to the following conditions:
10+ *
11+ * The above copyright notice and this permission notice shall be included in
12+ * all copies or substantial portions of the Software.
13+ *
14+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+ * OTHER DEALINGS IN THE SOFTWARE.
21+ *
22+ */
23+
24+#include "amdgpu.h"
25+#include "amdgpu_ras.h"
26+
27+int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev)
28+{
29+ int r;
30+ struct ras_ih_if ih_info = {
31+ .cb = NULL,
32+ };
33+ struct ras_fs_if fs_info = {
34+ .sysfs_name = "mmhub_err_count",
35+ .debugfs_name = "mmhub_err_inject",
36+ };
37+
38+ if (!adev->mmhub.ras_if) {
39+ adev->mmhub.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
40+ if (!adev->mmhub.ras_if)
41+ return -ENOMEM;
42+ adev->mmhub.ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
43+ adev->mmhub.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
44+ adev->mmhub.ras_if->sub_block_index = 0;
45+ strcpy(adev->mmhub.ras_if->name, "mmhub");
46+ }
47+ ih_info.head = fs_info.head = *adev->mmhub.ras_if;
48+ r = amdgpu_ras_late_init(adev, adev->mmhub.ras_if,
49+ &fs_info, &ih_info);
50+ if (r || !amdgpu_ras_is_supported(adev, adev->mmhub.ras_if->block)) {
51+ kfree(adev->mmhub.ras_if);
52+ adev->mmhub.ras_if = NULL;
53+ }
54+
55+ return r;
56+}
57+
58+void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev)
59+{
60+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
61+ adev->mmhub.ras_if) {
62+ struct ras_common_if *ras_if = adev->mmhub.ras_if;
63+ struct ras_ih_if ih_info = {
64+ .cb = NULL,
65+ };
66+
67+ amdgpu_ras_late_fini(adev, ras_if, &ih_info);
68+ kfree(ras_if);
69+ }
70+}
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h+8−0
@@ -23,9 +23,17 @@ · 22 unmodified lines
2323
2424 struct amdgpu_mmhub_funcs {
2525 void (*ras_init)(struct amdgpu_device *adev);
26+ int (*ras_late_init)(struct amdgpu_device *adev);
2627 void (*query_ras_error_count)(struct amdgpu_device *adev,
2728 void *ras_error_status);
2829 };
2930
31+struct amdgpu_mmhub {
32+ struct ras_common_if *ras_if;
33+ const struct amdgpu_mmhub_funcs *funcs;
34+};
35+
36+int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev);
37+void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev);
3038 #endif
3139
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c+1−0
@@ -136,6 +136,7 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn) · 135 unmodified lines
136136 * amdgpu_mn_read_lock - take the read side lock for this notifier
137137 *
138138 * @amn: our notifier
139+ * @blockable: is the notifier blockable
139140 */
140141 static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
141142 {
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c+84−0
@@ -0,0 +1,84 @@
1+/*
2+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
3+ *
4+ * Permission is hereby granted, free of charge, to any person obtaining a
5+ * copy of this software and associated documentation files (the "Software"),
6+ * to deal in the Software without restriction, including without limitation
7+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+ * and/or sell copies of the Software, and to permit persons to whom the
9+ * Software is furnished to do so, subject to the following conditions:
10+ *
11+ * The above copyright notice and this permission notice shall be included
12+ * in all copies or substantial portions of the Software.
13+ *
14+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20+ */
21+
22+#include "amdgpu.h"
23+#include "amdgpu_ras.h"
24+
25+int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev)
26+{
27+ int r;
28+ struct ras_ih_if ih_info = {
29+ .cb = NULL,
30+ };
31+ struct ras_fs_if fs_info = {
32+ .sysfs_name = "pcie_bif_err_count",
33+ .debugfs_name = "pcie_bif_err_inject",
34+ };
35+
36+ if (!adev->nbio.ras_if) {
37+ adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
38+ if (!adev->nbio.ras_if)
39+ return -ENOMEM;
40+ adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
41+ adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
42+ adev->nbio.ras_if->sub_block_index = 0;
43+ strcpy(adev->nbio.ras_if->name, "pcie_bif");
44+ }
45+ ih_info.head = fs_info.head = *adev->nbio.ras_if;
46+ r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,
47+ &fs_info, &ih_info);
48+ if (r)
49+ goto free;
50+
51+ if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
52+ r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
53+ if (r)
54+ goto late_fini;
55+ r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
56+ if (r)
57+ goto late_fini;
58+ } else {
59+ r = 0;
60+ goto free;
61+ }
62+
63+ return 0;
64+late_fini:
65+ amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);
66+free:
67+ kfree(adev->nbio.ras_if);
68+ adev->nbio.ras_if = NULL;
69+ return r;
70+}
71+
72+void amdgpu_nbio_ras_fini(struct amdgpu_device *adev)
73+{
74+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF) &&
75+ adev->nbio.ras_if) {
76+ struct ras_common_if *ras_if = adev->nbio.ras_if;
77+ struct ras_ih_if ih_info = {
78+ .cb = NULL,
79+ };
80+
81+ amdgpu_ras_late_fini(adev, ras_if, &ih_info);
82+ kfree(ras_if);
83+ }
84+}
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h+101−0
@@ -0,0 +1,101 @@
1+/*
2+ * Copyright 2019 Advanced Micro Devices, Inc.
3+ *
4+ * Permission is hereby granted, free of charge, to any person obtaining a
5+ * copy of this software and associated documentation files (the "Software"),
6+ * to deal in the Software without restriction, including without limitation
7+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+ * and/or sell copies of the Software, and to permit persons to whom the
9+ * Software is furnished to do so, subject to the following conditions:
10+ *
11+ * The above copyright notice and this permission notice shall be included in
12+ * all copies or substantial portions of the Software.
13+ *
14+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+ * OTHER DEALINGS IN THE SOFTWARE.
21+ *
22+ */
23+#ifndef __AMDGPU_NBIO_H__
24+#define __AMDGPU_NBIO_H__
25+
26+/*
27+ * amdgpu nbio functions
28+ */
29+struct nbio_hdp_flush_reg {
30+ u32 ref_and_mask_cp0;
31+ u32 ref_and_mask_cp1;
32+ u32 ref_and_mask_cp2;
33+ u32 ref_and_mask_cp3;
34+ u32 ref_and_mask_cp4;
35+ u32 ref_and_mask_cp5;
36+ u32 ref_and_mask_cp6;
37+ u32 ref_and_mask_cp7;
38+ u32 ref_and_mask_cp8;
39+ u32 ref_and_mask_cp9;
40+ u32 ref_and_mask_sdma0;
41+ u32 ref_and_mask_sdma1;
42+ u32 ref_and_mask_sdma2;
43+ u32 ref_and_mask_sdma3;
44+ u32 ref_and_mask_sdma4;
45+ u32 ref_and_mask_sdma5;
46+ u32 ref_and_mask_sdma6;
47+ u32 ref_and_mask_sdma7;
48+};
49+
50+struct amdgpu_nbio_funcs {
51+ const struct nbio_hdp_flush_reg *hdp_flush_reg;
52+ u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
53+ u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
54+ u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
55+ u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
56+ u32 (*get_rev_id)(struct amdgpu_device *adev);
57+ void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
58+ void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
59+ u32 (*get_memsize)(struct amdgpu_device *adev);
60+ void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
61+ bool use_doorbell, int doorbell_index, int doorbell_size);
62+ void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
63+ int doorbell_index, int instance);
64+ void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
65+ bool enable);
66+ void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
67+ bool enable);
68+ void (*ih_doorbell_range)(struct amdgpu_device *adev,
69+ bool use_doorbell, int doorbell_index);
70+ void (*enable_doorbell_interrupt)(struct amdgpu_device *adev,
71+ bool enable);
72+ void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
73+ bool enable);
74+ void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
75+ bool enable);
76+ void (*get_clockgating_state)(struct amdgpu_device *adev,
77+ u32 *flags);
78+ void (*ih_control)(struct amdgpu_device *adev);
79+ void (*init_registers)(struct amdgpu_device *adev);
80+ void (*detect_hw_virt)(struct amdgpu_device *adev);
81+ void (*remap_hdp_registers)(struct amdgpu_device *adev);
82+ void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev);
83+ void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
84+ int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
85+ int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
86+ void (*query_ras_error_count)(struct amdgpu_device *adev,
87+ void *ras_error_status);
88+ int (*ras_late_init)(struct amdgpu_device *adev);
89+};
90+
91+struct amdgpu_nbio {
92+ const struct nbio_hdp_flush_reg *hdp_flush_reg;
93+ struct amdgpu_irq_src ras_controller_irq;
94+ struct amdgpu_irq_src ras_err_event_athub_irq;
95+ struct ras_common_if *ras_if;
96+ const struct amdgpu_nbio_funcs *funcs;
97+};
98+
99+int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev);
100+void amdgpu_nbio_ras_fini(struct amdgpu_device *adev);
101+#endif
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+71−3
@@ -342,6 +342,70 @@ int amdgpu_bo_create_kernel(struct amdgpu_device *adev, · 341 unmodified lines
342342 return 0;
343343 }
344344
345+/**
346+ * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
347+ *
348+ * @adev: amdgpu device object
349+ * @offset: offset of the BO
350+ * @size: size of the BO
351+ * @domain: where to place it
352+ * @bo_ptr: used to initialize BOs in structures
353+ * @cpu_addr: optional CPU address mapping
354+ *
355+ * Creates a kernel BO at a specific offset in the address space of the domain.
356+ *
357+ * Returns:
358+ * 0 on success, negative error code otherwise.
359+ */
360+int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
361+ uint64_t offset, uint64_t size, uint32_t domain,
362+ struct amdgpu_bo **bo_ptr, void **cpu_addr)
363+{
364+ struct ttm_operation_ctx ctx = { false, false };
365+ unsigned int i;
366+ int r;
367+
368+ offset &= PAGE_MASK;
369+ size = ALIGN(size, PAGE_SIZE);
370+
371+ r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr,
372+ NULL, cpu_addr);
373+ if (r)
374+ return r;
375+
376+ /*
377+ * Remove the original mem node and create a new one at the request
378+ * position.
379+ */
380+ if (cpu_addr)
381+ amdgpu_bo_kunmap(*bo_ptr);
382+
383+ ttm_bo_mem_put(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem);
384+
385+ for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
386+ (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
387+ (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
388+ }
389+ r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
390+ &(*bo_ptr)->tbo.mem, &ctx);
391+ if (r)
392+ goto error;
393+
394+ if (cpu_addr) {
395+ r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
396+ if (r)
397+ goto error;
398+ }
399+
400+ amdgpu_bo_unreserve(*bo_ptr);
401+ return 0;
402+
403+error:
404+ amdgpu_bo_unreserve(*bo_ptr);
405+ amdgpu_bo_unref(bo_ptr);
406+ return r;
407+}
408+
345409 /**
346410 * amdgpu_bo_free_kernel - free BO for kernel use
347411 *
@@ -451,9 +515,10 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, · 103 unmodified lines
451515 {
452516 struct ttm_operation_ctx ctx = {
453517 .interruptible = (bp->type != ttm_bo_type_kernel),
454− .no_wait_gpu = false,
518+ .no_wait_gpu = bp->no_wait_gpu,
455519 .resv = bp->resv,
456− .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
520+ .flags = bp->type != ttm_bo_type_kernel ?
521+ TTM_OPT_FLAG_ALLOW_RES_EVICT : 0
457522 };
458523 struct amdgpu_bo *bo;
459524 unsigned long page_align, size = bp->size;
@@ -1058,7 +1123,10 @@ void amdgpu_bo_fini(struct amdgpu_device *adev) · 598 unmodified lines
10581123 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
10591124 struct vm_area_struct *vma)
10601125 {
1061− return ttm_fbdev_mmap(vma, &bo->tbo);
1126+ if (vma->vm_pgoff != 0)
1127+ return -EACCES;
1128+
1129+ return ttm_bo_mmap_obj(vma, &bo->tbo);
10621130 }
10631131
10641132 /**
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h+4−0
@@ -41,6 +41,7 @@ struct amdgpu_bo_param { · 40 unmodified lines
4141 u32 preferred_domain;
4242 u64 flags;
4343 enum ttm_bo_type type;
44+ bool no_wait_gpu;
4445 struct dma_resv *resv;
4546 };
4647
@@ -237,6 +238,9 @@ int amdgpu_bo_create_kernel(struct amdgpu_device *adev, · 190 unmodified lines
237238 unsigned long size, int align,
238239 u32 domain, struct amdgpu_bo **bo_ptr,
239240 u64 *gpu_addr, void **cpu_addr);
241+int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
242+ uint64_t offset, uint64_t size, uint32_t domain,
243+ struct amdgpu_bo **bo_ptr, void **cpu_addr);
240244 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
241245 void **cpu_addr);
242246 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c+36−17
@@ -161,7 +161,7 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev, · 160 unmodified lines
161161
162162 if (is_support_sw_smu(adev)) {
163163 if (adev->smu.ppt_funcs->get_current_power_state)
164− pm = amdgpu_smu_get_current_power_state(adev);
164+ pm = smu_get_current_power_state(&adev->smu);
165165 else
166166 pm = adev->pm.dpm.user_state;
167167 } else if (adev->powerplay.pp_funcs->get_current_power_state) {
@@ -805,8 +805,7 @@ static ssize_t amdgpu_get_pp_feature_status(struct device *dev, · 637 unmodified lines
805805 }
806806
807807 /**
808− * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
809− * pp_dpm_pcie
808+ * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
810809 *
811810 * The amdgpu driver provides a sysfs API for adjusting what power levels
812811 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
@@ -822,9 +821,15 @@ static ssize_t amdgpu_get_pp_feature_status(struct device *dev, · 9 unmodified lines
822821 *
823822 * To manually adjust these states, first select manual using
824823 * power_dpm_force_performance_level.
825− * Secondly,Enter a new value for each level by inputing a string that
824+ * Secondly, enter a new value for each level by inputing a string that
826825 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
827− * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
826+ * E.g.,
827+ *
828+ * .. code-block:: bash
829+ *
830+ * echo "4 5 6" > pp_dpm_sclk
831+ *
832+ * will enable sclk levels 4, 5, and 6.
828833 *
829834 * NOTE: change to the dcefclk max dpm level is not supported now
830835 */
@@ -902,7 +907,7 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, · 71 unmodified lines
902907 return ret;
903908
904909 if (is_support_sw_smu(adev))
905− ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
910+ ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);
906911 else if (adev->powerplay.pp_funcs->force_clock_level)
907912 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
908913
@@ -949,7 +954,7 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, · 40 unmodified lines
949954 return ret;
950955
951956 if (is_support_sw_smu(adev))
952− ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
957+ ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);
953958 else if (adev->powerplay.pp_funcs->force_clock_level)
954959 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
955960
@@ -989,7 +994,7 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, · 33 unmodified lines
989994 return ret;
990995
991996 if (is_support_sw_smu(adev))
992− ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
997+ ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);
993998 else if (adev->powerplay.pp_funcs->force_clock_level)
994999 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
9951000
@@ -1029,7 +1034,7 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, · 33 unmodified lines
10291034 return ret;
10301035
10311036 if (is_support_sw_smu(adev))
1032− ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
1037+ ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);
10331038 else if (adev->powerplay.pp_funcs->force_clock_level)
10341039 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
10351040
@@ -1069,7 +1074,7 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, · 33 unmodified lines
10691074 return ret;
10701075
10711076 if (is_support_sw_smu(adev))
1072− ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
1077+ ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);
10731078 else if (adev->powerplay.pp_funcs->force_clock_level)
10741079 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
10751080
@@ -1109,7 +1114,7 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, · 33 unmodified lines
11091114 return ret;
11101115
11111116 if (is_support_sw_smu(adev))
1112− ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
1117+ ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);
11131118 else if (adev->powerplay.pp_funcs->force_clock_level)
11141119 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
11151120
@@ -1301,7 +1306,7 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, · 185 unmodified lines
13011306 }
13021307 parameter[parameter_size] = profile_mode;
13031308 if (is_support_sw_smu(adev))
1304− ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
1309+ ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
13051310 else if (adev->powerplay.pp_funcs->set_power_profile_mode)
13061311 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
13071312 if (!ret)
@@ -2010,7 +2015,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, · 702 unmodified lines
20102015 uint32_t limit = 0;
20112016
20122017 if (is_support_sw_smu(adev)) {
2013− smu_get_power_limit(&adev->smu, &limit, true);
2018+ smu_get_power_limit(&adev->smu, &limit, true, true);
20142019 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
20152020 } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
20162021 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
@@ -2028,7 +2033,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, · 11 unmodified lines
20282033 uint32_t limit = 0;
20292034
20302035 if (is_support_sw_smu(adev)) {
2031− smu_get_power_limit(&adev->smu, &limit, false);
2036+ smu_get_power_limit(&adev->smu, &limit, false, true);
20322037 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
20332038 } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
20342039 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
@@ -2196,9 +2201,9 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, · 161 unmodified lines
21962201 *
21972202 * - fan1_input: fan speed in RPM
21982203 *
2199− * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
2204+ * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
22002205 *
2201− * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2206+ * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
22022207 *
22032208 * hwmon interfaces for GPU clocks:
22042209 *
@@ -2825,6 +2830,19 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) · 620 unmodified lines
28252830 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
28262831 return ret;
28272832 }
2833+
2834+ /* Arcturus does not support standalone mclk/socclk/fclk level setting */
2835+ if (adev->asic_type == CHIP_ARCTURUS) {
2836+ dev_attr_pp_dpm_mclk.attr.mode &= ~S_IWUGO;
2837+ dev_attr_pp_dpm_mclk.store = NULL;
2838+
2839+ dev_attr_pp_dpm_socclk.attr.mode &= ~S_IWUGO;
2840+ dev_attr_pp_dpm_socclk.store = NULL;
2841+
2842+ dev_attr_pp_dpm_fclk.attr.mode &= ~S_IWUGO;
2843+ dev_attr_pp_dpm_fclk.store = NULL;
2844+ }
2845+
28282846 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
28292847 if (ret) {
28302848 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
@@ -3008,7 +3026,8 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) · 177 unmodified lines
30083026 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
30093027 smu_handle_task(&adev->smu,
30103028 smu_dpm->dpm_level,
3011− AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
3029+ AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
3030+ true);
30123031 } else {
30133032 if (adev->powerplay.pp_funcs->dispatch_tasks) {
30143033 if (!amdgpu_device_has_dc_support(adev)) {
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c+394−40
@@ -34,6 +34,8 @@ · 33 unmodified lines
3434 #include "psp_v11_0.h"
3535 #include "psp_v12_0.h"
3636
37+#include "amdgpu_ras.h"
38+
3739 static void psp_set_funcs(struct amdgpu_device *adev);
3840
3941 static int psp_early_init(void *handle)
@@ -88,6 +90,17 @@ static int psp_sw_init(void *handle) · 48 unmodified lines
8890 return ret;
8991 }
9092
93+ ret = psp_mem_training_init(psp);
94+ if (ret) {
95+ DRM_ERROR("Failed to initialize memory training!\n");
96+ return ret;
97+ }
98+ ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
99+ if (ret) {
100+ DRM_ERROR("Failed to process memory training!\n");
101+ return ret;
102+ }
103+
91104 return 0;
92105 }
93106
@@ -95,6 +108,7 @@ static int psp_sw_fini(void *handle) · 1 unmodified line
95108 {
96109 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
97110
111+ psp_mem_training_fini(&adev->psp);
98112 release_firmware(adev->psp.sos_fw);
99113 adev->psp.sos_fw = NULL;
100114 release_firmware(adev->psp.asd_fw);
@@ -151,10 +165,19 @@ psp_cmd_submit_buf(struct psp_context *psp, · 50 unmodified lines
151165 return ret;
152166 }
153167
168+ amdgpu_asic_invalidate_hdp(psp->adev, NULL);
154169 while (*((unsigned int *)psp->fence_buf) != index) {
155170 if (--timeout == 0)
156171 break;
172+ /*
173+ * Shouldn't wait for timeout when err_event_athub occurs,
174+ * because gpu reset thread triggered and lock resource should
175+ * be released for psp resume sequence.
176+ */
177+ if (amdgpu_ras_intr_triggered())
178+ break;
157179 msleep(1);
180+ amdgpu_asic_invalidate_hdp(psp->adev, NULL);
158181 }
159182
160183 /* In some cases, psp response status is not 0 even there is no
@@ -168,8 +191,9 @@ psp_cmd_submit_buf(struct psp_context *psp, · 7 unmodified lines
168191 if (ucode)
169192 DRM_WARN("failed to load ucode id (%d) ",
170193 ucode->ucode_id);
171− DRM_WARN("psp command failed and response status is (0x%X)\n",
172− psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
194+ DRM_DEBUG_DRIVER("psp command (0x%X) failed and response status is (0x%X)\n",
195+ psp->cmd_buf_mem->cmd_id,
196+ psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
173197 if (!timeout) {
174198 mutex_unlock(&psp->mutex);
175199 return -EINVAL;
@@ -253,7 +277,8 @@ static int psp_tmr_init(struct psp_context *psp) · 77 unmodified lines
253277
254278 /* For ASICs support RLC autoload, psp will parse the toc
255279 * and calculate the total size of TMR needed */
256− if (psp->toc_start_addr &&
280+ if (!amdgpu_sriov_vf(psp->adev) &&
281+ psp->toc_start_addr &&
257282 psp->toc_bin_size &&
258283 psp->fw_pri_buf) {
259284 ret = psp_load_toc(psp, &tmr_size);
@@ -287,15 +312,9 @@ static int psp_tmr_load(struct psp_context *psp) · 27 unmodified lines
287312
288313 ret = psp_cmd_submit_buf(psp, NULL, cmd,
289314 psp->fence_buf_mc_addr);
290− if (ret)
291− goto failed;
292315
293316 kfree(cmd);
294317
295− return 0;
296−
297−failed:
298− kfree(cmd);
299318 return ret;
300319 }
301320
@@ -772,6 +791,324 @@ static int psp_ras_initialize(struct psp_context *psp) · 470 unmodified lines
772791 }
773792 // ras end
774793
794+// HDCP start
795+static void psp_prep_hdcp_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
796+ uint64_t hdcp_ta_mc,
797+ uint64_t hdcp_mc_shared,
798+ uint32_t hdcp_ta_size,
799+ uint32_t shared_size)
800+{
801+ cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
802+ cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(hdcp_ta_mc);
803+ cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(hdcp_ta_mc);
804+ cmd->cmd.cmd_load_ta.app_len = hdcp_ta_size;
805+
806+ cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
807+ lower_32_bits(hdcp_mc_shared);
808+ cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
809+ upper_32_bits(hdcp_mc_shared);
810+ cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
811+}
812+
813+static int psp_hdcp_init_shared_buf(struct psp_context *psp)
814+{
815+ int ret;
816+
817+ /*
818+ * Allocate 16k memory aligned to 4k from Frame Buffer (local
819+ * physical) for hdcp ta <-> Driver
820+ */
821+ ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
822+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
823+ &psp->hdcp_context.hdcp_shared_bo,
824+ &psp->hdcp_context.hdcp_shared_mc_addr,
825+ &psp->hdcp_context.hdcp_shared_buf);
826+
827+ return ret;
828+}
829+
830+static int psp_hdcp_load(struct psp_context *psp)
831+{
832+ int ret;
833+ struct psp_gfx_cmd_resp *cmd;
834+
835+ /*
836+ * TODO: bypass the loading in sriov for now
837+ */
838+ if (amdgpu_sriov_vf(psp->adev))
839+ return 0;
840+
841+ cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
842+ if (!cmd)
843+ return -ENOMEM;
844+
845+ memset(psp->fw_pri_buf, 0, PSP_1_MEG);
846+ memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,
847+ psp->ta_hdcp_ucode_size);
848+
849+ psp_prep_hdcp_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
850+ psp->hdcp_context.hdcp_shared_mc_addr,
851+ psp->ta_hdcp_ucode_size,
852+ PSP_HDCP_SHARED_MEM_SIZE);
853+
854+ ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
855+
856+ if (!ret) {
857+ psp->hdcp_context.hdcp_initialized = 1;
858+ psp->hdcp_context.session_id = cmd->resp.session_id;
859+ }
860+
861+ kfree(cmd);
862+
863+ return ret;
864+}
865+static int psp_hdcp_initialize(struct psp_context *psp)
866+{
867+ int ret;
868+
869+ if (!psp->hdcp_context.hdcp_initialized) {
870+ ret = psp_hdcp_init_shared_buf(psp);
871+ if (ret)
872+ return ret;
873+ }
874+
875+ ret = psp_hdcp_load(psp);
876+ if (ret)
877+ return ret;
878+
879+ return 0;
880+}
881+static void psp_prep_hdcp_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
882+ uint32_t hdcp_session_id)
883+{
884+ cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
885+ cmd->cmd.cmd_unload_ta.session_id = hdcp_session_id;
886+}
887+
888+static int psp_hdcp_unload(struct psp_context *psp)
889+{
890+ int ret;
891+ struct psp_gfx_cmd_resp *cmd;
892+
893+ /*
894+ * TODO: bypass the unloading in sriov for now
895+ */
896+ if (amdgpu_sriov_vf(psp->adev))
897+ return 0;
898+
899+ cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
900+ if (!cmd)
901+ return -ENOMEM;
902+
903+ psp_prep_hdcp_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
904+
905+ ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
906+
907+ kfree(cmd);
908+
909+ return ret;
910+}
911+
912+static void psp_prep_hdcp_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
913+ uint32_t ta_cmd_id,
914+ uint32_t hdcp_session_id)
915+{
916+ cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
917+ cmd->cmd.cmd_invoke_cmd.session_id = hdcp_session_id;
918+ cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
919+ /* Note: cmd_invoke_cmd.buf is not used for now */
920+}
921+
922+int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
923+{
924+ int ret;
925+ struct psp_gfx_cmd_resp *cmd;
926+
927+ /*
928+ * TODO: bypass the loading in sriov for now
929+ */
930+ if (amdgpu_sriov_vf(psp->adev))
931+ return 0;
932+
933+ cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
934+ if (!cmd)
935+ return -ENOMEM;
936+
937+ psp_prep_hdcp_ta_invoke_cmd_buf(cmd, ta_cmd_id,
938+ psp->hdcp_context.session_id);
939+
940+ ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
941+
942+ kfree(cmd);
943+
944+ return ret;
945+}
946+
947+static int psp_hdcp_terminate(struct psp_context *psp)
948+{
949+ int ret;
950+
951+ if (!psp->hdcp_context.hdcp_initialized)
952+ return 0;
953+
954+ ret = psp_hdcp_unload(psp);
955+ if (ret)
956+ return ret;
957+
958+ psp->hdcp_context.hdcp_initialized = 0;
959+
960+ /* free hdcp shared memory */
961+ amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
962+ &psp->hdcp_context.hdcp_shared_mc_addr,
963+ &psp->hdcp_context.hdcp_shared_buf);
964+
965+ return 0;
966+}
967+// HDCP end
968+
969+// DTM start
970+static void psp_prep_dtm_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
971+ uint64_t dtm_ta_mc,
972+ uint64_t dtm_mc_shared,
973+ uint32_t dtm_ta_size,
974+ uint32_t shared_size)
975+{
976+ cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
977+ cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(dtm_ta_mc);
978+ cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(dtm_ta_mc);
979+ cmd->cmd.cmd_load_ta.app_len = dtm_ta_size;
980+
981+ cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(dtm_mc_shared);
982+ cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(dtm_mc_shared);
983+ cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
984+}
985+
986+static int psp_dtm_init_shared_buf(struct psp_context *psp)
987+{
988+ int ret;
989+
990+ /*
991+ * Allocate 16k memory aligned to 4k from Frame Buffer (local
992+ * physical) for dtm ta <-> Driver
993+ */
994+ ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
995+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
996+ &psp->dtm_context.dtm_shared_bo,
997+ &psp->dtm_context.dtm_shared_mc_addr,
998+ &psp->dtm_context.dtm_shared_buf);
999+
1000+ return ret;
1001+}
1002+
1003+static int psp_dtm_load(struct psp_context *psp)
1004+{
1005+ int ret;
1006+ struct psp_gfx_cmd_resp *cmd;
1007+
1008+ /*
1009+ * TODO: bypass the loading in sriov for now
1010+ */
1011+ if (amdgpu_sriov_vf(psp->adev))
1012+ return 0;
1013+
1014+ cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1015+ if (!cmd)
1016+ return -ENOMEM;
1017+
1018+ memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1019+ memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
1020+
1021+ psp_prep_dtm_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
1022+ psp->dtm_context.dtm_shared_mc_addr,
1023+ psp->ta_dtm_ucode_size,
1024+ PSP_DTM_SHARED_MEM_SIZE);
1025+
1026+ ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1027+
1028+ if (!ret) {
1029+ psp->dtm_context.dtm_initialized = 1;
1030+ psp->dtm_context.session_id = cmd->resp.session_id;
1031+ }
1032+
1033+ kfree(cmd);
1034+
1035+ return ret;
1036+}
1037+
1038+static int psp_dtm_initialize(struct psp_context *psp)
1039+{
1040+ int ret;
1041+
1042+ if (!psp->dtm_context.dtm_initialized) {
1043+ ret = psp_dtm_init_shared_buf(psp);
1044+ if (ret)
1045+ return ret;
1046+ }
1047+
1048+ ret = psp_dtm_load(psp);
1049+ if (ret)
1050+ return ret;
1051+
1052+ return 0;
1053+}
1054+
1055+static void psp_prep_dtm_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1056+ uint32_t ta_cmd_id,
1057+ uint32_t dtm_session_id)
1058+{
1059+ cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1060+ cmd->cmd.cmd_invoke_cmd.session_id = dtm_session_id;
1061+ cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1062+ /* Note: cmd_invoke_cmd.buf is not used for now */
1063+}
1064+
1065+int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1066+{
1067+ int ret;
1068+ struct psp_gfx_cmd_resp *cmd;
1069+
1070+ /*
1071+ * TODO: bypass the loading in sriov for now
1072+ */
1073+ if (amdgpu_sriov_vf(psp->adev))
1074+ return 0;
1075+
1076+ cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1077+ if (!cmd)
1078+ return -ENOMEM;
1079+
1080+ psp_prep_dtm_ta_invoke_cmd_buf(cmd, ta_cmd_id,
1081+ psp->dtm_context.session_id);
1082+
1083+ ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1084+
1085+ kfree(cmd);
1086+
1087+ return ret;
1088+}
1089+
1090+static int psp_dtm_terminate(struct psp_context *psp)
1091+{
1092+ int ret;
1093+
1094+ if (!psp->dtm_context.dtm_initialized)
1095+ return 0;
1096+
1097+ ret = psp_hdcp_unload(psp);
1098+ if (ret)
1099+ return ret;
1100+
1101+ psp->dtm_context.dtm_initialized = 0;
1102+
1103+ /* free hdcp shared memory */
1104+ amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
1105+ &psp->dtm_context.dtm_shared_mc_addr,
1106+ &psp->dtm_context.dtm_shared_buf);
1107+
1108+ return 0;
1109+}
1110+// DTM end
1111+
7751112 static int psp_hw_start(struct psp_context *psp)
7761113 {
7771114 struct amdgpu_device *adev = psp->adev;
@@ -845,6 +1182,16 @@ static int psp_hw_start(struct psp_context *psp) · 67 unmodified lines
8451182 if (ret)
8461183 dev_err(psp->adev->dev,
8471184 "RAS: Failed to initialize RAS\n");
1185+
1186+ ret = psp_hdcp_initialize(psp);
1187+ if (ret)
1188+ dev_err(psp->adev->dev,
1189+ "HDCP: Failed to initialize HDCP\n");
1190+
1191+ ret = psp_dtm_initialize(psp);
1192+ if (ret)
1193+ dev_err(psp->adev->dev,
1194+ "DTM: Failed to initialize DTM\n");
8481195 }
8491196
8501197 return 0;
@@ -950,21 +1297,7 @@ static void psp_print_fw_hdr(struct psp_context *psp, · 99 unmodified lines
9501297 struct amdgpu_firmware_info *ucode)
9511298 {
9521299 struct amdgpu_device *adev = psp->adev;
953− const struct sdma_firmware_header_v1_0 *sdma_hdr =
954− (const struct sdma_firmware_header_v1_0 *)
955− adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
956− const struct gfx_firmware_header_v1_0 *ce_hdr =
957− (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
958− const struct gfx_firmware_header_v1_0 *pfp_hdr =
959− (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
960− const struct gfx_firmware_header_v1_0 *me_hdr =
961− (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
962− const struct gfx_firmware_header_v1_0 *mec_hdr =
963− (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
964− const struct rlc_firmware_header_v2_0 *rlc_hdr =
965− (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
966− const struct smc_firmware_header_v1_0 *smc_hdr =
967− (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
1300+ struct common_firmware_header *hdr;
9681301
9691302 switch (ucode->ucode_id) {
9701303 case AMDGPU_UCODE_ID_SDMA0:
@@ -975,25 +1308,33 @@ static void psp_print_fw_hdr(struct psp_context *psp, · 4 unmodified lines
9751308 case AMDGPU_UCODE_ID_SDMA5:
9761309 case AMDGPU_UCODE_ID_SDMA6:
9771310 case AMDGPU_UCODE_ID_SDMA7:
978− amdgpu_ucode_print_sdma_hdr(&sdma_hdr->header);
1311+ hdr = (struct common_firmware_header *)
1312+ adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
1313+ amdgpu_ucode_print_sdma_hdr(hdr);
9791314 break;
9801315 case AMDGPU_UCODE_ID_CP_CE:
981− amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1316+ hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
1317+ amdgpu_ucode_print_gfx_hdr(hdr);
9821318 break;
9831319 case AMDGPU_UCODE_ID_CP_PFP:
984− amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1320+ hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
1321+ amdgpu_ucode_print_gfx_hdr(hdr);
9851322 break;
9861323 case AMDGPU_UCODE_ID_CP_ME:
987− amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1324+ hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
1325+ amdgpu_ucode_print_gfx_hdr(hdr);
9881326 break;
9891327 case AMDGPU_UCODE_ID_CP_MEC1:
990− amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1328+ hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
1329+ amdgpu_ucode_print_gfx_hdr(hdr);
9911330 break;
9921331 case AMDGPU_UCODE_ID_RLC_G:
993− amdgpu_ucode_print_rlc_hdr(&rlc_hdr->header);
1332+ hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
1333+ amdgpu_ucode_print_rlc_hdr(hdr);
9941334 break;
9951335 case AMDGPU_UCODE_ID_SMC:
996− amdgpu_ucode_print_smc_hdr(&smc_hdr->header);
1336+ hdr = (struct common_firmware_header *)adev->pm.fw->data;
1337+ amdgpu_ucode_print_smc_hdr(hdr);
9971338 break;
9981339 default:
9991340 break;
@@ -1079,10 +1420,6 @@ out: · 79 unmodified lines
10791420 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
10801421 /* skip mec JT when autoload is enabled */
10811422 continue;
1082− /* Renoir only needs to load mec jump table one time */
1083− if (adev->asic_type == CHIP_RENOIR &&
1084− ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)
1085− continue;
10861423
10871424 psp_print_fw_hdr(psp, ucode);
10881425
@@ -1091,7 +1428,8 @@ out: · 2 unmodified lines
10911428 return ret;
10921429
10931430 /* Start rlc autoload after psp recieved all the gfx firmware */
1094− if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
1431+ if (psp->autoload_supported && ucode->ucode_id ==
1432+ AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
10951433 ret = psp_rlc_autoload(psp);
10961434 if (ret) {
10971435 DRM_ERROR("Failed to start rlc autoload\n");
@@ -1216,8 +1554,11 @@ static int psp_hw_fini(void *handle) · 118 unmodified lines
12161554 psp->xgmi_context.initialized == 1)
12171555 psp_xgmi_terminate(psp);
12181556
1219− if (psp->adev->psp.ta_fw)
1557+ if (psp->adev->psp.ta_fw) {
12201558 psp_ras_terminate(psp);
1559+ psp_dtm_terminate(psp);
1560+ psp_hdcp_terminate(psp);
1561+ }
12211562
12221563 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
12231564
@@ -1259,6 +1600,16 @@ static int psp_suspend(void *handle) · 35 unmodified lines
12591600 DRM_ERROR("Failed to terminate ras ta\n");
12601601 return ret;
12611602 }
1603+ ret = psp_hdcp_terminate(psp);
1604+ if (ret) {
1605+ DRM_ERROR("Failed to terminate hdcp ta\n");
1606+ return ret;
1607+ }
1608+ ret = psp_dtm_terminate(psp);
1609+ if (ret) {
1610+ DRM_ERROR("Failed to terminate dtm ta\n");
1611+ return ret;
1612+ }
12621613 }
12631614
12641615 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
@@ -1278,6 +1629,12 @@ static int psp_resume(void *handle) · 13 unmodified lines
12781629
12791630 DRM_INFO("PSP is resuming...\n");
12801631
1632+ ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
1633+ if (ret) {
1634+ DRM_ERROR("Failed to process memory training!\n");
1635+ return ret;
1636+ }
1637+
12811638 mutex_lock(&adev->firmware.mutex);
12821639
12831640 ret = psp_hw_start(psp);
@@ -1317,9 +1674,6 @@ int psp_rlc_autoload_start(struct psp_context *psp) · 33 unmodified lines
13171674 int ret;
13181675 struct psp_gfx_cmd_resp *cmd;
13191676
1320− if (amdgpu_sriov_vf(psp->adev))
1321− return 0;
1322−
13231677 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
13241678 if (!cmd)
13251679 return -ENOMEM;
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h+87−0
@@ -37,6 +37,9 @@ · 36 unmodified lines
3737 #define PSP_RAS_SHARED_MEM_SIZE 0x4000
3838 #define PSP_1_MEG 0x100000
3939 #define PSP_TMR_SIZE 0x400000
40+#define PSP_HDCP_SHARED_MEM_SIZE 0x4000
41+#define PSP_DTM_SHARED_MEM_SIZE 0x4000
42+#define PSP_SHARED_MEM_SIZE 0x4000
4043
4144 struct psp_context;
4245 struct psp_xgmi_node_info;
@@ -46,6 +49,8 @@ enum psp_bootloader_cmd { · 3 unmodified lines
4649 PSP_BL__LOAD_SYSDRV = 0x10000,
4750 PSP_BL__LOAD_SOSDRV = 0x20000,
4851 PSP_BL__LOAD_KEY_DATABASE = 0x80000,
52+ PSP_BL__DRAM_LONG_TRAIN = 0x100000,
53+ PSP_BL__DRAM_SHORT_TRAIN = 0x200000,
4954 };
5055
5156 enum psp_ring_type
@@ -108,6 +113,9 @@ struct psp_funcs · 56 unmodified lines
108113 struct ta_ras_trigger_error_input *info);
109114 int (*ras_cure_posion)(struct psp_context *psp, uint64_t *mode_ptr);
110115 int (*rlc_autoload_start)(struct psp_context *psp);
116+ int (*mem_training_init)(struct psp_context *psp);
117+ void (*mem_training_fini)(struct psp_context *psp);
118+ int (*mem_training)(struct psp_context *psp, uint32_t ops);
111119 };
112120
113121 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
@@ -142,6 +150,65 @@ struct psp_ras_context { · 28 unmodified lines
142150 struct amdgpu_ras *ras;
143151 };
144152
153+struct psp_hdcp_context {
154+ bool hdcp_initialized;
155+ uint32_t session_id;
156+ struct amdgpu_bo *hdcp_shared_bo;
157+ uint64_t hdcp_shared_mc_addr;
158+ void *hdcp_shared_buf;
159+};
160+
161+struct psp_dtm_context {
162+ bool dtm_initialized;
163+ uint32_t session_id;
164+ struct amdgpu_bo *dtm_shared_bo;
165+ uint64_t dtm_shared_mc_addr;
166+ void *dtm_shared_buf;
167+};
168+
169+#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
170+#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000
171+#define GDDR6_MEM_TRAINING_OFFSET 0x8000
172+
173+enum psp_memory_training_init_flag {
174+ PSP_MEM_TRAIN_NOT_SUPPORT = 0x0,
175+ PSP_MEM_TRAIN_SUPPORT = 0x1,
176+ PSP_MEM_TRAIN_INIT_FAILED = 0x2,
177+ PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4,
178+ PSP_MEM_TRAIN_INIT_SUCCESS = 0x8,
179+};
180+
181+enum psp_memory_training_ops {
182+ PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1,
183+ PSP_MEM_TRAIN_SAVE = 0x2,
184+ PSP_MEM_TRAIN_RESTORE = 0x4,
185+ PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8,
186+ PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG,
187+ PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG,
188+};
189+
190+struct psp_memory_training_context {
191+ /*training data size*/
192+ u64 train_data_size;
193+ /*
194+ * sys_cache
195+ * cpu virtual address
196+ * system memory buffer that used to store the training data.
197+ */
198+ void *sys_cache;
199+
200+ /*vram offset of the p2c training data*/
201+ u64 p2c_train_data_offset;
202+ struct amdgpu_bo *p2c_bo;
203+
204+ /*vram offset of the c2p training data*/
205+ u64 c2p_train_data_offset;
206+ struct amdgpu_bo *c2p_bo;
207+
208+ enum psp_memory_training_init_flag init;
209+ u32 training_cnt;
210+};
211+
145212 struct psp_context
146213 {
147214 struct amdgpu_device *adev;
@@ -206,9 +273,21 @@ struct psp_context · 58 unmodified lines
206273 uint32_t ta_ras_ucode_version;
207274 uint32_t ta_ras_ucode_size;
208275 uint8_t *ta_ras_start_addr;
276+
277+ uint32_t ta_hdcp_ucode_version;
278+ uint32_t ta_hdcp_ucode_size;
279+ uint8_t *ta_hdcp_start_addr;
280+
281+ uint32_t ta_dtm_ucode_version;
282+ uint32_t ta_dtm_ucode_size;
283+ uint8_t *ta_dtm_start_addr;
284+
209285 struct psp_xgmi_context xgmi_context;
210286 struct psp_ras_context ras;
287+ struct psp_hdcp_context hdcp_context;
288+ struct psp_dtm_context dtm_context;
211289 struct mutex mutex;
290+ struct psp_memory_training_context mem_train_ctx;
212291 };
213292
214293 struct amdgpu_psp_funcs {
@@ -251,6 +330,12 @@ struct amdgpu_psp_funcs { · 36 unmodified lines
251330 (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL)
252331 #define psp_rlc_autoload(psp) \
253332 ((psp)->funcs->rlc_autoload_start ? (psp)->funcs->rlc_autoload_start((psp)) : 0)
333+#define psp_mem_training_init(psp) \
334+ ((psp)->funcs->mem_training_init ? (psp)->funcs->mem_training_init((psp)) : 0)
335+#define psp_mem_training_fini(psp) \
336+ ((psp)->funcs->mem_training_fini ? (psp)->funcs->mem_training_fini((psp)) : 0)
337+#define psp_mem_training(psp, ops) \
338+ ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
254339
255340 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
256341
@@ -279,6 +364,8 @@ int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); · 22 unmodified lines
279364 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
280365 int psp_ras_enable_features(struct psp_context *psp,
281366 union ta_ras_cmd_input *info, bool enable);
367+int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
368+int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
282369
283370 int psp_rlc_autoload_start(struct psp_context *psp);
284371
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c+476−183
@@ -25,10 +25,13 @@ · 24 unmodified lines
2525 #include <linux/list.h>
2626 #include <linux/module.h>
2727 #include <linux/uaccess.h>
28+#include <linux/reboot.h>
29+#include <linux/syscalls.h>
2830
2931 #include "amdgpu.h"
3032 #include "amdgpu_ras.h"
3133 #include "amdgpu_atomfirmware.h"
34+#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
3235
3336 const char *ras_error_string[] = {
3437 "none",
@@ -65,11 +68,16 @@ const char *ras_block_string[] = { · 30 unmodified lines
6568 /* inject address is 52 bits */
6669 #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
6770
68−static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
69− uint64_t offset, uint64_t size,
70− struct amdgpu_bo **bo_ptr);
71−static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
72− struct amdgpu_bo **bo_ptr);
71+enum amdgpu_ras_retire_page_reservation {
72+ AMDGPU_RAS_RETIRE_PAGE_RESERVED,
73+ AMDGPU_RAS_RETIRE_PAGE_PENDING,
74+ AMDGPU_RAS_RETIRE_PAGE_FAULT,
75+};
76+
77+atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
78+
79+static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
80+ uint64_t addr);
7381
7482 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
7583 size_t size, loff_t *pos)
@@ -189,6 +197,10 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, · 113 unmodified lines
189197
190198 return 0;
191199 }
200+
201+static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
202+ struct ras_common_if *head);
203+
192204 /**
193205 * DOC: AMDGPU RAS debugfs control interface
194206 *
@@ -208,31 +220,44 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, · 13 unmodified lines
208220 * As their names indicate, inject operation will write the
209221 * value to the address.
210222 *
211− * Second member: struct ras_debug_if::op.
223+ * The second member: struct ras_debug_if::op.
212224 * It has three kinds of operations.
213− * 0: disable RAS on the block. Take ::head as its data.
214− * 1: enable RAS on the block. Take ::head as its data.
215− * 2: inject errors on the block. Take ::inject as its data.
225+ *
226+ * - 0: disable RAS on the block. Take ::head as its data.
227+ * - 1: enable RAS on the block. Take ::head as its data.
228+ * - 2: inject errors on the block. Take ::inject as its data.
216229 *
217230 * How to use the interface?
218− * programs:
219− * copy the struct ras_debug_if in your codes and initialize it.
220− * write the struct to the control node.
221231 *
222− * bash:
223− * echo op block [error [sub_blcok address value]] > .../ras/ras_ctrl
224− * op: disable, enable, inject
225− * disable: only block is needed
226− * enable: block and error are needed
227− * inject: error, address, value are needed
228− * block: umc, smda, gfx, .........
229− * see ras_block_string[] for details
230− * error: ue, ce
231− * ue: multi_uncorrectable
232− * ce: single_correctable
233− * sub_block: sub block index, pass 0 if there is no sub block
232+ * Programs
233+ *
234+ * Copy the struct ras_debug_if in your codes and initialize it.
235+ * Write the struct to the control node.
236+ *
237+ * Shells
238+ *
239+ * .. code-block:: bash
240+ *
241+ * echo op block [error [sub_block address value]] > .../ras/ras_ctrl
242+ *
243+ * Parameters:
244+ *
245+ * op: disable, enable, inject
246+ * disable: only block is needed
247+ * enable: block and error are needed
248+ * inject: error, address, value are needed
249+ * block: umc, sdma, gfx, .........
250+ * see ras_block_string[] for details
251+ * error: ue, ce
252+ * ue: multi_uncorrectable
253+ * ce: single_correctable
254+ * sub_block:
255+ * sub block index, pass 0 if there is no sub block
256+ *
257+ * here are some examples for bash commands:
258+ *
259+ * .. code-block:: bash
234260 *
235− * here are some examples for bash commands,
236261 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
237262 * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
238263 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
@@ -245,8 +270,11 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, · 6 unmodified lines
245270 * For inject, please check corresponding err count at
246271 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
247272 *
248− * NOTE: operation is only allowed on blocks which are supported.
249− * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
273+ * .. note::
274+ * Operations are only allowed on blocks which are supported.
275+ * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
276+ * to see which blocks support RAS on a particular asic.
277+ *
250278 */
251279 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
252280 size_t size, loff_t *pos)
@@ -276,6 +304,14 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user * · 23 unmodified lines
276304 break;
277305 }
278306
307+ /* umc ce/ue error injection for a bad page is not allowed */
308+ if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
309+ amdgpu_ras_check_bad_page(adev, data.inject.address)) {
310+ DRM_WARN("RAS WARN: 0x%llx has been marked as bad before error injection!\n",
311+ data.inject.address);
312+ break;
313+ }
314+
279315 /* data.inject.address is offset instead of absolute gpu address */
280316 ret = amdgpu_ras_error_inject(adev, &data.inject);
281317 break;
@@ -290,6 +326,33 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user * · 8 unmodified lines
290326 return size;
291327 }
292328
329+/**
330+ * DOC: AMDGPU RAS debugfs EEPROM table reset interface
331+ *
332+ * Some boards contain an EEPROM which is used to persistently store a list of
333+ * bad pages which experiences ECC errors in vram. This interface provides
334+ * a way to reset the EEPROM, e.g., after testing error injection.
335+ *
336+ * Usage:
337+ *
338+ * .. code-block:: bash
339+ *
340+ * echo 1 > ../ras/ras_eeprom_reset
341+ *
342+ * will reset EEPROM table to 0 entries.
343+ *
344+ */
345+static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
346+ size_t size, loff_t *pos)
347+{
348+ struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
349+ int ret;
350+
351+ ret = amdgpu_ras_eeprom_reset_table(&adev->psp.ras.ras->eeprom_control);
352+
353+ return ret == 1 ? size : -EIO;
354+}
355+
293356 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
294357 .owner = THIS_MODULE,
295358 .read = NULL,
@@ -297,6 +360,34 @@ static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { · 1 unmodified line
297360 .llseek = default_llseek
298361 };
299362
363+static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
364+ .owner = THIS_MODULE,
365+ .read = NULL,
366+ .write = amdgpu_ras_debugfs_eeprom_write,
367+ .llseek = default_llseek
368+};
369+
370+/**
371+ * DOC: AMDGPU RAS sysfs Error Count Interface
372+ *
373+ * It allows the user to read the error count for each IP block on the gpu through
374+ * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
375+ *
376+ * It outputs the multiple lines which report the uncorrected (ue) and corrected
377+ * (ce) error counts.
378+ *
379+ * The format of one line is below,
380+ *
381+ * [ce|ue]: count
382+ *
383+ * Example:
384+ *
385+ * .. code-block:: bash
386+ *
387+ * ue: 0
388+ * ce: 1
389+ *
390+ */
300391 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
301392 struct device_attribute *attr, char *buf)
302393 {
@@ -475,15 +566,17 @@ int amdgpu_ras_feature_enable(struct amdgpu_device *adev, · 172 unmodified lines
475566 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
476567 return 0;
477568
478− ret = psp_ras_enable_features(&adev->psp, &info, enable);
479− if (ret) {
480− DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n",
481− enable ? "enable":"disable",
482− ras_block_str(head->block),
483− ret);
484− if (ret == TA_RAS_STATUS__RESET_NEEDED)
485− return -EAGAIN;
486− return -EINVAL;
569+ if (!amdgpu_ras_intr_triggered()) {
570+ ret = psp_ras_enable_features(&adev->psp, &info, enable);
571+ if (ret) {
572+ DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n",
573+ enable ? "enable":"disable",
574+ ras_block_str(head->block),
575+ ret);
576+ if (ret == TA_RAS_STATUS__RESET_NEEDED)
577+ return -EAGAIN;
578+ return -EINVAL;
579+ }
487580 }
488581
489582 /* setup the obj */
@@ -615,8 +708,12 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev, · 125 unmodified lines
615708 adev->gfx.funcs->query_ras_error_count(adev, &err_data);
616709 break;
617710 case AMDGPU_RAS_BLOCK__MMHUB:
618− if (adev->mmhub_funcs->query_ras_error_count)
619− adev->mmhub_funcs->query_ras_error_count(adev, &err_data);
711+ if (adev->mmhub.funcs->query_ras_error_count)
712+ adev->mmhub.funcs->query_ras_error_count(adev, &err_data);
713+ break;
714+ case AMDGPU_RAS_BLOCK__PCIE_BIF:
715+ if (adev->nbio.funcs->query_ras_error_count)
716+ adev->nbio.funcs->query_ras_error_count(adev, &err_data);
620717 break;
621718 default:
622719 break;
@@ -628,12 +725,14 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev, · 5 unmodified lines
628725 info->ue_count = obj->err_data.ue_count;
629726 info->ce_count = obj->err_data.ce_count;
630727
631− if (err_data.ce_count)
728+ if (err_data.ce_count) {
632729 dev_info(adev->dev, "%ld correctable errors detected in %s block\n",
633730 obj->err_data.ce_count, ras_block_str(info->head.block));
634− if (err_data.ue_count)
731+ }
732+ if (err_data.ue_count) {
635733 dev_info(adev->dev, "%ld uncorrectable errors detected in %s block\n",
636734 obj->err_data.ue_count, ras_block_str(info->head.block));
735+ }
637736
638737 return 0;
639738 }
@@ -664,6 +763,8 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev, · 24 unmodified lines
664763 break;
665764 case AMDGPU_RAS_BLOCK__UMC:
666765 case AMDGPU_RAS_BLOCK__MMHUB:
766+ case AMDGPU_RAS_BLOCK__XGMI_WAFL:
767+ case AMDGPU_RAS_BLOCK__PCIE_BIF:
667768 ret = psp_ras_trigger_error(&adev->psp, &block_info);
668769 break;
669770 default:
@@ -723,18 +824,18 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, · 53 unmodified lines
723824 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
724825 {
725826 switch (flags) {
726− case 0:
827+ case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
727828 return "R";
728− case 1:
829+ case AMDGPU_RAS_RETIRE_PAGE_PENDING:
729830 return "P";
730− case 2:
831+ case AMDGPU_RAS_RETIRE_PAGE_FAULT:
731832 default:
732833 return "F";
733834 };
734835 }
735836
736−/*
737− * DOC: ras sysfs gpu_vram_bad_pages interface
837+/**
838+ * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
738839 *
739840 * It allows user to read the bad pages of vram on the gpu through
740841 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
@@ -746,14 +847,21 @@ static char *amdgpu_ras_badpage_flags_str(unsigned int flags) · 5 unmodified lines
746847 *
747848 * gpu pfn and gpu page size are printed in hex format.
748849 * flags can be one of below character,
850+ *
749851 * R: reserved, this gpu page is reserved and not able to use.
852+ *
750853 * P: pending for reserve, this gpu page is marked as bad, will be reserved
751− * in next window of page_reserve.
854+ * in next window of page_reserve.
855+ *
752856 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
753857 *
754− * examples:
755− * 0x00000001 : 0x00001000 : R
756− * 0x00000002 : 0x00001000 : P
858+ * Examples:
859+ *
860+ * .. code-block:: bash
861+ *
862+ * 0x00000001 : 0x00001000 : R
863+ * 0x00000002 : 0x00001000 : P
864+ *
757865 */
758866
759867 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
@@ -927,6 +1035,24 @@ static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) · 167 unmodified lines
9271035 }
9281036 /* sysfs end */
9291037
1038+/**
1039+ * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1040+ *
1041+ * Normally when there is an uncorrectable error, the driver will reset
1042+ * the GPU to recover. However, in the event of an unrecoverable error,
1043+ * the driver provides an interface to reboot the system automatically
1044+ * in that event.
1045+ *
1046+ * The following file in debugfs provides that interface:
1047+ * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1048+ *
1049+ * Usage:
1050+ *
1051+ * .. code-block:: bash
1052+ *
1053+ * echo true > .../ras/auto_reboot
1054+ *
1055+ */
9301056 /* debugfs begin */
9311057 static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
9321058 {
@@ -934,8 +1060,21 @@ static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) · 1 unmodified line
9341060 struct drm_minor *minor = adev->ddev->primary;
9351061
9361062 con->dir = debugfs_create_dir("ras", minor->debugfs_root);
937− con->ent = debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir,
938− adev, &amdgpu_ras_debugfs_ctrl_ops);
1063+ debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir,
1064+ adev, &amdgpu_ras_debugfs_ctrl_ops);
1065+ debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir,
1066+ adev, &amdgpu_ras_debugfs_eeprom_ops);
1067+
1068+ /*
1069+ * After one uncorrectable error happens, usually GPU recovery will
1070+ * be scheduled. But due to the known problem in GPU recovery failing
1071+ * to bring GPU back, below interface provides one direct way to
1072+ * user to reboot system automatically in such case within
1073+ * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1074+ * will never be called.
1075+ */
1076+ debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, con->dir,
1077+ &con->reboot);
9391078 }
9401079
9411080 void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
@@ -980,10 +1119,8 @@ static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) · 38 unmodified lines
9801119 amdgpu_ras_debugfs_remove(adev, &obj->head);
9811120 }
9821121
983− debugfs_remove(con->ent);
984− debugfs_remove(con->dir);
1122+ debugfs_remove_recursive(con->dir);
9851123 con->dir = NULL;
986− con->ent = NULL;
9871124 }
9881125 /* debugfs end */
9891126
@@ -1188,15 +1325,15 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, · 198 unmodified lines
11881325
11891326 for (; i < data->count; i++) {
11901327 (*bps)[i] = (struct ras_badpage){
1191− .bp = data->bps[i].bp,
1328+ .bp = data->bps[i].retired_page,
11921329 .size = AMDGPU_GPU_PAGE_SIZE,
1193− .flags = 0,
1330+ .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
11941331 };
11951332
11961333 if (data->last_reserved <= i)
1197− (*bps)[i].flags = 1;
1198− else if (data->bps[i].bo == NULL)
1199− (*bps)[i].flags = 2;
1334+ (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1335+ else if (data->bps_bo[i] == NULL)
1336+ (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
12001337 }
12011338
12021339 *count = data->count;
@@ -1214,105 +1351,46 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) · 11 unmodified lines
12141351 atomic_set(&ras->in_recovery, 0);
12151352 }
12161353
1217−static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
1218− struct amdgpu_bo **bo_ptr)
1219−{
1220− /* no need to free it actually. */
1221− amdgpu_bo_free_kernel(bo_ptr, NULL, NULL);
1222− return 0;
1223−}
1224−
1225−/* reserve vram with size@offset */
1226−static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
1227− uint64_t offset, uint64_t size,
1228− struct amdgpu_bo **bo_ptr)
1229−{
1230− struct ttm_operation_ctx ctx = { false, false };
1231− struct amdgpu_bo_param bp;
1232− int r = 0;
1233− int i;
1234− struct amdgpu_bo *bo;
1235−
1236− if (bo_ptr)
1237− *bo_ptr = NULL;
1238− memset(&bp, 0, sizeof(bp));
1239− bp.size = size;
1240− bp.byte_align = PAGE_SIZE;
1241− bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1242− bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
1243− AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
1244− bp.type = ttm_bo_type_kernel;
1245− bp.resv = NULL;
1246−
1247− r = amdgpu_bo_create(adev, &bp, &bo);
1248− if (r)
1249− return -EINVAL;
1250−
1251− r = amdgpu_bo_reserve(bo, false);
1252− if (r)
1253− goto error_reserve;
1254−
1255− offset = ALIGN(offset, PAGE_SIZE);
1256− for (i = 0; i < bo->placement.num_placement; ++i) {
1257− bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1258− bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1259− }
1260−
1261− ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1262− r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem, &ctx);
1263− if (r)
1264− goto error_pin;
1265−
1266− r = amdgpu_bo_pin_restricted(bo,
1267− AMDGPU_GEM_DOMAIN_VRAM,
1268− offset,
1269− offset + size);
1270− if (r)
1271− goto error_pin;
1272−
1273− if (bo_ptr)
1274− *bo_ptr = bo;
1275−
1276− amdgpu_bo_unreserve(bo);
1277− return r;
1278−
1279−error_pin:
1280− amdgpu_bo_unreserve(bo);
1281−error_reserve:
1282− amdgpu_bo_unref(&bo);
1283− return r;
1284−}
1285−
12861354 /* alloc/realloc bps array */
12871355 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
12881356 struct ras_err_handler_data *data, int pages)
12891357 {
12901358 unsigned int old_space = data->count + data->space_left;
12911359 unsigned int new_space = old_space + pages;
1292− unsigned int align_space = ALIGN(new_space, 1024);
1293− void *tmp = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1294−
1295− if (!tmp)
1360+ unsigned int align_space = ALIGN(new_space, 512);
1361+ void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1362+ struct amdgpu_bo **bps_bo =
1363+ kmalloc(align_space * sizeof(*data->bps_bo), GFP_KERNEL);
1364+
1365+ if (!bps || !bps_bo) {
1366+ kfree(bps);
1367+ kfree(bps_bo);
12961368 return -ENOMEM;
1369+ }
12971370
12981371 if (data->bps) {
1299− memcpy(tmp, data->bps,
1372+ memcpy(bps, data->bps,
13001373 data->count * sizeof(*data->bps));
13011374 kfree(data->bps);
13021375 }
1376+ if (data->bps_bo) {
1377+ memcpy(bps_bo, data->bps_bo,
1378+ data->count * sizeof(*data->bps_bo));
1379+ kfree(data->bps_bo);
1380+ }
13031381
1304− data->bps = tmp;
1382+ data->bps = bps;
1383+ data->bps_bo = bps_bo;
13051384 data->space_left += align_space - old_space;
13061385 return 0;
13071386 }
13081387
13091388 /* it deal with vram only. */
13101389 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1311− unsigned long *bps, int pages)
1390+ struct eeprom_table_record *bps, int pages)
13121391 {
13131392 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
13141393 struct ras_err_handler_data *data;
1315− int i = pages;
13161394 int ret = 0;
13171395
13181396 if (!con || !con->eh_data || !bps || pages <= 0)
@@ -1329,24 +1407,120 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, · 10 unmodified lines
13291407 goto out;
13301408 }
13311409
1332− while (i--)
1333− data->bps[data->count++].bp = bps[i];
1334−
1410+ memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps));
1411+ data->count += pages;
13351412 data->space_left -= pages;
1413+
13361414 out:
13371415 mutex_unlock(&con->recovery_lock);
13381416
13391417 return ret;
13401418 }
13411419
1420+/*
1421+ * write error record array to eeprom, the function should be
1422+ * protected by recovery_lock
1423+ */
1424+static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1425+{
1426+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1427+ struct ras_err_handler_data *data;
1428+ struct amdgpu_ras_eeprom_control *control;
1429+ int save_count;
1430+
1431+ if (!con || !con->eh_data)
1432+ return 0;
1433+
1434+ control = &con->eeprom_control;
1435+ data = con->eh_data;
1436+ save_count = data->count - control->num_recs;
1437+ /* only new entries are saved */
1438+ if (save_count > 0)
1439+ if (amdgpu_ras_eeprom_process_recods(control,
1440+ &data->bps[control->num_recs],
1441+ true,
1442+ save_count)) {
1443+ DRM_ERROR("Failed to save EEPROM table data!");
1444+ return -EIO;
1445+ }
1446+
1447+ return 0;
1448+}
1449+
1450+/*
1451+ * read error record array in eeprom and reserve enough space for
1452+ * storing new bad pages
1453+ */
1454+static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1455+{
1456+ struct amdgpu_ras_eeprom_control *control =
1457+ &adev->psp.ras.ras->eeprom_control;
1458+ struct eeprom_table_record *bps = NULL;
1459+ int ret = 0;
1460+
1461+ /* no bad page record, skip eeprom access */
1462+ if (!control->num_recs)
1463+ return ret;
1464+
1465+ bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1466+ if (!bps)
1467+ return -ENOMEM;
1468+
1469+ if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1470+ control->num_recs)) {
1471+ DRM_ERROR("Failed to load EEPROM table records!");
1472+ ret = -EIO;
1473+ goto out;
1474+ }
1475+
1476+ ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1477+
1478+out:
1479+ kfree(bps);
1480+ return ret;
1481+}
1482+
1483+/*
1484+ * check if an address belongs to bad page
1485+ *
1486+ * Note: this check is only for umc block
1487+ */
1488+static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1489+ uint64_t addr)
1490+{
1491+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1492+ struct ras_err_handler_data *data;
1493+ int i;
1494+ bool ret = false;
1495+
1496+ if (!con || !con->eh_data)
1497+ return ret;
1498+
1499+ mutex_lock(&con->recovery_lock);
1500+ data = con->eh_data;
1501+ if (!data)
1502+ goto out;
1503+
1504+ addr >>= AMDGPU_GPU_PAGE_SHIFT;
1505+ for (i = 0; i < data->count; i++)
1506+ if (addr == data->bps[i].retired_page) {
1507+ ret = true;
1508+ goto out;
1509+ }
1510+
1511+out:
1512+ mutex_unlock(&con->recovery_lock);
1513+ return ret;
1514+}
1515+
13421516 /* called in gpu recovery/init */
13431517 int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
13441518 {
13451519 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
13461520 struct ras_err_handler_data *data;
13471521 uint64_t bp;
1348− struct amdgpu_bo *bo;
1349− int i;
1522+ struct amdgpu_bo *bo = NULL;
1523+ int i, ret = 0;
13501524
13511525 if (!con || !con->eh_data)
13521526 return 0;
@@ -1357,18 +1531,29 @@ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev) · 4 unmodified lines
13571531 goto out;
13581532 /* reserve vram at driver post stage. */
13591533 for (i = data->last_reserved; i < data->count; i++) {
1360− bp = data->bps[i].bp;
1534+ bp = data->bps[i].retired_page;
13611535
1362− if (amdgpu_ras_reserve_vram(adev, bp << PAGE_SHIFT,
1363− PAGE_SIZE, &bo))
1364− DRM_ERROR("RAS ERROR: reserve vram %llx fail\n", bp);
1536+ /* There are two cases of reserve error should be ignored:
1537+ * 1) a ras bad page has been allocated (used by someone);
1538+ * 2) a ras bad page has been reserved (duplicate error injection
1539+ * for one page);
1540+ */
1541+ if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,
1542+ AMDGPU_GPU_PAGE_SIZE,
1543+ AMDGPU_GEM_DOMAIN_VRAM,
1544+ &bo, NULL))
1545+ DRM_WARN("RAS WARN: reserve vram for retired page %llx fail\n", bp);
13651546
1366− data->bps[i].bo = bo;
1547+ data->bps_bo[i] = bo;
13671548 data->last_reserved = i + 1;
1549+ bo = NULL;
13681550 }
1551+
1552+ /* continue to save bad pages to eeprom even reesrve_vram fails */
1553+ ret = amdgpu_ras_save_bad_pages(adev);
13691554 out:
13701555 mutex_unlock(&con->recovery_lock);
1371− return 0;
1556+ return ret;
13721557 }
13731558
13741559 /* called when driver unload */
@@ -1388,11 +1573,11 @@ static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev) · 13 unmodified lines
13881573 goto out;
13891574
13901575 for (i = data->last_reserved - 1; i >= 0; i--) {
1391− bo = data->bps[i].bo;
1576+ bo = data->bps_bo[i];
13921577
1393− amdgpu_ras_release_vram(adev, &bo);
1578+ amdgpu_bo_free_kernel(&bo, NULL, NULL);
13941579
1395− data->bps[i].bo = bo;
1580+ data->bps_bo[i] = bo;
13961581 data->last_reserved = i;
13971582 }
13981583 out:
@@ -1400,41 +1585,54 @@ out: · 1 unmodified line
14001585 return 0;
14011586 }
14021587
1403−static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1404−{
1405− /* TODO
1406− * write the array to eeprom when SMU disabled.
1407− */
1408− return 0;
1409−}
1410−
1411−static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1412−{
1413− /* TODO
1414− * read the array to eeprom when SMU disabled.
1415− */
1416− return 0;
1417−}
1418−
1419−static int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1588+int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
14201589 {
14211590 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1422− struct ras_err_handler_data **data = &con->eh_data;
1591+ struct ras_err_handler_data **data;
1592+ int ret;
14231593
1424− *data = kmalloc(sizeof(**data),
1425− GFP_KERNEL|__GFP_ZERO);
1426− if (!*data)
1427− return -ENOMEM;
1594+ if (con)
1595+ data = &con->eh_data;
1596+ else
1597+ return 0;
1598+
1599+ *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1600+ if (!*data) {
1601+ ret = -ENOMEM;
1602+ goto out;
1603+ }
14281604
14291605 mutex_init(&con->recovery_lock);
14301606 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
14311607 atomic_set(&con->in_recovery, 0);
14321608 con->adev = adev;
14331609
1434− amdgpu_ras_load_bad_pages(adev);
1435− amdgpu_ras_reserve_bad_pages(adev);
1610+ ret = amdgpu_ras_eeprom_init(&con->eeprom_control);
1611+ if (ret)
1612+ goto free;
1613+
1614+ if (con->eeprom_control.num_recs) {
1615+ ret = amdgpu_ras_load_bad_pages(adev);
1616+ if (ret)
1617+ goto free;
1618+ ret = amdgpu_ras_reserve_bad_pages(adev);
1619+ if (ret)
1620+ goto release;
1621+ }
14361622
14371623 return 0;
1624+
1625+release:
1626+ amdgpu_ras_release_bad_pages(adev);
1627+free:
1628+ kfree((*data)->bps);
1629+ kfree((*data)->bps_bo);
1630+ kfree(*data);
1631+ con->eh_data = NULL;
1632+out:
1633+ DRM_WARN("Failed to initialize ras recovery!\n");
1634+
1635+ return ret;
14381636 }
14391637
14401638 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
@@ -1442,13 +1640,17 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) · 1 unmodified line
14421640 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
14431641 struct ras_err_handler_data *data = con->eh_data;
14441642
1643+ /* recovery_init failed to init it, fini is useless */
1644+ if (!data)
1645+ return 0;
1646+
14451647 cancel_work_sync(&con->recovery_work);
1446− amdgpu_ras_save_bad_pages(adev);
14471648 amdgpu_ras_release_bad_pages(adev);
14481649
14491650 mutex_lock(&con->recovery_lock);
14501651 con->eh_data = NULL;
14511652 kfree(data->bps);
1653+ kfree(data->bps_bo);
14521654 kfree(data);
14531655 mutex_unlock(&con->recovery_lock);
14541656
@@ -1500,6 +1702,7 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev, · 45 unmodified lines
15001702 int amdgpu_ras_init(struct amdgpu_device *adev)
15011703 {
15021704 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1705+ int r;
15031706
15041707 if (con)
15051708 return 0;
@@ -1527,31 +1730,106 @@ int amdgpu_ras_init(struct amdgpu_device *adev) · 21 unmodified lines
15271730 /* Might need get this flag from vbios. */
15281731 con->flags = RAS_DEFAULT_FLAGS;
15291732
1530− if (amdgpu_ras_recovery_init(adev))
1531− goto recovery_out;
1733+ if (adev->nbio.funcs->init_ras_controller_interrupt) {
1734+ r = adev->nbio.funcs->init_ras_controller_interrupt(adev);
1735+ if (r)
1736+ return r;
1737+ }
1738+
1739+ if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) {
1740+ r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev);
1741+ if (r)
1742+ return r;
1743+ }
15321744
15331745 amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK;
15341746
15351747 if (amdgpu_ras_fs_init(adev))
15361748 goto fs_out;
15371749
1538− /* ras init for each ras block */
1539− if (adev->umc.funcs->ras_init)
1540− adev->umc.funcs->ras_init(adev);
1541−
15421750 DRM_INFO("RAS INFO: ras initialized successfully, "
15431751 "hardware ability[%x] ras_mask[%x]\n",
15441752 con->hw_supported, con->supported);
15451753 return 0;
15461754 fs_out:
1547− amdgpu_ras_recovery_fini(adev);
1548−recovery_out:
15491755 amdgpu_ras_set_context(adev, NULL);
15501756 kfree(con);
15511757
15521758 return -EINVAL;
15531759 }
15541760
1761+/* helper function to handle common stuff in ip late init phase */
1762+int amdgpu_ras_late_init(struct amdgpu_device *adev,
1763+ struct ras_common_if *ras_block,
1764+ struct ras_fs_if *fs_info,
1765+ struct ras_ih_if *ih_info)
1766+{
1767+ int r;
1768+
1769+ /* disable RAS feature per IP block if it is not supported */
1770+ if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
1771+ amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
1772+ return 0;
1773+ }
1774+
1775+ r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
1776+ if (r) {
1777+ if (r == -EAGAIN) {
1778+ /* request gpu reset. will run again */
1779+ amdgpu_ras_request_reset_on_boot(adev,
1780+ ras_block->block);
1781+ return 0;
1782+ } else if (adev->in_suspend || adev->in_gpu_reset) {
1783+ /* in resume phase, if fail to enable ras,
1784+ * clean up all ras fs nodes, and disable ras */
1785+ goto cleanup;
1786+ } else
1787+ return r;
1788+ }
1789+
1790+ /* in resume phase, no need to create ras fs node */
1791+ if (adev->in_suspend || adev->in_gpu_reset)
1792+ return 0;
1793+
1794+ if (ih_info->cb) {
1795+ r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
1796+ if (r)
1797+ goto interrupt;
1798+ }
1799+
1800+ amdgpu_ras_debugfs_create(adev, fs_info);
1801+
1802+ r = amdgpu_ras_sysfs_create(adev, fs_info);
1803+ if (r)
1804+ goto sysfs;
1805+
1806+ return 0;
1807+cleanup:
1808+ amdgpu_ras_sysfs_remove(adev, ras_block);
1809+sysfs:
1810+ amdgpu_ras_debugfs_remove(adev, ras_block);
1811+ if (ih_info->cb)
1812+ amdgpu_ras_interrupt_remove_handler(adev, ih_info);
1813+interrupt:
1814+ amdgpu_ras_feature_enable(adev, ras_block, 0);
1815+ return r;
1816+}
1817+
1818+/* helper function to remove ras fs node and interrupt handler */
1819+void amdgpu_ras_late_fini(struct amdgpu_device *adev,
1820+ struct ras_common_if *ras_block,
1821+ struct ras_ih_if *ih_info)
1822+{
1823+ if (!ras_block || !ih_info)
1824+ return;
1825+
1826+ amdgpu_ras_sysfs_remove(adev, ras_block);
1827+ amdgpu_ras_debugfs_remove(adev, ras_block);
1828+ if (ih_info->cb)
1829+ amdgpu_ras_interrupt_remove_handler(adev, ih_info);
1830+ amdgpu_ras_feature_enable(adev, ras_block, 0);
1831+}
1832+
15551833 /* do some init work after IP late init as dependence.
15561834 * and it runs in resume/gpu reset/booting up cases.
15571835 */
@@ -1645,3 +1923,18 @@ int amdgpu_ras_fini(struct amdgpu_device *adev) · 87 unmodified lines
16451923
16461924 return 0;
16471925 }
1926+
1927+void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
1928+{
1929+ uint32_t hw_supported, supported;
1930+
1931+ amdgpu_ras_check_supported(adev, &hw_supported, &supported);
1932+ if (!hw_supported)
1933+ return;
1934+
1935+ if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
1936+ DRM_WARN("RAS event of type ERREVENT_ATHUB_INTERRUPT detected!\n");
1937+
1938+ amdgpu_ras_reset_gpu(adev, false);
1939+ }
1940+}
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h+32−11
@@ -317,8 +317,6 @@ struct amdgpu_ras { · 316 unmodified lines
317317 struct list_head head;
318318 /* debugfs */
319319 struct dentry *dir;
320− /* debugfs ctrl */
321− struct dentry *ent;
322320 /* sysfs */
323321 struct device_attribute features_attr;
324322 struct bin_attribute badpages_attr;
@@ -334,7 +332,7 @@ struct amdgpu_ras { · 9 unmodified lines
334332 struct mutex recovery_lock;
335333
336334 uint32_t flags;
337−
335+ bool reboot;
338336 struct amdgpu_ras_eeprom_control eeprom_control;
339337 };
340338
@@ -347,15 +345,14 @@ struct ras_err_data { · 6 unmodified lines
347345 unsigned long ue_count;
348346 unsigned long ce_count;
349347 unsigned long err_addr_cnt;
350− uint64_t *err_addr;
348+ struct eeprom_table_record *err_addr;
351349 };
352350
353351 struct ras_err_handler_data {
354− /* point to bad pages array */
355− struct {
356− unsigned long bp;
357− struct amdgpu_bo *bo;
358− } *bps;
352+ /* point to bad page records array */
353+ struct eeprom_table_record *bps;
354+ /* point to reserved bo array */
355+ struct amdgpu_bo **bps_bo;
359356 /* the count of entries */
360357 int count;
361358 /* the space can place new entries */
@@ -365,7 +362,7 @@ struct ras_err_handler_data { · 3 unmodified lines
365362 };
366363
367364 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
368− struct ras_err_data *err_data,
365+ void *err_data,
369366 struct amdgpu_iv_entry *entry);
370367
371368 struct ras_ih_data {
@@ -481,6 +478,7 @@ static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev, · 109 unmodified lines
481478 return ras && (ras->supported & (1 << block));
482479 }
483480
481+int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
484482 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
485483 unsigned int block);
486484
@@ -492,7 +490,7 @@ unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, · 5 unmodified lines
492490
493491 /* error handling functions */
494492 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
495− unsigned long *bps, int pages);
493+ struct eeprom_table_record *bps, int pages);
496494
497495 int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev);
498496
@@ -501,6 +499,12 @@ static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev, · 2 unmodified lines
501499 {
502500 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
503501
502+ /* save bad page to eeprom before gpu reset,
503+ * i2c may be unstable in gpu reset
504+ */
505+ if (in_task())
506+ amdgpu_ras_reserve_bad_pages(adev);
507+
504508 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
505509 schedule_work(&ras->recovery_work);
506510 return 0;
@@ -566,6 +570,13 @@ amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { · 59 unmodified lines
566570 int amdgpu_ras_init(struct amdgpu_device *adev);
567571 int amdgpu_ras_fini(struct amdgpu_device *adev);
568572 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
573+int amdgpu_ras_late_init(struct amdgpu_device *adev,
574+ struct ras_common_if *ras_block,
575+ struct ras_fs_if *fs_info,
576+ struct ras_ih_if *ih_info);
577+void amdgpu_ras_late_fini(struct amdgpu_device *adev,
578+ struct ras_common_if *ras_block,
579+ struct ras_ih_if *ih_info);
569580
570581 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
571582 struct ras_common_if *head, bool enable);
@@ -599,4 +610,14 @@ int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, · 27 unmodified lines
599610
600611 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
601612 struct ras_dispatch_if *info);
613+
614+extern atomic_t amdgpu_ras_in_intr;
615+
616+static inline bool amdgpu_ras_intr_triggered(void)
617+{
618+ return !!atomic_read(&amdgpu_ras_in_intr);
619+}
620+
621+void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
622+
602623 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c+117−92
@@ -100,7 +100,101 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control, · 99 unmodified lines
100100 return ret;
101101 }
102102
103−static uint32_t __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control);
103+
104+
105+static uint32_t __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control)
106+{
107+ int i;
108+ uint32_t tbl_sum = 0;
109+
110+ /* Header checksum, skip checksum field in the calculation */
111+ for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++)
112+ tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i);
113+
114+ return tbl_sum;
115+}
116+
117+static uint32_t __calc_recs_byte_sum(struct eeprom_table_record *records,
118+ int num)
119+{
120+ int i, j;
121+ uint32_t tbl_sum = 0;
122+
123+ /* Records checksum */
124+ for (i = 0; i < num; i++) {
125+ struct eeprom_table_record *record = &records[i];
126+
127+ for (j = 0; j < sizeof(*record); j++) {
128+ tbl_sum += *(((unsigned char *)record) + j);
129+ }
130+ }
131+
132+ return tbl_sum;
133+}
134+
135+static inline uint32_t __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,
136+ struct eeprom_table_record *records, int num)
137+{
138+ return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num);
139+}
140+
141+/* Checksum = 256 -((sum of all table entries) mod 256) */
142+static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
143+ struct eeprom_table_record *records, int num,
144+ uint32_t old_hdr_byte_sum)
145+{
146+ /*
147+ * This will update the table sum with new records.
148+ *
149+ * TODO: What happens when the EEPROM table is to be wrapped around
150+ * and old records from start will get overridden.
151+ */
152+
153+ /* need to recalculate updated header byte sum */
154+ control->tbl_byte_sum -= old_hdr_byte_sum;
155+ control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num);
156+
157+ control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256);
158+}
159+
160+/* table sum mod 256 + checksum must equals 256 */
161+static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
162+ struct eeprom_table_record *records, int num)
163+{
164+ control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);
165+
166+ if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) {
167+ DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum);
168+ return false;
169+ }
170+
171+ return true;
172+}
173+
174+int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
175+{
176+ unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
177+ struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
178+ int ret = 0;
179+
180+ mutex_lock(&control->tbl_mutex);
181+
182+ hdr->header = EEPROM_TABLE_HDR_VAL;
183+ hdr->version = EEPROM_TABLE_VER;
184+ hdr->first_rec_offset = EEPROM_RECORD_START;
185+ hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE;
186+
187+ control->tbl_byte_sum = 0;
188+ __update_tbl_checksum(control, NULL, 0, 0);
189+ control->next_addr = EEPROM_RECORD_START;
190+
191+ ret = __update_table_header(control, buff);
192+
193+ mutex_unlock(&control->tbl_mutex);
194+
195+ return ret;
196+
197+}
104198
105199 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
106200 {
@@ -122,6 +216,10 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) · 15 unmodified lines
122216 ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor);
123217 break;
124218
219+ case CHIP_ARCTURUS:
220+ ret = smu_i2c_eeprom_init(&adev->smu, &control->eeprom_accessor);
221+ break;
222+
125223 default:
126224 return 0;
127225 }
@@ -143,25 +241,18 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) · 15 unmodified lines
143241 if (hdr->header == EEPROM_TABLE_HDR_VAL) {
144242 control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) /
145243 EEPROM_TABLE_RECORD_SIZE;
244+ control->tbl_byte_sum = __calc_hdr_byte_sum(control);
245+ control->next_addr = EEPROM_RECORD_START;
246+
146247 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
147248 control->num_recs);
148249
149250 } else {
150251 DRM_INFO("Creating new EEPROM table");
151252
152− hdr->header = EEPROM_TABLE_HDR_VAL;
153− hdr->version = EEPROM_TABLE_VER;
154− hdr->first_rec_offset = EEPROM_RECORD_START;
155− hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE;
156−
157− adev->psp.ras.ras->eeprom_control.tbl_byte_sum =
158− __calc_hdr_byte_sum(&adev->psp.ras.ras->eeprom_control);
159− ret = __update_table_header(control, buff);
253+ ret = amdgpu_ras_eeprom_reset_table(control);
160254 }
161255
162− /* Start inserting records from here */
163− adev->psp.ras.ras->eeprom_control.next_addr = EEPROM_RECORD_START;
164−
165256 return ret == 1 ? 0 : -EIO;
166257 }
167258
@@ -173,6 +264,9 @@ void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control) · 5 unmodified lines
173264 case CHIP_VEGA20:
174265 smu_v11_0_i2c_eeprom_control_fini(&control->eeprom_accessor);
175266 break;
267+ case CHIP_ARCTURUS:
268+ smu_i2c_eeprom_fini(&adev->smu, &control->eeprom_accessor);
269+ break;
176270
177271 default:
178272 return;
@@ -226,8 +320,8 @@ static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *co · 47 unmodified lines
226320 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
227321 i += 6;
228322
229− buff[i++] = record->mem_channel;
230− buff[i++] = record->mcumc_id;
323+ record->mem_channel = buff[i++];
324+ record->mcumc_id = buff[i++];
231325
232326 memcpy(&tmp, buff + i, 6);
233327 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
@@ -266,87 +360,18 @@ static uint32_t __correct_eeprom_dest_address(uint32_t curr_address) · 32 unmodified lines
266360 return curr_address;
267361 }
268362
269−
270−static uint32_t __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control)
271−{
272− int i;
273− uint32_t tbl_sum = 0;
274−
275− /* Header checksum, skip checksum field in the calculation */
276− for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++)
277− tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i);
278−
279− return tbl_sum;
280−}
281−
282−static uint32_t __calc_recs_byte_sum(struct eeprom_table_record *records,
283− int num)
284−{
285− int i, j;
286− uint32_t tbl_sum = 0;
287−
288− /* Records checksum */
289− for (i = 0; i < num; i++) {
290− struct eeprom_table_record *record = &records[i];
291−
292− for (j = 0; j < sizeof(*record); j++) {
293− tbl_sum += *(((unsigned char *)record) + j);
294− }
295− }
296−
297− return tbl_sum;
298−}
299−
300−static inline uint32_t __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,
301− struct eeprom_table_record *records, int num)
302−{
303− return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num);
304−}
305−
306−/* Checksum = 256 -((sum of all table entries) mod 256) */
307−static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
308− struct eeprom_table_record *records, int num,
309− uint32_t old_hdr_byte_sum)
310−{
311− /*
312− * This will update the table sum with new records.
313− *
314− * TODO: What happens when the EEPROM table is to be wrapped around
315− * and old records from start will get overridden.
316− */
317−
318− /* need to recalculate updated header byte sum */
319− control->tbl_byte_sum -= old_hdr_byte_sum;
320− control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num);
321−
322− control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256);
323−}
324−
325−/* table sum mod 256 + checksum must equals 256 */
326−static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
327− struct eeprom_table_record *records, int num)
328−{
329− control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);
330−
331− if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) {
332− DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum);
333− return false;
334− }
335−
336− return true;
337−}
338−
339363 int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
340364 struct eeprom_table_record *records,
341365 bool write,
342366 int num)
343367 {
344368 int i, ret = 0;
345− struct i2c_msg *msgs;
346− unsigned char *buffs;
369+ struct i2c_msg *msgs, *msg;
370+ unsigned char *buffs, *buff;
371+ struct eeprom_table_record *record;
347372 struct amdgpu_device *adev = to_amdgpu_device(control);
348373
349− if (adev->asic_type != CHIP_VEGA20)
374+ if (adev->asic_type != CHIP_VEGA20 && adev->asic_type != CHIP_ARCTURUS)
350375 return 0;
351376
352377 buffs = kcalloc(num, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE,
@@ -373,9 +398,9 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control, · 20 unmodified lines
373398 * 256b
374399 */
375400 for (i = 0; i < num; i++) {
376− unsigned char *buff = &buffs[i * (EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
377− struct eeprom_table_record *record = &records[i];
378− struct i2c_msg *msg = &msgs[i];
401+ buff = &buffs[i * (EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
402+ record = &records[i];
403+ msg = &msgs[i];
379404
380405 control->next_addr = __correct_eeprom_dest_address(control->next_addr);
381406
@@ -415,8 +440,8 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control, · 33 unmodified lines
415440
416441 if (!write) {
417442 for (i = 0; i < num; i++) {
418− unsigned char *buff = &buffs[i*(EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
419− struct eeprom_table_record *record = &records[i];
443+ buff = &buffs[i*(EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
444+ record = &records[i];
420445
421446 __decode_table_record_from_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
422447 }
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h+1−0
@@ -79,6 +79,7 @@ struct eeprom_table_record { · 78 unmodified lines
7979
8080 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control);
8181 void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control);
82+int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control);
8283
8384 int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
8485 struct eeprom_table_record *records,
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c+99−0
@@ -23,6 +23,7 @@ · 22 unmodified lines
2323
2424 #include "amdgpu.h"
2525 #include "amdgpu_sdma.h"
26+#include "amdgpu_ras.h"
2627
2728 #define AMDGPU_CSA_SDMA_SIZE 64
2829 /* SDMA CSA reside in the 3rd page of CSA */
@@ -83,3 +84,101 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, · 54 unmodified lines
8384
8485 return csa_mc_addr;
8586 }
87+
88+int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
89+ void *ras_ih_info)
90+{
91+ int r, i;
92+ struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
93+ struct ras_fs_if fs_info = {
94+ .sysfs_name = "sdma_err_count",
95+ .debugfs_name = "sdma_err_inject",
96+ };
97+
98+ if (!ih_info)
99+ return -EINVAL;
100+
101+ if (!adev->sdma.ras_if) {
102+ adev->sdma.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
103+ if (!adev->sdma.ras_if)
104+ return -ENOMEM;
105+ adev->sdma.ras_if->block = AMDGPU_RAS_BLOCK__SDMA;
106+ adev->sdma.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
107+ adev->sdma.ras_if->sub_block_index = 0;
108+ strcpy(adev->sdma.ras_if->name, "sdma");
109+ }
110+ fs_info.head = ih_info->head = *adev->sdma.ras_if;
111+
112+ r = amdgpu_ras_late_init(adev, adev->sdma.ras_if,
113+ &fs_info, ih_info);
114+ if (r)
115+ goto free;
116+
117+ if (amdgpu_ras_is_supported(adev, adev->sdma.ras_if->block)) {
118+ for (i = 0; i < adev->sdma.num_instances; i++) {
119+ r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
120+ AMDGPU_SDMA_IRQ_INSTANCE0 + i);
121+ if (r)
122+ goto late_fini;
123+ }
124+ } else {
125+ r = 0;
126+ goto free;
127+ }
128+
129+ return 0;
130+
131+late_fini:
132+ amdgpu_ras_late_fini(adev, adev->sdma.ras_if, ih_info);
133+free:
134+ kfree(adev->sdma.ras_if);
135+ adev->sdma.ras_if = NULL;
136+ return r;
137+}
138+
139+void amdgpu_sdma_ras_fini(struct amdgpu_device *adev)
140+{
141+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) &&
142+ adev->sdma.ras_if) {
143+ struct ras_common_if *ras_if = adev->sdma.ras_if;
144+ struct ras_ih_if ih_info = {
145+ .head = *ras_if,
146+ /* the cb member will not be used by
147+ * amdgpu_ras_interrupt_remove_handler, init it only
148+ * to cheat the check in ras_late_fini
149+ */
150+ .cb = amdgpu_sdma_process_ras_data_cb,
151+ };
152+
153+ amdgpu_ras_late_fini(adev, ras_if, &ih_info);
154+ kfree(ras_if);
155+ }
156+}
157+
158+int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
159+ void *err_data,
160+ struct amdgpu_iv_entry *entry)
161+{
162+ kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
163+ amdgpu_ras_reset_gpu(adev, 0);
164+
165+ return AMDGPU_RAS_SUCCESS;
166+}
167+
168+int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
169+ struct amdgpu_irq_src *source,
170+ struct amdgpu_iv_entry *entry)
171+{
172+ struct ras_common_if *ras_if = adev->sdma.ras_if;
173+ struct ras_dispatch_if ih_data = {
174+ .entry = entry,
175+ };
176+
177+ if (!ras_if)
178+ return 0;
179+
180+ ih_data.head = *ras_if;
181+
182+ amdgpu_ras_interrupt_dispatch(adev, &ih_data);
183+ return 0;
184+}
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h+9−0
@@ -104,4 +104,13 @@ struct amdgpu_sdma_instance * · 103 unmodified lines
104104 amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
105105 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
106106 uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
107+int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
108+ void *ras_ih_info);
109+void amdgpu_sdma_ras_fini(struct amdgpu_device *adev);
110+int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
111+ void *err_data,
112+ struct amdgpu_iv_entry *entry);
113+int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
114+ struct amdgpu_irq_src *source,
115+ struct amdgpu_iv_entry *entry);
107116 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_test.c+2−0
@@ -138,6 +138,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) · 137 unmodified lines
138138 }
139139
140140 dma_fence_put(fence);
141+ fence = NULL;
141142
142143 r = amdgpu_bo_kmap(vram_obj, &vram_map);
143144 if (r) {
@@ -183,6 +184,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) · 39 unmodified lines
183184 }
184185
185186 dma_fence_put(fence);
187+ fence = NULL;
186188
187189 r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
188190 if (r) {
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h+23−18
@@ -170,7 +170,7 @@ TRACE_EVENT(amdgpu_cs_ioctl, · 169 unmodified lines
170170 __field(unsigned int, context)
171171 __field(unsigned int, seqno)
172172 __field(struct dma_fence *, fence)
173− __field(char *, ring_name)
173+ __string(ring, to_amdgpu_ring(job->base.sched)->name)
174174 __field(u32, num_ibs)
175175 ),
176176
@@ -179,12 +179,12 @@ TRACE_EVENT(amdgpu_cs_ioctl, · 2 unmodified lines
179179 __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))
180180 __entry->context = job->base.s_fence->finished.context;
181181 __entry->seqno = job->base.s_fence->finished.seqno;
182− __entry->ring_name = to_amdgpu_ring(job->base.sched)->name;
182+ __assign_str(ring, to_amdgpu_ring(job->base.sched)->name)
183183 __entry->num_ibs = job->num_ibs;
184184 ),
185185 TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u",
186186 __entry->sched_job_id, __get_str(timeline), __entry->context,
187− __entry->seqno, __entry->ring_name, __entry->num_ibs)
187+ __entry->seqno, __get_str(ring), __entry->num_ibs)
188188 );
189189
190190 TRACE_EVENT(amdgpu_sched_run_job,
@@ -195,7 +195,7 @@ TRACE_EVENT(amdgpu_sched_run_job, · 4 unmodified lines
195195 __string(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))
196196 __field(unsigned int, context)
197197 __field(unsigned int, seqno)
198− __field(char *, ring_name)
198+ __string(ring, to_amdgpu_ring(job->base.sched)->name)
199199 __field(u32, num_ibs)
200200 ),
201201
@@ -204,12 +204,12 @@ TRACE_EVENT(amdgpu_sched_run_job, · 2 unmodified lines
204204 __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))
205205 __entry->context = job->base.s_fence->finished.context;
206206 __entry->seqno = job->base.s_fence->finished.seqno;
207− __entry->ring_name = to_amdgpu_ring(job->base.sched)->name;
207+ __assign_str(ring, to_amdgpu_ring(job->base.sched)->name)
208208 __entry->num_ibs = job->num_ibs;
209209 ),
210210 TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u",
211211 __entry->sched_job_id, __get_str(timeline), __entry->context,
212− __entry->seqno, __entry->ring_name, __entry->num_ibs)
212+ __entry->seqno, __get_str(ring), __entry->num_ibs)
213213 );
214214
215215
@@ -323,14 +323,15 @@ DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_cs, · 107 unmodified lines
323323
324324 TRACE_EVENT(amdgpu_vm_set_ptes,
325325 TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
326− uint32_t incr, uint64_t flags),
327− TP_ARGS(pe, addr, count, incr, flags),
326+ uint32_t incr, uint64_t flags, bool direct),
327+ TP_ARGS(pe, addr, count, incr, flags, direct),
328328 TP_STRUCT__entry(
329329 __field(u64, pe)
330330 __field(u64, addr)
331331 __field(u32, count)
332332 __field(u32, incr)
333333 __field(u64, flags)
334+ __field(bool, direct)
334335 ),
335336
336337 TP_fast_assign(
@@ -339,28 +340,32 @@ TRACE_EVENT(amdgpu_vm_set_ptes, · 2 unmodified lines
339340 __entry->count = count;
340341 __entry->incr = incr;
341342 __entry->flags = flags;
343+ __entry->direct = direct;
342344 ),
343− TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%llx, count=%u",
344− __entry->pe, __entry->addr, __entry->incr,
345− __entry->flags, __entry->count)
345+ TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%llx, count=%u, "
346+ "direct=%d", __entry->pe, __entry->addr, __entry->incr,
347+ __entry->flags, __entry->count, __entry->direct)
346348 );
347349
348350 TRACE_EVENT(amdgpu_vm_copy_ptes,
349− TP_PROTO(uint64_t pe, uint64_t src, unsigned count),
350− TP_ARGS(pe, src, count),
351+ TP_PROTO(uint64_t pe, uint64_t src, unsigned count, bool direct),
352+ TP_ARGS(pe, src, count, direct),
351353 TP_STRUCT__entry(
352354 __field(u64, pe)
353355 __field(u64, src)
354356 __field(u32, count)
357+ __field(bool, direct)
355358 ),
356359
357360 TP_fast_assign(
358361 __entry->pe = pe;
359362 __entry->src = src;
360363 __entry->count = count;
364+ __entry->direct = direct;
361365 ),
362− TP_printk("pe=%010Lx, src=%010Lx, count=%u",
363− __entry->pe, __entry->src, __entry->count)
366+ TP_printk("pe=%010Lx, src=%010Lx, count=%u, direct=%d",
367+ __entry->pe, __entry->src, __entry->count,
368+ __entry->direct)
364369 );
365370
366371 TRACE_EVENT(amdgpu_vm_flush,
@@ -468,7 +473,7 @@ TRACE_EVENT(amdgpu_ib_pipe_sync, · 101 unmodified lines
468473 TP_PROTO(struct amdgpu_job *sched_job, struct dma_fence *fence),
469474 TP_ARGS(sched_job, fence),
470475 TP_STRUCT__entry(
471− __field(const char *,name)
476+ __string(ring, sched_job->base.sched->name);
472477 __field(uint64_t, id)
473478 __field(struct dma_fence *, fence)
474479 __field(uint64_t, ctx)
@@ -476,14 +481,14 @@ TRACE_EVENT(amdgpu_ib_pipe_sync, · 1 unmodified line
476481 ),
477482
478483 TP_fast_assign(
479− __entry->name = sched_job->base.sched->name;
484+ __assign_str(ring, sched_job->base.sched->name)
480485 __entry->id = sched_job->base.id;
481486 __entry->fence = fence;
482487 __entry->ctx = fence->context;
483488 __entry->seqno = fence->seqno;
484489 ),
485490 TP_printk("job ring=%s, id=%llu, need pipe sync to fence=%p, context=%llu, seq=%u",
486− __entry->name, __entry->id,
491+ __get_str(ring), __entry->id,
487492 __entry->fence, __entry->ctx,
488493 __entry->seqno)
489494 );
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+143−86
@@ -39,6 +39,7 @@ · 38 unmodified lines
3939 #include <linux/slab.h>
4040 #include <linux/swap.h>
4141 #include <linux/swiotlb.h>
42+#include <linux/dma-buf.h>
4243
4344 #include <drm/ttm/ttm_bo_api.h>
4445 #include <drm/ttm/ttm_bo_driver.h>
@@ -54,6 +55,7 @@ · 9 unmodified lines
5455 #include "amdgpu_trace.h"
5556 #include "amdgpu_amdkfd.h"
5657 #include "amdgpu_sdma.h"
58+#include "amdgpu_ras.h"
5759 #include "bif/bif_4_1_d.h"
5860
5961 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
@@ -484,15 +486,12 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict, · 424 unmodified lines
484486 struct ttm_operation_ctx *ctx,
485487 struct ttm_mem_reg *new_mem)
486488 {
487− struct amdgpu_device *adev;
488489 struct ttm_mem_reg *old_mem = &bo->mem;
489490 struct ttm_mem_reg tmp_mem;
490491 struct ttm_place placements;
491492 struct ttm_placement placement;
492493 int r;
493494
494− adev = amdgpu_ttm_adev(bo->bdev);
495−
496495 /* create space/pages for new_mem in GTT space */
497496 tmp_mem = *new_mem;
498497 tmp_mem.mm_node = NULL;
@@ -543,15 +542,12 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict, · 44 unmodified lines
543542 struct ttm_operation_ctx *ctx,
544543 struct ttm_mem_reg *new_mem)
545544 {
546− struct amdgpu_device *adev;
547545 struct ttm_mem_reg *old_mem = &bo->mem;
548546 struct ttm_mem_reg tmp_mem;
549547 struct ttm_placement placement;
550548 struct ttm_place placements;
551549 int r;
552550
553− adev = amdgpu_ttm_adev(bo->bdev);
554−
555551 /* make space in GTT for old_mem buffer */
556552 tmp_mem = *new_mem;
557553 tmp_mem.mm_node = NULL;
@@ -763,6 +759,7 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, · 205 unmodified lines
763759 */
764760 struct amdgpu_ttm_tt {
765761 struct ttm_dma_tt ttm;
762+ struct drm_gem_object *gobj;
766763 u64 offset;
767764 uint64_t userptr;
768765 struct task_struct *usertask;
@@ -1217,16 +1214,14 @@ static struct ttm_backend_func amdgpu_backend_func = { · 448 unmodified lines
12171214 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
12181215 uint32_t page_flags)
12191216 {
1220− struct amdgpu_device *adev;
12211217 struct amdgpu_ttm_tt *gtt;
12221218
1223− adev = amdgpu_ttm_adev(bo->bdev);
1224−
12251219 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
12261220 if (gtt == NULL) {
12271221 return NULL;
12281222 }
12291223 gtt->ttm.ttm.func = &amdgpu_backend_func;
1224+ gtt->gobj = &bo->base;
12301225
12311226 /* allocate space for the uninitialized page entries */
12321227 if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
@@ -1247,7 +1242,6 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm, · 14 unmodified lines
12471242 {
12481243 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
12491244 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1250− bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
12511245
12521246 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
12531247 if (gtt && gtt->userptr) {
@@ -1260,7 +1254,19 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm, · 6 unmodified lines
12601254 return 0;
12611255 }
12621256
1263− if (slave && ttm->sg) {
1257+ if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1258+ if (!ttm->sg) {
1259+ struct dma_buf_attachment *attach;
1260+ struct sg_table *sgt;
1261+
1262+ attach = gtt->gobj->import_attach;
1263+ sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1264+ if (IS_ERR(sgt))
1265+ return PTR_ERR(sgt);
1266+
1267+ ttm->sg = sgt;
1268+ }
1269+
12641270 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
12651271 gtt->ttm.dma_address,
12661272 ttm->num_pages);
@@ -1287,9 +1293,8 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm, · 20 unmodified lines
12871293 */
12881294 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
12891295 {
1290− struct amdgpu_device *adev;
12911296 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1292− bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1297+ struct amdgpu_device *adev;
12931298
12941299 if (gtt && gtt->userptr) {
12951300 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
@@ -1298,7 +1303,16 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) · 2 unmodified lines
12981303 return;
12991304 }
13001305
1301− if (slave)
1306+ if (ttm->sg && gtt->gobj->import_attach) {
1307+ struct dma_buf_attachment *attach;
1308+
1309+ attach = gtt->gobj->import_attach;
1310+ dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1311+ ttm->sg = NULL;
1312+ return;
1313+ }
1314+
1315+ if (ttm->page_flags & TTM_PAGE_FLAG_SG)
13021316 return;
13031317
13041318 adev = amdgpu_ttm_adev(ttm->bdev);
@@ -1634,81 +1648,105 @@ static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) · 329 unmodified lines
16341648 */
16351649 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
16361650 {
1637− struct ttm_operation_ctx ctx = { false, false };
1638− struct amdgpu_bo_param bp;
1639− int r = 0;
1640− int i;
1641− u64 vram_size = adev->gmc.visible_vram_size;
1642− u64 offset = adev->fw_vram_usage.start_offset;
1643− u64 size = adev->fw_vram_usage.size;
1644− struct amdgpu_bo *bo;
1645−
1646− memset(&bp, 0, sizeof(bp));
1647− bp.size = adev->fw_vram_usage.size;
1648− bp.byte_align = PAGE_SIZE;
1649− bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1650− bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1651− AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1652− bp.type = ttm_bo_type_kernel;
1653− bp.resv = NULL;
1651+ uint64_t vram_size = adev->gmc.visible_vram_size;
1652+
16541653 adev->fw_vram_usage.va = NULL;
16551654 adev->fw_vram_usage.reserved_bo = NULL;
16561655
1657− if (adev->fw_vram_usage.size > 0 &&
1658− adev->fw_vram_usage.size <= vram_size) {
1656+ if (adev->fw_vram_usage.size == 0 ||
1657+ adev->fw_vram_usage.size > vram_size)
1658+ return 0;
16591659
1660− r = amdgpu_bo_create(adev, &bp,
1661− &adev->fw_vram_usage.reserved_bo);
1662− if (r)
1663− goto error_create;
1660+ return amdgpu_bo_create_kernel_at(adev,
1661+ adev->fw_vram_usage.start_offset,
1662+ adev->fw_vram_usage.size,
1663+ AMDGPU_GEM_DOMAIN_VRAM,
1664+ &adev->fw_vram_usage.reserved_bo,
1665+ &adev->fw_vram_usage.va);
1666+}
16641667
1665− r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
1666− if (r)
1667− goto error_reserve;
1668+/*
1669+ * Memoy training reservation functions
1670+ */
16681671
1669− /* remove the original mem node and create a new one at the
1670− * request position
1671− */
1672− bo = adev->fw_vram_usage.reserved_bo;
1673− offset = ALIGN(offset, PAGE_SIZE);
1674− for (i = 0; i < bo->placement.num_placement; ++i) {
1675− bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1676− bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1677− }
1672+/**
1673+ * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1674+ *
1675+ * @adev: amdgpu_device pointer
1676+ *
1677+ * free memory training reserved vram if it has been reserved.
1678+ */
1679+static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1680+{
1681+ struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
16781682
1679− ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1680− r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
1681− &bo->tbo.mem, &ctx);
1682− if (r)
1683− goto error_pin;
1683+ ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1684+ amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1685+ ctx->c2p_bo = NULL;
16841686
1685− r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
1686− AMDGPU_GEM_DOMAIN_VRAM,
1687− adev->fw_vram_usage.start_offset,
1688− (adev->fw_vram_usage.start_offset +
1689− adev->fw_vram_usage.size));
1690− if (r)
1691− goto error_pin;
1692− r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
1693− &adev->fw_vram_usage.va);
1694− if (r)
1695− goto error_kmap;
1687+ amdgpu_bo_free_kernel(&ctx->p2c_bo, NULL, NULL);
1688+ ctx->p2c_bo = NULL;
16961689
1697− amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1690+ return 0;
1691+}
1692+
1693+/**
1694+ * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
1695+ *
1696+ * @adev: amdgpu_device pointer
1697+ *
1698+ * create bo vram reservation from memory training.
1699+ */
1700+static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
1701+{
1702+ int ret;
1703+ struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1704+
1705+ memset(ctx, 0, sizeof(*ctx));
1706+ if (!adev->fw_vram_usage.mem_train_support) {
1707+ DRM_DEBUG("memory training does not support!\n");
1708+ return 0;
16981709 }
1699− return r;
17001710
1701−error_kmap:
1702− amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
1703−error_pin:
1704− amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1705−error_reserve:
1706− amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
1707−error_create:
1708− adev->fw_vram_usage.va = NULL;
1709− adev->fw_vram_usage.reserved_bo = NULL;
1710− return r;
1711+ ctx->c2p_train_data_offset = adev->fw_vram_usage.mem_train_fb_loc;
1712+ ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1713+ ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1714+
1715+ DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1716+ ctx->train_data_size,
1717+ ctx->p2c_train_data_offset,
1718+ ctx->c2p_train_data_offset);
1719+
1720+ ret = amdgpu_bo_create_kernel_at(adev,
1721+ ctx->p2c_train_data_offset,
1722+ ctx->train_data_size,
1723+ AMDGPU_GEM_DOMAIN_VRAM,
1724+ &ctx->p2c_bo,
1725+ NULL);
1726+ if (ret) {
1727+ DRM_ERROR("alloc p2c_bo failed(%d)!\n", ret);
1728+ goto Err_out;
1729+ }
1730+
1731+ ret = amdgpu_bo_create_kernel_at(adev,
1732+ ctx->c2p_train_data_offset,
1733+ ctx->train_data_size,
1734+ AMDGPU_GEM_DOMAIN_VRAM,
1735+ &ctx->c2p_bo,
1736+ NULL);
1737+ if (ret) {
1738+ DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1739+ goto Err_out;
1740+ }
1741+
1742+ ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1743+ return 0;
1744+
1745+Err_out:
1746+ amdgpu_ttm_training_reserve_vram_fini(adev);
1747+ return ret;
17111748 }
1749+
17121750 /**
17131751 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
17141752 * gtt/vram related fields.
@@ -1772,6 +1810,14 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) · 57 unmodified lines
17721810 return r;
17731811 }
17741812
1813+ /*
1814+ *The reserved vram for memory training must be pinned to the specified
1815+ *place on the VRAM, so reserve it early.
1816+ */
1817+ r = amdgpu_ttm_training_reserve_vram_init(adev);
1818+ if (r)
1819+ return r;
1820+
17751821 /* allocate memory as required for VGA
17761822 * This is used for VGA emulation and pre-OS scanout buffers to
17771823 * avoid display artifacts while transitioning between pre-OS
@@ -1782,6 +1828,20 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) · 4 unmodified lines
17821828 NULL, &stolen_vga_buf);
17831829 if (r)
17841830 return r;
1831+
1832+ /*
1833+ * reserve one TMR (64K) memory at the top of VRAM which holds
1834+ * IP Discovery data and is protected by PSP.
1835+ */
1836+ r = amdgpu_bo_create_kernel_at(adev,
1837+ adev->gmc.real_vram_size - DISCOVERY_TMR_SIZE,
1838+ DISCOVERY_TMR_SIZE,
1839+ AMDGPU_GEM_DOMAIN_VRAM,
1840+ &adev->discovery_memory,
1841+ NULL);
1842+ if (r)
1843+ return r;
1844+
17851845 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
17861846 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
17871847
@@ -1857,7 +1917,11 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) · 69 unmodified lines
18571917 return;
18581918
18591919 amdgpu_ttm_debugfs_fini(adev);
1920+ amdgpu_ttm_training_reserve_vram_fini(adev);
1921+ /* return the IP Discovery TMR memory back to VRAM */
1922+ amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
18601923 amdgpu_ttm_fw_reserve_vram_fini(adev);
1924+
18611925 if (adev->mman.aper_base_kaddr)
18621926 iounmap(adev->mman.aper_base_kaddr);
18631927 adev->mman.aper_base_kaddr = NULL;
@@ -1953,10 +2017,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object *bo, · 89 unmodified lines
19532017 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
19542018 AMDGPU_GPU_PAGE_SIZE;
19552019
1956− num_dw = adev->mman.buffer_funcs->copy_num_dw;
1957− while (num_dw & 0x7)
1958− num_dw++;
1959−
2020+ num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
19602021 num_bytes = num_pages * 8;
19612022
19622023 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
@@ -2016,11 +2077,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, · 53 unmodified lines
20162077
20172078 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
20182079 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2019− num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
2020−
2021− /* for IB padding */
2022− while (num_dw & 0x7)
2023− num_dw++;
2080+ num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
20242081
20252082 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
20262083 if (r)
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c+1−2
@@ -360,6 +360,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) · 359 unmodified lines
360360 case CHIP_RAVEN:
361361 case CHIP_VEGA12:
362362 case CHIP_VEGA20:
363+ case CHIP_ARCTURUS:
363364 case CHIP_RENOIR:
364365 case CHIP_NAVI10:
365366 case CHIP_NAVI14:
@@ -368,8 +369,6 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) · 2 unmodified lines
368369 return AMDGPU_FW_LOAD_DIRECT;
369370 else
370371 return AMDGPU_FW_LOAD_PSP;
371− case CHIP_ARCTURUS:
372− return AMDGPU_FW_LOAD_DIRECT;
373372
374373 default:
375374 DRM_ERROR("Unknown firmware load type\n");
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h+6−0
@@ -108,6 +108,12 @@ struct ta_firmware_header_v1_0 { · 107 unmodified lines
108108 uint32_t ta_ras_ucode_version;
109109 uint32_t ta_ras_offset_bytes;
110110 uint32_t ta_ras_size_bytes;
111+ uint32_t ta_hdcp_ucode_version;
112+ uint32_t ta_hdcp_offset_bytes;
113+ uint32_t ta_hdcp_size_bytes;
114+ uint32_t ta_dtm_ucode_version;
115+ uint32_t ta_dtm_offset_bytes;
116+ uint32_t ta_dtm_size_bytes;
111117 };
112118
113119 /* version_major=1, version_minor=0 */
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c+158−0
@@ -0,0 +1,158 @@
1+/*
2+ * Copyright 2019 Advanced Micro Devices, Inc.
3+ *
4+ * Permission is hereby granted, free of charge, to any person obtaining a
5+ * copy of this software and associated documentation files (the "Software"),
6+ * to deal in the Software without restriction, including without limitation
7+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+ * and/or sell copies of the Software, and to permit persons to whom the
9+ * Software is furnished to do so, subject to the following conditions:
10+ *
11+ * The above copyright notice and this permission notice shall be included in
12+ * all copies or substantial portions of the Software.
13+ *
14+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+ * OTHER DEALINGS IN THE SOFTWARE.
21+ *
22+ */
23+
24+#include "amdgpu_ras.h"
25+
26+int amdgpu_umc_ras_late_init(struct amdgpu_device *adev)
27+{
28+ int r;
29+ struct ras_fs_if fs_info = {
30+ .sysfs_name = "umc_err_count",
31+ .debugfs_name = "umc_err_inject",
32+ };
33+ struct ras_ih_if ih_info = {
34+ .cb = amdgpu_umc_process_ras_data_cb,
35+ };
36+
37+ if (!adev->umc.ras_if) {
38+ adev->umc.ras_if =
39+ kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
40+ if (!adev->umc.ras_if)
41+ return -ENOMEM;
42+ adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC;
43+ adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
44+ adev->umc.ras_if->sub_block_index = 0;
45+ strcpy(adev->umc.ras_if->name, "umc");
46+ }
47+ ih_info.head = fs_info.head = *adev->umc.ras_if;
48+
49+ r = amdgpu_ras_late_init(adev, adev->umc.ras_if,
50+ &fs_info, &ih_info);
51+ if (r)
52+ goto free;
53+
54+ if (amdgpu_ras_is_supported(adev, adev->umc.ras_if->block)) {
55+ r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
56+ if (r)
57+ goto late_fini;
58+ } else {
59+ r = 0;
60+ goto free;
61+ }
62+
63+ /* ras init of specific umc version */
64+ if (adev->umc.funcs && adev->umc.funcs->err_cnt_init)
65+ adev->umc.funcs->err_cnt_init(adev);
66+
67+ return 0;
68+
69+late_fini:
70+ amdgpu_ras_late_fini(adev, adev->umc.ras_if, &ih_info);
71+free:
72+ kfree(adev->umc.ras_if);
73+ adev->umc.ras_if = NULL;
74+ return r;
75+}
76+
77+void amdgpu_umc_ras_fini(struct amdgpu_device *adev)
78+{
79+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
80+ adev->umc.ras_if) {
81+ struct ras_common_if *ras_if = adev->umc.ras_if;
82+ struct ras_ih_if ih_info = {
83+ .head = *ras_if,
84+ .cb = amdgpu_umc_process_ras_data_cb,
85+ };
86+
87+ amdgpu_ras_late_fini(adev, ras_if, &ih_info);
88+ kfree(ras_if);
89+ }
90+}
91+
92+int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
93+ void *ras_error_status,
94+ struct amdgpu_iv_entry *entry)
95+{
96+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
97+
98+ /* When “Full RAS” is enabled, the per-IP interrupt sources should
99+ * be disabled and the driver should only look for the aggregated
100+ * interrupt via sync flood
101+ */
102+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
103+ return AMDGPU_RAS_SUCCESS;
104+
105+ kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
106+ if (adev->umc.funcs &&
107+ adev->umc.funcs->query_ras_error_count)
108+ adev->umc.funcs->query_ras_error_count(adev, ras_error_status);
109+
110+ if (adev->umc.funcs &&
111+ adev->umc.funcs->query_ras_error_address &&
112+ adev->umc.max_ras_err_cnt_per_query) {
113+ err_data->err_addr =
114+ kcalloc(adev->umc.max_ras_err_cnt_per_query,
115+ sizeof(struct eeprom_table_record), GFP_KERNEL);
116+ /* still call query_ras_error_address to clear error status
117+ * even NOMEM error is encountered
118+ */
119+ if(!err_data->err_addr)
120+ DRM_WARN("Failed to alloc memory for umc error address record!\n");
121+
122+ /* umc query_ras_error_address is also responsible for clearing
123+ * error status
124+ */
125+ adev->umc.funcs->query_ras_error_address(adev, ras_error_status);
126+ }
127+
128+ /* only uncorrectable error needs gpu reset */
129+ if (err_data->ue_count) {
130+ if (err_data->err_addr_cnt &&
131+ amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
132+ err_data->err_addr_cnt))
133+ DRM_WARN("Failed to add ras bad page!\n");
134+
135+ amdgpu_ras_reset_gpu(adev, 0);
136+ }
137+
138+ kfree(err_data->err_addr);
139+ return AMDGPU_RAS_SUCCESS;
140+}
141+
142+int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
143+ struct amdgpu_irq_src *source,
144+ struct amdgpu_iv_entry *entry)
145+{
146+ struct ras_common_if *ras_if = adev->umc.ras_if;
147+ struct ras_dispatch_if ih_data = {
148+ .entry = entry,
149+ };
150+
151+ if (!ras_if)
152+ return 0;
153+
154+ ih_data.head = *ras_if;
155+
156+ amdgpu_ras_interrupt_dispatch(adev, &ih_data);
157+ return 0;
158+}
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h+12−1
@@ -54,7 +54,8 @@ · 53 unmodified lines
5454 adev->umc.funcs->disable_umc_index_mode(adev);
5555
5656 struct amdgpu_umc_funcs {
57− void (*ras_init)(struct amdgpu_device *adev);
57+ void (*err_cnt_init)(struct amdgpu_device *adev);
58+ int (*ras_late_init)(struct amdgpu_device *adev);
5859 void (*query_ras_error_count)(struct amdgpu_device *adev,
5960 void *ras_error_status);
6061 void (*query_ras_error_address)(struct amdgpu_device *adev,
@@ -62,6 +63,7 @@ struct amdgpu_umc_funcs { · 1 unmodified line
6263 void (*enable_umc_index_mode)(struct amdgpu_device *adev,
6364 uint32_t umc_instance);
6465 void (*disable_umc_index_mode)(struct amdgpu_device *adev);
66+ void (*init_registers)(struct amdgpu_device *adev);
6567 };
6668
6769 struct amdgpu_umc {
@@ -75,8 +77,17 @@ struct amdgpu_umc { · 7 unmodified lines
7577 uint32_t channel_offs;
7678 /* channel index table of interleaved memory */
7779 const uint32_t *channel_idx_tbl;
80+ struct ras_common_if *ras_if;
7881
7982 const struct amdgpu_umc_funcs *funcs;
8083 };
8184
85+int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);
86+void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
87+int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
88+ void *ras_error_status,
89+ struct amdgpu_iv_entry *entry);
90+int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
91+ struct amdgpu_irq_src *source,
92+ struct amdgpu_iv_entry *entry);
8293 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c+9−1
@@ -39,6 +39,8 @@ · 38 unmodified lines
3939 #include "cikd.h"
4040 #include "uvd/uvd_4_2_d.h"
4141
42+#include "amdgpu_ras.h"
43+
4244 /* 1 second timeout */
4345 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
4446
@@ -372,7 +374,13 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev) · 327 unmodified lines
372374 if (!adev->uvd.inst[j].saved_bo)
373375 return -ENOMEM;
374376
375− memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
377+ /* re-write 0 since err_event_athub will corrupt VCPU buffer */
378+ if (amdgpu_ras_intr_triggered()) {
379+ DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");
380+ memset(adev->uvd.inst[j].saved_bo, 0, size);
381+ } else {
382+ memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
383+ }
376384 }
377385 return 0;
378386 }
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c+24−9
@@ -80,6 +80,11 @@ MODULE_FIRMWARE(FIRMWARE_VEGA12); · 79 unmodified lines
8080 MODULE_FIRMWARE(FIRMWARE_VEGA20);
8181
8282 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
83+static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
84+ struct amdgpu_bo *bo,
85+ struct dma_fence **fence);
86+static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
87+ bool direct, struct dma_fence **fence);
8388
8489 /**
8590 * amdgpu_vce_init - allocate memory, load vce firmware
@@ -428,14 +433,15 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp) · 342 unmodified lines
428433 *
429434 * Open up a stream for HW test
430435 */
431−int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
432− struct dma_fence **fence)
436+static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
437+ struct amdgpu_bo *bo,
438+ struct dma_fence **fence)
433439 {
434440 const unsigned ib_size_dw = 1024;
435441 struct amdgpu_job *job;
436442 struct amdgpu_ib *ib;
437443 struct dma_fence *f = NULL;
438− uint64_t dummy;
444+ uint64_t addr;
439445 int i, r;
440446
441447 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
@@ -444,7 +450,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, · 2 unmodified lines
444450
445451 ib = &job->ibs[0];
446452
447− dummy = ib->gpu_addr + 1024;
453+ addr = amdgpu_bo_gpu_offset(bo);
448454
449455 /* stitch together an VCE create msg */
450456 ib->length_dw = 0;
@@ -476,8 +482,8 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, · 25 unmodified lines
476482
477483 ib->ptr[ib->length_dw++] = 0x00000014; /* len */
478484 ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
479− ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
480− ib->ptr[ib->length_dw++] = dummy;
485+ ib->ptr[ib->length_dw++] = upper_32_bits(addr);
486+ ib->ptr[ib->length_dw++] = addr;
481487 ib->ptr[ib->length_dw++] = 0x00000001;
482488
483489 for (i = ib->length_dw; i < ib_size_dw; ++i)
@@ -507,8 +513,8 @@ err: · 23 unmodified lines
507513 *
508514 * Close up a stream for HW test or if userspace failed to do so
509515 */
510−int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
511− bool direct, struct dma_fence **fence)
516+static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
517+ bool direct, struct dma_fence **fence)
512518 {
513519 const unsigned ib_size_dw = 1024;
514520 struct amdgpu_job *job;
@@ -1110,13 +1116,20 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring) · 595 unmodified lines
11101116 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
11111117 {
11121118 struct dma_fence *fence = NULL;
1119+ struct amdgpu_bo *bo = NULL;
11131120 long r;
11141121
11151122 /* skip vce ring1/2 ib test for now, since it's not reliable */
11161123 if (ring != &ring->adev->vce.ring[0])
11171124 return 0;
11181125
1119− r = amdgpu_vce_get_create_msg(ring, 1, NULL);
1126+ r = amdgpu_bo_create_reserved(ring->adev, 512, PAGE_SIZE,
1127+ AMDGPU_GEM_DOMAIN_VRAM,
1128+ &bo, NULL, NULL);
1129+ if (r)
1130+ return r;
1131+
1132+ r = amdgpu_vce_get_create_msg(ring, 1, bo, NULL);
11201133 if (r)
11211134 goto error;
11221135
@@ -1132,5 +1145,7 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout) · 9 unmodified lines
11321145
11331146 error:
11341147 dma_fence_put(fence);
1148+ amdgpu_bo_unreserve(bo);
1149+ amdgpu_bo_unref(&bo);
11351150 return r;
11361151 }
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h+0−4
@@ -58,10 +58,6 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev); · 57 unmodified lines
5858 int amdgpu_vce_entity_init(struct amdgpu_device *adev);
5959 int amdgpu_vce_suspend(struct amdgpu_device *adev);
6060 int amdgpu_vce_resume(struct amdgpu_device *adev);
61−int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
62− struct dma_fence **fence);
63−int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
64− bool direct, struct dma_fence **fence);
6561 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
6662 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
6763 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c+23−12
@@ -569,13 +569,14 @@ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) · 568 unmodified lines
569569 }
570570
571571 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
572− struct dma_fence **fence)
572+ struct amdgpu_bo *bo,
573+ struct dma_fence **fence)
573574 {
574575 const unsigned ib_size_dw = 16;
575576 struct amdgpu_job *job;
576577 struct amdgpu_ib *ib;
577578 struct dma_fence *f = NULL;
578− uint64_t dummy;
579+ uint64_t addr;
579580 int i, r;
580581
581582 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
@@ -583,14 +584,14 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand · 1 unmodified line
583584 return r;
584585
585586 ib = &job->ibs[0];
586− dummy = ib->gpu_addr + 1024;
587+ addr = amdgpu_bo_gpu_offset(bo);
587588
588589 ib->length_dw = 0;
589590 ib->ptr[ib->length_dw++] = 0x00000018;
590591 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
591592 ib->ptr[ib->length_dw++] = handle;
592− ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
593− ib->ptr[ib->length_dw++] = dummy;
593+ ib->ptr[ib->length_dw++] = upper_32_bits(addr);
594+ ib->ptr[ib->length_dw++] = addr;
594595 ib->ptr[ib->length_dw++] = 0x0000000b;
595596
596597 ib->ptr[ib->length_dw++] = 0x00000014;
@@ -621,13 +622,14 @@ err: · 24 unmodified lines
621622 }
622623
623624 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
624− struct dma_fence **fence)
625+ struct amdgpu_bo *bo,
626+ struct dma_fence **fence)
625627 {
626628 const unsigned ib_size_dw = 16;
627629 struct amdgpu_job *job;
628630 struct amdgpu_ib *ib;
629631 struct dma_fence *f = NULL;
630− uint64_t dummy;
632+ uint64_t addr;
631633 int i, r;
632634
633635 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
@@ -635,14 +637,14 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han · 1 unmodified line
635637 return r;
636638
637639 ib = &job->ibs[0];
638− dummy = ib->gpu_addr + 1024;
640+ addr = amdgpu_bo_gpu_offset(bo);
639641
640642 ib->length_dw = 0;
641643 ib->ptr[ib->length_dw++] = 0x00000018;
642644 ib->ptr[ib->length_dw++] = 0x00000001;
643645 ib->ptr[ib->length_dw++] = handle;
644− ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
645− ib->ptr[ib->length_dw++] = dummy;
646+ ib->ptr[ib->length_dw++] = upper_32_bits(addr);
647+ ib->ptr[ib->length_dw++] = addr;
646648 ib->ptr[ib->length_dw++] = 0x0000000b;
647649
648650 ib->ptr[ib->length_dw++] = 0x00000014;
@@ -675,13 +677,20 @@ err: · 26 unmodified lines
675677 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
676678 {
677679 struct dma_fence *fence = NULL;
680+ struct amdgpu_bo *bo = NULL;
678681 long r;
679682
680− r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL);
683+ r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
684+ AMDGPU_GEM_DOMAIN_VRAM,
685+ &bo, NULL, NULL);
686+ if (r)
687+ return r;
688+
689+ r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL);
681690 if (r)
682691 goto error;
683692
684− r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence);
693+ r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence);
685694 if (r)
686695 goto error;
687696
@@ -693,6 +702,8 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) · 5 unmodified lines
693702
694703 error:
695704 dma_fence_put(fence);
705+ amdgpu_bo_unreserve(bo);
706+ amdgpu_bo_unref(&bo);
696707 return r;
697708 }
698709
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+210−108
@@ -130,7 +130,8 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, · 129 unmodified lines
130130
131131 if (level == adev->vm_manager.root_level)
132132 /* For the root directory */
133− return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift;
133+ return round_up(adev->vm_manager.max_pfn, 1ULL << shift)
134+ >> shift;
134135 else if (level != AMDGPU_VM_PTB)
135136 /* Everything in between */
136137 return 512;
@@ -341,7 +342,7 @@ static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt) · 204 unmodified lines
341342 return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
342343 }
343344
344−/**
345+/*
345346 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
346347 */
347348 struct amdgpu_vm_pt_cursor {
@@ -482,6 +483,7 @@ static void amdgpu_vm_pt_next(struct amdgpu_device *adev, · 134 unmodified lines
482483 *
483484 * @adev: amdgpu_device structure
484485 * @vm: amdgpu_vm structure
486+ * @start: optional cursor to start with
485487 * @cursor: state to initialize
486488 *
487489 * Starts a deep first traversal of the PD/PT tree.
@@ -535,7 +537,7 @@ static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev, · 47 unmodified lines
535537 amdgpu_vm_pt_ancestor(cursor);
536538 }
537539
538−/**
540+/*
539541 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
540542 */
541543 #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
@@ -566,6 +568,14 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, · 24 unmodified lines
566568 list_add(&entry->tv.head, validated);
567569 }
568570
571+/**
572+ * amdgpu_vm_del_from_lru_notify - update bulk_moveable flag
573+ *
574+ * @bo: BO which was removed from the LRU
575+ *
576+ * Make sure the bulk_moveable flag is updated when a BO is removed from the
577+ * LRU.
578+ */
569579 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
570580 {
571581 struct amdgpu_bo *abo;
@@ -600,19 +610,18 @@ void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo) · 28 unmodified lines
600610 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
601611 struct amdgpu_vm *vm)
602612 {
603− struct ttm_bo_global *glob = adev->mman.bdev.glob;
604613 struct amdgpu_vm_bo_base *bo_base;
605614
606615 if (vm->bulk_moveable) {
607− spin_lock(&glob->lru_lock);
616+ spin_lock(&ttm_bo_glob.lru_lock);
608617 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
609− spin_unlock(&glob->lru_lock);
618+ spin_unlock(&ttm_bo_glob.lru_lock);
610619 return;
611620 }
612621
613622 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
614623
615− spin_lock(&glob->lru_lock);
624+ spin_lock(&ttm_bo_glob.lru_lock);
616625 list_for_each_entry(bo_base, &vm->idle, vm_status) {
617626 struct amdgpu_bo *bo = bo_base->bo;
618627
@@ -624,7 +633,7 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, · 5 unmodified lines
624633 ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
625634 &vm->lru_bulk_move);
626635 }
627− spin_unlock(&glob->lru_lock);
636+ spin_unlock(&ttm_bo_glob.lru_lock);
628637
629638 vm->bulk_moveable = true;
630639 }
@@ -693,6 +702,7 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm) · 62 unmodified lines
693702 * @adev: amdgpu_device pointer
694703 * @vm: VM to clear BO from
695704 * @bo: BO to clear
705+ * @direct: use a direct update
696706 *
697707 * Root PD needs to be reserved when calling this.
698708 *
@@ -701,7 +711,8 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm) · 2 unmodified lines
701711 */
702712 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
703713 struct amdgpu_vm *vm,
704− struct amdgpu_bo *bo)
714+ struct amdgpu_bo *bo,
715+ bool direct)
705716 {
706717 struct ttm_operation_ctx ctx = { true, false };
707718 unsigned level = adev->vm_manager.root_level;
@@ -760,6 +771,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, · 52 unmodified lines
760771 memset(&params, 0, sizeof(params));
761772 params.adev = adev;
762773 params.vm = vm;
774+ params.direct = direct;
763775
764776 r = vm->update_funcs->prepare(&params, AMDGPU_FENCE_OWNER_KFD, NULL);
765777 if (r)
@@ -813,10 +825,13 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, · 47 unmodified lines
813825 *
814826 * @adev: amdgpu_device pointer
815827 * @vm: requesting vm
828+ * @level: the page table level
829+ * @direct: use a direct update
816830 * @bp: resulting BO allocation parameters
817831 */
818832 static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
819− int level, struct amdgpu_bo_param *bp)
833+ int level, bool direct,
834+ struct amdgpu_bo_param *bp)
820835 {
821836 memset(bp, 0, sizeof(*bp));
822837
@@ -831,6 +846,7 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 8 unmodified lines
831846 else if (!vm->root.base.bo || vm->root.base.bo->shadow)
832847 bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
833848 bp->type = ttm_bo_type_kernel;
849+ bp->no_wait_gpu = direct;
834850 if (vm->root.base.bo)
835851 bp->resv = vm->root.base.bo->tbo.base.resv;
836852 }
@@ -841,6 +857,7 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 4 unmodified lines
841857 * @adev: amdgpu_device pointer
842858 * @vm: VM to allocate page tables for
843859 * @cursor: Which page table to allocate
860+ * @direct: use a direct update
844861 *
845862 * Make sure a specific page table or directory is allocated.
846863 *
@@ -850,7 +867,8 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 3 unmodified lines
850867 */
851868 static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
852869 struct amdgpu_vm *vm,
853− struct amdgpu_vm_pt_cursor *cursor)
870+ struct amdgpu_vm_pt_cursor *cursor,
871+ bool direct)
854872 {
855873 struct amdgpu_vm_pt *entry = cursor->entry;
856874 struct amdgpu_bo_param bp;
@@ -871,7 +889,7 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, · 14 unmodified lines
871889 if (entry->base.bo)
872890 return 0;
873891
874− amdgpu_vm_bo_param(adev, vm, cursor->level, &bp);
892+ amdgpu_vm_bo_param(adev, vm, cursor->level, direct, &bp);
875893
876894 r = amdgpu_bo_create(adev, &bp, &pt);
877895 if (r)
@@ -883,7 +901,7 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, · 5 unmodified lines
883901 pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
884902 amdgpu_vm_bo_base_init(&entry->base, vm, pt);
885903
886− r = amdgpu_vm_clear_bo(adev, vm, pt);
904+ r = amdgpu_vm_clear_bo(adev, vm, pt, direct);
887905 if (r)
888906 goto error_free_pt;
889907
@@ -1020,7 +1038,8 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, · 130 unmodified lines
10201038 * Returns:
10211039 * 0 on success, errno otherwise.
10221040 */
1023−int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
1041+int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
1042+ bool need_pipe_sync)
10241043 {
10251044 struct amdgpu_device *adev = ring->adev;
10261045 unsigned vmhub = ring->funcs->vmhub;
@@ -1034,10 +1053,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_ · 7 unmodified lines
10341053 id->oa_base != job->oa_base ||
10351054 id->oa_size != job->oa_size);
10361055 bool vm_flush_needed = job->vm_needs_flush;
1037− bool pasid_mapping_needed = id->pasid != job->pasid ||
1038− !id->pasid_mapping ||
1039− !dma_fence_is_signaled(id->pasid_mapping);
10401056 struct dma_fence *fence = NULL;
1057+ bool pasid_mapping_needed = false;
10411058 unsigned patch_offset = 0;
10421059 int r;
10431060
@@ -1047,6 +1064,12 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_ · 3 unmodified lines
10471064 pasid_mapping_needed = true;
10481065 }
10491066
1067+ mutex_lock(&id_mgr->lock);
1068+ if (id->pasid != job->pasid || !id->pasid_mapping ||
1069+ !dma_fence_is_signaled(id->pasid_mapping))
1070+ pasid_mapping_needed = true;
1071+ mutex_unlock(&id_mgr->lock);
1072+
10501073 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
10511074 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
10521075 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
@@ -1086,9 +1109,11 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_ · 33 unmodified lines
10861109 }
10871110
10881111 if (pasid_mapping_needed) {
1112+ mutex_lock(&id_mgr->lock);
10891113 id->pasid = job->pasid;
10901114 dma_fence_put(id->pasid_mapping);
10911115 id->pasid_mapping = dma_fence_get(fence);
1116+ mutex_unlock(&id_mgr->lock);
10921117 }
10931118 dma_fence_put(fence);
10941119
@@ -1172,10 +1197,10 @@ uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) · 77 unmodified lines
11721197 return result;
11731198 }
11741199
1175−/*
1200+/**
11761201 * amdgpu_vm_update_pde - update a single level in the hierarchy
11771202 *
1178− * @param: parameters for the update
1203+ * @params: parameters for the update
11791204 * @vm: requested vm
11801205 * @entry: entry to update
11811206 *
@@ -1199,7 +1224,7 @@ static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params, · 17 unmodified lines
11991224 return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags);
12001225 }
12011226
1202−/*
1227+/**
12031228 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
12041229 *
12051230 * @adev: amdgpu_device pointer
@@ -1218,19 +1243,20 @@ static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev, · 12 unmodified lines
12181243 amdgpu_vm_bo_relocated(&entry->base);
12191244 }
12201245
1221−/*
1222− * amdgpu_vm_update_directories - make sure that all directories are valid
1246+/**
1247+ * amdgpu_vm_update_pdes - make sure that all directories are valid
12231248 *
12241249 * @adev: amdgpu_device pointer
12251250 * @vm: requested vm
1251+ * @direct: submit directly to the paging queue
12261252 *
12271253 * Makes sure all directories are up to date.
12281254 *
12291255 * Returns:
12301256 * 0 for success, error for failure.
12311257 */
1232−int amdgpu_vm_update_directories(struct amdgpu_device *adev,
1233− struct amdgpu_vm *vm)
1258+int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
1259+ struct amdgpu_vm *vm, bool direct)
12341260 {
12351261 struct amdgpu_vm_update_params params;
12361262 int r;
@@ -1241,6 +1267,7 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev, · 4 unmodified lines
12411267 memset(&params, 0, sizeof(params));
12421268 params.adev = adev;
12431269 params.vm = vm;
1270+ params.direct = direct;
12441271
12451272 r = vm->update_funcs->prepare(&params, AMDGPU_FENCE_OWNER_VM, NULL);
12461273 if (r)
@@ -1268,7 +1295,7 @@ error: · 21 unmodified lines
12681295 return r;
12691296 }
12701297
1271−/**
1298+/*
12721299 * amdgpu_vm_update_flags - figure out flags for PTE updates
12731300 *
12741301 * Make sure to set the right flags for the PTEs at the desired level.
@@ -1391,7 +1418,11 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, · 116 unmodified lines
13911418 uint64_t incr, entry_end, pe_start;
13921419 struct amdgpu_bo *pt;
13931420
1394− r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor);
1421+ /* make sure that the page tables covering the address range are
1422+ * actually allocated
1423+ */
1424+ r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor,
1425+ params->direct);
13951426 if (r)
13961427 return r;
13971428
@@ -1463,7 +1494,12 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, · 65 unmodified lines
14631494 } while (frag_start < entry_end);
14641495
14651496 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1466− /* Free all child entries */
1497+ /* Free all child entries.
1498+ * Update the tables with the flags and addresses and free up subsequent
1499+ * tables in the case of huge pages or freed up areas.
1500+ * This is the maximum you can free, because all other page tables are not
1501+ * completely covered by the range and so potentially still in use.
1502+ */
14671503 while (cursor.pfn < frag_start) {
14681504 amdgpu_vm_free_pts(adev, params->vm, &cursor);
14691505 amdgpu_vm_pt_next(adev, &cursor);
@@ -1482,13 +1518,14 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, · 12 unmodified lines
14821518 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
14831519 *
14841520 * @adev: amdgpu_device pointer
1485− * @exclusive: fence we need to sync to
1486− * @pages_addr: DMA addresses to use for mapping
14871521 * @vm: requested vm
1522+ * @direct: direct submission in a page fault
1523+ * @exclusive: fence we need to sync to
14881524 * @start: start of mapped range
14891525 * @last: last mapped entry
14901526 * @flags: flags for the entries
14911527 * @addr: addr to set the area to
1528+ * @pages_addr: DMA addresses to use for mapping
14921529 * @fence: optional resulting fence
14931530 *
14941531 * Fill in the page table entries between @start and @last.
@@ -1497,11 +1534,11 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, · 2 unmodified lines
14971534 * 0 for success, -EINVAL for failure.
14981535 */
14991536 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1537+ struct amdgpu_vm *vm, bool direct,
15001538 struct dma_fence *exclusive,
1501− dma_addr_t *pages_addr,
1502− struct amdgpu_vm *vm,
15031539 uint64_t start, uint64_t last,
15041540 uint64_t flags, uint64_t addr,
1541+ dma_addr_t *pages_addr,
15051542 struct dma_fence **fence)
15061543 {
15071544 struct amdgpu_vm_update_params params;
@@ -1511,6 +1548,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, · 3 unmodified lines
15111548 memset(&params, 0, sizeof(params));
15121549 params.adev = adev;
15131550 params.vm = vm;
1551+ params.direct = direct;
15141552 params.pages_addr = pages_addr;
15151553
15161554 /* sync to everything except eviction fences on unmapping */
@@ -1569,27 +1607,8 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, · 52 unmodified lines
15691607 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
15701608 flags &= ~AMDGPU_PTE_WRITEABLE;
15711609
1572− flags &= ~AMDGPU_PTE_EXECUTABLE;
1573− flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;

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drivers/gpu/drm/amd/amdgpu/navi10_ih.c+2−2

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drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h+1−0

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drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c+0−1

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drivers/gpu/drm/amd/amdgpu/nv.c+63−21

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drivers/gpu/drm/amd/amdgpu/psp_v10_0.c+43−1

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drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c+20−142

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drivers/gpu/drm/amd/amdgpu/si.c+11−0

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drivers/gpu/drm/amd/amdgpu/soc15.c+125−63

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drivers/gpu/drm/amd/amdgpu/soc15.h+2−0

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drivers/gpu/drm/amd/amdgpu/umc_v6_0.c+37−0

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drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c+21−10

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drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c+22−11

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drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c+0−1

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drivers/gpu/drm/amd/amdgpu/vega10_ih.c+40−1

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drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c+0−1

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drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c+0−1

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drivers/gpu/drm/amd/amdgpu/vi.c+79−5

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drivers/gpu/drm/amd/amdgpu/vi.h+3−0

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drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c+5−3

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drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h+70−69

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drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm+1−0

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drivers/gpu/drm/amd/amdkfd/kfd_chardev.c+10−9

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drivers/gpu/drm/amd/amdkfd/kfd_crat.c+8−1

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drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c+9−9

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drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c+83−25

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drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h+5−1

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drivers/gpu/drm/amd/amdkfd/kfd_events.c+8−7

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drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c+10−2

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drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c+1−2

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drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c+5−0

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drivers/gpu/drm/amd/amdkfd/kfd_iommu.c+3−3

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drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c+3−0

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drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c+4−33

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drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c+3−0

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drivers/gpu/drm/amd/amdkfd/kfd_priv.h+21−5

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drivers/gpu/drm/amd/amdkfd/kfd_process.c+18−14

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drivers/gpu/drm/amd/amdkfd/kfd_topology.c+25−0

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drivers/gpu/drm/amd/amdkfd/kfd_topology.h+3−0

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drivers/gpu/drm/amd/display/Kconfig+18−10

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drivers/gpu/drm/amd/display/Makefile+7−0

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drivers/gpu/drm/amd/display/amdgpu_dm/Makefile+4−0

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drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+343−30

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drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h+13−1

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drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c+2−0

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drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c+7−2

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drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c+52−0

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drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c+346−0

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drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h+66−0

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drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c+8−9

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drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c+8−2

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drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+23−24

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drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c+118−35

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drivers/gpu/drm/amd/display/dc/Makefile+4−0

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drivers/gpu/drm/amd/display/dc/bios/bios_parser.c+2−5

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drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c+2−6

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drivers/gpu/drm/amd/display/dc/calcs/Makefile+12−7

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drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c+25−0

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drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c+7−7

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drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c+2−2

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drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c+8−5

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drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c+80−106

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drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h+1−0

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drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c+201−103

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drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h+3−1

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drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c+18−20

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drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h+2−2

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drivers/gpu/drm/amd/display/dc/core/dc.c+209−76

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drivers/gpu/drm/amd/display/dc/core/dc_link.c+308−37

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drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c+92−33

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drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+38−6

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drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c+2−1

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drivers/gpu/drm/amd/display/dc/core/dc_resource.c+57−23

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drivers/gpu/drm/amd/display/dc/core/dc_stream.c+2−2

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drivers/gpu/drm/amd/display/dc/dc.h+34−10

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drivers/gpu/drm/amd/display/dc/dc_ddc_types.h+2−1

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drivers/gpu/drm/amd/display/dc/dc_dsc.h+12−2

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drivers/gpu/drm/amd/display/dc/dc_hw_types.h+38−53

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drivers/gpu/drm/amd/display/dc/dc_link.h+16−2

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drivers/gpu/drm/amd/display/dc/dc_stream.h+23−0

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drivers/gpu/drm/amd/display/dc/dc_types.h+22−0

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drivers/gpu/drm/amd/display/dc/dce/dce_abm.c+7−3

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drivers/gpu/drm/amd/display/dc/dce/dce_aux.c+86−7

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drivers/gpu/drm/amd/display/dc/dce/dce_aux.h+183−4

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drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c+0−3

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drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h+1−0

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drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c+4−4

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drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c+50−2

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drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c+8−36

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drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c+49−2

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drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c+49−3

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drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c+49−3

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drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c+49−2

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c+8−14

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c+2−2

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h+5−0

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c+8−0

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h+28−0

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c+18−9

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h+49−1

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c+7−1

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h+2−0

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c+13−47

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h+2−3

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c+41−2

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c+62−0

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h+5−0

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drivers/gpu/drm/amd/display/dc/dcn20/Makefile+12−7

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c+4−53

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h+1−1

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c+1−8

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h+49−40

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c+1−1

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c+0−4

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c+7−5

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h+1−0

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c+478−162

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h+16−0

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h+7−0

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c+5−1

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c+220−136

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h+31−3

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c+4−0

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drivers/gpu/drm/amd/display/dc/dcn21/Makefile+13−8

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drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c+89−27

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drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h+24−10

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drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c+3−1

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drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c+122−0

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drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h+33−0

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drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c+470−0

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drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h+61−0

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drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c+322−58

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drivers/gpu/drm/amd/display/dc/dm_cp_psp.h+49−0

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drivers/gpu/drm/amd/display/dc/dm_helpers.h+1−1

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drivers/gpu/drm/amd/display/dc/dm_pp_smu.h+1−4

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drivers/gpu/drm/amd/display/dc/dml/Makefile+12−7

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drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c+2−1

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drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c+10−2

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drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c+4−4

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drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c+4−4

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drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c+10−1

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drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h+2−1

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drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c+5−0

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drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h+1−0

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drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c+5−5

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drivers/gpu/drm/amd/display/dc/dsc/Makefile+12−7

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drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c+70−15

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drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c+0−3

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drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c+0−2

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drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c+0−2

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drivers/gpu/drm/amd/display/dc/hdcp/Makefile+28−0

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drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c+324−0

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drivers/gpu/drm/amd/display/dc/inc/core_types.h+4−5

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drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h+6−0

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drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h+5−0

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drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h+3−0

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drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h+11−1

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drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h+15−2

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drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h+1−2

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drivers/gpu/drm/arc/arcpgu_drv.c+13−3

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drivers/gpu/drm/arm/display/komeda/d71/d71_component.c+125−10

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drivers/gpu/drm/bridge/synopsys/dw-hdmi.c+82−1

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drivers/gpu/drm/drm_dp_mst_topology.c+884−300

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drivers/gpu/drm/i2c/tda998x_drv.c+4−5

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drivers/gpu/drm/i915/gem/i915_gem_context.c+5−0

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drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c+80−31

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drivers/gpu/drm/i915/gt/intel_engine_types.h+10−3

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drivers/gpu/drm/i915/gt/intel_gt_pm.c+8−0

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drivers/gpu/drm/i915/i915_cmd_parser.c+306−129

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drivers/gpu/drm/i915/i915_getparam.c+1−1

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drivers/infiniband/hw/cxgb4/cm.c+14−16

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drivers/isdn/capi/capi.c+1−1

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drivers/macintosh/windfarm_cpufreq_clamp.c+22−16

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drivers/md/dm-cache-target.c+2−26

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drivers/md/dm-clone-target.c+2−2

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drivers/md/raid0.c+1−1

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drivers/media/usb/stkwebcam/stk-webcam.c+1−2

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drivers/misc/fastrpc.c+1−0

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drivers/misc/mei/pci-me.c+8−5

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drivers/mmc/host/cqhci.c+2−1

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drivers/mmc/host/mxs-mmc.c+4−3

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drivers/mmc/host/renesas_sdhi_core.c+19−12

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drivers/mmc/host/sdhci-iproc.c+1−0

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drivers/mmc/host/sdhci-omap.c+1−1

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drivers/mmc/host/sh_mmcif.c+2−4

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drivers/mtd/nand/raw/au1550nd.c+2−3

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drivers/mtd/spi-nor/spi-nor.c+1−1

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drivers/net/bonding/bond_alb.c+1−1

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drivers/net/can/c_can/c_can.c+64−7

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drivers/net/can/c_can/c_can.h+1−0

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drivers/net/can/flexcan.c+9−2

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drivers/net/can/rx-offload.c+85−17

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drivers/net/can/spi/mcp251x.c+1−1

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drivers/net/can/ti_hecc.c+148−84

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drivers/net/can/usb/gs_usb.c+1−0

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drivers/net/can/usb/mcba_usb.c+1−2

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drivers/net/can/usb/peak_usb/pcan_usb.c+22−10

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drivers/net/can/xilinx_can.c+0−1

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drivers/net/dsa/b53/b53_common.c+0−1

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drivers/net/dsa/bcm_sf2.c+23−17

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drivers/net/dsa/microchip/ksz8795.c+0−4

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drivers/net/dsa/microchip/ksz8795_spi.c+4−3

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drivers/net/dsa/microchip/ksz9477_i2c.c+4−2

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drivers/net/dsa/microchip/ksz9477_reg.h+2−2

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drivers/net/dsa/microchip/ksz9477_spi.c+4−2

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drivers/net/dsa/microchip/ksz_common.c+1−1

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drivers/net/dsa/microchip/ksz_common.h+17−3

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drivers/net/dsa/sja1105/Kconfig+2−2

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drivers/net/dsa/sja1105/sja1105.h+2−2

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drivers/net/dsa/sja1105/sja1105_dynamic_config.h+2−2

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drivers/net/dsa/sja1105/sja1105_ptp.h+2−2

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drivers/net/dsa/sja1105/sja1105_static_config.h+2−2

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drivers/net/dsa/sja1105/sja1105_tas.h+2−2

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drivers/net/ethernet/aquantia/atlantic/aq_main.c+1−3

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drivers/net/ethernet/aquantia/atlantic/aq_nic.c+18−16

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drivers/net/ethernet/aquantia/atlantic/aq_ring.c+2−1

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drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c+18−5

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drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c+15−2

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drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h+5−2

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drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h+19−0

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drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c+1−1

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drivers/net/ethernet/arc/emac_rockchip.c+3−0

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drivers/net/ethernet/broadcom/Kconfig+3−1

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drivers/net/ethernet/broadcom/bnxt/bnxt.c+4−6

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drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c+67−45

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drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.h+2−1

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drivers/net/ethernet/broadcom/genet/bcmgenet.c+12−6

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drivers/net/ethernet/broadcom/genet/bcmgenet.h+1−0

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drivers/net/ethernet/broadcom/genet/bcmmii.c+41−3

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drivers/net/ethernet/cadence/macb_main.c+6−6

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drivers/net/ethernet/cavium/common/cavium_ptp.h+1−1

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drivers/net/ethernet/cavium/octeon/octeon_mgmt.c+1−1

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drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c+16−12

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drivers/net/ethernet/chelsio/cxgb4/sge.c+2−6

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drivers/net/ethernet/cortina/gemini.h+1−1

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drivers/net/ethernet/faraday/ftgmac100.c+12−13

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drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c+49−1

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drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.h+1−1

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drivers/net/ethernet/freescale/dpaa2/dpni.h+4−1

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drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h+1−1

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drivers/net/ethernet/freescale/dpaa2/dprtc.h+1−1

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drivers/net/ethernet/freescale/fec_main.c+3−1

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drivers/net/ethernet/freescale/fec_ptp.c+2−2

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drivers/net/ethernet/google/gve/gve_rx.c+2−0

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drivers/net/ethernet/google/gve/gve_tx.c+22−2

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drivers/net/ethernet/hisilicon/hip04_eth.c+9−7

This diff is large: its 60 lines aren’t shown here.

drivers/net/ethernet/hisilicon/hns/hnae.c+0−1

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drivers/net/ethernet/hisilicon/hns/hnae.h+0−3

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drivers/net/ethernet/hisilicon/hns/hns_enet.c+1−21

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drivers/net/ethernet/hisilicon/hns3/hnae3.h+3−1

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drivers/net/ethernet/hisilicon/hns3/hns3_enet.h+1−1

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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h+1−1

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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.h+1−1

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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c+37−2

This diff is large: its 93 lines aren’t shown here.

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h+2−1

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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.h+1−1

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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c+9−2

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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h+1−1

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drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c+25−3

This diff is large: its 82 lines aren’t shown here.

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/net/ethernet/i825xx/lasi_82596.c+3−1

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drivers/net/ethernet/i825xx/lib82596.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/i825xx/sni_82596.c+3−1

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/ibm/ibmvnic.c+3−5

This diff is large: its 16 lines aren’t shown here.

drivers/net/ethernet/intel/e1000/e1000_ethtool.c+3−4

This diff is large: its 33 lines aren’t shown here.

drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h+2−0

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/intel/i40e/i40e_common.c+2−1

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drivers/net/ethernet/intel/i40e/i40e_xsk.c+2−13

This diff is large: its 36 lines aren’t shown here.

drivers/net/ethernet/intel/iavf/iavf_main.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/intel/ice/ice_sched.c+1−1

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drivers/net/ethernet/intel/igb/e1000_82575.c+1−1

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drivers/net/ethernet/intel/igb/igb_main.c+7−5

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drivers/net/ethernet/intel/igc/igc_main.c+4−3

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drivers/net/ethernet/intel/ixgbe/ixgbe_main.c+0−1

This diff is large: its 8 lines aren’t shown here.

drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c+2−8

This diff is large: its 24 lines aren’t shown here.

drivers/net/ethernet/marvell/mvneta_bm.h+20−12

This diff is large: its 45 lines aren’t shown here.

drivers/net/ethernet/mediatek/mtk_eth_soc.c+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx4/main.c+1−2

This diff is large: its 10 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx4/resource_tracker.c+26−16

This diff is large: its 64 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en.h+2−1

This diff is large: its 17 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en/hv_vhca_stats.c+2−2

This diff is large: its 16 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c+9−3

This diff is large: its 34 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h+6−7

This diff is large: its 30 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.h+25−4

This diff is large: its 56 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c+114−76

This diff is large: its 369 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en_main.c+11−2

This diff is large: its 39 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en_rep.c+2−2

This diff is large: its 11 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en_rx.c+4−1

This diff is large: its 13 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c+3−12

This diff is large: its 33 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en_stats.c+10−6

This diff is large: its 45 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en_stats.h+6−4

This diff is large: its 30 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c+28−8

This diff is large: its 88 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/en_tx.c+20−15

This diff is large: its 73 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c+1−2

This diff is large: its 17 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_termtbl.c+17−6

This diff is large: its 40 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c+3−1

This diff is large: its 12 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c+2−1

This diff is large: its 10 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/health.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/mr.c+1−7

This diff is large: its 19 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c+6−6

This diff is large: its 26 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlxsw/core.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/net/ethernet/mscc/ocelot.c+14−6

This diff is large: its 54 lines aren’t shown here.

drivers/net/ethernet/mscc/ocelot.h+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/netronome/nfp/nfp_net_repr.c+0−18

This diff is large: its 32 lines aren’t shown here.

drivers/net/ethernet/nxp/lpc_eth.c+0−3

This diff is large: its 10 lines aren’t shown here.

drivers/net/ethernet/pensando/ionic/ionic_lif.c+2−0

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/pensando/ionic/ionic_lif.h+2−0

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/pensando/ionic/ionic_main.c+2−0

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/pensando/ionic/ionic_stats.c+19−10

This diff is large: its 89 lines aren’t shown here.

drivers/net/ethernet/qlogic/qed/qed_main.c+21−6

This diff is large: its 57 lines aren’t shown here.

drivers/net/ethernet/qlogic/qed/qed_sriov.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/qlogic/qede/qede_main.c+10−2

This diff is large: its 19 lines aren’t shown here.

drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c+2−2

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drivers/net/ethernet/realtek/r8169_main.c+18−24

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drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c+2−1

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drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c+2−2

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drivers/net/ethernet/stmicro/stmmac/dwmac5.c+1−0

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drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c+2−1

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drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c+2−1

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drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c+3−1

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drivers/net/ethernet/stmicro/stmmac/mmc_core.c+4−2

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drivers/net/ethernet/stmicro/stmmac/stmmac_main.c+48−37

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drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c+1−1

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drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c+99−38

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drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c+1−1

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drivers/net/ethernet/ti/davinci_cpdma.c+1−1

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drivers/net/fjes/fjes_main.c+14−1

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drivers/net/hamradio/bpqether.c+0−22

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drivers/net/hyperv/netvsc_drv.c+11−4

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drivers/net/ipvlan/ipvlan_main.c+0−2

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drivers/net/macsec.c+0−18

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drivers/net/macvlan.c+0−19

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drivers/net/netdevsim/dev.c+5−0

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drivers/net/netdevsim/fib.c+2−1

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drivers/net/phy/bcm7xxx.c+1−0

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drivers/net/phy/micrel.c+37−5

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drivers/net/phy/phy-c45.c+2−0

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drivers/net/phy/phy.c+0−3

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drivers/net/phy/phy_device.c+10−1

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drivers/net/phy/phylink.c+17−1

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drivers/net/phy/smsc.c+1−0

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drivers/net/ppp/ppp_generic.c+0−2

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drivers/net/team/team.c+12−4

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drivers/net/tun.c+2−2

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drivers/net/usb/cdc_ether.c+7−0

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drivers/net/usb/cdc_ncm.c+3−3

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drivers/net/usb/hso.c+9−4

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drivers/net/usb/lan78xx.c+10−7

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drivers/net/usb/qmi_wwan.c+2−0

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drivers/net/usb/r8152.c+1−0

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drivers/net/usb/sr9800.c+1−1

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drivers/net/vrf.c+0−1

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drivers/net/vxlan.c+50−12

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drivers/net/wimax/i2400m/op-rfkill.c+1−1

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drivers/net/wireless/ath/ath10k/core.c+9−6

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drivers/net/wireless/intel/iwlwifi/fw/acpi.c+6−4

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drivers/net/wireless/intel/iwlwifi/fw/api/scan.h+20−2

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drivers/net/wireless/intel/iwlwifi/fw/dbg.c+1−0

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drivers/net/wireless/intel/iwlwifi/fw/file.h+3−0

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drivers/net/wireless/intel/iwlwifi/iwl-csr.h+1−0

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drivers/net/wireless/intel/iwlwifi/iwl-io.h+6−6

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drivers/net/wireless/intel/iwlwifi/iwl-prph.h+5−0

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drivers/net/wireless/intel/iwlwifi/mvm/fw.c+30−13

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drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c+5−4

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drivers/net/wireless/intel/iwlwifi/mvm/mvm.h+6−0

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drivers/net/wireless/intel/iwlwifi/mvm/scan.c+32−8

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drivers/net/wireless/intel/iwlwifi/mvm/sta.c+83−57

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drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c+25−11

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drivers/net/wireless/intel/iwlwifi/pcie/drv.c+146−149

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drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c+25−0

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drivers/net/wireless/intel/iwlwifi/pcie/trans.c+19−6

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drivers/net/wireless/intersil/hostap/hostap_hw.c+0−25

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drivers/net/wireless/mac80211_hwsim.c+1−1

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drivers/net/wireless/mediatek/mt76/Makefile+2−0

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drivers/net/wireless/mediatek/mt76/dma.c+4−2

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drivers/net/wireless/mediatek/mt76/mt76.h+4−2

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drivers/net/wireless/mediatek/mt76/mt76x2/pci.c+2−0

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drivers/net/wireless/mediatek/mt76/pci.c+46−0

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drivers/net/wireless/ralink/rt2x00/rt2x00.h+0−1

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drivers/net/wireless/ralink/rt2x00/rt2x00debug.c+1−1

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drivers/net/wireless/realtek/rtlwifi/pci.c+2−1

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drivers/net/wireless/realtek/rtlwifi/ps.c+6−0

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drivers/net/wireless/virt_wifi.c+52−2

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drivers/net/xen-netback/interface.c+0−1

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drivers/nfc/fdp/i2c.c+1−1

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drivers/nfc/pn533/usb.c+8−1

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drivers/nfc/st21nfca/core.c+1−0

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drivers/nvme/host/core.c+68−26

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drivers/nvme/host/fabrics.h+1−2

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drivers/nvme/host/multipath.c+6−5

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drivers/nvme/host/nvme.h+4−1

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drivers/nvme/host/pci.c+49−34

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drivers/nvme/host/rdma.c+16−0

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drivers/nvme/host/tcp.c+12−1

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drivers/nvme/target/loop.c+3−1

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drivers/of/of_reserved_mem.c+3−1

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drivers/of/unittest.c+1−0

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drivers/opp/core.c+3−13

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drivers/opp/of.c+7−2

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drivers/parisc/sba_iommu.c+0−8

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drivers/pci/pci.c+11−13

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drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c+54−70

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drivers/pinctrl/aspeed/pinmux-aspeed.h+2−1

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drivers/pinctrl/bcm/pinctrl-iproc-gpio.c+2−10

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drivers/pinctrl/bcm/pinctrl-ns2-mux.c+2−2

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drivers/pinctrl/berlin/pinctrl-as370.c+1−1

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drivers/pinctrl/intel/pinctrl-cherryview.c+13−17

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drivers/pinctrl/intel/pinctrl-intel.c+34−14

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drivers/pinctrl/mvebu/pinctrl-armada-37xx.c+13−13

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drivers/pinctrl/pinctrl-stmfx.c+1−15

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drivers/platform/x86/classmate-laptop.c+0−12

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drivers/platform/x86/i2c-multi-instantiate.c+1−0

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drivers/platform/x86/intel_punit_ipc.c+1−2

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drivers/ptp/Kconfig+2−2

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drivers/pwm/core.c+1−8

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drivers/pwm/pwm-bcm-iproc.c+1−0

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drivers/regulator/core.c+13−0

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drivers/regulator/da9062-regulator.c+47−71

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drivers/regulator/fixed.c+2−3

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drivers/regulator/lochnagar-regulator.c+1−0

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drivers/regulator/of_regulator.c+18−9

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drivers/regulator/pfuze100-regulator.c+7−1

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drivers/regulator/qcom-rpmh-regulator.c+2−2

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drivers/regulator/ti-abb-regulator.c+8−18

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drivers/reset/core.c+3−2

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drivers/s390/cio/cio.h+1−0

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drivers/s390/cio/css.c+6−1

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drivers/s390/cio/device.c+1−1

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drivers/s390/crypto/zcrypt_api.c+1−2

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drivers/s390/net/qeth_l2_main.c+15−8

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drivers/s390/scsi/zfcp_fsf.c+13−3

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drivers/scsi/Kconfig+1−1

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drivers/scsi/ch.c+0−1

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drivers/scsi/device_handler/scsi_dh_alua.c+16−5

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drivers/scsi/hpsa.c+4−0

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drivers/scsi/lpfc/lpfc_init.c+0−2

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drivers/scsi/lpfc/lpfc_nportdisc.c+2−2

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drivers/scsi/lpfc/lpfc_scsi.c+0−2

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drivers/scsi/lpfc/lpfc_sli.c+1−1

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drivers/scsi/qla2xxx/qla_attr.c+3−4

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drivers/scsi/qla2xxx/qla_bsg.c+3−3

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drivers/scsi/qla2xxx/qla_isr.c+0−2

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drivers/scsi/qla2xxx/qla_mbx.c+2−1

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drivers/scsi/qla2xxx/qla_os.c+8−0

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drivers/scsi/scsi_error.c+3−0

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drivers/scsi/scsi_lib.c+3−1

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drivers/scsi/scsi_sysfs.c+10−1

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drivers/scsi/sd.c+4−2

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drivers/scsi/sni_53c710.c+1−3

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drivers/scsi/ufs/ufs_bsg.c+4−0

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drivers/soc/imx/gpc.c+4−4

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drivers/soc/imx/soc-imx-scu.c+1−1

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drivers/soundwire/Kconfig+1−0

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drivers/soundwire/intel.c+2−2

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drivers/soundwire/slave.c+2−1

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drivers/staging/Kconfig+2−0

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drivers/staging/Makefile+1−0

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drivers/staging/exfat/Kconfig+2−1

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drivers/staging/exfat/Makefile+1−1

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drivers/staging/exfat/exfat.h+1−1

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drivers/staging/exfat/exfat_blkdev.c+1−1

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drivers/staging/exfat/exfat_cache.c+1−1

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drivers/staging/exfat/exfat_core.c+1−1

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drivers/staging/exfat/exfat_nls.c+1−1

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drivers/staging/exfat/exfat_super.c+4−3

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drivers/staging/exfat/exfat_upcase.c+1−1

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drivers/staging/fbtft/Kconfig+1−11

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drivers/staging/fbtft/Makefile+0−4

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drivers/staging/fbtft/fbtft-core.c+5−2

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drivers/staging/fbtft/fbtft_device.c+0−1261

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drivers/staging/fbtft/flexfb.c+0−851

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drivers/staging/octeon/ethernet-tx.c+5−4

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drivers/staging/octeon/octeon-stubs.h+1−1

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drivers/staging/rtl8188eu/hal/hal8188e_rate_adaptive.c+1−1

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drivers/staging/rtl8188eu/os_dep/usb_intf.c+4−2

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drivers/staging/speakup/sysfs-driver-speakup+369−0

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drivers/staging/vboxsf/Kconfig+10−0

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drivers/staging/vboxsf/Makefile+5−0

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drivers/staging/vboxsf/TODO+7−0

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drivers/staging/vboxsf/dir.c+418−0

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drivers/staging/vboxsf/file.c+370−0

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drivers/staging/vboxsf/shfl_hostintf.h+901−0

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drivers/staging/vboxsf/super.c+501−0

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drivers/staging/vboxsf/utils.c+551−0

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drivers/staging/vboxsf/vboxsf_wrappers.c+371−0

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drivers/staging/vboxsf/vfsmod.h+137−0

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drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c+2−2

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drivers/staging/vc04_services/bcm2835-audio/bcm2835-vchiq.c+1−0

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drivers/staging/vt6655/device_main.c+3−1

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drivers/staging/wlan-ng/cfg80211.c+2−4

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drivers/target/iscsi/cxgbit/cxgbit_cm.c+2−1

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drivers/target/target_core_device.c+0−21

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drivers/thermal/cpu_cooling.c+7−7

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drivers/thunderbolt/nhi_ops.c+0−1

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drivers/thunderbolt/switch.c+11−17

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drivers/tty/n_hdlc.c+5−0

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drivers/tty/serial/8250/8250_men_mcb.c+4−4

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drivers/tty/serial/8250/8250_omap.c+3−2

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drivers/tty/serial/Kconfig+1−0

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drivers/tty/serial/fsl_linflexuart.c+14−7

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drivers/tty/serial/fsl_lpuart.c+1−1

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drivers/tty/serial/imx.c+2−2

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drivers/tty/serial/owl-uart.c+1−1

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drivers/tty/serial/rda-uart.c+1−1

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drivers/tty/serial/serial_core.c+2−0

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drivers/tty/serial/serial_mctrl_gpio.c+3−0

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drivers/tty/serial/sh-sci.c+6−2

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drivers/tty/serial/uartlite.c+2−1

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drivers/tty/serial/xilinx_uartps.c+7−1

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drivers/usb/cdns3/cdns3-pci-wrap.c+2−1

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drivers/usb/cdns3/core.c+21−1

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drivers/usb/cdns3/ep0.c+9−3

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drivers/usb/cdns3/gadget.c+55−23

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drivers/usb/cdns3/host-export.h+0−1

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drivers/usb/cdns3/host.c+1−0

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drivers/usb/class/usblp.c+8−4

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drivers/usb/core/config.c+5−0

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drivers/usb/dwc3/Kconfig+1−0

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drivers/usb/dwc3/core.c+1−2

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drivers/usb/dwc3/drd.c+2−5

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drivers/usb/dwc3/dwc3-pci.c+1−1

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drivers/usb/dwc3/gadget.c+8−5

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drivers/usb/dwc3/host.c+2−5

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drivers/usb/gadget/composite.c+4−0

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drivers/usb/gadget/configfs.c+105−5

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drivers/usb/gadget/udc/Kconfig+1−1

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drivers/usb/gadget/udc/atmel_usba_udc.c+4−2

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drivers/usb/gadget/udc/core.c+11−0

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drivers/usb/gadget/udc/dummy_hcd.c+2−1

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drivers/usb/gadget/udc/fsl_udc_core.c+1−1

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drivers/usb/gadget/udc/lpc32xx_udc.c+5−5

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drivers/usb/gadget/udc/renesas_usb3.c+6−5

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drivers/usb/host/xhci-debugfs.c+12−12

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