lael-labs/linux

Documentation/block/index.rst+0−1

@@ -18,7 +18,6 @@ Block · 17 unmodified lines
18	kyber-iosched	18	kyber-iosched
19	null_blk	19	null_blk
20	pr	20	pr
21	request
22	stat	21	stat
23	switching-sched	22	switching-sched
24	writeback_cache_control	23	writeback_cache_control

Documentation/block/request.rst+0−99

@@ -1,99 +0,0 @@
1	============================
2	struct request documentation
3	============================
4
5	Jens Axboe <jens.axboe@oracle.com> 27/05/02
6
7
8	.. FIXME:
9	No idea about what does mean - seems just some noise, so comment it
10
11	1.0
12	Index
13
14	2.0 Struct request members classification
15
16	2.1 struct request members explanation
17
18	3.0
19
20
21	2.0
22
23
24
25	Short explanation of request members
26	====================================
27
28	Classification flags:
29
30	= ====================
31	D driver member
32	B block layer member
33	I I/O scheduler member
34	= ====================
35
36	Unless an entry contains a D classification, a device driver must not access
37	this member. Some members may contain D classifications, but should only be
38	access through certain macros or functions (eg ->flags).
39
40	<linux/blkdev.h>
41
42	=============================== ======= =======================================
43	Member Flag Comment
44	=============================== ======= =======================================
45	struct list_head queuelist BI Organization on various internal
46	queues
47
48	``void *elevator_private`` I I/O scheduler private data
49
50	unsigned char cmd[16] D Driver can use this for setting up
51	a cdb before execution, see
52	blk_queue_prep_rq
53
54	unsigned long flags DBI Contains info about data direction,
55	request type, etc.
56
57	int rq_status D Request status bits
58
59	kdev_t rq_dev DBI Target device
60
61	int errors DB Error counts
62
63	sector_t sector DBI Target location
64
65	unsigned long hard_nr_sectors B Used to keep sector sane
66
67	unsigned long nr_sectors DBI Total number of sectors in request
68
69	unsigned long hard_nr_sectors B Used to keep nr_sectors sane
70
71	unsigned short nr_phys_segments DB Number of physical scatter gather
72	segments in a request
73
74	unsigned short nr_hw_segments DB Number of hardware scatter gather
75	segments in a request
76
77	unsigned int current_nr_sectors DB Number of sectors in first segment
78	of request
79
80	unsigned int hard_cur_sectors B Used to keep current_nr_sectors sane
81
82	int tag DB TCQ tag, if assigned
83
84	``void *special`` D Free to be used by driver
85
86	``char *buffer`` D Map of first segment, also see
87	section on bouncing SECTION
88
89	``struct completion *waiting`` D Can be used by driver to get signalled
90	on request completion
91
92	``struct bio *bio`` DBI First bio in request
93
94	``struct bio *biotail`` DBI Last bio in request
95
96	``struct request_queue *q`` DB Request queue this request belongs to
97
98	``struct request_list *rl`` B Request list this request came from
99	=============================== ======= =======================================

Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml+4−1

 properties:
   compatible:
     enum:
+      - fsl,imx6sx-ldb
       - fsl,imx8mp-ldb
       - fsl,imx93-ldb
       properties:
         compatible:
           contains:
-            const: fsl,imx93-ldb
+            enum:
+              - fsl,imx6sx-ldb
+              - fsl,imx93-ldb
     then:
       properties:
         ports:

Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml+23−0

@@ -105,6 +105,29 @@ properties: · 104 unmodified lines
105	DSI output port node to the panel or the next bridge	105	DSI output port node to the panel or the next bridge
106	in the chain.	106	in the chain.
107		107
		108	properties:
		109	endpoint:
		110	$ref: /schemas/media/video-interfaces.yaml#
		111	unevaluatedProperties: false
		112
		113	properties:
		114	data-lanes:
		115	minItems: 1
		116	maxItems: 4
		117	uniqueItems: true
		118	items:
		119	enum: [ 1, 2, 3, 4 ]
		120
		121	lane-polarities:
		122	minItems: 1
		123	maxItems: 5
		124	description:
		125	The Samsung MIPI DSI IP requires that all the data lanes have
		126	the same polarity.
		127
		128	dependencies:
		129	lane-polarities: [data-lanes]
		130
108	required:	131	required:
109	- clock-names	132	- clock-names
110	- clocks	133	- clocks

Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.yaml+11−3

 $id: http://devicetree.org/schemas/display/bridge/toshiba,tc358767.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Toshiba TC358767 eDP bridge
+title: Toshiba TC358767/TC358867/TC9595 DSI/DPI/eDP bridge
 maintainers:
   - Andrey Gusakov <andrey.gusakov@cogentembedded.com>
-description: The TC358767 is bridge device which converts DSI/DPI to eDP/DP
+description: |
+  The TC358767/TC358867/TC9595 is bridge device which
+  converts DSI/DPI to eDP/DP .
 properties:
   compatible:
-    const: toshiba,tc358767
+    oneOf:
+      - items:
+          - enum:
+              - toshiba,tc358867
+              - toshiba,tc9595
+          - const: toshiba,tc358767
+      - const: toshiba,tc358767
   reg:
     enum:

Documentation/devicetree/bindings/display/panel/novatek,nt36523.yaml+11−5

 properties:
   compatible:
-    items:
+    oneOf:
-      - enum:
+      - items:
-          - xiaomi,elish-boe-nt36523
+          - enum:
-          - xiaomi,elish-csot-nt36523
+              - xiaomi,elish-boe-nt36523
-      - const: novatek,nt36523
+              - xiaomi,elish-csot-nt36523
+          - const: novatek,nt36523
+      - items:
+          - enum:
+              - lenovo,j606f-boe-nt36523w
+          - const: novatek,nt36523w
   reset-gpios:
     maxItems: 1
   reg: true
   ports: true
+  rotation: true
   backlight: true
 required:

Documentation/devicetree/bindings/display/panel/panel-simple.yaml+4−0

       - auo,t215hvn01
         # Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel
       - avic,tm070ddh03
+        # BOE EV121WXM-N10-1850 12.1" WXGA (1280x800) TFT LCD panel
+      - boe,ev121wxm-n10-1850
         # BOE HV070WSA-100 7.01" WSVGA TFT LCD panel
       - boe,hv070wsa-100
         # BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel
       - innolux,at043tn24
         # Innolux AT070TN92 7.0" WQVGA TFT LCD panel
       - innolux,at070tn92
+        # Innolux G070ACE-L01 7" WVGA (800x480) TFT LCD panel
+      - innolux,g070ace-l01
         # Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel
       - innolux,g070y2-l01
         # Innolux G070Y2-T02 7" WVGA (800x480) TFT LCD TTL panel

Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml+2−0

 properties:
   compatible:
     enum:
+      # Anberic RG353V-V2 5.0" 640x480 TFT LCD panel
+      - anbernic,rg353v-panel-v2
       # Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel
       - rocktech,jh057n00900
       # Xingbangda XBD599 5.99" 720x1440 TFT LCD panel

Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml+70−0

@@ -0,0 +1,70 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/display/panel/samsung,s6d7aa0.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Samsung S6D7AA0 MIPI-DSI LCD panel controller
	8
	9	maintainers:
	10	- Artur Weber <aweber.kernel@gmail.com>
	11
	12	allOf:
	13	- $ref: panel-common.yaml#
	14
	15	properties:
	16	compatible:
	17	items:
	18	- enum:
	19	# 1280x800 LSL080AL02 panel
	20	- samsung,lsl080al02
	21	# 1024x768 LSL080AL03 panel
	22	- samsung,lsl080al03
	23	# 1024x768 LTL101AT01 panel
	24	- samsung,ltl101at01
	25	- const: samsung,s6d7aa0
	26
	27	reg: true
	28
	29	backlight:
	30	description:
	31	Backlight to use for the panel. If this property is set on panels
	32	that have DSI-based backlight control (LSL080AL03 and LTL101AT01),
	33	it overrides the DSI-based backlight.
	34
	35	reset-gpios:
	36	description: Reset GPIO pin, usually GPIO_ACTIVE_LOW.
	37
	38	power-supply:
	39	description:
	40	Main power supply for the panel; the exact voltage differs between
	41	panels, and is usually somewhere around 3.3-5v.
	42
	43	vmipi-supply:
	44	description: VMIPI supply, usually 1.8v.
	45
	46	required:
	47	- compatible
	48	- reg
	49	- reset-gpios
	50
	51	additionalProperties: false
	52
	53	examples:
	54	- \|
	55	#include <dt-bindings/gpio/gpio.h>
	56
	57	dsi {
	58	#address-cells = <1>;
	59	#size-cells = <0>;
	60
	61	panel@0 {
	62	compatible = "samsung,lsl080al02", "samsung,s6d7aa0";
	63	reg = <0>;
	64	power-supply = <&display_3v3_supply>;
	65	reset-gpios = <&gpf0 4 GPIO_ACTIVE_LOW>;
	66	backlight = <&backlight>;
	67	};
	68	};
	69
	70	...

Documentation/devicetree/bindings/media/i2c/ovti,ov2685.yaml+1−0

@@ -49,6 +49,7 @@ properties: · 48 unmodified lines
49		49
50	properties:	50	properties:
51	data-lanes:	51	data-lanes:
		52	minItems: 1
52	maxItems: 2	53	maxItems: 2
53		54
54	required:	55	required:

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml+2−11

 properties:
   clocks:
     minItems: 3
-    items:
+    maxItems: 4
-      - description: PCIe bridge clock.
-      - description: PCIe bus clock.
-      - description: PCIe PHY clock.
-      - description: Additional required clock entry for imx6sx-pcie,
-           imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
   clock-names:
     minItems: 3
-    items:
+    maxItems: 4
-      - const: pcie
-      - const: pcie_bus
-      - enum: [ pcie_phy, pcie_aux ]
-      - enum: [ pcie_inbound_axi, pcie_aux ]
   num-lanes:
     const: 1

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml+38−0

@@ -31,6 +31,19 @@ properties: · 30 unmodified lines
31	- const: dbi	31	- const: dbi
32	- const: addr_space	32	- const: addr_space
33		33
		34	clocks:
		35	minItems: 3
		36	items:
		37	- description: PCIe bridge clock.
		38	- description: PCIe bus clock.
		39	- description: PCIe PHY clock.
		40	- description: Additional required clock entry for imx6sx-pcie,
		41	imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
		42
		43	clock-names:
		44	minItems: 3
		45	maxItems: 4
		46
34	interrupts:	47	interrupts:
35	items:	48	items:
36	- description: builtin eDMA interrupter.	49	- description: builtin eDMA interrupter.
@@ -49,6 +62,31 @@ required: · 12 unmodified lines
49	allOf:	62	allOf:
50	- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#	63	- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
51	- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#	64	- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
		65	- if:
		66	properties:
		67	compatible:
		68	enum:
		69	- fsl,imx8mq-pcie-ep
		70	then:
		71	properties:
		72	clocks:
		73	minItems: 4
		74	clock-names:
		75	items:
		76	- const: pcie
		77	- const: pcie_bus
		78	- const: pcie_phy
		79	- const: pcie_aux
		80	else:
		81	properties:
		82	clocks:
		83	maxItems: 3
		84	clock-names:
		85	items:
		86	- const: pcie
		87	- const: pcie_bus
		88	- const: pcie_aux
		89
52		90
53	unevaluatedProperties: false	91	unevaluatedProperties: false
54		92

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml+77−0

@@ -40,6 +40,19 @@ properties: · 39 unmodified lines
40	- const: dbi	40	- const: dbi
41	- const: config	41	- const: config
42		42
		43	clocks:
		44	minItems: 3
		45	items:
		46	- description: PCIe bridge clock.
		47	- description: PCIe bus clock.
		48	- description: PCIe PHY clock.
		49	- description: Additional required clock entry for imx6sx-pcie,
		50	imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
		51
		52	clock-names:
		53	minItems: 3
		54	maxItems: 4
		55
43	interrupts:	56	interrupts:
44	items:	57	items:
45	- description: builtin MSI controller.	58	- description: builtin MSI controller.
@@ -77,6 +90,70 @@ required: · 31 unmodified lines
77	allOf:	90	allOf:
78	- $ref: /schemas/pci/snps,dw-pcie.yaml#	91	- $ref: /schemas/pci/snps,dw-pcie.yaml#
79	- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#	92	- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
		93	- if:
		94	properties:
		95	compatible:
		96	enum:
		97	- fsl,imx6sx-pcie
		98	then:
		99	properties:
		100	clocks:
		101	minItems: 4
		102	clock-names:
		103	items:
		104	- const: pcie
		105	- const: pcie_bus
		106	- const: pcie_phy
		107	- const: pcie_inbound_axi
		108
		109	- if:
		110	properties:
		111	compatible:
		112	enum:
		113	- fsl,imx8mq-pcie
		114	then:
		115	properties:
		116	clocks:
		117	minItems: 4
		118	clock-names:
		119	items:
		120	- const: pcie
		121	- const: pcie_bus
		122	- const: pcie_phy
		123	- const: pcie_aux
		124
		125	- if:
		126	properties:
		127	compatible:
		128	enum:
		129	- fsl,imx6q-pcie
		130	- fsl,imx6qp-pcie
		131	- fsl,imx7d-pcie
		132	then:
		133	properties:
		134	clocks:
		135	maxItems: 3
		136	clock-names:
		137	items:
		138	- const: pcie
		139	- const: pcie_bus
		140	- const: pcie_phy
		141
		142	- if:
		143	properties:
		144	compatible:
		145	enum:
		146	- fsl,imx8mm-pcie
		147	- fsl,imx8mp-pcie
		148	then:
		149	properties:
		150	clocks:
		151	maxItems: 3
		152	clock-names:
		153	items:
		154	- const: pcie
		155	- const: pcie_bus
		156	- const: pcie_aux
80		157
81	unevaluatedProperties: false	158	unevaluatedProperties: false
82		159

Documentation/gpu/rfc/index.rst+4−0

@@ -31,3 +31,7 @@ host such documentation: · 30 unmodified lines
31	.. toctree::	31	.. toctree::
32		32
33	i915_vm_bind.rst	33	i915_vm_bind.rst
		34
		35	.. toctree::
		36
		37	xe.rst

Documentation/gpu/rfc/xe.rst+235−0

@@ -0,0 +1,235 @@
	1	==========================
	2	Xe – Merge Acceptance Plan
	3	==========================
	4	Xe is a new driver for Intel GPUs that supports both integrated and
	5	discrete platforms starting with Tiger Lake (first Intel Xe Architecture).
	6
	7	This document aims to establish a merge plan for the Xe, by writing down clear
	8	pre-merge goals, in order to avoid unnecessary delays.
	9
	10	Xe – Overview
	11	=============
	12	The main motivation of Xe is to have a fresh base to work from that is
	13	unencumbered by older platforms, whilst also taking the opportunity to
	14	rearchitect our driver to increase sharing across the drm subsystem, both
	15	leveraging and allowing us to contribute more towards other shared components
	16	like TTM and drm/scheduler.
	17
	18	This is also an opportunity to start from the beginning with a clean uAPI that is
	19	extensible by design and already aligned with the modern userspace needs. For
	20	this reason, the memory model is solely based on GPU Virtual Address space
	21	bind/unbind (‘VM_BIND’) of GEM buffer objects (BOs) and execution only supporting
	22	explicit synchronization. With persistent mapping across the execution, the
	23	userspace does not need to provide a list of all required mappings during each
	24	submission.
	25
	26	The new driver leverages a lot from i915. As for display, the intent is to share
	27	the display code with the i915 driver so that there is maximum reuse there.
	28
	29	As for the power management area, the goal is to have a much-simplified support
	30	for the system suspend states (S-states), PCI device suspend states (D-states),
	31	GPU/Render suspend states (R-states) and frequency management. It should leverage
	32	as much as possible all the existent PCI-subsystem infrastructure (pm and
	33	runtime_pm) and underlying firmware components such PCODE and GuC for the power
	34	states and frequency decisions.
	35
	36	Repository:
	37
	38	https://gitlab.freedesktop.org/drm/xe/kernel (branch drm-xe-next)
	39
	40	Xe – Platforms
	41	==============
	42	Currently, Xe is already functional and has experimental support for multiple
	43	platforms starting from Tiger Lake, with initial support in userspace implemented
	44	in Mesa (for Iris and Anv, our OpenGL and Vulkan drivers), as well as in NEO
	45	(for OpenCL and Level0).
	46
	47	During a transition period, platforms will be supported by both Xe and i915.
	48	However, the force_probe mechanism existent in both drivers will allow only one
	49	official and by-default probe at a given time.
	50
	51	For instance, in order to probe a DG2 which PCI ID is 0x5690 by Xe instead of
	52	i915, the following set of parameters need to be used:
	53
	54	```
	55	i915.force_probe=!5690 xe.force_probe=5690
	56	```
	57
	58	In both drivers, the ‘.require_force_probe’ protection forces the user to use the
	59	force_probe parameter while the driver is under development. This protection is
	60	only removed when the support for the platform and the uAPI are stable. Stability
	61	which needs to be demonstrated by CI results.
	62
	63	In order to avoid user space regressions, i915 will continue to support all the
	64	current platforms that are already out of this protection. Xe support will be
	65	forever experimental and dependent on the usage of force_probe for these
	66	platforms.
	67
	68	When the time comes for Xe, the protection will be lifted on Xe and kept in i915.
	69
	70	Xe driver will be protected with both STAGING Kconfig and force_probe. Changes in
	71	the uAPI are expected while the driver is behind these protections. STAGING will
	72	be removed when the driver uAPI gets to a mature state where we can guarantee the
	73	‘no regression’ rule. Then force_probe will be lifted only for future platforms
	74	that will be productized with Xe driver, but not with i915.
	75
	76	Xe – Pre-Merge Goals
	77	====================
	78
	79	Drm_scheduler
	80	-------------
	81	Xe primarily uses Firmware based scheduling (GuC FW). However, it will use
	82	drm_scheduler as the scheduler ‘frontend’ for userspace submission in order to
	83	resolve syncobj and dma-buf implicit sync dependencies. However, drm_scheduler is
	84	not yet prepared to handle the 1-to-1 relationship between drm_gpu_scheduler and
	85	drm_sched_entity.
	86
	87	Deeper changes to drm_scheduler should not be required to get Xe accepted, but
	88	some consensus needs to be reached between Xe and other community drivers that
	89	could also benefit from this work, for coupling FW based/assisted submission such
	90	as the ARM’s new Mali GPU driver, and others.
	91
	92	As a key measurable result, the patch series introducing Xe itself shall not
	93	depend on any other patch touching drm_scheduler itself that was not yet merged
	94	through drm-misc. This, by itself, already includes the reach of an agreement for
	95	uniform 1 to 1 relationship implementation / usage across drivers.
	96
	97	GPU VA
	98	------
	99	Two main goals of Xe are meeting together here:
	100
	101	1) Have an uAPI that aligns with modern UMD needs.
	102
	103	2) Early upstream engagement.
	104
	105	RedHat engineers working on Nouveau proposed a new DRM feature to handle keeping
	106	track of GPU virtual address mappings. This is still not merged upstream, but
	107	this aligns very well with our goals and with our VM_BIND. The engagement with
	108	upstream and the port of Xe towards GPUVA is already ongoing.
	109
	110	As a key measurable result, Xe needs to be aligned with the GPU VA and working in
	111	our tree. Missing Nouveau patches should not block Xe and any needed GPUVA
	112	related patch should be independent and present on dri-devel or acked by
	113	maintainers to go along with the first Xe pull request towards drm-next.
	114
	115	DRM_VM_BIND
	116	-----------
	117	Nouveau, and Xe are all implementing ‘VM_BIND’ and new ‘Exec’ uAPIs in order to
	118	fulfill the needs of the modern uAPI. Xe merge should not be blocked on the
	119	development of a common new drm_infrastructure. However, the Xe team needs to
	120	engage with the community to explore the options of a common API.
	121
	122	As a key measurable result, the DRM_VM_BIND needs to be documented in this file
	123	below, or this entire block deleted if the consensus is for independent drivers
	124	vm_bind ioctls.
	125
	126	Although having a common DRM level IOCTL for VM_BIND is not a requirement to get
	127	Xe merged, it is mandatory to enforce the overall locking scheme for all major
	128	structs and list (so vm and vma). So, a consensus is needed, and possibly some
	129	common helpers. If helpers are needed, they should be also documented in this
	130	document.
	131
	132	ASYNC VM_BIND
	133	-------------
	134	Although having a common DRM level IOCTL for VM_BIND is not a requirement to get
	135	Xe merged, it is mandatory to have a consensus with other drivers and Mesa.
	136	It needs to be clear how to handle async VM_BIND and interactions with userspace
	137	memory fences. Ideally with helper support so people don't get it wrong in all
	138	possible ways.
	139
	140	As a key measurable result, the benefits of ASYNC VM_BIND and a discussion of
	141	various flavors, error handling and a sample API should be documented here or in
	142	a separate document pointed to by this document.
	143
	144	Userptr integration and vm_bind
	145	-------------------------------
	146	Different drivers implement different ways of dealing with execution of userptr.
	147	With multiple drivers currently introducing support to VM_BIND, the goal is to
	148	aim for a DRM consensus on what’s the best way to have that support. To some
	149	extent this is already getting addressed itself with the GPUVA where likely the
	150	userptr will be a GPUVA with a NULL GEM call VM bind directly on the userptr.
	151	However, there are more aspects around the rules for that and the usage of
	152	mmu_notifiers, locking and other aspects.
	153
	154	This task here has the goal of introducing a documentation of the basic rules.
	155
	156	The documentation needs to first live in this document (API session below) and
	157	then moved to another more specific document or at Xe level or at DRM level.
	158
	159	Documentation should include:
	160
	161	* The userptr part of the VM_BIND api.
	162
	163	* Locking, including the page-faulting case.
	164
	165	* O(1) complexity under VM_BIND.
	166
	167	Some parts of userptr like mmu_notifiers should become GPUVA or DRM helpers when
	168	the second driver supporting VM_BIND+userptr appears. Details to be defined when
	169	the time comes.
	170
	171	Long running compute: minimal data structure/scaffolding
	172	--------------------------------------------------------
	173	The generic scheduler code needs to include the handling of endless compute
	174	contexts, with the minimal scaffolding for preempt-ctx fences (probably on the
	175	drm_sched_entity) and making sure drm_scheduler can cope with the lack of job
	176	completion fence.
	177
	178	The goal is to achieve a consensus ahead of Xe initial pull-request, ideally with
	179	this minimal drm/scheduler work, if needed, merged to drm-misc in a way that any
	180	drm driver, including Xe, could re-use and add their own individual needs on top
	181	in a next stage. However, this should not block the initial merge.
	182
	183	This is a non-blocker item since the driver without the support for the long
	184	running compute enabled is not a showstopper.
	185
	186	Display integration with i915
	187	-----------------------------
	188	In order to share the display code with the i915 driver so that there is maximum
	189	reuse, the i915/display/ code is built twice, once for i915.ko and then for
	190	xe.ko. Currently, the i915/display code in Xe tree is polluted with many 'ifdefs'
	191	depending on the build target. The goal is to refactor both Xe and i915/display
	192	code simultaneously in order to get a clean result before they land upstream, so
	193	that display can already be part of the initial pull request towards drm-next.
	194
	195	However, display code should not gate the acceptance of Xe in upstream. Xe
	196	patches will be refactored in a way that display code can be removed, if needed,
	197	from the first pull request of Xe towards drm-next. The expectation is that when
	198	both drivers are part of the drm-tip, the introduction of cleaner patches will be
	199	easier and speed up.
	200
	201	Drm_exec
	202	--------
	203	Helper to make dma_resv locking for a big number of buffers is getting removed in
	204	the drm_exec series proposed in https://patchwork.freedesktop.org/patch/524376/
	205	If that happens, Xe needs to change and incorporate the changes in the driver.
	206	The goal is to engage with the Community to understand if the best approach is to
	207	move that to the drivers that are using it or if we should keep the helpers in
	208	place waiting for Xe to get merged.
	209
	210	This item ties into the GPUVA, VM_BIND, and even long-running compute support.
	211
	212	As a key measurable result, we need to have a community consensus documented in
	213	this document and the Xe driver prepared for the changes, if necessary.
	214
	215	Dev_coredump
	216	------------
	217
	218	Xe needs to align with other drivers on the way that the error states are
	219	dumped, avoiding a Xe only error_state solution. The goal is to use devcoredump
	220	infrastructure to report error states, since it produces a standardized way
	221	by exposing a virtual and temporary /sys/class/devcoredump device.
	222
	223	As the key measurable result, Xe driver needs to provide GPU snapshots captured
	224	at hang time through devcoredump, but without depending on any core modification
	225	of devcoredump infrastructure itself.
	226
	227	Later, when we are in-tree, the goal is to collaborate with devcoredump
	228	infrastructure with overall possible improvements, like multiple file support
	229	for better organization of the dumps, snapshot support, dmesg extra print,
	230	and whatever may make sense and help the overall infrastructure.
	231
	232	Xe – uAPI high level overview
	233	=============================
	234
	235	...Warning: To be done in follow up patches after/when/where the main consensus in various items are individually reached.

Documentation/gpu/todo.rst+2−5

 - Need to switch to drm_fbdev_generic_setup(), otherwise a lot of the custom fb
   setup code can't be deleted.
-- Many drivers wrap drm_gem_fb_create() only to check for valid formats. For
+- Need to switch to drm_gem_fb_create(), as now drm_gem_fb_create() checks for
-  atomic drivers we could check for valid formats by calling
+  valid formats for atomic drivers.
-  drm_plane_check_pixel_format() against all planes, and pass if any plane
-  supports the format. For non-atomic that's not possible since like the format
-  list for the primary plane is fake and we'd therefor reject valid formats.
 - Many drivers subclass drm_framebuffer, we'd need a embedding compatible
   version of the varios drm_gem_fb_create functions. Maybe called

Documentation/gpu/vkms.rst+1−6

@@ -118,14 +118,9 @@ Add Plane Features · 117 unmodified lines
118		118
119	There's lots of plane features we could add support for:	119	There's lots of plane features we could add support for:
120		120
121	- ARGB format on primary plane: blend the primary plane into background with
122	translucent alpha.
123
124	- Add background color KMS property[Good to get started].	121	- Add background color KMS property[Good to get started].
125		122
126	- Full alpha blending on all planes.	123	- Scaling.
127
128	- Rotation, scaling.
129		124
130	- Additional buffer formats, especially YUV formats for video like NV12.	125	- Additional buffer formats, especially YUV formats for video like NV12.
131	Low/high bpp RGB formats would also be interesting.	126	Low/high bpp RGB formats would also be interesting.

Documentation/networking/bonding.rst+5−4

@@ -776,10 +776,11 @@ peer_notif_delay · 775 unmodified lines
776	Specify the delay, in milliseconds, between each peer	776	Specify the delay, in milliseconds, between each peer
777	notification (gratuitous ARP and unsolicited IPv6 Neighbor	777	notification (gratuitous ARP and unsolicited IPv6 Neighbor
778	Advertisement) when they are issued after a failover event.	778	Advertisement) when they are issued after a failover event.
779	This delay should be a multiple of the link monitor interval	779	This delay should be a multiple of the MII link monitor interval
780	(arp_interval or miimon, whichever is active). The default	780	(miimon).
781	value is 0 which means to match the value of the link monitor	781
782	interval.	782	The valid range is 0 - 300000. The default value is 0, which means
		783	to match the value of the MII link monitor interval.
783		784
784	prio	785	prio
785	Slave priority. A higher number means higher priority.	786	Slave priority. A higher number means higher priority.

Documentation/networking/index.rst+1−1

    udplite
    vrf
    vxlan
-   x25-iface
    x25
+   x25-iface
    xfrm_device
    xfrm_proc
    xfrm_sync

Documentation/networking/x25-iface.rst+1−2

@@ -1,8 +1,7 @@
1	.. SPDX-License-Identifier: GPL-2.0	1	.. SPDX-License-Identifier: GPL-2.0
2		2
3	============================-
4	X.25 Device Driver Interface	3	X.25 Device Driver Interface
5	============================-	4	============================
6		5
7	Version 1.1	6	Version 1.1
8		7

MAINTAINERS+1156−1148

@@ -273,8 +273,8 @@ ABI/API · 272 unmodified lines
273	L: linux-api@vger.kernel.org	273	L: linux-api@vger.kernel.org
274	F: include/linux/syscalls.h	274	F: include/linux/syscalls.h
275	F: kernel/sys_ni.c	275	F: kernel/sys_ni.c
276	X: include/uapi/
277	X: arch/*/include/uapi/	276	X: arch/*/include/uapi/
		277	X: include/uapi/
278		278
279	ABIT UGURU 1,2 HARDWARE MONITOR DRIVER	279	ABIT UGURU 1,2 HARDWARE MONITOR DRIVER
280	M: Hans de Goede <hdegoede@redhat.com>	280	M: Hans de Goede <hdegoede@redhat.com>
@@ -406,12 +406,6 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) · 125 unmodified lines
406	S: Maintained	406	S: Maintained
407	F: drivers/acpi/arm64	407	F: drivers/acpi/arm64
408		408
409	ACPI SERIAL MULTI INSTANTIATE DRIVER
410	M: Hans de Goede <hdegoede@redhat.com>
411	L: platform-driver-x86@vger.kernel.org
412	S: Maintained
413	F: drivers/platform/x86/serial-multi-instantiate.c
414
415	ACPI PCC(Platform Communication Channel) MAILBOX DRIVER	409	ACPI PCC(Platform Communication Channel) MAILBOX DRIVER
416	M: Sudeep Holla <sudeep.holla@arm.com>	410	M: Sudeep Holla <sudeep.holla@arm.com>
417	L: linux-acpi@vger.kernel.org	411	L: linux-acpi@vger.kernel.org
@@ -430,6 +424,12 @@ B: https://bugzilla.kernel.org · 12 unmodified lines
430	T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm	424	T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
431	F: drivers/acpi/pmic/	425	F: drivers/acpi/pmic/
432		426
		427	ACPI SERIAL MULTI INSTANTIATE DRIVER
		428	M: Hans de Goede <hdegoede@redhat.com>
		429	L: platform-driver-x86@vger.kernel.org
		430	S: Maintained
		431	F: drivers/platform/x86/serial-multi-instantiate.c
		432
433	ACPI THERMAL DRIVER	433	ACPI THERMAL DRIVER
434	M: Rafael J. Wysocki <rafael@kernel.org>	434	M: Rafael J. Wysocki <rafael@kernel.org>
435	R: Zhang Rui <rui.zhang@intel.com>	435	R: Zhang Rui <rui.zhang@intel.com>
@@ -823,6 +823,13 @@ L: linux-crypto@vger.kernel.org · 387 unmodified lines
823	S: Maintained	823	S: Maintained
824	F: drivers/crypto/allwinner/	824	F: drivers/crypto/allwinner/
825		825
		826	ALLWINNER DMIC DRIVERS
		827	M: Ban Tao <fengzheng923@gmail.com>
		828	L: alsa-devel@alsa-project.org (moderated for non-subscribers)
		829	S: Maintained
		830	F: Documentation/devicetree/bindings/sound/allwinner,sun50i-h6-dmic.yaml
		831	F: sound/soc/sunxi/sun50i-dmic.c
		832
826	ALLWINNER HARDWARE SPINLOCK SUPPORT	833	ALLWINNER HARDWARE SPINLOCK SUPPORT
827	M: Wilken Gottwalt <wilken.gottwalt@posteo.net>	834	M: Wilken Gottwalt <wilken.gottwalt@posteo.net>
828	S: Maintained	835	S: Maintained
@@ -844,13 +851,6 @@ L: linux-media@vger.kernel.org · 15 unmodified lines
844	S: Maintained	851	S: Maintained
845	F: drivers/staging/media/sunxi/cedrus/	852	F: drivers/staging/media/sunxi/cedrus/
846		853
847	ALLWINNER DMIC DRIVERS
848	M: Ban Tao <fengzheng923@gmail.com>
849	L: alsa-devel@alsa-project.org (moderated for non-subscribers)
850	S: Maintained
851	F: Documentation/devicetree/bindings/sound/allwinner,sun50i-h6-dmic.yaml
852	F: sound/soc/sunxi/sun50i-dmic.c
853
854	ALPHA PORT	854	ALPHA PORT
855	M: Richard Henderson <richard.henderson@linaro.org>	855	M: Richard Henderson <richard.henderson@linaro.org>
856	M: Ivan Kokshaysky <ink@jurassic.park.msu.ru>	856	M: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
@@ -1026,6 +1026,16 @@ F: drivers/char/hw_random/geode-rng.c · 169 unmodified lines
1026	F: drivers/crypto/geode*	1026	F: drivers/crypto/geode*
1027	F: drivers/video/fbdev/geode/	1027	F: drivers/video/fbdev/geode/
1028		1028
		1029	AMD HSMP DRIVER
		1030	M: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
		1031	R: Carlos Bilbao <carlos.bilbao@amd.com>
		1032	L: platform-driver-x86@vger.kernel.org
		1033	S: Maintained
		1034	F: Documentation/arch/x86/amd_hsmp.rst
		1035	F: arch/x86/include/asm/amd_hsmp.h
		1036	F: arch/x86/include/uapi/asm/amd_hsmp.h
		1037	F: drivers/platform/x86/amd/hsmp.c
		1038
1029	AMD IOMMU (AMD-VI)	1039	AMD IOMMU (AMD-VI)
1030	M: Joerg Roedel <joro@8bytes.org>	1040	M: Joerg Roedel <joro@8bytes.org>
1031	R: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>	1041	R: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
@@ -1049,6 +1059,13 @@ F: drivers/gpu/drm/amd/include/vi_structs.h · 17 unmodified lines
1049	F: include/uapi/linux/kfd_ioctl.h	1059	F: include/uapi/linux/kfd_ioctl.h
1050	F: include/uapi/linux/kfd_sysfs.h	1060	F: include/uapi/linux/kfd_sysfs.h
1051		1061
		1062	AMD MP2 I2C DRIVER
		1063	M: Elie Morisse <syniurge@gmail.com>
		1064	M: Shyam Sundar S K <shyam-sundar.s-k@amd.com>
		1065	L: linux-i2c@vger.kernel.org
		1066	S: Maintained
		1067	F: drivers/i2c/busses/i2c-amd-mp2*
		1068
1052	AMD PDS CORE DRIVER	1069	AMD PDS CORE DRIVER
1053	M: Shannon Nelson <shannon.nelson@amd.com>	1070	M: Shannon Nelson <shannon.nelson@amd.com>
1054	M: Brett Creeley <brett.creeley@amd.com>	1071	M: Brett Creeley <brett.creeley@amd.com>
@@ -1058,18 +1075,6 @@ F: Documentation/networking/device_drivers/ethernet/amd/pds_core.rst · 3 unmodified lines
1058	F: drivers/net/ethernet/amd/pds_core/	1075	F: drivers/net/ethernet/amd/pds_core/
1059	F: include/linux/pds/	1076	F: include/linux/pds/
1060		1077
1061	AMD SPI DRIVER
1062	M: Sanjay R Mehta <sanju.mehta@amd.com>
1063	S: Maintained
1064	F: drivers/spi/spi-amd.c
1065
1066	AMD MP2 I2C DRIVER
1067	M: Elie Morisse <syniurge@gmail.com>
1068	M: Shyam Sundar S K <shyam-sundar.s-k@amd.com>
1069	L: linux-i2c@vger.kernel.org
1070	S: Maintained
1071	F: drivers/i2c/busses/i2c-amd-mp2*
1072
1073	AMD PMC DRIVER	1078	AMD PMC DRIVER
1074	M: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>	1079	M: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
1075	L: platform-driver-x86@vger.kernel.org	1080	L: platform-driver-x86@vger.kernel.org
@@ -1083,16 +1088,6 @@ S: Maintained · 7 unmodified lines
1083	F: Documentation/ABI/testing/sysfs-amd-pmf	1088	F: Documentation/ABI/testing/sysfs-amd-pmf
1084	F: drivers/platform/x86/amd/pmf/	1089	F: drivers/platform/x86/amd/pmf/
1085		1090
1086	AMD HSMP DRIVER
1087	M: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
1088	R: Carlos Bilbao <carlos.bilbao@amd.com>
1089	L: platform-driver-x86@vger.kernel.org
1090	S: Maintained
1091	F: Documentation/arch/x86/amd_hsmp.rst
1092	F: arch/x86/include/asm/amd_hsmp.h
1093	F: arch/x86/include/uapi/asm/amd_hsmp.h
1094	F: drivers/platform/x86/amd/hsmp.c
1095
1096	AMD POWERPLAY AND SWSMU	1091	AMD POWERPLAY AND SWSMU
1097	M: Evan Quan <evan.quan@amd.com>	1092	M: Evan Quan <evan.quan@amd.com>
1098	L: amd-gfx@lists.freedesktop.org	1093	L: amd-gfx@lists.freedesktop.org
@@ -1121,13 +1116,6 @@ M: Tom Lendacky <thomas.lendacky@amd.com> · 22 unmodified lines
1121	S: Supported	1116	S: Supported
1122	F: arch/arm64/boot/dts/amd/	1117	F: arch/arm64/boot/dts/amd/
1123		1118
1124	AMD XGBE DRIVER
1125	M: "Shyam Sundar S K" <Shyam-sundar.S-k@amd.com>
1126	L: netdev@vger.kernel.org
1127	S: Supported
1128	F: arch/arm64/boot/dts/amd/amd-seattle-xgbe*.dtsi
1129	F: drivers/net/ethernet/amd/xgbe/
1130
1131	AMD SENSOR FUSION HUB DRIVER	1119	AMD SENSOR FUSION HUB DRIVER
1132	M: Basavaraj Natikar <basavaraj.natikar@amd.com>	1120	M: Basavaraj Natikar <basavaraj.natikar@amd.com>
1133	L: linux-input@vger.kernel.org	1121	L: linux-input@vger.kernel.org
@@ -1135,6 +1123,18 @@ S: Maintained · 1 unmodified line
1135	F: Documentation/hid/amd-sfh*	1123	F: Documentation/hid/amd-sfh*
1136	F: drivers/hid/amd-sfh-hid/	1124	F: drivers/hid/amd-sfh-hid/
1137		1125
		1126	AMD SPI DRIVER
		1127	M: Sanjay R Mehta <sanju.mehta@amd.com>
		1128	S: Maintained
		1129	F: drivers/spi/spi-amd.c
		1130
		1131	AMD XGBE DRIVER
		1132	M: "Shyam Sundar S K" <Shyam-sundar.S-k@amd.com>
		1133	L: netdev@vger.kernel.org
		1134	S: Supported
		1135	F: arch/arm64/boot/dts/amd/amd-seattle-xgbe*.dtsi
		1136	F: drivers/net/ethernet/amd/xgbe/
		1137
1138	AMLOGIC DDR PMU DRIVER	1138	AMLOGIC DDR PMU DRIVER
1139	M: Jiucheng Xu <jiucheng.xu@amlogic.com>	1139	M: Jiucheng Xu <jiucheng.xu@amlogic.com>
1140	L: linux-amlogic@lists.infradead.org	1140	L: linux-amlogic@lists.infradead.org
@@ -1169,6 +1169,14 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git · 28 unmodified lines
1169	T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git	1169	T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git
1170	F: drivers/net/amt.c	1170	F: drivers/net/amt.c
1171		1171
		1172	ANALOG DEVICES INC AD3552R DRIVER
		1173	M: Nuno Sá <nuno.sa@analog.com>
		1174	L: linux-iio@vger.kernel.org
		1175	S: Supported
		1176	W: https://ez.analog.com/linux-software-drivers
		1177	F: Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
		1178	F: drivers/iio/dac/ad3552r.c
		1179
1172	ANALOG DEVICES INC AD4130 DRIVER	1180	ANALOG DEVICES INC AD4130 DRIVER
1173	M: Cosmin Tanislav <cosmin.tanislav@analog.com>	1181	M: Cosmin Tanislav <cosmin.tanislav@analog.com>
1174	L: linux-iio@vger.kernel.org	1182	L: linux-iio@vger.kernel.org
@@ -1194,14 +1202,6 @@ W: https://ez.analog.com/linux-software-drivers · 19 unmodified lines
1194	F: Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml	1202	F: Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml
1195	F: drivers/iio/adc/ad7292.c	1203	F: drivers/iio/adc/ad7292.c
1196		1204
1197	ANALOG DEVICES INC AD3552R DRIVER
1198	M: Nuno Sá <nuno.sa@analog.com>
1199	L: linux-iio@vger.kernel.org
1200	S: Supported
1201	W: https://ez.analog.com/linux-software-drivers
1202	F: Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
1203	F: drivers/iio/dac/ad3552r.c
1204
1205	ANALOG DEVICES INC AD7293 DRIVER	1205	ANALOG DEVICES INC AD7293 DRIVER
1206	M: Antoniu Miclaus <antoniu.miclaus@analog.com>	1206	M: Antoniu Miclaus <antoniu.miclaus@analog.com>
1207	L: linux-iio@vger.kernel.org	1207	L: linux-iio@vger.kernel.org
@@ -1210,23 +1210,6 @@ W: https://ez.analog.com/linux-software-drivers · 2 unmodified lines
1210	F: Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml	1210	F: Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml
1211	F: drivers/iio/dac/ad7293.c	1211	F: drivers/iio/dac/ad7293.c
1212		1212
1213	ANALOG DEVICES INC AD7768-1 DRIVER
1214	M: Michael Hennerich <Michael.Hennerich@analog.com>
1215	L: linux-iio@vger.kernel.org
1216	S: Supported
1217	W: https://ez.analog.com/linux-software-drivers
1218	F: Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml
1219	F: drivers/iio/adc/ad7768-1.c
1220
1221	ANALOG DEVICES INC AD7780 DRIVER
1222	M: Michael Hennerich <Michael.Hennerich@analog.com>
1223	M: Renato Lui Geh <renatogeh@gmail.com>
1224	L: linux-iio@vger.kernel.org
1225	S: Supported
1226	W: https://ez.analog.com/linux-software-drivers
1227	F: Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml
1228	F: drivers/iio/adc/ad7780.c
1229
1230	ANALOG DEVICES INC AD74115 DRIVER	1213	ANALOG DEVICES INC AD74115 DRIVER
1231	M: Cosmin Tanislav <cosmin.tanislav@analog.com>	1214	M: Cosmin Tanislav <cosmin.tanislav@analog.com>
1232	L: linux-iio@vger.kernel.org	1215	L: linux-iio@vger.kernel.org
@@ -1244,6 +1227,23 @@ F: Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml · 11 unmodified lines
1244	F: drivers/iio/addac/ad74413r.c	1227	F: drivers/iio/addac/ad74413r.c
1245	F: include/dt-bindings/iio/addac/adi,ad74413r.h	1228	F: include/dt-bindings/iio/addac/adi,ad74413r.h
1246		1229
		1230	ANALOG DEVICES INC AD7768-1 DRIVER
		1231	M: Michael Hennerich <Michael.Hennerich@analog.com>
		1232	L: linux-iio@vger.kernel.org
		1233	S: Supported
		1234	W: https://ez.analog.com/linux-software-drivers
		1235	F: Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml
		1236	F: drivers/iio/adc/ad7768-1.c
		1237
		1238	ANALOG DEVICES INC AD7780 DRIVER
		1239	M: Michael Hennerich <Michael.Hennerich@analog.com>
		1240	M: Renato Lui Geh <renatogeh@gmail.com>
		1241	L: linux-iio@vger.kernel.org
		1242	S: Supported
		1243	W: https://ez.analog.com/linux-software-drivers
		1244	F: Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml
		1245	F: drivers/iio/adc/ad7780.c
		1246
1247	ANALOG DEVICES INC ADA4250 DRIVER	1247	ANALOG DEVICES INC ADA4250 DRIVER
1248	M: Antoniu Miclaus <antoniu.miclaus@analog.com>	1248	M: Antoniu Miclaus <antoniu.miclaus@analog.com>
1249	L: linux-iio@vger.kernel.org	1249	L: linux-iio@vger.kernel.org
@@ -1294,10 +1294,10 @@ F: drivers/iio/imu/adis16460.c · 44 unmodified lines
1294	ANALOG DEVICES INC ADIS16475 DRIVER	1294	ANALOG DEVICES INC ADIS16475 DRIVER
1295	M: Nuno Sa <nuno.sa@analog.com>	1295	M: Nuno Sa <nuno.sa@analog.com>
1296	L: linux-iio@vger.kernel.org	1296	L: linux-iio@vger.kernel.org
1297	W: https://ez.analog.com/linux-software-drivers
1298	S: Supported	1297	S: Supported
1299	F: drivers/iio/imu/adis16475.c	1298	W: https://ez.analog.com/linux-software-drivers
1300	F: Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml	1299	F: Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml
		1300	F: drivers/iio/imu/adis16475.c
1301		1301
1302	ANALOG DEVICES INC ADM1177 DRIVER	1302	ANALOG DEVICES INC ADM1177 DRIVER
1303	M: Michael Hennerich <Michael.Hennerich@analog.com>	1303	M: Michael Hennerich <Michael.Hennerich@analog.com>
@@ -1315,21 +1315,21 @@ W: https://ez.analog.com/linux-software-drivers · 11 unmodified lines
1315	F: Documentation/devicetree/bindings/iio/frequency/adi,admv1013.yaml	1315	F: Documentation/devicetree/bindings/iio/frequency/adi,admv1013.yaml
1316	F: drivers/iio/frequency/admv1013.c	1316	F: drivers/iio/frequency/admv1013.c
1317		1317
1318	ANALOG DEVICES INC ADMV8818 DRIVER	1318	ANALOG DEVICES INC ADMV1014 DRIVER
1319	M: Antoniu Miclaus <antoniu.miclaus@analog.com>	1319	M: Antoniu Miclaus <antoniu.miclaus@analog.com>
1320	L: linux-iio@vger.kernel.org	1320	L: linux-iio@vger.kernel.org
1321	S: Supported	1321	S: Supported
1322	W: https://ez.analog.com/linux-software-drivers	1322	W: https://ez.analog.com/linux-software-drivers
1323	F: Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml	1323	F: Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml
1324	F: drivers/iio/filter/admv8818.c	1324	F: drivers/iio/frequency/admv1014.c
1325		1325
1326	ANALOG DEVICES INC ADMV1014 DRIVER	1326	ANALOG DEVICES INC ADMV8818 DRIVER
1327	M: Antoniu Miclaus <antoniu.miclaus@analog.com>	1327	M: Antoniu Miclaus <antoniu.miclaus@analog.com>
1328	L: linux-iio@vger.kernel.org	1328	L: linux-iio@vger.kernel.org
1329	S: Supported	1329	S: Supported
1330	W: https://ez.analog.com/linux-software-drivers	1330	W: https://ez.analog.com/linux-software-drivers
1331	F: Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml	1331	F: Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml
1332	F: drivers/iio/frequency/admv1014.c	1332	F: drivers/iio/filter/admv8818.c
1333		1333
1334	ANALOG DEVICES INC ADP5061 DRIVER	1334	ANALOG DEVICES INC ADP5061 DRIVER
1335	M: Michael Hennerich <Michael.Hennerich@analog.com>	1335	M: Michael Hennerich <Michael.Hennerich@analog.com>
@@ -1351,8 +1351,8 @@ M: Lars-Peter Clausen <lars@metafoo.de> · 15 unmodified lines
1351	L: linux-media@vger.kernel.org	1351	L: linux-media@vger.kernel.org
1352	S: Supported	1352	S: Supported
1353	W: https://ez.analog.com/linux-software-drivers	1353	W: https://ez.analog.com/linux-software-drivers
1354	F: drivers/media/i2c/adv7180.c
1355	F: Documentation/devicetree/bindings/media/i2c/adv7180.yaml	1354	F: Documentation/devicetree/bindings/media/i2c/adv7180.yaml
		1355	F: drivers/media/i2c/adv7180.c
1356		1356
1357	ANALOG DEVICES INC ADV748X DRIVER	1357	ANALOG DEVICES INC ADV748X DRIVER
1358	M: Kieran Bingham <kieran.bingham@ideasonboard.com>	1358	M: Kieran Bingham <kieran.bingham@ideasonboard.com>
@@ -1371,8 +1371,8 @@ ANALOG DEVICES INC ADV7604 DRIVER · 12 unmodified lines
1371	M: Hans Verkuil <hverkuil-cisco@xs4all.nl>	1371	M: Hans Verkuil <hverkuil-cisco@xs4all.nl>
1372	L: linux-media@vger.kernel.org	1372	L: linux-media@vger.kernel.org
1373	S: Maintained	1373	S: Maintained
1374	F: drivers/media/i2c/adv7604*
1375	F: Documentation/devicetree/bindings/media/i2c/adv7604.yaml	1374	F: Documentation/devicetree/bindings/media/i2c/adv7604.yaml
		1375	F: drivers/media/i2c/adv7604*
1376		1376
1377	ANALOG DEVICES INC ADV7842 DRIVER	1377	ANALOG DEVICES INC ADV7842 DRIVER
1378	M: Hans Verkuil <hverkuil-cisco@xs4all.nl>	1378	M: Hans Verkuil <hverkuil-cisco@xs4all.nl>
@@ -1384,8 +1384,8 @@ ANALOG DEVICES INC ADXRS290 DRIVER · 5 unmodified lines
1384	M: Nishant Malpani <nish.malpani25@gmail.com>	1384	M: Nishant Malpani <nish.malpani25@gmail.com>
1385	L: linux-iio@vger.kernel.org	1385	L: linux-iio@vger.kernel.org
1386	S: Supported	1386	S: Supported
1387	F: drivers/iio/gyro/adxrs290.c
1388	F: Documentation/devicetree/bindings/iio/gyroscope/adi,adxrs290.yaml	1387	F: Documentation/devicetree/bindings/iio/gyroscope/adi,adxrs290.yaml
		1388	F: drivers/iio/gyro/adxrs290.c
1389		1389
1390	ANALOG DEVICES INC ASOC CODEC DRIVERS	1390	ANALOG DEVICES INC ASOC CODEC DRIVERS
1391	M: Lars-Peter Clausen <lars@metafoo.de>	1391	M: Lars-Peter Clausen <lars@metafoo.de>
@@ -1625,6 +1625,17 @@ S: Maintained · 233 unmodified lines
1625	F: drivers/net/arcnet/	1625	F: drivers/net/arcnet/
1626	F: include/uapi/linux/if_arcnet.h	1626	F: include/uapi/linux/if_arcnet.h
1627		1627
		1628	ARM AND ARM64 SoC SUB-ARCHITECTURES (COMMON PARTS)
		1629	M: Arnd Bergmann <arnd@arndb.de>
		1630	M: Olof Johansson <olof@lixom.net>
		1631	M: soc@kernel.org
		1632	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
		1633	S: Maintained
		1634	C: irc://irc.libera.chat/armlinux
		1635	T: git git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
		1636	F: arch/arm/boot/dts/Makefile
		1637	F: arch/arm64/boot/dts/Makefile
		1638
1628	ARM ARCHITECTED TIMER DRIVER	1639	ARM ARCHITECTED TIMER DRIVER
1629	M: Mark Rutland <mark.rutland@arm.com>	1640	M: Mark Rutland <mark.rutland@arm.com>
1630	M: Marc Zyngier <maz@kernel.org>	1641	M: Marc Zyngier <maz@kernel.org>
@@ -1738,22 +1749,6 @@ S: Odd Fixes · 107 unmodified lines
1738	F: drivers/amba/	1749	F: drivers/amba/
1739	F: include/linux/amba/bus.h	1750	F: include/linux/amba/bus.h
1740		1751
1741	ARM PRIMECELL PL35X NAND CONTROLLER DRIVER
1742	M: Miquel Raynal <miquel.raynal@bootlin.com>
1743	M: Naga Sureshkumar Relli <nagasure@xilinx.com>
1744	L: linux-mtd@lists.infradead.org
1745	S: Maintained
1746	F: Documentation/devicetree/bindings/mtd/arm,pl353-nand-r2p1.yaml
1747	F: drivers/mtd/nand/raw/pl35x-nand-controller.c
1748
1749	ARM PRIMECELL PL35X SMC DRIVER
1750	M: Miquel Raynal <miquel.raynal@bootlin.com>
1751	M: Naga Sureshkumar Relli <nagasure@xilinx.com>
1752	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1753	S: Maintained
1754	F: Documentation/devicetree/bindings/memory-controllers/arm,pl35x-smc.yaml
1755	F: drivers/memory/pl353-smc.c
1756
1757	ARM PRIMECELL CLCD PL110 DRIVER	1752	ARM PRIMECELL CLCD PL110 DRIVER
1758	M: Russell King <linux@armlinux.org.uk>	1753	M: Russell King <linux@armlinux.org.uk>
1759	S: Odd Fixes	1754	S: Odd Fixes
@@ -1771,6 +1766,22 @@ S: Odd Fixes · 11 unmodified lines
1771	F: drivers/mmc/host/mmci.*	1766	F: drivers/mmc/host/mmci.*
1772	F: include/linux/amba/mmci.h	1767	F: include/linux/amba/mmci.h
1773		1768
		1769	ARM PRIMECELL PL35X NAND CONTROLLER DRIVER
		1770	M: Miquel Raynal <miquel.raynal@bootlin.com>
		1771	M: Naga Sureshkumar Relli <nagasure@xilinx.com>
		1772	L: linux-mtd@lists.infradead.org
		1773	S: Maintained
		1774	F: Documentation/devicetree/bindings/mtd/arm,pl353-nand-r2p1.yaml
		1775	F: drivers/mtd/nand/raw/pl35x-nand-controller.c
		1776
		1777	ARM PRIMECELL PL35X SMC DRIVER
		1778	M: Miquel Raynal <miquel.raynal@bootlin.com>
		1779	M: Naga Sureshkumar Relli <nagasure@xilinx.com>
		1780	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
		1781	S: Maintained
		1782	F: Documentation/devicetree/bindings/memory-controllers/arm,pl35x-smc.yaml
		1783	F: drivers/memory/pl353-smc.c
		1784
1774	ARM PRIMECELL SSP PL022 SPI DRIVER	1785	ARM PRIMECELL SSP PL022 SPI DRIVER
1775	M: Linus Walleij <linus.walleij@linaro.org>	1786	M: Linus Walleij <linus.walleij@linaro.org>
1776	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)	1787	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -1807,17 +1818,6 @@ F: Documentation/devicetree/bindings/iommu/arm,smmu* · 30 unmodified lines
1807	F: drivers/iommu/arm/	1818	F: drivers/iommu/arm/
1808	F: drivers/iommu/io-pgtable-arm*	1819	F: drivers/iommu/io-pgtable-arm*
1809		1820
1810	ARM AND ARM64 SoC SUB-ARCHITECTURES (COMMON PARTS)
1811	M: Arnd Bergmann <arnd@arndb.de>
1812	M: Olof Johansson <olof@lixom.net>
1813	M: soc@kernel.org
1814	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1815	S: Maintained
1816	C: irc://irc.libera.chat/armlinux
1817	T: git git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
1818	F: arch/arm/boot/dts/Makefile
1819	F: arch/arm64/boot/dts/Makefile
1820
1821	ARM SUB-ARCHITECTURES	1821	ARM SUB-ARCHITECTURES
1822	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)	1822	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1823	S: Maintained	1823	S: Maintained
@@ -1869,9 +1869,9 @@ M: Chen-Yu Tsai <wens@csie.org> · 45 unmodified lines
1869	M: Jernej Skrabec <jernej.skrabec@gmail.com>	1869	M: Jernej Skrabec <jernej.skrabec@gmail.com>
1870	M: Samuel Holland <samuel@sholland.org>	1870	M: Samuel Holland <samuel@sholland.org>
1871	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)	1871	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
		1872	L: linux-sunxi@lists.linux.dev
1872	S: Maintained	1873	S: Maintained
1873	T: git git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git	1874	T: git git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git
1874	L: linux-sunxi@lists.linux.dev
1875	F: arch/arm/mach-sunxi/	1875	F: arch/arm/mach-sunxi/
1876	F: arch/arm64/boot/dts/allwinner/	1876	F: arch/arm64/boot/dts/allwinner/
1877	F: drivers/clk/sunxi-ng/	1877	F: drivers/clk/sunxi-ng/
@@ -1934,6 +1934,15 @@ F: arch/arm/mach-alpine/ · 56 unmodified lines
1934	F: arch/arm64/boot/dts/amazon/	1934	F: arch/arm64/boot/dts/amazon/
1935	F: drivers//alpine*	1935	F: drivers//alpine*
1936		1936
		1937	ARM/APPLE MACHINE SOUND DRIVERS
		1938	M: Martin Povišer <povik+lin@cutebit.org>
		1939	L: asahi@lists.linux.dev
		1940	L: alsa-devel@alsa-project.org (moderated for non-subscribers)
		1941	S: Maintained
		1942	F: Documentation/devicetree/bindings/sound/apple,*
		1943	F: sound/soc/apple/*
		1944	F: sound/soc/codecs/cs42l83-i2c.c
		1945
1937	ARM/APPLE MACHINE SUPPORT	1946	ARM/APPLE MACHINE SUPPORT
1938	M: Hector Martin <marcan@marcan.st>	1947	M: Hector Martin <marcan@marcan.st>
1939	M: Sven Peter <sven@svenpeter.dev>	1948	M: Sven Peter <sven@svenpeter.dev>
@@ -1961,7 +1970,7 @@ F: Documentation/devicetree/bindings/nvmem/apple,efuses.yaml · 21 unmodified lines
1961	F: Documentation/devicetree/bindings/pci/apple,pcie.yaml	1970	F: Documentation/devicetree/bindings/pci/apple,pcie.yaml
1962	F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml	1971	F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
1963	F: Documentation/devicetree/bindings/power/apple*	1972	F: Documentation/devicetree/bindings/power/apple*
1964	F: Documentation/devicetree/bindings/pwm/pwm-apple.yaml	1973	F: Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml
1965	F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml	1974	F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml
1966	F: arch/arm64/boot/dts/apple/	1975	F: arch/arm64/boot/dts/apple/
1967	F: drivers/bluetooth/hci_bcm4377.c	1976	F: drivers/bluetooth/hci_bcm4377.c
@@ -1985,15 +1994,6 @@ F: include/dt-bindings/pinctrl/apple.h · 17 unmodified lines
1985	F: include/linux/apple-mailbox.h	1994	F: include/linux/apple-mailbox.h
1986	F: include/linux/soc/apple/*	1995	F: include/linux/soc/apple/*
1987		1996
1988	ARM/APPLE MACHINE SOUND DRIVERS
1989	M: Martin Povišer <povik+lin@cutebit.org>
1990	L: asahi@lists.linux.dev
1991	L: alsa-devel@alsa-project.org (moderated for non-subscribers)
1992	S: Maintained
1993	F: Documentation/devicetree/bindings/sound/apple,*
1994	F: sound/soc/apple/*
1995	F: sound/soc/codecs/cs42l83-i2c.c
1996
1997	ARM/ARTPEC MACHINE SUPPORT	1997	ARM/ARTPEC MACHINE SUPPORT
1998	M: Jesper Nilsson <jesper.nilsson@axis.com>	1998	M: Jesper Nilsson <jesper.nilsson@axis.com>
1999	M: Lars Persson <lars.persson@axis.com>	1999	M: Lars Persson <lars.persson@axis.com>
@@ -2109,19 +2109,19 @@ S: Maintained · 109 unmodified lines
2109	T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git	2109	T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
2110	F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*	2110	F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
2111	F: Documentation/devicetree/bindings/arm/arm,coresight-*.yaml	2111	F: Documentation/devicetree/bindings/arm/arm,coresight-*.yaml
2112	F: Documentation/devicetree/bindings/arm/qcom,coresight-*.yaml
2113	F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml	2112	F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml
2114	F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml	2113	F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
		2114	F: Documentation/devicetree/bindings/arm/qcom,coresight-*.yaml
2115	F: Documentation/trace/coresight/*	2115	F: Documentation/trace/coresight/*
2116	F: drivers/hwtracing/coresight/*	2116	F: drivers/hwtracing/coresight/*
2117	F: include/dt-bindings/arm/coresight-cti-dt.h	2117	F: include/dt-bindings/arm/coresight-cti-dt.h
2118	F: include/linux/coresight*	2118	F: include/linux/coresight*
2119	F: samples/coresight/*	2119	F: samples/coresight/*
2120	F: tools/perf/tests/shell/coresight/*
2121	F: tools/perf/arch/arm/util/auxtrace.c	2120	F: tools/perf/arch/arm/util/auxtrace.c
2122	F: tools/perf/arch/arm/util/cs-etm.c	2121	F: tools/perf/arch/arm/util/cs-etm.c
2123	F: tools/perf/arch/arm/util/cs-etm.h	2122	F: tools/perf/arch/arm/util/cs-etm.h
2124	F: tools/perf/arch/arm/util/pmu.c	2123	F: tools/perf/arch/arm/util/pmu.c
		2124	F: tools/perf/tests/shell/coresight/*
2125	F: tools/perf/util/cs-etm-decoder/*	2125	F: tools/perf/util/cs-etm-decoder/*
2126	F: tools/perf/util/cs-etm.*	2126	F: tools/perf/util/cs-etm.*
2127		2127
@@ -2156,9 +2156,9 @@ F: Documentation/devicetree/bindings/leds/cznic,turris-omnia-leds.yaml · 28 unmodified lines
2156	F: Documentation/devicetree/bindings/watchdog/armada-37xx-wdt.txt	2156	F: Documentation/devicetree/bindings/watchdog/armada-37xx-wdt.txt
2157	F: drivers/bus/moxtet.c	2157	F: drivers/bus/moxtet.c
2158	F: drivers/firmware/turris-mox-rwtm.c	2158	F: drivers/firmware/turris-mox-rwtm.c
		2159	F: drivers/gpio/gpio-moxtet.c
2159	F: drivers/leds/leds-turris-omnia.c	2160	F: drivers/leds/leds-turris-omnia.c
2160	F: drivers/mailbox/armada-37xx-rwtm-mailbox.c	2161	F: drivers/mailbox/armada-37xx-rwtm-mailbox.c
2161	F: drivers/gpio/gpio-moxtet.c
2162	F: drivers/watchdog/armada_37xx_wdt.c	2162	F: drivers/watchdog/armada_37xx_wdt.c
2163	F: include/dt-bindings/bus/moxtet.h	2163	F: include/dt-bindings/bus/moxtet.h
2164	F: include/linux/armada-37xx-rwtm-mailbox.h	2164	F: include/linux/armada-37xx-rwtm-mailbox.h
@@ -2188,10 +2188,10 @@ R: NXP Linux Team <linux-imx@nxp.com> · 23 unmodified lines
2188	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)	2188	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2189	S: Maintained	2189	S: Maintained
2190	T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git	2190	T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
2191	X: drivers/media/i2c/
2192	F: arch/arm64/boot/dts/freescale/	2191	F: arch/arm64/boot/dts/freescale/
2193	X: arch/arm64/boot/dts/freescale/fsl-*	2192	X: arch/arm64/boot/dts/freescale/fsl-*
2194	X: arch/arm64/boot/dts/freescale/qoriq-*	2193	X: arch/arm64/boot/dts/freescale/qoriq-*
		2194	X: drivers/media/i2c/
2195	N: imx	2195	N: imx
2196	N: mxs	2196	N: mxs
2197		2197
@@ -2245,12 +2245,12 @@ ARM/HPE GXP ARCHITECTURE · 47 unmodified lines
2245	M: Jean-Marie Verdun <verdun@hpe.com>	2245	M: Jean-Marie Verdun <verdun@hpe.com>
2246	M: Nick Hawkins <nick.hawkins@hpe.com>	2246	M: Nick Hawkins <nick.hawkins@hpe.com>
2247	S: Maintained	2247	S: Maintained
2248	F: Documentation/hwmon/gxp-fan-ctrl.rst
2249	F: Documentation/devicetree/bindings/arm/hpe,gxp.yaml	2248	F: Documentation/devicetree/bindings/arm/hpe,gxp.yaml
2250	F: Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml	2249	F: Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml
2251	F: Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml	2250	F: Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml
2252	F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml	2251	F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
2253	F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml	2252	F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
		2253	F: Documentation/hwmon/gxp-fan-ctrl.rst
2254	F: arch/arm/boot/dts/hpe-bmc*	2254	F: arch/arm/boot/dts/hpe-bmc*
2255	F: arch/arm/boot/dts/hpe-gxp*	2255	F: arch/arm/boot/dts/hpe-gxp*
2256	F: arch/arm/mach-hpe/	2256	F: arch/arm/mach-hpe/
@@ -2275,9 +2275,9 @@ M: Krzysztof Halasa <khalasa@piap.pl> · 18 unmodified lines
2275	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)	2275	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2276	S: Maintained	2276	S: Maintained
2277	F: Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml	2277	F: Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml
2278	F: Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion*
2279	F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt	2278	F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt
2280	F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml	2279	F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
		2280	F: Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion*
2281	F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml	2281	F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
2282	F: arch/arm/boot/dts/intel-ixp*	2282	F: arch/arm/boot/dts/intel-ixp*
2283	F: arch/arm/mach-ixp4xx/	2283	F: arch/arm/mach-ixp4xx/
@@ -2447,13 +2447,6 @@ F: drivers/net/ethernet/microchip/vcap/ · 163 unmodified lines
2447	F: drivers/pinctrl/pinctrl-microchip-sgpio.c	2447	F: drivers/pinctrl/pinctrl-microchip-sgpio.c
2448	N: sparx5	2448	N: sparx5
2449		2449
2450	Microchip Timer Counter Block (TCB) Capture Driver
2451	M: Kamel Bouhara <kamel.bouhara@bootlin.com>
2452	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2453	L: linux-iio@vger.kernel.org
2454	S: Maintained
2455	F: drivers/counter/microchip-tcb-capture.c
2456
2457	ARM/MILBEAUT ARCHITECTURE	2450	ARM/MILBEAUT ARCHITECTURE
2458	M: Taichi Sugaya <sugaya.taichi@socionext.com>	2451	M: Taichi Sugaya <sugaya.taichi@socionext.com>
2459	M: Takao Orito <orito.takao@socionext.com>	2452	M: Takao Orito <orito.takao@socionext.com>
@@ -2525,8 +2518,8 @@ F: Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml · 65 unmodified lines
2525	F: arch/arm/boot/dts/nuvoton-npcm*	2518	F: arch/arm/boot/dts/nuvoton-npcm*
2526	F: arch/arm/mach-npcm/	2519	F: arch/arm/mach-npcm/
2527	F: arch/arm64/boot/dts/nuvoton/	2520	F: arch/arm64/boot/dts/nuvoton/
2528	F: drivers//npcm*
2529	F: drivers///npcm	2521	F: drivers///npcm
		2522	F: drivers//npcm*
2530	F: drivers/rtc/rtc-nct3018y.c	2523	F: drivers/rtc/rtc-nct3018y.c
2531	F: include/dt-bindings/clock/nuvoton,npcm7xx-clock.h	2524	F: include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
2532	F: include/dt-bindings/clock/nuvoton,npcm845-clk.h	2525	F: include/dt-bindings/clock/nuvoton,npcm845-clk.h
@@ -2569,9 +2562,15 @@ F: arch/arm/mach-oxnas/ · 36 unmodified lines
2569	F: drivers/power/reset/oxnas-restart.c	2562	F: drivers/power/reset/oxnas-restart.c
2570	N: oxnas	2563	N: oxnas
2571		2564
2572	ARM/QUALCOMM SUPPORT	2565	ARM/QUALCOMM CHROMEBOOK SUPPORT
2573	M: Andy Gross <agross@kernel.org>	2566	R: cros-qcom-dts-watchers@chromium.org
2574	M: Bjorn Andersson <andersson@kernel.org>	2567	F: arch/arm64/boot/dts/qcom/sc7180*
		2568	F: arch/arm64/boot/dts/qcom/sc7280*
		2569	F: arch/arm64/boot/dts/qcom/sdm845-cheza*
		2570
		2571	ARM/QUALCOMM SUPPORT
		2572	M: Andy Gross <agross@kernel.org>
		2573	M: Bjorn Andersson <andersson@kernel.org>
2575	R: Konrad Dybcio <konrad.dybcio@linaro.org>	2574	R: Konrad Dybcio <konrad.dybcio@linaro.org>
2576	L: linux-arm-msm@vger.kernel.org	2575	L: linux-arm-msm@vger.kernel.org
2577	S: Maintained	2576	S: Maintained
@@ -2602,22 +2601,16 @@ F: drivers/pci/controller/dwc/pcie-qcom.c · 24 unmodified lines
2602	F: drivers/phy/qualcomm/	2601	F: drivers/phy/qualcomm/
2603	F: drivers/power//msm	2602	F: drivers/power//msm
2604	F: drivers/reset/reset-qcom-*	2603	F: drivers/reset/reset-qcom-*
2605	F: drivers/ufs/host/ufs-qcom*
2606	F: drivers/spi/spi-geni-qcom.c	2604	F: drivers/spi/spi-geni-qcom.c
2607	F: drivers/spi/spi-qcom-qspi.c	2605	F: drivers/spi/spi-qcom-qspi.c
2608	F: drivers/spi/spi-qup.c	2606	F: drivers/spi/spi-qup.c
2609	F: drivers/tty/serial/msm_serial.c	2607	F: drivers/tty/serial/msm_serial.c
		2608	F: drivers/ufs/host/ufs-qcom*
2610	F: drivers/usb/dwc3/dwc3-qcom.c	2609	F: drivers/usb/dwc3/dwc3-qcom.c
2611	F: include/dt-bindings//qcom	2610	F: include/dt-bindings//qcom
2612	F: include/linux//qcom	2611	F: include/linux//qcom
2613	F: include/linux/soc/qcom/	2612	F: include/linux/soc/qcom/
2614		2613
2615	ARM/QUALCOMM CHROMEBOOK SUPPORT
2616	R: cros-qcom-dts-watchers@chromium.org
2617	F: arch/arm64/boot/dts/qcom/sc7180*
2618	F: arch/arm64/boot/dts/qcom/sc7280*
2619	F: arch/arm64/boot/dts/qcom/sdm845-cheza*
2620
2621	ARM/RDA MICRO ARCHITECTURE	2614	ARM/RDA MICRO ARCHITECTURE
2622	M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>	2615	M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2623	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)	2616	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -2709,9 +2702,9 @@ R: Alim Akhtar <alim.akhtar@samsung.com> · 85 unmodified lines
2709	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)	2702	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2710	L: linux-samsung-soc@vger.kernel.org	2703	L: linux-samsung-soc@vger.kernel.org
2711	S: Maintained	2704	S: Maintained
2712	C: irc://irc.libera.chat/linux-exynos
2713	Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/	2705	Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
2714	B: mailto:linux-samsung-soc@vger.kernel.org	2706	B: mailto:linux-samsung-soc@vger.kernel.org
		2707	C: irc://irc.libera.chat/linux-exynos
2715	T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git	2708	T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
2716	F: Documentation/arm/samsung/	2709	F: Documentation/arm/samsung/
2717	F: Documentation/devicetree/bindings/arm/samsung/	2710	F: Documentation/devicetree/bindings/arm/samsung/
@@ -2811,8 +2804,8 @@ M: Patrice Chotard <patrice.chotard@foss.st.com> · 93 unmodified lines
2811	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)	2804	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2812	S: Maintained	2805	S: Maintained
2813	W: http://www.stlinux.com	2806	W: http://www.stlinux.com
2814	F: Documentation/devicetree/bindings/spi/st,ssc-spi.yaml
2815	F: Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml	2807	F: Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml
		2808	F: Documentation/devicetree/bindings/spi/st,ssc-spi.yaml
2816	F: arch/arm/boot/dts/sti*	2809	F: arch/arm/boot/dts/sti*
2817	F: arch/arm/mach-sti/	2810	F: arch/arm/mach-sti/
2818	F: drivers/ata/ahci_st.c	2811	F: drivers/ata/ahci_st.c
@@ -2959,15 +2952,15 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti.git · 140 unmodified lines
2959	F: Documentation/devicetree/bindings/arm/toshiba.yaml	2952	F: Documentation/devicetree/bindings/arm/toshiba.yaml
2960	F: Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml	2953	F: Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml
2961	F: Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml	2954	F: Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml
2962	F: Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml
2963	F: Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml	2955	F: Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml
		2956	F: Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml
2964	F: Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.yaml	2957	F: Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.yaml
2965	F: Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml	2958	F: Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml
2966	F: Documentation/devicetree/bindings/watchdog/toshiba,visconti-wdt.yaml	2959	F: Documentation/devicetree/bindings/watchdog/toshiba,visconti-wdt.yaml
2967	F: arch/arm64/boot/dts/toshiba/	2960	F: arch/arm64/boot/dts/toshiba/
2968	F: drivers/clk/visconti/	2961	F: drivers/clk/visconti/
2969	F: drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
2970	F: drivers/gpio/gpio-visconti.c	2962	F: drivers/gpio/gpio-visconti.c
		2963	F: drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
2971	F: drivers/pci/controller/dwc/pcie-visconti.c	2964	F: drivers/pci/controller/dwc/pcie-visconti.c
2972	F: drivers/pinctrl/visconti/	2965	F: drivers/pinctrl/visconti/
2973	F: drivers/watchdog/visconti_wdt.c	2966	F: drivers/watchdog/visconti_wdt.c
@@ -3112,6 +3105,13 @@ S: Maintained · 138 unmodified lines
3112	F: Documentation/devicetree/bindings/net/asix,ax88796c.yaml	3105	F: Documentation/devicetree/bindings/net/asix,ax88796c.yaml
3113	F: drivers/net/ethernet/asix/ax88796c_*	3106	F: drivers/net/ethernet/asix/ax88796c_*
3114		3107
		3108	ASPEED CRYPTO DRIVER
		3109	M: Neal Liu <neal_liu@aspeedtech.com>
		3110	L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
		3111	S: Maintained
		3112	F: Documentation/devicetree/bindings/crypto/aspeed,*
		3113	F: drivers/crypto/aspeed/
		3114
3115	ASPEED PECI CONTROLLER	3115	ASPEED PECI CONTROLLER
3116	M: Iwona Winiarska <iwona.winiarska@intel.com>	3116	M: Iwona Winiarska <iwona.winiarska@intel.com>
3117	L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)	3117	L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
@@ -3156,6 +3156,13 @@ S: Maintained · 38 unmodified lines
3156	F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml	3156	F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
3157	F: drivers/spi/spi-aspeed-smc.c	3157	F: drivers/spi/spi-aspeed-smc.c
3158		3158
		3159	ASPEED USB UDC DRIVER
		3160	M: Neal Liu <neal_liu@aspeedtech.com>
		3161	L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
		3162	S: Maintained
		3163	F: Documentation/devicetree/bindings/usb/aspeed,ast2600-udc.yaml
		3164	F: drivers/usb/gadget/udc/aspeed_udc.c
		3165
3159	ASPEED VIDEO ENGINE DRIVER	3166	ASPEED VIDEO ENGINE DRIVER
3160	M: Eddie James <eajames@linux.ibm.com>	3167	M: Eddie James <eajames@linux.ibm.com>
3161	L: linux-media@vger.kernel.org	3168	L: linux-media@vger.kernel.org
@@ -3164,19 +3171,11 @@ S: Maintained · 2 unmodified lines
3164	F: Documentation/devicetree/bindings/media/aspeed-video.txt	3171	F: Documentation/devicetree/bindings/media/aspeed-video.txt
3165	F: drivers/media/platform/aspeed/	3172	F: drivers/media/platform/aspeed/
3166		3173
3167	ASPEED USB UDC DRIVER	3174	ASUS EC HARDWARE MONITOR DRIVER
3168	M: Neal Liu <neal_liu@aspeedtech.com>	3175	M: Eugene Shalygin <eugene.shalygin@gmail.com>
3169	L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)	3176	L: linux-hwmon@vger.kernel.org
3170	S: Maintained
3171	F: Documentation/devicetree/bindings/usb/aspeed,ast2600-udc.yaml
3172	F: drivers/usb/gadget/udc/aspeed_udc.c
3173
3174	ASPEED CRYPTO DRIVER
3175	M: Neal Liu <neal_liu@aspeedtech.com>
3176	L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
3177	S: Maintained	3177	S: Maintained
3178	F: Documentation/devicetree/bindings/crypto/aspeed,*	3178	F: drivers/hwmon/asus-ec-sensors.c
3179	F: drivers/crypto/aspeed/
3180		3179
3181	ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS	3180	ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS
3182	M: Corentin Chary <corentin.chary@gmail.com>	3181	M: Corentin Chary <corentin.chary@gmail.com>
@@ -3194,6 +3193,12 @@ S: Maintained · 11 unmodified lines
3194	T: git git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git	3193	T: git git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git
3195	F: drivers/platform/x86/asus-tf103c-dock.c	3194	F: drivers/platform/x86/asus-tf103c-dock.c
3196		3195
		3196	ASUS WIRELESS RADIO CONTROL DRIVER
		3197	M: João Paulo Rechi Vita <jprvita@gmail.com>
		3198	L: platform-driver-x86@vger.kernel.org
		3199	S: Maintained
		3200	F: drivers/platform/x86/asus-wireless.c
		3201
3197	ASUS WMI HARDWARE MONITOR DRIVER	3202	ASUS WMI HARDWARE MONITOR DRIVER
3198	M: Ed Brindley <kernel@maidavale.org>	3203	M: Ed Brindley <kernel@maidavale.org>
3199	M: Denis Pauk <pauk.denis@gmail.com>	3204	M: Denis Pauk <pauk.denis@gmail.com>
@@ -3201,18 +3206,6 @@ L: linux-hwmon@vger.kernel.org · 1 unmodified line
3201	S: Maintained	3206	S: Maintained
3202	F: drivers/hwmon/asus_wmi_sensors.c	3207	F: drivers/hwmon/asus_wmi_sensors.c
3203		3208
3204	ASUS EC HARDWARE MONITOR DRIVER
3205	M: Eugene Shalygin <eugene.shalygin@gmail.com>
3206	L: linux-hwmon@vger.kernel.org
3207	S: Maintained
3208	F: drivers/hwmon/asus-ec-sensors.c
3209
3210	ASUS WIRELESS RADIO CONTROL DRIVER
3211	M: João Paulo Rechi Vita <jprvita@gmail.com>
3212	L: platform-driver-x86@vger.kernel.org
3213	S: Maintained
3214	F: drivers/platform/x86/asus-wireless.c
3215
3216	ASYMMETRIC KEYS	3209	ASYMMETRIC KEYS
3217	M: David Howells <dhowells@redhat.com>	3210	M: David Howells <dhowells@redhat.com>
3218	L: keyrings@vger.kernel.org	3211	L: keyrings@vger.kernel.org
@@ -3352,10 +3345,10 @@ R: Boqun Feng <boqun.feng@gmail.com> · 133 unmodified lines
3352	R: Mark Rutland <mark.rutland@arm.com>	3345	R: Mark Rutland <mark.rutland@arm.com>
3353	L: linux-kernel@vger.kernel.org	3346	L: linux-kernel@vger.kernel.org
3354	S: Maintained	3347	S: Maintained
		3348	F: Documentation/atomic_*.txt
3355	F: arch//include/asm/atomic.h	3349	F: arch//include/asm/atomic.h
3356	F: include//atomic.h	3350	F: include//atomic.h
3357	F: include/linux/refcount.h	3351	F: include/linux/refcount.h
3358	F: Documentation/atomic_*.txt
3359	F: scripts/atomic/	3352	F: scripts/atomic/
3360		3353
3361	ATTO EXPRESSSAS SAS/SATA RAID SCSI DRIVER	3354	ATTO EXPRESSSAS SAS/SATA RAID SCSI DRIVER
@@ -3649,50 +3642,6 @@ S: Maintained · 287 unmodified lines
3649	F: Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml	3642	F: Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml
3650	F: drivers/iio/accel/bma400*	3643	F: drivers/iio/accel/bma400*
3651		3644
3652	BPF [GENERAL] (Safe Dynamic Programs and Tools)
3653	M: Alexei Starovoitov <ast@kernel.org>
3654	M: Daniel Borkmann <daniel@iogearbox.net>
3655	M: Andrii Nakryiko <andrii@kernel.org>
3656	R: Martin KaFai Lau <martin.lau@linux.dev>
3657	R: Song Liu <song@kernel.org>
3658	R: Yonghong Song <yhs@fb.com>
3659	R: John Fastabend <john.fastabend@gmail.com>
3660	R: KP Singh <kpsingh@kernel.org>
3661	R: Stanislav Fomichev <sdf@google.com>
3662	R: Hao Luo <haoluo@google.com>
3663	R: Jiri Olsa <jolsa@kernel.org>
3664	L: bpf@vger.kernel.org
3665	S: Supported
3666	W: https://bpf.io/
3667	Q: https://patchwork.kernel.org/project/netdevbpf/list/?delegate=121173
3668	T: git git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git
3669	T: git git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git
3670	F: Documentation/bpf/
3671	F: Documentation/networking/filter.rst
3672	F: Documentation/userspace-api/ebpf/
3673	F: arch//net/
3674	F: include/linux/bpf*
3675	F: include/linux/btf*
3676	F: include/linux/filter.h
3677	F: include/trace/events/xdp.h
3678	F: include/uapi/linux/bpf*
3679	F: include/uapi/linux/btf*
3680	F: include/uapi/linux/filter.h
3681	F: kernel/bpf/
3682	F: kernel/trace/bpf_trace.c
3683	F: lib/test_bpf.c
3684	F: net/bpf/
3685	F: net/core/filter.c
3686	F: net/sched/act_bpf.c
3687	F: net/sched/cls_bpf.c
3688	F: samples/bpf/
3689	F: scripts/bpf_doc.py
3690	F: scripts/pahole-flags.sh
3691	F: scripts/pahole-version.sh
3692	F: tools/bpf/
3693	F: tools/lib/bpf/
3694	F: tools/testing/selftests/bpf/
3695
3696	BPF JIT for ARM	3645	BPF JIT for ARM
3697	M: Shubham Bansal <illusionist.neo@gmail.com>	3646	M: Shubham Bansal <illusionist.neo@gmail.com>
3698	L: bpf@vger.kernel.org	3647	L: bpf@vger.kernel.org
@@ -3771,79 +3720,79 @@ S: Supported · 72 unmodified lines
3771	F: arch/x86/net/	3720	F: arch/x86/net/
3772	X: arch/x86/net/bpf_jit_comp32.c	3721	X: arch/x86/net/bpf_jit_comp32.c
3773		3722
		3723	BPF [BTF]
		3724	M: Martin KaFai Lau <martin.lau@linux.dev>
		3725	L: bpf@vger.kernel.org
		3726	S: Maintained
		3727	F: include/linux/btf*
		3728	F: kernel/bpf/btf.c
		3729
3774	BPF [CORE]	3730	BPF [CORE]
3775	M: Alexei Starovoitov <ast@kernel.org>	3731	M: Alexei Starovoitov <ast@kernel.org>
3776	M: Daniel Borkmann <daniel@iogearbox.net>	3732	M: Daniel Borkmann <daniel@iogearbox.net>
3777	R: John Fastabend <john.fastabend@gmail.com>	3733	R: John Fastabend <john.fastabend@gmail.com>
3778	L: bpf@vger.kernel.org	3734	L: bpf@vger.kernel.org
3779	S: Maintained	3735	S: Maintained
3780	F: kernel/bpf/verifier.c
3781	F: kernel/bpf/tnum.c
3782	F: kernel/bpf/core.c
3783	F: kernel/bpf/syscall.c
3784	F: kernel/bpf/dispatcher.c
3785	F: kernel/bpf/trampoline.c
3786	F: include/linux/bpf*	3736	F: include/linux/bpf*
3787	F: include/linux/filter.h	3737	F: include/linux/filter.h
3788	F: include/linux/tnum.h	3738	F: include/linux/tnum.h
		3739	F: kernel/bpf/core.c
		3740	F: kernel/bpf/dispatcher.c
		3741	F: kernel/bpf/syscall.c
		3742	F: kernel/bpf/tnum.c
		3743	F: kernel/bpf/trampoline.c
		3744	F: kernel/bpf/verifier.c
3789		3745
3790	BPF [BTF]	3746	BPF [DOCUMENTATION] (Related to Standardization)
3791	M: Martin KaFai Lau <martin.lau@linux.dev>	3747	R: David Vernet <void@manifault.com>
3792	L: bpf@vger.kernel.org
3793	S: Maintained
3794	F: kernel/bpf/btf.c
3795	F: include/linux/btf*
3796
3797	BPF [TRACING]
3798	M: Song Liu <song@kernel.org>
3799	R: Jiri Olsa <jolsa@kernel.org>
3800	L: bpf@vger.kernel.org	3748	L: bpf@vger.kernel.org
		3749	L: bpf@ietf.org
3801	S: Maintained	3750	S: Maintained
3802	F: kernel/trace/bpf_trace.c	3751	F: Documentation/bpf/instruction-set.rst
3803	F: kernel/bpf/stackmap.c
3804		3752
3805	BPF [NETWORKING] (tc BPF, sock_addr)	3753	BPF [GENERAL] (Safe Dynamic Programs and Tools)
3806	M: Martin KaFai Lau <martin.lau@linux.dev>	3754	M: Alexei Starovoitov <ast@kernel.org>
3807	M: Daniel Borkmann <daniel@iogearbox.net>	3755	M: Daniel Borkmann <daniel@iogearbox.net>
		3756	M: Andrii Nakryiko <andrii@kernel.org>
		3757	R: Martin KaFai Lau <martin.lau@linux.dev>
		3758	R: Song Liu <song@kernel.org>
		3759	R: Yonghong Song <yhs@fb.com>
3808	R: John Fastabend <john.fastabend@gmail.com>	3760	R: John Fastabend <john.fastabend@gmail.com>
		3761	R: KP Singh <kpsingh@kernel.org>
		3762	R: Stanislav Fomichev <sdf@google.com>
		3763	R: Hao Luo <haoluo@google.com>
		3764	R: Jiri Olsa <jolsa@kernel.org>
3809	L: bpf@vger.kernel.org	3765	L: bpf@vger.kernel.org
3810	L: netdev@vger.kernel.org	3766	S: Supported
3811	S: Maintained	3767	W: https://bpf.io/
		3768	Q: https://patchwork.kernel.org/project/netdevbpf/list/?delegate=121173
		3769	T: git git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git
		3770	T: git git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git
		3771	F: Documentation/bpf/
		3772	F: Documentation/networking/filter.rst
		3773	F: Documentation/userspace-api/ebpf/
		3774	F: arch//net/
		3775	F: include/linux/bpf*
		3776	F: include/linux/btf*
		3777	F: include/linux/filter.h
		3778	F: include/trace/events/xdp.h
		3779	F: include/uapi/linux/bpf*
		3780	F: include/uapi/linux/btf*
		3781	F: include/uapi/linux/filter.h
		3782	F: kernel/bpf/
		3783	F: kernel/trace/bpf_trace.c
		3784	F: lib/test_bpf.c
		3785	F: net/bpf/
3812	F: net/core/filter.c	3786	F: net/core/filter.c
3813	F: net/sched/act_bpf.c	3787	F: net/sched/act_bpf.c
3814	F: net/sched/cls_bpf.c	3788	F: net/sched/cls_bpf.c
3815		3789	F: samples/bpf/
3816	BPF [NETWORKING] (struct_ops, reuseport)	3790	F: scripts/bpf_doc.py
3817	M: Martin KaFai Lau <martin.lau@linux.dev>	3791	F: scripts/pahole-flags.sh
3818	L: bpf@vger.kernel.org	3792	F: scripts/pahole-version.sh
3819	L: netdev@vger.kernel.org	3793	F: tools/bpf/
3820	S: Maintained	3794	F: tools/lib/bpf/
3821	F: kernel/bpf/bpf_struct*	3795	F: tools/testing/selftests/bpf/
3822
3823	BPF [SECURITY & LSM] (Security Audit and Enforcement using BPF)
3824	M: KP Singh <kpsingh@kernel.org>
3825	R: Florent Revest <revest@chromium.org>
3826	R: Brendan Jackman <jackmanb@chromium.org>
3827	L: bpf@vger.kernel.org
3828	S: Maintained
3829	F: Documentation/bpf/prog_lsm.rst
3830	F: include/linux/bpf_lsm.h
3831	F: kernel/bpf/bpf_lsm.c
3832	F: security/bpf/
3833
3834	BPF [STORAGE & CGROUPS]
3835	M: Martin KaFai Lau <martin.lau@linux.dev>
3836	L: bpf@vger.kernel.org
3837	S: Maintained
3838	F: kernel/bpf/cgroup.c
3839	F: kernel/bpf/*storage.c
3840	F: kernel/bpf/bpf_lru*
3841
3842	BPF [RINGBUF]
3843	M: Andrii Nakryiko <andrii@kernel.org>
3844	L: bpf@vger.kernel.org
3845	S: Maintained
3846	F: kernel/bpf/ringbuf.c
3847		3796
3848	BPF [ITERATOR]	3797	BPF [ITERATOR]
3849	M: Yonghong Song <yhs@fb.com>	3798	M: Yonghong Song <yhs@fb.com>
@@ -3870,12 +3819,45 @@ L: bpf@vger.kernel.org · 20 unmodified lines
3870	S: Maintained	3819	S: Maintained
3871	F: tools/lib/bpf/	3820	F: tools/lib/bpf/
3872		3821
3873	BPF [TOOLING] (bpftool)	3822	BPF [MISC]
3874	M: Quentin Monnet <quentin@isovalent.com>	3823	L: bpf@vger.kernel.org
		3824	S: Odd Fixes
		3825	K: (?:\b\|_)bpf(?:\b\|_)
		3826
		3827	BPF [NETWORKING] (struct_ops, reuseport)
		3828	M: Martin KaFai Lau <martin.lau@linux.dev>
3875	L: bpf@vger.kernel.org	3829	L: bpf@vger.kernel.org
		3830	L: netdev@vger.kernel.org
3876	S: Maintained	3831	S: Maintained
3877	F: kernel/bpf/disasm.*	3832	F: kernel/bpf/bpf_struct*
3878	F: tools/bpf/bpftool/	3833
		3834	BPF [NETWORKING] (tc BPF, sock_addr)
		3835	M: Martin KaFai Lau <martin.lau@linux.dev>
		3836	M: Daniel Borkmann <daniel@iogearbox.net>
		3837	R: John Fastabend <john.fastabend@gmail.com>
		3838	L: bpf@vger.kernel.org
		3839	L: netdev@vger.kernel.org
		3840	S: Maintained
		3841	F: net/core/filter.c
		3842	F: net/sched/act_bpf.c
		3843	F: net/sched/cls_bpf.c
		3844
		3845	BPF [RINGBUF]
		3846	M: Andrii Nakryiko <andrii@kernel.org>
		3847	L: bpf@vger.kernel.org
		3848	S: Maintained
		3849	F: kernel/bpf/ringbuf.c
		3850
		3851	BPF [SECURITY & LSM] (Security Audit and Enforcement using BPF)
		3852	M: KP Singh <kpsingh@kernel.org>
		3853	R: Florent Revest <revest@chromium.org>
		3854	R: Brendan Jackman <jackmanb@chromium.org>
		3855	L: bpf@vger.kernel.org
		3856	S: Maintained
		3857	F: Documentation/bpf/prog_lsm.rst
		3858	F: include/linux/bpf_lsm.h
		3859	F: kernel/bpf/bpf_lsm.c
		3860	F: security/bpf/
3879		3861
3880	BPF [SELFTESTS] (Test Runners & Infrastructure)	3862	BPF [SELFTESTS] (Test Runners & Infrastructure)
3881	M: Andrii Nakryiko <andrii@kernel.org>	3863	M: Andrii Nakryiko <andrii@kernel.org>
@@ -3884,17 +3866,28 @@ L: bpf@vger.kernel.org · 2 unmodified lines
3884	S: Maintained	3866	S: Maintained
3885	F: tools/testing/selftests/bpf/	3867	F: tools/testing/selftests/bpf/
3886		3868
3887	BPF [DOCUMENTATION] (Related to Standardization)	3869	BPF [STORAGE & CGROUPS]
3888	R: David Vernet <void@manifault.com>	3870	M: Martin KaFai Lau <martin.lau@linux.dev>
3889	L: bpf@vger.kernel.org	3871	L: bpf@vger.kernel.org
3890	L: bpf@ietf.org
3891	S: Maintained	3872	S: Maintained
3892	F: Documentation/bpf/instruction-set.rst	3873	F: kernel/bpf/*storage.c
		3874	F: kernel/bpf/bpf_lru*
		3875	F: kernel/bpf/cgroup.c
3893		3876
3894	BPF [MISC]	3877	BPF [TOOLING] (bpftool)
		3878	M: Quentin Monnet <quentin@isovalent.com>
3895	L: bpf@vger.kernel.org	3879	L: bpf@vger.kernel.org
3896	S: Odd Fixes	3880	S: Maintained
3897	K: (?:\b\|_)bpf(?:\b\|_)	3881	F: kernel/bpf/disasm.*
		3882	F: tools/bpf/bpftool/
		3883
		3884	BPF [TRACING]
		3885	M: Song Liu <song@kernel.org>
		3886	R: Jiri Olsa <jolsa@kernel.org>
		3887	L: bpf@vger.kernel.org
		3888	S: Maintained
		3889	F: kernel/bpf/stackmap.c
		3890	F: kernel/trace/bpf_trace.c
3898		3891
3899	BROADCOM B44 10/100 ETHERNET DRIVER	3892	BROADCOM B44 10/100 ETHERNET DRIVER
3900	M: Michael Chan <michael.chan@broadcom.com>	3893	M: Michael Chan <michael.chan@broadcom.com>
@@ -3913,34 +3906,6 @@ F: drivers/net/dsa/bcm_sf2* · 12 unmodified lines
3913	F: include/linux/dsa/brcm.h	3906	F: include/linux/dsa/brcm.h
3914	F: include/linux/platform_data/b53.h	3907	F: include/linux/platform_data/b53.h
3915		3908
3916	BROADCOM BCMBCA ARM ARCHITECTURE
3917	M: William Zhang <william.zhang@broadcom.com>
3918	M: Anand Gore <anand.gore@broadcom.com>
3919	M: Kursad Oney <kursad.oney@broadcom.com>
3920	M: Florian Fainelli <f.fainelli@gmail.com>
3921	M: Rafał Miłecki <rafal@milecki.pl>
3922	R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
3923	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
3924	S: Maintained
3925	T: git https://github.com/broadcom/stblinux.git
3926	F: Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml
3927	F: arch/arm64/boot/dts/broadcom/bcmbca/*
3928	N: bcmbca
3929	N: bcm[9]?47622
3930	N: bcm[9]?4912
3931	N: bcm[9]?63138
3932	N: bcm[9]?63146
3933	N: bcm[9]?63148
3934	N: bcm[9]?63158
3935	N: bcm[9]?63178
3936	N: bcm[9]?6756
3937	N: bcm[9]?6813
3938	N: bcm[9]?6846
3939	N: bcm[9]?6855
3940	N: bcm[9]?6856
3941	N: bcm[9]?6858
3942	N: bcm[9]?6878
3943
3944	BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE	3909	BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
3945	M: Florian Fainelli <f.fainelli@gmail.com>	3910	M: Florian Fainelli <f.fainelli@gmail.com>
3946	R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>	3911	R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
@@ -4038,11 +4003,39 @@ N: brcmstb · 91 unmodified lines
4038	N: bcm7038	4003	N: bcm7038
4039	N: bcm7120	4004	N: bcm7120
4040		4005
		4006	BROADCOM BCMBCA ARM ARCHITECTURE
		4007	M: William Zhang <william.zhang@broadcom.com>
		4008	M: Anand Gore <anand.gore@broadcom.com>
		4009	M: Kursad Oney <kursad.oney@broadcom.com>
		4010	M: Florian Fainelli <f.fainelli@gmail.com>
		4011	M: Rafał Miłecki <rafal@milecki.pl>
		4012	R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
		4013	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
		4014	S: Maintained
		4015	T: git https://github.com/broadcom/stblinux.git
		4016	F: Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml
		4017	F: arch/arm64/boot/dts/broadcom/bcmbca/*
		4018	N: bcmbca
		4019	N: bcm[9]?47622
		4020	N: bcm[9]?4912
		4021	N: bcm[9]?63138
		4022	N: bcm[9]?63146
		4023	N: bcm[9]?63148
		4024	N: bcm[9]?63158
		4025	N: bcm[9]?63178
		4026	N: bcm[9]?6756
		4027	N: bcm[9]?6813
		4028	N: bcm[9]?6846
		4029	N: bcm[9]?6855
		4030	N: bcm[9]?6856
		4031	N: bcm[9]?6858
		4032	N: bcm[9]?6878
		4033
4041	BROADCOM BDC DRIVER	4034	BROADCOM BDC DRIVER
4042	M: Justin Chen <justinpopo6@gmail.com>	4035	M: Justin Chen <justinpopo6@gmail.com>
4043	M: Al Cooper <alcooperx@gmail.com>	4036	M: Al Cooper <alcooperx@gmail.com>
4044	L: linux-usb@vger.kernel.org
4045	R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>	4037	R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
		4038	L: linux-usb@vger.kernel.org
4046	S: Maintained	4039	S: Maintained
4047	F: Documentation/devicetree/bindings/usb/brcm,bdc.yaml	4040	F: Documentation/devicetree/bindings/usb/brcm,bdc.yaml
4048	F: drivers/usb/gadget/udc/bdc/	4041	F: drivers/usb/gadget/udc/bdc/
@@ -4064,10 +4057,10 @@ F: arch/mips/bmips/* · 15 unmodified lines
4064	F: arch/mips/boot/dts/brcm/bcm.dts	4057	F: arch/mips/boot/dts/brcm/bcm.dts
4065	F: arch/mips/include/asm/mach-bmips/*	4058	F: arch/mips/include/asm/mach-bmips/*
4066	F: arch/mips/kernel/bmips	4059	F: arch/mips/kernel/bmips
4067	F: drivers/soc/bcm/bcm63xx
4068	F: drivers/irqchip/irq-bcm63*	4060	F: drivers/irqchip/irq-bcm63*
4069	F: drivers/irqchip/irq-bcm7*	4061	F: drivers/irqchip/irq-bcm7*
4070	F: drivers/irqchip/irq-brcmstb*	4062	F: drivers/irqchip/irq-brcmstb*
		4063	F: drivers/soc/bcm/bcm63xx
4071	F: include/linux/bcm963xx_nvram.h	4064	F: include/linux/bcm963xx_nvram.h
4072	F: include/linux/bcm963xx_tag.h	4065	F: include/linux/bcm963xx_tag.h
4073		4066
@@ -4349,9 +4342,9 @@ M: Florian Fainelli <f.fainelli@gmail.com> · 275 unmodified lines
4349	R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>	4342	R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
4350	L: netdev@vger.kernel.org	4343	L: netdev@vger.kernel.org
4351	S: Supported	4344	S: Supported
		4345	F: Documentation/devicetree/bindings/net/brcm,systemport.yaml
4352	F: drivers/net/ethernet/broadcom/bcmsysport.*	4346	F: drivers/net/ethernet/broadcom/bcmsysport.*
4353	F: drivers/net/ethernet/broadcom/unimac.h	4347	F: drivers/net/ethernet/broadcom/unimac.h
4354	F: Documentation/devicetree/bindings/net/brcm,systemport.yaml
4355		4348
4356	BROADCOM TG3 GIGABIT ETHERNET DRIVER	4349	BROADCOM TG3 GIGABIT ETHERNET DRIVER
4357	M: Siva Reddy Kallam <siva.kallam@broadcom.com>	4350	M: Siva Reddy Kallam <siva.kallam@broadcom.com>
@@ -4483,29 +4476,6 @@ W: https://github.com/Cascoda/ca8210-linux.git · 125 unmodified lines
4483	F: Documentation/devicetree/bindings/net/ieee802154/ca8210.txt	4476	F: Documentation/devicetree/bindings/net/ieee802154/ca8210.txt
4484	F: drivers/net/ieee802154/ca8210.c	4477	F: drivers/net/ieee802154/ca8210.c
4485		4478
4486	CANAAN/KENDRYTE K210 SOC FPIOA DRIVER
4487	M: Damien Le Moal <dlemoal@kernel.org>
4488	L: linux-riscv@lists.infradead.org
4489	L: linux-gpio@vger.kernel.org (pinctrl driver)
4490	F: Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml
4491	F: drivers/pinctrl/pinctrl-k210.c
4492
4493	CANAAN/KENDRYTE K210 SOC RESET CONTROLLER DRIVER
4494	M: Damien Le Moal <dlemoal@kernel.org>
4495	L: linux-kernel@vger.kernel.org
4496	L: linux-riscv@lists.infradead.org
4497	S: Maintained
4498	F: Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml
4499	F: drivers/reset/reset-k210.c
4500
4501	CANAAN/KENDRYTE K210 SOC SYSTEM CONTROLLER DRIVER
4502	M: Damien Le Moal <dlemoal@kernel.org>
4503	L: linux-riscv@lists.infradead.org
4504	S: Maintained
4505	F: Documentation/devicetree/bindings/mfd/canaan,k210-sysctl.yaml
4506	F: drivers/soc/canaan/
4507	F: include/soc/canaan/
4508
4509	CACHEFILES: FS-CACHE BACKEND FOR CACHING ON MOUNTED FILESYSTEMS	4479	CACHEFILES: FS-CACHE BACKEND FOR CACHING ON MOUNTED FILESYSTEMS
4510	M: David Howells <dhowells@redhat.com>	4480	M: David Howells <dhowells@redhat.com>
4511	L: linux-cachefs@redhat.com (moderated for non-subscribers)	4481	L: linux-cachefs@redhat.com (moderated for non-subscribers)
@@ -4627,6 +4597,29 @@ F: Documentation/networking/j1939.rst · 115 unmodified lines
4627	F: include/uapi/linux/can/j1939.h	4597	F: include/uapi/linux/can/j1939.h
4628	F: net/can/j1939/	4598	F: net/can/j1939/
4629		4599
		4600	CANAAN/KENDRYTE K210 SOC FPIOA DRIVER
		4601	M: Damien Le Moal <dlemoal@kernel.org>
		4602	L: linux-riscv@lists.infradead.org
		4603	L: linux-gpio@vger.kernel.org (pinctrl driver)
		4604	F: Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml
		4605	F: drivers/pinctrl/pinctrl-k210.c
		4606
		4607	CANAAN/KENDRYTE K210 SOC RESET CONTROLLER DRIVER
		4608	M: Damien Le Moal <dlemoal@kernel.org>
		4609	L: linux-kernel@vger.kernel.org
		4610	L: linux-riscv@lists.infradead.org
		4611	S: Maintained
		4612	F: Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml
		4613	F: drivers/reset/reset-k210.c
		4614
		4615	CANAAN/KENDRYTE K210 SOC SYSTEM CONTROLLER DRIVER
		4616	M: Damien Le Moal <dlemoal@kernel.org>
		4617	L: linux-riscv@lists.infradead.org
		4618	S: Maintained
		4619	F: Documentation/devicetree/bindings/mfd/canaan,k210-sysctl.yaml
		4620	F: drivers/soc/canaan/
		4621	F: include/soc/canaan/
		4622
4630	CAPABILITIES	4623	CAPABILITIES
4631	M: Serge Hallyn <serge@hallyn.com>	4624	M: Serge Hallyn <serge@hallyn.com>
4632	L: linux-security-module@vger.kernel.org	4625	L: linux-security-module@vger.kernel.org
@@ -4686,8 +4679,8 @@ F: arch/arm64/boot/dts/cavium/thunder2-99xx* · 53 unmodified lines
4686		4679
4687	CBS/ETF/TAPRIO QDISCS	4680	CBS/ETF/TAPRIO QDISCS
4688	M: Vinicius Costa Gomes <vinicius.gomes@intel.com>	4681	M: Vinicius Costa Gomes <vinicius.gomes@intel.com>
4689	S: Maintained
4690	L: netdev@vger.kernel.org	4682	L: netdev@vger.kernel.org
		4683	S: Maintained
4691	F: net/sched/sch_cbs.c	4684	F: net/sched/sch_cbs.c
4692	F: net/sched/sch_etf.c	4685	F: net/sched/sch_etf.c
4693	F: net/sched/sch_taprio.c	4686	F: net/sched/sch_taprio.c
@@ -4710,10 +4703,10 @@ CCTRNG ARM TRUSTZONE CRYPTOCELL TRUE RANDOM NUMBER GENERATOR (TRNG) DRIVER · 16 unmodified lines
4710	M: Hadar Gat <hadar.gat@arm.com>	4703	M: Hadar Gat <hadar.gat@arm.com>
4711	L: linux-crypto@vger.kernel.org	4704	L: linux-crypto@vger.kernel.org
4712	S: Supported	4705	S: Supported
		4706	W: https://developer.arm.com/products/system-ip/trustzone-cryptocell/cryptocell-700-family
		4707	F: Documentation/devicetree/bindings/rng/arm-cctrng.yaml
4713	F: drivers/char/hw_random/cctrng.c	4708	F: drivers/char/hw_random/cctrng.c
4714	F: drivers/char/hw_random/cctrng.h	4709	F: drivers/char/hw_random/cctrng.h
4715	F: Documentation/devicetree/bindings/rng/arm-cctrng.yaml
4716	W: https://developer.arm.com/products/system-ip/trustzone-cryptocell/cryptocell-700-family
4717		4710
4718	CEC FRAMEWORK	4711	CEC FRAMEWORK
4719	M: Hans Verkuil <hverkuil-cisco@xs4all.nl>	4712	M: Hans Verkuil <hverkuil-cisco@xs4all.nl>
@@ -4873,13 +4866,6 @@ S: Maintained · 153 unmodified lines
4873	F: Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml	4866	F: Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml
4874	F: sound/soc/codecs/cros_ec_codec.*	4867	F: sound/soc/codecs/cros_ec_codec.*
4875		4868
4876	CHROMEOS EC UART DRIVER
4877	M: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
4878	R: Benson Leung <bleung@chromium.org>
4879	R: Tzung-Bi Shih <tzungbi@kernel.org>
4880	S: Maintained
4881	F: drivers/platform/chrome/cros_ec_uart.c
4882
4883	CHROMEOS EC SUBDRIVERS	4869	CHROMEOS EC SUBDRIVERS
4884	M: Benson Leung <bleung@chromium.org>	4870	M: Benson Leung <bleung@chromium.org>
4885	R: Guenter Roeck <groeck@chromium.org>	4871	R: Guenter Roeck <groeck@chromium.org>
@@ -4889,13 +4875,12 @@ F: drivers/power/supply/cros_usbpd-charger.c · 3 unmodified lines
4889	N: cros_ec	4875	N: cros_ec
4890	N: cros-ec	4876	N: cros-ec
4891		4877
4892	CHROMEOS EC USB TYPE-C DRIVER	4878	CHROMEOS EC UART DRIVER
4893	M: Prashant Malani <pmalani@chromium.org>	4879	M: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
4894	L: chrome-platform@lists.linux.dev	4880	R: Benson Leung <bleung@chromium.org>
		4881	R: Tzung-Bi Shih <tzungbi@kernel.org>
4895	S: Maintained	4882	S: Maintained
4896	F: drivers/platform/chrome/cros_ec_typec.*	4883	F: drivers/platform/chrome/cros_ec_uart.c
4897	F: drivers/platform/chrome/cros_typec_switch.c
4898	F: drivers/platform/chrome/cros_typec_vdm.*
4899		4884
4900	CHROMEOS EC USB PD NOTIFY DRIVER	4885	CHROMEOS EC USB PD NOTIFY DRIVER
4901	M: Prashant Malani <pmalani@chromium.org>	4886	M: Prashant Malani <pmalani@chromium.org>
@@ -4904,6 +4889,14 @@ S: Maintained · 2 unmodified lines
4904	F: drivers/platform/chrome/cros_usbpd_notify.c	4889	F: drivers/platform/chrome/cros_usbpd_notify.c
4905	F: include/linux/platform_data/cros_usbpd_notify.h	4890	F: include/linux/platform_data/cros_usbpd_notify.h
4906		4891
		4892	CHROMEOS EC USB TYPE-C DRIVER
		4893	M: Prashant Malani <pmalani@chromium.org>
		4894	L: chrome-platform@lists.linux.dev
		4895	S: Maintained
		4896	F: drivers/platform/chrome/cros_ec_typec.*
		4897	F: drivers/platform/chrome/cros_typec_switch.c
		4898	F: drivers/platform/chrome/cros_typec_vdm.*
		4899
4907	CHROMEOS HPS DRIVER	4900	CHROMEOS HPS DRIVER
4908	M: Dan Callaghan <dcallagh@chromium.org>	4901	M: Dan Callaghan <dcallagh@chromium.org>
4909	R: Sami Kyöstilä <skyostil@chromium.org>	4902	R: Sami Kyöstilä <skyostil@chromium.org>
@@ -5021,6 +5014,18 @@ M: Nelson Escobar <neescoba@cisco.com> · 111 unmodified lines
5021	S: Supported	5014	S: Supported
5022	F: drivers/infiniband/hw/usnic/	5015	F: drivers/infiniband/hw/usnic/
5023		5016
		5017	CLANG CONTROL FLOW INTEGRITY SUPPORT
		5018	M: Sami Tolvanen <samitolvanen@google.com>
		5019	M: Kees Cook <keescook@chromium.org>
		5020	R: Nathan Chancellor <nathan@kernel.org>
		5021	R: Nick Desaulniers <ndesaulniers@google.com>
		5022	L: llvm@lists.linux.dev
		5023	S: Supported
		5024	B: https://github.com/ClangBuiltLinux/linux/issues
		5025	T: git git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git for-next/hardening
		5026	F: include/linux/cfi.h
		5027	F: kernel/cfi.c
		5028
5024	CLANG-FORMAT FILE	5029	CLANG-FORMAT FILE
5025	M: Miguel Ojeda <ojeda@kernel.org>	5030	M: Miguel Ojeda <ojeda@kernel.org>
5026	S: Maintained	5031	S: Maintained
@@ -5041,18 +5046,6 @@ F: scripts/Makefile.clang · 14 unmodified lines
5041	F: scripts/clang-tools/	5046	F: scripts/clang-tools/
5042	K: \b(?i:clang\|llvm)\b	5047	K: \b(?i:clang\|llvm)\b
5043		5048
5044	CLANG CONTROL FLOW INTEGRITY SUPPORT
5045	M: Sami Tolvanen <samitolvanen@google.com>
5046	M: Kees Cook <keescook@chromium.org>
5047	R: Nathan Chancellor <nathan@kernel.org>
5048	R: Nick Desaulniers <ndesaulniers@google.com>
5049	L: llvm@lists.linux.dev
5050	S: Supported
5051	B: https://github.com/ClangBuiltLinux/linux/issues
5052	T: git git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git for-next/hardening
5053	F: include/linux/cfi.h
5054	F: kernel/cfi.c
5055
5056	CLK API	5049	CLK API
5057	M: Russell King <linux@armlinux.org.uk>	5050	M: Russell King <linux@armlinux.org.uk>
5058	L: linux-clk@vger.kernel.org	5051	L: linux-clk@vger.kernel.org
@@ -5223,8 +5216,8 @@ CONTEXT TRACKING · 164 unmodified lines
5223	M: Frederic Weisbecker <frederic@kernel.org>	5216	M: Frederic Weisbecker <frederic@kernel.org>
5224	M: "Paul E. McKenney" <paulmck@kernel.org>	5217	M: "Paul E. McKenney" <paulmck@kernel.org>
5225	S: Maintained	5218	S: Maintained
5226	F: kernel/context_tracking.c
5227	F: include/linux/context_tracking*	5219	F: include/linux/context_tracking*
		5220	F: kernel/context_tracking.c
5228		5221
5229	CONTROL GROUP (CGROUP)	5222	CONTROL GROUP (CGROUP)
5230	M: Tejun Heo <tj@kernel.org>	5223	M: Tejun Heo <tj@kernel.org>
@@ -5385,8 +5378,8 @@ F: drivers/cpuidle/cpuidle-big_little.c · 154 unmodified lines
5385		5378
5386	CPUIDLE DRIVER - ARM EXYNOS	5379	CPUIDLE DRIVER - ARM EXYNOS
5387	M: Daniel Lezcano <daniel.lezcano@linaro.org>	5380	M: Daniel Lezcano <daniel.lezcano@linaro.org>
5388	R: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
5389	M: Kukjin Kim <kgene@kernel.org>	5381	M: Kukjin Kim <kgene@kernel.org>
		5382	R: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
5390	L: linux-pm@vger.kernel.org	5383	L: linux-pm@vger.kernel.org
5391	L: linux-samsung-soc@vger.kernel.org	5384	L: linux-samsung-soc@vger.kernel.org
5392	S: Supported	5385	S: Supported
@@ -5407,8 +5400,8 @@ M: Ulf Hansson <ulf.hansson@linaro.org> · 14 unmodified lines
5407	L: linux-pm@vger.kernel.org	5400	L: linux-pm@vger.kernel.org
5408	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)	5401	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
5409	S: Supported	5402	S: Supported
5410	F: drivers/cpuidle/cpuidle-psci.h
5411	F: drivers/cpuidle/cpuidle-psci-domain.c	5403	F: drivers/cpuidle/cpuidle-psci-domain.c
		5404	F: drivers/cpuidle/cpuidle-psci.h
5412		5405
5413	CPUIDLE DRIVER - DT IDLE PM DOMAIN	5406	CPUIDLE DRIVER - DT IDLE PM DOMAIN
5414	M: Ulf Hansson <ulf.hansson@linaro.org>	5407	M: Ulf Hansson <ulf.hansson@linaro.org>
@@ -5552,19 +5545,19 @@ S: Supported · 137 unmodified lines
5552	W: http://www.chelsio.com	5545	W: http://www.chelsio.com
5553	F: drivers/crypto/chelsio	5546	F: drivers/crypto/chelsio
5554		5547
5555	CXGB4 INLINE CRYPTO DRIVER	5548	CXGB4 ETHERNET DRIVER (CXGB4)
5556	M: Ayush Sawal <ayush.sawal@chelsio.com>	5549	M: Raju Rangoju <rajur@chelsio.com>
5557	L: netdev@vger.kernel.org	5550	L: netdev@vger.kernel.org
5558	S: Supported	5551	S: Supported
5559	W: http://www.chelsio.com	5552	W: http://www.chelsio.com
5560	F: drivers/net/ethernet/chelsio/inline_crypto/	5553	F: drivers/net/ethernet/chelsio/cxgb4/
5561		5554
5562	CXGB4 ETHERNET DRIVER (CXGB4)	5555	CXGB4 INLINE CRYPTO DRIVER
5563	M: Raju Rangoju <rajur@chelsio.com>	5556	M: Ayush Sawal <ayush.sawal@chelsio.com>
5564	L: netdev@vger.kernel.org	5557	L: netdev@vger.kernel.org
5565	S: Supported	5558	S: Supported
5566	W: http://www.chelsio.com	5559	W: http://www.chelsio.com
5567	F: drivers/net/ethernet/chelsio/cxgb4/	5560	F: drivers/net/ethernet/chelsio/inline_crypto/
5568		5561
5569	CXGB4 ISCSI DRIVER (CXGB4I)	5562	CXGB4 ISCSI DRIVER (CXGB4I)
5570	M: Varun Prakash <varun@chelsio.com>	5563	M: Varun Prakash <varun@chelsio.com>
@@ -5621,16 +5614,6 @@ CYCLADES PC300 DRIVER · 50 unmodified lines
5621	S: Orphan	5614	S: Orphan
5622	F: drivers/net/wan/pc300*	5615	F: drivers/net/wan/pc300*
5623		5616
5624	CYPRESS_FIRMWARE MEDIA DRIVER
5625	M: Antti Palosaari <crope@iki.fi>
5626	L: linux-media@vger.kernel.org
5627	S: Maintained
5628	W: https://linuxtv.org
5629	W: http://palosaari.fi/linux/
5630	Q: http://patchwork.linuxtv.org/project/linux-media/list/
5631	T: git git://linuxtv.org/anttip/media_tree.git
5632	F: drivers/media/common/cypress_firmware*
5633
5634	CYPRESS CY8C95X0 PINCTRL DRIVER	5617	CYPRESS CY8C95X0 PINCTRL DRIVER
5635	M: Patrick Rudolph <patrick.rudolph@9elements.com>	5618	M: Patrick Rudolph <patrick.rudolph@9elements.com>
5636	L: linux-gpio@vger.kernel.org	5619	L: linux-gpio@vger.kernel.org
@@ -5650,6 +5633,16 @@ S: Maintained · 13 unmodified lines
5650	F: Documentation/devicetree/bindings/input/cypress-sf.yaml	5633	F: Documentation/devicetree/bindings/input/cypress-sf.yaml
5651	F: drivers/input/keyboard/cypress-sf.c	5634	F: drivers/input/keyboard/cypress-sf.c
5652		5635
		5636	CYPRESS_FIRMWARE MEDIA DRIVER
		5637	M: Antti Palosaari <crope@iki.fi>
		5638	L: linux-media@vger.kernel.org
		5639	S: Maintained
		5640	W: https://linuxtv.org
		5641	W: http://palosaari.fi/linux/
		5642	Q: http://patchwork.linuxtv.org/project/linux-media/list/
		5643	T: git git://linuxtv.org/anttip/media_tree.git
		5644	F: drivers/media/common/cypress_firmware*
		5645
5653	CYTTSP TOUCHSCREEN DRIVER	5646	CYTTSP TOUCHSCREEN DRIVER
5654	M: Linus Walleij <linus.walleij@linaro.org>	5647	M: Linus Walleij <linus.walleij@linaro.org>
5655	L: linux-input@vger.kernel.org	5648	L: linux-input@vger.kernel.org
@@ -5816,11 +5809,6 @@ S: Maintained · 160 unmodified lines
5816	F: Documentation/driver-api/dcdbas.rst	5809	F: Documentation/driver-api/dcdbas.rst
5817	F: drivers/platform/x86/dell/dcdbas.*	5810	F: drivers/platform/x86/dell/dcdbas.*
5818		5811
5819	DELL WMI DESCRIPTOR DRIVER
5820	L: Dell.Client.Kernel@dell.com
5821	S: Maintained
5822	F: drivers/platform/x86/dell/dell-wmi-descriptor.c
5823
5824	DELL WMI DDV DRIVER	5812	DELL WMI DDV DRIVER
5825	M: Armin Wolf <W_Armin@gmx.de>	5813	M: Armin Wolf <W_Armin@gmx.de>
5826	S: Maintained	5814	S: Maintained
@@ -5828,13 +5816,17 @@ F: Documentation/ABI/testing/debugfs-dell-wmi-ddv · 1 unmodified line
5828	F: Documentation/ABI/testing/sysfs-platform-dell-wmi-ddv	5816	F: Documentation/ABI/testing/sysfs-platform-dell-wmi-ddv
5829	F: drivers/platform/x86/dell/dell-wmi-ddv.c	5817	F: drivers/platform/x86/dell/dell-wmi-ddv.c
5830		5818
5831	DELL WMI SYSMAN DRIVER	5819	DELL WMI DESCRIPTOR DRIVER
5832	M: Prasanth Ksr <prasanth.ksr@dell.com>	5820	L: Dell.Client.Kernel@dell.com
		5821	S: Maintained
		5822	F: drivers/platform/x86/dell/dell-wmi-descriptor.c
		5823
		5824	DELL WMI HARDWARE PRIVACY SUPPORT
		5825	M: Perry Yuan <Perry.Yuan@dell.com>
5833	L: Dell.Client.Kernel@dell.com	5826	L: Dell.Client.Kernel@dell.com
5834	L: platform-driver-x86@vger.kernel.org	5827	L: platform-driver-x86@vger.kernel.org
5835	S: Maintained	5828	S: Maintained
5836	F: Documentation/ABI/testing/sysfs-class-firmware-attributes	5829	F: drivers/platform/x86/dell/dell-wmi-privacy.c
5837	F: drivers/platform/x86/dell/dell-wmi-sysman/
5838		5830
5839	DELL WMI NOTIFICATIONS DRIVER	5831	DELL WMI NOTIFICATIONS DRIVER
5840	M: Matthew Garrett <mjg59@srcf.ucam.org>	5832	M: Matthew Garrett <mjg59@srcf.ucam.org>
@@ -5842,20 +5834,13 @@ M: Pali Rohár <pali@kernel.org> · 1 unmodified line
5842	S: Maintained	5834	S: Maintained
5843	F: drivers/platform/x86/dell/dell-wmi-base.c	5835	F: drivers/platform/x86/dell/dell-wmi-base.c
5844		5836
5845	DELL WMI HARDWARE PRIVACY SUPPORT	5837	DELL WMI SYSMAN DRIVER
5846	M: Perry Yuan <Perry.Yuan@dell.com>	5838	M: Prasanth Ksr <prasanth.ksr@dell.com>
5847	L: Dell.Client.Kernel@dell.com	5839	L: Dell.Client.Kernel@dell.com
5848	L: platform-driver-x86@vger.kernel.org	5840	L: platform-driver-x86@vger.kernel.org
5849	S: Maintained	5841	S: Maintained
5850	F: drivers/platform/x86/dell/dell-wmi-privacy.c	5842	F: Documentation/ABI/testing/sysfs-class-firmware-attributes
5851		5843	F: drivers/platform/x86/dell/dell-wmi-sysman/
5852	DELTA ST MEDIA DRIVER
5853	M: Hugues Fruchet <hugues.fruchet@foss.st.com>
5854	L: linux-media@vger.kernel.org
5855	S: Supported
5856	W: https://linuxtv.org
5857	T: git git://linuxtv.org/media_tree.git
5858	F: drivers/media/platform/st/sti/delta
5859		5844
5860	DELTA AHE-50DC FAN CONTROL MODULE DRIVER	5845	DELTA AHE-50DC FAN CONTROL MODULE DRIVER
5861	M: Zev Weiss <zev@bewilderbeest.net>	5846	M: Zev Weiss <zev@bewilderbeest.net>
@@ -5879,6 +5864,14 @@ F: Documentation/devicetree/bindings/reset/delta,tn48m-reset.yaml · 17 unmodified lines
5879	F: drivers/gpio/gpio-tn48m.c	5864	F: drivers/gpio/gpio-tn48m.c
5880	F: include/dt-bindings/reset/delta,tn48m-reset.h	5865	F: include/dt-bindings/reset/delta,tn48m-reset.h
5881		5866
		5867	DELTA ST MEDIA DRIVER
		5868	M: Hugues Fruchet <hugues.fruchet@foss.st.com>
		5869	L: linux-media@vger.kernel.org
		5870	S: Supported
		5871	W: https://linuxtv.org
		5872	T: git git://linuxtv.org/media_tree.git
		5873	F: drivers/media/platform/st/sti/delta
		5874
5882	DENALI NAND DRIVER	5875	DENALI NAND DRIVER
5883	L: linux-mtd@lists.infradead.org	5876	L: linux-mtd@lists.infradead.org
5884	S: Orphan	5877	S: Orphan
@@ -5891,13 +5884,6 @@ S: Maintained · 6 unmodified lines
5891	F: drivers/dma/dw-edma/	5884	F: drivers/dma/dw-edma/
5892	F: include/linux/dma/edma.h	5885	F: include/linux/dma/edma.h
5893		5886
5894	DESIGNWARE XDATA IP DRIVER
5895	M: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
5896	L: linux-pci@vger.kernel.org
5897	S: Maintained
5898	F: Documentation/misc-devices/dw-xdata-pcie.rst
5899	F: drivers/misc/dw-xdata-pcie.c
5900
5901	DESIGNWARE USB2 DRD IP DRIVER	5887	DESIGNWARE USB2 DRD IP DRIVER
5902	M: Minas Harutyunyan <hminas@synopsys.com>	5888	M: Minas Harutyunyan <hminas@synopsys.com>
5903	L: linux-usb@vger.kernel.org	5889	L: linux-usb@vger.kernel.org
@@ -5911,6 +5897,13 @@ L: linux-usb@vger.kernel.org · 7 unmodified lines
5911	S: Maintained	5897	S: Maintained
5912	F: drivers/usb/dwc3/	5898	F: drivers/usb/dwc3/
5913		5899
		5900	DESIGNWARE XDATA IP DRIVER
		5901	M: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
		5902	L: linux-pci@vger.kernel.org
		5903	S: Maintained
		5904	F: Documentation/misc-devices/dw-xdata-pcie.rst
		5905	F: drivers/misc/dw-xdata-pcie.c
		5906
5914	DEVANTECH SRF ULTRASONIC RANGER IIO DRIVER	5907	DEVANTECH SRF ULTRASONIC RANGER IIO DRIVER
5915	M: Andreas Klinger <ak@it-klinger.de>	5908	M: Andreas Klinger <ak@it-klinger.de>
5916	L: linux-iio@vger.kernel.org	5909	L: linux-iio@vger.kernel.org
@@ -6020,8 +6013,8 @@ F: Documentation/devicetree/bindings/input/da90??-onkey.txt · 103 unmodified lines
6020	F: Documentation/devicetree/bindings/input/dlg,da72??.txt	6013	F: Documentation/devicetree/bindings/input/dlg,da72??.txt
6021	F: Documentation/devicetree/bindings/mfd/da90*.txt	6014	F: Documentation/devicetree/bindings/mfd/da90*.txt
6022	F: Documentation/devicetree/bindings/mfd/da90*.yaml	6015	F: Documentation/devicetree/bindings/mfd/da90*.yaml
6023	F: Documentation/devicetree/bindings/regulator/dlg,da9*.yaml
6024	F: Documentation/devicetree/bindings/regulator/da92*.txt	6016	F: Documentation/devicetree/bindings/regulator/da92*.txt
		6017	F: Documentation/devicetree/bindings/regulator/dlg,da9*.yaml
6025	F: Documentation/devicetree/bindings/regulator/slg51000.txt	6018	F: Documentation/devicetree/bindings/regulator/slg51000.txt
6026	F: Documentation/devicetree/bindings/sound/da[79]*.txt	6019	F: Documentation/devicetree/bindings/sound/da[79]*.txt
6027	F: Documentation/devicetree/bindings/thermal/da90??-thermal.txt	6020	F: Documentation/devicetree/bindings/thermal/da90??-thermal.txt
@@ -6140,6 +6133,12 @@ F: include/linux/dma/ · 112 unmodified lines
6140	F: include/linux/dmaengine.h	6133	F: include/linux/dmaengine.h
6141	F: include/linux/of_dma.h	6134	F: include/linux/of_dma.h
6142		6135
		6136	DMA MAPPING BENCHMARK
		6137	M: Xiang Chen <chenxiang66@hisilicon.com>
		6138	L: iommu@lists.linux.dev
		6139	F: kernel/dma/map_benchmark.c
		6140	F: tools/testing/selftests/dma/
		6141
6143	DMA MAPPING HELPERS	6142	DMA MAPPING HELPERS
6144	M: Christoph Hellwig <hch@lst.de>	6143	M: Christoph Hellwig <hch@lst.de>
6145	M: Marek Szyprowski <m.szyprowski@samsung.com>	6144	M: Marek Szyprowski <m.szyprowski@samsung.com>
@@ -6150,17 +6149,11 @@ W: http://git.infradead.org/users/hch/dma-mapping.git · 4 unmodified lines
6150	T: git git://git.infradead.org/users/hch/dma-mapping.git	6149	T: git git://git.infradead.org/users/hch/dma-mapping.git
6151	F: include/asm-generic/dma-mapping.h	6150	F: include/asm-generic/dma-mapping.h
6152	F: include/linux/dma-direct.h	6151	F: include/linux/dma-direct.h
6153	F: include/linux/dma-mapping.h
6154	F: include/linux/dma-map-ops.h	6152	F: include/linux/dma-map-ops.h
		6153	F: include/linux/dma-mapping.h
6155	F: include/linux/swiotlb.h	6154	F: include/linux/swiotlb.h
6156	F: kernel/dma/	6155	F: kernel/dma/
6157		6156
6158	DMA MAPPING BENCHMARK
6159	M: Xiang Chen <chenxiang66@hisilicon.com>
6160	L: iommu@lists.linux.dev
6161	F: kernel/dma/map_benchmark.c
6162	F: tools/testing/selftests/dma/
6163
6164	DMA-BUF HEAPS FRAMEWORK	6157	DMA-BUF HEAPS FRAMEWORK
6165	M: Sumit Semwal <sumit.semwal@linaro.org>	6158	M: Sumit Semwal <sumit.semwal@linaro.org>
6166	R: Benjamin Gaignard <benjamin.gaignard@collabora.com>	6159	R: Benjamin Gaignard <benjamin.gaignard@collabora.com>
@@ -6350,6 +6343,25 @@ S: Maintained · 183 unmodified lines
6350	F: drivers/soc/ti/smartreflex.c	6343	F: drivers/soc/ti/smartreflex.c
6351	F: include/linux/power/smartreflex.h	6344	F: include/linux/power/smartreflex.h
6352		6345
		6346	DRM ACCEL DRIVERS FOR INTEL VPU
		6347	M: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
		6348	M: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
		6349	L: dri-devel@lists.freedesktop.org
		6350	S: Supported
		6351	T: git git://anongit.freedesktop.org/drm/drm-misc
		6352	F: drivers/accel/ivpu/
		6353	F: include/uapi/drm/ivpu_accel.h
		6354
		6355	DRM COMPUTE ACCELERATORS DRIVERS AND FRAMEWORK
		6356	M: Oded Gabbay <ogabbay@kernel.org>
		6357	L: dri-devel@lists.freedesktop.org
		6358	S: Maintained
		6359	C: irc://irc.oftc.net/dri-devel
		6360	T: git https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/accel.git
		6361	F: Documentation/accel/
		6362	F: drivers/accel/
		6363	F: include/drm/drm_accel.h
		6364
6353	DRM DRIVER FOR ALLWINNER DE2 AND DE3 ENGINE	6365	DRM DRIVER FOR ALLWINNER DE2 AND DE3 ENGINE
6354	M: Maxime Ripard <mripard@kernel.org>	6366	M: Maxime Ripard <mripard@kernel.org>
6355	M: Chen-Yu Tsai <wens@csie.org>	6367	M: Chen-Yu Tsai <wens@csie.org>
@@ -6432,6 +6444,21 @@ S: Maintained · 76 unmodified lines
6432	F: Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml	6444	F: Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml
6433	F: drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c	6445	F: drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
6434		6446
		6447	DRM DRIVER FOR FIRMWARE FRAMEBUFFERS
		6448	M: Thomas Zimmermann <tzimmermann@suse.de>
		6449	M: Javier Martinez Canillas <javierm@redhat.com>
		6450	L: dri-devel@lists.freedesktop.org
		6451	S: Maintained
		6452	T: git git://anongit.freedesktop.org/drm/drm-misc
		6453	F: drivers/gpu/drm/drm_aperture.c
		6454	F: drivers/gpu/drm/tiny/ofdrm.c
		6455	F: drivers/gpu/drm/tiny/simpledrm.c
		6456	F: drivers/video/aperture.c
		6457	F: drivers/video/nomodeset.c
		6458	F: include/drm/drm_aperture.h
		6459	F: include/linux/aperture.h
		6460	F: include/video/nomodeset.h
		6461
6435	DRM DRIVER FOR GENERIC EDP PANELS	6462	DRM DRIVER FOR GENERIC EDP PANELS
6436	R: Douglas Anderson <dianders@chromium.org>	6463	R: Douglas Anderson <dianders@chromium.org>
6437	F: Documentation/devicetree/bindings/display/panel/panel-edp.yaml	6464	F: Documentation/devicetree/bindings/display/panel/panel-edp.yaml
@@ -6466,6 +6493,14 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 28 unmodified lines
6466	F: Documentation/devicetree/bindings/display/himax,hx8357d.txt	6493	F: Documentation/devicetree/bindings/display/himax,hx8357d.txt
6467	F: drivers/gpu/drm/tiny/hx8357d.c	6494	F: drivers/gpu/drm/tiny/hx8357d.c
6468		6495
		6496	DRM DRIVER FOR HYPERV SYNTHETIC VIDEO DEVICE
		6497	M: Deepak Rawat <drawat.floss@gmail.com>
		6498	L: linux-hyperv@vger.kernel.org
		6499	L: dri-devel@lists.freedesktop.org
		6500	S: Maintained
		6501	T: git git://anongit.freedesktop.org/drm/drm-misc
		6502	F: drivers/gpu/drm/hyperv
		6503
6469	DRM DRIVER FOR ILITEK ILI9225 PANELS	6504	DRM DRIVER FOR ILITEK ILI9225 PANELS
6470	M: David Lechner <david@lechnology.com>	6505	M: David Lechner <david@lechnology.com>
6471	S: Maintained	6506	S: Maintained
@@ -6495,11 +6530,11 @@ F: drivers/gpu/drm/logicvc/ · 23 unmodified lines
6495	DRM DRIVER FOR LVDS PANELS	6530	DRM DRIVER FOR LVDS PANELS
6496	M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>	6531	M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6497	L: dri-devel@lists.freedesktop.org	6532	L: dri-devel@lists.freedesktop.org
6498	T: git git://anongit.freedesktop.org/drm/drm-misc
6499	S: Maintained	6533	S: Maintained
6500	F: drivers/gpu/drm/panel/panel-lvds.c	6534	T: git git://anongit.freedesktop.org/drm/drm-misc
6501	F: Documentation/devicetree/bindings/display/lvds.yaml	6535	F: Documentation/devicetree/bindings/display/lvds.yaml
6502	F: Documentation/devicetree/bindings/display/panel/panel-lvds.yaml	6536	F: Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
		6537	F: drivers/gpu/drm/panel/panel-lvds.c
6503		6538
6504	DRM DRIVER FOR MANTIX MLAF057WE51 PANELS	6539	DRM DRIVER FOR MANTIX MLAF057WE51 PANELS
6505	M: Guido Günther <agx@sigxcpu.org>	6540	M: Guido Günther <agx@sigxcpu.org>
@@ -6608,13 +6643,6 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 102 unmodified lines
6608	F: Documentation/devicetree/bindings/display/repaper.txt	6643	F: Documentation/devicetree/bindings/display/repaper.txt
6609	F: drivers/gpu/drm/tiny/repaper.c	6644	F: drivers/gpu/drm/tiny/repaper.c
6610		6645
6611	DRM DRIVER FOR SOLOMON SSD130X OLED DISPLAYS
6612	M: Javier Martinez Canillas <javierm@redhat.com>
6613	S: Maintained
6614	T: git git://anongit.freedesktop.org/drm/drm-misc
6615	F: Documentation/devicetree/bindings/display/solomon,ssd1307fb.yaml
6616	F: drivers/gpu/drm/solomon/ssd130x*
6617
6618	DRM DRIVER FOR QEMU'S CIRRUS DEVICE	6646	DRM DRIVER FOR QEMU'S CIRRUS DEVICE
6619	M: Dave Airlie <airlied@redhat.com>	6647	M: Dave Airlie <airlied@redhat.com>
6620	M: Gerd Hoffmann <kraxel@redhat.com>	6648	M: Gerd Hoffmann <kraxel@redhat.com>
@@ -6663,28 +6691,11 @@ S: Maintained · 42 unmodified lines
6663	F: Documentation/devicetree/bindings/display/panel/samsung,s6d27a1.yaml	6691	F: Documentation/devicetree/bindings/display/panel/samsung,s6d27a1.yaml
6664	F: drivers/gpu/drm/panel/panel-samsung-s6d27a1.c	6692	F: drivers/gpu/drm/panel/panel-samsung-s6d27a1.c
6665		6693
6666	DRM DRIVER FOR SITRONIX ST7703 PANELS	6694	DRM DRIVER FOR SAMSUNG S6D7AA0 PANELS
6667	M: Guido Günther <agx@sigxcpu.org>	6695	M: Artur Weber <aweber.kernel@gmail.com>
6668	R: Purism Kernel Team <kernel@puri.sm>
6669	R: Ondrej Jirman <megous@megous.com>
6670	S: Maintained
6671	F: Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml
6672	F: drivers/gpu/drm/panel/panel-sitronix-st7703.c
6673
6674	DRM DRIVER FOR FIRMWARE FRAMEBUFFERS
6675	M: Thomas Zimmermann <tzimmermann@suse.de>
6676	M: Javier Martinez Canillas <javierm@redhat.com>
6677	L: dri-devel@lists.freedesktop.org
6678	S: Maintained	6696	S: Maintained
6679	T: git git://anongit.freedesktop.org/drm/drm-misc	6697	F: Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml
6680	F: drivers/gpu/drm/drm_aperture.c	6698	F: drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c
6681	F: drivers/gpu/drm/tiny/ofdrm.c
6682	F: drivers/gpu/drm/tiny/simpledrm.c
6683	F: drivers/video/aperture.c
6684	F: drivers/video/nomodeset.c
6685	F: include/drm/drm_aperture.h
6686	F: include/linux/aperture.h
6687	F: include/video/nomodeset.h
6688		6699
6689	DRM DRIVER FOR SITRONIX ST7586 PANELS	6700	DRM DRIVER FOR SITRONIX ST7586 PANELS
6690	M: David Lechner <david@lechnology.com>	6701	M: David Lechner <david@lechnology.com>
@@ -6699,6 +6710,14 @@ S: Maintained · 8 unmodified lines
6699	F: Documentation/devicetree/bindings/display/panel/sitronix,st7701.yaml	6710	F: Documentation/devicetree/bindings/display/panel/sitronix,st7701.yaml
6700	F: drivers/gpu/drm/panel/panel-sitronix-st7701.c	6711	F: drivers/gpu/drm/panel/panel-sitronix-st7701.c
6701		6712
		6713	DRM DRIVER FOR SITRONIX ST7703 PANELS
		6714	M: Guido Günther <agx@sigxcpu.org>
		6715	R: Purism Kernel Team <kernel@puri.sm>
		6716	R: Ondrej Jirman <megous@megous.com>
		6717	S: Maintained
		6718	F: Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml
		6719	F: drivers/gpu/drm/panel/panel-sitronix-st7703.c
		6720
6702	DRM DRIVER FOR SITRONIX ST7735R PANELS	6721	DRM DRIVER FOR SITRONIX ST7735R PANELS
6703	M: David Lechner <david@lechnology.com>	6722	M: David Lechner <david@lechnology.com>
6704	S: Maintained	6723	S: Maintained
@@ -6706,6 +6725,13 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 1 unmodified line
6706	F: Documentation/devicetree/bindings/display/sitronix,st7735r.yaml	6725	F: Documentation/devicetree/bindings/display/sitronix,st7735r.yaml
6707	F: drivers/gpu/drm/tiny/st7735r.c	6726	F: drivers/gpu/drm/tiny/st7735r.c
6708		6727
		6728	DRM DRIVER FOR SOLOMON SSD130X OLED DISPLAYS
		6729	M: Javier Martinez Canillas <javierm@redhat.com>
		6730	S: Maintained
		6731	T: git git://anongit.freedesktop.org/drm/drm-misc
		6732	F: Documentation/devicetree/bindings/display/solomon,ssd1307fb.yaml
		6733	F: drivers/gpu/drm/solomon/ssd130x*
		6734
6709	DRM DRIVER FOR ST-ERICSSON MCDE	6735	DRM DRIVER FOR ST-ERICSSON MCDE
6710	M: Linus Walleij <linus.walleij@linaro.org>	6736	M: Linus Walleij <linus.walleij@linaro.org>
6711	S: Maintained	6737	S: Maintained
@@ -6743,6 +6769,7 @@ F: drivers/gpu/drm/udl/ · 31 unmodified lines
6743	DRM DRIVER FOR VIRTUAL KERNEL MODESETTING (VKMS)	6769	DRM DRIVER FOR VIRTUAL KERNEL MODESETTING (VKMS)
6744	M: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>	6770	M: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
6745	M: Melissa Wen <melissa.srw@gmail.com>	6771	M: Melissa Wen <melissa.srw@gmail.com>
		6772	M: Maíra Canal <mairacanal@riseup.net>
6746	R: Haneen Mohammed <hamohammed.sa@gmail.com>	6773	R: Haneen Mohammed <hamohammed.sa@gmail.com>
6747	R: Daniel Vetter <daniel@ffwll.ch>	6774	R: Daniel Vetter <daniel@ffwll.ch>
6748	L: dri-devel@lists.freedesktop.org	6775	L: dri-devel@lists.freedesktop.org
@@ -6804,25 +6831,6 @@ F: include/drm/drm* · 55 unmodified lines
6804	F: include/linux/vga*	6831	F: include/linux/vga*
6805	F: include/uapi/drm/drm*	6832	F: include/uapi/drm/drm*
6806		6833
6807	DRM COMPUTE ACCELERATORS DRIVERS AND FRAMEWORK
6808	M: Oded Gabbay <ogabbay@kernel.org>
6809	L: dri-devel@lists.freedesktop.org
6810	S: Maintained
6811	C: irc://irc.oftc.net/dri-devel
6812	T: git https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/accel.git
6813	F: Documentation/accel/
6814	F: drivers/accel/
6815	F: include/drm/drm_accel.h
6816
6817	DRM ACCEL DRIVERS FOR INTEL VPU
6818	M: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
6819	M: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
6820	L: dri-devel@lists.freedesktop.org
6821	S: Supported
6822	T: git git://anongit.freedesktop.org/drm/drm-misc
6823	F: drivers/accel/ivpu/
6824	F: include/uapi/drm/ivpu_accel.h
6825
6826	DRM DRIVERS FOR ALLWINNER A10	6834	DRM DRIVERS FOR ALLWINNER A10
6827	M: Maxime Ripard <mripard@kernel.org>	6835	M: Maxime Ripard <mripard@kernel.org>
6828	M: Chen-Yu Tsai <wens@csie.org>	6836	M: Chen-Yu Tsai <wens@csie.org>
@@ -6864,6 +6872,7 @@ S: Maintained · 35 unmodified lines
6864	T: git git://anongit.freedesktop.org/drm/drm-misc	6872	T: git git://anongit.freedesktop.org/drm/drm-misc
6865	F: Documentation/devicetree/bindings/display/bridge/	6873	F: Documentation/devicetree/bindings/display/bridge/
6866	F: drivers/gpu/drm/bridge/	6874	F: drivers/gpu/drm/bridge/
		6875	F: drivers/gpu/drm/drm_bridge.c
6867	F: include/drm/drm_bridge.h	6876	F: include/drm/drm_bridge.h
6868		6877
6869	DRM DRIVERS FOR EXYNOS	6878	DRM DRIVERS FOR EXYNOS
@@ -6926,14 +6935,6 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 56 unmodified lines
6926	F: Documentation/devicetree/bindings/display/hisilicon/	6935	F: Documentation/devicetree/bindings/display/hisilicon/
6927	F: drivers/gpu/drm/hisilicon/	6936	F: drivers/gpu/drm/hisilicon/
6928		6937
6929	DRM DRIVER FOR HYPERV SYNTHETIC VIDEO DEVICE
6930	M: Deepak Rawat <drawat.floss@gmail.com>
6931	L: linux-hyperv@vger.kernel.org
6932	L: dri-devel@lists.freedesktop.org
6933	S: Maintained
6934	T: git git://anongit.freedesktop.org/drm/drm-misc
6935	F: drivers/gpu/drm/hyperv
6936
6937	DRM DRIVERS FOR LIMA	6938	DRM DRIVERS FOR LIMA
6938	M: Qiang Yu <yuq825@gmail.com>	6939	M: Qiang Yu <yuq825@gmail.com>
6939	L: dri-devel@lists.freedesktop.org	6940	L: dri-devel@lists.freedesktop.org
@@ -7085,6 +7086,14 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 145 unmodified lines
7085	F: Documentation/devicetree/bindings/display/xlnx/	7086	F: Documentation/devicetree/bindings/display/xlnx/
7086	F: drivers/gpu/drm/xlnx/	7087	F: drivers/gpu/drm/xlnx/
7087		7088
		7089	DRM GPU SCHEDULER
		7090	M: Luben Tuikov <luben.tuikov@amd.com>
		7091	L: dri-devel@lists.freedesktop.org
		7092	S: Maintained
		7093	T: git git://anongit.freedesktop.org/drm/drm-misc
		7094	F: drivers/gpu/drm/scheduler/
		7095	F: include/drm/gpu_scheduler.h
		7096
7088	DRM PANEL DRIVERS	7097	DRM PANEL DRIVERS
7089	M: Neil Armstrong <neil.armstrong@linaro.org>	7098	M: Neil Armstrong <neil.armstrong@linaro.org>
7090	R: Sam Ravnborg <sam@ravnborg.org>	7099	R: Sam Ravnborg <sam@ravnborg.org>
@@ -7113,14 +7122,6 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 22 unmodified lines
7113	F: drivers/gpu/drm/ttm/	7122	F: drivers/gpu/drm/ttm/
7114	F: include/drm/ttm/	7123	F: include/drm/ttm/
7115		7124
7116	DRM GPU SCHEDULER
7117	M: Luben Tuikov <luben.tuikov@amd.com>
7118	L: dri-devel@lists.freedesktop.org
7119	S: Maintained
7120	T: git git://anongit.freedesktop.org/drm/drm-misc
7121	F: drivers/gpu/drm/scheduler/
7122	F: include/drm/gpu_scheduler.h
7123
7124	DSBR100 USB FM RADIO DRIVER	7125	DSBR100 USB FM RADIO DRIVER
7125	M: Alexey Klimov <klimov.linux@gmail.com>	7126	M: Alexey Klimov <klimov.linux@gmail.com>
7126	L: linux-media@vger.kernel.org	7127	L: linux-media@vger.kernel.org
@@ -7248,10 +7249,10 @@ F: drivers/media/usb/dvb-usb-v2/usb_urb.c · 121 unmodified lines
7248		7249
7249	DYNAMIC DEBUG	7250	DYNAMIC DEBUG
7250	M: Jason Baron <jbaron@akamai.com>	7251	M: Jason Baron <jbaron@akamai.com>
		7252	M: Jim Cromie <jim.cromie@gmail.com>
7251	S: Maintained	7253	S: Maintained
7252	F: include/linux/dynamic_debug.h	7254	F: include/linux/dynamic_debug.h
7253	F: lib/dynamic_debug.c	7255	F: lib/dynamic_debug.c
7254	M: Jim Cromie <jim.cromie@gmail.com>
7255	F: lib/test_dynamic_debug.c	7256	F: lib/test_dynamic_debug.c
7256		7257
7257	DYNAMIC INTERRUPT MODERATION	7258	DYNAMIC INTERRUPT MODERATION
@@ -7261,6 +7262,15 @@ F: Documentation/networking/net_dim.rst · 3 unmodified lines
7261	F: include/linux/dim.h	7262	F: include/linux/dim.h
7262	F: lib/dim/	7263	F: lib/dim/
7263		7264
		7265	DYNAMIC THERMAL POWER MANAGEMENT (DTPM)
		7266	M: Daniel Lezcano <daniel.lezcano@kernel.org>
		7267	L: linux-pm@vger.kernel.org
		7268	S: Supported
		7269	B: https://bugzilla.kernel.org
		7270	T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
		7271	F: drivers/powercap/dtpm*
		7272	F: include/linux/dtpm.h
		7273
7264	DZ DECSTATION DZ11 SERIAL DRIVER	7274	DZ DECSTATION DZ11 SERIAL DRIVER
7265	M: "Maciej W. Rozycki" <macro@orcam.me.uk>	7275	M: "Maciej W. Rozycki" <macro@orcam.me.uk>
7266	S: Maintained	7276	S: Maintained
@@ -7599,22 +7609,22 @@ W: http://www.broadcom.com · 332 unmodified lines
7599	F: drivers/infiniband/hw/ocrdma/	7609	F: drivers/infiniband/hw/ocrdma/
7600	F: include/uapi/rdma/ocrdma-abi.h	7610	F: include/uapi/rdma/ocrdma-abi.h
7601		7611
7602	EMULEX/BROADCOM LPFC FC/FCOE SCSI DRIVER	7612	EMULEX/BROADCOM EFCT FC/FCOE SCSI TARGET DRIVER
7603	M: James Smart <james.smart@broadcom.com>	7613	M: James Smart <james.smart@broadcom.com>
7604	M: Dick Kennedy <dick.kennedy@broadcom.com>	7614	M: Ram Vegesna <ram.vegesna@broadcom.com>
7605	L: linux-scsi@vger.kernel.org	7615	L: linux-scsi@vger.kernel.org
		7616	L: target-devel@vger.kernel.org
7606	S: Supported	7617	S: Supported
7607	W: http://www.broadcom.com	7618	W: http://www.broadcom.com
7608	F: drivers/scsi/lpfc/	7619	F: drivers/scsi/elx/
7609		7620
7610	EMULEX/BROADCOM EFCT FC/FCOE SCSI TARGET DRIVER	7621	EMULEX/BROADCOM LPFC FC/FCOE SCSI DRIVER
7611	M: James Smart <james.smart@broadcom.com>	7622	M: James Smart <james.smart@broadcom.com>
7612	M: Ram Vegesna <ram.vegesna@broadcom.com>	7623	M: Dick Kennedy <dick.kennedy@broadcom.com>
7613	L: linux-scsi@vger.kernel.org	7624	L: linux-scsi@vger.kernel.org
7614	L: target-devel@vger.kernel.org
7615	S: Supported	7625	S: Supported
7616	W: http://www.broadcom.com	7626	W: http://www.broadcom.com
7617	F: drivers/scsi/elx/	7627	F: drivers/scsi/lpfc/
7618		7628
7619	ENE CB710 FLASH CARD READER DRIVER	7629	ENE CB710 FLASH CARD READER DRIVER
7620	M: Michał Mirosław <mirq-linux@rere.qmqm.pl>	7630	M: Michał Mirosław <mirq-linux@rere.qmqm.pl>
@@ -7707,8 +7717,8 @@ F: drivers/net/mdio/of_mdio.c · 86 unmodified lines
7707	F: drivers/net/pcs/	7717	F: drivers/net/pcs/
7708	F: drivers/net/phy/	7718	F: drivers/net/phy/
7709	F: include/dt-bindings/net/qca-ar803x.h	7719	F: include/dt-bindings/net/qca-ar803x.h
7710	F: include/linux/linkmode.h
7711	F: include/linux/mdio.h	7720	F: include/linux/mdio.h
		7721	F: include/linux/linkmode.h
7712	F: include/linux/mdio/*.h	7722	F: include/linux/mdio/*.h
7713	F: include/linux/mii.h	7723	F: include/linux/mii.h
7714	F: include/linux/of_net.h	7724	F: include/linux/of_net.h
@@ -7771,8 +7781,8 @@ M: Mimi Zohar <zohar@linux.ibm.com> · 56 unmodified lines
7771	L: linux-integrity@vger.kernel.org	7781	L: linux-integrity@vger.kernel.org
7772	S: Supported	7782	S: Supported
7773	T: git git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity.git	7783	T: git git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity.git
7774	F: security/integrity/evm/
7775	F: security/integrity/	7784	F: security/integrity/
		7785	F: security/integrity/evm/
7776		7786
7777	EXTENSIBLE FIRMWARE INTERFACE (EFI)	7787	EXTENSIBLE FIRMWARE INTERFACE (EFI)
7778	M: Ard Biesheuvel <ardb@kernel.org>	7788	M: Ard Biesheuvel <ardb@kernel.org>
@@ -7803,8 +7813,8 @@ EXTRA BOOT CONFIG · 24 unmodified lines
7803	M: Masami Hiramatsu <mhiramat@kernel.org>	7813	M: Masami Hiramatsu <mhiramat@kernel.org>
7804	L: linux-kernel@vger.kernel.org	7814	L: linux-kernel@vger.kernel.org
7805	L: linux-trace-kernel@vger.kernel.org	7815	L: linux-trace-kernel@vger.kernel.org
7806	Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
7807	S: Maintained	7816	S: Maintained
		7817	Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
7808	T: git git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git	7818	T: git git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git
7809	F: Documentation/admin-guide/bootconfig.rst	7819	F: Documentation/admin-guide/bootconfig.rst
7810	F: fs/proc/bootconfig.c	7820	F: fs/proc/bootconfig.c
@@ -8091,21 +8101,6 @@ F: Documentation/fpga/ · 280 unmodified lines
8091	F: drivers/fpga/	8101	F: drivers/fpga/
8092	F: include/linux/fpga/	8102	F: include/linux/fpga/
8093		8103
8094	INTEL MAX10 BMC SECURE UPDATES
8095	M: Russ Weight <russell.h.weight@intel.com>
8096	L: linux-fpga@vger.kernel.org
8097	S: Maintained
8098	F: Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
8099	F: drivers/fpga/intel-m10-bmc-sec-update.c
8100
8101	MICROCHIP POLARFIRE FPGA DRIVERS
8102	M: Conor Dooley <conor.dooley@microchip.com>
8103	R: Ivan Bornyakov <i.bornyakov@metrotek.ru>
8104	L: linux-fpga@vger.kernel.org
8105	S: Supported
8106	F: Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
8107	F: drivers/fpga/microchip-spi.c
8108
8109	FPU EMULATOR	8104	FPU EMULATOR
8110	M: Bill Metzenthen <billm@melbpc.org.au>	8105	M: Bill Metzenthen <billm@melbpc.org.au>
8111	S: Maintained	8106	S: Maintained
@@ -8114,9 +8109,9 @@ F: arch/x86/math-emu/ · 2 unmodified lines
8114		8109
8115	FRAMEBUFFER CORE	8110	FRAMEBUFFER CORE
8116	M: Daniel Vetter <daniel@ffwll.ch>	8111	M: Daniel Vetter <daniel@ffwll.ch>
8117	F: drivers/video/fbdev/core/
8118	S: Odd Fixes	8112	S: Odd Fixes
8119	T: git git://anongit.freedesktop.org/drm/drm-misc	8113	T: git git://anongit.freedesktop.org/drm/drm-misc
		8114	F: drivers/video/fbdev/core/
8120		8115
8121	FRAMEBUFFER LAYER	8116	FRAMEBUFFER LAYER
8122	M: Helge Deller <deller@gmx.de>	8117	M: Helge Deller <deller@gmx.de>
@@ -8493,15 +8488,15 @@ M: Masami Hiramatsu <mhiramat@kernel.org> · 370 unmodified lines
8493	R: Mark Rutland <mark.rutland@arm.com>	8488	R: Mark Rutland <mark.rutland@arm.com>
8494	L: linux-kernel@vger.kernel.org	8489	L: linux-kernel@vger.kernel.org
8495	L: linux-trace-kernel@vger.kernel.org	8490	L: linux-trace-kernel@vger.kernel.org
8496	Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
8497	S: Maintained	8491	S: Maintained
		8492	Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
8498	T: git git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git	8493	T: git git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git
8499	F: Documentation/trace/ftrace*	8494	F: Documentation/trace/ftrace*
8500	F: kernel/trace/ftrace*
8501	F: kernel/trace/fgraph.c
8502	F: arch////ftrace*	8495	F: arch////ftrace*
8503	F: arch///ftrace	8496	F: arch///ftrace
8504	F: include/*/ftrace.h	8497	F: include/*/ftrace.h
		8498	F: kernel/trace/fgraph.c
		8499	F: kernel/trace/ftrace*
8505	F: samples/ftrace	8500	F: samples/ftrace
8506		8501
8507	FUNGIBLE ETHERNET DRIVERS	8502	FUNGIBLE ETHERNET DRIVERS
@@ -8542,10 +8537,10 @@ GATEWORKS SYSTEM CONTROLLER (GSC) DRIVER · 34 unmodified lines
8542	M: Tim Harvey <tharvey@gateworks.com>	8537	M: Tim Harvey <tharvey@gateworks.com>
8543	S: Maintained	8538	S: Maintained
8544	F: Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml	8539	F: Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml
8545	F: drivers/mfd/gateworks-gsc.c
8546	F: include/linux/mfd/gsc.h
8547	F: Documentation/hwmon/gsc-hwmon.rst	8540	F: Documentation/hwmon/gsc-hwmon.rst
8548	F: drivers/hwmon/gsc-hwmon.c	8541	F: drivers/hwmon/gsc-hwmon.c
		8542	F: drivers/mfd/gateworks-gsc.c
		8543	F: include/linux/mfd/gsc.h
8549	F: include/linux/platform_data/gsc_hwmon.h	8544	F: include/linux/platform_data/gsc_hwmon.h
8550		8545
8551	GCC PLUGINS	8546	GCC PLUGINS
@@ -8673,8 +8668,8 @@ R: Andy Shevchenko <andy@kernel.org> · 121 unmodified lines
8673	S: Maintained	8668	S: Maintained
8674	F: lib/string.c	8669	F: lib/string.c
8675	F: lib/string_helpers.c	8670	F: lib/string_helpers.c
8676	F: lib/test_string.c
8677	F: lib/test-string_helpers.c	8671	F: lib/test-string_helpers.c
		8672	F: lib/test_string.c
8678		8673
8679	GENERIC UIO DRIVER FOR PCI DEVICES	8674	GENERIC UIO DRIVER FOR PCI DEVICES
8680	M: "Michael S. Tsirkin" <mst@redhat.com>	8675	M: "Michael S. Tsirkin" <mst@redhat.com>
@@ -9157,12 +9152,11 @@ L: linux-input@vger.kernel.org · 476 unmodified lines
9157	S: Maintained	9152	S: Maintained
9158	F: drivers/hid/hid-logitech-*	9153	F: drivers/hid/hid-logitech-*
9159		9154
9160	HID++ LOGITECH DRIVERS	9155	HID PHOENIX RC FLIGHT CONTROLLER
9161	R: Filipe Laíns <lains@riseup.net>	9156	M: Marcus Folkesson <marcus.folkesson@gmail.com>
9162	R: Bastien Nocera <hadess@hadess.net>
9163	L: linux-input@vger.kernel.org	9157	L: linux-input@vger.kernel.org
9164	S: Maintained	9158	S: Maintained
9165	F: drivers/hid/hid-logitech-hidpp.c	9159	F: drivers/hid/hid-pxrc.c
9166		9160
9167	HID PLAYSTATION DRIVER	9161	HID PLAYSTATION DRIVER
9168	M: Roderick Colenbrander <roderick.colenbrander@sony.com>	9162	M: Roderick Colenbrander <roderick.colenbrander@sony.com>
@@ -9170,12 +9164,6 @@ L: linux-input@vger.kernel.org · 1 unmodified line
9170	S: Supported	9164	S: Supported
9171	F: drivers/hid/hid-playstation.c	9165	F: drivers/hid/hid-playstation.c
9172		9166
9173	HID PHOENIX RC FLIGHT CONTROLLER
9174	M: Marcus Folkesson <marcus.folkesson@gmail.com>
9175	L: linux-input@vger.kernel.org
9176	S: Maintained
9177	F: drivers/hid/hid-pxrc.c
9178
9179	HID SENSOR HUB DRIVERS	9167	HID SENSOR HUB DRIVERS
9180	M: Jiri Kosina <jikos@kernel.org>	9168	M: Jiri Kosina <jikos@kernel.org>
9181	M: Jonathan Cameron <jic23@kernel.org>	9169	M: Jonathan Cameron <jic23@kernel.org>
@@ -9202,6 +9190,13 @@ S: Maintained · 20 unmodified lines
9202	F: drivers/hid/wacom.h	9190	F: drivers/hid/wacom.h
9203	F: drivers/hid/wacom_*	9191	F: drivers/hid/wacom_*
9204		9192
		9193	HID++ LOGITECH DRIVERS
		9194	R: Filipe Laíns <lains@riseup.net>
		9195	R: Bastien Nocera <hadess@hadess.net>
		9196	L: linux-input@vger.kernel.org
		9197	S: Maintained
		9198	F: drivers/hid/hid-logitech-hidpp.c
		9199
9205	HIGH-RESOLUTION TIMERS, CLOCKEVENTS	9200	HIGH-RESOLUTION TIMERS, CLOCKEVENTS
9206	M: Thomas Gleixner <tglx@linutronix.de>	9201	M: Thomas Gleixner <tglx@linutronix.de>
9207	L: linux-kernel@vger.kernel.org	9202	L: linux-kernel@vger.kernel.org
@@ -9226,6 +9221,12 @@ W: http://www.highpoint-tech.com · 18 unmodified lines
9226	F: Documentation/scsi/hptiop.rst	9221	F: Documentation/scsi/hptiop.rst
9227	F: drivers/scsi/hptiop.c	9222	F: drivers/scsi/hptiop.c
9228		9223
		9224	HIKEY960 ONBOARD USB GPIO HUB DRIVER
		9225	M: John Stultz <jstultz@google.com>
		9226	L: linux-kernel@vger.kernel.org
		9227	S: Maintained
		9228	F: drivers/misc/hisi_hikey_usb.c
		9229
9229	HIMAX HX83112B TOUCHSCREEN SUPPORT	9230	HIMAX HX83112B TOUCHSCREEN SUPPORT
9230	M: Job Noorman <job@noorman.info>	9231	M: Job Noorman <job@noorman.info>
9231	L: linux-input@vger.kernel.org	9232	L: linux-input@vger.kernel.org
@@ -9274,6 +9275,12 @@ F: drivers/crypto/hisilicon/hpre/hpre.h · 42 unmodified lines
9274	F: drivers/crypto/hisilicon/hpre/hpre_crypto.c	9275	F: drivers/crypto/hisilicon/hpre/hpre_crypto.c
9275	F: drivers/crypto/hisilicon/hpre/hpre_main.c	9276	F: drivers/crypto/hisilicon/hpre/hpre_main.c
9276		9277
		9278	HISILICON HNS3 PMU DRIVER
		9279	M: Guangbin Huang <huangguangbin2@huawei.com>
		9280	S: Supported
		9281	F: Documentation/admin-guide/perf/hns3-pmu.rst
		9282	F: drivers/perf/hisilicon/hns3_pmu.c
		9283
9277	HISILICON I2C CONTROLLER DRIVER	9284	HISILICON I2C CONTROLLER DRIVER
9278	M: Yicong Yang <yangyicong@hisilicon.com>	9285	M: Yicong Yang <yangyicong@hisilicon.com>
9279	L: linux-i2c@vger.kernel.org	9286	L: linux-i2c@vger.kernel.org
@@ -9306,12 +9313,6 @@ W: http://www.hisilicon.com · 26 unmodified lines
9306	F: Documentation/devicetree/bindings/net/hisilicon*.txt	9313	F: Documentation/devicetree/bindings/net/hisilicon*.txt
9307	F: drivers/net/ethernet/hisilicon/	9314	F: drivers/net/ethernet/hisilicon/
9308		9315
9309	HIKEY960 ONBOARD USB GPIO HUB DRIVER
9310	M: John Stultz <jstultz@google.com>
9311	L: linux-kernel@vger.kernel.org
9312	S: Maintained
9313	F: drivers/misc/hisi_hikey_usb.c
9314
9315	HISILICON PMU DRIVER	9316	HISILICON PMU DRIVER
9316	M: Shaokun Zhang <zhangshaokun@hisilicon.com>	9317	M: Shaokun Zhang <zhangshaokun@hisilicon.com>
9317	M: Jonathan Cameron <jonathan.cameron@huawei.com>	9318	M: Jonathan Cameron <jonathan.cameron@huawei.com>
@@ -9321,12 +9322,6 @@ F: Documentation/admin-guide/perf/hisi-pcie-pmu.rst · 3 unmodified lines
9321	F: Documentation/admin-guide/perf/hisi-pmu.rst	9322	F: Documentation/admin-guide/perf/hisi-pmu.rst
9322	F: drivers/perf/hisilicon	9323	F: drivers/perf/hisilicon
9323		9324
9324	HISILICON HNS3 PMU DRIVER
9325	M: Guangbin Huang <huangguangbin2@huawei.com>
9326	S: Supported
9327	F: Documentation/admin-guide/perf/hns3-pmu.rst
9328	F: drivers/perf/hisilicon/hns3_pmu.c
9329
9330	HISILICON PTT DRIVER	9325	HISILICON PTT DRIVER
9331	M: Yicong Yang <yangyicong@hisilicon.com>	9326	M: Yicong Yang <yangyicong@hisilicon.com>
9332	M: Jonathan Cameron <jonathan.cameron@huawei.com>	9327	M: Jonathan Cameron <jonathan.cameron@huawei.com>
@@ -9350,14 +9345,6 @@ F: drivers/crypto/hisilicon/qm.c · 17 unmodified lines
9350	F: drivers/crypto/hisilicon/sgl.c	9345	F: drivers/crypto/hisilicon/sgl.c
9351	F: include/linux/hisi_acc_qm.h	9346	F: include/linux/hisi_acc_qm.h
9352		9347
9353	HISILICON ZIP Controller DRIVER
9354	M: Yang Shen <shenyang39@huawei.com>
9355	M: Zhou Wang <wangzhou1@hisilicon.com>
9356	L: linux-crypto@vger.kernel.org
9357	S: Maintained
9358	F: Documentation/ABI/testing/debugfs-hisi-zip
9359	F: drivers/crypto/hisilicon/zip/
9360
9361	HISILICON ROCE DRIVER	9348	HISILICON ROCE DRIVER
9362	M: Haoyue Xu <xuhaoyue1@hisilicon.com>	9349	M: Haoyue Xu <xuhaoyue1@hisilicon.com>
9363	M: Wenpeng Liang <liangwenpeng@huawei.com>	9350	M: Wenpeng Liang <liangwenpeng@huawei.com>
@@ -9416,6 +9403,14 @@ S: Maintained · 52 unmodified lines
9416	W: http://www.hisilicon.com	9403	W: http://www.hisilicon.com
9417	F: drivers/spi/spi-hisi-sfc-v3xx.c	9404	F: drivers/spi/spi-hisi-sfc-v3xx.c
9418		9405
		9406	HISILICON ZIP Controller DRIVER
		9407	M: Yang Shen <shenyang39@huawei.com>
		9408	M: Zhou Wang <wangzhou1@hisilicon.com>
		9409	L: linux-crypto@vger.kernel.org
		9410	S: Maintained
		9411	F: Documentation/ABI/testing/debugfs-hisi-zip
		9412	F: drivers/crypto/hisilicon/zip/
		9413
9419	HMM - Heterogeneous Memory Management	9414	HMM - Heterogeneous Memory Management
9420	M: Jérôme Glisse <jglisse@redhat.com>	9415	M: Jérôme Glisse <jglisse@redhat.com>
9421	L: linux-mm@kvack.org	9416	L: linux-mm@kvack.org
@@ -9492,9 +9487,9 @@ F: drivers/input/touchscreen/htcpen.c · 70 unmodified lines
9492	HTE SUBSYSTEM	9487	HTE SUBSYSTEM
9493	M: Dipen Patel <dipenp@nvidia.com>	9488	M: Dipen Patel <dipenp@nvidia.com>
9494	L: timestamp@lists.linux.dev	9489	L: timestamp@lists.linux.dev
9495	T: git git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git
9496	Q: https://patchwork.kernel.org/project/timestamp/list/
9497	S: Maintained	9490	S: Maintained
		9491	Q: https://patchwork.kernel.org/project/timestamp/list/
		9492	T: git git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git
9498	F: Documentation/devicetree/bindings/timestamp/	9493	F: Documentation/devicetree/bindings/timestamp/
9499	F: Documentation/driver-api/hte/	9494	F: Documentation/driver-api/hte/
9500	F: drivers/hte/	9495	F: drivers/hte/
@@ -9589,8 +9584,8 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git · 88 unmodified lines
9589	F: Documentation/ABI/stable/sysfs-bus-vmbus	9584	F: Documentation/ABI/stable/sysfs-bus-vmbus
9590	F: Documentation/ABI/testing/debugfs-hyperv	9585	F: Documentation/ABI/testing/debugfs-hyperv
9591	F: Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml	9586	F: Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml
9592	F: Documentation/virt/hyperv
9593	F: Documentation/networking/device_drivers/ethernet/microsoft/netvsc.rst	9587	F: Documentation/networking/device_drivers/ethernet/microsoft/netvsc.rst
		9588	F: Documentation/virt/hyperv
9594	F: arch/arm64/hyperv	9589	F: arch/arm64/hyperv
9595	F: arch/arm64/include/asm/hyperv-tlfs.h	9590	F: arch/arm64/include/asm/hyperv-tlfs.h
9596	F: arch/arm64/include/asm/mshyperv.h	9591	F: arch/arm64/include/asm/mshyperv.h
@@ -9772,6 +9767,12 @@ L: linux-i2c@vger.kernel.org · 175 unmodified lines
9772	S: Maintained	9767	S: Maintained
9773	F: drivers/i2c/i2c-stub.c	9768	F: drivers/i2c/i2c-stub.c
9774		9769
		9770	I3C DRIVER FOR ASPEED AST2600
		9771	M: Jeremy Kerr <jk@codeconstruct.com.au>
		9772	S: Maintained
		9773	F: Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml
		9774	F: drivers/i3c/master/ast2600-i3c-master.c
		9775
9775	I3C DRIVER FOR CADENCE I3C MASTER IP	9776	I3C DRIVER FOR CADENCE I3C MASTER IP
9776	M: Przemysław Gaj <pgaj@cadence.com>	9777	M: Przemysław Gaj <pgaj@cadence.com>
9777	S: Maintained	9778	S: Maintained
@@ -9783,12 +9784,6 @@ S: Orphan · 5 unmodified lines
9783	F: Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml	9784	F: Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
9784	F: drivers/i3c/master/dw*	9785	F: drivers/i3c/master/dw*
9785		9786
9786	I3C DRIVER FOR ASPEED AST2600
9787	M: Jeremy Kerr <jk@codeconstruct.com.au>
9788	S: Maintained
9789	F: Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml
9790	F: drivers/i3c/master/ast2600-i3c-master.c
9791
9792	I3C SUBSYSTEM	9787	I3C SUBSYSTEM
9793	M: Alexandre Belloni <alexandre.belloni@bootlin.com>	9788	M: Alexandre Belloni <alexandre.belloni@bootlin.com>
9794	L: linux-i3c@lists.infradead.org (moderated for non-subscribers)	9789	L: linux-i3c@lists.infradead.org (moderated for non-subscribers)
@@ -9867,6 +9862,11 @@ L: netdev@vger.kernel.org · 72 unmodified lines
9867	S: Supported	9862	S: Supported
9868	F: drivers/net/ethernet/ibm/ibmvnic.*	9863	F: drivers/net/ethernet/ibm/ibmvnic.*
9869		9864
		9865	IBM Power VFIO Support
		9866	M: Timothy Pearson <tpearson@raptorengineering.com>
		9867	S: Supported
		9868	F: drivers/vfio/vfio_iommu_spapr_tce.c
		9869
9870	IBM Power Virtual Ethernet Device Driver	9870	IBM Power Virtual Ethernet Device Driver
9871	M: Nick Child <nnac123@linux.ibm.com>	9871	M: Nick Child <nnac123@linux.ibm.com>
9872	L: netdev@vger.kernel.org	9872	L: netdev@vger.kernel.org
@@ -9912,11 +9912,6 @@ F: drivers/crypto/vmx/ghash* · 39 unmodified lines
9912	F: drivers/crypto/vmx/ppc-xlate.pl	9912	F: drivers/crypto/vmx/ppc-xlate.pl
9913	F: drivers/crypto/vmx/vmx.c	9913	F: drivers/crypto/vmx/vmx.c
9914		9914
9915	IBM Power VFIO Support
9916	M: Timothy Pearson <tpearson@raptorengineering.com>
9917	S: Supported
9918	F: drivers/vfio/vfio_iommu_spapr_tce.c
9919
9920	IBM ServeRAID RAID DRIVER	9915	IBM ServeRAID RAID DRIVER
9921	S: Orphan	9916	S: Orphan
9922	F: drivers/scsi/ips.*	9917	F: drivers/scsi/ips.*
@@ -9984,6 +9979,10 @@ F: include/net/nl802154.h · 61 unmodified lines
9984	F: net/ieee802154/	9979	F: net/ieee802154/
9985	F: net/mac802154/	9980	F: net/mac802154/
9986		9981
		9982	IFCVF VIRTIO DATA PATH ACCELERATOR
		9983	R: Zhu Lingshan <lingshan.zhu@intel.com>
		9984	F: drivers/vdpa/ifcvf/
		9985
9987	IFE PROTOCOL	9986	IFE PROTOCOL
9988	M: Yotam Gigi <yotam.gi@gmail.com>	9987	M: Yotam Gigi <yotam.gi@gmail.com>
9989	M: Jamal Hadi Salim <jhs@mojatatu.com>	9988	M: Jamal Hadi Salim <jhs@mojatatu.com>
@@ -10248,8 +10247,8 @@ M: Dmitry Kasatkin <dmitry.kasatkin@gmail.com> · 258 unmodified lines
10248	L: linux-integrity@vger.kernel.org	10247	L: linux-integrity@vger.kernel.org
10249	S: Supported	10248	S: Supported
10250	T: git git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity.git	10249	T: git git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity.git
10251	F: security/integrity/ima/
10252	F: security/integrity/	10250	F: security/integrity/
		10251	F: security/integrity/ima/
10253		10252
10254	INTEL 810/815 FRAMEBUFFER DRIVER	10253	INTEL 810/815 FRAMEBUFFER DRIVER
10255	M: Antonino Daplas <adaplas@gmail.com>	10254	M: Antonino Daplas <adaplas@gmail.com>
@@ -10403,14 +10402,6 @@ S: Supported · 147 unmodified lines
10403	Q: https://patchwork.kernel.org/project/linux-dmaengine/list/	10402	Q: https://patchwork.kernel.org/project/linux-dmaengine/list/
10404	F: drivers/dma/ioat*	10403	F: drivers/dma/ioat*
10405		10404
10406	INTEL IDXD DRIVER
10407	M: Fenghua Yu <fenghua.yu@intel.com>
10408	M: Dave Jiang <dave.jiang@intel.com>
10409	L: dmaengine@vger.kernel.org
10410	S: Supported
10411	F: drivers/dma/idxd/*
10412	F: include/uapi/linux/idxd.h
10413
10414	INTEL IDLE DRIVER	10405	INTEL IDLE DRIVER
10415	M: Jacob Pan <jacob.jun.pan@linux.intel.com>	10406	M: Jacob Pan <jacob.jun.pan@linux.intel.com>
10416	M: Len Brown <lenb@kernel.org>	10407	M: Len Brown <lenb@kernel.org>
@@ -10420,6 +10411,14 @@ B: https://bugzilla.kernel.org · 3 unmodified lines
10420	T: git git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux.git	10411	T: git git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux.git
10421	F: drivers/idle/intel_idle.c	10412	F: drivers/idle/intel_idle.c
10422		10413
		10414	INTEL IDXD DRIVER
		10415	M: Fenghua Yu <fenghua.yu@intel.com>
		10416	M: Dave Jiang <dave.jiang@intel.com>
		10417	L: dmaengine@vger.kernel.org
		10418	S: Supported
		10419	F: drivers/dma/idxd/*
		10420	F: include/uapi/linux/idxd.h
		10421
10423	INTEL IN FIELD SCAN (IFS) DEVICE	10422	INTEL IN FIELD SCAN (IFS) DEVICE
10424	M: Jithu Joseph <jithu.joseph@intel.com>	10423	M: Jithu Joseph <jithu.joseph@intel.com>
10425	R: Ashok Raj <ashok.raj@intel.com>	10424	R: Ashok Raj <ashok.raj@intel.com>
@@ -10466,18 +10465,18 @@ F: Documentation/admin-guide/media/ipu3_rcb.svg · 40 unmodified lines
10466	F: Documentation/userspace-api/media/v4l/pixfmt-meta-intel-ipu3.rst	10465	F: Documentation/userspace-api/media/v4l/pixfmt-meta-intel-ipu3.rst
10467	F: drivers/staging/media/ipu3/	10466	F: drivers/staging/media/ipu3/
10468		10467
10469	INTEL IXP4XX CRYPTO SUPPORT
10470	M: Corentin Labbe <clabbe@baylibre.com>
10471	L: linux-crypto@vger.kernel.org
10472	S: Maintained
10473	F: drivers/crypto/intel/ixp4xx/ixp4xx_crypto.c
10474
10475	INTEL ISHTP ECLITE DRIVER	10468	INTEL ISHTP ECLITE DRIVER
10476	M: Sumesh K Naduvalath <sumesh.k.naduvalath@intel.com>	10469	M: Sumesh K Naduvalath <sumesh.k.naduvalath@intel.com>
10477	L: platform-driver-x86@vger.kernel.org	10470	L: platform-driver-x86@vger.kernel.org
10478	S: Supported	10471	S: Supported
10479	F: drivers/platform/x86/intel/ishtp_eclite.c	10472	F: drivers/platform/x86/intel/ishtp_eclite.c
10480		10473
		10474	INTEL IXP4XX CRYPTO SUPPORT
		10475	M: Corentin Labbe <clabbe@baylibre.com>
		10476	L: linux-crypto@vger.kernel.org
		10477	S: Maintained
		10478	F: drivers/crypto/intel/ixp4xx/ixp4xx_crypto.c
		10479
10481	INTEL IXP4XX QMGR, NPE, ETHERNET and HSS SUPPORT	10480	INTEL IXP4XX QMGR, NPE, ETHERNET and HSS SUPPORT
10482	M: Krzysztof Halasa <khalasa@piap.pl>	10481	M: Krzysztof Halasa <khalasa@piap.pl>
10483	S: Maintained	10482	S: Maintained
@@ -10556,6 +10555,13 @@ F: drivers/hwmon/intel-m10-bmc-hwmon.c · 72 unmodified lines
10556	F: drivers/mfd/intel-m10-bmc*	10555	F: drivers/mfd/intel-m10-bmc*
10557	F: include/linux/mfd/intel-m10-bmc.h	10556	F: include/linux/mfd/intel-m10-bmc.h
10558		10557
		10558	INTEL MAX10 BMC SECURE UPDATES
		10559	M: Russ Weight <russell.h.weight@intel.com>
		10560	L: linux-fpga@vger.kernel.org
		10561	S: Maintained
		10562	F: Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
		10563	F: drivers/fpga/intel-m10-bmc-sec-update.c
		10564
10559	INTEL P-Unit IPC DRIVER	10565	INTEL P-Unit IPC DRIVER
10560	M: Zha Qipeng <qipeng.zha@intel.com>	10566	M: Zha Qipeng <qipeng.zha@intel.com>
10561	L: platform-driver-x86@vger.kernel.org	10567	L: platform-driver-x86@vger.kernel.org
@@ -10603,6 +10609,13 @@ L: linux-pm@vger.kernel.org · 41 unmodified lines
10603	S: Supported	10609	S: Supported
10604	F: drivers/cpufreq/intel_pstate.c	10610	F: drivers/cpufreq/intel_pstate.c
10605		10611
		10612	INTEL PTP DFL ToD DRIVER
		10613	M: Tianfei Zhang <tianfei.zhang@intel.com>
		10614	L: linux-fpga@vger.kernel.org
		10615	L: netdev@vger.kernel.org
		10616	S: Maintained
		10617	F: drivers/ptp/ptp_dfl_tod.c
		10618
10606	INTEL QUADRATURE ENCODER PERIPHERAL DRIVER	10619	INTEL QUADRATURE ENCODER PERIPHERAL DRIVER
10607	M: Jarkko Nikula <jarkko.nikula@linux.intel.com>	10620	M: Jarkko Nikula <jarkko.nikula@linux.intel.com>
10608	L: linux-iio@vger.kernel.org	10621	L: linux-iio@vger.kernel.org
@@ -10621,6 +10634,21 @@ F: drivers/platform/x86/intel/sdsi.c · 12 unmodified lines
10621	F: tools/arch/x86/intel_sdsi/	10634	F: tools/arch/x86/intel_sdsi/
10622	F: tools/testing/selftests/drivers/sdsi/	10635	F: tools/testing/selftests/drivers/sdsi/
10623		10636
		10637	INTEL SGX
		10638	M: Jarkko Sakkinen <jarkko@kernel.org>
		10639	R: Dave Hansen <dave.hansen@linux.intel.com>
		10640	L: linux-sgx@vger.kernel.org
		10641	S: Supported
		10642	Q: https://patchwork.kernel.org/project/intel-sgx/list/
		10643	T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/sgx
		10644	F: Documentation/arch/x86/sgx.rst
		10645	F: arch/x86/entry/vdso/vsgx.S
		10646	F: arch/x86/include/asm/sgx.h
		10647	F: arch/x86/include/uapi/asm/sgx.h
		10648	F: arch/x86/kernel/cpu/sgx/*
		10649	F: tools/testing/selftests/sgx/*
		10650	K: \bSGX_
		10651
10624	INTEL SKYLAKE INT3472 ACPI DEVICE DRIVER	10652	INTEL SKYLAKE INT3472 ACPI DEVICE DRIVER
10625	M: Daniel Scally <djrscally@gmail.com>	10653	M: Daniel Scally <djrscally@gmail.com>
10626	S: Maintained	10654	S: Maintained
@@ -10638,13 +10666,13 @@ INTEL STRATIX10 FIRMWARE DRIVERS · 11 unmodified lines
10638	M: Dinh Nguyen <dinguyen@kernel.org>	10666	M: Dinh Nguyen <dinguyen@kernel.org>
10639	L: linux-kernel@vger.kernel.org	10667	L: linux-kernel@vger.kernel.org
10640	S: Maintained	10668	S: Maintained
		10669	T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git
10641	F: Documentation/ABI/testing/sysfs-devices-platform-stratix10-rsu	10670	F: Documentation/ABI/testing/sysfs-devices-platform-stratix10-rsu
10642	F: Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt	10671	F: Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt
10643	F: drivers/firmware/stratix10-rsu.c	10672	F: drivers/firmware/stratix10-rsu.c
10644	F: drivers/firmware/stratix10-svc.c	10673	F: drivers/firmware/stratix10-svc.c
10645	F: include/linux/firmware/intel/stratix10-smc.h	10674	F: include/linux/firmware/intel/stratix10-smc.h
10646	F: include/linux/firmware/intel/stratix10-svc-client.h	10675	F: include/linux/firmware/intel/stratix10-svc-client.h
10647	T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git
10648		10676
10649	INTEL TELEMETRY DRIVER	10677	INTEL TELEMETRY DRIVER
10650	M: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>	10678	M: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
@@ -10729,21 +10757,6 @@ F: Documentation/arch/x86/intel_txt.rst · 78 unmodified lines
10729	F: arch/x86/kernel/tboot.c	10757	F: arch/x86/kernel/tboot.c
10730	F: include/linux/tboot.h	10758	F: include/linux/tboot.h
10731		10759
10732	INTEL SGX
10733	M: Jarkko Sakkinen <jarkko@kernel.org>
10734	R: Dave Hansen <dave.hansen@linux.intel.com>
10735	L: linux-sgx@vger.kernel.org
10736	S: Supported
10737	Q: https://patchwork.kernel.org/project/intel-sgx/list/
10738	T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/sgx
10739	F: Documentation/arch/x86/sgx.rst
10740	F: arch/x86/entry/vdso/vsgx.S
10741	F: arch/x86/include/asm/sgx.h
10742	F: arch/x86/include/uapi/asm/sgx.h
10743	F: arch/x86/kernel/cpu/sgx/*
10744	F: tools/testing/selftests/sgx/*
10745	K: \bSGX_
10746
10747	INTERCONNECT API	10760	INTERCONNECT API
10748	M: Georgi Djakov <djakov@kernel.org>	10761	M: Georgi Djakov <djakov@kernel.org>
10749	L: linux-pm@vger.kernel.org	10762	L: linux-pm@vger.kernel.org
@@ -10812,18 +10825,6 @@ F: drivers/iommu/dma-iommu.h · 62 unmodified lines
10812	F: drivers/iommu/iova.c	10825	F: drivers/iommu/iova.c
10813	F: include/linux/iova.h	10826	F: include/linux/iova.h
10814		10827
10815	IOMMUFD
10816	M: Jason Gunthorpe <jgg@nvidia.com>
10817	M: Kevin Tian <kevin.tian@intel.com>
10818	L: iommu@lists.linux.dev
10819	S: Maintained
10820	T: git git://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd.git
10821	F: Documentation/userspace-api/iommufd.rst
10822	F: drivers/iommu/iommufd/
10823	F: include/linux/iommufd.h
10824	F: include/uapi/linux/iommufd.h
10825	F: tools/testing/selftests/iommu/
10826
10827	IOMMU SUBSYSTEM	10828	IOMMU SUBSYSTEM
10828	M: Joerg Roedel <joro@8bytes.org>	10829	M: Joerg Roedel <joro@8bytes.org>
10829	M: Will Deacon <will@kernel.org>	10830	M: Will Deacon <will@kernel.org>
@@ -10839,6 +10840,18 @@ F: include/linux/iova.h · 9 unmodified lines
10839	F: include/linux/of_iommu.h	10840	F: include/linux/of_iommu.h
10840	F: include/uapi/linux/iommu.h	10841	F: include/uapi/linux/iommu.h
10841		10842
		10843	IOMMUFD
		10844	M: Jason Gunthorpe <jgg@nvidia.com>
		10845	M: Kevin Tian <kevin.tian@intel.com>
		10846	L: iommu@lists.linux.dev
		10847	S: Maintained
		10848	T: git git://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd.git
		10849	F: Documentation/userspace-api/iommufd.rst
		10850	F: drivers/iommu/iommufd/
		10851	F: include/linux/iommufd.h
		10852	F: include/uapi/linux/iommufd.h
		10853	F: tools/testing/selftests/iommu/
		10854
10842	IOSYS-MAP HELPERS	10855	IOSYS-MAP HELPERS
10843	M: Thomas Zimmermann <tzimmermann@suse.de>	10856	M: Thomas Zimmermann <tzimmermann@suse.de>
10844	L: dri-devel@lists.freedesktop.org	10857	L: dri-devel@lists.freedesktop.org
@@ -10853,11 +10866,11 @@ L: io-uring@vger.kernel.org · 8 unmodified lines
10853	S: Maintained	10866	S: Maintained
10854	T: git git://git.kernel.dk/linux-block	10867	T: git git://git.kernel.dk/linux-block
10855	T: git git://git.kernel.dk/liburing	10868	T: git git://git.kernel.dk/liburing
10856	F: io_uring/
10857	F: include/linux/io_uring.h	10869	F: include/linux/io_uring.h
10858	F: include/linux/io_uring_types.h	10870	F: include/linux/io_uring_types.h
10859	F: include/trace/events/io_uring.h	10871	F: include/trace/events/io_uring.h
10860	F: include/uapi/linux/io_uring.h	10872	F: include/uapi/linux/io_uring.h
		10873	F: io_uring/
10861	F: tools/io_uring/	10874	F: tools/io_uring/
10862		10875
10863	IPMI SUBSYSTEM	10876	IPMI SUBSYSTEM
@@ -10866,8 +10879,8 @@ L: openipmi-developer@lists.sourceforge.net (moderated for non-subscribers) · 2 unmodified lines
10866	S: Supported	10879	S: Supported
10867	W: http://openipmi.sourceforge.net/	10880	W: http://openipmi.sourceforge.net/
10868	T: git https://github.com/cminyard/linux-ipmi.git for-next	10881	T: git https://github.com/cminyard/linux-ipmi.git for-next
10869	F: Documentation/driver-api/ipmi.rst
10870	F: Documentation/devicetree/bindings/ipmi/	10882	F: Documentation/devicetree/bindings/ipmi/
		10883	F: Documentation/driver-api/ipmi.rst
10871	F: drivers/char/ipmi/	10884	F: drivers/char/ipmi/
10872	F: include/linux/ipmi*	10885	F: include/linux/ipmi*
10873	F: include/uapi/linux/ipmi*	10886	F: include/uapi/linux/ipmi*
@@ -10919,8 +10932,8 @@ M: Thomas Gleixner <tglx@linutronix.de> · 45 unmodified lines
10919	L: linux-kernel@vger.kernel.org	10932	L: linux-kernel@vger.kernel.org
10920	S: Maintained	10933	S: Maintained
10921	T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core	10934	T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
10922	F: kernel/irq/
10923	F: include/linux/group_cpus.h	10935	F: include/linux/group_cpus.h
		10936	F: kernel/irq/
10924	F: lib/group_cpus.c	10937	F: lib/group_cpus.c
10925		10938
10926	IRQCHIP DRIVERS	10939	IRQCHIP DRIVERS
@@ -11258,6 +11271,7 @@ L: linux-nfs@vger.kernel.org · 331 unmodified lines
11258	S: Supported	11271	S: Supported
11259	W: http://nfs.sourceforge.net/	11272	W: http://nfs.sourceforge.net/
11260	T: git git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux.git	11273	T: git git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux.git
		11274	F: Documentation/filesystems/nfs/
11261	F: fs/exportfs/	11275	F: fs/exportfs/
11262	F: fs/lockd/	11276	F: fs/lockd/
11263	F: fs/nfs_common/	11277	F: fs/nfs_common/
@@ -11273,7 +11287,6 @@ F: include/trace/misc/sunrpc.h · 9 unmodified lines
11273	F: include/uapi/linux/nfsd/	11287	F: include/uapi/linux/nfsd/
11274	F: include/uapi/linux/sunrpc/	11288	F: include/uapi/linux/sunrpc/
11275	F: net/sunrpc/	11289	F: net/sunrpc/
11276	F: Documentation/filesystems/nfs/
11277		11290
11278	KERNEL REGRESSIONS	11291	KERNEL REGRESSIONS
11279	M: Thorsten Leemhuis <linux@leemhuis.info>	11292	M: Thorsten Leemhuis <linux@leemhuis.info>
@@ -11388,83 +11401,42 @@ F: arch/riscv/include/asm/kvm* · 108 unmodified lines
11388	F: arch/riscv/include/uapi/asm/kvm*	11401	F: arch/riscv/include/uapi/asm/kvm*
11389	F: arch/riscv/kvm/	11402	F: arch/riscv/kvm/
11390	F: tools/testing/selftests/kvm/*/riscv/	11403	F: tools/testing/selftests/kvm/*/riscv/
11391		11404
11392	KERNEL VIRTUAL MACHINE for s390 (KVM/s390)	11405	KERNEL VIRTUAL MACHINE for s390 (KVM/s390)
11393	M: Christian Borntraeger <borntraeger@linux.ibm.com>	11406	M: Christian Borntraeger <borntraeger@linux.ibm.com>
11394	M: Janosch Frank <frankja@linux.ibm.com>	11407	M: Janosch Frank <frankja@linux.ibm.com>
11395	M: Claudio Imbrenda <imbrenda@linux.ibm.com>	11408	M: Claudio Imbrenda <imbrenda@linux.ibm.com>
11396	R: David Hildenbrand <david@redhat.com>	11409	R: David Hildenbrand <david@redhat.com>
11397	L: kvm@vger.kernel.org
11398	S: Supported
11399	T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git
11400	F: Documentation/virt/kvm/s390*
11401	F: arch/s390/include/asm/gmap.h
11402	F: arch/s390/include/asm/kvm*
11403	F: arch/s390/include/uapi/asm/kvm*
11404	F: arch/s390/include/uapi/asm/uvdevice.h
11405	F: arch/s390/kernel/uv.c
11406	F: arch/s390/kvm/
11407	F: arch/s390/mm/gmap.c
11408	F: drivers/s390/char/uvdevice.c
11409	F: tools/testing/selftests/drivers/s390x/uvdevice/
11410	F: tools/testing/selftests/kvm/*/s390x/
11411	F: tools/testing/selftests/kvm/s390x/
11412
11413	KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)
11414	M: Sean Christopherson <seanjc@google.com>
11415	M: Paolo Bonzini <pbonzini@redhat.com>
11416	L: kvm@vger.kernel.org
11417	S: Supported
11418	T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
11419	F: arch/x86/include/asm/kvm*
11420	F: arch/x86/include/asm/svm.h
11421	F: arch/x86/include/asm/vmx*.h
11422	F: arch/x86/include/uapi/asm/kvm*
11423	F: arch/x86/include/uapi/asm/svm.h
11424	F: arch/x86/include/uapi/asm/vmx.h
11425	F: arch/x86/kvm/
11426	F: arch/x86/kvm/*/
11427
11428	KVM PARAVIRT (KVM/paravirt)
11429	M: Paolo Bonzini <pbonzini@redhat.com>
11430	R: Wanpeng Li <wanpengli@tencent.com>
11431	R: Vitaly Kuznetsov <vkuznets@redhat.com>
11432	L: kvm@vger.kernel.org
11433	S: Supported
11434	T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
11435	F: arch/x86/kernel/kvm.c
11436	F: arch/x86/kernel/kvmclock.c
11437	F: arch/x86/include/asm/pvclock-abi.h
11438	F: include/linux/kvm_para.h
11439	F: include/uapi/linux/kvm_para.h
11440	F: include/uapi/asm-generic/kvm_para.h
11441	F: include/asm-generic/kvm_para.h
11442	F: arch/um/include/asm/kvm_para.h
11443	F: arch/x86/include/asm/kvm_para.h
11444	F: arch/x86/include/uapi/asm/kvm_para.h
11445
11446	KVM X86 HYPER-V (KVM/hyper-v)
11447	M: Vitaly Kuznetsov <vkuznets@redhat.com>
11448	M: Sean Christopherson <seanjc@google.com>
11449	M: Paolo Bonzini <pbonzini@redhat.com>
11450	L: kvm@vger.kernel.org	11410	L: kvm@vger.kernel.org
11451	S: Supported	11411	S: Supported
11452	T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git	11412	T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git
11453	F: arch/x86/kvm/hyperv.*	11413	F: Documentation/virt/kvm/s390*
11454	F: arch/x86/kvm/kvm_onhyperv.*	11414	F: arch/s390/include/asm/gmap.h
11455	F: arch/x86/kvm/svm/hyperv.*	11415	F: arch/s390/include/asm/kvm*
11456	F: arch/x86/kvm/svm/svm_onhyperv.*	11416	F: arch/s390/include/uapi/asm/kvm*
11457	F: arch/x86/kvm/vmx/hyperv.*	11417	F: arch/s390/include/uapi/asm/uvdevice.h
		11418	F: arch/s390/kernel/uv.c
		11419	F: arch/s390/kvm/
		11420	F: arch/s390/mm/gmap.c
		11421	F: drivers/s390/char/uvdevice.c
		11422	F: tools/testing/selftests/drivers/s390x/uvdevice/
		11423	F: tools/testing/selftests/kvm/*/s390x/
		11424	F: tools/testing/selftests/kvm/s390x/
11458		11425
11459	KVM X86 Xen (KVM/Xen)	11426	KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)
11460	M: David Woodhouse <dwmw2@infradead.org>
11461	M: Paul Durrant <paul@xen.org>
11462	M: Sean Christopherson <seanjc@google.com>	11427	M: Sean Christopherson <seanjc@google.com>
11463	M: Paolo Bonzini <pbonzini@redhat.com>	11428	M: Paolo Bonzini <pbonzini@redhat.com>
11464	L: kvm@vger.kernel.org	11429	L: kvm@vger.kernel.org
11465	S: Supported	11430	S: Supported
11466	T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git	11431	T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
11467	F: arch/x86/kvm/xen.*	11432	F: arch/x86/include/asm/kvm*
		11433	F: arch/x86/include/asm/svm.h
		11434	F: arch/x86/include/asm/vmx*.h
		11435	F: arch/x86/include/uapi/asm/kvm*
		11436	F: arch/x86/include/uapi/asm/svm.h
		11437	F: arch/x86/include/uapi/asm/vmx.h
		11438	F: arch/x86/kvm/
		11439	F: arch/x86/kvm/*/
11468		11440
11469	KERNFS	11441	KERNFS
11470	M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>	11442	M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
@@ -11504,14 +11476,6 @@ F: include/keys/trusted-type.h · 33 unmodified lines
11504	F: include/keys/trusted_tpm.h	11476	F: include/keys/trusted_tpm.h
11505	F: security/keys/trusted-keys/	11477	F: security/keys/trusted-keys/
11506		11478
11507	KEYS-TRUSTED-TEE
11508	M: Sumit Garg <sumit.garg@linaro.org>
11509	L: linux-integrity@vger.kernel.org
11510	L: keyrings@vger.kernel.org
11511	S: Supported
11512	F: include/keys/trusted_tee.h
11513	F: security/keys/trusted-keys/trusted_tee.c
11514
11515	KEYS-TRUSTED-CAAM	11479	KEYS-TRUSTED-CAAM
11516	M: Ahmad Fatoum <a.fatoum@pengutronix.de>	11480	M: Ahmad Fatoum <a.fatoum@pengutronix.de>
11517	R: Pengutronix Kernel Team <kernel@pengutronix.de>	11481	R: Pengutronix Kernel Team <kernel@pengutronix.de>
@@ -11521,6 +11485,14 @@ S: Maintained · 3 unmodified lines
11521	F: include/keys/trusted_caam.h	11485	F: include/keys/trusted_caam.h
11522	F: security/keys/trusted-keys/trusted_caam.c	11486	F: security/keys/trusted-keys/trusted_caam.c
11523		11487
		11488	KEYS-TRUSTED-TEE
		11489	M: Sumit Garg <sumit.garg@linaro.org>
		11490	L: linux-integrity@vger.kernel.org
		11491	L: keyrings@vger.kernel.org
		11492	S: Supported
		11493	F: include/keys/trusted_tee.h
		11494	F: security/keys/trusted-keys/trusted_tee.c
		11495
11524	KEYS/KEYRINGS	11496	KEYS/KEYRINGS
11525	M: David Howells <dhowells@redhat.com>	11497	M: David Howells <dhowells@redhat.com>
11526	M: Jarkko Sakkinen <jarkko@kernel.org>	11498	M: Jarkko Sakkinen <jarkko@kernel.org>
@@ -11583,8 +11555,8 @@ L: linux-amlogic@lists.infradead.org · 56 unmodified lines
11583	S: Maintained	11555	S: Maintained
11584	F: Documentation/devicetree/bindings/mfd/khadas,mcu.yaml	11556	F: Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
11585	F: drivers/mfd/khadas-mcu.c	11557	F: drivers/mfd/khadas-mcu.c
11586	F: include/linux/mfd/khadas-mcu.h
11587	F: drivers/thermal/khadas_mcu_fan.c	11558	F: drivers/thermal/khadas_mcu_fan.c
		11559	F: include/linux/mfd/khadas-mcu.h
11588		11560
11589	KIONIX/ROHM KX022A ACCELEROMETER	11561	KIONIX/ROHM KX022A ACCELEROMETER
11590	M: Matti Vaittinen <mazziesaccount@gmail.com>	11562	M: Matti Vaittinen <mazziesaccount@gmail.com>
@@ -11621,8 +11593,8 @@ M: "David S. Miller" <davem@davemloft.net> · 30 unmodified lines
11621	M: Masami Hiramatsu <mhiramat@kernel.org>	11593	M: Masami Hiramatsu <mhiramat@kernel.org>
11622	L: linux-kernel@vger.kernel.org	11594	L: linux-kernel@vger.kernel.org
11623	L: linux-trace-kernel@vger.kernel.org	11595	L: linux-trace-kernel@vger.kernel.org
11624	Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
11625	S: Maintained	11596	S: Maintained
		11597	Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
11626	T: git git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git	11598	T: git git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git
11627	F: Documentation/trace/kprobes.rst	11599	F: Documentation/trace/kprobes.rst
11628	F: include/asm-generic/kprobes.h	11600	F: include/asm-generic/kprobes.h
@@ -11656,6 +11628,47 @@ S: Maintained · 27 unmodified lines
11656	F: Documentation/devicetree/bindings/leds/backlight/kinetic,ktz8866.yaml	11628	F: Documentation/devicetree/bindings/leds/backlight/kinetic,ktz8866.yaml
11657	F: drivers/video/backlight/ktz8866.c	11629	F: drivers/video/backlight/ktz8866.c
11658		11630
		11631	KVM PARAVIRT (KVM/paravirt)
		11632	M: Paolo Bonzini <pbonzini@redhat.com>
		11633	R: Wanpeng Li <wanpengli@tencent.com>
		11634	R: Vitaly Kuznetsov <vkuznets@redhat.com>
		11635	L: kvm@vger.kernel.org
		11636	S: Supported
		11637	T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
		11638	F: arch/um/include/asm/kvm_para.h
		11639	F: arch/x86/include/asm/kvm_para.h
		11640	F: arch/x86/include/asm/pvclock-abi.h
		11641	F: arch/x86/include/uapi/asm/kvm_para.h
		11642	F: arch/x86/kernel/kvm.c
		11643	F: arch/x86/kernel/kvmclock.c
		11644	F: include/asm-generic/kvm_para.h
		11645	F: include/linux/kvm_para.h
		11646	F: include/uapi/asm-generic/kvm_para.h
		11647	F: include/uapi/linux/kvm_para.h
		11648
		11649	KVM X86 HYPER-V (KVM/hyper-v)
		11650	M: Vitaly Kuznetsov <vkuznets@redhat.com>
		11651	M: Sean Christopherson <seanjc@google.com>
		11652	M: Paolo Bonzini <pbonzini@redhat.com>
		11653	L: kvm@vger.kernel.org
		11654	S: Supported
		11655	T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
		11656	F: arch/x86/kvm/hyperv.*
		11657	F: arch/x86/kvm/kvm_onhyperv.*
		11658	F: arch/x86/kvm/svm/hyperv.*
		11659	F: arch/x86/kvm/svm/svm_onhyperv.*
		11660	F: arch/x86/kvm/vmx/hyperv.*
		11661
		11662	KVM X86 Xen (KVM/Xen)
		11663	M: David Woodhouse <dwmw2@infradead.org>
		11664	M: Paul Durrant <paul@xen.org>
		11665	M: Sean Christopherson <seanjc@google.com>
		11666	M: Paolo Bonzini <pbonzini@redhat.com>
		11667	L: kvm@vger.kernel.org
		11668	S: Supported
		11669	T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
		11670	F: arch/x86/kvm/xen.*
		11671
11659	L3MDEV	11672	L3MDEV
11660	M: David Ahern <dsahern@kernel.org>	11673	M: David Ahern <dsahern@kernel.org>
11661	L: netdev@vger.kernel.org	11674	L: netdev@vger.kernel.org
@@ -11897,9 +11910,9 @@ F: scripts/spdxexclude · 235 unmodified lines
11897	LINEAR RANGES HELPERS	11910	LINEAR RANGES HELPERS
11898	M: Mark Brown <broonie@kernel.org>	11911	M: Mark Brown <broonie@kernel.org>
11899	R: Matti Vaittinen <mazziesaccount@gmail.com>	11912	R: Matti Vaittinen <mazziesaccount@gmail.com>
		11913	F: include/linux/linear_range.h
11900	F: lib/linear_ranges.c	11914	F: lib/linear_ranges.c
11901	F: lib/test_linear_ranges.c	11915	F: lib/test_linear_ranges.c
11902	F: include/linux/linear_range.h
11903		11916
11904	LINUX FOR POWER MACINTOSH	11917	LINUX FOR POWER MACINTOSH
11905	M: Benjamin Herrenschmidt <benh@kernel.crashing.org>	11918	M: Benjamin Herrenschmidt <benh@kernel.crashing.org>
@@ -12026,11 +12039,11 @@ M: Joel Stanley <joel@jms.id.au> · 120 unmodified lines
12026	S: Maintained	12039	S: Maintained
12027	F: Documentation/devicetree/bindings//litex,.yaml	12040	F: Documentation/devicetree/bindings//litex,.yaml
12028	F: arch/openrisc/boot/dts/or1klitex.dts	12041	F: arch/openrisc/boot/dts/or1klitex.dts
12029	F: include/linux/litex.h
12030	F: drivers/tty/serial/liteuart.c
12031	F: drivers/soc/litex/*
12032	F: drivers/net/ethernet/litex/*
12033	F: drivers/mmc/host/litex_mmc.c	12042	F: drivers/mmc/host/litex_mmc.c
		12043	F: drivers/net/ethernet/litex/*
		12044	F: drivers/soc/litex/*
		12045	F: drivers/tty/serial/liteuart.c
		12046	F: include/linux/litex.h
12034	N: litex	12047	N: litex
12035		12048
12036	LIVE PATCHING	12049	LIVE PATCHING
@@ -12159,10 +12172,17 @@ R: WANG Xuerui <kernel@xen0n.name> · 122 unmodified lines
12159	L: loongarch@lists.linux.dev	12172	L: loongarch@lists.linux.dev
12160	S: Maintained	12173	S: Maintained
12161	T: git git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git	12174	T: git git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git
12162	F: arch/loongarch/
12163	F: drivers//loongarch*
12164	F: Documentation/loongarch/	12175	F: Documentation/loongarch/
12165	F: Documentation/translations/zh_CN/loongarch/	12176	F: Documentation/translations/zh_CN/loongarch/
		12177	F: arch/loongarch/
		12178	F: drivers//loongarch*
		12179
		12180	LOONGSON GPIO DRIVER
		12181	M: Yinbo Zhu <zhuyinbo@loongson.cn>
		12182	L: linux-gpio@vger.kernel.org
		12183	S: Maintained
		12184	F: Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml
		12185	F: drivers/gpio/gpio-loongson-64bit.c
12166		12186
12167	LOONGSON LS2X I2C DRIVER	12187	LOONGSON LS2X I2C DRIVER
12168	M: Binbin Zhou <zhoubinbin@loongson.cn>	12188	M: Binbin Zhou <zhoubinbin@loongson.cn>
@@ -12171,6 +12191,14 @@ S: Maintained · 2 unmodified lines
12171	F: Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml	12191	F: Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml
12172	F: drivers/i2c/busses/i2c-ls2x.c	12192	F: drivers/i2c/busses/i2c-ls2x.c
12173		12193
		12194	LOONGSON-2 SOC SERIES CLOCK DRIVER
		12195	M: Yinbo Zhu <zhuyinbo@loongson.cn>
		12196	L: linux-clk@vger.kernel.org
		12197	S: Maintained
		12198	F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
		12199	F: drivers/clk/clk-loongson2.c
		12200	F: include/dt-bindings/clock/loongson,ls2k-clk.h
		12201
12174	LOONGSON-2 SOC SERIES GUTS DRIVER	12202	LOONGSON-2 SOC SERIES GUTS DRIVER
12175	M: Yinbo Zhu <zhuyinbo@loongson.cn>	12203	M: Yinbo Zhu <zhuyinbo@loongson.cn>
12176	L: loongarch@lists.linux.dev	12204	L: loongarch@lists.linux.dev
@@ -12186,21 +12214,6 @@ S: Maintained · 9 unmodified lines
12186	F: Documentation/devicetree/bindings/pinctrl/loongson,ls2k-pinctrl.yaml	12214	F: Documentation/devicetree/bindings/pinctrl/loongson,ls2k-pinctrl.yaml
12187	F: drivers/pinctrl/pinctrl-loongson2.c	12215	F: drivers/pinctrl/pinctrl-loongson2.c
12188		12216
12189	LOONGSON GPIO DRIVER
12190	M: Yinbo Zhu <zhuyinbo@loongson.cn>
12191	L: linux-gpio@vger.kernel.org
12192	S: Maintained
12193	F: Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml
12194	F: drivers/gpio/gpio-loongson-64bit.c
12195
12196	LOONGSON-2 SOC SERIES CLOCK DRIVER
12197	M: Yinbo Zhu <zhuyinbo@loongson.cn>
12198	L: linux-clk@vger.kernel.org
12199	S: Maintained
12200	F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
12201	F: drivers/clk/clk-loongson2.c
12202	F: include/dt-bindings/clock/loongson,ls2k-clk.h
12203
12204	LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI)	12217	LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI)
12205	M: Sathya Prakash <sathya.prakash@broadcom.com>	12218	M: Sathya Prakash <sathya.prakash@broadcom.com>
12206	M: Sreekanth Reddy <sreekanth.reddy@broadcom.com>	12219	M: Sreekanth Reddy <sreekanth.reddy@broadcom.com>
@@ -12361,20 +12374,26 @@ MAILBOX API · 154 unmodified lines
12361	M: Jassi Brar <jassisinghbrar@gmail.com>	12374	M: Jassi Brar <jassisinghbrar@gmail.com>
12362	L: linux-kernel@vger.kernel.org	12375	L: linux-kernel@vger.kernel.org
12363	S: Maintained	12376	S: Maintained
		12377	F: Documentation/devicetree/bindings/mailbox/
12364	F: drivers/mailbox/	12378	F: drivers/mailbox/
		12379	F: include/dt-bindings/mailbox/
12365	F: include/linux/mailbox_client.h	12380	F: include/linux/mailbox_client.h
12366	F: include/linux/mailbox_controller.h	12381	F: include/linux/mailbox_controller.h
12367	F: include/dt-bindings/mailbox/
12368	F: Documentation/devicetree/bindings/mailbox/
12369		12382
12370	MAILBOX ARM MHUv2	12383	MAILBOX ARM MHUv2
12371	M: Viresh Kumar <viresh.kumar@linaro.org>	12384	M: Viresh Kumar <viresh.kumar@linaro.org>
12372	M: Tushar Khandelwal <Tushar.Khandelwal@arm.com>	12385	M: Tushar Khandelwal <Tushar.Khandelwal@arm.com>
12373	L: linux-kernel@vger.kernel.org	12386	L: linux-kernel@vger.kernel.org
12374	S: Maintained	12387	S: Maintained
		12388	F: Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
12375	F: drivers/mailbox/arm_mhuv2.c	12389	F: drivers/mailbox/arm_mhuv2.c
12376	F: include/linux/mailbox/arm_mhuv2_message.h	12390	F: include/linux/mailbox/arm_mhuv2_message.h
12377	F: Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml	12391
		12392	MAN-PAGES: MANUAL PAGES FOR LINUX -- Sections 2, 3, 4, 5, and 7
		12393	M: Michael Kerrisk <mtk.manpages@gmail.com>
		12394	L: linux-man@vger.kernel.org
		12395	S: Maintained
		12396	W: http://www.kernel.org/doc/man-pages
12378		12397
12379	MANAGEMENT COMPONENT TRANSPORT PROTOCOL (MCTP)	12398	MANAGEMENT COMPONENT TRANSPORT PROTOCOL (MCTP)
12380	M: Jeremy Kerr <jk@codeconstruct.com.au>	12399	M: Jeremy Kerr <jk@codeconstruct.com.au>
@@ -12388,12 +12407,6 @@ F: include/net/mctpdevice.h · 7 unmodified lines
12388	F: include/net/netns/mctp.h	12407	F: include/net/netns/mctp.h
12389	F: net/mctp/	12408	F: net/mctp/
12390		12409
12391	MAN-PAGES: MANUAL PAGES FOR LINUX -- Sections 2, 3, 4, 5, and 7
12392	M: Michael Kerrisk <mtk.manpages@gmail.com>
12393	L: linux-man@vger.kernel.org
12394	S: Maintained
12395	W: http://www.kernel.org/doc/man-pages
12396
12397	MAPLE TREE	12410	MAPLE TREE
12398	M: Liam R. Howlett <Liam.Howlett@oracle.com>	12411	M: Liam R. Howlett <Liam.Howlett@oracle.com>
12399	L: linux-mm@kvack.org	12412	L: linux-mm@kvack.org
@@ -12425,8 +12438,8 @@ F: include/linux/platform_data/mv88e6xxx.h · 25 unmodified lines
12425	MARVELL ARMADA 3700 PHY DRIVERS	12438	MARVELL ARMADA 3700 PHY DRIVERS
12426	M: Miquel Raynal <miquel.raynal@bootlin.com>	12439	M: Miquel Raynal <miquel.raynal@bootlin.com>
12427	S: Maintained	12440	S: Maintained
12428	F: Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
12429	F: Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml	12441	F: Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
		12442	F: Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
12430	F: drivers/phy/marvell/phy-mvebu-a3700-comphy.c	12443	F: drivers/phy/marvell/phy-mvebu-a3700-comphy.c
12431	F: drivers/phy/marvell/phy-mvebu-a3700-utmi.c	12444	F: drivers/phy/marvell/phy-mvebu-a3700-utmi.c
12432		12445
@@ -12528,6 +12541,13 @@ S: Maintained · 95 unmodified lines
12528	F: Documentation/devicetree/bindings/mtd/marvell-nand.txt	12541	F: Documentation/devicetree/bindings/mtd/marvell-nand.txt
12529	F: drivers/mtd/nand/raw/marvell_nand.c	12542	F: drivers/mtd/nand/raw/marvell_nand.c
12530		12543
		12544	MARVELL OCTEON ENDPOINT DRIVER
		12545	M: Veerasenareddy Burru <vburru@marvell.com>
		12546	M: Abhijit Ayarekar <aayarekar@marvell.com>
		12547	L: netdev@vger.kernel.org
		12548	S: Supported
		12549	F: drivers/net/ethernet/marvell/octeon_ep
		12550
12531	MARVELL OCTEONTX2 PHYSICAL FUNCTION DRIVER	12551	MARVELL OCTEONTX2 PHYSICAL FUNCTION DRIVER
12532	M: Sunil Goutham <sgoutham@marvell.com>	12552	M: Sunil Goutham <sgoutham@marvell.com>
12533	M: Geetha sowjanya <gakula@marvell.com>	12553	M: Geetha sowjanya <gakula@marvell.com>
@@ -12575,13 +12595,6 @@ S: Supported · 41 unmodified lines
12575	F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml	12595	F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
12576	F: drivers/mmc/host/sdhci-xenon*	12596	F: drivers/mmc/host/sdhci-xenon*
12577		12597
12578	MARVELL OCTEON ENDPOINT DRIVER
12579	M: Veerasenareddy Burru <vburru@marvell.com>
12580	M: Abhijit Ayarekar <aayarekar@marvell.com>
12581	L: netdev@vger.kernel.org
12582	S: Supported
12583	F: drivers/net/ethernet/marvell/octeon_ep
12584
12585	MATROX FRAMEBUFFER DRIVER	12598	MATROX FRAMEBUFFER DRIVER
12586	L: linux-fbdev@vger.kernel.org	12599	L: linux-fbdev@vger.kernel.org
12587	S: Orphan	12600	S: Orphan
@@ -12781,12 +12794,6 @@ L: netdev@vger.kernel.org · 193 unmodified lines
12781	S: Supported	12794	S: Supported
12782	F: drivers/net/phy/mxl-gpy.c	12795	F: drivers/net/phy/mxl-gpy.c
12783		12796
12784	MCBA MICROCHIP CAN BUS ANALYZER TOOL DRIVER
12785	R: Yasushi SHOJI <yashi@spacecubics.com>
12786	L: linux-can@vger.kernel.org
12787	S: Maintained
12788	F: drivers/net/can/usb/mcba_usb.c
12789
12790	MCAN MMIO DEVICE DRIVER	12797	MCAN MMIO DEVICE DRIVER
12791	M: Chandrasekar Ramakrishnan <rcsekar@samsung.com>	12798	M: Chandrasekar Ramakrishnan <rcsekar@samsung.com>
12792	L: linux-can@vger.kernel.org	12799	L: linux-can@vger.kernel.org
@@ -12796,6 +12803,12 @@ F: drivers/net/can/m_can/m_can.c · 3 unmodified lines
12796	F: drivers/net/can/m_can/m_can.h	12803	F: drivers/net/can/m_can/m_can.h
12797	F: drivers/net/can/m_can/m_can_platform.c	12804	F: drivers/net/can/m_can/m_can_platform.c
12798		12805
		12806	MCBA MICROCHIP CAN BUS ANALYZER TOOL DRIVER
		12807	R: Yasushi SHOJI <yashi@spacecubics.com>
		12808	L: linux-can@vger.kernel.org
		12809	S: Maintained
		12810	F: drivers/net/can/usb/mcba_usb.c
		12811
12799	MCP2221A MICROCHIP USB-HID TO I2C BRIDGE DRIVER	12812	MCP2221A MICROCHIP USB-HID TO I2C BRIDGE DRIVER
12800	M: Rishi Gupta <gupt21@gmail.com>	12813	M: Rishi Gupta <gupt21@gmail.com>
12801	L: linux-i2c@vger.kernel.org	12814	L: linux-i2c@vger.kernel.org
@@ -13204,13 +13217,6 @@ S: Maintained · 402 unmodified lines
13204	F: Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml	13217	F: Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
13205	F: drivers/clk/ralink/clk-mt7621.c	13218	F: drivers/clk/ralink/clk-mt7621.c
13206		13219
13207	MEDIATEK MT7621/28/88 I2C DRIVER
13208	M: Stefan Roese <sr@denx.de>
13209	L: linux-i2c@vger.kernel.org
13210	S: Maintained
13211	F: Documentation/devicetree/bindings/i2c/mediatek,mt7621-i2c.yaml
13212	F: drivers/i2c/busses/i2c-mt7621.c
13213
13214	MEDIATEK MT7621 PCIE CONTROLLER DRIVER	13220	MEDIATEK MT7621 PCIE CONTROLLER DRIVER
13215	M: Sergio Paracuellos <sergio.paracuellos@gmail.com>	13221	M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
13216	S: Maintained	13222	S: Maintained
@@ -13223,6 +13229,13 @@ S: Maintained · 6 unmodified lines
13223	F: Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml	13229	F: Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
13224	F: drivers/phy/ralink/phy-mt7621-pci.c	13230	F: drivers/phy/ralink/phy-mt7621-pci.c
13225		13231
		13232	MEDIATEK MT7621/28/88 I2C DRIVER
		13233	M: Stefan Roese <sr@denx.de>
		13234	L: linux-i2c@vger.kernel.org
		13235	S: Maintained
		13236	F: Documentation/devicetree/bindings/i2c/mediatek,mt7621-i2c.yaml
		13237	F: drivers/i2c/busses/i2c-mt7621.c
		13238
13226	MEDIATEK NAND CONTROLLER DRIVER	13239	MEDIATEK NAND CONTROLLER DRIVER
13227	L: linux-mtd@lists.infradead.org	13240	L: linux-mtd@lists.infradead.org
13228	S: Orphan	13241	S: Orphan
@@ -13482,10 +13495,22 @@ MEMORY FREQUENCY SCALING DRIVERS FOR NVIDIA TEGRA · 253 unmodified lines
13482	M: Dmitry Osipenko <digetx@gmail.com>	13495	M: Dmitry Osipenko <digetx@gmail.com>
13483	L: linux-pm@vger.kernel.org	13496	L: linux-pm@vger.kernel.org
13484	L: linux-tegra@vger.kernel.org	13497	L: linux-tegra@vger.kernel.org
13485	T: git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git
13486	S: Maintained	13498	S: Maintained
		13499	T: git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git
13487	F: drivers/devfreq/tegra30-devfreq.c	13500	F: drivers/devfreq/tegra30-devfreq.c
13488		13501
		13502	MEMORY HOT(UN)PLUG
		13503	M: David Hildenbrand <david@redhat.com>
		13504	M: Oscar Salvador <osalvador@suse.de>
		13505	L: linux-mm@kvack.org
		13506	S: Maintained
		13507	F: Documentation/admin-guide/mm/memory-hotplug.rst
		13508	F: Documentation/core-api/memory-hotplug.rst
		13509	F: drivers/base/memory.c
		13510	F: include/linux/memory_hotplug.h
		13511	F: mm/memory_hotplug.c
		13512	F: tools/testing/selftests/memory-hotplug/
		13513
13489	MEMORY MANAGEMENT	13514	MEMORY MANAGEMENT
13490	M: Andrew Morton <akpm@linux-foundation.org>	13515	M: Andrew Morton <akpm@linux-foundation.org>
13491	L: linux-mm@kvack.org	13516	L: linux-mm@kvack.org
@@ -13504,30 +13529,6 @@ F: mm/ · 12 unmodified lines
13504	F: tools/mm/	13529	F: tools/mm/
13505	F: tools/testing/selftests/mm/	13530	F: tools/testing/selftests/mm/
13506		13531
13507	VMALLOC
13508	M: Andrew Morton <akpm@linux-foundation.org>
13509	R: Uladzislau Rezki <urezki@gmail.com>
13510	R: Christoph Hellwig <hch@infradead.org>
13511	R: Lorenzo Stoakes <lstoakes@gmail.com>
13512	L: linux-mm@kvack.org
13513	S: Maintained
13514	W: http://www.linux-mm.org
13515	T: git git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
13516	F: include/linux/vmalloc.h
13517	F: mm/vmalloc.c
13518
13519	MEMORY HOT(UN)PLUG
13520	M: David Hildenbrand <david@redhat.com>
13521	M: Oscar Salvador <osalvador@suse.de>
13522	L: linux-mm@kvack.org
13523	S: Maintained
13524	F: Documentation/admin-guide/mm/memory-hotplug.rst
13525	F: Documentation/core-api/memory-hotplug.rst
13526	F: drivers/base/memory.c
13527	F: include/linux/memory_hotplug.h
13528	F: mm/memory_hotplug.c
13529	F: tools/testing/selftests/memory-hotplug/
13530
13531	MEMORY TECHNOLOGY DEVICES (MTD)	13532	MEMORY TECHNOLOGY DEVICES (MTD)
13532	M: Miquel Raynal <miquel.raynal@bootlin.com>	13533	M: Miquel Raynal <miquel.raynal@bootlin.com>
13533	M: Richard Weinberger <richard@nod.at>	13534	M: Richard Weinberger <richard@nod.at>
@@ -13638,6 +13639,12 @@ W: http://www.monstr.eu/fdt/ · 104 unmodified lines
13638	T: git git://git.monstr.eu/linux-2.6-microblaze.git	13639	T: git git://git.monstr.eu/linux-2.6-microblaze.git
13639	F: arch/microblaze/	13640	F: arch/microblaze/
13640		13641
		13642	MICROBLAZE TMR INJECT
		13643	M: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
		13644	S: Supported
		13645	F: Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml
		13646	F: drivers/misc/xilinx_tmr_inject.c
		13647
13641	MICROBLAZE TMR MANAGER	13648	MICROBLAZE TMR MANAGER
13642	M: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>	13649	M: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
13643	S: Supported	13650	S: Supported
@@ -13645,12 +13652,6 @@ F: Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager · 1 unmodified line
13645	F: Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml	13652	F: Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml
13646	F: drivers/misc/xilinx_tmr_manager.c	13653	F: drivers/misc/xilinx_tmr_manager.c
13647		13654
13648	MICROBLAZE TMR INJECT
13649	M: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
13650	S: Supported
13651	F: Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml
13652	F: drivers/misc/xilinx_tmr_inject.c
13653
13654	MICROCHIP AT91 DMA DRIVERS	13655	MICROCHIP AT91 DMA DRIVERS
13655	M: Ludovic Desroches <ludovic.desroches@microchip.com>	13656	M: Ludovic Desroches <ludovic.desroches@microchip.com>
13656	M: Tudor Ambarus <tudor.ambarus@linaro.org>	13657	M: Tudor Ambarus <tudor.ambarus@linaro.org>
@@ -13725,11 +13726,11 @@ M: Eugen Hristev <eugen.hristev@microchip.com> · 68 unmodified lines
13725	L: linux-media@vger.kernel.org	13726	L: linux-media@vger.kernel.org
13726	S: Supported	13727	S: Supported
13727	F: Documentation/devicetree/bindings/media/atmel,isc.yaml	13728	F: Documentation/devicetree/bindings/media/atmel,isc.yaml
13728	F: Documentation/devicetree/bindings/media/microchip,xisc.yaml	13729	F: Documentation/devicetree/bindings/media/microchip,xisc.yaml
13729	F: drivers/staging/media/deprecated/atmel/atmel-isc*
13730	F: drivers/staging/media/deprecated/atmel/atmel-sama-isc
13731	F: drivers/media/platform/microchip/microchip-isc*	13730	F: drivers/media/platform/microchip/microchip-isc*
13732	F: drivers/media/platform/microchip/microchip-sama-isc	13731	F: drivers/media/platform/microchip/microchip-sama-isc
		13732	F: drivers/staging/media/deprecated/atmel/atmel-isc*
		13733	F: drivers/staging/media/deprecated/atmel/atmel-sama-isc
13733	F: include/linux/atmel-isc-media.h	13734	F: include/linux/atmel-isc-media.h
13734		13735
13735	MICROCHIP ISI DRIVER	13736	MICROCHIP ISI DRIVER
@@ -13751,13 +13752,6 @@ F: include/linux/dsa/ksz_common.h · 15 unmodified lines
13751	F: include/linux/platform_data/microchip-ksz.h	13752	F: include/linux/platform_data/microchip-ksz.h
13752	F: net/dsa/tag_ksz.c	13753	F: net/dsa/tag_ksz.c
13753		13754
13754	MICROCHIP LAN87xx/LAN937x T1 PHY DRIVER
13755	M: Arun Ramadoss <arun.ramadoss@microchip.com>
13756	R: UNGLinuxDriver@microchip.com
13757	L: netdev@vger.kernel.org
13758	S: Maintained
13759	F: drivers/net/phy/microchip_t1.c
13760
13761	MICROCHIP LAN743X ETHERNET DRIVER	13755	MICROCHIP LAN743X ETHERNET DRIVER
13762	M: Bryan Whitehead <bryan.whitehead@microchip.com>	13756	M: Bryan Whitehead <bryan.whitehead@microchip.com>
13763	M: UNGLinuxDriver@microchip.com	13757	M: UNGLinuxDriver@microchip.com
@@ -13765,6 +13759,13 @@ L: netdev@vger.kernel.org · 1 unmodified line
13765	S: Maintained	13759	S: Maintained
13766	F: drivers/net/ethernet/microchip/lan743x_*	13760	F: drivers/net/ethernet/microchip/lan743x_*
13767		13761
		13762	MICROCHIP LAN87xx/LAN937x T1 PHY DRIVER
		13763	M: Arun Ramadoss <arun.ramadoss@microchip.com>
		13764	R: UNGLinuxDriver@microchip.com
		13765	L: netdev@vger.kernel.org
		13766	S: Maintained
		13767	F: drivers/net/phy/microchip_t1.c
		13768
13768	MICROCHIP LAN966X ETHERNET DRIVER	13769	MICROCHIP LAN966X ETHERNET DRIVER
13769	M: Horatiu Vultur <horatiu.vultur@microchip.com>	13770	M: Horatiu Vultur <horatiu.vultur@microchip.com>
13770	M: UNGLinuxDriver@microchip.com	13771	M: UNGLinuxDriver@microchip.com
@@ -13806,14 +13807,6 @@ S: Supported · 35 unmodified lines
13806	F: Documentation/devicetree/bindings/mtd/atmel-nand.txt	13807	F: Documentation/devicetree/bindings/mtd/atmel-nand.txt
13807	F: drivers/mtd/nand/raw/atmel/*	13808	F: drivers/mtd/nand/raw/atmel/*
13808		13809
13809	MICROCHIP PCI1XXXX GP DRIVER
13810	M: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
13811	L: linux-gpio@vger.kernel.org
13812	S: Supported
13813	F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.c
13814	F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.h
13815	F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
13816
13817	MICROCHIP OTPC DRIVER	13810	MICROCHIP OTPC DRIVER
13818	M: Claudiu Beznea <claudiu.beznea@microchip.com>	13811	M: Claudiu Beznea <claudiu.beznea@microchip.com>
13819	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)	13812	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -13822,6 +13815,14 @@ F: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml · 2 unmodified lines
13822	F: drivers/nvmem/microchip-otpc.c	13815	F: drivers/nvmem/microchip-otpc.c
13823	F: include/dt-bindings/nvmem/microchip,sama7g5-otpc.h	13816	F: include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
13824		13817
		13818	MICROCHIP PCI1XXXX GP DRIVER
		13819	M: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
		13820	L: linux-gpio@vger.kernel.org
		13821	S: Supported
		13822	F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.c
		13823	F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.h
		13824	F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
		13825
13825	MICROCHIP PCI1XXXX I2C DRIVER	13826	MICROCHIP PCI1XXXX I2C DRIVER
13826	M: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>	13827	M: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
13827	M: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>	13828	M: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
@@ -13837,6 +13838,14 @@ L: linux-serial@vger.kernel.org · 9 unmodified lines
13837	S: Maintained	13838	S: Maintained
13838	F: drivers/tty/serial/8250/8250_pci1xxxx.c	13839	F: drivers/tty/serial/8250/8250_pci1xxxx.c
13839		13840
		13841	MICROCHIP POLARFIRE FPGA DRIVERS
		13842	M: Conor Dooley <conor.dooley@microchip.com>
		13843	R: Ivan Bornyakov <i.bornyakov@metrotek.ru>
		13844	L: linux-fpga@vger.kernel.org
		13845	S: Supported
		13846	F: Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
		13847	F: drivers/fpga/microchip-spi.c
		13848
13840	MICROCHIP PWM DRIVER	13849	MICROCHIP PWM DRIVER
13841	M: Claudiu Beznea <claudiu.beznea@microchip.com>	13850	M: Claudiu Beznea <claudiu.beznea@microchip.com>
13842	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)	13851	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -13858,6 +13867,12 @@ M: Claudiu Beznea <claudiu.beznea@microchip.com> · 15 unmodified lines
13858	S: Supported	13867	S: Supported
13859	F: drivers/power/reset/at91-sama5d2_shdwc.c	13868	F: drivers/power/reset/at91-sama5d2_shdwc.c
13860		13869
		13870	MICROCHIP SOC DRIVERS
		13871	M: Conor Dooley <conor@kernel.org>
		13872	S: Supported
		13873	T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
		13874	F: drivers/soc/microchip/
		13875
13861	MICROCHIP SPI DRIVER	13876	MICROCHIP SPI DRIVER
13862	M: Tudor Ambarus <tudor.ambarus@linaro.org>	13877	M: Tudor Ambarus <tudor.ambarus@linaro.org>
13863	S: Supported	13878	S: Supported
@@ -13871,11 +13886,12 @@ F: Documentation/devicetree/bindings/misc/atmel-ssc.txt · 7 unmodified lines
13871	F: drivers/misc/atmel-ssc.c	13886	F: drivers/misc/atmel-ssc.c
13872	F: include/linux/atmel-ssc.h	13887	F: include/linux/atmel-ssc.h
13873		13888
13874	MICROCHIP SOC DRIVERS	13889	Microchip Timer Counter Block (TCB) Capture Driver
13875	M: Conor Dooley <conor@kernel.org>	13890	M: Kamel Bouhara <kamel.bouhara@bootlin.com>
13876	S: Supported	13891	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
13877	T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/	13892	L: linux-iio@vger.kernel.org
13878	F: drivers/soc/microchip/	13893	S: Maintained
		13894	F: drivers/counter/microchip-tcb-capture.c
13879		13895
13880	MICROCHIP USB251XB DRIVER	13896	MICROCHIP USB251XB DRIVER
13881	M: Richard Leitner <richard.leitner@skidata.com>	13897	M: Richard Leitner <richard.leitner@skidata.com>
@@ -13992,6 +14008,12 @@ L: platform-driver-x86@vger.kernel.org · 110 unmodified lines
13992	S: Supported	14008	S: Supported
13993	F: drivers/platform/surface/surfacepro3_button.c	14009	F: drivers/platform/surface/surfacepro3_button.c
13994		14010
		14011	MICROSOFT SURFACE SYSTEM AGGREGATOR HUB DRIVER
		14012	M: Maximilian Luz <luzmaximilian@gmail.com>
		14013	L: platform-driver-x86@vger.kernel.org
		14014	S: Maintained
		14015	F: drivers/platform/surface/surface_aggregator_hub.c
		14016
13995	MICROSOFT SURFACE SYSTEM AGGREGATOR SUBSYSTEM	14017	MICROSOFT SURFACE SYSTEM AGGREGATOR SUBSYSTEM
13996	M: Maximilian Luz <luzmaximilian@gmail.com>	14018	M: Maximilian Luz <luzmaximilian@gmail.com>
13997	L: platform-driver-x86@vger.kernel.org	14019	L: platform-driver-x86@vger.kernel.org
@@ -14007,12 +14029,6 @@ F: include/linux/surface_acpi_notify.h · 9 unmodified lines
14007	F: include/linux/surface_aggregator/	14029	F: include/linux/surface_aggregator/
14008	F: include/uapi/linux/surface_aggregator/	14030	F: include/uapi/linux/surface_aggregator/
14009		14031
14010	MICROSOFT SURFACE SYSTEM AGGREGATOR HUB DRIVER
14011	M: Maximilian Luz <luzmaximilian@gmail.com>
14012	L: platform-driver-x86@vger.kernel.org
14013	S: Maintained
14014	F: drivers/platform/surface/surface_aggregator_hub.c
14015
14016	MICROTEK X6 SCANNER	14032	MICROTEK X6 SCANNER
14017	M: Oliver Neukum <oliver@neukum.org>	14033	M: Oliver Neukum <oliver@neukum.org>
14018	S: Maintained	14034	S: Maintained
@@ -14178,11 +14194,11 @@ L: linux-modules@vger.kernel.org · 159 unmodified lines
14178	L: linux-kernel@vger.kernel.org	14194	L: linux-kernel@vger.kernel.org
14179	S: Maintained	14195	S: Maintained
14180	T: git git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux.git modules-next	14196	T: git git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux.git modules-next
14181	F: include/linux/module.h
14182	F: include/linux/kmod.h	14197	F: include/linux/kmod.h
		14198	F: include/linux/module.h
14183	F: kernel/module/	14199	F: kernel/module/
14184	F: scripts/module*
14185	F: lib/test_kmod.c	14200	F: lib/test_kmod.c
		14201	F: scripts/module*
14186	F: tools/testing/selftests/kmod/	14202	F: tools/testing/selftests/kmod/
14187		14203
14188	MONOLITHIC POWER SYSTEM PMIC DRIVER	14204	MONOLITHIC POWER SYSTEM PMIC DRIVER
@@ -14771,6 +14787,7 @@ L: linux-nfs@vger.kernel.org · 582 unmodified lines
14771	S: Maintained	14787	S: Maintained
14772	W: http://client.linux-nfs.org	14788	W: http://client.linux-nfs.org
14773	T: git git://git.linux-nfs.org/projects/trondmy/linux-nfs.git	14789	T: git git://git.linux-nfs.org/projects/trondmy/linux-nfs.git
		14790	F: Documentation/filesystems/nfs/
14774	F: fs/lockd/	14791	F: fs/lockd/
14775	F: fs/nfs/	14792	F: fs/nfs/
14776	F: fs/nfs_common/	14793	F: fs/nfs_common/
@@ -14780,7 +14797,6 @@ F: include/linux/sunrpc/ · 3 unmodified lines
14780	F: include/uapi/linux/nfs*	14797	F: include/uapi/linux/nfs*
14781	F: include/uapi/linux/sunrpc/	14798	F: include/uapi/linux/sunrpc/
14782	F: net/sunrpc/	14799	F: net/sunrpc/
14783	F: Documentation/filesystems/nfs/
14784		14800
14785	NILFS2 FILESYSTEM	14801	NILFS2 FILESYSTEM
14786	M: Ryusuke Konishi <konishi.ryusuke@gmail.com>	14802	M: Ryusuke Konishi <konishi.ryusuke@gmail.com>
@@ -14984,12 +15000,6 @@ F: drivers/nvme/target/auth.c · 197 unmodified lines
14984	F: drivers/nvme/target/fabrics-cmd-auth.c	15000	F: drivers/nvme/target/fabrics-cmd-auth.c
14985	F: include/linux/nvme-auth.h	15001	F: include/linux/nvme-auth.h
14986		15002
14987	NVM EXPRESS HARDWARE MONITORING SUPPORT
14988	M: Guenter Roeck <linux@roeck-us.net>
14989	L: linux-nvme@lists.infradead.org
14990	S: Supported
14991	F: drivers/nvme/host/hwmon.c
14992
14993	NVM EXPRESS FC TRANSPORT DRIVERS	15003	NVM EXPRESS FC TRANSPORT DRIVERS
14994	M: James Smart <james.smart@broadcom.com>	15004	M: James Smart <james.smart@broadcom.com>
14995	L: linux-nvme@lists.infradead.org	15005	L: linux-nvme@lists.infradead.org
@@ -15000,6 +15010,12 @@ F: drivers/nvme/target/fcloop.c · 4 unmodified lines
15000	F: include/linux/nvme-fc-driver.h	15010	F: include/linux/nvme-fc-driver.h
15001	F: include/linux/nvme-fc.h	15011	F: include/linux/nvme-fc.h
15002		15012
		15013	NVM EXPRESS HARDWARE MONITORING SUPPORT
		15014	M: Guenter Roeck <linux@roeck-us.net>
		15015	L: linux-nvme@lists.infradead.org
		15016	S: Supported
		15017	F: drivers/nvme/host/hwmon.c
		15018
15003	NVM EXPRESS TARGET DRIVER	15019	NVM EXPRESS TARGET DRIVER
15004	M: Christoph Hellwig <hch@lst.de>	15020	M: Christoph Hellwig <hch@lst.de>
15005	M: Sagi Grimberg <sagi@grimberg.me>	15021	M: Sagi Grimberg <sagi@grimberg.me>
@@ -15020,6 +15036,13 @@ F: drivers/nvmem/ · 14 unmodified lines
15020	F: include/linux/nvmem-consumer.h	15036	F: include/linux/nvmem-consumer.h
15021	F: include/linux/nvmem-provider.h	15037	F: include/linux/nvmem-provider.h
15022		15038
		15039	NXP BLUETOOTH WIRELESS DRIVERS
		15040	M: Amitkumar Karwar <amitkumar.karwar@nxp.com>
		15041	M: Neeraj Kale <neeraj.sanjaykale@nxp.com>
		15042	S: Maintained
		15043	F: Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml
		15044	F: drivers/bluetooth/btnxpuart.c
		15045
15023	NXP C45 TJA11XX PHY DRIVER	15046	NXP C45 TJA11XX PHY DRIVER
15024	M: Radu Pirea <radu-nicolae.pirea@oss.nxp.com>	15047	M: Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
15025	L: netdev@vger.kernel.org	15048	L: netdev@vger.kernel.org
@@ -15045,16 +15068,17 @@ F: drivers/iio/gyro/fxas21002c_core.c · 19 unmodified lines
15045	F: drivers/iio/gyro/fxas21002c_i2c.c	15068	F: drivers/iio/gyro/fxas21002c_i2c.c
15046	F: drivers/iio/gyro/fxas21002c_spi.c	15069	F: drivers/iio/gyro/fxas21002c_spi.c
15047		15070
15048	NXP i.MX CLOCK DRIVERS	15071	NXP i.MX 7D/6SX/6UL/93 AND VF610 ADC DRIVER
15049	M: Abel Vesa <abelvesa@kernel.org>	15072	M: Haibo Chen <haibo.chen@nxp.com>
15050	R: Peng Fan <peng.fan@nxp.com>	15073	L: linux-iio@vger.kernel.org
15051	L: linux-clk@vger.kernel.org
15052	L: linux-imx@nxp.com	15074	L: linux-imx@nxp.com
15053	S: Maintained	15075	S: Maintained
15054	T: git git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux.git clk/imx	15076	F: Documentation/devicetree/bindings/iio/adc/fsl,imx7d-adc.yaml
15055	F: Documentation/devicetree/bindings/clock/imx*	15077	F: Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml
15056	F: drivers/clk/imx/	15078	F: Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml
15057	F: include/dt-bindings/clock/imx*	15079	F: drivers/iio/adc/imx7d_adc.c
		15080	F: drivers/iio/adc/imx93_adc.c
		15081	F: drivers/iio/adc/vf610_adc.c
15058		15082
15059	NXP i.MX 8M ISI DRIVER	15083	NXP i.MX 8M ISI DRIVER
15060	M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>	15084	M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
@@ -15063,6 +15087,15 @@ S: Maintained · 2 unmodified lines
15063	F: Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml	15087	F: Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml
15064	F: drivers/media/platform/nxp/imx8-isi/	15088	F: drivers/media/platform/nxp/imx8-isi/
15065		15089
		15090	NXP i.MX 8MP DW100 V4L2 DRIVER
		15091	M: Xavier Roumegue <xavier.roumegue@oss.nxp.com>
		15092	L: linux-media@vger.kernel.org
		15093	S: Maintained
		15094	F: Documentation/devicetree/bindings/media/nxp,dw100.yaml
		15095	F: Documentation/userspace-api/media/drivers/dw100.rst
		15096	F: drivers/media/platform/nxp/dw100/
		15097	F: include/uapi/linux/dw100.h
		15098
15066	NXP i.MX 8MQ DCSS DRIVER	15099	NXP i.MX 8MQ DCSS DRIVER
15067	M: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>	15100	M: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
15068	R: Lucas Stach <l.stach@pengutronix.de>	15101	R: Lucas Stach <l.stach@pengutronix.de>
@@ -15080,17 +15113,24 @@ S: Maintained · 11 unmodified lines
15080	F: Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml	15113	F: Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml
15081	F: drivers/iio/adc/imx8qxp-adc.c	15114	F: drivers/iio/adc/imx8qxp-adc.c
15082		15115
15083	NXP i.MX 7D/6SX/6UL/93 AND VF610 ADC DRIVER	15116	NXP i.MX 8QXP/8QM JPEG V4L2 DRIVER
15084	M: Haibo Chen <haibo.chen@nxp.com>	15117	M: Mirela Rabulea <mirela.rabulea@nxp.com>
15085	L: linux-iio@vger.kernel.org	15118	R: NXP Linux Team <linux-imx@nxp.com>
		15119	L: linux-media@vger.kernel.org
		15120	S: Maintained
		15121	F: Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
		15122	F: drivers/media/platform/nxp/imx-jpeg
		15123
		15124	NXP i.MX CLOCK DRIVERS
		15125	M: Abel Vesa <abelvesa@kernel.org>
		15126	R: Peng Fan <peng.fan@nxp.com>
		15127	L: linux-clk@vger.kernel.org
15086	L: linux-imx@nxp.com	15128	L: linux-imx@nxp.com
15087	S: Maintained	15129	S: Maintained
15088	F: Documentation/devicetree/bindings/iio/adc/fsl,imx7d-adc.yaml	15130	T: git git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux.git clk/imx
15089	F: Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml	15131	F: Documentation/devicetree/bindings/clock/imx*
15090	F: Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml	15132	F: drivers/clk/imx/
15091	F: drivers/iio/adc/imx7d_adc.c	15133	F: include/dt-bindings/clock/imx*
15092	F: drivers/iio/adc/imx93_adc.c
15093	F: drivers/iio/adc/vf610_adc.c
15094		15134
15095	NXP PF8100/PF8121A/PF8200 PMIC REGULATOR DEVICE DRIVER	15135	NXP PF8100/PF8121A/PF8200 PMIC REGULATOR DEVICE DRIVER
15096	M: Jagan Teki <jagan@amarulasolutions.com>	15136	M: Jagan Teki <jagan@amarulasolutions.com>
@@ -15136,34 +15176,17 @@ S: Maintained · 39 unmodified lines
15136	F: Documentation/devicetree/bindings/sound/tfa9879.txt	15176	F: Documentation/devicetree/bindings/sound/tfa9879.txt
15137	F: sound/soc/codecs/tfa9879*	15177	F: sound/soc/codecs/tfa9879*
15138		15178
15139	NXP/Goodix TFA989X (TFA1) DRIVER
15140	M: Stephan Gerhold <stephan@gerhold.net>
15141	L: alsa-devel@alsa-project.org (moderated for non-subscribers)
15142	S: Maintained
15143	F: Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml
15144	F: sound/soc/codecs/tfa989x.c
15145
15146	NXP-NCI NFC DRIVER	15179	NXP-NCI NFC DRIVER
15147	S: Orphan	15180	S: Orphan
15148	F: Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml	15181	F: Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml
15149	F: drivers/nfc/nxp-nci	15182	F: drivers/nfc/nxp-nci
15150		15183
15151	NXP i.MX 8MP DW100 V4L2 DRIVER	15184	NXP/Goodix TFA989X (TFA1) DRIVER
15152	M: Xavier Roumegue <xavier.roumegue@oss.nxp.com>	15185	M: Stephan Gerhold <stephan@gerhold.net>
15153	L: linux-media@vger.kernel.org	15186	L: alsa-devel@alsa-project.org (moderated for non-subscribers)
15154	S: Maintained
15155	F: Documentation/devicetree/bindings/media/nxp,dw100.yaml
15156	F: Documentation/userspace-api/media/drivers/dw100.rst
15157	F: drivers/media/platform/nxp/dw100/
15158	F: include/uapi/linux/dw100.h
15159
15160	NXP i.MX 8QXP/8QM JPEG V4L2 DRIVER
15161	M: Mirela Rabulea <mirela.rabulea@nxp.com>
15162	R: NXP Linux Team <linux-imx@nxp.com>
15163	L: linux-media@vger.kernel.org
15164	S: Maintained	15187	S: Maintained
15165	F: Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml	15188	F: Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml
15166	F: drivers/media/platform/nxp/imx-jpeg	15189	F: sound/soc/codecs/tfa989x.c
15167		15190
15168	NZXT-KRAKEN2 HARDWARE MONITORING DRIVER	15191	NZXT-KRAKEN2 HARDWARE MONITORING DRIVER
15169	M: Jonas Malaco <jonas@protocubo.io>	15192	M: Jonas Malaco <jonas@protocubo.io>
@@ -15689,8 +15712,8 @@ M: Rob Herring <robh+dt@kernel.org> · 519 unmodified lines
15689	M: Frank Rowand <frowand.list@gmail.com>	15712	M: Frank Rowand <frowand.list@gmail.com>
15690	L: devicetree@vger.kernel.org	15713	L: devicetree@vger.kernel.org
15691	S: Maintained	15714	S: Maintained
15692	C: irc://irc.libera.chat/devicetree
15693	W: http://www.devicetree.org/	15715	W: http://www.devicetree.org/
		15716	C: irc://irc.libera.chat/devicetree
15694	T: git git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git	15717	T: git git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
15695	F: Documentation/ABI/testing/sysfs-firmware-ofw	15718	F: Documentation/ABI/testing/sysfs-firmware-ofw
15696	F: drivers/of/	15719	F: drivers/of/
@@ -15706,8 +15729,8 @@ M: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> · 9 unmodified lines
15706	M: Conor Dooley <conor+dt@kernel.org>	15729	M: Conor Dooley <conor+dt@kernel.org>
15707	L: devicetree@vger.kernel.org	15730	L: devicetree@vger.kernel.org
15708	S: Maintained	15731	S: Maintained
15709	C: irc://irc.libera.chat/devicetree
15710	Q: http://patchwork.ozlabs.org/project/devicetree-bindings/list/	15732	Q: http://patchwork.ozlabs.org/project/devicetree-bindings/list/
		15733	C: irc://irc.libera.chat/devicetree
15711	T: git git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git	15734	T: git git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
15712	F: Documentation/devicetree/	15735	F: Documentation/devicetree/
15713	F: arch/*/boot/dts/	15736	F: arch/*/boot/dts/
@@ -15720,13 +15743,6 @@ L: netdev@vger.kernel.org · 6 unmodified lines
15720	S: Maintained	15743	S: Maintained
15721	F: drivers/ptp/ptp_ocp.c	15744	F: drivers/ptp/ptp_ocp.c
15722		15745
15723	INTEL PTP DFL ToD DRIVER
15724	M: Tianfei Zhang <tianfei.zhang@intel.com>
15725	L: linux-fpga@vger.kernel.org
15726	L: netdev@vger.kernel.org
15727	S: Maintained
15728	F: drivers/ptp/ptp_dfl_tod.c
15729
15730	OPENCORES I2C BUS DRIVER	15746	OPENCORES I2C BUS DRIVER
15731	M: Peter Korsgaard <peter@korsgaard.com>	15747	M: Peter Korsgaard <peter@korsgaard.com>
15732	M: Andrew Lunn <andrew@lunn.ch>	15748	M: Andrew Lunn <andrew@lunn.ch>
@@ -15745,8 +15761,8 @@ L: linux-openrisc@vger.kernel.org · 12 unmodified lines
15745	S: Maintained	15761	S: Maintained
15746	W: http://openrisc.io	15762	W: http://openrisc.io
15747	T: git https://github.com/openrisc/linux.git	15763	T: git https://github.com/openrisc/linux.git
15748	F: Documentation/devicetree/bindings/openrisc/
15749	F: Documentation/arch/openrisc/	15764	F: Documentation/arch/openrisc/
		15765	F: Documentation/devicetree/bindings/openrisc/
15750	F: arch/openrisc/	15766	F: arch/openrisc/
15751	F: drivers/irqchip/irq-ompic.c	15767	F: drivers/irqchip/irq-ompic.c
15752	F: drivers/irqchip/irq-or1k-*	15768	F: drivers/irqchip/irq-or1k-*
@@ -16062,6 +16078,14 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) · 309 unmodified lines
16062	S: Maintained	16078	S: Maintained
16063	F: drivers/pci/controller/dwc/layerscape	16079	F: drivers/pci/controller/dwc/layerscape
16064		16080
		16081	PCI DRIVER FOR FU740
		16082	M: Paul Walmsley <paul.walmsley@sifive.com>
		16083	M: Greentime Hu <greentime.hu@sifive.com>
		16084	L: linux-pci@vger.kernel.org
		16085	S: Maintained
		16086	F: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
		16087	F: drivers/pci/controller/dwc/pcie-fu740.c
		16088
16065	PCI DRIVER FOR GENERIC OF HOSTS	16089	PCI DRIVER FOR GENERIC OF HOSTS
16066	M: Will Deacon <will@kernel.org>	16090	M: Will Deacon <will@kernel.org>
16067	L: linux-pci@vger.kernel.org	16091	L: linux-pci@vger.kernel.org
@@ -16082,14 +16106,6 @@ F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml · 14 unmodified lines
16082	F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml	16106	F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
16083	F: drivers/pci/controller/dwc/imx6	16107	F: drivers/pci/controller/dwc/imx6
16084		16108
16085	PCI DRIVER FOR FU740
16086	M: Paul Walmsley <paul.walmsley@sifive.com>
16087	M: Greentime Hu <greentime.hu@sifive.com>
16088	L: linux-pci@vger.kernel.org
16089	S: Maintained
16090	F: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
16091	F: drivers/pci/controller/dwc/pcie-fu740.c
16092
16093	PCI DRIVER FOR INTEL IXP4XX	16109	PCI DRIVER FOR INTEL IXP4XX
16094	M: Linus Walleij <linus.walleij@linaro.org>	16110	M: Linus Walleij <linus.walleij@linaro.org>
16095	S: Maintained	16111	S: Maintained
@@ -16169,8 +16185,8 @@ M: Jingoo Han <jingoohan1@gmail.com> · 73 unmodified lines
16169	M: Gustavo Pimentel <gustavo.pimentel@synopsys.com>	16185	M: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16170	L: linux-pci@vger.kernel.org	16186	L: linux-pci@vger.kernel.org
16171	S: Maintained	16187	S: Maintained
16172	F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
16173	F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml	16188	F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
		16189	F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
16174	F: drivers/pci/controller/dwc/designware	16190	F: drivers/pci/controller/dwc/designware
16175		16191
16176	PCI DRIVER FOR TI DRA7XX/J721E	16192	PCI DRIVER FOR TI DRA7XX/J721E
@@ -16190,6 +16206,14 @@ S: Maintained · 13 unmodified lines
16190	F: Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt	16206	F: Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
16191	F: drivers/pci/controller/pci-v3-semi.c	16207	F: drivers/pci/controller/pci-v3-semi.c
16192		16208
		16209	PCI DRIVER FOR XILINX VERSAL CPM
		16210	M: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
		16211	M: Michal Simek <michal.simek@amd.com>
		16212	L: linux-pci@vger.kernel.org
		16213	S: Maintained
		16214	F: Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
		16215	F: drivers/pci/controller/pcie-xilinx-cpm.c
		16216
16193	PCI ENDPOINT SUBSYSTEM	16217	PCI ENDPOINT SUBSYSTEM
16194	M: Lorenzo Pieralisi <lpieralisi@kernel.org>	16218	M: Lorenzo Pieralisi <lpieralisi@kernel.org>
16195	M: Krzysztof Wilczyński <kw@linux.com>	16219	M: Krzysztof Wilczyński <kw@linux.com>
@@ -16227,19 +16251,6 @@ L: linux-pci@vger.kernel.org · 31 unmodified lines
16227	S: Supported	16251	S: Supported
16228	F: Documentation/PCI/pci-error-recovery.rst	16252	F: Documentation/PCI/pci-error-recovery.rst
16229		16253
16230	PCI PEER-TO-PEER DMA (P2PDMA)
16231	M: Bjorn Helgaas <bhelgaas@google.com>
16232	M: Logan Gunthorpe <logang@deltatee.com>
16233	L: linux-pci@vger.kernel.org
16234	S: Supported
16235	Q: https://patchwork.kernel.org/project/linux-pci/list/
16236	B: https://bugzilla.kernel.org
16237	C: irc://irc.oftc.net/linux-pci
16238	T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
16239	F: Documentation/driver-api/pci/p2pdma.rst
16240	F: drivers/pci/p2pdma.c
16241	F: include/linux/pci-p2pdma.h
16242
16243	PCI MSI DRIVER FOR ALTERA MSI IP	16254	PCI MSI DRIVER FOR ALTERA MSI IP
16244	M: Joyce Ooi <joyce.ooi@intel.com>	16255	M: Joyce Ooi <joyce.ooi@intel.com>
16245	L: linux-pci@vger.kernel.org	16256	L: linux-pci@vger.kernel.org
@@ -16270,6 +16281,19 @@ F: drivers/pci/controller/ · 24 unmodified lines
16270	F: drivers/pci/pci-bridge-emul.c	16281	F: drivers/pci/pci-bridge-emul.c
16271	F: drivers/pci/pci-bridge-emul.h	16282	F: drivers/pci/pci-bridge-emul.h
16272		16283
		16284	PCI PEER-TO-PEER DMA (P2PDMA)
		16285	M: Bjorn Helgaas <bhelgaas@google.com>
		16286	M: Logan Gunthorpe <logang@deltatee.com>
		16287	L: linux-pci@vger.kernel.org
		16288	S: Supported
		16289	Q: https://patchwork.kernel.org/project/linux-pci/list/
		16290	B: https://bugzilla.kernel.org
		16291	C: irc://irc.oftc.net/linux-pci
		16292	T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
		16293	F: Documentation/driver-api/pci/p2pdma.rst
		16294	F: drivers/pci/p2pdma.c
		16295	F: include/linux/pci-p2pdma.h
		16296
16273	PCI SUBSYSTEM	16297	PCI SUBSYSTEM
16274	M: Bjorn Helgaas <bhelgaas@google.com>	16298	M: Bjorn Helgaas <bhelgaas@google.com>
16275	L: linux-pci@vger.kernel.org	16299	L: linux-pci@vger.kernel.org
@@ -16378,14 +16402,6 @@ L: linux-arm-msm@vger.kernel.org · 102 unmodified lines
16378	S: Maintained	16402	S: Maintained
16379	F: drivers/pci/controller/dwc/pcie-qcom.c	16403	F: drivers/pci/controller/dwc/pcie-qcom.c
16380		16404
16381	PCIE ENDPOINT DRIVER FOR QUALCOMM
16382	M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
16383	L: linux-pci@vger.kernel.org
16384	L: linux-arm-msm@vger.kernel.org
16385	S: Maintained
16386	F: Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
16387	F: drivers/pci/controller/dwc/pcie-qcom-ep.c
16388
16389	PCIE DRIVER FOR ROCKCHIP	16405	PCIE DRIVER FOR ROCKCHIP
16390	M: Shawn Lin <shawn.lin@rock-chips.com>	16406	M: Shawn Lin <shawn.lin@rock-chips.com>
16391	L: linux-pci@vger.kernel.org	16407	L: linux-pci@vger.kernel.org
@@ -16407,13 +16423,13 @@ L: linux-pci@vger.kernel.org · 15 unmodified lines
16407	S: Maintained	16423	S: Maintained
16408	F: drivers/pci/controller/dwc/spear	16424	F: drivers/pci/controller/dwc/spear
16409		16425
16410	PCI DRIVER FOR XILINX VERSAL CPM	16426	PCIE ENDPOINT DRIVER FOR QUALCOMM
16411	M: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>	16427	M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
16412	M: Michal Simek <michal.simek@amd.com>
16413	L: linux-pci@vger.kernel.org	16428	L: linux-pci@vger.kernel.org
		16429	L: linux-arm-msm@vger.kernel.org
16414	S: Maintained	16430	S: Maintained
16415	F: Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml	16431	F: Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
16416	F: drivers/pci/controller/pcie-xilinx-cpm.c	16432	F: drivers/pci/controller/dwc/pcie-qcom-ep.c
16417		16433
16418	PCMCIA SUBSYSTEM	16434	PCMCIA SUBSYSTEM
16419	M: Dominik Brodowski <linux@dominikbrodowski.net>	16435	M: Dominik Brodowski <linux@dominikbrodowski.net>
@@ -16683,9 +16699,9 @@ R: Alim Akhtar <alim.akhtar@samsung.com> · 263 unmodified lines
16683	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)	16699	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
16684	L: linux-samsung-soc@vger.kernel.org	16700	L: linux-samsung-soc@vger.kernel.org
16685	S: Maintained	16701	S: Maintained
16686	C: irc://irc.libera.chat/linux-exynos
16687	Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/	16702	Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
16688	B: mailto:linux-samsung-soc@vger.kernel.org	16703	B: mailto:linux-samsung-soc@vger.kernel.org
		16704	C: irc://irc.libera.chat/linux-exynos
16689	T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git	16705	T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git
16690	F: Documentation/devicetree/bindings/pinctrl/samsung,pinctrl*yaml	16706	F: Documentation/devicetree/bindings/pinctrl/samsung,pinctrl*yaml
16691	F: drivers/pinctrl/samsung/	16707	F: drivers/pinctrl/samsung/
@@ -16747,13 +16763,6 @@ M: Logan Gunthorpe <logang@deltatee.com> · 55 unmodified lines
16747	S: Maintained	16763	S: Maintained
16748	F: drivers/dma/plx_dma.c	16764	F: drivers/dma/plx_dma.c
16749		16765
16750	PM6764TR DRIVER
16751	M: Charles Hsu <hsu.yungteng@gmail.com>
16752	L: linux-hwmon@vger.kernel.org
16753	S: Maintained
16754	F: Documentation/hwmon/pm6764tr.rst
16755	F: drivers/hwmon/pmbus/pm6764tr.c
16756
16757	PM-GRAPH UTILITY	16766	PM-GRAPH UTILITY
16758	M: "Todd E Brandt" <todd.e.brandt@linux.intel.com>	16767	M: "Todd E Brandt" <todd.e.brandt@linux.intel.com>
16759	L: linux-pm@vger.kernel.org	16768	L: linux-pm@vger.kernel.org
@@ -16763,6 +16772,13 @@ B: https://bugzilla.kernel.org/buglist.cgi?component=pm-graph&product=Tools · 3 unmodified lines
16763	T: git git://github.com/intel/pm-graph	16772	T: git git://github.com/intel/pm-graph
16764	F: tools/power/pm-graph	16773	F: tools/power/pm-graph
16765		16774
		16775	PM6764TR DRIVER
		16776	M: Charles Hsu <hsu.yungteng@gmail.com>
		16777	L: linux-hwmon@vger.kernel.org
		16778	S: Maintained
		16779	F: Documentation/hwmon/pm6764tr.rst
		16780	F: drivers/hwmon/pmbus/pm6764tr.c
		16781
16766	PMBUS HARDWARE MONITORING DRIVERS	16782	PMBUS HARDWARE MONITORING DRIVERS
16767	M: Guenter Roeck <linux@roeck-us.net>	16783	M: Guenter Roeck <linux@roeck-us.net>
16768	L: linux-hwmon@vger.kernel.org	16784	L: linux-hwmon@vger.kernel.org
@@ -16843,15 +16859,6 @@ F: include/linux/pm_* · 74 unmodified lines
16843	F: include/linux/powercap.h	16859	F: include/linux/powercap.h
16844	F: kernel/configs/nopm.config	16860	F: kernel/configs/nopm.config
16845		16861
16846	DYNAMIC THERMAL POWER MANAGEMENT (DTPM)
16847	M: Daniel Lezcano <daniel.lezcano@kernel.org>
16848	L: linux-pm@vger.kernel.org
16849	S: Supported
16850	B: https://bugzilla.kernel.org
16851	T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
16852	F: drivers/powercap/dtpm*
16853	F: include/linux/dtpm.h
16854
16855	POWER STATE COORDINATION INTERFACE (PSCI)	16862	POWER STATE COORDINATION INTERFACE (PSCI)
16856	M: Mark Rutland <mark.rutland@arm.com>	16863	M: Mark Rutland <mark.rutland@arm.com>
16857	M: Lorenzo Pieralisi <lpieralisi@kernel.org>	16864	M: Lorenzo Pieralisi <lpieralisi@kernel.org>
@@ -17010,8 +17017,8 @@ R: Guilherme G. Piccoli <gpiccoli@igalia.com> · 152 unmodified lines
17010	L: linux-hardening@vger.kernel.org	17017	L: linux-hardening@vger.kernel.org
17011	S: Supported	17018	S: Supported
17012	T: git git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git for-next/pstore	17019	T: git git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git for-next/pstore
17013	F: Documentation/admin-guide/ramoops.rst
17014	F: Documentation/admin-guide/pstore-blk.rst	17020	F: Documentation/admin-guide/pstore-blk.rst
		17021	F: Documentation/admin-guide/ramoops.rst
17015	F: Documentation/devicetree/bindings/reserved-memory/ramoops.yaml	17022	F: Documentation/devicetree/bindings/reserved-memory/ramoops.yaml
17016	F: drivers/acpi/apei/erst.c	17023	F: drivers/acpi/apei/erst.c
17017	F: drivers/firmware/efi/efi-pstore.c	17024	F: drivers/firmware/efi/efi-pstore.c
@@ -17160,10 +17167,10 @@ F: sound/soc/codecs/lpass-va-macro.c · 142 unmodified lines
17160	F: sound/soc/codecs/lpass-wsa-macro.*	17167	F: sound/soc/codecs/lpass-wsa-macro.*
17161	F: sound/soc/codecs/msm8916-wcd-analog.c	17168	F: sound/soc/codecs/msm8916-wcd-analog.c
17162	F: sound/soc/codecs/msm8916-wcd-digital.c	17169	F: sound/soc/codecs/msm8916-wcd-digital.c
17163	F: sound/soc/codecs/wcd9335.*
17164	F: sound/soc/codecs/wcd934x.c
17165	F: sound/soc/codecs/wcd-clsh-v2.*	17170	F: sound/soc/codecs/wcd-clsh-v2.*
17166	F: sound/soc/codecs/wcd-mbhc-v2.*	17171	F: sound/soc/codecs/wcd-mbhc-v2.*
		17172	F: sound/soc/codecs/wcd9335.*
		17173	F: sound/soc/codecs/wcd934x.c
17167	F: sound/soc/codecs/wsa881x.c	17174	F: sound/soc/codecs/wsa881x.c
17168	F: sound/soc/codecs/wsa883x.c	17175	F: sound/soc/codecs/wsa883x.c
17169	F: sound/soc/qcom/	17176	F: sound/soc/qcom/
@@ -17320,14 +17327,21 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/ · 150 unmodified lines
17320	T: git git://linuxtv.org/anttip/media_tree.git	17327	T: git git://linuxtv.org/anttip/media_tree.git
17321	F: drivers/media/tuners/qt1010*	17328	F: drivers/media/tuners/qt1010*
17322		17329
		17330	QUALCOMM ATH12K WIRELESS DRIVER
		17331	M: Kalle Valo <kvalo@kernel.org>
		17332	L: ath12k@lists.infradead.org
		17333	S: Supported
		17334	T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
		17335	F: drivers/net/wireless/ath/ath12k/
		17336
17323	QUALCOMM ATHEROS ATH10K WIRELESS DRIVER	17337	QUALCOMM ATHEROS ATH10K WIRELESS DRIVER
17324	M: Kalle Valo <kvalo@kernel.org>	17338	M: Kalle Valo <kvalo@kernel.org>
17325	L: ath10k@lists.infradead.org	17339	L: ath10k@lists.infradead.org
17326	S: Supported	17340	S: Supported
17327	W: https://wireless.wiki.kernel.org/en/users/Drivers/ath10k	17341	W: https://wireless.wiki.kernel.org/en/users/Drivers/ath10k
17328	T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git	17342	T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
17329	F: drivers/net/wireless/ath/ath10k/
17330	F: Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml	17343	F: Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml
		17344	F: drivers/net/wireless/ath/ath10k/
17331		17345
17332	QUALCOMM ATHEROS ATH11K WIRELESS DRIVER	17346	QUALCOMM ATHEROS ATH11K WIRELESS DRIVER
17333	M: Kalle Valo <kvalo@kernel.org>	17347	M: Kalle Valo <kvalo@kernel.org>
@@ -17337,13 +17351,6 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git · 3 unmodified lines
17337	F: Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml	17351	F: Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
17338	F: drivers/net/wireless/ath/ath11k/	17352	F: drivers/net/wireless/ath/ath11k/
17339		17353
17340	QUALCOMM ATH12K WIRELESS DRIVER
17341	M: Kalle Valo <kvalo@kernel.org>
17342	L: ath12k@lists.infradead.org
17343	S: Supported
17344	T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
17345	F: drivers/net/wireless/ath/ath12k/
17346
17347	QUALCOMM ATHEROS ATH9K WIRELESS DRIVER	17354	QUALCOMM ATHEROS ATH9K WIRELESS DRIVER
17348	M: Toke Høiland-Jørgensen <toke@toke.dk>	17355	M: Toke Høiland-Jørgensen <toke@toke.dk>
17349	L: linux-wireless@vger.kernel.org	17356	L: linux-wireless@vger.kernel.org
@@ -17440,8 +17447,8 @@ F: include/uapi/misc/fastrpc.h · 90 unmodified lines
17440	QUALCOMM HEXAGON ARCHITECTURE	17447	QUALCOMM HEXAGON ARCHITECTURE
17441	M: Brian Cain <bcain@quicinc.com>	17448	M: Brian Cain <bcain@quicinc.com>
17442	L: linux-hexagon@vger.kernel.org	17449	L: linux-hexagon@vger.kernel.org
17443	T: git git://git.kernel.org/pub/scm/linux/kernel/git/bcain/linux.git
17444	S: Supported	17450	S: Supported
		17451	T: git git://git.kernel.org/pub/scm/linux/kernel/git/bcain/linux.git
17445	F: arch/hexagon/	17452	F: arch/hexagon/
17446		17453
17447	QUALCOMM HIDMA DRIVER	17454	QUALCOMM HIDMA DRIVER
@@ -17563,9 +17570,9 @@ M: Christian König <christian.koenig@amd.com> · 115 unmodified lines
17563	M: Pan, Xinhui <Xinhui.Pan@amd.com>	17570	M: Pan, Xinhui <Xinhui.Pan@amd.com>
17564	L: amd-gfx@lists.freedesktop.org	17571	L: amd-gfx@lists.freedesktop.org
17565	S: Supported	17572	S: Supported
17566	T: git https://gitlab.freedesktop.org/agd5f/linux.git
17567	B: https://gitlab.freedesktop.org/drm/amd/-/issues	17573	B: https://gitlab.freedesktop.org/drm/amd/-/issues
17568	C: irc://irc.oftc.net/radeon	17574	C: irc://irc.oftc.net/radeon
		17575	T: git https://gitlab.freedesktop.org/agd5f/linux.git
17569	F: Documentation/gpu/amdgpu/	17576	F: Documentation/gpu/amdgpu/
17570	F: drivers/gpu/drm/amd/	17577	F: drivers/gpu/drm/amd/
17571	F: drivers/gpu/drm/radeon/	17578	F: drivers/gpu/drm/radeon/
@@ -17653,8 +17660,8 @@ F: arch/mips/generic/board-ranchu.c · 81 unmodified lines
17653	RANDOM NUMBER DRIVER	17660	RANDOM NUMBER DRIVER
17654	M: "Theodore Ts'o" <tytso@mit.edu>	17661	M: "Theodore Ts'o" <tytso@mit.edu>
17655	M: Jason A. Donenfeld <Jason@zx2c4.com>	17662	M: Jason A. Donenfeld <Jason@zx2c4.com>
17656	T: git https://git.kernel.org/pub/scm/linux/kernel/git/crng/random.git
17657	S: Maintained	17663	S: Maintained
		17664	T: git https://git.kernel.org/pub/scm/linux/kernel/git/crng/random.git
17658	F: drivers/char/random.c	17665	F: drivers/char/random.c
17659	F: drivers/virt/vmgenid.c	17666	F: drivers/virt/vmgenid.c
17660		17667
@@ -17688,8 +17695,8 @@ T: git git://linuxtv.org/media_tree.git · 27 unmodified lines
17688	F: Documentation/driver-api/media/rc-core.rst	17695	F: Documentation/driver-api/media/rc-core.rst
17689	F: Documentation/userspace-api/media/rc/	17696	F: Documentation/userspace-api/media/rc/
17690	F: drivers/media/rc/	17697	F: drivers/media/rc/
17691	F: include/media/rc-map.h
17692	F: include/media/rc-core.h	17698	F: include/media/rc-core.h
		17699	F: include/media/rc-map.h
17693	F: include/uapi/linux/lirc.h	17700	F: include/uapi/linux/lirc.h
17694		17701
17695	RCMM REMOTE CONTROLS DECODER	17702	RCMM REMOTE CONTROLS DECODER
@@ -17806,6 +17813,14 @@ F: include/linux/rtc/ · 110 unmodified lines
17806	F: include/uapi/linux/rtc.h	17813	F: include/uapi/linux/rtc.h
17807	F: tools/testing/selftests/rtc/	17814	F: tools/testing/selftests/rtc/
17808		17815
		17816	Real-time Linux Analysis (RTLA) tools
		17817	M: Daniel Bristot de Oliveira <bristot@kernel.org>
		17818	M: Steven Rostedt <rostedt@goodmis.org>
		17819	L: linux-trace-devel@vger.kernel.org
		17820	S: Maintained
		17821	F: Documentation/tools/rtla/
		17822	F: tools/tracing/rtla/
		17823
17809	REALTEK AUDIO CODECS	17824	REALTEK AUDIO CODECS
17810	M: Oder Chiou <oder_chiou@realtek.com>	17825	M: Oder Chiou <oder_chiou@realtek.com>
17811	S: Maintained	17826	S: Maintained
@@ -17929,6 +17944,14 @@ S: Maintained · 117 unmodified lines
17929	F: Documentation/devicetree/bindings/sound/renesas,idt821034.yaml	17944	F: Documentation/devicetree/bindings/sound/renesas,idt821034.yaml
17930	F: sound/soc/codecs/idt821034.c	17945	F: sound/soc/codecs/idt821034.c
17931		17946
		17947	RENESAS R-CAR GEN3 & RZ/N1 NAND CONTROLLER DRIVER
		17948	M: Miquel Raynal <miquel.raynal@bootlin.com>
		17949	L: linux-mtd@lists.infradead.org
		17950	L: linux-renesas-soc@vger.kernel.org
		17951	S: Maintained
		17952	F: Documentation/devicetree/bindings/mtd/renesas-nandc.yaml
		17953	F: drivers/mtd/nand/raw/renesas-nand-controller.c
		17954
17932	RENESAS R-CAR GYROADC DRIVER	17955	RENESAS R-CAR GYROADC DRIVER
17933	M: Marek Vasut <marek.vasut@gmail.com>	17956	M: Marek Vasut <marek.vasut@gmail.com>
17934	L: linux-iio@vger.kernel.org	17957	L: linux-iio@vger.kernel.org
@@ -17947,9 +17970,9 @@ F: drivers/i2c/busses/i2c-sh_mobile.c · 12 unmodified lines
17947		17970
17948	RENESAS R-CAR SATA DRIVER	17971	RENESAS R-CAR SATA DRIVER
17949	R: Sergey Shtylyov <s.shtylyov@omp.ru>	17972	R: Sergey Shtylyov <s.shtylyov@omp.ru>
17950	S: Supported
17951	L: linux-ide@vger.kernel.org	17973	L: linux-ide@vger.kernel.org
17952	L: linux-renesas-soc@vger.kernel.org	17974	L: linux-renesas-soc@vger.kernel.org
		17975	S: Supported
17953	F: Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml	17976	F: Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
17954	F: drivers/ata/sata_rcar.c	17977	F: drivers/ata/sata_rcar.c
17955		17978
@@ -17969,12 +17992,6 @@ S: Supported · 13 unmodified lines
17969	F: Documentation/devicetree/bindings/i2c/renesas,riic.yaml	17992	F: Documentation/devicetree/bindings/i2c/renesas,riic.yaml
17970	F: drivers/i2c/busses/i2c-riic.c	17993	F: drivers/i2c/busses/i2c-riic.c
17971		17994
17972	RENESAS USB PHY DRIVER
17973	M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
17974	L: linux-renesas-soc@vger.kernel.org
17975	S: Maintained
17976	F: drivers/phy/renesas/phy-rcar-gen3-usb*.c
17977
17978	RENESAS RZ/G2L A/D DRIVER	17995	RENESAS RZ/G2L A/D DRIVER
17979	M: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>	17996	M: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17980	L: linux-iio@vger.kernel.org	17997	L: linux-iio@vger.kernel.org
@@ -18020,13 +18037,11 @@ S: Maintained · 39 unmodified lines
18020	F: Documentation/devicetree/bindings/usb/renesas,rzn1-usbf.yaml	18037	F: Documentation/devicetree/bindings/usb/renesas,rzn1-usbf.yaml
18021	F: drivers/usb/gadget/udc/renesas_usbf.c	18038	F: drivers/usb/gadget/udc/renesas_usbf.c
18022		18039
18023	RENESAS R-CAR GEN3 & RZ/N1 NAND CONTROLLER DRIVER	18040	RENESAS USB PHY DRIVER
18024	M: Miquel Raynal <miquel.raynal@bootlin.com>	18041	M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
18025	L: linux-mtd@lists.infradead.org
18026	L: linux-renesas-soc@vger.kernel.org	18042	L: linux-renesas-soc@vger.kernel.org
18027	S: Maintained	18043	S: Maintained
18028	F: Documentation/devicetree/bindings/mtd/renesas-nandc.yaml	18044	F: drivers/phy/renesas/phy-rcar-gen3-usb*.c
18029	F: drivers/mtd/nand/raw/renesas-nand-controller.c
18030		18045
18031	RENESAS VERSACLOCK 7 CLOCK DRIVER	18046	RENESAS VERSACLOCK 7 CLOCK DRIVER
18032	M: Alex Helms <alexander.helms.jy@renesas.com>	18047	M: Alex Helms <alexander.helms.jy@renesas.com>
@@ -18094,15 +18109,6 @@ S: Maintained · 61 unmodified lines
18094	F: drivers/mtd/nand/raw/r852.c	18109	F: drivers/mtd/nand/raw/r852.c
18095	F: drivers/mtd/nand/raw/r852.h	18110	F: drivers/mtd/nand/raw/r852.h
18096		18111
18097	RISC-V PMU DRIVERS
18098	M: Atish Patra <atishp@atishpatra.org>
18099	R: Anup Patel <anup@brainfault.org>
18100	L: linux-riscv@lists.infradead.org
18101	S: Supported
18102	F: drivers/perf/riscv_pmu.c
18103	F: drivers/perf/riscv_pmu_legacy.c
18104	F: drivers/perf/riscv_pmu_sbi.c
18105
18106	RISC-V ARCHITECTURE	18112	RISC-V ARCHITECTURE
18107	M: Paul Walmsley <paul.walmsley@sifive.com>	18113	M: Paul Walmsley <paul.walmsley@sifive.com>
18108	M: Palmer Dabbelt <palmer@dabbelt.com>	18114	M: Palmer Dabbelt <palmer@dabbelt.com>
@@ -18155,6 +18161,15 @@ T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ · 46 unmodified lines
18155	F: Documentation/devicetree/bindings/riscv/	18161	F: Documentation/devicetree/bindings/riscv/
18156	F: arch/riscv/boot/dts/	18162	F: arch/riscv/boot/dts/
18157		18163
		18164	RISC-V PMU DRIVERS
		18165	M: Atish Patra <atishp@atishpatra.org>
		18166	R: Anup Patel <anup@brainfault.org>
		18167	L: linux-riscv@lists.infradead.org
		18168	S: Supported
		18169	F: drivers/perf/riscv_pmu.c
		18170	F: drivers/perf/riscv_pmu_legacy.c
		18171	F: drivers/perf/riscv_pmu_sbi.c
		18172
18158	RNBD BLOCK DRIVERS	18173	RNBD BLOCK DRIVERS
18159	M: Md. Haris Iqbal <haris.iqbal@ionos.com>	18174	M: Md. Haris Iqbal <haris.iqbal@ionos.com>
18160	M: Jack Wang <jinpu.wang@ionos.com>	18175	M: Jack Wang <jinpu.wang@ionos.com>
@@ -18459,14 +18474,6 @@ F: drivers/s390/net/iucv · 298 unmodified lines
18459	F: include/net/iucv/	18474	F: include/net/iucv/
18460	F: net/iucv/	18475	F: net/iucv/
18461		18476
18462	S390 NETWORK DRIVERS
18463	M: Alexandra Winter <wintera@linux.ibm.com>
18464	M: Wenjia Zhang <wenjia@linux.ibm.com>
18465	L: linux-s390@vger.kernel.org
18466	L: netdev@vger.kernel.org
18467	S: Supported
18468	F: drivers/s390/net/
18469
18470	S390 MM	18477	S390 MM
18471	M: Alexander Gordeev <agordeev@linux.ibm.com>	18478	M: Alexander Gordeev <agordeev@linux.ibm.com>
18472	M: Gerald Schaefer <gerald.schaefer@linux.ibm.com>	18479	M: Gerald Schaefer <gerald.schaefer@linux.ibm.com>
@@ -18476,14 +18483,22 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux.git · 3 unmodified lines
18476	F: arch/s390/include/asm/pgtable.h	18483	F: arch/s390/include/asm/pgtable.h
18477	F: arch/s390/mm	18484	F: arch/s390/mm
18478		18485
		18486	S390 NETWORK DRIVERS
		18487	M: Alexandra Winter <wintera@linux.ibm.com>
		18488	M: Wenjia Zhang <wenjia@linux.ibm.com>
		18489	L: linux-s390@vger.kernel.org
		18490	L: netdev@vger.kernel.org
		18491	S: Supported
		18492	F: drivers/s390/net/
		18493
18479	S390 PCI SUBSYSTEM	18494	S390 PCI SUBSYSTEM
18480	M: Niklas Schnelle <schnelle@linux.ibm.com>	18495	M: Niklas Schnelle <schnelle@linux.ibm.com>
18481	M: Gerald Schaefer <gerald.schaefer@linux.ibm.com>	18496	M: Gerald Schaefer <gerald.schaefer@linux.ibm.com>
18482	L: linux-s390@vger.kernel.org	18497	L: linux-s390@vger.kernel.org
18483	S: Supported	18498	S: Supported
		18499	F: Documentation/s390/pci.rst
18484	F: arch/s390/pci/	18500	F: arch/s390/pci/
18485	F: drivers/pci/hotplug/s390_pci_hpc.c	18501	F: drivers/pci/hotplug/s390_pci_hpc.c
18486	F: Documentation/s390/pci.rst
18487		18502
18488	S390 SCM DRIVER	18503	S390 SCM DRIVER
18489	M: Vineeth Vijayan <vneethv@linux.ibm.com>	18504	M: Vineeth Vijayan <vneethv@linux.ibm.com>
@@ -18916,6 +18931,13 @@ L: linux-mmc@vger.kernel.org · 426 unmodified lines
18916	S: Supported	18931	S: Supported
18917	F: drivers/mmc/host/sdhci-of-at91.c	18932	F: drivers/mmc/host/sdhci-of-at91.c
18918		18933
		18934	SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) NXP i.MX DRIVER
		18935	M: Haibo Chen <haibo.chen@nxp.com>
		18936	L: linux-imx@nxp.com
		18937	L: linux-mmc@vger.kernel.org
		18938	S: Maintained
		18939	F: drivers/mmc/host/sdhci-esdhc-imx.c
		18940
18919	SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) SAMSUNG DRIVER	18941	SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) SAMSUNG DRIVER
18920	M: Ben Dooks <ben-linux@fluff.org>	18942	M: Ben Dooks <ben-linux@fluff.org>
18921	M: Jaehoon Chung <jh80.chung@samsung.com>	18943	M: Jaehoon Chung <jh80.chung@samsung.com>
@@ -18935,13 +18957,6 @@ L: linux-mmc@vger.kernel.org · 13 unmodified lines
18935	S: Maintained	18957	S: Maintained
18936	F: drivers/mmc/host/sdhci-omap.c	18958	F: drivers/mmc/host/sdhci-omap.c
18937		18959
18938	SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) NXP i.MX DRIVER
18939	M: Haibo Chen <haibo.chen@nxp.com>
18940	L: linux-imx@nxp.com
18941	L: linux-mmc@vger.kernel.org
18942	S: Maintained
18943	F: drivers/mmc/host/sdhci-esdhc-imx.c
18944
18945	SECURE ENCRYPTING DEVICE (SED) OPAL DRIVER	18960	SECURE ENCRYPTING DEVICE (SED) OPAL DRIVER
18946	M: Jonathan Derrick <jonathan.derrick@linux.dev>	18961	M: Jonathan Derrick <jonathan.derrick@linux.dev>
18947	L: linux-block@vger.kernel.org	18962	L: linux-block@vger.kernel.org
@@ -18951,6 +18966,15 @@ F: block/sed* · 3 unmodified lines
18951	F: include/linux/sed*	18966	F: include/linux/sed*
18952	F: include/uapi/linux/sed*	18967	F: include/uapi/linux/sed*
18953		18968
		18969	SECURE MONITOR CALL(SMC) CALLING CONVENTION (SMCCC)
		18970	M: Mark Rutland <mark.rutland@arm.com>
		18971	M: Lorenzo Pieralisi <lpieralisi@kernel.org>
		18972	M: Sudeep Holla <sudeep.holla@arm.com>
		18973	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
		18974	S: Maintained
		18975	F: drivers/firmware/smccc/
		18976	F: include/linux/arm-smccc.h
		18977
18954	SECURITY CONTACT	18978	SECURITY CONTACT
18955	M: Security Officers <security@kernel.org>	18979	M: Security Officers <security@kernel.org>
18956	S: Supported	18980	S: Supported
@@ -19400,15 +19424,6 @@ M: Nicolas Pitre <nico@fluxnic.net> · 443 unmodified lines
19400	S: Odd Fixes	19424	S: Odd Fixes
19401	F: drivers/net/ethernet/smsc/smc91x.*	19425	F: drivers/net/ethernet/smsc/smc91x.*
19402		19426
19403	SECURE MONITOR CALL(SMC) CALLING CONVENTION (SMCCC)
19404	M: Mark Rutland <mark.rutland@arm.com>
19405	M: Lorenzo Pieralisi <lpieralisi@kernel.org>
19406	M: Sudeep Holla <sudeep.holla@arm.com>
19407	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
19408	S: Maintained
19409	F: drivers/firmware/smccc/
19410	F: include/linux/arm-smccc.h
19411
19412	SMM665 HARDWARE MONITOR DRIVER	19427	SMM665 HARDWARE MONITOR DRIVER
19413	M: Guenter Roeck <linux@roeck-us.net>	19428	M: Guenter Roeck <linux@roeck-us.net>
19414	L: linux-hwmon@vger.kernel.org	19429	L: linux-hwmon@vger.kernel.org
@@ -19456,6 +19471,10 @@ L: netdev@vger.kernel.org · 41 unmodified lines
19456	S: Maintained	19471	S: Maintained
19457	F: drivers/net/ethernet/smsc/smsc9420.*	19472	F: drivers/net/ethernet/smsc/smsc9420.*
19458		19473
		19474	SNET DPU VIRTIO DATA PATH ACCELERATOR
		19475	R: Alvaro Karsz <alvaro.karsz@solid-run.com>
		19476	F: drivers/vdpa/solidrun/
		19477
19459	SOCIONEXT (SNI) AVE NETWORK DRIVER	19478	SOCIONEXT (SNI) AVE NETWORK DRIVER
19460	M: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>	19479	M: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19461	L: netdev@vger.kernel.org	19480	L: netdev@vger.kernel.org
@@ -19725,6 +19744,13 @@ F: include/uapi/sound/ · 263 unmodified lines
19725	F: sound/	19744	F: sound/
19726	F: tools/testing/selftests/alsa	19745	F: tools/testing/selftests/alsa
19727		19746
		19747	SOUND - ALSA SELFTESTS
		19748	M: Mark Brown <broonie@kernel.org>
		19749	L: alsa-devel@alsa-project.org (moderated for non-subscribers)
		19750	L: linux-kselftest@vger.kernel.org
		19751	S: Supported
		19752	F: tools/testing/selftests/alsa
		19753
19728	SOUND - COMPRESSED AUDIO	19754	SOUND - COMPRESSED AUDIO
19729	M: Vinod Koul <vkoul@kernel.org>	19755	M: Vinod Koul <vkoul@kernel.org>
19730	L: alsa-devel@alsa-project.org (moderated for non-subscribers)	19756	L: alsa-devel@alsa-project.org (moderated for non-subscribers)
@@ -19743,13 +19769,6 @@ F: include/sound/dmaengine_pcm.h · 12 unmodified lines
19743	F: sound/core/pcm_dmaengine.c	19769	F: sound/core/pcm_dmaengine.c
19744	F: sound/soc/soc-generic-dmaengine-pcm.c	19770	F: sound/soc/soc-generic-dmaengine-pcm.c
19745		19771
19746	SOUND - ALSA SELFTESTS
19747	M: Mark Brown <broonie@kernel.org>
19748	L: alsa-devel@alsa-project.org (moderated for non-subscribers)
19749	L: linux-kselftest@vger.kernel.org
19750	S: Supported
19751	F: tools/testing/selftests/alsa
19752
19753	SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEMENT (ASoC)	19772	SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEMENT (ASoC)
19754	M: Liam Girdwood <lgirdwood@gmail.com>	19773	M: Liam Girdwood <lgirdwood@gmail.com>
19755	M: Mark Brown <broonie@kernel.org>	19774	M: Mark Brown <broonie@kernel.org>
@@ -19769,8 +19788,8 @@ M: Liam Girdwood <lgirdwood@gmail.com> · 13 unmodified lines
19769	M: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>	19788	M: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
19770	M: Bard Liao <yung-chuan.liao@linux.intel.com>	19789	M: Bard Liao <yung-chuan.liao@linux.intel.com>
19771	M: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>	19790	M: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
19772	R: Kai Vehmanen <kai.vehmanen@linux.intel.com>
19773	M: Daniel Baluta <daniel.baluta@nxp.com>	19791	M: Daniel Baluta <daniel.baluta@nxp.com>
		19792	R: Kai Vehmanen <kai.vehmanen@linux.intel.com>
19774	L: sound-open-firmware@alsa-project.org (moderated for non-subscribers)	19793	L: sound-open-firmware@alsa-project.org (moderated for non-subscribers)
19775	S: Supported	19794	S: Supported
19776	W: https://github.com/thesofproject/linux/	19795	W: https://github.com/thesofproject/linux/
@@ -19832,9 +19851,9 @@ M: "Luc Van Oostenryck" <luc.vanoostenryck@gmail.com> · 55 unmodified lines
19832	L: linux-sparse@vger.kernel.org	19851	L: linux-sparse@vger.kernel.org
19833	S: Maintained	19852	S: Maintained
19834	W: https://sparse.docs.kernel.org/	19853	W: https://sparse.docs.kernel.org/
19835	T: git git://git.kernel.org/pub/scm/devel/sparse/sparse.git
19836	Q: https://patchwork.kernel.org/project/linux-sparse/list/	19854	Q: https://patchwork.kernel.org/project/linux-sparse/list/
19837	B: https://bugzilla.kernel.org/enter_bug.cgi?component=Sparse&product=Tools	19855	B: https://bugzilla.kernel.org/enter_bug.cgi?component=Sparse&product=Tools
		19856	T: git git://git.kernel.org/pub/scm/devel/sparse/sparse.git
19838	F: include/linux/compiler.h	19857	F: include/linux/compiler.h
19839		19858
19840	SPEAKUP CONSOLE SPEECH DRIVER	19859	SPEAKUP CONSOLE SPEECH DRIVER
@@ -20203,6 +20222,11 @@ W: http://www.stlinux.com · 362 unmodified lines
20203	F: Documentation/networking/device_drivers/ethernet/stmicro/	20222	F: Documentation/networking/device_drivers/ethernet/stmicro/
20204	F: drivers/net/ethernet/stmicro/stmmac/	20223	F: drivers/net/ethernet/stmicro/stmmac/
20205		20224
		20225	SUN HAPPY MEAL ETHERNET DRIVER
		20226	M: Sean Anderson <seanga2@gmail.com>
		20227	S: Maintained
		20228	F: drivers/net/ethernet/sun/sunhme.*
		20229
20206	SUN3/3X	20230	SUN3/3X
20207	M: Sam Creasey <sammy@sammy.net>	20231	M: Sam Creasey <sammy@sammy.net>
20208	S: Maintained	20232	S: Maintained
@@ -20225,11 +20249,6 @@ L: netdev@vger.kernel.org · 16 unmodified lines
20225	S: Maintained	20249	S: Maintained
20226	F: drivers/net/ethernet/dlink/sundance.c	20250	F: drivers/net/ethernet/dlink/sundance.c
20227		20251
20228	SUN HAPPY MEAL ETHERNET DRIVER
20229	M: Sean Anderson <seanga2@gmail.com>
20230	S: Maintained
20231	F: drivers/net/ethernet/sun/sunhme.*
20232
20233	SUNPLUS ETHERNET DRIVER	20252	SUNPLUS ETHERNET DRIVER
20234	M: Wells Lu <wellslutw@gmail.com>	20253	M: Wells Lu <wellslutw@gmail.com>
20235	L: netdev@vger.kernel.org	20254	L: netdev@vger.kernel.org
@@ -20251,15 +20270,6 @@ S: Maintained · 15 unmodified lines
20251	F: Documentation/devicetree/bindings/nvmem/sunplus,sp7021-ocotp.yaml	20270	F: Documentation/devicetree/bindings/nvmem/sunplus,sp7021-ocotp.yaml
20252	F: drivers/nvmem/sunplus-ocotp.c	20271	F: drivers/nvmem/sunplus-ocotp.c
20253		20272
20254	SUNPLUS USB2 PHY DRIVER
20255	M: Vincent Shih <vincent.sunplus@gmail.com>
20256	L: linux-usb@vger.kernel.org
20257	S: Maintained
20258	F: Documentation/devicetree/bindings/phy/sunplus,sp7021-usb2-phy.yaml
20259	F: drivers/phy/sunplus/Kconfig
20260	F: drivers/phy/sunplus/Makefile
20261	F: drivers/phy/sunplus/phy-sunplus-usb2.c
20262
20263	SUNPLUS PWM DRIVER	20273	SUNPLUS PWM DRIVER
20264	M: Hammer Hsieh <hammerh0314@gmail.com>	20274	M: Hammer Hsieh <hammerh0314@gmail.com>
20265	S: Maintained	20275	S: Maintained
@@ -20286,6 +20296,15 @@ S: Maintained · 20 unmodified lines
20286	F: Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml	20296	F: Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
20287	F: drivers/tty/serial/sunplus-uart.c	20297	F: drivers/tty/serial/sunplus-uart.c
20288		20298
		20299	SUNPLUS USB2 PHY DRIVER
		20300	M: Vincent Shih <vincent.sunplus@gmail.com>
		20301	L: linux-usb@vger.kernel.org
		20302	S: Maintained
		20303	F: Documentation/devicetree/bindings/phy/sunplus,sp7021-usb2-phy.yaml
		20304	F: drivers/phy/sunplus/Kconfig
		20305	F: drivers/phy/sunplus/Makefile
		20306	F: drivers/phy/sunplus/phy-sunplus-usb2.c
		20307
20289	SUNPLUS WATCHDOG DRIVER	20308	SUNPLUS WATCHDOG DRIVER
20290	M: Xiantao Hu <xt.hu@cqplus1.com>	20309	M: Xiantao Hu <xt.hu@cqplus1.com>
20291	L: linux-watchdog@vger.kernel.org	20310	L: linux-watchdog@vger.kernel.org
@@ -20697,6 +20716,14 @@ F: include/linux/if_team.h · 405 unmodified lines
20697	F: include/uapi/linux/if_team.h	20716	F: include/uapi/linux/if_team.h
20698	F: tools/testing/selftests/drivers/net/team/	20717	F: tools/testing/selftests/drivers/net/team/
20699		20718
		20719	TECHNICAL ADVISORY BOARD PROCESS DOCS
		20720	M: "Theodore Ts'o" <tytso@mit.edu>
		20721	M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
		20722	L: tech-board-discuss@lists.linux-foundation.org
		20723	S: Maintained
		20724	F: Documentation/process/contribution-maturity-model.rst
		20725	F: Documentation/process/researcher-guidelines.rst
		20726
20700	TECHNOLOGIC SYSTEMS TS-5500 PLATFORM SUPPORT	20727	TECHNOLOGIC SYSTEMS TS-5500 PLATFORM SUPPORT
20701	M: "Savoir-faire Linux Inc." <kernel@savoirfairelinux.com>	20728	M: "Savoir-faire Linux Inc." <kernel@savoirfairelinux.com>
20702	S: Maintained	20729	S: Maintained
@@ -20776,6 +20803,14 @@ M: Thierry Reding <thierry.reding@gmail.com> · 73 unmodified lines
20776	S: Supported	20803	S: Supported
20777	F: drivers/pwm/pwm-tegra.c	20804	F: drivers/pwm/pwm-tegra.c
20778		20805
		20806	TEGRA QUAD SPI DRIVER
		20807	M: Thierry Reding <thierry.reding@gmail.com>
		20808	M: Jonathan Hunter <jonathanh@nvidia.com>
		20809	M: Sowjanya Komatineni <skomatineni@nvidia.com>
		20810	L: linux-tegra@vger.kernel.org
		20811	S: Maintained
		20812	F: drivers/spi/spi-tegra210-quad.c
		20813
20779	TEGRA SERIAL DRIVER	20814	TEGRA SERIAL DRIVER
20780	M: Laxman Dewangan <ldewangan@nvidia.com>	20815	M: Laxman Dewangan <ldewangan@nvidia.com>
20781	S: Supported	20816	S: Supported
@@ -20786,14 +20821,6 @@ M: Laxman Dewangan <ldewangan@nvidia.com> · 4 unmodified lines
20786	S: Supported	20821	S: Supported
20787	F: drivers/spi/spi-tegra*	20822	F: drivers/spi/spi-tegra*
20788		20823
20789	TEGRA QUAD SPI DRIVER
20790	M: Thierry Reding <thierry.reding@gmail.com>
20791	M: Jonathan Hunter <jonathanh@nvidia.com>
20792	M: Sowjanya Komatineni <skomatineni@nvidia.com>
20793	L: linux-tegra@vger.kernel.org
20794	S: Maintained
20795	F: drivers/spi/spi-tegra210-quad.c
20796
20797	TEGRA VIDEO DRIVER	20824	TEGRA VIDEO DRIVER
20798	M: Thierry Reding <thierry.reding@gmail.com>	20825	M: Thierry Reding <thierry.reding@gmail.com>
20799	M: Jonathan Hunter <jonathanh@nvidia.com>	20826	M: Jonathan Hunter <jonathanh@nvidia.com>
@@ -20842,13 +20869,6 @@ S: Maintained · 42 unmodified lines
20842	F: Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml	20869	F: Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml
20843	F: sound/soc/ti/	20870	F: sound/soc/ti/
20844		20871
20845	TEXAS INSTRUMENTS' DAC7612 DAC DRIVER
20846	M: Ricardo Ribalda <ribalda@kernel.org>
20847	L: linux-iio@vger.kernel.org
20848	S: Supported
20849	F: Documentation/devicetree/bindings/iio/dac/ti,dac7612.yaml
20850	F: drivers/iio/dac/ti-dac7612.c
20851
20852	TEXAS INSTRUMENTS DMA DRIVERS	20872	TEXAS INSTRUMENTS DMA DRIVERS
20853	M: Peter Ujfalusi <peter.ujfalusi@gmail.com>	20873	M: Peter Ujfalusi <peter.ujfalusi@gmail.com>
20854	L: dmaengine@vger.kernel.org	20874	L: dmaengine@vger.kernel.org
@@ -20857,10 +20877,26 @@ F: Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt · 2 unmodified lines
20857	F: Documentation/devicetree/bindings/dma/ti-edma.txt	20877	F: Documentation/devicetree/bindings/dma/ti-edma.txt
20858	F: Documentation/devicetree/bindings/dma/ti/	20878	F: Documentation/devicetree/bindings/dma/ti/
20859	F: drivers/dma/ti/	20879	F: drivers/dma/ti/
20860	X: drivers/dma/ti/cppi41.c	20880	F: include/linux/dma/k3-psil.h
20861	F: include/linux/dma/k3-udma-glue.h	20881	F: include/linux/dma/k3-udma-glue.h
20862	F: include/linux/dma/ti-cppi5.h	20882	F: include/linux/dma/ti-cppi5.h
20863	F: include/linux/dma/k3-psil.h	20883	X: drivers/dma/ti/cppi41.c
		20884
		20885	TEXAS INSTRUMENTS TPS23861 PoE PSE DRIVER
		20886	M: Robert Marko <robert.marko@sartura.hr>
		20887	M: Luka Perkov <luka.perkov@sartura.hr>
		20888	L: linux-hwmon@vger.kernel.org
		20889	S: Maintained
		20890	F: Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml
		20891	F: Documentation/hwmon/tps23861.rst
		20892	F: drivers/hwmon/tps23861.c
		20893
		20894	TEXAS INSTRUMENTS' DAC7612 DAC DRIVER
		20895	M: Ricardo Ribalda <ribalda@kernel.org>
		20896	L: linux-iio@vger.kernel.org
		20897	S: Supported
		20898	F: Documentation/devicetree/bindings/iio/dac/ti,dac7612.yaml
		20899	F: drivers/iio/dac/ti-dac7612.c
20864		20900
20865	TEXAS INSTRUMENTS' SYSTEM CONTROL INTERFACE (TISCI) PROTOCOL DRIVER	20901	TEXAS INSTRUMENTS' SYSTEM CONTROL INTERFACE (TISCI) PROTOCOL DRIVER
20866	M: Nishanth Menon <nm@ti.com>	20902	M: Nishanth Menon <nm@ti.com>
@@ -20886,15 +20922,6 @@ F: include/dt-bindings/soc/ti,sci_pm_domain.h · 19 unmodified lines
20886	F: include/linux/soc/ti/ti_sci_inta_msi.h	20922	F: include/linux/soc/ti/ti_sci_inta_msi.h
20887	F: include/linux/soc/ti/ti_sci_protocol.h	20923	F: include/linux/soc/ti/ti_sci_protocol.h
20888		20924
20889	TEXAS INSTRUMENTS TPS23861 PoE PSE DRIVER
20890	M: Robert Marko <robert.marko@sartura.hr>
20891	M: Luka Perkov <luka.perkov@sartura.hr>
20892	L: linux-hwmon@vger.kernel.org
20893	S: Maintained
20894	F: Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml
20895	F: Documentation/hwmon/tps23861.rst
20896	F: drivers/hwmon/tps23861.c
20897
20898	TEXAS INSTRUMENTS' TMP117 TEMPERATURE SENSOR DRIVER	20925	TEXAS INSTRUMENTS' TMP117 TEMPERATURE SENSOR DRIVER
20899	M: Puranjay Mohan <puranjay12@gmail.com>	20926	M: Puranjay Mohan <puranjay12@gmail.com>
20900	L: linux-iio@vger.kernel.org	20927	L: linux-iio@vger.kernel.org
@@ -21371,8 +21398,8 @@ M: Steven Rostedt <rostedt@goodmis.org> · 470 unmodified lines
21371	M: Masami Hiramatsu <mhiramat@kernel.org>	21398	M: Masami Hiramatsu <mhiramat@kernel.org>
21372	L: linux-kernel@vger.kernel.org	21399	L: linux-kernel@vger.kernel.org
21373	L: linux-trace-kernel@vger.kernel.org	21400	L: linux-trace-kernel@vger.kernel.org
21374	Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
21375	S: Maintained	21401	S: Maintained
		21402	Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
21376	T: git git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git	21403	T: git git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git
21377	F: Documentation/trace/*	21404	F: Documentation/trace/*
21378	F: fs/tracefs/	21405	F: fs/tracefs/
@@ -21400,31 +21427,15 @@ TRACING OS NOISE / LATENCY TRACERS · 21 unmodified lines
21400	M: Steven Rostedt <rostedt@goodmis.org>	21427	M: Steven Rostedt <rostedt@goodmis.org>
21401	M: Daniel Bristot de Oliveira <bristot@kernel.org>	21428	M: Daniel Bristot de Oliveira <bristot@kernel.org>
21402	S: Maintained	21429	S: Maintained
21403	F: kernel/trace/trace_osnoise.c	21430	F: Documentation/trace/hwlat_detector.rst
		21431	F: Documentation/trace/osnoise-tracer.rst
		21432	F: Documentation/trace/timerlat-tracer.rst
		21433	F: arch/*/kernel/trace.c
21404	F: include/trace/events/osnoise.h	21434	F: include/trace/events/osnoise.h
21405	F: kernel/trace/trace_hwlat.c	21435	F: kernel/trace/trace_hwlat.c
21406	F: kernel/trace/trace_irqsoff.c	21436	F: kernel/trace/trace_irqsoff.c
		21437	F: kernel/trace/trace_osnoise.c
21407	F: kernel/trace/trace_sched_wakeup.c	21438	F: kernel/trace/trace_sched_wakeup.c
21408	F: Documentation/trace/osnoise-tracer.rst
21409	F: Documentation/trace/timerlat-tracer.rst
21410	F: Documentation/trace/hwlat_detector.rst
21411	F: arch/*/kernel/trace.c
21412
21413	Real-time Linux Analysis (RTLA) tools
21414	M: Daniel Bristot de Oliveira <bristot@kernel.org>
21415	M: Steven Rostedt <rostedt@goodmis.org>
21416	L: linux-trace-devel@vger.kernel.org
21417	S: Maintained
21418	F: Documentation/tools/rtla/
21419	F: tools/tracing/rtla/
21420
21421	TECHNICAL ADVISORY BOARD PROCESS DOCS
21422	M: "Theodore Ts'o" <tytso@mit.edu>
21423	M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
21424	L: tech-board-discuss@lists.linux-foundation.org
21425	S: Maintained
21426	F: Documentation/process/researcher-guidelines.rst
21427	F: Documentation/process/contribution-maturity-model.rst
21428		21439
21429	TRADITIONAL CHINESE DOCUMENTATION	21440	TRADITIONAL CHINESE DOCUMENTATION
21430	M: Hu Haowen <src.res@email.cn>	21441	M: Hu Haowen <src.res@email.cn>
@@ -21782,8 +21793,8 @@ USB ISP1760 DRIVER · 351 unmodified lines
21782	M: Rui Miguel Silva <rui.silva@linaro.org>	21793	M: Rui Miguel Silva <rui.silva@linaro.org>
21783	L: linux-usb@vger.kernel.org	21794	L: linux-usb@vger.kernel.org
21784	S: Maintained	21795	S: Maintained
21785	F: drivers/usb/isp1760/*
21786	F: Documentation/devicetree/bindings/usb/nxp,isp1760.yaml	21796	F: Documentation/devicetree/bindings/usb/nxp,isp1760.yaml
		21797	F: drivers/usb/isp1760/*
21787		21798
21788	USB LAN78XX ETHERNET DRIVER	21799	USB LAN78XX ETHERNET DRIVER
21789	M: Woojung Huh <woojung.huh@microchip.com>	21800	M: Woojung Huh <woojung.huh@microchip.com>
@@ -21854,6 +21865,13 @@ L: linux-usb@vger.kernel.org · 64 unmodified lines
21854	S: Supported	21865	S: Supported
21855	F: drivers/usb/class/usblp.c	21866	F: drivers/usb/class/usblp.c
21856		21867
		21868	USB QMI WWAN NETWORK DRIVER
		21869	M: Bjørn Mork <bjorn@mork.no>
		21870	L: netdev@vger.kernel.org
		21871	S: Maintained
		21872	F: Documentation/ABI/testing/sysfs-class-net-qmi
		21873	F: drivers/net/usb/qmi_wwan.c
		21874
21857	USB RAW GADGET DRIVER	21875	USB RAW GADGET DRIVER
21858	R: Andrey Konovalov <andreyknvl@gmail.com>	21876	R: Andrey Konovalov <andreyknvl@gmail.com>
21859	L: linux-usb@vger.kernel.org	21877	L: linux-usb@vger.kernel.org
@@ -21862,13 +21880,6 @@ F: Documentation/usb/raw-gadget.rst · 2 unmodified lines
21862	F: drivers/usb/gadget/legacy/raw_gadget.c	21880	F: drivers/usb/gadget/legacy/raw_gadget.c
21863	F: include/uapi/linux/usb/raw_gadget.h	21881	F: include/uapi/linux/usb/raw_gadget.h
21864		21882
21865	USB QMI WWAN NETWORK DRIVER
21866	M: Bjørn Mork <bjorn@mork.no>
21867	L: netdev@vger.kernel.org
21868	S: Maintained
21869	F: Documentation/ABI/testing/sysfs-class-net-qmi
21870	F: drivers/net/usb/qmi_wwan.c
21871
21872	USB RTL8150 DRIVER	21883	USB RTL8150 DRIVER
21873	M: Petko Manolov <petkan@nucleusys.com>	21884	M: Petko Manolov <petkan@nucleusys.com>
21874	L: linux-usb@vger.kernel.org	21885	L: linux-usb@vger.kernel.org
@@ -22120,6 +22131,12 @@ F: drivers/vfio/mdev/ · 245 unmodified lines
22120	F: include/linux/mdev.h	22131	F: include/linux/mdev.h
22121	F: samples/vfio-mdev/	22132	F: samples/vfio-mdev/
22122		22133
		22134	VFIO MLX5 PCI DRIVER
		22135	M: Yishai Hadas <yishaih@nvidia.com>
		22136	L: kvm@vger.kernel.org
		22137	S: Maintained
		22138	F: drivers/vfio/pci/mlx5/
		22139
22123	VFIO PCI DEVICE SPECIFIC DRIVERS	22140	VFIO PCI DEVICE SPECIFIC DRIVERS
22124	R: Jason Gunthorpe <jgg@nvidia.com>	22141	R: Jason Gunthorpe <jgg@nvidia.com>
22125	R: Yishai Hadas <yishaih@nvidia.com>	22142	R: Yishai Hadas <yishaih@nvidia.com>
@@ -22136,12 +22153,6 @@ L: kvm@vger.kernel.org · 10 unmodified lines
22136	S: Maintained	22153	S: Maintained
22137	F: drivers/vfio/platform/	22154	F: drivers/vfio/platform/
22138		22155
22139	VFIO MLX5 PCI DRIVER
22140	M: Yishai Hadas <yishaih@nvidia.com>
22141	L: kvm@vger.kernel.org
22142	S: Maintained
22143	F: drivers/vfio/pci/mlx5/
22144
22145	VGA_SWITCHEROO	22156	VGA_SWITCHEROO
22146	R: Lukas Wunner <lukas@wunner.de>	22157	R: Lukas Wunner <lukas@wunner.de>
22147	S: Maintained	22158	S: Maintained
@@ -22151,8 +22162,8 @@ F: drivers/gpu/vga/vga_switcheroo.c · 3 unmodified lines
22151	F: include/linux/vga_switcheroo.h	22162	F: include/linux/vga_switcheroo.h
22152		22163
22153	VIA RHINE NETWORK DRIVER	22164	VIA RHINE NETWORK DRIVER
22154	S: Maintained
22155	M: Kevin Brace <kevinbrace@bracecomputerlab.com>	22165	M: Kevin Brace <kevinbrace@bracecomputerlab.com>
		22166	S: Maintained
22156	F: drivers/net/ethernet/via/via-rhine.c	22167	F: drivers/net/ethernet/via/via-rhine.c
22157		22168
22158	VIA SD/MMC CARD CONTROLLER DRIVER	22169	VIA SD/MMC CARD CONTROLLER DRIVER
@@ -22204,6 +22215,14 @@ S: Maintained · 45 unmodified lines
22204	F: drivers/media/common/videobuf2/*	22215	F: drivers/media/common/videobuf2/*
22205	F: include/media/videobuf2-*	22216	F: include/media/videobuf2-*
22206		22217
		22218	VIDTV VIRTUAL DIGITAL TV DRIVER
		22219	M: Daniel W. S. Almeida <dwlsalmeida@gmail.com>
		22220	L: linux-media@vger.kernel.org
		22221	S: Maintained
		22222	W: https://linuxtv.org
		22223	T: git git://linuxtv.org/media_tree.git
		22224	F: drivers/media/test-drivers/vidtv/*
		22225
22207	VIMC VIRTUAL MEDIA CONTROLLER DRIVER	22226	VIMC VIRTUAL MEDIA CONTROLLER DRIVER
22208	M: Shuah Khan <skhan@linuxfoundation.org>	22227	M: Shuah Khan <skhan@linuxfoundation.org>
22209	R: Kieran Bingham <kieran.bingham@ideasonboard.com>	22228	R: Kieran Bingham <kieran.bingham@ideasonboard.com>
@@ -22233,6 +22252,16 @@ F: include/uapi/linux/virtio_vsock.h · 23 unmodified lines
22233	F: net/vmw_vsock/virtio_transport.c	22252	F: net/vmw_vsock/virtio_transport.c
22234	F: net/vmw_vsock/virtio_transport_common.c	22253	F: net/vmw_vsock/virtio_transport_common.c
22235		22254
		22255	VIRTIO BALLOON
		22256	M: "Michael S. Tsirkin" <mst@redhat.com>
		22257	M: David Hildenbrand <david@redhat.com>
		22258	L: virtualization@lists.linux-foundation.org
		22259	S: Maintained
		22260	F: drivers/virtio/virtio_balloon.c
		22261	F: include/linux/balloon_compaction.h
		22262	F: include/uapi/linux/virtio_balloon.h
		22263	F: mm/balloon_compaction.c
		22264
22236	VIRTIO BLOCK AND SCSI DRIVERS	22265	VIRTIO BLOCK AND SCSI DRIVERS
22237	M: "Michael S. Tsirkin" <mst@redhat.com>	22266	M: "Michael S. Tsirkin" <mst@redhat.com>
22238	M: Jason Wang <jasowang@redhat.com>	22267	M: Jason Wang <jasowang@redhat.com>
@@ -22275,30 +22304,6 @@ F: include/linux/vringh.h · 36 unmodified lines
22275	F: include/uapi/linux/virtio_*.h	22304	F: include/uapi/linux/virtio_*.h
22276	F: tools/virtio/	22305	F: tools/virtio/
22277		22306
22278	VISL VIRTUAL STATELESS DECODER DRIVER
22279	M: Daniel Almeida <daniel.almeida@collabora.com>
22280	L: linux-media@vger.kernel.org
22281	S: Supported
22282	F: drivers/media/test-drivers/visl
22283
22284	IFCVF VIRTIO DATA PATH ACCELERATOR
22285	R: Zhu Lingshan <lingshan.zhu@intel.com>
22286	F: drivers/vdpa/ifcvf/
22287
22288	SNET DPU VIRTIO DATA PATH ACCELERATOR
22289	R: Alvaro Karsz <alvaro.karsz@solid-run.com>
22290	F: drivers/vdpa/solidrun/
22291
22292	VIRTIO BALLOON
22293	M: "Michael S. Tsirkin" <mst@redhat.com>
22294	M: David Hildenbrand <david@redhat.com>
22295	L: virtualization@lists.linux-foundation.org
22296	S: Maintained
22297	F: drivers/virtio/virtio_balloon.c
22298	F: include/uapi/linux/virtio_balloon.h
22299	F: include/linux/balloon_compaction.h
22300	F: mm/balloon_compaction.c
22301
22302	VIRTIO CRYPTO DRIVER	22307	VIRTIO CRYPTO DRIVER
22303	M: Gonglei <arei.gonglei@huawei.com>	22308	M: Gonglei <arei.gonglei@huawei.com>
22304	L: virtualization@lists.linux-foundation.org	22309	L: virtualization@lists.linux-foundation.org
@@ -22359,11 +22364,20 @@ L: virtualization@lists.linux-foundation.org · 54 unmodified lines
22359	L: netdev@vger.kernel.org	22364	L: netdev@vger.kernel.org
22360	S: Maintained	22365	S: Maintained
22361	T: git git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost.git	22366	T: git git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost.git
22362	F: kernel/vhost_task.c
22363	F: drivers/vhost/	22367	F: drivers/vhost/
22364	F: include/linux/sched/vhost_task.h	22368	F: include/linux/sched/vhost_task.h
22365	F: include/linux/vhost_iotlb.h	22369	F: include/linux/vhost_iotlb.h
22366	F: include/uapi/linux/vhost.h	22370	F: include/uapi/linux/vhost.h
		22371	F: kernel/vhost_task.c
		22372
		22373	VIRTIO I2C DRIVER
		22374	M: Conghui Chen <conghui.chen@intel.com>
		22375	M: Viresh Kumar <viresh.kumar@linaro.org>
		22376	L: linux-i2c@vger.kernel.org
		22377	L: virtualization@lists.linux-foundation.org
		22378	S: Maintained
		22379	F: drivers/i2c/busses/i2c-virtio.c
		22380	F: include/uapi/linux/virtio_i2c.h
22367		22381
22368	VIRTIO INPUT DRIVER	22382	VIRTIO INPUT DRIVER
22369	M: Gerd Hoffmann <kraxel@redhat.com>	22383	M: Gerd Hoffmann <kraxel@redhat.com>
@@ -22386,6 +22400,13 @@ W: https://virtio-mem.gitlab.io/ · 16 unmodified lines
22386	F: drivers/virtio/virtio_mem.c	22400	F: drivers/virtio/virtio_mem.c
22387	F: include/uapi/linux/virtio_mem.h	22401	F: include/uapi/linux/virtio_mem.h
22388		22402
		22403	VIRTIO PMEM DRIVER
		22404	M: Pankaj Gupta <pankaj.gupta.linux@gmail.com>
		22405	L: virtualization@lists.linux-foundation.org
		22406	S: Maintained
		22407	F: drivers/nvdimm/nd_virtio.c
		22408	F: drivers/nvdimm/virtio_pmem.c
		22409
22389	VIRTIO SOUND DRIVER	22410	VIRTIO SOUND DRIVER
22390	M: Anton Yakovlev <anton.yakovlev@opensynergy.com>	22411	M: Anton Yakovlev <anton.yakovlev@opensynergy.com>
22391	M: "Michael S. Tsirkin" <mst@redhat.com>	22412	M: "Michael S. Tsirkin" <mst@redhat.com>
@@ -22395,22 +22416,6 @@ S: Maintained · 3 unmodified lines
22395	F: include/uapi/linux/virtio_snd.h	22416	F: include/uapi/linux/virtio_snd.h
22396	F: sound/virtio/*	22417	F: sound/virtio/*
22397		22418
22398	VIRTIO I2C DRIVER
22399	M: Conghui Chen <conghui.chen@intel.com>
22400	M: Viresh Kumar <viresh.kumar@linaro.org>
22401	L: linux-i2c@vger.kernel.org
22402	L: virtualization@lists.linux-foundation.org
22403	S: Maintained
22404	F: drivers/i2c/busses/i2c-virtio.c
22405	F: include/uapi/linux/virtio_i2c.h
22406
22407	VIRTIO PMEM DRIVER
22408	M: Pankaj Gupta <pankaj.gupta.linux@gmail.com>
22409	L: virtualization@lists.linux-foundation.org
22410	S: Maintained
22411	F: drivers/nvdimm/virtio_pmem.c
22412	F: drivers/nvdimm/nd_virtio.c
22413
22414	VIRTUAL BOX GUEST DEVICE DRIVER	22419	VIRTUAL BOX GUEST DEVICE DRIVER
22415	M: Hans de Goede <hdegoede@redhat.com>	22420	M: Hans de Goede <hdegoede@redhat.com>
22416	M: Arnd Bergmann <arnd@arndb.de>	22421	M: Arnd Bergmann <arnd@arndb.de>
@@ -22432,6 +22437,12 @@ S: Maintained · 15 unmodified lines
22432	F: drivers/input/serio/userio.c	22437	F: drivers/input/serio/userio.c
22433	F: include/uapi/linux/userio.h	22438	F: include/uapi/linux/userio.h
22434		22439
		22440	VISL VIRTUAL STATELESS DECODER DRIVER
		22441	M: Daniel Almeida <daniel.almeida@collabora.com>
		22442	L: linux-media@vger.kernel.org
		22443	S: Supported
		22444	F: drivers/media/test-drivers/visl
		22445
22435	VIVID VIRTUAL VIDEO DRIVER	22446	VIVID VIRTUAL VIDEO DRIVER
22436	M: Hans Verkuil <hverkuil@xs4all.nl>	22447	M: Hans Verkuil <hverkuil@xs4all.nl>
22437	L: linux-media@vger.kernel.org	22448	L: linux-media@vger.kernel.org
@@ -22440,14 +22451,6 @@ W: https://linuxtv.org · 2 unmodified lines
22440	T: git git://linuxtv.org/media_tree.git	22451	T: git git://linuxtv.org/media_tree.git
22441	F: drivers/media/test-drivers/vivid/*	22452	F: drivers/media/test-drivers/vivid/*
22442		22453
22443	VIDTV VIRTUAL DIGITAL TV DRIVER
22444	M: Daniel W. S. Almeida <dwlsalmeida@gmail.com>
22445	L: linux-media@vger.kernel.org
22446	S: Maintained
22447	W: https://linuxtv.org
22448	T: git git://linuxtv.org/media_tree.git
22449	F: drivers/media/test-drivers/vidtv/*
22450
22451	VLYNQ BUS	22454	VLYNQ BUS
22452	M: Florian Fainelli <f.fainelli@gmail.com>	22455	M: Florian Fainelli <f.fainelli@gmail.com>
22453	L: openwrt-devel@lists.openwrt.org (subscribers-only)	22456	L: openwrt-devel@lists.openwrt.org (subscribers-only)
@@ -22455,16 +22458,6 @@ S: Maintained · 1 unmodified line
22455	F: drivers/vlynq/vlynq.c	22458	F: drivers/vlynq/vlynq.c
22456	F: include/linux/vlynq.h	22459	F: include/linux/vlynq.h
22457		22460
22458	VME SUBSYSTEM
22459	M: Martyn Welch <martyn@welchs.me.uk>
22460	M: Manohar Vanga <manohar.vanga@gmail.com>
22461	M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22462	L: linux-kernel@vger.kernel.org
22463	S: Odd fixes
22464	T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git
22465	F: Documentation/driver-api/vme.rst
22466	F: drivers/staging/vme_user/
22467
22468	VM SOCKETS (AF_VSOCK)	22461	VM SOCKETS (AF_VSOCK)
22469	M: Stefano Garzarella <sgarzare@redhat.com>	22462	M: Stefano Garzarella <sgarzare@redhat.com>
22470	L: virtualization@lists.linux-foundation.org	22463	L: virtualization@lists.linux-foundation.org
@@ -22478,6 +22471,28 @@ F: include/uapi/linux/vsockmon.h · 7 unmodified lines
22478	F: net/vmw_vsock/	22471	F: net/vmw_vsock/
22479	F: tools/testing/vsock/	22472	F: tools/testing/vsock/
22480		22473
		22474	VMALLOC
		22475	M: Andrew Morton <akpm@linux-foundation.org>
		22476	R: Uladzislau Rezki <urezki@gmail.com>
		22477	R: Christoph Hellwig <hch@infradead.org>
		22478	R: Lorenzo Stoakes <lstoakes@gmail.com>
		22479	L: linux-mm@kvack.org
		22480	S: Maintained
		22481	W: http://www.linux-mm.org
		22482	T: git git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
		22483	F: include/linux/vmalloc.h
		22484	F: mm/vmalloc.c
		22485
		22486	VME SUBSYSTEM
		22487	M: Martyn Welch <martyn@welchs.me.uk>
		22488	M: Manohar Vanga <manohar.vanga@gmail.com>
		22489	M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
		22490	L: linux-kernel@vger.kernel.org
		22491	S: Odd fixes
		22492	T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git
		22493	F: Documentation/driver-api/vme.rst
		22494	F: drivers/staging/vme_user/
		22495
22481	VMWARE BALLOON DRIVER	22496	VMWARE BALLOON DRIVER
22482	M: Nadav Amit <namit@vmware.com>	22497	M: Nadav Amit <namit@vmware.com>
22483	R: VMware PV-Drivers Reviewers <pv-drivers@vmware.com>	22498	R: VMware PV-Drivers Reviewers <pv-drivers@vmware.com>
@@ -22659,9 +22674,9 @@ F: drivers/input/tablet/wacom_serial4.c · 175 unmodified lines
22659	WANGXUN ETHERNET DRIVER	22674	WANGXUN ETHERNET DRIVER
22660	M: Jiawen Wu <jiawenwu@trustnetic.com>	22675	M: Jiawen Wu <jiawenwu@trustnetic.com>
22661	M: Mengyuan Lou <mengyuanlou@net-swift.com>	22676	M: Mengyuan Lou <mengyuanlou@net-swift.com>
22662	W: https://www.net-swift.com
22663	L: netdev@vger.kernel.org	22677	L: netdev@vger.kernel.org
22664	S: Maintained	22678	S: Maintained
		22679	W: https://www.net-swift.com
22665	F: Documentation/networking/device_drivers/ethernet/wangxun/*	22680	F: Documentation/networking/device_drivers/ethernet/wangxun/*
22666	F: drivers/net/ethernet/wangxun/	22681	F: drivers/net/ethernet/wangxun/
22667		22682
@@ -22676,8 +22691,8 @@ F: Documentation/devicetree/bindings/watchdog/ · 8 unmodified lines
22676	F: Documentation/watchdog/	22691	F: Documentation/watchdog/
22677	F: drivers/watchdog/	22692	F: drivers/watchdog/
22678	F: include/linux/watchdog.h	22693	F: include/linux/watchdog.h
22679	F: include/uapi/linux/watchdog.h
22680	F: include/trace/events/watchdog.h	22694	F: include/trace/events/watchdog.h
		22695	F: include/uapi/linux/watchdog.h
22681		22696
22682	WHISKEYCOVE PMIC GPIO DRIVER	22697	WHISKEYCOVE PMIC GPIO DRIVER
22683	M: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>	22698	M: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
@@ -22834,8 +22849,8 @@ R: "H. Peter Anvin" <hpa@zytor.com> · 150 unmodified lines
22834	L: linux-kernel@vger.kernel.org	22849	L: linux-kernel@vger.kernel.org
22835	S: Maintained	22850	S: Maintained
22836	T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core	22851	T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core
22837	F: Documentation/devicetree/bindings/x86/
22838	F: Documentation/arch/x86/	22852	F: Documentation/arch/x86/
		22853	F: Documentation/devicetree/bindings/x86/
22839	F: arch/x86/	22854	F: arch/x86/
22840		22855
22841	X86 ENTRY CODE	22856	X86 ENTRY CODE
@@ -22966,6 +22981,8 @@ M: John Fastabend <john.fastabend@gmail.com> · 124 unmodified lines
22966	L: netdev@vger.kernel.org	22981	L: netdev@vger.kernel.org
22967	L: bpf@vger.kernel.org	22982	L: bpf@vger.kernel.org
22968	S: Supported	22983	S: Supported
		22984	F: drivers/net/ethernet/////xdp
		22985	F: drivers/net/ethernet///xdp
22969	F: include/net/xdp.h	22986	F: include/net/xdp.h
22970	F: include/net/xdp_priv.h	22987	F: include/net/xdp_priv.h
22971	F: include/trace/events/xdp.h	22988	F: include/trace/events/xdp.h
@@ -22973,10 +22990,8 @@ F: kernel/bpf/cpumap.c · 1 unmodified line
22973	F: kernel/bpf/devmap.c	22990	F: kernel/bpf/devmap.c
22974	F: net/core/xdp.c	22991	F: net/core/xdp.c
22975	F: samples/bpf/xdp*	22992	F: samples/bpf/xdp*
22976	F: tools/testing/selftests/bpf/xdp
22977	F: tools/testing/selftests/bpf//xdp*	22993	F: tools/testing/selftests/bpf//xdp*
22978	F: drivers/net/ethernet/////xdp	22994	F: tools/testing/selftests/bpf/xdp
22979	F: drivers/net/ethernet///xdp
22980	K: (?:\b\|_)xdp(?:\b\|_)	22995	K: (?:\b\|_)xdp(?:\b\|_)
22981		22996
22982	XDP SOCKETS (AF_XDP)	22997	XDP SOCKETS (AF_XDP)
@@ -22988,11 +23003,11 @@ L: netdev@vger.kernel.org · 5 unmodified lines
22988	L: bpf@vger.kernel.org	23003	L: bpf@vger.kernel.org
22989	S: Maintained	23004	S: Maintained
22990	F: Documentation/networking/af_xdp.rst	23005	F: Documentation/networking/af_xdp.rst
		23006	F: include/net/netns/xdp.h
22991	F: include/net/xdp_sock*	23007	F: include/net/xdp_sock*
22992	F: include/net/xsk_buff_pool.h	23008	F: include/net/xsk_buff_pool.h
22993	F: include/uapi/linux/if_xdp.h	23009	F: include/uapi/linux/if_xdp.h
22994	F: include/uapi/linux/xdp_diag.h	23010	F: include/uapi/linux/xdp_diag.h
22995	F: include/net/netns/xdp.h
22996	F: net/xdp/	23011	F: net/xdp/
22997	F: tools/testing/selftests/bpf/xsk	23012	F: tools/testing/selftests/bpf/xsk
22998		23013
@@ -23094,11 +23109,11 @@ F: include/xen/arm/swiotlb-xen.h · 95 unmodified lines
23094	F: include/xen/swiotlb-xen.h	23109	F: include/xen/swiotlb-xen.h
23095		23110
23096	XFS FILESYSTEM	23111	XFS FILESYSTEM
23097	C: irc://irc.oftc.net/xfs
23098	M: Darrick J. Wong <djwong@kernel.org>	23112	M: Darrick J. Wong <djwong@kernel.org>
23099	L: linux-xfs@vger.kernel.org	23113	L: linux-xfs@vger.kernel.org
23100	S: Supported	23114	S: Supported
23101	W: http://xfs.org/	23115	W: http://xfs.org/
		23116	C: irc://irc.oftc.net/xfs
23102	T: git git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git	23117	T: git git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git
23103	F: Documentation/ABI/testing/sysfs-fs-xfs	23118	F: Documentation/ABI/testing/sysfs-fs-xfs
23104	F: Documentation/admin-guide/xfs.rst	23119	F: Documentation/admin-guide/xfs.rst
@@ -23128,16 +23143,28 @@ S: Maintained · 23 unmodified lines
23128	F: Documentation/devicetree/bindings/net/can/xilinx,can.yaml	23143	F: Documentation/devicetree/bindings/net/can/xilinx,can.yaml
23129	F: drivers/net/can/xilinx_can.c	23144	F: drivers/net/can/xilinx_can.c
23130		23145
		23146	XILINX EVENT MANAGEMENT DRIVER
		23147	M: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
		23148	S: Maintained
		23149	F: drivers/soc/xilinx/xlnx_event_manager.c
		23150	F: include/linux/firmware/xlnx-event-manager.h
		23151
23131	XILINX GPIO DRIVER	23152	XILINX GPIO DRIVER
23132	M: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>	23153	M: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
23133	R: Srinivas Neeli <srinivas.neeli@xilinx.com>	23154	R: Srinivas Neeli <srinivas.neeli@xilinx.com>
23134	R: Michal Simek <michal.simek@amd.com>	23155	R: Michal Simek <michal.simek@amd.com>
23135	S: Maintained	23156	S: Maintained
23136	F: Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
23137	F: Documentation/devicetree/bindings/gpio/gpio-zynq.yaml	23157	F: Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
		23158	F: Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
23138	F: drivers/gpio/gpio-xilinx.c	23159	F: drivers/gpio/gpio-xilinx.c
23139	F: drivers/gpio/gpio-zynq.c	23160	F: drivers/gpio/gpio-zynq.c
23140		23161
		23162	XILINX PWM DRIVER
		23163	M: Sean Anderson <sean.anderson@seco.com>
		23164	S: Maintained
		23165	F: drivers/pwm/pwm-xilinx.c
		23166	F: include/clocksource/timer-xilinx.h
		23167
23141	XILINX SD-FEC IP CORES	23168	XILINX SD-FEC IP CORES
23142	M: Derek Kiernan <derek.kiernan@xilinx.com>	23169	M: Derek Kiernan <derek.kiernan@xilinx.com>
23143	M: Dragan Cvetic <dragan.cvetic@xilinx.com>	23170	M: Dragan Cvetic <dragan.cvetic@xilinx.com>
@@ -23149,12 +23176,6 @@ F: drivers/misc/Makefile · 5 unmodified lines
23149	F: drivers/misc/xilinx_sdfec.c	23176	F: drivers/misc/xilinx_sdfec.c
23150	F: include/uapi/misc/xilinx_sdfec.h	23177	F: include/uapi/misc/xilinx_sdfec.h
23151		23178
23152	XILINX PWM DRIVER
23153	M: Sean Anderson <sean.anderson@seco.com>
23154	S: Maintained
23155	F: drivers/pwm/pwm-xilinx.c
23156	F: include/clocksource/timer-xilinx.h
23157
23158	XILINX UARTLITE SERIAL DRIVER	23179	XILINX UARTLITE SERIAL DRIVER
23159	M: Peter Korsgaard <jacmet@sunsite.dk>	23180	M: Peter Korsgaard <jacmet@sunsite.dk>
23160	L: linux-serial@vger.kernel.org	23181	L: linux-serial@vger.kernel.org
@@ -23220,12 +23241,6 @@ M: Harsha <harsha.harsha@xilinx.com> · 59 unmodified lines
23220	S: Maintained	23241	S: Maintained
23221	F: drivers/crypto/xilinx/zynqmp-sha.c	23242	F: drivers/crypto/xilinx/zynqmp-sha.c
23222		23243
23223	XILINX EVENT MANAGEMENT DRIVER
23224	M: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
23225	S: Maintained
23226	F: drivers/soc/xilinx/xlnx_event_manager.c
23227	F: include/linux/firmware/xlnx-event-manager.h
23228
23229	XILLYBUS DRIVER	23244	XILLYBUS DRIVER
23230	M: Eli Billauer <eli.billauer@gmail.com>	23245	M: Eli Billauer <eli.billauer@gmail.com>
23231	L: linux-kernel@vger.kernel.org	23246	L: linux-kernel@vger.kernel.org
@@ -23273,6 +23288,13 @@ S: Maintained · 41 unmodified lines
23273	F: Documentation/input/devices/yealink.rst	23288	F: Documentation/input/devices/yealink.rst
23274	F: drivers/input/misc/yealink.*	23289	F: drivers/input/misc/yealink.*
23275		23290
		23291	Z3FOLD COMPRESSED PAGE ALLOCATOR
		23292	M: Vitaly Wool <vitaly.wool@konsulko.com>
		23293	R: Miaohe Lin <linmiaohe@huawei.com>
		23294	L: linux-mm@kvack.org
		23295	S: Maintained
		23296	F: mm/z3fold.c
		23297
23276	Z8530 DRIVER FOR AX.25	23298	Z8530 DRIVER FOR AX.25
23277	M: Joerg Reuter <jreuter@yaina.de>	23299	M: Joerg Reuter <jreuter@yaina.de>
23278	L: linux-hams@vger.kernel.org	23300	L: linux-hams@vger.kernel.org
@@ -23290,13 +23312,6 @@ L: linux-mm@kvack.org · 11 unmodified lines
23290	S: Maintained	23312	S: Maintained
23291	F: mm/zbud.c	23313	F: mm/zbud.c
23292		23314
23293	Z3FOLD COMPRESSED PAGE ALLOCATOR
23294	M: Vitaly Wool <vitaly.wool@konsulko.com>
23295	R: Miaohe Lin <linmiaohe@huawei.com>
23296	L: linux-mm@kvack.org
23297	S: Maintained
23298	F: mm/z3fold.c
23299
23300	ZD1211RW WIRELESS DRIVER	23315	ZD1211RW WIRELESS DRIVER
23301	M: Ulrich Kunitz <kune@deine-taler.de>	23316	M: Ulrich Kunitz <kune@deine-taler.de>
23302	L: linux-wireless@vger.kernel.org	23317	L: linux-wireless@vger.kernel.org
@@ -23383,10 +23398,10 @@ M: Nick Terrell <terrelln@fb.com> · 80 unmodified lines
23383	S: Maintained	23398	S: Maintained
23384	B: https://github.com/facebook/zstd/issues	23399	B: https://github.com/facebook/zstd/issues
23385	T: git https://github.com/terrelln/linux.git	23400	T: git https://github.com/terrelln/linux.git
		23401	F: crypto/zstd.c
23386	F: include/linux/zstd*	23402	F: include/linux/zstd*
23387	F: lib/zstd/
23388	F: lib/decompress_unzstd.c	23403	F: lib/decompress_unzstd.c
23389	F: crypto/zstd.c	23404	F: lib/zstd/
23390	N: zstd	23405	N: zstd
23391	K: zstd	23406	K: zstd
23392		23407
@@ -23398,13 +23413,6 @@ L: linux-mm@kvack.org · 5 unmodified lines
23398	S: Maintained	23413	S: Maintained
23399	F: mm/zswap.c	23414	F: mm/zswap.c
23400		23415
23401	NXP BLUETOOTH WIRELESS DRIVERS
23402	M: Amitkumar Karwar <amitkumar.karwar@nxp.com>
23403	M: Neeraj Kale <neeraj.sanjaykale@nxp.com>
23404	S: Maintained
23405	F: Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml
23406	F: drivers/bluetooth/btnxpuart.c
23407
23408	THE REST	23416	THE REST
23409	M: Linus Torvalds <torvalds@linux-foundation.org>	23417	M: Linus Torvalds <torvalds@linux-foundation.org>
23410	L: linux-kernel@vger.kernel.org	23418	L: linux-kernel@vger.kernel.org

Makefile+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2	VERSION = 6	2	VERSION = 6
3	PATCHLEVEL = 4	3	PATCHLEVEL = 4
4	SUBLEVEL = 0	4	SUBLEVEL = 0
5	EXTRAVERSION = -rc1	5	EXTRAVERSION = -rc2
6	NAME = Hurr durr I'ma ninja sloth	6	NAME = Hurr durr I'ma ninja sloth
7		7
8	# DOCUMENTATION	8	# DOCUMENTATION

arch/arc/include/asm/fb.h+2−14

@@ -1,20 +1,8 @@
1	/* SPDX-License-Identifier: GPL-2.0 */	1	/* SPDX-License-Identifier: GPL-2.0 */
		2
2	#ifndef _ASM_FB_H_	3	#ifndef _ASM_FB_H_
3	#define _ASM_FB_H_	4	#define _ASM_FB_H_
4		5
5	#include <linux/fb.h>	6	#include <asm-generic/fb.h>
6	#include <linux/fs.h>
7	#include <asm/page.h>
8
9	static inline void fb_pgprotect(struct file file, struct vm_area_struct vma,
10	unsigned long off)
11	{
12	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
13	}
14
15	static inline int fb_is_primary_device(struct fb_info *info)
16	{
17	return 0;
18	}
19		7
20	#endif /* _ASM_FB_H_ */	8	#endif /* _ASM_FB_H_ */

arch/arm/include/asm/fb.h+1−14

@@ -1,19 +1,6 @@
1	#ifndef _ASM_FB_H_	1	#ifndef _ASM_FB_H_
2	#define _ASM_FB_H_	2	#define _ASM_FB_H_
3		3
4	#include <linux/fb.h>	4	#include <asm-generic/fb.h>
5	#include <linux/fs.h>
6	#include <asm/page.h>
7
8	static inline void fb_pgprotect(struct file file, struct vm_area_struct vma,
9	unsigned long off)
10	{
11	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
12	}
13
14	static inline int fb_is_primary_device(struct fb_info *info)
15	{
16	return 0;
17	}
18		5
19	#endif /* _ASM_FB_H_ */	6	#endif /* _ASM_FB_H_ */

arch/arm/kernel/unwind.c+24−1

@@ -308,6 +308,29 @@ static int unwind_exec_pop_subset_r0_to_r3(struct unwind_ctrl_block *ctrl, · 307 unmodified lines
308	return URC_OK;	308	return URC_OK;
309	}	309	}
310		310
		311	static unsigned long unwind_decode_uleb128(struct unwind_ctrl_block *ctrl)
		312	{
		313	unsigned long bytes = 0;
		314	unsigned long insn;
		315	unsigned long result = 0;
		316
		317	/*
		318	* unwind_get_byte() will advance `ctrl` one instruction at a time, so
		319	* loop until we get an instruction byte where bit 7 is not set.
		320	*
		321	* Note: This decodes a maximum of 4 bytes to output 28 bits data where
		322	* max is 0xfffffff: that will cover a vsp increment of 1073742336, hence
		323	* it is sufficient for unwinding the stack.
		324	*/
		325	do {
		326	insn = unwind_get_byte(ctrl);
		327	result \|= (insn & 0x7f) << (bytes * 7);
		328	bytes++;
		329	} while (!!(insn & 0x80) && (bytes != sizeof(result)));
		330
		331	return result;
		332	}
		333
311	/*	334	/*
312	* Execute the current unwind instruction.	335	* Execute the current unwind instruction.
313	*/	336	*/
@@ -361,7 +384,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) · 47 unmodified lines
361	if (ret)	384	if (ret)
362	goto error;	385	goto error;
363	} else if (insn == 0xb2) {	386	} else if (insn == 0xb2) {
364	unsigned long uleb128 = unwind_get_byte(ctrl);	387	unsigned long uleb128 = unwind_decode_uleb128(ctrl);
365		388
366	ctrl->vrs[SP] += 0x204 + (uleb128 << 2);	389	ctrl->vrs[SP] += 0x204 + (uleb128 << 2);
367	} else {	390	} else {

arch/arm/mach-sa1100/jornada720_ssp.c+4−1

 // SPDX-License-Identifier: GPL-2.0-only
-/**
+/*
  *  arch/arm/mac-sa1100/jornada720_ssp.c
  *
  *  Copyright (C) 2006/2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
 /**
  * jornada_ssp_reverse - reverses input byte
+ * @byte: input byte to reverse
  *
  * we need to reverse all data we receive from the mcu due to its physical location
  * returns : 01110111 -> 11101110
 /**
  * jornada_ssp_byte - waits for ready ssp bus and sends byte
+ * @byte: input byte to transmit
  *
  * waits for fifo buffer to clear and then transmits, if it doesn't then we will
  * timeout after <timeout> rounds. Needs mcu running before its called.
 /**
  * jornada_ssp_inout - decide if input is command or trading byte
+ * @byte: input byte to send (may be %TXDUMMY)
  *
  * returns : (jornada_ssp_byte(byte)) on success
  *         : %-ETIMEDOUT on timeout failure

arch/arm/vfp/entry.S+5−2

 @
 ENTRY(do_vfp)
 	mov	r1, r10
-	mov	r3, r9
+	str	lr, [sp, #-8]!
-	b	vfp_entry
+	add	r3, sp, #4
+	str	r9, [r3]
+	bl	vfp_entry
+	ldr	pc, [sp], #8
 ENDPROC(do_vfp)

arch/arm/vfp/vfphw.S+4−2

 					@ out before setting an FPEXC that
 					@ stops us reading stuff
 	VFPFMXR	FPEXC, r1		@ Restore FPEXC last
+	mov	sp, r3			@ we think we have handled things
+	pop	{lr}
 	sub	r2, r2, #4		@ Retry current instruction - if Thumb
 	str	r2, [sp, #S_PC]		@ mode it's two 16-bit instructions,
 					@ else it's one 32-bit instruction, so
 					@ always subtract 4 from the following
 					@ instruction address.
-	mov	lr, r3			@ we think we have handled things
 local_bh_enable_and_ret:
 	adr	r0, .
 	mov	r1, #SOFTIRQ_DISABLE_OFFSET
 process_exception:
 	DBGSTR	"bounce"
+	mov	sp, r3			@ setup for a return to the user code.
+	pop	{lr}
 	mov	r2, sp			@ nothing stacked - regdump is at TOS
-	mov	lr, r3			@ setup for a return to the user code.
 	@ Now call the C code to package up the bounce to the support code
 	@   r0 holds the trigger instruction

arch/arm64/include/asm/fb.h+1−14

@@ -5,19 +5,6 @@ · 4 unmodified lines
5	#ifndef __ASM_FB_H_	5	#ifndef __ASM_FB_H_
6	#define __ASM_FB_H_	6	#define __ASM_FB_H_
7		7
8	#include <linux/fb.h>	8	#include <asm-generic/fb.h>
9	#include <linux/fs.h>
10	#include <asm/page.h>
11
12	static inline void fb_pgprotect(struct file file, struct vm_area_struct vma,
13	unsigned long off)
14	{
15	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
16	}
17
18	static inline int fb_is_primary_device(struct fb_info *info)
19	{
20	return 0;
21	}
22		9
23	#endif /* __ASM_FB_H_ */	10	#endif /* __ASM_FB_H_ */

arch/ia64/include/asm/fb.h+23−4

 #ifndef _ASM_FB_H_
 #define _ASM_FB_H_
-#include <linux/fb.h>
+#include <linux/compiler.h>
-#include <linux/fs.h>
 #include <linux/efi.h>
+#include <linux/string.h>
 #include <asm/page.h>
+struct file;
 static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
 				unsigned long off)
 {
 	else
 		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 }
+#define fb_pgprotect fb_pgprotect
+static inline void fb_memcpy_fromio(void *to, const volatile void __iomem *from, size_t n)
+{
+	memcpy(to, (void __force *)from, n);
+}
+#define fb_memcpy_fromio fb_memcpy_fromio
-static inline int fb_is_primary_device(struct fb_info *info)
+static inline void fb_memcpy_toio(volatile void __iomem *to, const void *from, size_t n)
 {
-	return 0;
+	memcpy((void __force *)to, from, n);
 }
+#define fb_memcpy_toio fb_memcpy_toio
+static inline void fb_memset_io(volatile void __iomem *addr, int c, size_t n)
+{
+	memset((void __force *)addr, c, n);
+}
+#define fb_memset fb_memset_io
+#include <asm-generic/fb.h>
 #endif /* _ASM_FB_H_ */

arch/loongarch/include/asm/fb.h+16−8

 #ifndef _ASM_FB_H_
 #define _ASM_FB_H_
-#include <linux/fb.h>
+#include <linux/compiler.h>
-#include <linux/fs.h>
+#include <linux/string.h>
-#include <asm/page.h>
-static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+static inline void fb_memcpy_fromio(void *to, const volatile void __iomem *from, size_t n)
-				unsigned long off)
 {
-	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+	memcpy(to, (void __force *)from, n);
 }
+#define fb_memcpy_fromio fb_memcpy_fromio
-static inline int fb_is_primary_device(struct fb_info *info)
+static inline void fb_memcpy_toio(volatile void __iomem *to, const void *from, size_t n)
 {
-	return 0;
+	memcpy((void __force *)to, from, n);
 }
+#define fb_memcpy_toio fb_memcpy_toio
+static inline void fb_memset_io(volatile void __iomem *addr, int c, size_t n)
+{
+	memset((void __force *)addr, c, n);
+}
+#define fb_memset fb_memset_io
+#include <asm-generic/fb.h>
 #endif /* _ASM_FB_H_ */

arch/m68k/include/asm/fb.h+7−15

@@ -2,22 +2,18 @@ · 1 unmodified line
2	#ifndef _ASM_FB_H_	2	#ifndef _ASM_FB_H_
3	#define _ASM_FB_H_	3	#define _ASM_FB_H_
4		4
5	#include <linux/fb.h>
6	#include <linux/fs.h>
7	#include <asm/page.h>	5	#include <asm/page.h>
8	#include <asm/setup.h>	6	#include <asm/setup.h>
9		7
10	#ifdef CONFIG_MMU	8	struct file;
11	#ifdef CONFIG_SUN3	9
12	static inline void fb_pgprotect(struct file file, struct vm_area_struct vma,	10	static inline void fb_pgprotect(struct file file, struct vm_area_struct vma,
13	unsigned long off)	11	unsigned long off)
14	{	12	{
		13	#ifdef CONFIG_MMU
		14	#ifdef CONFIG_SUN3
15	pgprot_val(vma->vm_page_prot) \|= SUN3_PAGE_NOCACHE;	15	pgprot_val(vma->vm_page_prot) \|= SUN3_PAGE_NOCACHE;
16	}
17	#else	16	#else
18	static inline void fb_pgprotect(struct file file, struct vm_area_struct vma,
19	unsigned long off)
20	{
21	if (CPU_IS_020_OR_030)	17	if (CPU_IS_020_OR_030)
22	pgprot_val(vma->vm_page_prot) \|= _PAGE_NOCACHE030;	18	pgprot_val(vma->vm_page_prot) \|= _PAGE_NOCACHE030;
23	if (CPU_IS_040_OR_060) {	19	if (CPU_IS_040_OR_060) {
@@ -25,15 +21,11 @@ static inline void fb_pgprotect(struct file file, struct vm_area_struct vma, · 1 unmodified line
25	/* Use no-cache mode, serialized */	21	/* Use no-cache mode, serialized */
26	pgprot_val(vma->vm_page_prot) \|= _PAGE_NOCACHE_S;	22	pgprot_val(vma->vm_page_prot) \|= _PAGE_NOCACHE_S;
27	}	23	}
28	}
29	#endif /* CONFIG_SUN3 */	24	#endif /* CONFIG_SUN3 */
30	#else
31	#define fb_pgprotect(...) do {} while (0)
32	#endif /* CONFIG_MMU */	25	#endif /* CONFIG_MMU */
33
34	static inline int fb_is_primary_device(struct fb_info *info)
35	{
36	return 0;
37	}	26	}
		27	#define fb_pgprotect fb_pgprotect
		28
		29	#include <asm-generic/fb.h>
38		30
39	#endif /* _ASM_FB_H_ */	31	#endif /* _ASM_FB_H_ */

arch/mips/include/asm/fb.h+24−4

@@ -1,19 +1,39 @@
1	#ifndef _ASM_FB_H_	1	#ifndef _ASM_FB_H_
2	#define _ASM_FB_H_	2	#define _ASM_FB_H_
3		3
4	#include <linux/fb.h>
5	#include <linux/fs.h>
6	#include <asm/page.h>	4	#include <asm/page.h>
7		5
		6	struct file;
		7
8	static inline void fb_pgprotect(struct file file, struct vm_area_struct vma,	8	static inline void fb_pgprotect(struct file file, struct vm_area_struct vma,
9	unsigned long off)	9	unsigned long off)
10	{	10	{
11	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);	11	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
12	}	12	}
		13	#define fb_pgprotect fb_pgprotect
13		14
14	static inline int fb_is_primary_device(struct fb_info *info)	15	/*
		16	* MIPS doesn't define __raw_ I/O macros, so the helpers
		17	* in <asm-generic/fb.h> don't generate fb_readq() and
		18	* fb_write(). We have to provide them here.
		19	*
		20	* TODO: Convert MIPS to generic I/O. The helpers below can
		21	* then be removed.
		22	*/
		23	#ifdef CONFIG_64BIT
		24	static inline u64 fb_readq(const volatile void __iomem *addr)
15	{	25	{
16	return 0;	26	return __raw_readq(addr);
17	}	27	}
		28	#define fb_readq fb_readq
		29
		30	static inline void fb_writeq(u64 b, volatile void __iomem *addr)
		31	{
		32	__raw_writeq(b, addr);
		33	}
		34	#define fb_writeq fb_writeq
		35	#endif
		36
		37	#include <asm-generic/fb.h>
18		38
19	#endif /* _ASM_FB_H_ */	39	#endif /* _ASM_FB_H_ */

arch/parisc/Makefile+3−1

 # Copyright (C) 1994 by Linus Torvalds
 # Portions Copyright (C) 1999 The Puffin Group
 #
 # Modified for PA-RISC Linux by Paul Lahaie, Alex deVries,
 # Mike Shaver, Helge Deller and Martin K. Petersen
 #
 libs-y	+= arch/parisc/lib/ $(LIBGCC)
+drivers-y += arch/parisc/video/
 boot	:= arch/parisc/boot
 PALO := $(shell if (which palo 2>&1); then : ; \

arch/parisc/include/asm/fb.h+5−15

 #ifndef _ASM_FB_H_
 #define _ASM_FB_H_
-#include <linux/fb.h>
+struct fb_info;
-#include <linux/fs.h>
-#include <asm/page.h>
-static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+#if defined(CONFIG_STI_CORE)
-				unsigned long off)
-{
-	pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE;
-}
-#if defined(CONFIG_FB_STI)
 int fb_is_primary_device(struct fb_info *info);
-#else
+#define fb_is_primary_device fb_is_primary_device
-static inline int fb_is_primary_device(struct fb_info *info)
-{
-	return 0;
-}
 #endif
+#include <asm-generic/fb.h>
 #endif /* _ASM_FB_H_ */

arch/parisc/include/asm/pgtable.h+4−4

@@ -413,12 +413,12 @@ extern void paging_init (void); · 412 unmodified lines
413	* For the 64bit version, the offset is extended by 32bit.	413	* For the 64bit version, the offset is extended by 32bit.
414	*/	414	*/
415	#define __swp_type(x) ((x).val & 0x1f)	415	#define __swp_type(x) ((x).val & 0x1f)
416	#define __swp_offset(x) ( (((x).val >> 6) & 0x7) \| \	416	#define __swp_offset(x) ( (((x).val >> 5) & 0x7) \| \
417	(((x).val >> 8) & ~0x7) )	417	(((x).val >> 10) << 3) )
418	#define __swp_entry(type, offset) ((swp_entry_t) { \	418	#define __swp_entry(type, offset) ((swp_entry_t) { \
419	((type) & 0x1f) \| \	419	((type) & 0x1f) \| \
420	((offset & 0x7) << 6) \| \	420	((offset & 0x7) << 5) \| \
421	((offset & ~0x7) << 8) })	421	((offset >> 3) << 10) })
422	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })	422	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
423	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })	423	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
424		424

arch/parisc/kernel/kexec.c+2−0

@@ -4,6 +4,8 @@ · 3 unmodified lines
4	#include <linux/console.h>	4	#include <linux/console.h>
5	#include <linux/kexec.h>	5	#include <linux/kexec.h>
6	#include <linux/delay.h>	6	#include <linux/delay.h>
		7	#include <linux/reboot.h>
		8
7	#include <asm/cacheflush.h>	9	#include <asm/cacheflush.h>
8	#include <asm/sections.h>	10	#include <asm/sections.h>
9		11

arch/parisc/video/Makefile+3−0

@@ -0,0 +1,3 @@
	1	# SPDX-License-Identifier: GPL-2.0-only
	2
	3	obj-$(CONFIG_STI_CORE) += fbdev.o

arch/parisc/video/fbdev.c+26−0

@@ -0,0 +1,26 @@
	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
	4	* Copyright (C) 2001-2020 Helge Deller <deller@gmx.de>
	5	* Copyright (C) 2001-2002 Thomas Bogendoerfer <tsbogend@alpha.franken.de>
	6	*/
	7
	8	#include <linux/fb.h>
	9	#include <linux/module.h>
	10
	11	#include <video/sticore.h>
	12
	13	int fb_is_primary_device(struct fb_info *info)
	14	{
	15	struct sti_struct *sti;
	16
	17	sti = sti_get_rom(0);
	18
	19	/* if no built-in graphics card found, allow any fb driver as default */
	20	if (!sti)
	21	return true;
	22
	23	/* return true if it's the default built-in framebuffer driver */
	24	return (sti->info == info);
	25	}
	26	EXPORT_SYMBOL(fb_is_primary_device);

arch/powerpc/include/asm/fb.h+3−5

 #ifndef _ASM_FB_H_
 #define _ASM_FB_H_
-#include <linux/fb.h>
 #include <linux/fs.h>
 #include <asm/page.h>
 static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
 						 vma->vm_end - vma->vm_start,
 						 vma->vm_page_prot);
 }
+#define fb_pgprotect fb_pgprotect
-static inline int fb_is_primary_device(struct fb_info *info)
+#include <asm-generic/fb.h>
-{
-	return 0;
-}
 #endif /* _ASM_FB_H_ */

arch/riscv/kernel/pi/Makefile+1−1

@@ -22,7 +22,7 @@ KCOV_INSTRUMENT := n · 21 unmodified lines
22		22
23	$(obj)/%.pi.o: OBJCOPYFLAGS := --prefix-symbols=__pi_ \	23	$(obj)/%.pi.o: OBJCOPYFLAGS := --prefix-symbols=__pi_ \
24	--remove-section=.note.gnu.property \	24	--remove-section=.note.gnu.property \
25	--prefix-alloc-sections=.init	25	--prefix-alloc-sections=.init.pi
26	$(obj)/%.pi.o: $(obj)/%.o FORCE	26	$(obj)/%.pi.o: $(obj)/%.o FORCE
27	$(call if_changed,objcopy)	27	$(call if_changed,objcopy)
28		28

arch/riscv/kernel/vmlinux.lds.S+2−5

 	__init_data_begin = .;
 	INIT_DATA_SECTION(16)
-	/* Those sections result from the compilation of kernel/pi/string.c */
+	.init.pi : {
-	.init.pidata : {
+		*(.init.pi*)
-		*(.init.srodata.cst8*)
-		*(.init__bug_table*)
-		*(.init.sdata*)
 	}
 	.init.bss : {

arch/sh/include/asm/fb.h+1−14

@@ -2,19 +2,6 @@ · 1 unmodified line
2	#ifndef _ASM_FB_H_	2	#ifndef _ASM_FB_H_
3	#define _ASM_FB_H_	3	#define _ASM_FB_H_
4		4
5	#include <linux/fb.h>	5	#include <asm-generic/fb.h>
6	#include <linux/fs.h>
7	#include <asm/page.h>
8
9	static inline void fb_pgprotect(struct file file, struct vm_area_struct vma,
10	unsigned long off)
11	{
12	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
13	}
14
15	static inline int fb_is_primary_device(struct fb_info *info)
16	{
17	return 0;
18	}
19		6
20	#endif /* _ASM_FB_H_ */	7	#endif /* _ASM_FB_H_ */

arch/sparc/Makefile+1−0

@@ -60,6 +60,7 @@ libs-y += arch/sparc/prom/ · 59 unmodified lines
60	libs-y += arch/sparc/lib/	60	libs-y += arch/sparc/lib/
61		61
62	drivers-$(CONFIG_PM) += arch/sparc/power/	62	drivers-$(CONFIG_PM) += arch/sparc/power/
		63	drivers-$(CONFIG_FB) += arch/sparc/video/
63		64
64	boot := arch/sparc/boot	65	boot := arch/sparc/boot
65		66

arch/sparc/include/asm/fb.h+27−20

 /* SPDX-License-Identifier: GPL-2.0 */
 #ifndef _SPARC_FB_H_
 #define _SPARC_FB_H_
-#include <linux/console.h>
-#include <linux/fb.h>
-#include <linux/fs.h>
-#include <asm/page.h>
-#include <asm/prom.h>
+#include <linux/io.h>
+struct fb_info;
+struct file;
+struct vm_area_struct;
+#ifdef CONFIG_SPARC32
 static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
 				unsigned long off)
-{
+{ }
-#ifdef CONFIG_SPARC64
+#define fb_pgprotect fb_pgprotect
-	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 #endif
-}
-static inline int fb_is_primary_device(struct fb_info *info)
+int fb_is_primary_device(struct fb_info *info);
-{
+#define fb_is_primary_device fb_is_primary_device
-	struct device *dev = info->device;
-	struct device_node *node;
-	if (console_set_on_cmdline)
+static inline void fb_memcpy_fromio(void *to, const volatile void __iomem *from, size_t n)
-		return 0;
+{
+	sbus_memcpy_fromio(to, from, n);
+}
+#define fb_memcpy_fromio fb_memcpy_fromio
-	node = dev->of_node;
+static inline void fb_memcpy_toio(volatile void __iomem *to, const void *from, size_t n)
-	if (node &&
+{
-	    node == of_console_device)
+	sbus_memcpy_toio(to, from, n);
-		return 1;
+}
+#define fb_memcpy_toio fb_memcpy_toio
-	return 0;
+static inline void fb_memset_io(volatile void __iomem *addr, int c, size_t n)
+{
+	sbus_memset_io(addr, c, n);
 }
+#define fb_memset fb_memset_io
+#include <asm-generic/fb.h>
 #endif /* _SPARC_FB_H_ */

arch/sparc/video/Makefile+3−0

@@ -0,0 +1,3 @@
	1	# SPDX-License-Identifier: GPL-2.0-only
	2
	3	obj-$(CONFIG_FB) += fbdev.o

arch/sparc/video/fbdev.c+23−0

@@ -0,0 +1,23 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2
	3	#include <linux/console.h>
	4	#include <linux/fb.h>
	5	#include <linux/module.h>
	6
	7	#include <asm/prom.h>
	8
	9	int fb_is_primary_device(struct fb_info *info)
	10	{
	11	struct device *dev = info->device;
	12	struct device_node *node;
	13
	14	if (console_set_on_cmdline)
	15	return 0;
	16
	17	node = dev->of_node;
	18	if (node && node == of_console_device)
	19	return 1;
	20
	21	return 0;
	22	}
	23	EXPORT_SYMBOL(fb_is_primary_device);

arch/x86/events/core.c+2−4

@@ -1703,10 +1703,8 @@ int x86_pmu_handle_irq(struct pt_regs *regs) · 1702 unmodified lines
1703		1703
1704	perf_sample_data_init(&data, 0, event->hw.last_period);	1704	perf_sample_data_init(&data, 0, event->hw.last_period);
1705		1705
1706	if (has_branch_stack(event)) {	1706	if (has_branch_stack(event))
1707	data.br_stack = &cpuc->lbr_stack;	1707	perf_sample_save_brstack(&data, event, &cpuc->lbr_stack);
1708	data.sample_flags \|= PERF_SAMPLE_BRANCH_STACK;
1709	}
1710		1708
1711	if (perf_event_overflow(event, &data, regs))	1709	if (perf_event_overflow(event, &data, regs))
1712	x86_pmu_stop(event, 0);	1710	x86_pmu_stop(event, 0);

arch/x86/events/intel/ds.c+32−24

@@ -1229,12 +1229,14 @@ pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, · 1228 unmodified lines
1229	struct perf_event *event, bool add)	1229	struct perf_event *event, bool add)
1230	{	1230	{
1231	struct pmu *pmu = event->pmu;	1231	struct pmu *pmu = event->pmu;
		1232
1232	/*	1233	/*
1233	* Make sure we get updated with the first PEBS	1234	* Make sure we get updated with the first PEBS
1234	* event. It will trigger also during removal, but	1235	* event. It will trigger also during removal, but
1235	* that does not hurt:	1236	* that does not hurt:
1236	*/	1237	*/
1237	bool update = cpuc->n_pebs == 1;	1238	if (cpuc->n_pebs == 1)
		1239	cpuc->pebs_data_cfg = PEBS_UPDATE_DS_SW;
1238		1240
1239	if (needed_cb != pebs_needs_sched_cb(cpuc)) {	1241	if (needed_cb != pebs_needs_sched_cb(cpuc)) {
1240	if (!needed_cb)	1242	if (!needed_cb)
@@ -1242,7 +1244,7 @@ pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, · 1 unmodified line
1242	else	1244	else
1243	perf_sched_cb_dec(pmu);	1245	perf_sched_cb_dec(pmu);
1244		1246
1245	update = true;	1247	cpuc->pebs_data_cfg \|= PEBS_UPDATE_DS_SW;
1246	}	1248	}
1247		1249
1248	/*	1250	/*
@@ -1252,24 +1254,13 @@ pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, · 3 unmodified lines
1252	if (x86_pmu.intel_cap.pebs_baseline && add) {	1254	if (x86_pmu.intel_cap.pebs_baseline && add) {
1253	u64 pebs_data_cfg;	1255	u64 pebs_data_cfg;
1254		1256
1255	/* Clear pebs_data_cfg and pebs_record_size for first PEBS. */
1256	if (cpuc->n_pebs == 1) {
1257	cpuc->pebs_data_cfg = 0;
1258	cpuc->pebs_record_size = sizeof(struct pebs_basic);
1259	}
1260
1261	pebs_data_cfg = pebs_update_adaptive_cfg(event);	1257	pebs_data_cfg = pebs_update_adaptive_cfg(event);
1262		1258	/*
1263	/* Update pebs_record_size if new event requires more data. */	1259	* Be sure to update the thresholds when we change the record.
1264	if (pebs_data_cfg & ~cpuc->pebs_data_cfg) {	1260	*/
1265	cpuc->pebs_data_cfg \|= pebs_data_cfg;	1261	if (pebs_data_cfg & ~cpuc->pebs_data_cfg)
1266	adaptive_pebs_record_size_update();	1262	cpuc->pebs_data_cfg \|= pebs_data_cfg \| PEBS_UPDATE_DS_SW;
1267	update = true;
1268	}
1269	}	1263	}
1270
1271	if (update)
1272	pebs_update_threshold(cpuc);
1273	}	1264	}
1274		1265
1275	void intel_pmu_pebs_add(struct perf_event *event)	1266	void intel_pmu_pebs_add(struct perf_event *event)
@@ -1326,9 +1317,17 @@ static void intel_pmu_pebs_via_pt_enable(struct perf_event *event) · 50 unmodified lines
1326	wrmsrl(base + idx, value);	1317	wrmsrl(base + idx, value);
1327	}	1318	}
1328		1319
		1320	static inline void intel_pmu_drain_large_pebs(struct cpu_hw_events *cpuc)
		1321	{
		1322	if (cpuc->n_pebs == cpuc->n_large_pebs &&
		1323	cpuc->n_pebs != cpuc->n_pebs_via_pt)
		1324	intel_pmu_drain_pebs_buffer();
		1325	}
		1326
1329	void intel_pmu_pebs_enable(struct perf_event *event)	1327	void intel_pmu_pebs_enable(struct perf_event *event)
1330	{	1328	{
1331	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);	1329	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
		1330	u64 pebs_data_cfg = cpuc->pebs_data_cfg & ~PEBS_UPDATE_DS_SW;
1332	struct hw_perf_event *hwc = &event->hw;	1331	struct hw_perf_event *hwc = &event->hw;
1333	struct debug_store *ds = cpuc->ds;	1332	struct debug_store *ds = cpuc->ds;
1334	unsigned int idx = hwc->idx;	1333	unsigned int idx = hwc->idx;
@@ -1344,11 +1343,22 @@ void intel_pmu_pebs_enable(struct perf_event *event) · 9 unmodified lines
1344		1343
1345	if (x86_pmu.intel_cap.pebs_baseline) {	1344	if (x86_pmu.intel_cap.pebs_baseline) {
1346	hwc->config \|= ICL_EVENTSEL_ADAPTIVE;	1345	hwc->config \|= ICL_EVENTSEL_ADAPTIVE;
1347	if (cpuc->pebs_data_cfg != cpuc->active_pebs_data_cfg) {	1346	if (pebs_data_cfg != cpuc->active_pebs_data_cfg) {
1348	wrmsrl(MSR_PEBS_DATA_CFG, cpuc->pebs_data_cfg);	1347	/*
1349	cpuc->active_pebs_data_cfg = cpuc->pebs_data_cfg;	1348	* drain_pebs() assumes uniform record size;
		1349	* hence we need to drain when changing said
		1350	* size.
		1351	*/
		1352	intel_pmu_drain_large_pebs(cpuc);
		1353	adaptive_pebs_record_size_update();
		1354	wrmsrl(MSR_PEBS_DATA_CFG, pebs_data_cfg);
		1355	cpuc->active_pebs_data_cfg = pebs_data_cfg;
1350	}	1356	}
1351	}	1357	}
		1358	if (cpuc->pebs_data_cfg & PEBS_UPDATE_DS_SW) {
		1359	cpuc->pebs_data_cfg = pebs_data_cfg;
		1360	pebs_update_threshold(cpuc);
		1361	}
1352		1362
1353	if (idx >= INTEL_PMC_IDX_FIXED) {	1363	if (idx >= INTEL_PMC_IDX_FIXED) {
1354	if (x86_pmu.intel_cap.pebs_format < 5)	1364	if (x86_pmu.intel_cap.pebs_format < 5)
@@ -1391,9 +1401,7 @@ void intel_pmu_pebs_disable(struct perf_event *event) · 36 unmodified lines
1391	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);	1401	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1392	struct hw_perf_event *hwc = &event->hw;	1402	struct hw_perf_event *hwc = &event->hw;
1393		1403
1394	if (cpuc->n_pebs == cpuc->n_large_pebs &&	1404	intel_pmu_drain_large_pebs(cpuc);
1395	cpuc->n_pebs != cpuc->n_pebs_via_pt)
1396	intel_pmu_drain_pebs_buffer();
1397		1405
1398	cpuc->pebs_enabled &= ~(1ULL << hwc->idx);	1406	cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
1399		1407

arch/x86/include/asm/fb.h+8−13

@@ -2,21 +2,16 @@ · 1 unmodified line
2	#ifndef _ASM_X86_FB_H	2	#ifndef _ASM_X86_FB_H
3	#define _ASM_X86_FB_H	3	#define _ASM_X86_FB_H
4		4
5	#include <linux/fb.h>	5	struct fb_info;
6	#include <linux/fs.h>	6	struct file;
7	#include <asm/page.h>	7	struct vm_area_struct;
8		8
9	static inline void fb_pgprotect(struct file file, struct vm_area_struct vma,	9	void fb_pgprotect(struct file file, struct vm_area_struct vma, unsigned long off);
10	unsigned long off)	10	#define fb_pgprotect fb_pgprotect
11	{
12	unsigned long prot;
13		11
14	prot = pgprot_val(vma->vm_page_prot) & ~_PAGE_CACHE_MASK;	12	int fb_is_primary_device(struct fb_info *info);
15	if (boot_cpu_data.x86 > 3)	13	#define fb_is_primary_device fb_is_primary_device
16	pgprot_val(vma->vm_page_prot) =
17	prot \| cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS);
18	}
19		14
20	extern int fb_is_primary_device(struct fb_info *info);	15	#include <asm-generic/fb.h>
21		16
22	#endif /* _ASM_X86_FB_H */	17	#endif /* _ASM_X86_FB_H */

arch/x86/include/asm/perf_event.h+3−0

@@ -121,6 +121,9 @@ · 120 unmodified lines
121	#define PEBS_DATACFG_LBRS BIT_ULL(3)	121	#define PEBS_DATACFG_LBRS BIT_ULL(3)
122	#define PEBS_DATACFG_LBR_SHIFT 24	122	#define PEBS_DATACFG_LBR_SHIFT 24
123		123
		124	/* Steal the highest bit of pebs_data_cfg for SW usage */
		125	#define PEBS_UPDATE_DS_SW BIT_ULL(63)
		126
124	/*	127	/*
125	* Intel "Architectural Performance Monitoring" CPUID	128	* Intel "Architectural Performance Monitoring" CPUID
126	* detection/enumeration details:	129	* detection/enumeration details:

arch/x86/kernel/amd_nb.c+2−0

 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
 #define PCI_DEVICE_ID_AMD_19H_M60H_DF_F4 0x14e4
 #define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4 0x14f4
+#define PCI_DEVICE_ID_AMD_19H_M78H_DF_F4 0x12fc
 /* Protect the PCI config register pairs used for SMN. */
 static DEFINE_MUTEX(smn_mutex);
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
 	{}
 };

arch/x86/lib/retpoline.S+2−2

@@ -144,8 +144,8 @@ SYM_CODE_END(__x86_indirect_jump_thunk_array) · 143 unmodified lines
144	*/	144	*/
145	.align 64	145	.align 64
146	.skip 63, 0xcc	146	.skip 63, 0xcc
147	SYM_FUNC_START_NOALIGN(zen_untrain_ret);	147	SYM_START(zen_untrain_ret, SYM_L_GLOBAL, SYM_A_NONE)
148		148	ANNOTATE_NOENDBR
149	/*	149	/*
150	* As executed from zen_untrain_ret, this is:	150	* As executed from zen_untrain_ret, this is:
151	*	151	*

arch/x86/video/fbdev.c+15−13

  * for more details.
  *
  */
 #include <linux/fb.h>
-#include <linux/pci.h>
 #include <linux/module.h>
+#include <linux/pci.h>
 #include <linux/vgaarb.h>
+void fb_pgprotect(struct file *file, struct vm_area_struct *vma, unsigned long off)
+{
+	unsigned long prot;
+	prot = pgprot_val(vma->vm_page_prot) & ~_PAGE_CACHE_MASK;
+	if (boot_cpu_data.x86 > 3)
+		pgprot_val(vma->vm_page_prot) =
+			prot | cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS);
+}
+EXPORT_SYMBOL(fb_pgprotect);
 int fb_is_primary_device(struct fb_info *info)
 {
 	struct device *device = info->device;
-	struct pci_dev *default_device = vga_default_device();
 	struct pci_dev *pci_dev;
-	struct resource *res;
 	if (!device || !dev_is_pci(device))
 		return 0;
 	pci_dev = to_pci_dev(device);
-	if (default_device) {
+	if (pci_dev == vga_default_device())
-		if (pci_dev == default_device)
-			return 1;
-		return 0;
-	}
-	res = pci_dev->resource + PCI_ROM_RESOURCE;
-	if (res->flags & IORESOURCE_ROM_SHADOW)
 		return 1;
 	return 0;
 }
 EXPORT_SYMBOL(fb_is_primary_device);
 MODULE_LICENSE("GPL");

drivers/auxdisplay/cfag12864bfb.c+1−1

@@ -72,7 +72,7 @@ static int cfag12864bfb_probe(struct platform_device *device) · 71 unmodified lines
72	if (!info)	72	if (!info)
73	goto none;	73	goto none;
74		74
75	info->screen_base = (char __iomem *) cfag12864b_buffer;	75	info->screen_buffer = cfag12864b_buffer;
76	info->screen_size = CFAG12864B_SIZE;	76	info->screen_size = CFAG12864B_SIZE;
77	info->fbops = &cfag12864bfb_ops;	77	info->fbops = &cfag12864bfb_ops;
78	info->fix = cfag12864bfb_fix;	78	info->fix = cfag12864bfb_fix;

drivers/auxdisplay/ht16k33.c+1−1

@@ -640,7 +640,7 @@ static int ht16k33_fbdev_probe(struct device dev, struct ht16k33_priv priv, · 639 unmodified lines
640		640
641	INIT_DELAYED_WORK(&priv->work, ht16k33_fb_update);	641	INIT_DELAYED_WORK(&priv->work, ht16k33_fb_update);
642	fbdev->info->fbops = &ht16k33_fb_ops;	642	fbdev->info->fbops = &ht16k33_fb_ops;
643	fbdev->info->screen_base = (char __iomem *) fbdev->buffer;	643	fbdev->info->screen_buffer = fbdev->buffer;
644	fbdev->info->screen_size = HT16K33_FB_SIZE;	644	fbdev->info->screen_size = HT16K33_FB_SIZE;
645	fbdev->info->fix = ht16k33_fb_fix;	645	fbdev->info->fix = ht16k33_fb_fix;
646	fbdev->info->var = ht16k33_fb_var;	646	fbdev->info->var = ht16k33_fb_var;

drivers/block/nbd.c+2−2

@@ -1666,7 +1666,7 @@ static int nbd_dev_dbg_init(struct nbd_device *nbd) · 1665 unmodified lines
1666	return -EIO;	1666	return -EIO;
1667		1667
1668	dir = debugfs_create_dir(nbd_name(nbd), nbd_dbg_dir);	1668	dir = debugfs_create_dir(nbd_name(nbd), nbd_dbg_dir);
1669	if (!dir) {	1669	if (IS_ERR(dir)) {
1670	dev_err(nbd_to_dev(nbd), "Failed to create debugfs dir for '%s'\n",	1670	dev_err(nbd_to_dev(nbd), "Failed to create debugfs dir for '%s'\n",
1671	nbd_name(nbd));	1671	nbd_name(nbd));
1672	return -EIO;	1672	return -EIO;
@@ -1692,7 +1692,7 @@ static int nbd_dbg_init(void) · 19 unmodified lines
1692	struct dentry *dbg_dir;	1692	struct dentry *dbg_dir;
1693		1693
1694	dbg_dir = debugfs_create_dir("nbd", NULL);	1694	dbg_dir = debugfs_create_dir("nbd", NULL);
1695	if (!dbg_dir)	1695	if (IS_ERR(dbg_dir))
1696	return -EIO;	1696	return -EIO;
1697		1697
1698	nbd_dbg_dir = dbg_dir;	1698	nbd_dbg_dir = dbg_dir;

drivers/block/rnbd/rnbd-proto.h+1−1

@@ -241,7 +241,7 @@ static inline blk_opf_t rnbd_to_bio_flags(u32 rnbd_opf) · 240 unmodified lines
241	bio_opf = REQ_OP_WRITE;	241	bio_opf = REQ_OP_WRITE;
242	break;	242	break;
243	case RNBD_OP_FLUSH:	243	case RNBD_OP_FLUSH:
244	bio_opf = REQ_OP_FLUSH \| REQ_PREFLUSH;	244	bio_opf = REQ_OP_WRITE \| REQ_PREFLUSH;
245	break;	245	break;
246	case RNBD_OP_DISCARD:	246	case RNBD_OP_DISCARD:
247	bio_opf = REQ_OP_DISCARD;	247	bio_opf = REQ_OP_DISCARD;

drivers/block/ublk_drv.c+1−1

@@ -1281,7 +1281,7 @@ static inline int ublk_check_cmd_op(u32 cmd_op) · 1280 unmodified lines
1281	{	1281	{
1282	u32 ioc_type = _IOC_TYPE(cmd_op);	1282	u32 ioc_type = _IOC_TYPE(cmd_op);
1283		1283
1284	if (IS_ENABLED(CONFIG_BLKDEV_UBLK_LEGACY_OPCODES) && ioc_type != 'u')	1284	if (!IS_ENABLED(CONFIG_BLKDEV_UBLK_LEGACY_OPCODES) && ioc_type != 'u')
1285	return -EOPNOTSUPP;	1285	return -EOPNOTSUPP;
1286		1286
1287	if (ioc_type != 'u' && ioc_type != 0)	1287	if (ioc_type != 'u' && ioc_type != 0)

drivers/cxl/core/pci.c+1−0

@@ -571,6 +571,7 @@ void read_cdat_data(struct cxl_port *port) · 570 unmodified lines
571	/* Don't leave table data allocated on error */	571	/* Don't leave table data allocated on error */
572	devm_kfree(dev, cdat_table);	572	devm_kfree(dev, cdat_table);
573	dev_err(dev, "CDAT data read error\n");	573	dev_err(dev, "CDAT data read error\n");
		574	return;
574	}	575	}
575		576
576	port->cdat.table = cdat_table + sizeof(__le32);	577	port->cdat.table = cdat_table + sizeof(__le32);

drivers/dma-buf/dma-resv.c+1−1

@@ -660,7 +660,7 @@ EXPORT_SYMBOL_GPL(dma_resv_get_singleton); · 659 unmodified lines
660	* dma_resv_lock() already	660	* dma_resv_lock() already
661	* RETURNS	661	* RETURNS
662	* Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or	662	* Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or
663	* greater than zer on success.	663	* greater than zero on success.
664	*/	664	*/
665	long dma_resv_wait_timeout(struct dma_resv *obj, enum dma_resv_usage usage,	665	long dma_resv_wait_timeout(struct dma_resv *obj, enum dma_resv_usage usage,
666	bool intr, unsigned long timeout)	666	bool intr, unsigned long timeout)

drivers/dma-buf/sw_sync.c+1−1

@@ -85,7 +85,7 @@ static struct sync_timeline sync_timeline_create(const char name) · 84 unmodified lines
85		85
86	kref_init(&obj->kref);	86	kref_init(&obj->kref);
87	obj->context = dma_fence_context_alloc(1);	87	obj->context = dma_fence_context_alloc(1);
88	strlcpy(obj->name, name, sizeof(obj->name));	88	strscpy(obj->name, name, sizeof(obj->name));
89		89
90	obj->pt_tree = RB_ROOT;	90	obj->pt_tree = RB_ROOT;
91	INIT_LIST_HEAD(&obj->pt_list);	91	INIT_LIST_HEAD(&obj->pt_list);

drivers/firewire/net.c+11−10

@@ -706,21 +706,22 @@ static void fwnet_receive_packet(struct fw_card card, struct fw_request r, · 705 unmodified lines
706	int rcode;	706	int rcode;
707		707
708	if (destination == IEEE1394_ALL_NODES) {	708	if (destination == IEEE1394_ALL_NODES) {
709	kfree(r);	709	// Although the response to the broadcast packet is not necessarily required, the
710		710	// fw_send_response() function should still be called to maintain the reference
711	return;	711	// counting of the object. In the case, the call of function just releases the
712	}	712	// object as a result to decrease the reference counting.
713		713	rcode = RCODE_COMPLETE;
714	if (offset != dev->handler.offset)	714	} else if (offset != dev->handler.offset) {
715	rcode = RCODE_ADDRESS_ERROR;	715	rcode = RCODE_ADDRESS_ERROR;
716	else if (tcode != TCODE_WRITE_BLOCK_REQUEST)	716	} else if (tcode != TCODE_WRITE_BLOCK_REQUEST) {
717	rcode = RCODE_TYPE_ERROR;	717	rcode = RCODE_TYPE_ERROR;
718	else if (fwnet_incoming_packet(dev, payload, length,	718	} else if (fwnet_incoming_packet(dev, payload, length,
719	source, generation, false) != 0) {	719	source, generation, false) != 0) {
720	dev_err(&dev->netdev->dev, "incoming packet failure\n");	720	dev_err(&dev->netdev->dev, "incoming packet failure\n");
721	rcode = RCODE_CONFLICT_ERROR;	721	rcode = RCODE_CONFLICT_ERROR;
722	} else	722	} else {
723	rcode = RCODE_COMPLETE;	723	rcode = RCODE_COMPLETE;
		724	}
724		725
725	fw_send_response(card, r, rcode);	726	fw_send_response(card, r, rcode);
726	}	727	}

drivers/firmware/sysfb.c+1−1

@@ -128,4 +128,4 @@ unlock_mutex: · 127 unmodified lines
128	}	128	}
129		129
130	/* must execute after PCI subsystem for EFI quirks */	130	/* must execute after PCI subsystem for EFI quirks */
131	device_initcall(sysfb_init);	131	subsys_initcall_sync(sysfb_init);

drivers/firmware/sysfb_simplefb.c+3−1

 	 *
 	 * It's not easily possible to fix this in struct screen_info,
 	 * as this could break UAPI. The best solution is to compute
-	 * bits_per_pixel here and ignore lfb_depth. In the loop below,
+	 * bits_per_pixel from the color bits, reserved bits and
+	 * reported lfb_depth, whichever is highest.  In the loop below,
 	 * ignore simplefb formats with alpha bits, as EFI and VESA
 	 * don't specify alpha channels.
 	 */
 					  si->green_size + si->green_pos,
 					  si->blue_size + si->blue_pos),
 				     si->rsvd_size + si->rsvd_pos);
+		bits_per_pixel = max_t(u32, bits_per_pixel, si->lfb_depth);
 	} else {
 		bits_per_pixel = si->lfb_depth;
 	}

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+11−1

 		adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
 			adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
 			(PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
+	/* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a
+	 * internal path natively support atomics, set have_atomics_support to true.
+	 */
+	else if ((adev->flags & AMD_IS_APU) &&
+		(adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0)))
+		adev->have_atomics_support = true;
 	else
 		adev->have_atomics_support =
 			!pci_enable_atomic_ops_to_root(adev->pdev,
 	dev_info(adev->dev, "recover vram bo from shadow start\n");
 	mutex_lock(&adev->shadow_list_lock);
 	list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
-		shadow = &vmbo->bo;
+		/* If vm is compute context or adev is APU, shadow will be NULL */
+		if (!vmbo->shadow)
+			continue;
+		shadow = vmbo->shadow;
 		/* No need to recover an evicted BO */
 		if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
 		    shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c+5−3

 		if (r)
 			return r;
-		r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
+		if (adev->gfx.cp_ecc_error_irq.funcs) {
-		if (r)
+			r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
-			goto late_fini;
+			if (r)
+				goto late_fini;
+		}
 	} else {
 		amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
 	}

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c+0−46

@@ -1315,13 +1315,6 @@ static int gfx_v11_0_sw_init(void *handle) · 1314 unmodified lines
1315	if (r)	1315	if (r)
1316	return r;	1316	return r;
1317		1317
1318	/* ECC error */
1319	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1320	GFX_11_0_0__SRCID__CP_ECC_ERROR,
1321	&adev->gfx.cp_ecc_error_irq);
1322	if (r)
1323	return r;
1324
1325	/* FED error */	1318	/* FED error */
1326	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,	1319	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1327	GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT,	1320	GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT,
@@ -4444,7 +4437,6 @@ static int gfx_v11_0_hw_fini(void *handle) · 3116 unmodified lines
4444	struct amdgpu_device adev = (struct amdgpu_device )handle;	4437	struct amdgpu_device adev = (struct amdgpu_device )handle;
4445	int r;	4438	int r;
4446		4439
4447	amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
4448	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);	4440	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4449	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);	4441	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4450		4442
@@ -5897,36 +5889,6 @@ static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev · 1446 unmodified lines
5897	}	5889	}
5898	}	5890	}
5899		5891
5900	#define CP_ME1_PIPE_INST_ADDR_INTERVAL 0x1
5901	#define SET_ECC_ME_PIPE_STATE(reg_addr, state) \
5902	do { \
5903	uint32_t tmp = RREG32_SOC15_IP(GC, reg_addr); \
5904	tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, state); \
5905	WREG32_SOC15_IP(GC, reg_addr, tmp); \
5906	} while (0)
5907
5908	static int gfx_v11_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
5909	struct amdgpu_irq_src *source,
5910	unsigned type,
5911	enum amdgpu_interrupt_state state)
5912	{
5913	uint32_t ecc_irq_state = 0;
5914	uint32_t pipe0_int_cntl_addr = 0;
5915	int i = 0;
5916
5917	ecc_irq_state = (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0;
5918
5919	pipe0_int_cntl_addr = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5920
5921	WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, ecc_irq_state);
5922
5923	for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++)
5924	SET_ECC_ME_PIPE_STATE(pipe0_int_cntl_addr + i * CP_ME1_PIPE_INST_ADDR_INTERVAL,
5925	ecc_irq_state);
5926
5927	return 0;
5928	}
5929
5930	static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,	5892	static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5931	struct amdgpu_irq_src *src,	5893	struct amdgpu_irq_src *src,
5932	unsigned type,	5894	unsigned type,
@@ -6341,11 +6303,6 @@ static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { · 408 unmodified lines
6341	.process = gfx_v11_0_priv_inst_irq,	6303	.process = gfx_v11_0_priv_inst_irq,
6342	};	6304	};
6343		6305
6344	static const struct amdgpu_irq_src_funcs gfx_v11_0_cp_ecc_error_irq_funcs = {
6345	.set = gfx_v11_0_set_cp_ecc_error_state,
6346	.process = amdgpu_gfx_cp_ecc_error_irq,
6347	};
6348
6349	static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = {	6306	static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = {
6350	.process = gfx_v11_0_rlc_gc_fed_irq,	6307	.process = gfx_v11_0_rlc_gc_fed_irq,
6351	};	6308	};
@@ -6361,9 +6318,6 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) · 9 unmodified lines
6361	adev->gfx.priv_inst_irq.num_types = 1;	6318	adev->gfx.priv_inst_irq.num_types = 1;
6362	adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;	6319	adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;
6363		6320
6364	adev->gfx.cp_ecc_error_irq.num_types = 1; /* CP ECC error */
6365	adev->gfx.cp_ecc_error_irq.funcs = &gfx_v11_0_cp_ecc_error_irq_funcs;
6366
6367	adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */	6321	adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */
6368	adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;	6322	adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;
6369		6323

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+2−1

@@ -3764,7 +3764,8 @@ static int gfx_v9_0_hw_fini(void *handle) · 3763 unmodified lines
3764	{	3764	{
3765	struct amdgpu_device adev = (struct amdgpu_device )handle;	3765	struct amdgpu_device adev = (struct amdgpu_device )handle;
3766		3766
3767	amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);	3767	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
		3768	amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
3768	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);	3769	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3769	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);	3770	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3770		3771

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c+1−0

@@ -54,6 +54,7 @@ static int jpeg_v3_0_early_init(void *handle) · 53 unmodified lines
54		54
55	switch (adev->ip_versions[UVD_HWIP][0]) {	55	switch (adev->ip_versions[UVD_HWIP][0]) {
56	case IP_VERSION(3, 1, 1):	56	case IP_VERSION(3, 1, 1):
		57	case IP_VERSION(3, 1, 2):
57	break;	58	break;
58	default:	59	default:
59	harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);	60	harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);

drivers/gpu/drm/amd/amdgpu/nv.c+16−6

 };
 /* Sienna Cichlid */
+static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = {
+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
+};
+static const struct amdgpu_video_codecs sc_video_codecs_encode = {
+	.codec_count = ARRAY_SIZE(sc_video_codecs_encode_array),
+	.codec_array = sc_video_codecs_encode_array,
+};
 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] =
 {
 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
 {
-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
 };
 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] =
 		} else {
 			if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
 				if (encode)
-					*codecs = &nv_video_codecs_encode;
+					*codecs = &sc_video_codecs_encode;
 				else
 					*codecs = &sc_video_codecs_decode_vcn1;
 			} else {
 				if (encode)
-					*codecs = &nv_video_codecs_encode;
+					*codecs = &sc_video_codecs_encode;
 				else
 					*codecs = &sc_video_codecs_decode_vcn0;
 			}
 	case IP_VERSION(3, 0, 16):
 	case IP_VERSION(3, 0, 2):
 		if (encode)
-			*codecs = &nv_video_codecs_encode;
+			*codecs = &sc_video_codecs_encode;
 		else
 			*codecs = &sc_video_codecs_decode_vcn0;
 		return 0;
 	case IP_VERSION(3, 1, 1):
 	case IP_VERSION(3, 1, 2):
 		if (encode)
-			*codecs = &nv_video_codecs_encode;
+			*codecs = &sc_video_codecs_encode;
 		else
 			*codecs = &yc_video_codecs_decode;
 		return 0;

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c+5−3

 		return 0;
 	}
-	for (i = 0; i < adev->sdma.num_instances; i++) {
+	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
-		amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
+		for (i = 0; i < adev->sdma.num_instances; i++) {
-			       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+			amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
+				       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+		}
 	}
 	sdma_v4_0_ctx_switch_enable(adev, false);

drivers/gpu/drm/amd/amdgpu/soc21.c+1−1

@@ -711,7 +711,7 @@ static int soc21_common_early_init(void *handle) · 710 unmodified lines
711	AMD_PG_SUPPORT_VCN_DPG \|	711	AMD_PG_SUPPORT_VCN_DPG \|
712	AMD_PG_SUPPORT_GFX_PG \|	712	AMD_PG_SUPPORT_GFX_PG \|
713	AMD_PG_SUPPORT_JPEG;	713	AMD_PG_SUPPORT_JPEG;
714	adev->external_rev_id = adev->rev_id + 0x1;	714	adev->external_rev_id = adev->rev_id + 0x80;
715	break;	715	break;
716		716
717	default:	717	default:

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c+65−0

@@ -423,3 +423,68 @@ void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool · 422 unmodified lines
423		423
424	PERF_TRACE();	424	PERF_TRACE();
425	}	425	}
		426	static void apply_symclk_on_tx_off_wa(struct dc_link *link)
		427	{
		428	/* There are use cases where SYMCLK is referenced by OTG. For instance
		429	* for TMDS signal, OTG relies SYMCLK even if TX video output is off.
		430	* However current link interface will power off PHY when disabling link
		431	* output. This will turn off SYMCLK generated by PHY. The workaround is
		432	* to identify such case where SYMCLK is still in use by OTG when we
		433	* power off PHY. When this is detected, we will temporarily power PHY
		434	* back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
		435	* program_pix_clk interface. When OTG is disabled, we will then power
		436	* off PHY by calling disable link output again.
		437	*
		438	* In future dcn generations, we plan to rework transmitter control
		439	* interface so that we could have an option to set SYMCLK ON TX OFF
		440	* state in one step without this workaround
		441	*/
		442
		443	struct dc *dc = link->ctx->dc;
		444	struct pipe_ctx *pipe_ctx = NULL;
		445	uint8_t i;
		446
		447	if (link->phy_state.symclk_ref_cnts.otg > 0) {
		448	for (i = 0; i < MAX_PIPES; i++) {
		449	pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
		450	if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {
		451	pipe_ctx->clock_source->funcs->program_pix_clk(
		452	pipe_ctx->clock_source,
		453	&pipe_ctx->stream_res.pix_clk_params,
		454	dc->link_srv->dp_get_encoding_format(
		455	&pipe_ctx->link_config.dp_link_settings),
		456	&pipe_ctx->pll_settings);
		457	link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
		458	break;
		459	}
		460	}
		461	}
		462	}
		463
		464	void dcn314_disable_link_output(struct dc_link *link,
		465	const struct link_resource *link_res,
		466	enum signal_type signal)
		467	{
		468	struct dc *dc = link->ctx->dc;
		469	const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
		470	struct dmcu *dmcu = dc->res_pool->dmcu;
		471
		472	if (signal == SIGNAL_TYPE_EDP &&
		473	link->dc->hwss.edp_backlight_control)
		474	link->dc->hwss.edp_backlight_control(link, false);
		475	else if (dmcu != NULL && dmcu->funcs->lock_phy)
		476	dmcu->funcs->lock_phy(dmcu);
		477
		478	link_hwss->disable_link_output(link, link_res, signal);
		479	link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
		480	/*
		481	* Add the logic to extract BOTH power up and power down sequences
		482	* from enable/disable link output and only call edp panel control
		483	* in enable_link_dp and disable_link_dp once.
		484	*/
		485	if (dmcu != NULL && dmcu->funcs->lock_phy)
		486	dmcu->funcs->unlock_phy(dmcu);
		487	dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
		488
		489	apply_symclk_on_tx_off_wa(link);
		490	}

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h+2−0

@@ -45,4 +45,6 @@ void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool · 44 unmodified lines
45		45
46	void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);	46	void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
47		47
		48	void dcn314_disable_link_output(struct dc_link link, const struct link_resource link_res, enum signal_type signal);
		49
48	#endif /* __DC_HWSS_DCN314_H__ */	50	#endif /* __DC_HWSS_DCN314_H__ */

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c+1−1

@@ -105,7 +105,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = { · 104 unmodified lines
105	.enable_lvds_link_output = dce110_enable_lvds_link_output,	105	.enable_lvds_link_output = dce110_enable_lvds_link_output,
106	.enable_tmds_link_output = dce110_enable_tmds_link_output,	106	.enable_tmds_link_output = dce110_enable_tmds_link_output,
107	.enable_dp_link_output = dce110_enable_dp_link_output,	107	.enable_dp_link_output = dce110_enable_dp_link_output,
108	.disable_link_output = dce110_disable_link_output,	108	.disable_link_output = dcn314_disable_link_output,
109	.z10_restore = dcn31_z10_restore,	109	.z10_restore = dcn31_z10_restore,
110	.z10_save_init = dcn31_z10_save_init,	110	.z10_save_init = dcn31_z10_save_init,
111	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,	111	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c+3−2

 					v->SwathHeightY[k],
 					v->SwathHeightC[k],
 					TWait,
-					v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ?
+					(v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ||
+						v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= MIN_DCFCLK_FREQ_MHZ) ?
 							mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
 					/* Output */
 					&v->DSTXAfterScaler[k],
 							v->swath_width_chroma_ub_this_state[k],
 							v->SwathHeightYThisState[k],
 							v->SwathHeightCThisState[k], v->TWait,
-							v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ ?
+							(v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= MIN_DCFCLK_FREQ_MHZ) ?
 									mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
 							/* Output */

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h+1−0

@@ -53,6 +53,7 @@ · 52 unmodified lines
53	#define BPP_BLENDED_PIPE 0xffffffff	53	#define BPP_BLENDED_PIPE 0xffffffff
54		54
55	#define MEM_STROBE_FREQ_MHZ 1600	55	#define MEM_STROBE_FREQ_MHZ 1600
		56	#define MIN_DCFCLK_FREQ_MHZ 200
56	#define MEM_STROBE_MAX_DELIVERY_TIME_US 60.0	57	#define MEM_STROBE_MAX_DELIVERY_TIME_US 60.0
57		58
58	struct display_mode_lib;	59	struct display_mode_lib;

drivers/gpu/drm/amd/pm/amdgpu_dpm.c+18−7

 #define amdgpu_dpm_enable_bapm(adev, e) \
 		((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
+#define amdgpu_dpm_is_legacy_dpm(adev) ((adev)->powerplay.pp_handle == (adev))
 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)
 {
 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev)
 {
-	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
+	if (is_support_sw_smu(adev)) {
-	struct smu_context *smu = adev->powerplay.pp_handle;
+		struct smu_context *smu = adev->powerplay.pp_handle;
-	if ((is_support_sw_smu(adev) && smu->od_enabled) ||
+		return (smu->od_enabled || smu->is_apu);
-	    (is_support_sw_smu(adev) && smu->is_apu) ||
+	} else {
-		(!is_support_sw_smu(adev) && hwmgr->od_enabled))
+		struct pp_hwmgr *hwmgr;
-		return true;
-	return false;
+		/*
+		 * dpm on some legacy asics don't carry od_enabled member
+		 * as its pp_handle is casted directly from adev.
+		 */
+		if (amdgpu_dpm_is_legacy_dpm(adev))
+			return false;
+		hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle;
+		return hwmgr->od_enabled;
+	}
 }
 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev,

drivers/gpu/drm/arm/hdlcd_drv.c+1−1

@@ -285,7 +285,7 @@ static int hdlcd_drm_bind(struct device *dev) · 284 unmodified lines
285	*/	285	*/
286	if (hdlcd_read(hdlcd, HDLCD_REG_COMMAND)) {	286	if (hdlcd_read(hdlcd, HDLCD_REG_COMMAND)) {
287	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);	287	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
288	drm_aperture_remove_framebuffers(false, &hdlcd_driver);	288	drm_aperture_remove_framebuffers(&hdlcd_driver);
289	}	289	}
290		290
291	drm_mode_config_reset(drm);	291	drm_mode_config_reset(drm);

drivers/gpu/drm/armada/Makefile+2−1

@@ -1,7 +1,8 @@
1	# SPDX-License-Identifier: GPL-2.0	1	# SPDX-License-Identifier: GPL-2.0
2	armada-y := armada_crtc.o armada_drv.o armada_fb.o armada_fbdev.o \	2	armada-y := armada_crtc.o armada_drv.o armada_fb.o \
3	armada_gem.o armada_overlay.o armada_plane.o armada_trace.o	3	armada_gem.o armada_overlay.o armada_plane.o armada_trace.o
4	armada-y += armada_510.o	4	armada-y += armada_510.o
5	armada-$(CONFIG_DEBUG_FS) += armada_debugfs.o	5	armada-$(CONFIG_DEBUG_FS) += armada_debugfs.o
		6	armada-$(CONFIG_DRM_FBDEV_EMULATION) += armada_fbdev.o
6		7
7	obj-$(CONFIG_DRM_ARMADA) := armada.o	8	obj-$(CONFIG_DRM_ARMADA) := armada.o

drivers/gpu/drm/armada/armada_drm.h+6−4

 struct armada_gem_object;
 struct clk;
 struct drm_display_mode;
-struct drm_fb_helper;
 static inline void
 armada_updatel(uint32_t val, uint32_t mask, void __iomem *ptr)
 struct armada_private {
 	struct drm_device	drm;
-	struct drm_fb_helper	*fbdev;
 	struct armada_crtc	*dcrtc[2];
 	struct drm_mm		linear; /* protected by linear_lock */
 	struct mutex		linear_lock;
 #define drm_to_armada_dev(dev) container_of(dev, struct armada_private, drm)
-int armada_fbdev_init(struct drm_device *);
+#if defined(CONFIG_DRM_FBDEV_EMULATION)
-void armada_fbdev_fini(struct drm_device *);
+void armada_fbdev_setup(struct drm_device *dev);
+#else
+static inline void armada_fbdev_setup(struct drm_device *dev)
+{ }
+#endif
 int armada_overlay_plane_create(struct drm_device *, unsigned long);

drivers/gpu/drm/armada/armada_drv.c+4−10

 #include <linux/clk.h>
 #include <linux/component.h>
 #include <linux/module.h>
+#include <linux/of.h>
 #include <linux/of_graph.h>
 #include <linux/platform_device.h>
 #include <drm/drm_managed.h>
 #include <drm/drm_prime.h>
 #include <drm/drm_probe_helper.h>
-#include <drm/drm_fb_helper.h>
 #include <drm/drm_of.h>
 #include <drm/drm_vblank.h>
 DEFINE_DRM_GEM_FOPS(armada_drm_fops);
 static const struct drm_driver armada_drm_driver = {
-	.lastclose		= drm_fb_helper_lastclose,
 	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
 	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
 	.gem_prime_import	= armada_gem_prime_import,
 static const struct drm_mode_config_funcs armada_drm_mode_config_funcs = {
 	.fb_create		= armada_fb_create,
-	.output_poll_changed	= drm_fb_helper_output_poll_changed,
 	.atomic_check		= drm_atomic_helper_check,
 	.atomic_commit		= drm_atomic_helper_commit,
 };
 	}
 	/* Remove early framebuffers */
-	ret = drm_aperture_remove_framebuffers(false, &armada_drm_driver);
+	ret = drm_aperture_remove_framebuffers(&armada_drm_driver);
 	if (ret) {
 		dev_err(dev, "[" DRM_NAME ":%s] can't kick out simple-fb: %d\n",
 			__func__, ret);
 	drm_mode_config_reset(&priv->drm);
-	ret = armada_fbdev_init(&priv->drm);
-	if (ret)
-		goto err_comp;
 	drm_kms_helper_poll_init(&priv->drm);
 	ret = drm_dev_register(&priv->drm, 0);
 	armada_drm_debugfs_init(priv->drm.primary);
 #endif
+	armada_fbdev_setup(&priv->drm);
 	return 0;
  err_poll:
 	drm_kms_helper_poll_fini(&priv->drm);
-	armada_fbdev_fini(&priv->drm);
  err_comp:
 	component_unbind_all(dev, &priv->drm);
  err_kms:
 	struct armada_private *priv = drm_to_armada_dev(drm);
 	drm_kms_helper_poll_fini(&priv->drm);
-	armada_fbdev_fini(&priv->drm);
 	drm_dev_unregister(&priv->drm);

drivers/gpu/drm/armada/armada_fb.c+0−1

@@ -4,7 +4,6 @@ · 3 unmodified lines
4	*/	4	*/
5		5
6	#include <drm/drm_modeset_helper.h>	6	#include <drm/drm_modeset_helper.h>
7	#include <drm/drm_fb_helper.h>
8	#include <drm/drm_fourcc.h>	7	#include <drm/drm_fourcc.h>
9	#include <drm/drm_gem_framebuffer_helper.h>	8	#include <drm/drm_gem_framebuffer_helper.h>
10		9

drivers/gpu/drm/armada/armada_fbdev.c+87−32

@@ -8,6 +8,8 @@ · 7 unmodified lines
8	#include <linux/kernel.h>	8	#include <linux/kernel.h>
9	#include <linux/module.h>	9	#include <linux/module.h>
10		10
		11	#include <drm/drm_crtc_helper.h>
		12	#include <drm/drm_drv.h>
11	#include <drm/drm_fb_helper.h>	13	#include <drm/drm_fb_helper.h>
12	#include <drm/drm_fourcc.h>	14	#include <drm/drm_fourcc.h>
13		15
@@ -16,6 +18,19 @@ · 2 unmodified lines
16	#include "armada_fb.h"	18	#include "armada_fb.h"
17	#include "armada_gem.h"	19	#include "armada_gem.h"
18		20
		21	static void armada_fbdev_fb_destroy(struct fb_info *info)
		22	{
		23	struct drm_fb_helper *fbh = info->par;
		24
		25	drm_fb_helper_fini(fbh);
		26
		27	fbh->fb->funcs->destroy(fbh->fb);
		28
		29	drm_client_release(&fbh->client);
		30	drm_fb_helper_unprepare(fbh);
		31	kfree(fbh);
		32	}
		33
19	static const struct fb_ops armada_fb_ops = {	34	static const struct fb_ops armada_fb_ops = {
20	.owner = THIS_MODULE,	35	.owner = THIS_MODULE,
21	DRM_FB_HELPER_DEFAULT_OPS,	36	DRM_FB_HELPER_DEFAULT_OPS,
@@ -24,6 +39,7 @@ static const struct fb_ops armada_fb_ops = { · 2 unmodified lines
24	.fb_fillrect = drm_fb_helper_cfb_fillrect,	39	.fb_fillrect = drm_fb_helper_cfb_fillrect,
25	.fb_copyarea = drm_fb_helper_cfb_copyarea,	40	.fb_copyarea = drm_fb_helper_cfb_copyarea,
26	.fb_imageblit = drm_fb_helper_cfb_imageblit,	41	.fb_imageblit = drm_fb_helper_cfb_imageblit,
		42	.fb_destroy = armada_fbdev_fb_destroy,
27	};	43	};
28		44
29	static int armada_fbdev_create(struct drm_fb_helper *fbh,	45	static int armada_fbdev_create(struct drm_fb_helper *fbh,
@@ -117,56 +133,95 @@ static const struct drm_fb_helper_funcs armada_fb_helper_funcs = { · 87 unmodified lines
117	.fb_probe = armada_fb_probe,	133	.fb_probe = armada_fb_probe,
118	};	134	};
119		135
120	int armada_fbdev_init(struct drm_device *dev)	136	/*
		137	* Fbdev client and struct drm_client_funcs
		138	*/
		139
		140	static void armada_fbdev_client_unregister(struct drm_client_dev *client)
121	{	141	{
122	struct armada_private *priv = drm_to_armada_dev(dev);	142	struct drm_fb_helper *fbh = drm_fb_helper_from_client(client);
123	struct drm_fb_helper *fbh;
124	int ret;
125		143
126	fbh = devm_kzalloc(dev->dev, sizeof(*fbh), GFP_KERNEL);	144	if (fbh->info) {
127	if (!fbh)	145	drm_fb_helper_unregister_info(fbh);
128	return -ENOMEM;	146	} else {
		147	drm_client_release(&fbh->client);
		148	drm_fb_helper_unprepare(fbh);
		149	kfree(fbh);
		150	}
		151	}
129		152
130	priv->fbdev = fbh;	153	static int armada_fbdev_client_restore(struct drm_client_dev *client)
		154	{
		155	drm_fb_helper_lastclose(client->dev);
131		156
132	drm_fb_helper_prepare(dev, fbh, 32, &armada_fb_helper_funcs);	157	return 0;
		158	}
		159
		160	static int armada_fbdev_client_hotplug(struct drm_client_dev *client)
		161	{
		162	struct drm_fb_helper *fbh = drm_fb_helper_from_client(client);
		163	struct drm_device *dev = client->dev;
		164	int ret;
		165
		166	if (dev->fb_helper)
		167	return drm_fb_helper_hotplug_event(dev->fb_helper);
133		168
134	ret = drm_fb_helper_init(dev, fbh);	169	ret = drm_fb_helper_init(dev, fbh);
135	if (ret) {	170	if (ret)
136	DRM_ERROR("failed to initialize drm fb helper\n");	171	goto err_drm_err;
137	goto err_fb_helper;	172
138	}	173	if (!drm_drv_uses_atomic_modeset(dev))
		174	drm_helper_disable_unused_functions(dev);
139		175
140	ret = drm_fb_helper_initial_config(fbh);	176	ret = drm_fb_helper_initial_config(fbh);
141	if (ret) {	177	if (ret)
142	DRM_ERROR("failed to set initial config\n");	178	goto err_drm_fb_helper_fini;
143	goto err_fb_setup;
144	}
145		179
146	return 0;	180	return 0;
147	err_fb_setup:	181
		182	err_drm_fb_helper_fini:
148	drm_fb_helper_fini(fbh);	183	drm_fb_helper_fini(fbh);
149	err_fb_helper:	184	err_drm_err:
150	drm_fb_helper_unprepare(fbh);	185	drm_err(dev, "armada: Failed to setup fbdev emulation (ret=%d)\n", ret);
151	priv->fbdev = NULL;
152	return ret;	186	return ret;
153	}	187	}
154		188
155	void armada_fbdev_fini(struct drm_device *dev)	189	static const struct drm_client_funcs armada_fbdev_client_funcs = {
		190	.owner = THIS_MODULE,
		191	.unregister = armada_fbdev_client_unregister,
		192	.restore = armada_fbdev_client_restore,
		193	.hotplug = armada_fbdev_client_hotplug,
		194	};
		195
		196	void armada_fbdev_setup(struct drm_device *dev)
156	{	197	{
157	struct armada_private *priv = drm_to_armada_dev(dev);	198	struct drm_fb_helper *fbh;
158	struct drm_fb_helper *fbh = priv->fbdev;	199	int ret;
159		200
160	if (fbh) {	201	drm_WARN(dev, !dev->registered, "Device has not been registered.\n");
161	drm_fb_helper_unregister_info(fbh);	202	drm_WARN(dev, dev->fb_helper, "fb_helper is already set!\n");
		203
		204	fbh = kzalloc(sizeof(*fbh), GFP_KERNEL);
		205	if (!fbh)
		206	return;
		207	drm_fb_helper_prepare(dev, fbh, 32, &armada_fb_helper_funcs);
162		208
163	drm_fb_helper_fini(fbh);	209	ret = drm_client_init(dev, &fbh->client, "fbdev", &armada_fbdev_client_funcs);
		210	if (ret) {
		211	drm_err(dev, "Failed to register client: %d\n", ret);
		212	goto err_drm_client_init;
		213	}
164		214
165	if (fbh->fb)	215	ret = armada_fbdev_client_hotplug(&fbh->client);
166	fbh->fb->funcs->destroy(fbh->fb);	216	if (ret)
		217	drm_dbg_kms(dev, "client hotplug ret=%d\n", ret);
167		218
168	drm_fb_helper_unprepare(fbh);	219	drm_client_register(&fbh->client);
169		220
170	priv->fbdev = NULL;	221	return;
171	}	222
		223	err_drm_client_init:
		224	drm_fb_helper_unprepare(fbh);
		225	kfree(fbh);
		226	return;
172	}	227	}

drivers/gpu/drm/ast/ast_main.c+5−4

 		return ERR_PTR(-EIO);
 	/*
-	 * If we don't have IO space at all, use MMIO now and
+	 * After AST2500, MMIO is enabled by default, and it should be adopted
-	 * assume the chip has MMIO enabled by default (rev 0x20
+	 * to be compatible with Arm.
-	 * and higher).
 	 */
-	if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) {
+	if (pdev->revision >= 0x40) {
+		ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
+	} else if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) {
 		drm_info(dev, "platform has no IO space, trying MMIO\n");
 		ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
 	}

drivers/gpu/drm/bridge/analogix/anx7625.c+88−41

@@ -17,7 +17,6 @@ · 16 unmodified lines
17	#include <linux/types.h>	17	#include <linux/types.h>
18	#include <linux/workqueue.h>	18	#include <linux/workqueue.h>
19		19
20	#include <linux/of_gpio.h>
21	#include <linux/of_graph.h>	20	#include <linux/of_graph.h>
22	#include <linux/of_platform.h>	21	#include <linux/of_platform.h>
23		22
@@ -1687,6 +1686,14 @@ static int anx7625_parse_dt(struct device *dev, · 1663 unmodified lines
1687	if (of_property_read_bool(np, "analogix,audio-enable"))	1686	if (of_property_read_bool(np, "analogix,audio-enable"))
1688	pdata->audio_en = 1;	1687	pdata->audio_en = 1;
1689		1688
		1689	return 0;
		1690	}
		1691
		1692	static int anx7625_parse_dt_panel(struct device *dev,
		1693	struct anx7625_platform_data *pdata)
		1694	{
		1695	struct device_node *np = dev->of_node;
		1696
1690	pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);	1697	pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
1691	if (IS_ERR(pdata->panel_bridge)) {	1698	if (IS_ERR(pdata->panel_bridge)) {
1692	if (PTR_ERR(pdata->panel_bridge) == -ENODEV) {	1699	if (PTR_ERR(pdata->panel_bridge) == -ENODEV) {
@@ -2032,7 +2039,7 @@ static int anx7625_register_audio(struct device dev, struct anx7625_data ctx) · 339 unmodified lines
2032	return 0;	2039	return 0;
2033	}	2040	}
2034		2041
2035	static int anx7625_attach_dsi(struct anx7625_data *ctx)	2042	static int anx7625_setup_dsi_device(struct anx7625_data *ctx)
2036	{	2043	{
2037	struct mipi_dsi_device *dsi;	2044	struct mipi_dsi_device *dsi;
2038	struct device *dev = &ctx->client->dev;	2045	struct device *dev = &ctx->client->dev;
@@ -2042,9 +2049,6 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx) · 3 unmodified lines
2042	.channel = 0,	2049	.channel = 0,
2043	.node = NULL,	2050	.node = NULL,
2044	};	2051	};
2045	int ret;
2046
2047	DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n");
2048		2052
2049	host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node);	2053	host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node);
2050	if (!host) {	2054	if (!host) {
@@ -2065,14 +2069,24 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx) · 14 unmodified lines
2065	MIPI_DSI_MODE_VIDEO_HSE \|	2069	MIPI_DSI_MODE_VIDEO_HSE \|
2066	MIPI_DSI_HS_PKT_END_ALIGNED;	2070	MIPI_DSI_HS_PKT_END_ALIGNED;
2067		2071
2068	ret = devm_mipi_dsi_attach(dev, dsi);	2072	ctx->dsi = dsi;
		2073
		2074	return 0;
		2075	}
		2076
		2077	static int anx7625_attach_dsi(struct anx7625_data *ctx)
		2078	{
		2079	struct device *dev = &ctx->client->dev;
		2080	int ret;
		2081
		2082	DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n");
		2083
		2084	ret = devm_mipi_dsi_attach(dev, ctx->dsi);
2069	if (ret) {	2085	if (ret) {
2070	DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");	2086	DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");
2071	return ret;	2087	return ret;
2072	}	2088	}
2073		2089
2074	ctx->dsi = dsi;
2075
2076	DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n");	2090	DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n");
2077		2091
2078	return 0;	2092	return 0;
@@ -2560,6 +2574,40 @@ static void anx7625_runtime_disable(void *data) · 481 unmodified lines
2560	pm_runtime_disable(data);	2574	pm_runtime_disable(data);
2561	}	2575	}
2562		2576
		2577	static int anx7625_link_bridge(struct drm_dp_aux *aux)
		2578	{
		2579	struct anx7625_data *platform = container_of(aux, struct anx7625_data, aux);
		2580	struct device *dev = aux->dev;
		2581	int ret;
		2582
		2583	ret = anx7625_parse_dt_panel(dev, &platform->pdata);
		2584	if (ret) {
		2585	DRM_DEV_ERROR(dev, "fail to parse DT for panel : %d\n", ret);
		2586	return ret;
		2587	}
		2588
		2589	platform->bridge.funcs = &anx7625_bridge_funcs;
		2590	platform->bridge.of_node = dev->of_node;
		2591	if (!anx7625_of_panel_on_aux_bus(dev))
		2592	platform->bridge.ops \|= DRM_BRIDGE_OP_EDID;
		2593	if (!platform->pdata.panel_bridge)
		2594	platform->bridge.ops \|= DRM_BRIDGE_OP_HPD \|
		2595	DRM_BRIDGE_OP_DETECT;
		2596	platform->bridge.type = platform->pdata.panel_bridge ?
		2597	DRM_MODE_CONNECTOR_eDP :
		2598	DRM_MODE_CONNECTOR_DisplayPort;
		2599
		2600	drm_bridge_add(&platform->bridge);
		2601
		2602	if (!platform->pdata.is_dpi) {
		2603	ret = anx7625_attach_dsi(platform);
		2604	if (ret)
		2605	drm_bridge_remove(&platform->bridge);
		2606	}
		2607
		2608	return ret;
		2609	}
		2610
2563	static int anx7625_i2c_probe(struct i2c_client *client)	2611	static int anx7625_i2c_probe(struct i2c_client *client)
2564	{	2612	{
2565	struct anx7625_data *platform;	2613	struct anx7625_data *platform;
@@ -2634,6 +2682,24 @@ static int anx7625_i2c_probe(struct i2c_client *client) · 68 unmodified lines
2634	platform->aux.wait_hpd_asserted = anx7625_wait_hpd_asserted;	2682	platform->aux.wait_hpd_asserted = anx7625_wait_hpd_asserted;
2635	drm_dp_aux_init(&platform->aux);	2683	drm_dp_aux_init(&platform->aux);
2636		2684
		2685	ret = anx7625_parse_dt(dev, pdata);
		2686	if (ret) {
		2687	if (ret != -EPROBE_DEFER)
		2688	DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret);
		2689	goto free_wq;
		2690	}
		2691
		2692	if (!platform->pdata.is_dpi) {
		2693	ret = anx7625_setup_dsi_device(platform);
		2694	if (ret < 0)
		2695	goto free_wq;
		2696	}
		2697
		2698	/*
		2699	* Registering the i2c devices will retrigger deferred probe, so it
		2700	* needs to be done after calls that might return EPROBE_DEFER,
		2701	* otherwise we can get an infinite loop.
		2702	*/
2637	if (anx7625_register_i2c_dummy_clients(platform, client) != 0) {	2703	if (anx7625_register_i2c_dummy_clients(platform, client) != 0) {
2638	ret = -ENOMEM;	2704	ret = -ENOMEM;
2639	DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n");	2705	DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n");
@@ -2648,13 +2714,21 @@ static int anx7625_i2c_probe(struct i2c_client *client) · 8 unmodified lines
2648	if (ret)	2714	if (ret)
2649	goto free_wq;	2715	goto free_wq;
2650		2716
2651	devm_of_dp_aux_populate_ep_devices(&platform->aux);	2717	/*
2652		2718	* Populating the aux bus will retrigger deferred probe, so it needs to
2653	ret = anx7625_parse_dt(dev, pdata);	2719	* be done after calls that might return EPROBE_DEFER, otherwise we can
		2720	* get an infinite loop.
		2721	*/
		2722	ret = devm_of_dp_aux_populate_bus(&platform->aux, anx7625_link_bridge);
2654	if (ret) {	2723	if (ret) {
2655	if (ret != -EPROBE_DEFER)	2724	if (ret != -ENODEV) {
2656	DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret);	2725	DRM_DEV_ERROR(dev, "failed to populate aux bus : %d\n", ret);
2657	goto free_wq;	2726	goto free_wq;
		2727	}
		2728
		2729	ret = anx7625_link_bridge(&platform->aux);
		2730	if (ret)
		2731	goto free_wq;
2658	}	2732	}
2659		2733
2660	if (!platform->pdata.low_power_mode) {	2734	if (!platform->pdata.low_power_mode) {
@@ -2667,27 +2741,6 @@ static int anx7625_i2c_probe(struct i2c_client *client) · 6 unmodified lines
2667	if (platform->pdata.intp_irq)	2741	if (platform->pdata.intp_irq)
2668	queue_work(platform->workqueue, &platform->work);	2742	queue_work(platform->workqueue, &platform->work);
2669		2743
2670	platform->bridge.funcs = &anx7625_bridge_funcs;
2671	platform->bridge.of_node = client->dev.of_node;
2672	if (!anx7625_of_panel_on_aux_bus(&client->dev))
2673	platform->bridge.ops \|= DRM_BRIDGE_OP_EDID;
2674	if (!platform->pdata.panel_bridge)
2675	platform->bridge.ops \|= DRM_BRIDGE_OP_HPD \|
2676	DRM_BRIDGE_OP_DETECT;
2677	platform->bridge.type = platform->pdata.panel_bridge ?
2678	DRM_MODE_CONNECTOR_eDP :
2679	DRM_MODE_CONNECTOR_DisplayPort;
2680
2681	drm_bridge_add(&platform->bridge);
2682
2683	if (!platform->pdata.is_dpi) {
2684	ret = anx7625_attach_dsi(platform);
2685	if (ret) {
2686	DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret);
2687	goto unregister_bridge;
2688	}
2689	}
2690
2691	if (platform->pdata.audio_en)	2744	if (platform->pdata.audio_en)
2692	anx7625_register_audio(dev, platform);	2745	anx7625_register_audio(dev, platform);
2693		2746
@@ -2695,12 +2748,6 @@ static int anx7625_i2c_probe(struct i2c_client *client) · 1 unmodified line
2695		2748
2696	return 0;	2749	return 0;
2697		2750
2698	unregister_bridge:
2699	drm_bridge_remove(&platform->bridge);
2700
2701	if (!platform->pdata.low_power_mode)
2702	pm_runtime_put_sync_suspend(&client->dev);
2703
2704	free_wq:	2751	free_wq:
2705	if (platform->workqueue)	2752	if (platform->workqueue)
2706	destroy_workqueue(platform->workqueue);	2753	destroy_workqueue(platform->workqueue);

drivers/gpu/drm/bridge/fsl-ldb.c+13−1

 #define LVDS_CTRL_VBG_ADJ_MASK			GENMASK(19, 17)
 enum fsl_ldb_devtype {
+	IMX6SX_LDB,
 	IMX8MP_LDB,
 	IMX93_LDB,
 };
 	u32 ldb_ctrl;
 	u32 lvds_ctrl;
 	bool lvds_en_bit;
+	bool single_ctrl_reg;
 };
 static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
+	[IMX6SX_LDB] = {
+		.ldb_ctrl = 0x18,
+		.single_ctrl_reg = true,
+	},
 	[IMX8MP_LDB] = {
 		.ldb_ctrl = 0x5c,
 		.lvds_ctrl = 0x128,
 	regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg);
+	if (fsl_ldb->devdata->single_ctrl_reg)
+		return;
 	/* Program LVDS_CTRL */
 	reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
 	      LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
 		regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl,
 			     LVDS_CTRL_LVDS_EN);
 	else
-		regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0);
+		if (!fsl_ldb->devdata->single_ctrl_reg)
+			regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0);
 	regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0);
 	clk_disable_unprepare(fsl_ldb->clk);
 }
 static const struct of_device_id fsl_ldb_match[] = {
+	{ .compatible = "fsl,imx6sx-ldb",
+	  .data = &fsl_ldb_devdata[IMX6SX_LDB], },
 	{ .compatible = "fsl,imx8mp-ldb",
 	  .data = &fsl_ldb_devdata[IMX8MP_LDB], },
 	{ .compatible = "fsl,imx93-ldb",

drivers/gpu/drm/bridge/ite-it6505.c+2−1

 					   size_t len, loff_t *ppos)
 {
 	struct it6505 *it6505 = file->private_data;
-	struct drm_display_mode *vid = &it6505->video_info;
+	struct drm_display_mode *vid;
 	u8 read_buf[READ_BUFFER_SIZE];
 	u8 *str = read_buf, *end = read_buf + READ_BUFFER_SIZE;
 	ssize_t ret, count;
 		return -ENODEV;
 	it6505_calc_video_info(it6505);
+	vid = &it6505->video_info;
 	str += scnprintf(str, end - str, "---video timing---\n");
 	str += scnprintf(str, end - str, "PCLK:%d.%03dMHz\n",
 			 vid->clock / 1000, vid->clock % 1000);

drivers/gpu/drm/bridge/lontium-lt9211.c+3−1

 	dsi->lanes = dsi_lanes;
 	dsi->format = MIPI_DSI_FMT_RGB888;
 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
-			  MIPI_DSI_MODE_VIDEO_HSE;
+			  MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO_NO_HSA |
+			  MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP |
+			  MIPI_DSI_MODE_NO_EOT_PACKET;
 	ret = devm_mipi_dsi_attach(dev, dsi);
 	if (ret < 0) {

drivers/gpu/drm/bridge/lontium-lt9611.c+3−1

 	dsi->lanes = 4;
 	dsi->format = MIPI_DSI_FMT_RGB888;
 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
-			  MIPI_DSI_MODE_VIDEO_HSE;
+			  MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO_NO_HSA |
+			  MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP |
+			  MIPI_DSI_MODE_NO_EOT_PACKET;
 	ret = devm_mipi_dsi_attach(dev, dsi);
 	if (ret < 0) {

drivers/gpu/drm/bridge/samsung-dsim.c+26−2

 #define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
 /* DSIM_PLLCTRL */
+#define DSIM_PLL_DPDNSWAP_CLK		(1 << 25)
+#define DSIM_PLL_DPDNSWAP_DAT		(1 << 24)
 #define DSIM_FREQ_BAND(x)		((x) << 24)
 #define DSIM_PLL_EN			BIT(23)
 #define DSIM_PLL_P(x, offset)		((x) << (offset))
 		reg |= DSIM_FREQ_BAND(band);
 	}
+	if (dsi->swap_dn_dp_clk)
+		reg |= DSIM_PLL_DPDNSWAP_CLK;
+	if (dsi->swap_dn_dp_data)
+		reg |= DSIM_PLL_DPDNSWAP_DAT;
 	samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
 	timeout = 1000;
 {
 	struct device *dev = dsi->dev;
 	struct device_node *node = dev->of_node;
-	int ret;
+	u32 lane_polarities[5] = { 0 };
+	struct device_node *endpoint;
+	int i, nr_lanes, ret;
 	ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
 				       &dsi->pll_clk_rate);
 	if (ret < 0)
 		return ret;
+	endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
+	nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
+	if (nr_lanes > 0 && nr_lanes <= 4) {
+		/* Polarity 0 is clock lane, 1..4 are data lanes. */
+		of_property_read_u32_array(endpoint, "lane-polarities",
+					   lane_polarities, nr_lanes + 1);
+		for (i = 1; i <= nr_lanes; i++) {
+			if (lane_polarities[1] != lane_polarities[i])
+				DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
+		}
+		if (lane_polarities[0])
+			dsi->swap_dn_dp_clk = true;
+		if (lane_polarities[1])
+			dsi->swap_dn_dp_data = true;
+	}
 	return 0;
 }
 	.remove = samsung_dsim_remove,
 	.driver = {
 		   .name = "samsung-dsim",
-		   .owner = THIS_MODULE,
 		   .pm = &samsung_dsim_pm_ops,
 		   .of_match_table = samsung_dsim_of_match,
 	},

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c+1−1

@@ -533,7 +533,7 @@ static struct i2c_adapter dw_hdmi_i2c_adapter(struct dw_hdmi hdmi) · 532 unmodified lines
533	adap->owner = THIS_MODULE;	533	adap->owner = THIS_MODULE;
534	adap->dev.parent = hdmi->dev;	534	adap->dev.parent = hdmi->dev;
535	adap->algo = &dw_hdmi_algorithm;	535	adap->algo = &dw_hdmi_algorithm;
536	strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));	536	strscpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
537	i2c_set_adapdata(adap, hdmi);	537	i2c_set_adapdata(adap, hdmi);
538		538
539	ret = i2c_add_adapter(adap);	539	ret = i2c_add_adapter(adap);

drivers/gpu/drm/bridge/tc358767.c+2−2

@@ -1890,7 +1890,7 @@ static int tc_mipi_dsi_host_attach(struct tc_data *tc) · 1889 unmodified lines
1890	if (dsi_lanes < 0)	1890	if (dsi_lanes < 0)
1891	return dsi_lanes;	1891	return dsi_lanes;
1892		1892
1893	dsi = mipi_dsi_device_register_full(host, &info);	1893	dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
1894	if (IS_ERR(dsi))	1894	if (IS_ERR(dsi))
1895	return dev_err_probe(dev, PTR_ERR(dsi),	1895	return dev_err_probe(dev, PTR_ERR(dsi),
1896	"failed to create dsi device\n");	1896	"failed to create dsi device\n");
@@ -1901,7 +1901,7 @@ static int tc_mipi_dsi_host_attach(struct tc_data *tc) · 4 unmodified lines
1901	dsi->mode_flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_MODE_VIDEO_BURST \|	1901	dsi->mode_flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_MODE_VIDEO_BURST \|
1902	MIPI_DSI_MODE_LPM \| MIPI_DSI_CLOCK_NON_CONTINUOUS;	1902	MIPI_DSI_MODE_LPM \| MIPI_DSI_CLOCK_NON_CONTINUOUS;
1903		1903
1904	ret = mipi_dsi_attach(dsi);	1904	ret = devm_mipi_dsi_attach(dev, dsi);
1905	if (ret < 0) {	1905	if (ret < 0) {
1906	dev_err(dev, "failed to attach dsi to host: %d\n", ret);	1906	dev_err(dev, "failed to attach dsi to host: %d\n", ret);
1907	return ret;	1907	return ret;

drivers/gpu/drm/bridge/tc358768.c+74−23

 #include <linux/gpio/consumer.h>
 #include <linux/i2c.h>
 #include <linux/kernel.h>
+#include <linux/media-bus-format.h>
+#include <linux/minmax.h>
 #include <linux/module.h>
 #include <linux/regmap.h>
 #include <linux/regulator/consumer.h>
 	u32 pd_lines; /* number of Parallel Port Input Data Lines */
 	u32 dsi_lanes; /* number of DSI Lanes */
+	u32 dsi_bpp; /* number of Bits Per Pixel over DSI */
 	/* Parameters for PLL programming */
 	u32 fbd;	/* PLL feedback divider */
 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
 {
-	return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->pd_lines);
+	return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp);
 }
 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
 {
-	return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes);
+	return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes);
 }
 static int tc358768_calc_pll(struct tc358768_priv *priv,
 		u32 fbd;
 		for (fbd = 0; fbd < 512; ++fbd) {
-			u32 pll, diff;
+			u32 pll, diff, pll_in;
 			pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
 			if (pll >= max_pll || pll < min_pll)
 				continue;
+			pll_in = (u32)div_u64((u64)refclk, prd + 1);
+			if (pll_in < 4000000)
+				continue;
 			diff = max(pll, target_pll) - min(pll, target_pll);
 			if (diff < best_diff) {
 	priv->output.panel = panel;
 	priv->dsi_lanes = dev->lanes;
+	priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format);
 	/* get input ep (port0/endpoint0) */
 	ret = -EINVAL;
 	}
 	if (ret)
-		priv->pd_lines = mipi_dsi_pixel_format_to_bpp(dev->format);
+		priv->pd_lines = priv->dsi_bpp;
 	drm_bridge_add(&priv->bridge);
 	struct mipi_dsi_device *dsi_dev = priv->output.dev;
 	unsigned long mode_flags = dsi_dev->mode_flags;
 	u32 val, val2, lptxcnt, hact, data_type;
+	s32 raw_val;
 	const struct drm_display_mode *mode;
-	u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk;
+	u32 dsibclk_nsk, dsiclk_nsk, ui_nsk;
 	u32 dsiclk, dsibclk, video_start;
 	const u32 internal_delay = 40;
 	int ret, i;
 				  dsibclk);
 	dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk);
 	ui_nsk = dsiclk_nsk / 2;
-	phy_delay_nsk = dsibclk_nsk + 2 * dsiclk_nsk;
 	dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk);
 	dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk);
 	dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk);
-	dev_dbg(priv->dev, "phy_delay_nsk: %u\n", phy_delay_nsk);
 	/* LP11 > 100us for D-PHY Rx Init */
 	val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1;
 	/* 38ns < TCLK_PREPARE < 95ns */
 	val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1;
-	/* TCLK_PREPARE > 300ns */
+	/* TCLK_PREPARE + TCLK_ZERO > 300ns */
-	val2 = tc358768_ns_to_cnt(300 + tc358768_to_ns(3 * ui_nsk),
+	val2 = tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk),
-				  dsibclk_nsk);
+				  dsibclk_nsk) - 2;
-	val |= (val2 - tc358768_to_ns(phy_delay_nsk - dsibclk_nsk)) << 8;
+	val |= val2 << 8;
 	dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val);
 	tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
-	/* TCLK_TRAIL > 60ns + 3*UI */
+	/* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */
-	val = 60 + tc358768_to_ns(3 * ui_nsk);
+	raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_nsk) - 5;
-	val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 5;
+	val = clamp(raw_val, 0, 127);
 	dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val);
 	tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
 	/* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
 	val = 50 + tc358768_to_ns(4 * ui_nsk);
 	val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
-	/* THS_ZERO > 145ns + 10*UI */
+	/* THS_PREPARE + THS_ZERO > 145ns + 10*UI */
-	val2 = tc358768_ns_to_cnt(145 - tc358768_to_ns(ui_nsk), dsibclk_nsk);
+	raw_val = tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_nsk) - 10;
-	val |= (val2 - tc358768_to_ns(phy_delay_nsk)) << 8;
+	val2 = clamp(raw_val, 0, 127);
+	val |= val2 << 8;
 	dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val);
 	tc358768_write(priv, TC358768_THS_HEADERCNT, val);
 	dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val);
 	tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
-	/* 60ns + 4*UI < THS_PREPARE < 105ns + 12*UI */
+	/* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */
-	val = tc358768_ns_to_cnt(60 + tc358768_to_ns(15 * ui_nsk),
+	raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk),
-				 dsibclk_nsk) - 5;
+				     dsibclk_nsk) - 4;
+	val = clamp(raw_val, 0, 15);
 	dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val);
 	tc358768_write(priv, TC358768_THS_TRAILCNT, val);
 	/* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
 	val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4);
-	val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
+	val = tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1;
 	val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk),
 				  dsibclk_nsk) - 2;
 	val = val << 16 | val2;
 	val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
 	val |= (dsi_dev->lanes - 1) << 1;
-	if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM))
+	val |= TC358768_DSI_CONTROL_TXMD;
-		val |= TC358768_DSI_CONTROL_TXMD;
 	if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
 		val |= TC358768_DSI_CONTROL_HSCKMD;
 	}
 }
+#define MAX_INPUT_SEL_FORMATS	1
+static u32 *
+tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+				   struct drm_bridge_state *bridge_state,
+				   struct drm_crtc_state *crtc_state,
+				   struct drm_connector_state *conn_state,
+				   u32 output_fmt,
+				   unsigned int *num_input_fmts)
+{
+	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
+	u32 *input_fmts;
+	*num_input_fmts = 0;
+	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
+			     GFP_KERNEL);
+	if (!input_fmts)
+		return NULL;
+	switch (priv->pd_lines) {
+	case 16:
+		input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16;
+		break;
+	case 18:
+		input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18;
+		break;
+	default:
+	case 24:
+		input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
+		break;
+	}
+	*num_input_fmts = MAX_INPUT_SEL_FORMATS;
+	return input_fmts;
+}
 static const struct drm_bridge_funcs tc358768_bridge_funcs = {
 	.attach = tc358768_bridge_attach,
 	.mode_valid = tc358768_bridge_mode_valid,
 	.enable = tc358768_bridge_enable,
 	.disable = tc358768_bridge_disable,
 	.post_disable = tc358768_bridge_post_disable,
+	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+	.atomic_reset = drm_atomic_helper_bridge_reset,
+	.atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts,
 };
 static const struct drm_bridge_timings default_tc358768_timings = {

drivers/gpu/drm/bridge/ti-sn65dsi83.c+1−0

@@ -478,6 +478,7 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, · 477 unmodified lines
478	dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret);	478	dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret);
479	/* On failure, disable PLL again and exit. */	479	/* On failure, disable PLL again and exit. */
480	regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);	480	regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
		481	regulator_disable(ctx->vcc);
481	return;	482	return;
482	}	483	}
483		484

drivers/gpu/drm/bridge/ti-sn65dsi86.c+19−0

@@ -618,6 +618,24 @@ exit: · 617 unmodified lines
618	return len;	618	return len;
619	}	619	}
620		620
		621	static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
		622	{
		623	/*
		624	* The HPD in this chip is a bit useless (See comment in
		625	* ti_sn65dsi86_enable_comms) so if our driver is expected to wait
		626	* for HPD, we just assume it's asserted after the wait_us delay.
		627	*
		628	* In case we are asked to wait forever (wait_us=0) take conservative
		629	* 500ms delay.
		630	*/
		631	if (wait_us == 0)
		632	wait_us = 500000;
		633
		634	usleep_range(wait_us, wait_us + 1000);
		635
		636	return 0;
		637	}
		638
621	static int ti_sn_aux_probe(struct auxiliary_device *adev,	639	static int ti_sn_aux_probe(struct auxiliary_device *adev,
622	const struct auxiliary_device_id *id)	640	const struct auxiliary_device_id *id)
623	{	641	{
@@ -627,6 +645,7 @@ static int ti_sn_aux_probe(struct auxiliary_device *adev, · 3 unmodified lines
627	pdata->aux.name = "ti-sn65dsi86-aux";	645	pdata->aux.name = "ti-sn65dsi86-aux";
628	pdata->aux.dev = &adev->dev;	646	pdata->aux.dev = &adev->dev;
629	pdata->aux.transfer = ti_sn_aux_transfer;	647	pdata->aux.transfer = ti_sn_aux_transfer;
		648	pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted;
630	drm_dp_aux_init(&pdata->aux);	649	drm_dp_aux_init(&pdata->aux);
631		650
632	ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);	651	ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);

drivers/gpu/drm/drm_aperture.c+3−8

  *
  *	static int remove_conflicting_framebuffers(struct pci_dev *pdev)
  *	{
- *		bool primary = false;
  *		resource_size_t base, size;
  *		int ret;
  *
  *		base = pci_resource_start(pdev, 0);
  *		size = pci_resource_len(pdev, 0);
- *	#ifdef CONFIG_X86
- *		primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
- *	#endif
  *
- *		return drm_aperture_remove_conflicting_framebuffers(base, size, primary,
+ *		return drm_aperture_remove_conflicting_framebuffers(base, size,
  *		                                                    &example_driver);
  *	}
  *
  * drm_aperture_remove_conflicting_framebuffers - remove existing framebuffers in the given range
  * @base: the aperture's base address in physical memory
  * @size: aperture size in bytes
- * @primary: also kick vga16fb if present
  * @req_driver: requesting DRM driver
  *
  * This function removes graphics device drivers which use the memory range described by
  * 0 on success, or a negative errno code otherwise
  */
 int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size,
-						 bool primary, const struct drm_driver *req_driver)
+						 const struct drm_driver *req_driver)
 {
-	return aperture_remove_conflicting_devices(base, size, primary, req_driver->name);
+	return aperture_remove_conflicting_devices(base, size, req_driver->name);
 }
 EXPORT_SYMBOL(drm_aperture_remove_conflicting_framebuffers);

drivers/gpu/drm/drm_atomic_helper.c+11−2

 			continue;
 		ret = drm_crtc_vblank_get(crtc);
-		WARN_ONCE(ret != -EINVAL, "driver forgot to call drm_crtc_vblank_off()\n");
+		/*
+		 * Self-refresh is not a true "disable"; ensure vblank remains
+		 * enabled.
+		 */
+		if (new_crtc_state->self_refresh_active)
+			WARN_ONCE(ret != 0,
+				  "driver disabled vblank in self-refresh\n");
+		else
+			WARN_ONCE(ret != -EINVAL,
+				  "driver forgot to call drm_crtc_vblank_off()\n");
 		if (ret == 0)
 			drm_crtc_vblank_put(crtc);
 	}
 EXPORT_SYMBOL(drm_atomic_helper_update_plane);
 /**
- * drm_atomic_helper_disable_plane - Helper for primary plane disable using * atomic
+ * drm_atomic_helper_disable_plane - Helper for primary plane disable using atomic
  * @plane: plane to disable
  * @ctx: lock acquire context
  *

drivers/gpu/drm/drm_drv.c+3−1

  *
  * Unregister the DRM device from the system. This does the reverse of
  * drm_dev_register() but does not deallocate the device. The caller must call
- * drm_dev_put() to drop their final reference.
+ * drm_dev_put() to drop their final reference, unless it is managed with devres
+ * (as devices allocated with devm_drm_dev_alloc() are), in which case there is
+ * already an unwind action registered.
  *
  * A special form of unregistering for hotpluggable devices is drm_dev_unplug(),
  * which can be called while there are still open users of @dev.

drivers/gpu/drm/drm_fb_helper.c+16−174

@@ -641,19 +641,27 @@ static void drm_fb_helper_damage(struct drm_fb_helper *helper, u32 x, u32 y, · 640 unmodified lines
641	static void drm_fb_helper_memory_range_to_clip(struct fb_info *info, off_t off, size_t len,	641	static void drm_fb_helper_memory_range_to_clip(struct fb_info *info, off_t off, size_t len,
642	struct drm_rect *clip)	642	struct drm_rect *clip)
643	{	643	{
		644	u32 line_length = info->fix.line_length;
		645	u32 fb_height = info->var.yres;
644	off_t end = off + len;	646	off_t end = off + len;
645	u32 x1 = 0;	647	u32 x1 = 0;
646	u32 y1 = off / info->fix.line_length;	648	u32 y1 = off / line_length;
647	u32 x2 = info->var.xres;	649	u32 x2 = info->var.xres;
648	u32 y2 = DIV_ROUND_UP(end, info->fix.line_length);	650	u32 y2 = DIV_ROUND_UP(end, line_length);
		651
		652	/* Don't allow any of them beyond the bottom bound of display area */
		653	if (y1 > fb_height)
		654	y1 = fb_height;
		655	if (y2 > fb_height)
		656	y2 = fb_height;
649		657
650	if ((y2 - y1) == 1) {	658	if ((y2 - y1) == 1) {
651	/*	659	/*
652	* We've only written to a single scanline. Try to reduce	660	* We've only written to a single scanline. Try to reduce
653	* the number of horizontal pixels that need an update.	661	* the number of horizontal pixels that need an update.
654	*/	662	*/
655	off_t bit_off = (off % info->fix.line_length) * 8;	663	off_t bit_off = (off % line_length) * 8;
656	off_t bit_end = (end % info->fix.line_length) * 8;	664	off_t bit_end = (end % line_length) * 8;
657		665
658	x1 = bit_off / info->var.bits_per_pixel;	666	x1 = bit_off / info->var.bits_per_pixel;
659	x2 = DIV_ROUND_UP(bit_end, info->var.bits_per_pixel);	667	x2 = DIV_ROUND_UP(bit_end, info->var.bits_per_pixel);
@@ -706,95 +714,6 @@ void drm_fb_helper_deferred_io(struct fb_info info, struct list_head pagerefli · 46 unmodified lines
706	}	714	}
707	EXPORT_SYMBOL(drm_fb_helper_deferred_io);	715	EXPORT_SYMBOL(drm_fb_helper_deferred_io);
708		716
709	typedef ssize_t (drm_fb_helper_read_screen)(struct fb_info info, char __user *buf,
710	size_t count, loff_t pos);
711
712	static ssize_t __drm_fb_helper_read(struct fb_info info, char __user buf, size_t count,
713	loff_t *ppos, drm_fb_helper_read_screen read_screen)
714	{
715	loff_t pos = *ppos;
716	size_t total_size;
717	ssize_t ret;
718
719	if (info->screen_size)
720	total_size = info->screen_size;
721	else
722	total_size = info->fix.smem_len;
723
724	if (pos >= total_size)
725	return 0;
726	if (count >= total_size)
727	count = total_size;
728	if (total_size - count < pos)
729	count = total_size - pos;
730
731	if (info->fbops->fb_sync)
732	info->fbops->fb_sync(info);
733
734	ret = read_screen(info, buf, count, pos);
735	if (ret > 0)
736	*ppos += ret;
737
738	return ret;
739	}
740
741	typedef ssize_t (drm_fb_helper_write_screen)(struct fb_info info, const char __user *buf,
742	size_t count, loff_t pos);
743
744	static ssize_t __drm_fb_helper_write(struct fb_info info, const char __user buf, size_t count,
745	loff_t *ppos, drm_fb_helper_write_screen write_screen)
746	{
747	loff_t pos = *ppos;
748	size_t total_size;
749	ssize_t ret;
750	int err = 0;
751
752	if (info->screen_size)
753	total_size = info->screen_size;
754	else
755	total_size = info->fix.smem_len;
756
757	if (pos > total_size)
758	return -EFBIG;
759	if (count > total_size) {
760	err = -EFBIG;
761	count = total_size;
762	}
763	if (total_size - count < pos) {
764	if (!err)
765	err = -ENOSPC;
766	count = total_size - pos;
767	}
768
769	if (info->fbops->fb_sync)
770	info->fbops->fb_sync(info);
771
772	/*
773	* Copy to framebuffer even if we already logged an error. Emulates
774	* the behavior of the original fbdev implementation.
775	*/
776	ret = write_screen(info, buf, count, pos);
777	if (ret < 0)
778	return ret; /* return last error, if any */
779	else if (!ret)
780	return err; /* return previous error, if any */
781
782	*ppos += ret;
783
784	return ret;
785	}
786
787	static ssize_t drm_fb_helper_read_screen_buffer(struct fb_info info, char __user buf,
788	size_t count, loff_t pos)
789	{
790	const char *src = info->screen_buffer + pos;
791
792	if (copy_to_user(buf, src, count))
793	return -EFAULT;
794
795	return count;
796	}
797
798	/**	717	/**
799	* drm_fb_helper_sys_read - Implements struct &fb_ops.fb_read for system memory	718	* drm_fb_helper_sys_read - Implements struct &fb_ops.fb_read for system memory
800	* @info: fb_info struct pointer	719	* @info: fb_info struct pointer
@@ -808,21 +727,10 @@ static ssize_t drm_fb_helper_read_screen_buffer(struct fb_info *info, char __use · 7 unmodified lines
808	ssize_t drm_fb_helper_sys_read(struct fb_info info, char __user buf,	727	ssize_t drm_fb_helper_sys_read(struct fb_info info, char __user buf,
809	size_t count, loff_t *ppos)	728	size_t count, loff_t *ppos)
810	{	729	{
811	return __drm_fb_helper_read(info, buf, count, ppos, drm_fb_helper_read_screen_buffer);	730	return fb_sys_read(info, buf, count, ppos);
812	}	731	}
813	EXPORT_SYMBOL(drm_fb_helper_sys_read);	732	EXPORT_SYMBOL(drm_fb_helper_sys_read);
814		733
815	static ssize_t drm_fb_helper_write_screen_buffer(struct fb_info info, const char __user buf,
816	size_t count, loff_t pos)
817	{
818	char *dst = info->screen_buffer + pos;
819
820	if (copy_from_user(dst, buf, count))
821	return -EFAULT;
822
823	return count;
824	}
825
826	/**	734	/**
827	* drm_fb_helper_sys_write - Implements struct &fb_ops.fb_write for system memory	735	* drm_fb_helper_sys_write - Implements struct &fb_ops.fb_write for system memory
828	* @info: fb_info struct pointer	736	* @info: fb_info struct pointer
@@ -841,7 +749,7 @@ ssize_t drm_fb_helper_sys_write(struct fb_info info, const char __user buf, · 12 unmodified lines
841	ssize_t ret;	749	ssize_t ret;
842	struct drm_rect damage_area;	750	struct drm_rect damage_area;
843		751
844	ret = __drm_fb_helper_write(info, buf, count, ppos, drm_fb_helper_write_screen_buffer);	752	ret = fb_sys_write(info, buf, count, ppos);
845	if (ret <= 0)	753	if (ret <= 0)
846	return ret;	754	return ret;
847		755
@@ -913,39 +821,6 @@ void drm_fb_helper_sys_imageblit(struct fb_info *info, · 65 unmodified lines
913	}	821	}
914	EXPORT_SYMBOL(drm_fb_helper_sys_imageblit);	822	EXPORT_SYMBOL(drm_fb_helper_sys_imageblit);
915		823
916	static ssize_t fb_read_screen_base(struct fb_info info, char __user buf, size_t count,
917	loff_t pos)
918	{
919	const char __iomem *src = info->screen_base + pos;
920	size_t alloc_size = min_t(size_t, count, PAGE_SIZE);
921	ssize_t ret = 0;
922	int err = 0;
923	char *tmp;
924
925	tmp = kmalloc(alloc_size, GFP_KERNEL);
926	if (!tmp)
927	return -ENOMEM;
928
929	while (count) {
930	size_t c = min_t(size_t, count, alloc_size);
931
932	memcpy_fromio(tmp, src, c);
933	if (copy_to_user(buf, tmp, c)) {
934	err = -EFAULT;
935	break;
936	}
937
938	src += c;
939	buf += c;
940	ret += c;
941	count -= c;
942	}
943
944	kfree(tmp);
945
946	return ret ? ret : err;
947	}
948
949	/**	824	/**
950	* drm_fb_helper_cfb_read - Implements struct &fb_ops.fb_read for I/O memory	825	* drm_fb_helper_cfb_read - Implements struct &fb_ops.fb_read for I/O memory
951	* @info: fb_info struct pointer	826	* @info: fb_info struct pointer
@@ -959,43 +834,10 @@ static ssize_t fb_read_screen_base(struct fb_info info, char __user buf, size_ · 7 unmodified lines
959	ssize_t drm_fb_helper_cfb_read(struct fb_info info, char __user buf,	834	ssize_t drm_fb_helper_cfb_read(struct fb_info info, char __user buf,
960	size_t count, loff_t *ppos)	835	size_t count, loff_t *ppos)
961	{	836	{
962	return __drm_fb_helper_read(info, buf, count, ppos, fb_read_screen_base);	837	return fb_io_read(info, buf, count, ppos);
963	}	838	}
964	EXPORT_SYMBOL(drm_fb_helper_cfb_read);	839	EXPORT_SYMBOL(drm_fb_helper_cfb_read);
965		840
966	static ssize_t fb_write_screen_base(struct fb_info info, const char __user buf, size_t count,
967	loff_t pos)
968	{
969	char __iomem *dst = info->screen_base + pos;
970	size_t alloc_size = min_t(size_t, count, PAGE_SIZE);
971	ssize_t ret = 0;
972	int err = 0;
973	u8 *tmp;
974
975	tmp = kmalloc(alloc_size, GFP_KERNEL);
976	if (!tmp)
977	return -ENOMEM;
978
979	while (count) {
980	size_t c = min_t(size_t, count, alloc_size);
981
982	if (copy_from_user(tmp, buf, c)) {
983	err = -EFAULT;
984	break;
985	}
986	memcpy_toio(dst, tmp, c);
987
988	dst += c;
989	buf += c;
990	ret += c;
991	count -= c;
992	}
993
994	kfree(tmp);
995
996	return ret ? ret : err;
997	}
998
999	/**	841	/**
1000	* drm_fb_helper_cfb_write - Implements struct &fb_ops.fb_write for I/O memory	842	* drm_fb_helper_cfb_write - Implements struct &fb_ops.fb_write for I/O memory
1001	* @info: fb_info struct pointer	843	* @info: fb_info struct pointer
@@ -1014,7 +856,7 @@ ssize_t drm_fb_helper_cfb_write(struct fb_info info, const char __user buf, · 12 unmodified lines
1014	ssize_t ret;	856	ssize_t ret;
1015	struct drm_rect damage_area;	857	struct drm_rect damage_area;
1016		858
1017	ret = __drm_fb_helper_write(info, buf, count, ppos, fb_write_screen_base);	859	ret = fb_io_write(info, buf, count, ppos);
1018	if (ret <= 0)	860	if (ret <= 0)
1019	return ret;	861	return ret;
1020		862

drivers/gpu/drm/drm_gem_framebuffer_helper.c+9−0

 #include <linux/module.h>
 #include <drm/drm_damage_helper.h>
+#include <drm/drm_drv.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_framebuffer.h>
 #include <drm/drm_gem.h>
 		return -EINVAL;
 	}
+	if (drm_drv_uses_atomic_modeset(dev) &&
+	    !drm_any_plane_has_format(dev, mode_cmd->pixel_format,
+				      mode_cmd->modifier[0])) {
+		drm_dbg(dev, "Unsupported pixel format %p4cc / modifier 0x%llx\n",
+			&mode_cmd->pixel_format, mode_cmd->modifier[0]);
+		return -EINVAL;
+	}
 	for (i = 0; i < info->num_planes; i++) {
 		unsigned int width = mode_cmd->width / (i ? info->hsub : 1);
 		unsigned int height = mode_cmd->height / (i ? info->vsub : 1);

drivers/gpu/drm/drm_gem_vram_helper.c+3−3

@@ -45,7 +45,7 @@ static const struct drm_gem_object_funcs drm_gem_vram_object_funcs; · 44 unmodified lines
45	* the frame's scanout buffer or the cursor image. If there's no more space	45	* the frame's scanout buffer or the cursor image. If there's no more space
46	* left in VRAM, inactive GEM objects can be moved to system memory.	46	* left in VRAM, inactive GEM objects can be moved to system memory.
47	*	47	*
48	* To initialize the VRAM helper library call drmm_vram_helper_alloc_mm().	48	* To initialize the VRAM helper library call drmm_vram_helper_init().
49	* The function allocates and initializes an instance of &struct drm_vram_mm	49	* The function allocates and initializes an instance of &struct drm_vram_mm
50	* in &struct drm_device.vram_mm . Use &DRM_GEM_VRAM_DRIVER to initialize	50	* in &struct drm_device.vram_mm . Use &DRM_GEM_VRAM_DRIVER to initialize
51	* &struct drm_driver and &DRM_VRAM_MM_FILE_OPERATIONS to initialize	51	* &struct drm_driver and &DRM_VRAM_MM_FILE_OPERATIONS to initialize
@@ -73,7 +73,7 @@ static const struct drm_gem_object_funcs drm_gem_vram_object_funcs; · 21 unmodified lines
73	* // setup device, vram base and size	73	* // setup device, vram base and size
74	* // ...	74	* // ...
75	*	75	*
76	* ret = drmm_vram_helper_alloc_mm(dev, vram_base, vram_size);	76	* ret = drmm_vram_helper_init(dev, vram_base, vram_size);
77	* if (ret)	77	* if (ret)
78	* return ret;	78	* return ret;
79	* return 0;	79	* return 0;
@@ -86,7 +86,7 @@ static const struct drm_gem_object_funcs drm_gem_vram_object_funcs; · 6 unmodified lines
86	* to userspace.	86	* to userspace.
87	*	87	*
88	* You don't have to clean up the instance of VRAM MM.	88	* You don't have to clean up the instance of VRAM MM.
89	* drmm_vram_helper_alloc_mm() is a managed interface that installs a	89	* drmm_vram_helper_init() is a managed interface that installs a
90	* clean-up handler to run during the DRM device's release.	90	* clean-up handler to run during the DRM device's release.
91	*	91	*
92	* For drawing or scanout operations, rsp. buffer objects have to be pinned	92	* For drawing or scanout operations, rsp. buffer objects have to be pinned

drivers/gpu/drm/drm_mipi_dsi.c+1−1

@@ -221,7 +221,7 @@ mipi_dsi_device_register_full(struct mipi_dsi_host *host, · 220 unmodified lines
221	return dsi;	221	return dsi;
222	}	222	}
223		223
224	dsi->dev.of_node = info->node;	224	device_set_node(&dsi->dev, of_fwnode_handle(info->node));
225	dsi->channel = info->channel;	225	dsi->channel = info->channel;
226	strlcpy(dsi->name, info->type, sizeof(dsi->name));	226	strlcpy(dsi->name, info->type, sizeof(dsi->name));
227		227

drivers/gpu/drm/drm_sysfs.c+51−0

@@ -11,12 +11,14 @@ · 10 unmodified lines
11	*/	11	*/
12		12
13	#include <linux/acpi.h>	13	#include <linux/acpi.h>
		14	#include <linux/component.h>
14	#include <linux/device.h>	15	#include <linux/device.h>
15	#include <linux/err.h>	16	#include <linux/err.h>
16	#include <linux/export.h>	17	#include <linux/export.h>
17	#include <linux/gfp.h>	18	#include <linux/gfp.h>
18	#include <linux/i2c.h>	19	#include <linux/i2c.h>
19	#include <linux/kdev_t.h>	20	#include <linux/kdev_t.h>
		21	#include <linux/property.h>
20	#include <linux/slab.h>	22	#include <linux/slab.h>
21		23
22	#include <drm/drm_accel.h>	24	#include <drm/drm_accel.h>
@@ -96,6 +98,34 @@ static char drm_devnode(const struct device dev, umode_t *mode) · 73 unmodified lines
96	return kasprintf(GFP_KERNEL, "dri/%s", dev_name(dev));	98	return kasprintf(GFP_KERNEL, "dri/%s", dev_name(dev));
97	}	99	}
98		100
		101	static int typec_connector_bind(struct device *dev,
		102	struct device typec_connector, void data)
		103	{
		104	int ret;
		105
		106	ret = sysfs_create_link(&dev->kobj, &typec_connector->kobj, "typec_connector");
		107	if (ret)
		108	return ret;
		109
		110	ret = sysfs_create_link(&typec_connector->kobj, &dev->kobj, "drm_connector");
		111	if (ret)
		112	sysfs_remove_link(&dev->kobj, "typec_connector");
		113
		114	return ret;
		115	}
		116
		117	static void typec_connector_unbind(struct device *dev,
		118	struct device typec_connector, void data)
		119	{
		120	sysfs_remove_link(&typec_connector->kobj, "drm_connector");
		121	sysfs_remove_link(&dev->kobj, "typec_connector");
		122	}
		123
		124	static const struct component_ops typec_connector_ops = {
		125	.bind = typec_connector_bind,
		126	.unbind = typec_connector_unbind,
		127	};
		128
99	static CLASS_ATTR_STRING(version, S_IRUGO, "drm 1.1.0 20060810");	129	static CLASS_ATTR_STRING(version, S_IRUGO, "drm 1.1.0 20060810");
100		130
101	/**	131	/**
@@ -282,16 +312,27 @@ static ssize_t modes_show(struct device *device, · 180 unmodified lines
282	return written;	312	return written;
283	}	313	}
284		314
		315	static ssize_t connector_id_show(struct device *device,
		316	struct device_attribute *attr,
		317	char *buf)
		318	{
		319	struct drm_connector *connector = to_drm_connector(device);
		320
		321	return sysfs_emit(buf, "%d\n", connector->base.id);
		322	}
		323
285	static DEVICE_ATTR_RW(status);	324	static DEVICE_ATTR_RW(status);
286	static DEVICE_ATTR_RO(enabled);	325	static DEVICE_ATTR_RO(enabled);
287	static DEVICE_ATTR_RO(dpms);	326	static DEVICE_ATTR_RO(dpms);
288	static DEVICE_ATTR_RO(modes);	327	static DEVICE_ATTR_RO(modes);
		328	static DEVICE_ATTR_RO(connector_id);
289		329
290	static struct attribute *connector_dev_attrs[] = {	330	static struct attribute *connector_dev_attrs[] = {
291	&dev_attr_status.attr,	331	&dev_attr_status.attr,
292	&dev_attr_enabled.attr,	332	&dev_attr_enabled.attr,
293	&dev_attr_dpms.attr,	333	&dev_attr_dpms.attr,
294	&dev_attr_modes.attr,	334	&dev_attr_modes.attr,
		335	&dev_attr_connector_id.attr,
295	NULL	336	NULL
296	};	337	};
297		338
@@ -353,9 +394,16 @@ int drm_sysfs_connector_add(struct drm_connector *connector) · 55 unmodified lines
353		394
354	connector->kdev = kdev;	395	connector->kdev = kdev;
355		396
		397	if (dev_fwnode(kdev)) {
		398	r = component_add(kdev, &typec_connector_ops);
		399	if (r)
		400	drm_err(dev, "failed to add component to create link to typec connector\n");
		401	}
		402
356	if (connector->ddc)	403	if (connector->ddc)
357	return sysfs_create_link(&connector->kdev->kobj,	404	return sysfs_create_link(&connector->kdev->kobj,
358	&connector->ddc->dev.kobj, "ddc");	405	&connector->ddc->dev.kobj, "ddc");
		406
359	return 0;	407	return 0;
360		408
361	err_free:	409	err_free:
@@ -371,6 +419,9 @@ void drm_sysfs_connector_remove(struct drm_connector *connector) · 9 unmodified lines
371	if (connector->ddc)	419	if (connector->ddc)
372	sysfs_remove_link(&connector->kdev->kobj, "ddc");	420	sysfs_remove_link(&connector->kdev->kobj, "ddc");
373		421
		422	if (dev_fwnode(connector->kdev))
		423	component_del(connector->kdev, &typec_connector_ops);
		424
374	DRM_DEBUG("removing \"%s\" from sysfs\n",	425	DRM_DEBUG("removing \"%s\" from sysfs\n",
375	connector->name);	426	connector->name);
376		427

drivers/gpu/drm/gma500/fbdev.c+1−1

@@ -231,7 +231,7 @@ static int psb_fbdev_fb_probe(struct drm_fb_helper *fb_helper, · 230 unmodified lines
231	info->fix.mmio_start = pci_resource_start(pdev, 0);	231	info->fix.mmio_start = pci_resource_start(pdev, 0);
232	info->fix.mmio_len = pci_resource_len(pdev, 0);	232	info->fix.mmio_len = pci_resource_len(pdev, 0);
233		233
234	memset(info->screen_base, 0, info->screen_size);	234	fb_memset_io(info->screen_base, 0, info->screen_size);
235		235
236	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */	236	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
237		237

drivers/gpu/drm/gma500/psb_drv.c+34−9

  *
  **************************************************************************/
+#include <linux/aperture.h>
 #include <linux/cpu.h>
 #include <linux/module.h>
 #include <linux/notifier.h>
 #include <acpi/video.h>
 #include <drm/drm.h>
-#include <drm/drm_aperture.h>
 #include <drm/drm_drv.h>
 #include <drm/drm_file.h>
 #include <drm/drm_ioctl.h>
 	return ret;
 }
+/*
+ * Hardware for gma500 is a hybrid device, which both acts as a PCI
+ * device (for legacy vga functionality) but also more like an
+ * integrated display on a SoC where the framebuffer simply
+ * resides in main memory and not in a special PCI bar (that
+ * internally redirects to a stolen range of main memory) like all
+ * other integrated PCI display devices implement it.
+ *
+ * To catch all cases we need to remove conflicting firmware devices
+ * for the stolen system memory and for the VGA functionality. As we
+ * currently cannot easily find the framebuffer's location in stolen
+ * memory, we remove all framebuffers here.
+ *
+ * TODO: Refactor psb_driver_load() to map vdc_reg earlier. Then
+ *       we might be able to read the framebuffer range from the
+ *       device.
+ */
+static int gma_remove_conflicting_framebuffers(struct pci_dev *pdev,
+					       const struct drm_driver *req_driver)
+{
+	resource_size_t base = 0;
+	resource_size_t size = U32_MAX; /* 4 GiB HW limit */
+	const char *name = req_driver->name;
+	int ret;
+	ret = aperture_remove_conflicting_devices(base, size, name);
+	if (ret)
+		return ret;
+	return __aperture_remove_legacy_vga_devices(pdev);
+}
 static int psb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
 	struct drm_psb_private *dev_priv;
 	struct drm_device *dev;
 	int ret;
-	/*
+	ret = gma_remove_conflicting_framebuffers(pdev, &driver);
-	 * We cannot yet easily find the framebuffer's location in memory. So
-	 * remove all framebuffers here.
-	 *
-	 * TODO: Refactor psb_driver_load() to map vdc_reg earlier. Then we
-	 *       might be able to read the framebuffer range from the device.
-	 */
-	ret = drm_aperture_remove_framebuffers(true, &driver);
 	if (ret)
 		return ret;

drivers/gpu/drm/hyperv/hyperv_drm_drv.c+0−1

@@ -74,7 +74,6 @@ static int hyperv_setup_vram(struct hyperv_drm_device *hv, · 73 unmodified lines
74		74
75	drm_aperture_remove_conflicting_framebuffers(screen_info.lfb_base,	75	drm_aperture_remove_conflicting_framebuffers(screen_info.lfb_base,
76	screen_info.lfb_size,	76	screen_info.lfb_size,
77	false,
78	&hyperv_driver);	77	&hyperv_driver);
79		78
80	hv->fb_size = (unsigned long)hv->mmio_megabytes * 1024 * 1024;	79	hv->fb_size = (unsigned long)hv->mmio_megabytes * 1024 * 1024;

drivers/gpu/drm/i915/Makefile+4−2

 # general-purpose microcontroller (GuC) support
 i915-y += \
 	  gt/uc/intel_gsc_fw.o \
+	  gt/uc/intel_gsc_proxy.o \
 	  gt/uc/intel_gsc_uc.o \
 	  gt/uc/intel_gsc_uc_heci_cmd_submit.o\
 	  gt/uc/intel_guc.o \
 i915-$(CONFIG_DRM_I915_PXP) += \
 	pxp/intel_pxp_cmd.o \
 	pxp/intel_pxp_debugfs.o \
+	pxp/intel_pxp_gsccs.o \
 	pxp/intel_pxp_irq.o \
 	pxp/intel_pxp_pm.o \
 	pxp/intel_pxp_session.o
 #
 # Enable locally for CONFIG_DRM_I915_WERROR=y. See also scripts/Makefile.build
 ifdef CONFIG_DRM_I915_WERROR
-    cmd_checkdoc = $(srctree)/scripts/kernel-doc -none $<
+    cmd_checkdoc = $(srctree)/scripts/kernel-doc -none -Werror $<
 endif
 # header test
 quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@)
       cmd_hdrtest = $(CC) $(filter-out $(CFLAGS_GCOV), $(c_flags)) -S -o /dev/null -x c /dev/null -include $<; \
-		$(srctree)/scripts/kernel-doc -none $<; touch $@
+		$(srctree)/scripts/kernel-doc -none -Werror $<; touch $@
 $(obj)/%.hdrtest: $(src)/%.h FORCE
 	$(call if_changed_dep,hdrtest)

drivers/gpu/drm/i915/display/intel_dpt.c+7−7

@@ -43,24 +43,24 @@ static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) · 42 unmodified lines
43	static void dpt_insert_page(struct i915_address_space *vm,	43	static void dpt_insert_page(struct i915_address_space *vm,
44	dma_addr_t addr,	44	dma_addr_t addr,
45	u64 offset,	45	u64 offset,
46	enum i915_cache_level level,	46	unsigned int pat_index,
47	u32 flags)	47	u32 flags)
48	{	48	{
49	struct i915_dpt *dpt = i915_vm_to_dpt(vm);	49	struct i915_dpt *dpt = i915_vm_to_dpt(vm);
50	gen8_pte_t __iomem *base = dpt->iomem;	50	gen8_pte_t __iomem *base = dpt->iomem;
51		51
52	gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE,	52	gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE,
53	vm->pte_encode(addr, level, flags));	53	vm->pte_encode(addr, pat_index, flags));
54	}	54	}
55		55
56	static void dpt_insert_entries(struct i915_address_space *vm,	56	static void dpt_insert_entries(struct i915_address_space *vm,
57	struct i915_vma_resource *vma_res,	57	struct i915_vma_resource *vma_res,
58	enum i915_cache_level level,	58	unsigned int pat_index,
59	u32 flags)	59	u32 flags)
60	{	60	{
61	struct i915_dpt *dpt = i915_vm_to_dpt(vm);	61	struct i915_dpt *dpt = i915_vm_to_dpt(vm);
62	gen8_pte_t __iomem *base = dpt->iomem;	62	gen8_pte_t __iomem *base = dpt->iomem;
63	const gen8_pte_t pte_encode = vm->pte_encode(0, level, flags);	63	const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
64	struct sgt_iter sgt_iter;	64	struct sgt_iter sgt_iter;
65	dma_addr_t addr;	65	dma_addr_t addr;
66	int i;	66	int i;
@@ -83,7 +83,7 @@ static void dpt_clear_range(struct i915_address_space *vm, · 16 unmodified lines
83	static void dpt_bind_vma(struct i915_address_space *vm,	83	static void dpt_bind_vma(struct i915_address_space *vm,
84	struct i915_vm_pt_stash *stash,	84	struct i915_vm_pt_stash *stash,
85	struct i915_vma_resource *vma_res,	85	struct i915_vma_resource *vma_res,
86	enum i915_cache_level cache_level,	86	unsigned int pat_index,
87	u32 flags)	87	u32 flags)
88	{	88	{
89	u32 pte_flags;	89	u32 pte_flags;
@@ -98,7 +98,7 @@ static void dpt_bind_vma(struct i915_address_space *vm, · 8 unmodified lines
98	if (vma_res->bi.lmem)	98	if (vma_res->bi.lmem)
99	pte_flags \|= PTE_LM;	99	pte_flags \|= PTE_LM;
100		100
101	vm->insert_entries(vm, vma_res, cache_level, pte_flags);	101	vm->insert_entries(vm, vma_res, pat_index, pte_flags);
102		102
103	vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;	103	vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
104		104
@@ -300,7 +300,7 @@ intel_dpt_create(struct intel_framebuffer *fb) · 195 unmodified lines
300	vm->vma_ops.bind_vma = dpt_bind_vma;	300	vm->vma_ops.bind_vma = dpt_bind_vma;
301	vm->vma_ops.unbind_vma = dpt_unbind_vma;	301	vm->vma_ops.unbind_vma = dpt_unbind_vma;
302		302
303	vm->pte_encode = gen8_ggtt_pte_encode;	303	vm->pte_encode = vm->gt->ggtt->vm.pte_encode;
304		304
305	dpt->obj = dpt_obj;	305	dpt->obj = dpt_obj;
306	dpt->obj->is_dpt = true;	306	dpt->obj->is_dpt = true;

drivers/gpu/drm/i915/display/intel_fb.c+6−3

 {
 	struct drm_i915_private *i915 = to_i915(fb->base.dev);
-	return IS_ALDERLAKE_P(i915) && intel_fb_uses_dpt(&fb->base);
+	return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) &&
+		intel_fb_uses_dpt(&fb->base);
 }
 static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation)
 			  unsigned int tile_width,
 			  unsigned int src_stride_tiles, unsigned int dst_stride_tiles)
 {
+	struct drm_i915_private *i915 = to_i915(fb->base.dev);
 	unsigned int stride_tiles;
-	if (IS_ALDERLAKE_P(to_i915(fb->base.dev)))
+	if (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
 		stride_tiles = src_stride_tiles;
 	else
 		stride_tiles = dst_stride_tiles;
 	memset(view, 0, sizeof(*view));
 	view->gtt.type = view_type;
-	if (view_type == I915_GTT_VIEW_REMAPPED && IS_ALDERLAKE_P(i915))
+	if (view_type == I915_GTT_VIEW_REMAPPED &&
+	    (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14))
 		view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE;
 }

drivers/gpu/drm/i915/display/intel_fbdev.c+24−14

 #include <drm/drm_crtc.h>
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_fourcc.h>
+#include <drm/drm_gem_framebuffer_helper.h>
 #include "gem/i915_gem_lmem.h"
+#include "gem/i915_gem_mman.h"
 #include "i915_drv.h"
 #include "intel_display_types.h"
 	struct mutex hpd_lock;
 };
+static struct intel_fbdev *to_intel_fbdev(struct drm_fb_helper *fb_helper)
+{
+	return container_of(fb_helper, struct intel_fbdev, helper);
+}
 static struct intel_frontbuffer *to_frontbuffer(struct intel_fbdev *ifbdev)
 {
 	return ifbdev->fb->frontbuffer;
 static int intel_fbdev_set_par(struct fb_info *info)
 {
-	struct drm_fb_helper *fb_helper = info->par;
+	struct intel_fbdev *ifbdev = to_intel_fbdev(info->par);
-	struct intel_fbdev *ifbdev =
-		container_of(fb_helper, struct intel_fbdev, helper);
 	int ret;
 	ret = drm_fb_helper_set_par(info);
 static int intel_fbdev_blank(int blank, struct fb_info *info)
 {
-	struct drm_fb_helper *fb_helper = info->par;
+	struct intel_fbdev *ifbdev = to_intel_fbdev(info->par);
-	struct intel_fbdev *ifbdev =
-		container_of(fb_helper, struct intel_fbdev, helper);
 	int ret;
 	ret = drm_fb_helper_blank(blank, info);
 static int intel_fbdev_pan_display(struct fb_var_screeninfo *var,
 				   struct fb_info *info)
 {
-	struct drm_fb_helper *fb_helper = info->par;
+	struct intel_fbdev *ifbdev = to_intel_fbdev(info->par);
-	struct intel_fbdev *ifbdev =
-		container_of(fb_helper, struct intel_fbdev, helper);
 	int ret;
 	ret = drm_fb_helper_pan_display(var, info);
 	return ret;
 }
+static int intel_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma)
+{
+	struct intel_fbdev *fbdev = to_intel_fbdev(info->par);
+	struct drm_gem_object *bo = drm_gem_fb_get_obj(&fbdev->fb->base, 0);
+	struct drm_i915_gem_object *obj = to_intel_bo(bo);
+	return i915_gem_fb_mmap(obj, vma);
+}
 static const struct fb_ops intelfb_ops = {
 	.owner = THIS_MODULE,
 	DRM_FB_HELPER_DEFAULT_OPS,
 	.fb_imageblit = drm_fb_helper_cfb_imageblit,
 	.fb_pan_display = intel_fbdev_pan_display,
 	.fb_blank = intel_fbdev_blank,
+	.fb_mmap = intel_fbdev_mmap,
 };
 static int intelfb_alloc(struct drm_fb_helper *helper,
 			 struct drm_fb_helper_surface_size *sizes)
 {
-	struct intel_fbdev *ifbdev =
+	struct intel_fbdev *ifbdev = to_intel_fbdev(helper);
-		container_of(helper, struct intel_fbdev, helper);
 	struct drm_framebuffer *fb;
 	struct drm_device *dev = helper->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	obj = ERR_PTR(-ENODEV);
 	if (HAS_LMEM(dev_priv)) {
 		obj = i915_gem_object_create_lmem(dev_priv, size,
-						  I915_BO_ALLOC_CONTIGUOUS);
+						  I915_BO_ALLOC_CONTIGUOUS |
+						  I915_BO_ALLOC_USER);
 	} else {
 		/*
 		 * If the FB is too big, just don't use it since fbdev is not very
 static int intelfb_create(struct drm_fb_helper *helper,
 			  struct drm_fb_helper_surface_size *sizes)
 {
-	struct intel_fbdev *ifbdev =
+	struct intel_fbdev *ifbdev = to_intel_fbdev(helper);
-		container_of(helper, struct intel_fbdev, helper);
 	struct intel_framebuffer *intel_fb = ifbdev->fb;
 	struct drm_device *dev = helper->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);

drivers/gpu/drm/i915/display/intel_plane_initial.c+3−1

@@ -110,7 +110,9 @@ initial_plane_vma(struct drm_i915_private *i915, · 109 unmodified lines
110	size * 2 > i915->dsm.usable_size)	110	size * 2 > i915->dsm.usable_size)
111	return NULL;	111	return NULL;
112		112
113	obj = i915_gem_object_create_region_at(mem, phys_base, size, 0);	113	obj = i915_gem_object_create_region_at(mem, phys_base, size,
		114	I915_BO_ALLOC_USER \|
		115	I915_BO_PREALLOC);
114	if (IS_ERR(obj))	116	if (IS_ERR(obj))
115	return NULL;	117	return NULL;
116		118

drivers/gpu/drm/i915/gem/i915_gem_domain.c+43−18

 	if (IS_DGFX(i915))
 		return false;
-	return !(obj->cache_level == I915_CACHE_NONE ||
+	/*
-		 obj->cache_level == I915_CACHE_WT);
+	 * For objects created by userspace through GEM_CREATE with pat_index
+	 * set by set_pat extension, i915_gem_object_has_cache_level() will
+	 * always return true, because the coherency of such object is managed
+	 * by userspace. Othereise the call here would fall back to checking
+	 * whether the object is un-cached or write-through.
+	 */
+	return !(i915_gem_object_has_cache_level(obj, I915_CACHE_NONE) ||
+		 i915_gem_object_has_cache_level(obj, I915_CACHE_WT));
 }
 bool i915_gem_cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
 {
 	int ret;
-	if (obj->cache_level == cache_level)
+	/*
+	 * For objects created by userspace through GEM_CREATE with pat_index
+	 * set by set_pat extension, simply return 0 here without touching
+	 * the cache setting, because such objects should have an immutable
+	 * cache setting by desgin and always managed by userspace.
+	 */
+	if (i915_gem_object_has_cache_level(obj, cache_level))
 		return 0;
 	ret = i915_gem_object_wait(obj,
 		return ret;
 	/* Always invalidate stale cachelines */
-	if (obj->cache_level != cache_level) {
+	i915_gem_object_set_cache_coherency(obj, cache_level);
-		i915_gem_object_set_cache_coherency(obj, cache_level);
+	obj->cache_dirty = true;
-		obj->cache_dirty = true;
-	}
 	/* The cache-level will be applied when each vma is rebound. */
 	return i915_gem_object_unbind(obj,
 		goto out;
 	}
-	switch (obj->cache_level) {
+	/*
-	case I915_CACHE_LLC:
+	 * This ioctl should be disabled for the objects with pat_index
-	case I915_CACHE_L3_LLC:
+	 * set by user space.
-		args->caching = I915_CACHING_CACHED;
+	 */
-		break;
+	if (obj->pat_set_by_user) {
+		err = -EOPNOTSUPP;
+		goto out;
+	}
-	case I915_CACHE_WT:
+	if (i915_gem_object_has_cache_level(obj, I915_CACHE_LLC) ||
+	    i915_gem_object_has_cache_level(obj, I915_CACHE_L3_LLC))
+		args->caching = I915_CACHING_CACHED;
+	else if (i915_gem_object_has_cache_level(obj, I915_CACHE_WT))
 		args->caching = I915_CACHING_DISPLAY;
-		break;
+	else
-	default:
 		args->caching = I915_CACHING_NONE;
-		break;
-	}
 out:
 	rcu_read_unlock();
 	return err;
 	if (IS_DGFX(i915))
 		return -ENODEV;
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+		return -EOPNOTSUPP;
 	switch (args->caching) {
 	case I915_CACHING_NONE:
 		level = I915_CACHE_NONE;
 	if (!obj)
 		return -ENOENT;
+	/*
+	 * This ioctl should be disabled for the objects with pat_index
+	 * set by user space.
+	 */
+	if (obj->pat_set_by_user) {
+		ret = -EOPNOTSUPP;
+		goto out;
+	}
 	/*
 	 * The caching mode of proxy object is handled by its generator, and
 	 * not allowed to be changed by userspace.

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c+12−3

 	if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
 		return false;
+	/*
+	 * For objects created by userspace through GEM_CREATE with pat_index
+	 * set by set_pat extension, i915_gem_object_has_cache_level() always
+	 * return true, otherwise the call would fall back to checking whether
+	 * the object is un-cached.
+	 */
 	return (cache->has_llc ||
 		obj->cache_dirty ||
-		obj->cache_level != I915_CACHE_NONE);
+		!i915_gem_object_has_cache_level(obj, I915_CACHE_NONE));
 }
 static int eb_reserve_vma(struct i915_execbuffer *eb,
 	if (drm_mm_node_allocated(&cache->node)) {
 		ggtt->vm.insert_page(&ggtt->vm,
 				     i915_gem_object_get_dma_address(obj, page),
-				     offset, I915_CACHE_NONE, 0);
+				     offset,
+				     i915_gem_get_pat_index(ggtt->vm.i915,
+							    I915_CACHE_NONE),
+				     0);
 	} else {
 		offset += page << PAGE_SHIFT;
 	}
 			reloc_cache_unmap(&eb->reloc_cache);
 			mutex_lock(&vma->vm->mutex);
 			err = i915_vma_bind(target->vma,
-					    target->vma->obj->cache_level,
+					    target->vma->obj->pat_index,
 					    PIN_GLOBAL, NULL, NULL);
 			mutex_unlock(&vma->vm->mutex);
 			reloc_cache_remap(&eb->reloc_cache, ev->vma->obj);

drivers/gpu/drm/i915/gem/i915_gem_mman.c+102−46

@@ -383,7 +383,16 @@ retry: · 382 unmodified lines
383	}	383	}
384		384
385	/* Access to snoopable pages through the GTT is incoherent. */	385	/* Access to snoopable pages through the GTT is incoherent. */
386	if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(i915)) {	386	/*
		387	* For objects created by userspace through GEM_CREATE with pat_index
		388	* set by set_pat extension, coherency is managed by userspace, make
		389	* sure we don't fail handling the vm fault by calling
		390	* i915_gem_object_has_cache_level() which always return true for such
		391	* objects. Otherwise this helper function would fall back to checking
		392	* whether the object is un-cached.
		393	*/
		394	if (!(i915_gem_object_has_cache_level(obj, I915_CACHE_NONE) \|\|
		395	HAS_LLC(i915))) {
387	ret = -EFAULT;	396	ret = -EFAULT;
388	goto err_unpin;	397	goto err_unpin;
389	}	398	}
@@ -927,53 +936,15 @@ static struct file mmap_singleton(struct drm_i915_private i915) · 537 unmodified lines
927	return file;	936	return file;
928	}	937	}
929		938
930	/*	939	static int
931	* This overcomes the limitation in drm_gem_mmap's assignment of a	940	i915_gem_object_mmap(struct drm_i915_gem_object *obj,
932	* drm_gem_object as the vma->vm_private_data. Since we need to	941	struct i915_mmap_offset *mmo,
933	* be able to resolve multiple mmap offsets which could be tied	942	struct vm_area_struct *vma)
934	* to a single gem object.
935	*/
936	int i915_gem_mmap(struct file filp, struct vm_area_struct vma)
937	{	943	{
938	struct drm_vma_offset_node *node;	944	struct drm_i915_private *i915 = to_i915(obj->base.dev);
939	struct drm_file *priv = filp->private_data;	945	struct drm_device *dev = &i915->drm;
940	struct drm_device *dev = priv->minor->dev;
941	struct drm_i915_gem_object *obj = NULL;
942	struct i915_mmap_offset *mmo = NULL;
943	struct file *anon;	946	struct file *anon;
944		947
945	if (drm_dev_is_unplugged(dev))
946	return -ENODEV;
947
948	rcu_read_lock();
949	drm_vma_offset_lock_lookup(dev->vma_offset_manager);
950	node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,
951	vma->vm_pgoff,
952	vma_pages(vma));
953	if (node && drm_vma_node_is_allowed(node, priv)) {
954	/*
955	* Skip 0-refcnted objects as it is in the process of being
956	* destroyed and will be invalid when the vma manager lock
957	* is released.
958	*/
959	if (!node->driver_private) {
960	mmo = container_of(node, struct i915_mmap_offset, vma_node);
961	obj = i915_gem_object_get_rcu(mmo->obj);
962
963	GEM_BUG_ON(obj && obj->ops->mmap_ops);
964	} else {
965	obj = i915_gem_object_get_rcu
966	(container_of(node, struct drm_i915_gem_object,
967	base.vma_node));
968
969	GEM_BUG_ON(obj && !obj->ops->mmap_ops);
970	}
971	}
972	drm_vma_offset_unlock_lookup(dev->vma_offset_manager);
973	rcu_read_unlock();
974	if (!obj)
975	return node ? -EACCES : -EINVAL;
976
977	if (i915_gem_object_is_readonly(obj)) {	948	if (i915_gem_object_is_readonly(obj)) {
978	if (vma->vm_flags & VM_WRITE) {	949	if (vma->vm_flags & VM_WRITE) {
979	i915_gem_object_put(obj);	950	i915_gem_object_put(obj);
@@ -1005,7 +976,7 @@ int i915_gem_mmap(struct file filp, struct vm_area_struct vma) · 25 unmodified lines
1005	if (obj->ops->mmap_ops) {	976	if (obj->ops->mmap_ops) {
1006	vma->vm_page_prot = pgprot_decrypted(vm_get_page_prot(vma->vm_flags));	977	vma->vm_page_prot = pgprot_decrypted(vm_get_page_prot(vma->vm_flags));
1007	vma->vm_ops = obj->ops->mmap_ops;	978	vma->vm_ops = obj->ops->mmap_ops;
1008	vma->vm_private_data = node->driver_private;	979	vma->vm_private_data = obj->base.vma_node.driver_private;
1009	return 0;	980	return 0;
1010	}	981	}
1011		982
@@ -1043,6 +1014,91 @@ int i915_gem_mmap(struct file filp, struct vm_area_struct vma) · 31 unmodified lines
1043	return 0;	1014	return 0;
1044	}	1015	}
1045		1016
		1017	/*
		1018	* This overcomes the limitation in drm_gem_mmap's assignment of a
		1019	* drm_gem_object as the vma->vm_private_data. Since we need to
		1020	* be able to resolve multiple mmap offsets which could be tied
		1021	* to a single gem object.
		1022	*/
		1023	int i915_gem_mmap(struct file filp, struct vm_area_struct vma)
		1024	{
		1025	struct drm_vma_offset_node *node;
		1026	struct drm_file *priv = filp->private_data;
		1027	struct drm_device *dev = priv->minor->dev;
		1028	struct drm_i915_gem_object *obj = NULL;
		1029	struct i915_mmap_offset *mmo = NULL;
		1030
		1031	if (drm_dev_is_unplugged(dev))
		1032	return -ENODEV;
		1033
		1034	rcu_read_lock();
		1035	drm_vma_offset_lock_lookup(dev->vma_offset_manager);
		1036	node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,
		1037	vma->vm_pgoff,
		1038	vma_pages(vma));
		1039	if (node && drm_vma_node_is_allowed(node, priv)) {
		1040	/*
		1041	* Skip 0-refcnted objects as it is in the process of being
		1042	* destroyed and will be invalid when the vma manager lock
		1043	* is released.
		1044	*/
		1045	if (!node->driver_private) {
		1046	mmo = container_of(node, struct i915_mmap_offset, vma_node);
		1047	obj = i915_gem_object_get_rcu(mmo->obj);
		1048
		1049	GEM_BUG_ON(obj && obj->ops->mmap_ops);
		1050	} else {
		1051	obj = i915_gem_object_get_rcu
		1052	(container_of(node, struct drm_i915_gem_object,
		1053	base.vma_node));
		1054
		1055	GEM_BUG_ON(obj && !obj->ops->mmap_ops);
		1056	}
		1057	}
		1058	drm_vma_offset_unlock_lookup(dev->vma_offset_manager);
		1059	rcu_read_unlock();
		1060	if (!obj)
		1061	return node ? -EACCES : -EINVAL;
		1062
		1063	return i915_gem_object_mmap(obj, mmo, vma);
		1064	}
		1065
		1066	int i915_gem_fb_mmap(struct drm_i915_gem_object obj, struct vm_area_struct vma)
		1067	{
		1068	struct drm_i915_private *i915 = to_i915(obj->base.dev);
		1069	struct drm_device *dev = &i915->drm;
		1070	struct i915_mmap_offset *mmo = NULL;
		1071	enum i915_mmap_type mmap_type;
		1072	struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
		1073
		1074	if (drm_dev_is_unplugged(dev))
		1075	return -ENODEV;
		1076
		1077	/* handle ttm object */
		1078	if (obj->ops->mmap_ops) {
		1079	/*
		1080	* ttm fault handler, ttm_bo_vm_fault_reserved() uses fake offset
		1081	* to calculate page offset so set that up.
		1082	*/
		1083	vma->vm_pgoff += drm_vma_node_start(&obj->base.vma_node);
		1084	} else {
		1085	/* handle stolen and smem objects */
		1086	mmap_type = i915_ggtt_has_aperture(ggtt) ? I915_MMAP_TYPE_GTT : I915_MMAP_TYPE_WC;
		1087	mmo = mmap_offset_attach(obj, mmap_type, NULL);
		1088	if (!mmo)
		1089	return -ENODEV;
		1090	}
		1091
		1092	/*
		1093	* When we install vm_ops for mmap we are too late for
		1094	* the vm_ops->open() which increases the ref_count of
		1095	* this obj and then it gets decreased by the vm_ops->close().
		1096	* To balance this increase the obj ref_count here.
		1097	*/
		1098	obj = i915_gem_object_get(obj);
		1099	return i915_gem_object_mmap(obj, mmo, vma);
		1100	}
		1101
1046	#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)	1102	#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1047	#include "selftests/i915_gem_mman.c"	1103	#include "selftests/i915_gem_mman.c"
1048	#endif	1104	#endif

drivers/gpu/drm/i915/gem/i915_gem_mman.h+1−1

@@ -29,5 +29,5 @@ void i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj); · 28 unmodified lines
29		29
30	void i915_gem_object_runtime_pm_release_mmap_offset(struct drm_i915_gem_object *obj);	30	void i915_gem_object_runtime_pm_release_mmap_offset(struct drm_i915_gem_object *obj);
31	void i915_gem_object_release_mmap_offset(struct drm_i915_gem_object *obj);	31	void i915_gem_object_release_mmap_offset(struct drm_i915_gem_object *obj);
32		32	int i915_gem_fb_mmap(struct drm_i915_gem_object obj, struct vm_area_struct vma);
33	#endif	33	#endif

drivers/gpu/drm/i915/gem/i915_gem_object.c+59−1

@@ -45,6 +45,33 @@ static struct kmem_cache *slab_objects; · 44 unmodified lines
45		45
46	static const struct drm_gem_object_funcs i915_gem_object_funcs;	46	static const struct drm_gem_object_funcs i915_gem_object_funcs;
47		47
		48	unsigned int i915_gem_get_pat_index(struct drm_i915_private *i915,
		49	enum i915_cache_level level)
		50	{
		51	if (drm_WARN_ON(&i915->drm, level >= I915_MAX_CACHE_LEVEL))
		52	return 0;
		53
		54	return INTEL_INFO(i915)->cachelevel_to_pat[level];
		55	}
		56
		57	bool i915_gem_object_has_cache_level(const struct drm_i915_gem_object *obj,
		58	enum i915_cache_level lvl)
		59	{
		60	/*
		61	* In case the pat_index is set by user space, this kernel mode
		62	* driver should leave the coherency to be managed by user space,
		63	* simply return true here.
		64	*/
		65	if (obj->pat_set_by_user)
		66	return true;
		67
		68	/*
		69	* Otherwise the pat_index should have been converted from cache_level
		70	* so that the following comparison is valid.
		71	*/
		72	return obj->pat_index == i915_gem_get_pat_index(obj_to_i915(obj), lvl);
		73	}
		74
48	struct drm_i915_gem_object *i915_gem_object_alloc(void)	75	struct drm_i915_gem_object *i915_gem_object_alloc(void)
49	{	76	{
50	struct drm_i915_gem_object *obj;	77	struct drm_i915_gem_object *obj;
@@ -124,7 +151,7 @@ void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, · 73 unmodified lines
124	{	151	{
125	struct drm_i915_private *i915 = to_i915(obj->base.dev);	152	struct drm_i915_private *i915 = to_i915(obj->base.dev);
126		153
127	obj->cache_level = cache_level;	154	obj->pat_index = i915_gem_get_pat_index(i915, cache_level);
128		155
129	if (cache_level != I915_CACHE_NONE)	156	if (cache_level != I915_CACHE_NONE)
130	obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ \|	157	obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ \|
@@ -139,6 +166,37 @@ void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, · 8 unmodified lines
139	!IS_DGFX(i915);	166	!IS_DGFX(i915);
140	}	167	}
141		168
		169	/**
		170	* i915_gem_object_set_pat_index - set PAT index to be used in PTE encode
		171	* @obj: #drm_i915_gem_object
		172	* @pat_index: PAT index
		173	*
		174	* This is a clone of i915_gem_object_set_cache_coherency taking pat index
		175	* instead of cache_level as its second argument.
		176	*/
		177	void i915_gem_object_set_pat_index(struct drm_i915_gem_object *obj,
		178	unsigned int pat_index)
		179	{
		180	struct drm_i915_private *i915 = to_i915(obj->base.dev);
		181
		182	if (obj->pat_index == pat_index)
		183	return;
		184
		185	obj->pat_index = pat_index;
		186
		187	if (pat_index != i915_gem_get_pat_index(i915, I915_CACHE_NONE))
		188	obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ \|
		189	I915_BO_CACHE_COHERENT_FOR_WRITE);
		190	else if (HAS_LLC(i915))
		191	obj->cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ;
		192	else
		193	obj->cache_coherent = 0;
		194
		195	obj->cache_dirty =
		196	!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE) &&
		197	!IS_DGFX(i915);
		198	}
		199
142	bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj)	200	bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj)
143	{	201	{
144	struct drm_i915_private *i915 = to_i915(obj->base.dev);	202	struct drm_i915_private *i915 = to_i915(obj->base.dev);

drivers/gpu/drm/i915/gem/i915_gem_object.h+9−1

 enum intel_region_id;
+#define obj_to_i915(obj__) to_i915((obj__)->base.dev)
 static inline bool i915_gem_object_size_2big(u64 size)
 {
 	struct drm_i915_gem_object *obj;
 	return false;
 }
+unsigned int i915_gem_get_pat_index(struct drm_i915_private *i915,
+				    enum i915_cache_level level);
+bool i915_gem_object_has_cache_level(const struct drm_i915_gem_object *obj,
+				     enum i915_cache_level lvl);
 void i915_gem_init__objects(struct drm_i915_private *i915);
 void i915_objects_module_exit(void);
 /**
  * i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle
- * @filp: DRM file private date
+ * @file: DRM file private date
  * @handle: userspace handle
  *
  * Returns:
 void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj,
 					 unsigned int cache_level);
+void i915_gem_object_set_pat_index(struct drm_i915_gem_object *obj,
+				   unsigned int pat_index);
 bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj);
 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj);
 void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj);

drivers/gpu/drm/i915/gem/i915_gem_object_types.h+60−8

@@ -194,6 +194,13 @@ enum i915_cache_level { · 193 unmodified lines
194	* engine.	194	* engine.
195	*/	195	*/
196	I915_CACHE_WT,	196	I915_CACHE_WT,
		197	/**
		198	* @I915_MAX_CACHE_LEVEL:
		199	*
		200	* Mark the last entry in the enum. Used for defining cachelevel_to_pat
		201	* array for cache_level to pat translation table.
		202	*/
		203	I915_MAX_CACHE_LEVEL,
197	};	204	};
198		205
199	enum i915_map_type {	206	enum i915_map_type {
@@ -328,6 +335,12 @@ struct drm_i915_gem_object { · 128 unmodified lines
328	*/	335	*/
329	#define I915_BO_ALLOC_GPU_ONLY BIT(6)	336	#define I915_BO_ALLOC_GPU_ONLY BIT(6)
330	#define I915_BO_ALLOC_CCS_AUX BIT(7)	337	#define I915_BO_ALLOC_CCS_AUX BIT(7)
		338	/*
		339	* Object is allowed to retain its initial data and will not be cleared on first
		340	* access if used along with I915_BO_ALLOC_USER. This is mainly to keep
		341	* preallocated framebuffer data intact while transitioning it to i915drmfb.
		342	*/
		343	#define I915_BO_PREALLOC BIT(8)
331	#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS \| \	344	#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS \| \
332	I915_BO_ALLOC_VOLATILE \| \	345	I915_BO_ALLOC_VOLATILE \| \
333	I915_BO_ALLOC_CPU_CLEAR \| \	346	I915_BO_ALLOC_CPU_CLEAR \| \
@@ -335,10 +348,11 @@ struct drm_i915_gem_object { · 1 unmodified line
335	I915_BO_ALLOC_PM_VOLATILE \| \	348	I915_BO_ALLOC_PM_VOLATILE \| \
336	I915_BO_ALLOC_PM_EARLY \| \	349	I915_BO_ALLOC_PM_EARLY \| \
337	I915_BO_ALLOC_GPU_ONLY \| \	350	I915_BO_ALLOC_GPU_ONLY \| \
338	I915_BO_ALLOC_CCS_AUX)	351	I915_BO_ALLOC_CCS_AUX \| \
339	#define I915_BO_READONLY BIT(8)	352	I915_BO_PREALLOC)
340	#define I915_TILING_QUIRK_BIT 9 /* unknown swizzling; do not release! */	353	#define I915_BO_READONLY BIT(9)
341	#define I915_BO_PROTECTED BIT(10)	354	#define I915_TILING_QUIRK_BIT 10 /* unknown swizzling; do not release! */
		355	#define I915_BO_PROTECTED BIT(11)
342	/**	356	/**
343	* @mem_flags - Mutable placement-related flags	357	* @mem_flags - Mutable placement-related flags
344	*	358	*
@@ -350,15 +364,43 @@ struct drm_i915_gem_object { · 5 unmodified lines
350	#define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */	364	#define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
351	#define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */	365	#define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
352	/**	366	/**
353	* @cache_level: The desired GTT caching level.	367	* @pat_index: The desired PAT index.
		368	*
		369	* See hardware specification for valid PAT indices for each platform.
		370	* This field replaces the @cache_level that contains a value of enum
		371	* i915_cache_level since PAT indices are being used by both userspace
		372	* and kernel mode driver for caching policy control after GEN12.
		373	* In the meantime platform specific tables are created to translate
		374	* i915_cache_level into pat index, for more details check the macros
		375	* defined i915/i915_pci.c, e.g. PVC_CACHELEVEL.
		376	* For backward compatibility, this field contains values exactly match
		377	* the entries of enum i915_cache_level for pre-GEN12 platforms (See
		378	* LEGACY_CACHELEVEL), so that the PTE encode functions for these
		379	* legacy platforms can stay the same.
		380	*/
		381	unsigned int pat_index:6;
		382	/**
		383	* @pat_set_by_user: Indicate whether pat_index is set by user space
354	*	384	*
355	* See enum i915_cache_level for possible values, along with what	385	* This field is set to false by default, only set to true if the
356	* each does.	386	* pat_index is set by user space. By design, user space is capable of
		387	* managing caching behavior by setting pat_index, in which case this
		388	* kernel mode driver should never touch the pat_index.
357	*/	389	*/
358	unsigned int cache_level:3;	390	unsigned int pat_set_by_user:1;
359	/**	391	/**
360	* @cache_coherent:	392	* @cache_coherent:
361	*	393	*
		394	* Note: with the change above which replaced @cache_level with pat_index,
		395	* the use of @cache_coherent is limited to the objects created by kernel
		396	* or by userspace without pat index specified.
		397	* Check for @pat_set_by_user to find out if an object has pat index set
		398	* by userspace. The ioctl's to change cache settings have also been
		399	* disabled for the objects with pat index set by userspace. Please don't
		400	* assume @cache_coherent having the flags set as describe here. A helper
		401	* function i915_gem_object_has_cache_level() provides one way to bypass
		402	* the use of this field.
		403	*
362	* Track whether the pages are coherent with the GPU if reading or	404	* Track whether the pages are coherent with the GPU if reading or
363	* writing through the CPU caches. The largely depends on the	405	* writing through the CPU caches. The largely depends on the
364	* @cache_level setting.	406	* @cache_level setting.
@@ -432,6 +474,16 @@ struct drm_i915_gem_object { · 67 unmodified lines
432	/**	474	/**
433	* @cache_dirty:	475	* @cache_dirty:
434	*	476	*
		477	* Note: with the change above which replaced cache_level with pat_index,
		478	* the use of @cache_dirty is limited to the objects created by kernel
		479	* or by userspace without pat index specified.
		480	* Check for @pat_set_by_user to find out if an object has pat index set
		481	* by userspace. The ioctl's to change cache settings have also been
		482	* disabled for the objects with pat_index set by userspace. Please don't
		483	* assume @cache_dirty is set as describe here. Also see helper function
		484	* i915_gem_object_has_cache_level() for possible ways to bypass the use
		485	* of this field.
		486	*
435	* Track if we are we dirty with writes through the CPU cache for this	487	* Track if we are we dirty with writes through the CPU cache for this
436	* object. As a result reading directly from main memory might yield	488	* object. As a result reading directly from main memory might yield
437	* stale data.	489	* stale data.

drivers/gpu/drm/i915/gem/i915_gem_pages.c+4−1

 					  struct drm_i915_gem_object *obj,
 					  bool always_coherent)
 {
-	if (i915_gem_object_is_lmem(obj))
+	/*
+	 * Wa_22016122933: always return I915_MAP_WC for MTL
+	 */
+	if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(i915))
 		return I915_MAP_WC;
 	if (HAS_LLC(i915) || always_coherent)
 		return I915_MAP_WB;

drivers/gpu/drm/i915/gem/i915_gem_region.h+1−3

  */
 struct i915_gem_apply_to_region_ops {
 	/**
-	 * process_obj - Process the current object
+	 * @process_obj: Process the current object
-	 * @apply: Embed this for private data.
-	 * @obj: The current object.
 	 *
 	 * Note that if this function is part of a ww transaction, and
 	 * if returns -EDEADLK for one of the objects, it may be

drivers/gpu/drm/i915/gem/i915_gem_shmem.c+8−1

 	obj->write_domain = I915_GEM_DOMAIN_CPU;
 	obj->read_domains = I915_GEM_DOMAIN_CPU;
-	if (HAS_LLC(i915))
+	/*
+	 * MTL doesn't snoop CPU cache by default for GPU access (namely
+	 * 1-way coherency). However some UMD's are currently depending on
+	 * that. Make 1-way coherent the default setting for MTL. A follow
+	 * up patch will extend the GEM_CREATE uAPI to allow UMD's specify
+	 * caching mode at BO creation time
+	 */
+	if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)))
 		/* On some devices, we can have the GPU use the LLC (the CPU
 		 * cache) for about a 10% performance improvement
 		 * compared to uncached.  Graphics requests other than

drivers/gpu/drm/i915/gem/i915_gem_shrinker.c+0−2

@@ -460,8 +460,6 @@ void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915, · 459 unmodified lines
460	fs_reclaim_release(GFP_KERNEL);	460	fs_reclaim_release(GFP_KERNEL);
461	}	461	}
462		462
463	#define obj_to_i915(obj__) to_i915((obj__)->base.dev)
464
465	/**	463	/**
466	* i915_gem_object_make_unshrinkable - Hide the object from the shrinker. By	464	* i915_gem_object_make_unshrinkable - Hide the object from the shrinker. By
467	* default all object types that support shrinking(see IS_SHRINKABLE), will also	465	* default all object types that support shrinking(see IS_SHRINKABLE), will also

drivers/gpu/drm/i915/gem/i915_gem_stolen.c+11−1

 	/* Basic memrange allocator for stolen space. */
 	drm_mm_init(&i915->mm.stolen, 0, i915->dsm.usable_size);
+	/*
+	 * Access to stolen lmem beyond certain size for MTL A0 stepping
+	 * would crash the machine. Disable stolen lmem for userspace access
+	 * by setting usable_size to zero.
+	 */
+	if (IS_METEORLAKE(i915) && INTEL_REVID(i915) == 0x0)
+		i915->dsm.usable_size = 0;
 	return 0;
 }
 		ggtt->vm.insert_page(&ggtt->vm, addr,
 				     ggtt->error_capture.start,
-				     I915_CACHE_NONE, 0);
+				     i915_gem_get_pat_index(ggtt->vm.i915,
+							    I915_CACHE_NONE),
+				     0);
 		mb();
 		s = io_mapping_map_wc(&ggtt->iomap,

drivers/gpu/drm/i915/gem/i915_gem_ttm.h+2−1

 /**
  * i915_ttm_to_gem - Convert a struct ttm_buffer_object to an embedding
  * struct drm_i915_gem_object.
+ * @bo: Pointer to the ttm buffer object
  *
- * Return: Pointer to the embedding struct ttm_buffer_object.
+ * Return: Pointer to the embedding struct drm_i915_gem_object.
  */
 static inline struct drm_i915_gem_object *
 i915_ttm_to_gem(struct ttm_buffer_object *bo)

drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c+8−5

 		intel_engine_pm_get(to_gt(i915)->migrate.context->engine);
 		ret = intel_context_migrate_clear(to_gt(i915)->migrate.context, deps,
-						  dst_st->sgl, dst_level,
+						  dst_st->sgl,
+						  i915_gem_get_pat_index(i915, dst_level),
 						  i915_ttm_gtt_binds_lmem(dst_mem),
 						  0, &rq);
 	} else {
 		intel_engine_pm_get(to_gt(i915)->migrate.context->engine);
 		ret = intel_context_migrate_copy(to_gt(i915)->migrate.context,
 						 deps, src_rsgt->table.sgl,
-						 src_level,
+						 i915_gem_get_pat_index(i915, src_level),
 						 i915_ttm_gtt_binds_lmem(bo->resource),
-						 dst_st->sgl, dst_level,
+						 dst_st->sgl,
+						 i915_gem_get_pat_index(i915, dst_level),
 						 i915_ttm_gtt_binds_lmem(dst_mem),
 						 &rq);
 	struct dma_fence *migration_fence = NULL;
 	struct ttm_tt *ttm = bo->ttm;
 	struct i915_refct_sgt *dst_rsgt;
-	bool clear;
+	bool clear, prealloc_bo;
 	int ret;
 	if (GEM_WARN_ON(i915_ttm_is_ghost_object(bo))) {
 		return PTR_ERR(dst_rsgt);
 	clear = !i915_ttm_cpu_maps_iomem(bo->resource) && (!ttm || !ttm_tt_is_populated(ttm));
-	if (!(clear && ttm && !(ttm->page_flags & TTM_TT_FLAG_ZERO_ALLOC))) {
+	prealloc_bo = obj->flags & I915_BO_PREALLOC;
+	if (!(clear && ttm && !((ttm->page_flags & TTM_TT_FLAG_ZERO_ALLOC) && !prealloc_bo))) {
 		struct i915_deps deps;
 		i915_deps_init(&deps, GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN);

drivers/gpu/drm/i915/gem/selftests/huge_pages.c+82−26

@@ -354,7 +354,7 @@ fake_huge_pages_object(struct drm_i915_private *i915, u64 size, bool single) · 353 unmodified lines
354		354
355	obj->write_domain = I915_GEM_DOMAIN_CPU;	355	obj->write_domain = I915_GEM_DOMAIN_CPU;
356	obj->read_domains = I915_GEM_DOMAIN_CPU;	356	obj->read_domains = I915_GEM_DOMAIN_CPU;
357	obj->cache_level = I915_CACHE_NONE;	357	obj->pat_index = i915_gem_get_pat_index(i915, I915_CACHE_NONE);
358		358
359	return obj;	359	return obj;
360	}	360	}
@@ -695,8 +695,7 @@ out_put: · 334 unmodified lines
695	return err;	695	return err;
696	}	696	}
697		697
698	static void close_object_list(struct list_head *objects,	698	static void close_object_list(struct list_head *objects)
699	struct i915_ppgtt *ppgtt)
700	{	699	{
701	struct drm_i915_gem_object obj, on;	700	struct drm_i915_gem_object obj, on;
702		701
@@ -710,17 +709,36 @@ static void close_object_list(struct list_head *objects, · 7 unmodified lines
710	}	709	}
711	}	710	}
712		711
713	static int igt_mock_ppgtt_huge_fill(void *arg)	712	static int igt_ppgtt_huge_fill(void *arg)
714	{	713	{
715	struct i915_ppgtt *ppgtt = arg;	714	struct drm_i915_private *i915 = arg;
716	struct drm_i915_private *i915 = ppgtt->vm.i915;	715	unsigned int supported = RUNTIME_INFO(i915)->page_sizes;
717	unsigned long max_pages = ppgtt->vm.total >> PAGE_SHIFT;	716	bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
		717	struct i915_address_space *vm;
		718	struct i915_gem_context *ctx;
		719	unsigned long max_pages;
718	unsigned long page_num;	720	unsigned long page_num;
		721	struct file *file;
719	bool single = false;	722	bool single = false;
720	LIST_HEAD(objects);	723	LIST_HEAD(objects);
721	IGT_TIMEOUT(end_time);	724	IGT_TIMEOUT(end_time);
722	int err = -ENODEV;	725	int err = -ENODEV;
723		726
		727	if (supported == I915_GTT_PAGE_SIZE_4K)
		728	return 0;
		729
		730	file = mock_file(i915);
		731	if (IS_ERR(file))
		732	return PTR_ERR(file);
		733
		734	ctx = hugepage_ctx(i915, file);
		735	if (IS_ERR(ctx)) {
		736	err = PTR_ERR(ctx);
		737	goto out;
		738	}
		739	vm = i915_gem_context_get_eb_vm(ctx);
		740	max_pages = vm->total >> PAGE_SHIFT;
		741
724	for_each_prime_number_from(page_num, 1, max_pages) {	742	for_each_prime_number_from(page_num, 1, max_pages) {
725	struct drm_i915_gem_object *obj;	743	struct drm_i915_gem_object *obj;
726	u64 size = page_num << PAGE_SHIFT;	744	u64 size = page_num << PAGE_SHIFT;
@@ -750,13 +768,14 @@ static int igt_mock_ppgtt_huge_fill(void *arg) · 23 unmodified lines
750		768
751	list_add(&obj->st_link, &objects);	769	list_add(&obj->st_link, &objects);
752		770
753	vma = i915_vma_instance(obj, &ppgtt->vm, NULL);	771	vma = i915_vma_instance(obj, vm, NULL);
754	if (IS_ERR(vma)) {	772	if (IS_ERR(vma)) {
755	err = PTR_ERR(vma);	773	err = PTR_ERR(vma);
756	break;	774	break;
757	}	775	}
758		776
759	err = i915_vma_pin(vma, 0, 0, PIN_USER);	777	/* vma start must be aligned to BIT(21) to allow 2M PTEs */
		778	err = i915_vma_pin(vma, 0, BIT(21), PIN_USER);
760	if (err)	779	if (err)
761	break;	780	break;
762		781
@@ -784,12 +803,13 @@ static int igt_mock_ppgtt_huge_fill(void *arg) · 21 unmodified lines
784	GEM_BUG_ON(!expected_gtt);	803	GEM_BUG_ON(!expected_gtt);
785	GEM_BUG_ON(size);	804	GEM_BUG_ON(size);
786		805
787	if (expected_gtt & I915_GTT_PAGE_SIZE_4K)	806	if (!has_pte64 && (obj->base.size < I915_GTT_PAGE_SIZE_2M \|\|
		807	expected_gtt & I915_GTT_PAGE_SIZE_2M))
788	expected_gtt &= ~I915_GTT_PAGE_SIZE_64K;	808	expected_gtt &= ~I915_GTT_PAGE_SIZE_64K;
789		809
790	i915_vma_unpin(vma);	810	i915_vma_unpin(vma);
791		811
792	if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {	812	if (!has_pte64 && vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {
793	if (!IS_ALIGNED(vma->node.start,	813	if (!IS_ALIGNED(vma->node.start,
794	I915_GTT_PAGE_SIZE_2M)) {	814	I915_GTT_PAGE_SIZE_2M)) {
795	pr_err("node.start(%llx) not aligned to 2M\n",	815	pr_err("node.start(%llx) not aligned to 2M\n",
@@ -808,7 +828,7 @@ static int igt_mock_ppgtt_huge_fill(void *arg) · 12 unmodified lines
808	}	828	}
809		829
810	if (vma->resource->page_sizes_gtt != expected_gtt) {	830	if (vma->resource->page_sizes_gtt != expected_gtt) {
811	pr_err("gtt=%u, expected=%u, size=%zd, single=%s\n",	831	pr_err("gtt=%#x, expected=%#x, size=0x%zx, single=%s\n",
812	vma->resource->page_sizes_gtt, expected_gtt,	832	vma->resource->page_sizes_gtt, expected_gtt,
813	obj->base.size, str_yes_no(!!single));	833	obj->base.size, str_yes_no(!!single));
814	err = -EINVAL;	834	err = -EINVAL;
@@ -823,19 +843,25 @@ static int igt_mock_ppgtt_huge_fill(void *arg) · 8 unmodified lines
823	single = !single;	843	single = !single;
824	}	844	}
825		845
826	close_object_list(&objects, ppgtt);	846	close_object_list(&objects);
827		847
828	if (err == -ENOMEM \|\| err == -ENOSPC)	848	if (err == -ENOMEM \|\| err == -ENOSPC)
829	err = 0;	849	err = 0;
830		850
		851	i915_vm_put(vm);
		852	out:
		853	fput(file);
831	return err;	854	return err;
832	}	855	}
833		856
834	static int igt_mock_ppgtt_64K(void *arg)	857	static int igt_ppgtt_64K(void *arg)
835	{	858	{
836	struct i915_ppgtt *ppgtt = arg;	859	struct drm_i915_private *i915 = arg;
837	struct drm_i915_private *i915 = ppgtt->vm.i915;	860	bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
838	struct drm_i915_gem_object *obj;	861	struct drm_i915_gem_object *obj;
		862	struct i915_address_space *vm;
		863	struct i915_gem_context *ctx;
		864	struct file *file;
839	const struct object_info {	865	const struct object_info {
840	unsigned int size;	866	unsigned int size;
841	unsigned int gtt;	867	unsigned int gtt;
@@ -907,16 +933,41 @@ static int igt_mock_ppgtt_64K(void *arg) · 65 unmodified lines
907	if (!HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K))	933	if (!HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K))
908	return 0;	934	return 0;
909		935
		936	file = mock_file(i915);
		937	if (IS_ERR(file))
		938	return PTR_ERR(file);
		939
		940	ctx = hugepage_ctx(i915, file);
		941	if (IS_ERR(ctx)) {
		942	err = PTR_ERR(ctx);
		943	goto out;
		944	}
		945	vm = i915_gem_context_get_eb_vm(ctx);
		946
910	for (i = 0; i < ARRAY_SIZE(objects); ++i) {	947	for (i = 0; i < ARRAY_SIZE(objects); ++i) {
911	unsigned int size = objects[i].size;	948	unsigned int size = objects[i].size;
912	unsigned int expected_gtt = objects[i].gtt;	949	unsigned int expected_gtt = objects[i].gtt;
913	unsigned int offset = objects[i].offset;	950	unsigned int offset = objects[i].offset;
914	unsigned int flags = PIN_USER;	951	unsigned int flags = PIN_USER;
915		952
		953	/*
		954	* For modern GTT models, the requirements for marking a page-table
		955	* as 64K have been relaxed. Account for this.
		956	*/
		957	if (has_pte64) {
		958	expected_gtt = 0;
		959	if (size >= SZ_64K)
		960	expected_gtt \|= I915_GTT_PAGE_SIZE_64K;
		961	if (size & (SZ_64K - 1))
		962	expected_gtt \|= I915_GTT_PAGE_SIZE_4K;
		963	}
		964
916	for (single = 0; single <= 1; single++) {	965	for (single = 0; single <= 1; single++) {
917	obj = fake_huge_pages_object(i915, size, !!single);	966	obj = fake_huge_pages_object(i915, size, !!single);
918	if (IS_ERR(obj))	967	if (IS_ERR(obj)) {
919	return PTR_ERR(obj);	968	err = PTR_ERR(obj);
		969	goto out_vm;
		970	}
920		971
921	err = i915_gem_object_pin_pages_unlocked(obj);	972	err = i915_gem_object_pin_pages_unlocked(obj);
922	if (err)	973	if (err)
@@ -928,7 +979,7 @@ static int igt_mock_ppgtt_64K(void *arg) · 5 unmodified lines
928	*/	979	*/
929	obj->mm.page_sizes.sg &= ~I915_GTT_PAGE_SIZE_2M;	980	obj->mm.page_sizes.sg &= ~I915_GTT_PAGE_SIZE_2M;
930		981
931	vma = i915_vma_instance(obj, &ppgtt->vm, NULL);	982	vma = i915_vma_instance(obj, vm, NULL);
932	if (IS_ERR(vma)) {	983	if (IS_ERR(vma)) {
933	err = PTR_ERR(vma);	984	err = PTR_ERR(vma);
934	goto out_object_unpin;	985	goto out_object_unpin;
@@ -945,7 +996,8 @@ static int igt_mock_ppgtt_64K(void *arg) · 10 unmodified lines
945	if (err)	996	if (err)
946	goto out_vma_unpin;	997	goto out_vma_unpin;
947		998
948	if (!offset && vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {	999	if (!has_pte64 && !offset &&
		1000	vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {
949	if (!IS_ALIGNED(vma->node.start,	1001	if (!IS_ALIGNED(vma->node.start,
950	I915_GTT_PAGE_SIZE_2M)) {	1002	I915_GTT_PAGE_SIZE_2M)) {
951	pr_err("node.start(%llx) not aligned to 2M\n",	1003	pr_err("node.start(%llx) not aligned to 2M\n",
@@ -964,9 +1016,10 @@ static int igt_mock_ppgtt_64K(void *arg) · 12 unmodified lines
964	}	1016	}
965		1017
966	if (vma->resource->page_sizes_gtt != expected_gtt) {	1018	if (vma->resource->page_sizes_gtt != expected_gtt) {
967	pr_err("gtt=%u, expected=%u, i=%d, single=%s\n",	1019	pr_err("gtt=%#x, expected=%#x, i=%d, single=%s offset=%#x size=%#x\n",
968	vma->resource->page_sizes_gtt,	1020	vma->resource->page_sizes_gtt,
969	expected_gtt, i, str_yes_no(!!single));	1021	expected_gtt, i, str_yes_no(!!single),
		1022	offset, size);
970	err = -EINVAL;	1023	err = -EINVAL;
971	goto out_vma_unpin;	1024	goto out_vma_unpin;
972	}	1025	}
@@ -982,7 +1035,7 @@ static int igt_mock_ppgtt_64K(void *arg) · 9 unmodified lines
982	}	1035	}
983	}	1036	}
984		1037
985	return 0;	1038	goto out_vm;
986		1039
987	out_vma_unpin:	1040	out_vma_unpin:
988	i915_vma_unpin(vma);	1041	i915_vma_unpin(vma);
@@ -992,7 +1045,10 @@ out_object_unpin: · 3 unmodified lines
992	i915_gem_object_unlock(obj);	1045	i915_gem_object_unlock(obj);
993	out_object_put:	1046	out_object_put:
994	i915_gem_object_put(obj);	1047	i915_gem_object_put(obj);
995		1048	out_vm:
		1049	i915_vm_put(vm);
		1050	out:
		1051	fput(file);
996	return err;	1052	return err;
997	}	1053	}
998		1054
@@ -1910,8 +1966,6 @@ int i915_gem_huge_page_mock_selftests(void) · 911 unmodified lines
1910	SUBTEST(igt_mock_exhaust_device_supported_pages),	1966	SUBTEST(igt_mock_exhaust_device_supported_pages),
1911	SUBTEST(igt_mock_memory_region_huge_pages),	1967	SUBTEST(igt_mock_memory_region_huge_pages),
1912	SUBTEST(igt_mock_ppgtt_misaligned_dma),	1968	SUBTEST(igt_mock_ppgtt_misaligned_dma),
1913	SUBTEST(igt_mock_ppgtt_huge_fill),
1914	SUBTEST(igt_mock_ppgtt_64K),
1915	};	1969	};
1916	struct drm_i915_private *dev_priv;	1970	struct drm_i915_private *dev_priv;
1917	struct i915_ppgtt *ppgtt;	1971	struct i915_ppgtt *ppgtt;
@@ -1962,6 +2016,8 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *i915) · 44 unmodified lines
1962	SUBTEST(igt_ppgtt_sanity_check),	2016	SUBTEST(igt_ppgtt_sanity_check),
1963	SUBTEST(igt_ppgtt_compact),	2017	SUBTEST(igt_ppgtt_compact),
1964	SUBTEST(igt_ppgtt_mixed),	2018	SUBTEST(igt_ppgtt_mixed),
		2019	SUBTEST(igt_ppgtt_huge_fill),
		2020	SUBTEST(igt_ppgtt_64K),
1965	};	2021	};
1966		2022
1967	if (!HAS_PPGTT(i915)) {	2023	if (!HAS_PPGTT(i915)) {

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c+10−8

 		ctx[n] = live_context(i915, file);
 		if (IS_ERR(ctx[n])) {
 			err = PTR_ERR(ctx[n]);
-			goto out_file;
+			goto out_ctx;
 		}
 	}
 			this = igt_request_alloc(ctx[n], engine);
 			if (IS_ERR(this)) {
 				err = PTR_ERR(this);
-				goto out_file;
+				goto out_ctx;
 			}
 			if (rq) {
 				i915_request_await_dma_fence(this, &rq->fence);
 		}
 		if (i915_request_wait(rq, 0, 10 * HZ) < 0) {
 			pr_err("Failed to populated %d contexts\n", nctx);
-			intel_gt_set_wedged(to_gt(i915));
+			intel_gt_set_wedged(engine->gt);
 			i915_request_put(rq);
 			err = -EIO;
-			goto out_file;
+			goto out_ctx;
 		}
 		i915_request_put(rq);
 		err = igt_live_test_begin(&t, i915, __func__, engine->name);
 		if (err)
-			goto out_file;
+			goto out_ctx;
 		end_time = jiffies + i915_selftest.timeout_jiffies;
 		for_each_prime_number_from(prime, 2, 8192) {
 				this = igt_request_alloc(ctx[n % nctx], engine);
 				if (IS_ERR(this)) {
 					err = PTR_ERR(this);
-					goto out_file;
+					goto out_ctx;
 				}
 				if (rq) { /* Force submission order */
 			if (i915_request_wait(rq, 0, HZ / 5) < 0) {
 				pr_err("Switching between %ld contexts timed out\n",
 				       prime);
-				intel_gt_set_wedged(to_gt(i915));
+				intel_gt_set_wedged(engine->gt);
 				i915_request_put(rq);
 				break;
 			}
 		err = igt_live_test_end(&t);
 		if (err)
-			goto out_file;
+			goto out_ctx;
 		pr_info("Switch latencies on %s: 1 = %lluns, %lu = %lluns\n",
 			engine->name,
 			prime - 1, div64_u64(ktime_to_ns(times[1]), prime - 1));
 	}
+out_ctx:
+	kfree(ctx);
 out_file:
 	fput(file);
 	return err;

drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c+1−1

@@ -219,7 +219,7 @@ static int __igt_lmem_pages_migrate(struct intel_gt *gt, · 218 unmodified lines
219	continue;	219	continue;
220		220
221	err = intel_migrate_clear(&gt->migrate, &ww, deps,	221	err = intel_migrate_clear(&gt->migrate, &ww, deps,
222	obj->mm.pages->sgl, obj->cache_level,	222	obj->mm.pages->sgl, obj->pat_index,
223	i915_gem_object_is_lmem(obj),	223	i915_gem_object_is_lmem(obj),
224	0xdeadbeaf, &rq);	224	0xdeadbeaf, &rq);
225	if (rq) {	225	if (rq) {

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c+1−1

@@ -1222,7 +1222,7 @@ static int __igt_mmap_migrate(struct intel_memory_region **placements, · 1221 unmodified lines
1222	}	1222	}
1223		1223
1224	err = intel_context_migrate_clear(to_gt(i915)->migrate.context, NULL,	1224	err = intel_context_migrate_clear(to_gt(i915)->migrate.context, NULL,
1225	obj->mm.pages->sgl, obj->cache_level,	1225	obj->mm.pages->sgl, obj->pat_index,
1226	i915_gem_object_is_lmem(obj),	1226	i915_gem_object_is_lmem(obj),
1227	expand32(POISON_INUSE), &rq);	1227	expand32(POISON_INUSE), &rq);
1228	i915_gem_object_unpin_pages(obj);	1228	i915_gem_object_unpin_pages(obj);

drivers/gpu/drm/i915/gt/gen6_ppgtt.c+6−4

 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 				      struct i915_vma_resource *vma_res,
-				      enum i915_cache_level cache_level,
+				      unsigned int pat_index,
 				      u32 flags)
 {
 	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 	unsigned int first_entry = vma_res->start / I915_GTT_PAGE_SIZE;
 	unsigned int act_pt = first_entry / GEN6_PTES;
 	unsigned int act_pte = first_entry % GEN6_PTES;
-	const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
+	const u32 pte_encode = vm->pte_encode(0, pat_index, flags);
 	struct sgt_dma iter = sgt_dma(vma_res);
 	gen6_pte_t *vaddr;
 	vm->scratch[0]->encode =
 		vm->pte_encode(px_dma(vm->scratch[0]),
-			       I915_CACHE_NONE, PTE_READ_ONLY);
+			       i915_gem_get_pat_index(vm->i915,
+						      I915_CACHE_NONE),
+			       PTE_READ_ONLY);
 	vm->scratch[1] = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K);
 	if (IS_ERR(vm->scratch[1])) {
 static void pd_vma_bind(struct i915_address_space *vm,
 			struct i915_vm_pt_stash *stash,
 			struct i915_vma_resource *vma_res,
-			enum i915_cache_level cache_level,
+			unsigned int pat_index,
 			u32 unused)
 {
 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);

drivers/gpu/drm/i915/gt/gen8_ppgtt.c+61−23

 }
 static u64 gen8_pte_encode(dma_addr_t addr,
-			   enum i915_cache_level level,
+			   unsigned int pat_index,
 			   u32 flags)
 {
 	gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
 	if (flags & PTE_LM)
 		pte |= GEN12_PPGTT_PTE_LM;
-	switch (level) {
+	/*
+	 * For pre-gen12 platforms pat_index is the same as enum
+	 * i915_cache_level, so the switch-case here is still valid.
+	 * See translation table defined by LEGACY_CACHELEVEL.
+	 */
+	switch (pat_index) {
 	case I915_CACHE_NONE:
 		pte |= PPAT_UNCACHED;
 		break;
 	return pte;
 }
+static u64 gen12_pte_encode(dma_addr_t addr,
+			    unsigned int pat_index,
+			    u32 flags)
+{
+	gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
+	if (unlikely(flags & PTE_READ_ONLY))
+		pte &= ~GEN8_PAGE_RW;
+	if (flags & PTE_LM)
+		pte |= GEN12_PPGTT_PTE_LM;
+	if (pat_index & BIT(0))
+		pte |= GEN12_PPGTT_PTE_PAT0;
+	if (pat_index & BIT(1))
+		pte |= GEN12_PPGTT_PTE_PAT1;
+	if (pat_index & BIT(2))
+		pte |= GEN12_PPGTT_PTE_PAT2;
+	if (pat_index & BIT(3))
+		pte |= MTL_PPGTT_PTE_PAT3;
+	return pte;
+}
 static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
 {
 	struct drm_i915_private *i915 = ppgtt->vm.i915;
 		      struct i915_page_directory *pdp,
 		      struct sgt_dma *iter,
 		      u64 idx,
-		      enum i915_cache_level cache_level,
+		      unsigned int pat_index,
 		      u32 flags)
 {
 	struct i915_page_directory *pd;
-	const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
+	const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, pat_index, flags);
 	gen8_pte_t *vaddr;
 	pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
 xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
 			  struct i915_vma_resource *vma_res,
 			  struct sgt_dma *iter,
-			  enum i915_cache_level cache_level,
+			  unsigned int pat_index,
 			  u32 flags)
 {
-	const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);
+	const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
 	unsigned int rem = sg_dma_len(iter->sg);
 	u64 start = vma_res->start;
 	u64 end = start + vma_res->vma_size;
 			}
 		} while (rem >= page_size && index < max);
+		drm_clflush_virt_range(vaddr, PAGE_SIZE);
 		vma_res->page_sizes_gtt |= page_size;
 	} while (iter->sg && sg_dma_len(iter->sg));
 }
 static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
 				   struct i915_vma_resource *vma_res,
 				   struct sgt_dma *iter,
-				   enum i915_cache_level cache_level,
+				   unsigned int pat_index,
 				   u32 flags)
 {
-	const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
+	const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
 	unsigned int rem = sg_dma_len(iter->sg);
 	u64 start = vma_res->start;
 static void gen8_ppgtt_insert(struct i915_address_space *vm,
 			      struct i915_vma_resource *vma_res,
-			      enum i915_cache_level cache_level,
+			      unsigned int pat_index,
 			      u32 flags)
 {
 	struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(vm);
 	struct sgt_dma iter = sgt_dma(vma_res);
 	if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
-		if (HAS_64K_PAGES(vm->i915))
+		if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
-			xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter, cache_level, flags);
+			xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
 		else
-			gen8_ppgtt_insert_huge(vm, vma_res, &iter, cache_level, flags);
+			gen8_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
 	} else  {
 		u64 idx = vma_res->start >> GEN8_PTE_SHIFT;
 				gen8_pdp_for_page_index(vm, idx);
 			idx = gen8_ppgtt_insert_pte(ppgtt, pdp, &iter, idx,
-						    cache_level, flags);
+						    pat_index, flags);
 		} while (idx);
 		vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
 static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
 				    dma_addr_t addr,
 				    u64 offset,
-				    enum i915_cache_level level,
+				    unsigned int pat_index,
 				    u32 flags)
 {
 	u64 idx = offset >> GEN8_PTE_SHIFT;
 	GEM_BUG_ON(pt->is_compact);
 	vaddr = px_vaddr(pt);
-	vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
+	vaddr[gen8_pd_index(idx, 0)] = vm->pte_encode(addr, pat_index, flags);
 	drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
 }
 static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
 					    dma_addr_t addr,
 					    u64 offset,
-					    enum i915_cache_level level,
+					    unsigned int pat_index,
 					    u32 flags)
 {
 	u64 idx = offset >> GEN8_PTE_SHIFT;
 	}
 	vaddr = px_vaddr(pt);
-	vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags);
+	vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, pat_index, flags);
 }
 static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
 				       dma_addr_t addr,
 				       u64 offset,
-				       enum i915_cache_level level,
+				       unsigned int pat_index,
 				       u32 flags)
 {
 	if (flags & PTE_LM)
 		return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
-						       level, flags);
+						       pat_index, flags);
-	return gen8_ppgtt_insert_entry(vm, addr, offset, level, flags);
+	return gen8_ppgtt_insert_entry(vm, addr, offset, pat_index, flags);
 }
 static int gen8_init_scratch(struct i915_address_space *vm)
 		pte_flags |= PTE_LM;
 	vm->scratch[0]->encode =
-		gen8_pte_encode(px_dma(vm->scratch[0]),
+		vm->pte_encode(px_dma(vm->scratch[0]),
-				I915_CACHE_NONE, pte_flags);
+			       i915_gem_get_pat_index(vm->i915,
+						      I915_CACHE_NONE),
+			       pte_flags);
 	for (i = 1; i <= vm->top; i++) {
 		struct drm_i915_gem_object *obj;
 	 */
 	ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
-	ppgtt->vm.pte_encode = gen8_pte_encode;
+	if (GRAPHICS_VER(gt->i915) >= 12)
+		ppgtt->vm.pte_encode = gen12_pte_encode;
+	else
+		ppgtt->vm.pte_encode = gen8_pte_encode;
 	ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
 	ppgtt->vm.insert_entries = gen8_ppgtt_insert;

drivers/gpu/drm/i915/gt/gen8_ppgtt.h+1−2

 struct i915_address_space;
 struct intel_gt;
-enum i915_cache_level;
 struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
 				     unsigned long lmem_pt_obj_flags);
 u64 gen8_ggtt_pte_encode(dma_addr_t addr,
-			 enum i915_cache_level level,
+			 unsigned int pat_index,
 			 u32 flags);
 #endif

drivers/gpu/drm/i915/gt/intel_context.c+4−1

 	child->parallel.parent = parent;
 }
-u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
+u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
 {
 	u64 total, active;
+	if (ce->ops->update_stats)
+		ce->ops->update_stats(ce);
 	total = ce->stats.runtime.total;
 	if (ce->ops->flags & COPS_RUNTIME_CYCLES)
 		total *= ce->engine->gt->clock_period_ns;

drivers/gpu/drm/i915/gt/intel_context.h+4−4

@@ -97,7 +97,7 @@ void intel_context_bind_parent_child(struct intel_context *parent, · 96 unmodified lines
97		97
98	/**	98	/**
99	* intel_context_lock_pinned - Stablises the 'pinned' status of the HW context	99	* intel_context_lock_pinned - Stablises the 'pinned' status of the HW context
100	* @ce - the context	100	* @ce: the context
101	*	101	*
102	* Acquire a lock on the pinned status of the HW context, such that the context	102	* Acquire a lock on the pinned status of the HW context, such that the context
103	* can neither be bound to the GPU or unbound whilst the lock is held, i.e.	103	* can neither be bound to the GPU or unbound whilst the lock is held, i.e.
@@ -111,7 +111,7 @@ static inline int intel_context_lock_pinned(struct intel_context *ce) · 7 unmodified lines
111		111
112	/**	112	/**
113	* intel_context_is_pinned - Reports the 'pinned' status	113	* intel_context_is_pinned - Reports the 'pinned' status
114	* @ce - the context	114	* @ce: the context
115	*	115	*
116	* While in use by the GPU, the context, along with its ring and page	116	* While in use by the GPU, the context, along with its ring and page
117	* tables is pinned into memory and the GTT.	117	* tables is pinned into memory and the GTT.
@@ -133,7 +133,7 @@ static inline void intel_context_cancel_request(struct intel_context *ce, · 15 unmodified lines
133		133
134	/**	134	/**
135	* intel_context_unlock_pinned - Releases the earlier locking of 'pinned' status	135	* intel_context_unlock_pinned - Releases the earlier locking of 'pinned' status
136	* @ce - the context	136	* @ce: the context
137	*	137	*
138	* Releases the lock earlier acquired by intel_context_unlock_pinned().	138	* Releases the lock earlier acquired by intel_context_unlock_pinned().
139	*/	139	*/
@@ -375,7 +375,7 @@ intel_context_clear_nopreempt(struct intel_context *ce) · 235 unmodified lines
375	clear_bit(CONTEXT_NOPREEMPT, &ce->flags);	375	clear_bit(CONTEXT_NOPREEMPT, &ce->flags);
376	}	376	}
377		377
378	u64 intel_context_get_total_runtime_ns(const struct intel_context *ce);	378	u64 intel_context_get_total_runtime_ns(struct intel_context *ce);
379	u64 intel_context_get_avg_runtime_ns(struct intel_context *ce);	379	u64 intel_context_get_avg_runtime_ns(struct intel_context *ce);
380		380
381	static inline u64 intel_context_clock(void)	381	static inline u64 intel_context_clock(void)

drivers/gpu/drm/i915/gt/intel_context_types.h+2−0

@@ -58,6 +58,8 @@ struct intel_context_ops { · 57 unmodified lines
58		58
59	void (sched_disable)(struct intel_context ce);	59	void (sched_disable)(struct intel_context ce);
60		60
		61	void (update_stats)(struct intel_context ce);
		62
61	void (reset)(struct intel_context ce);	63	void (reset)(struct intel_context ce);
62	void (destroy)(struct kref kref);	64	void (destroy)(struct kref kref);
63		65

drivers/gpu/drm/i915/gt/intel_engine_cs.c+1−1

@@ -1515,7 +1515,7 @@ int intel_engines_init(struct intel_gt *gt) · 1514 unmodified lines
1515	}	1515	}
1516		1516
1517	/**	1517	/**
1518	* intel_engines_cleanup_common - cleans up the engine state created by	1518	* intel_engine_cleanup_common - cleans up the engine state created by
1519	* the common initiailizers.	1519	* the common initiailizers.
1520	* @engine: Engine to cleanup.	1520	* @engine: Engine to cleanup.
1521	*	1521	*

drivers/gpu/drm/i915/gt/intel_engine_types.h+1−0

@@ -289,6 +289,7 @@ struct intel_engine_execlists { · 288 unmodified lines
289	*/	289	*/
290	u8 csb_head;	290	u8 csb_head;
291		291
		292	/* private: selftest */
292	I915_SELFTEST_DECLARE(struct st_preempt_hang preempt_hang;)	293	I915_SELFTEST_DECLARE(struct st_preempt_hang preempt_hang;)
293	};	294	};
294		295

drivers/gpu/drm/i915/gt/intel_engine_user.c+1−1

@@ -117,7 +117,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) · 116 unmodified lines
117	disabled \|= (I915_SCHEDULER_CAP_ENABLED \|	117	disabled \|= (I915_SCHEDULER_CAP_ENABLED \|
118	I915_SCHEDULER_CAP_PRIORITY);	118	I915_SCHEDULER_CAP_PRIORITY);
119		119
120	if (intel_uc_uses_guc_submission(&to_gt(i915)->uc))	120	if (intel_uc_uses_guc_submission(&engine->gt->uc))
121	enabled \|= I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP;	121	enabled \|= I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP;
122		122
123	for (i = 0; i < ARRAY_SIZE(map); i++) {	123	for (i = 0; i < ARRAY_SIZE(map); i++) {

drivers/gpu/drm/i915/gt/intel_ggtt.c+59−25

 	}
 }
+static u64 mtl_ggtt_pte_encode(dma_addr_t addr,
+			       unsigned int pat_index,
+			       u32 flags)
+{
+	gen8_pte_t pte = addr | GEN8_PAGE_PRESENT;
+	WARN_ON_ONCE(addr & ~GEN12_GGTT_PTE_ADDR_MASK);
+	if (flags & PTE_LM)
+		pte |= GEN12_GGTT_PTE_LM;
+	if (pat_index & BIT(0))
+		pte |= MTL_GGTT_PTE_PAT0;
+	if (pat_index & BIT(1))
+		pte |= MTL_GGTT_PTE_PAT1;
+	return pte;
+}
 u64 gen8_ggtt_pte_encode(dma_addr_t addr,
-			 enum i915_cache_level level,
+			 unsigned int pat_index,
 			 u32 flags)
 {
 	gen8_pte_t pte = addr | GEN8_PAGE_PRESENT;
 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
 				  dma_addr_t addr,
 				  u64 offset,
-				  enum i915_cache_level level,
+				  unsigned int pat_index,
 				  u32 flags)
 {
 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 	gen8_pte_t __iomem *pte =
 		(gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
-	gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
+	gen8_set_pte(pte, ggtt->vm.pte_encode(addr, pat_index, flags));
 	ggtt->invalidate(ggtt);
 }
 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 				     struct i915_vma_resource *vma_res,
-				     enum i915_cache_level level,
+				     unsigned int pat_index,
 				     u32 flags)
 {
-	const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+	const gen8_pte_t pte_encode = ggtt->vm.pte_encode(0, pat_index, flags);
 	gen8_pte_t __iomem *gte;
 	gen8_pte_t __iomem *end;
 	struct sgt_iter iter;
 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
 				  dma_addr_t addr,
 				  u64 offset,
-				  enum i915_cache_level level,
+				  unsigned int pat_index,
 				  u32 flags)
 {
 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 	gen6_pte_t __iomem *pte =
 		(gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
-	iowrite32(vm->pte_encode(addr, level, flags), pte);
+	iowrite32(vm->pte_encode(addr, pat_index, flags), pte);
 	ggtt->invalidate(ggtt);
 }
  */
 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
 				     struct i915_vma_resource *vma_res,
-				     enum i915_cache_level level,
+				     unsigned int pat_index,
 				     u32 flags)
 {
 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 		iowrite32(vm->scratch[0]->encode, gte++);
 	end += (vma_res->node_size + vma_res->guard) / I915_GTT_PAGE_SIZE;
 	for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
-		iowrite32(vm->pte_encode(addr, level, flags), gte++);
+		iowrite32(vm->pte_encode(addr, pat_index, flags), gte++);
 	GEM_BUG_ON(gte > end);
 	/* Fill the allocated but "unused" space beyond the end of the buffer */
 	struct i915_address_space *vm;
 	dma_addr_t addr;
 	u64 offset;
-	enum i915_cache_level level;
+	unsigned int pat_index;
 };
 static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
 {
 	struct insert_page *arg = _arg;
-	gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
+	gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset,
+			      arg->pat_index, 0);
 	bxt_vtd_ggtt_wa(arg->vm);
 	return 0;
 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
 					  dma_addr_t addr,
 					  u64 offset,
-					  enum i915_cache_level level,
+					  unsigned int pat_index,
 					  u32 unused)
 {
-	struct insert_page arg = { vm, addr, offset, level };
+	struct insert_page arg = { vm, addr, offset, pat_index };
 	stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
 }
 struct insert_entries {
 	struct i915_address_space *vm;
 	struct i915_vma_resource *vma_res;
-	enum i915_cache_level level;
+	unsigned int pat_index;
 	u32 flags;
 };
 {
 	struct insert_entries *arg = _arg;
-	gen8_ggtt_insert_entries(arg->vm, arg->vma_res, arg->level, arg->flags);
+	gen8_ggtt_insert_entries(arg->vm, arg->vma_res,
+				 arg->pat_index, arg->flags);
 	bxt_vtd_ggtt_wa(arg->vm);
 	return 0;
 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
 					     struct i915_vma_resource *vma_res,
-					     enum i915_cache_level level,
+					     unsigned int pat_index,
 					     u32 flags)
 {
-	struct insert_entries arg = { vm, vma_res, level, flags };
+	struct insert_entries arg = { vm, vma_res, pat_index, flags };
 	stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
 }
 void intel_ggtt_bind_vma(struct i915_address_space *vm,
 			 struct i915_vm_pt_stash *stash,
 			 struct i915_vma_resource *vma_res,
-			 enum i915_cache_level cache_level,
+			 unsigned int pat_index,
 			 u32 flags)
 {
 	u32 pte_flags;
 	if (vma_res->bi.lmem)
 		pte_flags |= PTE_LM;
-	vm->insert_entries(vm, vma_res, cache_level, pte_flags);
+	vm->insert_entries(vm, vma_res, pat_index, pte_flags);
 	vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
 }
 static void aliasing_gtt_bind_vma(struct i915_address_space *vm,
 				  struct i915_vm_pt_stash *stash,
 				  struct i915_vma_resource *vma_res,
-				  enum i915_cache_level cache_level,
+				  unsigned int pat_index,
 				  u32 flags)
 {
 	u32 pte_flags;
 	if (flags & I915_VMA_LOCAL_BIND)
 		ppgtt_bind_vma(&i915_vm_to_ggtt(vm)->alias->vm,
-			       stash, vma_res, cache_level, flags);
+			       stash, vma_res, pat_index, flags);
 	if (flags & I915_VMA_GLOBAL_BIND)
-		vm->insert_entries(vm, vma_res, cache_level, pte_flags);
+		vm->insert_entries(vm, vma_res, pat_index, pte_flags);
 	vma_res->bound_flags |= flags;
 }
 	ggtt->vm.scratch[0]->encode =
 		ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),
-				    I915_CACHE_NONE, pte_flags);
+				    i915_gem_get_pat_index(i915,
+							   I915_CACHE_NONE),
+				    pte_flags);
 	return 0;
 }
 	ggtt->vm.vma_ops.bind_vma    = intel_ggtt_bind_vma;
 	ggtt->vm.vma_ops.unbind_vma  = intel_ggtt_unbind_vma;
-	ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+		ggtt->vm.pte_encode = mtl_ggtt_pte_encode;
+	else
+		ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
 	return ggtt_probe_common(ggtt, size);
 }
+/*
+ * For pre-gen8 platforms pat_index is the same as enum i915_cache_level,
+ * so these PTE encode functions are left with using cache_level.
+ * See translation table LEGACY_CACHELEVEL.
+ */
 static u64 snb_pte_encode(dma_addr_t addr,
 			  enum i915_cache_level level,
 			  u32 flags)
 		 */
 		vma->resource->bound_flags = 0;
 		vma->ops->bind_vma(vm, NULL, vma->resource,
-				   obj ? obj->cache_level : 0,
+				   obj ? obj->pat_index :
+					 i915_gem_get_pat_index(vm->i915,
+								I915_CACHE_NONE),
 				   was_bound);
 		if (obj) { /* only used during resume => exclusive access */

drivers/gpu/drm/i915/gt/intel_gt_irq.c+21−4

 #include "intel_uncore.h"
 #include "intel_rps.h"
 #include "pxp/intel_pxp_irq.h"
+#include "uc/intel_gsc_proxy.h"
 static void guc_irq_handler(struct intel_guc *guc, u16 iir)
 {
 	if (instance == OTHER_GSC_INSTANCE)
 		return intel_gsc_irq_handler(gt, iir);
+	if (instance == OTHER_GSC_HECI_2_INSTANCE)
+		return intel_gsc_proxy_irq_handler(&gt->uc.gsc, iir);
 	WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
 		  instance, iir);
 }
 	case VIDEO_ENHANCEMENT_CLASS:
 		return media_gt;
 	case OTHER_CLASS:
-		if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
+		if (instance == OTHER_GSC_HECI_2_INSTANCE)
+			return media_gt;
+		if ((instance == OTHER_GSC_INSTANCE || instance == OTHER_KCR_INSTANCE) &&
+		    HAS_ENGINE(media_gt, GSC0))
 			return media_gt;
 		fallthrough;
 	default:
 	u32 irqs = GT_RENDER_USER_INTERRUPT;
 	u32 guc_mask = intel_uc_wants_guc(&gt->uc) ? GUC_INTR_GUC2HOST : 0;
 	u32 gsc_mask = 0;
+	u32 heci_mask = 0;
 	u32 dmask;
 	u32 smask;
 	dmask = irqs << 16 | irqs;
 	smask = irqs << 16;
-	if (HAS_ENGINE(gt, GSC0))
+	if (HAS_ENGINE(gt, GSC0)) {
+		/*
+		 * the heci2 interrupt is enabled via the same register as the
+		 * GSC interrupt, but it has its own mask register.
+		 */
 		gsc_mask = irqs;
-	else if (HAS_HECI_GSC(gt->i915))
+		heci_mask = GSC_IRQ_INTF(1); /* HECI2 IRQ for SW Proxy*/
+	} else if (HAS_HECI_GSC(gt->i915)) {
 		gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
+	}
 	BUILD_BUG_ON(irqs & 0xffff0000);
 	if (CCS_MASK(gt))
 		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
 	if (gsc_mask)
-		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask);
+		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask | heci_mask);
 	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
 	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
 		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
 	if (gsc_mask)
 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
+	if (heci_mask)
+		intel_uncore_write(uncore, GEN12_HECI2_RSVD_INTR_MASK,
+				   ~REG_FIELD_PREP(ENGINE1_MASK, heci_mask));
 	if (guc_mask) {
 		/* the enable bit is common for both GTs but the masks are separate */

drivers/gpu/drm/i915/gt/intel_gt_pm.c+2−2

@@ -87,7 +87,7 @@ static int __gt_unpark(struct intel_wakeref *wf) · 86 unmodified lines
87		87
88	intel_rc6_unpark(&gt->rc6);	88	intel_rc6_unpark(&gt->rc6);
89	intel_rps_unpark(&gt->rps);	89	intel_rps_unpark(&gt->rps);
90	i915_pmu_gt_unparked(i915);	90	i915_pmu_gt_unparked(gt);
91	intel_guc_busyness_unpark(gt);	91	intel_guc_busyness_unpark(gt);
92		92
93	intel_gt_unpark_requests(gt);	93	intel_gt_unpark_requests(gt);
@@ -109,7 +109,7 @@ static int __gt_park(struct intel_wakeref *wf) · 15 unmodified lines
109		109
110	intel_guc_busyness_park(gt);	110	intel_guc_busyness_park(gt);
111	i915_vma_parked(gt);	111	i915_vma_parked(gt);
112	i915_pmu_gt_parked(i915);	112	i915_pmu_gt_parked(gt);
113	intel_rps_park(&gt->rps);	113	intel_rps_park(&gt->rps);
114	intel_rc6_park(&gt->rc6);	114	intel_rc6_park(&gt->rc6);
115		115

drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c+4−1

 {
 	struct intel_gt *gt = data;
-	return HAS_RPS(gt->i915);
+	if (intel_guc_slpc_is_used(&gt->uc.guc))
+		return false;
+	else
+		return HAS_RPS(gt->i915);
 }
 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);

drivers/gpu/drm/i915/gt/intel_gt_regs.h+13−1

 #define GEN7_TLB_RD_ADDR			_MMIO(0x4700)
 #define GEN12_PAT_INDEX(index)			_MMIO(0x4800 + (index) * 4)
-#define XEHP_PAT_INDEX(index)			MCR_REG(0x4800 + (index) * 4)
+#define _PAT_INDEX(index)			_PICK_EVEN_2RANGES(index, 8, \
+								   0x4800, 0x4804, \
+								   0x4848, 0x484c)
+#define XEHP_PAT_INDEX(index)			MCR_REG(_PAT_INDEX(index))
+#define XELPMP_PAT_INDEX(index)			_MMIO(_PAT_INDEX(index))
 #define XEHP_TILE0_ADDR_RANGE			MCR_REG(0x4900)
 #define   XEHP_TILE_LMEM_RANGE_SHIFT		8
 #define GEN8_RC6_CTX_INFO			_MMIO(0x8504)
+#define GEN12_SQCNT1				_MMIO(0x8718)
+#define   GEN12_SQCNT1_PMON_ENABLE		REG_BIT(30)
+#define   GEN12_SQCNT1_OABPC			REG_BIT(29)
+#define   GEN12_STRICT_RAR_ENABLE		REG_BIT(23)
 #define XEHP_SQCM				MCR_REG(0x8724)
 #define   EN_32B_ACCESS				REG_BIT(30)
 #define GEN11_GT_INTR_DW(x)			_MMIO(0x190018 + ((x) * 4))
 #define   GEN11_CSME				(31)
+#define   GEN12_HECI_2				(30)
 #define   GEN11_GUNIT				(28)
 #define   GEN11_GUC				(25)
 #define   MTL_MGUC				(24)
 /* irq instances for OTHER_CLASS */
 #define   OTHER_GUC_INSTANCE			0
 #define   OTHER_GTPM_INSTANCE			1
+#define   OTHER_GSC_HECI_2_INSTANCE		3
 #define   OTHER_KCR_INSTANCE			4
 #define   OTHER_GSC_INSTANCE			6
 #define   OTHER_MEDIA_GUC_INSTANCE		16
 #define GEN12_VCS6_VCS7_INTR_MASK		_MMIO(0x1900b4)
 #define GEN11_VECS0_VECS1_INTR_MASK		_MMIO(0x1900d0)
 #define GEN12_VECS2_VECS3_INTR_MASK		_MMIO(0x1900d4)
+#define GEN12_HECI2_RSVD_INTR_MASK		_MMIO(0x1900e4)
 #define GEN11_GUC_SG_INTR_MASK			_MMIO(0x1900e8)
 #define MTL_GUC_MGUC_INTR_MASK			_MMIO(0x1900e8) /* MTL+ */
 #define GEN11_GPM_WGBOXPERF_INTR_MASK		_MMIO(0x1900ec)

drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c+35−0

@@ -451,6 +451,33 @@ static ssize_t punit_req_freq_mhz_show(struct kobject *kobj, · 450 unmodified lines
451	return sysfs_emit(buff, "%u\n", preq);	451	return sysfs_emit(buff, "%u\n", preq);
452	}	452	}
453		453
		454	static ssize_t slpc_ignore_eff_freq_show(struct kobject *kobj,
		455	struct kobj_attribute *attr,
		456	char *buff)
		457	{
		458	struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
		459	struct intel_guc_slpc *slpc = &gt->uc.guc.slpc;
		460
		461	return sysfs_emit(buff, "%u\n", slpc->ignore_eff_freq);
		462	}
		463
		464	static ssize_t slpc_ignore_eff_freq_store(struct kobject *kobj,
		465	struct kobj_attribute *attr,
		466	const char *buff, size_t count)
		467	{
		468	struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
		469	struct intel_guc_slpc *slpc = &gt->uc.guc.slpc;
		470	int err;
		471	u32 val;
		472
		473	err = kstrtou32(buff, 0, &val);
		474	if (err)
		475	return err;
		476
		477	err = intel_guc_slpc_set_ignore_eff_freq(slpc, val);
		478	return err ?: count;
		479	}
		480
454	struct intel_gt_bool_throttle_attr {	481	struct intel_gt_bool_throttle_attr {
455	struct attribute attr;	482	struct attribute attr;
456	ssize_t (show)(struct kobject kobj, struct kobj_attribute *attr,	483	ssize_t (show)(struct kobject kobj, struct kobj_attribute *attr,
@@ -663,6 +690,8 @@ static struct kobj_attribute attr_media_freq_factor_scale = · 206 unmodified lines
663	INTEL_GT_ATTR_RO(media_RP0_freq_mhz);	690	INTEL_GT_ATTR_RO(media_RP0_freq_mhz);
664	INTEL_GT_ATTR_RO(media_RPn_freq_mhz);	691	INTEL_GT_ATTR_RO(media_RPn_freq_mhz);
665		692
		693	INTEL_GT_ATTR_RW(slpc_ignore_eff_freq);
		694
666	static const struct attribute *media_perf_power_attrs[] = {	695	static const struct attribute *media_perf_power_attrs[] = {
667	&attr_media_freq_factor.attr,	696	&attr_media_freq_factor.attr,
668	&attr_media_freq_factor_scale.attr,	697	&attr_media_freq_factor_scale.attr,
@@ -744,6 +773,12 @@ void intel_gt_sysfs_pm_init(struct intel_gt gt, struct kobject kobj) · 75 unmodified lines
744	if (ret)	773	if (ret)
745	gt_warn(gt, "failed to create punit_req_freq_mhz sysfs (%pe)", ERR_PTR(ret));	774	gt_warn(gt, "failed to create punit_req_freq_mhz sysfs (%pe)", ERR_PTR(ret));
746		775
		776	if (intel_uc_uses_guc_slpc(&gt->uc)) {
		777	ret = sysfs_create_file(kobj, &attr_slpc_ignore_eff_freq.attr);
		778	if (ret)
		779	gt_warn(gt, "failed to create ignore_eff_freq sysfs (%pe)", ERR_PTR(ret));
		780	}
		781
747	if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {	782	if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
748	ret = sysfs_create_files(kobj, throttle_reason_attrs);	783	ret = sysfs_create_files(kobj, throttle_reason_attrs);
749	if (ret)	784	if (ret)

drivers/gpu/drm/i915/gt/intel_gtt.c+46−1

@@ -468,6 +468,44 @@ void gtt_write_workarounds(struct intel_gt *gt) · 467 unmodified lines
468	}	468	}
469	}	469	}
470		470
		471	static void xelpmp_setup_private_ppat(struct intel_uncore *uncore)
		472	{
		473	intel_uncore_write(uncore, XELPMP_PAT_INDEX(0),
		474	MTL_PPAT_L4_0_WB);
		475	intel_uncore_write(uncore, XELPMP_PAT_INDEX(1),
		476	MTL_PPAT_L4_1_WT);
		477	intel_uncore_write(uncore, XELPMP_PAT_INDEX(2),
		478	MTL_PPAT_L4_3_UC);
		479	intel_uncore_write(uncore, XELPMP_PAT_INDEX(3),
		480	MTL_PPAT_L4_0_WB \| MTL_2_COH_1W);
		481	intel_uncore_write(uncore, XELPMP_PAT_INDEX(4),
		482	MTL_PPAT_L4_0_WB \| MTL_3_COH_2W);
		483
		484	/*
		485	* Remaining PAT entries are left at the hardware-default
		486	* fully-cached setting
		487	*/
		488	}
		489
		490	static void xelpg_setup_private_ppat(struct intel_gt *gt)
		491	{
		492	intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0),
		493	MTL_PPAT_L4_0_WB);
		494	intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1),
		495	MTL_PPAT_L4_1_WT);
		496	intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2),
		497	MTL_PPAT_L4_3_UC);
		498	intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3),
		499	MTL_PPAT_L4_0_WB \| MTL_2_COH_1W);
		500	intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4),
		501	MTL_PPAT_L4_0_WB \| MTL_3_COH_2W);
		502
		503	/*
		504	* Remaining PAT entries are left at the hardware-default
		505	* fully-cached setting
		506	*/
		507	}
		508
471	static void tgl_setup_private_ppat(struct intel_uncore *uncore)	509	static void tgl_setup_private_ppat(struct intel_uncore *uncore)
472	{	510	{
473	/* TGL doesn't support LLC or AGE settings */	511	/* TGL doesn't support LLC or AGE settings */
@@ -603,7 +641,14 @@ void setup_private_pat(struct intel_gt *gt) · 129 unmodified lines
603		641
604	GEM_BUG_ON(GRAPHICS_VER(i915) < 8);	642	GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
605		643
606	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))	644	if (gt->type == GT_MEDIA) {
		645	xelpmp_setup_private_ppat(gt->uncore);
		646	return;
		647	}
		648
		649	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
		650	xelpg_setup_private_ppat(gt);
		651	else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
607	xehp_setup_private_ppat(gt);	652	xehp_setup_private_ppat(gt);
608	else if (GRAPHICS_VER(i915) >= 12)	653	else if (GRAPHICS_VER(i915) >= 12)
609	tgl_setup_private_ppat(uncore);	654	tgl_setup_private_ppat(uncore);

drivers/gpu/drm/i915/gt/intel_gtt.h+25−11

 #define BYT_PTE_SNOOPED_BY_CPU_CACHES	REG_BIT(2)
 #define BYT_PTE_WRITEABLE		REG_BIT(1)
+#define MTL_PPGTT_PTE_PAT3	BIT_ULL(62)
 #define GEN12_PPGTT_PTE_LM	BIT_ULL(11)
+#define GEN12_PPGTT_PTE_PAT2	BIT_ULL(7)
+#define GEN12_PPGTT_PTE_PAT1	BIT_ULL(4)
+#define GEN12_PPGTT_PTE_PAT0	BIT_ULL(3)
-#define GEN12_GGTT_PTE_LM	BIT_ULL(1)
+#define GEN12_GGTT_PTE_LM		BIT_ULL(1)
+#define MTL_GGTT_PTE_PAT0		BIT_ULL(52)
+#define MTL_GGTT_PTE_PAT1		BIT_ULL(53)
+#define GEN12_GGTT_PTE_ADDR_MASK	GENMASK_ULL(45, 12)
+#define MTL_GGTT_PTE_PAT_MASK		GENMASK_ULL(53, 52)
 #define GEN12_PDE_64K BIT(6)
 #define GEN12_PTE_PS64 BIT(8)
 #define GEN8_PDE_IPS_64K BIT(11)
 #define GEN8_PDE_PS_2M   BIT(7)
-enum i915_cache_level;
+#define MTL_PPAT_L4_CACHE_POLICY_MASK	REG_GENMASK(3, 2)
+#define MTL_PAT_INDEX_COH_MODE_MASK	REG_GENMASK(1, 0)
+#define MTL_PPAT_L4_3_UC	REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3)
+#define MTL_PPAT_L4_1_WT	REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1)
+#define MTL_PPAT_L4_0_WB	REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0)
+#define MTL_3_COH_2W	REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3)
+#define MTL_2_COH_1W	REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2)
 struct drm_i915_gem_object;
 struct i915_fence_reg;
 	void (*bind_vma)(struct i915_address_space *vm,
 			 struct i915_vm_pt_stash *stash,
 			 struct i915_vma_resource *vma_res,
-			 enum i915_cache_level cache_level,
+			 unsigned int pat_index,
 			 u32 flags);
 	/*
 	 * Unmap an object from an address space. This usually consists of
 		(*alloc_scratch_dma)(struct i915_address_space *vm, int sz);
 	u64 (*pte_encode)(dma_addr_t addr,
-			  enum i915_cache_level level,
+			  unsigned int pat_index,
 			  u32 flags); /* Create a valid PTE */
 #define PTE_READ_ONLY	BIT(0)
 #define PTE_LM		BIT(1)
 	void (*insert_page)(struct i915_address_space *vm,
 			    dma_addr_t addr,
 			    u64 offset,
-			    enum i915_cache_level cache_level,
+			    unsigned int pat_index,
 			    u32 flags);
 	void (*insert_entries)(struct i915_address_space *vm,
 			       struct i915_vma_resource *vma_res,
-			       enum i915_cache_level cache_level,
+			       unsigned int pat_index,
 			       u32 flags);
 	void (*raw_insert_page)(struct i915_address_space *vm,
 				dma_addr_t addr,
 				u64 offset,
-				enum i915_cache_level cache_level,
+				unsigned int pat_index,
 				u32 flags);
 	void (*raw_insert_entries)(struct i915_address_space *vm,
 				   struct i915_vma_resource *vma_res,
-				   enum i915_cache_level cache_level,
+				   unsigned int pat_index,
 				   u32 flags);
 	void (*cleanup)(struct i915_address_space *vm);
 /**
  * i915_vm_resv_put - Release a reference on the vm's reservation lock
- * @resv: Pointer to a reservation lock obtained from i915_vm_resv_get()
+ * @vm: The vm whose reservation lock reference we want to release
  */
 static inline void i915_vm_resv_put(struct i915_address_space *vm)
 {
 void intel_ggtt_bind_vma(struct i915_address_space *vm,
 			 struct i915_vm_pt_stash *stash,
 			 struct i915_vma_resource *vma_res,
-			 enum i915_cache_level cache_level,
+			 unsigned int pat_index,
 			 u32 flags);
 void intel_ggtt_unbind_vma(struct i915_address_space *vm,
 			   struct i915_vma_resource *vma_res);
 void ppgtt_bind_vma(struct i915_address_space *vm,
 		    struct i915_vm_pt_stash *stash,
 		    struct i915_vma_resource *vma_res,
-		    enum i915_cache_level cache_level,
+		    unsigned int pat_index,
 		    u32 flags);
 void ppgtt_unbind_vma(struct i915_address_space *vm,
 		      struct i915_vma_resource *vma_res);

drivers/gpu/drm/i915/gt/intel_lrc.c+3−1

@@ -1370,7 +1370,9 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context ce, u32 cs) · 1369 unmodified lines
1370	cs, GEN12_GFX_CCS_AUX_NV);	1370	cs, GEN12_GFX_CCS_AUX_NV);
1371		1371
1372	/* Wa_16014892111 */	1372	/* Wa_16014892111 */
1373	if (IS_DG2(ce->engine->i915))	1373	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) \|\|
		1374	IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) \|\|
		1375	IS_DG2(ce->engine->i915))
1374	cs = dg2_emit_draw_watermark_setting(cs);	1376	cs = dg2_emit_draw_watermark_setting(cs);
1375		1377
1376	return cs;	1378	return cs;

drivers/gpu/drm/i915/gt/intel_migrate.c+28−23

 	 * Insert a dummy PTE into every PT that will map to LMEM to ensure
 	 * we have a correctly setup PDE structure for later use.
 	 */
-	vm->insert_page(vm, 0, d->offset, I915_CACHE_NONE, PTE_LM);
+	vm->insert_page(vm, 0, d->offset,
+			i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE),
+			PTE_LM);
 	GEM_BUG_ON(!pt->is_compact);
 	d->offset += SZ_2M;
 }
 	 * alignment is 64K underneath for the pt, and we are careful
 	 * not to access the space in the void.
 	 */
-	vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE, PTE_LM);
+	vm->insert_page(vm, px_dma(pt), d->offset,
+			i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE),
+			PTE_LM);
 	d->offset += SZ_64K;
 }
 {
 	struct insert_pte_data *d = data;
-	vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE,
+	vm->insert_page(vm, px_dma(pt), d->offset,
+			i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE),
 			i915_gem_object_is_lmem(pt->base) ? PTE_LM : 0);
 	d->offset += PAGE_SIZE;
 }
 static int emit_pte(struct i915_request *rq,
 		    struct sgt_dma *it,
-		    enum i915_cache_level cache_level,
+		    unsigned int pat_index,
 		    bool is_lmem,
 		    u64 offset,
 		    int length)
 {
 	bool has_64K_pages = HAS_64K_PAGES(rq->engine->i915);
-	const u64 encode = rq->context->vm->pte_encode(0, cache_level,
+	const u64 encode = rq->context->vm->pte_encode(0, pat_index,
 						       is_lmem ? PTE_LM : 0);
 	struct intel_ring *ring = rq->ring;
 	int pkt, dword_length;
 intel_context_migrate_copy(struct intel_context *ce,
 			   const struct i915_deps *deps,
 			   struct scatterlist *src,
-			   enum i915_cache_level src_cache_level,
+			   unsigned int src_pat_index,
 			   bool src_is_lmem,
 			   struct scatterlist *dst,
-			   enum i915_cache_level dst_cache_level,
+			   unsigned int dst_pat_index,
 			   bool dst_is_lmem,
 			   struct i915_request **out)
 {
 	struct sgt_dma it_src = sg_sgt(src), it_dst = sg_sgt(dst), it_ccs;
 	struct drm_i915_private *i915 = ce->engine->i915;
 	u64 ccs_bytes_to_cpy = 0, bytes_to_cpy;
-	enum i915_cache_level ccs_cache_level;
+	unsigned int ccs_pat_index;
 	u32 src_offset, dst_offset;
 	u8 src_access, dst_access;
 	struct i915_request *rq;
 		dst_sz = scatter_list_length(dst);
 		if (src_is_lmem) {
 			it_ccs = it_dst;
-			ccs_cache_level = dst_cache_level;
+			ccs_pat_index = dst_pat_index;
 			ccs_is_src = false;
 		} else if (dst_is_lmem) {
 			bytes_to_cpy = dst_sz;
 			it_ccs = it_src;
-			ccs_cache_level = src_cache_level;
+			ccs_pat_index = src_pat_index;
 			ccs_is_src = true;
 		}
 		src_sz = calculate_chunk_sz(i915, src_is_lmem,
 					    bytes_to_cpy, ccs_bytes_to_cpy);
-		len = emit_pte(rq, &it_src, src_cache_level, src_is_lmem,
+		len = emit_pte(rq, &it_src, src_pat_index, src_is_lmem,
 			       src_offset, src_sz);
 		if (!len) {
 			err = -EINVAL;
 			goto out_rq;
 		}
-		err = emit_pte(rq, &it_dst, dst_cache_level, dst_is_lmem,
+		err = emit_pte(rq, &it_dst, dst_pat_index, dst_is_lmem,
 			       dst_offset, len);
 		if (err < 0)
 			goto out_rq;
 				goto out_rq;
 			ccs_sz = GET_CCS_BYTES(i915, len);
-			err = emit_pte(rq, &it_ccs, ccs_cache_level, false,
+			err = emit_pte(rq, &it_ccs, ccs_pat_index, false,
 				       ccs_is_src ? src_offset : dst_offset,
 				       ccs_sz);
 			if (err < 0)
 	GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
-	if (HAS_FLAT_CCS(i915) && ver >= 12)
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
 		ring_sz = XY_FAST_COLOR_BLT_DW;
 	else if (ver >= 8)
 		ring_sz = 8;
 	if (IS_ERR(cs))
 		return PTR_ERR(cs);
-	if (HAS_FLAT_CCS(i915) && ver >= 12) {
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
 		*cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 |
 			(XY_FAST_COLOR_BLT_DW - 2);
 		*cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) |
 intel_context_migrate_clear(struct intel_context *ce,
 			    const struct i915_deps *deps,
 			    struct scatterlist *sg,
-			    enum i915_cache_level cache_level,
+			    unsigned int pat_index,
 			    bool is_lmem,
 			    u32 value,
 			    struct i915_request **out)
 		if (err)
 			goto out_rq;
-		len = emit_pte(rq, &it, cache_level, is_lmem, offset, CHUNK_SZ);
+		len = emit_pte(rq, &it, pat_index, is_lmem, offset, CHUNK_SZ);
 		if (len <= 0) {
 			err = len;
 			goto out_rq;
 		       struct i915_gem_ww_ctx *ww,
 		       const struct i915_deps *deps,
 		       struct scatterlist *src,
-		       enum i915_cache_level src_cache_level,
+		       unsigned int src_pat_index,
 		       bool src_is_lmem,
 		       struct scatterlist *dst,
-		       enum i915_cache_level dst_cache_level,
+		       unsigned int dst_pat_index,
 		       bool dst_is_lmem,
 		       struct i915_request **out)
 {
 		goto out;
 	err = intel_context_migrate_copy(ce, deps,
-					 src, src_cache_level, src_is_lmem,
+					 src, src_pat_index, src_is_lmem,
-					 dst, dst_cache_level, dst_is_lmem,
+					 dst, dst_pat_index, dst_is_lmem,
 					 out);
 	intel_context_unpin(ce);
 		    struct i915_gem_ww_ctx *ww,
 		    const struct i915_deps *deps,
 		    struct scatterlist *sg,
-		    enum i915_cache_level cache_level,
+		    unsigned int pat_index,
 		    bool is_lmem,
 		    u32 value,
 		    struct i915_request **out)
 	if (err)
 		goto out;
-	err = intel_context_migrate_clear(ce, deps, sg, cache_level,
+	err = intel_context_migrate_clear(ce, deps, sg, pat_index,
 					  is_lmem, value, out);
 	intel_context_unpin(ce);

drivers/gpu/drm/i915/gt/intel_migrate.h+6−7

 struct i915_gem_ww_ctx;
 struct intel_gt;
 struct scatterlist;
-enum i915_cache_level;
 int intel_migrate_init(struct intel_migrate *m, struct intel_gt *gt);
 		       struct i915_gem_ww_ctx *ww,
 		       const struct i915_deps *deps,
 		       struct scatterlist *src,
-		       enum i915_cache_level src_cache_level,
+		       unsigned int src_pat_index,
 		       bool src_is_lmem,
 		       struct scatterlist *dst,
-		       enum i915_cache_level dst_cache_level,
+		       unsigned int dst_pat_index,
 		       bool dst_is_lmem,
 		       struct i915_request **out);
 int intel_context_migrate_copy(struct intel_context *ce,
 			       const struct i915_deps *deps,
 			       struct scatterlist *src,
-			       enum i915_cache_level src_cache_level,
+			       unsigned int src_pat_index,
 			       bool src_is_lmem,
 			       struct scatterlist *dst,
-			       enum i915_cache_level dst_cache_level,
+			       unsigned int dst_pat_index,
 			       bool dst_is_lmem,
 			       struct i915_request **out);
 		    struct i915_gem_ww_ctx *ww,
 		    const struct i915_deps *deps,
 		    struct scatterlist *sg,
-		    enum i915_cache_level cache_level,
+		    unsigned int pat_index,
 		    bool is_lmem,
 		    u32 value,
 		    struct i915_request **out);
 intel_context_migrate_clear(struct intel_context *ce,
 			    const struct i915_deps *deps,
 			    struct scatterlist *sg,
-			    enum i915_cache_level cache_level,
+			    unsigned int pat_index,
 			    bool is_lmem,
 			    u32 value,
 			    struct i915_request **out);

drivers/gpu/drm/i915/gt/intel_mocs.c+69−1

@@ -40,6 +40,10 @@ struct drm_i915_mocs_table { · 39 unmodified lines
40	#define LE_COS(value) ((value) << 15)	40	#define LE_COS(value) ((value) << 15)
41	#define LE_SSE(value) ((value) << 17)	41	#define LE_SSE(value) ((value) << 17)
42		42
		43	/* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */
		44	#define _L4_CACHEABILITY(value) ((value) << 2)
		45	#define IG_PAT(value) ((value) << 8)
		46
43	/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */	47	/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
44	#define L3_ESC(value) ((value) << 0)	48	#define L3_ESC(value) ((value) << 0)
45	#define L3_SCC(value) ((value) << 1)	49	#define L3_SCC(value) ((value) << 1)
@@ -50,6 +54,7 @@ struct drm_i915_mocs_table { · 4 unmodified lines
50	/* Helper defines */	54	/* Helper defines */
51	#define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */	55	#define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
52	#define PVC_NUM_MOCS_ENTRIES 3	56	#define PVC_NUM_MOCS_ENTRIES 3
		57	#define MTL_NUM_MOCS_ENTRIES 16
53		58
54	/* (e)LLC caching options */	59	/* (e)LLC caching options */
55	/*	60	/*
@@ -73,6 +78,12 @@ struct drm_i915_mocs_table { · 17 unmodified lines
73	#define L3_2_RESERVED _L3_CACHEABILITY(2)	78	#define L3_2_RESERVED _L3_CACHEABILITY(2)
74	#define L3_3_WB _L3_CACHEABILITY(3)	79	#define L3_3_WB _L3_CACHEABILITY(3)
75		80
		81	/* L4 caching options */
		82	#define L4_0_WB _L4_CACHEABILITY(0)
		83	#define L4_1_WT _L4_CACHEABILITY(1)
		84	#define L4_2_RESERVED _L4_CACHEABILITY(2)
		85	#define L4_3_UC _L4_CACHEABILITY(3)
		86
76	#define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \	87	#define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
77	[__idx] = { \	88	[__idx] = { \
78	.control_value = __control_value, \	89	.control_value = __control_value, \
@@ -416,6 +427,57 @@ static const struct drm_i915_mocs_entry pvc_mocs_table[] = { · 337 unmodified lines
416	MOCS_ENTRY(2, 0, L3_3_WB),	427	MOCS_ENTRY(2, 0, L3_3_WB),
417	};	428	};
418		429
		430	static const struct drm_i915_mocs_entry mtl_mocs_table[] = {
		431	/* Error - Reserved for Non-Use */
		432	MOCS_ENTRY(0,
		433	IG_PAT(0),
		434	L3_LKUP(1) \| L3_3_WB),
		435	/* Cached - L3 + L4 */
		436	MOCS_ENTRY(1,
		437	IG_PAT(1),
		438	L3_LKUP(1) \| L3_3_WB),
		439	/* L4 - GO:L3 */
		440	MOCS_ENTRY(2,
		441	IG_PAT(1),
		442	L3_LKUP(1) \| L3_1_UC),
		443	/* Uncached - GO:L3 */
		444	MOCS_ENTRY(3,
		445	IG_PAT(1) \| L4_3_UC,
		446	L3_LKUP(1) \| L3_1_UC),
		447	/* L4 - GO:Mem */
		448	MOCS_ENTRY(4,
		449	IG_PAT(1),
		450	L3_LKUP(1) \| L3_GLBGO(1) \| L3_1_UC),
		451	/* Uncached - GO:Mem */
		452	MOCS_ENTRY(5,
		453	IG_PAT(1) \| L4_3_UC,
		454	L3_LKUP(1) \| L3_GLBGO(1) \| L3_1_UC),
		455	/* L4 - L3:NoLKUP; GO:L3 */
		456	MOCS_ENTRY(6,
		457	IG_PAT(1),
		458	L3_1_UC),
		459	/* Uncached - L3:NoLKUP; GO:L3 */
		460	MOCS_ENTRY(7,
		461	IG_PAT(1) \| L4_3_UC,
		462	L3_1_UC),
		463	/* L4 - L3:NoLKUP; GO:Mem */
		464	MOCS_ENTRY(8,
		465	IG_PAT(1),
		466	L3_GLBGO(1) \| L3_1_UC),
		467	/* Uncached - L3:NoLKUP; GO:Mem */
		468	MOCS_ENTRY(9,
		469	IG_PAT(1) \| L4_3_UC,
		470	L3_GLBGO(1) \| L3_1_UC),
		471	/* Display - L3; L4:WT */
		472	MOCS_ENTRY(14,
		473	IG_PAT(1) \| L4_1_WT,
		474	L3_LKUP(1) \| L3_3_WB),
		475	/* CCS - Non-Displayable */
		476	MOCS_ENTRY(15,
		477	IG_PAT(1),
		478	L3_GLBGO(1) \| L3_1_UC),
		479	};
		480
419	enum {	481	enum {
420	HAS_GLOBAL_MOCS = BIT(0),	482	HAS_GLOBAL_MOCS = BIT(0),
421	HAS_ENGINE_MOCS = BIT(1),	483	HAS_ENGINE_MOCS = BIT(1),
@@ -445,7 +507,13 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, · 23 unmodified lines
445	memset(table, 0, sizeof(struct drm_i915_mocs_table));	507	memset(table, 0, sizeof(struct drm_i915_mocs_table));
446		508
447	table->unused_entries_index = I915_MOCS_PTE;	509	table->unused_entries_index = I915_MOCS_PTE;
448	if (IS_PONTEVECCHIO(i915)) {	510	if (IS_METEORLAKE(i915)) {
		511	table->size = ARRAY_SIZE(mtl_mocs_table);
		512	table->table = mtl_mocs_table;
		513	table->n_entries = MTL_NUM_MOCS_ENTRIES;
		514	table->uc_index = 9;
		515	table->unused_entries_index = 1;
		516	} else if (IS_PONTEVECCHIO(i915)) {
449	table->size = ARRAY_SIZE(pvc_mocs_table);	517	table->size = ARRAY_SIZE(pvc_mocs_table);
450	table->table = pvc_mocs_table;	518	table->table = pvc_mocs_table;
451	table->n_entries = PVC_NUM_MOCS_ENTRIES;	519	table->n_entries = PVC_NUM_MOCS_ENTRIES;

drivers/gpu/drm/i915/gt/intel_ppgtt.c+2−2

@@ -181,7 +181,7 @@ struct i915_ppgtt i915_ppgtt_create(struct intel_gt gt, · 180 unmodified lines
181	void ppgtt_bind_vma(struct i915_address_space *vm,	181	void ppgtt_bind_vma(struct i915_address_space *vm,
182	struct i915_vm_pt_stash *stash,	182	struct i915_vm_pt_stash *stash,
183	struct i915_vma_resource *vma_res,	183	struct i915_vma_resource *vma_res,
184	enum i915_cache_level cache_level,	184	unsigned int pat_index,
185	u32 flags)	185	u32 flags)
186	{	186	{
187	u32 pte_flags;	187	u32 pte_flags;
@@ -199,7 +199,7 @@ void ppgtt_bind_vma(struct i915_address_space *vm, · 11 unmodified lines
199	if (vma_res->bi.lmem)	199	if (vma_res->bi.lmem)
200	pte_flags \|= PTE_LM;	200	pte_flags \|= PTE_LM;
201		201
202	vm->insert_entries(vm, vma_res, cache_level, pte_flags);	202	vm->insert_entries(vm, vma_res, pat_index, pte_flags);
203	wmb();	203	wmb();
204	}	204	}
205		205

drivers/gpu/drm/i915/gt/intel_rc6.c+84−83

@@ -53,11 +53,6 @@ static struct drm_i915_private rc6_to_i915(struct intel_rc6 rc) · 52 unmodified lines
53	return rc6_to_gt(rc)->i915;	53	return rc6_to_gt(rc)->i915;
54	}	54	}
55		55
56	static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
57	{
58	intel_uncore_write_fw(uncore, reg, val);
59	}
60
61	static void gen11_rc6_enable(struct intel_rc6 *rc6)	56	static void gen11_rc6_enable(struct intel_rc6 *rc6)
62	{	57	{
63	struct intel_gt *gt = rc6_to_gt(rc6);	58	struct intel_gt *gt = rc6_to_gt(rc6);
@@ -72,19 +67,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) · 8 unmodified lines
72	*/	67	*/
73	if (!intel_uc_uses_guc_rc(&gt->uc)) {	68	if (!intel_uc_uses_guc_rc(&gt->uc)) {
74	/* 2b: Program RC6 thresholds.*/	69	/* 2b: Program RC6 thresholds.*/
75	set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 \| 85);	70	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 \| 85);
76	set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);	71	intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
77		72
78	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */	73	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
79	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */	74	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
80	for_each_engine(engine, rc6_to_gt(rc6), id)	75	for_each_engine(engine, rc6_to_gt(rc6), id)
81	set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);	76	intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
82		77
83	set(uncore, GUC_MAX_IDLE_COUNT, 0xA);	78	intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
84		79
85	set(uncore, GEN6_RC_SLEEP, 0);	80	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
86		81
87	set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */	82	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
88	}	83	}
89		84
90	/*	85	/*
@@ -105,8 +100,8 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) · 14 unmodified lines
105	* Broadwell+, To be conservative, we want to factor in a context	100	* Broadwell+, To be conservative, we want to factor in a context
106	* switch on top (due to ksoftirqd).	101	* switch on top (due to ksoftirqd).
107	*/	102	*/
108	set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);	103	intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
109	set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);	104	intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
110		105
111	/* 3a: Enable RC6	106	/* 3a: Enable RC6
112	*	107	*
@@ -122,8 +117,14 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) · 9 unmodified lines
122	GEN6_RC_CTL_RC6_ENABLE \|	117	GEN6_RC_CTL_RC6_ENABLE \|
123	GEN6_RC_CTL_EI_MODE(1);	118	GEN6_RC_CTL_EI_MODE(1);
124		119
125	/* Wa_16011777198 - Render powergating must remain disabled */	120	/*
126	if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) \|\|	121	* Wa_16011777198 and BSpec 52698 - Render powergating must be off.
		122	* FIXME BSpec is outdated, disabling powergating for MTL is just
		123	* temporary wa and should be removed after fixing real cause
		124	* of forcewake timeouts.
		125	*/
		126	if (IS_METEORLAKE(gt->i915) \|\|
		127	IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) \|\|
127	IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))	128	IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
128	pg_enable =	129	pg_enable =
129	GEN9_MEDIA_PG_ENABLE \|	130	GEN9_MEDIA_PG_ENABLE \|
@@ -141,7 +142,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) · 11 unmodified lines
141	VDN_MFX_POWERGATE_ENABLE(i));	142	VDN_MFX_POWERGATE_ENABLE(i));
142	}	143	}
143		144
144	set(uncore, GEN9_PG_ENABLE, pg_enable);	145	intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable);
145	}	146	}
146		147
147	static void gen9_rc6_enable(struct intel_rc6 *rc6)	148	static void gen9_rc6_enable(struct intel_rc6 *rc6)
@@ -152,26 +153,26 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) · 4 unmodified lines
152		153
153	/* 2b: Program RC6 thresholds.*/	154	/* 2b: Program RC6 thresholds.*/
154	if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) {	155	if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) {
155	set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 \| 85);	156	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 \| 85);
156	set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);	157	intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
157	} else if (IS_SKYLAKE(rc6_to_i915(rc6))) {	158	} else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
158	/*	159	/*
159	* WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only	160	* WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
160	* when CPG is enabled	161	* when CPG is enabled
161	*/	162	*/
162	set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);	163	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
163	} else {	164	} else {
164	set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);	165	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
165	}	166	}
166		167
167	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */	168	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
168	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */	169	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
169	for_each_engine(engine, rc6_to_gt(rc6), id)	170	for_each_engine(engine, rc6_to_gt(rc6), id)
170	set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);	171	intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
171		172
172	set(uncore, GUC_MAX_IDLE_COUNT, 0xA);	173	intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
173		174
174	set(uncore, GEN6_RC_SLEEP, 0);	175	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
175		176
176	/*	177	/*
177	* 2c: Program Coarse Power Gating Policies.	178	* 2c: Program Coarse Power Gating Policies.
@@ -194,11 +195,11 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) · 16 unmodified lines
194	* conservative, we have to factor in a context switch on top (due	195	* conservative, we have to factor in a context switch on top (due
195	* to ksoftirqd).	196	* to ksoftirqd).
196	*/	197	*/
197	set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);	198	intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
198	set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);	199	intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
199		200
200	/* 3a: Enable RC6 */	201	/* 3a: Enable RC6 */
201	set(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */	202	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
202		203
203	rc6->ctl_enable =	204	rc6->ctl_enable =
204	GEN6_RC_CTL_HW_ENABLE \|	205	GEN6_RC_CTL_HW_ENABLE \|
@@ -210,8 +211,8 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) · 5 unmodified lines
210	* - Render/Media PG need to be disabled with RC6.	211	* - Render/Media PG need to be disabled with RC6.
211	*/	212	*/
212	if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6)))	213	if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6)))
213	set(uncore, GEN9_PG_ENABLE,	214	intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,
214	GEN9_RENDER_PG_ENABLE \| GEN9_MEDIA_PG_ENABLE);	215	GEN9_RENDER_PG_ENABLE \| GEN9_MEDIA_PG_ENABLE);
215	}	216	}
216		217
217	static void gen8_rc6_enable(struct intel_rc6 *rc6)	218	static void gen8_rc6_enable(struct intel_rc6 *rc6)
@@ -221,13 +222,13 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6) · 3 unmodified lines
221	enum intel_engine_id id;	222	enum intel_engine_id id;
222		223
223	/* 2b: Program RC6 thresholds.*/	224	/* 2b: Program RC6 thresholds.*/
224	set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);	225	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
225	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */	226	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
226	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */	227	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
227	for_each_engine(engine, rc6_to_gt(rc6), id)	228	for_each_engine(engine, rc6_to_gt(rc6), id)
228	set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);	229	intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
229	set(uncore, GEN6_RC_SLEEP, 0);	230	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
230	set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */	231	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
231		232
232	/* 3: Enable RC6 */	233	/* 3: Enable RC6 */
233	rc6->ctl_enable =	234	rc6->ctl_enable =
@@ -245,20 +246,20 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6) · 11 unmodified lines
245	u32 rc6vids, rc6_mask;	246	u32 rc6vids, rc6_mask;
246	int ret;	247	int ret;
247		248
248	set(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);	249	intel_uncore_write_fw(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
249	set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 \| 30);	250	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 \| 30);
250	set(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);	251	intel_uncore_write_fw(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
251	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);	252	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
252	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);	253	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
253		254
254	for_each_engine(engine, rc6_to_gt(rc6), id)	255	for_each_engine(engine, rc6_to_gt(rc6), id)
255	set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);	256	intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
256		257
257	set(uncore, GEN6_RC_SLEEP, 0);	258	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
258	set(uncore, GEN6_RC1e_THRESHOLD, 1000);	259	intel_uncore_write_fw(uncore, GEN6_RC1e_THRESHOLD, 1000);
259	set(uncore, GEN6_RC6_THRESHOLD, 50000);	260	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000);
260	set(uncore, GEN6_RC6p_THRESHOLD, 150000);	261	intel_uncore_write_fw(uncore, GEN6_RC6p_THRESHOLD, 150000);
261	set(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */	262	intel_uncore_write_fw(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
262		263
263	/* We don't use those on Haswell */	264	/* We don't use those on Haswell */
264	rc6_mask = GEN6_RC_CTL_RC6_ENABLE;	265	rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
@@ -372,22 +373,22 @@ static void chv_rc6_enable(struct intel_rc6 *rc6) · 107 unmodified lines
372	enum intel_engine_id id;	373	enum intel_engine_id id;
373		374
374	/* 2a: Program RC6 thresholds.*/	375	/* 2a: Program RC6 thresholds.*/
375	set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);	376	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
376	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */	377	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
377	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */	378	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
378		379
379	for_each_engine(engine, rc6_to_gt(rc6), id)	380	for_each_engine(engine, rc6_to_gt(rc6), id)
380	set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);	381	intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
381	set(uncore, GEN6_RC_SLEEP, 0);	382	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
382		383
383	/* TO threshold set to 500 us (0x186 * 1.28 us) */	384	/* TO threshold set to 500 us (0x186 * 1.28 us) */
384	set(uncore, GEN6_RC6_THRESHOLD, 0x186);	385	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x186);
385		386
386	/* Allows RC6 residency counter to work */	387	/* Allows RC6 residency counter to work */
387	set(uncore, VLV_COUNTER_CONTROL,	388	intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
388	_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH \|	389	_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH \|
389	VLV_MEDIA_RC6_COUNT_EN \|	390	VLV_MEDIA_RC6_COUNT_EN \|
390	VLV_RENDER_RC6_COUNT_EN));	391	VLV_RENDER_RC6_COUNT_EN));
391		392
392	/* 3: Enable RC6 */	393	/* 3: Enable RC6 */
393	rc6->ctl_enable = GEN7_RC_CTL_TO_MODE;	394	rc6->ctl_enable = GEN7_RC_CTL_TO_MODE;
@@ -399,22 +400,22 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6) · 5 unmodified lines
399	struct intel_engine_cs *engine;	400	struct intel_engine_cs *engine;
400	enum intel_engine_id id;	401	enum intel_engine_id id;
401		402
402	set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);	403	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
403	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);	404	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
404	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);	405	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
405		406
406	for_each_engine(engine, rc6_to_gt(rc6), id)	407	for_each_engine(engine, rc6_to_gt(rc6), id)
407	set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);	408	intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
408		409
409	set(uncore, GEN6_RC6_THRESHOLD, 0x557);	410	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x557);
410		411
411	/* Allows RC6 residency counter to work */	412	/* Allows RC6 residency counter to work */
412	set(uncore, VLV_COUNTER_CONTROL,	413	intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
413	_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH \|	414	_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH \|
414	VLV_MEDIA_RC0_COUNT_EN \|	415	VLV_MEDIA_RC0_COUNT_EN \|
415	VLV_RENDER_RC0_COUNT_EN \|	416	VLV_RENDER_RC0_COUNT_EN \|
416	VLV_MEDIA_RC6_COUNT_EN \|	417	VLV_MEDIA_RC6_COUNT_EN \|
417	VLV_RENDER_RC6_COUNT_EN));	418	VLV_RENDER_RC6_COUNT_EN));
418		419
419	rc6->ctl_enable =	420	rc6->ctl_enable =
420	GEN7_RC_CTL_TO_MODE \| VLV_RC_CTL_CTX_RST_PARALLEL;	421	GEN7_RC_CTL_TO_MODE \| VLV_RC_CTL_CTX_RST_PARALLEL;
@@ -575,9 +576,9 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6) · 154 unmodified lines
575		576
576	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);	577	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
577	if (GRAPHICS_VER(i915) >= 9)	578	if (GRAPHICS_VER(i915) >= 9)
578	set(uncore, GEN9_PG_ENABLE, 0);	579	intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 0);
579	set(uncore, GEN6_RC_CONTROL, 0);	580	intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, 0);
580	set(uncore, GEN6_RC_STATE, 0);	581	intel_uncore_write_fw(uncore, GEN6_RC_STATE, 0);
581	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);	582	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
582	}	583	}
583		584
@@ -684,7 +685,7 @@ void intel_rc6_unpark(struct intel_rc6 *rc6) · 100 unmodified lines
684	return;	685	return;
685		686
686	/* Restore HW timers for automatic RC6 entry while busy */	687	/* Restore HW timers for automatic RC6 entry while busy */
687	set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);	688	intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
688	}	689	}
689		690
690	void intel_rc6_park(struct intel_rc6 *rc6)	691	void intel_rc6_park(struct intel_rc6 *rc6)
@@ -704,7 +705,7 @@ void intel_rc6_park(struct intel_rc6 *rc6) · 13 unmodified lines
704	return;	705	return;
705		706
706	/* Turn off the HW timers and go directly to rc6 */	707	/* Turn off the HW timers and go directly to rc6 */
707	set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);	708	intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
708		709
709	if (HAS_RC6pp(rc6_to_i915(rc6)))	710	if (HAS_RC6pp(rc6_to_i915(rc6)))
710	target = 0x6; /* deepest rc6 */	711	target = 0x6; /* deepest rc6 */
@@ -712,7 +713,7 @@ void intel_rc6_park(struct intel_rc6 *rc6) · 1 unmodified line
712	target = 0x5; /* deep rc6 */	713	target = 0x5; /* deep rc6 */
713	else	714	else
714	target = 0x4; /* normal rc6 */	715	target = 0x4; /* normal rc6 */
715	set(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);	716	intel_uncore_write_fw(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
716	}	717	}
717		718
718	void intel_rc6_disable(struct intel_rc6 *rc6)	719	void intel_rc6_disable(struct intel_rc6 *rc6)
@@ -735,7 +736,7 @@ void intel_rc6_fini(struct intel_rc6 *rc6) · 16 unmodified lines
735		736
736	/* We want the BIOS C6 state preserved across loads for MTL */	737	/* We want the BIOS C6 state preserved across loads for MTL */
737	if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured)	738	if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured)
738	set(uncore, GEN6_RC_STATE, rc6->bios_rc_state);	739	intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
739		740
740	pctx = fetch_and_zero(&rc6->pctx);	741	pctx = fetch_and_zero(&rc6->pctx);
741	if (pctx)	742	if (pctx)
@@ -766,18 +767,18 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg) · 24 unmodified lines
766	* before we have set the default VLV_COUNTER_CONTROL value. So always	767	* before we have set the default VLV_COUNTER_CONTROL value. So always
767	* set the high bit to be safe.	768	* set the high bit to be safe.
768	*/	769	*/
769	set(uncore, VLV_COUNTER_CONTROL,	770	intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
770	_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));	771	_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
771	upper = intel_uncore_read_fw(uncore, reg);	772	upper = intel_uncore_read_fw(uncore, reg);
772	do {	773	do {
773	tmp = upper;	774	tmp = upper;
774		775
775	set(uncore, VLV_COUNTER_CONTROL,	776	intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
776	_MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));	777	_MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
777	lower = intel_uncore_read_fw(uncore, reg);	778	lower = intel_uncore_read_fw(uncore, reg);
778		779
779	set(uncore, VLV_COUNTER_CONTROL,	780	intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
780	_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));	781	_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
781	upper = intel_uncore_read_fw(uncore, reg);	782	upper = intel_uncore_read_fw(uncore, reg);
782	} while (upper != tmp && --loop);	783	} while (upper != tmp && --loop);
783		784

drivers/gpu/drm/i915/gt/intel_workarounds.c+41−15

 	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
 }
+static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
+				   struct i915_wa_list *wal)
+{
+	struct drm_i915_private *i915 = engine->i915;
+	dg2_ctx_gt_tuning_init(engine, wal);
+	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
+	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
+}
 static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
+	mtl_ctx_gt_tuning_init(engine, wal);
 	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
 		/* Wa_14014947963 */
 static void
 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
+	/* Wa_14018778641 / Wa_18018781329 */
+	wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+	wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+	/* Wa_22016670082 */
+	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
 	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
 	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
 		/* Wa_14014830051 */
 		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
-		/* Wa_18018781329 */
+		/* Wa_14015795083 */
-		wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+		wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
-		wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
 	}
 	/*
 static void
 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0)) {
+	/*
-		/*
+	 * Wa_14018778641
-		 * Wa_18018781329
+	 * Wa_18018781329
-		 *
+	 *
-		 * Note that although these registers are MCR on the primary
+	 * Note that although these registers are MCR on the primary
-		 * GT, the media GT's versions are regular singleton registers.
+	 * GT, the media GT's versions are regular singleton registers.
-		 */
+	 */
-		wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB);
+	wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB);
-		wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+	wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
-		wa_write_or(wal, XELPMP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+	wa_write_or(wal, XELPMP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
-	}
 	debug_dump_steering(gt);
 }
  */
 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
 {
+	if (IS_METEORLAKE(gt->i915)) {
+		if (gt->type != GT_MEDIA)
+			wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+		wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
+	}
 	if (IS_PONTEVECCHIO(gt->i915)) {
 		wa_mcr_write(wal, XEHPC_L3SCRUB,
 			     SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
 add_render_compute_tuning_settings(struct drm_i915_private *i915,
 				   struct i915_wa_list *wal)
 {
-	if (IS_DG2(i915))
+	if (IS_METEORLAKE(i915) || IS_DG2(i915))
 		wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
 	/*

drivers/gpu/drm/i915/gt/selftest_engine_pm.c+2−1

 #include <linux/sort.h>
+#include "gt/intel_gt_print.h"
 #include "i915_selftest.h"
 #include "intel_engine_regs.h"
 #include "intel_gpu_commands.h"
 			/* gt wakeref is async (deferred to workqueue) */
 			if (intel_gt_pm_wait_for_idle(gt)) {
-				pr_err("GT failed to idle\n");
+				gt_err(gt, "GT failed to idle\n");
 				return -EINVAL;
 			}
 		}

drivers/gpu/drm/i915/gt/selftest_migrate.c+25−22

 static int intel_context_copy_ccs(struct intel_context *ce,
 				  const struct i915_deps *deps,
 				  struct scatterlist *sg,
-				  enum i915_cache_level cache_level,
+				  unsigned int pat_index,
 				  bool write_to_ccs,
 				  struct i915_request **out)
 {
 		if (err)
 			goto out_rq;
-		len = emit_pte(rq, &it, cache_level, true, offset, CHUNK_SZ);
+		len = emit_pte(rq, &it, pat_index, true, offset, CHUNK_SZ);
 		if (len <= 0) {
 			err = len;
 			goto out_rq;
 		       struct i915_gem_ww_ctx *ww,
 		       const struct i915_deps *deps,
 		       struct scatterlist *sg,
-		       enum i915_cache_level cache_level,
+		       unsigned int pat_index,
 		       bool write_to_ccs,
 		       struct i915_request **out)
 {
 	if (err)
 		goto out;
-	err = intel_context_copy_ccs(ce, deps, sg, cache_level,
+	err = intel_context_copy_ccs(ce, deps, sg, pat_index,
 				     write_to_ccs, out);
 	intel_context_unpin(ce);
 			/* Write the obj data into ccs surface */
 			err = intel_migrate_ccs_copy(migrate, &ww, NULL,
 						     obj->mm.pages->sgl,
-						     obj->cache_level,
+						     obj->pat_index,
 						     true, &rq);
 			if (rq && !err) {
 				if (i915_request_wait(rq, 0, HZ) < 0) {
 			err = intel_migrate_ccs_copy(migrate, &ww, NULL,
 						     obj->mm.pages->sgl,
-						     obj->cache_level,
+						     obj->pat_index,
 						     false, &rq);
 			if (rq && !err) {
 				if (i915_request_wait(rq, 0, HZ) < 0) {
 			  struct i915_request **out)
 {
 	return intel_migrate_copy(migrate, ww, NULL,
-				  src->mm.pages->sgl, src->cache_level,
+				  src->mm.pages->sgl, src->pat_index,
 				  i915_gem_object_is_lmem(src),
-				  dst->mm.pages->sgl, dst->cache_level,
+				  dst->mm.pages->sgl, dst->pat_index,
 				  i915_gem_object_is_lmem(dst),
 				  out);
 }
 			 struct i915_request **out)
 {
 	return intel_context_migrate_copy(migrate->context, NULL,
-					  src->mm.pages->sgl, src->cache_level,
+					  src->mm.pages->sgl, src->pat_index,
 					  i915_gem_object_is_lmem(src),
-					  dst->mm.pages->sgl, dst->cache_level,
+					  dst->mm.pages->sgl, dst->pat_index,
 					  i915_gem_object_is_lmem(dst),
 					  out);
 }
 {
 	return intel_migrate_clear(migrate, ww, NULL,
 				   obj->mm.pages->sgl,
-				   obj->cache_level,
+				   obj->pat_index,
 				   i915_gem_object_is_lmem(obj),
 				   value, out);
 }
 {
 	return intel_context_migrate_clear(migrate->context, NULL,
 					   obj->mm.pages->sgl,
-					   obj->cache_level,
+					   obj->pat_index,
 					   i915_gem_object_is_lmem(obj),
 					   value, out);
 }
 	 */
 	pr_info("%s emite_pte ring space=%u\n", __func__, rq->ring->space);
 	it = sg_sgt(obj->mm.pages->sgl);
-	len = emit_pte(rq, &it, obj->cache_level, false, 0, CHUNK_SZ);
+	len = emit_pte(rq, &it, obj->pat_index, false, 0, CHUNK_SZ);
 	if (!len) {
 		err = -EINVAL;
 		goto out_rq;
 static int __perf_clear_blt(struct intel_context *ce,
 			    struct scatterlist *sg,
-			    enum i915_cache_level cache_level,
+			    unsigned int pat_index,
 			    bool is_lmem,
 			    size_t sz)
 {
 		t0 = ktime_get();
-		err = intel_context_migrate_clear(ce, NULL, sg, cache_level,
+		err = intel_context_migrate_clear(ce, NULL, sg, pat_index,
 						  is_lmem, 0, &rq);
 		if (rq) {
 			if (i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT) < 0)
 		err = __perf_clear_blt(gt->migrate.context,
 				       dst->mm.pages->sgl,
-				       I915_CACHE_NONE,
+				       i915_gem_get_pat_index(gt->i915,
+							      I915_CACHE_NONE),
 				       i915_gem_object_is_lmem(dst),
 				       sizes[i]);
 static int __perf_copy_blt(struct intel_context *ce,
 			   struct scatterlist *src,
-			   enum i915_cache_level src_cache_level,
+			   unsigned int src_pat_index,
 			   bool src_is_lmem,
 			   struct scatterlist *dst,
-			   enum i915_cache_level dst_cache_level,
+			   unsigned int dst_pat_index,
 			   bool dst_is_lmem,
 			   size_t sz)
 {
 		t0 = ktime_get();
 		err = intel_context_migrate_copy(ce, NULL,
-						 src, src_cache_level,
+						 src, src_pat_index,
 						 src_is_lmem,
-						 dst, dst_cache_level,
+						 dst, dst_pat_index,
 						 dst_is_lmem,
 						 &rq);
 		if (rq) {
 		err = __perf_copy_blt(gt->migrate.context,
 				      src->mm.pages->sgl,
-				      I915_CACHE_NONE,
+				      i915_gem_get_pat_index(gt->i915,
+							     I915_CACHE_NONE),
 				      i915_gem_object_is_lmem(src),
 				      dst->mm.pages->sgl,
-				      I915_CACHE_NONE,
+				      i915_gem_get_pat_index(gt->i915,
+							     I915_CACHE_NONE),
 				      i915_gem_object_is_lmem(dst),
 				      sz);

drivers/gpu/drm/i915/gt/selftest_mocs.c+2−1

 			   const struct drm_i915_mocs_table *table,
 			   u32 *offset)
 {
+	struct intel_gt *gt = rq->engine->gt;
 	u32 addr;
 	if (!table)
 		return 0;
 	if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
-		addr = global_mocs_offset();
+		addr = global_mocs_offset() + gt->uncore->gsi_offset;
 	else
 		addr = mocs_offset(rq->engine);

drivers/gpu/drm/i915/gt/selftest_reset.c+6−2

 		ggtt->vm.insert_page(&ggtt->vm, dma,
 				     ggtt->error_capture.start,
-				     I915_CACHE_NONE, 0);
+				     i915_gem_get_pat_index(gt->i915,
+							    I915_CACHE_NONE),
+				     0);
 		mb();
 		s = io_mapping_map_wc(&ggtt->iomap,
 		ggtt->vm.insert_page(&ggtt->vm, dma,
 				     ggtt->error_capture.start,
-				     I915_CACHE_NONE, 0);
+				     i915_gem_get_pat_index(gt->i915,
+							    I915_CACHE_NONE),
+				     0);
 		mb();
 		s = io_mapping_map_wc(&ggtt->iomap,

drivers/gpu/drm/i915/gt/selftest_slpc.c+37−5

@@ -70,6 +70,31 @@ static int slpc_set_freq(struct intel_gt *gt, u32 freq) · 69 unmodified lines
70	return err;	70	return err;
71	}	71	}
72		72
		73	static int slpc_restore_freq(struct intel_guc_slpc *slpc, u32 min, u32 max)
		74	{
		75	int err;
		76
		77	err = slpc_set_max_freq(slpc, max);
		78	if (err) {
		79	pr_err("Unable to restore max freq");
		80	return err;
		81	}
		82
		83	err = slpc_set_min_freq(slpc, min);
		84	if (err) {
		85	pr_err("Unable to restore min freq");
		86	return err;
		87	}
		88
		89	err = intel_guc_slpc_set_ignore_eff_freq(slpc, false);
		90	if (err) {
		91	pr_err("Unable to restore efficient freq");
		92	return err;
		93	}
		94
		95	return 0;
		96	}
		97
73	static u64 measure_power_at_freq(struct intel_gt gt, int freq, u64 *power)	98	static u64 measure_power_at_freq(struct intel_gt gt, int freq, u64 *power)
74	{	99	{
75	int err = 0;	100	int err = 0;
@@ -268,8 +293,7 @@ static int run_test(struct intel_gt *gt, int test_type) · 192 unmodified lines
268		293
269	/*	294	/*
270	* Set min frequency to RPn so that we can test the whole	295	* Set min frequency to RPn so that we can test the whole
271	* range of RPn-RP0. This also turns off efficient freq	296	* range of RPn-RP0.
272	* usage and makes results more predictable.
273	*/	297	*/
274	err = slpc_set_min_freq(slpc, slpc->min_freq);	298	err = slpc_set_min_freq(slpc, slpc->min_freq);
275	if (err) {	299	if (err) {
@@ -277,6 +301,15 @@ static int run_test(struct intel_gt *gt, int test_type) · 1 unmodified line
277	return err;	301	return err;
278	}	302	}
279		303
		304	/*
		305	* Turn off efficient frequency so RPn/RP0 ranges are obeyed.
		306	*/
		307	err = intel_guc_slpc_set_ignore_eff_freq(slpc, true);
		308	if (err) {
		309	pr_err("Unable to turn off efficient freq!");
		310	return err;
		311	}
		312
280	intel_gt_pm_wait_for_idle(gt);	313	intel_gt_pm_wait_for_idle(gt);
281	intel_gt_pm_get(gt);	314	intel_gt_pm_get(gt);
282	for_each_engine(engine, gt, id) {	315	for_each_engine(engine, gt, id) {
@@ -358,9 +391,8 @@ static int run_test(struct intel_gt *gt, int test_type) · 75 unmodified lines
358	break;	391	break;
359	}	392	}
360		393
361	/* Restore min/max frequencies */	394	/* Restore min/max/efficient frequencies */
362	slpc_set_max_freq(slpc, slpc_max_freq);	395	err = slpc_restore_freq(slpc, slpc_min_freq, slpc_max_freq);
363	slpc_set_min_freq(slpc, slpc_min_freq);
364		396
365	if (igt_flush_test(gt->i915))	397	if (igt_flush_test(gt->i915))
366	err = -EIO;	398	err = -EIO;

drivers/gpu/drm/i915/gt/selftest_timeline.c+1−1

@@ -836,7 +836,7 @@ static int setup_watcher(struct hwsp_watcher w, struct intel_gt gt, · 835 unmodified lines
836	return PTR_ERR(obj);	836	return PTR_ERR(obj);
837		837
838	/* keep the same cache settings as timeline */	838	/* keep the same cache settings as timeline */
839	i915_gem_object_set_cache_coherency(obj, tl->hwsp_ggtt->obj->cache_level);	839	i915_gem_object_set_pat_index(obj, tl->hwsp_ggtt->obj->pat_index);
840	w->map = i915_gem_object_pin_map_unlocked(obj,	840	w->map = i915_gem_object_pin_map_unlocked(obj,
841	page_unmask_bits(tl->hwsp_ggtt->obj->mm.mapping));	841	page_unmask_bits(tl->hwsp_ggtt->obj->mm.mapping));
842	if (IS_ERR(w->map)) {	842	if (IS_ERR(w->map)) {

drivers/gpu/drm/i915/gt/selftest_tlb.c+3−1

 	   u64 length,
 	   struct rnd_state *prng)
 {
+	const unsigned int pat_index =
+		i915_gem_get_pat_index(ce->vm->i915, I915_CACHE_NONE);
 	struct drm_i915_gem_object *batch;
 	struct drm_mm_node vb_node;
 	struct i915_request *rq;
 		/* Flip the PTE between A and B */
 		if (i915_gem_object_is_lmem(vb->obj))
 			pte_flags |= PTE_LM;
-		ce->vm->insert_entries(ce->vm, &vb_res, 0, pte_flags);
+		ce->vm->insert_entries(ce->vm, &vb_res, pat_index, pte_flags);
 		/* Flush the PTE update to concurrent HW */
 		tlbinv(ce->vm, addr & -length, length);

drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h+1−0

@@ -44,6 +44,7 @@ enum intel_guc_load_status { · 43 unmodified lines
44	enum intel_bootrom_load_status {	44	enum intel_bootrom_load_status {
45	INTEL_BOOTROM_STATUS_NO_KEY_FOUND = 0x13,	45	INTEL_BOOTROM_STATUS_NO_KEY_FOUND = 0x13,
46	INTEL_BOOTROM_STATUS_AES_PROD_KEY_FOUND = 0x1A,	46	INTEL_BOOTROM_STATUS_AES_PROD_KEY_FOUND = 0x1A,
		47	INTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE = 0x2B,
47	INTEL_BOOTROM_STATUS_RSA_FAILED = 0x50,	48	INTEL_BOOTROM_STATUS_RSA_FAILED = 0x50,
48	INTEL_BOOTROM_STATUS_PAVPC_FAILED = 0x73,	49	INTEL_BOOTROM_STATUS_PAVPC_FAILED = 0x73,
49	INTEL_BOOTROM_STATUS_WOPCM_FAILED = 0x74,	50	INTEL_BOOTROM_STATUS_WOPCM_FAILED = 0x74,

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h+14−6

 struct intel_guc;
 struct file;
-/**
+/*
  * struct __guc_capture_bufstate
  *
  * Book-keeping structure used to track read and write pointers
 	u32 wr;
 };
-/**
+/*
  * struct __guc_capture_parsed_output - extracted error capture node
  *
  * A single unit of extracted error-capture output data grouped together
 #define GCAP_PARSED_REGLIST_INDEX_ENGINST  BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE)
 };
-/**
+/*
  * struct guc_debug_capture_list_header / struct guc_debug_capture_list
  *
  * As part of ADS registration, these header structures (followed by
 	struct guc_mmio_reg regs[];
 } __packed;
-/**
+/*
  * struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group
  *
  * intel_guc_capture module uses these structures to maintain static
 	struct __guc_mmio_reg_descr *extlist; /* only used for steered registers */
 };
-/**
+/*
  * struct guc_state_capture_header_t / struct guc_state_capture_t /
  * guc_state_capture_group_header_t / guc_state_capture_group_t
  *
 	struct guc_state_capture_t capture_entries[];
 } __packed;
-/**
+/*
  * struct __guc_capture_ads_cache
  *
  * A structure to cache register lists that were populated and registered
 	struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX]
 						[GUC_CAPTURE_LIST_TYPE_MAX]
 						[GUC_MAX_ENGINE_CLASSES];
+	/**
+	 * @ads_null_cache: ADS null cache.
+	 */
 	void *ads_null_cache;
 	/**
 	struct list_head cachelist;
 #define PREALLOC_NODES_MAX_COUNT (3 * GUC_MAX_ENGINE_CLASSES * GUC_MAX_INSTANCES_PER_CLASS)
 #define PREALLOC_NODES_DEFAULT_NUMREGS 64
+	/**
+	 * @max_mmio_per_node: Max MMIO per node.
+	 */
 	int max_mmio_per_node;
 	/**

drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c+23−0

 #define GSC_FW_STATUS_REG			_MMIO(0x116C40)
 #define GSC_FW_CURRENT_STATE			REG_GENMASK(3, 0)
 #define   GSC_FW_CURRENT_STATE_RESET		0
+#define   GSC_FW_PROXY_STATE_NORMAL		5
 #define GSC_FW_INIT_COMPLETE_BIT		REG_BIT(9)
 static bool gsc_is_in_reset(struct intel_uncore *uncore)
 	       GSC_FW_CURRENT_STATE_RESET;
 }
+bool intel_gsc_uc_fw_proxy_init_done(struct intel_gsc_uc *gsc)
+{
+	struct intel_uncore *uncore = gsc_uc_to_gt(gsc)->uncore;
+	u32 fw_status = intel_uncore_read(uncore, GSC_FW_STATUS_REG);
+	return REG_FIELD_GET(GSC_FW_CURRENT_STATE, fw_status) ==
+	       GSC_FW_PROXY_STATE_NORMAL;
+}
 bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc)
 {
 	struct intel_uncore *uncore = gsc_uc_to_gt(gsc)->uncore;
 	if (obj->base.size < gsc->fw.size)
 		return -ENOSPC;
+	/*
+	 * Wa_22016122933: For MTL the shared memory needs to be mapped
+	 * as WC on CPU side and UC (PAT index 2) on GPU side
+	 */
+	if (IS_METEORLAKE(i915))
+		i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
 	dst = i915_gem_object_pin_map_unlocked(obj,
 					       i915_coherent_map_type(i915, obj, true));
 	if (IS_ERR(dst))
 	memset(dst, 0, obj->base.size);
 	memcpy(dst, src, gsc->fw.size);
+	/*
+	 * Wa_22016122933: Making sure the data in dst is
+	 * visible to GSC right away
+	 */
+	intel_guc_write_barrier(&gt->uc.guc);
 	i915_gem_object_unpin_map(gsc->fw.obj);
 	i915_gem_object_unpin_map(obj);

drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h+1−0

@@ -13,5 +13,6 @@ struct intel_uncore; · 12 unmodified lines
13		13
14	int intel_gsc_uc_fw_upload(struct intel_gsc_uc *gsc);	14	int intel_gsc_uc_fw_upload(struct intel_gsc_uc *gsc);
15	bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc);	15	bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc);
		16	bool intel_gsc_uc_fw_proxy_init_done(struct intel_gsc_uc *gsc);
16		17
17	#endif	18	#endif

drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c+424−0

@@ -0,0 +1,424 @@
	1	// SPDX-License-Identifier: MIT
	2	/*
	3	* Copyright © 2023 Intel Corporation
	4	*/
	5
	6	#include <linux/component.h>
	7
	8	#include "drm/i915_component.h"
	9	#include "drm/i915_gsc_proxy_mei_interface.h"
	10
	11	#include "gt/intel_gt.h"
	12	#include "gt/intel_gt_print.h"
	13	#include "intel_gsc_proxy.h"
	14	#include "intel_gsc_uc.h"
	15	#include "intel_gsc_uc_heci_cmd_submit.h"
	16	#include "i915_drv.h"
	17	#include "i915_reg.h"
	18
	19	/*
	20	* GSC proxy:
	21	* The GSC uC needs to communicate with the CSME to perform certain operations.
	22	* Since the GSC can't perform this communication directly on platforms where it
	23	* is integrated in GT, i915 needs to transfer the messages from GSC to CSME
	24	* and back. i915 must manually start the proxy flow after the GSC is loaded to
	25	* signal to GSC that we're ready to handle its messages and allow it to query
	26	* its init data from CSME; GSC will then trigger an HECI2 interrupt if it needs
	27	* to send messages to CSME again.
	28	* The proxy flow is as follow:
	29	* 1 - i915 submits a request to GSC asking for the message to CSME
	30	* 2 - GSC replies with the proxy header + payload for CSME
	31	* 3 - i915 sends the reply from GSC as-is to CSME via the mei proxy component
	32	* 4 - CSME replies with the proxy header + payload for GSC
	33	* 5 - i915 submits a request to GSC with the reply from CSME
	34	* 6 - GSC replies either with a new header + payload (same as step 2, so we
	35	* restart from there) or with an end message.
	36	*/
	37
	38	/*
	39	* The component should load quite quickly in most cases, but it could take
	40	* a bit. Using a very big timeout just to cover the worst case scenario
	41	*/
	42	#define GSC_PROXY_INIT_TIMEOUT_MS 20000
	43
	44	/* the protocol supports up to 32K in each direction */
	45	#define GSC_PROXY_BUFFER_SIZE SZ_32K
	46	#define GSC_PROXY_CHANNEL_SIZE (GSC_PROXY_BUFFER_SIZE * 2)
	47	#define GSC_PROXY_MAX_MSG_SIZE (GSC_PROXY_BUFFER_SIZE - sizeof(struct intel_gsc_mtl_header))
	48
	49	/* FW-defined proxy header */
	50	struct intel_gsc_proxy_header {
	51	/*
	52	* hdr:
	53	* Bits 0-7: type of the proxy message (see enum intel_gsc_proxy_type)
	54	* Bits 8-15: rsvd
	55	* Bits 16-31: length in bytes of the payload following the proxy header
	56	*/
	57	u32 hdr;
	58	#define GSC_PROXY_TYPE GENMASK(7, 0)
	59	#define GSC_PROXY_PAYLOAD_LENGTH GENMASK(31, 16)
	60
	61	u32 source; /* Source of the Proxy message */
	62	u32 destination; /* Destination of the Proxy message */
	63	#define GSC_PROXY_ADDRESSING_KMD 0x10000
	64	#define GSC_PROXY_ADDRESSING_GSC 0x20000
	65	#define GSC_PROXY_ADDRESSING_CSME 0x30000
	66
	67	u32 status; /* Command status */
	68	} __packed;
	69
	70	/* FW-defined proxy types */
	71	enum intel_gsc_proxy_type {
	72	GSC_PROXY_MSG_TYPE_PROXY_INVALID = 0,
	73	GSC_PROXY_MSG_TYPE_PROXY_QUERY = 1,
	74	GSC_PROXY_MSG_TYPE_PROXY_PAYLOAD = 2,
	75	GSC_PROXY_MSG_TYPE_PROXY_END = 3,
	76	GSC_PROXY_MSG_TYPE_PROXY_NOTIFICATION = 4,
	77	};
	78
	79	struct gsc_proxy_msg {
	80	struct intel_gsc_mtl_header header;
	81	struct intel_gsc_proxy_header proxy_header;
	82	} __packed;
	83
	84	static int proxy_send_to_csme(struct intel_gsc_uc *gsc)
	85	{
	86	struct intel_gt *gt = gsc_uc_to_gt(gsc);
	87	struct i915_gsc_proxy_component *comp = gsc->proxy.component;
	88	struct intel_gsc_mtl_header *hdr;
	89	void *in = gsc->proxy.to_csme;
	90	void *out = gsc->proxy.to_gsc;
	91	u32 in_size;
	92	int ret;
	93
	94	/* CSME msg only includes the proxy */
	95	hdr = in;
	96	in += sizeof(struct intel_gsc_mtl_header);
	97	out += sizeof(struct intel_gsc_mtl_header);
	98
	99	in_size = hdr->message_size - sizeof(struct intel_gsc_mtl_header);
	100
	101	/* the message must contain at least the proxy header */
	102	if (in_size < sizeof(struct intel_gsc_proxy_header) \|\|
	103	in_size > GSC_PROXY_MAX_MSG_SIZE) {
	104	gt_err(gt, "Invalid CSME message size: %u\n", in_size);
	105	return -EINVAL;
	106	}
	107
	108	ret = comp->ops->send(comp->mei_dev, in, in_size);
	109	if (ret < 0) {
	110	gt_err(gt, "Failed to send CSME message\n");
	111	return ret;
	112	}
	113
	114	ret = comp->ops->recv(comp->mei_dev, out, GSC_PROXY_MAX_MSG_SIZE);
	115	if (ret < 0) {
	116	gt_err(gt, "Failed to receive CSME message\n");
	117	return ret;
	118	}
	119
	120	return ret;
	121	}
	122
	123	static int proxy_send_to_gsc(struct intel_gsc_uc *gsc)
	124	{
	125	struct intel_gt *gt = gsc_uc_to_gt(gsc);
	126	u32 marker = gsc->proxy.to_csme; / first dw of the reply header */
	127	u64 addr_in = i915_ggtt_offset(gsc->proxy.vma);
	128	u64 addr_out = addr_in + GSC_PROXY_BUFFER_SIZE;
	129	u32 size = ((struct gsc_proxy_msg *)gsc->proxy.to_gsc)->header.message_size;
	130	int err;
	131
	132	/* the message must contain at least the gsc and proxy headers */
	133	if (size < sizeof(struct gsc_proxy_msg) \|\| size > GSC_PROXY_BUFFER_SIZE) {
	134	gt_err(gt, "Invalid GSC proxy message size: %u\n", size);
	135	return -EINVAL;
	136	}
	137
	138	/* clear the message marker */
	139	*marker = 0;
	140
	141	/* make sure the marker write is flushed */
	142	wmb();
	143
	144	/* send the request */
	145	err = intel_gsc_uc_heci_cmd_submit_packet(gsc, addr_in, size,
	146	addr_out, GSC_PROXY_BUFFER_SIZE);
	147
	148	if (!err) {
	149	/* wait for the reply to show up */
	150	err = wait_for(*marker != 0, 300);
	151	if (err)
	152	gt_err(gt, "Failed to get a proxy reply from gsc\n");
	153	}
	154
	155	return err;
	156	}
	157
	158	static int validate_proxy_header(struct intel_gsc_proxy_header *header,
	159	u32 source, u32 dest)
	160	{
	161	u32 type = FIELD_GET(GSC_PROXY_TYPE, header->hdr);
	162	u32 length = FIELD_GET(GSC_PROXY_PAYLOAD_LENGTH, header->hdr);
	163	int ret = 0;
	164
	165	if (header->destination != dest \|\| header->source != source) {
	166	ret = -ENOEXEC;
	167	goto fail;
	168	}
	169
	170	switch (type) {
	171	case GSC_PROXY_MSG_TYPE_PROXY_PAYLOAD:
	172	if (length > 0)
	173	break;
	174	fallthrough;
	175	case GSC_PROXY_MSG_TYPE_PROXY_INVALID:
	176	ret = -EIO;
	177	goto fail;
	178	default:
	179	break;
	180	}
	181
	182	fail:
	183	return ret;
	184	}
	185
	186	static int proxy_query(struct intel_gsc_uc *gsc)
	187	{
	188	struct intel_gt *gt = gsc_uc_to_gt(gsc);
	189	struct gsc_proxy_msg *to_gsc = gsc->proxy.to_gsc;
	190	struct gsc_proxy_msg *to_csme = gsc->proxy.to_csme;
	191	int ret;
	192
	193	intel_gsc_uc_heci_cmd_emit_mtl_header(&to_gsc->header,
	194	HECI_MEADDRESS_PROXY,
	195	sizeof(struct gsc_proxy_msg),
	196	0);
	197
	198	to_gsc->proxy_header.hdr =
	199	FIELD_PREP(GSC_PROXY_TYPE, GSC_PROXY_MSG_TYPE_PROXY_QUERY) \|
	200	FIELD_PREP(GSC_PROXY_PAYLOAD_LENGTH, 0);
	201
	202	to_gsc->proxy_header.source = GSC_PROXY_ADDRESSING_KMD;
	203	to_gsc->proxy_header.destination = GSC_PROXY_ADDRESSING_GSC;
	204	to_gsc->proxy_header.status = 0;
	205
	206	while (1) {
	207	/* clear the GSC response header space */
	208	memset(gsc->proxy.to_csme, 0, sizeof(struct gsc_proxy_msg));
	209
	210	/* send proxy message to GSC */
	211	ret = proxy_send_to_gsc(gsc);
	212	if (ret) {
	213	gt_err(gt, "failed to send proxy message to GSC! %d\n", ret);
	214	goto proxy_error;
	215	}
	216
	217	/* stop if this was the last message */
	218	if (FIELD_GET(GSC_PROXY_TYPE, to_csme->proxy_header.hdr) ==
	219	GSC_PROXY_MSG_TYPE_PROXY_END)
	220	break;
	221
	222	/* make sure the GSC-to-CSME proxy header is sane */
	223	ret = validate_proxy_header(&to_csme->proxy_header,
	224	GSC_PROXY_ADDRESSING_GSC,
	225	GSC_PROXY_ADDRESSING_CSME);
	226	if (ret) {
	227	gt_err(gt, "invalid GSC to CSME proxy header! %d\n", ret);
	228	goto proxy_error;
	229	}
	230
	231	/* send the GSC message to the CSME */
	232	ret = proxy_send_to_csme(gsc);
	233	if (ret < 0) {
	234	gt_err(gt, "failed to send proxy message to CSME! %d\n", ret);
	235	goto proxy_error;
	236	}
	237
	238	/* update the GSC message size with the returned value from CSME */
	239	to_gsc->header.message_size = ret + sizeof(struct intel_gsc_mtl_header);
	240
	241	/* make sure the CSME-to-GSC proxy header is sane */
	242	ret = validate_proxy_header(&to_gsc->proxy_header,
	243	GSC_PROXY_ADDRESSING_CSME,
	244	GSC_PROXY_ADDRESSING_GSC);
	245	if (ret) {
	246	gt_err(gt, "invalid CSME to GSC proxy header! %d\n", ret);
	247	goto proxy_error;
	248	}
	249	}
	250
	251	proxy_error:
	252	return ret < 0 ? ret : 0;
	253	}
	254
	255	int intel_gsc_proxy_request_handler(struct intel_gsc_uc *gsc)
	256	{
	257	struct intel_gt *gt = gsc_uc_to_gt(gsc);
	258	int err;
	259
	260	if (!gsc->proxy.component_added)
	261	return -ENODEV;
	262
	263	assert_rpm_wakelock_held(gt->uncore->rpm);
	264
	265	/* when GSC is loaded, we can queue this before the component is bound */
	266	err = wait_for(gsc->proxy.component, GSC_PROXY_INIT_TIMEOUT_MS);
	267	if (err) {
	268	gt_err(gt, "GSC proxy component didn't bind within the expected timeout\n");
	269	return -EIO;
	270	}
	271
	272	mutex_lock(&gsc->proxy.mutex);
	273	if (!gsc->proxy.component) {
	274	gt_err(gt, "GSC proxy worker called without the component being bound!\n");
	275	err = -EIO;
	276	} else {
	277	/*
	278	* write the status bit to clear it and allow new proxy
	279	* interrupts to be generated while we handle the current
	280	* request, but be sure not to write the reset bit
	281	*/
	282	intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE),
	283	HECI_H_CSR_RST, HECI_H_CSR_IS);
	284	err = proxy_query(gsc);
	285	}
	286	mutex_unlock(&gsc->proxy.mutex);
	287	return err;
	288	}
	289
	290	void intel_gsc_proxy_irq_handler(struct intel_gsc_uc *gsc, u32 iir)
	291	{
	292	struct intel_gt *gt = gsc_uc_to_gt(gsc);
	293
	294	if (unlikely(!iir))
	295	return;
	296
	297	lockdep_assert_held(gt->irq_lock);
	298
	299	if (!gsc->proxy.component) {
	300	gt_err(gt, "GSC proxy irq received without the component being bound!\n");
	301	return;
	302	}
	303
	304	gsc->gsc_work_actions \|= GSC_ACTION_SW_PROXY;
	305	queue_work(gsc->wq, &gsc->work);
	306	}
	307
	308	static int i915_gsc_proxy_component_bind(struct device *i915_kdev,
	309	struct device mei_kdev, void data)
	310	{
	311	struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
	312	struct intel_gt *gt = i915->media_gt;
	313	struct intel_gsc_uc *gsc = &gt->uc.gsc;
	314	intel_wakeref_t wakeref;
	315
	316	/* enable HECI2 IRQs */
	317	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
	318	intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE),
	319	HECI_H_CSR_RST, HECI_H_CSR_IE);
	320
	321	mutex_lock(&gsc->proxy.mutex);
	322	gsc->proxy.component = data;
	323	gsc->proxy.component->mei_dev = mei_kdev;
	324	mutex_unlock(&gsc->proxy.mutex);
	325
	326	return 0;
	327	}
	328
	329	static void i915_gsc_proxy_component_unbind(struct device *i915_kdev,
	330	struct device mei_kdev, void data)
	331	{
	332	struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
	333	struct intel_gt *gt = i915->media_gt;
	334	struct intel_gsc_uc *gsc = &gt->uc.gsc;
	335	intel_wakeref_t wakeref;
	336
	337	mutex_lock(&gsc->proxy.mutex);
	338	gsc->proxy.component = NULL;
	339	mutex_unlock(&gsc->proxy.mutex);
	340
	341	/* disable HECI2 IRQs */
	342	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
	343	intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE),
	344	HECI_H_CSR_IE \| HECI_H_CSR_RST, 0);
	345	}
	346
	347	static const struct component_ops i915_gsc_proxy_component_ops = {
	348	.bind = i915_gsc_proxy_component_bind,
	349	.unbind = i915_gsc_proxy_component_unbind,
	350	};
	351
	352	static int proxy_channel_alloc(struct intel_gsc_uc *gsc)
	353	{
	354	struct intel_gt *gt = gsc_uc_to_gt(gsc);
	355	struct i915_vma *vma;
	356	void *vaddr;
	357	int err;
	358
	359	err = intel_guc_allocate_and_map_vma(&gt->uc.guc, GSC_PROXY_CHANNEL_SIZE,
	360	&vma, &vaddr);
	361	if (err)
	362	return err;
	363
	364	gsc->proxy.vma = vma;
	365	gsc->proxy.to_gsc = vaddr;
	366	gsc->proxy.to_csme = vaddr + GSC_PROXY_BUFFER_SIZE;
	367
	368	return 0;
	369	}
	370
	371	static void proxy_channel_free(struct intel_gsc_uc *gsc)
	372	{
	373	if (!gsc->proxy.vma)
	374	return;
	375
	376	gsc->proxy.to_gsc = NULL;
	377	gsc->proxy.to_csme = NULL;
	378	i915_vma_unpin_and_release(&gsc->proxy.vma, I915_VMA_RELEASE_MAP);
	379	}
	380
	381	void intel_gsc_proxy_fini(struct intel_gsc_uc *gsc)
	382	{
	383	struct intel_gt *gt = gsc_uc_to_gt(gsc);
	384	struct drm_i915_private *i915 = gt->i915;
	385
	386	if (fetch_and_zero(&gsc->proxy.component_added))
	387	component_del(i915->drm.dev, &i915_gsc_proxy_component_ops);
	388
	389	proxy_channel_free(gsc);
	390	}
	391
	392	int intel_gsc_proxy_init(struct intel_gsc_uc *gsc)
	393	{
	394	int err;
	395	struct intel_gt *gt = gsc_uc_to_gt(gsc);
	396	struct drm_i915_private *i915 = gt->i915;
	397
	398	mutex_init(&gsc->proxy.mutex);
	399
	400	if (!IS_ENABLED(CONFIG_INTEL_MEI_GSC_PROXY)) {
	401	gt_info(gt, "can't init GSC proxy due to missing mei component\n");
	402	return -ENODEV;
	403	}
	404
	405	err = proxy_channel_alloc(gsc);
	406	if (err)
	407	return err;
	408
	409	err = component_add_typed(i915->drm.dev, &i915_gsc_proxy_component_ops,
	410	I915_COMPONENT_GSC_PROXY);
	411	if (err < 0) {
	412	gt_err(gt, "Failed to add GSC_PROXY component (%d)\n", err);
	413	goto out_free;
	414	}
	415
	416	gsc->proxy.component_added = true;
	417
	418	return 0;
	419
	420	out_free:
	421	proxy_channel_free(gsc);
	422	return err;
	423	}
	424

drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h+18−0

@@ -0,0 +1,18 @@
	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2023 Intel Corporation
	4	*/
	5
	6	#ifndef _INTEL_GSC_PROXY_H_
	7	#define _INTEL_GSC_PROXY_H_
	8
	9	#include <linux/types.h>
	10
	11	struct intel_gsc_uc;
	12
	13	int intel_gsc_proxy_init(struct intel_gsc_uc *gsc);
	14	void intel_gsc_proxy_fini(struct intel_gsc_uc *gsc);
	15	int intel_gsc_proxy_request_handler(struct intel_gsc_uc *gsc);
	16	void intel_gsc_proxy_irq_handler(struct intel_gsc_uc *gsc, u32 iir);
	17
	18	#endif

drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c+72−4

@@ -10,15 +10,60 @@ · 9 unmodified lines
10	#include "intel_gsc_uc.h"	10	#include "intel_gsc_uc.h"
11	#include "intel_gsc_fw.h"	11	#include "intel_gsc_fw.h"
12	#include "i915_drv.h"	12	#include "i915_drv.h"
		13	#include "intel_gsc_proxy.h"
13		14
14	static void gsc_work(struct work_struct *work)	15	static void gsc_work(struct work_struct *work)
15	{	16	{
16	struct intel_gsc_uc gsc = container_of(work, typeof(gsc), work);	17	struct intel_gsc_uc gsc = container_of(work, typeof(gsc), work);
17	struct intel_gt *gt = gsc_uc_to_gt(gsc);	18	struct intel_gt *gt = gsc_uc_to_gt(gsc);
18	intel_wakeref_t wakeref;	19	intel_wakeref_t wakeref;
		20	u32 actions;
		21	int ret;
		22
		23	wakeref = intel_runtime_pm_get(gt->uncore->rpm);
		24
		25	spin_lock_irq(gt->irq_lock);
		26	actions = gsc->gsc_work_actions;
		27	gsc->gsc_work_actions = 0;
		28	spin_unlock_irq(gt->irq_lock);
		29
		30	if (actions & GSC_ACTION_FW_LOAD) {
		31	ret = intel_gsc_uc_fw_upload(gsc);
		32	if (ret == -EEXIST) /* skip proxy if not a new load */
		33	actions &= ~GSC_ACTION_FW_LOAD;
		34	else if (ret)
		35	goto out_put;
		36	}
		37
		38	if (actions & (GSC_ACTION_FW_LOAD \| GSC_ACTION_SW_PROXY)) {
		39	if (!intel_gsc_uc_fw_init_done(gsc)) {
		40	gt_err(gt, "Proxy request received with GSC not loaded!\n");
		41	goto out_put;
		42	}
		43
		44	ret = intel_gsc_proxy_request_handler(gsc);
		45	if (ret)
		46	goto out_put;
		47
		48	/* mark the GSC FW init as done the first time we run this */
		49	if (actions & GSC_ACTION_FW_LOAD) {
		50	/*
		51	* If there is a proxy establishment error, the GSC might still
		52	* complete the request handling cleanly, so we need to check the
		53	* status register to check if the proxy init was actually successful
		54	*/
		55	if (intel_gsc_uc_fw_proxy_init_done(gsc)) {
		56	drm_dbg(&gt->i915->drm, "GSC Proxy initialized\n");
		57	intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_RUNNING);
		58	} else {
		59	drm_err(&gt->i915->drm,
		60	"GSC status reports proxy init not complete\n");
		61	}
		62	}
		63	}
19		64
20	with_intel_runtime_pm(gt->uncore->rpm, wakeref)	65	out_put:
21	intel_gsc_uc_fw_upload(gsc);	66	intel_runtime_pm_put(gt->uncore->rpm, wakeref);
22	}	67	}
23		68
24	static bool gsc_engine_supported(struct intel_gt *gt)	69	static bool gsc_engine_supported(struct intel_gt *gt)
@@ -43,6 +88,8 @@ static bool gsc_engine_supported(struct intel_gt *gt) · 18 unmodified lines
43		88
44	void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc)	89	void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc)
45	{	90	{
		91	struct intel_gt *gt = gsc_uc_to_gt(gsc);
		92
46	intel_uc_fw_init_early(&gsc->fw, INTEL_UC_FW_TYPE_GSC);	93	intel_uc_fw_init_early(&gsc->fw, INTEL_UC_FW_TYPE_GSC);
47	INIT_WORK(&gsc->work, gsc_work);	94	INIT_WORK(&gsc->work, gsc_work);
48		95
@@ -50,10 +97,16 @@ void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc) · 1 unmodified line
50	* GT with it being not fully setup hence check device info's	97	* GT with it being not fully setup hence check device info's
51	* engine mask	98	* engine mask
52	*/	99	*/
53	if (!gsc_engine_supported(gsc_uc_to_gt(gsc))) {	100	if (!gsc_engine_supported(gt)) {
54	intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_NOT_SUPPORTED);	101	intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_NOT_SUPPORTED);
55	return;	102	return;
56	}	103	}
		104
		105	gsc->wq = alloc_ordered_workqueue("i915_gsc", 0);
		106	if (!gsc->wq) {
		107	gt_err(gt, "failed to allocate WQ for GSC, disabling FW\n");
		108	intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_NOT_SUPPORTED);
		109	}
57	}	110	}
58		111
59	int intel_gsc_uc_init(struct intel_gsc_uc *gsc)	112	int intel_gsc_uc_init(struct intel_gsc_uc *gsc)
@@ -88,6 +141,9 @@ int intel_gsc_uc_init(struct intel_gsc_uc *gsc) · 28 unmodified lines
88		141
89	gsc->ce = ce;	142	gsc->ce = ce;
90		143
		144	/* if we fail to init proxy we still want to load GSC for PM */
		145	intel_gsc_proxy_init(gsc);
		146
91	intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_LOADABLE);	147	intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_LOADABLE);
92		148
93	return 0;	149	return 0;
@@ -107,6 +163,12 @@ void intel_gsc_uc_fini(struct intel_gsc_uc *gsc) · 13 unmodified lines
107	return;	163	return;
108		164
109	flush_work(&gsc->work);	165	flush_work(&gsc->work);
		166	if (gsc->wq) {
		167	destroy_workqueue(gsc->wq);
		168	gsc->wq = NULL;
		169	}
		170
		171	intel_gsc_proxy_fini(gsc);
110		172
111	if (gsc->ce)	173	if (gsc->ce)
112	intel_engine_destroy_pinned_context(fetch_and_zero(&gsc->ce));	174	intel_engine_destroy_pinned_context(fetch_and_zero(&gsc->ce));
@@ -145,11 +207,17 @@ void intel_gsc_uc_resume(struct intel_gsc_uc *gsc) · 32 unmodified lines
145		207
146	void intel_gsc_uc_load_start(struct intel_gsc_uc *gsc)	208	void intel_gsc_uc_load_start(struct intel_gsc_uc *gsc)
147	{	209	{
		210	struct intel_gt *gt = gsc_uc_to_gt(gsc);
		211
148	if (!intel_uc_fw_is_loadable(&gsc->fw))	212	if (!intel_uc_fw_is_loadable(&gsc->fw))
149	return;	213	return;
150		214
151	if (intel_gsc_uc_fw_init_done(gsc))	215	if (intel_gsc_uc_fw_init_done(gsc))
152	return;	216	return;
153		217
154	queue_work(system_unbound_wq, &gsc->work);	218	spin_lock_irq(gt->irq_lock);
		219	gsc->gsc_work_actions \|= GSC_ACTION_FW_LOAD;
		220	spin_unlock_irq(gt->irq_lock);
		221
		222	queue_work(gsc->wq, &gsc->work);
155	}	223	}

drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h+16−1

@@ -10,6 +10,7 @@ · 9 unmodified lines
10		10
11	struct i915_vma;	11	struct i915_vma;
12	struct intel_context;	12	struct intel_context;
		13	struct i915_gsc_proxy_component;
13		14
14	struct intel_gsc_uc {	15	struct intel_gsc_uc {
15	/* Generic uC firmware management */	16	/* Generic uC firmware management */
@@ -19,7 +20,21 @@ struct intel_gsc_uc { · 3 unmodified lines
19	struct i915_vma local; / private memory for GSC usage */	20	struct i915_vma local; / private memory for GSC usage */
20	struct intel_context ce; / for submission to GSC FW via GSC engine */	21	struct intel_context ce; / for submission to GSC FW via GSC engine */
21		22
22	struct work_struct work; /* for delayed load */	23	/* for delayed load and proxy handling */
		24	struct workqueue_struct *wq;
		25	struct work_struct work;
		26	u32 gsc_work_actions; /* protected by gt->irq_lock */
		27	#define GSC_ACTION_FW_LOAD BIT(0)
		28	#define GSC_ACTION_SW_PROXY BIT(1)
		29
		30	struct {
		31	struct i915_gsc_proxy_component *component;
		32	bool component_added;
		33	struct i915_vma *vma;
		34	void *to_gsc;
		35	void *to_csme;
		36	struct mutex mutex; /* protects the tee channel binding */
		37	} proxy;
23	};	38	};
24		39
25	void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc);	40	void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc);

drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c+102−0

@@ -3,6 +3,7 @@ · 2 unmodified lines
3	* Copyright © 2023 Intel Corporation	3	* Copyright © 2023 Intel Corporation
4	*/	4	*/
5		5
		6	#include "gt/intel_context.h"
6	#include "gt/intel_engine_pm.h"	7	#include "gt/intel_engine_pm.h"
7	#include "gt/intel_gpu_commands.h"	8	#include "gt/intel_gpu_commands.h"
8	#include "gt/intel_gt.h"	9	#include "gt/intel_gt.h"
@@ -107,3 +108,104 @@ void intel_gsc_uc_heci_cmd_emit_mtl_header(struct intel_gsc_mtl_header *header, · 98 unmodified lines
107	header->header_version = MTL_GSC_HEADER_VERSION;	108	header->header_version = MTL_GSC_HEADER_VERSION;
108	header->message_size = message_size;	109	header->message_size = message_size;
109	}	110	}
		111
		112	static void
		113	emit_gsc_heci_pkt_nonpriv(u32 cmd, struct intel_gsc_heci_non_priv_pkt pkt)
		114	{
		115	*cmd++ = GSC_HECI_CMD_PKT;
		116	*cmd++ = lower_32_bits(pkt->addr_in);
		117	*cmd++ = upper_32_bits(pkt->addr_in);
		118	*cmd++ = pkt->size_in;
		119	*cmd++ = lower_32_bits(pkt->addr_out);
		120	*cmd++ = upper_32_bits(pkt->addr_out);
		121	*cmd++ = pkt->size_out;
		122	*cmd++ = 0;
		123	*cmd++ = MI_BATCH_BUFFER_END;
		124	}
		125
		126	int
		127	intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc,
		128	struct intel_context *ce,
		129	struct intel_gsc_heci_non_priv_pkt *pkt,
		130	u32 *cmd, int timeout_ms)
		131	{
		132	struct intel_engine_cs *engine;
		133	struct i915_gem_ww_ctx ww;
		134	struct i915_request *rq;
		135	int err, trials = 0;
		136
		137	i915_gem_ww_ctx_init(&ww, false);
		138	retry:
		139	err = i915_gem_object_lock(pkt->bb_vma->obj, &ww);
		140	if (err)
		141	goto out_ww;
		142	err = i915_gem_object_lock(pkt->heci_pkt_vma->obj, &ww);
		143	if (err)
		144	goto out_ww;
		145	err = intel_context_pin_ww(ce, &ww);
		146	if (err)
		147	goto out_ww;
		148
		149	rq = i915_request_create(ce);
		150	if (IS_ERR(rq)) {
		151	err = PTR_ERR(rq);
		152	goto out_unpin_ce;
		153	}
		154
		155	emit_gsc_heci_pkt_nonpriv(cmd, pkt);
		156
		157	err = i915_vma_move_to_active(pkt->bb_vma, rq, 0);
		158	if (err)
		159	goto out_rq;
		160	err = i915_vma_move_to_active(pkt->heci_pkt_vma, rq, EXEC_OBJECT_WRITE);
		161	if (err)
		162	goto out_rq;
		163
		164	engine = rq->context->engine;
		165	if (engine->emit_init_breadcrumb) {
		166	err = engine->emit_init_breadcrumb(rq);
		167	if (err)
		168	goto out_rq;
		169	}
		170
		171	err = engine->emit_bb_start(rq, i915_vma_offset(pkt->bb_vma), PAGE_SIZE, 0);
		172	if (err)
		173	goto out_rq;
		174
		175	err = ce->engine->emit_flush(rq, 0);
		176	if (err)
		177	drm_err(&gsc_uc_to_gt(gsc)->i915->drm,
		178	"Failed emit-flush for gsc-heci-non-priv-pkterr=%d\n", err);
		179
		180	out_rq:
		181	i915_request_get(rq);
		182
		183	if (unlikely(err))
		184	i915_request_set_error_once(rq, err);
		185
		186	i915_request_add(rq);
		187
		188	if (!err) {
		189	if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
		190	msecs_to_jiffies(timeout_ms)) < 0)
		191	err = -ETIME;
		192	}
		193
		194	i915_request_put(rq);
		195
		196	out_unpin_ce:
		197	intel_context_unpin(ce);
		198	out_ww:
		199	if (err == -EDEADLK) {
		200	err = i915_gem_ww_ctx_backoff(&ww);
		201	if (!err) {
		202	if (++trials < 10)
		203	goto retry;
		204	else
		205	err = EAGAIN;
		206	}
		207	}
		208	i915_gem_ww_ctx_fini(&ww);
		209
		210	return err;
		211	}

drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h+26−1

@@ -8,12 +8,16 @@ · 7 unmodified lines
8		8
9	#include <linux/types.h>	9	#include <linux/types.h>
10		10
		11	struct i915_vma;
		12	struct intel_context;
11	struct intel_gsc_uc;	13	struct intel_gsc_uc;
		14
12	struct intel_gsc_mtl_header {	15	struct intel_gsc_mtl_header {
13	u32 validity_marker;	16	u32 validity_marker;
14	#define GSC_HECI_VALIDITY_MARKER 0xA578875A	17	#define GSC_HECI_VALIDITY_MARKER 0xA578875A
15		18
16	u8 heci_client_id;	19	u8 heci_client_id;
		20	#define HECI_MEADDRESS_PROXY 10
17	#define HECI_MEADDRESS_PXP 17	21	#define HECI_MEADDRESS_PXP 17
18	#define HECI_MEADDRESS_HDCP 18	22	#define HECI_MEADDRESS_HDCP 18
19		23
@@ -47,7 +51,8 @@ struct intel_gsc_mtl_header { · 27 unmodified lines
47	* we distinguish the flags using OUTFLAG or INFLAG	51	* we distinguish the flags using OUTFLAG or INFLAG
48	*/	52	*/
49	u32 flags;	53	u32 flags;
50	#define GSC_OUTFLAG_MSG_PENDING 1	54	#define GSC_OUTFLAG_MSG_PENDING BIT(0)
		55	#define GSC_INFLAG_MSG_CLEANUP BIT(1)
51		56
52	u32 status;	57	u32 status;
53	} __packed;	58	} __packed;
@@ -58,4 +63,24 @@ int intel_gsc_uc_heci_cmd_submit_packet(struct intel_gsc_uc *gsc, · 4 unmodified lines
58	void intel_gsc_uc_heci_cmd_emit_mtl_header(struct intel_gsc_mtl_header *header,	63	void intel_gsc_uc_heci_cmd_emit_mtl_header(struct intel_gsc_mtl_header *header,
59	u8 heci_client_id, u32 message_size,	64	u8 heci_client_id, u32 message_size,
60	u64 host_session_id);	65	u64 host_session_id);
		66
		67	struct intel_gsc_heci_non_priv_pkt {
		68	u64 addr_in;
		69	u32 size_in;
		70	u64 addr_out;
		71	u32 size_out;
		72	struct i915_vma *heci_pkt_vma;
		73	struct i915_vma *bb_vma;
		74	};
		75
		76	void
		77	intel_gsc_uc_heci_cmd_emit_mtl_header(struct intel_gsc_mtl_header *header,
		78	u8 heci_client_id, u32 msg_size,
		79	u64 host_session_id);
		80
		81	int
		82	intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc,
		83	struct intel_context *ce,
		84	struct intel_gsc_heci_non_priv_pkt *pkt,
		85	u32 *cs, int timeout_ms);
61	#endif	86	#endif

drivers/gpu/drm/i915/gt/uc/intel_guc.c+7−0

@@ -744,6 +744,13 @@ struct i915_vma intel_guc_allocate_vma(struct intel_guc guc, u32 size) · 743 unmodified lines
744	if (IS_ERR(obj))	744	if (IS_ERR(obj))
745	return ERR_CAST(obj);	745	return ERR_CAST(obj);
746		746
		747	/*
		748	* Wa_22016122933: For MTL the shared memory needs to be mapped
		749	* as WC on CPU side and UC (PAT index 2) on GPU side
		750	*/
		751	if (IS_METEORLAKE(gt->i915))
		752	i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
		753
747	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);	754	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
748	if (IS_ERR(vma))	755	if (IS_ERR(vma))
749	goto err;	756	goto err;

drivers/gpu/drm/i915/gt/uc/intel_guc.h+1−0

@@ -42,6 +42,7 @@ struct intel_guc { · 41 unmodified lines
42	/** @capture: the error-state-capture module's data and objects */	42	/** @capture: the error-state-capture module's data and objects */
43	struct intel_guc_state_capture *capture;	43	struct intel_guc_state_capture *capture;
44		44
		45	/** @dbgfs_node: debugfs node */
45	struct dentry *dbgfs_node;	46	struct dentry *dbgfs_node;
46		47
47	/** @sched_engine: Global engine used to submit requests to GuC */	48	/** @sched_engine: Global engine used to submit requests to GuC */

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c+35−1

@@ -643,6 +643,39 @@ static void guc_init_golden_context(struct intel_guc *guc) · 642 unmodified lines
643	GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size);	643	GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size);
644	}	644	}
645		645
		646	static u32 guc_get_capture_engine_mask(struct iosys_map *info_map, u32 capture_class)
		647	{
		648	u32 mask;
		649
		650	switch (capture_class) {
		651	case GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE:
		652	mask = info_map_read(info_map, engine_enabled_masks[GUC_RENDER_CLASS]);
		653	mask \|= info_map_read(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS]);
		654	break;
		655
		656	case GUC_CAPTURE_LIST_CLASS_VIDEO:
		657	mask = info_map_read(info_map, engine_enabled_masks[GUC_VIDEO_CLASS]);
		658	break;
		659
		660	case GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE:
		661	mask = info_map_read(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS]);
		662	break;
		663
		664	case GUC_CAPTURE_LIST_CLASS_BLITTER:
		665	mask = info_map_read(info_map, engine_enabled_masks[GUC_BLITTER_CLASS]);
		666	break;
		667
		668	case GUC_CAPTURE_LIST_CLASS_GSC_OTHER:
		669	mask = info_map_read(info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS]);
		670	break;
		671
		672	default:
		673	mask = 0;
		674	}
		675
		676	return mask;
		677	}
		678
646	static int	679	static int
647	guc_capture_prep_lists(struct intel_guc *guc)	680	guc_capture_prep_lists(struct intel_guc *guc)
648	{	681	{
@@ -678,9 +711,10 @@ guc_capture_prep_lists(struct intel_guc *guc) · 29 unmodified lines
678		711
679	for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) {	712	for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) {
680	for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) {	713	for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) {
		714	u32 engine_mask = guc_get_capture_engine_mask(&info_map, j);
681		715
682	/* null list if we dont have said engine or list */	716	/* null list if we dont have said engine or list */
683	if (!info_map_read(&info_map, engine_enabled_masks[j])) {	717	if (!engine_mask) {
684	if (ads_is_mapped) {	718	if (ads_is_mapped) {
685	ads_blob_write(guc, ads.capture_class[i][j], null_ggtt);	719	ads_blob_write(guc, ads.capture_class[i][j], null_ggtt);
686	ads_blob_write(guc, ads.capture_instance[i][j], null_ggtt);	720	ads_blob_write(guc, ads.capture_instance[i][j], null_ggtt);

drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c+121−148

@@ -30,13 +30,15 @@ · 29 unmodified lines
30	#define COMMON_BASE_GLOBAL \	30	#define COMMON_BASE_GLOBAL \
31	{ FORCEWAKE_MT, 0, 0, "FORCEWAKE" }	31	{ FORCEWAKE_MT, 0, 0, "FORCEWAKE" }
32		32
33	#define COMMON_GEN9BASE_GLOBAL \	33	#define COMMON_GEN8BASE_GLOBAL \
34	{ GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
35	{ GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }, \
36	{ ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \	34	{ ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \
37	{ DONE_REG, 0, 0, "DONE_REG" }, \	35	{ DONE_REG, 0, 0, "DONE_REG" }, \
38	{ HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" }	36	{ HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" }
39		37
		38	#define GEN8_GLOBAL \
		39	{ GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
		40	{ GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }
		41
40	#define COMMON_GEN12BASE_GLOBAL \	42	#define COMMON_GEN12BASE_GLOBAL \
41	{ GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \	43	{ GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \
42	{ GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \	44	{ GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \
@@ -94,66 +96,65 @@ · 51 unmodified lines
94	{ GEN12_SFC_DONE(2), 0, 0, "SFC_DONE[2]" }, \	96	{ GEN12_SFC_DONE(2), 0, 0, "SFC_DONE[2]" }, \
95	{ GEN12_SFC_DONE(3), 0, 0, "SFC_DONE[3]" }	97	{ GEN12_SFC_DONE(3), 0, 0, "SFC_DONE[3]" }
96		98
97	/* XE_LPD - Global */	99	/* XE_LP Global */
98	static const struct __guc_mmio_reg_descr xe_lpd_global_regs[] = {	100	static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
99	COMMON_BASE_GLOBAL,	101	COMMON_BASE_GLOBAL,
100	COMMON_GEN9BASE_GLOBAL,	102	COMMON_GEN8BASE_GLOBAL,
101	COMMON_GEN12BASE_GLOBAL,	103	COMMON_GEN12BASE_GLOBAL,
102	};	104	};
103		105
104	/* XE_LPD - Render / Compute Per-Class */	106	/* XE_LP Render / Compute Per-Class */
105	static const struct __guc_mmio_reg_descr xe_lpd_rc_class_regs[] = {	107	static const struct __guc_mmio_reg_descr xe_lp_rc_class_regs[] = {
106	COMMON_BASE_HAS_EU,	108	COMMON_BASE_HAS_EU,
107	COMMON_BASE_RENDER,	109	COMMON_BASE_RENDER,
108	COMMON_GEN12BASE_RENDER,	110	COMMON_GEN12BASE_RENDER,
109	};	111	};
110		112
111	/* GEN9/XE_LPD - Render / Compute Per-Engine-Instance */	113	/* GEN8+ Render / Compute Per-Engine-Instance */
112	static const struct __guc_mmio_reg_descr xe_lpd_rc_inst_regs[] = {	114	static const struct __guc_mmio_reg_descr gen8_rc_inst_regs[] = {
113	COMMON_BASE_ENGINE_INSTANCE,	115	COMMON_BASE_ENGINE_INSTANCE,
114	};	116	};
115		117
116	/* GEN9/XE_LPD - Media Decode/Encode Per-Engine-Instance */	118	/* GEN8+ Media Decode/Encode Per-Engine-Instance */
117	static const struct __guc_mmio_reg_descr xe_lpd_vd_inst_regs[] = {	119	static const struct __guc_mmio_reg_descr gen8_vd_inst_regs[] = {
118	COMMON_BASE_ENGINE_INSTANCE,	120	COMMON_BASE_ENGINE_INSTANCE,
119	};	121	};
120		122
121	/* XE_LPD - Video Enhancement Per-Class */	123	/* XE_LP Video Enhancement Per-Class */
122	static const struct __guc_mmio_reg_descr xe_lpd_vec_class_regs[] = {	124	static const struct __guc_mmio_reg_descr xe_lp_vec_class_regs[] = {
123	COMMON_GEN12BASE_VEC,	125	COMMON_GEN12BASE_VEC,
124	};	126	};
125		127
126	/* GEN9/XE_LPD - Video Enhancement Per-Engine-Instance */	128	/* GEN8+ Video Enhancement Per-Engine-Instance */
127	static const struct __guc_mmio_reg_descr xe_lpd_vec_inst_regs[] = {	129	static const struct __guc_mmio_reg_descr gen8_vec_inst_regs[] = {
128	COMMON_BASE_ENGINE_INSTANCE,	130	COMMON_BASE_ENGINE_INSTANCE,
129	};	131	};
130		132
131	/* GEN9/XE_LPD - Blitter Per-Engine-Instance */	133	/* GEN8+ Blitter Per-Engine-Instance */
132	static const struct __guc_mmio_reg_descr xe_lpd_blt_inst_regs[] = {	134	static const struct __guc_mmio_reg_descr gen8_blt_inst_regs[] = {
133	COMMON_BASE_ENGINE_INSTANCE,	135	COMMON_BASE_ENGINE_INSTANCE,
134	};	136	};
135		137
136	/* XE_LPD - GSC Per-Engine-Instance */	138	/* XE_LP - GSC Per-Engine-Instance */
137	static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = {	139	static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
138	COMMON_BASE_ENGINE_INSTANCE,	140	COMMON_BASE_ENGINE_INSTANCE,
139	};	141	};
140		142
141	/* GEN9 - Global */	143	/* GEN8 - Global */
142	static const struct __guc_mmio_reg_descr default_global_regs[] = {	144	static const struct __guc_mmio_reg_descr gen8_global_regs[] = {
143	COMMON_BASE_GLOBAL,	145	COMMON_BASE_GLOBAL,
144	COMMON_GEN9BASE_GLOBAL,	146	COMMON_GEN8BASE_GLOBAL,
		147	GEN8_GLOBAL,
145	};	148	};
146		149
147	static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {	150	static const struct __guc_mmio_reg_descr gen8_rc_class_regs[] = {
148	COMMON_BASE_HAS_EU,	151	COMMON_BASE_HAS_EU,
149	COMMON_BASE_RENDER,	152	COMMON_BASE_RENDER,
150	};	153	};
151		154
152	/*	155	/*
153	* Empty lists:	156	* Empty list to prevent warnings about unknown class/instance types
154	* GEN9/XE_LPD - Blitter Per-Class	157	* as not all class/instanace types have entries on all platforms.
155	* GEN9/XE_LPD - Media Decode/Encode Per-Class
156	* GEN9 - VEC Class
157	*/	158	*/
158	static const struct __guc_mmio_reg_descr empty_regs_list[] = {	159	static const struct __guc_mmio_reg_descr empty_regs_list[] = {
159	};	160	};
@@ -171,37 +172,33 @@ static const struct __guc_mmio_reg_descr empty_regs_list[] = { · 11 unmodified lines
171	}	172	}
172		173
173	/* List of lists */	174	/* List of lists */
174	static const struct __guc_mmio_reg_descr_group default_lists[] = {	175	static const struct __guc_mmio_reg_descr_group gen8_lists[] = {
175	MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0),	176	MAKE_REGLIST(gen8_global_regs, PF, GLOBAL, 0),
176	MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),	177	MAKE_REGLIST(gen8_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
177	MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS),	178	MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
178	MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS),	179	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
179	MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS),	180	MAKE_REGLIST(gen8_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
180	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS),	181	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
181	MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS),	182	MAKE_REGLIST(gen8_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
182	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS),	183	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
183	MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS),	184	MAKE_REGLIST(gen8_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
184	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS),	185	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
185	MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS),	186	MAKE_REGLIST(empty_regs_list, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
186	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS),
187	MAKE_REGLIST(xe_lpd_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS),
188	{}	187	{}
189	};	188	};
190		189
191	static const struct __guc_mmio_reg_descr_group xe_lpd_lists[] = {	190	static const struct __guc_mmio_reg_descr_group xe_lp_lists[] = {
192	MAKE_REGLIST(xe_lpd_global_regs, PF, GLOBAL, 0),	191	MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
193	MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),	192	MAKE_REGLIST(xe_lp_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
194	MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS),	193	MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
195	MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS),	194	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
196	MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS),	195	MAKE_REGLIST(gen8_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
197	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS),	196	MAKE_REGLIST(xe_lp_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
198	MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS),	197	MAKE_REGLIST(gen8_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
199	MAKE_REGLIST(xe_lpd_vec_class_regs, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS),	198	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
200	MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS),	199	MAKE_REGLIST(gen8_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
201	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS),	200	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
202	MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS),	201	MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
203	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS),
204	MAKE_REGLIST(xe_lpd_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS),
205	{}	202	{}
206	};	203	};
207		204
@@ -257,11 +254,15 @@ struct __ext_steer_reg { · 49 unmodified lines
257	i915_mcr_reg_t reg;	254	i915_mcr_reg_t reg;
258	};	255	};
259		256
260	static const struct __ext_steer_reg xe_extregs[] = {	257	static const struct __ext_steer_reg gen8_extregs[] = {
261	{"GEN8_SAMPLER_INSTDONE", GEN8_SAMPLER_INSTDONE},	258	{"GEN8_SAMPLER_INSTDONE", GEN8_SAMPLER_INSTDONE},
262	{"GEN8_ROW_INSTDONE", GEN8_ROW_INSTDONE}	259	{"GEN8_ROW_INSTDONE", GEN8_ROW_INSTDONE}
263	};	260	};
264		261
		262	static const struct __ext_steer_reg xehpg_extregs[] = {
		263	{"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG}
		264	};
		265
265	static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,	266	static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
266	const struct __ext_steer_reg *extlist,	267	const struct __ext_steer_reg *extlist,
267	int slice_id, int subslice_id)	268	int slice_id, int subslice_id)
@@ -292,8 +293,8 @@ __alloc_ext_regs(struct __guc_mmio_reg_descr_group *newlist, · 24 unmodified lines
292	}	293	}
293		294
294	static void	295	static void
295	guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc *guc,	296	guc_capture_alloc_steered_lists(struct intel_guc *guc,
296	const struct __guc_mmio_reg_descr_group *lists)	297	const struct __guc_mmio_reg_descr_group *lists)
297	{	298	{
298	struct intel_gt *gt = guc_to_gt(guc);	299	struct intel_gt *gt = guc_to_gt(guc);
299	int slice, subslice, iter, i, num_steer_regs, num_tot_regs = 0;	300	int slice, subslice, iter, i, num_steer_regs, num_tot_regs = 0;
@@ -301,74 +302,20 @@ guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc *guc, · 1 unmodified line
301	struct __guc_mmio_reg_descr_group *extlists;	302	struct __guc_mmio_reg_descr_group *extlists;
302	struct __guc_mmio_reg_descr *extarray;	303	struct __guc_mmio_reg_descr *extarray;
303	struct sseu_dev_info *sseu;	304	struct sseu_dev_info *sseu;
		305	bool has_xehpg_extregs;
304		306
305	/* In XE_LPD we only have steered registers for the render-class */	307	/* steered registers currently only exist for the render-class */
306	list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF,	308	list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF,
307	GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS);	309	GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,
		310	GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE);
308	/* skip if extlists was previously allocated */	311	/* skip if extlists was previously allocated */
309	if (!list \|\| guc->capture->extlists)	312	if (!list \|\| guc->capture->extlists)
310	return;	313	return;
311		314
312	num_steer_regs = ARRAY_SIZE(xe_extregs);	315	has_xehpg_extregs = GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55);
313
314	sseu = &gt->info.sseu;
315	for_each_ss_steering(iter, gt, slice, subslice)
316	num_tot_regs += num_steer_regs;
317
318	if (!num_tot_regs)
319	return;
320
321	/* allocate an extra for an end marker */
322	extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL);
323	if (!extlists)
324	return;
325		316
326	if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) {	317	num_steer_regs = ARRAY_SIZE(gen8_extregs);
327	kfree(extlists);	318	if (has_xehpg_extregs)
328	return;
329	}
330
331	extarray = extlists[0].extlist;
332	for_each_ss_steering(iter, gt, slice, subslice) {
333	for (i = 0; i < num_steer_regs; ++i) {
334	__fill_ext_reg(extarray, &xe_extregs[i], slice, subslice);
335	++extarray;
336	}
337	}
338
339	guc->capture->extlists = extlists;
340	}
341
342	static const struct __ext_steer_reg xehpg_extregs[] = {
343	{"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG}
344	};
345
346	static bool __has_xehpg_extregs(u32 ipver)
347	{
348	return (ipver >= IP_VER(12, 55));
349	}
350
351	static void
352	guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
353	const struct __guc_mmio_reg_descr_group *lists,
354	u32 ipver)
355	{
356	struct intel_gt *gt = guc_to_gt(guc);
357	struct sseu_dev_info *sseu;
358	int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0;
359	const struct __guc_mmio_reg_descr_group *list;
360	struct __guc_mmio_reg_descr_group *extlists;
361	struct __guc_mmio_reg_descr *extarray;
362
363	/* In XE_LP / HPG we only have render-class steering registers during error-capture */
364	list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF,
365	GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS);
366	/* skip if extlists was previously allocated */
367	if (!list \|\| guc->capture->extlists)
368	return;
369
370	num_steer_regs = ARRAY_SIZE(xe_extregs);
371	if (__has_xehpg_extregs(ipver))
372	num_steer_regs += ARRAY_SIZE(xehpg_extregs);	319	num_steer_regs += ARRAY_SIZE(xehpg_extregs);
373		320
374	sseu = &gt->info.sseu;	321	sseu = &gt->info.sseu;
@@ -390,11 +337,12 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc, · 15 unmodified lines
390		337
391	extarray = extlists[0].extlist;	338	extarray = extlists[0].extlist;
392	for_each_ss_steering(iter, gt, slice, subslice) {	339	for_each_ss_steering(iter, gt, slice, subslice) {
393	for (i = 0; i < ARRAY_SIZE(xe_extregs); ++i) {	340	for (i = 0; i < ARRAY_SIZE(gen8_extregs); ++i) {
394	__fill_ext_reg(extarray, &xe_extregs[i], slice, subslice);	341	__fill_ext_reg(extarray, &gen8_extregs[i], slice, subslice);
395	++extarray;	342	++extarray;
396	}	343	}
397	if (__has_xehpg_extregs(ipver)) {	344
		345	if (has_xehpg_extregs) {
398	for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) {	346	for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) {
399	__fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice);	347	__fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice);
400	++extarray;	348	++extarray;
@@ -410,26 +358,22 @@ static const struct __guc_mmio_reg_descr_group * · 9 unmodified lines
410	guc_capture_get_device_reglist(struct intel_guc *guc)	358	guc_capture_get_device_reglist(struct intel_guc *guc)
411	{	359	{
412	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;	360	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
		361	const struct __guc_mmio_reg_descr_group *lists;
413		362
414	if (GRAPHICS_VER(i915) > 11) {	363	if (GRAPHICS_VER(i915) >= 12)
415	/*	364	lists = xe_lp_lists;
416	* For certain engine classes, there are slice and subslice	365	else
417	* level registers requiring steering. We allocate and populate	366	lists = gen8_lists;
418	* these at init time based on hw config add it as an extension
419	* list at the end of the pre-populated render list.
420	*/
421	if (IS_DG2(i915))
422	guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 55));
423	else if (IS_XEHPSDV(i915))
424	guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 50));
425	else
426	guc_capture_alloc_steered_lists_xe_lpd(guc, xe_lpd_lists);
427		367
428	return xe_lpd_lists;	368	/*
429	}	369	* For certain engine classes, there are slice and subslice
		370	* level registers requiring steering. We allocate and populate
		371	* these at init time based on hw config add it as an extension
		372	* list at the end of the pre-populated render list.
		373	*/
		374	guc_capture_alloc_steered_lists(guc, lists);
430		375
431	/* if GuC submission is enabled on a non-POR platform, just use a common baseline */	376	return lists;
432	return default_lists;
433	}	377	}
434		378
435	static const char *	379	static const char *
@@ -453,17 +397,15 @@ static const char * · 17 unmodified lines
453	__stringify_engclass(u32 class)	397	__stringify_engclass(u32 class)
454	{	398	{
455	switch (class) {	399	switch (class) {
456	case GUC_RENDER_CLASS:	400	case GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE:
457	return "Render";	401	return "Render/Compute";
458	case GUC_VIDEO_CLASS:	402	case GUC_CAPTURE_LIST_CLASS_VIDEO:
459	return "Video";	403	return "Video";
460	case GUC_VIDEOENHANCE_CLASS:	404	case GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE:
461	return "VideoEnhance";	405	return "VideoEnhance";
462	case GUC_BLITTER_CLASS:	406	case GUC_CAPTURE_LIST_CLASS_BLITTER:
463	return "Blitter";	407	return "Blitter";
464	case GUC_COMPUTE_CLASS:	408	case GUC_CAPTURE_LIST_CLASS_GSC_OTHER:
465	return "Compute";
466	case GUC_GSC_OTHER_CLASS:
467	return "GSC-Other";	409	return "GSC-Other";
468	default:	410	default:
469	break;	411	break;
@@ -1593,6 +1535,36 @@ void intel_guc_capture_free_node(struct intel_engine_coredump *ee) · 1123 unmodified lines
1593	ee->guc_capture_node = NULL;	1535	ee->guc_capture_node = NULL;
1594	}	1536	}
1595		1537
		1538	bool intel_guc_capture_is_matching_engine(struct intel_gt *gt,
		1539	struct intel_context *ce,
		1540	struct intel_engine_cs *engine)
		1541	{
		1542	struct __guc_capture_parsed_output *n;
		1543	struct intel_guc *guc;
		1544
		1545	if (!gt \|\| !ce \|\| !engine)
		1546	return false;
		1547
		1548	guc = &gt->uc.guc;
		1549	if (!guc->capture)
		1550	return false;
		1551
		1552	/*
		1553	* Look for a matching GuC reported error capture node from
		1554	* the internal output link-list based on lrca, guc-id and engine
		1555	* identification.
		1556	*/
		1557	list_for_each_entry(n, &guc->capture->outlist, link) {
		1558	if (n->eng_inst == GUC_ID_TO_ENGINE_INSTANCE(engine->guc_id) &&
		1559	n->eng_class == GUC_ID_TO_ENGINE_CLASS(engine->guc_id) &&
		1560	n->guc_id == ce->guc_id.id &&
		1561	(n->lrca & CTX_GTT_ADDRESS_MASK) == (ce->lrc.lrca & CTX_GTT_ADDRESS_MASK))
		1562	return true;
		1563	}
		1564
		1565	return false;
		1566	}
		1567
1596	void intel_guc_capture_get_matching_node(struct intel_gt *gt,	1568	void intel_guc_capture_get_matching_node(struct intel_gt *gt,
1597	struct intel_engine_coredump *ee,	1569	struct intel_engine_coredump *ee,
1598	struct intel_context *ce)	1570	struct intel_context *ce)
@@ -1608,6 +1580,7 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt, · 9 unmodified lines
1608	return;	1580	return;
1609		1581
1610	GEM_BUG_ON(ee->guc_capture_node);	1582	GEM_BUG_ON(ee->guc_capture_node);
		1583
1611	/*	1584	/*
1612	* Look for a matching GuC reported error capture node from	1585	* Look for a matching GuC reported error capture node from
1613	* the internal output link-list based on lrca, guc-id and engine	1586	* the internal output link-list based on lrca, guc-id and engine

drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h+3−0

 struct drm_i915_error_state_buf;
 struct guc_gt_system_info;
 struct intel_engine_coredump;
+struct intel_engine_cs;
 struct intel_context;
 struct intel_gt;
 struct intel_guc;
 					const struct intel_engine_coredump *ee);
 void intel_guc_capture_get_matching_node(struct intel_gt *gt, struct intel_engine_coredump *ee,
 					 struct intel_context *ce);
+bool intel_guc_capture_is_matching_engine(struct intel_gt *gt, struct intel_context *ce,
+					  struct intel_engine_cs *engine);
 void intel_guc_capture_process(struct intel_guc *guc);
 int intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
 			      void **outptr);

drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c+59−0

 #include "intel_guc_ct.h"
 #include "intel_guc_print.h"
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
+enum {
+	CT_DEAD_ALIVE = 0,
+	CT_DEAD_SETUP,
+	CT_DEAD_WRITE,
+	CT_DEAD_DEADLOCK,
+	CT_DEAD_H2G_HAS_ROOM,
+	CT_DEAD_READ,
+	CT_DEAD_PROCESS_FAILED,
+};
+static void ct_dead_ct_worker_func(struct work_struct *w);
+#define CT_DEAD(ct, reason)	\
+	do { \
+		if (!(ct)->dead_ct_reported) { \
+			(ct)->dead_ct_reason |= 1 << CT_DEAD_##reason; \
+			queue_work(system_unbound_wq, &(ct)->dead_ct_worker); \
+		} \
+	} while (0)
+#else
+#define CT_DEAD(ct, reason)	do { } while (0)
+#endif
 static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
 {
 	return container_of(ct, struct intel_guc, ct);
 	spin_lock_init(&ct->requests.lock);
 	INIT_LIST_HEAD(&ct->requests.pending);
 	INIT_LIST_HEAD(&ct->requests.incoming);
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
+	INIT_WORK(&ct->dead_ct_worker, ct_dead_ct_worker_func);
+#endif
 	INIT_WORK(&ct->requests.worker, ct_incoming_request_worker_func);
 	tasklet_setup(&ct->receive_tasklet, ct_receive_tasklet_func);
 	init_waitqueue_head(&ct->wq);
 	ct->enabled = true;
 	ct->stall_time = KTIME_MAX;
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
+	ct->dead_ct_reported = false;
+	ct->dead_ct_reason = CT_DEAD_ALIVE;
+#endif
 	return 0;
 err_out:
 	CT_PROBE_ERROR(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
+	CT_DEAD(ct, SETUP);
 	return err;
 }
 corrupted:
 	CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
 		 desc->head, desc->tail, desc->status);
+	CT_DEAD(ct, WRITE);
 	ctb->broken = true;
 	return -EPIPE;
 }
 		CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
 		CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
+		CT_DEAD(ct, DEADLOCK);
 		ct->ctbs.send.broken = true;
 	}
 			 head, ctb->size);
 		desc->status |= GUC_CTB_STATUS_OVERFLOW;
 		ctb->broken = true;
+		CT_DEAD(ct, H2G_HAS_ROOM);
 		return false;
 	}
 	/* now update descriptor */
 	WRITE_ONCE(desc->head, head);
+	/*
+	 * Wa_22016122933: Making sure the head update is
+	 * visible to GuC right away
+	 */
+	intel_guc_write_barrier(ct_to_guc(ct));
 	return available - len;
 corrupted:
 	CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
 		 desc->head, desc->tail, desc->status);
 	ctb->broken = true;
+	CT_DEAD(ct, READ);
 	return -EPIPE;
 }
 	if (unlikely(err)) {
 		CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
 			 ERR_PTR(err), 4 * request->size, request->msg);
+		CT_DEAD(ct, PROCESS_FAILED);
 		ct_free_msg(request);
 	}
 	drm_printf(p, "Tail: %u\n",
 		   ct->ctbs.recv.desc->tail);
 }
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
+static void ct_dead_ct_worker_func(struct work_struct *w)
+{
+	struct intel_guc_ct *ct = container_of(w, struct intel_guc_ct, dead_ct_worker);
+	struct intel_guc *guc = ct_to_guc(ct);
+	if (ct->dead_ct_reported)
+		return;
+	ct->dead_ct_reported = true;
+	guc_info(guc, "CTB is dead - reason=0x%X\n", ct->dead_ct_reason);
+	intel_klog_error_capture(guc_to_gt(guc), (intel_engine_mask_t)~0U);
+}
+#endif

drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h+6−0

 	/** @stall_time: time of first time a CTB submission is stalled */
 	ktime_t stall_time;
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
+	int dead_ct_reason;
+	bool dead_ct_reported;
+	struct work_struct dead_ct_worker;
+#endif
 };
 void intel_guc_ct_init_early(struct intel_guc_ct *ct);

drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c+10−2

 	case INTEL_BOOTROM_STATUS_RC6CTXCONFIG_FAILED:
 	case INTEL_BOOTROM_STATUS_MPUMAP_INCORRECT:
 	case INTEL_BOOTROM_STATUS_EXCEPTION:
+	case INTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE:
 		*success = false;
 		return true;
 	}
 		if (!ret || !success)
 			break;
-		guc_dbg(guc, "load still in progress, count = %d, freq = %dMHz\n",
+		guc_dbg(guc, "load still in progress, count = %d, freq = %dMHz, status = 0x%08X [0x%02X/%02X]\n",
-			count, intel_rps_read_actual_frequency(&uncore->gt->rps));
+			count, intel_rps_read_actual_frequency(&uncore->gt->rps), status,
+			REG_FIELD_GET(GS_BOOTROM_MASK, status),
+			REG_FIELD_GET(GS_UKERNEL_MASK, status));
 	}
 	after = ktime_get();
 	delta = ktime_sub(after, before);
 			guc_info(guc, "firmware signature verification failed\n");
 			ret = -ENOEXEC;
 			break;
+		case INTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE:
+			guc_info(guc, "firmware production part check failure\n");
+			ret = -ENOEXEC;
+			break;
 		}
 		switch (ukernel) {

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h+10−1

 	GUC_CAPTURE_LIST_TYPE_MAX,
 };
+/* Class indecies for capture_class and capture_instance arrays */
+enum {
+	GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0,
+	GUC_CAPTURE_LIST_CLASS_VIDEO = 1,
+	GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE = 2,
+	GUC_CAPTURE_LIST_CLASS_BLITTER = 3,
+	GUC_CAPTURE_LIST_CLASS_GSC_OTHER = 4,
+};
 /* GuC Additional Data Struct */
 struct guc_ads {
 	struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
 	GUC_MAX_LOG_BUFFER
 };
-/**
+/*
  * struct guc_log_buffer_state - GuC log buffer state
  *
  * Below state structure is used for coordination of retrieval of GuC firmware

drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c+29−11

 	slpc->max_freq_softlimit = 0;
 	slpc->min_freq_softlimit = 0;
+	slpc->ignore_eff_freq = false;
 	slpc->min_is_rpmax = false;
 	slpc->boost_freq = 0;
 	return ret;
 }
+int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val)
+{
+	struct drm_i915_private *i915 = slpc_to_i915(slpc);
+	intel_wakeref_t wakeref;
+	int ret;
+	mutex_lock(&slpc->lock);
+	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+	ret = slpc_set_param(slpc,
+			     SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
+			     val);
+	if (ret)
+		guc_probe_error(slpc_to_guc(slpc), "Failed to set efficient freq(%d): %pe\n",
+				val, ERR_PTR(ret));
+	else
+		slpc->ignore_eff_freq = val;
+	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+	mutex_unlock(&slpc->lock);
+	return ret;
+}
 /**
  * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
  * @slpc: pointer to intel_guc_slpc.
 	mutex_lock(&slpc->lock);
 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
-	/* Ignore efficient freq if lower min freq is requested */
-	ret = slpc_set_param(slpc,
-			     SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
-			     val < slpc->rp1_freq);
-	if (ret) {
-		guc_probe_error(slpc_to_guc(slpc), "Failed to toggle efficient freq: %pe\n",
-				ERR_PTR(ret));
-		goto out;
-	}
 	ret = slpc_set_param(slpc,
 			     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
 			     val);
 	if (!ret)
 		slpc->min_freq_softlimit = val;
-out:
 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
 	mutex_unlock(&slpc->lock);
 	/* Set cached media freq ratio mode */
 	intel_guc_slpc_set_media_ratio_mode(slpc, slpc->media_ratio_mode);
+	/* Set cached value of ignore efficient freq */
+	intel_guc_slpc_set_ignore_eff_freq(slpc, slpc->ignore_eff_freq);
 	return 0;
 }
 				   slpc_decode_min_freq(slpc));
 			drm_printf(p, "\twaitboosts: %u\n",
 				   slpc->num_boosts);
+			drm_printf(p, "\tBoosts outstanding: %u\n",
+				   atomic_read(&slpc->num_waiters));
 		}
 	}

drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h+1−0

@@ -46,5 +46,6 @@ void intel_guc_slpc_boost(struct intel_guc_slpc *slpc); · 45 unmodified lines
46	void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc);	46	void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc);
47	int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc);	47	int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc);
48	int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode);	48	int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode);
		49	int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val);
49		50
50	#endif	51	#endif

drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h+1−0

@@ -31,6 +31,7 @@ struct intel_guc_slpc { · 30 unmodified lines
31	/* frequency softlimits */	31	/* frequency softlimits */
32	u32 min_freq_softlimit;	32	u32 min_freq_softlimit;
33	u32 max_freq_softlimit;	33	u32 max_freq_softlimit;
		34	bool ignore_eff_freq;
34		35
35	/* cached media ratio mode */	36	/* cached media ratio mode */
36	u32 media_ratio_mode;	37	u32 media_ratio_mode;

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c+65−10

 	spin_unlock_irqrestore(&guc->timestamp.lock, flags);
 }
+static void __guc_context_update_stats(struct intel_context *ce)
+{
+	struct intel_guc *guc = ce_to_guc(ce);
+	unsigned long flags;
+	spin_lock_irqsave(&guc->timestamp.lock, flags);
+	lrc_update_runtime(ce);
+	spin_unlock_irqrestore(&guc->timestamp.lock, flags);
+}
+static void guc_context_update_stats(struct intel_context *ce)
+{
+	if (!intel_context_pin_if_active(ce))
+		return;
+	__guc_context_update_stats(ce);
+	intel_context_unpin(ce);
+}
 static void guc_timestamp_ping(struct work_struct *wrk)
 {
 	struct intel_guc *guc = container_of(wrk, typeof(*guc),
 					     timestamp.work.work);
 	struct intel_uc *uc = container_of(guc, typeof(*uc), guc);
 	struct intel_gt *gt = guc_to_gt(guc);
+	struct intel_context *ce;
 	intel_wakeref_t wakeref;
+	unsigned long index;
 	int srcu, ret;
 	/*
 	with_intel_runtime_pm(&gt->i915->runtime_pm, wakeref)
 		__update_guc_busyness_stats(guc);
+	/* adjust context stats for overflow */
+	xa_for_each(&guc->context_lookup, index, ce)
+		guc_context_update_stats(ce);
 	intel_gt_reset_unlock(gt, srcu);
 	guc_enable_busyness_worker(guc);
 static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
 {
-	if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
-		return;
-	intel_engine_stop_cs(engine);
 	/*
 	 * Wa_22011802037: In addition to stopping the cs, we need
 	 * to wait for any pending mi force wakeups
 	 */
-	intel_engine_wait_for_pending_mi_fw(engine);
+	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+	    (GRAPHICS_VER(engine->i915) >= 11 &&
+	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
+		intel_engine_stop_cs(engine);
+		intel_engine_wait_for_pending_mi_fw(engine);
+	}
 }
 static void guc_reset_nop(struct intel_engine_cs *engine)
 {
 	struct intel_guc *guc = ce_to_guc(ce);
+	__guc_context_update_stats(ce);
 	unpin_guc_id(guc, ce);
 	lrc_unpin(ce);
 }
 static const struct intel_context_ops guc_context_ops = {
+	.flags = COPS_RUNTIME_CYCLES,
 	.alloc = guc_context_alloc,
 	.close = guc_context_close,
 	.sched_disable = guc_context_sched_disable,
+	.update_stats = guc_context_update_stats,
 	.reset = lrc_reset,
 	.destroy = guc_context_destroy,
 }
 static const struct intel_context_ops virtual_guc_context_ops = {
+	.flags = COPS_RUNTIME_CYCLES,
 	.alloc = guc_virtual_context_alloc,
 	.close = guc_context_close,
 	.exit = guc_virtual_context_exit,
 	.sched_disable = guc_context_sched_disable,
+	.update_stats = guc_context_update_stats,
 	.destroy = guc_context_destroy,
 {
 	struct intel_gt *gt = guc_to_gt(guc);
 	struct drm_i915_private *i915 = gt->i915;
-	struct intel_engine_cs *engine = __context_to_physical_engine(ce);
 	intel_wakeref_t wakeref;
+	intel_engine_mask_t engine_mask;
+	if (intel_engine_is_virtual(ce->engine)) {
+		struct intel_engine_cs *e;
+		intel_engine_mask_t tmp, virtual_mask = ce->engine->mask;
+		engine_mask = 0;
+		for_each_engine_masked(e, ce->engine->gt, virtual_mask, tmp) {
+			bool match = intel_guc_capture_is_matching_engine(gt, ce, e);
+			if (match) {
+				intel_engine_set_hung_context(e, ce);
+				engine_mask |= e->mask;
+				atomic_inc(&i915->gpu_error.reset_engine_count[e->uabi_class]);
+			}
+		}
+		if (!engine_mask) {
+			guc_warn(guc, "No matching physical engine capture for virtual engine context 0x%04X / %s",
+				 ce->guc_id.id, ce->engine->name);
+			engine_mask = ~0U;
+		}
+	} else {
+		intel_engine_set_hung_context(ce->engine, ce);
+		engine_mask = ce->engine->mask;
+		atomic_inc(&i915->gpu_error.reset_engine_count[ce->engine->uabi_class]);
+	}
-	intel_engine_set_hung_context(engine, ce);
 	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
-		i915_capture_error_state(gt, engine->mask, CORE_DUMP_FLAG_IS_GUC_CAPTURE);
+		i915_capture_error_state(gt, engine_mask, CORE_DUMP_FLAG_IS_GUC_CAPTURE);
-	atomic_inc(&i915->gpu_error.reset_engine_count[engine->uabi_class]);
 }
 static void guc_context_replay(struct intel_context *ce)

drivers/gpu/drm/i915/gt/uc/intel_uc.c+14−2

 #include "intel_uc.h"
 #include "i915_drv.h"
+#include "i915_hwmon.h"
 static const struct intel_uc_ops uc_ops_off;
 static const struct intel_uc_ops uc_ops_on;
 static int __uc_check_hw(struct intel_uc *uc)
 {
+	if (uc->fw_table_invalid)
+		return -EIO;
 	if (!intel_uc_supports_guc(uc))
 		return 0;
 	struct intel_guc *guc = &uc->guc;
 	struct intel_huc *huc = &uc->huc;
 	int ret, attempts;
+	bool pl1en = false;
 	GEM_BUG_ON(!intel_uc_supports_guc(uc));
 	GEM_BUG_ON(!intel_uc_wants_guc(uc));
 	else
 		attempts = 1;
+	/* Disable a potentially low PL1 power limit to allow freq to be raised */
+	i915_hwmon_power_max_disable(gt->i915, &pl1en);
 	intel_rps_raise_unslice(&uc_to_gt(uc)->rps);
 	while (attempts--) {
 		 */
 		ret = __uc_sanitize(uc);
 		if (ret)
-			goto err_out;
+			goto err_rps;
 		intel_huc_fw_upload(huc);
 		intel_guc_ads_reset(guc);
 		intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
 	}
+	i915_hwmon_power_max_restore(gt->i915, pl1en);
 	guc_info(guc, "submission %s\n", str_enabled_disabled(intel_uc_uses_guc_submission(uc)));
 	guc_info(guc, "SLPC %s\n", str_enabled_disabled(intel_uc_uses_guc_slpc(uc)));
 	intel_guc_submission_disable(guc);
 err_log_capture:
 	__uc_capture_load_err_log(uc);
-err_out:
+err_rps:
 	/* Return GT back to RPn */
 	intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
+	i915_hwmon_power_max_restore(gt->i915, pl1en);
+err_out:
 	__uc_sanitize(uc);
 	if (!ret) {

drivers/gpu/drm/i915/gt/uc/intel_uc.h+1−0

@@ -36,6 +36,7 @@ struct intel_uc { · 35 unmodified lines
36	struct drm_i915_gem_object *load_err_log;	36	struct drm_i915_gem_object *load_err_log;
37		37
38	bool reset_in_progress;	38	bool reset_in_progress;
		39	bool fw_table_invalid;
39	};	40	};
40		41
41	void intel_uc_init_early(struct intel_uc *uc);	42	void intel_uc_init_early(struct intel_uc *uc);

drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c+154−84

 #include "i915_drv.h"
 #include "i915_reg.h"
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
+#define UNEXPECTED	gt_probe_error
+#else
+#define UNEXPECTED	gt_notice
+#endif
 static inline struct intel_gt *
 ____uc_fw_to_gt(struct intel_uc_fw *uc_fw, enum intel_uc_fw_type type)
 {
  * security fixes, etc. to be enabled.
  */
 #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \
-	fw_def(DG2,          0, guc_maj(dg2,  70, 5)) \
+	fw_def(METEORLAKE,   0, guc_maj(mtl,  70, 6, 6)) \
-	fw_def(ALDERLAKE_P,  0, guc_maj(adlp, 70, 5)) \
+	fw_def(DG2,          0, guc_maj(dg2,  70, 5, 1)) \
+	fw_def(ALDERLAKE_P,  0, guc_maj(adlp, 70, 5, 1)) \
 	fw_def(ALDERLAKE_P,  0, guc_mmp(adlp, 70, 1, 1)) \
 	fw_def(ALDERLAKE_P,  0, guc_mmp(adlp, 69, 0, 3)) \
-	fw_def(ALDERLAKE_S,  0, guc_maj(tgl,  70, 5)) \
+	fw_def(ALDERLAKE_S,  0, guc_maj(tgl,  70, 5, 1)) \
 	fw_def(ALDERLAKE_S,  0, guc_mmp(tgl,  70, 1, 1)) \
 	fw_def(ALDERLAKE_S,  0, guc_mmp(tgl,  69, 0, 3)) \
-	fw_def(DG1,          0, guc_maj(dg1,  70, 5)) \
+	fw_def(DG1,          0, guc_maj(dg1,  70, 5, 1)) \
 	fw_def(ROCKETLAKE,   0, guc_mmp(tgl,  70, 1, 1)) \
 	fw_def(TIGERLAKE,    0, guc_mmp(tgl,  70, 1, 1)) \
 	fw_def(JASPERLAKE,   0, guc_mmp(ehl,  70, 1, 1)) \
 	__stringify(patch_) ".bin"
 /* Minor for internal driver use, not part of file name */
-#define MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_) \
+#define MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_, patch_) \
 	__MAKE_UC_FW_PATH_MAJOR(prefix_, "guc", major_)
 #define MAKE_GUC_FW_PATH_MMP(prefix_, major_, minor_, patch_) \
 	{ UC_FW_BLOB_BASE(major_, minor_, patch_, path_) \
 	  .legacy = true }
-#define GUC_FW_BLOB(prefix_, major_, minor_) \
+#define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \
-	UC_FW_BLOB_NEW(major_, minor_, 0, false, \
+	UC_FW_BLOB_NEW(major_, minor_, patch_, false, \
-		       MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_))
+		       MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_, patch_))
 #define GUC_FW_BLOB_MMP(prefix_, major_, minor_, patch_) \
 	UC_FW_BLOB_OLD(major_, minor_, patch_, \
 	u32 count;
 };
+static const struct uc_fw_platform_requirement blobs_guc[] = {
+	INTEL_GUC_FIRMWARE_DEFS(MAKE_FW_LIST, GUC_FW_BLOB, GUC_FW_BLOB_MMP)
+};
+static const struct uc_fw_platform_requirement blobs_huc[] = {
+	INTEL_HUC_FIRMWARE_DEFS(MAKE_FW_LIST, HUC_FW_BLOB, HUC_FW_BLOB_MMP, HUC_FW_BLOB_GSC)
+};
+static const struct fw_blobs_by_type blobs_all[INTEL_UC_FW_NUM_TYPES] = {
+	[INTEL_UC_FW_TYPE_GUC] = { blobs_guc, ARRAY_SIZE(blobs_guc) },
+	[INTEL_UC_FW_TYPE_HUC] = { blobs_huc, ARRAY_SIZE(blobs_huc) },
+};
 static void
 __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw)
 {
-	static const struct uc_fw_platform_requirement blobs_guc[] = {
-		INTEL_GUC_FIRMWARE_DEFS(MAKE_FW_LIST, GUC_FW_BLOB, GUC_FW_BLOB_MMP)
-	};
-	static const struct uc_fw_platform_requirement blobs_huc[] = {
-		INTEL_HUC_FIRMWARE_DEFS(MAKE_FW_LIST, HUC_FW_BLOB, HUC_FW_BLOB_MMP, HUC_FW_BLOB_GSC)
-	};
-	static const struct fw_blobs_by_type blobs_all[INTEL_UC_FW_NUM_TYPES] = {
-		[INTEL_UC_FW_TYPE_GUC] = { blobs_guc, ARRAY_SIZE(blobs_guc) },
-		[INTEL_UC_FW_TYPE_HUC] = { blobs_huc, ARRAY_SIZE(blobs_huc) },
-	};
-	static bool verified[INTEL_UC_FW_NUM_TYPES];
 	const struct uc_fw_platform_requirement *fw_blobs;
 	enum intel_platform p = INTEL_INFO(i915)->platform;
 	u32 fw_count;
 			continue;
 		if (uc_fw->file_selected.path) {
+			/*
+			 * Continuing an earlier search after a found blob failed to load.
+			 * Once the previously chosen path has been found, clear it out
+			 * and let the search continue from there.
+			 */
 			if (uc_fw->file_selected.path == blob->path)
 				uc_fw->file_selected.path = NULL;
 		uc_fw->file_wanted.path = blob->path;
 		uc_fw->file_wanted.ver.major = blob->major;
 		uc_fw->file_wanted.ver.minor = blob->minor;
+		uc_fw->file_wanted.ver.patch = blob->patch;
 		uc_fw->loaded_via_gsc = blob->loaded_via_gsc;
 		found = true;
 		break;
 		/* Failed to find a match for the last attempt?! */
 		uc_fw->file_selected.path = NULL;
 	}
+}
-	/* make sure the list is ordered as expected */
+static bool validate_fw_table_type(struct drm_i915_private *i915, enum intel_uc_fw_type type)
-	if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST) && !verified[uc_fw->type]) {
+{
-		verified[uc_fw->type] = true;
+	const struct uc_fw_platform_requirement *fw_blobs;
+	u32 fw_count;
+	int i, j;
+	if (type >= ARRAY_SIZE(blobs_all)) {
+		drm_err(&i915->drm, "No blob array for %s\n", intel_uc_fw_type_repr(type));
+		return false;
+	}
+	fw_blobs = blobs_all[type].blobs;
+	fw_count = blobs_all[type].count;
+	if (!fw_count)
+		return true;
-		for (i = 1; i < fw_count; i++) {
+	/* make sure the list is ordered as expected */
-			/* Next platform is good: */
+	for (i = 1; i < fw_count; i++) {
-			if (fw_blobs[i].p < fw_blobs[i - 1].p)
+		/* Versionless file names must be unique per platform: */
+		for (j = i + 1; j < fw_count; j++) {
+			/* Same platform? */
+			if (fw_blobs[i].p != fw_blobs[j].p)
 				continue;
-			/* Next platform revision is good: */
+			if (fw_blobs[i].blob.path != fw_blobs[j].blob.path)
-			if (fw_blobs[i].p == fw_blobs[i - 1].p &&
-			    fw_blobs[i].rev < fw_blobs[i - 1].rev)
 				continue;
-			/* Platform/revision must be in order: */
+			drm_err(&i915->drm, "Duplicate %s blobs: %s r%u %s%d.%d.%d [%s] matches %s%d.%d.%d [%s]\n",
-			if (fw_blobs[i].p != fw_blobs[i - 1].p ||
+				intel_uc_fw_type_repr(type),
-			    fw_blobs[i].rev != fw_blobs[i - 1].rev)
+				intel_platform_name(fw_blobs[j].p), fw_blobs[j].rev,
-				goto bad;
+				fw_blobs[j].blob.legacy ? "L" : "v",
+				fw_blobs[j].blob.major, fw_blobs[j].blob.minor,
+				fw_blobs[j].blob.patch, fw_blobs[j].blob.path,
+				fw_blobs[i].blob.legacy ? "L" : "v",
+				fw_blobs[i].blob.major, fw_blobs[i].blob.minor,
+				fw_blobs[i].blob.patch, fw_blobs[i].blob.path);
+		}
-			/* Next major version is good: */
+		/* Next platform is good: */
-			if (fw_blobs[i].blob.major < fw_blobs[i - 1].blob.major)
+		if (fw_blobs[i].p < fw_blobs[i - 1].p)
-				continue;
+			continue;
-			/* New must be before legacy: */
+		/* Next platform revision is good: */
-			if (!fw_blobs[i].blob.legacy && fw_blobs[i - 1].blob.legacy)
+		if (fw_blobs[i].p == fw_blobs[i - 1].p &&
-				goto bad;
+		    fw_blobs[i].rev < fw_blobs[i - 1].rev)
+			continue;
-			/* New to legacy also means 0.0 to X.Y (HuC), or X.0 to X.Y (GuC) */
+		/* Platform/revision must be in order: */
-			if (fw_blobs[i].blob.legacy && !fw_blobs[i - 1].blob.legacy) {
+		if (fw_blobs[i].p != fw_blobs[i - 1].p ||
-				if (!fw_blobs[i - 1].blob.major)
+		    fw_blobs[i].rev != fw_blobs[i - 1].rev)
-					continue;
+			goto bad;
-				if (fw_blobs[i].blob.major == fw_blobs[i - 1].blob.major)
+		/* Next major version is good: */
-					continue;
+		if (fw_blobs[i].blob.major < fw_blobs[i - 1].blob.major)
-			}
+			continue;
-			/* Major versions must be in order: */
+		/* New must be before legacy: */
-			if (fw_blobs[i].blob.major != fw_blobs[i - 1].blob.major)
+		if (!fw_blobs[i].blob.legacy && fw_blobs[i - 1].blob.legacy)
-				goto bad;
+			goto bad;
-			/* Next minor version is good: */
+		/* New to legacy also means 0.0 to X.Y (HuC), or X.0 to X.Y (GuC) */
-			if (fw_blobs[i].blob.minor < fw_blobs[i - 1].blob.minor)
+		if (fw_blobs[i].blob.legacy && !fw_blobs[i - 1].blob.legacy) {
+			if (!fw_blobs[i - 1].blob.major)
 				continue;
-			/* Minor versions must be in order: */
+			if (fw_blobs[i].blob.major == fw_blobs[i - 1].blob.major)
-			if (fw_blobs[i].blob.minor != fw_blobs[i - 1].blob.minor)
-				goto bad;
-			/* Patch versions must be in order: */
-			if (fw_blobs[i].blob.patch <= fw_blobs[i - 1].blob.patch)
 				continue;
+		}
-bad:
+		/* Major versions must be in order: */
-			drm_err(&i915->drm, "Invalid %s blob order: %s r%u %s%d.%d.%d comes before %s r%u %s%d.%d.%d\n",
+		if (fw_blobs[i].blob.major != fw_blobs[i - 1].blob.major)
-				intel_uc_fw_type_repr(uc_fw->type),
+			goto bad;
-				intel_platform_name(fw_blobs[i - 1].p), fw_blobs[i - 1].rev,
-				fw_blobs[i - 1].blob.legacy ? "L" : "v",
-				fw_blobs[i - 1].blob.major,
-				fw_blobs[i - 1].blob.minor,
-				fw_blobs[i - 1].blob.patch,
-				intel_platform_name(fw_blobs[i].p), fw_blobs[i].rev,
-				fw_blobs[i].blob.legacy ? "L" : "v",
-				fw_blobs[i].blob.major,
-				fw_blobs[i].blob.minor,
-				fw_blobs[i].blob.patch);
-			uc_fw->file_selected.path = NULL;
+		/* Next minor version is good: */
-		}
+		if (fw_blobs[i].blob.minor < fw_blobs[i - 1].blob.minor)
+			continue;
+		/* Minor versions must be in order: */
+		if (fw_blobs[i].blob.minor != fw_blobs[i - 1].blob.minor)
+			goto bad;
+		/* Patch versions must be in order and unique: */
+		if (fw_blobs[i].blob.patch < fw_blobs[i - 1].blob.patch)
+			continue;
+bad:
+		drm_err(&i915->drm, "Invalid %s blob order: %s r%u %s%d.%d.%d comes before %s r%u %s%d.%d.%d\n",
+			intel_uc_fw_type_repr(type),
+			intel_platform_name(fw_blobs[i - 1].p), fw_blobs[i - 1].rev,
+			fw_blobs[i - 1].blob.legacy ? "L" : "v",
+			fw_blobs[i - 1].blob.major,
+			fw_blobs[i - 1].blob.minor,
+			fw_blobs[i - 1].blob.patch,
+			intel_platform_name(fw_blobs[i].p), fw_blobs[i].rev,
+			fw_blobs[i].blob.legacy ? "L" : "v",
+			fw_blobs[i].blob.major,
+			fw_blobs[i].blob.minor,
+			fw_blobs[i].blob.patch);
+		return false;
 	}
+	return true;
 }
 static const char *__override_guc_firmware_path(struct drm_i915_private *i915)
 void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
 			    enum intel_uc_fw_type type)
 {
-	struct drm_i915_private *i915 = ____uc_fw_to_gt(uc_fw, type)->i915;
+	struct intel_gt *gt = ____uc_fw_to_gt(uc_fw, type);
+	struct drm_i915_private *i915 = gt->i915;
 	/*
 	 * we use FIRMWARE_UNINITIALIZED to detect checks against uc_fw->status
 	uc_fw->type = type;
 	if (HAS_GT_UC(i915)) {
+		if (!validate_fw_table_type(i915, type)) {
+			gt->uc.fw_table_invalid = true;
+			intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_NOT_SUPPORTED);
+			return;
+		}
 		__uc_fw_auto_select(i915, uc_fw);
 		__uc_fw_user_override(i915, uc_fw);
 	}
 	if (uc_fw->file_wanted.ver.major && uc_fw->file_selected.ver.major) {
 		/* Check the file's major version was as it claimed */
 		if (uc_fw->file_selected.ver.major != uc_fw->file_wanted.ver.major) {
-			gt_notice(gt, "%s firmware %s: unexpected version: %u.%u != %u.%u\n",
+			UNEXPECTED(gt, "%s firmware %s: unexpected version: %u.%u != %u.%u\n",
-				  intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+				   intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
-				  uc_fw->file_selected.ver.major, uc_fw->file_selected.ver.minor,
+				   uc_fw->file_selected.ver.major, uc_fw->file_selected.ver.minor,
-				  uc_fw->file_wanted.ver.major, uc_fw->file_wanted.ver.minor);
+				   uc_fw->file_wanted.ver.major, uc_fw->file_wanted.ver.minor);
 			if (!intel_uc_fw_is_overridden(uc_fw)) {
 				err = -ENOEXEC;
 				goto fail;
 		} else {
 			if (uc_fw->file_selected.ver.minor < uc_fw->file_wanted.ver.minor)
 				old_ver = true;
+			else if ((uc_fw->file_selected.ver.minor == uc_fw->file_wanted.ver.minor) &&
+				 (uc_fw->file_selected.ver.patch < uc_fw->file_wanted.ver.patch))
+				old_ver = true;
 		}
 	}
 		/* Preserve the version that was really wanted */
 		memcpy(&uc_fw->file_wanted, &file_ideal, sizeof(uc_fw->file_wanted));
-		gt_notice(gt, "%s firmware %s (%d.%d) is recommended, but only %s (%d.%d) was found\n",
+		UNEXPECTED(gt, "%s firmware %s (%d.%d.%d) is recommended, but only %s (%d.%d.%d) was found\n",
-			  intel_uc_fw_type_repr(uc_fw->type),
+			   intel_uc_fw_type_repr(uc_fw->type),
-			  uc_fw->file_wanted.path,
+			   uc_fw->file_wanted.path,
-			  uc_fw->file_wanted.ver.major, uc_fw->file_wanted.ver.minor,
+			   uc_fw->file_wanted.ver.major,
-			  uc_fw->file_selected.path,
+			   uc_fw->file_wanted.ver.minor,
-			  uc_fw->file_selected.ver.major, uc_fw->file_selected.ver.minor);
+			   uc_fw->file_wanted.ver.patch,
+			   uc_fw->file_selected.path,
+			   uc_fw->file_selected.ver.major,
+			   uc_fw->file_selected.ver.minor,
+			   uc_fw->file_selected.ver.patch);
 		gt_info(gt, "Consider updating your linux-firmware pkg or downloading from %s\n",
 			INTEL_UC_FIRMWARE_URL);
 	}
 		pte_flags |= PTE_LM;
 	if (ggtt->vm.raw_insert_entries)
-		ggtt->vm.raw_insert_entries(&ggtt->vm, dummy, I915_CACHE_NONE, pte_flags);
+		ggtt->vm.raw_insert_entries(&ggtt->vm, dummy,
+					    i915_gem_get_pat_index(ggtt->vm.i915,
+								   I915_CACHE_NONE),
+					    pte_flags);
 	else
-		ggtt->vm.insert_entries(&ggtt->vm, dummy, I915_CACHE_NONE, pte_flags);
+		ggtt->vm.insert_entries(&ggtt->vm, dummy,
+					i915_gem_get_pat_index(ggtt->vm.i915,
+							       I915_CACHE_NONE),
+					pte_flags);
 }
 static void uc_fw_unbind_ggtt(struct intel_uc_fw *uc_fw)

drivers/gpu/drm/i915/gvt/aperture_gm.c+1−1

@@ -330,7 +330,7 @@ void intel_vgpu_reset_resource(struct intel_vgpu *vgpu) · 329 unmodified lines
330	/**	330	/**
331	* intel_vgpu_alloc_resource() - allocate HW resource for a vGPU	331	* intel_vgpu_alloc_resource() - allocate HW resource for a vGPU
332	* @vgpu: vGPU	332	* @vgpu: vGPU
333	* @param: vGPU creation params	333	* @conf: vGPU creation params
334	*	334	*
335	* This function is used to allocate HW resource for a vGPU. User specifies	335	* This function is used to allocate HW resource for a vGPU. User specifies
336	* the resource configuration through the creation params.	336	* the resource configuration through the creation params.

drivers/gpu/drm/i915/i915_active.h+7−7

@@ -49,9 +49,9 @@ void i915_active_noop(struct dma_fence fence, struct dma_fence_cb cb); · 48 unmodified lines
49		49
50	/**	50	/**
51	* __i915_active_fence_init - prepares the activity tracker for use	51	* __i915_active_fence_init - prepares the activity tracker for use
52	* @active - the active tracker	52	* @active: the active tracker
53	* @fence - initial fence to track, can be NULL	53	* @fence: initial fence to track, can be NULL
54	* @func - a callback when then the tracker is retired (becomes idle),	54	* @fn: a callback when then the tracker is retired (becomes idle),
55	* can be NULL	55	* can be NULL
56	*	56	*
57	* i915_active_fence_init() prepares the embedded @active struct for use as	57	* i915_active_fence_init() prepares the embedded @active struct for use as
@@ -77,8 +77,8 @@ __i915_active_fence_set(struct i915_active_fence *active, · 19 unmodified lines
77		77
78	/**	78	/**
79	* i915_active_fence_set - updates the tracker to watch the current fence	79	* i915_active_fence_set - updates the tracker to watch the current fence
80	* @active - the active tracker	80	* @active: the active tracker
81	* @rq - the request to watch	81	* @rq: the request to watch
82	*	82	*
83	* i915_active_fence_set() watches the given @rq for completion. While	83	* i915_active_fence_set() watches the given @rq for completion. While
84	* that @rq is busy, the @active reports busy. When that @rq is signaled	84	* that @rq is busy, the @active reports busy. When that @rq is signaled
@@ -89,7 +89,7 @@ i915_active_fence_set(struct i915_active_fence *active, · 4 unmodified lines
89	struct i915_request *rq);	89	struct i915_request *rq);
90	/**	90	/**
91	* i915_active_fence_get - return a reference to the active fence	91	* i915_active_fence_get - return a reference to the active fence
92	* @active - the active tracker	92	* @active: the active tracker
93	*	93	*
94	* i915_active_fence_get() returns a reference to the active fence,	94	* i915_active_fence_get() returns a reference to the active fence,
95	* or NULL if the active tracker is idle. The reference is obtained under RCU,	95	* or NULL if the active tracker is idle. The reference is obtained under RCU,
@@ -111,7 +111,7 @@ i915_active_fence_get(struct i915_active_fence *active) · 15 unmodified lines
111		111
112	/**	112	/**
113	* i915_active_fence_isset - report whether the active tracker is assigned	113	* i915_active_fence_isset - report whether the active tracker is assigned
114	* @active - the active tracker	114	* @active: the active tracker
115	*	115	*
116	* i915_active_fence_isset() returns true if the active tracker is currently	116	* i915_active_fence_isset() returns true if the active tracker is currently
117	* assigned to a fence. Due to the lazy retiring, that fence may be idle	117	* assigned to a fence. Due to the lazy retiring, that fence may be idle

drivers/gpu/drm/i915/i915_debugfs.c+43−10

@@ -139,21 +139,54 @@ static const char stringify_vma_type(const struct i915_vma vma) · 138 unmodified lines
139	return "ppgtt";	139	return "ppgtt";
140	}	140	}
141		141
142	static const char i915_cache_level_str(struct drm_i915_private i915, int type)	142	static const char i915_cache_level_str(struct drm_i915_gem_object obj)
143	{	143	{
144	switch (type) {	144	struct drm_i915_private *i915 = obj_to_i915(obj);
145	case I915_CACHE_NONE: return " uncached";	145
146	case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";	146	if (IS_METEORLAKE(i915)) {
147	case I915_CACHE_L3_LLC: return " L3+LLC";	147	switch (obj->pat_index) {
148	case I915_CACHE_WT: return " WT";	148	case 0: return " WB";
149	default: return "";	149	case 1: return " WT";
		150	case 2: return " UC";
		151	case 3: return " WB (1-Way Coh)";
		152	case 4: return " WB (2-Way Coh)";
		153	default: return " not defined";
		154	}
		155	} else if (IS_PONTEVECCHIO(i915)) {
		156	switch (obj->pat_index) {
		157	case 0: return " UC";
		158	case 1: return " WC";
		159	case 2: return " WT";
		160	case 3: return " WB";
		161	case 4: return " WT (CLOS1)";
		162	case 5: return " WB (CLOS1)";
		163	case 6: return " WT (CLOS2)";
		164	case 7: return " WT (CLOS2)";
		165	default: return " not defined";
		166	}
		167	} else if (GRAPHICS_VER(i915) >= 12) {
		168	switch (obj->pat_index) {
		169	case 0: return " WB";
		170	case 1: return " WC";
		171	case 2: return " WT";
		172	case 3: return " UC";
		173	default: return " not defined";
		174	}
		175	} else {
		176	switch (obj->pat_index) {
		177	case 0: return " UC";
		178	case 1: return HAS_LLC(i915) ?
		179	" LLC" : " snooped";
		180	case 2: return " L3+LLC";
		181	case 3: return " WT";
		182	default: return " not defined";
		183	}
150	}	184	}
151	}	185	}
152		186
153	void	187	void
154	i915_debugfs_describe_obj(struct seq_file m, struct drm_i915_gem_object obj)	188	i915_debugfs_describe_obj(struct seq_file m, struct drm_i915_gem_object obj)
155	{	189	{
156	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
157	struct i915_vma *vma;	190	struct i915_vma *vma;
158	int pin_count = 0;	191	int pin_count = 0;
159		192
@@ -165,7 +198,7 @@ i915_debugfs_describe_obj(struct seq_file m, struct drm_i915_gem_object obj) · 5 unmodified lines
165	obj->base.size / 1024,	198	obj->base.size / 1024,
166	obj->read_domains,	199	obj->read_domains,
167	obj->write_domain,	200	obj->write_domain,
168	i915_cache_level_str(dev_priv, obj->cache_level),	201	i915_cache_level_str(obj),
169	obj->mm.dirty ? " dirty" : "",	202	obj->mm.dirty ? " dirty" : "",
170	obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");	203	obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
171	if (obj->base.name)	204	if (obj->base.name)

drivers/gpu/drm/i915/i915_drm_client.c+1−5

 		   PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
 	seq_printf(m, "drm-client-id:\t%u\n", client->id);
-	/*
+	if (GRAPHICS_VER(i915) < 8)
-	 * Temporarily skip showing client engine information with GuC submission till
-	 * fetching engine busyness is implemented in the GuC submission backend
-	 */
-	if (GRAPHICS_VER(i915) < 8 || intel_uc_uses_guc_submission(&i915->gt0.uc))
 		return;
 	for (i = 0; i < ARRAY_SIZE(uabi_class_names); i++)

drivers/gpu/drm/i915/i915_drv.h+195−196

@@ -382,11 +382,11 @@ static inline struct intel_gt to_gt(struct drm_i915_private i915) · 381 unmodified lines
382	}	382	}
383		383
384	/* Simple iterator over all initialised engines */	384	/* Simple iterator over all initialised engines */
385	#define for_each_engine(engine__, dev_priv__, id__) \	385	#define for_each_engine(engine__, gt__, id__) \
386	for ((id__) = 0; \	386	for ((id__) = 0; \
387	(id__) < I915_NUM_ENGINES; \	387	(id__) < I915_NUM_ENGINES; \
388	(id__)++) \	388	(id__)++) \
389	for_each_if ((engine__) = (dev_priv__)->engine[(id__)])	389	for_each_if ((engine__) = (gt__)->engine[(id__)])
390		390
391	/* Iterator over subset of engines selected by mask */	391	/* Iterator over subset of engines selected by mask */
392	#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \	392	#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
@@ -408,13 +408,13 @@ static inline struct intel_gt to_gt(struct drm_i915_private i915) · 15 unmodified lines
408	(engine__) && (engine__)->uabi_class == (class__); \	408	(engine__) && (engine__)->uabi_class == (class__); \
409	(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))	409	(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
410		410
411	#define INTEL_INFO(dev_priv) (&(dev_priv)->__info)	411	#define INTEL_INFO(i915) (&(i915)->__info)
412	#define DISPLAY_INFO(i915) (INTEL_INFO(i915)->display)	412	#define DISPLAY_INFO(i915) (INTEL_INFO(i915)->display)
413	#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)	413	#define RUNTIME_INFO(i915) (&(i915)->__runtime)
414	#define DISPLAY_RUNTIME_INFO(i915) (&(i915)->__display_runtime)	414	#define DISPLAY_RUNTIME_INFO(i915) (&(i915)->__display_runtime)
415	#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)	415	#define DRIVER_CAPS(i915) (&(i915)->caps)
416		416
417	#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)	417	#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
418		418
419	#define IP_VER(ver, rel) ((ver) << 8 \| (rel))	419	#define IP_VER(ver, rel) ((ver) << 8 \| (rel))
420		420
@@ -434,7 +434,7 @@ static inline struct intel_gt to_gt(struct drm_i915_private i915) · 13 unmodified lines
434	#define IS_DISPLAY_VER(i915, from, until) \	434	#define IS_DISPLAY_VER(i915, from, until) \
435	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))	435	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
436		436
437	#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)	437	#define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision)
438		438
439	#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)	439	#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
440	#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)	440	#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
@@ -519,135 +519,135 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 78 unmodified lines
519	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);	519	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
520	}	520	}
521		521
522	#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)	522	#define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile)
523	#define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)	523	#define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx)
524		524
525	#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)	525	#define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830)
526	#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)	526	#define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G)
527	#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)	527	#define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X)
528	#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)	528	#define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G)
529	#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)	529	#define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G)
530	#define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)	530	#define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM)
531	#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)	531	#define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G)
532	#define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)	532	#define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM)
533	#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)	533	#define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G)
534	#define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)	534	#define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM)
535	#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)	535	#define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45)
536	#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)	536	#define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45)
537	#define IS_G4X(dev_priv) (IS_G45(dev_priv) \|\| IS_GM45(dev_priv))	537	#define IS_G4X(i915) (IS_G45(i915) \|\| IS_GM45(i915))
538	#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)	538	#define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW)
539	#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)	539	#define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33)
540	#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)	540	#define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE)
541	#define IS_IRONLAKE_M(dev_priv) \	541	#define IS_IRONLAKE_M(i915) \
542	(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))	542	(IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
543	#define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)	543	#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
544	#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)	544	#define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE)
545	#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \	545	#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \
546	INTEL_INFO(dev_priv)->gt == 1)	546	INTEL_INFO(i915)->gt == 1)
547	#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)	547	#define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW)
548	#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)	548	#define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW)
549	#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)	549	#define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL)
550	#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)	550	#define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL)
551	#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)	551	#define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE)
552	#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)	552	#define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON)
553	#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)	553	#define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE)
554	#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)	554	#define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE)
555	#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)	555	#define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE)
556	#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)	556	#define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE)
557	#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)	557	#define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE)
558	#define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) \|\| \	558	#define IS_JSL_EHL(i915) (IS_PLATFORM(i915, INTEL_JASPERLAKE) \|\| \
559	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))	559	IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
560	#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)	560	#define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE)
561	#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)	561	#define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE)
562	#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)	562	#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
563	#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)	563	#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
564	#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)	564	#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
565	#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)	565	#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV)
566	#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)	566	#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
567	#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)	567	#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
568	#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)	568	#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
569		569
570	#define IS_METEORLAKE_M(dev_priv) \	570	#define IS_METEORLAKE_M(i915) \
571	IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)	571	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
572	#define IS_METEORLAKE_P(dev_priv) \	572	#define IS_METEORLAKE_P(i915) \
573	IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)	573	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
574	#define IS_DG2_G10(dev_priv) \	574	#define IS_DG2_G10(i915) \
575	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)	575	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
576	#define IS_DG2_G11(dev_priv) \	576	#define IS_DG2_G11(i915) \
577	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)	577	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
578	#define IS_DG2_G12(dev_priv) \	578	#define IS_DG2_G12(i915) \
579	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)	579	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
580	#define IS_ADLS_RPLS(dev_priv) \	580	#define IS_ADLS_RPLS(i915) \
581	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)	581	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
582	#define IS_ADLP_N(dev_priv) \	582	#define IS_ADLP_N(i915) \
583	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)	583	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
584	#define IS_ADLP_RPLP(dev_priv) \	584	#define IS_ADLP_RPLP(i915) \
585	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)	585	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
586	#define IS_ADLP_RPLU(dev_priv) \	586	#define IS_ADLP_RPLU(i915) \
587	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)	587	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
588	#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \	588	#define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \
589	(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)	589	(INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
590	#define IS_BDW_ULT(dev_priv) \	590	#define IS_BDW_ULT(i915) \
591	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)	591	IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
592	#define IS_BDW_ULX(dev_priv) \	592	#define IS_BDW_ULX(i915) \
593	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)	593	IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
594	#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \	594	#define IS_BDW_GT3(i915) (IS_BROADWELL(i915) && \
595	INTEL_INFO(dev_priv)->gt == 3)	595	INTEL_INFO(i915)->gt == 3)
596	#define IS_HSW_ULT(dev_priv) \	596	#define IS_HSW_ULT(i915) \
597	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)	597	IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
598	#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \	598	#define IS_HSW_GT3(i915) (IS_HASWELL(i915) && \
599	INTEL_INFO(dev_priv)->gt == 3)	599	INTEL_INFO(i915)->gt == 3)
600	#define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \	600	#define IS_HSW_GT1(i915) (IS_HASWELL(i915) && \
601	INTEL_INFO(dev_priv)->gt == 1)	601	INTEL_INFO(i915)->gt == 1)
602	/* ULX machines are also considered ULT. */	602	/* ULX machines are also considered ULT. */
603	#define IS_HSW_ULX(dev_priv) \	603	#define IS_HSW_ULX(i915) \
604	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)	604	IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
605	#define IS_SKL_ULT(dev_priv) \	605	#define IS_SKL_ULT(i915) \
606	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)	606	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
607	#define IS_SKL_ULX(dev_priv) \	607	#define IS_SKL_ULX(i915) \
608	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)	608	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
609	#define IS_KBL_ULT(dev_priv) \	609	#define IS_KBL_ULT(i915) \
610	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)	610	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
611	#define IS_KBL_ULX(dev_priv) \	611	#define IS_KBL_ULX(i915) \
612	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)	612	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
613	#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \	613	#define IS_SKL_GT2(i915) (IS_SKYLAKE(i915) && \
614	INTEL_INFO(dev_priv)->gt == 2)	614	INTEL_INFO(i915)->gt == 2)
615	#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \	615	#define IS_SKL_GT3(i915) (IS_SKYLAKE(i915) && \
616	INTEL_INFO(dev_priv)->gt == 3)	616	INTEL_INFO(i915)->gt == 3)
617	#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \	617	#define IS_SKL_GT4(i915) (IS_SKYLAKE(i915) && \
618	INTEL_INFO(dev_priv)->gt == 4)	618	INTEL_INFO(i915)->gt == 4)
619	#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \	619	#define IS_KBL_GT2(i915) (IS_KABYLAKE(i915) && \
620	INTEL_INFO(dev_priv)->gt == 2)	620	INTEL_INFO(i915)->gt == 2)
621	#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \	621	#define IS_KBL_GT3(i915) (IS_KABYLAKE(i915) && \
622	INTEL_INFO(dev_priv)->gt == 3)	622	INTEL_INFO(i915)->gt == 3)
623	#define IS_CFL_ULT(dev_priv) \	623	#define IS_CFL_ULT(i915) \
624	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)	624	IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
625	#define IS_CFL_ULX(dev_priv) \	625	#define IS_CFL_ULX(i915) \
626	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)	626	IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
627	#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \	627	#define IS_CFL_GT2(i915) (IS_COFFEELAKE(i915) && \
628	INTEL_INFO(dev_priv)->gt == 2)	628	INTEL_INFO(i915)->gt == 2)
629	#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \	629	#define IS_CFL_GT3(i915) (IS_COFFEELAKE(i915) && \
630	INTEL_INFO(dev_priv)->gt == 3)	630	INTEL_INFO(i915)->gt == 3)
631		631
632	#define IS_CML_ULT(dev_priv) \	632	#define IS_CML_ULT(i915) \
633	IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)	633	IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
634	#define IS_CML_ULX(dev_priv) \	634	#define IS_CML_ULX(i915) \
635	IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)	635	IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
636	#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \	636	#define IS_CML_GT2(i915) (IS_COMETLAKE(i915) && \
637	INTEL_INFO(dev_priv)->gt == 2)	637	INTEL_INFO(i915)->gt == 2)
638		638
639	#define IS_ICL_WITH_PORT_F(dev_priv) \	639	#define IS_ICL_WITH_PORT_F(i915) \
640	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)	640	IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
641		641
642	#define IS_TGL_UY(dev_priv) \	642	#define IS_TGL_UY(i915) \
643	IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)	643	IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
644		644
645	#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))	645	#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
646		646
647	#define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \	647	#define IS_KBL_GRAPHICS_STEP(i915, since, until) \
648	(IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))	648	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
649	#define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \	649	#define IS_KBL_DISPLAY_STEP(i915, since, until) \
650	(IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))	650	(IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))
651		651
652	#define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \	652	#define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
653	(IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))	653	(IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
@@ -723,9 +723,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 69 unmodified lines
723	(IS_PONTEVECCHIO(__i915) && \	723	(IS_PONTEVECCHIO(__i915) && \
724	IS_GRAPHICS_STEP(__i915, since, until))	724	IS_GRAPHICS_STEP(__i915, since, until))
725		725
726	#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)	726	#define IS_LP(i915) (INTEL_INFO(i915)->is_lp)
727	#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))	727	#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915))
728	#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))	728	#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
729		729
730	#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))	730	#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
731	#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)	731	#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
@@ -750,122 +750,121 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 18 unmodified lines
750	#define CCS_MASK(gt) \	750	#define CCS_MASK(gt) \
751	ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)	751	ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
752		752
753	#define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)	753	#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
754		754
755	/*	755	/*
756	* The Gen7 cmdparser copies the scanned buffer to the ggtt for execution	756	* The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
757	* All later gens can run the final buffer from the ppgtt	757	* All later gens can run the final buffer from the ppgtt
758	*/	758	*/
759	#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)	759	#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
760		760
761	#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)	761	#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
762	#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)	762	#define HAS_4TILE(i915) (INTEL_INFO(i915)->has_4tile)
763	#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)	763	#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
764	#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)	764	#define HAS_EDRAM(i915) ((i915)->edram_size_mb)
765	#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)	765	#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
766	#define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)	766	#define HAS_WT(i915) HAS_EDRAM(i915)
767		767
768	#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)	768	#define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)
769		769
770	#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \	770	#define HAS_LOGICAL_RING_CONTEXTS(i915) \
771	(INTEL_INFO(dev_priv)->has_logical_ring_contexts)	771	(INTEL_INFO(i915)->has_logical_ring_contexts)
772	#define HAS_LOGICAL_RING_ELSQ(dev_priv) \	772	#define HAS_LOGICAL_RING_ELSQ(i915) \
773	(INTEL_INFO(dev_priv)->has_logical_ring_elsq)	773	(INTEL_INFO(i915)->has_logical_ring_elsq)
774		774
775	#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)	775	#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
776		776
777	#define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)	777	#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
778	#define HAS_PPGTT(dev_priv) \	778	#define HAS_PPGTT(i915) \
779	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)	779	(INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
780	#define HAS_FULL_PPGTT(dev_priv) \	780	#define HAS_FULL_PPGTT(i915) \
781	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)	781	(INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
782		782
783	#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \	783	#define HAS_PAGE_SIZES(i915, sizes) ({ \
784	GEM_BUG_ON((sizes) == 0); \	784	GEM_BUG_ON((sizes) == 0); \
785	((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \	785	((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
786	})	786	})
787		787
788	/* Early gen2 have a totally busted CS tlb and require pinned batches. */	788	/* Early gen2 have a totally busted CS tlb and require pinned batches. */
789	#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) \|\| IS_I845G(dev_priv))	789	#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) \|\| IS_I845G(i915))
790		790
791	#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \	791	#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \
792	(IS_BROADWELL(dev_priv) \|\| GRAPHICS_VER(dev_priv) == 9)	792	(IS_BROADWELL(i915) \|\| GRAPHICS_VER(i915) == 9)
793		793
794	/* WaRsDisableCoarsePowerGating:skl,cnl */	794	/* WaRsDisableCoarsePowerGating:skl,cnl */
795	#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \	795	#define NEEDS_WaRsDisableCoarsePowerGating(i915) \
796	(IS_SKL_GT3(dev_priv) \|\| IS_SKL_GT4(dev_priv))	796	(IS_SKL_GT3(i915) \|\| IS_SKL_GT4(i915))
797		797
798	/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte	798	/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
799	* rows, which changed the alignment requirements and fence programming.	799	* rows, which changed the alignment requirements and fence programming.
800	*/	800	*/
801	#define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \	801	#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
802	!(IS_I915G(dev_priv) \|\| IS_I915GM(dev_priv)))	802	!(IS_I915G(i915) \|\| IS_I915GM(i915)))
803		803
		804	#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
		805	#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
		806	#define HAS_RC6pp(i915) (false) /* HW was never validated */
804		807
805	#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)	808	#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
806	#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
807	#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
808		809
809	#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)	810	#define HAS_HECI_PXP(i915) \
		811	(INTEL_INFO(i915)->has_heci_pxp)
810		812
811	#define HAS_HECI_PXP(dev_priv) \	813	#define HAS_HECI_GSCFI(i915) \
812	(INTEL_INFO(dev_priv)->has_heci_pxp)	814	(INTEL_INFO(i915)->has_heci_gscfi)
813		815
814	#define HAS_HECI_GSCFI(dev_priv) \	816	#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) \|\| HAS_HECI_GSCFI(i915))
815	(INTEL_INFO(dev_priv)->has_heci_gscfi)
816		817
817	#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) \|\| HAS_HECI_GSCFI(dev_priv))	818	#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
		819	#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
818		820
819	#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)	821	#define HAS_OA_BPC_REPORTING(i915) \
820	#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)	822	(INTEL_INFO(i915)->has_oa_bpc_reporting)
821		823	#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
822	#define HAS_OA_BPC_REPORTING(dev_priv) \	824	(INTEL_INFO(i915)->has_oa_slice_contrib_limits)
823	(INTEL_INFO(dev_priv)->has_oa_bpc_reporting)	825	#define HAS_OAM(i915) \
824	#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \	826	(INTEL_INFO(i915)->has_oam)
825	(INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
826	#define HAS_OAM(dev_priv) \
827	(INTEL_INFO(dev_priv)->has_oam)
828		827
829	/*	828	/*
830	* Set this flag, when platform requires 64K GTT page sizes or larger for	829	* Set this flag, when platform requires 64K GTT page sizes or larger for
831	* device local memory access.	830	* device local memory access.
832	*/	831	*/
833	#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)	832	#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
834		833
835	#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))	834	#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
836	#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)	835	#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
837		836
838	#define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list)	837	#define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list)
839		838
840	/*	839	/*
841	* Platform has the dedicated compression control state for each lmem surfaces	840	* Platform has the dedicated compression control state for each lmem surfaces
842	* stored in lmem to support the 3D and media compression formats.	841	* stored in lmem to support the 3D and media compression formats.
843	*/	842	*/
844	#define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)	843	#define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)
845		844
846	#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)	845	#define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)
847		846
848	#define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)	847	#define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)
849		848
850	#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)	849	#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
851		850
852	#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)	851	#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
853		852
854	#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)	853	#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
855		854
856	/* DPF == dynamic parity feature */	855	/* DPF == dynamic parity feature */
857	#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)	856	#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
858	#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \	857	#define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
859	2 : HAS_L3_DPF(dev_priv))	858	2 : HAS_L3_DPF(i915))
860		859
861	/* Only valid when HAS_DISPLAY() is true */	860	/* Only valid when HAS_DISPLAY() is true */
862	#define INTEL_DISPLAY_ENABLED(dev_priv) \	861	#define INTEL_DISPLAY_ENABLED(i915) \
863	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), \	862	(drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \
864	!(dev_priv)->params.disable_display && \	863	!(i915)->params.disable_display && \
865	!intel_opregion_headless_sku(dev_priv))	864	!intel_opregion_headless_sku(i915))
866		865
867	#define HAS_GUC_DEPRIVILEGE(dev_priv) \	866	#define HAS_GUC_DEPRIVILEGE(i915) \
868	(INTEL_INFO(dev_priv)->has_guc_deprivilege)	867	(INTEL_INFO(i915)->has_guc_deprivilege)
869		868
870	#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)	869	#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
871		870

drivers/gpu/drm/i915/i915_gem.c+23−4

 		page_length = remain < page_length ? remain : page_length;
 		if (drm_mm_node_allocated(&node)) {
 			ggtt->vm.insert_page(&ggtt->vm,
-					     i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
+					     i915_gem_object_get_dma_address(obj,
-					     node.start, I915_CACHE_NONE, 0);
+									     offset >> PAGE_SHIFT),
+					     node.start,
+					     i915_gem_get_pat_index(i915,
+								    I915_CACHE_NONE), 0);
 		} else {
 			page_base += offset & PAGE_MASK;
 		}
 			/* flush the write before we modify the GGTT */
 			intel_gt_flush_ggtt_writes(ggtt->vm.gt);
 			ggtt->vm.insert_page(&ggtt->vm,
-					     i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
+					     i915_gem_object_get_dma_address(obj,
-					     node.start, I915_CACHE_NONE, 0);
+									     offset >> PAGE_SHIFT),
+					     node.start,
+					     i915_gem_get_pat_index(i915,
+								    I915_CACHE_NONE), 0);
 			wmb(); /* flush modifications to the GGTT (insert_page) */
 		} else {
 			page_base += offset & PAGE_MASK;
 	unsigned int i;
 	int ret;
+	/*
+	 * In the proccess of replacing cache_level with pat_index a tricky
+	 * dependency is created on the definition of the enum i915_cache_level.
+	 * in case this enum is changed, PTE encode would be broken.
+	 * Add a WARNING here. And remove when we completely quit using this
+	 * enum
+	 */
+	BUILD_BUG_ON(I915_CACHE_NONE != 0 ||
+		     I915_CACHE_LLC != 1 ||
+		     I915_CACHE_L3_LLC != 2 ||
+		     I915_CACHE_WT != 3 ||
+		     I915_MAX_CACHE_LEVEL != 4);
 	/* We need to fallback to 4K pages if host doesn't support huge gtt. */
 	if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
 		RUNTIME_INFO(dev_priv)->page_sizes = I915_GTT_PAGE_SIZE_4K;

drivers/gpu/drm/i915/i915_getparam.c+7−0

 #include "gem/i915_gem_mman.h"
 #include "gt/intel_engine_user.h"
+#include "pxp/intel_pxp.h"
 #include "i915_cmd_parser.h"
 #include "i915_drv.h"
 #include "i915_getparam.h"
 		if (value < 0)
 			return value;
 		break;
+	case I915_PARAM_PXP_STATUS:
+		value = intel_pxp_get_readiness_status(i915->pxp);
+		if (value < 0)
+			return value;
+		break;
 	case I915_PARAM_MMAP_GTT_VERSION:
 		/* Though we've started our numbering from 1, and so class all
 		 * earlier versions as 0, in effect their value is undefined as

drivers/gpu/drm/i915/i915_gpu_error.c+147−6

@@ -808,10 +808,15 @@ static void err_print_gt_engines(struct drm_i915_error_state_buf *m, · 807 unmodified lines
808	for (ee = gt->engine; ee; ee = ee->next) {	808	for (ee = gt->engine; ee; ee = ee->next) {
809	const struct i915_vma_coredump *vma;	809	const struct i915_vma_coredump *vma;
810		810
811	if (ee->guc_capture_node)	811	if (gt->uc && gt->uc->guc.is_guc_capture) {
812	intel_guc_capture_print_engine_node(m, ee);	812	if (ee->guc_capture_node)
813	else	813	intel_guc_capture_print_engine_node(m, ee);
		814	else
		815	err_printf(m, " Missing GuC capture node for %s\n",
		816	ee->engine->name);
		817	} else {
814	error_print_engine(m, ee);	818	error_print_engine(m, ee);
		819	}
815		820
816	err_printf(m, " hung: %u\n", ee->hung);	821	err_printf(m, " hung: %u\n", ee->hung);
817	err_printf(m, " engine reset count: %u\n", ee->reset_count);	822	err_printf(m, " engine reset count: %u\n", ee->reset_count);
@@ -1117,10 +1122,14 @@ i915_vma_coredump_create(const struct intel_gt *gt, · 299 unmodified lines
1117	mutex_lock(&ggtt->error_mutex);	1122	mutex_lock(&ggtt->error_mutex);
1118	if (ggtt->vm.raw_insert_page)	1123	if (ggtt->vm.raw_insert_page)
1119	ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot,	1124	ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot,
1120	I915_CACHE_NONE, 0);	1125	i915_gem_get_pat_index(gt->i915,
		1126	I915_CACHE_NONE),
		1127	0);
1121	else	1128	else
1122	ggtt->vm.insert_page(&ggtt->vm, dma, slot,	1129	ggtt->vm.insert_page(&ggtt->vm, dma, slot,
1123	I915_CACHE_NONE, 0);	1130	i915_gem_get_pat_index(gt->i915,
		1131	I915_CACHE_NONE),
		1132	0);
1124	mb();	1133	mb();
1125		1134
1126	s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);	1135	s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
@@ -2162,7 +2171,7 @@ void i915_error_state_store(struct i915_gpu_coredump *error) · 1035 unmodified lines
2162	* i915_capture_error_state - capture an error record for later analysis	2171	* i915_capture_error_state - capture an error record for later analysis
2163	* @gt: intel_gt which originated the hang	2172	* @gt: intel_gt which originated the hang
2164	* @engine_mask: hung engines	2173	* @engine_mask: hung engines
2165	*	2174	* @dump_flags: dump flags
2166	*	2175	*
2167	* Should be called when an error is detected (either a hang or an error	2176	* Should be called when an error is detected (either a hang or an error
2168	* interrupt) to capture error state from the time of the error. Fills	2177	* interrupt) to capture error state from the time of the error. Fills
@@ -2219,3 +2228,135 @@ void i915_disable_error_state(struct drm_i915_private *i915, int err) · 50 unmodified lines
2219	i915->gpu_error.first_error = ERR_PTR(err);	2228	i915->gpu_error.first_error = ERR_PTR(err);
2220	spin_unlock_irq(&i915->gpu_error.lock);	2229	spin_unlock_irq(&i915->gpu_error.lock);
2221	}	2230	}
		2231
		2232	#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
		2233	void intel_klog_error_capture(struct intel_gt *gt,
		2234	intel_engine_mask_t engine_mask)
		2235	{
		2236	static int g_count;
		2237	struct drm_i915_private *i915 = gt->i915;
		2238	struct i915_gpu_coredump *error;
		2239	intel_wakeref_t wakeref;
		2240	size_t buf_size = PAGE_SIZE * 128;
		2241	size_t pos_err;
		2242	char buf, ptr, *next;
		2243	int l_count = g_count++;
		2244	int line = 0;
		2245
		2246	/* Can't allocate memory during a reset */
		2247	if (test_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
		2248	drm_err(&gt->i915->drm, "[Capture/%d.%d] Inside GT reset, skipping error capture :(\n",
		2249	l_count, line++);
		2250	return;
		2251	}
		2252
		2253	error = READ_ONCE(i915->gpu_error.first_error);
		2254	if (error) {
		2255	drm_err(&i915->drm, "[Capture/%d.%d] Clearing existing error capture first...\n",
		2256	l_count, line++);
		2257	i915_reset_error_state(i915);
		2258	}
		2259
		2260	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
		2261	error = i915_gpu_coredump(gt, engine_mask, CORE_DUMP_FLAG_NONE);
		2262
		2263	if (IS_ERR(error)) {
		2264	drm_err(&i915->drm, "[Capture/%d.%d] Failed to capture error capture: %ld!\n",
		2265	l_count, line++, PTR_ERR(error));
		2266	return;
		2267	}
		2268
		2269	buf = kvmalloc(buf_size, GFP_KERNEL);
		2270	if (!buf) {
		2271	drm_err(&i915->drm, "[Capture/%d.%d] Failed to allocate buffer for error capture!\n",
		2272	l_count, line++);
		2273	i915_gpu_coredump_put(error);
		2274	return;
		2275	}
		2276
		2277	drm_info(&i915->drm, "[Capture/%d.%d] Dumping i915 error capture for %ps...\n",
		2278	l_count, line++, __builtin_return_address(0));
		2279
		2280	/* Largest string length safe to print via dmesg */
		2281	# define MAX_CHUNK 800
		2282
		2283	pos_err = 0;
		2284	while (1) {
		2285	ssize_t got = i915_gpu_coredump_copy_to_buffer(error, buf, pos_err, buf_size - 1);
		2286
		2287	if (got <= 0)
		2288	break;
		2289
		2290	buf[got] = 0;
		2291	pos_err += got;
		2292
		2293	ptr = buf;
		2294	while (got > 0) {
		2295	size_t count;
		2296	char tag[2];
		2297
		2298	next = strnchr(ptr, got, '\n');
		2299	if (next) {
		2300	count = next - ptr;
		2301	*next = 0;
		2302	tag[0] = '>';
		2303	tag[1] = '<';
		2304	} else {
		2305	count = got;
		2306	tag[0] = '}';
		2307	tag[1] = '{';
		2308	}
		2309
		2310	if (count > MAX_CHUNK) {
		2311	size_t pos;
		2312	char *ptr2 = ptr;
		2313
		2314	for (pos = MAX_CHUNK; pos < count; pos += MAX_CHUNK) {
		2315	char chr = ptr[pos];
		2316
		2317	ptr[pos] = 0;
		2318	drm_info(&i915->drm, "[Capture/%d.%d] }%s{\n",
		2319	l_count, line++, ptr2);
		2320	ptr[pos] = chr;
		2321	ptr2 = ptr + pos;
		2322
		2323	/*
		2324	* If spewing large amounts of data via a serial console,
		2325	* this can be a very slow process. So be friendly and try
		2326	* not to cause 'softlockup on CPU' problems.
		2327	*/
		2328	cond_resched();
		2329	}
		2330
		2331	if (ptr2 < (ptr + count))
		2332	drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n",
		2333	l_count, line++, tag[0], ptr2, tag[1]);
		2334	else if (tag[0] == '>')
		2335	drm_info(&i915->drm, "[Capture/%d.%d] ><\n",
		2336	l_count, line++);
		2337	} else {
		2338	drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n",
		2339	l_count, line++, tag[0], ptr, tag[1]);
		2340	}
		2341
		2342	ptr = next;
		2343	got -= count;
		2344	if (next) {
		2345	ptr++;
		2346	got--;
		2347	}
		2348
		2349	/* As above. */
		2350	cond_resched();
		2351	}
		2352
		2353	if (got)
		2354	drm_info(&i915->drm, "[Capture/%d.%d] Got %zd bytes remaining!\n",
		2355	l_count, line++, got);
		2356	}
		2357
		2358	kvfree(buf);
		2359
		2360	drm_info(&i915->drm, "[Capture/%d.%d] Dumped %zd bytes\n", l_count, line++, pos_err);
		2361	}
		2362	#endif

drivers/gpu/drm/i915/i915_gpu_error.h+10−0

@@ -258,6 +258,16 @@ static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, · 257 unmodified lines
258	#define CORE_DUMP_FLAG_NONE 0x0	258	#define CORE_DUMP_FLAG_NONE 0x0
259	#define CORE_DUMP_FLAG_IS_GUC_CAPTURE BIT(0)	259	#define CORE_DUMP_FLAG_IS_GUC_CAPTURE BIT(0)
260		260
		261	#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) && IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
		262	void intel_klog_error_capture(struct intel_gt *gt,
		263	intel_engine_mask_t engine_mask);
		264	#else
		265	static inline void intel_klog_error_capture(struct intel_gt *gt,
		266	intel_engine_mask_t engine_mask)
		267	{
		268	}
		269	#endif
		270
261	#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)	271	#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
262		272
263	__printf(2, 3)	273	__printf(2, 3)

drivers/gpu/drm/i915/i915_hwmon.c+75−12

@@ -50,6 +50,8 @@ struct hwm_drvdata { · 49 unmodified lines
50	struct hwm_energy_info ei; /* Energy info for energy1_input */	50	struct hwm_energy_info ei; /* Energy info for energy1_input */
51	char name[12];	51	char name[12];
52	int gt_n;	52	int gt_n;
		53	bool reset_in_progress;
		54	wait_queue_head_t waitq;
53	};	55	};
54		56
55	struct i915_hwmon {	57	struct i915_hwmon {
@@ -396,31 +398,56 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) · 340 unmodified lines
396	{	398	{
397	struct i915_hwmon *hwmon = ddat->hwmon;	399	struct i915_hwmon *hwmon = ddat->hwmon;
398	intel_wakeref_t wakeref;	400	intel_wakeref_t wakeref;
		401	DEFINE_WAIT(wait);
		402	int ret = 0;
399	u32 nval;	403	u32 nval;
400		404
401	/* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */	405	/* Block waiting for GuC reset to complete when needed */
402	if (val == PL1_DISABLE) {	406	for (;;) {
403	mutex_lock(&hwmon->hwmon_lock);	407	mutex_lock(&hwmon->hwmon_lock);
404	with_intel_runtime_pm(ddat->uncore->rpm, wakeref) {	408
405	intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit,	409	prepare_to_wait(&ddat->waitq, &wait, TASK_INTERRUPTIBLE);
406	PKG_PWR_LIM_1_EN, 0);	410
407	nval = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit);	411	if (!hwmon->ddat.reset_in_progress)
		412	break;
		413
		414	if (signal_pending(current)) {
		415	ret = -EINTR;
		416	break;
408	}	417	}
		418
409	mutex_unlock(&hwmon->hwmon_lock);	419	mutex_unlock(&hwmon->hwmon_lock);
410		420
		421	schedule();
		422	}
		423	finish_wait(&ddat->waitq, &wait);
		424	if (ret)
		425	goto unlock;
		426
		427	wakeref = intel_runtime_pm_get(ddat->uncore->rpm);
		428
		429	/* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */
		430	if (val == PL1_DISABLE) {
		431	intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit,
		432	PKG_PWR_LIM_1_EN, 0);
		433	nval = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit);
		434
411	if (nval & PKG_PWR_LIM_1_EN)	435	if (nval & PKG_PWR_LIM_1_EN)
412	return -ENODEV;	436	ret = -ENODEV;
413	return 0;	437	goto exit;
414	}	438	}
415		439
416	/* Computation in 64-bits to avoid overflow. Round to nearest. */	440	/* Computation in 64-bits to avoid overflow. Round to nearest. */
417	nval = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_power, SF_POWER);	441	nval = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_power, SF_POWER);
418	nval = PKG_PWR_LIM_1_EN \| REG_FIELD_PREP(PKG_PWR_LIM_1, nval);	442	nval = PKG_PWR_LIM_1_EN \| REG_FIELD_PREP(PKG_PWR_LIM_1, nval);
419		443
420	hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit,	444	intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit,
421	PKG_PWR_LIM_1_EN \| PKG_PWR_LIM_1,	445	PKG_PWR_LIM_1_EN \| PKG_PWR_LIM_1, nval);
422	nval);	446	exit:
423	return 0;	447	intel_runtime_pm_put(ddat->uncore->rpm, wakeref);
		448	unlock:
		449	mutex_unlock(&hwmon->hwmon_lock);
		450	return ret;
424	}	451	}
425		452
426	static int	453	static int
@@ -470,6 +497,41 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val) · 43 unmodified lines
470	}	497	}
471	}	498	}
472		499
		500	void i915_hwmon_power_max_disable(struct drm_i915_private i915, bool old)
		501	{
		502	struct i915_hwmon *hwmon = i915->hwmon;
		503	u32 r;
		504
		505	if (!hwmon \|\| !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit))
		506	return;
		507
		508	mutex_lock(&hwmon->hwmon_lock);
		509
		510	hwmon->ddat.reset_in_progress = true;
		511	r = intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit,
		512	PKG_PWR_LIM_1_EN, 0);
		513	*old = !!(r & PKG_PWR_LIM_1_EN);
		514
		515	mutex_unlock(&hwmon->hwmon_lock);
		516	}
		517
		518	void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old)
		519	{
		520	struct i915_hwmon *hwmon = i915->hwmon;
		521
		522	if (!hwmon \|\| !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit))
		523	return;
		524
		525	mutex_lock(&hwmon->hwmon_lock);
		526
		527	intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit,
		528	PKG_PWR_LIM_1_EN, old ? PKG_PWR_LIM_1_EN : 0);
		529	hwmon->ddat.reset_in_progress = false;
		530	wake_up_all(&hwmon->ddat.waitq);
		531
		532	mutex_unlock(&hwmon->hwmon_lock);
		533	}
		534
473	static umode_t	535	static umode_t
474	hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr)	536	hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr)
475	{	537	{
@@ -742,6 +804,7 @@ void i915_hwmon_register(struct drm_i915_private *i915) · 266 unmodified lines
742	ddat->uncore = &i915->uncore;	804	ddat->uncore = &i915->uncore;
743	snprintf(ddat->name, sizeof(ddat->name), "i915");	805	snprintf(ddat->name, sizeof(ddat->name), "i915");
744	ddat->gt_n = -1;	806	ddat->gt_n = -1;
		807	init_waitqueue_head(&ddat->waitq);
745		808
746	for_each_gt(gt, i915, i) {	809	for_each_gt(gt, i915, i) {
747	ddat_gt = hwmon->ddat_gt + i;	810	ddat_gt = hwmon->ddat_gt + i;

drivers/gpu/drm/i915/i915_hwmon.h+7−0

 #ifndef __I915_HWMON_H__
 #define __I915_HWMON_H__
+#include <linux/types.h>
 struct drm_i915_private;
+struct intel_gt;
 #if IS_REACHABLE(CONFIG_HWMON)
 void i915_hwmon_register(struct drm_i915_private *i915);
 void i915_hwmon_unregister(struct drm_i915_private *i915);
+void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old);
+void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old);
 #else
 static inline void i915_hwmon_register(struct drm_i915_private *i915) { };
 static inline void i915_hwmon_unregister(struct drm_i915_private *i915) { };
+static inline void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) { };
+static inline void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) { };
 #endif
 #endif /* __I915_HWMON_H__ */

drivers/gpu/drm/i915/i915_irq.c+11−6

 static void dg1_irq_reset(struct drm_i915_private *dev_priv)
 {
-	struct intel_gt *gt = to_gt(dev_priv);
+	struct intel_uncore *uncore = &dev_priv->uncore;
-	struct intel_uncore *uncore = gt->uncore;
+	struct intel_gt *gt;
+	unsigned int i;
 	dg1_master_intr_disable(dev_priv->uncore.regs);
-	gen11_gt_irq_reset(gt);
+	for_each_gt(gt, dev_priv, i)
+		gen11_gt_irq_reset(gt);
 	gen11_display_irq_reset(dev_priv);
 	GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 {
-	struct intel_gt *gt = to_gt(dev_priv);
+	struct intel_uncore *uncore = &dev_priv->uncore;
-	struct intel_uncore *uncore = gt->uncore;
 	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+	struct intel_gt *gt;
+	unsigned int i;
-	gen11_gt_irq_postinstall(gt);
+	for_each_gt(gt, dev_priv, i)
+		gen11_gt_irq_postinstall(gt);
 	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);

drivers/gpu/drm/i915/i915_pci.c+71−9

 #include "display/intel_display_driver.h"
 #include "gt/intel_gt_regs.h"
 #include "gt/intel_sa_media.h"
+#include "gem/i915_gem_object_types.h"
 #include "i915_driver.h"
 #include "i915_drv.h"
 	.__runtime.graphics.ip.ver = (x), \
 	.__runtime.media.ip.ver = (x)
+#define LEGACY_CACHELEVEL \
+	.cachelevel_to_pat = { \
+		[I915_CACHE_NONE]   = 0, \
+		[I915_CACHE_LLC]    = 1, \
+		[I915_CACHE_L3_LLC] = 2, \
+		[I915_CACHE_WT]     = 3, \
+	}
+#define TGL_CACHELEVEL \
+	.cachelevel_to_pat = { \
+		[I915_CACHE_NONE]   = 3, \
+		[I915_CACHE_LLC]    = 0, \
+		[I915_CACHE_L3_LLC] = 0, \
+		[I915_CACHE_WT]     = 2, \
+	}
+#define PVC_CACHELEVEL \
+	.cachelevel_to_pat = { \
+		[I915_CACHE_NONE]   = 0, \
+		[I915_CACHE_LLC]    = 3, \
+		[I915_CACHE_L3_LLC] = 3, \
+		[I915_CACHE_WT]     = 2, \
+	}
+#define MTL_CACHELEVEL \
+	.cachelevel_to_pat = { \
+		[I915_CACHE_NONE]   = 2, \
+		[I915_CACHE_LLC]    = 3, \
+		[I915_CACHE_L3_LLC] = 3, \
+		[I915_CACHE_WT]     = 1, \
+	}
 /* Keep in gen based order, and chronological order within a gen */
 #define GEN_DEFAULT_PAGE_SIZES \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
 	.dma_mask_size = 32, \
+	.max_pat_index = 3, \
 	GEN_DEFAULT_PAGE_SIZES, \
-	GEN_DEFAULT_REGIONS
+	GEN_DEFAULT_REGIONS, \
+	LEGACY_CACHELEVEL
 #define I845_FEATURES \
 	GEN(2), \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
 	.dma_mask_size = 32, \
+	.max_pat_index = 3, \
 	GEN_DEFAULT_PAGE_SIZES, \
-	GEN_DEFAULT_REGIONS
+	GEN_DEFAULT_REGIONS, \
+	LEGACY_CACHELEVEL
 static const struct intel_device_info i830_info = {
 	I830_FEATURES,
 	.has_snoop = true, \
 	.has_coherent_ggtt = true, \
 	.dma_mask_size = 32, \
+	.max_pat_index = 3, \
 	GEN_DEFAULT_PAGE_SIZES, \
-	GEN_DEFAULT_REGIONS
+	GEN_DEFAULT_REGIONS, \
+	LEGACY_CACHELEVEL
 static const struct intel_device_info i915g_info = {
 	GEN3_FEATURES,
 	.has_snoop = true, \
 	.has_coherent_ggtt = true, \
 	.dma_mask_size = 36, \
+	.max_pat_index = 3, \
 	GEN_DEFAULT_PAGE_SIZES, \
-	GEN_DEFAULT_REGIONS
+	GEN_DEFAULT_REGIONS, \
+	LEGACY_CACHELEVEL
 static const struct intel_device_info i965g_info = {
 	GEN4_FEATURES,
 	/* ilk does support rc6, but we do not implement [power] contexts */ \
 	.has_rc6 = 0, \
 	.dma_mask_size = 36, \
+	.max_pat_index = 3, \
 	GEN_DEFAULT_PAGE_SIZES, \
-	GEN_DEFAULT_REGIONS
+	GEN_DEFAULT_REGIONS, \
+	LEGACY_CACHELEVEL
 static const struct intel_device_info ilk_d_info = {
 	GEN5_FEATURES,
 	.has_rc6p = 0, \
 	.has_rps = true, \
 	.dma_mask_size = 40, \
+	.max_pat_index = 3, \
 	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
 	.__runtime.ppgtt_size = 31, \
 	GEN_DEFAULT_PAGE_SIZES, \
-	GEN_DEFAULT_REGIONS
+	GEN_DEFAULT_REGIONS, \
+	LEGACY_CACHELEVEL
 #define SNB_D_PLATFORM \
 	GEN6_FEATURES, \
 	.has_reset_engine = true, \
 	.has_rps = true, \
 	.dma_mask_size = 40, \
+	.max_pat_index = 3, \
 	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
 	.__runtime.ppgtt_size = 31, \
 	GEN_DEFAULT_PAGE_SIZES, \
-	GEN_DEFAULT_REGIONS
+	GEN_DEFAULT_REGIONS, \
+	LEGACY_CACHELEVEL
 #define IVB_D_PLATFORM \
 	GEN7_FEATURES, \
 	.has_reset_engine = true,
 	.has_rps = true,
 	.dma_mask_size = 40,
+	.max_pat_index = 3,
 	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
 	.__runtime.ppgtt_size = 31,
 	.has_snoop = true,
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
 	GEN_DEFAULT_PAGE_SIZES,
 	GEN_DEFAULT_REGIONS,
+	LEGACY_CACHELEVEL,
 };
 #define G75_FEATURES  \
 	.has_rps = true,
 	.has_logical_ring_contexts = 1,
 	.dma_mask_size = 39,
+	.max_pat_index = 3,
 	.__runtime.ppgtt_type = INTEL_PPGTT_FULL,
 	.__runtime.ppgtt_size = 32,
 	.has_reset_engine = 1,
 	.has_coherent_ggtt = false,
 	GEN_DEFAULT_PAGE_SIZES,
 	GEN_DEFAULT_REGIONS,
+	LEGACY_CACHELEVEL,
 };
 #define GEN9_DEFAULT_PAGE_SIZES \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
+	.max_pat_index = 3, \
 	GEN9_DEFAULT_PAGE_SIZES, \
-	GEN_DEFAULT_REGIONS
+	GEN_DEFAULT_REGIONS, \
+	LEGACY_CACHELEVEL
 static const struct intel_device_info bxt_info = {
 	GEN9_LP_FEATURES,
 #define GEN12_FEATURES \
 	GEN11_FEATURES, \
 	GEN(12), \
+	TGL_CACHELEVEL, \
 	.has_global_mocs = 1, \
-	.has_pxp = 1
+	.has_pxp = 1, \
+	.max_pat_index = 3
 static const struct intel_device_info tgl_info = {
 	GEN12_FEATURES,
 	.__runtime.graphics.ip.ver = 12, \
 	.__runtime.graphics.ip.rel = 50, \
 	XE_HP_PAGE_SIZES, \
+	TGL_CACHELEVEL, \
 	.dma_mask_size = 46, \
 	.has_3d_pipeline = 1, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1, \
 	.has_rps = 1, \
 	.has_runtime_pm = 1, \
+	.max_pat_index = 3, \
 	.__runtime.ppgtt_size = 48, \
 	.__runtime.ppgtt_type = INTEL_PPGTT_FULL
 	.__runtime.media.ip.rel = 60,
 	PLATFORM(INTEL_PONTEVECCHIO),
 	.has_flat_ccs = 0,
+	.max_pat_index = 7,
 	.__runtime.platform_engine_mask =
 		BIT(BCS0) |
 		BIT(VCS0) |
 		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
 	.require_force_probe = 1,
+	PVC_CACHELEVEL,
 };
 static const struct intel_gt_definition xelpmp_extra_gt[] = {
 	.has_llc = 0,
 	.has_mslice_steering = 0,
 	.has_snoop = 1,
+	.max_pat_index = 4,
+	.has_pxp = 1,
 	.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
 	.require_force_probe = 1,
+	MTL_CACHELEVEL,
 };
 #undef PLATFORM

drivers/gpu/drm/i915/i915_perf.c+1−0

@@ -5300,6 +5300,7 @@ void i915_perf_fini(struct drm_i915_private *i915) · 5299 unmodified lines
5300		5300
5301	/**	5301	/**
5302	* i915_perf_ioctl_version - Version of the i915-perf subsystem	5302	* i915_perf_ioctl_version - Version of the i915-perf subsystem
		5303	* @i915: The i915 device
5303	*	5304	*
5304	* This version number is used by userspace to detect available features.	5305	* This version number is used by userspace to detect available features.
5305	*/	5306	*/

drivers/gpu/drm/i915/i915_perf_oa_regs.h+0−4

 #define GDT_CHICKEN_BITS    _MMIO(0x9840)
 #define   GT_NOA_ENABLE	    0x00000080
-#define GEN12_SQCNT1				_MMIO(0x8718)
-#define   GEN12_SQCNT1_PMON_ENABLE		REG_BIT(30)
-#define   GEN12_SQCNT1_OABPC			REG_BIT(29)
 /* Gen12 OAM unit */
 #define GEN12_OAM_HEAD_POINTER_OFFSET   (0x1a0)
 #define  GEN12_OAM_HEAD_POINTER_MASK    0xffffffc0

drivers/gpu/drm/i915/i915_pmu.c+205−85

@@ -10,6 +10,7 @@ · 9 unmodified lines
10	#include "gt/intel_engine_pm.h"	10	#include "gt/intel_engine_pm.h"
11	#include "gt/intel_engine_regs.h"	11	#include "gt/intel_engine_regs.h"
12	#include "gt/intel_engine_user.h"	12	#include "gt/intel_engine_user.h"
		13	#include "gt/intel_gt.h"
13	#include "gt/intel_gt_pm.h"	14	#include "gt/intel_gt_pm.h"
14	#include "gt/intel_gt_regs.h"	15	#include "gt/intel_gt_regs.h"
15	#include "gt/intel_rc6.h"	16	#include "gt/intel_rc6.h"
@@ -50,16 +51,26 @@ static u8 engine_event_instance(struct perf_event *event) · 34 unmodified lines
50	return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;	51	return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
51	}	52	}
52		53
53	static bool is_engine_config(u64 config)	54	static bool is_engine_config(const u64 config)
54	{	55	{
55	return config < __I915_PMU_OTHER(0);	56	return config < __I915_PMU_OTHER(0);
56	}	57	}
57		58
		59	static unsigned int config_gt_id(const u64 config)
		60	{
		61	return config >> __I915_PMU_GT_SHIFT;
		62	}
		63
		64	static u64 config_counter(const u64 config)
		65	{
		66	return config & ~(~0ULL << __I915_PMU_GT_SHIFT);
		67	}
		68
58	static unsigned int other_bit(const u64 config)	69	static unsigned int other_bit(const u64 config)
59	{	70	{
60	unsigned int val;	71	unsigned int val;
61		72
62	switch (config) {	73	switch (config_counter(config)) {
63	case I915_PMU_ACTUAL_FREQUENCY:	74	case I915_PMU_ACTUAL_FREQUENCY:
64	val = __I915_PMU_ACTUAL_FREQUENCY_ENABLED;	75	val = __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
65	break;	76	break;
@@ -77,7 +88,9 @@ static unsigned int other_bit(const u64 config) · 11 unmodified lines
77	return -1;	88	return -1;
78	}	89	}
79		90
80	return I915_ENGINE_SAMPLE_COUNT + val;	91	return I915_ENGINE_SAMPLE_COUNT +
		92	config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT +
		93	val;
81	}	94	}
82		95
83	static unsigned int config_bit(const u64 config)	96	static unsigned int config_bit(const u64 config)
@@ -88,9 +101,20 @@ static unsigned int config_bit(const u64 config) · 4 unmodified lines
88	return other_bit(config);	101	return other_bit(config);
89	}	102	}
90		103
91	static u64 config_mask(u64 config)	104	static u32 config_mask(const u64 config)
92	{	105	{
93	return BIT_ULL(config_bit(config));	106	unsigned int bit = config_bit(config);
		107
		108	if (__builtin_constant_p(config))
		109	BUILD_BUG_ON(bit >
		110	BITS_PER_TYPE(typeof_member(struct i915_pmu,
		111	enable)) - 1);
		112	else
		113	WARN_ON_ONCE(bit >
		114	BITS_PER_TYPE(typeof_member(struct i915_pmu,
		115	enable)) - 1);
		116
		117	return BIT(config_bit(config));
94	}	118	}
95		119
96	static bool is_engine_event(struct perf_event *event)	120	static bool is_engine_event(struct perf_event *event)
@@ -103,6 +127,18 @@ static unsigned int event_bit(struct perf_event *event) · 6 unmodified lines
103	return config_bit(event->attr.config);	127	return config_bit(event->attr.config);
104	}	128	}
105		129
		130	static u32 frequency_enabled_mask(void)
		131	{
		132	unsigned int i;
		133	u32 mask = 0;
		134
		135	for (i = 0; i < I915_PMU_MAX_GTS; i++)
		136	mask \|= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) \|
		137	config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
		138
		139	return mask;
		140	}
		141
106	static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)	142	static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
107	{	143	{
108	struct drm_i915_private i915 = container_of(pmu, typeof(i915), pmu);	144	struct drm_i915_private i915 = container_of(pmu, typeof(i915), pmu);
@@ -119,9 +155,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active) · 10 unmodified lines
119	* Mask out all the ones which do not need the timer, or in	155	* Mask out all the ones which do not need the timer, or in
120	* other words keep all the ones that could need the timer.	156	* other words keep all the ones that could need the timer.
121	*/	157	*/
122	enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) \|	158	enable &= frequency_enabled_mask() \| ENGINE_SAMPLE_MASK;
123	config_mask(I915_PMU_REQUESTED_FREQUENCY) \|
124	ENGINE_SAMPLE_MASK;
125		159
126	/*	160	/*
127	* When the GPU is idle per-engine counters do not need to be	161	* When the GPU is idle per-engine counters do not need to be
@@ -163,9 +197,37 @@ static inline s64 ktime_since_raw(const ktime_t kt) · 35 unmodified lines
163	return ktime_to_ns(ktime_sub(ktime_get_raw(), kt));	197	return ktime_to_ns(ktime_sub(ktime_get_raw(), kt));
164	}	198	}
165		199
		200	static unsigned int
		201	__sample_idx(struct i915_pmu *pmu, unsigned int gt_id, int sample)
		202	{
		203	unsigned int idx = gt_id * __I915_NUM_PMU_SAMPLERS + sample;
		204
		205	GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
		206
		207	return idx;
		208	}
		209
		210	static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample)
		211	{
		212	return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
		213	}
		214
		215	static void
		216	store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val)
		217	{
		218	pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
		219	}
		220
		221	static void
		222	add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val, u32 mul)
		223	{
		224	pmu->sample[__sample_idx(pmu, gt_id, sample)].cur += mul_u32_u32(val, mul);
		225	}
		226
166	static u64 get_rc6(struct intel_gt *gt)	227	static u64 get_rc6(struct intel_gt *gt)
167	{	228	{
168	struct drm_i915_private *i915 = gt->i915;	229	struct drm_i915_private *i915 = gt->i915;
		230	const unsigned int gt_id = gt->info.id;
169	struct i915_pmu *pmu = &i915->pmu;	231	struct i915_pmu *pmu = &i915->pmu;
170	unsigned long flags;	232	unsigned long flags;
171	bool awake = false;	233	bool awake = false;
@@ -180,7 +242,7 @@ static u64 get_rc6(struct intel_gt *gt) · 8 unmodified lines
180	spin_lock_irqsave(&pmu->lock, flags);	242	spin_lock_irqsave(&pmu->lock, flags);
181		243
182	if (awake) {	244	if (awake) {
183	pmu->sample[__I915_SAMPLE_RC6].cur = val;	245	store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val);
184	} else {	246	} else {
185	/*	247	/*
186	* We think we are runtime suspended.	248	* We think we are runtime suspended.
@@ -189,14 +251,14 @@ static u64 get_rc6(struct intel_gt *gt) · 2 unmodified lines
189	* on top of the last known real value, as the approximated RC6	251	* on top of the last known real value, as the approximated RC6
190	* counter value.	252	* counter value.
191	*/	253	*/
192	val = ktime_since_raw(pmu->sleep_last);	254	val = ktime_since_raw(pmu->sleep_last[gt_id]);
193	val += pmu->sample[__I915_SAMPLE_RC6].cur;	255	val += read_sample(pmu, gt_id, __I915_SAMPLE_RC6);
194	}	256	}
195		257
196	if (val < pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur)	258	if (val < read_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED))
197	val = pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur;	259	val = read_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED);
198	else	260	else
199	pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur = val;	261	store_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED, val);
200		262
201	spin_unlock_irqrestore(&pmu->lock, flags);	263	spin_unlock_irqrestore(&pmu->lock, flags);
202		264
@@ -206,22 +268,29 @@ static u64 get_rc6(struct intel_gt *gt) · 3 unmodified lines
206	static void init_rc6(struct i915_pmu *pmu)	268	static void init_rc6(struct i915_pmu *pmu)
207	{	269	{
208	struct drm_i915_private i915 = container_of(pmu, typeof(i915), pmu);	270	struct drm_i915_private i915 = container_of(pmu, typeof(i915), pmu);
209	intel_wakeref_t wakeref;	271	struct intel_gt *gt;
		272	unsigned int i;
210		273
211	with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref) {	274	for_each_gt(gt, i915, i) {
212	pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915));	275	intel_wakeref_t wakeref;
213	pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur =	276
214	pmu->sample[__I915_SAMPLE_RC6].cur;	277	with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
215	pmu->sleep_last = ktime_get_raw();	278	u64 val = __get_rc6(gt);
		279
		280	store_sample(pmu, i, __I915_SAMPLE_RC6, val);
		281	store_sample(pmu, i, __I915_SAMPLE_RC6_LAST_REPORTED,
		282	val);
		283	pmu->sleep_last[i] = ktime_get_raw();
		284	}
216	}	285	}
217	}	286	}
218		287
219	static void park_rc6(struct drm_i915_private *i915)	288	static void park_rc6(struct intel_gt *gt)
220	{	289	{
221	struct i915_pmu *pmu = &i915->pmu;	290	struct i915_pmu *pmu = &gt->i915->pmu;
222		291
223	pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915));	292	store_sample(pmu, gt->info.id, __I915_SAMPLE_RC6, __get_rc6(gt));
224	pmu->sleep_last = ktime_get_raw();	293	pmu->sleep_last[gt->info.id] = ktime_get_raw();
225	}	294	}
226		295
227	static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu)	296	static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu)
@@ -235,29 +304,31 @@ static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu) · 7 unmodified lines
235	}	304	}
236	}	305	}
237		306
238	void i915_pmu_gt_parked(struct drm_i915_private *i915)	307	void i915_pmu_gt_parked(struct intel_gt *gt)
239	{	308	{
240	struct i915_pmu *pmu = &i915->pmu;	309	struct i915_pmu *pmu = &gt->i915->pmu;
241		310
242	if (!pmu->base.event_init)	311	if (!pmu->base.event_init)
243	return;	312	return;
244		313
245	spin_lock_irq(&pmu->lock);	314	spin_lock_irq(&pmu->lock);
246		315
247	park_rc6(i915);	316	park_rc6(gt);
248		317
249	/*	318	/*
250	* Signal sampling timer to stop if only engine events are enabled and	319	* Signal sampling timer to stop if only engine events are enabled and
251	* GPU went idle.	320	* GPU went idle.
252	*/	321	*/
253	pmu->timer_enabled = pmu_needs_timer(pmu, false);	322	pmu->unparked &= ~BIT(gt->info.id);
		323	if (pmu->unparked == 0)
		324	pmu->timer_enabled = pmu_needs_timer(pmu, false);
254		325
255	spin_unlock_irq(&pmu->lock);	326	spin_unlock_irq(&pmu->lock);
256	}	327	}
257		328
258	void i915_pmu_gt_unparked(struct drm_i915_private *i915)	329	void i915_pmu_gt_unparked(struct intel_gt *gt)
259	{	330	{
260	struct i915_pmu *pmu = &i915->pmu;	331	struct i915_pmu *pmu = &gt->i915->pmu;
261		332
262	if (!pmu->base.event_init)	333	if (!pmu->base.event_init)
263	return;	334	return;
@@ -267,7 +338,10 @@ void i915_pmu_gt_unparked(struct drm_i915_private *i915) · 3 unmodified lines
267	/*	338	/*
268	* Re-enable sampling timer when GPU goes active.	339	* Re-enable sampling timer when GPU goes active.
269	*/	340	*/
270	__i915_pmu_maybe_start_timer(pmu);	341	if (pmu->unparked == 0)
		342	__i915_pmu_maybe_start_timer(pmu);
		343
		344	pmu->unparked \|= BIT(gt->info.id);
271		345
272	spin_unlock_irq(&pmu->lock);	346	spin_unlock_irq(&pmu->lock);
273	}	347	}
@@ -338,6 +412,9 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns) · 64 unmodified lines
338	return;	412	return;
339		413
340	for_each_engine(engine, gt, id) {	414	for_each_engine(engine, gt, id) {
		415	if (!engine->pmu.enable)
		416	continue;
		417
341	if (!intel_engine_pm_get_if_awake(engine))	418	if (!intel_engine_pm_get_if_awake(engine))
342	continue;	419	continue;
343		420
@@ -353,34 +430,30 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns) · 9 unmodified lines
353	}	430	}
354	}	431	}
355		432
356	static void	433	static bool
357	add_sample_mult(struct i915_pmu_sample *sample, u32 val, u32 mul)	434	frequency_sampling_enabled(struct i915_pmu *pmu, unsigned int gt)
358	{
359	sample->cur += mul_u32_u32(val, mul);
360	}
361
362	static bool frequency_sampling_enabled(struct i915_pmu *pmu)
363	{	435	{
364	return pmu->enable &	436	return pmu->enable &
365	(config_mask(I915_PMU_ACTUAL_FREQUENCY) \|	437	(config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt)) \|
366	config_mask(I915_PMU_REQUESTED_FREQUENCY));	438	config_mask(__I915_PMU_REQUESTED_FREQUENCY(gt)));
367	}	439	}
368		440
369	static void	441	static void
370	frequency_sample(struct intel_gt *gt, unsigned int period_ns)	442	frequency_sample(struct intel_gt *gt, unsigned int period_ns)
371	{	443	{
372	struct drm_i915_private *i915 = gt->i915;	444	struct drm_i915_private *i915 = gt->i915;
		445	const unsigned int gt_id = gt->info.id;
373	struct i915_pmu *pmu = &i915->pmu;	446	struct i915_pmu *pmu = &i915->pmu;
374	struct intel_rps *rps = &gt->rps;	447	struct intel_rps *rps = &gt->rps;
375		448
376	if (!frequency_sampling_enabled(pmu))	449	if (!frequency_sampling_enabled(pmu, gt_id))
377	return;	450	return;
378		451
379	/* Report 0/0 (actual/requested) frequency while parked. */	452	/* Report 0/0 (actual/requested) frequency while parked. */
380	if (!intel_gt_pm_get_if_awake(gt))	453	if (!intel_gt_pm_get_if_awake(gt))
381	return;	454	return;
382		455
383	if (pmu->enable & config_mask(I915_PMU_ACTUAL_FREQUENCY)) {	456	if (pmu->enable & config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt_id))) {
384	u32 val;	457	u32 val;
385		458
386	/*	459	/*
@@ -396,12 +469,12 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) · 9 unmodified lines
396	if (!val)	469	if (!val)
397	val = intel_gpu_freq(rps, rps->cur_freq);	470	val = intel_gpu_freq(rps, rps->cur_freq);
398		471
399	add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_ACT],	472	add_sample_mult(pmu, gt_id, __I915_SAMPLE_FREQ_ACT,
400	val, period_ns / 1000);	473	val, period_ns / 1000);
401	}	474	}
402		475
403	if (pmu->enable & config_mask(I915_PMU_REQUESTED_FREQUENCY)) {	476	if (pmu->enable & config_mask(__I915_PMU_REQUESTED_FREQUENCY(gt_id))) {
404	add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_REQ],	477	add_sample_mult(pmu, gt_id, __I915_SAMPLE_FREQ_REQ,
405	intel_rps_get_requested_frequency(rps),	478	intel_rps_get_requested_frequency(rps),
406	period_ns / 1000);	479	period_ns / 1000);
407	}	480	}
@@ -414,8 +487,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) · 6 unmodified lines
414	struct drm_i915_private *i915 =	487	struct drm_i915_private *i915 =
415	container_of(hrtimer, struct drm_i915_private, pmu.timer);	488	container_of(hrtimer, struct drm_i915_private, pmu.timer);
416	struct i915_pmu *pmu = &i915->pmu;	489	struct i915_pmu *pmu = &i915->pmu;
417	struct intel_gt *gt = to_gt(i915);
418	unsigned int period_ns;	490	unsigned int period_ns;
		491	struct intel_gt *gt;
		492	unsigned int i;
419	ktime_t now;	493	ktime_t now;
420		494
421	if (!READ_ONCE(pmu->timer_enabled))	495	if (!READ_ONCE(pmu->timer_enabled))
@@ -431,8 +505,14 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) · 9 unmodified lines
431	* grabbing the forcewake. However the potential error from timer call-	505	* grabbing the forcewake. However the potential error from timer call-
432	* back delay greatly dominates this so we keep it simple.	506	* back delay greatly dominates this so we keep it simple.
433	*/	507	*/
434	engines_sample(gt, period_ns);	508
435	frequency_sample(gt, period_ns);	509	for_each_gt(gt, i915, i) {
		510	if (!(pmu->unparked & BIT(i)))
		511	continue;
		512
		513	engines_sample(gt, period_ns);
		514	frequency_sample(gt, period_ns);
		515	}
436		516
437	hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));	517	hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));
438		518
@@ -473,7 +553,13 @@ config_status(struct drm_i915_private *i915, u64 config) · 34 unmodified lines
473	{	553	{
474	struct intel_gt *gt = to_gt(i915);	554	struct intel_gt *gt = to_gt(i915);
475		555
476	switch (config) {	556	unsigned int gt_id = config_gt_id(config);
		557	unsigned int max_gt_id = HAS_EXTRA_GT_LIST(i915) ? 1 : 0;
		558
		559	if (gt_id > max_gt_id)
		560	return -ENOENT;
		561
		562	switch (config_counter(config)) {
477	case I915_PMU_ACTUAL_FREQUENCY:	563	case I915_PMU_ACTUAL_FREQUENCY:
478	if (IS_VALLEYVIEW(i915) \|\| IS_CHERRYVIEW(i915))	564	if (IS_VALLEYVIEW(i915) \|\| IS_CHERRYVIEW(i915))
479	/* Requires a mutex for sampling! */	565	/* Requires a mutex for sampling! */
@@ -484,6 +570,8 @@ config_status(struct drm_i915_private *i915, u64 config) · 4 unmodified lines
484	return -ENODEV;	570	return -ENODEV;
485	break;	571	break;
486	case I915_PMU_INTERRUPTS:	572	case I915_PMU_INTERRUPTS:
		573	if (gt_id)
		574	return -ENOENT;
487	break;	575	break;
488	case I915_PMU_RC6_RESIDENCY:	576	case I915_PMU_RC6_RESIDENCY:
489	if (!gt->rc6.supported)	577	if (!gt->rc6.supported)
@@ -581,22 +669,27 @@ static u64 __i915_pmu_event_read(struct perf_event *event) · 91 unmodified lines
581	val = engine->pmu.sample[sample].cur;	669	val = engine->pmu.sample[sample].cur;
582	}	670	}
583	} else {	671	} else {
584	switch (event->attr.config) {	672	const unsigned int gt_id = config_gt_id(event->attr.config);
		673	const u64 config = config_counter(event->attr.config);
		674
		675	switch (config) {
585	case I915_PMU_ACTUAL_FREQUENCY:	676	case I915_PMU_ACTUAL_FREQUENCY:
586	val =	677	val =
587	div_u64(pmu->sample[__I915_SAMPLE_FREQ_ACT].cur,	678	div_u64(read_sample(pmu, gt_id,
		679	__I915_SAMPLE_FREQ_ACT),
588	USEC_PER_SEC /* to MHz */);	680	USEC_PER_SEC /* to MHz */);
589	break;	681	break;
590	case I915_PMU_REQUESTED_FREQUENCY:	682	case I915_PMU_REQUESTED_FREQUENCY:
591	val =	683	val =
592	div_u64(pmu->sample[__I915_SAMPLE_FREQ_REQ].cur,	684	div_u64(read_sample(pmu, gt_id,
		685	__I915_SAMPLE_FREQ_REQ),
593	USEC_PER_SEC /* to MHz */);	686	USEC_PER_SEC /* to MHz */);
594	break;	687	break;
595	case I915_PMU_INTERRUPTS:	688	case I915_PMU_INTERRUPTS:
596	val = READ_ONCE(pmu->irq_count);	689	val = READ_ONCE(pmu->irq_count);
597	break;	690	break;
598	case I915_PMU_RC6_RESIDENCY:	691	case I915_PMU_RC6_RESIDENCY:
599	val = get_rc6(to_gt(i915));	692	val = get_rc6(i915->gt[gt_id]);
600	break;	693	break;
601	case I915_PMU_SOFTWARE_GT_AWAKE_TIME:	694	case I915_PMU_SOFTWARE_GT_AWAKE_TIME:
602	val = ktime_to_ns(intel_gt_get_awake_time(to_gt(i915)));	695	val = ktime_to_ns(intel_gt_get_awake_time(to_gt(i915)));
@@ -633,11 +726,10 @@ static void i915_pmu_enable(struct perf_event *event) · 30 unmodified lines
633	{	726	{
634	struct drm_i915_private *i915 =	727	struct drm_i915_private *i915 =
635	container_of(event->pmu, typeof(*i915), pmu.base);	728	container_of(event->pmu, typeof(*i915), pmu.base);
		729	const unsigned int bit = event_bit(event);
636	struct i915_pmu *pmu = &i915->pmu;	730	struct i915_pmu *pmu = &i915->pmu;
637	unsigned long flags;	731	unsigned long flags;
638	unsigned int bit;
639		732
640	bit = event_bit(event);
641	if (bit == -1)	733	if (bit == -1)
642	goto update;	734	goto update;
643		735
@@ -651,7 +743,7 @@ static void i915_pmu_enable(struct perf_event *event) · 7 unmodified lines
651	GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));	743	GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
652	GEM_BUG_ON(pmu->enable_count[bit] == ~0);	744	GEM_BUG_ON(pmu->enable_count[bit] == ~0);
653		745
654	pmu->enable \|= BIT_ULL(bit);	746	pmu->enable \|= BIT(bit);
655	pmu->enable_count[bit]++;	747	pmu->enable_count[bit]++;
656		748
657	/*	749	/*
@@ -698,7 +790,7 @@ static void i915_pmu_disable(struct perf_event *event) · 40 unmodified lines
698	{	790	{
699	struct drm_i915_private *i915 =	791	struct drm_i915_private *i915 =
700	container_of(event->pmu, typeof(*i915), pmu.base);	792	container_of(event->pmu, typeof(*i915), pmu.base);
701	unsigned int bit = event_bit(event);	793	const unsigned int bit = event_bit(event);
702	struct i915_pmu *pmu = &i915->pmu;	794	struct i915_pmu *pmu = &i915->pmu;
703	unsigned long flags;	795	unsigned long flags;
704		796
@@ -734,7 +826,7 @@ static void i915_pmu_disable(struct perf_event *event) · 29 unmodified lines
734	* bitmask when the last listener on an event goes away.	826	* bitmask when the last listener on an event goes away.
735	*/	827	*/
736	if (--pmu->enable_count[bit] == 0) {	828	if (--pmu->enable_count[bit] == 0) {
737	pmu->enable &= ~BIT_ULL(bit);	829	pmu->enable &= ~BIT(bit);
738	pmu->timer_enabled &= pmu_needs_timer(pmu, true);	830	pmu->timer_enabled &= pmu_needs_timer(pmu, true);
739	}	831	}
740		832
@@ -848,11 +940,20 @@ static const struct attribute_group i915_pmu_cpumask_attr_group = { · 107 unmodified lines
848	.attrs = i915_cpumask_attrs,	940	.attrs = i915_cpumask_attrs,
849	};	941	};
850		942
851	#define __event(__config, __name, __unit) \	943	#define __event(__counter, __name, __unit) \
852	{ \	944	{ \
853	.config = (__config), \	945	.counter = (__counter), \
854	.name = (__name), \	946	.name = (__name), \
855	.unit = (__unit), \	947	.unit = (__unit), \
		948	.global = false, \
		949	}
		950
		951	#define __global_event(__counter, __name, __unit) \
		952	{ \
		953	.counter = (__counter), \
		954	.name = (__name), \
		955	.unit = (__unit), \
		956	.global = true, \
856	}	957	}
857		958
858	#define __engine_event(__sample, __name) \	959	#define __engine_event(__sample, __name) \
@@ -891,15 +992,16 @@ create_event_attributes(struct i915_pmu *pmu) · 32 unmodified lines
891	{	992	{
892	struct drm_i915_private i915 = container_of(pmu, typeof(i915), pmu);	993	struct drm_i915_private i915 = container_of(pmu, typeof(i915), pmu);
893	static const struct {	994	static const struct {
894	u64 config;	995	unsigned int counter;
895	const char *name;	996	const char *name;
896	const char *unit;	997	const char *unit;
		998	bool global;
897	} events[] = {	999	} events[] = {
898	__event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"),	1000	__event(0, "actual-frequency", "M"),
899	__event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency", "M"),	1001	__event(1, "requested-frequency", "M"),
900	__event(I915_PMU_INTERRUPTS, "interrupts", NULL),	1002	__global_event(2, "interrupts", NULL),
901	__event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"),	1003	__event(3, "rc6-residency", "ns"),
902	__event(I915_PMU_SOFTWARE_GT_AWAKE_TIME, "software-gt-awake-time", "ns"),	1004	__event(4, "software-gt-awake-time", "ns"),
903	};	1005	};
904	static const struct {	1006	static const struct {
905	enum drm_i915_pmu_engine_sample sample;	1007	enum drm_i915_pmu_engine_sample sample;
@@ -914,12 +1016,17 @@ create_event_attributes(struct i915_pmu *pmu) · 8 unmodified lines
914	struct i915_ext_attribute i915_attr = NULL, i915_iter;	1016	struct i915_ext_attribute i915_attr = NULL, i915_iter;
915	struct attribute attr = NULL, attr_iter;	1017	struct attribute attr = NULL, attr_iter;
916	struct intel_engine_cs *engine;	1018	struct intel_engine_cs *engine;
917	unsigned int i;	1019	struct intel_gt *gt;
		1020	unsigned int i, j;
918		1021
919	/* Count how many counters we will be exposing. */	1022	/* Count how many counters we will be exposing. */
920	for (i = 0; i < ARRAY_SIZE(events); i++) {	1023	for_each_gt(gt, i915, j) {
921	if (!config_status(i915, events[i].config))	1024	for (i = 0; i < ARRAY_SIZE(events); i++) {
922	count++;	1025	u64 config = ___I915_PMU_OTHER(j, events[i].counter);
		1026
		1027	if (!config_status(i915, config))
		1028	count++;
		1029	}
923	}	1030	}
924		1031
925	for_each_uabi_engine(engine, i915) {	1032	for_each_uabi_engine(engine, i915) {
@@ -949,26 +1056,39 @@ create_event_attributes(struct i915_pmu *pmu) · 23 unmodified lines
949	attr_iter = attr;	1056	attr_iter = attr;
950		1057
951	/* Initialize supported non-engine counters. */	1058	/* Initialize supported non-engine counters. */
952	for (i = 0; i < ARRAY_SIZE(events); i++) {	1059	for_each_gt(gt, i915, j) {
953	char *str;	1060	for (i = 0; i < ARRAY_SIZE(events); i++) {
954		1061	u64 config = ___I915_PMU_OTHER(j, events[i].counter);
955	if (config_status(i915, events[i].config))	1062	char *str;
956	continue;
957
958	str = kstrdup(events[i].name, GFP_KERNEL);
959	if (!str)
960	goto err;
961		1063
962	*attr_iter++ = &i915_iter->attr.attr;	1064	if (config_status(i915, config))
963	i915_iter = add_i915_attr(i915_iter, str, events[i].config);	1065	continue;
964		1066
965	if (events[i].unit) {	1067	if (events[i].global \|\| !HAS_EXTRA_GT_LIST(i915))
966	str = kasprintf(GFP_KERNEL, "%s.unit", events[i].name);	1068	str = kstrdup(events[i].name, GFP_KERNEL);
		1069	else
		1070	str = kasprintf(GFP_KERNEL, "%s-gt%u",
		1071	events[i].name, j);
967	if (!str)	1072	if (!str)
968	goto err;	1073	goto err;
969		1074
970	*attr_iter++ = &pmu_iter->attr.attr;	1075	*attr_iter++ = &i915_iter->attr.attr;
971	pmu_iter = add_pmu_attr(pmu_iter, str, events[i].unit);	1076	i915_iter = add_i915_attr(i915_iter, str, config);
		1077
		1078	if (events[i].unit) {
		1079	if (events[i].global \|\| !HAS_EXTRA_GT_LIST(i915))
		1080	str = kasprintf(GFP_KERNEL, "%s.unit",
		1081	events[i].name);
		1082	else
		1083	str = kasprintf(GFP_KERNEL, "%s-gt%u.unit",
		1084	events[i].name, j);
		1085	if (!str)
		1086	goto err;
		1087
		1088	*attr_iter++ = &pmu_iter->attr.attr;
		1089	pmu_iter = add_pmu_attr(pmu_iter, str,
		1090	events[i].unit);
		1091	}
972	}	1092	}
973	}	1093	}
974		1094

drivers/gpu/drm/i915/i915_pmu.h+18−10

 #include <uapi/drm/i915_drm.h>
 struct drm_i915_private;
+struct intel_gt;
-/**
+/*
  * Non-engine events that we need to track enabled-disabled transition and
  * current state.
  */
 	__I915_PMU_TRACKED_EVENT_COUNT, /* count marker */
 };
-/**
+/*
  * Slots used from the sampling timer (non-engine events) with some extras for
  * convenience.
  */
 	__I915_NUM_PMU_SAMPLERS
 };
-/**
+#define I915_PMU_MAX_GTS 2
+/*
  * How many different events we track in the global PMU mask.
  *
  * It is also used to know to needed number of event reference counters.
  */
 #define I915_PMU_MASK_BITS \
-	(I915_ENGINE_SAMPLE_COUNT + __I915_PMU_TRACKED_EVENT_COUNT)
+	(I915_ENGINE_SAMPLE_COUNT + \
+	 I915_PMU_MAX_GTS * __I915_PMU_TRACKED_EVENT_COUNT)
 #define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
 	 * @lock: Lock protecting enable mask and ref count handling.
 	 */
 	spinlock_t lock;
+	/**
+	 * @unparked: GT unparked mask.
+	 */
+	unsigned int unparked;
 	/**
 	 * @timer: Timer for internal i915 PMU sampling.
 	 */
 	 * Only global counters are held here, while the per-engine ones are in
 	 * struct intel_engine_cs.
 	 */
-	struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
+	struct i915_pmu_sample sample[I915_PMU_MAX_GTS * __I915_NUM_PMU_SAMPLERS];
 	/**
 	 * @sleep_last: Last time GT parked for RC6 estimation.
 	 */
-	ktime_t sleep_last;
+	ktime_t sleep_last[I915_PMU_MAX_GTS];
 	/**
 	 * @irq_count: Number of interrupts
 	 *
 void i915_pmu_exit(void);
 void i915_pmu_register(struct drm_i915_private *i915);
 void i915_pmu_unregister(struct drm_i915_private *i915);
-void i915_pmu_gt_parked(struct drm_i915_private *i915);
+void i915_pmu_gt_parked(struct intel_gt *gt);
-void i915_pmu_gt_unparked(struct drm_i915_private *i915);
+void i915_pmu_gt_unparked(struct intel_gt *gt);
 #else
 static inline int i915_pmu_init(void) { return 0; }
 static inline void i915_pmu_exit(void) {}
 static inline void i915_pmu_register(struct drm_i915_private *i915) {}
 static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
-static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
+static inline void i915_pmu_gt_parked(struct intel_gt *gt) {}
-static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
+static inline void i915_pmu_gt_unparked(struct intel_gt *gt) {}
 #endif
 #endif

drivers/gpu/drm/i915/i915_request.h+26−26

@@ -172,7 +172,7 @@ enum { · 171 unmodified lines
172	I915_FENCE_FLAG_COMPOSITE,	172	I915_FENCE_FLAG_COMPOSITE,
173	};	173	};
174		174
175	/**	175	/*
176	* Request queue structure.	176	* Request queue structure.
177	*	177	*
178	* The request queue allows us to note sequence numbers that have been emitted	178	* The request queue allows us to note sequence numbers that have been emitted
@@ -198,7 +198,7 @@ struct i915_request { · 19 unmodified lines
198		198
199	struct drm_i915_private *i915;	199	struct drm_i915_private *i915;
200		200
201	/**	201	/*
202	* Context and ring buffer related to this request	202	* Context and ring buffer related to this request
203	* Contexts are refcounted, so when this request is associated with a	203	* Contexts are refcounted, so when this request is associated with a
204	* context, we must increment the context's refcount, to guarantee that	204	* context, we must increment the context's refcount, to guarantee that
@@ -251,9 +251,9 @@ struct i915_request { · 46 unmodified lines
251	};	251	};
252	struct llist_head execute_cb;	252	struct llist_head execute_cb;
253	struct i915_sw_fence semaphore;	253	struct i915_sw_fence semaphore;
254	/**	254	/*
255	* @submit_work: complete submit fence from an IRQ if needed for	255	* complete submit fence from an IRQ if needed for locking hierarchy
256	* locking hierarchy reasons.	256	* reasons.
257	*/	257	*/
258	struct irq_work submit_work;	258	struct irq_work submit_work;
259		259
@@ -277,35 +277,35 @@ struct i915_request { · 17 unmodified lines
277	*/	277	*/
278	const u32 *hwsp_seqno;	278	const u32 *hwsp_seqno;
279		279
280	/** Position in the ring of the start of the request */	280	/* Position in the ring of the start of the request */
281	u32 head;	281	u32 head;
282		282
283	/** Position in the ring of the start of the user packets */	283	/* Position in the ring of the start of the user packets */
284	u32 infix;	284	u32 infix;
285		285
286	/**	286	/*
287	* Position in the ring of the start of the postfix.	287	* Position in the ring of the start of the postfix.
288	* This is required to calculate the maximum available ring space	288	* This is required to calculate the maximum available ring space
289	* without overwriting the postfix.	289	* without overwriting the postfix.
290	*/	290	*/
291	u32 postfix;	291	u32 postfix;
292		292
293	/** Position in the ring of the end of the whole request */	293	/* Position in the ring of the end of the whole request */
294	u32 tail;	294	u32 tail;
295		295
296	/** Position in the ring of the end of any workarounds after the tail */	296	/* Position in the ring of the end of any workarounds after the tail */
297	u32 wa_tail;	297	u32 wa_tail;
298		298
299	/** Preallocate space in the ring for the emitting the request */	299	/* Preallocate space in the ring for the emitting the request */
300	u32 reserved_space;	300	u32 reserved_space;
301		301
302	/** Batch buffer pointer for selftest internal use. */	302	/* Batch buffer pointer for selftest internal use. */
303	I915_SELFTEST_DECLARE(struct i915_vma *batch);	303	I915_SELFTEST_DECLARE(struct i915_vma *batch);
304		304
305	struct i915_vma_resource *batch_res;	305	struct i915_vma_resource *batch_res;
306		306
307	#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)	307	#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
308	/**	308	/*
309	* Additional buffers requested by userspace to be captured upon	309	* Additional buffers requested by userspace to be captured upon
310	* a GPU hang. The vma/obj on this list are protected by their	310	* a GPU hang. The vma/obj on this list are protected by their
311	* active reference - all objects on this list must also be	311	* active reference - all objects on this list must also be
@@ -314,29 +314,29 @@ struct i915_request { · 2 unmodified lines
314	struct i915_capture_list *capture_list;	314	struct i915_capture_list *capture_list;
315	#endif	315	#endif
316		316
317	/** Time at which this request was emitted, in jiffies. */	317	/* Time at which this request was emitted, in jiffies. */
318	unsigned long emitted_jiffies;	318	unsigned long emitted_jiffies;
319		319
320	/** timeline->request entry for this request */	320	/* timeline->request entry for this request */
321	struct list_head link;	321	struct list_head link;
322		322
323	/** Watchdog support fields. */	323	/* Watchdog support fields. */
324	struct i915_request_watchdog {	324	struct i915_request_watchdog {
325	struct llist_node link;	325	struct llist_node link;
326	struct hrtimer timer;	326	struct hrtimer timer;
327	} watchdog;	327	} watchdog;
328		328
329	/**	329	/*
330	* @guc_fence_link: Requests may need to be stalled when using GuC	330	* Requests may need to be stalled when using GuC submission waiting for
331	* submission waiting for certain GuC operations to complete. If that is	331	* certain GuC operations to complete. If that is the case, stalled
332	* the case, stalled requests are added to a per context list of stalled	332	* requests are added to a per context list of stalled requests. The
333	* requests. The below list_head is the link in that list. Protected by	333	* below list_head is the link in that list. Protected by
334	* ce->guc_state.lock.	334	* ce->guc_state.lock.
335	*/	335	*/
336	struct list_head guc_fence_link;	336	struct list_head guc_fence_link;
337		337
338	/**	338	/*
339	* @guc_prio: Priority level while the request is in flight. Differs	339	* Priority level while the request is in flight. Differs
340	* from i915 scheduler priority. See comment above	340	* from i915 scheduler priority. See comment above
341	* I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP for details. Protected by	341	* I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP for details. Protected by
342	* ce->guc_active.lock. Two special values (GUC_PRIO_INIT and	342	* ce->guc_active.lock. Two special values (GUC_PRIO_INIT and
@@ -348,8 +348,8 @@ struct i915_request { · 5 unmodified lines
348	#define GUC_PRIO_FINI 0xfe	348	#define GUC_PRIO_FINI 0xfe
349	u8 guc_prio;	349	u8 guc_prio;
350		350
351	/**	351	/*
352	* @hucq: wait queue entry used to wait on the HuC load to complete	352	* wait queue entry used to wait on the HuC load to complete
353	*/	353	*/
354	wait_queue_entry_t hucq;	354	wait_queue_entry_t hucq;
355		355
@@ -473,7 +473,7 @@ i915_request_has_initial_breadcrumb(const struct i915_request *rq) · 117 unmodified lines
473	return test_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags);	473	return test_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags);
474	}	474	}
475		475
476	/**	476	/*
477	* Returns true if seq1 is later than seq2.	477	* Returns true if seq1 is later than seq2.
478	*/	478	*/
479	static inline bool i915_seqno_passed(u32 seq1, u32 seq2)	479	static inline bool i915_seqno_passed(u32 seq1, u32 seq2)

drivers/gpu/drm/i915/i915_scatterlist.h+4−5

  */
 struct i915_refct_sgt_ops {
 	/**
-	 * release() - Free the memory of the struct i915_refct_sgt
+	 * @release: Free the memory of the struct i915_refct_sgt
-	 * @ref: struct kref that is embedded in the struct i915_refct_sgt
 	 */
 	void (*release)(struct kref *ref);
 };
 /**
  * i915_refct_sgt_put - Put a refcounted sg-table
- * @rsgt the struct i915_refct_sgt to put.
+ * @rsgt: the struct i915_refct_sgt to put.
  */
 static inline void i915_refct_sgt_put(struct i915_refct_sgt *rsgt)
 {
 /**
  * i915_refct_sgt_get - Get a refcounted sg-table
- * @rsgt the struct i915_refct_sgt to get.
+ * @rsgt: the struct i915_refct_sgt to get.
  */
 static inline struct i915_refct_sgt *
 i915_refct_sgt_get(struct i915_refct_sgt *rsgt)
 /**
  * __i915_refct_sgt_init - Initialize a refcounted sg-list with a custom
  * operations structure
- * @rsgt The struct i915_refct_sgt to initialize.
+ * @rsgt: The struct i915_refct_sgt to initialize.
  * @size: Size in bytes of the underlying memory buffer.
  * @ops: A customized operations structure in case the refcounted sg-list
  * is embedded into another structure.

drivers/gpu/drm/i915/i915_utils.h+1−1

@@ -250,7 +250,7 @@ wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) · 249 unmodified lines
250	}	250	}
251	}	251	}
252		252
253	/**	253	/*
254	* __wait_for - magic wait macro	254	* __wait_for - magic wait macro
255	*	255	*
256	* Macro to help avoid open coding check/wait/timeout patterns. Note that it's	256	* Macro to help avoid open coding check/wait/timeout patterns. Note that it's

drivers/gpu/drm/i915/i915_vma.c+8−8

@@ -315,7 +315,7 @@ struct i915_vma_work { · 314 unmodified lines
315	struct i915_vma_resource *vma_res;	315	struct i915_vma_resource *vma_res;
316	struct drm_i915_gem_object *obj;	316	struct drm_i915_gem_object *obj;
317	struct i915_sw_dma_fence_cb cb;	317	struct i915_sw_dma_fence_cb cb;
318	enum i915_cache_level cache_level;	318	unsigned int pat_index;
319	unsigned int flags;	319	unsigned int flags;
320	};	320	};
321		321
@@ -334,7 +334,7 @@ static void __vma_bind(struct dma_fence_work *work) · 12 unmodified lines
334	return;	334	return;
335		335
336	vma_res->ops->bind_vma(vma_res->vm, &vw->stash,	336	vma_res->ops->bind_vma(vma_res->vm, &vw->stash,
337	vma_res, vw->cache_level, vw->flags);	337	vma_res, vw->pat_index, vw->flags);
338	}	338	}
339		339
340	static void __vma_release(struct dma_fence_work *work)	340	static void __vma_release(struct dma_fence_work *work)
@@ -426,7 +426,7 @@ i915_vma_resource_init_from_vma(struct i915_vma_resource *vma_res, · 85 unmodified lines
426	/**	426	/**
427	* i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.	427	* i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
428	* @vma: VMA to map	428	* @vma: VMA to map
429	* @cache_level: mapping cache level	429	* @pat_index: PAT index to set in PTE
430	* @flags: flags like global or local mapping	430	* @flags: flags like global or local mapping
431	* @work: preallocated worker for allocating and binding the PTE	431	* @work: preallocated worker for allocating and binding the PTE
432	* @vma_res: pointer to a preallocated vma resource. The resource is either	432	* @vma_res: pointer to a preallocated vma resource. The resource is either
@@ -437,7 +437,7 @@ i915_vma_resource_init_from_vma(struct i915_vma_resource *vma_res, · 4 unmodified lines
437	* Note that DMA addresses are also the only part of the SG table we care about.	437	* Note that DMA addresses are also the only part of the SG table we care about.
438	*/	438	*/
439	int i915_vma_bind(struct i915_vma *vma,	439	int i915_vma_bind(struct i915_vma *vma,
440	enum i915_cache_level cache_level,	440	unsigned int pat_index,
441	u32 flags,	441	u32 flags,
442	struct i915_vma_work *work,	442	struct i915_vma_work *work,
443	struct i915_vma_resource *vma_res)	443	struct i915_vma_resource *vma_res)
@@ -507,7 +507,7 @@ int i915_vma_bind(struct i915_vma *vma, · 63 unmodified lines
507	struct dma_fence *prev;	507	struct dma_fence *prev;
508		508
509	work->vma_res = i915_vma_resource_get(vma->resource);	509	work->vma_res = i915_vma_resource_get(vma->resource);
510	work->cache_level = cache_level;	510	work->pat_index = pat_index;
511	work->flags = bind_flags;	511	work->flags = bind_flags;
512		512
513	/*	513	/*
@@ -537,7 +537,7 @@ int i915_vma_bind(struct i915_vma *vma, · 23 unmodified lines
537		537
538	return ret;	538	return ret;
539	}	539	}
540	vma->ops->bind_vma(vma->vm, NULL, vma->resource, cache_level,	540	vma->ops->bind_vma(vma->vm, NULL, vma->resource, pat_index,
541	bind_flags);	541	bind_flags);
542	}	542	}
543		543
@@ -814,7 +814,7 @@ i915_vma_insert(struct i915_vma vma, struct i915_gem_ww_ctx ww, · 270 unmodified lines
814	color = 0;	814	color = 0;
815		815
816	if (i915_vm_has_cache_coloring(vma->vm))	816	if (i915_vm_has_cache_coloring(vma->vm))
817	color = vma->obj->cache_level;	817	color = vma->obj->pat_index;
818		818
819	if (flags & PIN_OFFSET_FIXED) {	819	if (flags & PIN_OFFSET_FIXED) {
820	u64 offset = flags & PIN_OFFSET_MASK;	820	u64 offset = flags & PIN_OFFSET_MASK;
@@ -1518,7 +1518,7 @@ int i915_vma_pin_ww(struct i915_vma vma, struct i915_gem_ww_ctx ww, · 697 unmodified lines
1518		1518
1519	GEM_BUG_ON(!vma->pages);	1519	GEM_BUG_ON(!vma->pages);
1520	err = i915_vma_bind(vma,	1520	err = i915_vma_bind(vma,
1521	vma->obj->cache_level,	1521	vma->obj->pat_index,
1522	flags, work, vma_res);	1522	flags, work, vma_res);
1523	vma_res = NULL;	1523	vma_res = NULL;
1524	if (err)	1524	if (err)

drivers/gpu/drm/i915/i915_vma.h+2−2

@@ -132,7 +132,7 @@ static inline u64 __i915_vma_size(const struct i915_vma *vma) · 131 unmodified lines
132	}	132	}
133		133
134	/**	134	/**
135	* i915_vma_offset - Obtain the va range size of the vma	135	* i915_vma_size - Obtain the va range size of the vma
136	* @vma: The vma	136	* @vma: The vma
137	*	137	*
138	* GPU virtual address space may be allocated with padding. This	138	* GPU virtual address space may be allocated with padding. This
@@ -250,7 +250,7 @@ i915_vma_compare(struct i915_vma *vma, · 111 unmodified lines
250		250
251	struct i915_vma_work *i915_vma_work(void);	251	struct i915_vma_work *i915_vma_work(void);
252	int i915_vma_bind(struct i915_vma *vma,	252	int i915_vma_bind(struct i915_vma *vma,
253	enum i915_cache_level cache_level,	253	unsigned int pat_index,
254	u32 flags,	254	u32 flags,
255	struct i915_vma_work *work,	255	struct i915_vma_work *work,
256	struct i915_vma_resource *vma_res);	256	struct i915_vma_resource *vma_res);

drivers/gpu/drm/i915/i915_vma_resource.h+28−18

 	unsigned int sg;
 };
+/**
+ * struct i915_vma_bindinfo - Information needed for async bind
+ * only but that can be dropped after the bind has taken place.
+ * Consider making this a separate argument to the bind_vma
+ * op, coalescing with other arguments like vm, stash, cache_level
+ * and flags
+ * @pages: The pages sg-table.
+ * @page_sizes: Page sizes of the pages.
+ * @pages_rsgt: Refcounted sg-table when delayed object destruction
+ * is supported. May be NULL.
+ * @readonly: Whether the vma should be bound read-only.
+ * @lmem: Whether the vma points to lmem.
+ */
+struct i915_vma_bindinfo {
+	struct sg_table *pages;
+	struct i915_page_sizes page_sizes;
+	struct i915_refct_sgt *pages_rsgt;
+	bool readonly:1;
+	bool lmem:1;
+};
 /**
  * struct i915_vma_resource - Snapshotted unbind information.
  * @unbind_fence: Fence to mark unbinding complete. Note that this fence
  * @chain: Pointer to struct i915_sw_fence used to await dependencies.
  * @rb: Rb node for the vm's pending unbind interval tree.
  * @__subtree_last: Interval tree private member.
+ * @wakeref: wakeref.
  * @vm: non-refcounted pointer to the vm. This is for internal use only and
  * this member is cleared after vm_resource unbind.
  * @mr: The memory region of the object pointed to by the vma.
 	intel_wakeref_t wakeref;
 	/**
-	 * struct i915_vma_bindinfo - Information needed for async bind
+	 * @bi: Information needed for async bind only but that can be dropped
-	 * only but that can be dropped after the bind has taken place.
+	 * after the bind has taken place.
-	 * Consider making this a separate argument to the bind_vma
+	 *
-	 * op, coalescing with other arguments like vm, stash, cache_level
+	 * Consider making this a separate argument to the bind_vma op,
-	 * and flags
+	 * coalescing with other arguments like vm, stash, cache_level and flags
-	 * @pages: The pages sg-table.
-	 * @page_sizes: Page sizes of the pages.
-	 * @pages_rsgt: Refcounted sg-table when delayed object destruction
-	 * is supported. May be NULL.
-	 * @readonly: Whether the vma should be bound read-only.
-	 * @lmem: Whether the vma points to lmem.
 	 */
-	struct i915_vma_bindinfo {
+	struct i915_vma_bindinfo bi;
-		struct sg_table *pages;
-		struct i915_page_sizes page_sizes;
-		struct i915_refct_sgt *pages_rsgt;
-		bool readonly:1;
-		bool lmem:1;
-	} bi;
 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 	struct intel_memory_region *mr;

drivers/gpu/drm/i915/i915_vma_types.h+0−2

@@ -32,8 +32,6 @@ · 31 unmodified lines
32		32
33	#include "gem/i915_gem_object_types.h"	33	#include "gem/i915_gem_object_types.h"
34		34
35	enum i915_cache_level;
36
37	/**	35	/**
38	* DOC: Global GTT views	36	* DOC: Global GTT views
39	*	37	*

drivers/gpu/drm/i915/intel_device_info.h+5−0

 #include "gt/intel_context_types.h"
 #include "gt/intel_sseu.h"
+#include "gem/i915_gem_object_types.h"
 struct drm_printer;
 struct drm_i915_private;
 struct intel_gt_definition;
 	 * Initial runtime info. Do not access outside of i915_driver_create().
 	 */
 	const struct intel_runtime_info __runtime;
+	u32 cachelevel_to_pat[I915_MAX_CACHE_LEVEL];
+	u32 max_pat_index;
 };
 struct intel_driver_caps {

drivers/gpu/drm/i915/pxp/intel_pxp.c+78−24

@@ -12,7 +12,9 @@ · 11 unmodified lines
12	#include "i915_drv.h"	12	#include "i915_drv.h"
13		13
14	#include "intel_pxp.h"	14	#include "intel_pxp.h"
		15	#include "intel_pxp_gsccs.h"
15	#include "intel_pxp_irq.h"	16	#include "intel_pxp_irq.h"
		17	#include "intel_pxp_regs.h"
16	#include "intel_pxp_session.h"	18	#include "intel_pxp_session.h"
17	#include "intel_pxp_tee.h"	19	#include "intel_pxp_tee.h"
18	#include "intel_pxp_types.h"	20	#include "intel_pxp_types.h"
@@ -60,21 +62,22 @@ bool intel_pxp_is_active(const struct intel_pxp *pxp) · 41 unmodified lines
60	return IS_ENABLED(CONFIG_DRM_I915_PXP) && pxp && pxp->arb_is_valid;	62	return IS_ENABLED(CONFIG_DRM_I915_PXP) && pxp && pxp->arb_is_valid;
61	}	63	}
62		64
63	/* KCR register definitions */	65	static void kcr_pxp_set_status(const struct intel_pxp *pxp, bool enable)
64	#define KCR_INIT _MMIO(0x320f0)	66	{
65	/* Setting KCR Init bit is required after system boot */	67	u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :
66	#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)	68	_MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
		69
		70	intel_uncore_write(pxp->ctrl_gt->uncore, KCR_INIT(pxp->kcr_base), val);
		71	}
67		72
68	static void kcr_pxp_enable(struct intel_gt *gt)	73	static void kcr_pxp_enable(const struct intel_pxp *pxp)
69	{	74	{
70	intel_uncore_write(gt->uncore, KCR_INIT,	75	kcr_pxp_set_status(pxp, true);
71	_MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
72	}	76	}
73		77
74	static void kcr_pxp_disable(struct intel_gt *gt)	78	static void kcr_pxp_disable(const struct intel_pxp *pxp)
75	{	79	{
76	intel_uncore_write(gt->uncore, KCR_INIT,	80	kcr_pxp_set_status(pxp, false);
77	_MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
78	}	81	}
79		82
80	static int create_vcs_context(struct intel_pxp *pxp)	83	static int create_vcs_context(struct intel_pxp *pxp)
@@ -126,13 +129,21 @@ static void pxp_init_full(struct intel_pxp *pxp) · 45 unmodified lines
126	init_completion(&pxp->termination);	129	init_completion(&pxp->termination);
127	complete_all(&pxp->termination);	130	complete_all(&pxp->termination);
128		131
		132	if (pxp->ctrl_gt->type == GT_MEDIA)
		133	pxp->kcr_base = MTL_KCR_BASE;
		134	else
		135	pxp->kcr_base = GEN12_KCR_BASE;
		136
129	intel_pxp_session_management_init(pxp);	137	intel_pxp_session_management_init(pxp);
130		138
131	ret = create_vcs_context(pxp);	139	ret = create_vcs_context(pxp);
132	if (ret)	140	if (ret)
133	return;	141	return;
134		142
135	ret = intel_pxp_tee_component_init(pxp);	143	if (HAS_ENGINE(pxp->ctrl_gt, GSC0))
		144	ret = intel_pxp_gsccs_init(pxp);
		145	else
		146	ret = intel_pxp_tee_component_init(pxp);
136	if (ret)	147	if (ret)
137	goto out_context;	148	goto out_context;
138		149
@@ -165,9 +176,12 @@ static struct intel_gt *find_gt_for_required_protected_content(struct drm_i915_p · 26 unmodified lines
165	/*	176	/*
166	* For MTL onwards, PXP-controller-GT needs to have a valid GSC engine	177	* For MTL onwards, PXP-controller-GT needs to have a valid GSC engine
167	* on the media GT. NOTE: if we have a media-tile with a GSC-engine,	178	* on the media GT. NOTE: if we have a media-tile with a GSC-engine,
168	* the VDBOX is already present so skip that check	179	* the VDBOX is already present so skip that check. We also have to
		180	* ensure the GSC and HUC firmware are coming online
169	*/	181	*/
170	if (i915->media_gt && HAS_ENGINE(i915->media_gt, GSC0))	182	if (i915->media_gt && HAS_ENGINE(i915->media_gt, GSC0) &&
		183	intel_uc_fw_is_loadable(&i915->media_gt->uc.gsc.fw) &&
		184	intel_uc_fw_is_loadable(&i915->media_gt->uc.huc.fw))
171	return i915->media_gt;	185	return i915->media_gt;
172		186
173	/*	187	/*
@@ -207,7 +221,9 @@ int intel_pxp_init(struct drm_i915_private *i915) · 33 unmodified lines
207	if (!i915->pxp)	221	if (!i915->pxp)
208	return -ENOMEM;	222	return -ENOMEM;
209		223
		224	/* init common info used by all feature-mode usages*/
210	i915->pxp->ctrl_gt = gt;	225	i915->pxp->ctrl_gt = gt;
		226	mutex_init(&i915->pxp->tee_mutex);
211		227
212	/*	228	/*
213	* If full PXP feature is not available but HuC is loaded by GSC on pre-MTL	229	* If full PXP feature is not available but HuC is loaded by GSC on pre-MTL
@@ -229,7 +245,10 @@ void intel_pxp_fini(struct drm_i915_private *i915) · 15 unmodified lines
229		245
230	i915->pxp->arb_is_valid = false;	246	i915->pxp->arb_is_valid = false;
231		247
232	intel_pxp_tee_component_fini(i915->pxp);	248	if (HAS_ENGINE(i915->pxp->ctrl_gt, GSC0))
		249	intel_pxp_gsccs_fini(i915->pxp);
		250	else
		251	intel_pxp_tee_component_fini(i915->pxp);
233		252
234	destroy_vcs_context(i915->pxp);	253	destroy_vcs_context(i915->pxp);
235		254
@@ -270,8 +289,18 @@ static bool pxp_component_bound(struct intel_pxp *pxp) · 34 unmodified lines
270	return bound;	289	return bound;
271	}	290	}
272		291
		292	int intel_pxp_get_backend_timeout_ms(struct intel_pxp *pxp)
		293	{
		294	if (HAS_ENGINE(pxp->ctrl_gt, GSC0))
		295	return GSCFW_MAX_ROUND_TRIP_LATENCY_MS;
		296	else
		297	return 250;
		298	}
		299
273	static int __pxp_global_teardown_final(struct intel_pxp *pxp)	300	static int __pxp_global_teardown_final(struct intel_pxp *pxp)
274	{	301	{
		302	int timeout;
		303
275	if (!pxp->arb_is_valid)	304	if (!pxp->arb_is_valid)
276	return 0;	305	return 0;
277	/*	306	/*
@@ -281,7 +310,9 @@ static int __pxp_global_teardown_final(struct intel_pxp *pxp) · 3 unmodified lines
281	intel_pxp_mark_termination_in_progress(pxp);	310	intel_pxp_mark_termination_in_progress(pxp);
282	intel_pxp_terminate(pxp, false);	311	intel_pxp_terminate(pxp, false);
283		312
284	if (!wait_for_completion_timeout(&pxp->termination, msecs_to_jiffies(250)))	313	timeout = intel_pxp_get_backend_timeout_ms(pxp);
		314
		315	if (!wait_for_completion_timeout(&pxp->termination, msecs_to_jiffies(timeout)))
285	return -ETIMEDOUT;	316	return -ETIMEDOUT;
286		317
287	return 0;	318	return 0;
@@ -289,6 +320,8 @@ static int __pxp_global_teardown_final(struct intel_pxp *pxp) · 1 unmodified line
289		320
290	static int __pxp_global_teardown_restart(struct intel_pxp *pxp)	321	static int __pxp_global_teardown_restart(struct intel_pxp *pxp)
291	{	322	{
		323	int timeout;
		324
292	if (pxp->arb_is_valid)	325	if (pxp->arb_is_valid)
293	return 0;	326	return 0;
294	/*	327	/*
@@ -297,7 +330,9 @@ static int __pxp_global_teardown_restart(struct intel_pxp *pxp) · 2 unmodified lines
297	*/	330	*/
298	pxp_queue_termination(pxp);	331	pxp_queue_termination(pxp);
299		332
300	if (!wait_for_completion_timeout(&pxp->termination, msecs_to_jiffies(250)))	333	timeout = intel_pxp_get_backend_timeout_ms(pxp);
		334
		335	if (!wait_for_completion_timeout(&pxp->termination, msecs_to_jiffies(timeout)))
301	return -ETIMEDOUT;	336	return -ETIMEDOUT;
302		337
303	return 0;	338	return 0;
@@ -324,6 +359,26 @@ void intel_pxp_end(struct intel_pxp *pxp) · 20 unmodified lines
324	intel_runtime_pm_put(&i915->runtime_pm, wakeref);	359	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
325	}	360	}
326		361
		362	/*
		363	* this helper is used by both intel_pxp_start and by
		364	* the GET_PARAM IOCTL that user space calls. Thus, the
		365	* return values here should match the UAPI spec.
		366	*/
		367	int intel_pxp_get_readiness_status(struct intel_pxp *pxp)
		368	{
		369	if (!intel_pxp_is_enabled(pxp))
		370	return -ENODEV;
		371
		372	if (HAS_ENGINE(pxp->ctrl_gt, GSC0)) {
		373	if (wait_for(intel_pxp_gsccs_is_ready_for_sessions(pxp), 250))
		374	return 2;
		375	} else {
		376	if (wait_for(pxp_component_bound(pxp), 250))
		377	return 2;
		378	}
		379	return 1;
		380	}
		381
327	/*	382	/*
328	* the arb session is restarted from the irq work when we receive the	383	* the arb session is restarted from the irq work when we receive the
329	* termination completion interrupt	384	* termination completion interrupt
@@ -332,11 +387,11 @@ int intel_pxp_start(struct intel_pxp *pxp) · 2 unmodified lines
332	{	387	{
333	int ret = 0;	388	int ret = 0;
334		389
335	if (!intel_pxp_is_enabled(pxp))	390	ret = intel_pxp_get_readiness_status(pxp);
336	return -ENODEV;	391	if (ret < 0)
337		392	return ret;
338	if (wait_for(pxp_component_bound(pxp), 250))	393	else if (ret > 1)
339	return -ENXIO;	394	return -EIO; /* per UAPI spec, user may retry later */
340		395
341	mutex_lock(&pxp->arb_mutex);	396	mutex_lock(&pxp->arb_mutex);
342		397
@@ -357,14 +412,13 @@ unlock: · 14 unmodified lines
357		412
358	void intel_pxp_init_hw(struct intel_pxp *pxp)	413	void intel_pxp_init_hw(struct intel_pxp *pxp)
359	{	414	{
360	kcr_pxp_enable(pxp->ctrl_gt);	415	kcr_pxp_enable(pxp);
361	intel_pxp_irq_enable(pxp);	416	intel_pxp_irq_enable(pxp);
362	}	417	}
363		418
364	void intel_pxp_fini_hw(struct intel_pxp *pxp)	419	void intel_pxp_fini_hw(struct intel_pxp *pxp)
365	{	420	{
366	kcr_pxp_disable(pxp->ctrl_gt);	421	kcr_pxp_disable(pxp);
367
368	intel_pxp_irq_disable(pxp);	422	intel_pxp_irq_disable(pxp);
369	}	423	}
370		424

drivers/gpu/drm/i915/pxp/intel_pxp.h+2−0

@@ -26,6 +26,8 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp); · 25 unmodified lines
26	void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);	26	void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
27	void intel_pxp_tee_end_arb_fw_session(struct intel_pxp *pxp, u32 arb_session_id);	27	void intel_pxp_tee_end_arb_fw_session(struct intel_pxp *pxp, u32 arb_session_id);
28		28
		29	int intel_pxp_get_readiness_status(struct intel_pxp *pxp);
		30	int intel_pxp_get_backend_timeout_ms(struct intel_pxp *pxp);
29	int intel_pxp_start(struct intel_pxp *pxp);	31	int intel_pxp_start(struct intel_pxp *pxp);
30	void intel_pxp_end(struct intel_pxp *pxp);	32	void intel_pxp_end(struct intel_pxp *pxp);
31		33

drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h+24−0

@@ -11,6 +11,10 @@ · 10 unmodified lines
11		11
12	/* PXP-Cmd-Op definitions */	12	/* PXP-Cmd-Op definitions */
13	#define PXP43_CMDID_START_HUC_AUTH 0x0000003A	13	#define PXP43_CMDID_START_HUC_AUTH 0x0000003A
		14	#define PXP43_CMDID_INIT_SESSION 0x00000036
		15
		16	/* PXP-Packet sizes for MTL's GSCCS-HECI instruction */
		17	#define PXP43_MAX_HECI_INOUT_SIZE (SZ_32K)
14		18
15	/* PXP-Input-Packet: HUC-Authentication */	19	/* PXP-Input-Packet: HUC-Authentication */
16	struct pxp43_start_huc_auth_in {	20	struct pxp43_start_huc_auth_in {
@@ -23,4 +27,24 @@ struct pxp43_start_huc_auth_out { · 6 unmodified lines
23	struct pxp_cmd_header header;	27	struct pxp_cmd_header header;
24	} __packed;	28	} __packed;
25		29
		30	/* PXP-Input-Packet: Init PXP session */
		31	struct pxp43_create_arb_in {
		32	struct pxp_cmd_header header;
		33	/* header.stream_id fields for vesion 4.3 of Init PXP session: */
		34	#define PXP43_INIT_SESSION_VALID BIT(0)
		35	#define PXP43_INIT_SESSION_APPTYPE BIT(1)
		36	#define PXP43_INIT_SESSION_APPID GENMASK(17, 2)
		37	u32 protection_mode;
		38	#define PXP43_INIT_SESSION_PROTECTION_ARB 0x2
		39	u32 sub_session_id;
		40	u32 init_flags;
		41	u32 rsvd[12];
		42	} __packed;
		43
		44	/* PXP-Input-Packet: Init PXP session */
		45	struct pxp43_create_arb_out {
		46	struct pxp_cmd_header header;
		47	u32 rsvd[8];
		48	} __packed;
		49
26	#endif /* __INTEL_PXP_FW_INTERFACE_43_H__ */	50	#endif /* __INTEL_PXP_FW_INTERFACE_43_H__ */

drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c+5−1

 #include "intel_pxp.h"
 #include "intel_pxp_debugfs.h"
+#include "intel_pxp_gsccs.h"
 #include "intel_pxp_irq.h"
 #include "intel_pxp_types.h"
 {
 	struct intel_pxp *pxp = data;
 	struct intel_gt *gt = pxp->ctrl_gt;
+	int timeout_ms;
 	if (!intel_pxp_is_active(pxp))
 		return -ENODEV;
 	intel_pxp_irq_handler(pxp, GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT);
 	spin_unlock_irq(gt->irq_lock);
+	timeout_ms = intel_pxp_get_backend_timeout_ms(pxp);
 	if (!wait_for_completion_timeout(&pxp->termination,
-					 msecs_to_jiffies(100)))
+					 msecs_to_jiffies(timeout_ms)))
 		return -ETIMEDOUT;
 	return 0;

drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c+444−0

@@ -0,0 +1,444 @@
	1	// SPDX-License-Identifier: MIT
	2	/*
	3	* Copyright(c) 2023 Intel Corporation.
	4	*/
	5
	6	#include "gem/i915_gem_internal.h"
	7
	8	#include "gt/intel_context.h"
	9	#include "gt/uc/intel_gsc_fw.h"
	10	#include "gt/uc/intel_gsc_uc_heci_cmd_submit.h"
	11
	12	#include "i915_drv.h"
	13	#include "intel_pxp.h"
	14	#include "intel_pxp_cmd_interface_42.h"
	15	#include "intel_pxp_cmd_interface_43.h"
	16	#include "intel_pxp_gsccs.h"
	17	#include "intel_pxp_types.h"
	18
	19	static bool
	20	is_fw_err_platform_config(u32 type)
	21	{
	22	switch (type) {
	23	case PXP_STATUS_ERROR_API_VERSION:
	24	case PXP_STATUS_PLATFCONFIG_KF1_NOVERIF:
	25	case PXP_STATUS_PLATFCONFIG_KF1_BAD:
	26	return true;
	27	default:
	28	break;
	29	}
	30	return false;
	31	}
	32
	33	static const char *
	34	fw_err_to_string(u32 type)
	35	{
	36	switch (type) {
	37	case PXP_STATUS_ERROR_API_VERSION:
	38	return "ERR_API_VERSION";
	39	case PXP_STATUS_NOT_READY:
	40	return "ERR_NOT_READY";
	41	case PXP_STATUS_PLATFCONFIG_KF1_NOVERIF:
	42	case PXP_STATUS_PLATFCONFIG_KF1_BAD:
	43	return "ERR_PLATFORM_CONFIG";
	44	default:
	45	break;
	46	}
	47	return NULL;
	48	}
	49
	50	static int
	51	gsccs_send_message(struct intel_pxp *pxp,
	52	void *msg_in, size_t msg_in_size,
	53	void *msg_out, size_t msg_out_size_max,
	54	size_t *msg_out_len,
	55	u64 *gsc_msg_handle_retry)
	56	{
	57	struct intel_gt *gt = pxp->ctrl_gt;
	58	struct drm_i915_private *i915 = gt->i915;
	59	struct gsccs_session_resources *exec_res = &pxp->gsccs_res;
	60	struct intel_gsc_mtl_header *header = exec_res->pkt_vaddr;
	61	struct intel_gsc_heci_non_priv_pkt pkt;
	62	size_t max_msg_size;
	63	u32 reply_size;
	64	int ret;
	65
	66	if (!exec_res->ce)
	67	return -ENODEV;
	68
	69	max_msg_size = PXP43_MAX_HECI_INOUT_SIZE - sizeof(*header);
	70
	71	if (msg_in_size > max_msg_size \|\| msg_out_size_max > max_msg_size)
	72	return -ENOSPC;
	73
	74	if (!exec_res->pkt_vma \|\| !exec_res->bb_vma)
	75	return -ENOENT;
	76
	77	GEM_BUG_ON(exec_res->pkt_vma->size < (2 * PXP43_MAX_HECI_INOUT_SIZE));
	78
	79	mutex_lock(&pxp->tee_mutex);
	80
	81	memset(header, 0, sizeof(*header));
	82	intel_gsc_uc_heci_cmd_emit_mtl_header(header, HECI_MEADDRESS_PXP,
	83	msg_in_size + sizeof(*header),
	84	exec_res->host_session_handle);
	85
	86	/* check if this is a host-session-handle cleanup call (empty packet) */
	87	if (!msg_in && !msg_out)
	88	header->flags \|= GSC_INFLAG_MSG_CLEANUP;
	89
	90	/* copy caller provided gsc message handle if this is polling for a prior msg completion */
	91	header->gsc_message_handle = *gsc_msg_handle_retry;
	92
	93	/* NOTE: zero size packets are used for session-cleanups */
	94	if (msg_in && msg_in_size)
	95	memcpy(exec_res->pkt_vaddr + sizeof(*header), msg_in, msg_in_size);
	96
	97	pkt.addr_in = i915_vma_offset(exec_res->pkt_vma);
	98	pkt.size_in = header->message_size;
	99	pkt.addr_out = pkt.addr_in + PXP43_MAX_HECI_INOUT_SIZE;
	100	pkt.size_out = msg_out_size_max + sizeof(*header);
	101	pkt.heci_pkt_vma = exec_res->pkt_vma;
	102	pkt.bb_vma = exec_res->bb_vma;
	103
	104	/*
	105	* Before submitting, let's clear-out the validity marker on the reply offset.
	106	* We use offset PXP43_MAX_HECI_INOUT_SIZE for reply location so point header there.
	107	*/
	108	header = exec_res->pkt_vaddr + PXP43_MAX_HECI_INOUT_SIZE;
	109	header->validity_marker = 0;
	110
	111	ret = intel_gsc_uc_heci_cmd_submit_nonpriv(&gt->uc.gsc,
	112	exec_res->ce, &pkt, exec_res->bb_vaddr,
	113	GSC_REPLY_LATENCY_MS);
	114	if (ret) {
	115	drm_err(&i915->drm, "failed to send gsc PXP msg (%d)\n", ret);
	116	goto unlock;
	117	}
	118
	119	/* Response validity marker, status and busyness */
	120	if (header->validity_marker != GSC_HECI_VALIDITY_MARKER) {
	121	drm_err(&i915->drm, "gsc PXP reply with invalid validity marker\n");
	122	ret = -EINVAL;
	123	goto unlock;
	124	}
	125	if (header->status != 0) {
	126	drm_dbg(&i915->drm, "gsc PXP reply status has error = 0x%08x\n",
	127	header->status);
	128	ret = -EINVAL;
	129	goto unlock;
	130	}
	131	if (header->flags & GSC_OUTFLAG_MSG_PENDING) {
	132	drm_dbg(&i915->drm, "gsc PXP reply is busy\n");
	133	/*
	134	* When the GSC firmware replies with pending bit, it means that the requested
	135	* operation has begun but the completion is pending and the caller needs
	136	* to re-request with the gsc_message_handle that was returned by the firmware.
	137	* until the pending bit is turned off.
	138	*/
	139	*gsc_msg_handle_retry = header->gsc_message_handle;
	140	ret = -EAGAIN;
	141	goto unlock;
	142	}
	143
	144	reply_size = header->message_size - sizeof(*header);
	145	if (reply_size > msg_out_size_max) {
	146	drm_warn(&i915->drm, "caller with insufficient PXP reply size %u (%ld)\n",
	147	reply_size, msg_out_size_max);
	148	reply_size = msg_out_size_max;
	149	}
	150
	151	if (msg_out)
	152	memcpy(msg_out, exec_res->pkt_vaddr + PXP43_MAX_HECI_INOUT_SIZE + sizeof(*header),
	153	reply_size);
	154	if (msg_out_len)
	155	*msg_out_len = reply_size;
	156
	157	unlock:
	158	mutex_unlock(&pxp->tee_mutex);
	159	return ret;
	160	}
	161
	162	static int
	163	gsccs_send_message_retry_complete(struct intel_pxp *pxp,
	164	void *msg_in, size_t msg_in_size,
	165	void *msg_out, size_t msg_out_size_max,
	166	size_t *msg_out_len)
	167	{
	168	u64 gsc_session_retry = 0;
	169	int ret, tries = 0;
	170
	171	/*
	172	* Keep sending request if GSC firmware was busy. Based on fw specs +
	173	* sw overhead (and testing) we expect a worst case pending-bit delay of
	174	* GSC_PENDING_RETRY_MAXCOUNT x GSC_PENDING_RETRY_PAUSE_MS millisecs.
	175	*/
	176	do {
	177	ret = gsccs_send_message(pxp, msg_in, msg_in_size, msg_out, msg_out_size_max,
	178	msg_out_len, &gsc_session_retry);
	179	/* Only try again if gsc says so */
	180	if (ret != -EAGAIN)
	181	break;
	182
	183	msleep(GSC_PENDING_RETRY_PAUSE_MS);
	184	} while (++tries < GSC_PENDING_RETRY_MAXCOUNT);
	185
	186	return ret;
	187	}
	188
	189	bool intel_pxp_gsccs_is_ready_for_sessions(struct intel_pxp *pxp)
	190	{
	191	/*
	192	* GSC-fw loading, HuC-fw loading, HuC-fw authentication and
	193	* GSC-proxy init flow (requiring an mei component driver)
	194	* must all occur first before we can start requesting for PXP
	195	* sessions. Checking for completion on HuC authentication and
	196	* gsc-proxy init flow (the last set of dependencies that
	197	* are out of order) will suffice.
	198	*/
	199	if (intel_huc_is_authenticated(&pxp->ctrl_gt->uc.huc) &&
	200	intel_gsc_uc_fw_proxy_init_done(&pxp->ctrl_gt->uc.gsc))
	201	return true;
	202
	203	return false;
	204	}
	205
	206	int intel_pxp_gsccs_create_session(struct intel_pxp *pxp,
	207	int arb_session_id)
	208	{
	209	struct drm_i915_private *i915 = pxp->ctrl_gt->i915;
	210	struct pxp43_create_arb_in msg_in = {0};
	211	struct pxp43_create_arb_out msg_out = {0};
	212	int ret;
	213
	214	msg_in.header.api_version = PXP_APIVER(4, 3);
	215	msg_in.header.command_id = PXP43_CMDID_INIT_SESSION;
	216	msg_in.header.stream_id = (FIELD_PREP(PXP43_INIT_SESSION_APPID, arb_session_id) \|
	217	FIELD_PREP(PXP43_INIT_SESSION_VALID, 1) \|
	218	FIELD_PREP(PXP43_INIT_SESSION_APPTYPE, 0));
	219	msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header);
	220	msg_in.protection_mode = PXP43_INIT_SESSION_PROTECTION_ARB;
	221
	222	ret = gsccs_send_message_retry_complete(pxp,
	223	&msg_in, sizeof(msg_in),
	224	&msg_out, sizeof(msg_out), NULL);
	225	if (ret) {
	226	drm_err(&i915->drm, "Failed to init session %d, ret=[%d]\n", arb_session_id, ret);
	227	} else if (msg_out.header.status != 0) {
	228	if (is_fw_err_platform_config(msg_out.header.status)) {
	229	drm_info_once(&i915->drm,
	230	"PXP init-session-%d failed due to BIOS/SOC:0x%08x:%s\n",
	231	arb_session_id, msg_out.header.status,
	232	fw_err_to_string(msg_out.header.status));
	233	} else {
	234	drm_dbg(&i915->drm, "PXP init-session-%d failed 0x%08x:%st:\n",
	235	arb_session_id, msg_out.header.status,
	236	fw_err_to_string(msg_out.header.status));
	237	drm_dbg(&i915->drm, " cmd-detail: ID=[0x%08x],API-Ver-[0x%08x]\n",
	238	msg_in.header.command_id, msg_in.header.api_version);
	239	}
	240	}
	241
	242	return ret;
	243	}
	244
	245	void intel_pxp_gsccs_end_arb_fw_session(struct intel_pxp *pxp, u32 session_id)
	246	{
	247	struct drm_i915_private *i915 = pxp->ctrl_gt->i915;
	248	struct pxp42_inv_stream_key_in msg_in = {0};
	249	struct pxp42_inv_stream_key_out msg_out = {0};
	250	int ret = 0;
	251
	252	/*
	253	* Stream key invalidation reuses the same version 4.2 input/output
	254	* command format but firmware requires 4.3 API interaction
	255	*/
	256	msg_in.header.api_version = PXP_APIVER(4, 3);
	257	msg_in.header.command_id = PXP42_CMDID_INVALIDATE_STREAM_KEY;
	258	msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header);
	259
	260	msg_in.header.stream_id = FIELD_PREP(PXP_CMDHDR_EXTDATA_SESSION_VALID, 1);
	261	msg_in.header.stream_id \|= FIELD_PREP(PXP_CMDHDR_EXTDATA_APP_TYPE, 0);
	262	msg_in.header.stream_id \|= FIELD_PREP(PXP_CMDHDR_EXTDATA_SESSION_ID, session_id);
	263
	264	ret = gsccs_send_message_retry_complete(pxp,
	265	&msg_in, sizeof(msg_in),
	266	&msg_out, sizeof(msg_out), NULL);
	267	if (ret) {
	268	drm_err(&i915->drm, "Failed to inv-stream-key-%u, ret=[%d]\n",
	269	session_id, ret);
	270	} else if (msg_out.header.status != 0) {
	271	if (is_fw_err_platform_config(msg_out.header.status)) {
	272	drm_info_once(&i915->drm,
	273	"PXP inv-stream-key-%u failed due to BIOS/SOC :0x%08x:%s\n",
	274	session_id, msg_out.header.status,
	275	fw_err_to_string(msg_out.header.status));
	276	} else {
	277	drm_dbg(&i915->drm, "PXP inv-stream-key-%u failed 0x%08x:%s:\n",
	278	session_id, msg_out.header.status,
	279	fw_err_to_string(msg_out.header.status));
	280	drm_dbg(&i915->drm, " cmd-detail: ID=[0x%08x],API-Ver-[0x%08x]\n",
	281	msg_in.header.command_id, msg_in.header.api_version);
	282	}
	283	}
	284	}
	285
	286	static void
	287	gsccs_cleanup_fw_host_session_handle(struct intel_pxp *pxp)
	288	{
	289	struct drm_i915_private *i915 = pxp->ctrl_gt->i915;
	290	int ret;
	291
	292	ret = gsccs_send_message_retry_complete(pxp, NULL, 0, NULL, 0, NULL);
	293	if (ret)
	294	drm_dbg(&i915->drm, "Failed to send gsccs msg host-session-cleanup: ret=[%d]\n",
	295	ret);
	296	}
	297
	298	static void
	299	gsccs_destroy_execution_resource(struct intel_pxp *pxp)
	300	{
	301	struct gsccs_session_resources *exec_res = &pxp->gsccs_res;
	302
	303	if (exec_res->host_session_handle)
	304	gsccs_cleanup_fw_host_session_handle(pxp);
	305	if (exec_res->ce)
	306	intel_context_put(exec_res->ce);
	307	if (exec_res->bb_vma)
	308	i915_vma_unpin_and_release(&exec_res->bb_vma, I915_VMA_RELEASE_MAP);
	309	if (exec_res->pkt_vma)
	310	i915_vma_unpin_and_release(&exec_res->pkt_vma, I915_VMA_RELEASE_MAP);
	311
	312	memset(exec_res, 0, sizeof(*exec_res));
	313	}
	314
	315	static int
	316	gsccs_create_buffer(struct intel_gt *gt,
	317	const char *bufname, size_t size,
	318	struct i915_vma vma, void map)
	319	{
	320	struct drm_i915_private *i915 = gt->i915;
	321	struct drm_i915_gem_object *obj;
	322	int err = 0;
	323
	324	obj = i915_gem_object_create_internal(i915, size);
	325	if (IS_ERR(obj)) {
	326	drm_err(&i915->drm, "Failed to allocate gsccs backend %s.\n", bufname);
	327	err = PTR_ERR(obj);
	328	goto out_none;
	329	}
	330
	331	*vma = i915_vma_instance(obj, gt->vm, NULL);
	332	if (IS_ERR(*vma)) {
	333	drm_err(&i915->drm, "Failed to vma-instance gsccs backend %s.\n", bufname);
	334	err = PTR_ERR(*vma);
	335	goto out_put;
	336	}
	337
	338	/* return a virtual pointer */
	339	*map = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(i915, obj, true));
	340	if (IS_ERR(*map)) {
	341	drm_err(&i915->drm, "Failed to map gsccs backend %s.\n", bufname);
	342	err = PTR_ERR(*map);
	343	goto out_put;
	344	}
	345
	346	/* all PXP sessions commands are treated as non-privileged */
	347	err = i915_vma_pin(*vma, 0, 0, PIN_USER);
	348	if (err) {
	349	drm_err(&i915->drm, "Failed to vma-pin gsccs backend %s.\n", bufname);
	350	goto out_unmap;
	351	}
	352
	353	return 0;
	354
	355	out_unmap:
	356	i915_gem_object_unpin_map(obj);
	357	out_put:
	358	i915_gem_object_put(obj);
	359	out_none:
	360	*vma = NULL;
	361	*map = NULL;
	362
	363	return err;
	364	}
	365
	366	static int
	367	gsccs_allocate_execution_resource(struct intel_pxp *pxp)
	368	{
	369	struct intel_gt *gt = pxp->ctrl_gt;
	370	struct gsccs_session_resources *exec_res = &pxp->gsccs_res;
	371	struct intel_engine_cs *engine = gt->engine[GSC0];
	372	struct intel_context *ce;
	373	int err = 0;
	374
	375	/*
	376	* First, ensure the GSC engine is present.
	377	* NOTE: Backend would only be called with the correct gt.
	378	*/
	379	if (!engine)
	380	return -ENODEV;
	381
	382	/*
	383	* Now, allocate, pin and map two objects, one for the heci message packet
	384	* and another for the batch buffer we submit into GSC engine (that includes the packet).
	385	* NOTE: GSC-CS backend is currently only supported on MTL, so we allocate shmem.
	386	*/
	387	err = gsccs_create_buffer(pxp->ctrl_gt, "Heci Packet",
	388	2 * PXP43_MAX_HECI_INOUT_SIZE,
	389	&exec_res->pkt_vma, &exec_res->pkt_vaddr);
	390	if (err)
	391	return err;
	392
	393	err = gsccs_create_buffer(pxp->ctrl_gt, "Batch Buffer", PAGE_SIZE,
	394	&exec_res->bb_vma, &exec_res->bb_vaddr);
	395	if (err)
	396	goto free_pkt;
	397
	398	/* Finally, create an intel_context to be used during the submission */
	399	ce = intel_context_create(engine);
	400	if (IS_ERR(ce)) {
	401	drm_err(&gt->i915->drm, "Failed creating gsccs backend ctx\n");
	402	err = PTR_ERR(ce);
	403	goto free_batch;
	404	}
	405
	406	i915_vm_put(ce->vm);
	407	ce->vm = i915_vm_get(pxp->ctrl_gt->vm);
	408	exec_res->ce = ce;
	409
	410	/* initialize host-session-handle (for all i915-to-gsc-firmware PXP cmds) */
	411	get_random_bytes(&exec_res->host_session_handle, sizeof(exec_res->host_session_handle));
	412
	413	return 0;
	414
	415	free_batch:
	416	i915_vma_unpin_and_release(&exec_res->bb_vma, I915_VMA_RELEASE_MAP);
	417	free_pkt:
	418	i915_vma_unpin_and_release(&exec_res->pkt_vma, I915_VMA_RELEASE_MAP);
	419	memset(exec_res, 0, sizeof(*exec_res));
	420
	421	return err;
	422	}
	423
	424	void intel_pxp_gsccs_fini(struct intel_pxp *pxp)
	425	{
	426	intel_wakeref_t wakeref;
	427
	428	gsccs_destroy_execution_resource(pxp);
	429	with_intel_runtime_pm(&pxp->ctrl_gt->i915->runtime_pm, wakeref)
	430	intel_pxp_fini_hw(pxp);
	431	}
	432
	433	int intel_pxp_gsccs_init(struct intel_pxp *pxp)
	434	{
	435	int ret;
	436	intel_wakeref_t wakeref;
	437
	438	ret = gsccs_allocate_execution_resource(pxp);
	439	if (!ret) {
	440	with_intel_runtime_pm(&pxp->ctrl_gt->i915->runtime_pm, wakeref)
	441	intel_pxp_init_hw(pxp);
	442	}
	443	return ret;
	444	}

drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h+43−0

@@ -0,0 +1,43 @@
	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright(c) 2022, Intel Corporation. All rights reserved.
	4	*/
	5
	6	#ifndef __INTEL_PXP_GSCCS_H__
	7	#define __INTEL_PXP_GSCCS_H__
	8
	9	#include <linux/types.h>
	10
	11	struct intel_pxp;
	12
	13	#define GSC_REPLY_LATENCY_MS 210
	14	/*
	15	* Max FW response time is 200ms, to which we add 10ms to account for overhead
	16	* such as request preparation, GuC submission to hw and pipeline completion times.
	17	*/
	18	#define GSC_PENDING_RETRY_MAXCOUNT 40
	19	#define GSC_PENDING_RETRY_PAUSE_MS 50
	20	#define GSCFW_MAX_ROUND_TRIP_LATENCY_MS (GSC_PENDING_RETRY_MAXCOUNT * GSC_PENDING_RETRY_PAUSE_MS)
	21
	22	#ifdef CONFIG_DRM_I915_PXP
	23	void intel_pxp_gsccs_fini(struct intel_pxp *pxp);
	24	int intel_pxp_gsccs_init(struct intel_pxp *pxp);
	25
	26	int intel_pxp_gsccs_create_session(struct intel_pxp *pxp, int arb_session_id);
	27	void intel_pxp_gsccs_end_arb_fw_session(struct intel_pxp *pxp, u32 arb_session_id);
	28
	29	#else
	30	static inline void intel_pxp_gsccs_fini(struct intel_pxp *pxp)
	31	{
	32	}
	33
	34	static inline int intel_pxp_gsccs_init(struct intel_pxp *pxp)
	35	{
	36	return 0;
	37	}
	38
	39	#endif
	40
	41	bool intel_pxp_gsccs_is_ready_for_sessions(struct intel_pxp *pxp);
	42
	43	#endif /__INTEL_PXP_GSCCS_H__ /

drivers/gpu/drm/i915/pxp/intel_pxp_pm.c+2−1

 	 * The PXP component gets automatically unbound when we go into S3 and
 	 * re-bound after we come out, so in that scenario we can defer the
 	 * hw init to the bind call.
+	 * NOTE: GSC-CS backend doesn't rely on components.
 	 */
-	if (!pxp->pxp_component)
+	if (!HAS_ENGINE(pxp->ctrl_gt, GSC0) && !pxp->pxp_component)
 		return;
 	intel_pxp_init_hw(pxp);

drivers/gpu/drm/i915/pxp/intel_pxp_regs.h+27−0

@@ -0,0 +1,27 @@
	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright(c) 2023, Intel Corporation. All rights reserved.
	4	*/
	5
	6	#ifndef __INTEL_PXP_REGS_H__
	7	#define __INTEL_PXP_REGS_H__
	8
	9	#include "i915_reg_defs.h"
	10
	11	/* KCR subsystem register base address */
	12	#define GEN12_KCR_BASE 0x32000
	13	#define MTL_KCR_BASE 0x386000
	14
	15	/* KCR enable/disable control */
	16	#define KCR_INIT(base) _MMIO((base) + 0xf0)
	17
	18	/* Setting KCR Init bit is required after system boot */
	19	#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
	20
	21	/* KCR hwdrm session in play status 0-31 */
	22	#define KCR_SIP(base) _MMIO((base) + 0x260)
	23
	24	/* PXP global terminate register for session termination */
	25	#define KCR_GLOBAL_TERMINATE(base) _MMIO((base) + 0xf8)
	26
	27	#endif /* __INTEL_PXP_REGS_H__ */

drivers/gpu/drm/i915/pxp/intel_pxp_session.c+14−11

 #include "intel_pxp.h"
 #include "intel_pxp_cmd.h"
+#include "intel_pxp_gsccs.h"
 #include "intel_pxp_session.h"
 #include "intel_pxp_tee.h"
 #include "intel_pxp_types.h"
+#include "intel_pxp_regs.h"
 #define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define */
-#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
-/* PXP global terminate register for session termination */
-#define PXP_GLOBAL_TERMINATE _MMIO(0x320f8)
 static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
 {
 	struct intel_uncore *uncore = pxp->ctrl_gt->uncore;
 	/* if we're suspended the session is considered off */
 	with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref)
-		sip = intel_uncore_read(uncore, GEN12_KCR_SIP);
+		sip = intel_uncore_read(uncore, KCR_SIP(pxp->kcr_base));
 	return sip & BIT(id);
 }
 		return in_play ? -ENODEV : 0;
 	ret = intel_wait_for_register(uncore,
-				      GEN12_KCR_SIP,
+				      KCR_SIP(pxp->kcr_base),
 				      mask,
 				      in_play ? mask : 0,
-				      100);
+				      250);
 	intel_runtime_pm_put(uncore->rpm, wakeref);
 		return -EEXIST;
 	}
-	ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION);
+	if (HAS_ENGINE(pxp->ctrl_gt, GSC0))
+		ret = intel_pxp_gsccs_create_session(pxp, ARB_SESSION);
+	else
+		ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION);
 	if (ret) {
 		drm_err(&gt->i915->drm, "tee cmd for arb session creation failed\n");
 		return ret;
 		return ret;
 	}
-	intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1);
+	intel_uncore_write(gt->uncore, KCR_GLOBAL_TERMINATE(pxp->kcr_base), 1);
-	intel_pxp_tee_end_arb_fw_session(pxp, ARB_SESSION);
+	if (HAS_ENGINE(gt, GSC0))
+		intel_pxp_gsccs_end_arb_fw_session(pxp, ARB_SESSION);
+	else
+		intel_pxp_tee_end_arb_fw_session(pxp, ARB_SESSION);
 	return ret;
 }

drivers/gpu/drm/i915/pxp/intel_pxp_tee.c+0−2

@@ -284,8 +284,6 @@ int intel_pxp_tee_component_init(struct intel_pxp *pxp) · 283 unmodified lines
284	struct intel_gt *gt = pxp->ctrl_gt;	284	struct intel_gt *gt = pxp->ctrl_gt;
285	struct drm_i915_private *i915 = gt->i915;	285	struct drm_i915_private *i915 = gt->i915;
286		286
287	mutex_init(&pxp->tee_mutex);
288
289	ret = alloc_streaming_command(pxp);	287	ret = alloc_streaming_command(pxp);
290	if (ret)	288	if (ret)
291	return ret;	289	return ret;

drivers/gpu/drm/i915/pxp/intel_pxp_types.h+23−1

@@ -26,6 +26,26 @@ struct intel_pxp { · 25 unmodified lines
26	*/	26	*/
27	struct intel_gt *ctrl_gt;	27	struct intel_gt *ctrl_gt;
28		28
		29	/**
		30	* @kcr_base: base mmio offset for the KCR engine which is different on legacy platforms
		31	* vs newer platforms where the KCR is inside the media-tile.
		32	*/
		33	u32 kcr_base;
		34
		35	/**
		36	* @gsccs_res: resources for request submission for platforms that have a GSC engine.
		37	*/
		38	struct gsccs_session_resources {
		39	u64 host_session_handle; /* used by firmware to link commands to sessions */
		40	struct intel_context ce; / context for gsc command submission */
		41
		42	struct i915_vma pkt_vma; / GSC FW cmd packet vma */
		43	void pkt_vaddr; / GSC FW cmd packet virt pointer */
		44
		45	struct i915_vma bb_vma; / HECI_PKT batch buffer vma */
		46	void bb_vaddr; / HECI_PKT batch buffer virt pointer */
		47	} gsccs_res;
		48
29	/**	49	/**
30	* @pxp_component: i915_pxp_component struct of the bound mei_pxp	50	* @pxp_component: i915_pxp_component struct of the bound mei_pxp
31	* module. Only set and cleared inside component bind/unbind functions,	51	* module. Only set and cleared inside component bind/unbind functions,
@@ -33,7 +53,9 @@ struct intel_pxp { · 1 unmodified line
33	*/	53	*/
34	struct i915_pxp_component *pxp_component;	54	struct i915_pxp_component *pxp_component;
35		55
36	/* @dev_link: Enforce module relationship for power management ordering. */	56	/**
		57	* @dev_link: Enforce module relationship for power management ordering.
		58	*/
37	struct device_link *dev_link;	59	struct device_link *dev_link;
38	/**	60	/**
39	* @pxp_component_added: track if the pxp component has been added.	61	* @pxp_component_added: track if the pxp component has been added.

drivers/gpu/drm/i915/selftests/i915_gem.c+4−1

 		u32 __iomem *s;
 		int x;
-		ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
+		ggtt->vm.insert_page(&ggtt->vm, dma, slot,
+				     i915_gem_get_pat_index(i915,
+							    I915_CACHE_NONE),
+				     0);
 		s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
 		for (x = 0; x < PAGE_SIZE / sizeof(u32); x++) {

drivers/gpu/drm/i915/selftests/i915_gem_evict.c+5−3

 #include "gem/selftests/igt_gem_utils.h"
 #include "gem/selftests/mock_context.h"
 #include "gt/intel_gt.h"
+#include "gt/intel_gt_print.h"
 #include "i915_selftest.h"
 	struct drm_mm_node target = {
 		.start = I915_GTT_PAGE_SIZE * 2,
 		.size = I915_GTT_PAGE_SIZE,
-		.color = I915_CACHE_LLC,
+		.color = i915_gem_get_pat_index(gt->i915, I915_CACHE_LLC),
 	};
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
 	/* Attempt to remove the first *pinned* vma, by removing the (empty)
 	 * neighbour -- this should fail.
 	 */
-	target.color = I915_CACHE_L3_LLC;
+	target.color = i915_gem_get_pat_index(gt->i915, I915_CACHE_L3_LLC);
 	mutex_lock(&ggtt->vm.mutex);
 	err = i915_gem_evict_for_node(&ggtt->vm, NULL, &target, 0);
 		}
 		err = intel_gt_wait_for_idle(engine->gt, HZ * 3);
 		if (err) {
-			pr_err("Failed to idle GT (on %s)", engine->name);
+			gt_err(engine->gt, "Failed to idle GT (on %s)",
+			       engine->name);
 			break;
 		}
 	}

drivers/gpu/drm/i915/selftests/i915_gem_gtt.c+10−5

 	obj->write_domain = I915_GEM_DOMAIN_CPU;
 	obj->read_domains = I915_GEM_DOMAIN_CPU;
-	obj->cache_level = I915_CACHE_NONE;
+	obj->pat_index = i915_gem_get_pat_index(i915, I915_CACHE_NONE);
 	/* Preallocate the "backing storage" */
 	if (i915_gem_object_pin_pages_unlocked(obj))
 			with_intel_runtime_pm(vm->gt->uncore->rpm, wakeref)
 			  vm->insert_entries(vm, mock_vma_res,
-						   I915_CACHE_NONE, 0);
+					     i915_gem_get_pat_index(vm->i915,
+								    I915_CACHE_NONE),
+					     0);
 		}
 		count = n;
 		ggtt->vm.insert_page(&ggtt->vm,
 				     i915_gem_object_get_dma_address(obj, 0),
-				     offset, I915_CACHE_NONE, 0);
+				     offset,
+				     i915_gem_get_pat_index(i915,
+							    I915_CACHE_NONE),
+				     0);
 	}
 	order = i915_random_order(count, &prng);
 	mutex_lock(&vm->mutex);
 	err = i915_gem_gtt_reserve(vm, NULL, &vma->node, obj->base.size,
 				   offset,
-				   obj->cache_level,
+				   obj->pat_index,
 				   0);
 	if (!err) {
 		i915_vma_resource_init_from_vma(vma_res, vma);
 	mutex_lock(&vm->mutex);
 	err = i915_gem_gtt_insert(vm, NULL, &vma->node, obj->base.size, 0,
-				  obj->cache_level, 0, vm->total, 0);
+				  obj->pat_index, 0, vm->total, 0);
 	if (!err) {
 		i915_vma_resource_init_from_vma(vma_res, vma);
 		vma->resource = vma_res;

drivers/gpu/drm/i915/selftests/igt_live_test.c+28−19

 #include "i915_drv.h"
 #include "gt/intel_gt.h"
+#include "gt/intel_gt_print.h"
 #include "../i915_selftest.h"
 #include "igt_flush_test.h"
 			const char *func,
 			const char *name)
 {
-	struct intel_gt *gt = to_gt(i915);
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
+	struct intel_gt *gt;
+	unsigned int i;
 	int err;
 	t->i915 = i915;
 	t->func = func;
 	t->name = name;
-	err = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
+	for_each_gt(gt, i915, i) {
-	if (err) {
-		pr_err("%s(%s): failed to idle before, with err=%d!",
-		       func, name, err);
-		return err;
-	}
-	t->reset_global = i915_reset_count(&i915->gpu_error);
+		err = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
+		if (err) {
+			gt_err(gt, "%s(%s): GT failed to idle before, with err=%d!",
+			       func, name, err);
+			return err;
+		}
-	for_each_engine(engine, gt, id)
+		for_each_engine(engine, gt, id)
-		t->reset_engine[id] =
+			t->reset_engine[id] =
 			i915_reset_engine_count(&i915->gpu_error, engine);
+	}
+	t->reset_global = i915_reset_count(&i915->gpu_error);
 	return 0;
 }
 	struct drm_i915_private *i915 = t->i915;
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
+	struct intel_gt *gt;
+	unsigned int i;
 	if (igt_flush_test(i915))
 		return -EIO;
 		return -EIO;
 	}
-	for_each_engine(engine, to_gt(i915), id) {
+	for_each_gt(gt, i915, i) {
-		if (t->reset_engine[id] ==
+		for_each_engine(engine, gt, id) {
-		    i915_reset_engine_count(&i915->gpu_error, engine))
+			if (t->reset_engine[id] ==
-			continue;
+			    i915_reset_engine_count(&i915->gpu_error, engine))
+				continue;
-		pr_err("%s(%s): engine '%s' was reset %d times!\n",
+			gt_err(gt, "%s(%s): engine '%s' was reset %d times!\n",
-		       t->func, t->name, engine->name,
+			       t->func, t->name, engine->name,
-		       i915_reset_engine_count(&i915->gpu_error, engine) -
+			       i915_reset_engine_count(&i915->gpu_error, engine) -
-		       t->reset_engine[id]);
+			       t->reset_engine[id]);
-		return -EIO;
+			return -EIO;
+		}
 	}
 	return 0;

drivers/gpu/drm/i915/selftests/intel_memory_region.c+3−1

 	/* Put the pages into a known state -- from the gpu for added fun */
 	intel_engine_pm_get(engine);
 	err = intel_context_migrate_clear(engine->gt->migrate.context, NULL,
-					  obj->mm.pages->sgl, I915_CACHE_NONE,
+					  obj->mm.pages->sgl,
+					  i915_gem_get_pat_index(i915,
+								 I915_CACHE_NONE),
 					  true, 0xdeadbeaf, &rq);
 	if (rq) {
 		dma_resv_add_fence(obj->base.resv, &rq->fence,

drivers/gpu/drm/i915/selftests/mock_gem_device.c+9−0

 	static struct dev_iommu fake_iommu = { .priv = (void *)-1 };
 #endif
 	struct drm_i915_private *i915;
+	struct intel_device_info *i915_info;
 	struct pci_dev *pdev;
+	unsigned int i;
 	int ret;
 	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
 		I915_GTT_PAGE_SIZE_2M;
 	RUNTIME_INFO(i915)->memory_regions = REGION_SMEM;
+	/* simply use legacy cache level for mock device */
+	i915_info = (struct intel_device_info *)INTEL_INFO(i915);
+	i915_info->max_pat_index = 3;
+	for (i = 0; i < I915_MAX_CACHE_LEVEL; i++)
+		i915_info->cachelevel_to_pat[i] = i;
 	intel_memory_regions_hw_probe(i915);
 	spin_lock_init(&i915->gpu_error.lock);

drivers/gpu/drm/i915/selftests/mock_gtt.c+4−4

@@ -27,21 +27,21 @@ · 26 unmodified lines
27	static void mock_insert_page(struct i915_address_space *vm,	27	static void mock_insert_page(struct i915_address_space *vm,
28	dma_addr_t addr,	28	dma_addr_t addr,
29	u64 offset,	29	u64 offset,
30	enum i915_cache_level level,	30	unsigned int pat_index,
31	u32 flags)	31	u32 flags)
32	{	32	{
33	}	33	}
34		34
35	static void mock_insert_entries(struct i915_address_space *vm,	35	static void mock_insert_entries(struct i915_address_space *vm,
36	struct i915_vma_resource *vma_res,	36	struct i915_vma_resource *vma_res,
37	enum i915_cache_level level, u32 flags)	37	unsigned int pat_index, u32 flags)
38	{	38	{
39	}	39	}
40		40
41	static void mock_bind_ppgtt(struct i915_address_space *vm,	41	static void mock_bind_ppgtt(struct i915_address_space *vm,
42	struct i915_vm_pt_stash *stash,	42	struct i915_vm_pt_stash *stash,
43	struct i915_vma_resource *vma_res,	43	struct i915_vma_resource *vma_res,
44	enum i915_cache_level cache_level,	44	unsigned int pat_index,
45	u32 flags)	45	u32 flags)
46	{	46	{
47	GEM_BUG_ON(flags & I915_VMA_GLOBAL_BIND);	47	GEM_BUG_ON(flags & I915_VMA_GLOBAL_BIND);
@@ -94,7 +94,7 @@ struct i915_ppgtt mock_ppgtt(struct drm_i915_private i915, const char *name) · 46 unmodified lines
94	static void mock_bind_ggtt(struct i915_address_space *vm,	94	static void mock_bind_ggtt(struct i915_address_space *vm,
95	struct i915_vm_pt_stash *stash,	95	struct i915_vm_pt_stash *stash,
96	struct i915_vma_resource *vma_res,	96	struct i915_vma_resource *vma_res,
97	enum i915_cache_level cache_level,	97	unsigned int pat_index,
98	u32 flags)	98	u32 flags)
99	{	99	{
100	}	100	}

drivers/gpu/drm/imx/lcdc/imx-lcdc.c+2−2

@@ -400,8 +400,8 @@ static int imx_lcdc_probe(struct platform_device *pdev) · 399 unmodified lines
400		400
401	lcdc = devm_drm_dev_alloc(dev, &imx_lcdc_drm_driver,	401	lcdc = devm_drm_dev_alloc(dev, &imx_lcdc_drm_driver,
402	struct imx_lcdc, drm);	402	struct imx_lcdc, drm);
403	if (!lcdc)	403	if (IS_ERR(lcdc))
404	return -ENOMEM;	404	return PTR_ERR(lcdc);
405		405
406	drm = &lcdc->drm;	406	drm = &lcdc->drm;
407		407

drivers/gpu/drm/meson/meson_drv.c+1−1

@@ -285,7 +285,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) · 284 unmodified lines
285	* Remove early framebuffers (ie. simplefb). The framebuffer can be	285	* Remove early framebuffers (ie. simplefb). The framebuffer can be
286	* located anywhere in RAM	286	* located anywhere in RAM
287	*/	287	*/
288	ret = drm_aperture_remove_framebuffers(false, &meson_driver);	288	ret = drm_aperture_remove_framebuffers(&meson_driver);
289	if (ret)	289	if (ret)
290	goto free_drm;	290	goto free_drm;
291		291

drivers/gpu/drm/meson/meson_venc.c+16−16

@@ -186,7 +186,7 @@ union meson_hdmi_venc_mode { · 185 unmodified lines
186	} encp;	186	} encp;
187	};	187	};
188		188
189	union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = {	189	static union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = {
190	.enci = {	190	.enci = {
191	.hso_begin = 5,	191	.hso_begin = 5,
192	.hso_end = 129,	192	.hso_end = 129,
@@ -206,7 +206,7 @@ union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = { · 13 unmodified lines
206	},	206	},
207	};	207	};
208		208
209	union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = {	209	static union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = {
210	.enci = {	210	.enci = {
211	.hso_begin = 3,	211	.hso_begin = 3,
212	.hso_end = 129,	212	.hso_end = 129,
@@ -226,7 +226,7 @@ union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = { · 13 unmodified lines
226	},	226	},
227	};	227	};
228		228
229	union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = {	229	static union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = {
230	.encp = {	230	.encp = {
231	.dvi_settings = 0x21,	231	.dvi_settings = 0x21,
232	.video_mode = 0x4000,	232	.video_mode = 0x4000,
@@ -272,7 +272,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = { · 39 unmodified lines
272	},	272	},
273	};	273	};
274		274
275	union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = {	275	static union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = {
276	.encp = {	276	.encp = {
277	.dvi_settings = 0x21,	277	.dvi_settings = 0x21,
278	.video_mode = 0x4000,	278	.video_mode = 0x4000,
@@ -318,7 +318,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = { · 39 unmodified lines
318	},	318	},
319	};	319	};
320		320
321	union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {	321	static union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {
322	.encp = {	322	.encp = {
323	.dvi_settings = 0x2029,	323	.dvi_settings = 0x2029,
324	.video_mode = 0x4040,	324	.video_mode = 0x4040,
@@ -360,7 +360,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = { · 35 unmodified lines
360	},	360	},
361	};	361	};
362		362
363	union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {	363	static union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {
364	.encp = {	364	.encp = {
365	.dvi_settings = 0x202d,	365	.dvi_settings = 0x202d,
366	.video_mode = 0x4040,	366	.video_mode = 0x4040,
@@ -405,7 +405,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = { · 38 unmodified lines
405	},	405	},
406	};	406	};
407		407
408	union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {	408	static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {
409	.encp = {	409	.encp = {
410	.dvi_settings = 0x2029,	410	.dvi_settings = 0x2029,
411	.video_mode = 0x5ffc,	411	.video_mode = 0x5ffc,
@@ -454,7 +454,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = { · 42 unmodified lines
454	},	454	},
455	};	455	};
456		456
457	union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {	457	static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {
458	.encp = {	458	.encp = {
459	.dvi_settings = 0x202d,	459	.dvi_settings = 0x202d,
460	.video_mode = 0x5ffc,	460	.video_mode = 0x5ffc,
@@ -503,7 +503,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = { · 42 unmodified lines
503	},	503	},
504	};	504	};
505		505
506	union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = {	506	static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = {
507	.encp = {	507	.encp = {
508	.dvi_settings = 0xd,	508	.dvi_settings = 0xd,
509	.video_mode = 0x4040,	509	.video_mode = 0x4040,
@@ -552,7 +552,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = { · 42 unmodified lines
552	},	552	},
553	};	553	};
554		554
555	union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = {	555	static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = {
556	.encp = {	556	.encp = {
557	.dvi_settings = 0x1,	557	.dvi_settings = 0x1,
558	.video_mode = 0x4040,	558	.video_mode = 0x4040,
@@ -596,7 +596,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = { · 37 unmodified lines
596	},	596	},
597	};	597	};
598		598
599	union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = {	599	static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = {
600	.encp = {	600	.encp = {
601	.dvi_settings = 0xd,	601	.dvi_settings = 0xd,
602	.video_mode = 0x4040,	602	.video_mode = 0x4040,
@@ -644,7 +644,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = { · 41 unmodified lines
644	},	644	},
645	};	645	};
646		646
647	union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {	647	static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
648	.encp = {	648	.encp = {
649	.dvi_settings = 0x1,	649	.dvi_settings = 0x1,
650	.video_mode = 0x4040,	650	.video_mode = 0x4040,
@@ -688,7 +688,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = { · 37 unmodified lines
688	},	688	},
689	};	689	};
690		690
691	union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p24 = {	691	static union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p24 = {
692	.encp = {	692	.encp = {
693	.dvi_settings = 0x1,	693	.dvi_settings = 0x1,
694	.video_mode = 0x4040,	694	.video_mode = 0x4040,
@@ -730,7 +730,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p24 = { · 35 unmodified lines
730	},	730	},
731	};	731	};
732		732
733	union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p25 = {	733	static union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p25 = {
734	.encp = {	734	.encp = {
735	.dvi_settings = 0x1,	735	.dvi_settings = 0x1,
736	.video_mode = 0x4040,	736	.video_mode = 0x4040,
@@ -772,7 +772,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p25 = { · 35 unmodified lines
772	},	772	},
773	};	773	};
774		774
775	union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = {	775	static union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = {
776	.encp = {	776	.encp = {
777	.dvi_settings = 0x1,	777	.dvi_settings = 0x1,
778	.video_mode = 0x4040,	778	.video_mode = 0x4040,
@@ -814,7 +814,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = { · 35 unmodified lines
814	},	814	},
815	};	815	};
816		816
817	struct meson_hdmi_venc_vic_mode {	817	static struct meson_hdmi_venc_vic_mode {
818	unsigned int vic;	818	unsigned int vic;
819	union meson_hdmi_venc_mode *mode;	819	union meson_hdmi_venc_mode *mode;
820	} meson_hdmi_venc_vic_modes[] = {	820	} meson_hdmi_venc_vic_modes[] = {

drivers/gpu/drm/msm/msm_drv.c+1−1

@@ -455,7 +455,7 @@ static int msm_drm_init(struct device dev, const struct drm_driver drv) · 454 unmodified lines
455	goto err_deinit_vram;	455	goto err_deinit_vram;
456		456
457	/* the fw fb could be anywhere in memory */	457	/* the fw fb could be anywhere in memory */
458	ret = drm_aperture_remove_framebuffers(false, drv);	458	ret = drm_aperture_remove_framebuffers(drv);
459	if (ret)	459	if (ret)
460	goto err_msm_uninit;	460	goto err_msm_uninit;
461		461

drivers/gpu/drm/msm/msm_fbdev.c+3−3

@@ -121,9 +121,9 @@ static int msm_fbdev_create(struct drm_fb_helper *helper, · 120 unmodified lines
121		121
122	drm_fb_helper_fill_info(fbi, helper, sizes);	122	drm_fb_helper_fill_info(fbi, helper, sizes);
123		123
124	fbi->screen_base = msm_gem_get_vaddr(bo);	124	fbi->screen_buffer = msm_gem_get_vaddr(bo);
125	if (IS_ERR(fbi->screen_base)) {	125	if (IS_ERR(fbi->screen_buffer)) {
126	ret = PTR_ERR(fbi->screen_base);	126	ret = PTR_ERR(fbi->screen_buffer);
127	goto fail;	127	goto fail;
128	}	128	}
129	fbi->screen_size = bo->size;	129	fbi->screen_size = bo->size;

drivers/gpu/drm/nouveau/dispnv50/disp.c+1−0

@@ -64,6 +64,7 @@ · 63 unmodified lines
64	#include "nouveau_connector.h"	64	#include "nouveau_connector.h"
65	#include "nouveau_encoder.h"	65	#include "nouveau_encoder.h"
66	#include "nouveau_fence.h"	66	#include "nouveau_fence.h"
		67	#include "nv50_display.h"
67		68
68	#include <subdev/bios/dp.h>	69	#include <subdev/bios/dp.h>
69		70

drivers/gpu/drm/nouveau/include/nvif/if0012.h+3−1

 #ifndef __NVIF_IF0012_H__
 #define __NVIF_IF0012_H__
+#include <drm/display/drm_dp.h>
 union nvif_outp_args {
 	struct nvif_outp_v0 {
 		__u8 version;
 				__u8 hda;
 				__u8 mst;
 				__u8 pad04[4];
-				__u8 dpcd[16];
+				__u8 dpcd[DP_RECEIVER_CAP_SIZE];
 			} dp;
 		};
 	} v0;

drivers/gpu/drm/nouveau/nouveau_debugfs.c+10−9

 {
 	struct drm_device *drm = m->private;
 	struct nouveau_debugfs *debugfs = nouveau_debugfs(drm);
-	struct nvif_object *ctrl = &debugfs->ctrl;
+	struct nvif_object *ctrl;
 	struct nvif_control_pstate_info_v0 info = {};
 	int ret, i;
 	if (!debugfs)
 		return -ENODEV;
+	ctrl = &debugfs->ctrl;
 	ret = nvif_mthd(ctrl, NVIF_CONTROL_PSTATE_INFO, &info, sizeof(info));
 	if (ret)
 		return ret;
 		if (state >= 0) {
 			if (info.ustate_ac == state)
-				seq_printf(m, " AC");
+				seq_puts(m, " AC");
 			if (info.ustate_dc == state)
-				seq_printf(m, " DC");
+				seq_puts(m, " DC");
 			if (info.pstate == state)
-				seq_printf(m, " *");
+				seq_puts(m, " *");
 		} else {
 			if (info.ustate_ac < -1)
-				seq_printf(m, " AC");
+				seq_puts(m, " AC");
 			if (info.ustate_dc < -1)
-				seq_printf(m, " DC");
+				seq_puts(m, " DC");
 		}
-		seq_printf(m, "\n");
+		seq_putc(m, '\n');
 	}
 	return 0;
 	struct seq_file *m = file->private_data;
 	struct drm_device *drm = m->private;
 	struct nouveau_debugfs *debugfs = nouveau_debugfs(drm);
-	struct nvif_object *ctrl = &debugfs->ctrl;
 	struct nvif_control_pstate_user_v0 args = { .pwrsrc = -EINVAL };
 	char buf[32] = {}, *tmp, *cur = buf;
 	long value, ret;
 		return ret;
 	}
-	ret = nvif_mthd(ctrl, NVIF_CONTROL_PSTATE_USER, &args, sizeof(args));
+	ret = nvif_mthd(&debugfs->ctrl, NVIF_CONTROL_PSTATE_USER,
+			&args, sizeof(args));
 	pm_runtime_put_autosuspend(drm->dev);
 	if (ret < 0)
 		return ret;

drivers/gpu/drm/nouveau/nouveau_hwmon.c+1−1

@@ -211,7 +211,7 @@ static const struct attribute_group temp1_auto_point_sensor_group = { · 210 unmodified lines
211		211
212	#define N_ATTR_GROUPS 3	212	#define N_ATTR_GROUPS 3
213		213
214	static const struct hwmon_channel_info *nouveau_info[] = {	214	static const struct hwmon_channel_info * const nouveau_info[] = {
215	HWMON_CHANNEL_INFO(chip,	215	HWMON_CHANNEL_INFO(chip,
216	HWMON_C_UPDATE_INTERVAL),	216	HWMON_C_UPDATE_INTERVAL),
217	HWMON_CHANNEL_INFO(temp,	217	HWMON_CHANNEL_INFO(temp,

drivers/gpu/drm/nouveau/nv50_display.h+1−3

@@ -31,7 +31,5 @@ · 30 unmodified lines
31	#include "nouveau_reg.h"	31	#include "nouveau_reg.h"
32		32
33	int nv50_display_create(struct drm_device *);	33	int nv50_display_create(struct drm_device *);
34	void nv50_display_destroy(struct drm_device *);	34
35	int nv50_display_init(struct drm_device *);
36	void nv50_display_fini(struct drm_device *);
37	#endif /* __NV50_DISPLAY_H__ */	35	#endif /* __NV50_DISPLAY_H__ */

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h+2−1

 #define __NVKM_DISP_OUTP_H__
 #include "priv.h"
+#include <drm/display/drm_dp.h>
 #include <subdev/bios.h>
 #include <subdev/bios/dcb.h>
 #include <subdev/bios/dp.h>
 			bool aux_pwr_pu;
 			u8 lttpr[6];
 			u8 lttprs;
-			u8 dpcd[16];
+			u8 dpcd[DP_RECEIVER_CAP_SIZE];
 			struct {
 				int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c+1−1

@@ -146,7 +146,7 @@ nvkm_uoutp_mthd_release(struct nvkm_outp outp, void argv, u32 argc) · 145 unmodified lines
146	}	146	}
147		147
148	static int	148	static int
149	nvkm_uoutp_mthd_acquire_dp(struct nvkm_outp *outp, u8 dpcd[16],	149	nvkm_uoutp_mthd_acquire_dp(struct nvkm_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE],
150	u8 link_nr, u8 link_bw, bool hda, bool mst)	150	u8 link_nr, u8 link_bw, bool hda, bool mst)
151	{	151	{
152	int ret;	152	int ret;

drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.c+1−2

 nvbios_power_budget_header(struct nvkm_bios *bios,
                            struct nvbios_power_budget *budget)
 {
-	struct nvkm_subdev *subdev = &bios->subdev;
 	u8 ver, hdr, cnt, len, cap_entry;
 	u32 header;
 	}
 	if (cap_entry >= cnt && cap_entry != 0xff) {
-		nvkm_warn(subdev,
+		nvkm_warn(&bios->subdev,
 		          "invalid cap_entry in power budget table found\n");
 		budget->cap_entry = 0xff;
 		return -EINVAL;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c+1−1

 		return 0;
 	pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
-	cstate = &pstate->base;
 	if (!pstate)
 		return -ENOMEM;
 	pstate->fanspeed = perfE.fanspeed;
 	pstate->pcie_speed = perfE.pcie_speed;
 	pstate->pcie_width = perfE.pcie_width;
+	cstate = &pstate->base;
 	cstate->voltage = perfE.voltage;
 	cstate->domain[nv_clk_src_core] = perfE.core;
 	cstate->domain[nv_clk_src_shader] = perfE.shader;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c+1−1

@@ -45,7 +45,7 @@ ga102_gsp_nofw(struct nvkm_gsp gsp, int ver, const struct nvkm_gsp_fwif fwif) · 44 unmodified lines
45	return 0;	45	return 0;
46	}	46	}
47		47
48	struct nvkm_gsp_fwif	48	static struct nvkm_gsp_fwif
49	ga102_gsps[] = {	49	ga102_gsps[] = {
50	{ -1, ga102_gsp_nofw, &ga102_gsp },	50	{ -1, ga102_gsp_nofw, &ga102_gsp },
51	{}	51	{}

drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.c+3−4

 int
 nvkm_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8 width)
 {
-	struct nvkm_subdev *subdev = &pci->subdev;
+	struct nvkm_subdev *subdev;
 	enum nvkm_pcie_speed cur_speed, max_speed;
-	struct pci_bus *pbus;
 	int ret;
 	if (!pci || !pci_is_pcie(pci->pdev))
 		return 0;
-	pbus = pci->pdev->bus;
 	if (!pci->func->pcie.set_link)
 		return -ENOSYS;
+	subdev = &pci->subdev;
 	nvkm_trace(subdev, "requested %s\n", nvkm_pcie_speeds[speed]);
 	if (pci->func->pcie.version(pci) < 2) {
 	}
 	cur_speed = pci->func->pcie.cur_speed(pci);
-	max_speed = min(nvkm_pcie_speed(pbus->max_bus_speed),
+	max_speed = min(nvkm_pcie_speed(pci->pdev->bus->max_bus_speed),
 			pci->func->pcie.max_speed(pci));
 	nvkm_trace(subdev, "current speed: %s\n", nvkm_pcie_speeds[cur_speed]);

drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c+1−1

 		return -ENODEV;
 	fan = kzalloc(sizeof(*fan), GFP_KERNEL);
-	therm->fan = &fan->base;
 	if (!fan)
 		return -ENOMEM;
+	therm->fan = &fan->base;
 	fan->base.type = "PWM";
 	fan->base.get = nvkm_fanpwm_get;
 	fan->base.set = nvkm_fanpwm_set;

drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c+1−1

 	}
 	fan = kzalloc(sizeof(*fan), GFP_KERNEL);
-	therm->fan = &fan->base;
 	if (!fan)
 		return -ENOMEM;
+	therm->fan = &fan->base;
 	fan->base.type = "toggle";
 	fan->base.get = nvkm_fantog_get;
 	fan->base.set = nvkm_fantog_set;

drivers/gpu/drm/panel/Kconfig+7−0

@@ -553,6 +553,13 @@ config DRM_PANEL_SAMSUNG_S6D27A1 · 552 unmodified lines
553	This panel can be found in Samsung Galaxy Ace 2	553	This panel can be found in Samsung Galaxy Ace 2
554	GT-I8160 mobile phone.	554	GT-I8160 mobile phone.
555		555
		556	config DRM_PANEL_SAMSUNG_S6D7AA0
		557	tristate "Samsung S6D7AA0 MIPI-DSI video mode panel controller"
		558	depends on OF
		559	depends on BACKLIGHT_CLASS_DEVICE
		560	select DRM_MIPI_DSI
		561	select VIDEOMODE_HELPERS
		562
556	config DRM_PANEL_SAMSUNG_S6E3HA2	563	config DRM_PANEL_SAMSUNG_S6E3HA2
557	tristate "Samsung S6E3HA2 DSI video mode panel"	564	tristate "Samsung S6E3HA2 DSI video mode panel"
558	depends on OF	565	depends on OF

drivers/gpu/drm/panel/Makefile+1−0

@@ -54,6 +54,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_DB7430) += panel-samsung-db7430.o · 53 unmodified lines
54	obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o	54	obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
55	obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D16D0) += panel-samsung-s6d16d0.o	55	obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D16D0) += panel-samsung-s6d16d0.o
56	obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D27A1) += panel-samsung-s6d27a1.o	56	obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D27A1) += panel-samsung-s6d27a1.o
		57	obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0) += panel-samsung-s6d7aa0.o
57	obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o	58	obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o
58	obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o	59	obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o
59	obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0) += panel-samsung-s6e63m0.o	60	obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0) += panel-samsung-s6e63m0.o

drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c+241−163

@@ -36,6 +36,7 @@ struct panel_desc { · 35 unmodified lines
36	const struct panel_init_cmd *init_cmds;	36	const struct panel_init_cmd *init_cmds;
37	unsigned int lanes;	37	unsigned int lanes;
38	bool discharge_on_disable;	38	bool discharge_on_disable;
		39	bool lp11_before_reset;
39	};	40	};
40		41
41	struct boe_panel {	42	struct boe_panel {
@@ -451,11 +452,14 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = { · 409 unmodified lines
451	_INIT_DCS_CMD(0xFF, 0x20),	452	_INIT_DCS_CMD(0xFF, 0x20),
452	_INIT_DCS_CMD(0xFB, 0x01),	453	_INIT_DCS_CMD(0xFB, 0x01),
453	_INIT_DCS_CMD(0x05, 0xD1),	454	_INIT_DCS_CMD(0x05, 0xD1),
454	_INIT_DCS_CMD(0x0D, 0x63),	455	_INIT_DCS_CMD(0x06, 0xC0),
455	_INIT_DCS_CMD(0x07, 0x8C),	456	_INIT_DCS_CMD(0x07, 0x87),
456	_INIT_DCS_CMD(0x08, 0x4B),	457	_INIT_DCS_CMD(0x08, 0x4B),
		458
		459	_INIT_DCS_CMD(0x0D, 0x63),
457	_INIT_DCS_CMD(0x0E, 0x91),	460	_INIT_DCS_CMD(0x0E, 0x91),
458	_INIT_DCS_CMD(0x0F, 0x69),	461	_INIT_DCS_CMD(0x0F, 0x69),
		462	_INIT_DCS_CMD(0x94, 0x00),
459	_INIT_DCS_CMD(0x95, 0xF5),	463	_INIT_DCS_CMD(0x95, 0xF5),
460	_INIT_DCS_CMD(0x96, 0xF5),	464	_INIT_DCS_CMD(0x96, 0xF5),
461	_INIT_DCS_CMD(0x9D, 0x00),	465	_INIT_DCS_CMD(0x9D, 0x00),
@@ -463,98 +467,96 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = { · 1 unmodified line
463	_INIT_DCS_CMD(0x69, 0x98),	467	_INIT_DCS_CMD(0x69, 0x98),
464	_INIT_DCS_CMD(0x75, 0xA2),	468	_INIT_DCS_CMD(0x75, 0xA2),
465	_INIT_DCS_CMD(0x77, 0xB3),	469	_INIT_DCS_CMD(0x77, 0xB3),
		470
		471	_INIT_DCS_CMD(0x58, 0x43),
466	_INIT_DCS_CMD(0xFF, 0x24),	472	_INIT_DCS_CMD(0xFF, 0x24),
467	_INIT_DCS_CMD(0xFB, 0x01),	473	_INIT_DCS_CMD(0xFB, 0x01),
468	_INIT_DCS_CMD(0x91, 0x44),	474	_INIT_DCS_CMD(0x91, 0x44),
469	_INIT_DCS_CMD(0x92, 0x7A),	475	_INIT_DCS_CMD(0x92, 0x4C),
470	_INIT_DCS_CMD(0x93, 0x1A),	476	_INIT_DCS_CMD(0x94, 0x86),
471	_INIT_DCS_CMD(0x94, 0x40),
472	_INIT_DCS_CMD(0x9A, 0x08),
473	_INIT_DCS_CMD(0x60, 0x96),	477	_INIT_DCS_CMD(0x60, 0x96),
474	_INIT_DCS_CMD(0x61, 0xD0),	478	_INIT_DCS_CMD(0x61, 0xD0),
475	_INIT_DCS_CMD(0x63, 0x70),	479	_INIT_DCS_CMD(0x63, 0x70),
476	_INIT_DCS_CMD(0xC2, 0xCF),	480	_INIT_DCS_CMD(0xC2, 0xCA),
477	_INIT_DCS_CMD(0x9B, 0x0F),	481
478	_INIT_DCS_CMD(0x9A, 0x08),
479	_INIT_DCS_CMD(0x00, 0x03),	482	_INIT_DCS_CMD(0x00, 0x03),
480	_INIT_DCS_CMD(0x01, 0x03),	483	_INIT_DCS_CMD(0x01, 0x03),
481	_INIT_DCS_CMD(0x02, 0x03),	484	_INIT_DCS_CMD(0x02, 0x03),
482	_INIT_DCS_CMD(0x03, 0x03),	485	_INIT_DCS_CMD(0x03, 0x29),
483	_INIT_DCS_CMD(0x04, 0x03),	486	_INIT_DCS_CMD(0x04, 0x22),
484	_INIT_DCS_CMD(0x05, 0x03),	487	_INIT_DCS_CMD(0x05, 0x22),
485	_INIT_DCS_CMD(0x06, 0x22),	488	_INIT_DCS_CMD(0x06, 0x0B),
486	_INIT_DCS_CMD(0x07, 0x06),	489	_INIT_DCS_CMD(0x07, 0x1D),
487	_INIT_DCS_CMD(0x08, 0x00),	490	_INIT_DCS_CMD(0x08, 0x1C),
488	_INIT_DCS_CMD(0x09, 0x1D),	491	_INIT_DCS_CMD(0x09, 0x05),
489	_INIT_DCS_CMD(0x0A, 0x1C),	492	_INIT_DCS_CMD(0x0A, 0x08),
490	_INIT_DCS_CMD(0x0B, 0x13),	493	_INIT_DCS_CMD(0x0B, 0x09),
491	_INIT_DCS_CMD(0x0C, 0x12),	494	_INIT_DCS_CMD(0x0C, 0x0A),
492	_INIT_DCS_CMD(0x0D, 0x11),	495	_INIT_DCS_CMD(0x0D, 0x0C),
493	_INIT_DCS_CMD(0x0E, 0x10),	496	_INIT_DCS_CMD(0x0E, 0x0D),
494	_INIT_DCS_CMD(0x0F, 0x0F),	497	_INIT_DCS_CMD(0x0F, 0x0E),
495	_INIT_DCS_CMD(0x10, 0x0E),	498	_INIT_DCS_CMD(0x10, 0x0F),
496	_INIT_DCS_CMD(0x11, 0x0D),	499	_INIT_DCS_CMD(0x11, 0x10),
497	_INIT_DCS_CMD(0x12, 0x0C),	500	_INIT_DCS_CMD(0x12, 0x11),
498	_INIT_DCS_CMD(0x13, 0x04),	501	_INIT_DCS_CMD(0x13, 0x04),
499	_INIT_DCS_CMD(0x14, 0x03),	502	_INIT_DCS_CMD(0x14, 0x00),
500	_INIT_DCS_CMD(0x15, 0x03),	503	_INIT_DCS_CMD(0x15, 0x03),
501	_INIT_DCS_CMD(0x16, 0x03),	504	_INIT_DCS_CMD(0x16, 0x03),
502	_INIT_DCS_CMD(0x17, 0x03),	505	_INIT_DCS_CMD(0x17, 0x03),
503	_INIT_DCS_CMD(0x18, 0x03),	506	_INIT_DCS_CMD(0x18, 0x03),
504	_INIT_DCS_CMD(0x19, 0x03),	507	_INIT_DCS_CMD(0x19, 0x29),
505	_INIT_DCS_CMD(0x1A, 0x03),	508	_INIT_DCS_CMD(0x1A, 0x22),
506	_INIT_DCS_CMD(0x1B, 0x03),	509	_INIT_DCS_CMD(0x1B, 0x22),
507	_INIT_DCS_CMD(0x1C, 0x22),	510	_INIT_DCS_CMD(0x1C, 0x0B),
508	_INIT_DCS_CMD(0x1D, 0x06),	511	_INIT_DCS_CMD(0x1D, 0x1D),
509	_INIT_DCS_CMD(0x1E, 0x00),	512	_INIT_DCS_CMD(0x1E, 0x1C),
510	_INIT_DCS_CMD(0x1F, 0x1D),	513	_INIT_DCS_CMD(0x1F, 0x05),
511	_INIT_DCS_CMD(0x20, 0x1C),	514	_INIT_DCS_CMD(0x20, 0x08),
512	_INIT_DCS_CMD(0x21, 0x13),	515	_INIT_DCS_CMD(0x21, 0x09),
513	_INIT_DCS_CMD(0x22, 0x12),	516	_INIT_DCS_CMD(0x22, 0x0A),
514	_INIT_DCS_CMD(0x23, 0x11),	517	_INIT_DCS_CMD(0x23, 0x0C),
515	_INIT_DCS_CMD(0x24, 0x10),	518	_INIT_DCS_CMD(0x24, 0x0D),
516	_INIT_DCS_CMD(0x25, 0x0F),	519	_INIT_DCS_CMD(0x25, 0x0E),
517	_INIT_DCS_CMD(0x26, 0x0E),	520	_INIT_DCS_CMD(0x26, 0x0F),
518	_INIT_DCS_CMD(0x27, 0x0D),	521	_INIT_DCS_CMD(0x27, 0x10),
519	_INIT_DCS_CMD(0x28, 0x0C),	522	_INIT_DCS_CMD(0x28, 0x11),
520	_INIT_DCS_CMD(0x29, 0x04),	523	_INIT_DCS_CMD(0x29, 0x04),
521	_INIT_DCS_CMD(0x2A, 0x03),	524	_INIT_DCS_CMD(0x2A, 0x00),
522	_INIT_DCS_CMD(0x2B, 0x03),	525	_INIT_DCS_CMD(0x2B, 0x03),
523		526
524	_INIT_DCS_CMD(0x2F, 0x05),	527	_INIT_DCS_CMD(0x2F, 0x0A),
525	_INIT_DCS_CMD(0x30, 0x32),	528	_INIT_DCS_CMD(0x30, 0x35),
526	_INIT_DCS_CMD(0x31, 0x43),	529	_INIT_DCS_CMD(0x37, 0xA7),
527	_INIT_DCS_CMD(0x33, 0x05),
528	_INIT_DCS_CMD(0x34, 0x32),
529	_INIT_DCS_CMD(0x35, 0x43),
530	_INIT_DCS_CMD(0x37, 0x44),
531	_INIT_DCS_CMD(0x38, 0x40),
532	_INIT_DCS_CMD(0x39, 0x00),	530	_INIT_DCS_CMD(0x39, 0x00),
533	_INIT_DCS_CMD(0x3A, 0x18),	531	_INIT_DCS_CMD(0x3A, 0x46),
534	_INIT_DCS_CMD(0x3B, 0x00),	532	_INIT_DCS_CMD(0x3B, 0x32),
535	_INIT_DCS_CMD(0x3D, 0x93),	533	_INIT_DCS_CMD(0x3D, 0x12),
536	_INIT_DCS_CMD(0xAB, 0x44),	534
537	_INIT_DCS_CMD(0xAC, 0x40),	535	_INIT_DCS_CMD(0x3F, 0x33),
		536	_INIT_DCS_CMD(0x40, 0x31),
		537	_INIT_DCS_CMD(0x41, 0x40),
		538	_INIT_DCS_CMD(0x42, 0x42),
		539	_INIT_DCS_CMD(0x47, 0x77),
		540	_INIT_DCS_CMD(0x48, 0x77),
		541	_INIT_DCS_CMD(0x4A, 0x45),
		542	_INIT_DCS_CMD(0x4B, 0x45),
		543	_INIT_DCS_CMD(0x4C, 0x14),
538		544
539	_INIT_DCS_CMD(0x4D, 0x21),	545	_INIT_DCS_CMD(0x4D, 0x21),
540	_INIT_DCS_CMD(0x4E, 0x43),	546	_INIT_DCS_CMD(0x4E, 0x43),
541	_INIT_DCS_CMD(0x4F, 0x65),	547	_INIT_DCS_CMD(0x4F, 0x65),
542	_INIT_DCS_CMD(0x50, 0x87),	548	_INIT_DCS_CMD(0x55, 0x06),
543	_INIT_DCS_CMD(0x51, 0x78),	549	_INIT_DCS_CMD(0x56, 0x06),
544	_INIT_DCS_CMD(0x52, 0x56),
545	_INIT_DCS_CMD(0x53, 0x34),
546	_INIT_DCS_CMD(0x54, 0x21),
547	_INIT_DCS_CMD(0x55, 0x83),
548	_INIT_DCS_CMD(0x56, 0x08),
549	_INIT_DCS_CMD(0x58, 0x21),	550	_INIT_DCS_CMD(0x58, 0x21),
550	_INIT_DCS_CMD(0x59, 0x40),	551	_INIT_DCS_CMD(0x59, 0x70),
551	_INIT_DCS_CMD(0x5A, 0x00),	552	_INIT_DCS_CMD(0x5A, 0x46),
552	_INIT_DCS_CMD(0x5B, 0x2C),	553	_INIT_DCS_CMD(0x5B, 0x32),
553	_INIT_DCS_CMD(0x5E, 0x00, 0x10),	554	_INIT_DCS_CMD(0x5C, 0x88),
		555	_INIT_DCS_CMD(0x5E, 0x00, 0x00),
554	_INIT_DCS_CMD(0x5F, 0x00),	556	_INIT_DCS_CMD(0x5F, 0x00),
555		557
556	_INIT_DCS_CMD(0x7A, 0x00),	558	_INIT_DCS_CMD(0x7A, 0xFF),
557	_INIT_DCS_CMD(0x7B, 0x00),	559	_INIT_DCS_CMD(0x7B, 0xFF),
558	_INIT_DCS_CMD(0x7C, 0x00),	560	_INIT_DCS_CMD(0x7C, 0x00),
559	_INIT_DCS_CMD(0x7D, 0x00),	561	_INIT_DCS_CMD(0x7D, 0x00),
560	_INIT_DCS_CMD(0x7E, 0x20),	562	_INIT_DCS_CMD(0x7E, 0x20),
@@ -564,152 +566,183 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = { · 3 unmodified lines
564	_INIT_DCS_CMD(0x82, 0x08),	566	_INIT_DCS_CMD(0x82, 0x08),
565	_INIT_DCS_CMD(0x97, 0x02),	567	_INIT_DCS_CMD(0x97, 0x02),
566	_INIT_DCS_CMD(0xC5, 0x10),	568	_INIT_DCS_CMD(0xC5, 0x10),
		569
		570	_INIT_DCS_CMD(0xD7, 0x55),
		571	_INIT_DCS_CMD(0xD8, 0x55),
		572	_INIT_DCS_CMD(0xD9, 0x23),
567	_INIT_DCS_CMD(0xDA, 0x05),	573	_INIT_DCS_CMD(0xDA, 0x05),
568	_INIT_DCS_CMD(0xDB, 0x01),	574	_INIT_DCS_CMD(0xDB, 0x01),
569	_INIT_DCS_CMD(0xDC, 0x7A),	575	_INIT_DCS_CMD(0xDC, 0x65),
570	_INIT_DCS_CMD(0xDD, 0x55),	576	_INIT_DCS_CMD(0xDD, 0x55),
571	_INIT_DCS_CMD(0xDE, 0x27),	577	_INIT_DCS_CMD(0xDE, 0x27),
572	_INIT_DCS_CMD(0xDF, 0x01),	578	_INIT_DCS_CMD(0xDF, 0x01),
573	_INIT_DCS_CMD(0xE0, 0x7A),	579	_INIT_DCS_CMD(0xE0, 0x65),
574	_INIT_DCS_CMD(0xE1, 0x01),	580	_INIT_DCS_CMD(0xE1, 0x01),
575	_INIT_DCS_CMD(0xE2, 0x7A),	581	_INIT_DCS_CMD(0xE2, 0x65),
576	_INIT_DCS_CMD(0xE3, 0x01),	582	_INIT_DCS_CMD(0xE3, 0x01),
577	_INIT_DCS_CMD(0xE4, 0x7A),	583	_INIT_DCS_CMD(0xE4, 0x65),
578	_INIT_DCS_CMD(0xE5, 0x01),	584	_INIT_DCS_CMD(0xE5, 0x01),
579	_INIT_DCS_CMD(0xE6, 0x7A),	585	_INIT_DCS_CMD(0xE6, 0x65),
580	_INIT_DCS_CMD(0xE7, 0x00),	586	_INIT_DCS_CMD(0xE7, 0x00),
581	_INIT_DCS_CMD(0xE8, 0x00),	587	_INIT_DCS_CMD(0xE8, 0x00),
582	_INIT_DCS_CMD(0xE9, 0x01),	588	_INIT_DCS_CMD(0xE9, 0x01),
583	_INIT_DCS_CMD(0xEA, 0x7A),	589	_INIT_DCS_CMD(0xEA, 0x65),
584	_INIT_DCS_CMD(0xEB, 0x01),	590	_INIT_DCS_CMD(0xEB, 0x01),
585	_INIT_DCS_CMD(0xEE, 0x7A),	591	_INIT_DCS_CMD(0xEE, 0x65),
586	_INIT_DCS_CMD(0xEF, 0x01),	592	_INIT_DCS_CMD(0xEF, 0x01),
587	_INIT_DCS_CMD(0xF0, 0x7A),	593	_INIT_DCS_CMD(0xF0, 0x65),
588
589	_INIT_DCS_CMD(0xB6, 0x05, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x00, 0x00),	594	_INIT_DCS_CMD(0xB6, 0x05, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x00, 0x00),
		595
590	_INIT_DCS_CMD(0xFF, 0x25),	596	_INIT_DCS_CMD(0xFF, 0x25),
591	_INIT_DCS_CMD(0xFB, 0x01),
592		597
		598	_INIT_DCS_CMD(0xFB, 0x01),
593	_INIT_DCS_CMD(0x05, 0x00),	599	_INIT_DCS_CMD(0x05, 0x00),
594
595	_INIT_DCS_CMD(0x13, 0x02),
596	_INIT_DCS_CMD(0x14, 0xDF),
597	_INIT_DCS_CMD(0xF1, 0x10),	600	_INIT_DCS_CMD(0xF1, 0x10),
		601
598	_INIT_DCS_CMD(0x1E, 0x00),	602	_INIT_DCS_CMD(0x1E, 0x00),
599	_INIT_DCS_CMD(0x1F, 0x00),	603	_INIT_DCS_CMD(0x1F, 0x46),
600	_INIT_DCS_CMD(0x20, 0x2C),	604	_INIT_DCS_CMD(0x20, 0x32),
		605
601	_INIT_DCS_CMD(0x25, 0x00),	606	_INIT_DCS_CMD(0x25, 0x00),
602	_INIT_DCS_CMD(0x26, 0x00),	607	_INIT_DCS_CMD(0x26, 0x46),
603	_INIT_DCS_CMD(0x27, 0x2C),	608	_INIT_DCS_CMD(0x27, 0x32),
		609
604	_INIT_DCS_CMD(0x3F, 0x80),	610	_INIT_DCS_CMD(0x3F, 0x80),
605	_INIT_DCS_CMD(0x40, 0x00),	611	_INIT_DCS_CMD(0x40, 0x00),
606	_INIT_DCS_CMD(0x43, 0x00),	612	_INIT_DCS_CMD(0x43, 0x00),
607		613
608	_INIT_DCS_CMD(0x44, 0x18),	614	_INIT_DCS_CMD(0x44, 0x46),
609	_INIT_DCS_CMD(0x45, 0x00),	615	_INIT_DCS_CMD(0x45, 0x46),
		616
		617	_INIT_DCS_CMD(0x48, 0x46),
		618	_INIT_DCS_CMD(0x49, 0x32),
610		619
611	_INIT_DCS_CMD(0x48, 0x00),
612	_INIT_DCS_CMD(0x49, 0x2C),
613	_INIT_DCS_CMD(0x5B, 0x80),	620	_INIT_DCS_CMD(0x5B, 0x80),
		621
614	_INIT_DCS_CMD(0x5C, 0x00),	622	_INIT_DCS_CMD(0x5C, 0x00),
615	_INIT_DCS_CMD(0x5D, 0x00),	623	_INIT_DCS_CMD(0x5D, 0x46),
616	_INIT_DCS_CMD(0x5E, 0x00),	624	_INIT_DCS_CMD(0x5E, 0x32),
617	_INIT_DCS_CMD(0x61, 0x00),	625
618	_INIT_DCS_CMD(0x62, 0x2C),	626	_INIT_DCS_CMD(0x5F, 0x46),
619	_INIT_DCS_CMD(0x68, 0x10),	627	_INIT_DCS_CMD(0x60, 0x32),
		628
		629	_INIT_DCS_CMD(0x61, 0x46),
		630	_INIT_DCS_CMD(0x62, 0x32),
		631	_INIT_DCS_CMD(0x68, 0x0C),
		632
		633	_INIT_DCS_CMD(0x6C, 0x0D),
		634	_INIT_DCS_CMD(0x6E, 0x0D),
		635	_INIT_DCS_CMD(0x78, 0x00),
		636	_INIT_DCS_CMD(0x79, 0xC5),
		637	_INIT_DCS_CMD(0x7A, 0x0C),
		638	_INIT_DCS_CMD(0x7B, 0xB0),
		639
620	_INIT_DCS_CMD(0xFF, 0x26),	640	_INIT_DCS_CMD(0xFF, 0x26),
621	_INIT_DCS_CMD(0xFB, 0x01),	641	_INIT_DCS_CMD(0xFB, 0x01),
622		642
623	_INIT_DCS_CMD(0x00, 0xA1),	643	_INIT_DCS_CMD(0x00, 0xA1),
624	_INIT_DCS_CMD(0x02, 0x31),	644	_INIT_DCS_CMD(0x02, 0x31),
625	_INIT_DCS_CMD(0x0A, 0xF2),	645	_INIT_DCS_CMD(0x0A, 0xF4),
626	_INIT_DCS_CMD(0x04, 0x28),	646	_INIT_DCS_CMD(0x04, 0x50),
627	_INIT_DCS_CMD(0x06, 0x30),	647	_INIT_DCS_CMD(0x06, 0x30),
628	_INIT_DCS_CMD(0x0C, 0x16),	648	_INIT_DCS_CMD(0x0C, 0x16),
629	_INIT_DCS_CMD(0x0D, 0x0D),	649	_INIT_DCS_CMD(0x0D, 0x0D),
630	_INIT_DCS_CMD(0x0F, 0x00),	650	_INIT_DCS_CMD(0x0F, 0x00),
631	_INIT_DCS_CMD(0x11, 0x00),	651	_INIT_DCS_CMD(0x11, 0x00),
632	_INIT_DCS_CMD(0x12, 0x50),	652	_INIT_DCS_CMD(0x12, 0x50),
633	_INIT_DCS_CMD(0x13, 0x56),	653	_INIT_DCS_CMD(0x13, 0x40),
634	_INIT_DCS_CMD(0x14, 0x57),	654	_INIT_DCS_CMD(0x14, 0x58),
635	_INIT_DCS_CMD(0x15, 0x00),	655	_INIT_DCS_CMD(0x15, 0x00),
636	_INIT_DCS_CMD(0x16, 0x10),	656	_INIT_DCS_CMD(0x16, 0x10),
637	_INIT_DCS_CMD(0x17, 0xA0),	657	_INIT_DCS_CMD(0x17, 0xA0),
638	_INIT_DCS_CMD(0x18, 0x86),	658	_INIT_DCS_CMD(0x18, 0x86),
639	_INIT_DCS_CMD(0x22, 0x00),	659	_INIT_DCS_CMD(0x22, 0x00),
640	_INIT_DCS_CMD(0x23, 0x00),	660	_INIT_DCS_CMD(0x23, 0x00),
641	_INIT_DCS_CMD(0x19, 0x0D),	661
642	_INIT_DCS_CMD(0x1A, 0x7F),	662	_INIT_DCS_CMD(0x19, 0x0E),
643	_INIT_DCS_CMD(0x1B, 0x0C),	663	_INIT_DCS_CMD(0x1A, 0x31),
644	_INIT_DCS_CMD(0x1C, 0xBF),	664	_INIT_DCS_CMD(0x1B, 0x0D),
645	_INIT_DCS_CMD(0x2A, 0x0D),	665	_INIT_DCS_CMD(0x1C, 0x29),
646	_INIT_DCS_CMD(0x2B, 0x7F),	666	_INIT_DCS_CMD(0x2A, 0x0E),
647	_INIT_DCS_CMD(0x20, 0x00),	667	_INIT_DCS_CMD(0x2B, 0x31),
648		668
649	_INIT_DCS_CMD(0x1D, 0x00),	669	_INIT_DCS_CMD(0x1D, 0x00),
650	_INIT_DCS_CMD(0x1E, 0x78),	670	_INIT_DCS_CMD(0x1E, 0x62),
651	_INIT_DCS_CMD(0x1F, 0x78),	671	_INIT_DCS_CMD(0x1F, 0x62),
652		672
653	_INIT_DCS_CMD(0x2F, 0x03),	673	_INIT_DCS_CMD(0x2F, 0x06),
654	_INIT_DCS_CMD(0x30, 0x78),	674	_INIT_DCS_CMD(0x30, 0x62),
655	_INIT_DCS_CMD(0x33, 0x78),	675	_INIT_DCS_CMD(0x31, 0x06),
656	_INIT_DCS_CMD(0x34, 0x66),	676	_INIT_DCS_CMD(0x32, 0x7F),
657	_INIT_DCS_CMD(0x35, 0x11),	677	_INIT_DCS_CMD(0x33, 0x11),
		678	_INIT_DCS_CMD(0x34, 0x89),
		679	_INIT_DCS_CMD(0x35, 0x67),
658		680
659	_INIT_DCS_CMD(0x39, 0x10),	681	_INIT_DCS_CMD(0x39, 0x0B),
660	_INIT_DCS_CMD(0x3A, 0x78),	682	_INIT_DCS_CMD(0x3A, 0x62),
661	_INIT_DCS_CMD(0x3B, 0x06),	683	_INIT_DCS_CMD(0x3B, 0x06),
662		684
663	_INIT_DCS_CMD(0xC8, 0x04),	685	_INIT_DCS_CMD(0xC8, 0x04),
664	_INIT_DCS_CMD(0xC9, 0x84),	686	_INIT_DCS_CMD(0xC9, 0x89),
665	_INIT_DCS_CMD(0xCA, 0x4E),	687	_INIT_DCS_CMD(0xCA, 0x4E),
666	_INIT_DCS_CMD(0xCB, 0x00),	688	_INIT_DCS_CMD(0xCB, 0x00),
		689	_INIT_DCS_CMD(0xA9, 0x3F),
		690	_INIT_DCS_CMD(0xAA, 0x3E),
		691	_INIT_DCS_CMD(0xAB, 0x3D),
		692	_INIT_DCS_CMD(0xAC, 0x3C),
		693	_INIT_DCS_CMD(0xAD, 0x3B),
		694	_INIT_DCS_CMD(0xAE, 0x3A),
		695	_INIT_DCS_CMD(0xAF, 0x39),
		696	_INIT_DCS_CMD(0xB0, 0x38),
667		697
668	_INIT_DCS_CMD(0xA9, 0x50),
669	_INIT_DCS_CMD(0xAA, 0x4F),
670	_INIT_DCS_CMD(0xAB, 0x4D),
671	_INIT_DCS_CMD(0xAC, 0x4A),
672	_INIT_DCS_CMD(0xAD, 0x48),
673	_INIT_DCS_CMD(0xAE, 0x46),
674	_INIT_DCS_CMD(0xFF, 0x27),	698	_INIT_DCS_CMD(0xFF, 0x27),
675	_INIT_DCS_CMD(0xFB, 0x01),	699	_INIT_DCS_CMD(0xFB, 0x01),
		700
		701	_INIT_DCS_CMD(0xD0, 0x11),
		702	_INIT_DCS_CMD(0xD1, 0x54),
		703	_INIT_DCS_CMD(0xDE, 0x43),
		704	_INIT_DCS_CMD(0xDF, 0x02),
		705
676	_INIT_DCS_CMD(0xC0, 0x18),	706	_INIT_DCS_CMD(0xC0, 0x18),
677	_INIT_DCS_CMD(0xC1, 0x00),	707	_INIT_DCS_CMD(0xC1, 0x00),
678	_INIT_DCS_CMD(0xC2, 0x00),	708	_INIT_DCS_CMD(0xC2, 0x00),
		709	_INIT_DCS_CMD(0x00, 0x00),
		710	_INIT_DCS_CMD(0xC3, 0x00),
679	_INIT_DCS_CMD(0x56, 0x06),	711	_INIT_DCS_CMD(0x56, 0x06),
		712
680	_INIT_DCS_CMD(0x58, 0x80),	713	_INIT_DCS_CMD(0x58, 0x80),
681	_INIT_DCS_CMD(0x59, 0x75),	714	_INIT_DCS_CMD(0x59, 0x78),
682	_INIT_DCS_CMD(0x5A, 0x00),	715	_INIT_DCS_CMD(0x5A, 0x00),
683	_INIT_DCS_CMD(0x5B, 0x02),	716	_INIT_DCS_CMD(0x5B, 0x18),
684	_INIT_DCS_CMD(0x5C, 0x00),	717	_INIT_DCS_CMD(0x5C, 0x00),
685	_INIT_DCS_CMD(0x5D, 0x00),	718	_INIT_DCS_CMD(0x5D, 0x01),
686	_INIT_DCS_CMD(0x5E, 0x20),	719	_INIT_DCS_CMD(0x5E, 0x20),
687	_INIT_DCS_CMD(0x5F, 0x10),	720	_INIT_DCS_CMD(0x5F, 0x10),
688	_INIT_DCS_CMD(0x60, 0x00),	721	_INIT_DCS_CMD(0x60, 0x00),
689	_INIT_DCS_CMD(0x61, 0x2E),	722	_INIT_DCS_CMD(0x61, 0x1C),
690	_INIT_DCS_CMD(0x62, 0x00),	723	_INIT_DCS_CMD(0x62, 0x00),
691	_INIT_DCS_CMD(0x63, 0x01),	724	_INIT_DCS_CMD(0x63, 0x01),
692	_INIT_DCS_CMD(0x64, 0x43),	725	_INIT_DCS_CMD(0x64, 0x44),
693	_INIT_DCS_CMD(0x65, 0x2D),	726	_INIT_DCS_CMD(0x65, 0x1B),
694	_INIT_DCS_CMD(0x66, 0x00),	727	_INIT_DCS_CMD(0x66, 0x00),
695	_INIT_DCS_CMD(0x67, 0x01),	728	_INIT_DCS_CMD(0x67, 0x01),
696	_INIT_DCS_CMD(0x68, 0x43),	729	_INIT_DCS_CMD(0x68, 0x44),
		730
697	_INIT_DCS_CMD(0x98, 0x01),	731	_INIT_DCS_CMD(0x98, 0x01),
698	_INIT_DCS_CMD(0xB4, 0x03),	732	_INIT_DCS_CMD(0xB4, 0x03),
699	_INIT_DCS_CMD(0x9B, 0xBD),	733	_INIT_DCS_CMD(0x9B, 0xBE),
700	_INIT_DCS_CMD(0xA0, 0x90),	734
701	_INIT_DCS_CMD(0xAB, 0x1B),	735	_INIT_DCS_CMD(0xAB, 0x14),
702	_INIT_DCS_CMD(0xBC, 0x0C),	736	_INIT_DCS_CMD(0xBC, 0x08),
703	_INIT_DCS_CMD(0xBD, 0x28),	737	_INIT_DCS_CMD(0xBD, 0x28),
704		738
705	_INIT_DCS_CMD(0xFF, 0x2A),	739	_INIT_DCS_CMD(0xFF, 0x2A),
706	_INIT_DCS_CMD(0xFB, 0x01),	740	_INIT_DCS_CMD(0xFB, 0x01),
707
708	_INIT_DCS_CMD(0x22, 0x2F),	741	_INIT_DCS_CMD(0x22, 0x2F),
709	_INIT_DCS_CMD(0x23, 0x08),	742	_INIT_DCS_CMD(0x23, 0x08),
710		743
711	_INIT_DCS_CMD(0x24, 0x00),	744	_INIT_DCS_CMD(0x24, 0x00),
712	_INIT_DCS_CMD(0x25, 0x65),	745	_INIT_DCS_CMD(0x25, 0x62),
713	_INIT_DCS_CMD(0x26, 0xF8),	746	_INIT_DCS_CMD(0x26, 0xF8),
714	_INIT_DCS_CMD(0x27, 0x00),	747	_INIT_DCS_CMD(0x27, 0x00),
715	_INIT_DCS_CMD(0x28, 0x1A),	748	_INIT_DCS_CMD(0x28, 0x1A),
@@ -719,18 +752,29 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = { · 3 unmodified lines
719	_INIT_DCS_CMD(0x2D, 0x1A),	752	_INIT_DCS_CMD(0x2D, 0x1A),
720		753
721	_INIT_DCS_CMD(0x64, 0x96),	754	_INIT_DCS_CMD(0x64, 0x96),
722	_INIT_DCS_CMD(0x65, 0x00),	755	_INIT_DCS_CMD(0x65, 0x10),
723	_INIT_DCS_CMD(0x66, 0x00),	756	_INIT_DCS_CMD(0x66, 0x00),
		757	_INIT_DCS_CMD(0x67, 0x96),
		758	_INIT_DCS_CMD(0x68, 0x10),
		759	_INIT_DCS_CMD(0x69, 0x00),
724	_INIT_DCS_CMD(0x6A, 0x96),	760	_INIT_DCS_CMD(0x6A, 0x96),
725	_INIT_DCS_CMD(0x6B, 0x00),	761	_INIT_DCS_CMD(0x6B, 0x10),
726	_INIT_DCS_CMD(0x6C, 0x00),	762	_INIT_DCS_CMD(0x6C, 0x00),
727	_INIT_DCS_CMD(0x70, 0x92),	763	_INIT_DCS_CMD(0x70, 0x92),
728	_INIT_DCS_CMD(0x71, 0x00),	764	_INIT_DCS_CMD(0x71, 0x10),
729	_INIT_DCS_CMD(0x72, 0x00),	765	_INIT_DCS_CMD(0x72, 0x00),
730	_INIT_DCS_CMD(0xA2, 0x33),	766	_INIT_DCS_CMD(0x79, 0x96),
		767	_INIT_DCS_CMD(0x7A, 0x10),
		768	_INIT_DCS_CMD(0x88, 0x96),
		769	_INIT_DCS_CMD(0x89, 0x10),
		770
		771	_INIT_DCS_CMD(0xA2, 0x3F),
731	_INIT_DCS_CMD(0xA3, 0x30),	772	_INIT_DCS_CMD(0xA3, 0x30),
732	_INIT_DCS_CMD(0xA4, 0xC0),	773	_INIT_DCS_CMD(0xA4, 0xC0),
		774	_INIT_DCS_CMD(0xA5, 0x03),
		775
733	_INIT_DCS_CMD(0xE8, 0x00),	776	_INIT_DCS_CMD(0xE8, 0x00),
		777
734	_INIT_DCS_CMD(0x97, 0x3C),	778	_INIT_DCS_CMD(0x97, 0x3C),
735	_INIT_DCS_CMD(0x98, 0x02),	779	_INIT_DCS_CMD(0x98, 0x02),
736	_INIT_DCS_CMD(0x99, 0x95),	780	_INIT_DCS_CMD(0x99, 0x95),
@@ -739,38 +783,68 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = { · 2 unmodified lines
739	_INIT_DCS_CMD(0x9C, 0x0B),	783	_INIT_DCS_CMD(0x9C, 0x0B),
740	_INIT_DCS_CMD(0x9D, 0x0A),	784	_INIT_DCS_CMD(0x9D, 0x0A),
741	_INIT_DCS_CMD(0x9E, 0x90),	785	_INIT_DCS_CMD(0x9E, 0x90),
		786
		787	_INIT_DCS_CMD(0xFF, 0x25),
		788	_INIT_DCS_CMD(0x13, 0x02),
		789	_INIT_DCS_CMD(0x14, 0xD7),
		790	_INIT_DCS_CMD(0xDB, 0x02),
		791	_INIT_DCS_CMD(0xDC, 0xD7),
		792	_INIT_DCS_CMD(0x17, 0xCF),
		793	_INIT_DCS_CMD(0x19, 0x0F),
		794	_INIT_DCS_CMD(0x1B, 0x5B),
		795
		796	_INIT_DCS_CMD(0xFF, 0x20),
		797
		798	_INIT_DCS_CMD(0xB0, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x24, 0x00, 0x38, 0x00, 0x4C, 0x00, 0x5E, 0x00, 0x6F, 0x00, 0x7E),
		799	_INIT_DCS_CMD(0xB1, 0x00, 0x8C, 0x00, 0xBE, 0x00, 0xE5, 0x01, 0x27, 0x01, 0x58, 0x01, 0xA8, 0x01, 0xE8, 0x01, 0xEA),
		800	_INIT_DCS_CMD(0xB2, 0x02, 0x28, 0x02, 0x71, 0x02, 0x9E, 0x02, 0xDA, 0x03, 0x00, 0x03, 0x31, 0x03, 0x40, 0x03, 0x51),
		801	_INIT_DCS_CMD(0xB3, 0x03, 0x62, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9C, 0x03, 0xAA, 0x03, 0xB2),
		802
		803	_INIT_DCS_CMD(0xB4, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x27, 0x00, 0x3D, 0x00, 0x52, 0x00, 0x64, 0x00, 0x75, 0x00, 0x84),
		804	_INIT_DCS_CMD(0xB5, 0x00, 0x93, 0x00, 0xC5, 0x00, 0xEC, 0x01, 0x2C, 0x01, 0x5D, 0x01, 0xAC, 0x01, 0xEC, 0x01, 0xEE),
		805	_INIT_DCS_CMD(0xB6, 0x02, 0x2B, 0x02, 0x73, 0x02, 0xA0, 0x02, 0xDB, 0x03, 0x01, 0x03, 0x31, 0x03, 0x41, 0x03, 0x51),
		806	_INIT_DCS_CMD(0xB7, 0x03, 0x63, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9C, 0x03, 0xAA, 0x03, 0xB2),
		807
		808	_INIT_DCS_CMD(0xB8, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x2A, 0x00, 0x40, 0x00, 0x56, 0x00, 0x68, 0x00, 0x7A, 0x00, 0x89),
		809	_INIT_DCS_CMD(0xB9, 0x00, 0x98, 0x00, 0xC9, 0x00, 0xF1, 0x01, 0x30, 0x01, 0x61, 0x01, 0xB0, 0x01, 0xEF, 0x01, 0xF1),
		810	_INIT_DCS_CMD(0xBA, 0x02, 0x2E, 0x02, 0x76, 0x02, 0xA3, 0x02, 0xDD, 0x03, 0x02, 0x03, 0x32, 0x03, 0x42, 0x03, 0x53),
		811	_INIT_DCS_CMD(0xBB, 0x03, 0x66, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9C, 0x03, 0xAA, 0x03, 0xB2),
		812
		813	_INIT_DCS_CMD(0xFF, 0x21),
		814	_INIT_DCS_CMD(0xB0, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x24, 0x00, 0x38, 0x00, 0x4C, 0x00, 0x5E, 0x00, 0x6F, 0x00, 0x7E),
		815	_INIT_DCS_CMD(0xB1, 0x00, 0x8C, 0x00, 0xBE, 0x00, 0xE5, 0x01, 0x27, 0x01, 0x58, 0x01, 0xA8, 0x01, 0xE8, 0x01, 0xEA),
		816	_INIT_DCS_CMD(0xB2, 0x02, 0x28, 0x02, 0x71, 0x02, 0x9E, 0x02, 0xDA, 0x03, 0x00, 0x03, 0x31, 0x03, 0x40, 0x03, 0x51),
		817	_INIT_DCS_CMD(0xB3, 0x03, 0x62, 0x03, 0x77, 0x03, 0x90, 0x03, 0xAC, 0x03, 0xCA, 0x03, 0xDA),
		818
		819	_INIT_DCS_CMD(0xB4, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x27, 0x00, 0x3D, 0x00, 0x52, 0x00, 0x64, 0x00, 0x75, 0x00, 0x84),
		820	_INIT_DCS_CMD(0xB5, 0x00, 0x93, 0x00, 0xC5, 0x00, 0xEC, 0x01, 0x2C, 0x01, 0x5D, 0x01, 0xAC, 0x01, 0xEC, 0x01, 0xEE),
		821	_INIT_DCS_CMD(0xB6, 0x02, 0x2B, 0x02, 0x73, 0x02, 0xA0, 0x02, 0xDB, 0x03, 0x01, 0x03, 0x31, 0x03, 0x41, 0x03, 0x51),
		822	_INIT_DCS_CMD(0xB7, 0x03, 0x63, 0x03, 0x77, 0x03, 0x90, 0x03, 0xAC, 0x03, 0xCA, 0x03, 0xDA),
		823
		824	_INIT_DCS_CMD(0xB8, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x2A, 0x00, 0x40, 0x00, 0x56, 0x00, 0x68, 0x00, 0x7A, 0x00, 0x89),
		825	_INIT_DCS_CMD(0xB9, 0x00, 0x98, 0x00, 0xC9, 0x00, 0xF1, 0x01, 0x30, 0x01, 0x61, 0x01, 0xB0, 0x01, 0xEF, 0x01, 0xF1),
		826	_INIT_DCS_CMD(0xBA, 0x02, 0x2E, 0x02, 0x76, 0x02, 0xA3, 0x02, 0xDD, 0x03, 0x02, 0x03, 0x32, 0x03, 0x42, 0x03, 0x53),
		827	_INIT_DCS_CMD(0xBB, 0x03, 0x66, 0x03, 0x77, 0x03, 0x90, 0x03, 0xAC, 0x03, 0xCA, 0x03, 0xDA),
		828
742	_INIT_DCS_CMD(0xFF, 0xF0),	829	_INIT_DCS_CMD(0xFF, 0xF0),
743	_INIT_DCS_CMD(0xFB, 0x01),	830	_INIT_DCS_CMD(0xFB, 0x01),
744	_INIT_DCS_CMD(0x3A, 0x08),	831	_INIT_DCS_CMD(0x3A, 0x08),
745	_INIT_DCS_CMD(0xFF, 0xD0),	832
746	_INIT_DCS_CMD(0xFB, 0x01),
747	_INIT_DCS_CMD(0x00, 0x33),
748	_INIT_DCS_CMD(0x08, 0x01),
749	_INIT_DCS_CMD(0x09, 0xBF),
750	_INIT_DCS_CMD(0x2F, 0x33),
751	_INIT_DCS_CMD(0xFF, 0x23),
752	_INIT_DCS_CMD(0xFB, 0x01),
753	_INIT_DCS_CMD(0x00, 0x80),
754	_INIT_DCS_CMD(0x07, 0x00),
755	_INIT_DCS_CMD(0xFF, 0x20),
756	_INIT_DCS_CMD(0xFB, 0x01),
757	_INIT_DCS_CMD(0x30, 0x00),
758	_INIT_DCS_CMD(0xFF, 0x24),
759	_INIT_DCS_CMD(0x5C, 0x88),
760	_INIT_DCS_CMD(0x5D, 0x08),
761	_INIT_DCS_CMD(0xFF, 0x10),	833	_INIT_DCS_CMD(0xFF, 0x10),
762	_INIT_DCS_CMD(0xB9, 0x01),	834	_INIT_DCS_CMD(0xB9, 0x01),
		835
763	_INIT_DCS_CMD(0xFF, 0x20),	836	_INIT_DCS_CMD(0xFF, 0x20),
		837
764	_INIT_DCS_CMD(0x18, 0x40),	838	_INIT_DCS_CMD(0x18, 0x40),
765	_INIT_DCS_CMD(0xFF, 0x10),	839	_INIT_DCS_CMD(0xFF, 0x10),
		840
766	_INIT_DCS_CMD(0xB9, 0x02),	841	_INIT_DCS_CMD(0xB9, 0x02),
767	_INIT_DCS_CMD(0xFF, 0x10),	842	_INIT_DCS_CMD(0xFF, 0x10),
		843
768	_INIT_DCS_CMD(0xFB, 0x01),	844	_INIT_DCS_CMD(0xFB, 0x01),
769	_INIT_DCS_CMD(0xBB, 0x13),	845	_INIT_DCS_CMD(0xB0, 0x01),
770	_INIT_DCS_CMD(0x3B, 0x03, 0x96, 0x1A, 0x04, 0x04),
771	_INIT_DCS_CMD(0x35, 0x00),	846	_INIT_DCS_CMD(0x35, 0x00),
772	_INIT_DCS_CMD(0x51, 0x0F, 0xFF),	847	_INIT_DCS_CMD(0x3B, 0x03, 0xAE, 0x1A, 0x04, 0x04),
773	_INIT_DCS_CMD(0x53, 0x24),
774	_INIT_DELAY_CMD(100),	848	_INIT_DELAY_CMD(100),
775	_INIT_DCS_CMD(0x11),	849	_INIT_DCS_CMD(0x11),
776	_INIT_DELAY_CMD(200),	850	_INIT_DELAY_CMD(200),
@@ -780,7 +854,6 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = { · 3 unmodified lines
780	};	854	};
781		855
782	static const struct panel_init_cmd boe_init_cmd[] = {	856	static const struct panel_init_cmd boe_init_cmd[] = {
783	_INIT_DELAY_CMD(24),
784	_INIT_DCS_CMD(0xB0, 0x05),	857	_INIT_DCS_CMD(0xB0, 0x05),
785	_INIT_DCS_CMD(0xB1, 0xE5),	858	_INIT_DCS_CMD(0xB1, 0xE5),
786	_INIT_DCS_CMD(0xB3, 0x52),	859	_INIT_DCS_CMD(0xB3, 0x52),
@@ -1366,6 +1439,10 @@ static int boe_panel_prepare(struct drm_panel *panel) · 579 unmodified lines
1366		1439
1367	usleep_range(10000, 11000);	1440	usleep_range(10000, 11000);
1368		1441
		1442	if (boe->desc->lp11_before_reset) {
		1443	mipi_dsi_dcs_nop(boe->dsi);
		1444	usleep_range(1000, 2000);
		1445	}
1369	gpiod_set_value(boe->enable_gpio, 1);	1446	gpiod_set_value(boe->enable_gpio, 1);
1370	usleep_range(1000, 2000);	1447	usleep_range(1000, 2000);
1371	gpiod_set_value(boe->enable_gpio, 0);	1448	gpiod_set_value(boe->enable_gpio, 0);
@@ -1431,15 +1508,15 @@ static const struct panel_desc boe_tv110c9m_desc = { · 59 unmodified lines
1431	};	1508	};
1432		1509
1433	static const struct drm_display_mode inx_hj110iz_default_mode = {	1510	static const struct drm_display_mode inx_hj110iz_default_mode = {
1434	.clock = 166594,	1511	.clock = 168432,
1435	.hdisplay = 1200,	1512	.hdisplay = 1200,
1436	.hsync_start = 1200 + 40,	1513	.hsync_start = 1200 + 40,
1437	.hsync_end = 1200 + 40 + 8,	1514	.hsync_end = 1200 + 40 + 8,
1438	.htotal = 1200 + 40 + 8 + 28,	1515	.htotal = 1200 + 40 + 8 + 28,
1439	.vdisplay = 2000,	1516	.vdisplay = 2000,
1440	.vsync_start = 2000 + 26,	1517	.vsync_start = 2000 + 26,
1441	.vsync_end = 2000 + 26 + 1,	1518	.vsync_end = 2000 + 26 + 2,
1442	.vtotal = 2000 + 26 + 1 + 149,	1519	.vtotal = 2000 + 26 + 2 + 172,
1443	.type = DRM_MODE_TYPE_DRIVER \| DRM_MODE_TYPE_PREFERRED,	1520	.type = DRM_MODE_TYPE_DRIVER \| DRM_MODE_TYPE_PREFERRED,
1444	};	1521	};
1445		1522
@@ -1592,6 +1669,7 @@ static const struct panel_desc boe_tv105wum_nw0_desc = { · 146 unmodified lines
1592	.mode_flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_MODE_VIDEO_SYNC_PULSE \|	1669	.mode_flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_MODE_VIDEO_SYNC_PULSE \|
1593	MIPI_DSI_MODE_LPM,	1670	MIPI_DSI_MODE_LPM,
1594	.init_cmds = boe_init_cmd,	1671	.init_cmds = boe_init_cmd,
		1672	.lp11_before_reset = true,
1595	};	1673	};
1596		1674
1597	static const struct drm_display_mode starry_qfh032011_53g_default_mode = {	1675	static const struct drm_display_mode starry_qfh032011_53g_default_mode = {

drivers/gpu/drm/panel/panel-novatek-nt36523.c+566−3

@@ -5,6 +5,7 @@ · 4 unmodified lines
5	* Copyright (c) 2022, 2023 Jianhua Lu <lujianhua000@gmail.com>	5	* Copyright (c) 2022, 2023 Jianhua Lu <lujianhua000@gmail.com>
6	*/	6	*/
7		7
		8	#include <linux/backlight.h>
8	#include <linux/delay.h>	9	#include <linux/delay.h>
9	#include <linux/gpio/consumer.h>	10	#include <linux/gpio/consumer.h>
10	#include <linux/module.h>	11	#include <linux/module.h>
@@ -12,6 +13,8 @@ · 1 unmodified line
12	#include <linux/of_graph.h>	13	#include <linux/of_graph.h>
13	#include <linux/regulator/consumer.h>	14	#include <linux/regulator/consumer.h>
14		15
		16	#include <video/mipi_display.h>
		17
15	#include <drm/drm_connector.h>	18	#include <drm/drm_connector.h>
16	#include <drm/drm_crtc.h>	19	#include <drm/drm_crtc.h>
17	#include <drm/drm_mipi_dsi.h>	20	#include <drm/drm_mipi_dsi.h>
@@ -30,6 +33,7 @@ struct panel_info { · 12 unmodified lines
30	struct drm_panel panel;	33	struct drm_panel panel;
31	struct mipi_dsi_device *dsi[2];	34	struct mipi_dsi_device *dsi[2];
32	const struct panel_desc *desc;	35	const struct panel_desc *desc;
		36	enum drm_panel_orientation orientation;
33		37
34	struct gpio_desc *reset_gpio;	38	struct gpio_desc *reset_gpio;
35	struct backlight_device *backlight;	39	struct backlight_device *backlight;
@@ -53,6 +57,7 @@ struct panel_desc { · 17 unmodified lines
53	int (init_sequence)(struct panel_info pinfo);	57	int (init_sequence)(struct panel_info pinfo);
54		58
55	bool is_dual_dsi;	59	bool is_dual_dsi;
		60	bool has_dcs_backlight;
56	};	61	};
57		62
58	static inline struct panel_info to_panel_info(struct drm_panel panel)	63	static inline struct panel_info to_panel_info(struct drm_panel panel)
@@ -478,6 +483,456 @@ static int elish_csot_init_sequence(struct panel_info *pinfo) · 419 unmodified lines
478	return 0;	483	return 0;
479	}	484	}
480		485
		486	static int j606f_boe_init_sequence(struct panel_info *pinfo)
		487	{
		488	struct mipi_dsi_device *dsi = pinfo->dsi[0];
		489	struct device *dev = &dsi->dev;
		490	int ret;
		491
		492	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x20);
		493	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		494	mipi_dsi_dcs_write_seq(dsi, 0x05, 0xd9);
		495	mipi_dsi_dcs_write_seq(dsi, 0x07, 0x78);
		496	mipi_dsi_dcs_write_seq(dsi, 0x08, 0x5a);
		497	mipi_dsi_dcs_write_seq(dsi, 0x0d, 0x63);
		498	mipi_dsi_dcs_write_seq(dsi, 0x0e, 0x91);
		499	mipi_dsi_dcs_write_seq(dsi, 0x0f, 0x73);
		500	mipi_dsi_dcs_write_seq(dsi, 0x95, 0xeb);
		501	mipi_dsi_dcs_write_seq(dsi, 0x96, 0xeb);
		502	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, 0x11);
		503	mipi_dsi_dcs_write_seq(dsi, 0x6d, 0x66);
		504	mipi_dsi_dcs_write_seq(dsi, 0x75, 0xa2);
		505	mipi_dsi_dcs_write_seq(dsi, 0x77, 0xb3);
		506	mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4d, 0x00, 0x6d, 0x00,
		507	0x89, 0x00, 0xa1, 0x00, 0xb6, 0x00, 0xc9);
		508	mipi_dsi_dcs_write_seq(dsi, 0xb1, 0x00, 0xda, 0x01, 0x13, 0x01, 0x3c, 0x01, 0x7e, 0x01,
		509	0xab, 0x01, 0xf7, 0x02, 0x2f, 0x02, 0x31);
		510	mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x02, 0x67, 0x02, 0xa6, 0x02, 0xd1, 0x03, 0x08, 0x03,
		511	0x2e, 0x03, 0x5b, 0x03, 0x6b, 0x03, 0x7b);
		512	mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x03, 0x8e, 0x03, 0xa2, 0x03, 0xb7, 0x03, 0xe7, 0x03,
		513	0xfd, 0x03, 0xff);
		514	mipi_dsi_dcs_write_seq(dsi, 0xb4, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4d, 0x00, 0x6d, 0x00,
		515	0x89, 0x00, 0xa1, 0x00, 0xb6, 0x00, 0xc9);
		516	mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x00, 0xda, 0x01, 0x13, 0x01, 0x3c, 0x01, 0x7e, 0x01,
		517	0xab, 0x01, 0xf7, 0x02, 0x2f, 0x02, 0x31);
		518	mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x02, 0x67, 0x02, 0xa6, 0x02, 0xd1, 0x03, 0x08, 0x03,
		519	0x2e, 0x03, 0x5b, 0x03, 0x6b, 0x03, 0x7b);
		520	mipi_dsi_dcs_write_seq(dsi, 0xb7, 0x03, 0x8e, 0x03, 0xa2, 0x03, 0xb7, 0x03, 0xe7, 0x03,
		521	0xfd, 0x03, 0xff);
		522	mipi_dsi_dcs_write_seq(dsi, 0xb8, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4d, 0x00, 0x6d, 0x00,
		523	0x89, 0x00, 0xa1, 0x00, 0xb6, 0x00, 0xc9);
		524	mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0xda, 0x01, 0x13, 0x01, 0x3c, 0x01, 0x7e, 0x01,
		525	0xab, 0x01, 0xf7, 0x02, 0x2f, 0x02, 0x31);
		526	mipi_dsi_dcs_write_seq(dsi, 0xba, 0x02, 0x67, 0x02, 0xa6, 0x02, 0xd1, 0x03, 0x08, 0x03,
		527	0x2e, 0x03, 0x5b, 0x03, 0x6b, 0x03, 0x7b);
		528	mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x03, 0x8e, 0x03, 0xa2, 0x03, 0xb7, 0x03, 0xe7, 0x03,
		529	0xfd, 0x03, 0xff);
		530	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x21);
		531	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		532	mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x45, 0x00, 0x65, 0x00,
		533	0x81, 0x00, 0x99, 0x00, 0xae, 0x00, 0xc1);
		534	mipi_dsi_dcs_write_seq(dsi, 0xb1, 0x00, 0xd2, 0x01, 0x0b, 0x01, 0x34, 0x01, 0x76, 0x01,
		535	0xa3, 0x01, 0xef, 0x02, 0x27, 0x02, 0x29);
		536	mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x02, 0x5f, 0x02, 0x9e, 0x02, 0xc9, 0x03, 0x00, 0x03,
		537	0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73);
		538	mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x03, 0x86, 0x03, 0x9a, 0x03, 0xaf, 0x03, 0xdf, 0x03,
		539	0xf5, 0x03, 0xf7);
		540	mipi_dsi_dcs_write_seq(dsi, 0xb4, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x45, 0x00, 0x65, 0x00,
		541	0x81, 0x00, 0x99, 0x00, 0xae, 0x00, 0xc1);
		542	mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x00, 0xd2, 0x01, 0x0b, 0x01, 0x34, 0x01, 0x76, 0x01,
		543	0xa3, 0x01, 0xef, 0x02, 0x27, 0x02, 0x29);
		544	mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x02, 0x5f, 0x02, 0x9e, 0x02, 0xc9, 0x03, 0x00, 0x03,
		545	0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73);
		546	mipi_dsi_dcs_write_seq(dsi, 0xb7, 0x03, 0x86, 0x03, 0x9a, 0x03, 0xaf, 0x03, 0xdf, 0x03,
		547	0xf5, 0x03, 0xf7);
		548	mipi_dsi_dcs_write_seq(dsi, 0xb8, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x45, 0x00, 0x65, 0x00,
		549	0x81, 0x00, 0x99, 0x00, 0xae, 0x00, 0xc1);
		550	mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0xd2, 0x01, 0x0b, 0x01, 0x34, 0x01, 0x76, 0x01,
		551	0xa3, 0x01, 0xef, 0x02, 0x27, 0x02, 0x29);
		552	mipi_dsi_dcs_write_seq(dsi, 0xba, 0x02, 0x5f, 0x02, 0x9e, 0x02, 0xc9, 0x03, 0x00, 0x03,
		553	0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73);
		554	mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x03, 0x86, 0x03, 0x9a, 0x03, 0xaf, 0x03, 0xdf, 0x03,
		555	0xf5, 0x03, 0xf7);
		556	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x23);
		557	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		558	mipi_dsi_dcs_write_seq(dsi, 0x00, 0x80);
		559	mipi_dsi_dcs_write_seq(dsi, 0x07, 0x00);
		560	mipi_dsi_dcs_write_seq(dsi, 0x11, 0x01);
		561	mipi_dsi_dcs_write_seq(dsi, 0x12, 0x77);
		562	mipi_dsi_dcs_write_seq(dsi, 0x15, 0x07);
		563	mipi_dsi_dcs_write_seq(dsi, 0x16, 0x07);
		564	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x24);
		565	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		566	mipi_dsi_dcs_write_seq(dsi, 0x00, 0x00);
		567	mipi_dsi_dcs_write_seq(dsi, 0x01, 0x00);
		568	mipi_dsi_dcs_write_seq(dsi, 0x02, 0x1c);
		569	mipi_dsi_dcs_write_seq(dsi, 0x03, 0x1c);
		570	mipi_dsi_dcs_write_seq(dsi, 0x04, 0x1d);
		571	mipi_dsi_dcs_write_seq(dsi, 0x05, 0x1d);
		572	mipi_dsi_dcs_write_seq(dsi, 0x06, 0x04);
		573	mipi_dsi_dcs_write_seq(dsi, 0x07, 0x04);
		574	mipi_dsi_dcs_write_seq(dsi, 0x08, 0x0f);
		575	mipi_dsi_dcs_write_seq(dsi, 0x09, 0x0f);
		576	mipi_dsi_dcs_write_seq(dsi, 0x0a, 0x0e);
		577	mipi_dsi_dcs_write_seq(dsi, 0x0b, 0x0e);
		578	mipi_dsi_dcs_write_seq(dsi, 0x0c, 0x0d);
		579	mipi_dsi_dcs_write_seq(dsi, 0x0d, 0x0d);
		580	mipi_dsi_dcs_write_seq(dsi, 0x0e, 0x0c);
		581	mipi_dsi_dcs_write_seq(dsi, 0x0f, 0x0c);
		582	mipi_dsi_dcs_write_seq(dsi, 0x10, 0x08);
		583	mipi_dsi_dcs_write_seq(dsi, 0x11, 0x08);
		584	mipi_dsi_dcs_write_seq(dsi, 0x12, 0x00);
		585	mipi_dsi_dcs_write_seq(dsi, 0x13, 0x00);
		586	mipi_dsi_dcs_write_seq(dsi, 0x14, 0x00);
		587	mipi_dsi_dcs_write_seq(dsi, 0x15, 0x00);
		588	mipi_dsi_dcs_write_seq(dsi, 0x16, 0x00);
		589	mipi_dsi_dcs_write_seq(dsi, 0x17, 0x00);
		590	mipi_dsi_dcs_write_seq(dsi, 0x18, 0x1c);
		591	mipi_dsi_dcs_write_seq(dsi, 0x19, 0x1c);
		592	mipi_dsi_dcs_write_seq(dsi, 0x1a, 0x1d);
		593	mipi_dsi_dcs_write_seq(dsi, 0x1b, 0x1d);
		594	mipi_dsi_dcs_write_seq(dsi, 0x1c, 0x04);
		595	mipi_dsi_dcs_write_seq(dsi, 0x1d, 0x04);
		596	mipi_dsi_dcs_write_seq(dsi, 0x1e, 0x0f);
		597	mipi_dsi_dcs_write_seq(dsi, 0x1f, 0x0f);
		598	mipi_dsi_dcs_write_seq(dsi, 0x20, 0x0e);
		599	mipi_dsi_dcs_write_seq(dsi, 0x21, 0x0e);
		600	mipi_dsi_dcs_write_seq(dsi, 0x22, 0x0d);
		601	mipi_dsi_dcs_write_seq(dsi, 0x23, 0x0d);
		602	mipi_dsi_dcs_write_seq(dsi, 0x24, 0x0c);
		603	mipi_dsi_dcs_write_seq(dsi, 0x25, 0x0c);
		604	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_GAMMA_CURVE, 0x08);
		605	mipi_dsi_dcs_write_seq(dsi, 0x27, 0x08);
		606	mipi_dsi_dcs_write_seq(dsi, 0x28, 0x00);
		607	mipi_dsi_dcs_write_seq(dsi, 0x29, 0x00);
		608	mipi_dsi_dcs_write_seq(dsi, 0x2a, 0x00);
		609	mipi_dsi_dcs_write_seq(dsi, 0x2b, 0x00);
		610	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_LUT, 0x20);
		611	mipi_dsi_dcs_write_seq(dsi, 0x2f, 0x0a);
		612	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, 0x44);
		613	mipi_dsi_dcs_write_seq(dsi, 0x33, 0x0c);
		614	mipi_dsi_dcs_write_seq(dsi, 0x34, 0x32);
		615	mipi_dsi_dcs_write_seq(dsi, 0x37, 0x44);
		616	mipi_dsi_dcs_write_seq(dsi, 0x38, 0x40);
		617	mipi_dsi_dcs_write_seq(dsi, 0x39, 0x00);
		618
		619	ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x9a);
		620	if (ret < 0) {
		621	dev_err(dev, "Failed to set pixel format: %d\n", ret);
		622	return ret;
		623	}
		624
		625	mipi_dsi_dcs_write_seq(dsi, 0x3b, 0xa0);
		626	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_3D_CONTROL, 0x42);
		627	mipi_dsi_dcs_write_seq(dsi, 0x3f, 0x06);
		628	mipi_dsi_dcs_write_seq(dsi, 0x43, 0x06);
		629	mipi_dsi_dcs_write_seq(dsi, 0x47, 0x66);
		630	mipi_dsi_dcs_write_seq(dsi, 0x4a, 0x9a);
		631	mipi_dsi_dcs_write_seq(dsi, 0x4b, 0xa0);
		632	mipi_dsi_dcs_write_seq(dsi, 0x4c, 0x91);
		633	mipi_dsi_dcs_write_seq(dsi, 0x4d, 0x21);
		634	mipi_dsi_dcs_write_seq(dsi, 0x4e, 0x43);
		635
		636	ret = mipi_dsi_dcs_set_display_brightness(dsi, 18);
		637	if (ret < 0) {
		638	dev_err(dev, "Failed to set display brightness: %d\n", ret);
		639	return ret;
		640	}
		641
		642	mipi_dsi_dcs_write_seq(dsi, 0x52, 0x34);
		643	mipi_dsi_dcs_write_seq(dsi, 0x55, 0x82, 0x02);
		644	mipi_dsi_dcs_write_seq(dsi, 0x56, 0x04);
		645	mipi_dsi_dcs_write_seq(dsi, 0x58, 0x21);
		646	mipi_dsi_dcs_write_seq(dsi, 0x59, 0x30);
		647	mipi_dsi_dcs_write_seq(dsi, 0x5a, 0xba);
		648	mipi_dsi_dcs_write_seq(dsi, 0x5b, 0xa0);
		649	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x00, 0x06);
		650	mipi_dsi_dcs_write_seq(dsi, 0x5f, 0x00);
		651	mipi_dsi_dcs_write_seq(dsi, 0x65, 0x82);
		652	mipi_dsi_dcs_write_seq(dsi, 0x7e, 0x20);
		653	mipi_dsi_dcs_write_seq(dsi, 0x7f, 0x3c);
		654	mipi_dsi_dcs_write_seq(dsi, 0x82, 0x04);
		655	mipi_dsi_dcs_write_seq(dsi, 0x97, 0xc0);
		656	mipi_dsi_dcs_write_seq(dsi, 0xb6,
		657	0x05, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05,
		658	0x05, 0x00, 0x00);
		659	mipi_dsi_dcs_write_seq(dsi, 0x92, 0xc4);
		660	mipi_dsi_dcs_write_seq(dsi, 0x93, 0x1a);
		661	mipi_dsi_dcs_write_seq(dsi, 0x94, 0x5f);
		662	mipi_dsi_dcs_write_seq(dsi, 0xd7, 0x55);
		663	mipi_dsi_dcs_write_seq(dsi, 0xda, 0x0a);
		664	mipi_dsi_dcs_write_seq(dsi, 0xde, 0x08);
		665	mipi_dsi_dcs_write_seq(dsi, 0xdb, 0x05);
		666	mipi_dsi_dcs_write_seq(dsi, 0xdc, 0xc4);
		667	mipi_dsi_dcs_write_seq(dsi, 0xdd, 0x22);
		668	mipi_dsi_dcs_write_seq(dsi, 0xdf, 0x05);
		669	mipi_dsi_dcs_write_seq(dsi, 0xe0, 0xc4);
		670	mipi_dsi_dcs_write_seq(dsi, 0xe1, 0x05);
		671	mipi_dsi_dcs_write_seq(dsi, 0xe2, 0xc4);
		672	mipi_dsi_dcs_write_seq(dsi, 0xe3, 0x05);
		673	mipi_dsi_dcs_write_seq(dsi, 0xe4, 0xc4);
		674	mipi_dsi_dcs_write_seq(dsi, 0xe5, 0x05);
		675	mipi_dsi_dcs_write_seq(dsi, 0xe6, 0xc4);
		676	mipi_dsi_dcs_write_seq(dsi, 0x5c, 0x88);
		677	mipi_dsi_dcs_write_seq(dsi, 0x5d, 0x08);
		678	mipi_dsi_dcs_write_seq(dsi, 0x8d, 0x88);
		679	mipi_dsi_dcs_write_seq(dsi, 0x8e, 0x08);
		680	mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x90);
		681	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x25);
		682	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		683	mipi_dsi_dcs_write_seq(dsi, 0x05, 0x00);
		684	mipi_dsi_dcs_write_seq(dsi, 0x19, 0x07);
		685	mipi_dsi_dcs_write_seq(dsi, 0x1f, 0xba);
		686	mipi_dsi_dcs_write_seq(dsi, 0x20, 0xa0);
		687	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_GAMMA_CURVE, 0xba);
		688	mipi_dsi_dcs_write_seq(dsi, 0x27, 0xa0);
		689	mipi_dsi_dcs_write_seq(dsi, 0x33, 0xba);
		690	mipi_dsi_dcs_write_seq(dsi, 0x34, 0xa0);
		691	mipi_dsi_dcs_write_seq(dsi, 0x3f, 0xe0);
		692	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_VSYNC_TIMING, 0x00);
		693	mipi_dsi_dcs_write_seq(dsi, 0x44, 0x00);
		694	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_GET_SCANLINE, 0x40);
		695	mipi_dsi_dcs_write_seq(dsi, 0x48, 0xba);
		696	mipi_dsi_dcs_write_seq(dsi, 0x49, 0xa0);
		697	mipi_dsi_dcs_write_seq(dsi, 0x5b, 0x00);
		698	mipi_dsi_dcs_write_seq(dsi, 0x5c, 0x00);
		699	mipi_dsi_dcs_write_seq(dsi, 0x5d, 0x00);
		700	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0xd0);
		701	mipi_dsi_dcs_write_seq(dsi, 0x61, 0xba);
		702	mipi_dsi_dcs_write_seq(dsi, 0x62, 0xa0);
		703	mipi_dsi_dcs_write_seq(dsi, 0xf1, 0x10);
		704	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x2a);
		705	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		706	mipi_dsi_dcs_write_seq(dsi, 0x64, 0x16);
		707	mipi_dsi_dcs_write_seq(dsi, 0x67, 0x16);
		708	mipi_dsi_dcs_write_seq(dsi, 0x6a, 0x16);
		709	mipi_dsi_dcs_write_seq(dsi, 0x70, 0x30);
		710	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_READ_PPS_START, 0xf3);
		711	mipi_dsi_dcs_write_seq(dsi, 0xa3, 0xff);
		712	mipi_dsi_dcs_write_seq(dsi, 0xa4, 0xff);
		713	mipi_dsi_dcs_write_seq(dsi, 0xa5, 0xff);
		714	mipi_dsi_dcs_write_seq(dsi, 0xd6, 0x08);
		715	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x26);
		716	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		717	mipi_dsi_dcs_write_seq(dsi, 0x00, 0xa1);
		718	mipi_dsi_dcs_write_seq(dsi, 0x0a, 0xf2);
		719	mipi_dsi_dcs_write_seq(dsi, 0x04, 0x28);
		720	mipi_dsi_dcs_write_seq(dsi, 0x06, 0x30);
		721	mipi_dsi_dcs_write_seq(dsi, 0x0c, 0x13);
		722	mipi_dsi_dcs_write_seq(dsi, 0x0d, 0x0a);
		723	mipi_dsi_dcs_write_seq(dsi, 0x0f, 0x0a);
		724	mipi_dsi_dcs_write_seq(dsi, 0x11, 0x00);
		725	mipi_dsi_dcs_write_seq(dsi, 0x12, 0x50);
		726	mipi_dsi_dcs_write_seq(dsi, 0x13, 0x51);
		727	mipi_dsi_dcs_write_seq(dsi, 0x14, 0x65);
		728	mipi_dsi_dcs_write_seq(dsi, 0x15, 0x00);
		729	mipi_dsi_dcs_write_seq(dsi, 0x16, 0x10);
		730	mipi_dsi_dcs_write_seq(dsi, 0x17, 0xa0);
		731	mipi_dsi_dcs_write_seq(dsi, 0x18, 0x86);
		732	mipi_dsi_dcs_write_seq(dsi, 0x19, 0x11);
		733	mipi_dsi_dcs_write_seq(dsi, 0x1a, 0x7b);
		734	mipi_dsi_dcs_write_seq(dsi, 0x1b, 0x10);
		735	mipi_dsi_dcs_write_seq(dsi, 0x1c, 0xbb);
		736	mipi_dsi_dcs_write_seq(dsi, 0x22, 0x00);
		737	mipi_dsi_dcs_write_seq(dsi, 0x23, 0x00);
		738	mipi_dsi_dcs_write_seq(dsi, 0x2a, 0x11);
		739	mipi_dsi_dcs_write_seq(dsi, 0x2b, 0x7b);
		740	mipi_dsi_dcs_write_seq(dsi, 0x1d, 0x00);
		741	mipi_dsi_dcs_write_seq(dsi, 0x1e, 0xc3);
		742	mipi_dsi_dcs_write_seq(dsi, 0x1f, 0xc3);
		743	mipi_dsi_dcs_write_seq(dsi, 0x24, 0x00);
		744	mipi_dsi_dcs_write_seq(dsi, 0x25, 0xc3);
		745	mipi_dsi_dcs_write_seq(dsi, 0x2f, 0x05);
		746	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, 0xc3);
		747	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_COLUMNS, 0x00);
		748	mipi_dsi_dcs_write_seq(dsi, 0x32, 0xc3);
		749	mipi_dsi_dcs_write_seq(dsi, 0x39, 0x00);
		750
		751	ret = mipi_dsi_dcs_set_pixel_format(dsi, 0xc3);
		752	if (ret < 0) {
		753	dev_err(dev, "Failed to set pixel format: %d\n", ret);
		754	return ret;
		755	}
		756
		757	mipi_dsi_dcs_write_seq(dsi, 0x20, 0x01);
		758	mipi_dsi_dcs_write_seq(dsi, 0x33, 0x11);
		759	mipi_dsi_dcs_write_seq(dsi, 0x34, 0x78);
		760	mipi_dsi_dcs_write_seq(dsi, 0x35, 0x16);
		761	mipi_dsi_dcs_write_seq(dsi, 0xc8, 0x04);
		762	mipi_dsi_dcs_write_seq(dsi, 0xc9, 0x82);
		763	mipi_dsi_dcs_write_seq(dsi, 0xca, 0x4e);
		764	mipi_dsi_dcs_write_seq(dsi, 0xcb, 0x00);
		765	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_READ_PPS_CONTINUE, 0x4c);
		766	mipi_dsi_dcs_write_seq(dsi, 0xaa, 0x47);
		767	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x27);
		768	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		769	mipi_dsi_dcs_write_seq(dsi, 0x56, 0x06);
		770	mipi_dsi_dcs_write_seq(dsi, 0x58, 0x80);
		771	mipi_dsi_dcs_write_seq(dsi, 0x59, 0x53);
		772	mipi_dsi_dcs_write_seq(dsi, 0x5a, 0x00);
		773	mipi_dsi_dcs_write_seq(dsi, 0x5b, 0x14);
		774	mipi_dsi_dcs_write_seq(dsi, 0x5c, 0x00);
		775	mipi_dsi_dcs_write_seq(dsi, 0x5d, 0x01);
		776	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x20);
		777	mipi_dsi_dcs_write_seq(dsi, 0x5f, 0x10);
		778	mipi_dsi_dcs_write_seq(dsi, 0x60, 0x00);
		779	mipi_dsi_dcs_write_seq(dsi, 0x61, 0x1d);
		780	mipi_dsi_dcs_write_seq(dsi, 0x62, 0x00);
		781	mipi_dsi_dcs_write_seq(dsi, 0x63, 0x01);
		782	mipi_dsi_dcs_write_seq(dsi, 0x64, 0x24);
		783	mipi_dsi_dcs_write_seq(dsi, 0x65, 0x1c);
		784	mipi_dsi_dcs_write_seq(dsi, 0x66, 0x00);
		785	mipi_dsi_dcs_write_seq(dsi, 0x67, 0x01);
		786	mipi_dsi_dcs_write_seq(dsi, 0x68, 0x25);
		787	mipi_dsi_dcs_write_seq(dsi, 0x00, 0x00);
		788	mipi_dsi_dcs_write_seq(dsi, 0x78, 0x00);
		789	mipi_dsi_dcs_write_seq(dsi, 0xc3, 0x00);
		790	mipi_dsi_dcs_write_seq(dsi, 0xd1, 0x24);
		791	mipi_dsi_dcs_write_seq(dsi, 0xd2, 0x30);
		792	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x2a);
		793	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		794	mipi_dsi_dcs_write_seq(dsi, 0x22, 0x2f);
		795	mipi_dsi_dcs_write_seq(dsi, 0x23, 0x08);
		796	mipi_dsi_dcs_write_seq(dsi, 0x24, 0x00);
		797	mipi_dsi_dcs_write_seq(dsi, 0x25, 0xc3);
		798	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_GAMMA_CURVE, 0xf8);
		799	mipi_dsi_dcs_write_seq(dsi, 0x27, 0x00);
		800	mipi_dsi_dcs_write_seq(dsi, 0x28, 0x1a);
		801	mipi_dsi_dcs_write_seq(dsi, 0x29, 0x00);
		802	mipi_dsi_dcs_write_seq(dsi, 0x2a, 0x1a);
		803	mipi_dsi_dcs_write_seq(dsi, 0x2b, 0x00);
		804	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_LUT, 0x1a);
		805	mipi_dsi_dcs_write_seq(dsi, 0xff, 0xe0);
		806	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		807	mipi_dsi_dcs_write_seq(dsi, 0x14, 0x60);
		808	mipi_dsi_dcs_write_seq(dsi, 0x16, 0xc0);
		809	mipi_dsi_dcs_write_seq(dsi, 0xff, 0xf0);
		810	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		811
		812	ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x08);
		813	if (ret < 0) {
		814	dev_err(dev, "Failed to set pixel format: %d\n", ret);
		815	return ret;
		816	}
		817
		818	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x24);
		819	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		820
		821	ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x5d);
		822	if (ret < 0) {
		823	dev_err(dev, "Failed to set pixel format: %d\n", ret);
		824	return ret;
		825	}
		826
		827	mipi_dsi_dcs_write_seq(dsi, 0x3b, 0x60);
		828	mipi_dsi_dcs_write_seq(dsi, 0x4a, 0x5d);
		829	mipi_dsi_dcs_write_seq(dsi, 0x4b, 0x60);
		830	mipi_dsi_dcs_write_seq(dsi, 0x5a, 0x70);
		831	mipi_dsi_dcs_write_seq(dsi, 0x5b, 0x60);
		832	mipi_dsi_dcs_write_seq(dsi, 0x91, 0x44);
		833	mipi_dsi_dcs_write_seq(dsi, 0x92, 0x75);
		834	mipi_dsi_dcs_write_seq(dsi, 0xdb, 0x05);
		835	mipi_dsi_dcs_write_seq(dsi, 0xdc, 0x75);
		836	mipi_dsi_dcs_write_seq(dsi, 0xdd, 0x22);
		837	mipi_dsi_dcs_write_seq(dsi, 0xdf, 0x05);
		838	mipi_dsi_dcs_write_seq(dsi, 0xe0, 0x75);
		839	mipi_dsi_dcs_write_seq(dsi, 0xe1, 0x05);
		840	mipi_dsi_dcs_write_seq(dsi, 0xe2, 0x75);
		841	mipi_dsi_dcs_write_seq(dsi, 0xe3, 0x05);
		842	mipi_dsi_dcs_write_seq(dsi, 0xe4, 0x75);
		843	mipi_dsi_dcs_write_seq(dsi, 0xe5, 0x05);
		844	mipi_dsi_dcs_write_seq(dsi, 0xe6, 0x75);
		845	mipi_dsi_dcs_write_seq(dsi, 0x5c, 0x00);
		846	mipi_dsi_dcs_write_seq(dsi, 0x5d, 0x00);
		847	mipi_dsi_dcs_write_seq(dsi, 0x8d, 0x00);
		848	mipi_dsi_dcs_write_seq(dsi, 0x8e, 0x00);
		849	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x25);
		850	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		851	mipi_dsi_dcs_write_seq(dsi, 0x1f, 0x70);
		852	mipi_dsi_dcs_write_seq(dsi, 0x20, 0x60);
		853	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_GAMMA_CURVE, 0x70);
		854	mipi_dsi_dcs_write_seq(dsi, 0x27, 0x60);
		855	mipi_dsi_dcs_write_seq(dsi, 0x33, 0x70);
		856	mipi_dsi_dcs_write_seq(dsi, 0x34, 0x60);
		857	mipi_dsi_dcs_write_seq(dsi, 0x48, 0x70);
		858	mipi_dsi_dcs_write_seq(dsi, 0x49, 0x60);
		859	mipi_dsi_dcs_write_seq(dsi, 0x5b, 0x00);
		860	mipi_dsi_dcs_write_seq(dsi, 0x61, 0x70);
		861	mipi_dsi_dcs_write_seq(dsi, 0x62, 0x60);
		862	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x26);
		863	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		864	mipi_dsi_dcs_write_seq(dsi, 0x02, 0x31);
		865	mipi_dsi_dcs_write_seq(dsi, 0x19, 0x0a);
		866	mipi_dsi_dcs_write_seq(dsi, 0x1a, 0x7f);
		867	mipi_dsi_dcs_write_seq(dsi, 0x1b, 0x0a);
		868	mipi_dsi_dcs_write_seq(dsi, 0x1c, 0x0c);
		869	mipi_dsi_dcs_write_seq(dsi, 0x2a, 0x0a);
		870	mipi_dsi_dcs_write_seq(dsi, 0x2b, 0x7f);
		871	mipi_dsi_dcs_write_seq(dsi, 0x1e, 0x75);
		872	mipi_dsi_dcs_write_seq(dsi, 0x1f, 0x75);
		873	mipi_dsi_dcs_write_seq(dsi, 0x25, 0x75);
		874	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, 0x75);
		875	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_COLUMNS, 0x05);
		876	mipi_dsi_dcs_write_seq(dsi, 0x32, 0x8d);
		877
		878	ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x75);
		879	if (ret < 0) {
		880	dev_err(dev, "Failed to set pixel format: %d\n", ret);
		881	return ret;
		882	}
		883
		884	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x2a);
		885	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		886	mipi_dsi_dcs_write_seq(dsi, 0x25, 0x75);
		887	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x10);
		888	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		889	mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x01);
		890	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x20);
		891	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		892	mipi_dsi_dcs_write_seq(dsi, 0x18, 0x40);
		893	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x10);
		894	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		895	mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x02);
		896
		897	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
		898	if (ret < 0) {
		899	dev_err(dev, "Failed to set tear on: %d\n", ret);
		900	return ret;
		901	}
		902
		903	mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x13);
		904	mipi_dsi_dcs_write_seq(dsi, 0x3b, 0x03, 0x5f, 0x1a, 0x04, 0x04);
		905	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x10);
		906	usleep_range(10000, 11000);
		907	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
		908
		909	ret = mipi_dsi_dcs_set_display_brightness(dsi, 0);
		910	if (ret < 0) {
		911	dev_err(dev, "Failed to set display brightness: %d\n", ret);
		912	return ret;
		913	}
		914
		915	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x2c);
		916	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
		917	mipi_dsi_dcs_write_seq(dsi, 0x68, 0x05, 0x01);
		918
		919	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
		920	if (ret < 0) {
		921	dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
		922	return ret;
		923	}
		924	msleep(100);
		925
		926	ret = mipi_dsi_dcs_set_display_on(dsi);
		927	if (ret < 0) {
		928	dev_err(dev, "Failed to set display on: %d\n", ret);
		929	return ret;
		930	}
		931	msleep(30);
		932
		933	return 0;
		934	}
		935
481	static const struct drm_display_mode elish_boe_modes[] = {	936	static const struct drm_display_mode elish_boe_modes[] = {
482	{	937	{
483	/* There is only one 120 Hz timing, but it doesn't work perfectly, 104 Hz preferred */	938	/* There is only one 120 Hz timing, but it doesn't work perfectly, 104 Hz preferred */
@@ -508,6 +963,22 @@ static const struct drm_display_mode elish_csot_modes[] = { · 24 unmodified lines
508	},	963	},
509	};	964	};
510		965
		966	static const struct drm_display_mode j606f_boe_modes[] = {
		967	{
		968	.clock = (1200 + 58 + 2 + 60) * (2000 + 26 + 2 + 93) * 60 / 1000,
		969	.hdisplay = 1200,
		970	.hsync_start = 1200 + 58,
		971	.hsync_end = 1200 + 58 + 2,
		972	.htotal = 1200 + 58 + 2 + 60,
		973	.vdisplay = 2000,
		974	.vsync_start = 2000 + 26,
		975	.vsync_end = 2000 + 26 + 2,
		976	.vtotal = 2000 + 26 + 2 + 93,
		977	.width_mm = 143,
		978	.height_mm = 235,
		979	},
		980	};
		981
511	static const struct panel_desc elish_boe_desc = {	982	static const struct panel_desc elish_boe_desc = {
512	.modes = elish_boe_modes,	983	.modes = elish_boe_modes,
513	.num_modes = ARRAY_SIZE(elish_boe_modes),	984	.num_modes = ARRAY_SIZE(elish_boe_modes),
@@ -544,6 +1015,20 @@ static const struct panel_desc elish_csot_desc = { · 30 unmodified lines
544	.is_dual_dsi = true,	1015	.is_dual_dsi = true,
545	};	1016	};
546		1017
		1018	static const struct panel_desc j606f_boe_desc = {
		1019	.modes = j606f_boe_modes,
		1020	.num_modes = ARRAY_SIZE(j606f_boe_modes),
		1021	.width_mm = 143,
		1022	.height_mm = 235,
		1023	.bpc = 8,
		1024	.lanes = 4,
		1025	.format = MIPI_DSI_FMT_RGB888,
		1026	.mode_flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_MODE_VIDEO_BURST \|
		1027	MIPI_DSI_CLOCK_NON_CONTINUOUS \| MIPI_DSI_MODE_LPM,
		1028	.init_sequence = j606f_boe_init_sequence,
		1029	.has_dcs_backlight = true,
		1030	};
		1031
547	static void nt36523_reset(struct panel_info *pinfo)	1032	static void nt36523_reset(struct panel_info *pinfo)
548	{	1033	{
549	gpiod_set_value_cansleep(pinfo->reset_gpio, 1);	1034	gpiod_set_value_cansleep(pinfo->reset_gpio, 1);
@@ -672,13 +1157,74 @@ static int nt36523_get_modes(struct drm_panel *panel, · 122 unmodified lines
672	return pinfo->desc->num_modes;	1157	return pinfo->desc->num_modes;
673	}	1158	}
674		1159
		1160	static enum drm_panel_orientation nt36523_get_orientation(struct drm_panel *panel)
		1161	{
		1162	struct panel_info *pinfo = to_panel_info(panel);
		1163
		1164	return pinfo->orientation;
		1165	}
		1166
675	static const struct drm_panel_funcs nt36523_panel_funcs = {	1167	static const struct drm_panel_funcs nt36523_panel_funcs = {
676	.disable = nt36523_disable,	1168	.disable = nt36523_disable,
677	.prepare = nt36523_prepare,	1169	.prepare = nt36523_prepare,
678	.unprepare = nt36523_unprepare,	1170	.unprepare = nt36523_unprepare,
679	.get_modes = nt36523_get_modes,	1171	.get_modes = nt36523_get_modes,
		1172	.get_orientation = nt36523_get_orientation,
680	};	1173	};
681		1174
		1175	static int nt36523_bl_update_status(struct backlight_device *bl)
		1176	{
		1177	struct mipi_dsi_device *dsi = bl_get_data(bl);
		1178	u16 brightness = backlight_get_brightness(bl);
		1179	int ret;
		1180
		1181	dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
		1182
		1183	ret = mipi_dsi_dcs_set_display_brightness_large(dsi, brightness);
		1184	if (ret < 0)
		1185	return ret;
		1186
		1187	dsi->mode_flags \|= MIPI_DSI_MODE_LPM;
		1188
		1189	return 0;
		1190	}
		1191
		1192	static int nt36523_bl_get_brightness(struct backlight_device *bl)
		1193	{
		1194	struct mipi_dsi_device *dsi = bl_get_data(bl);
		1195	u16 brightness;
		1196	int ret;
		1197
		1198	dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
		1199
		1200	ret = mipi_dsi_dcs_get_display_brightness_large(dsi, &brightness);
		1201	if (ret < 0)
		1202	return ret;
		1203
		1204	dsi->mode_flags \|= MIPI_DSI_MODE_LPM;
		1205
		1206	return brightness;
		1207	}
		1208
		1209	static const struct backlight_ops nt36523_bl_ops = {
		1210	.update_status = nt36523_bl_update_status,
		1211	.get_brightness = nt36523_bl_get_brightness,
		1212	};
		1213
		1214	static struct backlight_device nt36523_create_backlight(struct mipi_dsi_device dsi)
		1215	{
		1216	struct device *dev = &dsi->dev;
		1217	const struct backlight_properties props = {
		1218	.type = BACKLIGHT_RAW,
		1219	.brightness = 512,
		1220	.max_brightness = 4095,
		1221	.scale = BACKLIGHT_SCALE_NON_LINEAR,
		1222	};
		1223
		1224	return devm_backlight_device_register(dev, dev_name(dev), dev, dsi,
		1225	&nt36523_bl_ops, &props);
		1226	}
		1227
682	static int nt36523_probe(struct mipi_dsi_device *dsi)	1228	static int nt36523_probe(struct mipi_dsi_device *dsi)
683	{	1229	{
684	struct device *dev = &dsi->dev;	1230	struct device *dev = &dsi->dev;
@@ -730,9 +1276,22 @@ static int nt36523_probe(struct mipi_dsi_device *dsi) · 45 unmodified lines
730	mipi_dsi_set_drvdata(dsi, pinfo);	1276	mipi_dsi_set_drvdata(dsi, pinfo);
731	drm_panel_init(&pinfo->panel, dev, &nt36523_panel_funcs, DRM_MODE_CONNECTOR_DSI);	1277	drm_panel_init(&pinfo->panel, dev, &nt36523_panel_funcs, DRM_MODE_CONNECTOR_DSI);
732		1278
733	ret = drm_panel_of_backlight(&pinfo->panel);	1279	ret = of_drm_get_panel_orientation(dev->of_node, &pinfo->orientation);
734	if (ret)	1280	if (ret < 0) {
735	return dev_err_probe(dev, ret, "failed to get backlight\n");	1281	dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, ret);
		1282	return ret;
		1283	}
		1284
		1285	if (pinfo->desc->has_dcs_backlight) {
		1286	pinfo->panel.backlight = nt36523_create_backlight(dsi);
		1287	if (IS_ERR(pinfo->panel.backlight))
		1288	return dev_err_probe(dev, PTR_ERR(pinfo->panel.backlight),
		1289	"Failed to create backlight\n");
		1290	} else {
		1291	ret = drm_panel_of_backlight(&pinfo->panel);
		1292	if (ret)
		1293	return dev_err_probe(dev, ret, "Failed to get backlight\n");
		1294	}
736		1295
737	drm_panel_add(&pinfo->panel);	1296	drm_panel_add(&pinfo->panel);
738		1297
@@ -750,6 +1309,10 @@ static int nt36523_probe(struct mipi_dsi_device *dsi) · 11 unmodified lines
750	}	1309	}
751		1310
752	static const struct of_device_id nt36523_of_match[] = {	1311	static const struct of_device_id nt36523_of_match[] = {
		1312	{
		1313	.compatible = "lenovo,j606f-boe-nt36523w",
		1314	.data = &j606f_boe_desc,
		1315	},
753	{	1316	{
754	.compatible = "xiaomi,elish-boe-nt36523",	1317	.compatible = "xiaomi,elish-boe-nt36523",
755	.data = &elish_boe_desc,	1318	.data = &elish_boe_desc,

drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c+585−0

@@ -0,0 +1,585 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Samsung S6D7AA0 MIPI-DSI TFT LCD controller drm_panel driver.
	4	*
	5	* Copyright (C) 2022 Artur Weber <aweber.kernel@gmail.com>
	6	*/
	7
	8	#include <linux/backlight.h>
	9	#include <linux/delay.h>
	10	#include <linux/gpio/consumer.h>
	11	#include <linux/module.h>
	12	#include <linux/regulator/consumer.h>
	13	#include <linux/of.h>
	14	#include <linux/of_device.h>
	15
	16	#include <video/mipi_display.h>
	17	#include <drm/drm_mipi_dsi.h>
	18	#include <drm/drm_modes.h>
	19	#include <drm/drm_panel.h>
	20
	21	/* Manufacturer command set */
	22	#define MCS_BL_CTL 0xc3
	23	#define MCS_OTP_RELOAD 0xd0
	24	#define MCS_PASSWD1 0xf0
	25	#define MCS_PASSWD2 0xf1
	26	#define MCS_PASSWD3 0xfc
	27
	28	struct s6d7aa0 {
	29	struct drm_panel panel;
	30	struct mipi_dsi_device *dsi;
	31	struct gpio_desc *reset_gpio;
	32	struct regulator_bulk_data supplies[2];
	33	const struct s6d7aa0_panel_desc *desc;
	34	};
	35
	36	struct s6d7aa0_panel_desc {
	37	unsigned int panel_type;
	38	int (init_func)(struct s6d7aa0 ctx);
	39	int (off_func)(struct s6d7aa0 ctx);
	40	const struct drm_display_mode *drm_mode;
	41	unsigned long mode_flags;
	42	u32 bus_flags;
	43	bool has_backlight;
	44	bool use_passwd3;
	45	};
	46
	47	enum s6d7aa0_panels {
	48	S6D7AA0_PANEL_LSL080AL02,
	49	S6D7AA0_PANEL_LSL080AL03,
	50	S6D7AA0_PANEL_LTL101AT01,
	51	};
	52
	53	static inline struct s6d7aa0 panel_to_s6d7aa0(struct drm_panel panel)
	54	{
	55	return container_of(panel, struct s6d7aa0, panel);
	56	}
	57
	58	static void s6d7aa0_reset(struct s6d7aa0 *ctx)
	59	{
	60	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
	61	msleep(50);
	62	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
	63	msleep(50);
	64	}
	65
	66	static int s6d7aa0_lock(struct s6d7aa0 *ctx, bool lock)
	67	{
	68	struct mipi_dsi_device *dsi = ctx->dsi;
	69	int ret = 0;
	70
	71	if (lock) {
	72	mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0xa5, 0xa5);
	73	mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0xa5, 0xa5);
	74	if (ctx->desc->use_passwd3)
	75	mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD3, 0x5a, 0x5a);
	76	} else {
	77	mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0x5a, 0x5a);
	78	mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0x5a, 0x5a);
	79	if (ctx->desc->use_passwd3)
	80	mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD3, 0xa5, 0xa5);
	81	}
	82
	83	return ret;
	84	}
	85
	86	static int s6d7aa0_on(struct s6d7aa0 *ctx)
	87	{
	88	struct mipi_dsi_device *dsi = ctx->dsi;
	89	struct device *dev = &dsi->dev;
	90	int ret;
	91
	92	ret = ctx->desc->init_func(ctx);
	93	if (ret < 0) {
	94	dev_err(dev, "Failed to initialize panel: %d\n", ret);
	95	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
	96	return ret;
	97	}
	98
	99	ret = mipi_dsi_dcs_set_display_on(dsi);
	100	if (ret < 0) {
	101	dev_err(dev, "Failed to set display on: %d\n", ret);
	102	return ret;
	103	}
	104
	105	return 0;
	106	}
	107
	108	static int s6d7aa0_off(struct s6d7aa0 *ctx)
	109	{
	110	struct mipi_dsi_device *dsi = ctx->dsi;
	111	struct device *dev = &dsi->dev;
	112	int ret;
	113
	114	ret = ctx->desc->off_func(ctx);
	115	if (ret < 0) {
	116	dev_err(dev, "Panel-specific off function failed: %d\n", ret);
	117	return ret;
	118	}
	119
	120	ret = mipi_dsi_dcs_set_display_off(dsi);
	121	if (ret < 0) {
	122	dev_err(dev, "Failed to set display off: %d\n", ret);
	123	return ret;
	124	}
	125	msleep(64);
	126
	127	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
	128	if (ret < 0) {
	129	dev_err(dev, "Failed to enter sleep mode: %d\n", ret);
	130	return ret;
	131	}
	132	msleep(120);
	133
	134	return 0;
	135	}
	136
	137	static int s6d7aa0_prepare(struct drm_panel *panel)
	138	{
	139	struct s6d7aa0 *ctx = panel_to_s6d7aa0(panel);
	140	struct device *dev = &ctx->dsi->dev;
	141	int ret;
	142
	143	ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
	144	if (ret < 0) {
	145	dev_err(dev, "Failed to enable regulators: %d\n", ret);
	146	return ret;
	147	}
	148
	149	s6d7aa0_reset(ctx);
	150
	151	ret = s6d7aa0_on(ctx);
	152	if (ret < 0) {
	153	dev_err(dev, "Failed to initialize panel: %d\n", ret);
	154	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
	155	return ret;
	156	}
	157
	158	return 0;
	159	}
	160
	161	static int s6d7aa0_disable(struct drm_panel *panel)
	162	{
	163	struct s6d7aa0 *ctx = panel_to_s6d7aa0(panel);
	164	struct device *dev = &ctx->dsi->dev;
	165	int ret;
	166
	167	ret = s6d7aa0_off(ctx);
	168	if (ret < 0)
	169	dev_err(dev, "Failed to un-initialize panel: %d\n", ret);
	170
	171	return 0;
	172	}
	173
	174	static int s6d7aa0_unprepare(struct drm_panel *panel)
	175	{
	176	struct s6d7aa0 *ctx = panel_to_s6d7aa0(panel);
	177
	178	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
	179	regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
	180
	181	return 0;
	182	}
	183
	184	/* Backlight control code */
	185
	186	static int s6d7aa0_bl_update_status(struct backlight_device *bl)
	187	{
	188	struct mipi_dsi_device *dsi = bl_get_data(bl);
	189	u16 brightness = backlight_get_brightness(bl);
	190	int ret;
	191
	192	ret = mipi_dsi_dcs_set_display_brightness(dsi, brightness);
	193	if (ret < 0)
	194	return ret;
	195
	196	return 0;
	197	}
	198
	199	static int s6d7aa0_bl_get_brightness(struct backlight_device *bl)
	200	{
	201	struct mipi_dsi_device *dsi = bl_get_data(bl);
	202	u16 brightness;
	203	int ret;
	204
	205	ret = mipi_dsi_dcs_get_display_brightness(dsi, &brightness);
	206	if (ret < 0)
	207	return ret;
	208
	209	return brightness & 0xff;
	210	}
	211
	212	static const struct backlight_ops s6d7aa0_bl_ops = {
	213	.update_status = s6d7aa0_bl_update_status,
	214	.get_brightness = s6d7aa0_bl_get_brightness,
	215	};
	216
	217	static struct backlight_device *
	218	s6d7aa0_create_backlight(struct mipi_dsi_device *dsi)
	219	{
	220	struct device *dev = &dsi->dev;
	221	const struct backlight_properties props = {
	222	.type = BACKLIGHT_RAW,
	223	.brightness = 255,
	224	.max_brightness = 255,
	225	};
	226
	227	return devm_backlight_device_register(dev, dev_name(dev), dev, dsi,
	228	&s6d7aa0_bl_ops, &props);
	229	}
	230
	231	/* Initialization code and structures for LSL080AL02 panel */
	232
	233	static int s6d7aa0_lsl080al02_init(struct s6d7aa0 *ctx)
	234	{
	235	struct mipi_dsi_device *dsi = ctx->dsi;
	236	struct device *dev = &dsi->dev;
	237	int ret;
	238
	239	usleep_range(20000, 25000);
	240
	241	ret = s6d7aa0_lock(ctx, false);
	242	if (ret < 0) {
	243	dev_err(dev, "Failed to unlock registers: %d\n", ret);
	244	return ret;
	245	}
	246
	247	mipi_dsi_dcs_write_seq(dsi, MCS_OTP_RELOAD, 0x00, 0x10);
	248	usleep_range(1000, 1500);
	249
	250	/* SEQ_B6_PARAM_8_R01 */
	251	mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x10);
	252
	253	/* BL_CTL_ON */
	254	mipi_dsi_dcs_write_seq(dsi, MCS_BL_CTL, 0x40, 0x00, 0x28);
	255
	256	usleep_range(5000, 6000);
	257
	258	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x04);
	259
	260	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
	261	if (ret < 0) {
	262	dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
	263	return ret;
	264	}
	265
	266	msleep(120);
	267	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	268
	269	ret = s6d7aa0_lock(ctx, true);
	270	if (ret < 0) {
	271	dev_err(dev, "Failed to lock registers: %d\n", ret);
	272	return ret;
	273	}
	274
	275	ret = mipi_dsi_dcs_set_display_on(dsi);
	276	if (ret < 0) {
	277	dev_err(dev, "Failed to set display on: %d\n", ret);
	278	return ret;
	279	}
	280
	281	return 0;
	282	}
	283
	284	static int s6d7aa0_lsl080al02_off(struct s6d7aa0 *ctx)
	285	{
	286	struct mipi_dsi_device *dsi = ctx->dsi;
	287
	288	/* BL_CTL_OFF */
	289	mipi_dsi_dcs_write_seq(dsi, MCS_BL_CTL, 0x40, 0x00, 0x20);
	290
	291	return 0;
	292	}
	293
	294	static const struct drm_display_mode s6d7aa0_lsl080al02_mode = {
	295	.clock = (800 + 16 + 4 + 140) * (1280 + 8 + 4 + 4) * 60 / 1000,
	296	.hdisplay = 800,
	297	.hsync_start = 800 + 16,
	298	.hsync_end = 800 + 16 + 4,
	299	.htotal = 800 + 16 + 4 + 140,
	300	.vdisplay = 1280,
	301	.vsync_start = 1280 + 8,
	302	.vsync_end = 1280 + 8 + 4,
	303	.vtotal = 1280 + 8 + 4 + 4,
	304	.width_mm = 108,
	305	.height_mm = 173,
	306	};
	307
	308	static const struct s6d7aa0_panel_desc s6d7aa0_lsl080al02_desc = {
	309	.panel_type = S6D7AA0_PANEL_LSL080AL02,
	310	.init_func = s6d7aa0_lsl080al02_init,
	311	.off_func = s6d7aa0_lsl080al02_off,
	312	.drm_mode = &s6d7aa0_lsl080al02_mode,
	313	.mode_flags = MIPI_DSI_MODE_VSYNC_FLUSH \| MIPI_DSI_MODE_VIDEO_NO_HFP,
	314	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
	315
	316	.has_backlight = false,
	317	.use_passwd3 = false,
	318	};
	319
	320	/* Initialization code and structures for LSL080AL03 panel */
	321
	322	static int s6d7aa0_lsl080al03_init(struct s6d7aa0 *ctx)
	323	{
	324	struct mipi_dsi_device *dsi = ctx->dsi;
	325	struct device *dev = &dsi->dev;
	326	int ret;
	327
	328	usleep_range(20000, 25000);
	329
	330	ret = s6d7aa0_lock(ctx, false);
	331	if (ret < 0) {
	332	dev_err(dev, "Failed to unlock registers: %d\n", ret);
	333	return ret;
	334	}
	335
	336	if (ctx->desc->panel_type == S6D7AA0_PANEL_LSL080AL03) {
	337	mipi_dsi_dcs_write_seq(dsi, MCS_BL_CTL, 0xc7, 0x00, 0x29);
	338	mipi_dsi_dcs_write_seq(dsi, 0xbc, 0x01, 0x4e, 0xa0);
	339	mipi_dsi_dcs_write_seq(dsi, 0xfd, 0x16, 0x10, 0x11, 0x23,
	340	0x09);
	341	mipi_dsi_dcs_write_seq(dsi, 0xfe, 0x00, 0x02, 0x03, 0x21,
	342	0x80, 0x78);
	343	} else if (ctx->desc->panel_type == S6D7AA0_PANEL_LTL101AT01) {
	344	mipi_dsi_dcs_write_seq(dsi, MCS_BL_CTL, 0x40, 0x00, 0x08);
	345	mipi_dsi_dcs_write_seq(dsi, 0xbc, 0x01, 0x4e, 0x0b);
	346	mipi_dsi_dcs_write_seq(dsi, 0xfd, 0x16, 0x10, 0x11, 0x23,
	347	0x09);
	348	mipi_dsi_dcs_write_seq(dsi, 0xfe, 0x00, 0x02, 0x03, 0x21,
	349	0x80, 0x68);
	350	}
	351
	352	mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x51);
	353	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24);
	354	mipi_dsi_dcs_write_seq(dsi, 0xf2, 0x02, 0x08, 0x08);
	355
	356	usleep_range(10000, 11000);
	357
	358	mipi_dsi_dcs_write_seq(dsi, 0xc0, 0x80, 0x80, 0x30);
	359	mipi_dsi_dcs_write_seq(dsi, 0xcd,
	360	0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e,
	361	0x2e, 0x2e, 0x2e, 0x2e, 0x2e);
	362	mipi_dsi_dcs_write_seq(dsi, 0xce,
	363	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	364	0x00, 0x00, 0x00, 0x00, 0x00);
	365	mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x03);
	366
	367	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
	368	if (ret < 0) {
	369	dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
	370	return ret;
	371	}
	372
	373	ret = s6d7aa0_lock(ctx, true);
	374	if (ret < 0) {
	375	dev_err(dev, "Failed to lock registers: %d\n", ret);
	376	return ret;
	377	}
	378
	379	ret = mipi_dsi_dcs_set_display_on(dsi);
	380	if (ret < 0) {
	381	dev_err(dev, "Failed to set display on: %d\n", ret);
	382	return ret;
	383	}
	384
	385	return 0;
	386	}
	387
	388	static int s6d7aa0_lsl080al03_off(struct s6d7aa0 *ctx)
	389	{
	390	struct mipi_dsi_device *dsi = ctx->dsi;
	391
	392	mipi_dsi_dcs_write_seq(dsi, 0x22, 0x00);
	393
	394	return 0;
	395	}
	396
	397	static const struct drm_display_mode s6d7aa0_lsl080al03_mode = {
	398	.clock = (768 + 18 + 16 + 126) * (1024 + 8 + 2 + 6) * 60 / 1000,
	399	.hdisplay = 768,
	400	.hsync_start = 768 + 18,
	401	.hsync_end = 768 + 18 + 16,
	402	.htotal = 768 + 18 + 16 + 126,
	403	.vdisplay = 1024,
	404	.vsync_start = 1024 + 8,
	405	.vsync_end = 1024 + 8 + 2,
	406	.vtotal = 1024 + 8 + 2 + 6,
	407	.width_mm = 122,
	408	.height_mm = 163,
	409	};
	410
	411	static const struct s6d7aa0_panel_desc s6d7aa0_lsl080al03_desc = {
	412	.panel_type = S6D7AA0_PANEL_LSL080AL03,
	413	.init_func = s6d7aa0_lsl080al03_init,
	414	.off_func = s6d7aa0_lsl080al03_off,
	415	.drm_mode = &s6d7aa0_lsl080al03_mode,
	416	.mode_flags = MIPI_DSI_MODE_NO_EOT_PACKET,
	417	.bus_flags = 0,
	418
	419	.has_backlight = true,
	420	.use_passwd3 = true,
	421	};
	422
	423	/* Initialization structures for LTL101AT01 panel */
	424
	425	static const struct drm_display_mode s6d7aa0_ltl101at01_mode = {
	426	.clock = (768 + 96 + 16 + 184) * (1024 + 8 + 2 + 6) * 60 / 1000,
	427	.hdisplay = 768,
	428	.hsync_start = 768 + 96,
	429	.hsync_end = 768 + 96 + 16,
	430	.htotal = 768 + 96 + 16 + 184,
	431	.vdisplay = 1024,
	432	.vsync_start = 1024 + 8,
	433	.vsync_end = 1024 + 8 + 2,
	434	.vtotal = 1024 + 8 + 2 + 6,
	435	.width_mm = 148,
	436	.height_mm = 197,
	437	};
	438
	439	static const struct s6d7aa0_panel_desc s6d7aa0_ltl101at01_desc = {
	440	.panel_type = S6D7AA0_PANEL_LTL101AT01,
	441	.init_func = s6d7aa0_lsl080al03_init, /* Similar init to LSL080AL03 */
	442	.off_func = s6d7aa0_lsl080al03_off,
	443	.drm_mode = &s6d7aa0_ltl101at01_mode,
	444	.mode_flags = MIPI_DSI_MODE_NO_EOT_PACKET,
	445	.bus_flags = 0,
	446
	447	.has_backlight = true,
	448	.use_passwd3 = true,
	449	};
	450
	451	static int s6d7aa0_get_modes(struct drm_panel *panel,
	452	struct drm_connector *connector)
	453	{
	454	struct drm_display_mode *mode;
	455	struct s6d7aa0 *ctx;
	456
	457	ctx = container_of(panel, struct s6d7aa0, panel);
	458	if (!ctx)
	459	return -EINVAL;
	460
	461	mode = drm_mode_duplicate(connector->dev, ctx->desc->drm_mode);
	462	if (!mode)
	463	return -ENOMEM;
	464
	465	drm_mode_set_name(mode);
	466
	467	mode->type = DRM_MODE_TYPE_DRIVER \| DRM_MODE_TYPE_PREFERRED;
	468	connector->display_info.width_mm = mode->width_mm;
	469	connector->display_info.height_mm = mode->height_mm;
	470	connector->display_info.bus_flags = ctx->desc->bus_flags;
	471	drm_mode_probed_add(connector, mode);
	472
	473	return 1;
	474	}
	475
	476	static const struct drm_panel_funcs s6d7aa0_panel_funcs = {
	477	.disable = s6d7aa0_disable,
	478	.prepare = s6d7aa0_prepare,
	479	.unprepare = s6d7aa0_unprepare,
	480	.get_modes = s6d7aa0_get_modes,
	481	};
	482
	483	static int s6d7aa0_probe(struct mipi_dsi_device *dsi)
	484	{
	485	struct device *dev = &dsi->dev;
	486	struct s6d7aa0 *ctx;
	487	int ret;
	488
	489	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
	490	if (!ctx)
	491	return -ENOMEM;
	492
	493	ctx->desc = of_device_get_match_data(dev);
	494	if (!ctx->desc)
	495	return -ENODEV;
	496
	497	ctx->supplies[0].supply = "power";
	498	ctx->supplies[1].supply = "vmipi";
	499	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
	500	ctx->supplies);
	501	if (ret < 0)
	502	return dev_err_probe(dev, ret, "Failed to get regulators\n");
	503
	504	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
	505	if (IS_ERR(ctx->reset_gpio))
	506	return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
	507	"Failed to get reset-gpios\n");
	508
	509	ctx->dsi = dsi;
	510	mipi_dsi_set_drvdata(dsi, ctx);
	511
	512	dsi->lanes = 4;
	513	dsi->format = MIPI_DSI_FMT_RGB888;
	514	dsi->mode_flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_MODE_VIDEO_BURST
	515	\| ctx->desc->mode_flags;
	516
	517	drm_panel_init(&ctx->panel, dev, &s6d7aa0_panel_funcs,
	518	DRM_MODE_CONNECTOR_DSI);
	519	ctx->panel.prepare_prev_first = true;
	520
	521	ret = drm_panel_of_backlight(&ctx->panel);
	522	if (ret)
	523	return dev_err_probe(dev, ret, "Failed to get backlight\n");
	524
	525	/* Use DSI-based backlight as fallback if available */
	526	if (ctx->desc->has_backlight && !ctx->panel.backlight) {
	527	ctx->panel.backlight = s6d7aa0_create_backlight(dsi);
	528	if (IS_ERR(ctx->panel.backlight))
	529	return dev_err_probe(dev, PTR_ERR(ctx->panel.backlight),
	530	"Failed to create backlight\n");
	531	}
	532
	533	drm_panel_add(&ctx->panel);
	534
	535	ret = mipi_dsi_attach(dsi);
	536	if (ret < 0) {
	537	dev_err(dev, "Failed to attach to DSI host: %d\n", ret);
	538	drm_panel_remove(&ctx->panel);
	539	return ret;
	540	}
	541
	542	return 0;
	543	}
	544
	545	static void s6d7aa0_remove(struct mipi_dsi_device *dsi)
	546	{
	547	struct s6d7aa0 *ctx = mipi_dsi_get_drvdata(dsi);
	548	int ret;
	549
	550	ret = mipi_dsi_detach(dsi);
	551	if (ret < 0)
	552	dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
	553
	554	drm_panel_remove(&ctx->panel);
	555	}
	556
	557	static const struct of_device_id s6d7aa0_of_match[] = {
	558	{
	559	.compatible = "samsung,lsl080al02",
	560	.data = &s6d7aa0_lsl080al02_desc
	561	},
	562	{
	563	.compatible = "samsung,lsl080al03",
	564	.data = &s6d7aa0_lsl080al03_desc
	565	},
	566	{
	567	.compatible = "samsung,ltl101at01",
	568	.data = &s6d7aa0_ltl101at01_desc
	569	},
	570	{ /* sentinel */ }
	571	};
	572
	573	static struct mipi_dsi_driver s6d7aa0_driver = {
	574	.probe = s6d7aa0_probe,
	575	.remove = s6d7aa0_remove,
	576	.driver = {
	577	.name = "panel-samsung-s6d7aa0",
	578	.of_match_table = s6d7aa0_of_match,
	579	},
	580	};
	581	module_mipi_dsi_driver(s6d7aa0_driver);
	582
	583	MODULE_AUTHOR("Artur Weber <aweber.kernel@gmail.com>");
	584	MODULE_DESCRIPTION("Samsung S6D7AA0 MIPI-DSI LCD controller driver");
	585	MODULE_LICENSE("GPL");

drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c+6−37

 	struct gpio_desc *reset_gpio;
 	bool prepared;
-	bool enabled;
-	const struct drm_display_mode *mode;
 };
 static inline struct sharp_nt_panel *to_sharp_nt_panel(struct drm_panel *panel)
 	return 0;
 }
-static int sharp_nt_panel_disable(struct drm_panel *panel)
-{
-	struct sharp_nt_panel *sharp_nt = to_sharp_nt_panel(panel);
-	if (!sharp_nt->enabled)
-		return 0;
-	sharp_nt->enabled = false;
-	return 0;
-}
 static int sharp_nt_panel_unprepare(struct drm_panel *panel)
 {
 	struct sharp_nt_panel *sharp_nt = to_sharp_nt_panel(panel);
 	return ret;
 }
-static int sharp_nt_panel_enable(struct drm_panel *panel)
-{
-	struct sharp_nt_panel *sharp_nt = to_sharp_nt_panel(panel);
-	if (sharp_nt->enabled)
-		return 0;
-	sharp_nt->enabled = true;
-	return 0;
-}
 static const struct drm_display_mode default_mode = {
-	.clock = 41118,
+	.clock = (540 + 48 + 32 + 80) * (960 + 3 + 10 + 15) * 60 / 1000,
 	.hdisplay = 540,
 	.hsync_start = 540 + 48,
-	.hsync_end = 540 + 48 + 80,
+	.hsync_end = 540 + 48 + 32,
-	.htotal = 540 + 48 + 80 + 32,
+	.htotal = 540 + 48 + 32 + 80,
 	.vdisplay = 960,
 	.vsync_start = 960 + 3,
-	.vsync_end = 960 + 3 + 15,
+	.vsync_end = 960 + 3 + 10,
-	.vtotal = 960 + 3 + 15 + 1,
+	.vtotal = 960 + 3 + 10 + 15,
 };
 static int sharp_nt_panel_get_modes(struct drm_panel *panel,
 }
 static const struct drm_panel_funcs sharp_nt_panel_funcs = {
-	.disable = sharp_nt_panel_disable,
 	.unprepare = sharp_nt_panel_unprepare,
 	.prepare = sharp_nt_panel_prepare,
-	.enable = sharp_nt_panel_enable,
 	.get_modes = sharp_nt_panel_get_modes,
 };
 	struct device *dev = &sharp_nt->dsi->dev;
 	int ret;
-	sharp_nt->mode = &default_mode;
 	sharp_nt->supply = devm_regulator_get(dev, "avdd");
 	if (IS_ERR(sharp_nt->supply))
 		return PTR_ERR(sharp_nt->supply);
 	dsi->lanes = 2;
 	dsi->format = MIPI_DSI_FMT_RGB888;
 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
+			MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
 			MIPI_DSI_MODE_VIDEO_HSE |
 			MIPI_DSI_CLOCK_NON_CONTINUOUS |
 			MIPI_DSI_MODE_NO_EOT_PACKET;

drivers/gpu/drm/panel/panel-simple.c+69−0

@@ -1211,6 +1211,37 @@ static const struct panel_desc bananapi_s070wv20_ct16 = { · 1210 unmodified lines
1211	},	1211	},
1212	};	1212	};
1213		1213
		1214	static const struct display_timing boe_ev121wxm_n10_1850_timing = {
		1215	.pixelclock = { 69922000, 71000000, 72293000 },
		1216	.hactive = { 1280, 1280, 1280 },
		1217	.hfront_porch = { 48, 48, 48 },
		1218	.hback_porch = { 80, 80, 80 },
		1219	.hsync_len = { 32, 32, 32 },
		1220	.vactive = { 800, 800, 800 },
		1221	.vfront_porch = { 3, 3, 3 },
		1222	.vback_porch = { 14, 14, 14 },
		1223	.vsync_len = { 6, 6, 6 },
		1224	};
		1225
		1226	static const struct panel_desc boe_ev121wxm_n10_1850 = {
		1227	.timings = &boe_ev121wxm_n10_1850_timing,
		1228	.num_timings = 1,
		1229	.bpc = 8,
		1230	.size = {
		1231	.width = 261,
		1232	.height = 163,
		1233	},
		1234	.delay = {
		1235	.prepare = 9,
		1236	.enable = 300,
		1237	.unprepare = 300,
		1238	.disable = 560,
		1239	},
		1240	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
		1241	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
		1242	.connector_type = DRM_MODE_CONNECTOR_LVDS,
		1243	};
		1244
1214	static const struct drm_display_mode boe_hv070wsa_mode = {	1245	static const struct drm_display_mode boe_hv070wsa_mode = {
1215	.clock = 42105,	1246	.clock = 42105,
1216	.hdisplay = 1024,	1247	.hdisplay = 1024,
@@ -2142,6 +2173,38 @@ static const struct panel_desc innolux_at070tn92 = { · 925 unmodified lines
2142	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,	2173	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2143	};	2174	};
2144		2175
		2176	static const struct display_timing innolux_g070ace_l01_timing = {
		2177	.pixelclock = { 25200000, 35000000, 35700000 },
		2178	.hactive = { 800, 800, 800 },
		2179	.hfront_porch = { 30, 32, 87 },
		2180	.hback_porch = { 30, 32, 87 },
		2181	.hsync_len = { 1, 1, 1 },
		2182	.vactive = { 480, 480, 480 },
		2183	.vfront_porch = { 3, 3, 3 },
		2184	.vback_porch = { 13, 13, 13 },
		2185	.vsync_len = { 1, 1, 4 },
		2186	.flags = DISPLAY_FLAGS_DE_HIGH,
		2187	};
		2188
		2189	static const struct panel_desc innolux_g070ace_l01 = {
		2190	.timings = &innolux_g070ace_l01_timing,
		2191	.num_timings = 1,
		2192	.bpc = 8,
		2193	.size = {
		2194	.width = 152,
		2195	.height = 91,
		2196	},
		2197	.delay = {
		2198	.prepare = 10,
		2199	.enable = 50,
		2200	.disable = 50,
		2201	.unprepare = 500,
		2202	},
		2203	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
		2204	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
		2205	.connector_type = DRM_MODE_CONNECTOR_LVDS,
		2206	};
		2207
2145	static const struct display_timing innolux_g070y2_l01_timing = {	2208	static const struct display_timing innolux_g070y2_l01_timing = {
2146	.pixelclock = { 28000000, 29500000, 32000000 },	2209	.pixelclock = { 28000000, 29500000, 32000000 },
2147	.hactive = { 800, 800, 800 },	2210	.hactive = { 800, 800, 800 },
@@ -3984,6 +4047,9 @@ static const struct of_device_id platform_of_match[] = { · 1836 unmodified lines
3984	}, {	4047	}, {
3985	.compatible = "bananapi,s070wv20-ct16",	4048	.compatible = "bananapi,s070wv20-ct16",
3986	.data = &bananapi_s070wv20_ct16,	4049	.data = &bananapi_s070wv20_ct16,
		4050	}, {
		4051	.compatible = "boe,ev121wxm-n10-1850",
		4052	.data = &boe_ev121wxm_n10_1850,
3987	}, {	4053	}, {
3988	.compatible = "boe,hv070wsa-100",	4054	.compatible = "boe,hv070wsa-100",
3989	.data = &boe_hv070wsa	4055	.data = &boe_hv070wsa
@@ -4098,6 +4164,9 @@ static const struct of_device_id platform_of_match[] = { · 108 unmodified lines
4098	}, {	4164	}, {
4099	.compatible = "innolux,at070tn92",	4165	.compatible = "innolux,at070tn92",
4100	.data = &innolux_at070tn92,	4166	.data = &innolux_at070tn92,
		4167	}, {
		4168	.compatible = "innolux,g070ace-l01",
		4169	.data = &innolux_g070ace_l01,
4101	}, {	4170	}, {
4102	.compatible = "innolux,g070y2-l01",	4171	.compatible = "innolux,g070y2-l01",
4103	.data = &innolux_g070y2_l01,	4172	.data = &innolux_g070y2_l01,

drivers/gpu/drm/panel/panel-sitronix-st7703.c+99−3

@@ -28,6 +28,7 @@ · 27 unmodified lines
28	/* Manufacturer specific Commands send via DSI */	28	/* Manufacturer specific Commands send via DSI */
29	#define ST7703_CMD_ALL_PIXEL_OFF 0x22	29	#define ST7703_CMD_ALL_PIXEL_OFF 0x22
30	#define ST7703_CMD_ALL_PIXEL_ON 0x23	30	#define ST7703_CMD_ALL_PIXEL_ON 0x23
		31	#define ST7703_CMD_SETAPID 0xB1
31	#define ST7703_CMD_SETDISP 0xB2	32	#define ST7703_CMD_SETDISP 0xB2
32	#define ST7703_CMD_SETRGBIF 0xB3	33	#define ST7703_CMD_SETRGBIF 0xB3
33	#define ST7703_CMD_SETCYC 0xB4	34	#define ST7703_CMD_SETCYC 0xB4
@@ -41,12 +42,15 @@ · 7 unmodified lines
41	#define ST7703_CMD_UNKNOWN_BF 0xBF	42	#define ST7703_CMD_UNKNOWN_BF 0xBF
42	#define ST7703_CMD_SETSCR 0xC0	43	#define ST7703_CMD_SETSCR 0xC0
43	#define ST7703_CMD_SETPOWER 0xC1	44	#define ST7703_CMD_SETPOWER 0xC1
		45	#define ST7703_CMD_SETECO 0xC6
		46	#define ST7703_CMD_SETIO 0xC7
		47	#define ST7703_CMD_SETCABC 0xC8
44	#define ST7703_CMD_SETPANEL 0xCC	48	#define ST7703_CMD_SETPANEL 0xCC
45	#define ST7703_CMD_UNKNOWN_C6 0xC6
46	#define ST7703_CMD_SETGAMMA 0xE0	49	#define ST7703_CMD_SETGAMMA 0xE0
47	#define ST7703_CMD_SETEQ 0xE3	50	#define ST7703_CMD_SETEQ 0xE3
48	#define ST7703_CMD_SETGIP1 0xE9	51	#define ST7703_CMD_SETGIP1 0xE9
49	#define ST7703_CMD_SETGIP2 0xEA	52	#define ST7703_CMD_SETGIP2 0xEA
		53	#define ST7703_CMD_UNKNOWN_EF 0xEF
50		54
51	struct st7703 {	55	struct st7703 {
52	struct device *dev;	56	struct device *dev;
@@ -249,8 +253,7 @@ static int xbd599_init_sequence(struct st7703 *ctx) · 196 unmodified lines
249	* ESD_DET_TIME_SEL = 0 frames	253	* ESD_DET_TIME_SEL = 0 frames
250	*/);	254	*/);
251		255
252	/* Undocumented command. */	256	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETECO, 0x01, 0x00, 0xFF, 0xFF, 0x00);
253	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_C6, 0x01, 0x00, 0xFF, 0xFF, 0x00);
254		257
255	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER,	258	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER,
256	0x74, /* VBTHS, VBTLS: VGH = 17V, VBL = -11V */	259	0x74, /* VBTHS, VBTLS: VGH = 17V, VBL = -11V */
@@ -338,6 +341,98 @@ static const struct st7703_panel_desc xbd599_desc = { · 81 unmodified lines
338	.init_sequence = xbd599_init_sequence,	341	.init_sequence = xbd599_init_sequence,
339	};	342	};
340		343
		344	static int rg353v2_init_sequence(struct st7703 *ctx)
		345	{
		346	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
		347
		348	/*
		349	* Init sequence was supplied by the panel vendor.
		350	*/
		351
		352	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83);
		353	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00,
		354	0xda, 0x80);
		355	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0x00, 0x13, 0x70);
		356	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28,
		357	0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00);
		358	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
		359	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x0a, 0x0a);
		360	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x92, 0x92);
		361	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22,
		362	0xf0, 0x63);
		363	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05,
		364	0xf9, 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00,
		365	0x00, 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a,
		366	0x00, 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37);
		367	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x47);
		368	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
		369	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50,
		370	0x00, 0x00, 0x12, 0x50, 0x00);
		371	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x53, 0xc0, 0x32,
		372	0x32, 0x77, 0xe1, 0xdd, 0xdd, 0x77, 0x77, 0x33,
		373	0x33);
		374	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff,
		375	0x00, 0xff);
		376	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00,
		377	0x00, 0x00);
		378	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e,
		379	0x02);
		380	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b);
		381	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0d,
		382	0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c, 0x0d,
		383	0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a, 0x00, 0x07,
		384	0x0d, 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c,
		385	0x0d, 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a);
		386	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b,
		387	0x0b, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00,
		388	0xc0, 0x10);
		389	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x02, 0x00,
		390	0x00, 0xb0, 0xb1, 0x11, 0x31, 0x23, 0x28, 0x80,
		391	0xb0, 0xb1, 0x27, 0x08, 0x00, 0x04, 0x02, 0x00,
		392	0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00,
		393	0x88, 0x88, 0xba, 0x60, 0x24, 0x08, 0x88, 0x88,
		394	0x88, 0x88, 0x88, 0x88, 0x88, 0xba, 0x71, 0x35,
		395	0x18, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00,
		396	0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		397	0x00, 0x00, 0x00);
		398	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02,
		399	0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		400	0x81, 0x88, 0xba, 0x17, 0x53, 0x88, 0x88, 0x88,
		401	0x88, 0x88, 0x88, 0x80, 0x88, 0xba, 0x06, 0x42,
		402	0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x00,
		403	0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
		404	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		405	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		406	0x00);
		407	mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01);
		408
		409	return 0;
		410	}
		411
		412	static const struct drm_display_mode rg353v2_mode = {
		413	.hdisplay = 640,
		414	.hsync_start = 640 + 40,
		415	.hsync_end = 640 + 40 + 2,
		416	.htotal = 640 + 40 + 2 + 80,
		417	.vdisplay = 480,
		418	.vsync_start = 480 + 18,
		419	.vsync_end = 480 + 18 + 2,
		420	.vtotal = 480 + 18 + 2 + 28,
		421	.clock = 24150,
		422	.flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
		423	.width_mm = 70,
		424	.height_mm = 57,
		425	};
		426
		427	static const struct st7703_panel_desc rg353v2_desc = {
		428	.mode = &rg353v2_mode,
		429	.lanes = 4,
		430	.mode_flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_MODE_VIDEO_BURST \|
		431	MIPI_DSI_MODE_NO_EOT_PACKET \| MIPI_DSI_MODE_LPM,
		432	.format = MIPI_DSI_FMT_RGB888,
		433	.init_sequence = rg353v2_init_sequence,
		434	};
		435
341	static int st7703_enable(struct drm_panel *panel)	436	static int st7703_enable(struct drm_panel *panel)
342	{	437	{
343	struct st7703 *ctx = panel_to_st7703(panel);	438	struct st7703 *ctx = panel_to_st7703(panel);
@@ -598,6 +693,7 @@ static void st7703_remove(struct mipi_dsi_device *dsi) · 254 unmodified lines
598	}	693	}
599		694
600	static const struct of_device_id st7703_of_match[] = {	695	static const struct of_device_id st7703_of_match[] = {
		696	{ .compatible = "anbernic,rg353v-panel-v2", .data = &rg353v2_desc },
601	{ .compatible = "rocktech,jh057n00900", .data = &jh057n00900_panel_desc },	697	{ .compatible = "rocktech,jh057n00900", .data = &jh057n00900_panel_desc },
602	{ .compatible = "xingbangda,xbd599", .data = &xbd599_desc },	698	{ .compatible = "xingbangda,xbd599", .data = &xbd599_desc },
603	{ /* sentinel */ }	699	{ /* sentinel */ }

drivers/gpu/drm/rockchip/cdn-dp-core.c+2−3

 				  edid->width_cm, edid->height_cm);
 		dp->sink_has_audio = drm_detect_monitor_audio(edid);
+		drm_connector_update_edid_property(connector, edid);
 		ret = drm_add_edid_modes(connector, edid);
-		if (ret)
-			drm_connector_update_edid_property(connector,
-								edid);
 	}
 	mutex_unlock(&dp->lock);

drivers/gpu/drm/rockchip/rockchip_drm_drv.c+1−1

@@ -140,7 +140,7 @@ static int rockchip_drm_bind(struct device *dev) · 139 unmodified lines
140	int ret;	140	int ret;
141		141
142	/* Remove existing drivers that may own the framebuffer memory. */	142	/* Remove existing drivers that may own the framebuffer memory. */
143	ret = drm_aperture_remove_framebuffers(false, &rockchip_drm_driver);	143	ret = drm_aperture_remove_framebuffers(&rockchip_drm_driver);
144	if (ret) {	144	if (ret) {
145	DRM_DEV_ERROR(dev,	145	DRM_DEV_ERROR(dev,
146	"Failed to remove existing framebuffers - %d.\n",	146	"Failed to remove existing framebuffers - %d.\n",

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include/asm-generic/fb.h+124−2

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include/drm/i915_component.h+2−1

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include/drm/i915_gsc_proxy_mei_interface.h+53−0

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include/uapi/drm/drm_mode.h+5−0

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include/uapi/drm/i915_drm.h+50−1

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include/video/sticore.hrenamed from drivers/video/fbdev/sticore.h+9−7

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tools/testing/selftests/netfilter/nft_flowtable.sh+139−6

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Merge drm/drm-next into drm-intel-next

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