We add a config for user to enable or disable this feature. It can be used to control the hardware prefetch function.
Unified · Split
| @@ -177,6 +177,13 @@ config CACHE_L2 · 176 unmodified lines | |||
| 177 | Say Y here to enable L2 cache if your SoC are integrated with L2CC. | 177 | Say Y here to enable L2 cache if your SoC are integrated with L2CC. |
| 178 | If unsure, say N. | 178 | If unsure, say N. |
| 179 | 179 | ||
| 180 | config HW_PRE | ||
| 181 | bool "Enable hardware prefetcher" | ||
| 182 | default y | ||
| 183 | help | ||
| 184 | Say Y here to enable hardware prefetcher feature. | ||
| 185 | Only when CPU_VER.REV >= 0x09 can support. | ||
| 186 | |||
| 180 | menu "Memory configuration" | 187 | menu "Memory configuration" |
| 181 | 188 | ||
| 182 | choice | 189 | choice |
| @@ -740,14 +740,20 @@ · 739 unmodified lines | |||
| 740 | #define N13MISC_CTL_offRTP 1 /* Disable Return Target Predictor */ | 740 | #define N13MISC_CTL_offRTP 1 /* Disable Return Target Predictor */ |
| 741 | #define N13MISC_CTL_offPTEPF 2 /* Disable HPTWK L2 PTE pefetch */ | 741 | #define N13MISC_CTL_offPTEPF 2 /* Disable HPTWK L2 PTE pefetch */ |
| 742 | #define N13MISC_CTL_offSP_SHADOW_EN 4 /* Enable shadow stack pointers */ | 742 | #define N13MISC_CTL_offSP_SHADOW_EN 4 /* Enable shadow stack pointers */ |
| 743 | #define MISC_CTL_offHWPRE 11 /* Enable HardWare PREFETCH */ | ||
| 743 | /* bit 6, 9:31 reserved */ | 744 | /* bit 6, 9:31 reserved */ |
| 744 | 745 | ||
| 745 | #define N13MISC_CTL_makBTB ( 0x1 << N13MISC_CTL_offBTB ) | 746 | #define N13MISC_CTL_makBTB ( 0x1 << N13MISC_CTL_offBTB ) |
| 746 | #define N13MISC_CTL_makRTP ( 0x1 << N13MISC_CTL_offRTP ) | 747 | #define N13MISC_CTL_makRTP ( 0x1 << N13MISC_CTL_offRTP ) |
| 747 | #define N13MISC_CTL_makPTEPF ( 0x1 << N13MISC_CTL_offPTEPF ) | 748 | #define N13MISC_CTL_makPTEPF ( 0x1 << N13MISC_CTL_offPTEPF ) |
| 748 | #define N13MISC_CTL_makSP_SHADOW_EN ( 0x1 << N13MISC_CTL_offSP_SHADOW_EN ) | 749 | #define N13MISC_CTL_makSP_SHADOW_EN ( 0x1 << N13MISC_CTL_offSP_SHADOW_EN ) |
| 750 | #define MISC_CTL_makHWPRE_EN ( 0x1 << MISC_CTL_offHWPRE ) | ||
| 749 | 751 | ||
| 752 | #ifdef CONFIG_HW_PRE | ||
| 753 | #define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN|MISC_CTL_makHWPRE_EN) | ||
| 754 | #else | ||
| 750 | #define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN) | 755 | #define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN) |
| 756 | #endif | ||
| 751 | 757 | ||
| 752 | /****************************************************************************** | 758 | /****************************************************************************** |
| 753 | * PRUSR_ACC_CTL (Privileged Resource User Access Control Registers) | 759 | * PRUSR_ACC_CTL (Privileged Resource User Access Control Registers) |
| @@ -151,7 +151,7 @@ _tlb: · 150 unmodified lines | |||
| 151 | #endif | 151 | #endif |
| 152 | mtsr $r3, $TLB_MISC | 152 | mtsr $r3, $TLB_MISC |
| 153 | 153 | ||
| 154 | mfsr $r0, $MISC_CTL ! Enable BTB and RTP and shadow sp | 154 | mfsr $r0, $MISC_CTL ! Enable BTB, RTP, shadow sp, and HW_PRE |
| 155 | ori $r0, $r0, #MISC_init | 155 | ori $r0, $r0, #MISC_init |
| 156 | mtsr $r0, $MISC_CTL | 156 | mtsr $r0, $MISC_CTL |
| 157 | 157 | ||
| @@ -39,6 +39,7 @@ · 38 unmodified lines | |||
| 39 | #define HWCAP_FPU_DP 0x040000 | 39 | #define HWCAP_FPU_DP 0x040000 |
| 40 | #define HWCAP_V2 0x080000 | 40 | #define HWCAP_V2 0x080000 |
| 41 | #define HWCAP_DX_REGS 0x100000 | 41 | #define HWCAP_DX_REGS 0x100000 |
| 42 | #define HWCAP_HWPRE 0x200000 | ||
| 42 | 43 | ||
| 43 | unsigned long cpu_id, cpu_rev, cpu_cfgid; | 44 | unsigned long cpu_id, cpu_rev, cpu_cfgid; |
| 44 | bool has_fpu = false; | 45 | bool has_fpu = false; |
| @@ -75,6 +76,7 @@ static const char *hwcap_str[] = { · 30 unmodified lines | |||
| 75 | "fpu_dp", | 76 | "fpu_dp", |
| 76 | "v2", | 77 | "v2", |
| 77 | "dx_regs", | 78 | "dx_regs", |
| 79 | "hw_pre", | ||
| 78 | NULL, | 80 | NULL, |
| 79 | }; | 81 | }; |
| 80 | 82 | ||
| @@ -221,6 +223,11 @@ static void __init setup_cpuinfo(void) · 140 unmodified lines | |||
| 221 | if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C) | 223 | if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C) |
| 222 | elf_hwcap |= HWCAP_L2C; | 224 | elf_hwcap |= HWCAP_L2C; |
| 223 | 225 | ||
| 226 | #ifdef CONFIG_HW_PRE | ||
| 227 | if (__nds32__mfsr(NDS32_SR_MISC_CTL) & MISC_CTL_makHWPRE_EN) | ||
| 228 | elf_hwcap |= HWCAP_HWPRE; | ||
| 229 | #endif | ||
| 230 | |||
| 224 | tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL); | 231 | tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL); |
| 225 | if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE)) | 232 | if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE)) |
| 226 | tmp |= CACHE_CTL_mskDC_EN; | 233 | tmp |= CACHE_CTL_mskDC_EN; |