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pinctrl/msm: Setup GPIO chip in hierarchy

Some GPIOs are marked as wakeup capable and are routed to another interrupt controller that is an always-domain and can detect interrupts even when most of the SoC is powered off. The wakeup interrupt controller wakes up the GIC and replays the interrupt at the GIC. Setup the TLMM irqchip in hierarchy with the wakeup interrupt controller and ensure the wakeup GPIOs are handled correctly. Co-developed-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1573855915-9841-9-git-send-email-ilina@codeaurora.org ---- Changes in v2: - Address review comments - Fix Co-developed-by tag Changes in v1: - Address minor review comments - Remove redundant call to set irq handler - Move irq_domain_qcom_handle_wakeup() to this patch Changes in RFC v2: - Rebase on top of GPIO hierarchy support in linux-next - Set the chained irq handler for summary line

Lina Iyer committed 7 years ago

Commit e35a6ae1 parent e71374c3 files · +137 −2Browse files

Showing the changes to include/linux (1 of 3 files). Show all

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include/linux/soc/qcom/irq.h+13−0
@@ -18,4 +18,17 @@ · 17 unmodified lines
18#define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 0)18#define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 0)
19#define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 1)19#define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 1)
20 20
21/**
22 * irq_domain_qcom_handle_wakeup: Return if the domain handles interrupt
23 * configuration
24 * @d: irq domain
25 *
26 * This QCOM specific irq domain call returns if the interrupt controller
27 * requires the interrupt be masked at the child interrupt controller.
28 */
29static inline bool irq_domain_qcom_handle_wakeup(const struct irq_domain *d)
30{
31 return (d->flags & IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP);
32}
33
21#endif34#endif

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