We've found two bugs here: NT_RISCV_VECTOR steps on NT_RISCV_CSR (which is only for embedded), and we don't have vlenb in the core dumps. Given that we've have a pair of bugs croup up as part of the GDB review we've probably got other issues, so let's just cut this for 6.5 and get it right.
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| @@ -443,7 +443,6 @@ typedef struct elf64_shdr { · 442 unmodified lines | ||
| 443 | 443 | #define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */ |
| 444 | 444 | #define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode */ |
| 445 | 445 | #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */ |
| 446 | −#define NT_RISCV_VECTOR 0x900 /* RISC-V vector registers */ | |
| 447 | 446 | #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ |
| 448 | 447 | #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ |
| 449 | 448 | #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */ |