Merge tag 'dmaengine-fix-5.4-rc6' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine fixes from Vinod Koul: "A few fixes to the dmaengine drivers: - fix in sprd driver for link list and potential memory leak - tegra transfer failure fix - imx size check fix for script_number - xilinx fix for 64bit AXIDMA and control reg update - qcom bam dma resource leak fix - cppi slave transfer fix when idle" * tag 'dmaengine-fix-5.4-rc6' of git://git.infradead.org/users/vkoul/slave-dma: dmaengine: cppi41: Fix cppi41_dma_prep_slave_sg() when idle dmaengine: qcom: bam_dma: Fix resource leak dmaengine: sprd: Fix the possible memory leak issue dmaengine: xilinx_dma: Fix control reg update in vdma_channel_set_config dmaengine: xilinx_dma: Fix 64-bit simple AXIDMA transfer dmaengine: imx-sdma: fix size check for sdma script_number dmaengine: tegra210-adma: fix transfer failure dmaengine: sprd: Fix the link-list pointer register configuration issue

Linus Torvalds committed 7 years ago

Commit e472c642 parents 320000e bacdcb67 files · +91 −4Browse files

Unified · Split

7 files

drivers/dma/imx-sdma.c +8 −0
drivers/dma/qcom/bam_dma.c +19 −0
drivers/dma/sprd-dma.c +25 −2
drivers/dma/tegra210-adma.c +7 −0
drivers/dma/ti/cppi41.c +20 −1
drivers/dma/xilinx/xilinx_dma.c +9 −1
include/linux/platform_data/dma-imx-sdma.h +3 −0

drivers/dma/imx-sdma.c+8−0

@@ -1707,6 +1707,14 @@ static void sdma_add_scripts(struct sdma_engine *sdma, · 1706 unmodified lines
1707	if (!sdma->script_number)	1707	if (!sdma->script_number)
1708	sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;	1708	sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1709		1709
		1710	if (sdma->script_number > sizeof(struct sdma_script_start_addrs)
		1711	/ sizeof(s32)) {
		1712	dev_err(sdma->dev,
		1713	"SDMA script number %d not match with firmware.\n",
		1714	sdma->script_number);
		1715	return;
		1716	}
		1717
1710	for (i = 0; i < sdma->script_number; i++)	1718	for (i = 0; i < sdma->script_number; i++)
1711	if (addr_arr[i] > 0)	1719	if (addr_arr[i] > 0)
1712	saddr_arr[i] = addr_arr[i];	1720	saddr_arr[i] = addr_arr[i];

drivers/dma/qcom/bam_dma.c+19−0

@@ -694,6 +694,25 @@ static int bam_dma_terminate_all(struct dma_chan *chan) · 693 unmodified lines
694		694
695	/* remove all transactions, including active transaction */	695	/* remove all transactions, including active transaction */
696	spin_lock_irqsave(&bchan->vc.lock, flag);	696	spin_lock_irqsave(&bchan->vc.lock, flag);
		697	/*
		698	* If we have transactions queued, then some might be committed to the
		699	* hardware in the desc fifo. The only way to reset the desc fifo is
		700	* to do a hardware reset (either by pipe or the entire block).
		701	* bam_chan_init_hw() will trigger a pipe reset, and also reinit the
		702	* pipe. If the pipe is left disabled (default state after pipe reset)
		703	* and is accessed by a connected hardware engine, a fatal error in
		704	* the BAM will occur. There is a small window where this could happen
		705	* with bam_chan_init_hw(), but it is assumed that the caller has
		706	* stopped activity on any attached hardware engine. Make sure to do
		707	* this first so that the BAM hardware doesn't cause memory corruption
		708	* by accessing freed resources.
		709	*/
		710	if (!list_empty(&bchan->desc_list)) {
		711	async_desc = list_first_entry(&bchan->desc_list,
		712	struct bam_async_desc, desc_node);
		713	bam_chan_init_hw(bchan, async_desc->dir);
		714	}
		715
697	list_for_each_entry_safe(async_desc, tmp,	716	list_for_each_entry_safe(async_desc, tmp,
698	&bchan->desc_list, desc_node) {	717	&bchan->desc_list, desc_node) {
699	list_add(&async_desc->vd.node, &bchan->vc.desc_issued);	718	list_add(&async_desc->vd.node, &bchan->vc.desc_issued);

drivers/dma/sprd-dma.c+25−2

 #define SPRD_DMA_SRC_TRSF_STEP_OFFSET	0
 #define SPRD_DMA_TRSF_STEP_MASK		GENMASK(15, 0)
+/* SPRD DMA_SRC_BLK_STEP register definition */
+#define SPRD_DMA_LLIST_HIGH_MASK	GENMASK(31, 28)
+#define SPRD_DMA_LLIST_HIGH_SHIFT	28
 /* define DMA channel mode & trigger mode mask */
 #define SPRD_DMA_CHN_MODE_MASK		GENMASK(7, 0)
 #define SPRD_DMA_TRG_MODE_MASK		GENMASK(7, 0)
 	struct sprd_dma_chn	channels[0];
 };
+static void sprd_dma_free_desc(struct virt_dma_desc *vd);
 static bool sprd_dma_filter_fn(struct dma_chan *chan, void *param);
 static struct of_dma_filter_info sprd_dma_info = {
 	.filter_fn = sprd_dma_filter_fn,
 static void sprd_dma_free_chan_resources(struct dma_chan *chan)
 {
 	struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
+	struct virt_dma_desc *cur_vd = NULL;
 	unsigned long flags;
 	spin_lock_irqsave(&schan->vc.lock, flags);
+	if (schan->cur_desc)
+		cur_vd = &schan->cur_desc->vd;
 	sprd_dma_stop(schan);
 	spin_unlock_irqrestore(&schan->vc.lock, flags);
+	if (cur_vd)
+		sprd_dma_free_desc(cur_vd);
 	vchan_free_chan_resources(&schan->vc);
 	pm_runtime_put(chan->device->dev);
 }
 	u32 int_mode = flags & SPRD_DMA_INT_MASK;
 	int src_datawidth, dst_datawidth, src_step, dst_step;
 	u32 temp, fix_mode = 0, fix_en = 0;
+	phys_addr_t llist_ptr;
 	if (dir == DMA_MEM_TO_DEV) {
 		src_step = sprd_dma_get_step(slave_cfg->src_addr_width);
 		 * Set the link-list pointer point to next link-list
 		 * configuration's physical address.
 		 */
-		hw->llist_ptr = schan->linklist.phy_addr + temp;
+		llist_ptr = schan->linklist.phy_addr + temp;
+		hw->llist_ptr = lower_32_bits(llist_ptr);
+		hw->src_blk_step = (upper_32_bits(llist_ptr) << SPRD_DMA_LLIST_HIGH_SHIFT) &
+			SPRD_DMA_LLIST_HIGH_MASK;
 	} else {
 		hw->llist_ptr = 0;
+		hw->src_blk_step = 0;
 	}
 	hw->frg_step = 0;
-	hw->src_blk_step = 0;
 	hw->des_blk_step = 0;
 	return 0;
 }
 static int sprd_dma_terminate_all(struct dma_chan *chan)
 {
 	struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
+	struct virt_dma_desc *cur_vd = NULL;
 	unsigned long flags;
 	LIST_HEAD(head);
 	spin_lock_irqsave(&schan->vc.lock, flags);
+	if (schan->cur_desc)
+		cur_vd = &schan->cur_desc->vd;
 	sprd_dma_stop(schan);
 	vchan_get_all_descriptors(&schan->vc, &head);
 	spin_unlock_irqrestore(&schan->vc.lock, flags);
+	if (cur_vd)
+		sprd_dma_free_desc(cur_vd);
 	vchan_dma_desc_free_list(&schan->vc, &head);
 	return 0;
 }

drivers/dma/tegra210-adma.c+7−0

 #define ADMA_CH_CONFIG_MAX_BURST_SIZE                   16
 #define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val)		((val) & 0xf)
 #define ADMA_CH_CONFIG_MAX_BUFS				8
+#define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs)	(reqs << 4)
 #define ADMA_CH_FIFO_CTRL				0x2c
 #define TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(val)		(((val) & 0xf) << 8)
  * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
  * @ch_req_rx_shift: Register offset for AHUB receive channel select.
  * @ch_base_offset: Register offset of DMA channel registers.
+ * @has_outstanding_reqs: If DMA channel can have outstanding requests.
  * @ch_fifo_ctrl: Default value for channel FIFO CTRL register.
  * @ch_req_mask: Mask for Tx or Rx channel select.
  * @ch_req_max: Maximum number of Tx or Rx channels available.
 	unsigned int ch_req_max;
 	unsigned int ch_reg_size;
 	unsigned int nr_channels;
+	bool has_outstanding_reqs;
 };
 /*
 			 ADMA_CH_CTRL_FLOWCTRL_EN;
 	ch_regs->config |= cdata->adma_get_burst_config(burst_size);
 	ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
+	if (cdata->has_outstanding_reqs)
+		ch_regs->config |= TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8);
 	ch_regs->fifo_ctrl = cdata->ch_fifo_ctrl;
 	ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
 	.ch_req_tx_shift	= 28,
 	.ch_req_rx_shift	= 24,
 	.ch_base_offset		= 0,
+	.has_outstanding_reqs	= false,
 	.ch_fifo_ctrl		= TEGRA210_FIFO_CTRL_DEFAULT,
 	.ch_req_mask		= 0xf,
 	.ch_req_max		= 10,
 	.ch_req_tx_shift	= 27,
 	.ch_req_rx_shift	= 22,
 	.ch_base_offset		= 0x10000,
+	.has_outstanding_reqs	= true,
 	.ch_fifo_ctrl		= TEGRA186_FIFO_CTRL_DEFAULT,
 	.ch_req_mask		= 0x1f,
 	.ch_req_max		= 20,

drivers/dma/ti/cppi41.c+20−1

@@ -586,9 +586,22 @@ static struct dma_async_tx_descriptor *cppi41_dma_prep_slave_sg( · 585 unmodified lines
586	enum dma_transfer_direction dir, unsigned long tx_flags, void *context)	586	enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
587	{	587	{
588	struct cppi41_channel *c = to_cpp41_chan(chan);	588	struct cppi41_channel *c = to_cpp41_chan(chan);
		589	struct dma_async_tx_descriptor *txd = NULL;
		590	struct cppi41_dd *cdd = c->cdd;
589	struct cppi41_desc *d;	591	struct cppi41_desc *d;
590	struct scatterlist *sg;	592	struct scatterlist *sg;
591	unsigned int i;	593	unsigned int i;
		594	int error;
		595
		596	error = pm_runtime_get(cdd->ddev.dev);
		597	if (error < 0) {
		598	pm_runtime_put_noidle(cdd->ddev.dev);
		599
		600	return NULL;
		601	}
		602
		603	if (cdd->is_suspended)
		604	goto err_out_not_ready;
592		605
593	d = c->desc;	606	d = c->desc;
594	for_each_sg(sgl, sg, sg_len, i) {	607	for_each_sg(sgl, sg, sg_len, i) {
@@ -611,7 +624,13 @@ static struct dma_async_tx_descriptor *cppi41_dma_prep_slave_sg( · 16 unmodified lines
611	d++;	624	d++;
612	}	625	}
613		626
614	return &c->txd;	627	txd = &c->txd;
		628
		629	err_out_not_ready:
		630	pm_runtime_mark_last_busy(cdd->ddev.dev);
		631	pm_runtime_put_autosuspend(cdd->ddev.dev);
		632
		633	return txd;
615	}	634	}
616		635
617	static void cppi41_compute_td_desc(struct cppi41_desc *d)	636	static void cppi41_compute_td_desc(struct cppi41_desc *d)

drivers/dma/xilinx/xilinx_dma.c+9−1

 #define XILINX_DMA_DMACR_CIRC_EN		BIT(1)
 #define XILINX_DMA_DMACR_RUNSTOP		BIT(0)
 #define XILINX_DMA_DMACR_FSYNCSRC_MASK		GENMASK(6, 5)
+#define XILINX_DMA_DMACR_DELAY_MASK		GENMASK(31, 24)
+#define XILINX_DMA_DMACR_FRAME_COUNT_MASK	GENMASK(23, 16)
+#define XILINX_DMA_DMACR_MASTER_MASK		GENMASK(11, 8)
 #define XILINX_DMA_REG_DMASR			0x0004
 #define XILINX_DMA_DMASR_EOL_LATE_ERR		BIT(15)
 					   node);
 		hw = &segment->hw;
-		xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr);
+		xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR,
+			     xilinx_prep_dma_addr_t(hw->buf_addr));
 		/* Start the transfer */
 		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
 	chan->config.gen_lock = cfg->gen_lock;
 	chan->config.master = cfg->master;
+	dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;
 	if (cfg->gen_lock && chan->genlock) {
 		dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
+		dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;
 		dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
 	}
 	chan->config.delay = cfg->delay;
 	if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
+		dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;
 		dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
 		chan->config.coalesc = cfg->coalesc;
 	}
 	if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
+		dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;
 		dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
 		chan->config.delay = cfg->delay;
 	}

include/linux/platform_data/dma-imx-sdma.h+3−0

 	/* End of v2 array */
 	s32 zcanfd_2_mcu_addr;
 	s32 zqspi_2_mcu_addr;
+	s32 mcu_2_ecspi_addr;
 	/* End of v3 array */
+	s32 mcu_2_zqspi_addr;
+	/* End of v4 array */
 };
 /**

Merge tag 'dmaengine-fix-5.4-rc6' of git://git.infradead.org/users/vkoul/slave-dma

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