Samsung's S2MU005 PMIC includes subdevices for a charger, an MUIC (Micro USB Interface Controller), and flash and RGB LED controllers. S2MU005's interrupt registers divided into three domains, each for the charger, flash LEDs, and the MUIC, packed into a single regmap IRQ chip construct. In devices other than S2MPG1X, the revision can be retrieved from the first register of the PMIC regmap. In S2MU005 however, the location is in offset 0x73. Introduce a switch-case block to allow selecting the REG_ID register. S2MU005 also has a field mask for the revision. Apply it using FIELD_GET() and get the extracted value. Add initial support for S2MU005 in the PMIC driver, along with its three interrupt chips, and support for allowing to fetch revision based on the device variant.
Showing the changes to include (3 of 6 files). Show all
Unified · Split
| @@ -47,6 +47,7 @@ enum sec_device_type { · 46 unmodified lines | |||
| 47 | S2MPS15X, | 47 | S2MPS15X, |
| 48 | S2MPU02, | 48 | S2MPU02, |
| 49 | S2MPU05, | 49 | S2MPU05, |
| 50 | S2MU005, | ||
| 50 | }; | 51 | }; |
| 51 | 52 | ||
| 52 | /** | 53 | /** |
| @@ -408,6 +408,72 @@ enum s2mpu05_irq { · 407 unmodified lines | |||
| 408 | #define S2MPU05_IRQ_INT140C_MASK BIT(1) | 408 | #define S2MPU05_IRQ_INT140C_MASK BIT(1) |
| 409 | #define S2MPU05_IRQ_TSD_MASK BIT(2) | 409 | #define S2MPU05_IRQ_TSD_MASK BIT(2) |
| 410 | 410 | ||
| 411 | enum s2mu005_irq { | ||
| 412 | S2MU005_IRQ_CHGR_DETBAT, | ||
| 413 | S2MU005_IRQ_CHGR_BAT, | ||
| 414 | S2MU005_IRQ_CHGR_IVR, | ||
| 415 | S2MU005_IRQ_CHGR_EVENT, | ||
| 416 | S2MU005_IRQ_CHGR_CHG, | ||
| 417 | S2MU005_IRQ_CHGR_VMID, | ||
| 418 | S2MU005_IRQ_CHGR_WCIN, | ||
| 419 | S2MU005_IRQ_CHGR_VBUS, | ||
| 420 | |||
| 421 | S2MU005_IRQ_FLED_LBPROT, | ||
| 422 | S2MU005_IRQ_FLED_OPENCH2, | ||
| 423 | S2MU005_IRQ_FLED_OPENCH1, | ||
| 424 | S2MU005_IRQ_FLED_SHORTCH2, | ||
| 425 | S2MU005_IRQ_FLED_SHORTCH1, | ||
| 426 | |||
| 427 | S2MU005_IRQ_MUIC_ATTACH, | ||
| 428 | S2MU005_IRQ_MUIC_DETACH, | ||
| 429 | S2MU005_IRQ_MUIC_KP, | ||
| 430 | S2MU005_IRQ_MUIC_LKP, | ||
| 431 | S2MU005_IRQ_MUIC_LKR, | ||
| 432 | S2MU005_IRQ_MUIC_RIDCHG, | ||
| 433 | |||
| 434 | S2MU005_IRQ_MUIC_VBUSON, | ||
| 435 | S2MU005_IRQ_MUIC_RSVD, | ||
| 436 | S2MU005_IRQ_MUIC_ADC, | ||
| 437 | S2MU005_IRQ_MUIC_STUCK, | ||
| 438 | S2MU005_IRQ_MUIC_STUCKRCV, | ||
| 439 | S2MU005_IRQ_MUIC_MHDL, | ||
| 440 | S2MU005_IRQ_MUIC_AVCHG, | ||
| 441 | S2MU005_IRQ_MUIC_VBUSOFF, | ||
| 442 | |||
| 443 | S2MU005_IRQ_NR, | ||
| 444 | }; | ||
| 445 | |||
| 446 | #define S2MU005_IRQ_CHGR_DETBAT_MASK BIT(0) | ||
| 447 | #define S2MU005_IRQ_CHGR_BAT_MASK BIT(1) | ||
| 448 | #define S2MU005_IRQ_CHGR_IVR_MASK BIT(2) | ||
| 449 | #define S2MU005_IRQ_CHGR_EVENT_MASK BIT(3) | ||
| 450 | #define S2MU005_IRQ_CHGR_CHG_MASK BIT(4) | ||
| 451 | #define S2MU005_IRQ_CHGR_VMID_MASK BIT(5) | ||
| 452 | #define S2MU005_IRQ_CHGR_WCIN_MASK BIT(6) | ||
| 453 | #define S2MU005_IRQ_CHGR_VBUS_MASK BIT(7) | ||
| 454 | |||
| 455 | #define S2MU005_IRQ_FLED_LBPROT_MASK BIT(2) | ||
| 456 | #define S2MU005_IRQ_FLED_OPENCH2_MASK BIT(4) | ||
| 457 | #define S2MU005_IRQ_FLED_OPENCH1_MASK BIT(5) | ||
| 458 | #define S2MU005_IRQ_FLED_SHORTCH2_MASK BIT(6) | ||
| 459 | #define S2MU005_IRQ_FLED_SHORTCH1_MASK BIT(7) | ||
| 460 | |||
| 461 | #define S2MU005_IRQ_MUIC_ATTACH_MASK BIT(0) | ||
| 462 | #define S2MU005_IRQ_MUIC_DETACH_MASK BIT(1) | ||
| 463 | #define S2MU005_IRQ_MUIC_KP_MASK BIT(2) | ||
| 464 | #define S2MU005_IRQ_MUIC_LKP_MASK BIT(3) | ||
| 465 | #define S2MU005_IRQ_MUIC_LKR_MASK BIT(4) | ||
| 466 | #define S2MU005_IRQ_MUIC_RIDCHG_MASK BIT(5) | ||
| 467 | |||
| 468 | #define S2MU005_IRQ_MUIC_VBUSON_MASK BIT(0) | ||
| 469 | #define S2MU005_IRQ_MUIC_RSVD_MASK BIT(1) | ||
| 470 | #define S2MU005_IRQ_MUIC_ADC_MASK BIT(2) | ||
| 471 | #define S2MU005_IRQ_MUIC_STUCK_MASK BIT(3) | ||
| 472 | #define S2MU005_IRQ_MUIC_STUCKRCV_MASK BIT(4) | ||
| 473 | #define S2MU005_IRQ_MUIC_MHDL_MASK BIT(5) | ||
| 474 | #define S2MU005_IRQ_MUIC_AVCHG_MASK BIT(6) | ||
| 475 | #define S2MU005_IRQ_MUIC_VBUSOFF_MASK BIT(7) | ||
| 476 | |||
| 411 | enum s5m8767_irq { | 477 | enum s5m8767_irq { |
| 412 | S5M8767_IRQ_PWRR, | 478 | S5M8767_IRQ_PWRR, |
| 413 | S5M8767_IRQ_PWRF, | 479 | S5M8767_IRQ_PWRF, |
| @@ -0,0 +1,332 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ | ||
| 2 | /* | ||
| 3 | * Copyright (c) 2015 Samsung Electronics Co., Ltd | ||
| 4 | * Copyright (c) 2026 Kaustabh Chakraborty <kauschluss@disroot.org> | ||
| 5 | * Copyright (c) 2026 Łukasz Lebiedziński <kernel@lvkasz.us> | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __LINUX_MFD_S2MU005_H | ||
| 9 | #define __LINUX_MFD_S2MU005_H | ||
| 10 | |||
| 11 | #include <linux/bitfield.h> | ||
| 12 | #include <linux/bits.h> | ||
| 13 | |||
| 14 | /* S2MU005 registers */ | ||
| 15 | enum s2mu005_reg { | ||
| 16 | S2MU005_REG_CHGR_INT1, | ||
| 17 | S2MU005_REG_CHGR_INT1M, | ||
| 18 | |||
| 19 | S2MU005_REG_FLED_INT1, | ||
| 20 | S2MU005_REG_FLED_INT1M, | ||
| 21 | |||
| 22 | S2MU005_REG_MUIC_INT1, | ||
| 23 | S2MU005_REG_MUIC_INT2, | ||
| 24 | S2MU005_REG_MUIC_INT1M, | ||
| 25 | S2MU005_REG_MUIC_INT2M, | ||
| 26 | |||
| 27 | S2MU005_REG_CHGR_STATUS0, | ||
| 28 | S2MU005_REG_CHGR_STATUS1, | ||
| 29 | S2MU005_REG_CHGR_STATUS2, | ||
| 30 | S2MU005_REG_CHGR_STATUS3, | ||
| 31 | S2MU005_REG_CHGR_STATUS4, | ||
| 32 | S2MU005_REG_CHGR_STATUS5, | ||
| 33 | S2MU005_REG_CHGR_CTRL0, | ||
| 34 | S2MU005_REG_CHGR_CTRL1, | ||
| 35 | S2MU005_REG_CHGR_CTRL2, | ||
| 36 | S2MU005_REG_CHGR_CTRL3, | ||
| 37 | S2MU005_REG_CHGR_CTRL4, | ||
| 38 | S2MU005_REG_CHGR_CTRL5, | ||
| 39 | S2MU005_REG_CHGR_CTRL6, | ||
| 40 | S2MU005_REG_CHGR_CTRL7, | ||
| 41 | S2MU005_REG_CHGR_CTRL8, | ||
| 42 | S2MU005_REG_CHGR_CTRL9, | ||
| 43 | S2MU005_REG_CHGR_CTRL10, | ||
| 44 | S2MU005_REG_CHGR_CTRL11, | ||
| 45 | S2MU005_REG_CHGR_CTRL12, | ||
| 46 | S2MU005_REG_CHGR_CTRL13, | ||
| 47 | S2MU005_REG_CHGR_CTRL14, | ||
| 48 | S2MU005_REG_CHGR_CTRL15, | ||
| 49 | S2MU005_REG_CHGR_CTRL16, | ||
| 50 | S2MU005_REG_CHGR_CTRL17, | ||
| 51 | S2MU005_REG_CHGR_CTRL18, | ||
| 52 | S2MU005_REG_CHGR_CTRL19, | ||
| 53 | S2MU005_REG_CHGR_TEST0, | ||
| 54 | S2MU005_REG_CHGR_TEST1, | ||
| 55 | S2MU005_REG_CHGR_TEST2, | ||
| 56 | S2MU005_REG_CHGR_TEST3, | ||
| 57 | S2MU005_REG_CHGR_TEST4, | ||
| 58 | S2MU005_REG_CHGR_TEST5, | ||
| 59 | S2MU005_REG_CHGR_TEST6, | ||
| 60 | S2MU005_REG_CHGR_TEST7, | ||
| 61 | S2MU005_REG_CHGR_TEST8, | ||
| 62 | S2MU005_REG_CHGR_TEST9, | ||
| 63 | S2MU005_REG_CHGR_TEST10, | ||
| 64 | |||
| 65 | S2MU005_REG_FLED_STATUS, | ||
| 66 | S2MU005_REG_FLED_CH0_CTRL0, | ||
| 67 | S2MU005_REG_FLED_CH0_CTRL1, | ||
| 68 | S2MU005_REG_FLED_CH0_CTRL2, | ||
| 69 | S2MU005_REG_FLED_CH0_CTRL3, | ||
| 70 | S2MU005_REG_FLED_CH1_CTRL0, | ||
| 71 | S2MU005_REG_FLED_CH1_CTRL1, | ||
| 72 | S2MU005_REG_FLED_CH1_CTRL2, | ||
| 73 | S2MU005_REG_FLED_CH1_CTRL3, | ||
| 74 | S2MU005_REG_FLED_CTRL0, | ||
| 75 | S2MU005_REG_FLED_CTRL1, | ||
| 76 | S2MU005_REG_FLED_CTRL2, | ||
| 77 | S2MU005_REG_FLED_CTRL3, | ||
| 78 | S2MU005_REG_FLED_CTRL4, | ||
| 79 | S2MU005_REG_FLED_CTRL5, | ||
| 80 | S2MU005_REG_FLED_CTRL6, | ||
| 81 | |||
| 82 | S2MU005_REG_RGB_EN, | ||
| 83 | S2MU005_REG_RGB_CH0_CTRL, | ||
| 84 | S2MU005_REG_RGB_CH1_CTRL, | ||
| 85 | S2MU005_REG_RGB_CH2_CTRL, | ||
| 86 | S2MU005_REG_RGB_CH0_RAMP, | ||
| 87 | S2MU005_REG_RGB_CH0_STAY, | ||
| 88 | S2MU005_REG_RGB_CH1_RAMP, | ||
| 89 | S2MU005_REG_RGB_CH1_STAY, | ||
| 90 | S2MU005_REG_RGB_CH2_RAMP, | ||
| 91 | S2MU005_REG_RGB_CH2_STAY, | ||
| 92 | S2MU005_REG_RGB_TEST0, | ||
| 93 | S2MU005_REG_RGB_CTRL0, | ||
| 94 | |||
| 95 | S2MU005_REG_MUIC_ADC, | ||
| 96 | S2MU005_REG_MUIC_DEV1, | ||
| 97 | S2MU005_REG_MUIC_DEV2, | ||
| 98 | S2MU005_REG_MUIC_DEV3, | ||
| 99 | S2MU005_REG_MUIC_BUTTON1, | ||
| 100 | S2MU005_REG_MUIC_BUTTON2, | ||
| 101 | S2MU005_REG_MUIC_RESET, | ||
| 102 | S2MU005_REG_MUIC_CHGTYPE, | ||
| 103 | S2MU005_REG_MUIC_DEVAPPLE, | ||
| 104 | S2MU005_REG_MUIC_BCDRESCAN, | ||
| 105 | S2MU005_REG_MUIC_TEST1, | ||
| 106 | S2MU005_REG_MUIC_TEST2, | ||
| 107 | S2MU005_REG_MUIC_TEST3, | ||
| 108 | |||
| 109 | S2MU005_REG_ID = 0x73, | ||
| 110 | |||
| 111 | S2MU005_REG_MUIC_CTRL1 = 0xb2, | ||
| 112 | S2MU005_REG_MUIC_TIMERSET1, | ||
| 113 | S2MU005_REG_MUIC_TIMERSET2, | ||
| 114 | S2MU005_REG_MUIC_SWCTRL, | ||
| 115 | S2MU005_REG_MUIC_TIMERSET3, | ||
| 116 | S2MU005_REG_MUIC_CTRL2, | ||
| 117 | S2MU005_REG_MUIC_CTRL3, | ||
| 118 | |||
| 119 | S2MU005_REG_MUIC_LDOADC_L = 0xbf, | ||
| 120 | S2MU005_REG_MUIC_LDOADC_H, | ||
| 121 | }; | ||
| 122 | |||
| 123 | #define S2MU005_REG_FLED_CH_CTRL0(x) (S2MU005_REG_FLED_CH0_CTRL0 + 4 * (x)) | ||
| 124 | #define S2MU005_REG_FLED_CH_CTRL1(x) (S2MU005_REG_FLED_CH0_CTRL1 + 4 * (x)) | ||
| 125 | #define S2MU005_REG_FLED_CH_CTRL2(x) (S2MU005_REG_FLED_CH0_CTRL2 + 4 * (x)) | ||
| 126 | #define S2MU005_REG_FLED_CH_CTRL3(x) (S2MU005_REG_FLED_CH0_CTRL3 + 4 * (x)) | ||
| 127 | |||
| 128 | #define S2MU005_REG_RGB_CH_CTRL(x) (S2MU005_REG_RGB_CH0_CTRL + 1 * (x)) | ||
| 129 | #define S2MU005_REG_RGB_CH_RAMP(x) (S2MU005_REG_RGB_CH0_RAMP + 2 * (x)) | ||
| 130 | #define S2MU005_REG_RGB_CH_STAY(x) (S2MU005_REG_RGB_CH0_STAY + 2 * (x)) | ||
| 131 | |||
| 132 | /* S2MU005_REG_CHGR_STATUS0 */ | ||
| 133 | #define S2MU005_CHGR_VBUS BIT(7) | ||
| 134 | #define S2MU005_CHGR_WCIN BIT(6) | ||
| 135 | #define S2MU005_CHGR_VMID BIT(5) | ||
| 136 | #define S2MU005_CHGR_CHG BIT(4) | ||
| 137 | #define S2MU005_CHGR_STAT GENMASK(3, 0) | ||
| 138 | |||
| 139 | #define S2MU005_CHGR_STAT_DONE 8 | ||
| 140 | #define S2MU005_CHGR_STAT_TOPOFF 7 | ||
| 141 | #define S2MU005_CHGR_STAT_DONE_FLAG 6 | ||
| 142 | #define S2MU005_CHGR_STAT_CV 5 | ||
| 143 | #define S2MU005_CHGR_STAT_CC 4 | ||
| 144 | #define S2MU005_CHGR_STAT_COOL_CHG 3 | ||
| 145 | #define S2MU005_CHGR_STAT_PRE_CHG 2 | ||
| 146 | |||
| 147 | /* S2MU005_REG_CHGR_STATUS1 */ | ||
| 148 | #define S2MU005_CHGR_DETBAT BIT(7) | ||
| 149 | #define S2MU005_CHGR_VBUS_OVP GENMASK(6, 4) | ||
| 150 | |||
| 151 | #define S2MU005_CHGR_VBUS_OVP_OVERVOLT 2 | ||
| 152 | |||
| 153 | /* S2MU005_REG_CHGR_STATUS2 */ | ||
| 154 | #define S2MU005_CHGR_BAT GENMASK(6, 4) | ||
| 155 | |||
| 156 | #define S2MU005_CHGR_BAT_VOLT_DET 7 | ||
| 157 | #define S2MU005_CHGR_BAT_FAST_CHG_DET 6 | ||
| 158 | #define S2MU005_CHGR_BAT_COOL_CHG_DET 5 | ||
| 159 | #define S2MU005_CHGR_BAT_LOW_CHG 2 | ||
| 160 | #define S2MU005_CHGR_BAT_SELF_DISCHG 1 | ||
| 161 | #define S2MU005_CHGR_BAT_OVP_DET 0 | ||
| 162 | |||
| 163 | /* S2MU005_REG_CHGR_STATUS3 */ | ||
| 164 | #define S2MU005_CHGR_EVT GENMASK(3, 0) | ||
| 165 | |||
| 166 | #define S2MU005_CHGR_EVT_WDT_RST 6 | ||
| 167 | #define S2MU005_CHGR_EVT_WDT_SUSP 5 | ||
| 168 | #define S2MU005_CHGR_EVT_VSYS_VUVLO 4 | ||
| 169 | #define S2MU005_CHGR_EVT_VSYS_VOVP 3 | ||
| 170 | #define S2MU005_CHGR_EVT_THERM_FOLDBACK 2 | ||
| 171 | #define S2MU005_CHGR_EVT_THERM_SHUTDOWN 1 | ||
| 172 | |||
| 173 | /* S2MU005_REG_CHGR_CTRL0 */ | ||
| 174 | #define S2MU005_CHGR_CHG_EN BIT(4) | ||
| 175 | #define S2MU005_CHGR_OP_MODE GENMASK(2, 0) | ||
| 176 | |||
| 177 | #define S2MU005_CHGR_OP_MODE_OTG BIT(2) | ||
| 178 | #define S2MU005_CHGR_OP_MODE_CHG BIT(1) | ||
| 179 | |||
| 180 | /* S2MU005_REG_CHGR_CTRL1 */ | ||
| 181 | #define S2MU005_CHGR_VIN_DROP GENMASK(6, 4) | ||
| 182 | |||
| 183 | /* S2MU005_REG_CHGR_CTRL2 */ | ||
| 184 | #define S2MU005_CHGR_IN_CURR_LIM GENMASK(5, 0) | ||
| 185 | |||
| 186 | /* S2MU005_REG_CHGR_CTRL4 */ | ||
| 187 | #define S2MU005_CHGR_OTG_OCP_ON BIT(5) | ||
| 188 | #define S2MU005_CHGR_OTG_OCP_OFF BIT(4) | ||
| 189 | #define S2MU005_CHGR_OTG_OCP GENMASK(3, 2) | ||
| 190 | #define S2MU005_CHGR_OTG_OCP_1P5A 0x3 | ||
| 191 | |||
| 192 | /* S2MU005_REG_CHGR_CTRL5 */ | ||
| 193 | #define S2MU005_CHGR_VMID_BOOST GENMASK(4, 0) | ||
| 194 | #define S2MU005_CHGR_VMID_BOOST_5P1V 0x16 | ||
| 195 | |||
| 196 | /* S2MU005_REG_CHGR_CTRL6 */ | ||
| 197 | #define S2MU005_CHGR_COOL_CHG_CURR GENMASK(5, 0) | ||
| 198 | |||
| 199 | /* S2MU005_REG_CHGR_CTRL7 */ | ||
| 200 | #define S2MU005_CHGR_FAST_CHG_CURR GENMASK(5, 0) | ||
| 201 | |||
| 202 | /* S2MU005_REG_CHGR_CTRL8 */ | ||
| 203 | #define S2MU005_CHGR_VF_VBAT GENMASK(6, 1) | ||
| 204 | |||
| 205 | /* S2MU005_REG_CHGR_CTRL10 */ | ||
| 206 | #define S2MU005_CHGR_TOPOFF_CURR(x) (GENMASK(3, 0) << 4 * (x)) | ||
| 207 | |||
| 208 | /* S2MU005_REG_CHGR_CTRL11 */ | ||
| 209 | #define S2MU005_CHGR_OSC_BOOST GENMASK(6, 5) | ||
| 210 | #define S2MU005_CHGR_OSC_BUCK GENMASK(4, 3) | ||
| 211 | #define S2MU005_CHGR_OSC_BOOST_2MHZ 0x3 | ||
| 212 | |||
| 213 | /* S2MU005_REG_CHGR_CTRL12 */ | ||
| 214 | #define S2MU005_CHGR_WDT GENMASK(2, 0) | ||
| 215 | |||
| 216 | #define S2MU005_CHGR_WDT_ON BIT(2) | ||
| 217 | #define S2MU005_CHGR_WDT_OFF BIT(1) | ||
| 218 | |||
| 219 | /* S2MU005_REG_CHGR_CTRL15 */ | ||
| 220 | #define S2MU005_CHGR_OTG_EN GENMASK(3, 2) | ||
| 221 | #define S2MU005_CHGR_OTG_EN_ON 0x3 | ||
| 222 | |||
| 223 | /* S2MU005_REG_FLED_STATUS */ | ||
| 224 | #define S2MU005_FLED_FLASH_STATUS(x) (BIT(7) >> 2 * (x)) | ||
| 225 | #define S2MU005_FLED_TORCH_STATUS(x) (BIT(6) >> 2 * (x)) | ||
| 226 | |||
| 227 | /* S2MU005_REG_FLED_CHx_CTRL0 */ | ||
| 228 | #define S2MU005_FLED_FLASH_IOUT GENMASK(3, 0) | ||
| 229 | |||
| 230 | /* S2MU005_REG_FLED_CHx_CTRL1 */ | ||
| 231 | #define S2MU005_FLED_TORCH_IOUT GENMASK(3, 0) | ||
| 232 | |||
| 233 | /* S2MU005_REG_FLED_CHx_CTRL2 */ | ||
| 234 | #define S2MU005_FLED_TORCH_TIMEOUT GENMASK(3, 0) | ||
| 235 | |||
| 236 | /* S2MU005_REG_FLED_CHx_CTRL3 */ | ||
| 237 | #define S2MU005_FLED_FLASH_TIMEOUT GENMASK(3, 0) | ||
| 238 | |||
| 239 | /* S2MU005_REG_FLED_CTRL1 */ | ||
| 240 | #define S2MU005_FLED_CH_EN BIT(7) | ||
| 241 | |||
| 242 | /* | ||
| 243 | * S2MU005_REG_FLED_CTRL4 - Rev. EVT0 | ||
| 244 | * S2MU005_REG_FLED_CTRL6 - Rev. EVT1 and later | ||
| 245 | */ | ||
| 246 | #define S2MU005_FLED_FLASH_EN(x) (GENMASK(7, 6) >> 4 * (x)) | ||
| 247 | #define S2MU005_FLED_TORCH_EN(x) (GENMASK(5, 4) >> 4 * (x)) | ||
| 248 | |||
| 249 | /* S2MU005_REG_RGB_EN */ | ||
| 250 | #define S2MU005_RGB_RESET BIT(6) | ||
| 251 | #define S2MU005_RGB_SLOPE GENMASK(5, 0) | ||
| 252 | |||
| 253 | #define S2MU005_RGB_SLOPE_CONST (BIT(4) | BIT(2) | BIT(0)) | ||
| 254 | #define S2MU005_RGB_SLOPE_SMOOTH (BIT(5) | BIT(3) | BIT(1)) | ||
| 255 | |||
| 256 | /* S2MU005_REG_RGB_CHx_RAMP */ | ||
| 257 | #define S2MU005_RGB_CH_RAMP_UP GENMASK(7, 4) | ||
| 258 | #define S2MU005_RGB_CH_RAMP_DN GENMASK(3, 0) | ||
| 259 | |||
| 260 | /* S2MU005_REG_RGB_CHx_STAY */ | ||
| 261 | #define S2MU005_RGB_CH_STAY_HI GENMASK(7, 4) | ||
| 262 | #define S2MU005_RGB_CH_STAY_LO GENMASK(3, 0) | ||
| 263 | |||
| 264 | /* S2MU005_REG_MUIC_DEV1 */ | ||
| 265 | #define S2MU005_MUIC_OTG BIT(7) | ||
| 266 | #define S2MU005_MUIC_DCP BIT(6) | ||
| 267 | #define S2MU005_MUIC_CDP BIT(5) | ||
| 268 | #define S2MU005_MUIC_T1_T2_CHG BIT(4) | ||
| 269 | #define S2MU005_MUIC_UART BIT(3) | ||
| 270 | #define S2MU005_MUIC_SDP BIT(2) | ||
| 271 | #define S2MU005_MUIC_LANHUB BIT(1) | ||
| 272 | #define S2MU005_MUIC_AUDIO BIT(0) | ||
| 273 | |||
| 274 | /* S2MU005_REG_MUIC_DEV2 */ | ||
| 275 | #define S2MU005_MUIC_SDP_1P8S BIT(7) | ||
| 276 | #define S2MU005_MUIC_AV BIT(6) | ||
| 277 | #define S2MU005_MUIC_TTY BIT(5) | ||
| 278 | #define S2MU005_MUIC_PPD BIT(4) | ||
| 279 | #define S2MU005_MUIC_JIG_UART_OFF BIT(3) | ||
| 280 | #define S2MU005_MUIC_JIG_UART_ON BIT(2) | ||
| 281 | #define S2MU005_MUIC_JIG_USB_OFF BIT(1) | ||
| 282 | #define S2MU005_MUIC_JIG_USB_ON BIT(0) | ||
| 283 | |||
| 284 | /* S2MU005_REG_MUIC_DEV3 */ | ||
| 285 | #define S2MU005_MUIC_U200_CHG BIT(7) | ||
| 286 | #define S2MU005_MUIC_VBUS_AV BIT(4) | ||
| 287 | #define S2MU005_MUIC_VBUS_R255 BIT(1) | ||
| 288 | #define S2MU005_MUIC_MHL BIT(0) | ||
| 289 | |||
| 290 | /* S2MU005_REG_MUIC_DEVAPPLE */ | ||
| 291 | #define S2MU005_MUIC_APPLE_CHG_0P5A BIT(7) | ||
| 292 | #define S2MU005_MUIC_APPLE_CHG_1P0A BIT(6) | ||
| 293 | #define S2MU005_MUIC_APPLE_CHG_2P0A BIT(5) | ||
| 294 | #define S2MU005_MUIC_APPLE_CHG_2P4A BIT(4) | ||
| 295 | #define S2MU005_MUIC_SDP_DCD_OUT BIT(3) | ||
| 296 | #define S2MU005_MUIC_RID_WAKEUP BIT(2) | ||
| 297 | #define S2MU005_MUIC_VBUS_WAKEUP BIT(1) | ||
| 298 | #define S2MU005_MUIC_BCV1P2_OR_OPEN BIT(0) | ||
| 299 | |||
| 300 | /* S2MU005_REG_ID */ | ||
| 301 | #define S2MU005_ID_MASK GENMASK(3, 0) | ||
| 302 | |||
| 303 | /* S2MU005_REG_MUIC_SWCTRL */ | ||
| 304 | #define S2MU005_MUIC_DM_DP GENMASK(7, 2) | ||
| 305 | #define S2MU005_MUIC_JIG BIT(0) | ||
| 306 | |||
| 307 | #define S2MU005_MUIC_DM_DP_UART 0x12 | ||
| 308 | #define S2MU005_MUIC_DM_DP_USB 0x09 | ||
| 309 | |||
| 310 | /* S2MU005_REG_MUIC_CTRL1 */ | ||
| 311 | #define S2MU005_MUIC_OPEN BIT(4) | ||
| 312 | #define S2MU005_MUIC_RAW_DATA BIT(3) | ||
| 313 | #define S2MU005_MUIC_MAN_SW BIT(2) | ||
| 314 | #define S2MU005_MUIC_WAIT BIT(1) | ||
| 315 | #define S2MU005_MUIC_IRQ BIT(0) | ||
| 316 | |||
| 317 | /* S2MU005_REG_MUIC_CTRL3 */ | ||
| 318 | #define S2MU005_MUIC_ONESHOT_ADC BIT(2) | ||
| 319 | |||
| 320 | /* S2MU005_REG_MUIC_LDOADC_L and S2MU005_REG_MUIC_LDOADC_H */ | ||
| 321 | #define S2MU005_MUIC_VSET GENMASK(4, 0) | ||
| 322 | |||
| 323 | #define S2MU005_MUIC_VSET_3P0V 0x1f | ||
| 324 | #define S2MU005_MUIC_VSET_2P6V 0x0e | ||
| 325 | #define S2MU005_MUIC_VSET_2P4V 0x0c | ||
| 326 | #define S2MU005_MUIC_VSET_2P2V 0x0a | ||
| 327 | #define S2MU005_MUIC_VSET_2P0V 0x08 | ||
| 328 | #define S2MU005_MUIC_VSET_1P5V 0x03 | ||
| 329 | #define S2MU005_MUIC_VSET_1P4V 0x02 | ||
| 330 | #define S2MU005_MUIC_VSET_1P2V 0x00 | ||
| 331 | |||
| 332 | #endif /* __LINUX_MFD_S2MU005_H */ | ||