Current comment makes not clear the direction of mclk. Previously, similar description caused a misunderstanding for bclk_master and fsync_master. This commit solves the potential confusion the same way it is solved for bclk_master and fsync_master.
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| @@ -144,6 +144,10 @@ · 143 unmodified lines | ||
| 144 | 144 | #define SND_SOC_TPLG_DAI_CLK_GATE_GATED 1 |
| 145 | 145 | #define SND_SOC_TPLG_DAI_CLK_GATE_CONT 2 |
| 146 | 146 | |
| 147 | +/* DAI mclk_direction */ | |
| 148 | +#define SND_SOC_TPLG_MCLK_CO 0 /* for codec, mclk is output */ | |
| 149 | +#define SND_SOC_TPLG_MCLK_CI 1 /* for codec, mclk is input */ | |
| 150 | + | |
| 147 | 151 | /* DAI physical PCM data formats. |
| 148 | 152 | * Add new formats to the end of the list. |
| 149 | 153 | */ |
| @@ -334,7 +338,7 @@ struct snd_soc_tplg_hw_config { · 184 unmodified lines | ||
| 334 | 338 | __u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */ |
| 335 | 339 | __u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */ |
| 336 | 340 | __u8 fsync_master; /* SND_SOC_TPLG_FSYNC_ value */ |
| 337 | − __u8 mclk_direction; /* 0 for input, 1 for output */ | |
| 341 | + __u8 mclk_direction; /* SND_SOC_TPLG_MCLK_ value */ | |
| 338 | 342 | __le16 reserved; /* for 32bit alignment */ |
| 339 | 343 | __le32 mclk_rate; /* MCLK or SYSCLK freqency in Hz */ |
| 340 | 344 | __le32 bclk_rate; /* BCLK freqency in Hz */ |