lael-labs/linux

Documentation/devicetree/bindings/powerpc/fsl/mpc5121-psc.txt+18−6

 For PSC in UART mode the needed PSC serial devices
 are specified by fsl,mpc5121-psc-uart nodes in the
 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
-Controller node fsl,mpc5121-psc-fifo is requered there:
+Controller node fsl,mpc5121-psc-fifo is required there:
-fsl,mpc5121-psc-uart nodes
+fsl,mpc512x-psc-uart nodes
 --------------------------
 Required properties :
- - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc"
+ - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
- - cell-index : Index of the PSC in hardware
+   Supported <soc>s: mpc5121, mpc5125
  - reg : Offset and length of the register set for the PSC device
  - interrupts : <a b> where a is the interrupt number of the
    PSC FIFO Controller and b is a field that represents an
  - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
  - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
+PSC in SPI mode
+---------------
-fsl,mpc5121-psc-fifo node
+Similar to the UART mode a PSC can be operated in SPI mode. The compatible used
+for that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well.
+The required and recommended properties are identical to the
+fsl,mpc5121-psc-uart nodes, just use spi instead of uart in the compatible
+string.
+fsl,mpc512x-psc-fifo node
 -------------------------
 Required properties :
- - compatible : Should be "fsl,mpc5121-psc-fifo"
+ - compatible : Should be "fsl,<soc>-psc-fifo"
+   Supported <soc>s: mpc5121, mpc5125
  - reg : Offset and length of the register set for the PSC
          FIFO Controller
  - interrupts : <a b> where a is the interrupt number of the
  - interrupt-parent : the phandle for the interrupt controller that
    services interrupts for this device.
+Recommended properties :
+ - clocks : specifies the clock needed to operate the fifo controller
+ - clock-names : name(s) for the clock(s) listed in clocks
 Example for a board using PSC0 and PSC1 devices in serial mode:

Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt+2−0

@@ -10,6 +10,8 @@ Required properties: · 9 unmodified lines
10	Optional properties:	10	Optional properties:
11	- cs-gpios : Specifies the gpio pis to be used for chipselects.	11	- cs-gpios : Specifies the gpio pis to be used for chipselects.
12	- num-cs : The number of chipselects. If omitted, this will default to 4.	12	- num-cs : The number of chipselects. If omitted, this will default to 4.
		13	- reg-io-width : The I/O register width (in bytes) implemented by this
		14	device. Supported values are 2 or 4 (the default).
13		15
14	Child nodes as per the generic SPI binding.	16	Child nodes as per the generic SPI binding.
15		17

Documentation/devicetree/bindings/spi/spi-davinci.txt+2−0

 - compatible:
 	- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
 	- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
+	- "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
+		family
 - reg: Offset and length of SPI controller register space
 - num-cs: Number of chip selects. This includes internal as well as
 	GPIO chip selects.

Documentation/devicetree/bindings/spi/spi-img-spfi.txt+1−0

@@ -21,6 +21,7 @@ Required properties: · 20 unmodified lines
21	Optional properties:	21	Optional properties:
22	- img,supports-quad-mode: Should be set if the interface supports quad mode	22	- img,supports-quad-mode: Should be set if the interface supports quad mode
23	SPI transfers.	23	SPI transfers.
		24	- spfi-max-frequency: Maximum speed supported by the spfi block.
24		25
25	Example:	26	Example:
26		27

Documentation/devicetree/bindings/spi/spi-mt65xx.txt+51−0

@@ -0,0 +1,51 @@
	1	Binding for MTK SPI controller
	2
	3	Required properties:
	4	- compatible: should be one of the following.
	5	- mediatek,mt8173-spi: for mt8173 platforms
	6	- mediatek,mt8135-spi: for mt8135 platforms
	7	- mediatek,mt6589-spi: for mt6589 platforms
	8
	9	- #address-cells: should be 1.
	10
	11	- #size-cells: should be 0.
	12
	13	- reg: Address and length of the register set for the device
	14
	15	- interrupts: Should contain spi interrupt
	16
	17	- clocks: phandles to input clocks.
	18	The first should be <&topckgen CLK_TOP_SPI_SEL>.
	19	The second should be one of the following.
	20	- <&clk26m>: specify parent clock 26MHZ.
	21	- <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
	22	It's the default one.
	23	- <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
	24	- <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
	25	- <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
	26
	27	- clock-names: shall be "spi-clk" for the controller clock, and
	28	"parent-clk" for the parent clock.
	29
	30	Optional properties:
	31	- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
	32	controller used, this value should be 0~3, only required for MT8173.
	33	0: specify GPIO69,70,71,72 for spi pins.
	34	1: specify GPIO102,103,104,105 for spi pins.
	35	2: specify GPIO128,129,130,131 for spi pins.
	36	3: specify GPIO5,6,7,8 for spi pins.
	37
	38	Example:
	39
	40	- SoC Specific Portion:
	41	spi: spi@1100a000 {
	42	compatible = "mediatek,mt8173-spi";
	43	#address-cells = <1>;
	44	#size-cells = <0>;
	45	reg = <0 0x1100a000 0 0x1000>;
	46	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
	47	clocks = <&topckgen CLK_TOP_SPI_SEL>, <&topckgen CLK_TOP_SYSPLL3_D2>;
	48	clock-names = "spi-clk", "parent-clk";
	49	mediatek,pad-select = <0>;
	50	status = "disabled";
	51	};

Documentation/devicetree/bindings/spi/spi-xlp.txt+39−0

@@ -0,0 +1,39 @@
	1	SPI Master controller for Netlogic XLP MIPS64 SOCs
	2	==================================================
	3
	4	Currently this SPI controller driver is supported for the following
	5	Netlogic XLP SoCs:
	6	XLP832, XLP316, XLP208, XLP980, XLP532
	7
	8	Required properties:
	9	- compatible : Should be "netlogic,xlp832-spi".
	10	- #address-cells : Number of cells required to define a chip select address
	11	on the SPI bus.
	12	- #size-cells : Should be zero.
	13	- reg : Should contain register location and length.
	14	- clocks : Phandle of the spi clock
	15	- interrupts : Interrupt number used by this controller.
	16	- interrupt-parent : Phandle of the parent interrupt controller.
	17
	18	SPI slave nodes must be children of the SPI master node and can contain
	19	properties described in Documentation/devicetree/bindings/spi/spi-bus.txt.
	20
	21	Example:
	22
	23	spi: xlp_spi@3a100 {
	24	compatible = "netlogic,xlp832-spi";
	25	#address-cells = <1>;
	26	#size-cells = <0>;
	27	reg = <0 0x3a100 0x100>;
	28	clocks = <&spi_clk>;
	29	interrupts = <34>;
	30	interrupt-parent = <&pic>;
	31
	32	spi_nor@1 {
	33	compatible = "spansion,s25sl12801";
	34	#address-cells = <1>;
	35	#size-cells = <1>;
	36	reg = <1>; /* Chip Select */
	37	spi-max-frequency = <40000000>;
	38	};
	39	};

arch/arm/mach-davinci/devices-da8xx.c+2−0

 		.version	= SPI_VERSION_2,
 		.intr_line	= 1,
 		.dma_event_q	= EVENTQ_0,
+		.prescaler_limit = 2,
 	},
 	[1] = {
 		.version	= SPI_VERSION_2,
 		.intr_line	= 1,
 		.dma_event_q	= EVENTQ_0,
+		.prescaler_limit = 2,
 	},
 };

arch/arm/mach-davinci/dm355.c+1−0

@@ -411,6 +411,7 @@ static struct davinci_spi_platform_data dm355_spi0_pdata = { · 410 unmodified lines
411	.num_chipselect = 2,	411	.num_chipselect = 2,
412	.cshold_bug = true,	412	.cshold_bug = true,
413	.dma_event_q = EVENTQ_1,	413	.dma_event_q = EVENTQ_1,
		414	.prescaler_limit = 1,
414	};	415	};
415	static struct platform_device dm355_spi0_device = {	416	static struct platform_device dm355_spi0_device = {
416	.name = "spi_davinci",	417	.name = "spi_davinci",

arch/arm/mach-davinci/dm365.c+1−0

@@ -646,6 +646,7 @@ static struct davinci_spi_platform_data dm365_spi0_pdata = { · 645 unmodified lines
646	.version = SPI_VERSION_1,	646	.version = SPI_VERSION_1,
647	.num_chipselect = 2,	647	.num_chipselect = 2,
648	.dma_event_q = EVENTQ_3,	648	.dma_event_q = EVENTQ_3,
		649	.prescaler_limit = 1,
649	};	650	};
650		651
651	static struct resource dm365_spi0_resources[] = {	652	static struct resource dm365_spi0_resources[] = {

arch/powerpc/include/asm/mpc52xx_psc.h+4−1

 /* Structure of the hardware registers */
 struct mpc52xx_psc {
-	u8		mode;		/* PSC + 0x00 */
+	union {
+		u8	mode;		/* PSC + 0x00 */
+		u8	mr2;
+	};
 	u8		reserved0[3];
 	union {				/* PSC + 0x04 */
 		u16	status;

drivers/spi/Kconfig+20−0

@@ -326,6 +326,15 @@ config SPI_MESON_SPIFC · 325 unmodified lines
326	This enables master mode support for the SPIFC (SPI flash	326	This enables master mode support for the SPIFC (SPI flash
327	controller) available in Amlogic Meson SoCs.	327	controller) available in Amlogic Meson SoCs.
328		328
		329	config SPI_MT65XX
		330	tristate "MediaTek SPI controller"
		331	depends on ARCH_MEDIATEK \|\| COMPILE_TEST
		332	help
		333	This selects the MediaTek(R) SPI bus driver.
		334	If you want to use MediaTek(R) SPI interface,
		335	say Y or M here.If you are not sure, say N.
		336	SPI drivers for Mediatek MT65XX and MT81XX series ARM SoCs.
		337
329	config SPI_OC_TINY	338	config SPI_OC_TINY
330	tristate "OpenCores tiny SPI"	339	tristate "OpenCores tiny SPI"
331	depends on GPIOLIB \|\| COMPILE_TEST	340	depends on GPIOLIB \|\| COMPILE_TEST
@@ -598,6 +607,17 @@ config SPI_XILINX · 266 unmodified lines
598		607
599	Or for the DS570, see "XPS Serial Peripheral Interface (SPI) (v2.00b)"	608	Or for the DS570, see "XPS Serial Peripheral Interface (SPI) (v2.00b)"
600		609
		610	config SPI_XLP
		611	tristate "Netlogic XLP SPI controller driver"
		612	depends on CPU_XLP \|\| COMPILE_TEST
		613	help
		614	Enable support for the SPI controller on the Netlogic XLP SoCs.
		615	Currently supported XLP variants are XLP8XX, XLP3XX, XLP2XX, XLP9XX
		616	and XLP5XX.
		617
		618	If you have a Netlogic XLP platform say Y here.
		619	If unsure, say N.
		620
601	config SPI_XTENSA_XTFPGA	621	config SPI_XTENSA_XTFPGA
602	tristate "Xtensa SPI controller for xtfpga"	622	tristate "Xtensa SPI controller for xtfpga"
603	depends on (XTENSA && XTENSA_PLATFORM_XTFPGA) \|\| COMPILE_TEST	623	depends on (XTENSA && XTENSA_PLATFORM_XTFPGA) \|\| COMPILE_TEST

drivers/spi/Makefile+2−0

 obj-$(CONFIG_SPI_MPC512x_PSC)		+= spi-mpc512x-psc.o
 obj-$(CONFIG_SPI_MPC52xx_PSC)		+= spi-mpc52xx-psc.o
 obj-$(CONFIG_SPI_MPC52xx)		+= spi-mpc52xx.o
+obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
 obj-$(CONFIG_SPI_MXS)			+= spi-mxs.o
 obj-$(CONFIG_SPI_NUC900)		+= spi-nuc900.o
 obj-$(CONFIG_SPI_OC_TINY)		+= spi-oc-tiny.o
 obj-$(CONFIG_SPI_TXX9)			+= spi-txx9.o
 obj-$(CONFIG_SPI_XCOMM)		+= spi-xcomm.o
 obj-$(CONFIG_SPI_XILINX)		+= spi-xilinx.o
+obj-$(CONFIG_SPI_XLP)			+= spi-xlp.o
 obj-$(CONFIG_SPI_XTENSA_XTFPGA)		+= spi-xtensa-xtfpga.o
 obj-$(CONFIG_SPI_ZYNQMP_GQSPI)		+= spi-zynqmp-gqspi.o

drivers/spi/spi-atmel.c+0−1

@@ -19,7 +19,6 @@ · 18 unmodified lines
19	#include <linux/interrupt.h>	19	#include <linux/interrupt.h>
20	#include <linux/spi/spi.h>	20	#include <linux/spi/spi.h>
21	#include <linux/slab.h>	21	#include <linux/slab.h>
22	#include <linux/platform_data/atmel.h>
23	#include <linux/platform_data/dma-atmel.h>	22	#include <linux/platform_data/dma-atmel.h>
24	#include <linux/of.h>	23	#include <linux/of.h>
25		24

drivers/spi/spi-bcm2835.c+29−9

 					 struct spi_device *spi,
 					 struct spi_transfer *tfr,
 					 u32 cs,
-					 unsigned long xfer_time_us)
+					 unsigned long long xfer_time_us)
 {
 	struct bcm2835_spi *bs = spi_master_get_devdata(master);
 	unsigned long timeout;
 {
 	struct bcm2835_spi *bs = spi_master_get_devdata(master);
 	unsigned long spi_hz, clk_hz, cdiv;
-	unsigned long spi_used_hz, xfer_time_us;
+	unsigned long spi_used_hz;
+	unsigned long long xfer_time_us;
 	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
 	/* set clock */
 	spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
 	bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
-	/* handle all the modes */
+	/* handle all the 3-wire mode */
 	if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
 		cs |= BCM2835_SPI_CS_REN;
-	if (spi->mode & SPI_CPOL)
+	else
-		cs |= BCM2835_SPI_CS_CPOL;
+		cs &= ~BCM2835_SPI_CS_REN;
-	if (spi->mode & SPI_CPHA)
-		cs |= BCM2835_SPI_CS_CPHA;
 	/* for gpio_cs set dummy CS so that no HW-CS get changed
 	 * we can not run this in bcm2835_spi_set_cs, as it does
 	bs->rx_len = tfr->len;
 	/* calculate the estimated time in us the transfer runs */
-	xfer_time_us = tfr->len
+	xfer_time_us = (unsigned long long)tfr->len
 		* 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */
-		* 1000000 / spi_used_hz;
+		* 1000000;
+	do_div(xfer_time_us, spi_used_hz);
 	/* for short requests run polling*/
 	if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US)
 	return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs);
 }
+static int bcm2835_spi_prepare_message(struct spi_master *master,
+				       struct spi_message *msg)
+{
+	struct spi_device *spi = msg->spi;
+	struct bcm2835_spi *bs = spi_master_get_devdata(master);
+	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
+	cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA);
+	if (spi->mode & SPI_CPOL)
+		cs |= BCM2835_SPI_CS_CPOL;
+	if (spi->mode & SPI_CPHA)
+		cs |= BCM2835_SPI_CS_CPHA;
+	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
+	return 0;
+}
 static void bcm2835_spi_handle_err(struct spi_master *master,
 				   struct spi_message *msg)
 {
 	master->set_cs = bcm2835_spi_set_cs;
 	master->transfer_one = bcm2835_spi_transfer_one;
 	master->handle_err = bcm2835_spi_handle_err;
+	master->prepare_message = bcm2835_spi_prepare_message;
 	master->dev.of_node = pdev->dev.of_node;
 	bs = spi_master_get_devdata(master);

drivers/spi/spi-bcm63xx-hsspi.c+9−4

 #define HSSPI_FIFO_REG(x)			(0x200 + (x) * 0x200)
+#define HSSPI_OP_MULTIBIT			BIT(11)
 #define HSSPI_OP_CODE_SHIFT			13
 #define HSSPI_OP_SLEEP				(0 << HSSPI_OP_CODE_SHIFT)
 #define HSSPI_OP_READ_WRITE			(1 << HSSPI_OP_CODE_SHIFT)
 	if (opcode != HSSPI_OP_READ)
 		step_size -= HSSPI_OPCODE_LEN;
-	__raw_writel(0 << MODE_CTRL_PREPENDBYTE_CNT_SHIFT |
+	if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
-		     2 << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT |
+	    (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
-		     2 << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff,
+		opcode |= HSSPI_OP_MULTIBIT;
+	__raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT |
+		     1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff,
 		     bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
 	while (pending > 0) {
 	master->num_chipselect = 8;
 	master->setup = bcm63xx_hsspi_setup;
 	master->transfer_one_message = bcm63xx_hsspi_transfer_one;
-	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
+	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
+			    SPI_RX_DUAL | SPI_TX_DUAL;
 	master->bits_per_word_mask = SPI_BPW_MASK(8);
 	master->auto_runtime_pm = true;

drivers/spi/spi-bitbang-txrx.h+2−2

@@ -49,7 +49,7 @@ bitbang_txrx_be_cpha0(struct spi_device *spi, · 48 unmodified lines
49	{	49	{
50	/* if (cpol == 0) this is SPI_MODE_0; else this is SPI_MODE_2 */	50	/* if (cpol == 0) this is SPI_MODE_0; else this is SPI_MODE_2 */
51		51
52	bool oldbit = !(word & 1);	52	u32 oldbit = (!(word & (1<<(bits-1)))) << 31;
53	/* clock starts at inactive polarity */	53	/* clock starts at inactive polarity */
54	for (word <<= (32 - bits); likely(bits); bits--) {	54	for (word <<= (32 - bits); likely(bits); bits--) {
55		55
@@ -81,7 +81,7 @@ bitbang_txrx_be_cpha1(struct spi_device *spi, · 25 unmodified lines
81	{	81	{
82	/* if (cpol == 0) this is SPI_MODE_1; else this is SPI_MODE_3 */	82	/* if (cpol == 0) this is SPI_MODE_1; else this is SPI_MODE_3 */
83		83
84	bool oldbit = !(word & (1 << 31));	84	u32 oldbit = (!(word & (1<<(bits-1)))) << 31;
85	/* clock starts at inactive polarity */	85	/* clock starts at inactive polarity */
86	for (word <<= (32 - bits); likely(bits); bits--) {	86	for (word <<= (32 - bits); likely(bits); bits--) {
87		87

drivers/spi/spi-davinci.c+40−10

@@ -139,6 +139,8 @@ struct davinci_spi { · 138 unmodified lines
139	u32 (get_tx)(struct davinci_spi );	139	u32 (get_tx)(struct davinci_spi );
140		140
141	u8 *bytes_per_word;	141	u8 *bytes_per_word;
		142
		143	u8 prescaler_limit;
142	};	144	};
143		145
144	static struct davinci_spi_config davinci_spi_default_cfg;	146	static struct davinci_spi_config davinci_spi_default_cfg;
@@ -255,7 +257,7 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) · 110 unmodified lines
255	* This function calculates the prescale value that generates a clock rate	257	* This function calculates the prescale value that generates a clock rate
256	* less than or equal to the specified maximum.	258	* less than or equal to the specified maximum.
257	*	259	*
258	* Returns: calculated prescale - 1 for easy programming into SPI registers	260	* Returns: calculated prescale value for easy programming into SPI registers
259	* or negative error number if valid prescalar cannot be updated.	261	* or negative error number if valid prescalar cannot be updated.
260	*/	262	*/
261	static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,	263	static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
@@ -263,12 +265,13 @@ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, · 1 unmodified line
263	{	265	{
264	int ret;	266	int ret;
265		267
266	ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);	268	/* Subtract 1 to match what will be programmed into SPI register. */
		269	ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1;
267		270
268	if (ret < 1 \|\| ret > 256)	271	if (ret < dspi->prescaler_limit \|\| ret > 255)
269	return -EINVAL;	272	return -EINVAL;
270		273
271	return ret - 1;	274	return ret;
272	}	275	}
273		276
274	/**	277	/**
@@ -832,13 +835,40 @@ rx_dma_failed: · 557 unmodified lines
832	}	835	}
833		836
834	#if defined(CONFIG_OF)	837	#if defined(CONFIG_OF)
		838
		839	/* OF SPI data structure */
		840	struct davinci_spi_of_data {
		841	u8 version;
		842	u8 prescaler_limit;
		843	};
		844
		845	static const struct davinci_spi_of_data dm6441_spi_data = {
		846	.version = SPI_VERSION_1,
		847	.prescaler_limit = 2,
		848	};
		849
		850	static const struct davinci_spi_of_data da830_spi_data = {
		851	.version = SPI_VERSION_2,
		852	.prescaler_limit = 2,
		853	};
		854
		855	static const struct davinci_spi_of_data keystone_spi_data = {
		856	.version = SPI_VERSION_1,
		857	.prescaler_limit = 0,
		858	};
		859
835	static const struct of_device_id davinci_spi_of_match[] = {	860	static const struct of_device_id davinci_spi_of_match[] = {
836	{	861	{
837	.compatible = "ti,dm6441-spi",	862	.compatible = "ti,dm6441-spi",
		863	.data = &dm6441_spi_data,
838	},	864	},
839	{	865	{
840	.compatible = "ti,da830-spi",	866	.compatible = "ti,da830-spi",
841	.data = (void *)SPI_VERSION_2,	867	.data = &da830_spi_data,
		868	},
		869	{
		870	.compatible = "ti,keystone-spi",
		871	.data = &keystone_spi_data,
842	},	872	},
843	{ },	873	{ },
844	};	874	};
@@ -857,21 +887,21 @@ static int spi_davinci_get_pdata(struct platform_device *pdev, · 12 unmodified lines
857	struct davinci_spi *dspi)	887	struct davinci_spi *dspi)
858	{	888	{
859	struct device_node *node = pdev->dev.of_node;	889	struct device_node *node = pdev->dev.of_node;
		890	struct davinci_spi_of_data *spi_data;
860	struct davinci_spi_platform_data *pdata;	891	struct davinci_spi_platform_data *pdata;
861	unsigned int num_cs, intr_line = 0;	892	unsigned int num_cs, intr_line = 0;
862	const struct of_device_id *match;	893	const struct of_device_id *match;
863		894
864	pdata = &dspi->pdata;	895	pdata = &dspi->pdata;
865		896
866	pdata->version = SPI_VERSION_1;
867	match = of_match_device(davinci_spi_of_match, &pdev->dev);	897	match = of_match_device(davinci_spi_of_match, &pdev->dev);
868	if (!match)	898	if (!match)
869	return -ENODEV;	899	return -ENODEV;
870		900
871	/* match data has the SPI version number for SPI_VERSION_2 */	901	spi_data = (struct davinci_spi_of_data *)match->data;
872	if (match->data == (void *)SPI_VERSION_2)
873	pdata->version = SPI_VERSION_2;
874		902
		903	pdata->version = spi_data->version;
		904	pdata->prescaler_limit = spi_data->prescaler_limit;
875	/*	905	/*
876	* default num_cs is 1 and all chipsel are internal to the chip	906	* default num_cs is 1 and all chipsel are internal to the chip
877	* indicated by chip_sel being NULL or cs_gpios being NULL or	907	* indicated by chip_sel being NULL or cs_gpios being NULL or
@@ -991,7 +1021,7 @@ static int davinci_spi_probe(struct platform_device *pdev) · 113 unmodified lines
991		1021
992	dspi->bitbang.chipselect = davinci_spi_chipselect;	1022	dspi->bitbang.chipselect = davinci_spi_chipselect;
993	dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;	1023	dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
994		1024	dspi->prescaler_limit = pdata->prescaler_limit;
995	dspi->version = pdata->version;	1025	dspi->version = pdata->version;
996		1026
997	dspi->bitbang.flags = SPI_NO_CS \| SPI_LSB_FIRST \| SPI_LOOP;	1027	dspi->bitbang.flags = SPI_NO_CS \| SPI_LSB_FIRST \| SPI_LOOP;

drivers/spi/spi-dw-mmio.c+3−0

@@ -74,6 +74,9 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) · 73 unmodified lines
74		74
75	dws->max_freq = clk_get_rate(dwsmmio->clk);	75	dws->max_freq = clk_get_rate(dwsmmio->clk);
76		76
		77	of_property_read_u32(pdev->dev.of_node, "reg-io-width",
		78	&dws->reg_io_width);
		79
77	num_cs = 4;	80	num_cs = 4;
78		81
79	if (pdev->dev.of_node)	82	if (pdev->dev.of_node)

drivers/spi/spi-dw.c+2−2

@@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws) · 193 unmodified lines
194	else	194	else
195	txw = (u16 )(dws->tx);	195	txw = (u16 )(dws->tx);
196	}	196	}
197	dw_writel(dws, DW_SPI_DR, txw);	197	dw_write_io_reg(dws, DW_SPI_DR, txw);
198	dws->tx += dws->n_bytes;	198	dws->tx += dws->n_bytes;
199	}	199	}
200	}	200	}
@@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws) · 4 unmodified lines
205	u16 rxw;	205	u16 rxw;
206		206
207	while (max--) {	207	while (max--) {
208	rxw = dw_readl(dws, DW_SPI_DR);	208	rxw = dw_read_io_reg(dws, DW_SPI_DR);
209	/* Care rx only if the transfer's original "rx" is not null */	209	/* Care rx only if the transfer's original "rx" is not null */
210	if (dws->rx_end - dws->len) {	210	if (dws->rx_end - dws->len) {
211	if (dws->n_bytes == 1)	211	if (dws->n_bytes == 1)

drivers/spi/spi-dw.h+35−0

@@ -109,6 +109,7 @@ struct dw_spi { · 108 unmodified lines
109	u32 fifo_len; /* depth of the FIFO buffer */	109	u32 fifo_len; /* depth of the FIFO buffer */
110	u32 max_freq; /* max bus freq supported */	110	u32 max_freq; /* max bus freq supported */
111		111
		112	u32 reg_io_width; /* DR I/O width in bytes */
112	u16 bus_num;	113	u16 bus_num;
113	u16 num_cs; /* supported slave numbers */	114	u16 num_cs; /* supported slave numbers */
114		115
@@ -145,11 +146,45 @@ static inline u32 dw_readl(struct dw_spi *dws, u32 offset) · 30 unmodified lines
145	return __raw_readl(dws->regs + offset);	146	return __raw_readl(dws->regs + offset);
146	}	147	}
147		148
		149	static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
		150	{
		151	return __raw_readw(dws->regs + offset);
		152	}
		153
148	static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)	154	static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
149	{	155	{
150	__raw_writel(val, dws->regs + offset);	156	__raw_writel(val, dws->regs + offset);
151	}	157	}
152		158
		159	static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
		160	{
		161	__raw_writew(val, dws->regs + offset);
		162	}
		163
		164	static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
		165	{
		166	switch (dws->reg_io_width) {
		167	case 2:
		168	return dw_readw(dws, offset);
		169	case 4:
		170	default:
		171	return dw_readl(dws, offset);
		172	}
		173	}
		174
		175	static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
		176	{
		177	switch (dws->reg_io_width) {
		178	case 2:
		179	dw_writew(dws, offset, val);
		180	break;
		181	case 4:
		182	default:
		183	dw_writel(dws, offset, val);
		184	break;
		185	}
		186	}
		187
153	static inline void spi_enable_chip(struct dw_spi *dws, int enable)	188	static inline void spi_enable_chip(struct dw_spi *dws, int enable)
154	{	189	{
155	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));	190	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));

drivers/spi/spi-fsl-espi.c+55−34

@@ -21,6 +21,7 @@ · 20 unmodified lines
21	#include <linux/of_platform.h>	21	#include <linux/of_platform.h>
22	#include <linux/platform_device.h>	22	#include <linux/platform_device.h>
23	#include <linux/spi/spi.h>	23	#include <linux/spi/spi.h>
		24	#include <linux/pm_runtime.h>
24	#include <sysdev/fsl_soc.h>	25	#include <sysdev/fsl_soc.h>
25		26
26	#include "spi-fsl-lib.h"	27	#include "spi-fsl-lib.h"
@@ -85,6 +86,8 @@ struct fsl_espi_transfer { · 58 unmodified lines
85	#define SPCOM_TRANLEN(x) ((x) << 0)	86	#define SPCOM_TRANLEN(x) ((x) << 0)
86	#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */	87	#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
87		88
		89	#define AUTOSUSPEND_TIMEOUT 2000
		90
88	static void fsl_espi_change_mode(struct spi_device *spi)	91	static void fsl_espi_change_mode(struct spi_device *spi)
89	{	92	{
90	struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);	93	struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
@@ -485,6 +488,8 @@ static int fsl_espi_setup(struct spi_device *spi) · 394 unmodified lines
485	mpc8xxx_spi = spi_master_get_devdata(spi->master);	488	mpc8xxx_spi = spi_master_get_devdata(spi->master);
486	reg_base = mpc8xxx_spi->reg_base;	489	reg_base = mpc8xxx_spi->reg_base;
487		490
		491	pm_runtime_get_sync(mpc8xxx_spi->dev);
		492
488	hw_mode = cs->hw_mode; /* Save original settings */	493	hw_mode = cs->hw_mode; /* Save original settings */
489	cs->hw_mode = mpc8xxx_spi_read_reg(	494	cs->hw_mode = mpc8xxx_spi_read_reg(
490	&reg_base->csmode[spi->chip_select]);	495	&reg_base->csmode[spi->chip_select]);
@@ -507,6 +512,10 @@ static int fsl_espi_setup(struct spi_device *spi) · 16 unmodified lines
507	mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);	512	mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);
508		513
509	retval = fsl_espi_setup_transfer(spi, NULL);	514	retval = fsl_espi_setup_transfer(spi, NULL);
		515
		516	pm_runtime_mark_last_busy(mpc8xxx_spi->dev);
		517	pm_runtime_put_autosuspend(mpc8xxx_spi->dev);
		518
510	if (retval < 0) {	519	if (retval < 0) {
511	cs->hw_mode = hw_mode; /* Restore settings */	520	cs->hw_mode = hw_mode; /* Restore settings */
512	return retval;	521	return retval;
@@ -604,20 +613,14 @@ static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) · 91 unmodified lines
604	return ret;	613	return ret;
605	}	614	}
606		615
607	static void fsl_espi_remove(struct mpc8xxx_spi *mspi)	616	#ifdef CONFIG_PM
		617	static int fsl_espi_runtime_suspend(struct device *dev)
608	{	618	{
609	iounmap(mspi->reg_base);	619	struct spi_master *master = dev_get_drvdata(dev);
610	}	620	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
611		621	struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
612	static int fsl_espi_suspend(struct spi_master *master)
613	{
614	struct mpc8xxx_spi *mpc8xxx_spi;
615	struct fsl_espi_reg *reg_base;
616	u32 regval;	622	u32 regval;
617		623
618	mpc8xxx_spi = spi_master_get_devdata(master);
619	reg_base = mpc8xxx_spi->reg_base;
620
621	regval = mpc8xxx_spi_read_reg(&reg_base->mode);	624	regval = mpc8xxx_spi_read_reg(&reg_base->mode);
622	regval &= ~SPMODE_ENABLE;	625	regval &= ~SPMODE_ENABLE;
623	mpc8xxx_spi_write_reg(&reg_base->mode, regval);	626	mpc8xxx_spi_write_reg(&reg_base->mode, regval);
@@ -625,21 +628,20 @@ static int fsl_espi_suspend(struct spi_master *master) · 1 unmodified line
625	return 0;	628	return 0;
626	}	629	}
627		630
628	static int fsl_espi_resume(struct spi_master *master)	631	static int fsl_espi_runtime_resume(struct device *dev)
629	{	632	{
630	struct mpc8xxx_spi *mpc8xxx_spi;	633	struct spi_master *master = dev_get_drvdata(dev);
631	struct fsl_espi_reg *reg_base;	634	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
		635	struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
632	u32 regval;	636	u32 regval;
633		637
634	mpc8xxx_spi = spi_master_get_devdata(master);
635	reg_base = mpc8xxx_spi->reg_base;
636
637	regval = mpc8xxx_spi_read_reg(&reg_base->mode);	638	regval = mpc8xxx_spi_read_reg(&reg_base->mode);
638	regval \|= SPMODE_ENABLE;	639	regval \|= SPMODE_ENABLE;
639	mpc8xxx_spi_write_reg(&reg_base->mode, regval);	640	mpc8xxx_spi_write_reg(&reg_base->mode, regval);
640		641
641	return 0;	642	return 0;
642	}	643	}
		644	#endif
643		645
644	static struct spi_master * fsl_espi_probe(struct device *dev,	646	static struct spi_master * fsl_espi_probe(struct device *dev,
645	struct resource *mem, unsigned int irq)	647	struct resource *mem, unsigned int irq)
@@ -667,25 +669,23 @@ static struct spi_master * fsl_espi_probe(struct device *dev, · 21 unmodified lines
667	master->setup = fsl_espi_setup;	669	master->setup = fsl_espi_setup;
668	master->cleanup = fsl_espi_cleanup;	670	master->cleanup = fsl_espi_cleanup;
669	master->transfer_one_message = fsl_espi_do_one_msg;	671	master->transfer_one_message = fsl_espi_do_one_msg;
670	master->prepare_transfer_hardware = fsl_espi_resume;	672	master->auto_runtime_pm = true;
671	master->unprepare_transfer_hardware = fsl_espi_suspend;
672		673
673	mpc8xxx_spi = spi_master_get_devdata(master);	674	mpc8xxx_spi = spi_master_get_devdata(master);
674	mpc8xxx_spi->spi_remove = fsl_espi_remove;
675		675
676	mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));	676	mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
677	if (!mpc8xxx_spi->reg_base) {	677	if (IS_ERR(mpc8xxx_spi->reg_base)) {
678	ret = -ENOMEM;	678	ret = PTR_ERR(mpc8xxx_spi->reg_base);
679	goto err_probe;	679	goto err_probe;
680	}	680	}
681		681
682	reg_base = mpc8xxx_spi->reg_base;	682	reg_base = mpc8xxx_spi->reg_base;
683		683
684	/* Register for SPI Interrupt */	684	/* Register for SPI Interrupt */
685	ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,	685	ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq,
686	0, "fsl_espi", mpc8xxx_spi);	686	0, "fsl_espi", mpc8xxx_spi);
687	if (ret)	687	if (ret)
688	goto free_irq;	688	goto err_probe;
689		689
690	if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {	690	if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
691	mpc8xxx_spi->rx_shift = 16;	691	mpc8xxx_spi->rx_shift = 16;
@@ -731,18 +731,27 @@ static struct spi_master * fsl_espi_probe(struct device *dev, · 39 unmodified lines
731		731
732	mpc8xxx_spi_write_reg(&reg_base->mode, regval);	732	mpc8xxx_spi_write_reg(&reg_base->mode, regval);
733		733
734	ret = spi_register_master(master);	734	pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
		735	pm_runtime_use_autosuspend(dev);
		736	pm_runtime_set_active(dev);
		737	pm_runtime_enable(dev);
		738	pm_runtime_get_sync(dev);
		739
		740	ret = devm_spi_register_master(dev, master);
735	if (ret < 0)	741	if (ret < 0)
736	goto unreg_master;	742	goto err_pm;
737		743
738	dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);	744	dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
739		745
		746	pm_runtime_mark_last_busy(dev);
		747	pm_runtime_put_autosuspend(dev);
		748
740	return master;	749	return master;
741		750
742	unreg_master:	751	err_pm:
743	free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);	752	pm_runtime_put_noidle(dev);
744	free_irq:	753	pm_runtime_disable(dev);
745	iounmap(mpc8xxx_spi->reg_base);	754	pm_runtime_set_suspended(dev);
746	err_probe:	755	err_probe:
747	spi_master_put(master);	756	spi_master_put(master);
748	err:	757	err:
@@ -809,7 +818,9 @@ err: · 60 unmodified lines
809		818
810	static int of_fsl_espi_remove(struct platform_device *dev)	819	static int of_fsl_espi_remove(struct platform_device *dev)
811	{	820	{
812	return mpc8xxx_spi_remove(&dev->dev);	821	pm_runtime_disable(&dev->dev);
		822
		823	return 0;
813	}	824	}
814		825
815	#ifdef CONFIG_PM_SLEEP	826	#ifdef CONFIG_PM_SLEEP
@@ -824,7 +835,11 @@ static int of_fsl_espi_suspend(struct device *dev) · 8 unmodified lines
824	return ret;	835	return ret;
825	}	836	}
826		837
827	return fsl_espi_suspend(master);	838	ret = pm_runtime_force_suspend(dev);
		839	if (ret < 0)
		840	return ret;
		841
		842	return 0;
828	}	843	}
829		844
830	static int of_fsl_espi_resume(struct device *dev)	845	static int of_fsl_espi_resume(struct device *dev)
@@ -834,7 +849,7 @@ static int of_fsl_espi_resume(struct device *dev) · 3 unmodified lines
834	struct mpc8xxx_spi *mpc8xxx_spi;	849	struct mpc8xxx_spi *mpc8xxx_spi;
835	struct fsl_espi_reg *reg_base;	850	struct fsl_espi_reg *reg_base;
836	u32 regval;	851	u32 regval;
837	int i;	852	int i, ret;
838		853
839	mpc8xxx_spi = spi_master_get_devdata(master);	854	mpc8xxx_spi = spi_master_get_devdata(master);
840	reg_base = mpc8xxx_spi->reg_base;	855	reg_base = mpc8xxx_spi->reg_base;
@@ -854,11 +869,17 @@ static int of_fsl_espi_resume(struct device *dev) · 13 unmodified lines
854		869
855	mpc8xxx_spi_write_reg(&reg_base->mode, regval);	870	mpc8xxx_spi_write_reg(&reg_base->mode, regval);
856		871
		872	ret = pm_runtime_force_resume(dev);
		873	if (ret < 0)
		874	return ret;
		875
857	return spi_master_resume(master);	876	return spi_master_resume(master);
858	}	877	}
859	#endif /* CONFIG_PM_SLEEP */	878	#endif /* CONFIG_PM_SLEEP */
860		879
861	static const struct dev_pm_ops espi_pm = {	880	static const struct dev_pm_ops espi_pm = {
		881	SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
		882	fsl_espi_runtime_resume, NULL)
862	SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)	883	SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
863	};	884	};
864		885

drivers/spi/spi-fsl-lib.c+0−19

@@ -114,25 +114,6 @@ void mpc8xxx_spi_probe(struct device dev, struct resource mem, · 113 unmodified lines
114	}	114	}
115	EXPORT_SYMBOL_GPL(mpc8xxx_spi_probe);	115	EXPORT_SYMBOL_GPL(mpc8xxx_spi_probe);
116		116
117	int mpc8xxx_spi_remove(struct device *dev)
118	{
119	struct mpc8xxx_spi *mpc8xxx_spi;
120	struct spi_master *master;
121
122	master = dev_get_drvdata(dev);
123	mpc8xxx_spi = spi_master_get_devdata(master);
124
125	spi_unregister_master(master);
126
127	free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
128
129	if (mpc8xxx_spi->spi_remove)
130	mpc8xxx_spi->spi_remove(mpc8xxx_spi);
131
132	return 0;
133	}
134	EXPORT_SYMBOL_GPL(mpc8xxx_spi_remove);
135
136	int of_mpc8xxx_spi_probe(struct platform_device *ofdev)	117	int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
137	{	118	{
138	struct device *dev = &ofdev->dev;	119	struct device *dev = &ofdev->dev;

drivers/spi/spi-fsl-lib.h+0−3

@@ -54,9 +54,6 @@ struct mpc8xxx_spi { · 53 unmodified lines
54	void (get_rx) (u32 rx_data, struct mpc8xxx_spi );	54	void (get_rx) (u32 rx_data, struct mpc8xxx_spi );
55	u32(get_tx) (struct mpc8xxx_spi );	55	u32(get_tx) (struct mpc8xxx_spi );
56		56
57	/* hooks for different controller driver */
58	void (spi_remove) (struct mpc8xxx_spi mspi);
59
60	unsigned int count;	57	unsigned int count;
61	unsigned int irq;	58	unsigned int irq;
62		59

drivers/spi/spi-fsl-spi.c+17−26

 	return ret;
 }
-static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
-{
-	iounmap(mspi->reg_base);
-	fsl_spi_cpm_free(mspi);
-}
 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
 {
 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 	master->transfer_one_message = fsl_spi_do_one_msg;
 	mpc8xxx_spi = spi_master_get_devdata(master);
-	mpc8xxx_spi->spi_remove = fsl_spi_remove;
 	mpc8xxx_spi->max_bits_per_word = 32;
 	mpc8xxx_spi->type = fsl_spi_get_type(dev);
 	if (ret)
 		goto err_cpm_init;
-	mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
+	mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
-	if (mpc8xxx_spi->reg_base == NULL) {
+	if (IS_ERR(mpc8xxx_spi->reg_base)) {
-		ret = -ENOMEM;
+		ret = PTR_ERR(mpc8xxx_spi->reg_base);
-		goto err_ioremap;
+		goto err_probe;
 	}
 	if (mpc8xxx_spi->type == TYPE_GRLIB)
 					&mpc8xxx_spi->tx_shift, 8, 1);
 	/* Register for SPI Interrupt */
-	ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq,
+	ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
-			  0, "fsl_spi", mpc8xxx_spi);
+			       0, "fsl_spi", mpc8xxx_spi);
 	if (ret != 0)
-		goto free_irq;
+		goto err_probe;
 	reg_base = mpc8xxx_spi->reg_base;
 	mpc8xxx_spi_write_reg(&reg_base->mode, regval);
-	ret = spi_register_master(master);
+	ret = devm_spi_register_master(dev, master);
 	if (ret < 0)
-		goto unreg_master;
+		goto err_probe;
 	dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
 		 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
 	return master;
-unreg_master:
+err_probe:
-	free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
-free_irq:
-	iounmap(mpc8xxx_spi->reg_base);
-err_ioremap:
 	fsl_spi_cpm_free(mpc8xxx_spi);
 err_cpm_init:
 	spi_master_put(master);
 {
 	struct spi_master *master = platform_get_drvdata(ofdev);
 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
-	int ret;
-	ret = mpc8xxx_spi_remove(&ofdev->dev);
+	fsl_spi_cpm_free(mpc8xxx_spi);
-	if (ret)
-		return ret;
 	if (mpc8xxx_spi->type == TYPE_FSL)
 		of_fsl_spi_free_chipselects(&ofdev->dev);
 	return 0;
 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
 {
-	return mpc8xxx_spi_remove(&pdev->dev);
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
+	fsl_spi_cpm_free(mpc8xxx_spi);
+	return 0;
 }
 MODULE_ALIAS("platform:mpc8xxx_spi");

drivers/spi/spi-img-spfi.c+60−13

@@ -105,6 +105,10 @@ struct img_spfi { · 104 unmodified lines
105	bool rx_dma_busy;	105	bool rx_dma_busy;
106	};	106	};
107		107
		108	struct img_spfi_device_data {
		109	bool gpio_requested;
		110	};
		111
108	static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg)	112	static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg)
109	{	113	{
110	return readl(spfi->regs + reg);	114	return readl(spfi->regs + reg);
@@ -267,15 +271,15 @@ static int img_spfi_start_pio(struct spi_master *master, · 156 unmodified lines
267	cpu_relax();	271	cpu_relax();
268	}	272	}
269		273
270	ret = spfi_wait_all_done(spfi);
271	if (ret < 0)
272	return ret;
273
274	if (rx_bytes > 0 \|\| tx_bytes > 0) {	274	if (rx_bytes > 0 \|\| tx_bytes > 0) {
275	dev_err(spfi->dev, "PIO transfer timed out\n");	275	dev_err(spfi->dev, "PIO transfer timed out\n");
276	return -ETIMEDOUT;	276	return -ETIMEDOUT;
277	}	277	}
278		278
		279	ret = spfi_wait_all_done(spfi);
		280	if (ret < 0)
		281	return ret;
		282
279	return 0;	283	return 0;
280	}	284	}
281		285
@@ -440,21 +444,50 @@ static int img_spfi_unprepare(struct spi_master *master, · 158 unmodified lines
440		444
441	static int img_spfi_setup(struct spi_device *spi)	445	static int img_spfi_setup(struct spi_device *spi)
442	{	446	{
443	int ret;	447	int ret = -EINVAL;
444		448	struct img_spfi_device_data *spfi_data = spi_get_ctldata(spi);
445	ret = gpio_request_one(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ?	449
446	GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,	450	if (!spfi_data) {
447	dev_name(&spi->dev));	451	spfi_data = kzalloc(sizeof(*spfi_data), GFP_KERNEL);
448	if (ret)	452	if (!spfi_data)
449	dev_err(&spi->dev, "can't request chipselect gpio %d\n",	453	return -ENOMEM;
		454	spfi_data->gpio_requested = false;
		455	spi_set_ctldata(spi, spfi_data);
		456	}
		457	if (!spfi_data->gpio_requested) {
		458	ret = gpio_request_one(spi->cs_gpio,
		459	(spi->mode & SPI_CS_HIGH) ?
		460	GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,
		461	dev_name(&spi->dev));
		462	if (ret)
		463	dev_err(&spi->dev, "can't request chipselect gpio %d\n",
450	spi->cs_gpio);	464	spi->cs_gpio);
451		465	else
		466	spfi_data->gpio_requested = true;
		467	} else {
		468	if (gpio_is_valid(spi->cs_gpio)) {
		469	int mode = ((spi->mode & SPI_CS_HIGH) ?
		470	GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH);
		471
		472	ret = gpio_direction_output(spi->cs_gpio, mode);
		473	if (ret)
		474	dev_err(&spi->dev, "chipselect gpio %d setup failed (%d)\n",
		475	spi->cs_gpio, ret);
		476	}
		477	}
452	return ret;	478	return ret;
453	}	479	}
454		480
455	static void img_spfi_cleanup(struct spi_device *spi)	481	static void img_spfi_cleanup(struct spi_device *spi)
456	{	482	{
457	gpio_free(spi->cs_gpio);	483	struct img_spfi_device_data *spfi_data = spi_get_ctldata(spi);
		484
		485	if (spfi_data) {
		486	if (spfi_data->gpio_requested)
		487	gpio_free(spi->cs_gpio);
		488	kfree(spfi_data);
		489	spi_set_ctldata(spi, NULL);
		490	}
458	}	491	}
459		492
460	static void img_spfi_config(struct spi_master master, struct spi_device spi,	493	static void img_spfi_config(struct spi_master master, struct spi_device spi,
@@ -548,6 +581,7 @@ static int img_spfi_probe(struct platform_device *pdev) · 87 unmodified lines
548	struct img_spfi *spfi;	581	struct img_spfi *spfi;
549	struct resource *res;	582	struct resource *res;
550	int ret;	583	int ret;
		584	u32 max_speed_hz;
551		585
552	master = spi_alloc_master(&pdev->dev, sizeof(*spfi));	586	master = spi_alloc_master(&pdev->dev, sizeof(*spfi));
553	if (!master)	587	if (!master)
@@ -612,6 +646,19 @@ static int img_spfi_probe(struct platform_device *pdev) · 58 unmodified lines
612	master->max_speed_hz = clk_get_rate(spfi->spfi_clk) / 4;	646	master->max_speed_hz = clk_get_rate(spfi->spfi_clk) / 4;
613	master->min_speed_hz = clk_get_rate(spfi->spfi_clk) / 512;	647	master->min_speed_hz = clk_get_rate(spfi->spfi_clk) / 512;
614		648
		649	/*
		650	* Maximum speed supported by spfi is limited to the lower value
		651	* between 1/4 of the SPFI clock or to "spfi-max-frequency"
		652	* defined in the device tree.
		653	* If no value is defined in the device tree assume the maximum
		654	* speed supported to be 1/4 of the SPFI clock.
		655	*/
		656	if (!of_property_read_u32(spfi->dev->of_node, "spfi-max-frequency",
		657	&max_speed_hz)) {
		658	if (master->max_speed_hz > max_speed_hz)
		659	master->max_speed_hz = max_speed_hz;
		660	}
		661
615	master->setup = img_spfi_setup;	662	master->setup = img_spfi_setup;
616	master->cleanup = img_spfi_cleanup;	663	master->cleanup = img_spfi_cleanup;
617	master->transfer_one = img_spfi_transfer_one;	664	master->transfer_one = img_spfi_transfer_one;

drivers/spi/spi-mpc512x-psc.c+47−23

 #include <linux/gpio.h>
 #include <asm/mpc52xx_psc.h>
+enum {
+	TYPE_MPC5121,
+	TYPE_MPC5125,
+};
+/*
+ * This macro abstracts the differences in the PSC register layout between
+ * MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc).
+ */
+#define psc_addr(mps, regname) ({					\
+	void *__ret = NULL;						\
+	switch (mps->type) {						\
+	case TYPE_MPC5121: {						\
+			struct mpc52xx_psc __iomem *psc = mps->psc;	\
+			__ret = &psc->regname;				\
+		};							\
+		break;							\
+	case TYPE_MPC5125: {						\
+			struct mpc5125_psc __iomem *psc = mps->psc;	\
+			__ret = &psc->regname;				\
+		};							\
+		break;							\
+	}								\
+	__ret; })
 struct mpc512x_psc_spi {
 	void (*cs_control)(struct spi_device *spi, bool on);
 	/* driver internal data */
-	struct mpc52xx_psc __iomem *psc;
+	int type;
+	void __iomem *psc;
 	struct mpc512x_psc_fifo __iomem *fifo;
 	unsigned int irq;
 	u8 bits_per_word;
 {
 	struct mpc512x_psc_spi_cs *cs = spi->controller_state;
 	struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
-	struct mpc52xx_psc __iomem *psc = mps->psc;
 	u32 sicr;
 	u32 ccr;
 	int speed;
 	u16 bclkdiv;
-	sicr = in_be32(&psc->sicr);
+	sicr = in_be32(psc_addr(mps, sicr));
 	/* Set clock phase and polarity */
 	if (spi->mode & SPI_CPHA)
 		sicr |= 0x10000000;
 	else
 		sicr &= ~0x10000000;
-	out_be32(&psc->sicr, sicr);
+	out_be32(psc_addr(mps, sicr), sicr);
-	ccr = in_be32(&psc->ccr);
+	ccr = in_be32(psc_addr(mps, ccr));
 	ccr &= 0xFF000000;
 	speed = cs->speed_hz;
 	if (!speed)
 	bclkdiv = (mps->mclk_rate / speed) - 1;
 	ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
-	out_be32(&psc->ccr, ccr);
+	out_be32(psc_addr(mps, ccr), ccr);
 	mps->bits_per_word = cs->bits_per_word;
 	if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
 static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master)
 {
 	struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
-	struct mpc52xx_psc __iomem *psc = mps->psc;
 	dev_dbg(&master->dev, "%s()\n", __func__);
 	/* Zero MR2 */
-	in_8(&psc->mode);
+	in_8(psc_addr(mps, mr2));
-	out_8(&psc->mode, 0x0);
+	out_8(psc_addr(mps, mr2), 0x0);
 	/* enable transmitter/receiver */
-	out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
+	out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
 	return 0;
 }
 static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master)
 {
 	struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
-	struct mpc52xx_psc __iomem *psc = mps->psc;
 	struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 	dev_dbg(&master->dev, "%s()\n", __func__);
 	/* disable transmitter/receiver and fifo interrupt */
-	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
+	out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 	out_be32(&fifo->tximr, 0);
 	return 0;
 static int mpc512x_psc_spi_port_config(struct spi_master *master,
 				       struct mpc512x_psc_spi *mps)
 {
-	struct mpc52xx_psc __iomem *psc = mps->psc;
 	struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 	u32 sicr;
 	u32 ccr;
 	u16 bclkdiv;
 	/* Reset the PSC into a known state */
-	out_8(&psc->command, MPC52xx_PSC_RST_RX);
+	out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX);
-	out_8(&psc->command, MPC52xx_PSC_RST_TX);
+	out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX);
-	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
+	out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 	/* Disable psc interrupts all useful interrupts are in fifo */
-	out_be16(&psc->isr_imr.imr, 0);
+	out_be16(psc_addr(mps, isr_imr.imr), 0);
 	/* Disable fifo interrupts, will be enabled later */
 	out_be32(&fifo->tximr, 0);
 		0x00004000 |	/* MSTR = 1   -- SPI master */
 		0x00000800;	/* UseEOF = 1 -- SS low until EOF */
-	out_be32(&psc->sicr, sicr);
+	out_be32(psc_addr(mps, sicr), sicr);
-	ccr = in_be32(&psc->ccr);
+	ccr = in_be32(psc_addr(mps, ccr));
 	ccr &= 0xFF000000;
 	speed = 1000000;	/* default 1MHz */
 	bclkdiv = (mps->mclk_rate / speed) - 1;
 	ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
-	out_be32(&psc->ccr, ccr);
+	out_be32(psc_addr(mps, ccr), ccr);
 	/* Set 2ms DTL delay */
-	out_8(&psc->ctur, 0x00);
+	out_8(psc_addr(mps, ctur), 0x00);
-	out_8(&psc->ctlr, 0x82);
+	out_8(psc_addr(mps, ctlr), 0x82);
 	/* we don't use the alarms */
 	out_be32(&fifo->rxalarm, 0xfff);
 	dev_set_drvdata(dev, master);
 	mps = spi_master_get_devdata(master);
+	mps->type = (int)of_device_get_match_data(dev);
 	mps->irq = irq;
 	if (pdata == NULL) {
 }
 static const struct of_device_id mpc512x_psc_spi_of_match[] = {
-	{ .compatible = "fsl,mpc5121-psc-spi", },
+	{ .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 },
+	{ .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 },
 	{},
 };

drivers/spi/spi-mt65xx.c+726−0

@@ -0,0 +1,726 @@
	1	/*
	2	* Copyright (c) 2015 MediaTek Inc.
	3	* Author: Leilk Liu <leilk.liu@mediatek.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/clk.h>
	16	#include <linux/device.h>
	17	#include <linux/err.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/io.h>
	20	#include <linux/ioport.h>
	21	#include <linux/module.h>
	22	#include <linux/of.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/platform_data/spi-mt65xx.h>
	25	#include <linux/pm_runtime.h>
	26	#include <linux/spi/spi.h>
	27
	28	#define SPI_CFG0_REG 0x0000
	29	#define SPI_CFG1_REG 0x0004
	30	#define SPI_TX_SRC_REG 0x0008
	31	#define SPI_RX_DST_REG 0x000c
	32	#define SPI_TX_DATA_REG 0x0010
	33	#define SPI_RX_DATA_REG 0x0014
	34	#define SPI_CMD_REG 0x0018
	35	#define SPI_STATUS0_REG 0x001c
	36	#define SPI_PAD_SEL_REG 0x0024
	37
	38	#define SPI_CFG0_SCK_HIGH_OFFSET 0
	39	#define SPI_CFG0_SCK_LOW_OFFSET 8
	40	#define SPI_CFG0_CS_HOLD_OFFSET 16
	41	#define SPI_CFG0_CS_SETUP_OFFSET 24
	42
	43	#define SPI_CFG1_CS_IDLE_OFFSET 0
	44	#define SPI_CFG1_PACKET_LOOP_OFFSET 8
	45	#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
	46	#define SPI_CFG1_GET_TICK_DLY_OFFSET 30
	47
	48	#define SPI_CFG1_CS_IDLE_MASK 0xff
	49	#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
	50	#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
	51
	52	#define SPI_CMD_ACT BIT(0)
	53	#define SPI_CMD_RESUME BIT(1)
	54	#define SPI_CMD_RST BIT(2)
	55	#define SPI_CMD_PAUSE_EN BIT(4)
	56	#define SPI_CMD_DEASSERT BIT(5)
	57	#define SPI_CMD_CPHA BIT(8)
	58	#define SPI_CMD_CPOL BIT(9)
	59	#define SPI_CMD_RX_DMA BIT(10)
	60	#define SPI_CMD_TX_DMA BIT(11)
	61	#define SPI_CMD_TXMSBF BIT(12)
	62	#define SPI_CMD_RXMSBF BIT(13)
	63	#define SPI_CMD_RX_ENDIAN BIT(14)
	64	#define SPI_CMD_TX_ENDIAN BIT(15)
	65	#define SPI_CMD_FINISH_IE BIT(16)
	66	#define SPI_CMD_PAUSE_IE BIT(17)
	67
	68	#define MT8173_SPI_MAX_PAD_SEL 3
	69
	70	#define MTK_SPI_PAUSE_INT_STATUS 0x2
	71
	72	#define MTK_SPI_IDLE 0
	73	#define MTK_SPI_PAUSED 1
	74
	75	#define MTK_SPI_MAX_FIFO_SIZE 32
	76	#define MTK_SPI_PACKET_SIZE 1024
	77
	78	struct mtk_spi_compatible {
	79	bool need_pad_sel;
	80	/* Must explicitly send dummy Tx bytes to do Rx only transfer */
	81	bool must_tx;
	82	};
	83
	84	struct mtk_spi {
	85	void __iomem *base;
	86	u32 state;
	87	u32 pad_sel;
	88	struct clk spi_clk, parent_clk;
	89	struct spi_transfer *cur_transfer;
	90	u32 xfer_len;
	91	struct scatterlist tx_sgl, rx_sgl;
	92	u32 tx_sgl_len, rx_sgl_len;
	93	const struct mtk_spi_compatible *dev_comp;
	94	};
	95
	96	static const struct mtk_spi_compatible mt6589_compat;
	97	static const struct mtk_spi_compatible mt8135_compat;
	98	static const struct mtk_spi_compatible mt8173_compat = {
	99	.need_pad_sel = true,
	100	.must_tx = true,
	101	};
	102
	103	/*
	104	* A piece of default chip info unless the platform
	105	* supplies it.
	106	*/
	107	static const struct mtk_chip_config mtk_default_chip_info = {
	108	.rx_mlsb = 1,
	109	.tx_mlsb = 1,
	110	};
	111
	112	static const struct of_device_id mtk_spi_of_match[] = {
	113	{ .compatible = "mediatek,mt6589-spi", .data = (void *)&mt6589_compat },
	114	{ .compatible = "mediatek,mt8135-spi", .data = (void *)&mt8135_compat },
	115	{ .compatible = "mediatek,mt8173-spi", .data = (void *)&mt8173_compat },
	116	{}
	117	};
	118	MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
	119
	120	static void mtk_spi_reset(struct mtk_spi *mdata)
	121	{
	122	u32 reg_val;
	123
	124	/* set the software reset bit in SPI_CMD_REG. */
	125	reg_val = readl(mdata->base + SPI_CMD_REG);
	126	reg_val \|= SPI_CMD_RST;
	127	writel(reg_val, mdata->base + SPI_CMD_REG);
	128
	129	reg_val = readl(mdata->base + SPI_CMD_REG);
	130	reg_val &= ~SPI_CMD_RST;
	131	writel(reg_val, mdata->base + SPI_CMD_REG);
	132	}
	133
	134	static void mtk_spi_config(struct mtk_spi *mdata,
	135	struct mtk_chip_config *chip_config)
	136	{
	137	u32 reg_val;
	138
	139	reg_val = readl(mdata->base + SPI_CMD_REG);
	140
	141	/* set the mlsbx and mlsbtx */
	142	if (chip_config->tx_mlsb)
	143	reg_val \|= SPI_CMD_TXMSBF;
	144	else
	145	reg_val &= ~SPI_CMD_TXMSBF;
	146	if (chip_config->rx_mlsb)
	147	reg_val \|= SPI_CMD_RXMSBF;
	148	else
	149	reg_val &= ~SPI_CMD_RXMSBF;
	150
	151	/* set the tx/rx endian */
	152	#ifdef __LITTLE_ENDIAN
	153	reg_val &= ~SPI_CMD_TX_ENDIAN;
	154	reg_val &= ~SPI_CMD_RX_ENDIAN;
	155	#else
	156	reg_val \|= SPI_CMD_TX_ENDIAN;
	157	reg_val \|= SPI_CMD_RX_ENDIAN;
	158	#endif
	159
	160	/* set finish and pause interrupt always enable */
	161	reg_val \|= SPI_CMD_FINISH_IE \| SPI_CMD_PAUSE_IE;
	162
	163	/* disable dma mode */
	164	reg_val &= ~(SPI_CMD_TX_DMA \| SPI_CMD_RX_DMA);
	165
	166	/* disable deassert mode */
	167	reg_val &= ~SPI_CMD_DEASSERT;
	168
	169	writel(reg_val, mdata->base + SPI_CMD_REG);
	170
	171	/* pad select */
	172	if (mdata->dev_comp->need_pad_sel)
	173	writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG);
	174	}
	175
	176	static int mtk_spi_prepare_hardware(struct spi_master *master)
	177	{
	178	struct spi_transfer *trans;
	179	struct mtk_spi *mdata = spi_master_get_devdata(master);
	180	struct spi_message *msg = master->cur_msg;
	181
	182	trans = list_first_entry(&msg->transfers, struct spi_transfer,
	183	transfer_list);
	184	if (!trans->cs_change) {
	185	mdata->state = MTK_SPI_IDLE;
	186	mtk_spi_reset(mdata);
	187	}
	188
	189	return 0;
	190	}
	191
	192	static int mtk_spi_prepare_message(struct spi_master *master,
	193	struct spi_message *msg)
	194	{
	195	u32 reg_val;
	196	u8 cpha, cpol;
	197	struct mtk_chip_config *chip_config;
	198	struct spi_device *spi = msg->spi;
	199	struct mtk_spi *mdata = spi_master_get_devdata(master);
	200
	201	cpha = spi->mode & SPI_CPHA ? 1 : 0;
	202	cpol = spi->mode & SPI_CPOL ? 1 : 0;
	203
	204	reg_val = readl(mdata->base + SPI_CMD_REG);
	205	if (cpha)
	206	reg_val \|= SPI_CMD_CPHA;
	207	else
	208	reg_val &= ~SPI_CMD_CPHA;
	209	if (cpol)
	210	reg_val \|= SPI_CMD_CPOL;
	211	else
	212	reg_val &= ~SPI_CMD_CPOL;
	213	writel(reg_val, mdata->base + SPI_CMD_REG);
	214
	215	chip_config = spi->controller_data;
	216	if (!chip_config) {
	217	chip_config = (void *)&mtk_default_chip_info;
	218	spi->controller_data = chip_config;
	219	}
	220	mtk_spi_config(mdata, chip_config);
	221
	222	return 0;
	223	}
	224
	225	static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
	226	{
	227	u32 reg_val;
	228	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
	229
	230	reg_val = readl(mdata->base + SPI_CMD_REG);
	231	if (!enable)
	232	reg_val \|= SPI_CMD_PAUSE_EN;
	233	else
	234	reg_val &= ~SPI_CMD_PAUSE_EN;
	235	writel(reg_val, mdata->base + SPI_CMD_REG);
	236	}
	237
	238	static void mtk_spi_prepare_transfer(struct spi_master *master,
	239	struct spi_transfer *xfer)
	240	{
	241	u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
	242	struct mtk_spi *mdata = spi_master_get_devdata(master);
	243
	244	spi_clk_hz = clk_get_rate(mdata->spi_clk);
	245	if (xfer->speed_hz < spi_clk_hz / 2)
	246	div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
	247	else
	248	div = 1;
	249
	250	sck_time = (div + 1) / 2;
	251	cs_time = sck_time * 2;
	252
	253	reg_val \|= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET);
	254	reg_val \|= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
	255	reg_val \|= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
	256	reg_val \|= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
	257	writel(reg_val, mdata->base + SPI_CFG0_REG);
	258
	259	reg_val = readl(mdata->base + SPI_CFG1_REG);
	260	reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
	261	reg_val \|= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
	262	writel(reg_val, mdata->base + SPI_CFG1_REG);
	263	}
	264
	265	static void mtk_spi_setup_packet(struct spi_master *master)
	266	{
	267	u32 packet_size, packet_loop, reg_val;
	268	struct mtk_spi *mdata = spi_master_get_devdata(master);
	269
	270	packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
	271	packet_loop = mdata->xfer_len / packet_size;
	272
	273	reg_val = readl(mdata->base + SPI_CFG1_REG);
	274	reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK \| SPI_CFG1_PACKET_LOOP_MASK);
	275	reg_val \|= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
	276	reg_val \|= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
	277	writel(reg_val, mdata->base + SPI_CFG1_REG);
	278	}
	279
	280	static void mtk_spi_enable_transfer(struct spi_master *master)
	281	{
	282	u32 cmd;
	283	struct mtk_spi *mdata = spi_master_get_devdata(master);
	284
	285	cmd = readl(mdata->base + SPI_CMD_REG);
	286	if (mdata->state == MTK_SPI_IDLE)
	287	cmd \|= SPI_CMD_ACT;
	288	else
	289	cmd \|= SPI_CMD_RESUME;
	290	writel(cmd, mdata->base + SPI_CMD_REG);
	291	}
	292
	293	static int mtk_spi_get_mult_delta(u32 xfer_len)
	294	{
	295	u32 mult_delta;
	296
	297	if (xfer_len > MTK_SPI_PACKET_SIZE)
	298	mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
	299	else
	300	mult_delta = 0;
	301
	302	return mult_delta;
	303	}
	304
	305	static void mtk_spi_update_mdata_len(struct spi_master *master)
	306	{
	307	int mult_delta;
	308	struct mtk_spi *mdata = spi_master_get_devdata(master);
	309
	310	if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
	311	if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
	312	mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
	313	mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
	314	mdata->rx_sgl_len = mult_delta;
	315	mdata->tx_sgl_len -= mdata->xfer_len;
	316	} else {
	317	mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
	318	mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
	319	mdata->tx_sgl_len = mult_delta;
	320	mdata->rx_sgl_len -= mdata->xfer_len;
	321	}
	322	} else if (mdata->tx_sgl_len) {
	323	mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
	324	mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
	325	mdata->tx_sgl_len = mult_delta;
	326	} else if (mdata->rx_sgl_len) {
	327	mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
	328	mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
	329	mdata->rx_sgl_len = mult_delta;
	330	}
	331	}
	332
	333	static void mtk_spi_setup_dma_addr(struct spi_master *master,
	334	struct spi_transfer *xfer)
	335	{
	336	struct mtk_spi *mdata = spi_master_get_devdata(master);
	337
	338	if (mdata->tx_sgl)
	339	writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
	340	if (mdata->rx_sgl)
	341	writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
	342	}
	343
	344	static int mtk_spi_fifo_transfer(struct spi_master *master,
	345	struct spi_device *spi,
	346	struct spi_transfer *xfer)
	347	{
	348	int cnt;
	349	struct mtk_spi *mdata = spi_master_get_devdata(master);
	350
	351	mdata->cur_transfer = xfer;
	352	mdata->xfer_len = xfer->len;
	353	mtk_spi_prepare_transfer(master, xfer);
	354	mtk_spi_setup_packet(master);
	355
	356	if (xfer->len % 4)
	357	cnt = xfer->len / 4 + 1;
	358	else
	359	cnt = xfer->len / 4;
	360	iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
	361
	362	mtk_spi_enable_transfer(master);
	363
	364	return 1;
	365	}
	366
	367	static int mtk_spi_dma_transfer(struct spi_master *master,
	368	struct spi_device *spi,
	369	struct spi_transfer *xfer)
	370	{
	371	int cmd;
	372	struct mtk_spi *mdata = spi_master_get_devdata(master);
	373
	374	mdata->tx_sgl = NULL;
	375	mdata->rx_sgl = NULL;
	376	mdata->tx_sgl_len = 0;
	377	mdata->rx_sgl_len = 0;
	378	mdata->cur_transfer = xfer;
	379
	380	mtk_spi_prepare_transfer(master, xfer);
	381
	382	cmd = readl(mdata->base + SPI_CMD_REG);
	383	if (xfer->tx_buf)
	384	cmd \|= SPI_CMD_TX_DMA;
	385	if (xfer->rx_buf)
	386	cmd \|= SPI_CMD_RX_DMA;
	387	writel(cmd, mdata->base + SPI_CMD_REG);
	388
	389	if (xfer->tx_buf)
	390	mdata->tx_sgl = xfer->tx_sg.sgl;
	391	if (xfer->rx_buf)
	392	mdata->rx_sgl = xfer->rx_sg.sgl;
	393
	394	if (mdata->tx_sgl) {
	395	xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
	396	mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
	397	}
	398	if (mdata->rx_sgl) {
	399	xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
	400	mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
	401	}
	402
	403	mtk_spi_update_mdata_len(master);
	404	mtk_spi_setup_packet(master);
	405	mtk_spi_setup_dma_addr(master, xfer);
	406	mtk_spi_enable_transfer(master);
	407
	408	return 1;
	409	}
	410
	411	static int mtk_spi_transfer_one(struct spi_master *master,
	412	struct spi_device *spi,
	413	struct spi_transfer *xfer)
	414	{
	415	if (master->can_dma(master, spi, xfer))
	416	return mtk_spi_dma_transfer(master, spi, xfer);
	417	else
	418	return mtk_spi_fifo_transfer(master, spi, xfer);
	419	}
	420
	421	static bool mtk_spi_can_dma(struct spi_master *master,
	422	struct spi_device *spi,
	423	struct spi_transfer *xfer)
	424	{
	425	return xfer->len > MTK_SPI_MAX_FIFO_SIZE;
	426	}
	427
	428	static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
	429	{
	430	u32 cmd, reg_val, cnt;
	431	struct spi_master *master = dev_id;
	432	struct mtk_spi *mdata = spi_master_get_devdata(master);
	433	struct spi_transfer *trans = mdata->cur_transfer;
	434
	435	reg_val = readl(mdata->base + SPI_STATUS0_REG);
	436	if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
	437	mdata->state = MTK_SPI_PAUSED;
	438	else
	439	mdata->state = MTK_SPI_IDLE;
	440
	441	if (!master->can_dma(master, master->cur_msg->spi, trans)) {
	442	if (trans->rx_buf) {
	443	if (mdata->xfer_len % 4)
	444	cnt = mdata->xfer_len / 4 + 1;
	445	else
	446	cnt = mdata->xfer_len / 4;
	447	ioread32_rep(mdata->base + SPI_RX_DATA_REG,
	448	trans->rx_buf, cnt);
	449	}
	450	spi_finalize_current_transfer(master);
	451	return IRQ_HANDLED;
	452	}
	453
	454	if (mdata->tx_sgl)
	455	trans->tx_dma += mdata->xfer_len;
	456	if (mdata->rx_sgl)
	457	trans->rx_dma += mdata->xfer_len;
	458
	459	if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
	460	mdata->tx_sgl = sg_next(mdata->tx_sgl);
	461	if (mdata->tx_sgl) {
	462	trans->tx_dma = sg_dma_address(mdata->tx_sgl);
	463	mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
	464	}
	465	}
	466	if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
	467	mdata->rx_sgl = sg_next(mdata->rx_sgl);
	468	if (mdata->rx_sgl) {
	469	trans->rx_dma = sg_dma_address(mdata->rx_sgl);
	470	mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
	471	}
	472	}
	473
	474	if (!mdata->tx_sgl && !mdata->rx_sgl) {
	475	/* spi disable dma */
	476	cmd = readl(mdata->base + SPI_CMD_REG);
	477	cmd &= ~SPI_CMD_TX_DMA;
	478	cmd &= ~SPI_CMD_RX_DMA;
	479	writel(cmd, mdata->base + SPI_CMD_REG);
	480
	481	spi_finalize_current_transfer(master);
	482	return IRQ_HANDLED;
	483	}
	484
	485	mtk_spi_update_mdata_len(master);
	486	mtk_spi_setup_packet(master);
	487	mtk_spi_setup_dma_addr(master, trans);
	488	mtk_spi_enable_transfer(master);
	489
	490	return IRQ_HANDLED;
	491	}
	492
	493	static int mtk_spi_probe(struct platform_device *pdev)
	494	{
	495	struct spi_master *master;
	496	struct mtk_spi *mdata;
	497	const struct of_device_id *of_id;
	498	struct resource *res;
	499	int irq, ret;
	500
	501	master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
	502	if (!master) {
	503	dev_err(&pdev->dev, "failed to alloc spi master\n");
	504	return -ENOMEM;
	505	}
	506
	507	master->auto_runtime_pm = true;
	508	master->dev.of_node = pdev->dev.of_node;
	509	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	510
	511	master->set_cs = mtk_spi_set_cs;
	512	master->prepare_transfer_hardware = mtk_spi_prepare_hardware;
	513	master->prepare_message = mtk_spi_prepare_message;
	514	master->transfer_one = mtk_spi_transfer_one;
	515	master->can_dma = mtk_spi_can_dma;
	516
	517	of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
	518	if (!of_id) {
	519	dev_err(&pdev->dev, "failed to probe of_node\n");
	520	ret = -EINVAL;
	521	goto err_put_master;
	522	}
	523
	524	mdata = spi_master_get_devdata(master);
	525	mdata->dev_comp = of_id->data;
	526	if (mdata->dev_comp->must_tx)
	527	master->flags = SPI_MASTER_MUST_TX;
	528
	529	if (mdata->dev_comp->need_pad_sel) {
	530	ret = of_property_read_u32(pdev->dev.of_node,
	531	"mediatek,pad-select",
	532	&mdata->pad_sel);
	533	if (ret) {
	534	dev_err(&pdev->dev, "failed to read pad select: %d\n",
	535	ret);
	536	goto err_put_master;
	537	}
	538
	539	if (mdata->pad_sel > MT8173_SPI_MAX_PAD_SEL) {
	540	dev_err(&pdev->dev, "wrong pad-select: %u\n",
	541	mdata->pad_sel);
	542	ret = -EINVAL;
	543	goto err_put_master;
	544	}
	545	}
	546
	547	platform_set_drvdata(pdev, master);
	548
	549	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	550	if (!res) {
	551	ret = -ENODEV;
	552	dev_err(&pdev->dev, "failed to determine base address\n");
	553	goto err_put_master;
	554	}
	555
	556	mdata->base = devm_ioremap_resource(&pdev->dev, res);
	557	if (IS_ERR(mdata->base)) {
	558	ret = PTR_ERR(mdata->base);
	559	goto err_put_master;
	560	}
	561
	562	irq = platform_get_irq(pdev, 0);
	563	if (irq < 0) {
	564	dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
	565	ret = irq;
	566	goto err_put_master;
	567	}
	568
	569	if (!pdev->dev.dma_mask)
	570	pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
	571
	572	ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
	573	IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
	574	if (ret) {
	575	dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
	576	goto err_put_master;
	577	}
	578
	579	mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
	580	if (IS_ERR(mdata->spi_clk)) {
	581	ret = PTR_ERR(mdata->spi_clk);
	582	dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
	583	goto err_put_master;
	584	}
	585
	586	mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
	587	if (IS_ERR(mdata->parent_clk)) {
	588	ret = PTR_ERR(mdata->parent_clk);
	589	dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
	590	goto err_put_master;
	591	}
	592
	593	ret = clk_prepare_enable(mdata->spi_clk);
	594	if (ret < 0) {
	595	dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
	596	goto err_put_master;
	597	}
	598
	599	ret = clk_set_parent(mdata->spi_clk, mdata->parent_clk);
	600	if (ret < 0) {
	601	dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
	602	goto err_disable_clk;
	603	}
	604
	605	clk_disable_unprepare(mdata->spi_clk);
	606
	607	pm_runtime_enable(&pdev->dev);
	608
	609	ret = devm_spi_register_master(&pdev->dev, master);
	610	if (ret) {
	611	dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
	612	goto err_put_master;
	613	}
	614
	615	return 0;
	616
	617	err_disable_clk:
	618	clk_disable_unprepare(mdata->spi_clk);
	619	err_put_master:
	620	spi_master_put(master);
	621
	622	return ret;
	623	}
	624
	625	static int mtk_spi_remove(struct platform_device *pdev)
	626	{
	627	struct spi_master *master = platform_get_drvdata(pdev);
	628	struct mtk_spi *mdata = spi_master_get_devdata(master);
	629
	630	pm_runtime_disable(&pdev->dev);
	631
	632	mtk_spi_reset(mdata);
	633	clk_disable_unprepare(mdata->spi_clk);
	634	spi_master_put(master);
	635
	636	return 0;
	637	}
	638
	639	#ifdef CONFIG_PM_SLEEP
	640	static int mtk_spi_suspend(struct device *dev)
	641	{
	642	int ret;
	643	struct spi_master *master = dev_get_drvdata(dev);
	644	struct mtk_spi *mdata = spi_master_get_devdata(master);
	645
	646	ret = spi_master_suspend(master);
	647	if (ret)
	648	return ret;
	649
	650	if (!pm_runtime_suspended(dev))
	651	clk_disable_unprepare(mdata->spi_clk);
	652
	653	return ret;
	654	}
	655
	656	static int mtk_spi_resume(struct device *dev)
	657	{
	658	int ret;
	659	struct spi_master *master = dev_get_drvdata(dev);
	660	struct mtk_spi *mdata = spi_master_get_devdata(master);
	661
	662	if (!pm_runtime_suspended(dev)) {
	663	ret = clk_prepare_enable(mdata->spi_clk);
	664	if (ret < 0) {
	665	dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
	666	return ret;
	667	}
	668	}
	669
	670	ret = spi_master_resume(master);
	671	if (ret < 0)
	672	clk_disable_unprepare(mdata->spi_clk);
	673
	674	return ret;
	675	}
	676	#endif /* CONFIG_PM_SLEEP */
	677
	678	#ifdef CONFIG_PM
	679	static int mtk_spi_runtime_suspend(struct device *dev)
	680	{
	681	struct spi_master *master = dev_get_drvdata(dev);
	682	struct mtk_spi *mdata = spi_master_get_devdata(master);
	683
	684	clk_disable_unprepare(mdata->spi_clk);
	685
	686	return 0;
	687	}
	688
	689	static int mtk_spi_runtime_resume(struct device *dev)
	690	{
	691	struct spi_master *master = dev_get_drvdata(dev);
	692	struct mtk_spi *mdata = spi_master_get_devdata(master);
	693	int ret;
	694
	695	ret = clk_prepare_enable(mdata->spi_clk);
	696	if (ret < 0) {
	697	dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
	698	return ret;
	699	}
	700
	701	return 0;
	702	}
	703	#endif /* CONFIG_PM */
	704
	705	static const struct dev_pm_ops mtk_spi_pm = {
	706	SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
	707	SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
	708	mtk_spi_runtime_resume, NULL)
	709	};
	710
	711	static struct platform_driver mtk_spi_driver = {
	712	.driver = {
	713	.name = "mtk-spi",
	714	.pm = &mtk_spi_pm,
	715	.of_match_table = mtk_spi_of_match,
	716	},
	717	.probe = mtk_spi_probe,
	718	.remove = mtk_spi_remove,
	719	};
	720
	721	module_platform_driver(mtk_spi_driver);
	722
	723	MODULE_DESCRIPTION("MTK SPI Controller driver");
	724	MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
	725	MODULE_LICENSE("GPL v2");
	726	MODULE_ALIAS("platform:mtk-spi");

drivers/spi/spi-omap2-mcspi.c+10−0

 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
 {
+	struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 	u32 l;
 	/* The controller handles the inverted chip selects
 		enable = !enable;
 	if (spi->controller_state) {
+		int err = pm_runtime_get_sync(mcspi->dev);
+		if (err < 0) {
+			dev_err(mcspi->dev, "failed to get sync: %d\n", err);
+			return;
+		}
 		l = mcspi_cached_chconf0(spi);
 		if (enable)
 			l |= OMAP2_MCSPI_CHCONF_FORCE;
 		mcspi_write_chconf0(spi, l);
+		pm_runtime_mark_last_busy(mcspi->dev);
+		pm_runtime_put_autosuspend(mcspi->dev);
 	}
 }

drivers/spi/spi-orion.c+53−1

@@ -41,6 +41,11 @@ · 40 unmodified lines
41	#define ORION_SPI_DATA_OUT_REG 0x08	41	#define ORION_SPI_DATA_OUT_REG 0x08
42	#define ORION_SPI_DATA_IN_REG 0x0c	42	#define ORION_SPI_DATA_IN_REG 0x0c
43	#define ORION_SPI_INT_CAUSE_REG 0x10	43	#define ORION_SPI_INT_CAUSE_REG 0x10
		44	#define ORION_SPI_TIMING_PARAMS_REG 0x18
		45
		46	#define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6)
		47	#define ORION_SPI_TMISO_SAMPLE_1 (1 << 6)
		48	#define ORION_SPI_TMISO_SAMPLE_2 (2 << 6)
44		49
45	#define ORION_SPI_MODE_CPOL (1 << 11)	50	#define ORION_SPI_MODE_CPOL (1 << 11)
46	#define ORION_SPI_MODE_CPHA (1 << 12)	51	#define ORION_SPI_MODE_CPHA (1 << 12)
@@ -70,6 +75,7 @@ struct orion_spi_dev { · 23 unmodified lines
70	unsigned int min_divisor;	75	unsigned int min_divisor;
71	unsigned int max_divisor;	76	unsigned int max_divisor;
72	u32 prescale_mask;	77	u32 prescale_mask;
		78	bool is_errata_50mhz_ac;
73	};	79	};
74		80
75	struct orion_spi {	81	struct orion_spi {
@@ -195,6 +201,41 @@ orion_spi_mode_set(struct spi_device *spi) · 119 unmodified lines
195	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));	201	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
196	}	202	}
197		203
		204	static void
		205	orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
		206	{
		207	u32 reg;
		208	struct orion_spi *orion_spi;
		209
		210	orion_spi = spi_master_get_devdata(spi->master);
		211
		212	/*
		213	* Erratum description: (Erratum NO. FE-9144572) The device
		214	* SPI interface supports frequencies of up to 50 MHz.
		215	* However, due to this erratum, when the device core clock is
		216	* 250 MHz and the SPI interfaces is configured for 50MHz SPI
		217	* clock and CPOL=CPHA=1 there might occur data corruption on
		218	* reads from the SPI device.
		219	* Erratum Workaround:
		220	* Work in one of the following configurations:
		221	* 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
		222	* Register".
		223	* 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
		224	* Register" before setting the interface.
		225	*/
		226	reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
		227	reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
		228
		229	if (clk_get_rate(orion_spi->clk) == 250000000 &&
		230	speed == 50000000 && spi->mode & SPI_CPOL &&
		231	spi->mode & SPI_CPHA)
		232	reg \|= ORION_SPI_TMISO_SAMPLE_2;
		233	else
		234	reg \|= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
		235
		236	writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
		237	}
		238
198	/*	239	/*
199	* called only when no transfer is active on the bus	240	* called only when no transfer is active on the bus
200	*/	241	*/
@@ -216,6 +257,9 @@ orion_spi_setup_transfer(struct spi_device spi, struct spi_transfer t) · 15 unmodified lines
216		257
217	orion_spi_mode_set(spi);	258	orion_spi_mode_set(spi);
218		259
		260	if (orion_spi->devdata->is_errata_50mhz_ac)
		261	orion_spi_50mhz_ac_timing_erratum(spi, speed);
		262
219	rc = orion_spi_baudrate_set(spi, speed);	263	rc = orion_spi_baudrate_set(spi, speed);
220	if (rc)	264	if (rc)
221	return rc;	265	return rc;
@@ -413,6 +457,14 @@ static const struct orion_spi_dev armada_375_spi_dev_data = { · 191 unmodified lines
413	.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,	457	.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
414	};	458	};
415		459
		460	static const struct orion_spi_dev armada_380_spi_dev_data = {
		461	.typ = ARMADA_SPI,
		462	.max_hz = 50000000,
		463	.max_divisor = 1920,
		464	.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
		465	.is_errata_50mhz_ac = true,
		466	};
		467
416	static const struct of_device_id orion_spi_of_match_table[] = {	468	static const struct of_device_id orion_spi_of_match_table[] = {
417	{	469	{
418	.compatible = "marvell,orion-spi",	470	.compatible = "marvell,orion-spi",
@@ -428,7 +480,7 @@ static const struct of_device_id orion_spi_of_match_table[] = { · 9 unmodified lines
428	},	480	},
429	{	481	{
430	.compatible = "marvell,armada-380-spi",	482	.compatible = "marvell,armada-380-spi",
431	.data = &armada_xp_spi_dev_data,	483	.data = &armada_380_spi_dev_data,
432	},	484	},
433	{	485	{
434	.compatible = "marvell,armada-390-spi",	486	.compatible = "marvell,armada-390-spi",

drivers/spi/spi-pxa2xx-pci.c+0−1

@@ -7,7 +7,6 @@ · 6 unmodified lines
7	#include <linux/of_device.h>	7	#include <linux/of_device.h>
8	#include <linux/module.h>	8	#include <linux/module.h>
9	#include <linux/spi/pxa2xx_spi.h>	9	#include <linux/spi/pxa2xx_spi.h>
10	#include <linux/clk.h>
11	#include <linux/clk-provider.h>	10	#include <linux/clk-provider.h>
12		11
13	#include <linux/dmaengine.h>	12	#include <linux/dmaengine.h>

drivers/spi/spi-pxa2xx.c+57−9

 #include <linux/err.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
+#include <linux/pci.h>
 #include <linux/platform_device.h>
 #include <linux/spi/pxa2xx_spi.h>
 #include <linux/spi/spi.h>
 		.tx_threshold_lo = 160,
 		.tx_threshold_hi = 224,
 	},
+	{	/* LPSS_SPT_SSP */
+		.offset = 0x200,
+		.reg_general = -1,
+		.reg_ssp = 0x20,
+		.reg_cs_ctrl = 0x24,
+		.rx_threshold = 1,
+		.tx_threshold_lo = 32,
+		.tx_threshold_hi = 56,
+	},
 };
 static inline const struct lpss_config
 	switch (drv_data->ssp_type) {
 	case LPSS_LPT_SSP:
 	case LPSS_BYT_SSP:
+	case LPSS_SPT_SSP:
 		return true;
 	default:
 		return false;
 		break;
 	case LPSS_LPT_SSP:
 	case LPSS_BYT_SSP:
+	case LPSS_SPT_SSP:
 		config = lpss_get_config(drv_data);
 		tx_thres = config->tx_threshold_lo;
 		tx_hi_thres = config->tx_threshold_hi;
 };
 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
+/*
+ * PCI IDs of compound devices that integrate both host controller and private
+ * integrated DMA engine. Please note these are not used in module
+ * autoloading and probing in this module but matching the LPSS SSP type.
+ */
+static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
+	/* SPT-LP */
+	{ PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
+	{ PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
+	/* SPT-H */
+	{ PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
+	{ PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
+	{ },
+};
+static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
+{
+	struct device *dev = param;
+	if (dev != chan->device->dev->parent)
+		return false;
+	return true;
+}
 static struct pxa2xx_spi_master *
 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
 {
 	struct acpi_device *adev;
 	struct ssp_device *ssp;
 	struct resource *res;
-	const struct acpi_device_id *id;
+	const struct acpi_device_id *adev_id = NULL;
+	const struct pci_device_id *pcidev_id = NULL;
 	int devid, type;
 	if (!ACPI_HANDLE(&pdev->dev) ||
 	    acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
 		return NULL;
-	id = acpi_match_device(pdev->dev.driver->acpi_match_table, &pdev->dev);
+	if (dev_is_pci(pdev->dev.parent))
-	if (id)
+		pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
-		type = (int)id->driver_data;
+					 to_pci_dev(pdev->dev.parent));
+	else
+		adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
+					    &pdev->dev);
+	if (adev_id)
+		type = (int)adev_id->driver_data;
+	else if (pcidev_id)
+		type = (int)pcidev_id->driver_data;
 	else
 		return NULL;
 	if (IS_ERR(ssp->mmio_base))
 		return NULL;
+	if (pcidev_id) {
+		pdata->tx_param = pdev->dev.parent;
+		pdata->rx_param = pdev->dev.parent;
+		pdata->dma_filter = pxa2xx_spi_idma_filter;
+	}
 	ssp->clk = devm_clk_get(&pdev->dev, NULL);
 	ssp->irq = platform_get_irq(pdev, 0);
 	ssp->type = type;
 		return -ENODEV;
 	}
-	/* Allocate master with space for drv_data and null dma buffer */
+	master = spi_alloc_master(dev, sizeof(struct driver_data));
-	master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
 	if (!master) {
 		dev_err(&pdev->dev, "cannot alloc spi_master\n");
 		pxa_ssp_free(ssp);
 	master->auto_runtime_pm = true;
 	drv_data->ssp_type = ssp->type;
-	drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
 	drv_data->ioaddr = ssp->mmio_base;
 	drv_data->ssdr_physical = ssp->phys_base + SSDR;
 	}
 	/* Setup DMA if requested */
-	drv_data->tx_channel = -1;
-	drv_data->rx_channel = -1;
 	if (platform_info->enable_dma) {
 		status = pxa2xx_spi_dma_setup(drv_data);
 		if (status) {

drivers/spi/spi-pxa2xx.h+0−5

 	/* PXA hookup */
 	struct pxa2xx_spi_master *master_info;
-	/* PXA private DMA setup stuff */
-	int rx_channel;
-	int tx_channel;
-	u32 *null_dma_buf;
 	/* SSP register addresses */
 	void __iomem *ioaddr;
 	u32 ssdr_physical;

drivers/spi/spi-rockchip.c+0−1

@@ -645,7 +645,6 @@ static int rockchip_spi_probe(struct platform_device *pdev) · 644 unmodified lines
645	platform_set_drvdata(pdev, master);	645	platform_set_drvdata(pdev, master);
646		646
647	rs = spi_master_get_devdata(master);	647	rs = spi_master_get_devdata(master);
648	memset(rs, 0, sizeof(struct rockchip_spi));
649		648
650	/* Get basic io resource and map it */	649	/* Get basic io resource and map it */
651	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);	650	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);

drivers/spi/spi-rspi.c+10−9

 	rspi_write8(rspi, data, reg);
 }
-static int qspi_set_send_trigger(struct rspi_data *rspi, unsigned int len)
+static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
+					  unsigned int len)
 {
 	unsigned int n;
 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
 					u8 *rx, unsigned int len)
 {
-	int i, n, ret;
+	unsigned int i, n;
-	int error;
+	int ret;
 	while (len > 0) {
 		n = qspi_set_send_trigger(rspi, len);
 		qspi_set_receive_trigger(rspi, len);
 		if (n == QSPI_BUFFER_SIZE) {
-			error = rspi_wait_for_tx_empty(rspi);
+			ret = rspi_wait_for_tx_empty(rspi);
-			if (error < 0) {
+			if (ret < 0) {
 				dev_err(&rspi->master->dev, "transmit timeout\n");
-				return error;
+				return ret;
 			}
 			for (i = 0; i < n; i++)
 				rspi_write_data(rspi, *tx++);
-			error = rspi_wait_for_rx_full(rspi);
+			ret = rspi_wait_for_rx_full(rspi);
-			if (error < 0) {
+			if (ret < 0) {
 				dev_err(&rspi->master->dev, "receive timeout\n");
-				return error;
+				return ret;
 			}
 			for (i = 0; i < n; i++)
 				*rx++ = rspi_read_data(rspi);

drivers/spi/spi-s3c24xx.c+0−1

@@ -501,7 +501,6 @@ static int s3c24xx_spi_probe(struct platform_device *pdev) · 500 unmodified lines
501	}	501	}
502		502
503	hw = spi_master_get_devdata(master);	503	hw = spi_master_get_devdata(master);
504	memset(hw, 0, sizeof(struct s3c24xx_spi));
505		504
506	hw->master = master;	505	hw->master = master;
507	hw->pdata = pdata = dev_get_platdata(&pdev->dev);	506	hw->pdata = pdata = dev_get_platdata(&pdev->dev);

drivers/spi/spi-s3c64xx.c+2−2

@@ -1191,8 +1191,8 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) · 1190 unmodified lines
1191		1191
1192	dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",	1192	dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1193	sdd->port_id, master->num_chipselect);	1193	sdd->port_id, master->num_chipselect);
1194	dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tDMA=[Rx-%d, Tx-%d]\n",	1194	dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\tDMA=[Rx-%d, Tx-%d]\n",
1195	mem_res,	1195	mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1,
1196	sdd->rx_dma.dmach, sdd->tx_dma.dmach);	1196	sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1197		1197
1198	return 0;	1198	return 0;

drivers/spi/spi-sh-msiof.c+9−11

 	const struct sh_msiof_chipdata *chipdata;
 	struct sh_msiof_spi_info *info;
 	struct completion done;
-	int tx_fifo_size;
+	unsigned int tx_fifo_size;
-	int rx_fifo_size;
+	unsigned int rx_fifo_size;
 	void *tx_dma_page;
 	void *rx_dma_page;
 	dma_addr_t tx_dma_addr;
 #define MDR2_WDLEN1(i)	(((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
 #define MDR2_GRPMASK1	0x00000001 /* Group Output Mask 1 (SH, A1) */
-#define MAX_WDLEN	256U
 /* TSCR and RSCR */
 #define SCR_BRPS_MASK	    0x1f00 /* Prescaler Setting (1-32) */
 #define SCR_BRPS(i)	(((i) - 1) << 8)
 		 *  DMA supports 32-bit words only, hence pack 8-bit and 16-bit
 		 *  words, with byte resp. word swapping.
 		 */
-		unsigned int l = min(len, MAX_WDLEN * 4);
+		unsigned int l = 0;
+		if (tx_buf)
+			l = min(len, p->tx_fifo_size * 4);
+		if (rx_buf)
+			l = min(len, p->rx_fifo_size * 4);
 		if (bits <= 8) {
 			if (l & 3)
 static const struct sh_msiof_chipdata r8a779x_data = {
 	.tx_fifo_size = 64,
-	.rx_fifo_size = 256,
+	.rx_fifo_size = 64,
 	.master_flags = SPI_MASTER_MUST_TX,
 };
 static const struct platform_device_id spi_driver_ids[] = {
 	{ "spi_sh_msiof",	(kernel_ulong_t)&sh_data },
-	{ "spi_r8a7790_msiof",	(kernel_ulong_t)&r8a779x_data },
-	{ "spi_r8a7791_msiof",	(kernel_ulong_t)&r8a779x_data },
-	{ "spi_r8a7792_msiof",	(kernel_ulong_t)&r8a779x_data },
-	{ "spi_r8a7793_msiof",	(kernel_ulong_t)&r8a779x_data },
-	{ "spi_r8a7794_msiof",	(kernel_ulong_t)&r8a779x_data },
 	{},
 };
 MODULE_DEVICE_TABLE(platform, spi_driver_ids);

drivers/spi/spi-ti-qspi.c+30−4

 #define QSPI_INVAL			(4 << 16)
 #define QSPI_WC_CMD_INT_EN			(1 << 14)
 #define QSPI_FLEN(n)			((n - 1) << 0)
+#define QSPI_WLEN_MAX_BITS		128
+#define QSPI_WLEN_MAX_BYTES		16
 /* STATUS REGISTER */
 #define BUSY				0x01
 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
 {
-	int wlen, count;
+	int wlen, count, xfer_len;
 	unsigned int cmd;
 	const u8 *txbuf;
+	u32 data;
 	txbuf = t->tx_buf;
 	cmd = qspi->cmd | QSPI_WR_SNGL;
 	count = t->len;
 	wlen = t->bits_per_word >> 3;	/* in bytes */
+	xfer_len = wlen;
 	while (count) {
 		if (qspi_is_busy(qspi))
 		case 1:
 			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
 					cmd, qspi->dc, *txbuf);
-			writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
+			if (count >= QSPI_WLEN_MAX_BYTES) {
+				u32 *txp = (u32 *)txbuf;
+				data = cpu_to_be32(*txp++);
+				writel(data, qspi->base +
+				       QSPI_SPI_DATA_REG_3);
+				data = cpu_to_be32(*txp++);
+				writel(data, qspi->base +
+				       QSPI_SPI_DATA_REG_2);
+				data = cpu_to_be32(*txp++);
+				writel(data, qspi->base +
+				       QSPI_SPI_DATA_REG_1);
+				data = cpu_to_be32(*txp++);
+				writel(data, qspi->base +
+				       QSPI_SPI_DATA_REG);
+				xfer_len = QSPI_WLEN_MAX_BYTES;
+				cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
+			} else {
+				writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
+				cmd = qspi->cmd | QSPI_WR_SNGL;
+				xfer_len = wlen;
+				cmd |= QSPI_WLEN(wlen);
+			}
 			break;
 		case 2:
 			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
 			dev_err(qspi->dev, "write timed out\n");
 			return -ETIMEDOUT;
 		}
-		txbuf += wlen;
+		txbuf += xfer_len;
-		count -= wlen;
+		count -= xfer_len;
 	}
 	return 0;

drivers/spi/spi-xcomm.c+1−1

 	{ "spi-xcomm" },
 	{ },
 };
+MODULE_DEVICE_TABLE(i2c, spi_xcomm_ids);
 static struct i2c_driver spi_xcomm_driver = {
 	.driver = {
 		.name	= "spi-xcomm",
-		.owner	= THIS_MODULE,
 	},
 	.id_table	= spi_xcomm_ids,
 	.probe		= spi_xcomm_probe,

drivers/spi/spi-xilinx.c+13−7

 	xspi->tx_ptr = t->tx_buf;
 	xspi->rx_ptr = t->rx_buf;
 	remaining_words = t->len / xspi->bytes_per_word;
-	reinit_completion(&xspi->done);
 	if (xspi->irq >= 0 &&  remaining_words > xspi->buffer_size) {
+		u32 isr;
 		use_irq = true;
-		xspi->write_fn(XSPI_INTR_TX_EMPTY,
-				xspi->regs + XIPIF_V123B_IISR_OFFSET);
-		/* Enable the global IPIF interrupt */
-		xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
-				xspi->regs + XIPIF_V123B_DGIER_OFFSET);
 		/* Inhibit irq to avoid spurious irqs on tx_empty*/
 		cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
 		xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
 			       xspi->regs + XSPI_CR_OFFSET);
+		/* ACK old irqs (if any) */
+		isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
+		if (isr)
+			xspi->write_fn(isr,
+				       xspi->regs + XIPIF_V123B_IISR_OFFSET);
+		/* Enable the global IPIF interrupt */
+		xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
+				xspi->regs + XIPIF_V123B_DGIER_OFFSET);
+		reinit_completion(&xspi->done);
 	}
 	while (remaining_words) {
 		remaining_words -= n_words;
 	}
-	if (use_irq)
+	if (use_irq) {
 		xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
+		xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
+	}
 	return t->len;
 }

drivers/spi/spi-xlp.c+456−0

@@ -0,0 +1,456 @@
	1	/*
	2	* Copyright (C) 2003-2015 Broadcom Corporation
	3	* All Rights Reserved
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 (GPL v2)
	7	* as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14	#include <linux/clk.h>
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/spi/spi.h>
	19	#include <linux/of.h>
	20	#include <linux/interrupt.h>
	21
	22	/* SPI Configuration Register */
	23	#define XLP_SPI_CONFIG 0x00
	24	#define XLP_SPI_CPHA BIT(0)
	25	#define XLP_SPI_CPOL BIT(1)
	26	#define XLP_SPI_CS_POL BIT(2)
	27	#define XLP_SPI_TXMISO_EN BIT(3)
	28	#define XLP_SPI_TXMOSI_EN BIT(4)
	29	#define XLP_SPI_RXMISO_EN BIT(5)
	30	#define XLP_SPI_CS_LSBFE BIT(10)
	31	#define XLP_SPI_RXCAP_EN BIT(11)
	32
	33	/* SPI Frequency Divider Register */
	34	#define XLP_SPI_FDIV 0x04
	35
	36	/* SPI Command Register */
	37	#define XLP_SPI_CMD 0x08
	38	#define XLP_SPI_CMD_IDLE_MASK 0x0
	39	#define XLP_SPI_CMD_TX_MASK 0x1
	40	#define XLP_SPI_CMD_RX_MASK 0x2
	41	#define XLP_SPI_CMD_TXRX_MASK 0x3
	42	#define XLP_SPI_CMD_CONT BIT(4)
	43	#define XLP_SPI_XFR_BITCNT_SHIFT 16
	44
	45	/* SPI Status Register */
	46	#define XLP_SPI_STATUS 0x0c
	47	#define XLP_SPI_XFR_PENDING BIT(0)
	48	#define XLP_SPI_XFR_DONE BIT(1)
	49	#define XLP_SPI_TX_INT BIT(2)
	50	#define XLP_SPI_RX_INT BIT(3)
	51	#define XLP_SPI_TX_UF BIT(4)
	52	#define XLP_SPI_RX_OF BIT(5)
	53	#define XLP_SPI_STAT_MASK 0x3f
	54
	55	/* SPI Interrupt Enable Register */
	56	#define XLP_SPI_INTR_EN 0x10
	57	#define XLP_SPI_INTR_DONE BIT(0)
	58	#define XLP_SPI_INTR_TXTH BIT(1)
	59	#define XLP_SPI_INTR_RXTH BIT(2)
	60	#define XLP_SPI_INTR_TXUF BIT(3)
	61	#define XLP_SPI_INTR_RXOF BIT(4)
	62
	63	/* SPI FIFO Threshold Register */
	64	#define XLP_SPI_FIFO_THRESH 0x14
	65
	66	/* SPI FIFO Word Count Register */
	67	#define XLP_SPI_FIFO_WCNT 0x18
	68	#define XLP_SPI_RXFIFO_WCNT_MASK 0xf
	69	#define XLP_SPI_TXFIFO_WCNT_MASK 0xf0
	70	#define XLP_SPI_TXFIFO_WCNT_SHIFT 4
	71
	72	/* SPI Transmit Data FIFO Register */
	73	#define XLP_SPI_TXDATA_FIFO 0x1c
	74
	75	/* SPI Receive Data FIFO Register */
	76	#define XLP_SPI_RXDATA_FIFO 0x20
	77
	78	/* SPI System Control Register */
	79	#define XLP_SPI_SYSCTRL 0x100
	80	#define XLP_SPI_SYS_RESET BIT(0)
	81	#define XLP_SPI_SYS_CLKDIS BIT(1)
	82	#define XLP_SPI_SYS_PMEN BIT(8)
	83
	84	#define SPI_CS_OFFSET 0x40
	85	#define XLP_SPI_TXRXTH 0x80
	86	#define XLP_SPI_FIFO_SIZE 8
	87	#define XLP_SPI_MAX_CS 4
	88	#define XLP_SPI_DEFAULT_FREQ 133333333
	89	#define XLP_SPI_FDIV_MIN 4
	90	#define XLP_SPI_FDIV_MAX 65535
	91	/*
	92	* SPI can transfer only 28 bytes properly at a time. So split the
	93	* transfer into 28 bytes size.
	94	*/
	95	#define XLP_SPI_XFER_SIZE 28
	96
	97	struct xlp_spi_priv {
	98	struct device dev; /* device structure */
	99	void __iomem base; / spi registers base address */
	100	const u8 tx_buf; / tx data buffer */
	101	u8 rx_buf; / rx data buffer */
	102	int tx_len; /* tx xfer length */
	103	int rx_len; /* rx xfer length */
	104	int txerrors; /* TXFIFO underflow count */
	105	int rxerrors; /* RXFIFO overflow count */
	106	int cs; /* slave device chip select */
	107	u32 spi_clk; /* spi clock frequency */
	108	bool cmd_cont; /* cs active */
	109	struct completion done; /* completion notification */
	110	};
	111
	112	static inline u32 xlp_spi_reg_read(struct xlp_spi_priv *priv,
	113	int cs, int regoff)
	114	{
	115	return readl(priv->base + regoff + cs * SPI_CS_OFFSET);
	116	}
	117
	118	static inline void xlp_spi_reg_write(struct xlp_spi_priv *priv, int cs,
	119	int regoff, u32 val)
	120	{
	121	writel(val, priv->base + regoff + cs * SPI_CS_OFFSET);
	122	}
	123
	124	static inline void xlp_spi_sysctl_write(struct xlp_spi_priv *priv,
	125	int regoff, u32 val)
	126	{
	127	writel(val, priv->base + regoff);
	128	}
	129
	130	/*
	131	* Setup global SPI_SYSCTRL register for all SPI channels.
	132	*/
	133	static void xlp_spi_sysctl_setup(struct xlp_spi_priv *xspi)
	134	{
	135	int cs;
	136
	137	for (cs = 0; cs < XLP_SPI_MAX_CS; cs++)
	138	xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL,
	139	XLP_SPI_SYS_RESET << cs);
	140	xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL, XLP_SPI_SYS_PMEN);
	141	}
	142
	143	static int xlp_spi_setup(struct spi_device *spi)
	144	{
	145	struct xlp_spi_priv *xspi;
	146	u32 fdiv, cfg;
	147	int cs;
	148
	149	xspi = spi_master_get_devdata(spi->master);
	150	cs = spi->chip_select;
	151	/*
	152	* The value of fdiv must be between 4 and 65535.
	153	*/
	154	fdiv = DIV_ROUND_UP(xspi->spi_clk, spi->max_speed_hz);
	155	if (fdiv > XLP_SPI_FDIV_MAX)
	156	fdiv = XLP_SPI_FDIV_MAX;
	157	else if (fdiv < XLP_SPI_FDIV_MIN)
	158	fdiv = XLP_SPI_FDIV_MIN;
	159
	160	xlp_spi_reg_write(xspi, cs, XLP_SPI_FDIV, fdiv);
	161	xlp_spi_reg_write(xspi, cs, XLP_SPI_FIFO_THRESH, XLP_SPI_TXRXTH);
	162	cfg = xlp_spi_reg_read(xspi, cs, XLP_SPI_CONFIG);
	163	if (spi->mode & SPI_CPHA)
	164	cfg \|= XLP_SPI_CPHA;
	165	else
	166	cfg &= ~XLP_SPI_CPHA;
	167	if (spi->mode & SPI_CPOL)
	168	cfg \|= XLP_SPI_CPOL;
	169	else
	170	cfg &= ~XLP_SPI_CPOL;
	171	if (!(spi->mode & SPI_CS_HIGH))
	172	cfg \|= XLP_SPI_CS_POL;
	173	else
	174	cfg &= ~XLP_SPI_CS_POL;
	175	if (spi->mode & SPI_LSB_FIRST)
	176	cfg \|= XLP_SPI_CS_LSBFE;
	177	else
	178	cfg &= ~XLP_SPI_CS_LSBFE;
	179
	180	cfg \|= XLP_SPI_TXMOSI_EN \| XLP_SPI_RXMISO_EN;
	181	if (fdiv == 4)
	182	cfg \|= XLP_SPI_RXCAP_EN;
	183	xlp_spi_reg_write(xspi, cs, XLP_SPI_CONFIG, cfg);
	184
	185	return 0;
	186	}
	187
	188	static void xlp_spi_read_rxfifo(struct xlp_spi_priv *xspi)
	189	{
	190	u32 rx_data, rxfifo_cnt;
	191	int i, j, nbytes;
	192
	193	rxfifo_cnt = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_FIFO_WCNT);
	194	rxfifo_cnt &= XLP_SPI_RXFIFO_WCNT_MASK;
	195	while (rxfifo_cnt) {
	196	rx_data = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_RXDATA_FIFO);
	197	j = 0;
	198	nbytes = min(xspi->rx_len, 4);
	199	for (i = nbytes - 1; i >= 0; i--, j++)
	200	xspi->rx_buf[i] = (rx_data >> (j * 8)) & 0xff;
	201
	202	xspi->rx_len -= nbytes;
	203	xspi->rx_buf += nbytes;
	204	rxfifo_cnt--;
	205	}
	206	}
	207
	208	static void xlp_spi_fill_txfifo(struct xlp_spi_priv *xspi)
	209	{
	210	u32 tx_data, txfifo_cnt;
	211	int i, j, nbytes;
	212
	213	txfifo_cnt = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_FIFO_WCNT);
	214	txfifo_cnt &= XLP_SPI_TXFIFO_WCNT_MASK;
	215	txfifo_cnt >>= XLP_SPI_TXFIFO_WCNT_SHIFT;
	216	while (xspi->tx_len && (txfifo_cnt < XLP_SPI_FIFO_SIZE)) {
	217	j = 0;
	218	tx_data = 0;
	219	nbytes = min(xspi->tx_len, 4);
	220	for (i = nbytes - 1; i >= 0; i--, j++)
	221	tx_data \|= xspi->tx_buf[i] << (j * 8);
	222
	223	xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_TXDATA_FIFO, tx_data);
	224	xspi->tx_len -= nbytes;
	225	xspi->tx_buf += nbytes;
	226	txfifo_cnt++;
	227	}
	228	}
	229
	230	static irqreturn_t xlp_spi_interrupt(int irq, void *dev_id)
	231	{
	232	struct xlp_spi_priv *xspi = dev_id;
	233	u32 stat;
	234
	235	stat = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_STATUS) &
	236	XLP_SPI_STAT_MASK;
	237	if (!stat)
	238	return IRQ_NONE;
	239
	240	if (stat & XLP_SPI_TX_INT) {
	241	if (xspi->tx_len)
	242	xlp_spi_fill_txfifo(xspi);
	243	if (stat & XLP_SPI_TX_UF)
	244	xspi->txerrors++;
	245	}
	246
	247	if (stat & XLP_SPI_RX_INT) {
	248	if (xspi->rx_len)
	249	xlp_spi_read_rxfifo(xspi);
	250	if (stat & XLP_SPI_RX_OF)
	251	xspi->rxerrors++;
	252	}
	253
	254	/* write status back to clear interrupts */
	255	xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_STATUS, stat);
	256	if (stat & XLP_SPI_XFR_DONE)
	257	complete(&xspi->done);
	258
	259	return IRQ_HANDLED;
	260	}
	261
	262	static void xlp_spi_send_cmd(struct xlp_spi_priv *xspi, int xfer_len,
	263	int cmd_cont)
	264	{
	265	u32 cmd = 0;
	266
	267	if (xspi->tx_buf)
	268	cmd \|= XLP_SPI_CMD_TX_MASK;
	269	if (xspi->rx_buf)
	270	cmd \|= XLP_SPI_CMD_RX_MASK;
	271	if (cmd_cont)
	272	cmd \|= XLP_SPI_CMD_CONT;
	273	cmd \|= ((xfer_len * 8 - 1) << XLP_SPI_XFR_BITCNT_SHIFT);
	274	xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_CMD, cmd);
	275	}
	276
	277	static int xlp_spi_xfer_block(struct xlp_spi_priv *xs,
	278	const unsigned char *tx_buf,
	279	unsigned char *rx_buf, int xfer_len, int cmd_cont)
	280	{
	281	int timeout;
	282	u32 intr_mask = 0;
	283
	284	xs->tx_buf = tx_buf;
	285	xs->rx_buf = rx_buf;
	286	xs->tx_len = (xs->tx_buf == NULL) ? 0 : xfer_len;
	287	xs->rx_len = (xs->rx_buf == NULL) ? 0 : xfer_len;
	288	xs->txerrors = xs->rxerrors = 0;
	289
	290	/* fill TXDATA_FIFO, then send the CMD */
	291	if (xs->tx_len)
	292	xlp_spi_fill_txfifo(xs);
	293
	294	xlp_spi_send_cmd(xs, xfer_len, cmd_cont);
	295
	296	/*
	297	* We are getting some spurious tx interrupts, so avoid enabling
	298	* tx interrupts when only rx is in process.
	299	* Enable all the interrupts in tx case.
	300	*/
	301	if (xs->tx_len)
	302	intr_mask \|= XLP_SPI_INTR_TXTH \| XLP_SPI_INTR_TXUF \|
	303	XLP_SPI_INTR_RXTH \| XLP_SPI_INTR_RXOF;
	304	else
	305	intr_mask \|= XLP_SPI_INTR_RXTH \| XLP_SPI_INTR_RXOF;
	306
	307	intr_mask \|= XLP_SPI_INTR_DONE;
	308	xlp_spi_reg_write(xs, xs->cs, XLP_SPI_INTR_EN, intr_mask);
	309
	310	timeout = wait_for_completion_timeout(&xs->done,
	311	msecs_to_jiffies(1000));
	312	/* Disable interrupts */
	313	xlp_spi_reg_write(xs, xs->cs, XLP_SPI_INTR_EN, 0x0);
	314	if (!timeout) {
	315	dev_err(&xs->dev, "xfer timedout!\n");
	316	goto out;
	317	}
	318	if (xs->txerrors \|\| xs->rxerrors)
	319	dev_err(&xs->dev, "Over/Underflow rx %d tx %d xfer %d!\n",
	320	xs->rxerrors, xs->txerrors, xfer_len);
	321
	322	return xfer_len;
	323	out:
	324	return -ETIMEDOUT;
	325	}
	326
	327	static int xlp_spi_txrx_bufs(struct xlp_spi_priv xs, struct spi_transfer t)
	328	{
	329	int bytesleft, sz;
	330	unsigned char *rx_buf;
	331	const unsigned char *tx_buf;
	332
	333	tx_buf = t->tx_buf;
	334	rx_buf = t->rx_buf;
	335	bytesleft = t->len;
	336	while (bytesleft) {
	337	if (bytesleft > XLP_SPI_XFER_SIZE)
	338	sz = xlp_spi_xfer_block(xs, tx_buf, rx_buf,
	339	XLP_SPI_XFER_SIZE, 1);
	340	else
	341	sz = xlp_spi_xfer_block(xs, tx_buf, rx_buf,
	342	bytesleft, xs->cmd_cont);
	343	if (sz < 0)
	344	return sz;
	345	bytesleft -= sz;
	346	if (tx_buf)
	347	tx_buf += sz;
	348	if (rx_buf)
	349	rx_buf += sz;
	350	}
	351	return bytesleft;
	352	}
	353
	354	static int xlp_spi_transfer_one(struct spi_master *master,
	355	struct spi_device *spi,
	356	struct spi_transfer *t)
	357	{
	358	struct xlp_spi_priv *xspi = spi_master_get_devdata(master);
	359	int ret = 0;
	360
	361	xspi->cs = spi->chip_select;
	362	xspi->dev = spi->dev;
	363
	364	if (spi_transfer_is_last(master, t))
	365	xspi->cmd_cont = 0;
	366	else
	367	xspi->cmd_cont = 1;
	368
	369	if (xlp_spi_txrx_bufs(xspi, t))
	370	ret = -EIO;
	371
	372	spi_finalize_current_transfer(master);
	373	return ret;
	374	}
	375
	376	static int xlp_spi_probe(struct platform_device *pdev)
	377	{
	378	struct spi_master *master;
	379	struct xlp_spi_priv *xspi;
	380	struct resource *res;
	381	struct clk *clk;
	382	int irq, err;
	383
	384	xspi = devm_kzalloc(&pdev->dev, sizeof(*xspi), GFP_KERNEL);
	385	if (!xspi)
	386	return -ENOMEM;
	387
	388	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	389	xspi->base = devm_ioremap_resource(&pdev->dev, res);
	390	if (IS_ERR(xspi->base))
	391	return PTR_ERR(xspi->base);
	392
	393	irq = platform_get_irq(pdev, 0);
	394	if (irq < 0) {
	395	dev_err(&pdev->dev, "no IRQ resource found\n");
	396	return -EINVAL;
	397	}
	398	err = devm_request_irq(&pdev->dev, irq, xlp_spi_interrupt, 0,
	399	pdev->name, xspi);
	400	if (err) {
	401	dev_err(&pdev->dev, "unable to request irq %d\n", irq);
	402	return err;
	403	}
	404
	405	clk = devm_clk_get(&pdev->dev, NULL);
	406	if (IS_ERR(clk)) {
	407	dev_err(&pdev->dev, "could not get spi clock\n");
	408	return -ENODEV;
	409	}
	410	xspi->spi_clk = clk_get_rate(clk);
	411
	412	master = spi_alloc_master(&pdev->dev, 0);
	413	if (!master) {
	414	dev_err(&pdev->dev, "could not alloc master\n");
	415	return -ENOMEM;
	416	}
	417
	418	master->bus_num = 0;
	419	master->num_chipselect = XLP_SPI_MAX_CS;
	420	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
	421	master->setup = xlp_spi_setup;
	422	master->transfer_one = xlp_spi_transfer_one;
	423	master->dev.of_node = pdev->dev.of_node;
	424
	425	init_completion(&xspi->done);
	426	spi_master_set_devdata(master, xspi);
	427	xlp_spi_sysctl_setup(xspi);
	428
	429	/* register spi controller */
	430	err = devm_spi_register_master(&pdev->dev, master);
	431	if (err) {
	432	dev_err(&pdev->dev, "spi register master failed!\n");
	433	spi_master_put(master);
	434	return err;
	435	}
	436
	437	return 0;
	438	}
	439
	440	static const struct of_device_id xlp_spi_dt_id[] = {
	441	{ .compatible = "netlogic,xlp832-spi" },
	442	{ },
	443	};
	444
	445	static struct platform_driver xlp_spi_driver = {
	446	.probe = xlp_spi_probe,
	447	.driver = {
	448	.name = "xlp-spi",
	449	.of_match_table = xlp_spi_dt_id,
	450	},
	451	};
	452	module_platform_driver(xlp_spi_driver);
	453
	454	MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
	455	MODULE_DESCRIPTION("Netlogic XLP SPI controller driver");
	456	MODULE_LICENSE("GPL v2");

drivers/spi/spi.c+217−18

@@ -67,11 +67,141 @@ modalias_show(struct device dev, struct device_attribute a, char *buf) · 66 unmodified lines
67	}	67	}
68	static DEVICE_ATTR_RO(modalias);	68	static DEVICE_ATTR_RO(modalias);
69		69
		70	#define SPI_STATISTICS_ATTRS(field, file) \
		71	static ssize_t spi_master_##field##_show(struct device *dev, \
		72	struct device_attribute *attr, \
		73	char *buf) \
		74	{ \
		75	struct spi_master *master = container_of(dev, \
		76	struct spi_master, dev); \
		77	return spi_statistics_##field##_show(&master->statistics, buf); \
		78	} \
		79	static struct device_attribute dev_attr_spi_master_##field = { \
		80	.attr = { .name = file, .mode = S_IRUGO }, \
		81	.show = spi_master_##field##_show, \
		82	}; \
		83	static ssize_t spi_device_##field##_show(struct device *dev, \
		84	struct device_attribute *attr, \
		85	char *buf) \
		86	{ \
		87	struct spi_device *spi = container_of(dev, \
		88	struct spi_device, dev); \
		89	return spi_statistics_##field##_show(&spi->statistics, buf); \
		90	} \
		91	static struct device_attribute dev_attr_spi_device_##field = { \
		92	.attr = { .name = file, .mode = S_IRUGO }, \
		93	.show = spi_device_##field##_show, \
		94	}
		95
		96	#define SPI_STATISTICS_SHOW_NAME(name, file, field, format_string) \
		97	static ssize_t spi_statistics_##name##_show(struct spi_statistics *stat, \
		98	char *buf) \
		99	{ \
		100	unsigned long flags; \
		101	ssize_t len; \
		102	spin_lock_irqsave(&stat->lock, flags); \
		103	len = sprintf(buf, format_string, stat->field); \
		104	spin_unlock_irqrestore(&stat->lock, flags); \
		105	return len; \
		106	} \
		107	SPI_STATISTICS_ATTRS(name, file)
		108
		109	#define SPI_STATISTICS_SHOW(field, format_string) \
		110	SPI_STATISTICS_SHOW_NAME(field, __stringify(field), \
		111	field, format_string)
		112
		113	SPI_STATISTICS_SHOW(messages, "%lu");
		114	SPI_STATISTICS_SHOW(transfers, "%lu");
		115	SPI_STATISTICS_SHOW(errors, "%lu");
		116	SPI_STATISTICS_SHOW(timedout, "%lu");
		117
		118	SPI_STATISTICS_SHOW(spi_sync, "%lu");
		119	SPI_STATISTICS_SHOW(spi_sync_immediate, "%lu");
		120	SPI_STATISTICS_SHOW(spi_async, "%lu");
		121
		122	SPI_STATISTICS_SHOW(bytes, "%llu");
		123	SPI_STATISTICS_SHOW(bytes_rx, "%llu");
		124	SPI_STATISTICS_SHOW(bytes_tx, "%llu");
		125
70	static struct attribute *spi_dev_attrs[] = {	126	static struct attribute *spi_dev_attrs[] = {
71	&dev_attr_modalias.attr,	127	&dev_attr_modalias.attr,
72	NULL,	128	NULL,
73	};	129	};
74	ATTRIBUTE_GROUPS(spi_dev);	130
		131	static const struct attribute_group spi_dev_group = {
		132	.attrs = spi_dev_attrs,
		133	};
		134
		135	static struct attribute *spi_device_statistics_attrs[] = {
		136	&dev_attr_spi_device_messages.attr,
		137	&dev_attr_spi_device_transfers.attr,
		138	&dev_attr_spi_device_errors.attr,
		139	&dev_attr_spi_device_timedout.attr,
		140	&dev_attr_spi_device_spi_sync.attr,
		141	&dev_attr_spi_device_spi_sync_immediate.attr,
		142	&dev_attr_spi_device_spi_async.attr,
		143	&dev_attr_spi_device_bytes.attr,
		144	&dev_attr_spi_device_bytes_rx.attr,
		145	&dev_attr_spi_device_bytes_tx.attr,
		146	NULL,
		147	};
		148
		149	static const struct attribute_group spi_device_statistics_group = {
		150	.name = "statistics",
		151	.attrs = spi_device_statistics_attrs,
		152	};
		153
		154	static const struct attribute_group *spi_dev_groups[] = {
		155	&spi_dev_group,
		156	&spi_device_statistics_group,
		157	NULL,
		158	};
		159
		160	static struct attribute *spi_master_statistics_attrs[] = {
		161	&dev_attr_spi_master_messages.attr,
		162	&dev_attr_spi_master_transfers.attr,
		163	&dev_attr_spi_master_errors.attr,
		164	&dev_attr_spi_master_timedout.attr,
		165	&dev_attr_spi_master_spi_sync.attr,
		166	&dev_attr_spi_master_spi_sync_immediate.attr,
		167	&dev_attr_spi_master_spi_async.attr,
		168	&dev_attr_spi_master_bytes.attr,
		169	&dev_attr_spi_master_bytes_rx.attr,
		170	&dev_attr_spi_master_bytes_tx.attr,
		171	NULL,
		172	};
		173
		174	static const struct attribute_group spi_master_statistics_group = {
		175	.name = "statistics",
		176	.attrs = spi_master_statistics_attrs,
		177	};
		178
		179	static const struct attribute_group *spi_master_groups[] = {
		180	&spi_master_statistics_group,
		181	NULL,
		182	};
		183
		184	void spi_statistics_add_transfer_stats(struct spi_statistics *stats,
		185	struct spi_transfer *xfer,
		186	struct spi_master *master)
		187	{
		188	unsigned long flags;
		189
		190	spin_lock_irqsave(&stats->lock, flags);
		191
		192	stats->transfers++;
		193
		194	stats->bytes += xfer->len;
		195	if ((xfer->tx_buf) &&
		196	(xfer->tx_buf != master->dummy_tx))
		197	stats->bytes_tx += xfer->len;
		198	if ((xfer->rx_buf) &&
		199	(xfer->rx_buf != master->dummy_rx))
		200	stats->bytes_rx += xfer->len;
		201
		202	spin_unlock_irqrestore(&stats->lock, flags);
		203	}
		204	EXPORT_SYMBOL_GPL(spi_statistics_add_transfer_stats);
75		205
76	/* modalias support makes "modprobe $MODALIAS" new-style hotplug work,	206	/* modalias support makes "modprobe $MODALIAS" new-style hotplug work,
77	* and the sysfs version makes coldplug work too.	207	* and the sysfs version makes coldplug work too.
@@ -249,6 +379,9 @@ struct spi_device spi_alloc_device(struct spi_master master) · 171 unmodified lines
249	spi->dev.bus = &spi_bus_type;	379	spi->dev.bus = &spi_bus_type;
250	spi->dev.release = spidev_release;	380	spi->dev.release = spidev_release;
251	spi->cs_gpio = -ENOENT;	381	spi->cs_gpio = -ENOENT;
		382
		383	spin_lock_init(&spi->statistics.lock);
		384
252	device_initialize(&spi->dev);	385	device_initialize(&spi->dev);
253	return spi;	386	return spi;
254	}	387	}
@@ -476,21 +609,30 @@ static int spi_map_buf(struct spi_master master, struct device dev, · 221 unmodified lines
476	enum dma_data_direction dir)	609	enum dma_data_direction dir)
477	{	610	{
478	const bool vmalloced_buf = is_vmalloc_addr(buf);	611	const bool vmalloced_buf = is_vmalloc_addr(buf);
479	const int desc_len = vmalloced_buf ? PAGE_SIZE : master->max_dma_len;	612	int desc_len;
480	const int sgs = DIV_ROUND_UP(len, desc_len);	613	int sgs;
481	struct page *vm_page;	614	struct page *vm_page;
482	void *sg_buf;	615	void *sg_buf;
483	size_t min;	616	size_t min;
484	int i, ret;	617	int i, ret;
485		618
		619	if (vmalloced_buf) {
		620	desc_len = PAGE_SIZE;
		621	sgs = DIV_ROUND_UP(len + offset_in_page(buf), desc_len);
		622	} else {
		623	desc_len = master->max_dma_len;
		624	sgs = DIV_ROUND_UP(len, desc_len);
		625	}
		626
486	ret = sg_alloc_table(sgt, sgs, GFP_KERNEL);	627	ret = sg_alloc_table(sgt, sgs, GFP_KERNEL);
487	if (ret != 0)	628	if (ret != 0)
488	return ret;	629	return ret;
489		630
490	for (i = 0; i < sgs; i++) {	631	for (i = 0; i < sgs; i++) {
491	min = min_t(size_t, len, desc_len);
492		632
493	if (vmalloced_buf) {	633	if (vmalloced_buf) {
		634	min = min_t(size_t,
		635	len, desc_len - offset_in_page(buf));
494	vm_page = vmalloc_to_page(buf);	636	vm_page = vmalloc_to_page(buf);
495	if (!vm_page) {	637	if (!vm_page) {
496	sg_free_table(sgt);	638	sg_free_table(sgt);
@@ -499,6 +641,7 @@ static int spi_map_buf(struct spi_master master, struct device dev, · 2 unmodified lines
499	sg_set_page(&sgt->sgl[i], vm_page,	641	sg_set_page(&sgt->sgl[i], vm_page,
500	min, offset_in_page(buf));	642	min, offset_in_page(buf));
501	} else {	643	} else {
		644	min = min_t(size_t, len, desc_len);
502	sg_buf = buf;	645	sg_buf = buf;
503	sg_set_buf(&sgt->sgl[i], sg_buf, min);	646	sg_set_buf(&sgt->sgl[i], sg_buf, min);
504	}	647	}
@@ -539,8 +682,15 @@ static int __spi_map_msg(struct spi_master master, struct spi_message msg) · 34 unmodified lines
539	if (!master->can_dma)	682	if (!master->can_dma)
540	return 0;	683	return 0;
541		684
542	tx_dev = master->dma_tx->device->dev;	685	if (master->dma_tx)
543	rx_dev = master->dma_rx->device->dev;	686	tx_dev = master->dma_tx->device->dev;
		687	else
		688	tx_dev = &master->dev;
		689
		690	if (master->dma_rx)
		691	rx_dev = master->dma_rx->device->dev;
		692	else
		693	rx_dev = &master->dev;
544		694
545	list_for_each_entry(xfer, &msg->transfers, transfer_list) {	695	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
546	if (!master->can_dma(master, msg->spi, xfer))	696	if (!master->can_dma(master, msg->spi, xfer))
@@ -579,8 +729,15 @@ static int __spi_unmap_msg(struct spi_master master, struct spi_message msg) · 32 unmodified lines
579	if (!master->cur_msg_mapped \|\| !master->can_dma)	729	if (!master->cur_msg_mapped \|\| !master->can_dma)
580	return 0;	730	return 0;
581		731
582	tx_dev = master->dma_tx->device->dev;	732	if (master->dma_tx)
583	rx_dev = master->dma_rx->device->dev;	733	tx_dev = master->dma_tx->device->dev;
		734	else
		735	tx_dev = &master->dev;
		736
		737	if (master->dma_rx)
		738	rx_dev = master->dma_rx->device->dev;
		739	else
		740	rx_dev = &master->dev;
584		741
585	list_for_each_entry(xfer, &msg->transfers, transfer_list) {	742	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
586	if (!master->can_dma(master, msg->spi, xfer))	743	if (!master->can_dma(master, msg->spi, xfer))
@@ -689,17 +846,29 @@ static int spi_transfer_one_message(struct spi_master *master, · 102 unmodified lines
689	bool keep_cs = false;	846	bool keep_cs = false;
690	int ret = 0;	847	int ret = 0;
691	unsigned long ms = 1;	848	unsigned long ms = 1;
		849	struct spi_statistics *statm = &master->statistics;
		850	struct spi_statistics *stats = &msg->spi->statistics;
692		851
693	spi_set_cs(msg->spi, true);	852	spi_set_cs(msg->spi, true);
694		853
		854	SPI_STATISTICS_INCREMENT_FIELD(statm, messages);
		855	SPI_STATISTICS_INCREMENT_FIELD(stats, messages);
		856
695	list_for_each_entry(xfer, &msg->transfers, transfer_list) {	857	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
696	trace_spi_transfer_start(msg, xfer);	858	trace_spi_transfer_start(msg, xfer);
697		859
		860	spi_statistics_add_transfer_stats(statm, xfer, master);
		861	spi_statistics_add_transfer_stats(stats, xfer, master);
		862
698	if (xfer->tx_buf \|\| xfer->rx_buf) {	863	if (xfer->tx_buf \|\| xfer->rx_buf) {
699	reinit_completion(&master->xfer_completion);	864	reinit_completion(&master->xfer_completion);
700		865
701	ret = master->transfer_one(master, msg->spi, xfer);	866	ret = master->transfer_one(master, msg->spi, xfer);
702	if (ret < 0) {	867	if (ret < 0) {
		868	SPI_STATISTICS_INCREMENT_FIELD(statm,
		869	errors);
		870	SPI_STATISTICS_INCREMENT_FIELD(stats,
		871	errors);
703	dev_err(&msg->spi->dev,	872	dev_err(&msg->spi->dev,
704	"SPI transfer failed: %d\n", ret);	873	"SPI transfer failed: %d\n", ret);
705	goto out;	874	goto out;
@@ -715,6 +884,10 @@ static int spi_transfer_one_message(struct spi_master *master, · 9 unmodified lines
715	}	884	}
716		885
717	if (ms == 0) {	886	if (ms == 0) {
		887	SPI_STATISTICS_INCREMENT_FIELD(statm,
		888	timedout);
		889	SPI_STATISTICS_INCREMENT_FIELD(stats,
		890	timedout);
718	dev_err(&msg->spi->dev,	891	dev_err(&msg->spi->dev,
719	"SPI transfer timed out\n");	892	"SPI transfer timed out\n");
720	msg->status = -ETIMEDOUT;	893	msg->status = -ETIMEDOUT;
@@ -1416,10 +1589,10 @@ static struct class spi_master_class = { · 695 unmodified lines
1416	.name = "spi_master",	1589	.name = "spi_master",
1417	.owner = THIS_MODULE,	1590	.owner = THIS_MODULE,
1418	.dev_release = spi_master_release,	1591	.dev_release = spi_master_release,
		1592	.dev_groups = spi_master_groups,
1419	};	1593	};
1420		1594
1421		1595
1422
1423	/**	1596	/**
1424	* spi_alloc_master - allocate SPI master controller	1597	* spi_alloc_master - allocate SPI master controller
1425	* @dev: the controller, possibly using the platform_bus	1598	* @dev: the controller, possibly using the platform_bus
@@ -1585,6 +1758,8 @@ int spi_register_master(struct spi_master *master) · 159 unmodified lines
1585	goto done;	1758	goto done;
1586	}	1759	}
1587	}	1760	}
		1761	/* add statistics */
		1762	spin_lock_init(&master->statistics.lock);
1588		1763
1589	mutex_lock(&board_lock);	1764	mutex_lock(&board_lock);
1590	list_add_tail(&master->list, &spi_master_list);	1765	list_add_tail(&master->list, &spi_master_list);
@@ -1740,6 +1915,20 @@ EXPORT_SYMBOL_GPL(spi_busnum_to_master); · 149 unmodified lines
1740	* other core methods are currently defined as inline functions.	1915	* other core methods are currently defined as inline functions.
1741	*/	1916	*/
1742		1917
		1918	static int __spi_validate_bits_per_word(struct spi_master *master, u8 bits_per_word)
		1919	{
		1920	if (master->bits_per_word_mask) {
		1921	/* Only 32 bits fit in the mask */
		1922	if (bits_per_word > 32)
		1923	return -EINVAL;
		1924	if (!(master->bits_per_word_mask &
		1925	SPI_BPW_MASK(bits_per_word)))
		1926	return -EINVAL;
		1927	}
		1928
		1929	return 0;
		1930	}
		1931
1743	/**	1932	/**
1744	* spi_setup - setup SPI mode and clock rate	1933	* spi_setup - setup SPI mode and clock rate
1745	* @spi: the device whose settings are being modified	1934	* @spi: the device whose settings are being modified
@@ -1798,6 +1987,9 @@ int spi_setup(struct spi_device *spi) · 52 unmodified lines
1798	if (!spi->bits_per_word)	1987	if (!spi->bits_per_word)
1799	spi->bits_per_word = 8;	1988	spi->bits_per_word = 8;
1800		1989
		1990	if (__spi_validate_bits_per_word(spi->master, spi->bits_per_word))
		1991	return -EINVAL;
		1992
1801	if (!spi->max_speed_hz)	1993	if (!spi->max_speed_hz)
1802	spi->max_speed_hz = spi->master->max_speed_hz;	1994	spi->max_speed_hz = spi->master->max_speed_hz;
1803		1995
@@ -1860,19 +2052,15 @@ static int __spi_validate(struct spi_device spi, struct spi_message message) · 56 unmodified lines
1860		2052
1861	if (!xfer->speed_hz)	2053	if (!xfer->speed_hz)
1862	xfer->speed_hz = spi->max_speed_hz;	2054	xfer->speed_hz = spi->max_speed_hz;
		2055	if (!xfer->speed_hz)
		2056	xfer->speed_hz = master->max_speed_hz;
1863		2057
1864	if (master->max_speed_hz &&	2058	if (master->max_speed_hz &&
1865	xfer->speed_hz > master->max_speed_hz)	2059	xfer->speed_hz > master->max_speed_hz)
1866	xfer->speed_hz = master->max_speed_hz;	2060	xfer->speed_hz = master->max_speed_hz;
1867		2061
1868	if (master->bits_per_word_mask) {	2062	if (__spi_validate_bits_per_word(master, xfer->bits_per_word))
1869	/* Only 32 bits fit in the mask */	2063	return -EINVAL;
1870	if (xfer->bits_per_word > 32)
1871	return -EINVAL;
1872	if (!(master->bits_per_word_mask &
1873	BIT(xfer->bits_per_word - 1)))
1874	return -EINVAL;
1875	}
1876		2064
1877	/*	2065	/*
1878	* SPI transfer length should be multiple of SPI word size	2066	* SPI transfer length should be multiple of SPI word size
@@ -1939,6 +2127,9 @@ static int __spi_async(struct spi_device spi, struct spi_message message) · 60 unmodified lines
1939		2127
1940	message->spi = spi;	2128	message->spi = spi;
1941		2129
		2130	SPI_STATISTICS_INCREMENT_FIELD(&master->statistics, spi_async);
		2131	SPI_STATISTICS_INCREMENT_FIELD(&spi->statistics, spi_async);
		2132
1942	trace_spi_message_submit(message);	2133	trace_spi_message_submit(message);
1943		2134
1944	return master->transfer(spi, message);	2135	return master->transfer(spi, message);
@@ -2075,6 +2266,9 @@ static int __spi_sync(struct spi_device spi, struct spi_message message, · 130 unmodified lines
2075	message->context = &done;	2266	message->context = &done;
2076	message->spi = spi;	2267	message->spi = spi;
2077		2268
		2269	SPI_STATISTICS_INCREMENT_FIELD(&master->statistics, spi_sync);
		2270	SPI_STATISTICS_INCREMENT_FIELD(&spi->statistics, spi_sync);
		2271
2078	if (!bus_locked)	2272	if (!bus_locked)
2079	mutex_lock(&master->bus_lock_mutex);	2273	mutex_lock(&master->bus_lock_mutex);
2080		2274
@@ -2102,8 +2296,13 @@ static int __spi_sync(struct spi_device spi, struct spi_message message, · 21 unmodified lines
2102	/* Push out the messages in the calling context if we	2296	/* Push out the messages in the calling context if we
2103	* can.	2297	* can.
2104	*/	2298	*/
2105	if (master->transfer == spi_queued_transfer)	2299	if (master->transfer == spi_queued_transfer) {
		2300	SPI_STATISTICS_INCREMENT_FIELD(&master->statistics,
		2301	spi_sync_immediate);
		2302	SPI_STATISTICS_INCREMENT_FIELD(&spi->statistics,
		2303	spi_sync_immediate);
2106	__spi_pump_messages(master, false);	2304	__spi_pump_messages(master, false);
		2305	}
2107		2306
2108	wait_for_completion(&done);	2307	wait_for_completion(&done);
2109	status = message->status;	2308	status = message->status;

drivers/spi/spidev.c+4−4

 	if (!spidev->tx_buffer) {
 		spidev->tx_buffer = kmalloc(bufsiz, GFP_KERNEL);
 		if (!spidev->tx_buffer) {
-				dev_dbg(&spidev->spi->dev, "open/ENOMEM\n");
+			dev_dbg(&spidev->spi->dev, "open/ENOMEM\n");
-				status = -ENOMEM;
+			status = -ENOMEM;
 			goto err_find_dev;
-			}
 		}
+	}
 	if (!spidev->rx_buffer) {
 		spidev->rx_buffer = kmalloc(bufsiz, GFP_KERNEL);
 	/*
 	 * spidev should never be referenced in DT without a specific
-	 * compatbile string, it is a Linux implementation thing
+	 * compatible string, it is a Linux implementation thing
 	 * rather than a description of the hardware.
 	 */
 	if (spi->dev.of_node && !of_match_device(spidev_dt_ids, &spi->dev)) {

include/linux/platform_data/spi-davinci.h+1−0

@@ -49,6 +49,7 @@ struct davinci_spi_platform_data { · 48 unmodified lines
49	u8 num_chipselect;	49	u8 num_chipselect;
50	u8 intr_line;	50	u8 intr_line;
51	u8 *chip_sel;	51	u8 *chip_sel;
		52	u8 prescaler_limit;
52	bool cshold_bug;	53	bool cshold_bug;
53	enum dma_event_q dma_event_q;	54	enum dma_event_q dma_event_q;
54	};	55	};

include/linux/platform_data/spi-mt65xx.h+20−0

@@ -0,0 +1,20 @@
	1	/*
	2	* MTK SPI bus driver definitions
	3	*
	4	* Copyright (c) 2015 MediaTek Inc.
	5	* Author: Leilk Liu <leilk.liu@mediatek.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
	13	#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
	14
	15	/* Board specific platform_data */
	16	struct mtk_chip_config {
	17	u32 tx_mlsb;
	18	u32 rx_mlsb;
	19	};
	20	#endif

include/linux/pxa2xx_ssp.h+1−0

@@ -197,6 +197,7 @@ enum pxa_ssp_type { · 196 unmodified lines
197	QUARK_X1000_SSP,	197	QUARK_X1000_SSP,
198	LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */	198	LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */
199	LPSS_BYT_SSP,	199	LPSS_BYT_SSP,
		200	LPSS_SPT_SSP,
200	};	201	};
201		202
202	struct ssp_device {	203	struct ssp_device {

include/linux/spi/spi.h+64−0

@@ -23,6 +23,8 @@ · 22 unmodified lines
23	#include <linux/scatterlist.h>	23	#include <linux/scatterlist.h>
24		24
25	struct dma_chan;	25	struct dma_chan;
		26	struct spi_master;
		27	struct spi_transfer;
26		28
27	/*	29	/*
28	* INTERFACES between SPI master-side drivers and SPI infrastructure.	30	* INTERFACES between SPI master-side drivers and SPI infrastructure.
@@ -30,6 +32,59 @@ struct dma_chan; · 1 unmodified line
30	*/	32	*/
31	extern struct bus_type spi_bus_type;	33	extern struct bus_type spi_bus_type;
32		34
		35	/**
		36	* struct spi_statistics - statistics for spi transfers
		37	* @clock: lock protecting this structure
		38	*
		39	* @messages: number of spi-messages handled
		40	* @transfers: number of spi_transfers handled
		41	* @errors: number of errors during spi_transfer
		42	* @timedout: number of timeouts during spi_transfer
		43	*
		44	* @spi_sync: number of times spi_sync is used
		45	* @spi_sync_immediate:
		46	* number of times spi_sync is executed immediately
		47	* in calling context without queuing and scheduling
		48	* @spi_async: number of times spi_async is used
		49	*
		50	* @bytes: number of bytes transferred to/from device
		51	* @bytes_tx: number of bytes sent to device
		52	* @bytes_rx: number of bytes received from device
		53	*
		54	*/
		55	struct spi_statistics {
		56	spinlock_t lock; /* lock for the whole structure */
		57
		58	unsigned long messages;
		59	unsigned long transfers;
		60	unsigned long errors;
		61	unsigned long timedout;
		62
		63	unsigned long spi_sync;
		64	unsigned long spi_sync_immediate;
		65	unsigned long spi_async;
		66
		67	unsigned long long bytes;
		68	unsigned long long bytes_rx;
		69	unsigned long long bytes_tx;
		70
		71	};
		72
		73	void spi_statistics_add_transfer_stats(struct spi_statistics *stats,
		74	struct spi_transfer *xfer,
		75	struct spi_master *master);
		76
		77	#define SPI_STATISTICS_ADD_TO_FIELD(stats, field, count) \
		78	do { \
		79	unsigned long flags; \
		80	spin_lock_irqsave(&(stats)->lock, flags); \
		81	(stats)->field += count; \
		82	spin_unlock_irqrestore(&(stats)->lock, flags); \
		83	} while (0)
		84
		85	#define SPI_STATISTICS_INCREMENT_FIELD(stats, field) \
		86	SPI_STATISTICS_ADD_TO_FIELD(stats, field, 1)
		87
33	/**	88	/**
34	* struct spi_device - Master side proxy for an SPI slave device	89	* struct spi_device - Master side proxy for an SPI slave device
35	* @dev: Driver model representation of the device.	90	* @dev: Driver model representation of the device.
@@ -60,6 +115,8 @@ extern struct bus_type spi_bus_type; · 24 unmodified lines
60	* @cs_gpio: gpio number of the chipselect line (optional, -ENOENT when	115	* @cs_gpio: gpio number of the chipselect line (optional, -ENOENT when
61	* when not using a GPIO line)	116	* when not using a GPIO line)
62	*	117	*
		118	* @statistics: statistics for the spi_device
		119	*
63	* A @spi_device is used to interchange data between an SPI slave	120	* A @spi_device is used to interchange data between an SPI slave
64	* (usually a discrete chip) and CPU memory.	121	* (usually a discrete chip) and CPU memory.
65	*	122	*
@@ -98,6 +155,9 @@ struct spi_device { · 32 unmodified lines
98	char modalias[SPI_NAME_SIZE];	155	char modalias[SPI_NAME_SIZE];
99	int cs_gpio; /* chip select gpio */	156	int cs_gpio; /* chip select gpio */
100		157
		158	/* the statistics */
		159	struct spi_statistics statistics;
		160
101	/*	161	/*
102	* likely need more hooks for more protocol options affecting how	162	* likely need more hooks for more protocol options affecting how
103	* the controller talks to each chip, like:	163	* the controller talks to each chip, like:
@@ -296,6 +356,7 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv) · 192 unmodified lines
296	* @cs_gpios: Array of GPIOs to use as chip select lines; one per CS	356	* @cs_gpios: Array of GPIOs to use as chip select lines; one per CS
297	* number. Any individual value may be -ENOENT for CS lines that	357	* number. Any individual value may be -ENOENT for CS lines that
298	* are not GPIOs (driven by the SPI controller itself).	358	* are not GPIOs (driven by the SPI controller itself).
		359	* @statistics: statistics for the spi_master
299	* @dma_tx: DMA transmit channel	360	* @dma_tx: DMA transmit channel
300	* @dma_rx: DMA receive channel	361	* @dma_rx: DMA receive channel
301	* @dummy_rx: dummy receive buffer for full-duplex devices	362	* @dummy_rx: dummy receive buffer for full-duplex devices
@@ -452,6 +513,9 @@ struct spi_master { · 150 unmodified lines
452	/* gpio chip select */	513	/* gpio chip select */
453	int *cs_gpios;	514	int *cs_gpios;
454		515
		516	/* statistics */
		517	struct spi_statistics statistics;
		518
455	/* DMA channels for use with core dmaengine helpers */	519	/* DMA channels for use with core dmaengine helpers */
456	struct dma_chan *dma_tx;	520	struct dma_chan *dma_tx;
457	struct dma_chan *dma_rx;	521	struct dma_chan *dma_rx;

Merge tag 'spi-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

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