ASoC: Set BQ parameters for some Dell models

There are some Dell SKUs that need to set the parameters of the crossover filter (biquad). Each amplifier connects to one tweeter speaker and one woofer speaker. We should control HPF/LPF to output the proper frequency for the different speakers. If the codec driver got the BQ parameters from the device property, it will apply these parameters to the hardware.

Mark Brown committed 4 years ago

Commit e5fa3cc2 parents 9f63869 cf6946d1113 files · +14144 −8935Browse files

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7 files

include/uapi/drm/amdgpu_drm.h +2 −0
include/uapi/drm/panfrost_drm.h +20 −16
include/uapi/linux/cec-funcs.h +14 −0
include/uapi/linux/cec.h +2 −0
include/uapi/linux/perf_event.h +1 −1
include/uapi/linux/rkisp1-config.h +61 −16
include/uapi/linux/videodev2.h +2 −1

include/uapi/drm/amdgpu_drm.h+2−0

@@ -763,6 +763,8 @@ struct drm_amdgpu_cs_chunk_data { · 762 unmodified lines
763	763	#define AMDGPU_INFO_FW_MES_KIQ 0x19
764	764	/* Subquery id: Query MES firmware version */
765	765	#define AMDGPU_INFO_FW_MES 0x1a
	766	+ /* Subquery id: Query IMU firmware version */
	767	+ #define AMDGPU_INFO_FW_IMU 0x1b
766	768
767	769	/* number of bytes moved for TTM migration */
768	770	#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f

include/uapi/drm/panfrost_drm.h+20−16

@@ -235,25 +235,29 @@ struct drm_panfrost_madvise { · 234 unmodified lines
235	235	#define PANFROSTDUMP_BUF_BO (PANFROSTDUMP_BUF_BOMAP + 1)
236	236	#define PANFROSTDUMP_BUF_TRAILER (PANFROSTDUMP_BUF_BO + 1)
237	237
	238	+/*
	239	+ * This structure is the native endianness of the dumping machine, tools can
	240	+ * detect the endianness by looking at the value in 'magic'.
	241	+ */
238	242	struct panfrost_dump_object_header {
239		− __le32 magic;
240		− __le32 type;
241		− __le32 file_size;
242		− __le32 file_offset;
	243	+ __u32 magic;
	244	+ __u32 type;
	245	+ __u32 file_size;
	246	+ __u32 file_offset;
243	247
244	248	union {
245		− struct pan_reg_hdr {
246		− __le64 jc;
247		− __le32 gpu_id;
248		− __le32 major;
249		− __le32 minor;
250		− __le64 nbos;
	249	+ struct {
	250	+ __u64 jc;
	251	+ __u32 gpu_id;
	252	+ __u32 major;
	253	+ __u32 minor;
	254	+ __u64 nbos;
251	255	} reghdr;
252	256
253	257	struct pan_bomap_hdr {
254		− __le32 valid;
255		− __le64 iova;
256		− __le32 data[2];
	258	+ __u32 valid;
	259	+ __u64 iova;
	260	+ __u32 data[2];
257	261	} bomap;
258	262
259	263	/*
@@ -261,14 +265,14 @@ struct panfrost_dump_object_header { · 1 unmodified line
261	265	* with new fields and also keep it 512-byte aligned
262	266	*/
263	267
264		− __le32 sizer[496];
	268	+ __u32 sizer[496];
265	269	};
266	270	};
267	271
268	272	/* Registers object, an array of these */
269	273	struct panfrost_dump_registers {
270		− __le32 reg;
271		− __le32 value;
	274	+ __u32 reg;
	275	+ __u32 value;
272	276	};
273	277
274	278	#if defined(__cplusplus)

include/uapi/linux/cec-funcs.h+14−0

@@ -1568,6 +1568,20 @@ static inline void cec_ops_request_short_audio_descriptor(const struct cec_msg * · 1567 unmodified lines
1568	1568	}
1569	1569	}
1570	1570
	1571	+static inline void cec_msg_set_audio_volume_level(struct cec_msg *msg,
	1572	+ __u8 audio_volume_level)
	1573	+{
	1574	+ msg->len = 3;
	1575	+ msg->msg[1] = CEC_MSG_SET_AUDIO_VOLUME_LEVEL;
	1576	+ msg->msg[2] = audio_volume_level;
	1577	+}
	1578	+
	1579	+static inline void cec_ops_set_audio_volume_level(const struct cec_msg *msg,
	1580	+ __u8 *audio_volume_level)
	1581	+{
	1582	+ *audio_volume_level = msg->msg[2];
	1583	+}
	1584	+
1571	1585
1572	1586	/* Audio Rate Control Feature */
1573	1587	static inline void cec_msg_set_audio_rate(struct cec_msg *msg,

include/uapi/linux/cec.h+2−0

@@ -768,6 +768,7 @@ struct cec_event { · 767 unmodified lines
768	768	#define CEC_OP_FEAT_DEV_HAS_SET_AUDIO_RATE 0x08
769	769	#define CEC_OP_FEAT_DEV_SINK_HAS_ARC_TX 0x04
770	770	#define CEC_OP_FEAT_DEV_SOURCE_HAS_ARC_RX 0x02
	771	+#define CEC_OP_FEAT_DEV_HAS_SET_AUDIO_VOLUME_LEVEL 0x01
771	772
772	773	#define CEC_MSG_GIVE_FEATURES 0xa5 /* HDMI 2.0 */
773	774
@@ -1059,6 +1060,7 @@ struct cec_event { · 285 unmodified lines
1059	1060	#define CEC_OP_AUD_FMT_ID_CEA861 0
1060	1061	#define CEC_OP_AUD_FMT_ID_CEA861_CXT 1
1061	1062
	1063	+#define CEC_MSG_SET_AUDIO_VOLUME_LEVEL 0x73
1062	1064
1063	1065	/* Audio Rate Control Feature */
1064	1066	#define CEC_MSG_SET_AUDIO_RATE 0x9a

include/uapi/linux/perf_event.h+1−1

@@ -1337,7 +1337,7 @@ union perf_mem_data_src { · 1336 unmodified lines
1337	1337	#define PERF_MEM_LVLNUM_L3 0x03 /* L3 */
1338	1338	#define PERF_MEM_LVLNUM_L4 0x04 /* L4 */
1339	1339	/* 5-0x8 available */
1340		−#define PERF_MEM_LVLNUM_EXTN_MEM 0x09 /* Extension memory */
	1340	+#define PERF_MEM_LVLNUM_CXL 0x09 /* CXL */
1341	1341	#define PERF_MEM_LVLNUM_IO 0x0a /* I/O */
1342	1342	#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
1343	1343	#define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */

include/uapi/linux/rkisp1-config.h+61−16

@@ -117,7 +117,46 @@ · 116 unmodified lines
117	117	/*
118	118	* Defect Pixel Cluster Correction
119	119	*/
120		−#define RKISP1_CIF_ISP_DPCC_METHODS_MAX 3
	120	+#define RKISP1_CIF_ISP_DPCC_METHODS_MAX 3
	121	+
	122	+#define RKISP1_CIF_ISP_DPCC_MODE_STAGE1_ENABLE (1U << 2)
	123	+
	124	+#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_STAGE1_INCL_G_CENTER (1U << 0)
	125	+#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_STAGE1_INCL_RB_CENTER (1U << 1)
	126	+#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_STAGE1_G_3X3 (1U << 2)
	127	+#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_STAGE1_RB_3X3 (1U << 3)
	128	+
	129	+/* 0-2 for sets 1-3 */
	130	+#define RKISP1_CIF_ISP_DPCC_SET_USE_STAGE1_USE_SET(n) ((n) << 0)
	131	+#define RKISP1_CIF_ISP_DPCC_SET_USE_STAGE1_USE_FIX_SET (1U << 3)
	132	+
	133	+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_PG_GREEN_ENABLE (1U << 0)
	134	+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_LC_GREEN_ENABLE (1U << 1)
	135	+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RO_GREEN_ENABLE (1U << 2)
	136	+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RND_GREEN_ENABLE (1U << 3)
	137	+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RG_GREEN_ENABLE (1U << 4)
	138	+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_PG_RED_BLUE_ENABLE (1U << 8)
	139	+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_LC_RED_BLUE_ENABLE (1U << 9)
	140	+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RO_RED_BLUE_ENABLE (1U << 10)
	141	+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RND_RED_BLUE_ENABLE (1U << 11)
	142	+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RG_RED_BLUE_ENABLE (1U << 12)
	143	+
	144	+#define RKISP1_CIF_ISP_DPCC_LINE_THRESH_G(v) ((v) << 0)
	145	+#define RKISP1_CIF_ISP_DPCC_LINE_THRESH_RB(v) ((v) << 8)
	146	+#define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_G(v) ((v) << 0)
	147	+#define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_RB(v) ((v) << 8)
	148	+#define RKISP1_CIF_ISP_DPCC_PG_FAC_G(v) ((v) << 0)
	149	+#define RKISP1_CIF_ISP_DPCC_PG_FAC_RB(v) ((v) << 8)
	150	+#define RKISP1_CIF_ISP_DPCC_RND_THRESH_G(v) ((v) << 0)
	151	+#define RKISP1_CIF_ISP_DPCC_RND_THRESH_RB(v) ((v) << 8)
	152	+#define RKISP1_CIF_ISP_DPCC_RG_FAC_G(v) ((v) << 0)
	153	+#define RKISP1_CIF_ISP_DPCC_RG_FAC_RB(v) ((v) << 8)
	154	+
	155	+#define RKISP1_CIF_ISP_DPCC_RO_LIMITS_n_G(n, v) ((v) << ((n) * 4))
	156	+#define RKISP1_CIF_ISP_DPCC_RO_LIMITS_n_RB(n, v) ((v) << ((n) * 4 + 2))
	157	+
	158	+#define RKISP1_CIF_ISP_DPCC_RND_OFFS_n_G(n, v) ((v) << ((n) * 4))
	159	+#define RKISP1_CIF_ISP_DPCC_RND_OFFS_n_RB(n, v) ((v) << ((n) * 4 + 2))
121	160
122	161	/*
123	162	* Denoising pre filter
@@ -249,16 +288,20 @@ struct rkisp1_cif_isp_bls_config { · 125 unmodified lines
249	288	};
250	289
251	290	/**
252		− * struct rkisp1_cif_isp_dpcc_methods_config - Methods Configuration used by DPCC
	291	+ * struct rkisp1_cif_isp_dpcc_methods_config - DPCC methods set configuration
253	292	*
254		− * Methods Configuration used by Defect Pixel Cluster Correction
	293	+ * This structure stores the configuration of one set of methods for the DPCC
	294	+ * algorithm. Multiple methods can be selected in each set (independently for
	295	+ * the Green and Red/Blue components) through the @method field, the result is
	296	+ * the logical AND of all enabled methods. The remaining fields set thresholds
	297	+ * and factors for each method.
255	298	*
256		− * @method: Method enable bits
257		− * @line_thresh: Line threshold
258		− * @line_mad_fac: Line MAD factor
259		− * @pg_fac: Peak gradient factor
260		− * @rnd_thresh: Rank Neighbor Difference threshold
261		− * @rg_fac: Rank gradient factor
	299	+ * @method: Method enable bits (RKISP1_CIF_ISP_DPCC_METHODS_SET_*)
	300	+ * @line_thresh: Line threshold (RKISP1_CIF_ISP_DPCC_LINE_THRESH_*)
	301	+ * @line_mad_fac: Line Mean Absolute Difference factor (RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_*)
	302	+ * @pg_fac: Peak gradient factor (RKISP1_CIF_ISP_DPCC_PG_FAC_*)
	303	+ * @rnd_thresh: Rank Neighbor Difference threshold (RKISP1_CIF_ISP_DPCC_RND_THRESH_*)
	304	+ * @rg_fac: Rank gradient factor (RKISP1_CIF_ISP_DPCC_RG_FAC_*)
262	305	*/
263	306	struct rkisp1_cif_isp_dpcc_methods_config {
264	307	__u32 method;
@@ -272,14 +315,16 @@ struct rkisp1_cif_isp_dpcc_methods_config { · 7 unmodified lines
272	315	/**
273	316	* struct rkisp1_cif_isp_dpcc_config - Configuration used by DPCC
274	317	*
275		− * Configuration used by Defect Pixel Cluster Correction
	318	+ * Configuration used by Defect Pixel Cluster Correction. Three sets of methods
	319	+ * can be configured and selected through the @set_use field. The result is the
	320	+ * logical OR of all enabled sets.
276	321	*
277		− * @mode: dpcc output mode
278		− * @output_mode: whether use hard coded methods
279		− * @set_use: stage1 methods set
280		− * @methods: methods config
281		− * @ro_limits: rank order limits
282		− * @rnd_offs: differential rank offsets for rank neighbor difference
	322	+ * @mode: DPCC mode (RKISP1_CIF_ISP_DPCC_MODE_*)
	323	+ * @output_mode: Interpolation output mode (RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_*)
	324	+ * @set_use: Methods sets selection (RKISP1_CIF_ISP_DPCC_SET_USE_*)
	325	+ * @methods: Methods sets configuration
	326	+ * @ro_limits: Rank order limits (RKISP1_CIF_ISP_DPCC_RO_LIMITS_*)
	327	+ * @rnd_offs: Differential rank offsets for rank neighbor difference (RKISP1_CIF_ISP_DPCC_RND_OFFS_*)
283	328	*/
284	329	struct rkisp1_cif_isp_dpcc_config {
285	330	__u32 mode;

include/uapi/linux/videodev2.h+2−1

@@ -1601,7 +1601,8 @@ struct v4l2_bt_timings { · 1600 unmodified lines
1601	1601	((bt)->width + V4L2_DV_BT_BLANKING_WIDTH(bt))
1602	1602	#define V4L2_DV_BT_BLANKING_HEIGHT(bt) \
1603	1603	((bt)->vfrontporch + (bt)->vsync + (bt)->vbackporch + \
1604		− (bt)->il_vfrontporch + (bt)->il_vsync + (bt)->il_vbackporch)
	1604	+ ((bt)->interlaced ? \
	1605	+ ((bt)->il_vfrontporch + (bt)->il_vsync + (bt)->il_vbackporch) : 0))
1605	1606	#define V4L2_DV_BT_FRAME_HEIGHT(bt) \
1606	1607	((bt)->height + V4L2_DV_BT_BLANKING_HEIGHT(bt))
1607	1608