History

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle: "This is the main pull request for 3.17. It contains: - misc Cavium Octeon, BCM47xx, BCM63xx and Alchemy updates - MIPS ptrace updates and cleanups - various fixes that will also go to -stable - a number of cleanups and small non-critical fixes. - NUMA support for the Loongson 3. - more support for MSA - support for MAAR - various FP enhancements and fixes" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) MIPS: jz4740: remove unnecessary null test before debugfs_remove MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursive MIPS: ZBOOT: implement stack protector in compressed boot phase MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT MIPS: Bonito64: remove a duplicate define MIPS: Malta: initialise MAARs MIPS: Initialise MAARs MIPS: detect presence of MAARs MIPS: define MAAR register accessors & bits MIPS: mark MSA experimental MIPS: Don't build MSA support unless it can be used MIPS: consistently clear MSA flags when starting & copying threads MIPS: 16 byte align MSA vector context MIPS: disable preemption whilst initialising MSA MIPS: ensure MSA gets disabled during boot MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains MIPS: fix MSA context for tasks which don't use FP first MIPS: init upper 64b of vector registers when MSA is first used MIPS: save/disable MSA in lose_fpu MIPS: preserve scalar FP CSR when switching vector context ...

Linus Torvalds committed 12 years ago

Commit e6698302 parents ebb067d 475d592156 files · +5979 −3529Browse files

Unified · Split

156 files
  1. Documentation/kernel-parameters.txt +6 −0
  2. arch/mips/Kconfig +7 −2
  3. arch/mips/Makefile +3 −1
  4. arch/mips/alchemy/board-mtx1.c +2 −2
  5. arch/mips/alchemy/board-xxs1500.c +2 −2
  6. arch/mips/alchemy/common/Makefile +2 −2
  7. arch/mips/alchemy/common/clock.c +1094 −0
  8. arch/mips/alchemy/common/clocks.c +0 −105
  9. arch/mips/alchemy/common/dbdma.c +11 −11
  10. arch/mips/alchemy/common/dma.c +8 −7
  11. arch/mips/alchemy/common/irq.c +2 −3
  12. arch/mips/alchemy/common/platform.c +13 −2
  13. arch/mips/alchemy/common/power.c +36 −38
  14. arch/mips/alchemy/common/setup.c +0 −15
  15. arch/mips/alchemy/common/time.c +10 −13
  16. arch/mips/alchemy/common/usb.c +40 −7
  17. arch/mips/alchemy/devboards/db1000.c +16 −3
  18. arch/mips/alchemy/devboards/db1200.c +28 −33
  19. arch/mips/alchemy/devboards/db1300.c +8 −1
  20. arch/mips/alchemy/devboards/db1550.c +20 −7
  21. arch/mips/alchemy/devboards/pm.c +15 −24
  22. arch/mips/bcm47xx/Kconfig +1 −4
  23. arch/mips/bcm47xx/bcm47xx_private.h +3 −0
  24. arch/mips/bcm47xx/board.c +22 −4
  25. arch/mips/bcm47xx/buttons.c +34 −4
  26. arch/mips/bcm47xx/leds.c +79 −13
  27. arch/mips/bcm47xx/prom.c +67 −1
  28. arch/mips/bcm47xx/setup.c +5 −2
  29. arch/mips/bcm47xx/sprom.c +48 −0
  30. arch/mips/bcm63xx/cpu.c +3 −8
  31. arch/mips/bcm63xx/dev-enet.c +0 −4
  32. arch/mips/bcm63xx/dev-spi.c +0 −4
  33. arch/mips/bcm63xx/gpio.c +0 −14
  34. arch/mips/bcm63xx/irq.c +269 −289
  35. arch/mips/bcm63xx/reset.c +0 −60
  36. arch/mips/boot/compressed/decompress.c +14 −0
  37. arch/mips/cavium-octeon/executive/cvmx-helper-board.c +22 −0
  38. arch/mips/cavium-octeon/oct_ilm.c +1 −2
  39. arch/mips/cavium-octeon/smp.c +12 −11
  40. arch/mips/configs/loongson3_defconfig +1 −1
  41. arch/mips/include/asm/Kbuild +1 −0
  42. arch/mips/include/asm/addrspace.h +1 −1
  43. arch/mips/include/asm/asmmacro.h +31 −0
  44. arch/mips/include/asm/bitops.h +7 −1
  45. arch/mips/include/asm/cop2.h +8 −0
  46. arch/mips/include/asm/cpu-features.h +9 −0
  47. arch/mips/include/asm/cpu-info.h +3 −2
  48. arch/mips/include/asm/cpu.h +33 −28
  49. arch/mips/include/asm/elf.h +0 −17
  50. arch/mips/include/asm/fpu.h +12 −7
  51. arch/mips/include/asm/gic.h +15 −26
  52. arch/mips/include/asm/maar.h +109 −0
  53. arch/mips/include/asm/mach-au1x00/au1000.h +1082 −1433
  54. arch/mips/include/asm/mach-au1x00/au1000_dma.h +25 −25
  55. arch/mips/include/asm/mach-au1x00/gpio-au1000.h +26 −30
  56. arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h +6 −1
  57. arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +35 −163
  58. arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h +0 −46
  59. arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h +0 −31
  60. arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +8 −8
  61. arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h +1 −1
  62. arch/mips/include/asm/mach-loongson/boot_param.h +4 −0
  63. arch/mips/include/asm/mach-loongson/kernel-entry-init.h +52 −0
  64. arch/mips/include/asm/mach-loongson/loongson.h +9 −2
  65. arch/mips/include/asm/mach-loongson/machine.h +2 −2
  66. arch/mips/include/asm/mach-loongson/mmzone.h +53 −0
  67. arch/mips/include/asm/mach-loongson/topology.h +23 −0
  68. arch/mips/include/asm/mach-malta/irq.h +1 −0
  69. arch/mips/include/asm/mach-sead3/irq.h +1 −0
  70. arch/mips/include/asm/mips-boards/bonito64.h +0 −1
  71. arch/mips/include/asm/mipsregs.h +57 −1
  72. arch/mips/include/asm/mmu_context.h +10 −0
  73. arch/mips/include/asm/msa.h +18 −13
  74. arch/mips/include/asm/octeon/cvmx-bootinfo.h +2 −0
  75. arch/mips/include/asm/pgtable-32.h +12 −0
  76. arch/mips/include/asm/pgtable.h +27 −0
  77. arch/mips/include/asm/processor.h +8 −2
  78. arch/mips/include/asm/ptrace.h +5 −3
  79. arch/mips/include/asm/reg.h +1 −128
  80. arch/mips/include/asm/smp-cps.h +10 −2
  81. arch/mips/include/asm/smp.h +6 −0
  82. arch/mips/include/asm/sparsemem.h +1 −1
  83. arch/mips/include/asm/user.h +0 −58
  84. arch/mips/include/uapi/asm/ptrace.h +14 −11
  85. arch/mips/include/uapi/asm/reg.h +206 −0
  86. arch/mips/jz4740/clock-debugfs.c +1 −2
  87. arch/mips/jz4740/platform.c +1 −1
  88. arch/mips/kernel/asm-offsets.c +1 −0
  89. arch/mips/kernel/binfmt_elfo32.c +0 −38
  90. arch/mips/kernel/cpu-probe.c +42 −3
  91. arch/mips/kernel/ftrace.c +47 −9
  92. arch/mips/kernel/irq-gic.c +30 −8
  93. arch/mips/kernel/mcount.S +13 −0
  94. arch/mips/kernel/perf_event_mipsxx.c +34 −8
  95. arch/mips/kernel/pm-cps.c +9 −1
  96. arch/mips/kernel/proc.c +2 −0
  97. arch/mips/kernel/process.c +4 −56
  98. arch/mips/kernel/ptrace.c +177 −46
  99. arch/mips/kernel/ptrace32.c +6 −4
  100. arch/mips/kernel/r4k_switch.S +8 −1
  101. arch/mips/kernel/rtlx-cmp.c +3 −0
  102. arch/mips/kernel/rtlx-mt.c +3 −0
  103. arch/mips/kernel/scall32-o32.S +2 −4
  104. arch/mips/kernel/scall64-64.S +2 −2
  105. arch/mips/kernel/scall64-n32.S +6 −6
  106. arch/mips/kernel/scall64-o32.S +4 −4
  107. arch/mips/kernel/setup.c +21 −1
  108. arch/mips/kernel/smp-cps.c +8 −4
  109. arch/mips/kernel/smp-mt.c +2 −0
  110. arch/mips/kernel/smp.c +25 −1
  111. arch/mips/kernel/traps.c +52 −9
  112. arch/mips/kernel/unaligned.c +0 −1
  113. arch/mips/loongson/Kconfig +5 −4
  114. arch/mips/loongson/Platform +1 −1
  115. arch/mips/loongson/common/env.c +48 −1
  116. arch/mips/loongson/common/init.c +4 −0
  117. arch/mips/loongson/common/pm.c +4 −4
  118. arch/mips/loongson/lemote-2f/clock.c +2 −2
  119. arch/mips/loongson/lemote-2f/reset.c +1 −1
  120. arch/mips/loongson/loongson-3/Makefile +3 −1
  121. arch/mips/loongson/loongson-3/cop2-ex.c +63 −0
  122. arch/mips/loongson/loongson-3/irq.c +20 −6
  123. arch/mips/loongson/loongson-3/numa.c +291 −0
  124. arch/mips/loongson/loongson-3/smp.c +292 −95
  125. arch/mips/loongson/loongson-3/smp.h +19 −18
  126. arch/mips/math-emu/cp1emu.c +1 −1
  127. arch/mips/mm/c-r4k.c +4 −4
  128. arch/mips/mm/init.c +33 −0
  129. arch/mips/mm/tlb-r3k.c +1 −1
  130. arch/mips/mm/tlb-r4k.c +59 −0
  131. arch/mips/mm/tlbex.c +96 −2
  132. arch/mips/mti-malta/malta-int.c +19 −8
  133. arch/mips/mti-malta/malta-memory.c +26 −0
  134. arch/mips/pci/Makefile +1 −1
  135. arch/mips/pci/ops-tx4927.c +0 −2
  136. arch/mips/pci/pci-alchemy.c +23 −1
  137. arch/mips/ralink/of.c +1 −1
  138. arch/mips/rb532/devices.c +5 −23
  139. arch/mips/sgi-ip22/ip22-gio.c +9 −1
  140. arch/mips/txx9/generic/7segled.c +11 −3
  141. arch/mips/txx9/generic/pci.c +2 −2
  142. arch/mips/txx9/generic/setup.c +19 −10
  143. drivers/cpufreq/loongson2_cpufreq.c +3 −3
  144. drivers/mmc/host/au1xmmc.c +107 −91
  145. drivers/mtd/nand/au1550nd.c +13 −16
  146. drivers/net/ethernet/amd/au1000_eth.c +137 −12
  147. drivers/net/irda/au1k_ir.c +46 −2
  148. drivers/rtc/rtc-au1xxx.c +8 −10
  149. drivers/spi/spi-au1550.c +33 −33
  150. drivers/video/fbdev/au1100fb.c +24 −15
  151. drivers/video/fbdev/au1100fb.h +1 −0
  152. drivers/video/fbdev/au1200fb.c +38 −43
  153. drivers/watchdog/octeon-wdt-main.c +34 −28
  154. sound/soc/au1x/psc-ac97.c +70 −70
  155. sound/soc/au1x/psc-i2s.c +50 −50
  156. sound/soc/au1x/psc.h +11 −11
Documentation/kernel-parameters.txt+6−0
@@ -571,6 +571,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted. · 570 unmodified lines
571571 trust validation.
572572 format: { id:<keyid> | builtin }
573573
574+ cca= [MIPS] Override the kernel pages' cache coherency
575+ algorithm. Accepted values range from 0 to 7
576+ inclusive. See arch/mips/include/asm/pgtable-bits.h
577+ for platform specific values (SB1, Loongson3 and
578+ others).
579+
574580 ccw_timeout_log [S390]
575581 See Documentation/s390/CommonIO for details.
576582
arch/mips/Kconfig+7−2
@@ -71,6 +71,7 @@ config MIPS_ALCHEMY · 70 unmodified lines
7171 select SYS_SUPPORTS_APM_EMULATION
7272 select ARCH_REQUIRE_GPIOLIB
7373 select SYS_SUPPORTS_ZBOOT
74+ select COMMON_CLK
7475
7576 config AR7
7677 bool "Texas Instruments AR7"
@@ -129,6 +130,8 @@ config BCM47XX · 52 unmodified lines
129130 select SYS_SUPPORTS_MIPS16
130131 select SYS_HAS_EARLY_PRINTK
131132 select USE_GENERIC_EARLY_PRINTK_8250
133+ select GPIOLIB
134+ select LEDS_GPIO_REGISTER
132135 help
133136 Support for BCM47XX based boards
134137
@@ -137,6 +140,7 @@ config BCM63XX · 2 unmodified lines
137140 select BOOT_RAW
138141 select CEVT_R4K
139142 select CSRC_R4K
143+ select SYNC_R4K
140144 select DMA_NONCOHERENT
141145 select IRQ_CPU
142146 select SYS_SUPPORTS_32BIT_KERNEL
@@ -2056,6 +2060,7 @@ config MIPS_CPS · 1913 unmodified lines
20562060 support is unavailable.
20572061
20582062 config MIPS_CPS_PM
2063+ select MIPS_CPC
20592064 bool
20602065
20612066 config MIPS_GIC_IPI
@@ -2109,9 +2114,9 @@ config CPU_MICROMIPS · 47 unmodified lines
21092114 microMIPS ISA
21102115
21112116 config CPU_HAS_MSA
2112− bool "Support for the MIPS SIMD Architecture"
2117+ bool "Support for the MIPS SIMD Architecture (EXPERIMENTAL)"
21132118 depends on CPU_SUPPORTS_MSA
2114− default y
2119+ depends on 64BIT || MIPS_O32_FP64_SUPPORT
21152120 help
21162121 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
21172122 and a set of SIMD instructions to operate on them. When this option
arch/mips/Makefile+3−1
@@ -151,8 +151,10 @@ cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=r5000) \ · 150 unmodified lines
151151 -Wa,--trap
152152 cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \
153153 -Wa,--trap
154−cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1 -mno-mdmx -mno-mips3d,-march=r5000) \
154+cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \
155155 -Wa,--trap
156+cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mdmx)
157+cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mips3d)
156158 cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap
157159 cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \
158160 -Wa,--trap
arch/mips/alchemy/board-mtx1.c+2−2
@@ -85,10 +85,10 @@ void __init board_setup(void) · 84 unmodified lines
8585 #endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
8686
8787 /* Initialize sys_pinfunc */
88− au_writel(SYS_PF_NI2, SYS_PINFUNC);
88+ alchemy_wrsys(SYS_PF_NI2, AU1000_SYS_PINFUNC);
8989
9090 /* Initialize GPIO */
91− au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR);
91+ alchemy_wrsys(~0, AU1000_SYS_TRIOUTCLR);
9292 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
9393 alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
9494 alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
arch/mips/alchemy/board-xxs1500.c+2−2
@@ -87,9 +87,9 @@ void __init board_setup(void) · 86 unmodified lines
8787 alchemy_gpio2_enable();
8888
8989 /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
90− pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
90+ pin_func = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PF_UR3;
9191 pin_func |= SYS_PF_UR3;
92− au_writel(pin_func, SYS_PINFUNC);
92+ alchemy_wrsys(pin_func, AU1000_SYS_PINFUNC);
9393
9494 /* Enable UART */
9595 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
arch/mips/alchemy/common/Makefile+2−2
@@ -5,8 +5,8 @@ · 4 unmodified lines
55 # Makefile for the Alchemy Au1xx0 CPUs, generic files.
66 #
77
8−obj-y += prom.o time.o clocks.o platform.o power.o setup.o \
9− sleeper.o dma.o dbdma.o vss.o irq.o usb.o
8+obj-y += prom.o time.o clock.o platform.o power.o \
9+ setup.o sleeper.o dma.o dbdma.o vss.o irq.o usb.o
1010
1111 # optional gpiolib support
1212 ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
arch/mips/alchemy/common/clock.c+1094−0
@@ -0,0 +1,1094 @@
1+/*
2+ * Alchemy clocks.
3+ *
4+ * Exposes all configurable internal clock sources to the clk framework.
5+ *
6+ * We have:
7+ * - Root source, usually 12MHz supplied by an external crystal
8+ * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
9+ *
10+ * Dividers:
11+ * - 6 clock dividers with:
12+ * * selectable source [one of the PLLs],
13+ * * output divided between [2 .. 512 in steps of 2] (!Au1300)
14+ * or [1 .. 256 in steps of 1] (Au1300),
15+ * * can be enabled individually.
16+ *
17+ * - up to 6 "internal" (fixed) consumers which:
18+ * * take either AUXPLL or one of the above 6 dividers as input,
19+ * * divide this input by 1, 2, or 4 (and 3 on Au1300).
20+ * * can be disabled separately.
21+ *
22+ * Misc clocks:
23+ * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
24+ * depends on board design and should be set by bootloader, read-only.
25+ * - peripheral clock: half the rate of sysbus clock, source for a lot
26+ * of peripheral blocks, read-only.
27+ * - memory clock: clk rate to main memory chips, depends on board
28+ * design and is read-only,
29+ * - lrclk: the static bus clock signal for synchronous operation.
30+ * depends on board design, must be set by bootloader,
31+ * but may be required to correctly configure devices attached to
32+ * the static bus. The Au1000/1500/1100 manuals call it LCLK, on
33+ * later models it's called RCLK.
34+ */
35+
36+#include <linux/init.h>
37+#include <linux/io.h>
38+#include <linux/clk-provider.h>
39+#include <linux/clkdev.h>
40+#include <linux/clk-private.h>
41+#include <linux/slab.h>
42+#include <linux/spinlock.h>
43+#include <linux/types.h>
44+#include <asm/mach-au1x00/au1000.h>
45+
46+/* Base clock: 12MHz is the default in all databooks, and I haven't
47+ * found any board yet which uses a different rate.
48+ */
49+#define ALCHEMY_ROOTCLK_RATE 12000000
50+
51+/*
52+ * the internal sources which can be driven by the PLLs and dividers.
53+ * Names taken from the databooks, refer to them for more information,
54+ * especially which ones are share a clock line.
55+ */
56+static const char * const alchemy_au1300_intclknames[] = {
57+ "lcd_intclk", "gpemgp_clk", "maempe_clk", "maebsa_clk",
58+ "EXTCLK0", "EXTCLK1"
59+};
60+
61+static const char * const alchemy_au1200_intclknames[] = {
62+ "lcd_intclk", NULL, NULL, NULL, "EXTCLK0", "EXTCLK1"
63+};
64+
65+static const char * const alchemy_au1550_intclknames[] = {
66+ "usb_clk", "psc0_intclk", "psc1_intclk", "pci_clko",
67+ "EXTCLK0", "EXTCLK1"
68+};
69+
70+static const char * const alchemy_au1100_intclknames[] = {
71+ "usb_clk", "lcd_intclk", NULL, "i2s_clk", "EXTCLK0", "EXTCLK1"
72+};
73+
74+static const char * const alchemy_au1500_intclknames[] = {
75+ NULL, "usbd_clk", "usbh_clk", "pci_clko", "EXTCLK0", "EXTCLK1"
76+};
77+
78+static const char * const alchemy_au1000_intclknames[] = {
79+ "irda_clk", "usbd_clk", "usbh_clk", "i2s_clk", "EXTCLK0",
80+ "EXTCLK1"
81+};
82+
83+/* aliases for a few on-chip sources which are either shared
84+ * or have gone through name changes.
85+ */
86+static struct clk_aliastable {
87+ char *alias;
88+ char *base;
89+ int cputype;
90+} alchemy_clk_aliases[] __initdata = {
91+ { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
92+ { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
93+ { "irda_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
94+ { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1550 },
95+ { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1550 },
96+ { "psc2_intclk", "usb_clk", ALCHEMY_CPU_AU1550 },
97+ { "psc3_intclk", "EXTCLK0", ALCHEMY_CPU_AU1550 },
98+ { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1200 },
99+ { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1200 },
100+ { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
101+ { "psc2_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
102+ { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
103+ { "psc3_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
104+
105+ { NULL, NULL, 0 },
106+};
107+
108+#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x))))
109+
110+/* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
111+static spinlock_t alchemy_clk_fg0_lock;
112+static spinlock_t alchemy_clk_fg1_lock;
113+static spinlock_t alchemy_clk_csrc_lock;
114+
115+/* CPU Core clock *****************************************************/
116+
117+static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
118+ unsigned long parent_rate)
119+{
120+ unsigned long t;
121+
122+ /*
123+ * On early Au1000, sys_cpupll was write-only. Since these
124+ * silicon versions of Au1000 are not sold, we don't bend
125+ * over backwards trying to determine the frequency.
126+ */
127+ if (unlikely(au1xxx_cpu_has_pll_wo()))
128+ t = 396000000;
129+ else {
130+ t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
131+ t *= parent_rate;
132+ }
133+
134+ return t;
135+}
136+
137+static struct clk_ops alchemy_clkops_cpu = {
138+ .recalc_rate = alchemy_clk_cpu_recalc,
139+};
140+
141+static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name,
142+ int ctype)
143+{
144+ struct clk_init_data id;
145+ struct clk_hw *h;
146+
147+ h = kzalloc(sizeof(*h), GFP_KERNEL);
148+ if (!h)
149+ return ERR_PTR(-ENOMEM);
150+
151+ id.name = ALCHEMY_CPU_CLK;
152+ id.parent_names = &parent_name;
153+ id.num_parents = 1;
154+ id.flags = CLK_IS_BASIC;
155+ id.ops = &alchemy_clkops_cpu;
156+ h->init = &id;
157+
158+ return clk_register(NULL, h);
159+}
160+
161+/* AUXPLLs ************************************************************/
162+
163+struct alchemy_auxpll_clk {
164+ struct clk_hw hw;
165+ unsigned long reg; /* au1300 has also AUXPLL2 */
166+ int maxmult; /* max multiplier */
167+};
168+#define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
169+
170+static unsigned long alchemy_clk_aux_recalc(struct clk_hw *hw,
171+ unsigned long parent_rate)
172+{
173+ struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
174+
175+ return (alchemy_rdsys(a->reg) & 0xff) * parent_rate;
176+}
177+
178+static int alchemy_clk_aux_setr(struct clk_hw *hw,
179+ unsigned long rate,
180+ unsigned long parent_rate)
181+{
182+ struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
183+ unsigned long d = rate;
184+
185+ if (rate)
186+ d /= parent_rate;
187+ else
188+ d = 0;
189+
190+ /* minimum is 84MHz, max is 756-1032 depending on variant */
191+ if (((d < 7) && (d != 0)) || (d > a->maxmult))
192+ return -EINVAL;
193+
194+ alchemy_wrsys(d, a->reg);
195+ return 0;
196+}
197+
198+static long alchemy_clk_aux_roundr(struct clk_hw *hw,
199+ unsigned long rate,
200+ unsigned long *parent_rate)
201+{
202+ struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
203+ unsigned long mult;
204+
205+ if (!rate || !*parent_rate)
206+ return 0;
207+
208+ mult = rate / (*parent_rate);
209+
210+ if (mult && (mult < 7))
211+ mult = 7;
212+ if (mult > a->maxmult)
213+ mult = a->maxmult;
214+
215+ return (*parent_rate) * mult;
216+}
217+
218+static struct clk_ops alchemy_clkops_aux = {
219+ .recalc_rate = alchemy_clk_aux_recalc,
220+ .set_rate = alchemy_clk_aux_setr,
221+ .round_rate = alchemy_clk_aux_roundr,
222+};
223+
224+static struct clk __init *alchemy_clk_setup_aux(const char *parent_name,
225+ char *name, int maxmult,
226+ unsigned long reg)
227+{
228+ struct clk_init_data id;
229+ struct clk *c;
230+ struct alchemy_auxpll_clk *a;
231+
232+ a = kzalloc(sizeof(*a), GFP_KERNEL);
233+ if (!a)
234+ return ERR_PTR(-ENOMEM);
235+
236+ id.name = name;
237+ id.parent_names = &parent_name;
238+ id.num_parents = 1;
239+ id.flags = CLK_GET_RATE_NOCACHE;
240+ id.ops = &alchemy_clkops_aux;
241+
242+ a->reg = reg;
243+ a->maxmult = maxmult;
244+ a->hw.init = &id;
245+
246+ c = clk_register(NULL, &a->hw);
247+ if (!IS_ERR(c))
248+ clk_register_clkdev(c, name, NULL);
249+ else
250+ kfree(a);
251+
252+ return c;
253+}
254+
255+/* sysbus_clk *********************************************************/
256+
257+static struct clk __init *alchemy_clk_setup_sysbus(const char *pn)
258+{
259+ unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2;
260+ struct clk *c;
261+
262+ c = clk_register_fixed_factor(NULL, ALCHEMY_SYSBUS_CLK,
263+ pn, 0, 1, v);
264+ if (!IS_ERR(c))
265+ clk_register_clkdev(c, ALCHEMY_SYSBUS_CLK, NULL);
266+ return c;
267+}
268+
269+/* Peripheral Clock ***************************************************/
270+
271+static struct clk __init *alchemy_clk_setup_periph(const char *pn)
272+{
273+ /* Peripheral clock runs at half the rate of sysbus clk */
274+ struct clk *c;
275+
276+ c = clk_register_fixed_factor(NULL, ALCHEMY_PERIPH_CLK,
277+ pn, 0, 1, 2);
278+ if (!IS_ERR(c))
279+ clk_register_clkdev(c, ALCHEMY_PERIPH_CLK, NULL);
280+ return c;
281+}
282+
283+/* mem clock **********************************************************/
284+
285+static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
286+{
287+ void __iomem *addr = IOMEM(AU1000_MEM_PHYS_ADDR);
288+ unsigned long v;
289+ struct clk *c;
290+ int div;
291+
292+ switch (ct) {
293+ case ALCHEMY_CPU_AU1550:
294+ case ALCHEMY_CPU_AU1200:
295+ v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
296+ div = (v & (1 << 15)) ? 1 : 2;
297+ break;
298+ case ALCHEMY_CPU_AU1300:
299+ v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
300+ div = (v & (1 << 31)) ? 1 : 2;
301+ break;
302+ case ALCHEMY_CPU_AU1000:
303+ case ALCHEMY_CPU_AU1500:
304+ case ALCHEMY_CPU_AU1100:
305+ default:
306+ div = 2;
307+ break;
308+ }
309+
310+ c = clk_register_fixed_factor(NULL, ALCHEMY_MEM_CLK, pn,
311+ 0, 1, div);
312+ if (!IS_ERR(c))
313+ clk_register_clkdev(c, ALCHEMY_MEM_CLK, NULL);
314+ return c;
315+}
316+
317+/* lrclk: external synchronous static bus clock ***********************/
318+
319+static struct clk __init *alchemy_clk_setup_lrclk(const char *pn)
320+{
321+ /* MEM_STCFG0[15:13] = divisor.
322+ * L/RCLK = periph_clk / (divisor + 1)
323+ * On Au1000, Au1500, Au1100 it's called LCLK,
324+ * on later models it's called RCLK, but it's the same thing.
325+ */
326+ struct clk *c;
327+ unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13;
328+
329+ v = (v & 7) + 1;
330+ c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
331+ pn, 0, 1, v);
332+ if (!IS_ERR(c))
333+ clk_register_clkdev(c, ALCHEMY_LR_CLK, NULL);
334+ return c;
335+}
336+
337+/* Clock dividers and muxes *******************************************/
338+
339+/* data for fgen and csrc mux-dividers */
340+struct alchemy_fgcs_clk {
341+ struct clk_hw hw;
342+ spinlock_t *reglock; /* register lock */
343+ unsigned long reg; /* SYS_FREQCTRL0/1 */
344+ int shift; /* offset in register */
345+ int parent; /* parent before disable [Au1300] */
346+ int isen; /* is it enabled? */
347+ int *dt; /* dividertable for csrc */
348+};
349+#define to_fgcs_clk(x) container_of(x, struct alchemy_fgcs_clk, hw)
350+
351+static long alchemy_calc_div(unsigned long rate, unsigned long prate,
352+ int scale, int maxdiv, unsigned long *rv)
353+{
354+ long div1, div2;
355+
356+ div1 = prate / rate;
357+ if ((prate / div1) > rate)
358+ div1++;
359+
360+ if (scale == 2) { /* only div-by-multiple-of-2 possible */
361+ if (div1 & 1)
362+ div1++; /* stay <=prate */
363+ }
364+
365+ div2 = (div1 / scale) - 1; /* value to write to register */
366+
367+ if (div2 > maxdiv)
368+ div2 = maxdiv;
369+ if (rv)
370+ *rv = div2;
371+
372+ div1 = ((div2 + 1) * scale);
373+ return div1;
374+}
375+
376+static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
377+ unsigned long *best_parent_rate,
378+ struct clk **best_parent_clk,
379+ int scale, int maxdiv)
380+{
381+ struct clk *pc, *bpc, *free;
382+ long tdv, tpr, pr, nr, br, bpr, diff, lastdiff;
383+ int j;
384+
385+ lastdiff = INT_MAX;
386+ bpr = 0;
387+ bpc = NULL;
388+ br = -EINVAL;
389+ free = NULL;
390+
391+ /* look at the rates each enabled parent supplies and select
392+ * the one that gets closest to but not over the requested rate.
393+ */
394+ for (j = 0; j < 7; j++) {
395+ pc = clk_get_parent_by_index(hw->clk, j);
396+ if (!pc)
397+ break;
398+
399+ /* if this parent is currently unused, remember it.
400+ * XXX: I know it's a layering violation, but it works
401+ * so well.. (if (!clk_has_active_children(pc)) )
402+ */
403+ if (pc->prepare_count == 0) {
404+ if (!free)
405+ free = pc;
406+ }
407+
408+ pr = clk_get_rate(pc);
409+ if (pr < rate)
410+ continue;
411+
412+ /* what can hardware actually provide */
413+ tdv = alchemy_calc_div(rate, pr, scale, maxdiv, NULL);
414+ nr = pr / tdv;
415+ diff = rate - nr;
416+ if (nr > rate)
417+ continue;
418+
419+ if (diff < lastdiff) {
420+ lastdiff = diff;
421+ bpr = pr;
422+ bpc = pc;
423+ br = nr;
424+ }
425+ if (diff == 0)
426+ break;
427+ }
428+
429+ /* if we couldn't get the exact rate we wanted from the enabled
430+ * parents, maybe we can tell an available disabled/inactive one
431+ * to give us a rate we can divide down to the requested rate.
432+ */
433+ if (lastdiff && free) {
434+ for (j = (maxdiv == 4) ? 1 : scale; j <= maxdiv; j += scale) {
435+ tpr = rate * j;
436+ if (tpr < 0)
437+ break;
438+ pr = clk_round_rate(free, tpr);
439+
440+ tdv = alchemy_calc_div(rate, pr, scale, maxdiv, NULL);
441+ nr = pr / tdv;
442+ diff = rate - nr;
443+ if (nr > rate)
444+ continue;
445+ if (diff < lastdiff) {
446+ lastdiff = diff;
447+ bpr = pr;
448+ bpc = free;
449+ br = nr;
450+ }
451+ if (diff == 0)
452+ break;
453+ }
454+ }
455+
456+ *best_parent_rate = bpr;
457+ *best_parent_clk = bpc;
458+ return br;
459+}
460+
461+static int alchemy_clk_fgv1_en(struct clk_hw *hw)
462+{
463+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
464+ unsigned long v, flags;
465+
466+ spin_lock_irqsave(c->reglock, flags);
467+ v = alchemy_rdsys(c->reg);
468+ v |= (1 << 1) << c->shift;
469+ alchemy_wrsys(v, c->reg);
470+ spin_unlock_irqrestore(c->reglock, flags);
471+
472+ return 0;
473+}
474+
475+static int alchemy_clk_fgv1_isen(struct clk_hw *hw)
476+{
477+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
478+ unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1);
479+
480+ return v & 1;
481+}
482+
483+static void alchemy_clk_fgv1_dis(struct clk_hw *hw)
484+{
485+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
486+ unsigned long v, flags;
487+
488+ spin_lock_irqsave(c->reglock, flags);
489+ v = alchemy_rdsys(c->reg);
490+ v &= ~((1 << 1) << c->shift);
491+ alchemy_wrsys(v, c->reg);
492+ spin_unlock_irqrestore(c->reglock, flags);
493+}
494+
495+static int alchemy_clk_fgv1_setp(struct clk_hw *hw, u8 index)
496+{
497+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
498+ unsigned long v, flags;
499+
500+ spin_lock_irqsave(c->reglock, flags);
501+ v = alchemy_rdsys(c->reg);
502+ if (index)
503+ v |= (1 << c->shift);
504+ else
505+ v &= ~(1 << c->shift);
506+ alchemy_wrsys(v, c->reg);
507+ spin_unlock_irqrestore(c->reglock, flags);
508+
509+ return 0;
510+}
511+
512+static u8 alchemy_clk_fgv1_getp(struct clk_hw *hw)
513+{
514+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
515+
516+ return (alchemy_rdsys(c->reg) >> c->shift) & 1;
517+}
518+
519+static int alchemy_clk_fgv1_setr(struct clk_hw *hw, unsigned long rate,
520+ unsigned long parent_rate)
521+{
522+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
523+ unsigned long div, v, flags, ret;
524+ int sh = c->shift + 2;
525+
526+ if (!rate || !parent_rate || rate > (parent_rate / 2))
527+ return -EINVAL;
528+ ret = alchemy_calc_div(rate, parent_rate, 2, 512, &div);
529+ spin_lock_irqsave(c->reglock, flags);
530+ v = alchemy_rdsys(c->reg);
531+ v &= ~(0xff << sh);
532+ v |= div << sh;
533+ alchemy_wrsys(v, c->reg);
534+ spin_unlock_irqrestore(c->reglock, flags);
535+
536+ return 0;
537+}
538+
539+static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw *hw,
540+ unsigned long parent_rate)
541+{
542+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
543+ unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2);
544+
545+ v = ((v & 0xff) + 1) * 2;
546+ return parent_rate / v;
547+}
548+
549+static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate,
550+ unsigned long *best_parent_rate,
551+ struct clk **best_parent_clk)
552+{
553+ return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
554+ best_parent_clk, 2, 512);
555+}
556+
557+/* Au1000, Au1100, Au15x0, Au12x0 */
558+static struct clk_ops alchemy_clkops_fgenv1 = {
559+ .recalc_rate = alchemy_clk_fgv1_recalc,
560+ .determine_rate = alchemy_clk_fgv1_detr,
561+ .set_rate = alchemy_clk_fgv1_setr,
562+ .set_parent = alchemy_clk_fgv1_setp,
563+ .get_parent = alchemy_clk_fgv1_getp,
564+ .enable = alchemy_clk_fgv1_en,
565+ .disable = alchemy_clk_fgv1_dis,
566+ .is_enabled = alchemy_clk_fgv1_isen,
567+};
568+
569+static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk *c)
570+{
571+ unsigned long v = alchemy_rdsys(c->reg);
572+
573+ v &= ~(3 << c->shift);
574+ v |= (c->parent & 3) << c->shift;
575+ alchemy_wrsys(v, c->reg);
576+ c->isen = 1;
577+}
578+
579+static int alchemy_clk_fgv2_en(struct clk_hw *hw)
580+{
581+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
582+ unsigned long flags;
583+
584+ /* enable by setting the previous parent clock */
585+ spin_lock_irqsave(c->reglock, flags);
586+ __alchemy_clk_fgv2_en(c);
587+ spin_unlock_irqrestore(c->reglock, flags);
588+
589+ return 0;
590+}
591+
592+static int alchemy_clk_fgv2_isen(struct clk_hw *hw)
593+{
594+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
595+
596+ return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0;
597+}
598+
599+static void alchemy_clk_fgv2_dis(struct clk_hw *hw)
600+{
601+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
602+ unsigned long v, flags;
603+
604+ spin_lock_irqsave(c->reglock, flags);
605+ v = alchemy_rdsys(c->reg);
606+ v &= ~(3 << c->shift); /* set input mux to "disabled" state */
607+ alchemy_wrsys(v, c->reg);
608+ c->isen = 0;
609+ spin_unlock_irqrestore(c->reglock, flags);
610+}
611+
612+static int alchemy_clk_fgv2_setp(struct clk_hw *hw, u8 index)
613+{
614+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
615+ unsigned long flags;
616+
617+ spin_lock_irqsave(c->reglock, flags);
618+ c->parent = index + 1; /* value to write to register */
619+ if (c->isen)
620+ __alchemy_clk_fgv2_en(c);
621+ spin_unlock_irqrestore(c->reglock, flags);
622+
623+ return 0;
624+}
625+
626+static u8 alchemy_clk_fgv2_getp(struct clk_hw *hw)
627+{
628+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
629+ unsigned long flags, v;
630+
631+ spin_lock_irqsave(c->reglock, flags);
632+ v = c->parent - 1;
633+ spin_unlock_irqrestore(c->reglock, flags);
634+ return v;
635+}
636+
637+/* fg0-2 and fg4-6 share a "scale"-bit. With this bit cleared, the
638+ * dividers behave exactly as on previous models (dividers are multiples
639+ * of 2); with the bit set, dividers are multiples of 1, halving their
640+ * range, but making them also much more flexible.
641+ */
642+static int alchemy_clk_fgv2_setr(struct clk_hw *hw, unsigned long rate,
643+ unsigned long parent_rate)
644+{
645+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
646+ int sh = c->shift + 2;
647+ unsigned long div, v, flags, ret;
648+
649+ if (!rate || !parent_rate || rate > parent_rate)
650+ return -EINVAL;
651+
652+ v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */
653+ ret = alchemy_calc_div(rate, parent_rate, v ? 1 : 2,
654+ v ? 256 : 512, &div);
655+
656+ spin_lock_irqsave(c->reglock, flags);
657+ v = alchemy_rdsys(c->reg);
658+ v &= ~(0xff << sh);
659+ v |= (div & 0xff) << sh;
660+ alchemy_wrsys(v, c->reg);
661+ spin_unlock_irqrestore(c->reglock, flags);
662+
663+ return 0;
664+}
665+
666+static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw *hw,
667+ unsigned long parent_rate)
668+{
669+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
670+ int sh = c->shift + 2;
671+ unsigned long v, t;
672+
673+ v = alchemy_rdsys(c->reg);
674+ t = parent_rate / (((v >> sh) & 0xff) + 1);
675+ if ((v & (1 << 30)) == 0) /* test scale bit */
676+ t /= 2;
677+
678+ return t;
679+}
680+
681+static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate,
682+ unsigned long *best_parent_rate,
683+ struct clk **best_parent_clk)
684+{
685+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
686+ int scale, maxdiv;
687+
688+ if (alchemy_rdsys(c->reg) & (1 << 30)) {
689+ scale = 1;
690+ maxdiv = 256;
691+ } else {
692+ scale = 2;
693+ maxdiv = 512;
694+ }
695+
696+ return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
697+ best_parent_clk, scale, maxdiv);
698+}
699+
700+/* Au1300 larger input mux, no separate disable bit, flexible divider */
701+static struct clk_ops alchemy_clkops_fgenv2 = {
702+ .recalc_rate = alchemy_clk_fgv2_recalc,
703+ .determine_rate = alchemy_clk_fgv2_detr,
704+ .set_rate = alchemy_clk_fgv2_setr,
705+ .set_parent = alchemy_clk_fgv2_setp,
706+ .get_parent = alchemy_clk_fgv2_getp,
707+ .enable = alchemy_clk_fgv2_en,
708+ .disable = alchemy_clk_fgv2_dis,
709+ .is_enabled = alchemy_clk_fgv2_isen,
710+};
711+
712+static const char * const alchemy_clk_fgv1_parents[] = {
713+ ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK
714+};
715+
716+static const char * const alchemy_clk_fgv2_parents[] = {
717+ ALCHEMY_AUXPLL2_CLK, ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK
718+};
719+
720+static const char * const alchemy_clk_fgen_names[] = {
721+ ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK,
722+ ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK };
723+
724+static int __init alchemy_clk_init_fgens(int ctype)
725+{
726+ struct clk *c;
727+ struct clk_init_data id;
728+ struct alchemy_fgcs_clk *a;
729+ unsigned long v;
730+ int i, ret;
731+
732+ switch (ctype) {
733+ case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
734+ id.ops = &alchemy_clkops_fgenv1;
735+ id.parent_names = (const char **)alchemy_clk_fgv1_parents;
736+ id.num_parents = 2;
737+ break;
738+ case ALCHEMY_CPU_AU1300:
739+ id.ops = &alchemy_clkops_fgenv2;
740+ id.parent_names = (const char **)alchemy_clk_fgv2_parents;
741+ id.num_parents = 3;
742+ break;
743+ default:
744+ return -ENODEV;
745+ }
746+ id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
747+
748+ a = kzalloc((sizeof(*a)) * 6, GFP_KERNEL);
749+ if (!a)
750+ return -ENOMEM;
751+
752+ spin_lock_init(&alchemy_clk_fg0_lock);
753+ spin_lock_init(&alchemy_clk_fg1_lock);
754+ ret = 0;
755+ for (i = 0; i < 6; i++) {
756+ id.name = alchemy_clk_fgen_names[i];
757+ a->shift = 10 * (i < 3 ? i : i - 3);
758+ if (i > 2) {
759+ a->reg = AU1000_SYS_FREQCTRL1;
760+ a->reglock = &alchemy_clk_fg1_lock;
761+ } else {
762+ a->reg = AU1000_SYS_FREQCTRL0;
763+ a->reglock = &alchemy_clk_fg0_lock;
764+ }
765+
766+ /* default to first parent if bootloader has set
767+ * the mux to disabled state.
768+ */
769+ if (ctype == ALCHEMY_CPU_AU1300) {
770+ v = alchemy_rdsys(a->reg);
771+ a->parent = (v >> a->shift) & 3;
772+ if (!a->parent) {
773+ a->parent = 1;
774+ a->isen = 0;
775+ } else
776+ a->isen = 1;
777+ }
778+
779+ a->hw.init = &id;
780+ c = clk_register(NULL, &a->hw);
781+ if (IS_ERR(c))
782+ ret++;
783+ else
784+ clk_register_clkdev(c, id.name, NULL);
785+ a++;
786+ }
787+
788+ return ret;
789+}
790+
791+/* internal sources muxes *********************************************/
792+
793+static int alchemy_clk_csrc_isen(struct clk_hw *hw)
794+{
795+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
796+ unsigned long v = alchemy_rdsys(c->reg);
797+
798+ return (((v >> c->shift) >> 2) & 7) != 0;
799+}
800+
801+static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk *c)
802+{
803+ unsigned long v = alchemy_rdsys(c->reg);
804+
805+ v &= ~((7 << 2) << c->shift);
806+ v |= ((c->parent & 7) << 2) << c->shift;
807+ alchemy_wrsys(v, c->reg);
808+ c->isen = 1;
809+}
810+
811+static int alchemy_clk_csrc_en(struct clk_hw *hw)
812+{
813+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
814+ unsigned long flags;
815+
816+ /* enable by setting the previous parent clock */
817+ spin_lock_irqsave(c->reglock, flags);
818+ __alchemy_clk_csrc_en(c);
819+ spin_unlock_irqrestore(c->reglock, flags);
820+
821+ return 0;
822+}
823+
824+static void alchemy_clk_csrc_dis(struct clk_hw *hw)
825+{
826+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
827+ unsigned long v, flags;
828+
829+ spin_lock_irqsave(c->reglock, flags);
830+ v = alchemy_rdsys(c->reg);
831+ v &= ~((3 << 2) << c->shift); /* mux to "disabled" state */
832+ alchemy_wrsys(v, c->reg);
833+ c->isen = 0;
834+ spin_unlock_irqrestore(c->reglock, flags);
835+}
836+
837+static int alchemy_clk_csrc_setp(struct clk_hw *hw, u8 index)
838+{
839+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
840+ unsigned long flags;
841+
842+ spin_lock_irqsave(c->reglock, flags);
843+ c->parent = index + 1; /* value to write to register */
844+ if (c->isen)
845+ __alchemy_clk_csrc_en(c);
846+ spin_unlock_irqrestore(c->reglock, flags);
847+
848+ return 0;
849+}
850+
851+static u8 alchemy_clk_csrc_getp(struct clk_hw *hw)
852+{
853+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
854+
855+ return c->parent - 1;
856+}
857+
858+static unsigned long alchemy_clk_csrc_recalc(struct clk_hw *hw,
859+ unsigned long parent_rate)
860+{
861+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
862+ unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3;
863+
864+ return parent_rate / c->dt[v];
865+}
866+
867+static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate,
868+ unsigned long parent_rate)
869+{
870+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
871+ unsigned long d, v, flags;
872+ int i;
873+
874+ if (!rate || !parent_rate || rate > parent_rate)
875+ return -EINVAL;
876+
877+ d = (parent_rate + (rate / 2)) / rate;
878+ if (d > 4)
879+ return -EINVAL;
880+ if ((d == 3) && (c->dt[2] != 3))
881+ d = 4;
882+
883+ for (i = 0; i < 4; i++)
884+ if (c->dt[i] == d)
885+ break;
886+
887+ if (i >= 4)
888+ return -EINVAL; /* oops */
889+
890+ spin_lock_irqsave(c->reglock, flags);
891+ v = alchemy_rdsys(c->reg);
892+ v &= ~(3 << c->shift);
893+ v |= (i & 3) << c->shift;
894+ alchemy_wrsys(v, c->reg);
895+ spin_unlock_irqrestore(c->reglock, flags);
896+
897+ return 0;
898+}
899+
900+static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate,
901+ unsigned long *best_parent_rate,
902+ struct clk **best_parent_clk)
903+{
904+ struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
905+ int scale = c->dt[2] == 3 ? 1 : 2; /* au1300 check */
906+
907+ return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
908+ best_parent_clk, scale, 4);
909+}
910+
911+static struct clk_ops alchemy_clkops_csrc = {
912+ .recalc_rate = alchemy_clk_csrc_recalc,
913+ .determine_rate = alchemy_clk_csrc_detr,
914+ .set_rate = alchemy_clk_csrc_setr,
915+ .set_parent = alchemy_clk_csrc_setp,
916+ .get_parent = alchemy_clk_csrc_getp,
917+ .enable = alchemy_clk_csrc_en,
918+ .disable = alchemy_clk_csrc_dis,
919+ .is_enabled = alchemy_clk_csrc_isen,
920+};
921+
922+static const char * const alchemy_clk_csrc_parents[] = {
923+ /* disabled at index 0 */ ALCHEMY_AUXPLL_CLK,
924+ ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK,
925+ ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK
926+};
927+
928+/* divider tables */
929+static int alchemy_csrc_dt1[] = { 1, 4, 1, 2 }; /* rest */
930+static int alchemy_csrc_dt2[] = { 1, 4, 3, 2 }; /* Au1300 */
931+
932+static int __init alchemy_clk_setup_imux(int ctype)
933+{
934+ struct alchemy_fgcs_clk *a;
935+ const char * const *names;
936+ struct clk_init_data id;
937+ unsigned long v;
938+ int i, ret, *dt;
939+ struct clk *c;
940+
941+ id.ops = &alchemy_clkops_csrc;
942+ id.parent_names = (const char **)alchemy_clk_csrc_parents;
943+ id.num_parents = 7;
944+ id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
945+
946+ dt = alchemy_csrc_dt1;
947+ switch (ctype) {
948+ case ALCHEMY_CPU_AU1000:
949+ names = alchemy_au1000_intclknames;
950+ break;
951+ case ALCHEMY_CPU_AU1500:
952+ names = alchemy_au1500_intclknames;
953+ break;
954+ case ALCHEMY_CPU_AU1100:
955+ names = alchemy_au1100_intclknames;
956+ break;
957+ case ALCHEMY_CPU_AU1550:
958+ names = alchemy_au1550_intclknames;
959+ break;
960+ case ALCHEMY_CPU_AU1200:
961+ names = alchemy_au1200_intclknames;
962+ break;
963+ case ALCHEMY_CPU_AU1300:
964+ dt = alchemy_csrc_dt2;
965+ names = alchemy_au1300_intclknames;
966+ break;
967+ default:
968+ return -ENODEV;
969+ }
970+
971+ a = kzalloc((sizeof(*a)) * 6, GFP_KERNEL);
972+ if (!a)
973+ return -ENOMEM;
974+
975+ spin_lock_init(&alchemy_clk_csrc_lock);
976+ ret = 0;
977+
978+ for (i = 0; i < 6; i++) {
979+ id.name = names[i];
980+ if (!id.name)
981+ goto next;
982+
983+ a->shift = i * 5;
984+ a->reg = AU1000_SYS_CLKSRC;
985+ a->reglock = &alchemy_clk_csrc_lock;
986+ a->dt = dt;
987+
988+ /* default to first parent clock if mux is initially
989+ * set to disabled state.
990+ */
991+ v = alchemy_rdsys(a->reg);
992+ a->parent = ((v >> a->shift) >> 2) & 7;
993+ if (!a->parent) {
994+ a->parent = 1;
995+ a->isen = 0;
996+ } else
997+ a->isen = 1;
998+
999+ a->hw.init = &id;
1000+ c = clk_register(NULL, &a->hw);
1001+ if (IS_ERR(c))
1002+ ret++;
1003+ else
1004+ clk_register_clkdev(c, id.name, NULL);
1005+next:
1006+ a++;
1007+ }
1008+
1009+ return ret;
1010+}
1011+
1012+
1013+/**********************************************************************/
1014+
1015+
1016+#define ERRCK(x) \
1017+ if (IS_ERR(x)) { \
1018+ ret = PTR_ERR(x); \
1019+ goto out; \
1020+ }
1021+
1022+static int __init alchemy_clk_init(void)
1023+{
1024+ int ctype = alchemy_get_cputype(), ret, i;
1025+ struct clk_aliastable *t = alchemy_clk_aliases;
1026+ struct clk *c;
1027+
1028+ /* Root of the Alchemy clock tree: external 12MHz crystal osc */
1029+ c = clk_register_fixed_rate(NULL, ALCHEMY_ROOT_CLK, NULL,
1030+ CLK_IS_ROOT,
1031+ ALCHEMY_ROOTCLK_RATE);
1032+ ERRCK(c)
1033+
1034+ /* CPU core clock */
1035+ c = alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK, ctype);
1036+ ERRCK(c)
1037+
1038+ /* AUXPLLs: max 1GHz on Au1300, 748MHz on older models */
1039+ i = (ctype == ALCHEMY_CPU_AU1300) ? 84 : 63;
1040+ c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK, ALCHEMY_AUXPLL_CLK,
1041+ i, AU1000_SYS_AUXPLL);
1042+ ERRCK(c)
1043+
1044+ if (ctype == ALCHEMY_CPU_AU1300) {
1045+ c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK,
1046+ ALCHEMY_AUXPLL2_CLK, i,
1047+ AU1300_SYS_AUXPLL2);
1048+ ERRCK(c)
1049+ }
1050+
1051+ /* sysbus clock: cpu core clock divided by 2, 3 or 4 */
1052+ c = alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK);
1053+ ERRCK(c)
1054+
1055+ /* peripheral clock: runs at half rate of sysbus clk */
1056+ c = alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK);
1057+ ERRCK(c)
1058+
1059+ /* SDR/DDR memory clock */
1060+ c = alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK, ctype);
1061+ ERRCK(c)
1062+
1063+ /* L/RCLK: external static bus clock for synchronous mode */
1064+ c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK);
1065+ ERRCK(c)
1066+
1067+ /* Frequency dividers 0-5 */
1068+ ret = alchemy_clk_init_fgens(ctype);
1069+ if (ret) {
1070+ ret = -ENODEV;
1071+ goto out;
1072+ }
1073+
1074+ /* diving muxes for internal sources */
1075+ ret = alchemy_clk_setup_imux(ctype);
1076+ if (ret) {
1077+ ret = -ENODEV;
1078+ goto out;
1079+ }
1080+
1081+ /* set up aliases drivers might look for */
1082+ while (t->base) {
1083+ if (t->cputype == ctype)
1084+ clk_add_alias(t->alias, NULL, t->base, NULL);
1085+ t++;
1086+ }
1087+
1088+ pr_info("Alchemy clocktree installed\n");
1089+ return 0;
1090+
1091+out:
1092+ return ret;
1093+}
1094+postcore_initcall(alchemy_clk_init);
arch/mips/alchemy/common/clocks.c+0−105
@@ -1,105 +0,0 @@
1−/*
2− * BRIEF MODULE DESCRIPTION
3− * Simple Au1xx0 clocks routines.
4− *
5− * Copyright 2001, 2008 MontaVista Software Inc.
6− * Author: MontaVista Software, Inc. <source@mvista.com>
7− *
8− * This program is free software; you can redistribute it and/or modify it
9− * under the terms of the GNU General Public License as published by the
10− * Free Software Foundation; either version 2 of the License, or (at your
11− * option) any later version.
12− *
13− * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14− * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15− * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16− * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17− * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18− * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19− * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20− * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21− * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22− * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23− *
24− * You should have received a copy of the GNU General Public License along
25− * with this program; if not, write to the Free Software Foundation, Inc.,
26− * 675 Mass Ave, Cambridge, MA 02139, USA.
27− */
28−
29−#include <linux/module.h>
30−#include <linux/spinlock.h>
31−#include <asm/time.h>
32−#include <asm/mach-au1x00/au1000.h>
33−
34−/*
35− * I haven't found anyone that doesn't use a 12 MHz source clock,
36− * but just in case.....
37− */
38−#define AU1000_SRC_CLK 12000000
39−
40−static unsigned int au1x00_clock; /* Hz */
41−static unsigned long uart_baud_base;
42−
43−/*
44− * Set the au1000_clock
45− */
46−void set_au1x00_speed(unsigned int new_freq)
47−{
48− au1x00_clock = new_freq;
49−}
50−
51−unsigned int get_au1x00_speed(void)
52−{
53− return au1x00_clock;
54−}
55−EXPORT_SYMBOL(get_au1x00_speed);
56−
57−/*
58− * The UART baud base is not known at compile time ... if
59− * we want to be able to use the same code on different
60− * speed CPUs.
61− */
62−unsigned long get_au1x00_uart_baud_base(void)
63−{
64− return uart_baud_base;
65−}
66−
67−void set_au1x00_uart_baud_base(unsigned long new_baud_base)
68−{
69− uart_baud_base = new_baud_base;
70−}
71−
72−/*
73− * We read the real processor speed from the PLL. This is important
74− * because it is more accurate than computing it from the 32 KHz
75− * counter, if it exists. If we don't have an accurate processor
76− * speed, all of the peripherals that derive their clocks based on
77− * this advertised speed will introduce error and sometimes not work
78− * properly. This function is further convoluted to still allow configurations
79− * to do that in case they have really, really old silicon with a
80− * write-only PLL register. -- Dan
81− */
82−unsigned long au1xxx_calc_clock(void)
83−{
84− unsigned long cpu_speed;
85−
86− /*
87− * On early Au1000, sys_cpupll was write-only. Since these
88− * silicon versions of Au1000 are not sold by AMD, we don't bend
89− * over backwards trying to determine the frequency.
90− */
91− if (au1xxx_cpu_has_pll_wo())
92− cpu_speed = 396000000;
93− else
94− cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
95−
96− /* On Alchemy CPU:counter ratio is 1:1 */
97− mips_hpt_frequency = cpu_speed;
98− /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
99− set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
100− & 0x03) + 2) * 16));
101−
102− set_au1x00_speed(cpu_speed);
103−
104− return cpu_speed;
105−}
arch/mips/alchemy/common/dbdma.c+11−11
@@ -341,7 +341,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, · 340 unmodified lines
341341 (dtp->dev_flags & DEV_FLAGS_SYNC))
342342 i |= DDMA_CFG_SYNC;
343343 cp->ddma_cfg = i;
344− au_sync();
344+ wmb(); /* drain writebuffer */
345345
346346 /*
347347 * Return a non-zero value that can be used to find the channel
@@ -631,7 +631,7 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) · 283 unmodified lines
631631 */
632632 dma_cache_wback_inv((unsigned long)buf, nbytes);
633633 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
634− au_sync();
634+ wmb(); /* drain writebuffer */
635635 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
636636 ctp->chan_ptr->ddma_dbell = 0;
637637
@@ -693,7 +693,7 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) · 55 unmodified lines
693693 */
694694 dma_cache_inv((unsigned long)buf, nbytes);
695695 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
696− au_sync();
696+ wmb(); /* drain writebuffer */
697697 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
698698 ctp->chan_ptr->ddma_dbell = 0;
699699
@@ -760,7 +760,7 @@ void au1xxx_dbdma_stop(u32 chanid) · 60 unmodified lines
760760
761761 cp = ctp->chan_ptr;
762762 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
763− au_sync();
763+ wmb(); /* drain writebuffer */
764764 while (!(cp->ddma_stat & DDMA_STAT_H)) {
765765 udelay(1);
766766 halt_timeout++;
@@ -771,7 +771,7 @@ void au1xxx_dbdma_stop(u32 chanid) · 4 unmodified lines
771771 }
772772 /* clear current desc valid and doorbell */
773773 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
774− au_sync();
774+ wmb(); /* drain writebuffer */
775775 }
776776 EXPORT_SYMBOL(au1xxx_dbdma_stop);
777777
@@ -789,9 +789,9 @@ void au1xxx_dbdma_start(u32 chanid) · 11 unmodified lines
789789 cp = ctp->chan_ptr;
790790 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
791791 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
792− au_sync();
792+ wmb(); /* drain writebuffer */
793793 cp->ddma_dbell = 0;
794− au_sync();
794+ wmb(); /* drain writebuffer */
795795 }
796796 EXPORT_SYMBOL(au1xxx_dbdma_start);
797797
@@ -832,7 +832,7 @@ u32 au1xxx_get_dma_residue(u32 chanid) · 34 unmodified lines
832832
833833 /* This is only valid if the channel is stopped. */
834834 rv = cp->ddma_bytecnt;
835− au_sync();
835+ wmb(); /* drain writebuffer */
836836
837837 return rv;
838838 }
@@ -868,7 +868,7 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id) · 29 unmodified lines
868868 au1x_dma_chan_t *cp;
869869
870870 intstat = dbdma_gptr->ddma_intstat;
871− au_sync();
871+ wmb(); /* drain writebuffer */
872872 chan_index = __ffs(intstat);
873873
874874 ctp = chan_tab_ptr[chan_index];
@@ -877,7 +877,7 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id) · 2 unmodified lines
877877
878878 /* Reset interrupt. */
879879 cp->ddma_irq = 0;
880− au_sync();
880+ wmb(); /* drain writebuffer */
881881
882882 if (ctp->chan_callback)
883883 ctp->chan_callback(irq, ctp->chan_callparam);
@@ -1061,7 +1061,7 @@ static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable) · 177 unmodified lines
10611061 dbdma_gptr->ddma_config = 0;
10621062 dbdma_gptr->ddma_throttle = 0;
10631063 dbdma_gptr->ddma_inten = 0xffff;
1064− au_sync();
1064+ wmb(); /* drain writebuffer */
10651065
10661066 ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr);
10671067 if (ret)
arch/mips/alchemy/common/dma.c+8−7
@@ -141,17 +141,17 @@ void dump_au1000_dma_channel(unsigned int dmanr) · 140 unmodified lines
141141
142142 printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
143143 printk(KERN_INFO " mode = 0x%08x\n",
144− au_readl(chan->io + DMA_MODE_SET));
144+ __raw_readl(chan->io + DMA_MODE_SET));
145145 printk(KERN_INFO " addr = 0x%08x\n",
146− au_readl(chan->io + DMA_PERIPHERAL_ADDR));
146+ __raw_readl(chan->io + DMA_PERIPHERAL_ADDR));
147147 printk(KERN_INFO " start0 = 0x%08x\n",
148− au_readl(chan->io + DMA_BUFFER0_START));
148+ __raw_readl(chan->io + DMA_BUFFER0_START));
149149 printk(KERN_INFO " start1 = 0x%08x\n",
150− au_readl(chan->io + DMA_BUFFER1_START));
150+ __raw_readl(chan->io + DMA_BUFFER1_START));
151151 printk(KERN_INFO " count0 = 0x%08x\n",
152− au_readl(chan->io + DMA_BUFFER0_COUNT));
152+ __raw_readl(chan->io + DMA_BUFFER0_COUNT));
153153 printk(KERN_INFO " count1 = 0x%08x\n",
154− au_readl(chan->io + DMA_BUFFER1_COUNT));
154+ __raw_readl(chan->io + DMA_BUFFER1_COUNT));
155155 }
156156
157157 /*
@@ -204,7 +204,8 @@ int request_au1000_dma(int dev_id, const char *dev_str, · 46 unmodified lines
204204 }
205205
206206 /* fill it in */
207− chan->io = KSEG1ADDR(AU1000_DMA_PHYS_ADDR) + i * DMA_CHANNEL_LEN;
207+ chan->io = (void __iomem *)(KSEG1ADDR(AU1000_DMA_PHYS_ADDR) +
208+ i * DMA_CHANNEL_LEN);
208209 chan->dev_id = dev_id;
209210 chan->dev_str = dev_str;
210211 chan->fifo_addr = dev->fifo_addr;
arch/mips/alchemy/common/irq.c+2−3
@@ -389,13 +389,12 @@ static int au1x_ic1_setwake(struct irq_data *d, unsigned int on) · 388 unmodified lines
389389 return -EINVAL;
390390
391391 local_irq_save(flags);
392− wakemsk = __raw_readl((void __iomem *)SYS_WAKEMSK);
392+ wakemsk = alchemy_rdsys(AU1000_SYS_WAKEMSK);
393393 if (on)
394394 wakemsk |= 1 << bit;
395395 else
396396 wakemsk &= ~(1 << bit);
397− __raw_writel(wakemsk, (void __iomem *)SYS_WAKEMSK);
398− wmb();
397+ alchemy_wrsys(wakemsk, AU1000_SYS_WAKEMSK);
399398 local_irq_restore(flags);
400399
401400 return 0;
arch/mips/alchemy/common/platform.c+13−2
@@ -11,6 +11,7 @@ · 10 unmodified lines
1111 * warranty of any kind, whether express or implied.
1212 */
1313
14+#include <linux/clk.h>
1415 #include <linux/dma-mapping.h>
1516 #include <linux/etherdevice.h>
1617 #include <linux/init.h>
@@ -99,10 +100,20 @@ static struct platform_device au1xx0_uart_device = { · 82 unmodified lines
99100
100101 static void __init alchemy_setup_uarts(int ctype)
101102 {
102− unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
103+ long uartclk;
103104 int s = sizeof(struct plat_serial8250_port);
104105 int c = alchemy_get_uarts(ctype);
105106 struct plat_serial8250_port *ports;
107+ struct clk *clk = clk_get(NULL, ALCHEMY_PERIPH_CLK);
108+
109+ if (IS_ERR(clk))
110+ return;
111+ if (clk_prepare_enable(clk)) {
112+ clk_put(clk);
113+ return;
114+ }
115+ uartclk = clk_get_rate(clk);
116+ clk_put(clk);
106117
107118 ports = kzalloc(s * (c + 1), GFP_KERNEL);
108119 if (!ports) {
@@ -420,7 +431,7 @@ static void __init alchemy_setup_macs(int ctype) · 311 unmodified lines
420431 memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
421432
422433 /* Register second MAC if enabled in pinfunc */
423− if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) {
434+ if (!(alchemy_rdsys(AU1000_SYS_PINFUNC) & SYS_PF_NI2)) {
424435 ret = platform_device_register(&au1xxx_eth1_device);
425436 if (ret)
426437 printk(KERN_INFO "Alchemy: failed to register MAC1\n");
arch/mips/alchemy/common/power.c+36−38
@@ -54,28 +54,28 @@ static unsigned int sleep_static_memctlr[4][3]; · 53 unmodified lines
5454 static void save_core_regs(void)
5555 {
5656 /* Clocks and PLLs. */
57− sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
58− sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
59− sleep_sys_clocks[2] = au_readl(SYS_CLKSRC);
60− sleep_sys_clocks[3] = au_readl(SYS_CPUPLL);
61− sleep_sys_clocks[4] = au_readl(SYS_AUXPLL);
57+ sleep_sys_clocks[0] = alchemy_rdsys(AU1000_SYS_FREQCTRL0);
58+ sleep_sys_clocks[1] = alchemy_rdsys(AU1000_SYS_FREQCTRL1);
59+ sleep_sys_clocks[2] = alchemy_rdsys(AU1000_SYS_CLKSRC);
60+ sleep_sys_clocks[3] = alchemy_rdsys(AU1000_SYS_CPUPLL);
61+ sleep_sys_clocks[4] = alchemy_rdsys(AU1000_SYS_AUXPLL);
6262
6363 /* pin mux config */
64− sleep_sys_pinfunc = au_readl(SYS_PINFUNC);
64+ sleep_sys_pinfunc = alchemy_rdsys(AU1000_SYS_PINFUNC);
6565
6666 /* Save the static memory controller configuration. */
67− sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
68− sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
69− sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
70− sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1);
71− sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1);
72− sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1);
73− sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2);
74− sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2);
75− sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2);
76− sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
77− sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
78− sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
67+ sleep_static_memctlr[0][0] = alchemy_rdsmem(AU1000_MEM_STCFG0);
68+ sleep_static_memctlr[0][1] = alchemy_rdsmem(AU1000_MEM_STTIME0);
69+ sleep_static_memctlr[0][2] = alchemy_rdsmem(AU1000_MEM_STADDR0);
70+ sleep_static_memctlr[1][0] = alchemy_rdsmem(AU1000_MEM_STCFG1);
71+ sleep_static_memctlr[1][1] = alchemy_rdsmem(AU1000_MEM_STTIME1);
72+ sleep_static_memctlr[1][2] = alchemy_rdsmem(AU1000_MEM_STADDR1);
73+ sleep_static_memctlr[2][0] = alchemy_rdsmem(AU1000_MEM_STCFG2);
74+ sleep_static_memctlr[2][1] = alchemy_rdsmem(AU1000_MEM_STTIME2);
75+ sleep_static_memctlr[2][2] = alchemy_rdsmem(AU1000_MEM_STADDR2);
76+ sleep_static_memctlr[3][0] = alchemy_rdsmem(AU1000_MEM_STCFG3);
77+ sleep_static_memctlr[3][1] = alchemy_rdsmem(AU1000_MEM_STTIME3);
78+ sleep_static_memctlr[3][2] = alchemy_rdsmem(AU1000_MEM_STADDR3);
7979 }
8080
8181 static void restore_core_regs(void)
@@ -85,30 +85,28 @@ static void restore_core_regs(void) · 3 unmodified lines
8585 * one of those Au1000 with a write-only PLL, where we dont
8686 * have a valid value)
8787 */
88− au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0);
89− au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1);
90− au_writel(sleep_sys_clocks[2], SYS_CLKSRC);
91− au_writel(sleep_sys_clocks[4], SYS_AUXPLL);
88+ alchemy_wrsys(sleep_sys_clocks[0], AU1000_SYS_FREQCTRL0);
89+ alchemy_wrsys(sleep_sys_clocks[1], AU1000_SYS_FREQCTRL1);
90+ alchemy_wrsys(sleep_sys_clocks[2], AU1000_SYS_CLKSRC);
91+ alchemy_wrsys(sleep_sys_clocks[4], AU1000_SYS_AUXPLL);
9292 if (!au1xxx_cpu_has_pll_wo())
93− au_writel(sleep_sys_clocks[3], SYS_CPUPLL);
94− au_sync();
93+ alchemy_wrsys(sleep_sys_clocks[3], AU1000_SYS_CPUPLL);
9594
96− au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
97− au_sync();
95+ alchemy_wrsys(sleep_sys_pinfunc, AU1000_SYS_PINFUNC);
9896
9997 /* Restore the static memory controller configuration. */
100− au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
101− au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
102− au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
103− au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
104− au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
105− au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
106− au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
107− au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
108− au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
109− au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
110− au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
111− au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
98+ alchemy_wrsmem(sleep_static_memctlr[0][0], AU1000_MEM_STCFG0);
99+ alchemy_wrsmem(sleep_static_memctlr[0][1], AU1000_MEM_STTIME0);
100+ alchemy_wrsmem(sleep_static_memctlr[0][2], AU1000_MEM_STADDR0);
101+ alchemy_wrsmem(sleep_static_memctlr[1][0], AU1000_MEM_STCFG1);
102+ alchemy_wrsmem(sleep_static_memctlr[1][1], AU1000_MEM_STTIME1);
103+ alchemy_wrsmem(sleep_static_memctlr[1][2], AU1000_MEM_STADDR1);
104+ alchemy_wrsmem(sleep_static_memctlr[2][0], AU1000_MEM_STCFG2);
105+ alchemy_wrsmem(sleep_static_memctlr[2][1], AU1000_MEM_STTIME2);
106+ alchemy_wrsmem(sleep_static_memctlr[2][2], AU1000_MEM_STADDR2);
107+ alchemy_wrsmem(sleep_static_memctlr[3][0], AU1000_MEM_STCFG3);
108+ alchemy_wrsmem(sleep_static_memctlr[3][1], AU1000_MEM_STTIME3);
109+ alchemy_wrsmem(sleep_static_memctlr[3][2], AU1000_MEM_STADDR3);
112110 }
113111
114112 void au_sleep(void)
arch/mips/alchemy/common/setup.c+0−15
@@ -27,12 +27,9 @@ · 26 unmodified lines
2727
2828 #include <linux/init.h>
2929 #include <linux/ioport.h>
30−#include <linux/jiffies.h>
31−#include <linux/module.h>
3230
3331 #include <asm/dma-coherence.h>
3432 #include <asm/mipsregs.h>
35−#include <asm/time.h>
3633
3734 #include <au1000.h>
3835
@@ -41,18 +38,6 @@ extern void set_cpuspec(void); · 2 unmodified lines
4138
4239 void __init plat_mem_setup(void)
4340 {
44− unsigned long est_freq;
45−
46− /* determine core clock */
47− est_freq = au1xxx_calc_clock();
48− est_freq += 5000; /* round */
49− est_freq -= est_freq % 10000;
50− printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(),
51− est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);
52−
53− /* this is faster than wasting cycles trying to approximate it */
54− preset_lpj = (est_freq >> 1) / HZ;
55−
5641 if (au1xxx_cpu_needs_config_od())
5742 /* Various early Au1xx0 errata corrected by this */
5843 set_c0_config(1 << 19); /* Set Config[OD] */
arch/mips/alchemy/common/time.c+10−13
@@ -46,7 +46,7 @@ · 45 unmodified lines
4646
4747 static cycle_t au1x_counter1_read(struct clocksource *cs)
4848 {
49− return au_readl(SYS_RTCREAD);
49+ return alchemy_rdsys(AU1000_SYS_RTCREAD);
5050 }
5151
5252 static struct clocksource au1x_counter1_clocksource = {
@@ -60,12 +60,11 @@ static struct clocksource au1x_counter1_clocksource = { · 7 unmodified lines
6060 static int au1x_rtcmatch2_set_next_event(unsigned long delta,
6161 struct clock_event_device *cd)
6262 {
63− delta += au_readl(SYS_RTCREAD);
63+ delta += alchemy_rdsys(AU1000_SYS_RTCREAD);
6464 /* wait for register access */
65− while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21)
65+ while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_M21)
6666 ;
67− au_writel(delta, SYS_RTCMATCH2);
68− au_sync();
67+ alchemy_wrsys(delta, AU1000_SYS_RTCMATCH2);
6968
7069 return 0;
7170 }
@@ -112,31 +111,29 @@ static int __init alchemy_time_init(unsigned int m2int) · 40 unmodified lines
112111 * (the 32S bit seems to be stuck set to 1 once a single clock-
113112 * edge is detected, hence the timeouts).
114113 */
115− if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK))
114+ if (CNTR_OK != (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & CNTR_OK))
116115 goto cntr_err;
117116
118117 /*
119118 * setup counter 1 (RTC) to tick at full speed
120119 */
121120 t = 0xffffff;
122− while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && --t)
121+ while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T1S) && --t)
123122 asm volatile ("nop");
124123 if (!t)
125124 goto cntr_err;
126125
127− au_writel(0, SYS_RTCTRIM); /* 32.768 kHz */
128− au_sync();
126+ alchemy_wrsys(0, AU1000_SYS_RTCTRIM); /* 32.768 kHz */
129127
130128 t = 0xffffff;
131− while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
129+ while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
132130 asm volatile ("nop");
133131 if (!t)
134132 goto cntr_err;
135− au_writel(0, SYS_RTCWRITE);
136− au_sync();
133+ alchemy_wrsys(0, AU1000_SYS_RTCWRITE);
137134
138135 t = 0xffffff;
139− while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
136+ while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
140137 asm volatile ("nop");
141138 if (!t)
142139 goto cntr_err;
arch/mips/alchemy/common/usb.c+40−7
@@ -9,6 +9,7 @@ · 8 unmodified lines
99 *
1010 */
1111
12+#include <linux/clk.h>
1213 #include <linux/init.h>
1314 #include <linux/io.h>
1415 #include <linux/module.h>
@@ -387,10 +388,25 @@ static inline void au1200_usb_init(void) · 372 unmodified lines
387388 udelay(1000);
388389 }
389390
390−static inline void au1000_usb_init(unsigned long rb, int reg)
391+static inline int au1000_usb_init(unsigned long rb, int reg)
391392 {
392393 void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
393394 unsigned long r = __raw_readl(base);
395+ struct clk *c;
396+
397+ /* 48MHz check. Don't init if no one can provide it */
398+ c = clk_get(NULL, "usbh_clk");
399+ if (IS_ERR(c))
400+ return -ENODEV;
401+ if (clk_round_rate(c, 48000000) != 48000000) {
402+ clk_put(c);
403+ return -ENODEV;
404+ }
405+ if (clk_set_rate(c, 48000000)) {
406+ clk_put(c);
407+ return -ENODEV;
408+ }
409+ clk_put(c);
394410
395411 #if defined(__BIG_ENDIAN)
396412 r |= USBHEN_BE;
@@ -400,6 +416,8 @@ static inline void au1000_usb_init(unsigned long rb, int reg) · 3 unmodified lines
400416 __raw_writel(r, base);
401417 wmb();
402418 udelay(1000);
419+
420+ return 0;
403421 }
404422
405423
@@ -407,8 +425,15 @@ static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg) · 1 unmodified line
407425 {
408426 void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
409427 unsigned long r = __raw_readl(base + creg);
428+ struct clk *c = clk_get(NULL, "usbh_clk");
429+
430+ if (IS_ERR(c))
431+ return;
410432
411433 if (enable) {
434+ if (clk_prepare_enable(c))
435+ goto out;
436+
412437 __raw_writel(r | USBHEN_CE, base + creg);
413438 wmb();
414439 udelay(1000);
@@ -423,7 +448,10 @@ static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg) · 8 unmodified lines
423448 } else {
424449 __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
425450 wmb();
451+ clk_disable_unprepare(c);
426452 }
453+out:
454+ clk_put(c);
427455 }
428456
429457 static inline int au1000_usb_control(int block, int enable, unsigned long rb,
@@ -457,11 +485,11 @@ int alchemy_usb_control(int block, int enable) · 27 unmodified lines
457485 case ALCHEMY_CPU_AU1500:
458486 case ALCHEMY_CPU_AU1100:
459487 ret = au1000_usb_control(block, enable,
460− AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
488+ AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
461489 break;
462490 case ALCHEMY_CPU_AU1550:
463491 ret = au1000_usb_control(block, enable,
464− AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
492+ AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
465493 break;
466494 case ALCHEMY_CPU_AU1200:
467495 ret = au1200_usb_control(block, enable);
@@ -569,14 +597,18 @@ static struct syscore_ops alchemy_usb_pm_ops = { · 101 unmodified lines
569597
570598 static int __init alchemy_usb_init(void)
571599 {
600+ int ret = 0;
601+
572602 switch (alchemy_get_cputype()) {
573603 case ALCHEMY_CPU_AU1000:
574604 case ALCHEMY_CPU_AU1500:
575605 case ALCHEMY_CPU_AU1100:
576− au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
606+ ret = au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR,
607+ AU1000_OHCICFG);
577608 break;
578609 case ALCHEMY_CPU_AU1550:
579− au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
610+ ret = au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR,
611+ AU1550_OHCICFG);
580612 break;
581613 case ALCHEMY_CPU_AU1200:
582614 au1200_usb_init();
@@ -586,8 +618,9 @@ static int __init alchemy_usb_init(void) · 3 unmodified lines
586618 break;
587619 }
588620
589− register_syscore_ops(&alchemy_usb_pm_ops);
621+ if (!ret)
622+ register_syscore_ops(&alchemy_usb_pm_ops);
590623
591− return 0;
624+ return ret;
592625 }
593626 arch_initcall(alchemy_usb_init);
arch/mips/alchemy/devboards/db1000.c+16−3
@@ -19,6 +19,7 @@ · 18 unmodified lines
1919 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
2020 */
2121
22+#include <linux/clk.h>
2223 #include <linux/dma-mapping.h>
2324 #include <linux/gpio.h>
2425 #include <linux/init.h>
@@ -496,6 +497,7 @@ int __init db1000_dev_setup(void) · 471 unmodified lines
496497 int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
497498 int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1;
498499 unsigned long pfc;
500+ struct clk *c, *p;
499501
500502 if (board == BCSR_WHOAMI_DB1500) {
501503 c0 = AU1500_GPIO2_INT;
@@ -518,14 +520,25 @@ int __init db1000_dev_setup(void) · 16 unmodified lines
518520 gpio_direction_input(20); /* sd1 cd# */
519521
520522 /* spi_gpio on SSI0 pins */
521− pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
523+ pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
522524 pfc |= (1 << 0); /* SSI0 pins as GPIOs */
523− __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
524− wmb();
525+ alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
525526
526527 spi_register_board_info(db1100_spi_info,
527528 ARRAY_SIZE(db1100_spi_info));
528529
530+ /* link LCD clock to AUXPLL */
531+ p = clk_get(NULL, "auxpll_clk");
532+ c = clk_get(NULL, "lcd_intclk");
533+ if (!IS_ERR(c) && !IS_ERR(p)) {
534+ clk_set_parent(c, p);
535+ clk_set_rate(c, clk_get_rate(p));
536+ }
537+ if (!IS_ERR(c))
538+ clk_put(c);
539+ if (!IS_ERR(p))
540+ clk_put(p);
541+
529542 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
530543 platform_device_register(&db1100_spi_dev);
531544 } else if (board == BCSR_WHOAMI_DB1000) {
arch/mips/alchemy/devboards/db1200.c+28−33
@@ -18,6 +18,7 @@ · 17 unmodified lines
1818 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
1919 */
2020
21+#include <linux/clk.h>
2122 #include <linux/dma-mapping.h>
2223 #include <linux/gpio.h>
2324 #include <linux/i2c.h>
@@ -129,7 +130,6 @@ static int __init db1200_detect_board(void) · 105 unmodified lines
129130
130131 int __init db1200_board_setup(void)
131132 {
132− unsigned long freq0, clksrc, div, pfc;
133133 unsigned short whoami;
134134
135135 if (db1200_detect_board())
@@ -149,34 +149,6 @@ int __init db1200_board_setup(void) · 13 unmodified lines
149149 " Board-ID %d Daughtercard ID %d\n", get_system_type(),
150150 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
151151
152− /* SMBus/SPI on PSC0, Audio on PSC1 */
153− pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
154− pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
155− pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
156− pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
157− __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
158− wmb();
159−
160− /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
161− * CPU clock; all other clock generators off/unused.
162− */
163− div = (get_au1x00_speed() + 25000000) / 50000000;
164− if (div & 1)
165− div++;
166− div = ((div >> 1) - 1) & 0xff;
167−
168− freq0 = div << SYS_FC_FRDIV0_BIT;
169− __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
170− wmb();
171− freq0 |= SYS_FC_FE0; /* enable F0 */
172− __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
173− wmb();
174−
175− /* psc0_intclk comes 1:1 from F0 */
176− clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
177− __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
178− wmb();
179−
180152 return 0;
181153 }
182154
@@ -250,7 +222,7 @@ static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, · 67 unmodified lines
250222
251223 static int au1200_nand_device_ready(struct mtd_info *mtd)
252224 {
253− return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
225+ return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
254226 }
255227
256228 static struct mtd_partition db1200_nand_parts[] = {
@@ -847,6 +819,7 @@ int __init db1200_dev_setup(void) · 590 unmodified lines
847819 unsigned long pfc;
848820 unsigned short sw;
849821 int swapped, bid;
822+ struct clk *c;
850823
851824 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
852825 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
@@ -859,6 +832,24 @@ int __init db1200_dev_setup(void) · 6 unmodified lines
859832 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
860833 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
861834
835+ /* SMBus/SPI on PSC0, Audio on PSC1 */
836+ pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
837+ pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
838+ pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
839+ pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
840+ alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
841+
842+ /* get 50MHz for I2C driver on PSC0 */
843+ c = clk_get(NULL, "psc0_intclk");
844+ if (!IS_ERR(c)) {
845+ pfc = clk_round_rate(c, 50000000);
846+ if ((pfc < 1) || (abs(50000000 - pfc) > 2500000))
847+ pr_warn("DB1200: cant get I2C close to 50MHz\n");
848+ else
849+ clk_set_rate(c, pfc);
850+ clk_put(c);
851+ }
852+
862853 /* insert/eject pairs: one of both is always screaming. To avoid
863854 * issues they must not be automatically enabled when initially
864855 * requested.
@@ -886,7 +877,7 @@ int __init db1200_dev_setup(void) · 21 unmodified lines
886877 * As a result, in SPI mode, OTG simply won't work (PSC0 uses
887878 * it as an input pin which is pulled high on the boards).
888879 */
889− pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
880+ pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
890881
891882 /* switch off OTG VBUS supply */
892883 gpio_request(215, "otg-vbus");
@@ -912,8 +903,7 @@ int __init db1200_dev_setup(void) · 19 unmodified lines
912903 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
913904 printk(KERN_INFO " OTG port VBUS supply disabled\n");
914905 }
915− __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
916− wmb();
906+ alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
917907
918908 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
919909 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
@@ -932,6 +922,11 @@ int __init db1200_dev_setup(void) · 12 unmodified lines
932922 }
933923
934924 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
925+ c = clk_get(NULL, "psc1_intclk");
926+ if (!IS_ERR(c)) {
927+ clk_prepare_enable(c);
928+ clk_put(c);
929+ }
935930 __raw_writel(PSC_SEL_CLK_SERCLK,
936931 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
937932 wmb();
arch/mips/alchemy/devboards/db1300.c+8−1
@@ -4,6 +4,7 @@ · 3 unmodified lines
44 * (c) 2009 Manuel Lauss <manuel.lauss@googlemail.com>
55 */
66
7+#include <linux/clk.h>
78 #include <linux/dma-mapping.h>
89 #include <linux/gpio.h>
910 #include <linux/gpio_keys.h>
@@ -169,7 +170,7 @@ static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, · 159 unmodified lines
169170
170171 static int au1300_nand_device_ready(struct mtd_info *mtd)
171172 {
172− return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
173+ return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
173174 }
174175
175176 static struct mtd_partition db1300_nand_parts[] = {
@@ -731,6 +732,7 @@ static struct platform_device *db1300_dev[] __initdata = { · 555 unmodified lines
731732 int __init db1300_dev_setup(void)
732733 {
733734 int swapped, cpldirq;
735+ struct clk *c;
734736
735737 /* setup CPLD IRQ muxer */
736738 cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1);
@@ -761,6 +763,11 @@ int __init db1300_dev_setup(void) · 24 unmodified lines
761763 (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
762764 wmb();
763765 /* I2C uses internal 48MHz EXTCLK1 */
766+ c = clk_get(NULL, "psc3_intclk");
767+ if (!IS_ERR(c)) {
768+ clk_prepare_enable(c);
769+ clk_put(c);
770+ }
764771 __raw_writel(PSC_SEL_CLK_INTCLK,
765772 (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
766773 wmb();
arch/mips/alchemy/devboards/db1550.c+20−7
@@ -4,6 +4,7 @@ · 3 unmodified lines
44 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
55 */
66
7+#include <linux/clk.h>
78 #include <linux/dma-mapping.h>
89 #include <linux/gpio.h>
910 #include <linux/i2c.h>
@@ -31,16 +32,16 @@ · 21 unmodified lines
3132 static void __init db1550_hw_setup(void)
3233 {
3334 void __iomem *base;
35+ unsigned long v;
3436
3537 /* complete SPI setup: link psc0_intclk to a 48MHz source,
3638 * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line) as well as PSC1_SYNC
3739 * for AC97 on PB1550.
3840 */
39− base = (void __iomem *)SYS_CLKSRC;
40− __raw_writel(__raw_readl(base) | 0x000001e0, base);
41− base = (void __iomem *)SYS_PINFUNC;
42− __raw_writel(__raw_readl(base) | 1 | SYS_PF_PSC1_S1, base);
43− wmb();
41+ v = alchemy_rdsys(AU1000_SYS_CLKSRC);
42+ alchemy_wrsys(v | 0x000001e0, AU1000_SYS_CLKSRC);
43+ v = alchemy_rdsys(AU1000_SYS_PINFUNC);
44+ alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC);
4445
4546 /* reset the AC97 codec now, the reset time in the psc-ac97 driver
4647 * is apparently too short although it's ridiculous as it is.
@@ -151,7 +152,7 @@ static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, · 104 unmodified lines
151152
152153 static int au1550_nand_device_ready(struct mtd_info *mtd)
153154 {
154− return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
155+ return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
155156 }
156157
157158 static struct mtd_partition db1550_nand_parts[] = {
@@ -217,7 +218,7 @@ static struct platform_device pb1550_nand_dev = { · 59 unmodified lines
217218
218219 static void __init pb1550_nand_setup(void)
219220 {
220− int boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) |
221+ int boot_swapboot = (alchemy_rdsmem(AU1000_MEM_STSTAT) & (0x7 << 1)) |
221222 ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
222223
223224 gpio_direction_input(206); /* de-assert NAND CS# */
@@ -574,6 +575,7 @@ static void __init pb1550_devices(void) · 350 unmodified lines
574575 int __init db1550_dev_setup(void)
575576 {
576577 int swapped, id;
578+ struct clk *c;
577579
578580 id = (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) != BCSR_WHOAMI_DB1550);
579581
@@ -582,6 +584,17 @@ int __init db1550_dev_setup(void) · 2 unmodified lines
582584 spi_register_board_info(db1550_spi_devs,
583585 ARRAY_SIZE(db1550_i2c_devs));
584586
587+ c = clk_get(NULL, "psc0_intclk");
588+ if (!IS_ERR(c)) {
589+ clk_prepare_enable(c);
590+ clk_put(c);
591+ }
592+ c = clk_get(NULL, "psc2_intclk");
593+ if (!IS_ERR(c)) {
594+ clk_prepare_enable(c);
595+ clk_put(c);
596+ }
597+
585598 /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
586599 __raw_writel(PSC_SEL_CLK_SERCLK,
587600 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
arch/mips/alchemy/devboards/pm.c+15−24
@@ -45,23 +45,20 @@ static int db1x_pm_enter(suspend_state_t state) · 44 unmodified lines
4545 alchemy_gpio1_input_enable();
4646
4747 /* clear and setup wake cause and source */
48− au_writel(0, SYS_WAKEMSK);
49− au_sync();
50− au_writel(0, SYS_WAKESRC);
51− au_sync();
48+ alchemy_wrsys(0, AU1000_SYS_WAKEMSK);
49+ alchemy_wrsys(0, AU1000_SYS_WAKESRC);
5250
53− au_writel(db1x_pm_wakemsk, SYS_WAKEMSK);
54− au_sync();
51+ alchemy_wrsys(db1x_pm_wakemsk, AU1000_SYS_WAKEMSK);
5552
5653 /* setup 1Hz-timer-based wakeup: wait for reg access */
57− while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20)
54+ while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_M20)
5855 asm volatile ("nop");
5956
60− au_writel(au_readl(SYS_TOYREAD) + db1x_pm_sleep_secs, SYS_TOYMATCH2);
61− au_sync();
57+ alchemy_wrsys(alchemy_rdsys(AU1000_SYS_TOYREAD) + db1x_pm_sleep_secs,
58+ AU1000_SYS_TOYMATCH2);
6259
6360 /* wait for value to really hit the register */
64− while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20)
61+ while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_M20)
6562 asm volatile ("nop");
6663
6764 /* ...and now the sandman can come! */
@@ -102,12 +99,10 @@ static void db1x_pm_end(void) · 34 unmodified lines
10299 /* read and store wakeup source, the clear the register. To
103100 * be able to clear it, WAKEMSK must be cleared first.
104101 */
105− db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC);
106−
107− au_writel(0, SYS_WAKEMSK);
108− au_writel(0, SYS_WAKESRC);
109− au_sync();
102+ db1x_pm_last_wakesrc = alchemy_rdsys(AU1000_SYS_WAKESRC);
110103
104+ alchemy_wrsys(0, AU1000_SYS_WAKEMSK);
105+ alchemy_wrsys(0, AU1000_SYS_WAKESRC);
111106 }
112107
113108 static const struct platform_suspend_ops db1x_pm_ops = {
@@ -242,17 +237,13 @@ static int __init pm_init(void) · 128 unmodified lines
242237 * for confirmation since there's plenty of time from here to
243238 * the next suspend cycle.
244239 */
245− if (au_readl(SYS_TOYTRIM) != 32767) {
246− au_writel(32767, SYS_TOYTRIM);
247− au_sync();
248− }
240+ if (alchemy_rdsys(AU1000_SYS_TOYTRIM) != 32767)
241+ alchemy_wrsys(32767, AU1000_SYS_TOYTRIM);
249242
250− db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC);
243+ db1x_pm_last_wakesrc = alchemy_rdsys(AU1000_SYS_WAKESRC);
251244
252− au_writel(0, SYS_WAKESRC);
253− au_sync();
254− au_writel(0, SYS_WAKEMSK);
255− au_sync();
245+ alchemy_wrsys(0, AU1000_SYS_WAKESRC);
246+ alchemy_wrsys(0, AU1000_SYS_WAKEMSK);
256247
257248 suspend_set_ops(&db1x_pm_ops);
258249
arch/mips/bcm47xx/Kconfig+1−4
@@ -11,8 +11,6 @@ config BCM47XX_SSB · 10 unmodified lines
1111 select SSB_DRIVER_PCICORE if PCI
1212 select SSB_PCICORE_HOSTMODE if PCI
1313 select SSB_DRIVER_GPIO
14− select GPIOLIB
15− select LEDS_GPIO_REGISTER
1614 default y
1715 help
1816 Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support.
@@ -22,6 +20,7 @@ config BCM47XX_SSB · 3 unmodified lines
2220 config BCM47XX_BCMA
2321 bool "BCMA Support for Broadcom BCM47XX"
2422 select SYS_HAS_CPU_MIPS32_R2
23+ select SYS_SUPPORTS_HIGHMEM
2524 select CPU_MIPSR2_IRQ_VI
2625 select BCMA
2726 select BCMA_HOST_SOC
@@ -29,8 +28,6 @@ config BCM47XX_BCMA · 1 unmodified line
2928 select BCMA_HOST_PCI if PCI
3029 select BCMA_DRIVER_PCI_HOSTMODE if PCI
3130 select BCMA_DRIVER_GPIO
32− select GPIOLIB
33− select LEDS_GPIO_REGISTER
3431 default y
3532 help
3633 Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.
arch/mips/bcm47xx/bcm47xx_private.h+3−0
@@ -3,6 +3,9 @@ · 2 unmodified lines
33
44 #include <linux/kernel.h>
55
6+/* prom.c */
7+void __init bcm47xx_prom_highmem_init(void);
8+
69 /* buttons.c */
710 int __init bcm47xx_buttons_register(void);
811
arch/mips/bcm47xx/board.c+22−4
@@ -58,6 +58,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = · 57 unmodified lines
5858 static const
5959 struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = {
6060 {{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RTN10U"},
61+ {{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RTN10D"},
6162 {{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"},
6263 {{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RTN12B1"},
6364 {{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RTN12C1"},
@@ -80,6 +81,14 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initcons · 16 unmodified lines
8081 { {0}, NULL},
8182 };
8283
84+/* hardware_version, boardnum */
85+static const
86+struct bcm47xx_board_type_list2 bcm47xx_board_list_hw_version_num[] __initconst = {
87+ {{BCM47XX_BOARD_MICROSOFT_MN700, "Microsoft MN-700"}, "WL500-", "mn700"},
88+ {{BCM47XX_BOARD_ASUS_WL500G, "Asus WL500G"}, "WL500-", "asusX"},
89+ { {0}, NULL},
90+};
91+
8392 /* productid */
8493 static const
8594 struct bcm47xx_board_type_list1 bcm47xx_board_list_productid[] __initconst = {
@@ -98,7 +107,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_productid[] __initconst = { · 12 unmodified lines
98107 /* ModelId */
99108 static const
100109 struct bcm47xx_board_type_list1 bcm47xx_board_list_ModelId[] __initconst = {
101− {{BCM47XX_BOARD_DELL_TM2300, "Dell WX-5565"}, "WX-5565"},
110+ {{BCM47XX_BOARD_DELL_TM2300, "Dell TrueMobile 2300"}, "WX-5565"},
102111 {{BCM47XX_BOARD_MOTOROLA_WE800G, "Motorola WE800G"}, "WE800G"},
103112 {{BCM47XX_BOARD_MOTOROLA_WR850GP, "Motorola WR850GP"}, "WR850GP"},
104113 {{BCM47XX_BOARD_MOTOROLA_WR850GV2V3, "Motorola WR850G"}, "WR850G"},
@@ -180,9 +189,9 @@ struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = { · 75 unmodified lines
180189 {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
181190 {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
182191 {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "0x04CF", "3500", "02"},
183− {{BCM47XX_BOARD_LINKSYS_WRT54G, "Linksys WRT54G/GS/GL"}, "0x0101", "42", "0x10"},
184− {{BCM47XX_BOARD_LINKSYS_WRT54G, "Linksys WRT54G/GS/GL"}, "0x0467", "42", "0x10"},
185− {{BCM47XX_BOARD_LINKSYS_WRT54G, "Linksys WRT54G/GS/GL"}, "0x0708", "42", "0x10"},
192+ {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101, "Linksys WRT54G/GS/GL"}, "0x0101", "42", "0x10"},
193+ {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467, "Linksys WRT54G/GS/GL"}, "0x0467", "42", "0x10"},
194+ {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708, "Linksys WRT54G/GS/GL"}, "0x0708", "42", "0x10"},
186195 { {0}, NULL},
187196 };
188197
@@ -237,6 +246,15 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void) · 48 unmodified lines
237246 }
238247 }
239248
249+ if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0 &&
250+ bcm47xx_nvram_getenv("boardtype", buf2, sizeof(buf2)) >= 0) {
251+ for (e2 = bcm47xx_board_list_boot_hw; e2->value1; e2++) {
252+ if (!strstarts(buf1, e2->value1) &&
253+ !strcmp(buf2, e2->value2))
254+ return &e2->board;
255+ }
256+ }
257+
240258 if (bcm47xx_nvram_getenv("productid", buf1, sizeof(buf1)) >= 0) {
241259 for (e1 = bcm47xx_board_list_productid; e1->value1; e1++) {
242260 if (!strcmp(buf1, e1->value1))
arch/mips/bcm47xx/buttons.c+34−4
@@ -55,6 +55,11 @@ bcm47xx_buttons_asus_wl330ge[] __initconst = { · 54 unmodified lines
5555 BCM47XX_GPIO_KEY(2, KEY_RESTART),
5656 };
5757
58+static const struct gpio_keys_button
59+bcm47xx_buttons_asus_wl500g[] __initconst = {
60+ BCM47XX_GPIO_KEY(6, KEY_RESTART),
61+};
62+
5863 static const struct gpio_keys_button
5964 bcm47xx_buttons_asus_wl500gd[] __initconst = {
6065 BCM47XX_GPIO_KEY(6, KEY_RESTART),
@@ -265,7 +270,7 @@ bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = { · 204 unmodified lines
265270 };
266271
267272 static const struct gpio_keys_button
268−bcm47xx_buttons_linksys_wrt54gsv1[] __initconst = {
273+bcm47xx_buttons_linksys_wrt54g_generic[] __initconst = {
269274 BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
270275 BCM47XX_GPIO_KEY(6, KEY_RESTART),
271276 };
@@ -288,6 +293,13 @@ bcm47xx_buttons_linksys_wrtsl54gs[] __initconst = { · 16 unmodified lines
288293 BCM47XX_GPIO_KEY(6, KEY_RESTART),
289294 };
290295
296+/* Microsoft */
297+
298+static const struct gpio_keys_button
299+bcm47xx_buttons_microsoft_nm700[] __initconst = {
300+ BCM47XX_GPIO_KEY(7, KEY_RESTART),
301+};
302+
291303 /* Motorola */
292304
293305 static const struct gpio_keys_button
@@ -328,6 +340,12 @@ bcm47xx_buttons_netgear_wndr4500v1[] __initconst = { · 34 unmodified lines
328340 BCM47XX_GPIO_KEY(6, KEY_RESTART),
329341 };
330342
343+static const struct gpio_keys_button
344+bcm47xx_buttons_netgear_wnr3500lv1[] __initconst = {
345+ BCM47XX_GPIO_KEY(4, KEY_RESTART),
346+ BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),
347+};
348+
331349 static const struct gpio_keys_button
332350 bcm47xx_buttons_netgear_wnr834bv2[] __initconst = {
333351 BCM47XX_GPIO_KEY(6, KEY_RESTART),
@@ -395,6 +413,9 @@ int __init bcm47xx_buttons_register(void) · 61 unmodified lines
395413 case BCM47XX_BOARD_ASUS_WL330GE:
396414 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl330ge);
397415 break;
416+ case BCM47XX_BOARD_ASUS_WL500G:
417+ err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500g);
418+ break;
398419 case BCM47XX_BOARD_ASUS_WL500GD:
399420 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500gd);
400421 break;
@@ -501,12 +522,14 @@ int __init bcm47xx_buttons_register(void) · 100 unmodified lines
501522 case BCM47XX_BOARD_LINKSYS_WRT310NV1:
502523 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1);
503524 break;
504− case BCM47XX_BOARD_LINKSYS_WRT54G:
505− err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54gsv1);
506− break;
507525 case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
508526 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2);
509527 break;
528+ case BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101:
529+ case BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467:
530+ case BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708:
531+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g_generic);
532+ break;
510533 case BCM47XX_BOARD_LINKSYS_WRT610NV1:
511534 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt610nv1);
512535 break;
@@ -517,6 +540,10 @@ int __init bcm47xx_buttons_register(void) · 4 unmodified lines
517540 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrtsl54gs);
518541 break;
519542
543+ case BCM47XX_BOARD_MICROSOFT_MN700:
544+ err = bcm47xx_copy_bdata(bcm47xx_buttons_microsoft_nm700);
545+ break;
546+
520547 case BCM47XX_BOARD_MOTOROLA_WE800G:
521548 err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_we800g);
522549 break;
@@ -536,6 +563,9 @@ int __init bcm47xx_buttons_register(void) · 13 unmodified lines
536563 case BCM47XX_BOARD_NETGEAR_WNDR4500V1:
537564 err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr4500v1);
538565 break;
566+ case BCM47XX_BOARD_NETGEAR_WNR3500L:
567+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr3500lv1);
568+ break;
539569 case BCM47XX_BOARD_NETGEAR_WNR834BV2:
540570 err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr834bv2);
541571 break;
arch/mips/bcm47xx/leds.c+79−13
@@ -34,6 +34,15 @@ bcm47xx_leds_asus_rtn12[] __initconst = { · 33 unmodified lines
3434 BCM47XX_GPIO_LED(7, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
3535 };
3636
37+static const struct gpio_led
38+bcm47xx_leds_asus_rtn15u[] __initconst = {
39+ /* TODO: Add "wlan" LED */
40+ BCM47XX_GPIO_LED(3, "blue", "wan", 1, LEDS_GPIO_DEFSTATE_OFF),
41+ BCM47XX_GPIO_LED(4, "blue", "lan", 1, LEDS_GPIO_DEFSTATE_OFF),
42+ BCM47XX_GPIO_LED(6, "blue", "power", 1, LEDS_GPIO_DEFSTATE_ON),
43+ BCM47XX_GPIO_LED(9, "blue", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
44+};
45+
3746 static const struct gpio_led
3847 bcm47xx_leds_asus_rtn16[] __initconst = {
3948 BCM47XX_GPIO_LED(1, "blue", "power", 1, LEDS_GPIO_DEFSTATE_ON),
@@ -42,8 +51,8 @@ bcm47xx_leds_asus_rtn16[] __initconst = { · 2 unmodified lines
4251
4352 static const struct gpio_led
4453 bcm47xx_leds_asus_rtn66u[] __initconst = {
45− BCM47XX_GPIO_LED(12, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
46− BCM47XX_GPIO_LED(15, "unk", "usb", 1, LEDS_GPIO_DEFSTATE_OFF),
54+ BCM47XX_GPIO_LED(12, "blue", "power", 1, LEDS_GPIO_DEFSTATE_ON),
55+ BCM47XX_GPIO_LED(15, "blue", "usb", 1, LEDS_GPIO_DEFSTATE_OFF),
4756 };
4857
4958 static const struct gpio_led
@@ -63,6 +72,11 @@ bcm47xx_leds_asus_wl330ge[] __initconst = { · 13 unmodified lines
6372 BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
6473 };
6574
75+static const struct gpio_led
76+bcm47xx_leds_asus_wl500g[] __initconst = {
77+ BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
78+};
79+
6680 static const struct gpio_led
6781 bcm47xx_leds_asus_wl500gd[] __initconst = {
6882 BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
@@ -216,8 +230,8 @@ bcm47xx_leds_linksys_e1000v1[] __initconst = { · 147 unmodified lines
216230
217231 static const struct gpio_led
218232 bcm47xx_leds_linksys_e1000v21[] __initconst = {
219− BCM47XX_GPIO_LED(5, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
220− BCM47XX_GPIO_LED(6, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
233+ BCM47XX_GPIO_LED(5, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
234+ BCM47XX_GPIO_LED(6, "blue", "power", 1, LEDS_GPIO_DEFSTATE_ON),
221235 BCM47XX_GPIO_LED(7, "amber", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
222236 BCM47XX_GPIO_LED(8, "blue", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
223237 };
@@ -292,7 +306,7 @@ bcm47xx_leds_linksys_wrt310nv1[] __initconst = { · 68 unmodified lines
292306 };
293307
294308 static const struct gpio_led
295−bcm47xx_leds_linksys_wrt54gsv1[] __initconst = {
309+bcm47xx_leds_linksys_wrt54g_generic[] __initconst = {
296310 BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
297311 BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
298312 BCM47XX_GPIO_LED(5, "white", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
@@ -306,6 +320,24 @@ bcm47xx_leds_linksys_wrt54g3gv2[] __initconst = { · 7 unmodified lines
306320 BCM47XX_GPIO_LED(3, "blue", "3g", 0, LEDS_GPIO_DEFSTATE_OFF),
307321 };
308322
323+/* Verified on: WRT54GS V1.0 */
324+static const struct gpio_led
325+bcm47xx_leds_linksys_wrt54g_type_0101[] __initconst = {
326+ BCM47XX_GPIO_LED(0, "green", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
327+ BCM47XX_GPIO_LED(1, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
328+ BCM47XX_GPIO_LED(7, "green", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
329+};
330+
331+/* Verified on: WRT54GL V1.1 */
332+static const struct gpio_led
333+bcm47xx_leds_linksys_wrt54g_type_0467[] __initconst = {
334+ BCM47XX_GPIO_LED(0, "green", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
335+ BCM47XX_GPIO_LED(1, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
336+ BCM47XX_GPIO_LED(2, "white", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
337+ BCM47XX_GPIO_LED(3, "orange", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
338+ BCM47XX_GPIO_LED(7, "green", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
339+};
340+
309341 static const struct gpio_led
310342 bcm47xx_leds_linksys_wrt610nv1[] __initconst = {
311343 BCM47XX_GPIO_LED(0, "unk", "usb", 1, LEDS_GPIO_DEFSTATE_OFF),
@@ -325,11 +357,17 @@ bcm47xx_leds_linksys_wrt610nv2[] __initconst = { · 13 unmodified lines
325357
326358 static const struct gpio_led
327359 bcm47xx_leds_linksys_wrtsl54gs[] __initconst = {
328− BCM47XX_GPIO_LED(0, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
329− BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
330− BCM47XX_GPIO_LED(2, "white", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
331− BCM47XX_GPIO_LED(3, "orange", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
332− BCM47XX_GPIO_LED(7, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
360+ BCM47XX_GPIO_LED(0, "green", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
361+ BCM47XX_GPIO_LED(1, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
362+ BCM47XX_GPIO_LED(5, "white", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
363+ BCM47XX_GPIO_LED(7, "orange", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
364+};
365+
366+/* Microsoft */
367+
368+static const struct gpio_led
369+bcm47xx_leds_microsoft_nm700[] __initconst = {
370+ BCM47XX_GPIO_LED(6, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
333371 };
334372
335373 /* Motorola */
@@ -376,6 +414,15 @@ bcm47xx_leds_netgear_wndr4500v1[] __initconst = { · 40 unmodified lines
376414 BCM47XX_GPIO_LED(14, "green", "usb2", 1, LEDS_GPIO_DEFSTATE_OFF),
377415 };
378416
417+static const struct gpio_led
418+bcm47xx_leds_netgear_wnr3500lv1[] __initconst = {
419+ BCM47XX_GPIO_LED(0, "blue", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
420+ BCM47XX_GPIO_LED(1, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
421+ BCM47XX_GPIO_LED(2, "green", "wan", 1, LEDS_GPIO_DEFSTATE_OFF),
422+ BCM47XX_GPIO_LED(3, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
423+ BCM47XX_GPIO_LED(7, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF),
424+};
425+
379426 static const struct gpio_led
380427 bcm47xx_leds_netgear_wnr834bv2[] __initconst = {
381428 BCM47XX_GPIO_LED(2, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
@@ -417,6 +464,9 @@ void __init bcm47xx_leds_register(void) · 35 unmodified lines
417464 case BCM47XX_BOARD_ASUS_RTN12:
418465 bcm47xx_set_pdata(bcm47xx_leds_asus_rtn12);
419466 break;
467+ case BCM47XX_BOARD_ASUS_RTN15U:
468+ bcm47xx_set_pdata(bcm47xx_leds_asus_rtn15u);
469+ break;
420470 case BCM47XX_BOARD_ASUS_RTN16:
421471 bcm47xx_set_pdata(bcm47xx_leds_asus_rtn16);
422472 break;
@@ -432,6 +482,9 @@ void __init bcm47xx_leds_register(void) · 9 unmodified lines
432482 case BCM47XX_BOARD_ASUS_WL330GE:
433483 bcm47xx_set_pdata(bcm47xx_leds_asus_wl330ge);
434484 break;
485+ case BCM47XX_BOARD_ASUS_WL500G:
486+ bcm47xx_set_pdata(bcm47xx_leds_asus_wl500g);
487+ break;
435488 case BCM47XX_BOARD_ASUS_WL500GD:
436489 bcm47xx_set_pdata(bcm47xx_leds_asus_wl500gd);
437490 break;
@@ -538,12 +591,18 @@ void __init bcm47xx_leds_register(void) · 100 unmodified lines
538591 case BCM47XX_BOARD_LINKSYS_WRT310NV1:
539592 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1);
540593 break;
541− case BCM47XX_BOARD_LINKSYS_WRT54G:
542− bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54gsv1);
543− break;
544594 case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
545595 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g3gv2);
546596 break;
597+ case BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101:
598+ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g_type_0101);
599+ break;
600+ case BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467:
601+ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g_type_0467);
602+ break;
603+ case BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708:
604+ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g_generic);
605+ break;
547606 case BCM47XX_BOARD_LINKSYS_WRT610NV1:
548607 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt610nv1);
549608 break;
@@ -554,6 +613,10 @@ void __init bcm47xx_leds_register(void) · 4 unmodified lines
554613 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrtsl54gs);
555614 break;
556615
616+ case BCM47XX_BOARD_MICROSOFT_MN700:
617+ bcm47xx_set_pdata(bcm47xx_leds_microsoft_nm700);
618+ break;
619+
557620 case BCM47XX_BOARD_MOTOROLA_WE800G:
558621 bcm47xx_set_pdata(bcm47xx_leds_motorola_we800g);
559622 break;
@@ -570,6 +633,9 @@ void __init bcm47xx_leds_register(void) · 10 unmodified lines
570633 case BCM47XX_BOARD_NETGEAR_WNDR4500V1:
571634 bcm47xx_set_pdata(bcm47xx_leds_netgear_wndr4500v1);
572635 break;
636+ case BCM47XX_BOARD_NETGEAR_WNR3500L:
637+ bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr3500lv1);
638+ break;
573639 case BCM47XX_BOARD_NETGEAR_WNR834BV2:
574640 bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr834bv2);
575641 break;
arch/mips/bcm47xx/prom.c+67−1
@@ -51,6 +51,8 @@ __init void bcm47xx_set_system_type(u16 chip_id) · 50 unmodified lines
5151 chip_id);
5252 }
5353
54+static unsigned long lowmem __initdata;
55+
5456 static __init void prom_init_mem(void)
5557 {
5658 unsigned long mem;
@@ -87,6 +89,7 @@ static __init void prom_init_mem(void) · 30 unmodified lines
8789 if (!memcmp(prom_init, prom_init + mem, 32))
8890 break;
8991 }
92+ lowmem = mem;
9093
9194 /* Ignoring the last page when ddr size is 128M. Cached
9295 * accesses to last page is causing the processor to prefetch
@@ -95,7 +98,6 @@ static __init void prom_init_mem(void) · 2 unmodified lines
9598 */
9699 if (c->cputype == CPU_74K && (mem == (128 << 20)))
97100 mem -= 0x1000;
98−
99101 add_memory_region(0, mem, BOOT_MEM_RAM);
100102 }
101103
@@ -114,3 +116,67 @@ void __init prom_init(void) · 12 unmodified lines
114116 void __init prom_free_prom_memory(void)
115117 {
116118 }
119+
120+#if defined(CONFIG_BCM47XX_BCMA) && defined(CONFIG_HIGHMEM)
121+
122+#define EXTVBASE 0xc0000000
123+#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> _PFN_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6) | 1)
124+
125+#include <asm/tlbflush.h>
126+
127+/* Stripped version of tlb_init, with the call to build_tlb_refill_handler
128+ * dropped. Calling it at this stage causes a hang.
129+ */
130+void __cpuinit early_tlb_init(void)
131+{
132+ write_c0_pagemask(PM_DEFAULT_MASK);
133+ write_c0_wired(0);
134+ temp_tlb_entry = current_cpu_data.tlbsize - 1;
135+ local_flush_tlb_all();
136+}
137+
138+void __init bcm47xx_prom_highmem_init(void)
139+{
140+ unsigned long off = (unsigned long)prom_init;
141+ unsigned long extmem = 0;
142+ bool highmem_region = false;
143+
144+ if (WARN_ON(bcm47xx_bus_type != BCM47XX_BUS_TYPE_BCMA))
145+ return;
146+
147+ if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
148+ highmem_region = true;
149+
150+ if (lowmem != 128 << 20 || !highmem_region)
151+ return;
152+
153+ early_tlb_init();
154+
155+ /* Add one temporary TLB entry to map SDRAM Region 2.
156+ * Physical Virtual
157+ * 0x80000000 0xc0000000 (1st: 256MB)
158+ * 0x90000000 0xd0000000 (2nd: 256MB)
159+ */
160+ add_temporary_entry(ENTRYLO(0x80000000),
161+ ENTRYLO(0x80000000 + (256 << 20)),
162+ EXTVBASE, PM_256M);
163+
164+ off = EXTVBASE + __pa(off);
165+ for (extmem = 128 << 20; extmem < 512 << 20; extmem <<= 1) {
166+ if (!memcmp(prom_init, (void *)(off + extmem), 16))
167+ break;
168+ }
169+ extmem -= lowmem;
170+
171+ early_tlb_init();
172+
173+ if (!extmem)
174+ return;
175+
176+ pr_warn("Found %lu MiB of extra memory, but highmem is unsupported yet!\n",
177+ extmem >> 20);
178+
179+ /* TODO: Register extra memory */
180+}
181+
182+#endif /* defined(CONFIG_BCM47XX_BCMA) && defined(CONFIG_HIGHMEM) */
arch/mips/bcm47xx/setup.c+5−2
@@ -59,12 +59,12 @@ static void bcm47xx_machine_restart(char *command) · 58 unmodified lines
5959 switch (bcm47xx_bus_type) {
6060 #ifdef CONFIG_BCM47XX_SSB
6161 case BCM47XX_BUS_TYPE_SSB:
62− ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
62+ ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 3);
6363 break;
6464 #endif
6565 #ifdef CONFIG_BCM47XX_BCMA
6666 case BCM47XX_BUS_TYPE_BCMA:
67− bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 1);
67+ bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 3);
6868 break;
6969 #endif
7070 }
@@ -218,6 +218,9 @@ void __init plat_mem_setup(void) · 147 unmodified lines
218218 bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
219219 bcm47xx_register_bcma();
220220 bcm47xx_set_system_type(bcm47xx_bus.bcma.bus.chipinfo.id);
221+#ifdef CONFIG_HIGHMEM
222+ bcm47xx_prom_highmem_init();
223+#endif
221224 #endif
222225 } else {
223226 printk(KERN_INFO "bcm47xx: using ssb bus\n");
arch/mips/bcm47xx/sprom.c+48−0
@@ -28,6 +28,8 @@ · 27 unmodified lines
2828
2929 #include <bcm47xx.h>
3030 #include <bcm47xx_nvram.h>
31+#include <linux/if_ether.h>
32+#include <linux/etherdevice.h>
3133
3234 static void create_key(const char *prefix, const char *postfix,
3335 const char *name, char *buf, int len)
@@ -631,6 +633,33 @@ static void bcm47xx_fill_sprom_path_r45(struct ssb_sprom *sprom, · 597 unmodified lines
631633 }
632634 }
633635
636+static bool bcm47xx_is_valid_mac(u8 *mac)
637+{
638+ return mac && !(mac[0] == 0x00 && mac[1] == 0x90 && mac[2] == 0x4c);
639+}
640+
641+static int bcm47xx_increase_mac_addr(u8 *mac, u8 num)
642+{
643+ u8 *oui = mac + ETH_ALEN/2 - 1;
644+ u8 *p = mac + ETH_ALEN - 1;
645+
646+ do {
647+ (*p) += num;
648+ if (*p > num)
649+ break;
650+ p--;
651+ num = 1;
652+ } while (p != oui);
653+
654+ if (p == oui) {
655+ pr_err("unable to fetch mac address\n");
656+ return -ENOENT;
657+ }
658+ return 0;
659+}
660+
661+static int mac_addr_used = 2;
662+
634663 static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom,
635664 const char *prefix, bool fallback)
636665 {
@@ -648,6 +677,25 @@ static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom, · 11 unmodified lines
648677
649678 nvram_read_macaddr(prefix, "macaddr", sprom->il0mac, fallback);
650679 nvram_read_macaddr(prefix, "il0macaddr", sprom->il0mac, fallback);
680+
681+ /* The address prefix 00:90:4C is used by Broadcom in their initial
682+ configuration. When a mac address with the prefix 00:90:4C is used
683+ all devices from the same series are sharing the same mac address.
684+ To prevent mac address collisions we replace them with a mac address
685+ based on the base address. */
686+ if (!bcm47xx_is_valid_mac(sprom->il0mac)) {
687+ u8 mac[6];
688+
689+ nvram_read_macaddr(NULL, "et0macaddr", mac, false);
690+ if (bcm47xx_is_valid_mac(mac)) {
691+ int err = bcm47xx_increase_mac_addr(mac, mac_addr_used);
692+
693+ if (!err) {
694+ ether_addr_copy(sprom->il0mac, mac);
695+ mac_addr_used++;
696+ }
697+ }
698+ }
651699 }
652700
653701 static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix,
arch/mips/bcm63xx/cpu.c+3−8
@@ -24,7 +24,9 @@ EXPORT_SYMBOL(bcm63xx_regs_base); · 23 unmodified lines
2424 const int *bcm63xx_irqs;
2525 EXPORT_SYMBOL(bcm63xx_irqs);
2626
27−static u16 bcm63xx_cpu_id;
27+u16 bcm63xx_cpu_id __read_mostly;
28+EXPORT_SYMBOL(bcm63xx_cpu_id);
29+
2830 static u8 bcm63xx_cpu_rev;
2931 static unsigned int bcm63xx_cpu_freq;
3032 static unsigned int bcm63xx_memory_size;
@@ -97,13 +99,6 @@ static const int bcm6368_irqs[] = { · 66 unmodified lines
9799
98100 };
99101
100−u16 __bcm63xx_get_cpu_id(void)
101−{
102− return bcm63xx_cpu_id;
103−}
104−
105−EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
106−
107102 u8 bcm63xx_get_cpu_rev(void)
108103 {
109104 return bcm63xx_cpu_rev;
arch/mips/bcm63xx/dev-enet.c+0−4
@@ -14,7 +14,6 @@ · 13 unmodified lines
1414 #include <bcm63xx_io.h>
1515 #include <bcm63xx_regs.h>
1616
17−#ifdef BCMCPU_RUNTIME_DETECT
1817 static const unsigned long bcm6348_regs_enetdmac[] = {
1918 [ENETDMAC_CHANCFG] = ENETDMAC_CHANCFG_REG,
2019 [ENETDMAC_IR] = ENETDMAC_IR_REG,
@@ -43,9 +42,6 @@ static __init void bcm63xx_enetdmac_regs_init(void) · 22 unmodified lines
4342 else
4443 bcm63xx_regs_enetdmac = bcm6348_regs_enetdmac;
4544 }
46−#else
47−static __init void bcm63xx_enetdmac_regs_init(void) { }
48−#endif
4945
5046 static struct resource shared_res[] = {
5147 {
arch/mips/bcm63xx/dev-spi.c+0−4
@@ -18,7 +18,6 @@ · 17 unmodified lines
1818 #include <bcm63xx_dev_spi.h>
1919 #include <bcm63xx_regs.h>
2020
21−#ifdef BCMCPU_RUNTIME_DETECT
2221 /*
2322 * register offsets
2423 */
@@ -41,9 +40,6 @@ static __init void bcm63xx_spi_regs_init(void) · 16 unmodified lines
4140 BCMCPU_IS_6362() || BCMCPU_IS_6368())
4241 bcm63xx_regs_spi = bcm6358_regs_spi;
4342 }
44−#else
45−static __init void bcm63xx_spi_regs_init(void) { }
46−#endif
4743
4844 static struct resource spi_resources[] = {
4945 {
arch/mips/bcm63xx/gpio.c+0−14
@@ -18,19 +18,6 @@ · 17 unmodified lines
1818 #include <bcm63xx_io.h>
1919 #include <bcm63xx_regs.h>
2020
21−#ifndef BCMCPU_RUNTIME_DETECT
22−#define gpio_out_low_reg GPIO_DATA_LO_REG
23−#ifdef CONFIG_BCM63XX_CPU_6345
24−#ifdef gpio_out_low_reg
25−#undef gpio_out_low_reg
26−#define gpio_out_low_reg GPIO_DATA_LO_REG_6345
27−#endif /* gpio_out_low_reg */
28−#endif /* CONFIG_BCM63XX_CPU_6345 */
29−
30−static inline void bcm63xx_gpio_out_low_reg_init(void)
31−{
32−}
33−#else /* ! BCMCPU_RUNTIME_DETECT */
3421 static u32 gpio_out_low_reg;
3522
3623 static void bcm63xx_gpio_out_low_reg_init(void)
@@ -44,7 +31,6 @@ static void bcm63xx_gpio_out_low_reg_init(void) · 7 unmodified lines
4431 break;
4532 }
4633 }
47−#endif /* ! BCMCPU_RUNTIME_DETECT */
4834
4935 static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
5036 static u32 gpio_out_low, gpio_out_high;
arch/mips/bcm63xx/irq.c+269−289
@@ -12,6 +12,7 @@ · 11 unmodified lines
1212 #include <linux/interrupt.h>
1313 #include <linux/module.h>
1414 #include <linux/irq.h>
15+#include <linux/spinlock.h>
1516 #include <asm/irq_cpu.h>
1617 #include <asm/mipsregs.h>
1718 #include <bcm63xx_cpu.h>
@@ -19,222 +20,20 @@ · 1 unmodified line
1920 #include <bcm63xx_io.h>
2021 #include <bcm63xx_irq.h>
2122
22−static void __dispatch_internal(void) __maybe_unused;
23−static void __dispatch_internal_64(void) __maybe_unused;
24−static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
25−static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
26−static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
27−static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
28−
29−#ifndef BCMCPU_RUNTIME_DETECT
30−#ifdef CONFIG_BCM63XX_CPU_3368
31−#define irq_stat_reg PERF_IRQSTAT_3368_REG
32−#define irq_mask_reg PERF_IRQMASK_3368_REG
33−#define irq_bits 32
34−#define is_ext_irq_cascaded 0
35−#define ext_irq_start 0
36−#define ext_irq_end 0
37−#define ext_irq_count 4
38−#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_3368
39−#define ext_irq_cfg_reg2 0
40−#endif
41−#ifdef CONFIG_BCM63XX_CPU_6328
42−#define irq_stat_reg PERF_IRQSTAT_6328_REG
43−#define irq_mask_reg PERF_IRQMASK_6328_REG
44−#define irq_bits 64
45−#define is_ext_irq_cascaded 1
46−#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
47−#define ext_irq_end (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE)
48−#define ext_irq_count 4
49−#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6328
50−#define ext_irq_cfg_reg2 0
51−#endif
52−#ifdef CONFIG_BCM63XX_CPU_6338
53−#define irq_stat_reg PERF_IRQSTAT_6338_REG
54−#define irq_mask_reg PERF_IRQMASK_6338_REG
55−#define irq_bits 32
56−#define is_ext_irq_cascaded 0
57−#define ext_irq_start 0
58−#define ext_irq_end 0
59−#define ext_irq_count 4
60−#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6338
61−#define ext_irq_cfg_reg2 0
62−#endif
63−#ifdef CONFIG_BCM63XX_CPU_6345
64−#define irq_stat_reg PERF_IRQSTAT_6345_REG
65−#define irq_mask_reg PERF_IRQMASK_6345_REG
66−#define irq_bits 32
67−#define is_ext_irq_cascaded 0
68−#define ext_irq_start 0
69−#define ext_irq_end 0
70−#define ext_irq_count 4
71−#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6345
72−#define ext_irq_cfg_reg2 0
73−#endif
74−#ifdef CONFIG_BCM63XX_CPU_6348
75−#define irq_stat_reg PERF_IRQSTAT_6348_REG
76−#define irq_mask_reg PERF_IRQMASK_6348_REG
77−#define irq_bits 32
78−#define is_ext_irq_cascaded 0
79−#define ext_irq_start 0
80−#define ext_irq_end 0
81−#define ext_irq_count 4
82−#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6348
83−#define ext_irq_cfg_reg2 0
84−#endif
85−#ifdef CONFIG_BCM63XX_CPU_6358
86−#define irq_stat_reg PERF_IRQSTAT_6358_REG
87−#define irq_mask_reg PERF_IRQMASK_6358_REG
88−#define irq_bits 32
89−#define is_ext_irq_cascaded 1
90−#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
91−#define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
92−#define ext_irq_count 4
93−#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
94−#define ext_irq_cfg_reg2 0
95−#endif
96−#ifdef CONFIG_BCM63XX_CPU_6362
97−#define irq_stat_reg PERF_IRQSTAT_6362_REG
98−#define irq_mask_reg PERF_IRQMASK_6362_REG
99−#define irq_bits 64
100−#define is_ext_irq_cascaded 1
101−#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
102−#define ext_irq_end (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE)
103−#define ext_irq_count 4
104−#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6362
105−#define ext_irq_cfg_reg2 0
106−#endif
107−#ifdef CONFIG_BCM63XX_CPU_6368
108−#define irq_stat_reg PERF_IRQSTAT_6368_REG
109−#define irq_mask_reg PERF_IRQMASK_6368_REG
110−#define irq_bits 64
111−#define is_ext_irq_cascaded 1
112−#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
113−#define ext_irq_end (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
114−#define ext_irq_count 6
115−#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6368
116−#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6368
117−#endif
118−
119−#if irq_bits == 32
120−#define dispatch_internal __dispatch_internal
121−#define internal_irq_mask __internal_irq_mask_32
122−#define internal_irq_unmask __internal_irq_unmask_32
123−#else
124−#define dispatch_internal __dispatch_internal_64
125−#define internal_irq_mask __internal_irq_mask_64
126−#define internal_irq_unmask __internal_irq_unmask_64
127−#endif
12823
129−#define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
130−#define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
24+static DEFINE_SPINLOCK(ipic_lock);
25+static DEFINE_SPINLOCK(epic_lock);
13126
132−static inline void bcm63xx_init_irq(void)
133−{
134−}
135−#else /* ! BCMCPU_RUNTIME_DETECT */
136−
137−static u32 irq_stat_addr, irq_mask_addr;
138−static void (*dispatch_internal)(void);
27+static u32 irq_stat_addr[2];
28+static u32 irq_mask_addr[2];
29+static void (*dispatch_internal)(int cpu);
13930 static int is_ext_irq_cascaded;
14031 static unsigned int ext_irq_count;
14132 static unsigned int ext_irq_start, ext_irq_end;
14233 static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
143−static void (*internal_irq_mask)(unsigned int irq);
144−static void (*internal_irq_unmask)(unsigned int irq);
34+static void (*internal_irq_mask)(struct irq_data *d);
35+static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m);
14536
146−static void bcm63xx_init_irq(void)
147−{
148− int irq_bits;
149−
150− irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
151− irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
152−
153− switch (bcm63xx_get_cpu_id()) {
154− case BCM3368_CPU_ID:
155− irq_stat_addr += PERF_IRQSTAT_3368_REG;
156− irq_mask_addr += PERF_IRQMASK_3368_REG;
157− irq_bits = 32;
158− ext_irq_count = 4;
159− ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
160− break;
161− case BCM6328_CPU_ID:
162− irq_stat_addr += PERF_IRQSTAT_6328_REG;
163− irq_mask_addr += PERF_IRQMASK_6328_REG;
164− irq_bits = 64;
165− ext_irq_count = 4;
166− is_ext_irq_cascaded = 1;
167− ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
168− ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
169− ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
170− break;
171− case BCM6338_CPU_ID:
172− irq_stat_addr += PERF_IRQSTAT_6338_REG;
173− irq_mask_addr += PERF_IRQMASK_6338_REG;
174− irq_bits = 32;
175− ext_irq_count = 4;
176− ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
177− break;
178− case BCM6345_CPU_ID:
179− irq_stat_addr += PERF_IRQSTAT_6345_REG;
180− irq_mask_addr += PERF_IRQMASK_6345_REG;
181− irq_bits = 32;
182− ext_irq_count = 4;
183− ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
184− break;
185− case BCM6348_CPU_ID:
186− irq_stat_addr += PERF_IRQSTAT_6348_REG;
187− irq_mask_addr += PERF_IRQMASK_6348_REG;
188− irq_bits = 32;
189− ext_irq_count = 4;
190− ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
191− break;
192− case BCM6358_CPU_ID:
193− irq_stat_addr += PERF_IRQSTAT_6358_REG;
194− irq_mask_addr += PERF_IRQMASK_6358_REG;
195− irq_bits = 32;
196− ext_irq_count = 4;
197− is_ext_irq_cascaded = 1;
198− ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
199− ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
200− ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
201− break;
202− case BCM6362_CPU_ID:
203− irq_stat_addr += PERF_IRQSTAT_6362_REG;
204− irq_mask_addr += PERF_IRQMASK_6362_REG;
205− irq_bits = 64;
206− ext_irq_count = 4;
207− is_ext_irq_cascaded = 1;
208− ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
209− ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
210− ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
211− break;
212− case BCM6368_CPU_ID:
213− irq_stat_addr += PERF_IRQSTAT_6368_REG;
214− irq_mask_addr += PERF_IRQMASK_6368_REG;
215− irq_bits = 64;
216− ext_irq_count = 6;
217− is_ext_irq_cascaded = 1;
218− ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
219− ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
220− ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
221− ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
222− break;
223− default:
224− BUG();
225− }
226−
227− if (irq_bits == 32) {
228− dispatch_internal = __dispatch_internal;
229− internal_irq_mask = __internal_irq_mask_32;
230− internal_irq_unmask = __internal_irq_unmask_32;
231− } else {
232− dispatch_internal = __dispatch_internal_64;
233− internal_irq_mask = __internal_irq_mask_64;
234− internal_irq_unmask = __internal_irq_unmask_64;
235− }
236−}
237−#endif /* ! BCMCPU_RUNTIME_DETECT */
23837
23938 static inline u32 get_ext_irq_perf_reg(int irq)
24039 {
@@ -252,53 +51,113 @@ static inline void handle_internal(int intbit) · 11 unmodified lines
25251 do_IRQ(intbit + IRQ_INTERNAL_BASE);
25352 }
25453
54+static inline int enable_irq_for_cpu(int cpu, struct irq_data *d,
55+ const struct cpumask *m)
56+{
57+ bool enable = cpu_online(cpu);
58+
59+#ifdef CONFIG_SMP
60+ if (m)
61+ enable &= cpu_isset(cpu, *m);
62+ else if (irqd_affinity_was_set(d))
63+ enable &= cpu_isset(cpu, *d->affinity);
64+#endif
65+ return enable;
66+}
67+
25568 /*
25669 * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
25770 * prioritize any interrupt relatively to another. the static counter
25871 * will resume the loop where it ended the last time we left this
25972 * function.
26073 */
261−static void __dispatch_internal(void)
262−{
263− u32 pending;
264− static int i;
265−
266− pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr);
26774
268− if (!pending)
269− return ;
270−
271− while (1) {
272− int to_call = i;
273−
274− i = (i + 1) & 0x1f;
275− if (pending & (1 << to_call)) {
276− handle_internal(to_call);
277− break;
278− }
279− }
75+#define BUILD_IPIC_INTERNAL(width) \
76+void __dispatch_internal_##width(int cpu) \
77+{ \
78+ u32 pending[width / 32]; \
79+ unsigned int src, tgt; \
80+ bool irqs_pending = false; \
81+ static unsigned int i[2]; \
82+ unsigned int *next = &i[cpu]; \
83+ unsigned long flags; \
84+ \
85+ /* read registers in reverse order */ \
86+ spin_lock_irqsave(&ipic_lock, flags); \
87+ for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
88+ u32 val; \
89+ \
90+ val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \
91+ val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \
92+ pending[--tgt] = val; \
93+ \
94+ if (val) \
95+ irqs_pending = true; \
96+ } \
97+ spin_unlock_irqrestore(&ipic_lock, flags); \
98+ \
99+ if (!irqs_pending) \
100+ return; \
101+ \
102+ while (1) { \
103+ unsigned int to_call = *next; \
104+ \
105+ *next = (*next + 1) & (width - 1); \
106+ if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \
107+ handle_internal(to_call); \
108+ break; \
109+ } \
110+ } \
111+} \
112+ \
113+static void __internal_irq_mask_##width(struct irq_data *d) \
114+{ \
115+ u32 val; \
116+ unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
117+ unsigned reg = (irq / 32) ^ (width/32 - 1); \
118+ unsigned bit = irq & 0x1f; \
119+ unsigned long flags; \
120+ int cpu; \
121+ \
122+ spin_lock_irqsave(&ipic_lock, flags); \
123+ for_each_present_cpu(cpu) { \
124+ if (!irq_mask_addr[cpu]) \
125+ break; \
126+ \
127+ val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
128+ val &= ~(1 << bit); \
129+ bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
130+ } \
131+ spin_unlock_irqrestore(&ipic_lock, flags); \
132+} \
133+ \
134+static void __internal_irq_unmask_##width(struct irq_data *d, \
135+ const struct cpumask *m) \
136+{ \
137+ u32 val; \
138+ unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
139+ unsigned reg = (irq / 32) ^ (width/32 - 1); \
140+ unsigned bit = irq & 0x1f; \
141+ unsigned long flags; \
142+ int cpu; \
143+ \
144+ spin_lock_irqsave(&ipic_lock, flags); \
145+ for_each_present_cpu(cpu) { \
146+ if (!irq_mask_addr[cpu]) \
147+ break; \
148+ \
149+ val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
150+ if (enable_irq_for_cpu(cpu, d, m)) \
151+ val |= (1 << bit); \
152+ else \
153+ val &= ~(1 << bit); \
154+ bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
155+ } \
156+ spin_unlock_irqrestore(&ipic_lock, flags); \
280157 }
281158
282−static void __dispatch_internal_64(void)
283−{
284− u64 pending;
285− static int i;
286−
287− pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr);
288−
289− if (!pending)
290− return ;
291−
292− while (1) {
293− int to_call = i;
294−
295− i = (i + 1) & 0x3f;
296− if (pending & (1ull << to_call)) {
297− handle_internal(to_call);
298− break;
299− }
300− }
301−}
159+BUILD_IPIC_INTERNAL(32);
160+BUILD_IPIC_INTERNAL(64);
302161
303162 asmlinkage void plat_irq_dispatch(void)
304163 {
@@ -317,8 +176,11 @@ asmlinkage void plat_irq_dispatch(void) · 12 unmodified lines
317176 if (cause & CAUSEF_IP1)
318177 do_IRQ(1);
319178 if (cause & CAUSEF_IP2)
320− dispatch_internal();
321− if (!is_ext_irq_cascaded) {
179+ dispatch_internal(0);
180+ if (is_ext_irq_cascaded) {
181+ if (cause & CAUSEF_IP3)
182+ dispatch_internal(1);
183+ } else {
322184 if (cause & CAUSEF_IP3)
323185 do_IRQ(IRQ_EXT_0);
324186 if (cause & CAUSEF_IP4)
@@ -335,50 +197,14 @@ asmlinkage void plat_irq_dispatch(void) · 10 unmodified lines
335197 * internal IRQs operations: only mask/unmask on PERF irq mask
336198 * register.
337199 */
338−static void __internal_irq_mask_32(unsigned int irq)
339−{
340− u32 mask;
341−
342− mask = bcm_readl(irq_mask_addr);
343− mask &= ~(1 << irq);
344− bcm_writel(mask, irq_mask_addr);
345−}
346−
347−static void __internal_irq_mask_64(unsigned int irq)
348−{
349− u64 mask;
350−
351− mask = bcm_readq(irq_mask_addr);
352− mask &= ~(1ull << irq);
353− bcm_writeq(mask, irq_mask_addr);
354−}
355−
356−static void __internal_irq_unmask_32(unsigned int irq)
357−{
358− u32 mask;
359−
360− mask = bcm_readl(irq_mask_addr);
361− mask |= (1 << irq);
362− bcm_writel(mask, irq_mask_addr);
363−}
364−
365−static void __internal_irq_unmask_64(unsigned int irq)
366−{
367− u64 mask;
368−
369− mask = bcm_readq(irq_mask_addr);
370− mask |= (1ull << irq);
371− bcm_writeq(mask, irq_mask_addr);
372−}
373−
374200 static void bcm63xx_internal_irq_mask(struct irq_data *d)
375201 {
376− internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
202+ internal_irq_mask(d);
377203 }
378204
379205 static void bcm63xx_internal_irq_unmask(struct irq_data *d)
380206 {
381− internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
207+ internal_irq_unmask(d, NULL);
382208 }
383209
384210 /*
@@ -389,8 +215,10 @@ static void bcm63xx_external_irq_mask(struct irq_data *d) · 4 unmodified lines
389215 {
390216 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
391217 u32 reg, regaddr;
218+ unsigned long flags;
392219
393220 regaddr = get_ext_irq_perf_reg(irq);
221+ spin_lock_irqsave(&epic_lock, flags);
394222 reg = bcm_perf_readl(regaddr);
395223
396224 if (BCMCPU_IS_6348())
@@ -399,16 +227,20 @@ static void bcm63xx_external_irq_mask(struct irq_data *d) · 2 unmodified lines
399227 reg &= ~EXTIRQ_CFG_MASK(irq % 4);
400228
401229 bcm_perf_writel(reg, regaddr);
230+ spin_unlock_irqrestore(&epic_lock, flags);
231+
402232 if (is_ext_irq_cascaded)
403− internal_irq_mask(irq + ext_irq_start);
233+ internal_irq_mask(irq_get_irq_data(irq + ext_irq_start));
404234 }
405235
406236 static void bcm63xx_external_irq_unmask(struct irq_data *d)
407237 {
408238 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
409239 u32 reg, regaddr;
240+ unsigned long flags;
410241
411242 regaddr = get_ext_irq_perf_reg(irq);
243+ spin_lock_irqsave(&epic_lock, flags);
412244 reg = bcm_perf_readl(regaddr);
413245
414246 if (BCMCPU_IS_6348())
@@ -417,17 +249,21 @@ static void bcm63xx_external_irq_unmask(struct irq_data *d) · 2 unmodified lines
417249 reg |= EXTIRQ_CFG_MASK(irq % 4);
418250
419251 bcm_perf_writel(reg, regaddr);
252+ spin_unlock_irqrestore(&epic_lock, flags);
420253
421254 if (is_ext_irq_cascaded)
422− internal_irq_unmask(irq + ext_irq_start);
255+ internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start),
256+ NULL);
423257 }
424258
425259 static void bcm63xx_external_irq_clear(struct irq_data *d)
426260 {
427261 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
428262 u32 reg, regaddr;
263+ unsigned long flags;
429264
430265 regaddr = get_ext_irq_perf_reg(irq);
266+ spin_lock_irqsave(&epic_lock, flags);
431267 reg = bcm_perf_readl(regaddr);
432268
433269 if (BCMCPU_IS_6348())
@@ -436,6 +272,7 @@ static void bcm63xx_external_irq_clear(struct irq_data *d) · 2 unmodified lines
436272 reg |= EXTIRQ_CFG_CLEAR(irq % 4);
437273
438274 bcm_perf_writel(reg, regaddr);
275+ spin_unlock_irqrestore(&epic_lock, flags);
439276 }
440277
441278 static int bcm63xx_external_irq_set_type(struct irq_data *d,
@@ -444,6 +281,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, · 2 unmodified lines
444281 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
445282 u32 reg, regaddr;
446283 int levelsense, sense, bothedge;
284+ unsigned long flags;
447285
448286 flow_type &= IRQ_TYPE_SENSE_MASK;
449287
@@ -478,6 +316,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, · 28 unmodified lines
478316 }
479317
480318 regaddr = get_ext_irq_perf_reg(irq);
319+ spin_lock_irqsave(&epic_lock, flags);
481320 reg = bcm_perf_readl(regaddr);
482321 irq %= 4;
483322
@@ -522,6 +361,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, · 38 unmodified lines
522361 }
523362
524363 bcm_perf_writel(reg, regaddr);
364+ spin_unlock_irqrestore(&epic_lock, flags);
525365
526366 irqd_set_trigger_type(d, flow_type);
527367 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
@@ -532,6 +372,18 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d, · 4 unmodified lines
532372 return IRQ_SET_MASK_OK_NOCOPY;
533373 }
534374
375+#ifdef CONFIG_SMP
376+static int bcm63xx_internal_set_affinity(struct irq_data *data,
377+ const struct cpumask *dest,
378+ bool force)
379+{
380+ if (!irqd_irq_disabled(data))
381+ internal_irq_unmask(data, dest);
382+
383+ return 0;
384+}
385+#endif
386+
535387 static struct irq_chip bcm63xx_internal_irq_chip = {
536388 .name = "bcm63xx_ipic",
537389 .irq_mask = bcm63xx_internal_irq_mask,
@@ -554,12 +406,130 @@ static struct irqaction cpu_ip2_cascade_action = { · 16 unmodified lines
554406 .flags = IRQF_NO_THREAD,
555407 };
556408
409+#ifdef CONFIG_SMP
410+static struct irqaction cpu_ip3_cascade_action = {
411+ .handler = no_action,
412+ .name = "cascade_ip3",
413+ .flags = IRQF_NO_THREAD,
414+};
415+#endif
416+
557417 static struct irqaction cpu_ext_cascade_action = {
558418 .handler = no_action,
559419 .name = "cascade_extirq",
560420 .flags = IRQF_NO_THREAD,
561421 };
562422
423+static void bcm63xx_init_irq(void)
424+{
425+ int irq_bits;
426+
427+ irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
428+ irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
429+ irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF);
430+ irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);
431+
432+ switch (bcm63xx_get_cpu_id()) {
433+ case BCM3368_CPU_ID:
434+ irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
435+ irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
436+ irq_stat_addr[1] = 0;
437+ irq_stat_addr[1] = 0;
438+ irq_bits = 32;
439+ ext_irq_count = 4;
440+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
441+ break;
442+ case BCM6328_CPU_ID:
443+ irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
444+ irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
445+ irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1);
446+ irq_stat_addr[1] += PERF_IRQMASK_6328_REG(1);
447+ irq_bits = 64;
448+ ext_irq_count = 4;
449+ is_ext_irq_cascaded = 1;
450+ ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
451+ ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
452+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
453+ break;
454+ case BCM6338_CPU_ID:
455+ irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
456+ irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
457+ irq_stat_addr[1] = 0;
458+ irq_mask_addr[1] = 0;
459+ irq_bits = 32;
460+ ext_irq_count = 4;
461+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
462+ break;
463+ case BCM6345_CPU_ID:
464+ irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
465+ irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
466+ irq_stat_addr[1] = 0;
467+ irq_mask_addr[1] = 0;
468+ irq_bits = 32;
469+ ext_irq_count = 4;
470+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
471+ break;
472+ case BCM6348_CPU_ID:
473+ irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
474+ irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
475+ irq_stat_addr[1] = 0;
476+ irq_mask_addr[1] = 0;
477+ irq_bits = 32;
478+ ext_irq_count = 4;
479+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
480+ break;
481+ case BCM6358_CPU_ID:
482+ irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
483+ irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
484+ irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1);
485+ irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1);
486+ irq_bits = 32;
487+ ext_irq_count = 4;
488+ is_ext_irq_cascaded = 1;
489+ ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
490+ ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
491+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
492+ break;
493+ case BCM6362_CPU_ID:
494+ irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
495+ irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
496+ irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1);
497+ irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1);
498+ irq_bits = 64;
499+ ext_irq_count = 4;
500+ is_ext_irq_cascaded = 1;
501+ ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
502+ ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
503+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
504+ break;
505+ case BCM6368_CPU_ID:
506+ irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
507+ irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
508+ irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1);
509+ irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);
510+ irq_bits = 64;
511+ ext_irq_count = 6;
512+ is_ext_irq_cascaded = 1;
513+ ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
514+ ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
515+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
516+ ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
517+ break;
518+ default:
519+ BUG();
520+ }
521+
522+ if (irq_bits == 32) {
523+ dispatch_internal = __dispatch_internal_32;
524+ internal_irq_mask = __internal_irq_mask_32;
525+ internal_irq_unmask = __internal_irq_unmask_32;
526+ } else {
527+ dispatch_internal = __dispatch_internal_64;
528+ internal_irq_mask = __internal_irq_mask_64;
529+ internal_irq_unmask = __internal_irq_unmask_64;
530+ }
531+}
532+
563533 void __init arch_init_irq(void)
564534 {
565535 int i;
@@ -580,4 +550,14 @@ void __init arch_init_irq(void) · 14 unmodified lines
580550 }
581551
582552 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
553+#ifdef CONFIG_SMP
554+ if (is_ext_irq_cascaded) {
555+ setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
556+ bcm63xx_internal_irq_chip.irq_set_affinity =
557+ bcm63xx_internal_set_affinity;
558+
559+ cpumask_clear(irq_default_affinity);
560+ cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
561+ }
562+#endif
583563 }
arch/mips/bcm63xx/reset.c+0−60
@@ -125,8 +125,6 @@ · 124 unmodified lines
125125 #define BCM6368_RESET_PCIE 0
126126 #define BCM6368_RESET_PCIE_EXT 0
127127
128−#ifdef BCMCPU_RUNTIME_DETECT
129−
130128 /*
131129 * core reset bits
132130 */
@@ -188,64 +186,6 @@ static int __init bcm63xx_reset_bits_init(void) · 55 unmodified lines
188186
189187 return 0;
190188 }
191−#else
192−
193−#ifdef CONFIG_BCM63XX_CPU_3368
194−static const u32 bcm63xx_reset_bits[] = {
195− __GEN_RESET_BITS_TABLE(3368)
196−};
197−#define reset_reg PERF_SOFTRESET_6358_REG
198−#endif
199−
200−#ifdef CONFIG_BCM63XX_CPU_6328
201−static const u32 bcm63xx_reset_bits[] = {
202− __GEN_RESET_BITS_TABLE(6328)
203−};
204−#define reset_reg PERF_SOFTRESET_6328_REG
205−#endif
206−
207−#ifdef CONFIG_BCM63XX_CPU_6338
208−static const u32 bcm63xx_reset_bits[] = {
209− __GEN_RESET_BITS_TABLE(6338)
210−};
211−#define reset_reg PERF_SOFTRESET_REG
212−#endif
213−
214−#ifdef CONFIG_BCM63XX_CPU_6345
215−static const u32 bcm63xx_reset_bits[] = { };
216−#define reset_reg 0
217−#endif
218−
219−#ifdef CONFIG_BCM63XX_CPU_6348
220−static const u32 bcm63xx_reset_bits[] = {
221− __GEN_RESET_BITS_TABLE(6348)
222−};
223−#define reset_reg PERF_SOFTRESET_REG
224−#endif
225−
226−#ifdef CONFIG_BCM63XX_CPU_6358
227−static const u32 bcm63xx_reset_bits[] = {
228− __GEN_RESET_BITS_TABLE(6358)
229−};
230−#define reset_reg PERF_SOFTRESET_6358_REG
231−#endif
232−
233−#ifdef CONFIG_BCM63XX_CPU_6362
234−static const u32 bcm63xx_reset_bits[] = {
235− __GEN_RESET_BITS_TABLE(6362)
236−};
237−#define reset_reg PERF_SOFTRESET_6362_REG
238−#endif
239−
240−#ifdef CONFIG_BCM63XX_CPU_6368
241−static const u32 bcm63xx_reset_bits[] = {
242− __GEN_RESET_BITS_TABLE(6368)
243−};
244−#define reset_reg PERF_SOFTRESET_6368_REG
245−#endif
246−
247−static int __init bcm63xx_reset_bits_init(void) { return 0; }
248−#endif
249189
250190 static DEFINE_SPINLOCK(reset_mutex);
251191
arch/mips/boot/compressed/decompress.c+14−0
@@ -67,10 +67,24 @@ void error(char *x) · 66 unmodified lines
6767 #include "../../../../lib/decompress_unxz.c"
6868 #endif
6969
70+unsigned long __stack_chk_guard;
71+
72+void __stack_chk_guard_setup(void)
73+{
74+ __stack_chk_guard = 0x000a0dff;
75+}
76+
77+void __stack_chk_fail(void)
78+{
79+ error("stack-protector: Kernel stack is corrupted\n");
80+}
81+
7082 void decompress_kernel(unsigned long boot_heap_start)
7183 {
7284 unsigned long zimage_start, zimage_size;
7385
86+ __stack_chk_guard_setup();
87+
7488 zimage_start = (unsigned long)(&__image_begin);
7589 zimage_size = (unsigned long)(&__image_end) -
7690 (unsigned long)(&__image_begin);
arch/mips/cavium-octeon/executive/cvmx-helper-board.c+22−0
@@ -186,6 +186,15 @@ int cvmx_helper_board_get_mii_address(int ipd_port) · 185 unmodified lines
186186 return 7 - ipd_port;
187187 else
188188 return -1;
189+ case CVMX_BOARD_TYPE_CUST_DSR1000N:
190+ /*
191+ * Port 2 connects to Broadcom PHY (B5081). Other ports (0-1)
192+ * connect to a switch (BCM53115).
193+ */
194+ if (ipd_port == 2)
195+ return 8;
196+ else
197+ return -1;
189198 }
190199
191200 /* Some unknown board. Somebody forgot to update this function... */
@@ -274,6 +283,18 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port) · 82 unmodified lines
274283 return result;
275284 }
276285 break;
286+ case CVMX_BOARD_TYPE_CUST_DSR1000N:
287+ if (ipd_port == 0 || ipd_port == 1) {
288+ /* Ports 0 and 1 connect to a switch (BCM53115). */
289+ result.s.link_up = 1;
290+ result.s.full_duplex = 1;
291+ result.s.speed = 1000;
292+ return result;
293+ } else {
294+ /* Port 2 uses a Broadcom PHY (B5081). */
295+ is_broadcom_phy = 1;
296+ }
297+ break;
277298 }
278299
279300 phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
@@ -738,6 +759,7 @@ enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(vo · 458 unmodified lines
738759 case CVMX_BOARD_TYPE_LANAI2_G:
739760 case CVMX_BOARD_TYPE_NIC10E_66:
740761 case CVMX_BOARD_TYPE_UBNT_E100:
762+ case CVMX_BOARD_TYPE_CUST_DSR1000N:
741763 return USB_CLOCK_TYPE_CRYSTAL_12;
742764 case CVMX_BOARD_TYPE_NIC10E:
743765 return USB_CLOCK_TYPE_REF_12;
arch/mips/cavium-octeon/oct_ilm.c+1−2
@@ -194,8 +194,7 @@ err_irq: · 193 unmodified lines
194194 static __exit void oct_ilm_module_exit(void)
195195 {
196196 disable_timer(TIMER_NUM);
197− if (dir)
198− debugfs_remove_recursive(dir);
197+ debugfs_remove_recursive(dir);
199198 free_irq(OCTEON_IRQ_TIMER0 + TIMER_NUM, 0);
200199 }
201200
arch/mips/cavium-octeon/smp.c+12−11
@@ -84,9 +84,14 @@ static void octeon_smp_hotplug_setup(void) · 83 unmodified lines
8484 #ifdef CONFIG_HOTPLUG_CPU
8585 struct linux_app_boot_info *labi;
8686
87+ if (!setup_max_cpus)
88+ return;
89+
8790 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
88− if (labi->labi_signature != LABI_SIGNATURE)
89− panic("The bootloader version on this board is incorrect.");
91+ if (labi->labi_signature != LABI_SIGNATURE) {
92+ pr_info("The bootloader on this board does not support HOTPLUG_CPU.");
93+ return;
94+ }
9095
9196 octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
9297 #endif
@@ -129,7 +134,8 @@ static void octeon_smp_setup(void) · 36 unmodified lines
129134 * will assign CPU numbers for possible cores as well. Cores
130135 * are always consecutively numberd from 0.
131136 */
132− for (id = 0; id < num_cores && id < NR_CPUS; id++) {
137+ for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr &&
138+ id < num_cores && id < NR_CPUS; id++) {
133139 if (!(core_mask & (1 << id))) {
134140 set_cpu_possible(cpus, true);
135141 __cpu_number_map[id] = cpus;
@@ -192,14 +198,6 @@ static void octeon_init_secondary(void) · 56 unmodified lines
192198 */
193199 void octeon_prepare_cpus(unsigned int max_cpus)
194200 {
195−#ifdef CONFIG_HOTPLUG_CPU
196− struct linux_app_boot_info *labi;
197−
198− labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
199−
200− if (labi->labi_signature != LABI_SIGNATURE)
201− panic("The bootloader version on this board is incorrect.");
202−#endif
203201 /*
204202 * Only the low order mailbox bits are used for IPIs, leave
205203 * the other bits alone.
@@ -237,6 +235,9 @@ static int octeon_cpu_disable(void) · 31 unmodified lines
237235 if (cpu == 0)
238236 return -EBUSY;
239237
238+ if (!octeon_bootloader_entry_addr)
239+ return -ENOTSUPP;
240+
240241 set_cpu_online(cpu, false);
241242 cpu_clear(cpu, cpu_callin_map);
242243 local_irq_disable();
arch/mips/configs/loongson3_defconfig+1−1
@@ -1,6 +1,6 @@
11 CONFIG_MACH_LOONGSON=y
22 CONFIG_SWIOTLB=y
3−CONFIG_LEMOTE_MACH3A=y
3+CONFIG_LOONGSON_MACH3X=y
44 CONFIG_CPU_LOONGSON3=y
55 CONFIG_64BIT=y
66 CONFIG_PAGE_SIZE_16KB=y
arch/mips/include/asm/Kbuild+1−0
@@ -15,4 +15,5 @@ generic-y += segment.h · 14 unmodified lines
1515 generic-y += serial.h
1616 generic-y += trace_clock.h
1717 generic-y += ucontext.h
18+generic-y += user.h
1819 generic-y += xor.h
arch/mips/include/asm/addrspace.h+1−1
@@ -52,7 +52,7 @@ · 51 unmodified lines
5252 */
5353 #define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
5454 #define XPHYSADDR(a) ((_ACAST64_(a)) & \
55− _CONST64_(0x000000ffffffffff))
55+ _CONST64_(0x0000ffffffffffff))
5656
5757 #ifdef CONFIG_64BIT
5858
arch/mips/include/asm/asmmacro.h+31−0
@@ -10,6 +10,7 @@ · 9 unmodified lines
1010
1111 #include <asm/hazards.h>
1212 #include <asm/asm-offsets.h>
13+#include <asm/msa.h>
1314
1415 #ifdef CONFIG_32BIT
1516 #include <asm/asmmacro-32.h>
@@ -378,9 +379,19 @@ · 362 unmodified lines
378379 st_d 29, THREAD_FPR29, \thread
379380 st_d 30, THREAD_FPR30, \thread
380381 st_d 31, THREAD_FPR31, \thread
382+ .set push
383+ .set noat
384+ cfcmsa $1, MSA_CSR
385+ sw $1, THREAD_MSA_CSR(\thread)
386+ .set pop
381387 .endm
382388
383389 .macro msa_restore_all thread
390+ .set push
391+ .set noat
392+ lw $1, THREAD_MSA_CSR(\thread)
393+ ctcmsa MSA_CSR, $1
394+ .set pop
384395 ld_d 0, THREAD_FPR0, \thread
385396 ld_d 1, THREAD_FPR1, \thread
386397 ld_d 2, THREAD_FPR2, \thread
@@ -415,4 +426,24 @@ · 28 unmodified lines
415426 ld_d 31, THREAD_FPR31, \thread
416427 .endm
417428
429+ .macro msa_init_upper wd
430+#ifdef CONFIG_64BIT
431+ insert_d \wd, 1
432+#else
433+ insert_w \wd, 2
434+ insert_w \wd, 3
435+#endif
436+ .if 31-\wd
437+ msa_init_upper (\wd+1)
438+ .endif
439+ .endm
440+
441+ .macro msa_init_all_upper
442+ .set push
443+ .set noat
444+ not $1, zero
445+ msa_init_upper 0
446+ .set pop
447+ .endm
448+
418449 #endif /* _ASM_ASMMACRO_H */
arch/mips/include/asm/bitops.h+7−1
@@ -559,7 +559,13 @@ static inline int fls(int x) · 558 unmodified lines
559559 int r;
560560
561561 if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
562− __asm__("clz %0, %1" : "=r" (x) : "r" (x));
562+ __asm__(
563+ " .set push \n"
564+ " .set mips32 \n"
565+ " clz %0, %1 \n"
566+ " .set pop \n"
567+ : "=r" (x)
568+ : "r" (x));
563569
564570 return 32 - x;
565571 }
arch/mips/include/asm/cop2.h+8−0
@@ -32,6 +32,14 @@ extern void nlm_cop2_restore(struct nlm_cop2_state *); · 31 unmodified lines
3232 #define cop2_present 1
3333 #define cop2_lazy_restore 0
3434
35+#elif defined(CONFIG_CPU_LOONGSON3)
36+
37+#define cop2_save(r)
38+#define cop2_restore(r)
39+
40+#define cop2_present 1
41+#define cop2_lazy_restore 1
42+
3543 #else
3644
3745 #define cop2_present 0
arch/mips/include/asm/cpu-features.h+9−0
@@ -29,6 +29,15 @@ · 28 unmodified lines
2929 #ifndef cpu_has_eva
3030 #define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
3131 #endif
32+#ifndef cpu_has_htw
33+#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
34+#endif
35+#ifndef cpu_has_rixiex
36+#define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
37+#endif
38+#ifndef cpu_has_maar
39+#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
40+#endif
3241
3342 /*
3443 * For the moment we don't consider R6000 and R8000 so we can assume that
arch/mips/include/asm/cpu-info.h+3−2
@@ -44,8 +44,8 @@ struct cpuinfo_mips { · 43 unmodified lines
4444 /*
4545 * Capability and feature descriptor structure for MIPS CPU
4646 */
47− unsigned long options;
4847 unsigned long ases;
48+ unsigned long long options;
4949 unsigned int udelay_val;
5050 unsigned int processor_id;
5151 unsigned int fpu_id;
@@ -61,6 +61,7 @@ struct cpuinfo_mips { · 9 unmodified lines
6161 struct cache_desc scache; /* Secondary cache */
6262 struct cache_desc tcache; /* Tertiary/split secondary cache */
6363 int srsets; /* Shadow register sets */
64+ int package;/* physical package number */
6465 int core; /* physical core number */
6566 #ifdef CONFIG_64BIT
6667 int vmbits; /* Virtual memory size in bits */
@@ -115,7 +116,7 @@ struct proc_cpuinfo_notifier_args { · 48 unmodified lines
115116 #ifdef CONFIG_MIPS_MT_SMP
116117 # define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id)
117118 #else
118−# define cpu_vpe_id(cpuinfo) 0
119+# define cpu_vpe_id(cpuinfo) ({ (void)cpuinfo; 0; })
119120 #endif
120121
121122 #endif /* __ASM_CPU_INFO_H */
arch/mips/include/asm/cpu.h+33−28
@@ -233,6 +233,8 @@ · 232 unmodified lines
233233 #define PRID_REV_LOONGSON2E 0x0002
234234 #define PRID_REV_LOONGSON2F 0x0003
235235 #define PRID_REV_LOONGSON3A 0x0005
236+#define PRID_REV_LOONGSON3B_R1 0x0006
237+#define PRID_REV_LOONGSON3B_R2 0x0007
236238
237239 /*
238240 * Older processors used to encode processor version and revision in two
@@ -335,34 +337,37 @@ enum cpu_type_enum { · 96 unmodified lines
335337 /*
336338 * CPU Option encodings
337339 */
338−#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
339−#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */
340−#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
341−#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
342−#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
343−#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */
344−#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */
345−#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */
346−#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */
347−#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
348−#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
349−#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
350−#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
351−#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
352−#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
353−#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
354−#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
355−#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
356−#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
357−#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
358−#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
359−#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
360−#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
361−#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
362−#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
363−#define MIPS_CPU_TLBINV 0x02000000 /* CPU supports TLBINV/F */
364−#define MIPS_CPU_SEGMENTS 0x04000000 /* CPU supports Segmentation Control registers */
365−#define MIPS_CPU_EVA 0x80000000 /* CPU supports Enhanced Virtual Addressing */
340+#define MIPS_CPU_TLB 0x00000001ull /* CPU has TLB */
341+#define MIPS_CPU_4KEX 0x00000002ull /* "R4K" exception model */
342+#define MIPS_CPU_3K_CACHE 0x00000004ull /* R3000-style caches */
343+#define MIPS_CPU_4K_CACHE 0x00000008ull /* R4000-style caches */
344+#define MIPS_CPU_TX39_CACHE 0x00000010ull /* TX3900-style caches */
345+#define MIPS_CPU_FPU 0x00000020ull /* CPU has FPU */
346+#define MIPS_CPU_32FPR 0x00000040ull /* 32 dbl. prec. FP registers */
347+#define MIPS_CPU_COUNTER 0x00000080ull /* Cycle count/compare */
348+#define MIPS_CPU_WATCH 0x00000100ull /* watchpoint registers */
349+#define MIPS_CPU_DIVEC 0x00000200ull /* dedicated interrupt vector */
350+#define MIPS_CPU_VCE 0x00000400ull /* virt. coherence conflict possible */
351+#define MIPS_CPU_CACHE_CDEX_P 0x00000800ull /* Create_Dirty_Exclusive CACHE op */
352+#define MIPS_CPU_CACHE_CDEX_S 0x00001000ull /* ... same for seconary cache ... */
353+#define MIPS_CPU_MCHECK 0x00002000ull /* Machine check exception */
354+#define MIPS_CPU_EJTAG 0x00004000ull /* EJTAG exception */
355+#define MIPS_CPU_NOFPUEX 0x00008000ull /* no FPU exception */
356+#define MIPS_CPU_LLSC 0x00010000ull /* CPU has ll/sc instructions */
357+#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000ull /* P-cache subset enforced */
358+#define MIPS_CPU_PREFETCH 0x00040000ull /* CPU has usable prefetch */
359+#define MIPS_CPU_VINT 0x00080000ull /* CPU supports MIPSR2 vectored interrupts */
360+#define MIPS_CPU_VEIC 0x00100000ull /* CPU supports MIPSR2 external interrupt controller mode */
361+#define MIPS_CPU_ULRI 0x00200000ull /* CPU has ULRI feature */
362+#define MIPS_CPU_PCI 0x00400000ull /* CPU has Perf Ctr Int indicator */
363+#define MIPS_CPU_RIXI 0x00800000ull /* CPU has TLB Read/eXec Inhibit */
364+#define MIPS_CPU_MICROMIPS 0x01000000ull /* CPU has microMIPS capability */
365+#define MIPS_CPU_TLBINV 0x02000000ull /* CPU supports TLBINV/F */
366+#define MIPS_CPU_SEGMENTS 0x04000000ull /* CPU supports Segmentation Control registers */
367+#define MIPS_CPU_EVA 0x80000000ull /* CPU supports Enhanced Virtual Addressing */
368+#define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */
369+#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
370+#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */
366371
367372 /*
368373 * CPU ASE encodings
arch/mips/include/asm/elf.h+0−17
@@ -339,23 +339,6 @@ do { \ · 338 unmodified lines
339339
340340 #endif /* CONFIG_64BIT */
341341
342−struct pt_regs;
343−struct task_struct;
344−
345−extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs);
346−extern int dump_task_regs(struct task_struct *, elf_gregset_t *);
347−extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
348−
349−#ifndef ELF_CORE_COPY_REGS
350−#define ELF_CORE_COPY_REGS(elf_regs, regs) \
351− elf_dump_regs((elf_greg_t *)&(elf_regs), regs);
352−#endif
353−#ifndef ELF_CORE_COPY_TASK_REGS
354−#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
355−#endif
356−#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \
357− dump_task_fpu(tsk, elf_fpregs)
358−
359342 #define CORE_DUMP_USE_REGSET
360343 #define ELF_EXEC_PAGESIZE PAGE_SIZE
361344
arch/mips/include/asm/fpu.h+12−7
@@ -21,6 +21,7 @@ · 20 unmodified lines
2121 #include <asm/hazards.h>
2222 #include <asm/processor.h>
2323 #include <asm/current.h>
24+#include <asm/msa.h>
2425
2526 #ifdef CONFIG_MIPS_MT_FPAFF
2627 #include <asm/mips_mt.h>
@@ -141,13 +142,21 @@ static inline int own_fpu(int restore) · 114 unmodified lines
141142 static inline void lose_fpu(int save)
142143 {
143144 preempt_disable();
144− if (is_fpu_owner()) {
145+ if (is_msa_enabled()) {
146+ if (save) {
147+ save_msa(current);
148+ asm volatile("cfc1 %0, $31"
149+ : "=r"(current->thread.fpu.fcr31));
150+ }
151+ disable_msa();
152+ clear_thread_flag(TIF_USEDMSA);
153+ } else if (is_fpu_owner()) {
145154 if (save)
146155 _save_fp(current);
147− KSTK_STATUS(current) &= ~ST0_CU1;
148− clear_thread_flag(TIF_USEDFPU);
149156 __disable_fpu();
150157 }
158+ KSTK_STATUS(current) &= ~ST0_CU1;
159+ clear_thread_flag(TIF_USEDFPU);
151160 preempt_enable();
152161 }
153162
@@ -155,8 +164,6 @@ static inline int init_fpu(void) · 1 unmodified line
155164 {
156165 int ret = 0;
157166
158− preempt_disable();
159−
160167 if (cpu_has_fpu) {
161168 ret = __own_fpu();
162169 if (!ret)
@@ -164,8 +171,6 @@ static inline int init_fpu(void) · 1 unmodified line
164171 } else
165172 fpu_emulator_init_fpu();
166173
167− preempt_enable();
168−
169174 return ret;
170175 }
171176
arch/mips/include/asm/gic.h+15−26
@@ -14,6 +14,8 @@ · 13 unmodified lines
1414 #include <linux/bitmap.h>
1515 #include <linux/threads.h>
1616
17+#include <irq.h>
18+
1719 #undef GICISBYTELITTLEENDIAN
1820
1921 /* Constants */
@@ -22,8 +24,6 @@ · 2 unmodified lines
2224 #define GIC_TRIG_EDGE 1
2325 #define GIC_TRIG_LEVEL 0
2426
25−#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
26−
2727 #define MSK(n) ((1 << (n)) - 1)
2828 #define REG32(addr) (*(volatile unsigned int *) (addr))
2929 #define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
@@ -43,18 +43,17 @@ · 13 unmodified lines
4343 #ifdef GICISBYTELITTLEENDIAN
4444 #define GICREAD(reg, data) ((data) = (reg), (data) = le32_to_cpu(data))
4545 #define GICWRITE(reg, data) ((reg) = cpu_to_le32(data))
46−#define GICBIS(reg, bits) \
47− ({unsigned int data; \
48− GICREAD(reg, data); \
49− data |= bits; \
50− GICWRITE(reg, data); \
51− })
52−
5346 #else
5447 #define GICREAD(reg, data) ((data) = (reg))
5548 #define GICWRITE(reg, data) ((reg) = (data))
56−#define GICBIS(reg, bits) ((reg) |= (bits))
5749 #endif
50+#define GICBIS(reg, mask, bits) \
51+ do { u32 data; \
52+ GICREAD((reg), data); \
53+ data &= ~(mask); \
54+ data |= ((bits) & (mask)); \
55+ GICWRITE((reg), data); \
56+ } while (0)
5857
5958
6059 /* GIC Address Space */
@@ -170,13 +169,15 @@ · 109 unmodified lines
170169 #define GIC_SH_SET_POLARITY_OFS 0x0100
171170 #define GIC_SET_POLARITY(intr, pol) \
172171 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
173− GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr))
172+ GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
173+ (pol) << GIC_INTR_BIT(intr))
174174
175175 /* Triggering : Reset Value is always 0 */
176176 #define GIC_SH_SET_TRIGGER_OFS 0x0180
177177 #define GIC_SET_TRIGGER(intr, trig) \
178178 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
179− GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr))
179+ GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
180+ (trig) << GIC_INTR_BIT(intr))
180181
181182 /* Mask manipulation */
182183 #define GIC_SH_SMASK_OFS 0x0380
@@ -306,18 +307,6 @@ · 123 unmodified lines
306307 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
307308 GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
308309
309−struct gic_pcpu_mask {
310− DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
311−};
312−
313−struct gic_pending_regs {
314− DECLARE_BITMAP(pending, GIC_NUM_INTRS);
315−};
316−
317−struct gic_intrmask_regs {
318− DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
319−};
320−
321310 /*
322311 * Interrupt Meta-data specification. The ipiflag helps
323312 * in building ipi_map.
@@ -329,8 +318,7 @@ struct gic_intr_map { · 5 unmodified lines
329318 unsigned int polarity; /* Polarity : +/- */
330319 unsigned int trigtype; /* Trigger : Edge/Levl */
331320 unsigned int flags; /* Misc flags */
332−#define GIC_FLAG_IPI 0x01
333−#define GIC_FLAG_TRANSPARENT 0x02
321+#define GIC_FLAG_TRANSPARENT 0x01
334322 };
335323
336324 /*
@@ -386,6 +374,7 @@ extern unsigned int plat_ipi_call_int_xlate(unsigned int); · 49 unmodified lines
386374 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
387375 extern void gic_bind_eic_interrupt(int irq, int set);
388376 extern unsigned int gic_get_timer_pending(void);
377+extern void gic_get_int_mask(unsigned long *dst, const unsigned long *src);
389378 extern unsigned int gic_get_int(void);
390379 extern void gic_enable_interrupt(int irq_vec);
391380 extern void gic_disable_interrupt(int irq_vec);
arch/mips/include/asm/maar.h+109−0
@@ -0,0 +1,109 @@
1+/*
2+ * Copyright (C) 2014 Imagination Technologies
3+ * Author: Paul Burton <paul.burton@imgtec.com>
4+ *
5+ * This program is free software; you can redistribute it and/or modify it
6+ * under the terms of the GNU General Public License as published by the
7+ * Free Software Foundation; either version 2 of the License, or (at your
8+ * option) any later version.
9+ */
10+
11+#ifndef __MIPS_ASM_MIPS_MAAR_H__
12+#define __MIPS_ASM_MIPS_MAAR_H__
13+
14+#include <asm/hazards.h>
15+#include <asm/mipsregs.h>
16+
17+/**
18+ * platform_maar_init() - perform platform-level MAAR configuration
19+ * @num_pairs: The number of MAAR pairs present in the system.
20+ *
21+ * Platforms should implement this function such that it configures as many
22+ * MAAR pairs as required, from 0 up to the maximum of num_pairs-1, and returns
23+ * the number that were used. Any further MAARs will be configured to be
24+ * invalid. The default implementation of this function will simply indicate
25+ * that it has configured 0 MAAR pairs.
26+ *
27+ * Return: The number of MAAR pairs configured.
28+ */
29+unsigned __weak platform_maar_init(unsigned num_pairs);
30+
31+/**
32+ * write_maar_pair() - write to a pair of MAARs
33+ * @idx: The index of the pair (ie. use MAARs idx*2 & (idx*2)+1).
34+ * @lower: The lowest address that the MAAR pair will affect. Must be
35+ * aligned to a 2^16 byte boundary.
36+ * @upper: The highest address that the MAAR pair will affect. Must be
37+ * aligned to one byte before a 2^16 byte boundary.
38+ * @attrs: The accessibility attributes to program, eg. MIPS_MAAR_S. The
39+ * MIPS_MAAR_V attribute will automatically be set.
40+ *
41+ * Program the pair of MAAR registers specified by idx to apply the attributes
42+ * specified by attrs to the range of addresses from lower to higher.
43+ */
44+static inline void write_maar_pair(unsigned idx, phys_addr_t lower,
45+ phys_addr_t upper, unsigned attrs)
46+{
47+ /* Addresses begin at bit 16, but are shifted right 4 bits */
48+ BUG_ON(lower & (0xffff | ~(MIPS_MAAR_ADDR << 4)));
49+ BUG_ON(((upper & 0xffff) != 0xffff)
50+ || ((upper & ~0xffffull) & ~(MIPS_MAAR_ADDR << 4)));
51+
52+ /* Automatically set MIPS_MAAR_V */
53+ attrs |= MIPS_MAAR_V;
54+
55+ /* Write the upper address & attributes (only MIPS_MAAR_V matters) */
56+ write_c0_maari(idx << 1);
57+ back_to_back_c0_hazard();
58+ write_c0_maar(((upper >> 4) & MIPS_MAAR_ADDR) | attrs);
59+ back_to_back_c0_hazard();
60+
61+ /* Write the lower address & attributes */
62+ write_c0_maari((idx << 1) | 0x1);
63+ back_to_back_c0_hazard();
64+ write_c0_maar((lower >> 4) | attrs);
65+ back_to_back_c0_hazard();
66+}
67+
68+/**
69+ * struct maar_config - MAAR configuration data
70+ * @lower: The lowest address that the MAAR pair will affect. Must be
71+ * aligned to a 2^16 byte boundary.
72+ * @upper: The highest address that the MAAR pair will affect. Must be
73+ * aligned to one byte before a 2^16 byte boundary.
74+ * @attrs: The accessibility attributes to program, eg. MIPS_MAAR_S. The
75+ * MIPS_MAAR_V attribute will automatically be set.
76+ *
77+ * Describes the configuration of a pair of Memory Accessibility Attribute
78+ * Registers - applying attributes from attrs to the range of physical
79+ * addresses from lower to upper inclusive.
80+ */
81+struct maar_config {
82+ phys_addr_t lower;
83+ phys_addr_t upper;
84+ unsigned attrs;
85+};
86+
87+/**
88+ * maar_config() - configure MAARs according to provided data
89+ * @cfg: Pointer to an array of struct maar_config.
90+ * @num_cfg: The number of structs in the cfg array.
91+ * @num_pairs: The number of MAAR pairs present in the system.
92+ *
93+ * Configures as many MAARs as are present and specified in the cfg
94+ * array with the values taken from the cfg array.
95+ *
96+ * Return: The number of MAAR pairs configured.
97+ */
98+static inline unsigned maar_config(const struct maar_config *cfg,
99+ unsigned num_cfg, unsigned num_pairs)
100+{
101+ unsigned i;
102+
103+ for (i = 0; i < min(num_cfg, num_pairs); i++)
104+ write_maar_pair(i, cfg[i].lower, cfg[i].upper, cfg[i].attrs);
105+
106+ return i;
107+}
108+
109+#endif /* __MIPS_ASM_MIPS_MAAR_H__ */
arch/mips/include/asm/mach-au1x00/au1000.h+1082−1433
@@ -34,1529 +34,1178 @@ · 33 unmodified lines
3434 #ifndef _AU1000_H_
3535 #define _AU1000_H_
3636
37+/* SOC Interrupt numbers */
38+/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
39+#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
40+#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
41+#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
42+#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
43+#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
3744
38−#ifndef _LANGUAGE_ASSEMBLY
45+/* Au1300-style (GPIC): 1 controller with up to 128 sources */
46+#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
47+#define ALCHEMY_GPIC_INT_NUM 128
48+#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
3949
40−#include <linux/delay.h>
41−#include <linux/types.h>
50+/* common clock names, shared among all variants. AUXPLL2 is Au1300 */
51+#define ALCHEMY_ROOT_CLK "root_clk"
52+#define ALCHEMY_CPU_CLK "cpu_clk"
53+#define ALCHEMY_AUXPLL_CLK "auxpll_clk"
54+#define ALCHEMY_AUXPLL2_CLK "auxpll2_clk"
55+#define ALCHEMY_SYSBUS_CLK "sysbus_clk"
56+#define ALCHEMY_PERIPH_CLK "periph_clk"
57+#define ALCHEMY_MEM_CLK "mem_clk"
58+#define ALCHEMY_LR_CLK "lr_clk"
59+#define ALCHEMY_FG0_CLK "fg0_clk"
60+#define ALCHEMY_FG1_CLK "fg1_clk"
61+#define ALCHEMY_FG2_CLK "fg2_clk"
62+#define ALCHEMY_FG3_CLK "fg3_clk"
63+#define ALCHEMY_FG4_CLK "fg4_clk"
64+#define ALCHEMY_FG5_CLK "fg5_clk"
4265
43−#include <linux/io.h>
44−#include <linux/irq.h>
66+/* Au1300 peripheral interrupt numbers */
67+#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
68+#define AU1300_UART1_INT (AU1300_FIRST_INT + 17)
69+#define AU1300_UART2_INT (AU1300_FIRST_INT + 25)
70+#define AU1300_UART3_INT (AU1300_FIRST_INT + 27)
71+#define AU1300_SD1_INT (AU1300_FIRST_INT + 32)
72+#define AU1300_SD2_INT (AU1300_FIRST_INT + 38)
73+#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48)
74+#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52)
75+#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56)
76+#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60)
77+#define AU1300_NAND_INT (AU1300_FIRST_INT + 62)
78+#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75)
79+#define AU1300_MMU_INT (AU1300_FIRST_INT + 76)
80+#define AU1300_MPU_INT (AU1300_FIRST_INT + 77)
81+#define AU1300_GPU_INT (AU1300_FIRST_INT + 78)
82+#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79)
83+#define AU1300_TOY_INT (AU1300_FIRST_INT + 80)
84+#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81)
85+#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82)
86+#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83)
87+#define AU1300_RTC_INT (AU1300_FIRST_INT + 84)
88+#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85)
89+#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86)
90+#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87)
91+#define AU1300_UART0_INT (AU1300_FIRST_INT + 88)
92+#define AU1300_SD0_INT (AU1300_FIRST_INT + 89)
93+#define AU1300_USB_INT (AU1300_FIRST_INT + 90)
94+#define AU1300_LCD_INT (AU1300_FIRST_INT + 91)
95+#define AU1300_BSA_INT (AU1300_FIRST_INT + 92)
96+#define AU1300_MPE_INT (AU1300_FIRST_INT + 93)
97+#define AU1300_ITE_INT (AU1300_FIRST_INT + 94)
98+#define AU1300_AES_INT (AU1300_FIRST_INT + 95)
99+#define AU1300_CIM_INT (AU1300_FIRST_INT + 96)
45100
46−#include <asm/cpu.h>
101+/**********************************************************************/
47102
48−/* cpu pipeline flush */
49−void static inline au_sync(void)
50−{
51− __asm__ volatile ("sync");
52−}
103+/*
104+ * Physical base addresses for integrated peripherals
105+ * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
106+ */
53107
54−void static inline au_sync_udelay(int us)
55−{
56− __asm__ volatile ("sync");
57− udelay(us);
58−}
108+#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
109+#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
110+#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
111+#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
112+#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
113+#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
114+#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
115+#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
116+#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
117+#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
118+#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
119+#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
120+#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */
121+#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
122+#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
123+#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
124+#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
125+#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
126+#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */
127+#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
128+#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
129+#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
130+#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
131+#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
132+#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
133+#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
134+#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
135+#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
136+#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
137+#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
138+#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
139+#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
140+#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
141+#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
142+#define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */
143+#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
144+#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
145+#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
146+#define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */
147+#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
148+#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
149+#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
150+#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */
151+#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
152+#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
153+#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
154+#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
155+#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
156+#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
157+#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */
158+#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */
159+#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
160+#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
161+#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */
162+#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
163+#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
164+#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
165+#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
166+#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
167+#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
168+#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
169+#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
170+#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
171+#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
172+#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
173+#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
174+#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
175+#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
176+#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
177+#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
178+#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
179+#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
180+#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
181+#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */
182+#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
183+#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
184+#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
185+#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
186+#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */
187+#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */
188+#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */
59189
60−void static inline au_sync_delay(int ms)
61−{
62− __asm__ volatile ("sync");
63− mdelay(ms);
64−}
190+/**********************************************************************/
65191
66−void static inline au_writeb(u8 val, unsigned long reg)
67−{
68− *(volatile u8 *)reg = val;
69−}
70192
71−void static inline au_writew(u16 val, unsigned long reg)
72−{
73− *(volatile u16 *)reg = val;
74−}
193+/*
194+ * Au1300 GPIO+INT controller (GPIC) register offsets and bits
195+ * Registers are 128bits (0x10 bytes), divided into 4 "banks".
196+ */
197+#define AU1300_GPIC_PINVAL 0x0000
198+#define AU1300_GPIC_PINVALCLR 0x0010
199+#define AU1300_GPIC_IPEND 0x0020
200+#define AU1300_GPIC_PRIENC 0x0030
201+#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */
202+#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */
203+#define AU1300_GPIC_DMASEL 0x0060
204+#define AU1300_GPIC_DEVSEL 0x0080
205+#define AU1300_GPIC_DEVCLR 0x0090
206+#define AU1300_GPIC_RSTVAL 0x00a0
207+/* pin configuration space. one 32bit register for up to 128 IRQs */
208+#define AU1300_GPIC_PINCFG 0x1000
75209
76−void static inline au_writel(u32 val, unsigned long reg)
77−{
78− *(volatile u32 *)reg = val;
79−}
210+#define GPIC_GPIO_TO_BIT(gpio) \
211+ (1 << ((gpio) & 0x1f))
80212
81−static inline u8 au_readb(unsigned long reg)
82−{
83− return *(volatile u8 *)reg;
84−}
213+#define GPIC_GPIO_BANKOFF(gpio) \
214+ (((gpio) >> 5) * 4)
85215
86−static inline u16 au_readw(unsigned long reg)
87−{
88− return *(volatile u16 *)reg;
89−}
216+/* Pin Control bits: who owns the pin, what does it do */
217+#define GPIC_CFG_PC_GPIN 0
218+#define GPIC_CFG_PC_DEV 1
219+#define GPIC_CFG_PC_GPOLOW 2
220+#define GPIC_CFG_PC_GPOHIGH 3
221+#define GPIC_CFG_PC_MASK 3
90222
91−static inline u32 au_readl(unsigned long reg)
92−{
93− return *(volatile u32 *)reg;
94−}
223+/* assign pin to MIPS IRQ line */
224+#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2)
225+#define GPIC_CFG_IL_MASK (3 << 2)
95226
96−/* Early Au1000 have a write-only SYS_CPUPLL register. */
97−static inline int au1xxx_cpu_has_pll_wo(void)
98−{
99− switch (read_c0_prid()) {
100− case 0x00030100: /* Au1000 DA */
101− case 0x00030201: /* Au1000 HA */
102− case 0x00030202: /* Au1000 HB */
103− return 1;
104− }
105− return 0;
106−}
227+/* pin interrupt type setup */
228+#define GPIC_CFG_IC_OFF (0 << 4)
229+#define GPIC_CFG_IC_LEVEL_LOW (1 << 4)
230+#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4)
231+#define GPIC_CFG_IC_EDGE_FALL (5 << 4)
232+#define GPIC_CFG_IC_EDGE_RISE (6 << 4)
233+#define GPIC_CFG_IC_EDGE_BOTH (7 << 4)
234+#define GPIC_CFG_IC_MASK (7 << 4)
107235
108−/* does CPU need CONFIG[OD] set to fix tons of errata? */
109−static inline int au1xxx_cpu_needs_config_od(void)
110−{
111− /*
112− * c0_config.od (bit 19) was write only (and read as 0) on the
113− * early revisions of Alchemy SOCs. It disables the bus trans-
114− * action overlapping and needs to be set to fix various errata.
115− */
116− switch (read_c0_prid()) {
117− case 0x00030100: /* Au1000 DA */
118− case 0x00030201: /* Au1000 HA */
119− case 0x00030202: /* Au1000 HB */
120− case 0x01030200: /* Au1500 AB */
121− /*
122− * Au1100/Au1200 errata actually keep silence about this bit,
123− * so we set it just in case for those revisions that require
124− * it to be set according to the (now gone) cpu_table.
125− */
126− case 0x02030200: /* Au1100 AB */
127− case 0x02030201: /* Au1100 BA */
128− case 0x02030202: /* Au1100 BC */
129− case 0x04030201: /* Au1200 AC */
130− return 1;
131− }
132− return 0;
133−}
236+/* allow interrupt to wake cpu from 'wait' */
237+#define GPIC_CFG_IDLEWAKE (1 << 7)
134238
135−#define ALCHEMY_CPU_UNKNOWN -1
136−#define ALCHEMY_CPU_AU1000 0
137−#define ALCHEMY_CPU_AU1500 1
138−#define ALCHEMY_CPU_AU1100 2
139−#define ALCHEMY_CPU_AU1550 3
140−#define ALCHEMY_CPU_AU1200 4
141−#define ALCHEMY_CPU_AU1300 5
239+/***********************************************************************/
142240
143−static inline int alchemy_get_cputype(void)
144−{
145− switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) {
146− case 0x00030000:
147− return ALCHEMY_CPU_AU1000;
148− break;
149− case 0x01030000:
150− return ALCHEMY_CPU_AU1500;
151− break;
152− case 0x02030000:
153− return ALCHEMY_CPU_AU1100;
154− break;
155− case 0x03030000:
156− return ALCHEMY_CPU_AU1550;
157− break;
158− case 0x04030000:
159− case 0x05030000:
160− return ALCHEMY_CPU_AU1200;
161− break;
162− case 0x800c0000:
163− return ALCHEMY_CPU_AU1300;
164− break;
165− }
241+/* Au1000 SDRAM memory controller register offsets */
242+#define AU1000_MEM_SDMODE0 0x0000
243+#define AU1000_MEM_SDMODE1 0x0004
244+#define AU1000_MEM_SDMODE2 0x0008
245+#define AU1000_MEM_SDADDR0 0x000C
246+#define AU1000_MEM_SDADDR1 0x0010
247+#define AU1000_MEM_SDADDR2 0x0014
248+#define AU1000_MEM_SDREFCFG 0x0018
249+#define AU1000_MEM_SDPRECMD 0x001C
250+#define AU1000_MEM_SDAUTOREF 0x0020
251+#define AU1000_MEM_SDWRMD0 0x0024
252+#define AU1000_MEM_SDWRMD1 0x0028
253+#define AU1000_MEM_SDWRMD2 0x002C
254+#define AU1000_MEM_SDSLEEP 0x0030
255+#define AU1000_MEM_SDSMCKE 0x0034
166256
167− return ALCHEMY_CPU_UNKNOWN;
168−}
257+/* MEM_SDMODE register content definitions */
258+#define MEM_SDMODE_F (1 << 22)
259+#define MEM_SDMODE_SR (1 << 21)
260+#define MEM_SDMODE_BS (1 << 20)
261+#define MEM_SDMODE_RS (3 << 18)
262+#define MEM_SDMODE_CS (7 << 15)
263+#define MEM_SDMODE_TRAS (15 << 11)
264+#define MEM_SDMODE_TMRD (3 << 9)
265+#define MEM_SDMODE_TWR (3 << 7)
266+#define MEM_SDMODE_TRP (3 << 5)
267+#define MEM_SDMODE_TRCD (3 << 3)
268+#define MEM_SDMODE_TCL (7 << 0)
169269
170−/* return number of uarts on a given cputype */
171−static inline int alchemy_get_uarts(int type)
172−{
173− switch (type) {
174− case ALCHEMY_CPU_AU1000:
175− case ALCHEMY_CPU_AU1300:
176− return 4;
177− case ALCHEMY_CPU_AU1500:
178− case ALCHEMY_CPU_AU1200:
179− return 2;
180− case ALCHEMY_CPU_AU1100:
181− case ALCHEMY_CPU_AU1550:
182− return 3;
183− }
184− return 0;
185−}
270+#define MEM_SDMODE_BS_2Bank (0 << 20)
271+#define MEM_SDMODE_BS_4Bank (1 << 20)
272+#define MEM_SDMODE_RS_11Row (0 << 18)
273+#define MEM_SDMODE_RS_12Row (1 << 18)
274+#define MEM_SDMODE_RS_13Row (2 << 18)
275+#define MEM_SDMODE_RS_N(N) ((N) << 18)
276+#define MEM_SDMODE_CS_7Col (0 << 15)
277+#define MEM_SDMODE_CS_8Col (1 << 15)
278+#define MEM_SDMODE_CS_9Col (2 << 15)
279+#define MEM_SDMODE_CS_10Col (3 << 15)
280+#define MEM_SDMODE_CS_11Col (4 << 15)
281+#define MEM_SDMODE_CS_N(N) ((N) << 15)
282+#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
283+#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
284+#define MEM_SDMODE_TWR_N(N) ((N) << 7)
285+#define MEM_SDMODE_TRP_N(N) ((N) << 5)
286+#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
287+#define MEM_SDMODE_TCL_N(N) ((N) << 0)
186288
187−/* enable an UART block if it isn't already */
188−static inline void alchemy_uart_enable(u32 uart_phys)
189−{
190− void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
289+/* MEM_SDADDR register contents definitions */
290+#define MEM_SDADDR_E (1 << 20)
291+#define MEM_SDADDR_CSBA (0x03FF << 10)
292+#define MEM_SDADDR_CSMASK (0x03FF << 0)
293+#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
294+#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
191295
192− /* reset, enable clock, deassert reset */
193− if ((__raw_readl(addr + 0x100) & 3) != 3) {
194− __raw_writel(0, addr + 0x100);
195− wmb();
196− __raw_writel(1, addr + 0x100);
197− wmb();
198− }
199− __raw_writel(3, addr + 0x100);
200− wmb();
201−}
296+/* MEM_SDREFCFG register content definitions */
297+#define MEM_SDREFCFG_TRC (15 << 28)
298+#define MEM_SDREFCFG_TRPM (3 << 26)
299+#define MEM_SDREFCFG_E (1 << 25)
300+#define MEM_SDREFCFG_RE (0x1ffffff << 0)
301+#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
302+#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
303+#define MEM_SDREFCFG_REF_N(N) (N)
202304
203−static inline void alchemy_uart_disable(u32 uart_phys)
204−{
205− void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
206− __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */
207− wmb();
208−}
305+/* Au1550 SDRAM Register Offsets */
306+#define AU1550_MEM_SDMODE0 0x0800
307+#define AU1550_MEM_SDMODE1 0x0808
308+#define AU1550_MEM_SDMODE2 0x0810
309+#define AU1550_MEM_SDADDR0 0x0820
310+#define AU1550_MEM_SDADDR1 0x0828
311+#define AU1550_MEM_SDADDR2 0x0830
312+#define AU1550_MEM_SDCONFIGA 0x0840
313+#define AU1550_MEM_SDCONFIGB 0x0848
314+#define AU1550_MEM_SDSTAT 0x0850
315+#define AU1550_MEM_SDERRADDR 0x0858
316+#define AU1550_MEM_SDSTRIDE0 0x0860
317+#define AU1550_MEM_SDSTRIDE1 0x0868
318+#define AU1550_MEM_SDSTRIDE2 0x0870
319+#define AU1550_MEM_SDWRMD0 0x0880
320+#define AU1550_MEM_SDWRMD1 0x0888
321+#define AU1550_MEM_SDWRMD2 0x0890
322+#define AU1550_MEM_SDPRECMD 0x08C0
323+#define AU1550_MEM_SDAUTOREF 0x08C8
324+#define AU1550_MEM_SDSREF 0x08D0
325+#define AU1550_MEM_SDSLEEP MEM_SDSREF
209326
210−static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
211−{
212− void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
213− int timeout, i;
327+/* Static Bus Controller register offsets */
328+#define AU1000_MEM_STCFG0 0x000
329+#define AU1000_MEM_STTIME0 0x004
330+#define AU1000_MEM_STADDR0 0x008
331+#define AU1000_MEM_STCFG1 0x010
332+#define AU1000_MEM_STTIME1 0x014
333+#define AU1000_MEM_STADDR1 0x018
334+#define AU1000_MEM_STCFG2 0x020
335+#define AU1000_MEM_STTIME2 0x024
336+#define AU1000_MEM_STADDR2 0x028
337+#define AU1000_MEM_STCFG3 0x030
338+#define AU1000_MEM_STTIME3 0x034
339+#define AU1000_MEM_STADDR3 0x038
340+#define AU1000_MEM_STNDCTL 0x100
341+#define AU1000_MEM_STSTAT 0x104
214342
215− /* check LSR TX_EMPTY bit */
216− timeout = 0xffffff;
217− do {
218− if (__raw_readl(base + 0x1c) & 0x20)
219− break;
220− /* slow down */
221− for (i = 10000; i; i--)
222− asm volatile ("nop");
223− } while (--timeout);
343+#define MEM_STNAND_CMD 0x0
344+#define MEM_STNAND_ADDR 0x4
345+#define MEM_STNAND_DATA 0x20
224346
225− __raw_writel(c, base + 0x04); /* tx */
226− wmb();
227−}
228347
229−/* return number of ethernet MACs on a given cputype */
230−static inline int alchemy_get_macs(int type)
231−{
232− switch (type) {
233− case ALCHEMY_CPU_AU1000:
234− case ALCHEMY_CPU_AU1500:
235− case ALCHEMY_CPU_AU1550:
236− return 2;
237− case ALCHEMY_CPU_AU1100:
238− return 1;
239− }
240− return 0;
241−}
348+/* Programmable Counters 0 and 1 */
349+#define AU1000_SYS_CNTRCTRL 0x14
350+# define SYS_CNTRL_E1S (1 << 23)
351+# define SYS_CNTRL_T1S (1 << 20)
352+# define SYS_CNTRL_M21 (1 << 19)
353+# define SYS_CNTRL_M11 (1 << 18)
354+# define SYS_CNTRL_M01 (1 << 17)
355+# define SYS_CNTRL_C1S (1 << 16)
356+# define SYS_CNTRL_BP (1 << 14)
357+# define SYS_CNTRL_EN1 (1 << 13)
358+# define SYS_CNTRL_BT1 (1 << 12)
359+# define SYS_CNTRL_EN0 (1 << 11)
360+# define SYS_CNTRL_BT0 (1 << 10)
361+# define SYS_CNTRL_E0 (1 << 8)
362+# define SYS_CNTRL_E0S (1 << 7)
363+# define SYS_CNTRL_32S (1 << 5)
364+# define SYS_CNTRL_T0S (1 << 4)
365+# define SYS_CNTRL_M20 (1 << 3)
366+# define SYS_CNTRL_M10 (1 << 2)
367+# define SYS_CNTRL_M00 (1 << 1)
368+# define SYS_CNTRL_C0S (1 << 0)
242369
243−/* arch/mips/au1000/common/clocks.c */
244−extern void set_au1x00_speed(unsigned int new_freq);
245−extern unsigned int get_au1x00_speed(void);
246−extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
247−extern unsigned long get_au1x00_uart_baud_base(void);
248−extern unsigned long au1xxx_calc_clock(void);
370+/* Programmable Counter 0 Registers */
371+#define AU1000_SYS_TOYTRIM 0x00
372+#define AU1000_SYS_TOYWRITE 0x04
373+#define AU1000_SYS_TOYMATCH0 0x08
374+#define AU1000_SYS_TOYMATCH1 0x0c
375+#define AU1000_SYS_TOYMATCH2 0x10
376+#define AU1000_SYS_TOYREAD 0x40
249377
250−/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
251−void alchemy_sleep_au1000(void);
252−void alchemy_sleep_au1550(void);
253−void alchemy_sleep_au1300(void);
254−void au_sleep(void);
378+/* Programmable Counter 1 Registers */
379+#define AU1000_SYS_RTCTRIM 0x44
380+#define AU1000_SYS_RTCWRITE 0x48
381+#define AU1000_SYS_RTCMATCH0 0x4c
382+#define AU1000_SYS_RTCMATCH1 0x50
383+#define AU1000_SYS_RTCMATCH2 0x54
384+#define AU1000_SYS_RTCREAD 0x58
255385
256−/* USB: drivers/usb/host/alchemy-common.c */
257−enum alchemy_usb_block {
258− ALCHEMY_USB_OHCI0,
259− ALCHEMY_USB_UDC0,
260− ALCHEMY_USB_EHCI0,
261− ALCHEMY_USB_OTG0,
262− ALCHEMY_USB_OHCI1,
263−};
264−int alchemy_usb_control(int block, int enable);
265386
266−/* PCI controller platform data */
267−struct alchemy_pci_platdata {
268− int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
269− int (*board_pci_idsel)(unsigned int devsel, int assert);
270− /* bits to set/clear in PCI_CONFIG register */
271− unsigned long pci_cfg_set;
272− unsigned long pci_cfg_clr;
273−};
387+/* GPIO */
388+#define AU1000_SYS_PINFUNC 0x2C
389+# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
390+# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
391+# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
392+# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
393+# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
394+# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
395+# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
396+# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
397+# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
398+# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
399+# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
400+# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
401+# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
402+# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
403+# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
404+# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
274405
275−/* Multifunction pins: Each of these pins can either be assigned to the
276− * GPIO controller or a on-chip peripheral.
277− * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
278− * assign one of these to either the GPIO controller or the device.
279− */
280−enum au1300_multifunc_pins {
281− /* wake-from-str pins 0-3 */
282− AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
283− AU1300_PIN_WAKE3,
284− /* external clock sources for PSCs: 4-5 */
285− AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
286− /* 8bit MMC interface on SD0: 6-9 */
287− AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
288− AU1300_PIN_SD0DAT7,
289− /* aux clk input for freqgen 3: 10 */
290− AU1300_PIN_FG3AUX,
291− /* UART1 pins: 11-18 */
292− AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
293− AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
294− AU1300_PIN_U1RX, AU1300_PIN_U1TX,
295− /* UART0 pins: 19-24 */
296− AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
297− AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
298− /* UART2: 25-26 */
299− AU1300_PIN_U2RX, AU1300_PIN_U2TX,
300− /* UART3: 27-28 */
301− AU1300_PIN_U3RX, AU1300_PIN_U3TX,
302− /* LCD controller PWMs, ext pixclock: 29-31 */
303− AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
304− /* SD1 interface: 32-37 */
305− AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
306− AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
307− /* SD2 interface: 38-43 */
308− AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
309− AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
310− /* PSC0/1 clocks: 44-45 */
311− AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
312− /* PSCs: 46-49/50-53/54-57/58-61 */
313− AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
314− AU1300_PIN_PSC0D1,
315− AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
316− AU1300_PIN_PSC1D1,
317− AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
318− AU1300_PIN_PSC2D1,
319− AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
320− AU1300_PIN_PSC3D1,
321− /* PCMCIA interface: 62-70 */
322− AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
323− AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
324− AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
325− /* camera interface H/V sync inputs: 71-72 */
326− AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
327− /* PSC2/3 clocks: 73-74 */
328− AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
329−};
406+/* Au1100 only */
407+# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
408+# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
409+# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
410+# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
330411
331−/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
332−extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
333−extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
334−extern void au1300_set_irq_priority(unsigned int irq, int p);
335−extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
412+/* Au1550 only. Redefines lots of pins */
413+# define SYS_PF_PSC2_MASK (7 << 17)
414+# define SYS_PF_PSC2_AC97 0
415+# define SYS_PF_PSC2_SPI 0
416+# define SYS_PF_PSC2_I2S (1 << 17)
417+# define SYS_PF_PSC2_SMBUS (3 << 17)
418+# define SYS_PF_PSC2_GPIO (7 << 17)
419+# define SYS_PF_PSC3_MASK (7 << 20)
420+# define SYS_PF_PSC3_AC97 0
421+# define SYS_PF_PSC3_SPI 0
422+# define SYS_PF_PSC3_I2S (1 << 20)
423+# define SYS_PF_PSC3_SMBUS (3 << 20)
424+# define SYS_PF_PSC3_GPIO (7 << 20)
425+# define SYS_PF_PSC1_S1 (1 << 1)
426+# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
336427
337−/* Au1300 allows to disconnect certain blocks from internal power supply */
338−enum au1300_vss_block {
339− AU1300_VSS_MPE = 0,
340− AU1300_VSS_BSA,
341− AU1300_VSS_GPE,
342− AU1300_VSS_MGP,
343−};
428+/* Au1200 only */
429+#define SYS_PINFUNC_DMA (1 << 31)
430+#define SYS_PINFUNC_S0A (1 << 30)
431+#define SYS_PINFUNC_S1A (1 << 29)
432+#define SYS_PINFUNC_LP0 (1 << 28)
433+#define SYS_PINFUNC_LP1 (1 << 27)
434+#define SYS_PINFUNC_LD16 (1 << 26)
435+#define SYS_PINFUNC_LD8 (1 << 25)
436+#define SYS_PINFUNC_LD1 (1 << 24)
437+#define SYS_PINFUNC_LD0 (1 << 23)
438+#define SYS_PINFUNC_P1A (3 << 21)
439+#define SYS_PINFUNC_P1B (1 << 20)
440+#define SYS_PINFUNC_FS3 (1 << 19)
441+#define SYS_PINFUNC_P0A (3 << 17)
442+#define SYS_PINFUNC_CS (1 << 16)
443+#define SYS_PINFUNC_CIM (1 << 15)
444+#define SYS_PINFUNC_P1C (1 << 14)
445+#define SYS_PINFUNC_U1T (1 << 12)
446+#define SYS_PINFUNC_U1R (1 << 11)
447+#define SYS_PINFUNC_EX1 (1 << 10)
448+#define SYS_PINFUNC_EX0 (1 << 9)
449+#define SYS_PINFUNC_U0R (1 << 8)
450+#define SYS_PINFUNC_MC (1 << 7)
451+#define SYS_PINFUNC_S0B (1 << 6)
452+#define SYS_PINFUNC_S0C (1 << 5)
453+#define SYS_PINFUNC_P0B (1 << 4)
454+#define SYS_PINFUNC_U0T (1 << 3)
455+#define SYS_PINFUNC_S1B (1 << 2)
344456
345−extern void au1300_vss_block_control(int block, int enable);
457+/* Power Management */
458+#define AU1000_SYS_SCRATCH0 0x18
459+#define AU1000_SYS_SCRATCH1 0x1c
460+#define AU1000_SYS_WAKEMSK 0x34
461+#define AU1000_SYS_ENDIAN 0x38
462+#define AU1000_SYS_POWERCTRL 0x3c
463+#define AU1000_SYS_WAKESRC 0x5c
464+#define AU1000_SYS_SLPPWR 0x78
465+#define AU1000_SYS_SLEEP 0x7c
346466
467+#define SYS_WAKEMSK_D2 (1 << 9)
468+#define SYS_WAKEMSK_M2 (1 << 8)
469+#define SYS_WAKEMSK_GPIO(x) (1 << (x))
347470
348−/* SOC Interrupt numbers */
349−/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
350−#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
351−#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
352−#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
353−#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
354−#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
471+/* Clock Controller */
472+#define AU1000_SYS_FREQCTRL0 0x20
473+#define AU1000_SYS_FREQCTRL1 0x24
474+#define AU1000_SYS_CLKSRC 0x28
475+#define AU1000_SYS_CPUPLL 0x60
476+#define AU1000_SYS_AUXPLL 0x64
477+#define AU1300_SYS_AUXPLL2 0x68
355478
356−/* Au1300-style (GPIC): 1 controller with up to 128 sources */
357−#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
358−#define ALCHEMY_GPIC_INT_NUM 128
359−#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
360479
361−enum soc_au1000_ints {
362− AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
363− AU1000_UART0_INT = AU1000_FIRST_INT,
364− AU1000_UART1_INT,
365− AU1000_UART2_INT,
366− AU1000_UART3_INT,
367− AU1000_SSI0_INT,
368− AU1000_SSI1_INT,
369− AU1000_DMA_INT_BASE,
480+/**********************************************************************/
370481
371− AU1000_TOY_INT = AU1000_FIRST_INT + 14,
372− AU1000_TOY_MATCH0_INT,
373− AU1000_TOY_MATCH1_INT,
374− AU1000_TOY_MATCH2_INT,
375− AU1000_RTC_INT,
376− AU1000_RTC_MATCH0_INT,
377− AU1000_RTC_MATCH1_INT,
378− AU1000_RTC_MATCH2_INT,
379− AU1000_IRDA_TX_INT,
380− AU1000_IRDA_RX_INT,
381− AU1000_USB_DEV_REQ_INT,
382− AU1000_USB_DEV_SUS_INT,
383− AU1000_USB_HOST_INT,
384− AU1000_ACSYNC_INT,
385− AU1000_MAC0_DMA_INT,
386− AU1000_MAC1_DMA_INT,
387− AU1000_I2S_UO_INT,
388− AU1000_AC97C_INT,
389− AU1000_GPIO0_INT,
390− AU1000_GPIO1_INT,
391− AU1000_GPIO2_INT,
392− AU1000_GPIO3_INT,
393− AU1000_GPIO4_INT,
394− AU1000_GPIO5_INT,
395− AU1000_GPIO6_INT,
396− AU1000_GPIO7_INT,
397− AU1000_GPIO8_INT,
398− AU1000_GPIO9_INT,
399− AU1000_GPIO10_INT,
400− AU1000_GPIO11_INT,
401− AU1000_GPIO12_INT,
402− AU1000_GPIO13_INT,
403− AU1000_GPIO14_INT,
404− AU1000_GPIO15_INT,
405− AU1000_GPIO16_INT,
406− AU1000_GPIO17_INT,
407− AU1000_GPIO18_INT,
408− AU1000_GPIO19_INT,
409− AU1000_GPIO20_INT,
410− AU1000_GPIO21_INT,
411− AU1000_GPIO22_INT,
412− AU1000_GPIO23_INT,
413− AU1000_GPIO24_INT,
414− AU1000_GPIO25_INT,
415− AU1000_GPIO26_INT,
416− AU1000_GPIO27_INT,
417− AU1000_GPIO28_INT,
418− AU1000_GPIO29_INT,
419− AU1000_GPIO30_INT,
420− AU1000_GPIO31_INT,
421−};
422482
423−enum soc_au1100_ints {
424− AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
425− AU1100_UART0_INT = AU1100_FIRST_INT,
426− AU1100_UART1_INT,
427− AU1100_SD_INT,
428− AU1100_UART3_INT,
429− AU1100_SSI0_INT,
430− AU1100_SSI1_INT,
431− AU1100_DMA_INT_BASE,
483+/* The PCI chip selects are outside the 32bit space, and since we can't
484+ * just program the 36bit addresses into BARs, we have to take a chunk
485+ * out of the 32bit space and reserve it for PCI. When these addresses
486+ * are ioremap()ed, they'll be fixed up to the real 36bit address before
487+ * being passed to the real ioremap function.
488+ */
489+#define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4)
490+#define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)
432491
433− AU1100_TOY_INT = AU1100_FIRST_INT + 14,
434− AU1100_TOY_MATCH0_INT,
435− AU1100_TOY_MATCH1_INT,
436− AU1100_TOY_MATCH2_INT,
437− AU1100_RTC_INT,
438− AU1100_RTC_MATCH0_INT,
439− AU1100_RTC_MATCH1_INT,
440− AU1100_RTC_MATCH2_INT,
441− AU1100_IRDA_TX_INT,
442− AU1100_IRDA_RX_INT,
443− AU1100_USB_DEV_REQ_INT,
444− AU1100_USB_DEV_SUS_INT,
445− AU1100_USB_HOST_INT,
446− AU1100_ACSYNC_INT,
447− AU1100_MAC0_DMA_INT,
448− AU1100_GPIO208_215_INT,
449− AU1100_LCD_INT,
450− AU1100_AC97C_INT,
451− AU1100_GPIO0_INT,
452− AU1100_GPIO1_INT,
453− AU1100_GPIO2_INT,
454− AU1100_GPIO3_INT,
455− AU1100_GPIO4_INT,
456− AU1100_GPIO5_INT,
457− AU1100_GPIO6_INT,
458− AU1100_GPIO7_INT,
459− AU1100_GPIO8_INT,
460− AU1100_GPIO9_INT,
461− AU1100_GPIO10_INT,
462− AU1100_GPIO11_INT,
463− AU1100_GPIO12_INT,
464− AU1100_GPIO13_INT,
465− AU1100_GPIO14_INT,
466− AU1100_GPIO15_INT,
467− AU1100_GPIO16_INT,
468− AU1100_GPIO17_INT,
469− AU1100_GPIO18_INT,
470− AU1100_GPIO19_INT,
471− AU1100_GPIO20_INT,
472− AU1100_GPIO21_INT,
473− AU1100_GPIO22_INT,
474− AU1100_GPIO23_INT,
475− AU1100_GPIO24_INT,
476− AU1100_GPIO25_INT,
477− AU1100_GPIO26_INT,
478− AU1100_GPIO27_INT,
479− AU1100_GPIO28_INT,
480− AU1100_GPIO29_INT,
481− AU1100_GPIO30_INT,
482− AU1100_GPIO31_INT,
483−};
492+/* for PCI IO it's simpler because we get to do the ioremap ourselves and then
493+ * adjust the device's resources.
494+ */
495+#define ALCHEMY_PCI_IOWIN_START 0x00001000
496+#define ALCHEMY_PCI_IOWIN_END 0x0000FFFF
484497
485−enum soc_au1500_ints {
486− AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
487− AU1500_UART0_INT = AU1500_FIRST_INT,
488− AU1500_PCI_INTA,
489− AU1500_PCI_INTB,
490− AU1500_UART3_INT,
491− AU1500_PCI_INTC,
492− AU1500_PCI_INTD,
493− AU1500_DMA_INT_BASE,
498+#ifdef CONFIG_PCI
494499
495− AU1500_TOY_INT = AU1500_FIRST_INT + 14,
496− AU1500_TOY_MATCH0_INT,
497− AU1500_TOY_MATCH1_INT,
498− AU1500_TOY_MATCH2_INT,
499− AU1500_RTC_INT,
500− AU1500_RTC_MATCH0_INT,
501− AU1500_RTC_MATCH1_INT,
502− AU1500_RTC_MATCH2_INT,
503− AU1500_PCI_ERR_INT,
504− AU1500_RESERVED_INT,
505− AU1500_USB_DEV_REQ_INT,
506− AU1500_USB_DEV_SUS_INT,
507− AU1500_USB_HOST_INT,
508− AU1500_ACSYNC_INT,
509− AU1500_MAC0_DMA_INT,
510− AU1500_MAC1_DMA_INT,
511− AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
512− AU1500_GPIO0_INT,
513− AU1500_GPIO1_INT,
514− AU1500_GPIO2_INT,
515− AU1500_GPIO3_INT,
516− AU1500_GPIO4_INT,
517− AU1500_GPIO5_INT,
518− AU1500_GPIO6_INT,
519− AU1500_GPIO7_INT,
520− AU1500_GPIO8_INT,
521− AU1500_GPIO9_INT,
522− AU1500_GPIO10_INT,
523− AU1500_GPIO11_INT,
524− AU1500_GPIO12_INT,
525− AU1500_GPIO13_INT,
526− AU1500_GPIO14_INT,
527− AU1500_GPIO15_INT,
528− AU1500_GPIO200_INT,
529− AU1500_GPIO201_INT,
530− AU1500_GPIO202_INT,
531− AU1500_GPIO203_INT,
532− AU1500_GPIO20_INT,
533− AU1500_GPIO204_INT,
534− AU1500_GPIO205_INT,
535− AU1500_GPIO23_INT,
536− AU1500_GPIO24_INT,
537− AU1500_GPIO25_INT,
538− AU1500_GPIO26_INT,
539− AU1500_GPIO27_INT,
540− AU1500_GPIO28_INT,
541− AU1500_GPIO206_INT,
542− AU1500_GPIO207_INT,
543− AU1500_GPIO208_215_INT,
544−};
545−
546−enum soc_au1550_ints {
547− AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
548− AU1550_UART0_INT = AU1550_FIRST_INT,
549− AU1550_PCI_INTA,
550− AU1550_PCI_INTB,
551− AU1550_DDMA_INT,
552− AU1550_CRYPTO_INT,
553− AU1550_PCI_INTC,
554− AU1550_PCI_INTD,
555− AU1550_PCI_RST_INT,
556− AU1550_UART1_INT,
557− AU1550_UART3_INT,
558− AU1550_PSC0_INT,
559− AU1550_PSC1_INT,
560− AU1550_PSC2_INT,
561− AU1550_PSC3_INT,
562− AU1550_TOY_INT,
563− AU1550_TOY_MATCH0_INT,
564− AU1550_TOY_MATCH1_INT,
565− AU1550_TOY_MATCH2_INT,
566− AU1550_RTC_INT,
567− AU1550_RTC_MATCH0_INT,
568− AU1550_RTC_MATCH1_INT,
569− AU1550_RTC_MATCH2_INT,
570−
571− AU1550_NAND_INT = AU1550_FIRST_INT + 23,
572− AU1550_USB_DEV_REQ_INT,
573− AU1550_USB_DEV_SUS_INT,
574− AU1550_USB_HOST_INT,
575− AU1550_MAC0_DMA_INT,
576− AU1550_MAC1_DMA_INT,
577− AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
578− AU1550_GPIO1_INT,
579− AU1550_GPIO2_INT,
580− AU1550_GPIO3_INT,
581− AU1550_GPIO4_INT,
582− AU1550_GPIO5_INT,
583− AU1550_GPIO6_INT,
584− AU1550_GPIO7_INT,
585− AU1550_GPIO8_INT,
586− AU1550_GPIO9_INT,
587− AU1550_GPIO10_INT,
588− AU1550_GPIO11_INT,
589− AU1550_GPIO12_INT,
590− AU1550_GPIO13_INT,
591− AU1550_GPIO14_INT,
592− AU1550_GPIO15_INT,
593− AU1550_GPIO200_INT,
594− AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
595− AU1550_GPIO16_INT,
596− AU1550_GPIO17_INT,
597− AU1550_GPIO20_INT,
598− AU1550_GPIO21_INT,
599− AU1550_GPIO22_INT,
600− AU1550_GPIO23_INT,
601− AU1550_GPIO24_INT,
602− AU1550_GPIO25_INT,
603− AU1550_GPIO26_INT,
604− AU1550_GPIO27_INT,
605− AU1550_GPIO28_INT,
606− AU1550_GPIO206_INT,
607− AU1550_GPIO207_INT,
608− AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
609−};
610−
611−enum soc_au1200_ints {
612− AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
613− AU1200_UART0_INT = AU1200_FIRST_INT,
614− AU1200_SWT_INT,
615− AU1200_SD_INT,
616− AU1200_DDMA_INT,
617− AU1200_MAE_BE_INT,
618− AU1200_GPIO200_INT,
619− AU1200_GPIO201_INT,
620− AU1200_GPIO202_INT,
621− AU1200_UART1_INT,
622− AU1200_MAE_FE_INT,
623− AU1200_PSC0_INT,
624− AU1200_PSC1_INT,
625− AU1200_AES_INT,
626− AU1200_CAMERA_INT,
627− AU1200_TOY_INT,
628− AU1200_TOY_MATCH0_INT,
629− AU1200_TOY_MATCH1_INT,
630− AU1200_TOY_MATCH2_INT,
631− AU1200_RTC_INT,
632− AU1200_RTC_MATCH0_INT,
633− AU1200_RTC_MATCH1_INT,
634− AU1200_RTC_MATCH2_INT,
635− AU1200_GPIO203_INT,
636− AU1200_NAND_INT,
637− AU1200_GPIO204_INT,
638− AU1200_GPIO205_INT,
639− AU1200_GPIO206_INT,
640− AU1200_GPIO207_INT,
641− AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
642− AU1200_USB_INT,
643− AU1200_LCD_INT,
644− AU1200_MAE_BOTH_INT,
645− AU1200_GPIO0_INT,
646− AU1200_GPIO1_INT,
647− AU1200_GPIO2_INT,
648− AU1200_GPIO3_INT,
649− AU1200_GPIO4_INT,
650− AU1200_GPIO5_INT,
651− AU1200_GPIO6_INT,
652− AU1200_GPIO7_INT,
653− AU1200_GPIO8_INT,
654− AU1200_GPIO9_INT,
655− AU1200_GPIO10_INT,
656− AU1200_GPIO11_INT,
657− AU1200_GPIO12_INT,
658− AU1200_GPIO13_INT,
659− AU1200_GPIO14_INT,
660− AU1200_GPIO15_INT,
661− AU1200_GPIO16_INT,
662− AU1200_GPIO17_INT,
663− AU1200_GPIO18_INT,
664− AU1200_GPIO19_INT,
665− AU1200_GPIO20_INT,
666− AU1200_GPIO21_INT,
667− AU1200_GPIO22_INT,
668− AU1200_GPIO23_INT,
669− AU1200_GPIO24_INT,
670− AU1200_GPIO25_INT,
671− AU1200_GPIO26_INT,
672− AU1200_GPIO27_INT,
673− AU1200_GPIO28_INT,
674− AU1200_GPIO29_INT,
675− AU1200_GPIO30_INT,
676− AU1200_GPIO31_INT,
677−};
500+#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
501+#define IOPORT_RESOURCE_END 0xffffffff
502+#define IOMEM_RESOURCE_START 0x10000000
503+#define IOMEM_RESOURCE_END 0xfffffffffULL
678504
679−#endif /* !defined (_LANGUAGE_ASSEMBLY) */
505+#else
680506
681−/* Au1300 peripheral interrupt numbers */
682−#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
683−#define AU1300_UART1_INT (AU1300_FIRST_INT + 17)
684−#define AU1300_UART2_INT (AU1300_FIRST_INT + 25)
685−#define AU1300_UART3_INT (AU1300_FIRST_INT + 27)
686−#define AU1300_SD1_INT (AU1300_FIRST_INT + 32)
687−#define AU1300_SD2_INT (AU1300_FIRST_INT + 38)
688−#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48)
689−#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52)
690−#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56)
691−#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60)
692−#define AU1300_NAND_INT (AU1300_FIRST_INT + 62)
693−#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75)
694−#define AU1300_MMU_INT (AU1300_FIRST_INT + 76)
695−#define AU1300_MPU_INT (AU1300_FIRST_INT + 77)
696−#define AU1300_GPU_INT (AU1300_FIRST_INT + 78)
697−#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79)
698−#define AU1300_TOY_INT (AU1300_FIRST_INT + 80)
699−#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81)
700−#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82)
701−#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83)
702−#define AU1300_RTC_INT (AU1300_FIRST_INT + 84)
703−#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85)
704−#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86)
705−#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87)
706−#define AU1300_UART0_INT (AU1300_FIRST_INT + 88)
707−#define AU1300_SD0_INT (AU1300_FIRST_INT + 89)
708−#define AU1300_USB_INT (AU1300_FIRST_INT + 90)
709−#define AU1300_LCD_INT (AU1300_FIRST_INT + 91)
710−#define AU1300_BSA_INT (AU1300_FIRST_INT + 92)
711−#define AU1300_MPE_INT (AU1300_FIRST_INT + 93)
712−#define AU1300_ITE_INT (AU1300_FIRST_INT + 94)
713−#define AU1300_AES_INT (AU1300_FIRST_INT + 95)
714−#define AU1300_CIM_INT (AU1300_FIRST_INT + 96)
507+/* Don't allow any legacy ports probing */
508+#define IOPORT_RESOURCE_START 0x10000000
509+#define IOPORT_RESOURCE_END 0xffffffff
510+#define IOMEM_RESOURCE_START 0x10000000
511+#define IOMEM_RESOURCE_END 0xfffffffffULL
715512
716−/**********************************************************************/
513+#endif
717514
718−/*
719− * Physical base addresses for integrated peripherals
720− * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
721− */
515+/* PCI controller block register offsets */
516+#define PCI_REG_CMEM 0x0000
517+#define PCI_REG_CONFIG 0x0004
518+#define PCI_REG_B2BMASK_CCH 0x0008
519+#define PCI_REG_B2BBASE0_VID 0x000C
520+#define PCI_REG_B2BBASE1_SID 0x0010
521+#define PCI_REG_MWMASK_DEV 0x0014
522+#define PCI_REG_MWBASE_REV_CCL 0x0018
523+#define PCI_REG_ERR_ADDR 0x001C
524+#define PCI_REG_SPEC_INTACK 0x0020
525+#define PCI_REG_ID 0x0100
526+#define PCI_REG_STATCMD 0x0104
527+#define PCI_REG_CLASSREV 0x0108
528+#define PCI_REG_PARAM 0x010C
529+#define PCI_REG_MBAR 0x0110
530+#define PCI_REG_TIMEOUT 0x0140
722531
723−#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
724−#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
725−#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
726−#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
727−#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
728−#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
729−#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
730−#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
731−#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
732−#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
733−#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
734−#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
735−#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */
736−#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
737−#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
738−#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
739−#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
740−#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
741−#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */
742−#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
743−#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
744−#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
745−#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
746−#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
747−#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
748−#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
749−#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
750−#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
751−#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
752−#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
753−#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
754−#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
755−#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
756−#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
757−#define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */
758−#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
759−#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
760−#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
761−#define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */
762−#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
763−#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
764−#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
765−#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */
766−#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
767−#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
768−#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
769−#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
770−#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
771−#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
772−#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */
773−#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */
774−#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
775−#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
776−#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */
777−#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
778−#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
779−#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
780−#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
781−#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
782−#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
783−#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
784−#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
785−#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
786−#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
787−#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
788−#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
789−#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
790−#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
791−#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
792−#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
793−#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
794−#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
795−#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
796−#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */
797−#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
798−#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
799−#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
800−#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
801−#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */
802−#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */
803−#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */
804−
805−/**********************************************************************/
806−
807−
808−/*
809− * Au1300 GPIO+INT controller (GPIC) register offsets and bits
810− * Registers are 128bits (0x10 bytes), divided into 4 "banks".
811− */
812−#define AU1300_GPIC_PINVAL 0x0000
813−#define AU1300_GPIC_PINVALCLR 0x0010
814−#define AU1300_GPIC_IPEND 0x0020
815−#define AU1300_GPIC_PRIENC 0x0030
816−#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */
817−#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */
818−#define AU1300_GPIC_DMASEL 0x0060
819−#define AU1300_GPIC_DEVSEL 0x0080
820−#define AU1300_GPIC_DEVCLR 0x0090
821−#define AU1300_GPIC_RSTVAL 0x00a0
822−/* pin configuration space. one 32bit register for up to 128 IRQs */
823−#define AU1300_GPIC_PINCFG 0x1000
824−
825−#define GPIC_GPIO_TO_BIT(gpio) \
826− (1 << ((gpio) & 0x1f))
827−
828−#define GPIC_GPIO_BANKOFF(gpio) \
829− (((gpio) >> 5) * 4)
532+/* PCI controller block register bits */
533+#define PCI_CMEM_E (1 << 28) /* enable cacheable memory */
534+#define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14)
535+#define PCI_CMEM_CMMASK(x) ((x) & 0x3fff)
536+#define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */
537+#define PCI_CONFIG_ET (1 << 26) /* error in target mode */
538+#define PCI_CONFIG_EF (1 << 25) /* fatal error */
539+#define PCI_CONFIG_EP (1 << 24) /* parity error */
540+#define PCI_CONFIG_EM (1 << 23) /* multiple errors */
541+#define PCI_CONFIG_BM (1 << 22) /* bad master error */
542+#define PCI_CONFIG_PD (1 << 20) /* PCI Disable */
543+#define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */
544+#define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */
545+#define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */
546+#define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */
547+#define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */
548+#define PCI_CONFIG_IMM (1 << 11) /* int on master abort */
549+#define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */
550+#define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */
551+#define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */
552+#define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */
553+#define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */
554+#define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */
555+#define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */
556+#define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */
557+#define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */
558+#define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */
559+#define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */
560+#define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */
561+#define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */
562+#define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16)
563+#define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */
564+#define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16)
565+#define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff)
566+#define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16)
567+#define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff)
568+#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
569+#define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff)
570+#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)
571+#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8)
572+#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff)
573+#define PCI_ID_DID(x) (((x) & 0xffff) << 16)
574+#define PCI_ID_VID(x) ((x) & 0xffff)
575+#define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16)
576+#define PCI_STATCMD_CMD(x) ((x) & 0xffff)
577+#define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8)
578+#define PCI_CLASSREV_REV(x) ((x) & 0xff)
579+#define PCI_PARAM_BIST(x) (((x) & 0xff) << 24)
580+#define PCI_PARAM_HT(x) (((x) & 0xff) << 16)
581+#define PCI_PARAM_LT(x) (((x) & 0xff) << 8)
582+#define PCI_PARAM_CLS(x) ((x) & 0xff)
583+#define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */
584+#define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */
830585
831−/* Pin Control bits: who owns the pin, what does it do */
832−#define GPIC_CFG_PC_GPIN 0
833−#define GPIC_CFG_PC_DEV 1
834−#define GPIC_CFG_PC_GPOLOW 2
835−#define GPIC_CFG_PC_GPOHIGH 3
836−#define GPIC_CFG_PC_MASK 3
837586
838−/* assign pin to MIPS IRQ line */
839−#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2)
840−#define GPIC_CFG_IL_MASK (3 << 2)
587+/**********************************************************************/
841588
842−/* pin interrupt type setup */
843−#define GPIC_CFG_IC_OFF (0 << 4)
844−#define GPIC_CFG_IC_LEVEL_LOW (1 << 4)
845−#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4)
846−#define GPIC_CFG_IC_EDGE_FALL (5 << 4)
847−#define GPIC_CFG_IC_EDGE_RISE (6 << 4)
848−#define GPIC_CFG_IC_EDGE_BOTH (7 << 4)
849−#define GPIC_CFG_IC_MASK (7 << 4)
850589
851−/* allow interrupt to wake cpu from 'wait' */
852−#define GPIC_CFG_IDLEWAKE (1 << 7)
590+#ifndef _LANGUAGE_ASSEMBLY
853591
854−/***********************************************************************/
592+#include <linux/delay.h>
593+#include <linux/types.h>
855594
856−/* Au1000 SDRAM memory controller register offsets */
857−#define AU1000_MEM_SDMODE0 0x0000
858−#define AU1000_MEM_SDMODE1 0x0004
859−#define AU1000_MEM_SDMODE2 0x0008
860−#define AU1000_MEM_SDADDR0 0x000C
861−#define AU1000_MEM_SDADDR1 0x0010
862−#define AU1000_MEM_SDADDR2 0x0014
863−#define AU1000_MEM_SDREFCFG 0x0018
864−#define AU1000_MEM_SDPRECMD 0x001C
865−#define AU1000_MEM_SDAUTOREF 0x0020
866−#define AU1000_MEM_SDWRMD0 0x0024
867−#define AU1000_MEM_SDWRMD1 0x0028
868−#define AU1000_MEM_SDWRMD2 0x002C
869−#define AU1000_MEM_SDSLEEP 0x0030
870−#define AU1000_MEM_SDSMCKE 0x0034
595+#include <linux/io.h>
596+#include <linux/irq.h>
871597
872−/* MEM_SDMODE register content definitions */
873−#define MEM_SDMODE_F (1 << 22)
874−#define MEM_SDMODE_SR (1 << 21)
875−#define MEM_SDMODE_BS (1 << 20)
876−#define MEM_SDMODE_RS (3 << 18)
877−#define MEM_SDMODE_CS (7 << 15)
878−#define MEM_SDMODE_TRAS (15 << 11)
879−#define MEM_SDMODE_TMRD (3 << 9)
880−#define MEM_SDMODE_TWR (3 << 7)
881−#define MEM_SDMODE_TRP (3 << 5)
882−#define MEM_SDMODE_TRCD (3 << 3)
883−#define MEM_SDMODE_TCL (7 << 0)
598+#include <asm/cpu.h>
884599
885−#define MEM_SDMODE_BS_2Bank (0 << 20)
886−#define MEM_SDMODE_BS_4Bank (1 << 20)
887−#define MEM_SDMODE_RS_11Row (0 << 18)
888−#define MEM_SDMODE_RS_12Row (1 << 18)
889−#define MEM_SDMODE_RS_13Row (2 << 18)
890−#define MEM_SDMODE_RS_N(N) ((N) << 18)
891−#define MEM_SDMODE_CS_7Col (0 << 15)
892−#define MEM_SDMODE_CS_8Col (1 << 15)
893−#define MEM_SDMODE_CS_9Col (2 << 15)
894−#define MEM_SDMODE_CS_10Col (3 << 15)
895−#define MEM_SDMODE_CS_11Col (4 << 15)
896−#define MEM_SDMODE_CS_N(N) ((N) << 15)
897−#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
898−#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
899−#define MEM_SDMODE_TWR_N(N) ((N) << 7)
900−#define MEM_SDMODE_TRP_N(N) ((N) << 5)
901−#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
902−#define MEM_SDMODE_TCL_N(N) ((N) << 0)
600+/* helpers to access the SYS_* registers */
601+static inline unsigned long alchemy_rdsys(int regofs)
602+{
603+ void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
903604
904−/* MEM_SDADDR register contents definitions */
905−#define MEM_SDADDR_E (1 << 20)
906−#define MEM_SDADDR_CSBA (0x03FF << 10)
907−#define MEM_SDADDR_CSMASK (0x03FF << 0)
908−#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
909−#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
605+ return __raw_readl(b + regofs);
606+}
910607
911−/* MEM_SDREFCFG register content definitions */
912−#define MEM_SDREFCFG_TRC (15 << 28)
913−#define MEM_SDREFCFG_TRPM (3 << 26)
914−#define MEM_SDREFCFG_E (1 << 25)
915−#define MEM_SDREFCFG_RE (0x1ffffff << 0)
916−#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
917−#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
918−#define MEM_SDREFCFG_REF_N(N) (N)
608+static inline void alchemy_wrsys(unsigned long v, int regofs)
609+{
610+ void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
919611
920−/* Au1550 SDRAM Register Offsets */
921−#define AU1550_MEM_SDMODE0 0x0800
922−#define AU1550_MEM_SDMODE1 0x0808
923−#define AU1550_MEM_SDMODE2 0x0810
924−#define AU1550_MEM_SDADDR0 0x0820
925−#define AU1550_MEM_SDADDR1 0x0828
926−#define AU1550_MEM_SDADDR2 0x0830
927−#define AU1550_MEM_SDCONFIGA 0x0840
928−#define AU1550_MEM_SDCONFIGB 0x0848
929−#define AU1550_MEM_SDSTAT 0x0850
930−#define AU1550_MEM_SDERRADDR 0x0858
931−#define AU1550_MEM_SDSTRIDE0 0x0860
932−#define AU1550_MEM_SDSTRIDE1 0x0868
933−#define AU1550_MEM_SDSTRIDE2 0x0870
934−#define AU1550_MEM_SDWRMD0 0x0880
935−#define AU1550_MEM_SDWRMD1 0x0888
936−#define AU1550_MEM_SDWRMD2 0x0890
937−#define AU1550_MEM_SDPRECMD 0x08C0
938−#define AU1550_MEM_SDAUTOREF 0x08C8
939−#define AU1550_MEM_SDSREF 0x08D0
940−#define AU1550_MEM_SDSLEEP MEM_SDSREF
612+ __raw_writel(v, b + regofs);
613+ wmb(); /* drain writebuffer */
614+}
941615
942−/* Static Bus Controller */
943−#define MEM_STCFG0 0xB4001000
944−#define MEM_STTIME0 0xB4001004
945−#define MEM_STADDR0 0xB4001008
616+/* helpers to access static memctrl registers */
617+static inline unsigned long alchemy_rdsmem(int regofs)
618+{
619+ void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
946620
947−#define MEM_STCFG1 0xB4001010
948−#define MEM_STTIME1 0xB4001014
949−#define MEM_STADDR1 0xB4001018
621+ return __raw_readl(b + regofs);
622+}
950623
951−#define MEM_STCFG2 0xB4001020
952−#define MEM_STTIME2 0xB4001024
953−#define MEM_STADDR2 0xB4001028
624+static inline void alchemy_wrsmem(unsigned long v, int regofs)
625+{
626+ void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
954627
955−#define MEM_STCFG3 0xB4001030
956−#define MEM_STTIME3 0xB4001034
957−#define MEM_STADDR3 0xB4001038
628+ __raw_writel(v, b + regofs);
629+ wmb(); /* drain writebuffer */
630+}
958631
959−#define MEM_STNDCTL 0xB4001100
960−#define MEM_STSTAT 0xB4001104
632+/* Early Au1000 have a write-only SYS_CPUPLL register. */
633+static inline int au1xxx_cpu_has_pll_wo(void)
634+{
635+ switch (read_c0_prid()) {
636+ case 0x00030100: /* Au1000 DA */
637+ case 0x00030201: /* Au1000 HA */
638+ case 0x00030202: /* Au1000 HB */
639+ return 1;
640+ }
641+ return 0;
642+}
961643
962−#define MEM_STNAND_CMD 0x0
963−#define MEM_STNAND_ADDR 0x4
964−#define MEM_STNAND_DATA 0x20
965−
966−
967−/* Programmable Counters 0 and 1 */
968−#define SYS_BASE 0xB1900000
969−#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
970−# define SYS_CNTRL_E1S (1 << 23)
971−# define SYS_CNTRL_T1S (1 << 20)
972−# define SYS_CNTRL_M21 (1 << 19)
973−# define SYS_CNTRL_M11 (1 << 18)
974−# define SYS_CNTRL_M01 (1 << 17)
975−# define SYS_CNTRL_C1S (1 << 16)
976−# define SYS_CNTRL_BP (1 << 14)
977−# define SYS_CNTRL_EN1 (1 << 13)
978−# define SYS_CNTRL_BT1 (1 << 12)
979−# define SYS_CNTRL_EN0 (1 << 11)
980−# define SYS_CNTRL_BT0 (1 << 10)
981−# define SYS_CNTRL_E0 (1 << 8)
982−# define SYS_CNTRL_E0S (1 << 7)
983−# define SYS_CNTRL_32S (1 << 5)
984−# define SYS_CNTRL_T0S (1 << 4)
985−# define SYS_CNTRL_M20 (1 << 3)
986−# define SYS_CNTRL_M10 (1 << 2)
987−# define SYS_CNTRL_M00 (1 << 1)
988−# define SYS_CNTRL_C0S (1 << 0)
644+/* does CPU need CONFIG[OD] set to fix tons of errata? */
645+static inline int au1xxx_cpu_needs_config_od(void)
646+{
647+ /*
648+ * c0_config.od (bit 19) was write only (and read as 0) on the
649+ * early revisions of Alchemy SOCs. It disables the bus trans-
650+ * action overlapping and needs to be set to fix various errata.
651+ */
652+ switch (read_c0_prid()) {
653+ case 0x00030100: /* Au1000 DA */
654+ case 0x00030201: /* Au1000 HA */
655+ case 0x00030202: /* Au1000 HB */
656+ case 0x01030200: /* Au1500 AB */
657+ /*
658+ * Au1100/Au1200 errata actually keep silence about this bit,
659+ * so we set it just in case for those revisions that require
660+ * it to be set according to the (now gone) cpu_table.
661+ */
662+ case 0x02030200: /* Au1100 AB */
663+ case 0x02030201: /* Au1100 BA */
664+ case 0x02030202: /* Au1100 BC */
665+ case 0x04030201: /* Au1200 AC */
666+ return 1;
667+ }
668+ return 0;
669+}
989670
990−/* Programmable Counter 0 Registers */
991−#define SYS_TOYTRIM (SYS_BASE + 0)
992−#define SYS_TOYWRITE (SYS_BASE + 4)
993−#define SYS_TOYMATCH0 (SYS_BASE + 8)
994−#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
995−#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
996−#define SYS_TOYREAD (SYS_BASE + 0x40)
671+#define ALCHEMY_CPU_UNKNOWN -1
672+#define ALCHEMY_CPU_AU1000 0
673+#define ALCHEMY_CPU_AU1500 1
674+#define ALCHEMY_CPU_AU1100 2
675+#define ALCHEMY_CPU_AU1550 3
676+#define ALCHEMY_CPU_AU1200 4
677+#define ALCHEMY_CPU_AU1300 5
997678
998−/* Programmable Counter 1 Registers */
999−#define SYS_RTCTRIM (SYS_BASE + 0x44)
1000−#define SYS_RTCWRITE (SYS_BASE + 0x48)
1001−#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
1002−#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
1003−#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
1004−#define SYS_RTCREAD (SYS_BASE + 0x58)
1005−
1006−/* I2S Controller */
1007−#define I2S_DATA 0xB1000000
1008−# define I2S_DATA_MASK 0xffffff
1009−#define I2S_CONFIG 0xB1000004
1010−# define I2S_CONFIG_XU (1 << 25)
1011−# define I2S_CONFIG_XO (1 << 24)
1012−# define I2S_CONFIG_RU (1 << 23)
1013−# define I2S_CONFIG_RO (1 << 22)
1014−# define I2S_CONFIG_TR (1 << 21)
1015−# define I2S_CONFIG_TE (1 << 20)
1016−# define I2S_CONFIG_TF (1 << 19)
1017−# define I2S_CONFIG_RR (1 << 18)
1018−# define I2S_CONFIG_RE (1 << 17)
1019−# define I2S_CONFIG_RF (1 << 16)
1020−# define I2S_CONFIG_PD (1 << 11)
1021−# define I2S_CONFIG_LB (1 << 10)
1022−# define I2S_CONFIG_IC (1 << 9)
1023−# define I2S_CONFIG_FM_BIT 7
1024−# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1025−# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1026−# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1027−# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1028−# define I2S_CONFIG_TN (1 << 6)
1029−# define I2S_CONFIG_RN (1 << 5)
1030−# define I2S_CONFIG_SZ_BIT 0
1031−# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1032−
1033−#define I2S_CONTROL 0xB1000008
1034−# define I2S_CONTROL_D (1 << 1)
1035−# define I2S_CONTROL_CE (1 << 0)
1036−
1037−
1038−/* Ethernet Controllers */
1039−
1040−/* 4 byte offsets from AU1000_ETH_BASE */
1041−#define MAC_CONTROL 0x0
1042−# define MAC_RX_ENABLE (1 << 2)
1043−# define MAC_TX_ENABLE (1 << 3)
1044−# define MAC_DEF_CHECK (1 << 5)
1045−# define MAC_SET_BL(X) (((X) & 0x3) << 6)
1046−# define MAC_AUTO_PAD (1 << 8)
1047−# define MAC_DISABLE_RETRY (1 << 10)
1048−# define MAC_DISABLE_BCAST (1 << 11)
1049−# define MAC_LATE_COL (1 << 12)
1050−# define MAC_HASH_MODE (1 << 13)
1051−# define MAC_HASH_ONLY (1 << 15)
1052−# define MAC_PASS_ALL (1 << 16)
1053−# define MAC_INVERSE_FILTER (1 << 17)
1054−# define MAC_PROMISCUOUS (1 << 18)
1055−# define MAC_PASS_ALL_MULTI (1 << 19)
1056−# define MAC_FULL_DUPLEX (1 << 20)
1057−# define MAC_NORMAL_MODE 0
1058−# define MAC_INT_LOOPBACK (1 << 21)
1059−# define MAC_EXT_LOOPBACK (1 << 22)
1060−# define MAC_DISABLE_RX_OWN (1 << 23)
1061−# define MAC_BIG_ENDIAN (1 << 30)
1062−# define MAC_RX_ALL (1 << 31)
1063−#define MAC_ADDRESS_HIGH 0x4
1064−#define MAC_ADDRESS_LOW 0x8
1065−#define MAC_MCAST_HIGH 0xC
1066−#define MAC_MCAST_LOW 0x10
1067−#define MAC_MII_CNTRL 0x14
1068−# define MAC_MII_BUSY (1 << 0)
1069−# define MAC_MII_READ 0
1070−# define MAC_MII_WRITE (1 << 1)
1071−# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1072−# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1073−#define MAC_MII_DATA 0x18
1074−#define MAC_FLOW_CNTRL 0x1C
1075−# define MAC_FLOW_CNTRL_BUSY (1 << 0)
1076−# define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1077−# define MAC_PASS_CONTROL (1 << 2)
1078−# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1079−#define MAC_VLAN1_TAG 0x20
1080−#define MAC_VLAN2_TAG 0x24
1081−
1082−/* Ethernet Controller Enable */
1083−
1084−# define MAC_EN_CLOCK_ENABLE (1 << 0)
1085−# define MAC_EN_RESET0 (1 << 1)
1086−# define MAC_EN_TOSS (0 << 2)
1087−# define MAC_EN_CACHEABLE (1 << 3)
1088−# define MAC_EN_RESET1 (1 << 4)
1089−# define MAC_EN_RESET2 (1 << 5)
1090−# define MAC_DMA_RESET (1 << 6)
1091−
1092−/* Ethernet Controller DMA Channels */
1093−
1094−#define MAC0_TX_DMA_ADDR 0xB4004000
1095−#define MAC1_TX_DMA_ADDR 0xB4004200
1096−/* offsets from MAC_TX_RING_ADDR address */
1097−#define MAC_TX_BUFF0_STATUS 0x0
1098−# define TX_FRAME_ABORTED (1 << 0)
1099−# define TX_JAB_TIMEOUT (1 << 1)
1100−# define TX_NO_CARRIER (1 << 2)
1101−# define TX_LOSS_CARRIER (1 << 3)
1102−# define TX_EXC_DEF (1 << 4)
1103−# define TX_LATE_COLL_ABORT (1 << 5)
1104−# define TX_EXC_COLL (1 << 6)
1105−# define TX_UNDERRUN (1 << 7)
1106−# define TX_DEFERRED (1 << 8)
1107−# define TX_LATE_COLL (1 << 9)
1108−# define TX_COLL_CNT_MASK (0xF << 10)
1109−# define TX_PKT_RETRY (1 << 31)
1110−#define MAC_TX_BUFF0_ADDR 0x4
1111−# define TX_DMA_ENABLE (1 << 0)
1112−# define TX_T_DONE (1 << 1)
1113−# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1114−#define MAC_TX_BUFF0_LEN 0x8
1115−#define MAC_TX_BUFF1_STATUS 0x10
1116−#define MAC_TX_BUFF1_ADDR 0x14
1117−#define MAC_TX_BUFF1_LEN 0x18
1118−#define MAC_TX_BUFF2_STATUS 0x20
1119−#define MAC_TX_BUFF2_ADDR 0x24
1120−#define MAC_TX_BUFF2_LEN 0x28
1121−#define MAC_TX_BUFF3_STATUS 0x30
1122−#define MAC_TX_BUFF3_ADDR 0x34
1123−#define MAC_TX_BUFF3_LEN 0x38
1124−
1125−#define MAC0_RX_DMA_ADDR 0xB4004100
1126−#define MAC1_RX_DMA_ADDR 0xB4004300
1127−/* offsets from MAC_RX_RING_ADDR */
1128−#define MAC_RX_BUFF0_STATUS 0x0
1129−# define RX_FRAME_LEN_MASK 0x3fff
1130−# define RX_WDOG_TIMER (1 << 14)
1131−# define RX_RUNT (1 << 15)
1132−# define RX_OVERLEN (1 << 16)
1133−# define RX_COLL (1 << 17)
1134−# define RX_ETHER (1 << 18)
1135−# define RX_MII_ERROR (1 << 19)
1136−# define RX_DRIBBLING (1 << 20)
1137−# define RX_CRC_ERROR (1 << 21)
1138−# define RX_VLAN1 (1 << 22)
1139−# define RX_VLAN2 (1 << 23)
1140−# define RX_LEN_ERROR (1 << 24)
1141−# define RX_CNTRL_FRAME (1 << 25)
1142−# define RX_U_CNTRL_FRAME (1 << 26)
1143−# define RX_MCAST_FRAME (1 << 27)
1144−# define RX_BCAST_FRAME (1 << 28)
1145−# define RX_FILTER_FAIL (1 << 29)
1146−# define RX_PACKET_FILTER (1 << 30)
1147−# define RX_MISSED_FRAME (1 << 31)
1148−
1149−# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1150− RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1151− RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1152−#define MAC_RX_BUFF0_ADDR 0x4
1153−# define RX_DMA_ENABLE (1 << 0)
1154−# define RX_T_DONE (1 << 1)
1155−# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1156−# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1157−#define MAC_RX_BUFF1_STATUS 0x10
1158−#define MAC_RX_BUFF1_ADDR 0x14
1159−#define MAC_RX_BUFF2_STATUS 0x20
1160−#define MAC_RX_BUFF2_ADDR 0x24
1161−#define MAC_RX_BUFF3_STATUS 0x30
1162−#define MAC_RX_BUFF3_ADDR 0x34
1163−
1164−/* SSIO */
1165−#define SSI0_STATUS 0xB1600000
1166−# define SSI_STATUS_BF (1 << 4)
1167−# define SSI_STATUS_OF (1 << 3)
1168−# define SSI_STATUS_UF (1 << 2)
1169−# define SSI_STATUS_D (1 << 1)
1170−# define SSI_STATUS_B (1 << 0)
1171−#define SSI0_INT 0xB1600004
1172−# define SSI_INT_OI (1 << 3)
1173−# define SSI_INT_UI (1 << 2)
1174−# define SSI_INT_DI (1 << 1)
1175−#define SSI0_INT_ENABLE 0xB1600008
1176−# define SSI_INTE_OIE (1 << 3)
1177−# define SSI_INTE_UIE (1 << 2)
1178−# define SSI_INTE_DIE (1 << 1)
1179−#define SSI0_CONFIG 0xB1600020
1180−# define SSI_CONFIG_AO (1 << 24)
1181−# define SSI_CONFIG_DO (1 << 23)
1182−# define SSI_CONFIG_ALEN_BIT 20
1183−# define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1184−# define SSI_CONFIG_DLEN_BIT 16
1185−# define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1186−# define SSI_CONFIG_DD (1 << 11)
1187−# define SSI_CONFIG_AD (1 << 10)
1188−# define SSI_CONFIG_BM_BIT 8
1189−# define SSI_CONFIG_BM_MASK (0x3 << 8)
1190−# define SSI_CONFIG_CE (1 << 7)
1191−# define SSI_CONFIG_DP (1 << 6)
1192−# define SSI_CONFIG_DL (1 << 5)
1193−# define SSI_CONFIG_EP (1 << 4)
1194−#define SSI0_ADATA 0xB1600024
1195−# define SSI_AD_D (1 << 24)
1196−# define SSI_AD_ADDR_BIT 16
1197−# define SSI_AD_ADDR_MASK (0xff << 16)
1198−# define SSI_AD_DATA_BIT 0
1199−# define SSI_AD_DATA_MASK (0xfff << 0)
1200−#define SSI0_CLKDIV 0xB1600028
1201−#define SSI0_CONTROL 0xB1600100
1202−# define SSI_CONTROL_CD (1 << 1)
1203−# define SSI_CONTROL_E (1 << 0)
1204−
1205−/* SSI1 */
1206−#define SSI1_STATUS 0xB1680000
1207−#define SSI1_INT 0xB1680004
1208−#define SSI1_INT_ENABLE 0xB1680008
1209−#define SSI1_CONFIG 0xB1680020
1210−#define SSI1_ADATA 0xB1680024
1211−#define SSI1_CLKDIV 0xB1680028
1212−#define SSI1_ENABLE 0xB1680100
679+static inline int alchemy_get_cputype(void)
680+{
681+ switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) {
682+ case 0x00030000:
683+ return ALCHEMY_CPU_AU1000;
684+ break;
685+ case 0x01030000:
686+ return ALCHEMY_CPU_AU1500;
687+ break;
688+ case 0x02030000:
689+ return ALCHEMY_CPU_AU1100;
690+ break;
691+ case 0x03030000:
692+ return ALCHEMY_CPU_AU1550;
693+ break;
694+ case 0x04030000:
695+ case 0x05030000:
696+ return ALCHEMY_CPU_AU1200;
697+ break;
698+ case 0x800c0000:
699+ return ALCHEMY_CPU_AU1300;
700+ break;
701+ }
1213702
1214−/*
1215− * Register content definitions
1216− */
1217−#define SSI_STATUS_BF (1 << 4)
1218−#define SSI_STATUS_OF (1 << 3)
1219−#define SSI_STATUS_UF (1 << 2)
1220−#define SSI_STATUS_D (1 << 1)
1221−#define SSI_STATUS_B (1 << 0)
1222−
1223−/* SSI_INT */
1224−#define SSI_INT_OI (1 << 3)
1225−#define SSI_INT_UI (1 << 2)
1226−#define SSI_INT_DI (1 << 1)
1227−
1228−/* SSI_INTEN */
1229−#define SSI_INTEN_OIE (1 << 3)
1230−#define SSI_INTEN_UIE (1 << 2)
1231−#define SSI_INTEN_DIE (1 << 1)
1232−
1233−#define SSI_CONFIG_AO (1 << 24)
1234−#define SSI_CONFIG_DO (1 << 23)
1235−#define SSI_CONFIG_ALEN (7 << 20)
1236−#define SSI_CONFIG_DLEN (15 << 16)
1237−#define SSI_CONFIG_DD (1 << 11)
1238−#define SSI_CONFIG_AD (1 << 10)
1239−#define SSI_CONFIG_BM (3 << 8)
1240−#define SSI_CONFIG_CE (1 << 7)
1241−#define SSI_CONFIG_DP (1 << 6)
1242−#define SSI_CONFIG_DL (1 << 5)
1243−#define SSI_CONFIG_EP (1 << 4)
1244−#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1245−#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1246−#define SSI_CONFIG_BM_HI (0 << 8)
1247−#define SSI_CONFIG_BM_LO (1 << 8)
1248−#define SSI_CONFIG_BM_CY (2 << 8)
1249−
1250−#define SSI_ADATA_D (1 << 24)
1251−#define SSI_ADATA_ADDR (0xFF << 16)
1252−#define SSI_ADATA_DATA 0x0FFF
1253−#define SSI_ADATA_ADDR_N(N) (N << 16)
1254−
1255−#define SSI_ENABLE_CD (1 << 1)
1256−#define SSI_ENABLE_E (1 << 0)
703+ return ALCHEMY_CPU_UNKNOWN;
704+}
1257705
706+/* return number of uarts on a given cputype */
707+static inline int alchemy_get_uarts(int type)
708+{
709+ switch (type) {
710+ case ALCHEMY_CPU_AU1000:
711+ case ALCHEMY_CPU_AU1300:
712+ return 4;
713+ case ALCHEMY_CPU_AU1500:
714+ case ALCHEMY_CPU_AU1200:
715+ return 2;
716+ case ALCHEMY_CPU_AU1100:
717+ case ALCHEMY_CPU_AU1550:
718+ return 3;
719+ }
720+ return 0;
721+}
1258722
1259−/*
1260− * The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's not
1261− * used to select FIR/SIR mode on the transceiver but as a GPIO. Instead a
1262− * CPLD has to be told about the mode.
1263− */
1264−#define AU1000_IRDA_PHY_MODE_OFF 0
1265−#define AU1000_IRDA_PHY_MODE_SIR 1
1266−#define AU1000_IRDA_PHY_MODE_FIR 2
723+/* enable an UART block if it isn't already */
724+static inline void alchemy_uart_enable(u32 uart_phys)
725+{
726+ void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
1267727
1268−struct au1k_irda_platform_data {
1269− void(*set_phy_mode)(int mode);
1270−};
728+ /* reset, enable clock, deassert reset */
729+ if ((__raw_readl(addr + 0x100) & 3) != 3) {
730+ __raw_writel(0, addr + 0x100);
731+ wmb(); /* drain writebuffer */
732+ __raw_writel(1, addr + 0x100);
733+ wmb(); /* drain writebuffer */
734+ }
735+ __raw_writel(3, addr + 0x100);
736+ wmb(); /* drain writebuffer */
737+}
1271738
739+static inline void alchemy_uart_disable(u32 uart_phys)
740+{
741+ void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
1272742
1273−/* GPIO */
1274−#define SYS_PINFUNC 0xB190002C
1275−# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1276−# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1277−# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1278−# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1279−# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1280−# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1281−# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1282−# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1283−# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1284−# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1285−# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1286−# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1287−# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1288−# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1289−# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1290−# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
743+ __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */
744+ wmb(); /* drain writebuffer */
745+}
1291746
1292−/* Au1100 only */
1293−# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1294−# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1295−# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1296−# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
747+static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
748+{
749+ void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
750+ int timeout, i;
1297751
1298−/* Au1550 only. Redefines lots of pins */
1299−# define SYS_PF_PSC2_MASK (7 << 17)
1300−# define SYS_PF_PSC2_AC97 0
1301−# define SYS_PF_PSC2_SPI 0
1302−# define SYS_PF_PSC2_I2S (1 << 17)
1303−# define SYS_PF_PSC2_SMBUS (3 << 17)
1304−# define SYS_PF_PSC2_GPIO (7 << 17)
1305−# define SYS_PF_PSC3_MASK (7 << 20)
1306−# define SYS_PF_PSC3_AC97 0
1307−# define SYS_PF_PSC3_SPI 0
1308−# define SYS_PF_PSC3_I2S (1 << 20)
1309−# define SYS_PF_PSC3_SMBUS (3 << 20)
1310−# define SYS_PF_PSC3_GPIO (7 << 20)
1311−# define SYS_PF_PSC1_S1 (1 << 1)
1312−# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
752+ /* check LSR TX_EMPTY bit */
753+ timeout = 0xffffff;
754+ do {
755+ if (__raw_readl(base + 0x1c) & 0x20)
756+ break;
757+ /* slow down */
758+ for (i = 10000; i; i--)
759+ asm volatile ("nop");
760+ } while (--timeout);
1313761
1314−/* Au1200 only */
1315−#define SYS_PINFUNC_DMA (1 << 31)
1316−#define SYS_PINFUNC_S0A (1 << 30)
1317−#define SYS_PINFUNC_S1A (1 << 29)
1318−#define SYS_PINFUNC_LP0 (1 << 28)
1319−#define SYS_PINFUNC_LP1 (1 << 27)
1320−#define SYS_PINFUNC_LD16 (1 << 26)
1321−#define SYS_PINFUNC_LD8 (1 << 25)
1322−#define SYS_PINFUNC_LD1 (1 << 24)
1323−#define SYS_PINFUNC_LD0 (1 << 23)
1324−#define SYS_PINFUNC_P1A (3 << 21)
1325−#define SYS_PINFUNC_P1B (1 << 20)
1326−#define SYS_PINFUNC_FS3 (1 << 19)
1327−#define SYS_PINFUNC_P0A (3 << 17)
1328−#define SYS_PINFUNC_CS (1 << 16)
1329−#define SYS_PINFUNC_CIM (1 << 15)
1330−#define SYS_PINFUNC_P1C (1 << 14)
1331−#define SYS_PINFUNC_U1T (1 << 12)
1332−#define SYS_PINFUNC_U1R (1 << 11)
1333−#define SYS_PINFUNC_EX1 (1 << 10)
1334−#define SYS_PINFUNC_EX0 (1 << 9)
1335−#define SYS_PINFUNC_U0R (1 << 8)
1336−#define SYS_PINFUNC_MC (1 << 7)
1337−#define SYS_PINFUNC_S0B (1 << 6)
1338−#define SYS_PINFUNC_S0C (1 << 5)
1339−#define SYS_PINFUNC_P0B (1 << 4)
1340−#define SYS_PINFUNC_U0T (1 << 3)
1341−#define SYS_PINFUNC_S1B (1 << 2)
762+ __raw_writel(c, base + 0x04); /* tx */
763+ wmb(); /* drain writebuffer */
764+}
1342765
1343−/* Power Management */
1344−#define SYS_SCRATCH0 0xB1900018
1345−#define SYS_SCRATCH1 0xB190001C
1346−#define SYS_WAKEMSK 0xB1900034
1347−#define SYS_ENDIAN 0xB1900038
1348−#define SYS_POWERCTRL 0xB190003C
1349−#define SYS_WAKESRC 0xB190005C
1350−#define SYS_SLPPWR 0xB1900078
1351−#define SYS_SLEEP 0xB190007C
766+/* return number of ethernet MACs on a given cputype */
767+static inline int alchemy_get_macs(int type)
768+{
769+ switch (type) {
770+ case ALCHEMY_CPU_AU1000:
771+ case ALCHEMY_CPU_AU1500:
772+ case ALCHEMY_CPU_AU1550:
773+ return 2;
774+ case ALCHEMY_CPU_AU1100:
775+ return 1;
776+ }
777+ return 0;
778+}
1352779
1353−#define SYS_WAKEMSK_D2 (1 << 9)
1354−#define SYS_WAKEMSK_M2 (1 << 8)
1355−#define SYS_WAKEMSK_GPIO(x) (1 << (x))
780+/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
781+void alchemy_sleep_au1000(void);
782+void alchemy_sleep_au1550(void);
783+void alchemy_sleep_au1300(void);
784+void au_sleep(void);
1356785
1357−/* Clock Controller */
1358−#define SYS_FREQCTRL0 0xB1900020
1359−# define SYS_FC_FRDIV2_BIT 22
1360−# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1361−# define SYS_FC_FE2 (1 << 21)
1362−# define SYS_FC_FS2 (1 << 20)
1363−# define SYS_FC_FRDIV1_BIT 12
1364−# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1365−# define SYS_FC_FE1 (1 << 11)
1366−# define SYS_FC_FS1 (1 << 10)
1367−# define SYS_FC_FRDIV0_BIT 2
1368−# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1369−# define SYS_FC_FE0 (1 << 1)
1370−# define SYS_FC_FS0 (1 << 0)
1371−#define SYS_FREQCTRL1 0xB1900024
1372−# define SYS_FC_FRDIV5_BIT 22
1373−# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1374−# define SYS_FC_FE5 (1 << 21)
1375−# define SYS_FC_FS5 (1 << 20)
1376−# define SYS_FC_FRDIV4_BIT 12
1377−# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1378−# define SYS_FC_FE4 (1 << 11)
1379−# define SYS_FC_FS4 (1 << 10)
1380−# define SYS_FC_FRDIV3_BIT 2
1381−# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1382−# define SYS_FC_FE3 (1 << 1)
1383−# define SYS_FC_FS3 (1 << 0)
1384−#define SYS_CLKSRC 0xB1900028
1385−# define SYS_CS_ME1_BIT 27
1386−# define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1387−# define SYS_CS_DE1 (1 << 26)
1388−# define SYS_CS_CE1 (1 << 25)
1389−# define SYS_CS_ME0_BIT 22
1390−# define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1391−# define SYS_CS_DE0 (1 << 21)
1392−# define SYS_CS_CE0 (1 << 20)
1393−# define SYS_CS_MI2_BIT 17
1394−# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1395−# define SYS_CS_DI2 (1 << 16)
1396−# define SYS_CS_CI2 (1 << 15)
1397−
1398−# define SYS_CS_ML_BIT 7
1399−# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1400−# define SYS_CS_DL (1 << 6)
1401−# define SYS_CS_CL (1 << 5)
1402−
1403−# define SYS_CS_MUH_BIT 12
1404−# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1405−# define SYS_CS_DUH (1 << 11)
1406−# define SYS_CS_CUH (1 << 10)
1407−# define SYS_CS_MUD_BIT 7
1408−# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1409−# define SYS_CS_DUD (1 << 6)
1410−# define SYS_CS_CUD (1 << 5)
1411−
1412−# define SYS_CS_MIR_BIT 2
1413−# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1414−# define SYS_CS_DIR (1 << 1)
1415−# define SYS_CS_CIR (1 << 0)
1416−
1417−# define SYS_CS_MUX_AUX 0x1
1418−# define SYS_CS_MUX_FQ0 0x2
1419−# define SYS_CS_MUX_FQ1 0x3
1420−# define SYS_CS_MUX_FQ2 0x4
1421−# define SYS_CS_MUX_FQ3 0x5
1422−# define SYS_CS_MUX_FQ4 0x6
1423−# define SYS_CS_MUX_FQ5 0x7
1424−#define SYS_CPUPLL 0xB1900060
1425−#define SYS_AUXPLL 0xB1900064
1426−
1427−/* AC97 Controller */
1428−#define AC97C_CONFIG 0xB0000000
1429−# define AC97C_RECV_SLOTS_BIT 13
1430−# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1431−# define AC97C_XMIT_SLOTS_BIT 3
1432−# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1433−# define AC97C_SG (1 << 2)
1434−# define AC97C_SYNC (1 << 1)
1435−# define AC97C_RESET (1 << 0)
1436−#define AC97C_STATUS 0xB0000004
1437−# define AC97C_XU (1 << 11)
1438−# define AC97C_XO (1 << 10)
1439−# define AC97C_RU (1 << 9)
1440−# define AC97C_RO (1 << 8)
1441−# define AC97C_READY (1 << 7)
1442−# define AC97C_CP (1 << 6)
1443−# define AC97C_TR (1 << 5)
1444−# define AC97C_TE (1 << 4)
1445−# define AC97C_TF (1 << 3)
1446−# define AC97C_RR (1 << 2)
1447−# define AC97C_RE (1 << 1)
1448−# define AC97C_RF (1 << 0)
1449−#define AC97C_DATA 0xB0000008
1450−#define AC97C_CMD 0xB000000C
1451−# define AC97C_WD_BIT 16
1452−# define AC97C_READ (1 << 7)
1453−# define AC97C_INDEX_MASK 0x7f
1454−#define AC97C_CNTRL 0xB0000010
1455−# define AC97C_RS (1 << 1)
1456−# define AC97C_CE (1 << 0)
786+/* USB: arch/mips/alchemy/common/usb.c */
787+enum alchemy_usb_block {
788+ ALCHEMY_USB_OHCI0,
789+ ALCHEMY_USB_UDC0,
790+ ALCHEMY_USB_EHCI0,
791+ ALCHEMY_USB_OTG0,
792+ ALCHEMY_USB_OHCI1,
793+};
794+int alchemy_usb_control(int block, int enable);
1457795
796+/* PCI controller platform data */
797+struct alchemy_pci_platdata {
798+ int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
799+ int (*board_pci_idsel)(unsigned int devsel, int assert);
800+ /* bits to set/clear in PCI_CONFIG register */
801+ unsigned long pci_cfg_set;
802+ unsigned long pci_cfg_clr;
803+};
1458804
1459−/* The PCI chip selects are outside the 32bit space, and since we can't
1460− * just program the 36bit addresses into BARs, we have to take a chunk
1461− * out of the 32bit space and reserve it for PCI. When these addresses
1462− * are ioremap()ed, they'll be fixed up to the real 36bit address before
1463− * being passed to the real ioremap function.
805+/* The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's
806+ * not used to select FIR/SIR mode on the transceiver but as a GPIO.
807+ * Instead a CPLD has to be told about the mode. The driver calls the
808+ * set_phy_mode() function in addition to driving the IRFIRSEL pin.
1464809 */
1465−#define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4)
1466−#define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)
810+#define AU1000_IRDA_PHY_MODE_OFF 0
811+#define AU1000_IRDA_PHY_MODE_SIR 1
812+#define AU1000_IRDA_PHY_MODE_FIR 2
1467813
1468−/* for PCI IO it's simpler because we get to do the ioremap ourselves and then
1469− * adjust the device's resources.
814+struct au1k_irda_platform_data {
815+ void (*set_phy_mode)(int mode);
816+};
817+
818+
819+/* Multifunction pins: Each of these pins can either be assigned to the
820+ * GPIO controller or a on-chip peripheral.
821+ * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
822+ * assign one of these to either the GPIO controller or the device.
1470823 */
1471−#define ALCHEMY_PCI_IOWIN_START 0x00001000
1472−#define ALCHEMY_PCI_IOWIN_END 0x0000FFFF
824+enum au1300_multifunc_pins {
825+ /* wake-from-str pins 0-3 */
826+ AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
827+ AU1300_PIN_WAKE3,
828+ /* external clock sources for PSCs: 4-5 */
829+ AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
830+ /* 8bit MMC interface on SD0: 6-9 */
831+ AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
832+ AU1300_PIN_SD0DAT7,
833+ /* aux clk input for freqgen 3: 10 */
834+ AU1300_PIN_FG3AUX,
835+ /* UART1 pins: 11-18 */
836+ AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
837+ AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
838+ AU1300_PIN_U1RX, AU1300_PIN_U1TX,
839+ /* UART0 pins: 19-24 */
840+ AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
841+ AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
842+ /* UART2: 25-26 */
843+ AU1300_PIN_U2RX, AU1300_PIN_U2TX,
844+ /* UART3: 27-28 */
845+ AU1300_PIN_U3RX, AU1300_PIN_U3TX,
846+ /* LCD controller PWMs, ext pixclock: 29-31 */
847+ AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
848+ /* SD1 interface: 32-37 */
849+ AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
850+ AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
851+ /* SD2 interface: 38-43 */
852+ AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
853+ AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
854+ /* PSC0/1 clocks: 44-45 */
855+ AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
856+ /* PSCs: 46-49/50-53/54-57/58-61 */
857+ AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
858+ AU1300_PIN_PSC0D1,
859+ AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
860+ AU1300_PIN_PSC1D1,
861+ AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
862+ AU1300_PIN_PSC2D1,
863+ AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
864+ AU1300_PIN_PSC3D1,
865+ /* PCMCIA interface: 62-70 */
866+ AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
867+ AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
868+ AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
869+ /* camera interface H/V sync inputs: 71-72 */
870+ AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
871+ /* PSC2/3 clocks: 73-74 */
872+ AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
873+};
1473874
1474−#ifdef CONFIG_PCI
875+/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
876+extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
877+extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
878+extern void au1300_set_irq_priority(unsigned int irq, int p);
879+extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
1475880
1476−#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1477−#define IOPORT_RESOURCE_END 0xffffffff
1478−#define IOMEM_RESOURCE_START 0x10000000
1479−#define IOMEM_RESOURCE_END 0xfffffffffULL
881+/* Au1300 allows to disconnect certain blocks from internal power supply */
882+enum au1300_vss_block {
883+ AU1300_VSS_MPE = 0,
884+ AU1300_VSS_BSA,
885+ AU1300_VSS_GPE,
886+ AU1300_VSS_MGP,
887+};
1480888
1481−#else
889+extern void au1300_vss_block_control(int block, int enable);
1482890
1483−/* Don't allow any legacy ports probing */
1484−#define IOPORT_RESOURCE_START 0x10000000
1485−#define IOPORT_RESOURCE_END 0xffffffff
1486−#define IOMEM_RESOURCE_START 0x10000000
1487−#define IOMEM_RESOURCE_END 0xfffffffffULL
891+enum soc_au1000_ints {
892+ AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
893+ AU1000_UART0_INT = AU1000_FIRST_INT,
894+ AU1000_UART1_INT,
895+ AU1000_UART2_INT,
896+ AU1000_UART3_INT,
897+ AU1000_SSI0_INT,
898+ AU1000_SSI1_INT,
899+ AU1000_DMA_INT_BASE,
1488900
1489−#endif
901+ AU1000_TOY_INT = AU1000_FIRST_INT + 14,
902+ AU1000_TOY_MATCH0_INT,
903+ AU1000_TOY_MATCH1_INT,
904+ AU1000_TOY_MATCH2_INT,
905+ AU1000_RTC_INT,
906+ AU1000_RTC_MATCH0_INT,
907+ AU1000_RTC_MATCH1_INT,
908+ AU1000_RTC_MATCH2_INT,
909+ AU1000_IRDA_TX_INT,
910+ AU1000_IRDA_RX_INT,
911+ AU1000_USB_DEV_REQ_INT,
912+ AU1000_USB_DEV_SUS_INT,
913+ AU1000_USB_HOST_INT,
914+ AU1000_ACSYNC_INT,
915+ AU1000_MAC0_DMA_INT,
916+ AU1000_MAC1_DMA_INT,
917+ AU1000_I2S_UO_INT,
918+ AU1000_AC97C_INT,
919+ AU1000_GPIO0_INT,
920+ AU1000_GPIO1_INT,
921+ AU1000_GPIO2_INT,
922+ AU1000_GPIO3_INT,
923+ AU1000_GPIO4_INT,
924+ AU1000_GPIO5_INT,
925+ AU1000_GPIO6_INT,
926+ AU1000_GPIO7_INT,
927+ AU1000_GPIO8_INT,
928+ AU1000_GPIO9_INT,
929+ AU1000_GPIO10_INT,
930+ AU1000_GPIO11_INT,
931+ AU1000_GPIO12_INT,
932+ AU1000_GPIO13_INT,
933+ AU1000_GPIO14_INT,
934+ AU1000_GPIO15_INT,
935+ AU1000_GPIO16_INT,
936+ AU1000_GPIO17_INT,
937+ AU1000_GPIO18_INT,
938+ AU1000_GPIO19_INT,
939+ AU1000_GPIO20_INT,
940+ AU1000_GPIO21_INT,
941+ AU1000_GPIO22_INT,
942+ AU1000_GPIO23_INT,
943+ AU1000_GPIO24_INT,
944+ AU1000_GPIO25_INT,
945+ AU1000_GPIO26_INT,
946+ AU1000_GPIO27_INT,
947+ AU1000_GPIO28_INT,
948+ AU1000_GPIO29_INT,
949+ AU1000_GPIO30_INT,
950+ AU1000_GPIO31_INT,
951+};
1490952
1491−/* PCI controller block register offsets */
1492−#define PCI_REG_CMEM 0x0000
1493−#define PCI_REG_CONFIG 0x0004
1494−#define PCI_REG_B2BMASK_CCH 0x0008
1495−#define PCI_REG_B2BBASE0_VID 0x000C
1496−#define PCI_REG_B2BBASE1_SID 0x0010
1497−#define PCI_REG_MWMASK_DEV 0x0014
1498−#define PCI_REG_MWBASE_REV_CCL 0x0018
1499−#define PCI_REG_ERR_ADDR 0x001C
1500−#define PCI_REG_SPEC_INTACK 0x0020
1501−#define PCI_REG_ID 0x0100
1502−#define PCI_REG_STATCMD 0x0104
1503−#define PCI_REG_CLASSREV 0x0108
1504−#define PCI_REG_PARAM 0x010C
1505−#define PCI_REG_MBAR 0x0110
1506−#define PCI_REG_TIMEOUT 0x0140
953+enum soc_au1100_ints {
954+ AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
955+ AU1100_UART0_INT = AU1100_FIRST_INT,
956+ AU1100_UART1_INT,
957+ AU1100_SD_INT,
958+ AU1100_UART3_INT,
959+ AU1100_SSI0_INT,
960+ AU1100_SSI1_INT,
961+ AU1100_DMA_INT_BASE,
1507962
1508−/* PCI controller block register bits */
1509−#define PCI_CMEM_E (1 << 28) /* enable cacheable memory */
1510−#define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14)
1511−#define PCI_CMEM_CMMASK(x) ((x) & 0x3fff)
1512−#define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */
1513−#define PCI_CONFIG_ET (1 << 26) /* error in target mode */
1514−#define PCI_CONFIG_EF (1 << 25) /* fatal error */
1515−#define PCI_CONFIG_EP (1 << 24) /* parity error */
1516−#define PCI_CONFIG_EM (1 << 23) /* multiple errors */
1517−#define PCI_CONFIG_BM (1 << 22) /* bad master error */
1518−#define PCI_CONFIG_PD (1 << 20) /* PCI Disable */
1519−#define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */
1520−#define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */
1521−#define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */
1522−#define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */
1523−#define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */
1524−#define PCI_CONFIG_IMM (1 << 11) /* int on master abort */
1525−#define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */
1526−#define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */
1527−#define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */
1528−#define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */
1529−#define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */
1530−#define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */
1531−#define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */
1532−#define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */
1533−#define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */
1534−#define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */
1535−#define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */
1536−#define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */
1537−#define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */
1538−#define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16)
1539−#define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */
1540−#define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16)
1541−#define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff)
1542−#define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16)
1543−#define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff)
1544−#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
1545−#define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff)
1546−#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)
1547−#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8)
1548−#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff)
1549−#define PCI_ID_DID(x) (((x) & 0xffff) << 16)
1550−#define PCI_ID_VID(x) ((x) & 0xffff)
1551−#define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16)
1552−#define PCI_STATCMD_CMD(x) ((x) & 0xffff)
1553−#define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8)
1554−#define PCI_CLASSREV_REV(x) ((x) & 0xff)
1555−#define PCI_PARAM_BIST(x) (((x) & 0xff) << 24)
1556−#define PCI_PARAM_HT(x) (((x) & 0xff) << 16)
1557−#define PCI_PARAM_LT(x) (((x) & 0xff) << 8)
1558−#define PCI_PARAM_CLS(x) ((x) & 0xff)
1559−#define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */
1560−#define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */
963+ AU1100_TOY_INT = AU1100_FIRST_INT + 14,
964+ AU1100_TOY_MATCH0_INT,
965+ AU1100_TOY_MATCH1_INT,
966+ AU1100_TOY_MATCH2_INT,
967+ AU1100_RTC_INT,
968+ AU1100_RTC_MATCH0_INT,
969+ AU1100_RTC_MATCH1_INT,
970+ AU1100_RTC_MATCH2_INT,
971+ AU1100_IRDA_TX_INT,
972+ AU1100_IRDA_RX_INT,
973+ AU1100_USB_DEV_REQ_INT,
974+ AU1100_USB_DEV_SUS_INT,
975+ AU1100_USB_HOST_INT,
976+ AU1100_ACSYNC_INT,
977+ AU1100_MAC0_DMA_INT,
978+ AU1100_GPIO208_215_INT,
979+ AU1100_LCD_INT,
980+ AU1100_AC97C_INT,
981+ AU1100_GPIO0_INT,
982+ AU1100_GPIO1_INT,
983+ AU1100_GPIO2_INT,
984+ AU1100_GPIO3_INT,
985+ AU1100_GPIO4_INT,
986+ AU1100_GPIO5_INT,
987+ AU1100_GPIO6_INT,
988+ AU1100_GPIO7_INT,
989+ AU1100_GPIO8_INT,
990+ AU1100_GPIO9_INT,
991+ AU1100_GPIO10_INT,
992+ AU1100_GPIO11_INT,
993+ AU1100_GPIO12_INT,
994+ AU1100_GPIO13_INT,
995+ AU1100_GPIO14_INT,
996+ AU1100_GPIO15_INT,
997+ AU1100_GPIO16_INT,
998+ AU1100_GPIO17_INT,
999+ AU1100_GPIO18_INT,
1000+ AU1100_GPIO19_INT,
1001+ AU1100_GPIO20_INT,
1002+ AU1100_GPIO21_INT,
1003+ AU1100_GPIO22_INT,
1004+ AU1100_GPIO23_INT,
1005+ AU1100_GPIO24_INT,
1006+ AU1100_GPIO25_INT,
1007+ AU1100_GPIO26_INT,
1008+ AU1100_GPIO27_INT,
1009+ AU1100_GPIO28_INT,
1010+ AU1100_GPIO29_INT,
1011+ AU1100_GPIO30_INT,
1012+ AU1100_GPIO31_INT,
1013+};
1014+
1015+enum soc_au1500_ints {
1016+ AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
1017+ AU1500_UART0_INT = AU1500_FIRST_INT,
1018+ AU1500_PCI_INTA,
1019+ AU1500_PCI_INTB,
1020+ AU1500_UART3_INT,
1021+ AU1500_PCI_INTC,
1022+ AU1500_PCI_INTD,
1023+ AU1500_DMA_INT_BASE,
1024+
1025+ AU1500_TOY_INT = AU1500_FIRST_INT + 14,
1026+ AU1500_TOY_MATCH0_INT,
1027+ AU1500_TOY_MATCH1_INT,
1028+ AU1500_TOY_MATCH2_INT,
1029+ AU1500_RTC_INT,
1030+ AU1500_RTC_MATCH0_INT,
1031+ AU1500_RTC_MATCH1_INT,
1032+ AU1500_RTC_MATCH2_INT,
1033+ AU1500_PCI_ERR_INT,
1034+ AU1500_RESERVED_INT,
1035+ AU1500_USB_DEV_REQ_INT,
1036+ AU1500_USB_DEV_SUS_INT,
1037+ AU1500_USB_HOST_INT,
1038+ AU1500_ACSYNC_INT,
1039+ AU1500_MAC0_DMA_INT,
1040+ AU1500_MAC1_DMA_INT,
1041+ AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
1042+ AU1500_GPIO0_INT,
1043+ AU1500_GPIO1_INT,
1044+ AU1500_GPIO2_INT,
1045+ AU1500_GPIO3_INT,
1046+ AU1500_GPIO4_INT,
1047+ AU1500_GPIO5_INT,
1048+ AU1500_GPIO6_INT,
1049+ AU1500_GPIO7_INT,
1050+ AU1500_GPIO8_INT,
1051+ AU1500_GPIO9_INT,
1052+ AU1500_GPIO10_INT,
1053+ AU1500_GPIO11_INT,
1054+ AU1500_GPIO12_INT,
1055+ AU1500_GPIO13_INT,
1056+ AU1500_GPIO14_INT,
1057+ AU1500_GPIO15_INT,
1058+ AU1500_GPIO200_INT,
1059+ AU1500_GPIO201_INT,
1060+ AU1500_GPIO202_INT,
1061+ AU1500_GPIO203_INT,
1062+ AU1500_GPIO20_INT,
1063+ AU1500_GPIO204_INT,
1064+ AU1500_GPIO205_INT,
1065+ AU1500_GPIO23_INT,
1066+ AU1500_GPIO24_INT,
1067+ AU1500_GPIO25_INT,
1068+ AU1500_GPIO26_INT,
1069+ AU1500_GPIO27_INT,
1070+ AU1500_GPIO28_INT,
1071+ AU1500_GPIO206_INT,
1072+ AU1500_GPIO207_INT,
1073+ AU1500_GPIO208_215_INT,
1074+};
1075+
1076+enum soc_au1550_ints {
1077+ AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
1078+ AU1550_UART0_INT = AU1550_FIRST_INT,
1079+ AU1550_PCI_INTA,
1080+ AU1550_PCI_INTB,
1081+ AU1550_DDMA_INT,
1082+ AU1550_CRYPTO_INT,
1083+ AU1550_PCI_INTC,
1084+ AU1550_PCI_INTD,
1085+ AU1550_PCI_RST_INT,
1086+ AU1550_UART1_INT,
1087+ AU1550_UART3_INT,
1088+ AU1550_PSC0_INT,
1089+ AU1550_PSC1_INT,
1090+ AU1550_PSC2_INT,
1091+ AU1550_PSC3_INT,
1092+ AU1550_TOY_INT,
1093+ AU1550_TOY_MATCH0_INT,
1094+ AU1550_TOY_MATCH1_INT,
1095+ AU1550_TOY_MATCH2_INT,
1096+ AU1550_RTC_INT,
1097+ AU1550_RTC_MATCH0_INT,
1098+ AU1550_RTC_MATCH1_INT,
1099+ AU1550_RTC_MATCH2_INT,
1100+
1101+ AU1550_NAND_INT = AU1550_FIRST_INT + 23,
1102+ AU1550_USB_DEV_REQ_INT,
1103+ AU1550_USB_DEV_SUS_INT,
1104+ AU1550_USB_HOST_INT,
1105+ AU1550_MAC0_DMA_INT,
1106+ AU1550_MAC1_DMA_INT,
1107+ AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
1108+ AU1550_GPIO1_INT,
1109+ AU1550_GPIO2_INT,
1110+ AU1550_GPIO3_INT,
1111+ AU1550_GPIO4_INT,
1112+ AU1550_GPIO5_INT,
1113+ AU1550_GPIO6_INT,
1114+ AU1550_GPIO7_INT,
1115+ AU1550_GPIO8_INT,
1116+ AU1550_GPIO9_INT,
1117+ AU1550_GPIO10_INT,
1118+ AU1550_GPIO11_INT,
1119+ AU1550_GPIO12_INT,
1120+ AU1550_GPIO13_INT,
1121+ AU1550_GPIO14_INT,
1122+ AU1550_GPIO15_INT,
1123+ AU1550_GPIO200_INT,
1124+ AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
1125+ AU1550_GPIO16_INT,
1126+ AU1550_GPIO17_INT,
1127+ AU1550_GPIO20_INT,
1128+ AU1550_GPIO21_INT,
1129+ AU1550_GPIO22_INT,
1130+ AU1550_GPIO23_INT,
1131+ AU1550_GPIO24_INT,
1132+ AU1550_GPIO25_INT,
1133+ AU1550_GPIO26_INT,
1134+ AU1550_GPIO27_INT,
1135+ AU1550_GPIO28_INT,
1136+ AU1550_GPIO206_INT,
1137+ AU1550_GPIO207_INT,
1138+ AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
1139+};
1140+
1141+enum soc_au1200_ints {
1142+ AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
1143+ AU1200_UART0_INT = AU1200_FIRST_INT,
1144+ AU1200_SWT_INT,
1145+ AU1200_SD_INT,
1146+ AU1200_DDMA_INT,
1147+ AU1200_MAE_BE_INT,
1148+ AU1200_GPIO200_INT,
1149+ AU1200_GPIO201_INT,
1150+ AU1200_GPIO202_INT,
1151+ AU1200_UART1_INT,
1152+ AU1200_MAE_FE_INT,
1153+ AU1200_PSC0_INT,
1154+ AU1200_PSC1_INT,
1155+ AU1200_AES_INT,
1156+ AU1200_CAMERA_INT,
1157+ AU1200_TOY_INT,
1158+ AU1200_TOY_MATCH0_INT,
1159+ AU1200_TOY_MATCH1_INT,
1160+ AU1200_TOY_MATCH2_INT,
1161+ AU1200_RTC_INT,
1162+ AU1200_RTC_MATCH0_INT,
1163+ AU1200_RTC_MATCH1_INT,
1164+ AU1200_RTC_MATCH2_INT,
1165+ AU1200_GPIO203_INT,
1166+ AU1200_NAND_INT,
1167+ AU1200_GPIO204_INT,
1168+ AU1200_GPIO205_INT,
1169+ AU1200_GPIO206_INT,
1170+ AU1200_GPIO207_INT,
1171+ AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
1172+ AU1200_USB_INT,
1173+ AU1200_LCD_INT,
1174+ AU1200_MAE_BOTH_INT,
1175+ AU1200_GPIO0_INT,
1176+ AU1200_GPIO1_INT,
1177+ AU1200_GPIO2_INT,
1178+ AU1200_GPIO3_INT,
1179+ AU1200_GPIO4_INT,
1180+ AU1200_GPIO5_INT,
1181+ AU1200_GPIO6_INT,
1182+ AU1200_GPIO7_INT,
1183+ AU1200_GPIO8_INT,
1184+ AU1200_GPIO9_INT,
1185+ AU1200_GPIO10_INT,
1186+ AU1200_GPIO11_INT,
1187+ AU1200_GPIO12_INT,
1188+ AU1200_GPIO13_INT,
1189+ AU1200_GPIO14_INT,
1190+ AU1200_GPIO15_INT,
1191+ AU1200_GPIO16_INT,
1192+ AU1200_GPIO17_INT,
1193+ AU1200_GPIO18_INT,
1194+ AU1200_GPIO19_INT,
1195+ AU1200_GPIO20_INT,
1196+ AU1200_GPIO21_INT,
1197+ AU1200_GPIO22_INT,
1198+ AU1200_GPIO23_INT,
1199+ AU1200_GPIO24_INT,
1200+ AU1200_GPIO25_INT,
1201+ AU1200_GPIO26_INT,
1202+ AU1200_GPIO27_INT,
1203+ AU1200_GPIO28_INT,
1204+ AU1200_GPIO29_INT,
1205+ AU1200_GPIO30_INT,
1206+ AU1200_GPIO31_INT,
1207+};
1208+
1209+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
15611210
15621211 #endif
arch/mips/include/asm/mach-au1x00/au1000_dma.h+25−25
@@ -106,7 +106,7 @@ enum { · 105 unmodified lines
106106 struct dma_chan {
107107 int dev_id; /* this channel is allocated if >= 0, */
108108 /* free otherwise */
109− unsigned int io;
109+ void __iomem *io;
110110 const char *dev_str;
111111 int irq;
112112 void *irq_dev;
@@ -157,7 +157,7 @@ static inline void enable_dma_buffer0(unsigned int dmanr) · 44 unmodified lines
157157
158158 if (!chan)
159159 return;
160− au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
160+ __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET);
161161 }
162162
163163 static inline void enable_dma_buffer1(unsigned int dmanr)
@@ -166,7 +166,7 @@ static inline void enable_dma_buffer1(unsigned int dmanr) · 2 unmodified lines
166166
167167 if (!chan)
168168 return;
169− au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
169+ __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET);
170170 }
171171 static inline void enable_dma_buffers(unsigned int dmanr)
172172 {
@@ -174,7 +174,7 @@ static inline void enable_dma_buffers(unsigned int dmanr) · 1 unmodified line
174174
175175 if (!chan)
176176 return;
177− au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
177+ __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
178178 }
179179
180180 static inline void start_dma(unsigned int dmanr)
@@ -183,7 +183,7 @@ static inline void start_dma(unsigned int dmanr) · 2 unmodified lines
183183
184184 if (!chan)
185185 return;
186− au_writel(DMA_GO, chan->io + DMA_MODE_SET);
186+ __raw_writel(DMA_GO, chan->io + DMA_MODE_SET);
187187 }
188188
189189 #define DMA_HALT_POLL 0x5000
@@ -195,11 +195,11 @@ static inline void halt_dma(unsigned int dmanr) · 5 unmodified lines
195195
196196 if (!chan)
197197 return;
198− au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
198+ __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
199199
200200 /* Poll the halt bit */
201201 for (i = 0; i < DMA_HALT_POLL; i++)
202− if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
202+ if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
203203 break;
204204 if (i == DMA_HALT_POLL)
205205 printk(KERN_INFO "halt_dma: HALT poll expired!\n");
@@ -215,7 +215,7 @@ static inline void disable_dma(unsigned int dmanr) · 9 unmodified lines
215215 halt_dma(dmanr);
216216
217217 /* Now we can disable the buffers */
218− au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
218+ __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
219219 }
220220
221221 static inline int dma_halted(unsigned int dmanr)
@@ -224,7 +224,7 @@ static inline int dma_halted(unsigned int dmanr) · 2 unmodified lines
224224
225225 if (!chan)
226226 return 1;
227− return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
227+ return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
228228 }
229229
230230 /* Initialize a DMA channel. */
@@ -239,14 +239,14 @@ static inline void init_dma(unsigned int dmanr) · 8 unmodified lines
239239 disable_dma(dmanr);
240240
241241 /* Set device FIFO address */
242− au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
242+ __raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
243243
244244 mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
245245 if (chan->irq)
246246 mode |= DMA_IE;
247247
248− au_writel(~mode, chan->io + DMA_MODE_CLEAR);
249− au_writel(mode, chan->io + DMA_MODE_SET);
248+ __raw_writel(~mode, chan->io + DMA_MODE_CLEAR);
249+ __raw_writel(mode, chan->io + DMA_MODE_SET);
250250 }
251251
252252 /*
@@ -283,7 +283,7 @@ static inline int get_dma_active_buffer(unsigned int dmanr) · 30 unmodified lines
283283
284284 if (!chan)
285285 return -1;
286− return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
286+ return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
287287 }
288288
289289 /*
@@ -304,7 +304,7 @@ static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a) · 14 unmodified lines
304304 if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
305305 return;
306306
307− au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
307+ __raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
308308 }
309309
310310 /*
@@ -316,7 +316,7 @@ static inline void clear_dma_done0(unsigned int dmanr) · 5 unmodified lines
316316
317317 if (!chan)
318318 return;
319− au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
319+ __raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
320320 }
321321
322322 static inline void clear_dma_done1(unsigned int dmanr)
@@ -325,7 +325,7 @@ static inline void clear_dma_done1(unsigned int dmanr) · 2 unmodified lines
325325
326326 if (!chan)
327327 return;
328− au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
328+ __raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
329329 }
330330
331331 /*
@@ -344,7 +344,7 @@ static inline void set_dma_addr0(unsigned int dmanr, unsigned int a) · 12 unmodified lines
344344
345345 if (!chan)
346346 return;
347− au_writel(a, chan->io + DMA_BUFFER0_START);
347+ __raw_writel(a, chan->io + DMA_BUFFER0_START);
348348 }
349349
350350 /*
@@ -356,7 +356,7 @@ static inline void set_dma_addr1(unsigned int dmanr, unsigned int a) · 5 unmodified lines
356356
357357 if (!chan)
358358 return;
359− au_writel(a, chan->io + DMA_BUFFER1_START);
359+ __raw_writel(a, chan->io + DMA_BUFFER1_START);
360360 }
361361
362362
@@ -370,7 +370,7 @@ static inline void set_dma_count0(unsigned int dmanr, unsigned int count) · 7 unmodified lines
370370 if (!chan)
371371 return;
372372 count &= DMA_COUNT_MASK;
373− au_writel(count, chan->io + DMA_BUFFER0_COUNT);
373+ __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
374374 }
375375
376376 /*
@@ -383,7 +383,7 @@ static inline void set_dma_count1(unsigned int dmanr, unsigned int count) · 6 unmodified lines
383383 if (!chan)
384384 return;
385385 count &= DMA_COUNT_MASK;
386− au_writel(count, chan->io + DMA_BUFFER1_COUNT);
386+ __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
387387 }
388388
389389 /*
@@ -396,8 +396,8 @@ static inline void set_dma_count(unsigned int dmanr, unsigned int count) · 6 unmodified lines
396396 if (!chan)
397397 return;
398398 count &= DMA_COUNT_MASK;
399− au_writel(count, chan->io + DMA_BUFFER0_COUNT);
400− au_writel(count, chan->io + DMA_BUFFER1_COUNT);
399+ __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
400+ __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
401401 }
402402
403403 /*
@@ -410,7 +410,7 @@ static inline unsigned int get_dma_buffer_done(unsigned int dmanr) · 6 unmodified lines
410410
411411 if (!chan)
412412 return 0;
413− return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
413+ return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
414414 }
415415
416416
@@ -437,10 +437,10 @@ static inline int get_dma_residue(unsigned int dmanr) · 20 unmodified lines
437437 if (!chan)
438438 return 0;
439439
440− curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
440+ curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
441441 DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
442442
443− count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
443+ count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
444444
445445 if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
446446 count <<= 1;
arch/mips/include/asm/mach-au1x00/gpio-au1000.h+26−30
@@ -25,20 +25,20 @@ · 24 unmodified lines
2525 #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
2626
2727 /* GPIO1 registers within SYS_ area */
28−#define SYS_TRIOUTRD 0x100
29−#define SYS_TRIOUTCLR 0x100
30−#define SYS_OUTPUTRD 0x108
31−#define SYS_OUTPUTSET 0x108
32−#define SYS_OUTPUTCLR 0x10C
33−#define SYS_PINSTATERD 0x110
34−#define SYS_PININPUTEN 0x110
28+#define AU1000_SYS_TRIOUTRD 0x100
29+#define AU1000_SYS_TRIOUTCLR 0x100
30+#define AU1000_SYS_OUTPUTRD 0x108
31+#define AU1000_SYS_OUTPUTSET 0x108
32+#define AU1000_SYS_OUTPUTCLR 0x10C
33+#define AU1000_SYS_PINSTATERD 0x110
34+#define AU1000_SYS_PININPUTEN 0x110
3535
3636 /* register offsets within GPIO2 block */
37−#define GPIO2_DIR 0x00
38−#define GPIO2_OUTPUT 0x08
39−#define GPIO2_PINSTATE 0x0C
40−#define GPIO2_INTENABLE 0x10
41−#define GPIO2_ENABLE 0x14
37+#define AU1000_GPIO2_DIR 0x00
38+#define AU1000_GPIO2_OUTPUT 0x08
39+#define AU1000_GPIO2_PINSTATE 0x0C
40+#define AU1000_GPIO2_INTENABLE 0x10
41+#define AU1000_GPIO2_ENABLE 0x14
4242
4343 struct gpio;
4444
@@ -217,26 +217,21 @@ static inline int au1200_irq_to_gpio(int irq) · 172 unmodified lines
217217 */
218218 static inline void alchemy_gpio1_set_value(int gpio, int v)
219219 {
220− void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
221220 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
222− unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
223− __raw_writel(mask, base + r);
224− wmb();
221+ unsigned long r = v ? AU1000_SYS_OUTPUTSET : AU1000_SYS_OUTPUTCLR;
222+ alchemy_wrsys(mask, r);
225223 }
226224
227225 static inline int alchemy_gpio1_get_value(int gpio)
228226 {
229− void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
230227 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
231− return __raw_readl(base + SYS_PINSTATERD) & mask;
228+ return alchemy_rdsys(AU1000_SYS_PINSTATERD) & mask;
232229 }
233230
234231 static inline int alchemy_gpio1_direction_input(int gpio)
235232 {
236− void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
237233 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
238− __raw_writel(mask, base + SYS_TRIOUTCLR);
239− wmb();
234+ alchemy_wrsys(mask, AU1000_SYS_TRIOUTCLR);
240235 return 0;
241236 }
242237
@@ -279,13 +274,13 @@ static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out) · 36 unmodified lines
279274 {
280275 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
281276 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
282− unsigned long d = __raw_readl(base + GPIO2_DIR);
277+ unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR);
283278
284279 if (to_out)
285280 d |= mask;
286281 else
287282 d &= ~mask;
288− __raw_writel(d, base + GPIO2_DIR);
283+ __raw_writel(d, base + AU1000_GPIO2_DIR);
289284 wmb();
290285 }
291286
@@ -294,14 +289,15 @@ static inline void alchemy_gpio2_set_value(int gpio, int v) · 2 unmodified lines
294289 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
295290 unsigned long mask;
296291 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
297− __raw_writel(mask, base + GPIO2_OUTPUT);
292+ __raw_writel(mask, base + AU1000_GPIO2_OUTPUT);
298293 wmb();
299294 }
300295
301296 static inline int alchemy_gpio2_get_value(int gpio)
302297 {
303298 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
304− return __raw_readl(base + GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
299+ return __raw_readl(base + AU1000_GPIO2_PINSTATE) &
300+ (1 << (gpio - ALCHEMY_GPIO2_BASE));
305301 }
306302
307303 static inline int alchemy_gpio2_direction_input(int gpio)
@@ -352,12 +348,12 @@ static inline int alchemy_gpio2_to_irq(int gpio) · 44 unmodified lines
352348 static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
353349 {
354350 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
355− unsigned long r = __raw_readl(base + GPIO2_INTENABLE);
351+ unsigned long r = __raw_readl(base + AU1000_GPIO2_INTENABLE);
356352 if (en)
357353 r |= 1 << gpio2;
358354 else
359355 r &= ~(1 << gpio2);
360− __raw_writel(r, base + GPIO2_INTENABLE);
356+ __raw_writel(r, base + AU1000_GPIO2_INTENABLE);
361357 wmb();
362358 }
363359
@@ -434,9 +430,9 @@ static inline void alchemy_gpio2_disable_int(int gpio2) · 70 unmodified lines
434430 static inline void alchemy_gpio2_enable(void)
435431 {
436432 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
437− __raw_writel(3, base + GPIO2_ENABLE); /* reset, clock enabled */
433+ __raw_writel(3, base + AU1000_GPIO2_ENABLE); /* reset, clock enabled */
438434 wmb();
439− __raw_writel(1, base + GPIO2_ENABLE); /* clock enabled */
435+ __raw_writel(1, base + AU1000_GPIO2_ENABLE); /* clock enabled */
440436 wmb();
441437 }
442438
@@ -448,7 +444,7 @@ static inline void alchemy_gpio2_enable(void) · 5 unmodified lines
448444 static inline void alchemy_gpio2_disable(void)
449445 {
450446 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
451− __raw_writel(2, base + GPIO2_ENABLE); /* reset, clock disabled */
447+ __raw_writel(2, base + AU1000_GPIO2_ENABLE); /* reset, clock disabled */
452448 wmb();
453449 }
454450
arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h+6−1
@@ -18,6 +18,7 @@ enum bcm47xx_board { · 17 unmodified lines
1818 BCM47XX_BOARD_ASUS_WL300G,
1919 BCM47XX_BOARD_ASUS_WL320GE,
2020 BCM47XX_BOARD_ASUS_WL330GE,
21+ BCM47XX_BOARD_ASUS_WL500G,
2122 BCM47XX_BOARD_ASUS_WL500GD,
2223 BCM47XX_BOARD_ASUS_WL500GPV1,
2324 BCM47XX_BOARD_ASUS_WL500GPV2,
@@ -70,11 +71,15 @@ enum bcm47xx_board { · 46 unmodified lines
7071 BCM47XX_BOARD_LINKSYS_WRT310NV1,
7172 BCM47XX_BOARD_LINKSYS_WRT310NV2,
7273 BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
73− BCM47XX_BOARD_LINKSYS_WRT54G,
74+ BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101,
75+ BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467,
76+ BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708,
7477 BCM47XX_BOARD_LINKSYS_WRT610NV1,
7578 BCM47XX_BOARD_LINKSYS_WRT610NV2,
7679 BCM47XX_BOARD_LINKSYS_WRTSL54GS,
7780
81+ BCM47XX_BOARD_MICROSOFT_MN700,
82+
7883 BCM47XX_BOARD_MOTOROLA_WE800G,
7984 BCM47XX_BOARD_MOTOROLA_WR850GP,
8085 BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h+35−163
@@ -19,118 +19,68 @@ · 18 unmodified lines
1919 #define BCM6368_CPU_ID 0x6368
2020
2121 void __init bcm63xx_cpu_init(void);
22−u16 __bcm63xx_get_cpu_id(void);
2322 u8 bcm63xx_get_cpu_rev(void);
2423 unsigned int bcm63xx_get_cpu_freq(void);
2524
25+static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id)
26+{
27+ switch (cpu_id) {
2628 #ifdef CONFIG_BCM63XX_CPU_3368
27−# ifdef bcm63xx_get_cpu_id
28−# undef bcm63xx_get_cpu_id
29−# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
30−# define BCMCPU_RUNTIME_DETECT
31−# else
32−# define bcm63xx_get_cpu_id() BCM3368_CPU_ID
33−# endif
34−# define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
35−#else
36−# define BCMCPU_IS_3368() (0)
29+ case BCM3368_CPU_ID:
3730 #endif
3831
3932 #ifdef CONFIG_BCM63XX_CPU_6328
40−# ifdef bcm63xx_get_cpu_id
41−# undef bcm63xx_get_cpu_id
42−# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
43−# define BCMCPU_RUNTIME_DETECT
44−# else
45−# define bcm63xx_get_cpu_id() BCM6328_CPU_ID
46−# endif
47−# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
48−#else
49−# define BCMCPU_IS_6328() (0)
33+ case BCM6328_CPU_ID:
5034 #endif
5135
5236 #ifdef CONFIG_BCM63XX_CPU_6338
53−# ifdef bcm63xx_get_cpu_id
54−# undef bcm63xx_get_cpu_id
55−# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
56−# define BCMCPU_RUNTIME_DETECT
57−# else
58−# define bcm63xx_get_cpu_id() BCM6338_CPU_ID
59−# endif
60−# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
61−#else
62−# define BCMCPU_IS_6338() (0)
37+ case BCM6338_CPU_ID:
6338 #endif
6439
6540 #ifdef CONFIG_BCM63XX_CPU_6345
66−# ifdef bcm63xx_get_cpu_id
67−# undef bcm63xx_get_cpu_id
68−# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
69−# define BCMCPU_RUNTIME_DETECT
70−# else
71−# define bcm63xx_get_cpu_id() BCM6345_CPU_ID
72−# endif
73−# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
74−#else
75−# define BCMCPU_IS_6345() (0)
41+ case BCM6345_CPU_ID:
7642 #endif
7743
7844 #ifdef CONFIG_BCM63XX_CPU_6348
79−# ifdef bcm63xx_get_cpu_id
80−# undef bcm63xx_get_cpu_id
81−# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
82−# define BCMCPU_RUNTIME_DETECT
83−# else
84−# define bcm63xx_get_cpu_id() BCM6348_CPU_ID
85−# endif
86−# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
87−#else
88−# define BCMCPU_IS_6348() (0)
45+ case BCM6348_CPU_ID:
8946 #endif
9047
9148 #ifdef CONFIG_BCM63XX_CPU_6358
92−# ifdef bcm63xx_get_cpu_id
93−# undef bcm63xx_get_cpu_id
94−# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
95−# define BCMCPU_RUNTIME_DETECT
96−# else
97−# define bcm63xx_get_cpu_id() BCM6358_CPU_ID
98−# endif
99−# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
100−#else
101−# define BCMCPU_IS_6358() (0)
49+ case BCM6358_CPU_ID:
10250 #endif
10351
10452 #ifdef CONFIG_BCM63XX_CPU_6362
105−# ifdef bcm63xx_get_cpu_id
106−# undef bcm63xx_get_cpu_id
107−# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
108−# define BCMCPU_RUNTIME_DETECT
109−# else
110−# define bcm63xx_get_cpu_id() BCM6362_CPU_ID
111−# endif
112−# define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
113−#else
114−# define BCMCPU_IS_6362() (0)
53+ case BCM6362_CPU_ID:
11554 #endif
11655
117−
11856 #ifdef CONFIG_BCM63XX_CPU_6368
119−# ifdef bcm63xx_get_cpu_id
120−# undef bcm63xx_get_cpu_id
121−# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
122−# define BCMCPU_RUNTIME_DETECT
123−# else
124−# define bcm63xx_get_cpu_id() BCM6368_CPU_ID
125−# endif
126−# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
127−#else
128−# define BCMCPU_IS_6368() (0)
57+ case BCM6368_CPU_ID:
12958 #endif
59+ break;
60+ default:
61+ unreachable();
62+ }
13063
131−#ifndef bcm63xx_get_cpu_id
132−#error "No CPU support configured"
133−#endif
64+ return cpu_id;
65+}
66+
67+extern u16 bcm63xx_cpu_id;
68+
69+static inline u16 __pure bcm63xx_get_cpu_id(void)
70+{
71+ const u16 cpu_id = bcm63xx_cpu_id;
72+
73+ return __bcm63xx_get_cpu_id(cpu_id);
74+}
75+
76+#define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
77+#define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
78+#define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
79+#define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
80+#define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
81+#define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
82+#define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
83+#define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
13484
13585 /*
13686 * While registers sets are (mostly) the same across 63xx CPU, base
@@ -598,55 +548,6 @@ enum bcm63xx_regs_set { · 461 unmodified lines
598548
599549 extern const unsigned long *bcm63xx_regs_base;
600550
601−#define __GEN_RSET_BASE(__cpu, __rset) \
602− case RSET_## __rset : \
603− return BCM_## __cpu ##_## __rset ##_BASE;
604−
605−#define __GEN_RSET(__cpu) \
606− switch (set) { \
607− __GEN_RSET_BASE(__cpu, DSL_LMEM) \
608− __GEN_RSET_BASE(__cpu, PERF) \
609− __GEN_RSET_BASE(__cpu, TIMER) \
610− __GEN_RSET_BASE(__cpu, WDT) \
611− __GEN_RSET_BASE(__cpu, UART0) \
612− __GEN_RSET_BASE(__cpu, UART1) \
613− __GEN_RSET_BASE(__cpu, GPIO) \
614− __GEN_RSET_BASE(__cpu, SPI) \
615− __GEN_RSET_BASE(__cpu, HSSPI) \
616− __GEN_RSET_BASE(__cpu, UDC0) \
617− __GEN_RSET_BASE(__cpu, OHCI0) \
618− __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
619− __GEN_RSET_BASE(__cpu, USBH_PRIV) \
620− __GEN_RSET_BASE(__cpu, USBD) \
621− __GEN_RSET_BASE(__cpu, USBDMA) \
622− __GEN_RSET_BASE(__cpu, MPI) \
623− __GEN_RSET_BASE(__cpu, PCMCIA) \
624− __GEN_RSET_BASE(__cpu, PCIE) \
625− __GEN_RSET_BASE(__cpu, DSL) \
626− __GEN_RSET_BASE(__cpu, ENET0) \
627− __GEN_RSET_BASE(__cpu, ENET1) \
628− __GEN_RSET_BASE(__cpu, ENETDMA) \
629− __GEN_RSET_BASE(__cpu, ENETDMAC) \
630− __GEN_RSET_BASE(__cpu, ENETDMAS) \
631− __GEN_RSET_BASE(__cpu, ENETSW) \
632− __GEN_RSET_BASE(__cpu, EHCI0) \
633− __GEN_RSET_BASE(__cpu, SDRAM) \
634− __GEN_RSET_BASE(__cpu, MEMC) \
635− __GEN_RSET_BASE(__cpu, DDR) \
636− __GEN_RSET_BASE(__cpu, M2M) \
637− __GEN_RSET_BASE(__cpu, ATM) \
638− __GEN_RSET_BASE(__cpu, XTM) \
639− __GEN_RSET_BASE(__cpu, XTMDMA) \
640− __GEN_RSET_BASE(__cpu, XTMDMAC) \
641− __GEN_RSET_BASE(__cpu, XTMDMAS) \
642− __GEN_RSET_BASE(__cpu, PCM) \
643− __GEN_RSET_BASE(__cpu, PCMDMA) \
644− __GEN_RSET_BASE(__cpu, PCMDMAC) \
645− __GEN_RSET_BASE(__cpu, PCMDMAS) \
646− __GEN_RSET_BASE(__cpu, RNG) \
647− __GEN_RSET_BASE(__cpu, MISC) \
648− }
649−
650551 #define __GEN_CPU_REGS_TABLE(__cpu) \
651552 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
652553 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
@@ -693,36 +594,7 @@ extern const unsigned long *bcm63xx_regs_base; · 40 unmodified lines
693594
694595 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
695596 {
696−#ifdef BCMCPU_RUNTIME_DETECT
697597 return bcm63xx_regs_base[set];
698−#else
699−#ifdef CONFIG_BCM63XX_CPU_3368
700− __GEN_RSET(3368)
701−#endif
702−#ifdef CONFIG_BCM63XX_CPU_6328
703− __GEN_RSET(6328)
704−#endif
705−#ifdef CONFIG_BCM63XX_CPU_6338
706− __GEN_RSET(6338)
707−#endif
708−#ifdef CONFIG_BCM63XX_CPU_6345
709− __GEN_RSET(6345)
710−#endif
711−#ifdef CONFIG_BCM63XX_CPU_6348
712− __GEN_RSET(6348)
713−#endif
714−#ifdef CONFIG_BCM63XX_CPU_6358
715− __GEN_RSET(6358)
716−#endif
717−#ifdef CONFIG_BCM63XX_CPU_6362
718− __GEN_RSET(6362)
719−#endif
720−#ifdef CONFIG_BCM63XX_CPU_6368
721− __GEN_RSET(6368)
722−#endif
723−#endif
724− /* unreached */
725− return 0;
726598 }
727599
728600 /*
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h+0−46
@@ -112,55 +112,9 @@ enum bcm63xx_regs_enetdmac { · 111 unmodified lines
112112
113113 static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
114114 {
115−#ifdef BCMCPU_RUNTIME_DETECT
116115 extern const unsigned long *bcm63xx_regs_enetdmac;
117116
118117 return bcm63xx_regs_enetdmac[reg];
119−#else
120−#ifdef CONFIG_BCM63XX_CPU_6345
121− switch (reg) {
122− case ENETDMAC_CHANCFG:
123− return ENETDMA_6345_CHANCFG_REG;
124− case ENETDMAC_IR:
125− return ENETDMA_6345_IR_REG;
126− case ENETDMAC_IRMASK:
127− return ENETDMA_6345_IRMASK_REG;
128− case ENETDMAC_MAXBURST:
129− return ENETDMA_6345_MAXBURST_REG;
130− case ENETDMAC_BUFALLOC:
131− return ENETDMA_6345_BUFALLOC_REG;
132− case ENETDMAC_RSTART:
133− return ENETDMA_6345_RSTART_REG;
134− case ENETDMAC_FC:
135− return ENETDMA_6345_FC_REG;
136− case ENETDMAC_LEN:
137− return ENETDMA_6345_LEN_REG;
138− }
139−#endif
140−#if defined(CONFIG_BCM63XX_CPU_6328) || \
141− defined(CONFIG_BCM63XX_CPU_6338) || \
142− defined(CONFIG_BCM63XX_CPU_6348) || \
143− defined(CONFIG_BCM63XX_CPU_6358) || \
144− defined(CONFIG_BCM63XX_CPU_6362) || \
145− defined(CONFIG_BCM63XX_CPU_6368)
146− switch (reg) {
147− case ENETDMAC_CHANCFG:
148− return ENETDMAC_CHANCFG_REG;
149− case ENETDMAC_IR:
150− return ENETDMAC_IR_REG;
151− case ENETDMAC_IRMASK:
152− return ENETDMAC_IRMASK_REG;
153− case ENETDMAC_MAXBURST:
154− return ENETDMAC_MAXBURST_REG;
155− case ENETDMAC_BUFALLOC:
156− case ENETDMAC_RSTART:
157− case ENETDMAC_FC:
158− case ENETDMAC_LEN:
159− return 0;
160− }
161−#endif
162−#endif
163− return 0;
164118 }
165119
166120
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h+0−31
@@ -30,26 +30,6 @@ enum bcm63xx_regs_spi { · 29 unmodified lines
3030 SPI_RX_DATA,
3131 };
3232
33−#define __GEN_SPI_RSET_BASE(__cpu, __rset) \
34− case SPI_## __rset: \
35− return SPI_## __cpu ##_## __rset;
36−
37−#define __GEN_SPI_RSET(__cpu) \
38− switch (reg) { \
39− __GEN_SPI_RSET_BASE(__cpu, CMD) \
40− __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \
41− __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \
42− __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \
43− __GEN_SPI_RSET_BASE(__cpu, ST) \
44− __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \
45− __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \
46− __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \
47− __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \
48− __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \
49− __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \
50− __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \
51− }
52−
5333 #define __GEN_SPI_REGS_TABLE(__cpu) \
5434 [SPI_CMD] = SPI_## __cpu ##_CMD, \
5535 [SPI_INT_STATUS] = SPI_## __cpu ##_INT_STATUS, \
@@ -66,20 +46,9 @@ enum bcm63xx_regs_spi { · 10 unmodified lines
6646
6747 static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
6848 {
69−#ifdef BCMCPU_RUNTIME_DETECT
7049 extern const unsigned long *bcm63xx_regs_spi;
7150
7251 return bcm63xx_regs_spi[reg];
73−#else
74−#if defined(CONFIG_BCM63XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348)
75− __GEN_SPI_RSET(6348)
76−#endif
77−#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6362) || \
78− defined(CONFIG_BCM63XX_CPU_6368)
79− __GEN_SPI_RSET(6358)
80−#endif
81−#endif
82− return 0;
8352 }
8453
8554 #endif /* BCM63XX_DEV_SPI_H */
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h+8−8
@@ -215,23 +215,23 @@ · 214 unmodified lines
215215
216216 /* Interrupt Mask register */
217217 #define PERF_IRQMASK_3368_REG 0xc
218−#define PERF_IRQMASK_6328_REG 0x20
218+#define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
219219 #define PERF_IRQMASK_6338_REG 0xc
220220 #define PERF_IRQMASK_6345_REG 0xc
221221 #define PERF_IRQMASK_6348_REG 0xc
222−#define PERF_IRQMASK_6358_REG 0xc
223−#define PERF_IRQMASK_6362_REG 0x20
224−#define PERF_IRQMASK_6368_REG 0x20
222+#define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c)
223+#define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10)
224+#define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
225225
226226 /* Interrupt Status register */
227227 #define PERF_IRQSTAT_3368_REG 0x10
228−#define PERF_IRQSTAT_6328_REG 0x28
228+#define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
229229 #define PERF_IRQSTAT_6338_REG 0x10
230230 #define PERF_IRQSTAT_6345_REG 0x10
231231 #define PERF_IRQSTAT_6348_REG 0x10
232−#define PERF_IRQSTAT_6358_REG 0x10
233−#define PERF_IRQSTAT_6362_REG 0x28
234−#define PERF_IRQSTAT_6368_REG 0x28
232+#define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c)
233+#define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10)
234+#define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
235235
236236 /* External Interrupt Configuration register */
237237 #define PERF_EXTIRQ_CFG_REG_3368 0x14
arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h+1−1
@@ -24,7 +24,7 @@ · 23 unmodified lines
2424 #define cpu_has_smartmips 0
2525 #define cpu_has_vtag_icache 0
2626
27−#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCM63XX_CPU_6348) || defined(CONFIG_BCM63XX_CPU_6345) || defined(CONFIG_BCM63XX_CPU_6338))
27+#if !defined(CONFIG_SYS_HAS_CPU_BMIPS4350)
2828 #define cpu_has_dc_aliases 0
2929 #endif
3030
arch/mips/include/asm/mach-loongson/boot_param.h+4−0
@@ -146,6 +146,9 @@ struct boot_params { · 145 unmodified lines
146146
147147 struct loongson_system_configuration {
148148 u32 nr_cpus;
149+ u32 nr_nodes;
150+ int cores_per_node;
151+ int cores_per_package;
149152 enum loongson_cpu_type cputype;
150153 u64 ht_control_base;
151154 u64 pci_mem_start_addr;
@@ -160,4 +163,5 @@ struct loongson_system_configuration { · 8 unmodified lines
160163
161164 extern struct efi_memory_map_loongson *loongson_memmap;
162165 extern struct loongson_system_configuration loongson_sysconf;
166+extern int cpuhotplug_workaround;
163167 #endif
arch/mips/include/asm/mach-loongson/kernel-entry-init.h+52−0
@@ -0,0 +1,52 @@
1+/*
2+ * This file is subject to the terms and conditions of the GNU General Public
3+ * License. See the file "COPYING" in the main directory of this archive
4+ * for more details.
5+ *
6+ * Copyright (C) 2005 Embedded Alley Solutions, Inc
7+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
8+ * Copyright (C) 2009 Jiajie Chen (chenjiajie@cse.buaa.edu.cn)
9+ * Copyright (C) 2012 Huacai Chen (chenhc@lemote.com)
10+ */
11+#ifndef __ASM_MACH_LOONGSON_KERNEL_ENTRY_H
12+#define __ASM_MACH_LOONGSON_KERNEL_ENTRY_H
13+
14+/*
15+ * Override macros used in arch/mips/kernel/head.S.
16+ */
17+ .macro kernel_entry_setup
18+#ifdef CONFIG_CPU_LOONGSON3
19+ .set push
20+ .set mips64
21+ /* Set LPA on LOONGSON3 config3 */
22+ mfc0 t0, $16, 3
23+ or t0, (0x1 << 7)
24+ mtc0 t0, $16, 3
25+ /* Set ELPA on LOONGSON3 pagegrain */
26+ li t0, (0x1 << 29)
27+ mtc0 t0, $5, 1
28+ _ehb
29+ .set pop
30+#endif
31+ .endm
32+
33+/*
34+ * Do SMP slave processor setup.
35+ */
36+ .macro smp_slave_setup
37+#ifdef CONFIG_CPU_LOONGSON3
38+ .set push
39+ .set mips64
40+ /* Set LPA on LOONGSON3 config3 */
41+ mfc0 t0, $16, 3
42+ or t0, (0x1 << 7)
43+ mtc0 t0, $16, 3
44+ /* Set ELPA on LOONGSON3 pagegrain */
45+ li t0, (0x1 << 29)
46+ mtc0 t0, $5, 1
47+ _ehb
48+ .set pop
49+#endif
50+ .endm
51+
52+#endif /* __ASM_MACH_LOONGSON_KERNEL_ENTRY_H */
arch/mips/include/asm/mach-loongson/loongson.h+9−2
@@ -249,8 +249,15 @@ static inline void do_perfcnt_IRQ(void) · 248 unmodified lines
249249 #define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
250250 #define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
251251
252−/* Chip Config */
253−#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80)
252+#define MAX_PACKAGES 4
253+
254+/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
255+extern u64 loongson_chipcfg[MAX_PACKAGES];
256+#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
257+
258+/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */
259+extern u64 loongson_freqctrl[MAX_PACKAGES];
260+#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))
254261
255262 /* pcimap */
256263
arch/mips/include/asm/mach-loongson/machine.h+2−2
@@ -24,10 +24,10 @@ · 23 unmodified lines
2424
2525 #endif
2626
27−#ifdef CONFIG_LEMOTE_MACH3A
27+#ifdef CONFIG_LOONGSON_MACH3X
2828
2929 #define LOONGSON_MACHTYPE MACH_LEMOTE_A1101
3030
31−#endif /* CONFIG_LEMOTE_MACH3A */
31+#endif /* CONFIG_LOONGSON_MACH3X */
3232
3333 #endif /* __ASM_MACH_LOONGSON_MACHINE_H */
arch/mips/include/asm/mach-loongson/mmzone.h+53−0
@@ -0,0 +1,53 @@
1+/*
2+ * Copyright (C) 2010 Loongson Inc. & Lemote Inc. &
3+ * Insititute of Computing Technology
4+ * Author: Xiang Gao, gaoxiang@ict.ac.cn
5+ * Huacai Chen, chenhc@lemote.com
6+ * Xiaofu Meng, Shuangshuang Zhang
7+ *
8+ * This program is free software; you can redistribute it and/or modify it
9+ * under the terms of the GNU General Public License as published by the
10+ * Free Software Foundation; either version 2 of the License, or (at your
11+ * option) any later version.
12+ */
13+#ifndef _ASM_MACH_MMZONE_H
14+#define _ASM_MACH_MMZONE_H
15+
16+#include <boot_param.h>
17+#define NODE_ADDRSPACE_SHIFT 44
18+#define NODE0_ADDRSPACE_OFFSET 0x000000000000UL
19+#define NODE1_ADDRSPACE_OFFSET 0x100000000000UL
20+#define NODE2_ADDRSPACE_OFFSET 0x200000000000UL
21+#define NODE3_ADDRSPACE_OFFSET 0x300000000000UL
22+
23+#define pa_to_nid(addr) (((addr) & 0xf00000000000) >> NODE_ADDRSPACE_SHIFT)
24+
25+#define LEVELS_PER_SLICE 128
26+
27+struct slice_data {
28+ unsigned long irq_enable_mask[2];
29+ int level_to_irq[LEVELS_PER_SLICE];
30+};
31+
32+struct hub_data {
33+ cpumask_t h_cpus;
34+ unsigned long slice_map;
35+ unsigned long irq_alloc_mask[2];
36+ struct slice_data slice[2];
37+};
38+
39+struct node_data {
40+ struct pglist_data pglist;
41+ struct hub_data hub;
42+ cpumask_t cpumask;
43+};
44+
45+extern struct node_data *__node_data[];
46+
47+#define NODE_DATA(n) (&__node_data[(n)]->pglist)
48+#define hub_data(n) (&__node_data[(n)]->hub)
49+
50+extern void setup_zero_pages(void);
51+extern void __init prom_init_numa_memory(void);
52+
53+#endif /* _ASM_MACH_MMZONE_H */
arch/mips/include/asm/mach-loongson/topology.h+23−0
@@ -0,0 +1,23 @@
1+#ifndef _ASM_MACH_TOPOLOGY_H
2+#define _ASM_MACH_TOPOLOGY_H
3+
4+#ifdef CONFIG_NUMA
5+
6+#define cpu_to_node(cpu) ((cpu) >> 2)
7+#define parent_node(node) (node)
8+#define cpumask_of_node(node) (&__node_data[(node)]->cpumask)
9+
10+struct pci_bus;
11+extern int pcibus_to_node(struct pci_bus *);
12+
13+#define cpumask_of_pcibus(bus) (cpu_online_mask)
14+
15+extern unsigned char __node_distances[MAX_NUMNODES][MAX_NUMNODES];
16+
17+#define node_distance(from, to) (__node_distances[(from)][(to)])
18+
19+#endif
20+
21+#include <asm-generic/topology.h>
22+
23+#endif /* _ASM_MACH_TOPOLOGY_H */
arch/mips/include/asm/mach-malta/irq.h+1−0
@@ -2,6 +2,7 @@ · 1 unmodified line
22 #define __ASM_MACH_MIPS_IRQ_H
33
44
5+#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
56 #define NR_IRQS 256
67
78 #include_next <irq.h>
arch/mips/include/asm/mach-sead3/irq.h+1−0
@@ -1,6 +1,7 @@
11 #ifndef __ASM_MACH_MIPS_IRQ_H
22 #define __ASM_MACH_MIPS_IRQ_H
33
4+#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
45 #define NR_IRQS 256
56
67
arch/mips/include/asm/mips-boards/bonito64.h+0−1
@@ -413,7 +413,6 @@ extern unsigned long _pcictrl_bonito_pcicfg; · 412 unmodified lines
413413 #define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
414414
415415
416−#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
417416 #define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
418417 #define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
419418
arch/mips/include/asm/mipsregs.h+57−1
@@ -265,6 +265,7 @@ · 264 unmodified lines
265265 #define PG_XIE (_ULCAST_(1) << 30)
266266 #define PG_ELPA (_ULCAST_(1) << 29)
267267 #define PG_ESP (_ULCAST_(1) << 28)
268+#define PG_IEC (_ULCAST_(1) << 27)
268269
269270 /*
270271 * R4x00 interrupt enable / cause bits
@@ -630,7 +631,6 @@ · 359 unmodified lines
630631 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
631632 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
632633 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
633−#define MIPS_CONF4_FTLBSETS_SHIFT (0)
634634 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
635635 #define MIPS_CONF4_FTLBWAYS_SHIFT (4)
636636 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
@@ -652,6 +652,7 @@ · 15 unmodified lines
652652
653653 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
654654 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
655+#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
655656 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
656657 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
657658 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
@@ -668,6 +669,12 @@ · 10 unmodified lines
668669 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
669670 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
670671
672+/* MAAR bit definitions */
673+#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
674+#define MIPS_MAAR_ADDR_SHIFT 12
675+#define MIPS_MAAR_S (_ULCAST_(1) << 1)
676+#define MIPS_MAAR_V (_ULCAST_(1) << 0)
677+
671678 /* EntryHI bit definition */
672679 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
673680
@@ -706,6 +713,37 @@ · 32 unmodified lines
706713 #define MIPS_SEGCFG_MK _ULCAST_(1)
707714 #define MIPS_SEGCFG_UK _ULCAST_(0)
708715
716+#define MIPS_PWFIELD_GDI_SHIFT 24
717+#define MIPS_PWFIELD_GDI_MASK 0x3f000000
718+#define MIPS_PWFIELD_UDI_SHIFT 18
719+#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
720+#define MIPS_PWFIELD_MDI_SHIFT 12
721+#define MIPS_PWFIELD_MDI_MASK 0x0003f000
722+#define MIPS_PWFIELD_PTI_SHIFT 6
723+#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
724+#define MIPS_PWFIELD_PTEI_SHIFT 0
725+#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
726+
727+#define MIPS_PWSIZE_GDW_SHIFT 24
728+#define MIPS_PWSIZE_GDW_MASK 0x3f000000
729+#define MIPS_PWSIZE_UDW_SHIFT 18
730+#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
731+#define MIPS_PWSIZE_MDW_SHIFT 12
732+#define MIPS_PWSIZE_MDW_MASK 0x0003f000
733+#define MIPS_PWSIZE_PTW_SHIFT 6
734+#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
735+#define MIPS_PWSIZE_PTEW_SHIFT 0
736+#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
737+
738+#define MIPS_PWCTL_PWEN_SHIFT 31
739+#define MIPS_PWCTL_PWEN_MASK 0x80000000
740+#define MIPS_PWCTL_DPH_SHIFT 7
741+#define MIPS_PWCTL_DPH_MASK 0x00000080
742+#define MIPS_PWCTL_HUGEPG_SHIFT 6
743+#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
744+#define MIPS_PWCTL_PSN_SHIFT 0
745+#define MIPS_PWCTL_PSN_MASK 0x0000003f
746+
709747 #ifndef __ASSEMBLY__
710748
711749 /*
@@ -1044,6 +1082,11 @@ do { \ · 332 unmodified lines
10441082 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
10451083 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
10461084
1085+#define read_c0_maar() __read_ulong_c0_register($17, 1)
1086+#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1087+#define read_c0_maari() __read_32bit_c0_register($17, 2)
1088+#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1089+
10471090 /*
10481091 * The WatchLo register. There may be up to 8 of them.
10491092 */
@@ -1201,6 +1244,19 @@ do { \ · 151 unmodified lines
12011244 #define read_c0_segctl2() __read_32bit_c0_register($5, 4)
12021245 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
12031246
1247+/* Hardware Page Table Walker */
1248+#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1249+#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1250+
1251+#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1252+#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1253+
1254+#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1255+#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1256+
1257+#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1258+#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1259+
12041260 /* Cavium OCTEON (cnMIPS) */
12051261 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
12061262 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
arch/mips/include/asm/mmu_context.h+10−0
@@ -20,10 +20,20 @@ · 19 unmodified lines
2020 #include <asm/tlbflush.h>
2121 #include <asm-generic/mm_hooks.h>
2222
23+#define htw_set_pwbase(pgd) \
24+do { \
25+ if (cpu_has_htw) { \
26+ write_c0_pwbase(pgd); \
27+ back_to_back_c0_hazard(); \
28+ htw_reset(); \
29+ } \
30+} while (0)
31+
2332 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \
2433 do { \
2534 extern void tlbmiss_handler_setup_pgd(unsigned long); \
2635 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
36+ htw_set_pwbase((unsigned long)pgd); \
2737 } while (0)
2838
2939 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
arch/mips/include/asm/msa.h+18−13
@@ -12,8 +12,11 @@ · 11 unmodified lines
1212
1313 #include <asm/mipsregs.h>
1414
15+#ifndef __ASSEMBLY__
16+
1517 extern void _save_msa(struct task_struct *);
1618 extern void _restore_msa(struct task_struct *);
19+extern void _init_msa_upper(void);
1720
1821 static inline void enable_msa(void)
1922 {
@@ -112,10 +115,10 @@ static inline unsigned int read_msa_##name(void) \ · 92 unmodified lines
112115 " .set push\n" \
113116 " .set noat\n" \
114117 " .insn\n" \
115− " .word #CFC_MSA_INSN | (" #cs " << 11)\n" \
118+ " .word %1 | (" #cs " << 11)\n" \
116119 " move %0, $1\n" \
117120 " .set pop\n" \
118− : "=r"(reg)); \
121+ : "=r"(reg) : "i"(CFC_MSA_INSN)); \
119122 return reg; \
120123 } \
121124 \
@@ -126,22 +129,13 @@ static inline void write_msa_##name(unsigned int val) \ · 4 unmodified lines
126129 " .set noat\n" \
127130 " move $1, %0\n" \
128131 " .insn\n" \
129− " .word #CTC_MSA_INSN | (" #cs " << 6)\n" \
132+ " .word %1 | (" #cs " << 6)\n" \
130133 " .set pop\n" \
131− : : "r"(val)); \
134+ : : "r"(val), "i"(CTC_MSA_INSN)); \
132135 }
133136
134137 #endif /* !TOOLCHAIN_SUPPORTS_MSA */
135138
136−#define MSA_IR 0
137−#define MSA_CSR 1
138−#define MSA_ACCESS 2
139−#define MSA_SAVE 3
140−#define MSA_MODIFY 4
141−#define MSA_REQUEST 5
142−#define MSA_MAP 6
143−#define MSA_UNMAP 7
144−
145139 __BUILD_MSA_CTL_REG(ir, 0)
146140 __BUILD_MSA_CTL_REG(csr, 1)
147141 __BUILD_MSA_CTL_REG(access, 2)
@@ -151,6 +145,17 @@ __BUILD_MSA_CTL_REG(request, 5) · 3 unmodified lines
151145 __BUILD_MSA_CTL_REG(map, 6)
152146 __BUILD_MSA_CTL_REG(unmap, 7)
153147
148+#endif /* !__ASSEMBLY__ */
149+
150+#define MSA_IR 0
151+#define MSA_CSR 1
152+#define MSA_ACCESS 2
153+#define MSA_SAVE 3
154+#define MSA_MODIFY 4
155+#define MSA_REQUEST 5
156+#define MSA_MAP 6
157+#define MSA_UNMAP 7
158+
154159 /* MSA Implementation Register (MSAIR) */
155160 #define MSA_IR_REVB 0
156161 #define MSA_IR_REVF (_ULCAST_(0xff) << MSA_IR_REVB)
arch/mips/include/asm/octeon/cvmx-bootinfo.h+2−0
@@ -228,6 +228,7 @@ enum cvmx_board_types_enum { · 227 unmodified lines
228228 */
229229 CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
230230 CVMX_BOARD_TYPE_UBNT_E100 = 20002,
231+ CVMX_BOARD_TYPE_CUST_DSR1000N = 20006,
231232 CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
232233
233234 /* The remaining range is reserved for future use. */
@@ -327,6 +328,7 @@ static inline const char *cvmx_board_type_to_string(enum · 93 unmodified lines
327328 /* Customer private range */
328329 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
329330 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)
331+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N)
330332 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
331333 }
332334 return "Unsupported Board";
arch/mips/include/asm/pgtable-32.h+12−0
@@ -18,6 +18,18 @@ · 17 unmodified lines
1818
1919 #include <asm-generic/pgtable-nopmd.h>
2020
21+extern int temp_tlb_entry __cpuinitdata;
22+
23+/*
24+ * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
25+ * starting at the top and working down. This is for populating the
26+ * TLB before trap_init() puts the TLB miss handler in place. It
27+ * should be used only for entries matching the actual page tables,
28+ * to prevent inconsistencies.
29+ */
30+extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
31+ unsigned long entryhi, unsigned long pagemask);
32+
2133 /*
2234 * Basically we have the same two-level (which is the logical three level
2335 * Linux page table layout folded) page tables as the i386. Some day
arch/mips/include/asm/pgtable.h+27−0
@@ -97,6 +97,31 @@ extern void paging_init(void); · 96 unmodified lines
9797
9898 #define pmd_page_vaddr(pmd) pmd_val(pmd)
9999
100+#define htw_stop() \
101+do { \
102+ if (cpu_has_htw) \
103+ write_c0_pwctl(read_c0_pwctl() & \
104+ ~(1 << MIPS_PWCTL_PWEN_SHIFT)); \
105+} while(0)
106+
107+#define htw_start() \
108+do { \
109+ if (cpu_has_htw) \
110+ write_c0_pwctl(read_c0_pwctl() | \
111+ (1 << MIPS_PWCTL_PWEN_SHIFT)); \
112+} while(0)
113+
114+
115+#define htw_reset() \
116+do { \
117+ if (cpu_has_htw) { \
118+ htw_stop(); \
119+ back_to_back_c0_hazard(); \
120+ htw_start(); \
121+ back_to_back_c0_hazard(); \
122+ } \
123+} while(0)
124+
100125 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
101126
102127 #define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
@@ -131,6 +156,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt · 28 unmodified lines
131156 null.pte_low = null.pte_high = _PAGE_GLOBAL;
132157
133158 set_pte_at(mm, addr, ptep, null);
159+ htw_reset();
134160 }
135161 #else
136162
@@ -168,6 +194,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt · 31 unmodified lines
168194 else
169195 #endif
170196 set_pte_at(mm, addr, ptep, __pte(0));
197+ htw_reset();
171198 }
172199 #endif
173200
arch/mips/include/asm/processor.h+8−2
@@ -238,7 +238,13 @@ typedef struct { · 237 unmodified lines
238238 unsigned long seg;
239239 } mm_segment_t;
240240
241−#define ARCH_MIN_TASKALIGN 8
241+#ifdef CONFIG_CPU_HAS_MSA
242+# define ARCH_MIN_TASKALIGN 16
243+# define FPU_ALIGN __aligned(16)
244+#else
245+# define ARCH_MIN_TASKALIGN 8
246+# define FPU_ALIGN
247+#endif
242248
243249 struct mips_abi;
244250
@@ -255,7 +261,7 @@ struct thread_struct { · 10 unmodified lines
255261 unsigned long cp0_status;
256262
257263 /* Saved fpu/fpu emulator stuff. */
258− struct mips_fpu_struct fpu;
264+ struct mips_fpu_struct fpu FPU_ALIGN;
259265 #ifdef CONFIG_MIPS_MT_FPAFF
260266 /* Emulated instruction count */
261267 unsigned long emulated_fp;
arch/mips/include/asm/ptrace.h+5−3
@@ -23,7 +23,7 @@ · 22 unmodified lines
2323 struct pt_regs {
2424 #ifdef CONFIG_32BIT
2525 /* Pad bytes for argument save space on the stack. */
26− unsigned long pad0[6];
26+ unsigned long pad0[8];
2727 #endif
2828
2929 /* Saved main processor registers. */
@@ -47,8 +47,10 @@ struct pt_regs { · 17 unmodified lines
4747
4848 struct task_struct;
4949
50−extern int ptrace_getregs(struct task_struct *child, __s64 __user *data);
51−extern int ptrace_setregs(struct task_struct *child, __s64 __user *data);
50+extern int ptrace_getregs(struct task_struct *child,
51+ struct user_pt_regs __user *data);
52+extern int ptrace_setregs(struct task_struct *child,
53+ struct user_pt_regs __user *data);
5254
5355 extern int ptrace_getfpregs(struct task_struct *child, __u32 __user *data);
5456 extern int ptrace_setfpregs(struct task_struct *child, __u32 __user *data);
arch/mips/include/asm/reg.h+1−128
@@ -1,128 +1 @@
1−/*
2− * Various register offset definitions for debuggers, core file
3− * examiners and whatnot.
4− *
5− * This file is subject to the terms and conditions of the GNU General Public
6− * License. See the file "COPYING" in the main directory of this archive
7− * for more details.
8− *
9− * Copyright (C) 1995, 1999 Ralf Baechle
10− * Copyright (C) 1995, 1999 Silicon Graphics
11− */
12−#ifndef __ASM_MIPS_REG_H
13−#define __ASM_MIPS_REG_H
14−
15−
16−#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H)
17−
18−#define EF_R0 6
19−#define EF_R1 7
20−#define EF_R2 8
21−#define EF_R3 9
22−#define EF_R4 10
23−#define EF_R5 11
24−#define EF_R6 12
25−#define EF_R7 13
26−#define EF_R8 14
27−#define EF_R9 15
28−#define EF_R10 16
29−#define EF_R11 17
30−#define EF_R12 18
31−#define EF_R13 19
32−#define EF_R14 20
33−#define EF_R15 21
34−#define EF_R16 22
35−#define EF_R17 23
36−#define EF_R18 24
37−#define EF_R19 25
38−#define EF_R20 26
39−#define EF_R21 27
40−#define EF_R22 28
41−#define EF_R23 29
42−#define EF_R24 30
43−#define EF_R25 31
44−
45−/*
46− * k0/k1 unsaved
47− */
48−#define EF_R26 32
49−#define EF_R27 33
50−
51−#define EF_R28 34
52−#define EF_R29 35
53−#define EF_R30 36
54−#define EF_R31 37
55−
56−/*
57− * Saved special registers
58− */
59−#define EF_LO 38
60−#define EF_HI 39
61−
62−#define EF_CP0_EPC 40
63−#define EF_CP0_BADVADDR 41
64−#define EF_CP0_STATUS 42
65−#define EF_CP0_CAUSE 43
66−#define EF_UNUSED0 44
67−
68−#define EF_SIZE 180
69−
70−#endif
71−
72−#if defined(CONFIG_64BIT) && !defined(WANT_COMPAT_REG_H)
73−
74−#define EF_R0 0
75−#define EF_R1 1
76−#define EF_R2 2
77−#define EF_R3 3
78−#define EF_R4 4
79−#define EF_R5 5
80−#define EF_R6 6
81−#define EF_R7 7
82−#define EF_R8 8
83−#define EF_R9 9
84−#define EF_R10 10
85−#define EF_R11 11
86−#define EF_R12 12
87−#define EF_R13 13
88−#define EF_R14 14
89−#define EF_R15 15
90−#define EF_R16 16
91−#define EF_R17 17
92−#define EF_R18 18
93−#define EF_R19 19
94−#define EF_R20 20
95−#define EF_R21 21
96−#define EF_R22 22
97−#define EF_R23 23
98−#define EF_R24 24
99−#define EF_R25 25
100−
101−/*
102− * k0/k1 unsaved
103− */
104−#define EF_R26 26
105−#define EF_R27 27
106−
107−
108−#define EF_R28 28
109−#define EF_R29 29
110−#define EF_R30 30
111−#define EF_R31 31
112−
113−/*
114− * Saved special registers
115− */
116−#define EF_LO 32
117−#define EF_HI 33
118−
119−#define EF_CP0_EPC 34
120−#define EF_CP0_BADVADDR 35
121−#define EF_CP0_STATUS 36
122−#define EF_CP0_CAUSE 37
123−
124−#define EF_SIZE 304 /* size in bytes */
125−
126−#endif /* CONFIG_64BIT */
127−
128−#endif /* __ASM_MIPS_REG_H */
1+#include <uapi/asm/reg.h>
arch/mips/include/asm/smp-cps.h+10−2
@@ -31,11 +31,19 @@ extern void mips_cps_core_init(void); · 30 unmodified lines
3131
3232 extern struct vpe_boot_config *mips_cps_boot_vpes(void);
3333
34−extern bool mips_cps_smp_in_use(void);
35−
3634 extern void mips_cps_pm_save(void);
3735 extern void mips_cps_pm_restore(void);
3836
37+#ifdef CONFIG_MIPS_CPS
38+
39+extern bool mips_cps_smp_in_use(void);
40+
41+#else /* !CONFIG_MIPS_CPS */
42+
43+static inline bool mips_cps_smp_in_use(void) { return false; }
44+
45+#endif /* !CONFIG_MIPS_CPS */
46+
3947 #else /* __ASSEMBLY__ */
4048
4149 .extern mips_cps_bootcfg;
arch/mips/include/asm/smp.h+6−0
@@ -22,6 +22,7 @@ · 21 unmodified lines
2222
2323 extern int smp_num_siblings;
2424 extern cpumask_t cpu_sibling_map[];
25+extern cpumask_t cpu_core_map[];
2526
2627 #define raw_smp_processor_id() (current_thread_info()->cpu)
2728
@@ -36,6 +37,11 @@ extern int __cpu_logical_map[NR_CPUS]; · 8 unmodified lines
3637
3738 #define NO_PROC_ID (-1)
3839
40+#define topology_physical_package_id(cpu) (cpu_data[cpu].package)
41+#define topology_core_id(cpu) (cpu_data[cpu].core)
42+#define topology_core_cpumask(cpu) (&cpu_core_map[cpu])
43+#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu])
44+
3945 #define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
4046 #define SMP_CALL_FUNCTION 0x2
4147 /* Octeon - Tell another core to flush its icache */
arch/mips/include/asm/sparsemem.h+1−1
@@ -11,7 +11,7 @@ · 10 unmodified lines
1111 #else
1212 # define SECTION_SIZE_BITS 28
1313 #endif
14−#define MAX_PHYSMEM_BITS 35
14+#define MAX_PHYSMEM_BITS 48
1515
1616 #endif /* CONFIG_SPARSEMEM */
1717 #endif /* _MIPS_SPARSEMEM_H */
arch/mips/include/asm/user.h+0−58
@@ -1,58 +0,0 @@
1−/*
2− * This file is subject to the terms and conditions of the GNU General Public
3− * License. See the file "COPYING" in the main directory of this archive
4− * for more details.
5− *
6− * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
7− */
8−#ifndef _ASM_USER_H
9−#define _ASM_USER_H
10−
11−#include <asm/page.h>
12−#include <asm/reg.h>
13−
14−/*
15− * Core file format: The core file is written in such a way that gdb
16− * can understand it and provide useful information to the user (under
17− * linux we use the `trad-core' bfd, NOT the irix-core). The file
18− * contents are as follows:
19− *
20− * upage: 1 page consisting of a user struct that tells gdb
21− * what is present in the file. Directly after this is a
22− * copy of the task_struct, which is currently not used by gdb,
23− * but it may come in handy at some point. All of the registers
24− * are stored as part of the upage. The upage should always be
25− * only one page long.
26− * data: The data segment follows next. We use current->end_text to
27− * current->brk to pick up all of the user variables, plus any memory
28− * that may have been sbrk'ed. No attempt is made to determine if a
29− * page is demand-zero or if a page is totally unused, we just cover
30− * the entire range. All of the addresses are rounded in such a way
31− * that an integral number of pages is written.
32− * stack: We need the stack information in order to get a meaningful
33− * backtrace. We need to write the data from usp to
34− * current->start_stack, so we round each of these in order to be able
35− * to write an integer number of pages.
36− */
37−struct user {
38− unsigned long regs[EF_SIZE / /* integer and fp regs */
39− sizeof(unsigned long) + 64];
40− size_t u_tsize; /* text size (pages) */
41− size_t u_dsize; /* data size (pages) */
42− size_t u_ssize; /* stack size (pages) */
43− unsigned long start_code; /* text starting address */
44− unsigned long start_data; /* data starting address */
45− unsigned long start_stack; /* stack starting address */
46− long int signal; /* signal causing core dump */
47− unsigned long u_ar0; /* help gdb find registers */
48− unsigned long magic; /* identifies a core file */
49− char u_comm[32]; /* user command name */
50−};
51−
52−#define NBPG PAGE_SIZE
53−#define UPAGES 1
54−#define HOST_TEXT_START_ADDR (u.start_code)
55−#define HOST_DATA_START_ADDR (u.start_data)
56−#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
57−
58−#endif /* _ASM_USER_H */
arch/mips/include/uapi/asm/ptrace.h+14−11
@@ -22,24 +22,27 @@ · 21 unmodified lines
2222 #define DSP_CONTROL 77
2323 #define ACX 78
2424
25−#ifndef __KERNEL__
2625 /*
27− * This struct defines the way the registers are stored on the stack during a
28− * system call/exception. As usual the registers k0/k1 aren't being saved.
26+ * This struct defines the registers as used by PTRACE_{GET,SET}REGS. The
27+ * format is the same for both 32- and 64-bit processes. Registers for 32-bit
28+ * processes are sign extended.
2929 */
30+#ifdef __KERNEL__
31+struct user_pt_regs {
32+#else
3033 struct pt_regs {
34+#endif
3135 /* Saved main processor registers. */
32− unsigned long regs[32];
36+ __u64 regs[32];
3337
3438 /* Saved special registers. */
35− unsigned long cp0_status;
36− unsigned long hi;
37− unsigned long lo;
38− unsigned long cp0_badvaddr;
39− unsigned long cp0_cause;
40− unsigned long cp0_epc;
39+ __u64 lo;
40+ __u64 hi;
41+ __u64 cp0_epc;
42+ __u64 cp0_badvaddr;
43+ __u64 cp0_status;
44+ __u64 cp0_cause;
4145 } __attribute__ ((aligned (8)));
42−#endif /* __KERNEL__ */
4346
4447 /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
4548 #define PTRACE_GETREGS 12
arch/mips/include/uapi/asm/reg.h+206−0
@@ -0,0 +1,206 @@
1+/*
2+ * Various register offset definitions for debuggers, core file
3+ * examiners and whatnot.
4+ *
5+ * This file is subject to the terms and conditions of the GNU General Public
6+ * License. See the file "COPYING" in the main directory of this archive
7+ * for more details.
8+ *
9+ * Copyright (C) 1995, 1999 Ralf Baechle
10+ * Copyright (C) 1995, 1999 Silicon Graphics
11+ */
12+#ifndef __UAPI_ASM_MIPS_REG_H
13+#define __UAPI_ASM_MIPS_REG_H
14+
15+#define MIPS32_EF_R0 6
16+#define MIPS32_EF_R1 7
17+#define MIPS32_EF_R2 8
18+#define MIPS32_EF_R3 9
19+#define MIPS32_EF_R4 10
20+#define MIPS32_EF_R5 11
21+#define MIPS32_EF_R6 12
22+#define MIPS32_EF_R7 13
23+#define MIPS32_EF_R8 14
24+#define MIPS32_EF_R9 15
25+#define MIPS32_EF_R10 16
26+#define MIPS32_EF_R11 17
27+#define MIPS32_EF_R12 18
28+#define MIPS32_EF_R13 19
29+#define MIPS32_EF_R14 20
30+#define MIPS32_EF_R15 21
31+#define MIPS32_EF_R16 22
32+#define MIPS32_EF_R17 23
33+#define MIPS32_EF_R18 24
34+#define MIPS32_EF_R19 25
35+#define MIPS32_EF_R20 26
36+#define MIPS32_EF_R21 27
37+#define MIPS32_EF_R22 28
38+#define MIPS32_EF_R23 29
39+#define MIPS32_EF_R24 30
40+#define MIPS32_EF_R25 31
41+
42+/*
43+ * k0/k1 unsaved
44+ */
45+#define MIPS32_EF_R26 32
46+#define MIPS32_EF_R27 33
47+
48+#define MIPS32_EF_R28 34
49+#define MIPS32_EF_R29 35
50+#define MIPS32_EF_R30 36
51+#define MIPS32_EF_R31 37
52+
53+/*
54+ * Saved special registers
55+ */
56+#define MIPS32_EF_LO 38
57+#define MIPS32_EF_HI 39
58+
59+#define MIPS32_EF_CP0_EPC 40
60+#define MIPS32_EF_CP0_BADVADDR 41
61+#define MIPS32_EF_CP0_STATUS 42
62+#define MIPS32_EF_CP0_CAUSE 43
63+#define MIPS32_EF_UNUSED0 44
64+
65+#define MIPS32_EF_SIZE 180
66+
67+#define MIPS64_EF_R0 0
68+#define MIPS64_EF_R1 1
69+#define MIPS64_EF_R2 2
70+#define MIPS64_EF_R3 3
71+#define MIPS64_EF_R4 4
72+#define MIPS64_EF_R5 5
73+#define MIPS64_EF_R6 6
74+#define MIPS64_EF_R7 7
75+#define MIPS64_EF_R8 8
76+#define MIPS64_EF_R9 9
77+#define MIPS64_EF_R10 10
78+#define MIPS64_EF_R11 11
79+#define MIPS64_EF_R12 12
80+#define MIPS64_EF_R13 13
81+#define MIPS64_EF_R14 14
82+#define MIPS64_EF_R15 15
83+#define MIPS64_EF_R16 16
84+#define MIPS64_EF_R17 17
85+#define MIPS64_EF_R18 18
86+#define MIPS64_EF_R19 19
87+#define MIPS64_EF_R20 20
88+#define MIPS64_EF_R21 21
89+#define MIPS64_EF_R22 22
90+#define MIPS64_EF_R23 23
91+#define MIPS64_EF_R24 24
92+#define MIPS64_EF_R25 25
93+
94+/*
95+ * k0/k1 unsaved
96+ */
97+#define MIPS64_EF_R26 26
98+#define MIPS64_EF_R27 27
99+
100+
101+#define MIPS64_EF_R28 28
102+#define MIPS64_EF_R29 29
103+#define MIPS64_EF_R30 30
104+#define MIPS64_EF_R31 31
105+
106+/*
107+ * Saved special registers
108+ */
109+#define MIPS64_EF_LO 32
110+#define MIPS64_EF_HI 33
111+
112+#define MIPS64_EF_CP0_EPC 34
113+#define MIPS64_EF_CP0_BADVADDR 35
114+#define MIPS64_EF_CP0_STATUS 36
115+#define MIPS64_EF_CP0_CAUSE 37
116+
117+#define MIPS64_EF_SIZE 304 /* size in bytes */
118+
119+#if _MIPS_SIM == _MIPS_SIM_ABI32
120+
121+#define EF_R0 MIPS32_EF_R0
122+#define EF_R1 MIPS32_EF_R1
123+#define EF_R2 MIPS32_EF_R2
124+#define EF_R3 MIPS32_EF_R3
125+#define EF_R4 MIPS32_EF_R4
126+#define EF_R5 MIPS32_EF_R5
127+#define EF_R6 MIPS32_EF_R6
128+#define EF_R7 MIPS32_EF_R7
129+#define EF_R8 MIPS32_EF_R8
130+#define EF_R9 MIPS32_EF_R9
131+#define EF_R10 MIPS32_EF_R10
132+#define EF_R11 MIPS32_EF_R11
133+#define EF_R12 MIPS32_EF_R12
134+#define EF_R13 MIPS32_EF_R13
135+#define EF_R14 MIPS32_EF_R14
136+#define EF_R15 MIPS32_EF_R15
137+#define EF_R16 MIPS32_EF_R16
138+#define EF_R17 MIPS32_EF_R17
139+#define EF_R18 MIPS32_EF_R18
140+#define EF_R19 MIPS32_EF_R19
141+#define EF_R20 MIPS32_EF_R20
142+#define EF_R21 MIPS32_EF_R21
143+#define EF_R22 MIPS32_EF_R22
144+#define EF_R23 MIPS32_EF_R23
145+#define EF_R24 MIPS32_EF_R24
146+#define EF_R25 MIPS32_EF_R25
147+#define EF_R26 MIPS32_EF_R26
148+#define EF_R27 MIPS32_EF_R27
149+#define EF_R28 MIPS32_EF_R28
150+#define EF_R29 MIPS32_EF_R29
151+#define EF_R30 MIPS32_EF_R30
152+#define EF_R31 MIPS32_EF_R31
153+#define EF_LO MIPS32_EF_LO
154+#define EF_HI MIPS32_EF_HI
155+#define EF_CP0_EPC MIPS32_EF_CP0_EPC
156+#define EF_CP0_BADVADDR MIPS32_EF_CP0_BADVADDR
157+#define EF_CP0_STATUS MIPS32_EF_CP0_STATUS
158+#define EF_CP0_CAUSE MIPS32_EF_CP0_CAUSE
159+#define EF_UNUSED0 MIPS32_EF_UNUSED0
160+#define EF_SIZE MIPS32_EF_SIZE
161+
162+#elif _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
163+
164+#define EF_R0 MIPS64_EF_R0
165+#define EF_R1 MIPS64_EF_R1
166+#define EF_R2 MIPS64_EF_R2
167+#define EF_R3 MIPS64_EF_R3
168+#define EF_R4 MIPS64_EF_R4
169+#define EF_R5 MIPS64_EF_R5
170+#define EF_R6 MIPS64_EF_R6
171+#define EF_R7 MIPS64_EF_R7
172+#define EF_R8 MIPS64_EF_R8
173+#define EF_R9 MIPS64_EF_R9
174+#define EF_R10 MIPS64_EF_R10
175+#define EF_R11 MIPS64_EF_R11
176+#define EF_R12 MIPS64_EF_R12
177+#define EF_R13 MIPS64_EF_R13
178+#define EF_R14 MIPS64_EF_R14
179+#define EF_R15 MIPS64_EF_R15
180+#define EF_R16 MIPS64_EF_R16
181+#define EF_R17 MIPS64_EF_R17
182+#define EF_R18 MIPS64_EF_R18
183+#define EF_R19 MIPS64_EF_R19
184+#define EF_R20 MIPS64_EF_R20
185+#define EF_R21 MIPS64_EF_R21
186+#define EF_R22 MIPS64_EF_R22
187+#define EF_R23 MIPS64_EF_R23
188+#define EF_R24 MIPS64_EF_R24
189+#define EF_R25 MIPS64_EF_R25
190+#define EF_R26 MIPS64_EF_R26
191+#define EF_R27 MIPS64_EF_R27
192+#define EF_R28 MIPS64_EF_R28
193+#define EF_R29 MIPS64_EF_R29
194+#define EF_R30 MIPS64_EF_R30
195+#define EF_R31 MIPS64_EF_R31
196+#define EF_LO MIPS64_EF_LO
197+#define EF_HI MIPS64_EF_HI
198+#define EF_CP0_EPC MIPS64_EF_CP0_EPC
199+#define EF_CP0_BADVADDR MIPS64_EF_CP0_BADVADDR
200+#define EF_CP0_STATUS MIPS64_EF_CP0_STATUS
201+#define EF_CP0_CAUSE MIPS64_EF_CP0_CAUSE
202+#define EF_SIZE MIPS64_EF_SIZE
203+
204+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
205+
206+#endif /* __UAPI_ASM_MIPS_REG_H */
arch/mips/jz4740/clock-debugfs.c+1−2
@@ -87,8 +87,7 @@ void jz4740_clock_debugfs_add_clk(struct clk *clk) · 86 unmodified lines
8787 /* TODO: Locking */
8888 void jz4740_clock_debugfs_update_parent(struct clk *clk)
8989 {
90− if (clk->debugfs_parent_entry)
91− debugfs_remove(clk->debugfs_parent_entry);
90+ debugfs_remove(clk->debugfs_parent_entry);
9291
9392 if (clk->parent) {
9493 char parent_path[100];
arch/mips/jz4740/platform.c+1−1
@@ -59,7 +59,7 @@ struct platform_device jz4740_usb_ohci_device = { · 58 unmodified lines
5959
6060 /* USB Device Controller */
6161 struct platform_device jz4740_udc_xceiv_device = {
62− .name = "usb_phy_gen_xceiv",
62+ .name = "usb_phy_generic",
6363 .id = 0,
6464 };
6565
arch/mips/kernel/asm-offsets.c+1−0
@@ -234,6 +234,7 @@ void output_thread_fpu_defines(void) · 233 unmodified lines
234234 thread.fpu.fpr[31].val64[FPR_IDX(64, 0)]);
235235
236236 OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
237+ OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
237238 BLANK();
238239 }
239240
arch/mips/kernel/binfmt_elfo32.c+0−38
@@ -72,22 +72,6 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; · 71 unmodified lines
7272
7373 #include <asm/processor.h>
7474
75−/*
76− * When this file is selected, we are definitely running a 64bit kernel.
77− * So using the right regs define in asm/reg.h
78− */
79−#define WANT_COMPAT_REG_H
80−
81−/* These MUST be defined before elf.h gets included */
82−extern void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs);
83−#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs);
84−#define ELF_CORE_COPY_TASK_REGS(_tsk, _dest) \
85−({ \
86− int __res = 1; \
87− elf32_core_copy_regs(*(_dest), task_pt_regs(_tsk)); \
88− __res; \
89−})
90−
9175 #include <linux/module.h>
9276 #include <linux/elfcore.h>
9377 #include <linux/compat.h>
@@ -145,28 +129,6 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) · 51 unmodified lines
145129 value->tv_usec = rem / NSEC_PER_USEC;
146130 }
147131
148−void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs)
149−{
150− int i;
151−
152− for (i = 0; i < EF_R0; i++)
153− grp[i] = 0;
154− grp[EF_R0] = 0;
155− for (i = 1; i <= 31; i++)
156− grp[EF_R0 + i] = (elf_greg_t) regs->regs[i];
157− grp[EF_R26] = 0;
158− grp[EF_R27] = 0;
159− grp[EF_LO] = (elf_greg_t) regs->lo;
160− grp[EF_HI] = (elf_greg_t) regs->hi;
161− grp[EF_CP0_EPC] = (elf_greg_t) regs->cp0_epc;
162− grp[EF_CP0_BADVADDR] = (elf_greg_t) regs->cp0_badvaddr;
163− grp[EF_CP0_STATUS] = (elf_greg_t) regs->cp0_status;
164− grp[EF_CP0_CAUSE] = (elf_greg_t) regs->cp0_cause;
165−#ifdef EF_UNUSED0
166− grp[EF_UNUSED0] = 0;
167−#endif
168−}
169−
170132 MODULE_DESCRIPTION("Binary format loader for compatibility with o32 Linux/MIPS binaries");
171133 MODULE_AUTHOR("Ralf Baechle (ralf@linux-mips.org)");
172134
arch/mips/kernel/cpu-probe.c+42−3
@@ -54,6 +54,20 @@ static int __init dsp_disable(char *s) · 53 unmodified lines
5454
5555 __setup("nodsp", dsp_disable);
5656
57+static int mips_htw_disabled;
58+
59+static int __init htw_disable(char *s)
60+{
61+ mips_htw_disabled = 1;
62+ cpu_data[0].options &= ~MIPS_CPU_HTW;
63+ write_c0_pwctl(read_c0_pwctl() &
64+ ~(1 << MIPS_PWCTL_PWEN_SHIFT));
65+
66+ return 1;
67+}
68+
69+__setup("nohtw", htw_disable);
70+
5771 static inline void check_errata(void)
5872 {
5973 struct cpuinfo_mips *c = &current_cpu_data;
@@ -130,14 +144,13 @@ static inline int __cpu_has_fpu(void) · 70 unmodified lines
130144
131145 static inline unsigned long cpu_get_msa_id(void)
132146 {
133− unsigned long status, conf5, msa_id;
147+ unsigned long status, msa_id;
134148
135149 status = read_c0_status();
136150 __enable_fpu(FPU_64BIT);
137− conf5 = read_c0_config5();
138151 enable_msa();
139152 msa_id = read_msa_ir();
140− write_c0_config5(conf5);
153+ disable_msa();
141154 write_c0_status(status);
142155 return msa_id;
143156 }
@@ -321,6 +334,9 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) · 177 unmodified lines
321334 c->options |= MIPS_CPU_SEGMENTS;
322335 if (config3 & MIPS_CONF3_MSA)
323336 c->ases |= MIPS_ASE_MSA;
337+ /* Only tested on 32-bit cores */
338+ if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT))
339+ c->options |= MIPS_CPU_HTW;
324340
325341 return config3 & MIPS_CONF_M;
326342 }
@@ -389,6 +405,8 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c) · 62 unmodified lines
389405
390406 if (config5 & MIPS_CONF5_EVA)
391407 c->options |= MIPS_CPU_EVA;
408+ if (config5 & MIPS_CONF5_MRP)
409+ c->options |= MIPS_CPU_MAAR;
392410
393411 return config5 & MIPS_CONF_M;
394412 }
@@ -421,6 +439,15 @@ static void decode_configs(struct cpuinfo_mips *c) · 26 unmodified lines
421439
422440 mips_probe_watch_registers(c);
423441
442+ if (cpu_has_rixi) {
443+ /* Enable the RIXI exceptions */
444+ write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
445+ back_to_back_c0_hazard();
446+ /* Verify the IEC bit is set */
447+ if (read_c0_pagegrain() & PG_IEC)
448+ c->options |= MIPS_CPU_RIXIEX;
449+ }
450+
424451 #ifndef CONFIG_MIPS_CPS
425452 if (cpu_has_mips_r2) {
426453 c->core = get_ebase_cpunum();
@@ -740,6 +767,12 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) · 313 unmodified lines
740767 __cpu_name[cpu] = "ICT Loongson-3";
741768 set_elf_platform(cpu, "loongson3a");
742769 break;
770+ case PRID_REV_LOONGSON3B_R1:
771+ case PRID_REV_LOONGSON3B_R2:
772+ c->cputype = CPU_LOONGSON3;
773+ __cpu_name[cpu] = "ICT Loongson-3";
774+ set_elf_platform(cpu, "loongson3b");
775+ break;
743776 }
744777
745778 set_isa(c, MIPS_CPU_ISA_III);
@@ -1187,6 +1220,12 @@ void cpu_probe(void) · 441 unmodified lines
11871220 if (mips_dsp_disabled)
11881221 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
11891222
1223+ if (mips_htw_disabled) {
1224+ c->options &= ~MIPS_CPU_HTW;
1225+ write_c0_pwctl(read_c0_pwctl() &
1226+ ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1227+ }
1228+
11901229 if (c->options & MIPS_CPU_FPU) {
11911230 c->fpu_id = cpu_get_fpu_id();
11921231
arch/mips/kernel/ftrace.c+47−9
@@ -63,7 +63,7 @@ static inline int in_kernel_space(unsigned long ip) · 62 unmodified lines
6363 ((unsigned int)(JAL | (((addr) >> 2) & ADDR_MASK)))
6464
6565 static unsigned int insn_jal_ftrace_caller __read_mostly;
66−static unsigned int insn_lui_v1_hi16_mcount __read_mostly;
66+static unsigned int insn_la_mcount[2] __read_mostly;
6767 static unsigned int insn_j_ftrace_graph_caller __maybe_unused __read_mostly;
6868
6969 static inline void ftrace_dyn_arch_init_insns(void)
@@ -71,10 +71,10 @@ static inline void ftrace_dyn_arch_init_insns(void) · 1 unmodified line
7171 u32 *buf;
7272 unsigned int v1;
7373
74− /* lui v1, hi16_mcount */
74+ /* la v1, _mcount */
7575 v1 = 3;
76− buf = (u32 *)&insn_lui_v1_hi16_mcount;
77− UASM_i_LA_mostly(&buf, v1, MCOUNT_ADDR);
76+ buf = (u32 *)&insn_la_mcount[0];
77+ UASM_i_LA(&buf, v1, MCOUNT_ADDR);
7878
7979 /* jal (ftrace_caller + 8), jump over the first two instruction */
8080 buf = (u32 *)&insn_jal_ftrace_caller;
@@ -111,14 +111,47 @@ static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1, · 30 unmodified lines
111111 unsigned int new_code2)
112112 {
113113 int faulted;
114+ mm_segment_t old_fs;
114115
115116 safe_store_code(new_code1, ip, faulted);
116117 if (unlikely(faulted))
117118 return -EFAULT;
118− safe_store_code(new_code2, ip + 4, faulted);
119+
120+ ip += 4;
121+ safe_store_code(new_code2, ip, faulted);
119122 if (unlikely(faulted))
120123 return -EFAULT;
124+
125+ ip -= 4;
126+ old_fs = get_fs();
127+ set_fs(get_ds());
121128 flush_icache_range(ip, ip + 8);
129+ set_fs(old_fs);
130+
131+ return 0;
132+}
133+
134+static int ftrace_modify_code_2r(unsigned long ip, unsigned int new_code1,
135+ unsigned int new_code2)
136+{
137+ int faulted;
138+ mm_segment_t old_fs;
139+
140+ ip += 4;
141+ safe_store_code(new_code2, ip, faulted);
142+ if (unlikely(faulted))
143+ return -EFAULT;
144+
145+ ip -= 4;
146+ safe_store_code(new_code1, ip, faulted);
147+ if (unlikely(faulted))
148+ return -EFAULT;
149+
150+ old_fs = get_fs();
151+ set_fs(get_ds());
152+ flush_icache_range(ip, ip + 8);
153+ set_fs(old_fs);
154+
122155 return 0;
123156 }
124157 #endif
@@ -130,13 +163,14 @@ static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1, · 5 unmodified lines
130163 *
131164 * move at, ra
132165 * jal _mcount --> nop
166+ * sub sp, sp, 8 --> nop (CONFIG_32BIT)
133167 *
134168 * 2. For modules:
135169 *
136170 * 2.1 For KBUILD_MCOUNT_RA_ADDRESS and CONFIG_32BIT
137171 *
138172 * lui v1, hi_16bit_of_mcount --> b 1f (0x10000005)
139− * addiu v1, v1, low_16bit_of_mcount
173+ * addiu v1, v1, low_16bit_of_mcount --> nop (CONFIG_32BIT)
140174 * move at, ra
141175 * move $12, ra_address
142176 * jalr v1
@@ -145,7 +179,7 @@ static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1, · 2 unmodified lines
145179 * 2.2 For the Other situations
146180 *
147181 * lui v1, hi_16bit_of_mcount --> b 1f (0x10000004)
148− * addiu v1, v1, low_16bit_of_mcount
182+ * addiu v1, v1, low_16bit_of_mcount --> nop (CONFIG_32BIT)
149183 * move at, ra
150184 * jalr v1
151185 * nop | move $12, ra_address | sub sp, sp, 8
@@ -184,10 +218,14 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) · 32 unmodified lines
184218 unsigned int new;
185219 unsigned long ip = rec->ip;
186220
187− new = in_kernel_space(ip) ? insn_jal_ftrace_caller :
188− insn_lui_v1_hi16_mcount;
221+ new = in_kernel_space(ip) ? insn_jal_ftrace_caller : insn_la_mcount[0];
189222
223+#ifdef CONFIG_64BIT
190224 return ftrace_modify_code(ip, new);
225+#else
226+ return ftrace_modify_code_2r(ip, new, in_kernel_space(ip) ?
227+ INSN_NOP : insn_la_mcount[1]);
228+#endif
191229 }
192230
193231 #define FTRACE_CALL_IP ((unsigned long)(&ftrace_call))
arch/mips/kernel/irq-gic.c+30−8
@@ -28,6 +28,18 @@ unsigned int gic_irq_flags[GIC_NUM_INTRS]; · 27 unmodified lines
2828 /* The index into this array is the vector # of the interrupt. */
2929 struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
3030
31+struct gic_pcpu_mask {
32+ DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
33+};
34+
35+struct gic_pending_regs {
36+ DECLARE_BITMAP(pending, GIC_NUM_INTRS);
37+};
38+
39+struct gic_intrmask_regs {
40+ DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
41+};
42+
3143 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
3244 static struct gic_pending_regs pending_regs[NR_CPUS];
3345 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
@@ -177,7 +189,7 @@ unsigned int gic_compare_int(void) · 143 unmodified lines
177189 return 0;
178190 }
179191
180−unsigned int gic_get_int(void)
192+void gic_get_int_mask(unsigned long *dst, const unsigned long *src)
181193 {
182194 unsigned int i;
183195 unsigned long *pending, *intrmask, *pcpu_mask;
@@ -202,8 +214,17 @@ unsigned int gic_get_int(void) · 18 unmodified lines
202214
203215 bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
204216 bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
217+ bitmap_and(dst, src, pending, GIC_NUM_INTRS);
218+}
205219
206− return find_first_bit(pending, GIC_NUM_INTRS);
220+unsigned int gic_get_int(void)
221+{
222+ DECLARE_BITMAP(interrupts, GIC_NUM_INTRS);
223+
224+ bitmap_fill(interrupts, GIC_NUM_INTRS);
225+ gic_get_int_mask(interrupts, interrupts);
226+
227+ return find_first_bit(interrupts, GIC_NUM_INTRS);
207228 }
208229
209230 static void gic_mask_irq(struct irq_data *d)
@@ -269,11 +290,13 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, · 59 unmodified lines
269290
270291 /* Setup Intr to Pin mapping */
271292 if (pin & GIC_MAP_TO_NMI_MSK) {
293+ int i;
294+
272295 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
273296 /* FIXME: hack to route NMI to all cpu's */
274− for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
297+ for (i = 0; i < NR_CPUS; i += 32) {
275298 GICWRITE(GIC_REG_ADDR(SHARED,
276− GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
299+ GIC_SH_MAP_TO_VPE_REG_OFF(intr, i)),
277300 0xffffffff);
278301 }
279302 } else {
@@ -299,9 +322,10 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, · 19 unmodified lines
299322
300323 /* Init Intr Masks */
301324 GIC_CLR_INTR_MASK(intr);
325+
302326 /* Initialise per-cpu Interrupt software masks */
303− if (flags & GIC_FLAG_IPI)
304− set_bit(intr, pcpu_masks[cpu].pcpu_mask);
327+ set_bit(intr, pcpu_masks[cpu].pcpu_mask);
328+
305329 if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
306330 GIC_SET_INTR_MASK(intr);
307331 if (trigtype == GIC_TRIG_EDGE)
@@ -340,8 +364,6 @@ static void __init gic_basic_init(int numintrs, int numvpes, · 32 unmodified lines
340364 cpu = intrmap[i].cpunum;
341365 if (cpu == GIC_UNUSED)
342366 continue;
343− if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
344− continue;
345367 gic_setup_intr(i,
346368 intrmap[i].cpunum,
347369 intrmap[i].pin + pin_offset,
arch/mips/kernel/mcount.S+13−0
@@ -80,6 +80,19 @@ _mcount: · 79 unmodified lines
8080 #endif
8181
8282 PTR_SUBU a0, ra, 8 /* arg1: self address */
83+ PTR_LA t1, _stext
84+ sltu t2, a0, t1 /* t2 = (a0 < _stext) */
85+ PTR_LA t1, _etext
86+ sltu t3, t1, a0 /* t3 = (a0 > _etext) */
87+ or t1, t2, t3
88+ beqz t1, ftrace_call
89+ nop
90+#if defined(KBUILD_MCOUNT_RA_ADDRESS) && defined(CONFIG_32BIT)
91+ PTR_SUBU a0, a0, 16 /* arg1: adjust to module's recorded callsite */
92+#else
93+ PTR_SUBU a0, a0, 12
94+#endif
95+
8396 .globl ftrace_call
8497 ftrace_call:
8598 nop /* a placeholder for the call to a real tracing function */
arch/mips/kernel/perf_event_mipsxx.c+34−8
@@ -1386,6 +1386,9 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev) · 1385 unmodified lines
13861386 /* proAptiv */
13871387 #define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b) \
13881388 ((b) == 0 || (b) == 1)
1389+/* P5600 */
1390+#define IS_BOTH_COUNTERS_P5600_EVENT(b) \
1391+ ((b) == 0 || (b) == 1)
13891392
13901393 /* 1004K */
13911394 #define IS_BOTH_COUNTERS_1004K_EVENT(b) \
@@ -1420,20 +1423,23 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev) · 28 unmodified lines
14201423
14211424
14221425 /*
1423− * User can use 0-255 raw events, where 0-127 for the events of even
1424− * counters, and 128-255 for odd counters. Note that bit 7 is used to
1425− * indicate the parity. So, for example, when user wants to take the
1426− * Event Num of 15 for odd counters (by referring to the user manual),
1427− * then 128 needs to be added to 15 as the input for the event config,
1428− * i.e., 143 (0x8F) to be used.
1426+ * For most cores the user can use 0-255 raw events, where 0-127 for the events
1427+ * of even counters, and 128-255 for odd counters. Note that bit 7 is used to
1428+ * indicate the even/odd bank selector. So, for example, when user wants to take
1429+ * the Event Num of 15 for odd counters (by referring to the user manual), then
1430+ * 128 needs to be added to 15 as the input for the event config, i.e., 143 (0x8F)
1431+ * to be used.
1432+ *
1433+ * Some newer cores have even more events, in which case the user can use raw
1434+ * events 0-511, where 0-255 are for the events of even counters, and 256-511
1435+ * are for odd counters, so bit 8 is used to indicate the even/odd bank selector.
14291436 */
14301437 static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
14311438 {
1439+ /* currently most cores have 7-bit event numbers */
14321440 unsigned int raw_id = config & 0xff;
14331441 unsigned int base_id = raw_id & 0x7f;
14341442
1435− raw_event.event_id = base_id;
1436−
14371443 switch (current_cpu_type()) {
14381444 case CPU_24K:
14391445 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
@@ -1483,6 +1489,19 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) · 43 unmodified lines
14831489 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
14841490 #ifdef CONFIG_MIPS_MT_SMP
14851491 raw_event.range = P;
1492+#endif
1493+ break;
1494+ case CPU_P5600:
1495+ /* 8-bit event numbers */
1496+ raw_id = config & 0x1ff;
1497+ base_id = raw_id & 0xff;
1498+ if (IS_BOTH_COUNTERS_P5600_EVENT(base_id))
1499+ raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1500+ else
1501+ raw_event.cntr_mask =
1502+ raw_id > 255 ? CNTR_ODD : CNTR_EVEN;
1503+#ifdef CONFIG_MIPS_MT_SMP
1504+ raw_event.range = P;
14861505 #endif
14871506 break;
14881507 case CPU_1004K:
@@ -1523,6 +1542,8 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) · 34 unmodified lines
15231542 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
15241543 }
15251544
1545+ raw_event.event_id = base_id;
1546+
15261547 return &raw_event;
15271548 }
15281549
@@ -1633,6 +1654,11 @@ init_hw_perf_events(void) · 104 unmodified lines
16331654 mipspmu.general_event_map = &mipsxxcore_event_map2;
16341655 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
16351656 break;
1657+ case CPU_P5600:
1658+ mipspmu.name = "mips/P5600";
1659+ mipspmu.general_event_map = &mipsxxcore_event_map2;
1660+ mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1661+ break;
16361662 case CPU_1004K:
16371663 mipspmu.name = "mips/1004K";
16381664 mipspmu.general_event_map = &mipsxxcore_event_map;
arch/mips/kernel/pm-cps.c+9−1
@@ -149,8 +149,12 @@ int cps_pm_enter_state(enum cps_pm_state state) · 148 unmodified lines
149149
150150 /* Setup the VPE to run mips_cps_pm_restore when started again */
151151 if (config_enabled(CONFIG_CPU_PM) && state == CPS_PM_POWER_GATED) {
152+ /* Power gating relies upon CPS SMP */
153+ if (!mips_cps_smp_in_use())
154+ return -EINVAL;
155+
152156 core_cfg = &mips_cps_core_bootcfg[core];
153− vpe_cfg = &core_cfg->vpe_config[current_cpu_data.vpe_id];
157+ vpe_cfg = &core_cfg->vpe_config[cpu_vpe_id(&current_cpu_data)];
154158 vpe_cfg->pc = (unsigned long)mips_cps_pm_restore;
155159 vpe_cfg->gp = (unsigned long)current_thread_info();
156160 vpe_cfg->sp = 0;
@@ -376,6 +380,10 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) · 219 unmodified lines
376380 memset(relocs, 0, sizeof(relocs));
377381
378382 if (config_enabled(CONFIG_CPU_PM) && state == CPS_PM_POWER_GATED) {
383+ /* Power gating relies upon CPS SMP */
384+ if (!mips_cps_smp_in_use())
385+ goto out_err;
386+
379387 /*
380388 * Save CPU state. Note the non-standard calling convention
381389 * with the return address placed in v0 to avoid clobbering
arch/mips/kernel/proc.c+2−0
@@ -113,6 +113,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) · 112 unmodified lines
113113 if (cpu_has_vz) seq_printf(m, "%s", " vz");
114114 if (cpu_has_msa) seq_printf(m, "%s", " msa");
115115 if (cpu_has_eva) seq_printf(m, "%s", " eva");
116+ if (cpu_has_htw) seq_printf(m, "%s", " htw");
116117 seq_printf(m, "\n");
117118
118119 if (cpu_has_mmips) {
@@ -123,6 +124,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) · 4 unmodified lines
123124 cpu_data[n].srsets);
124125 seq_printf(m, "kscratch registers\t: %d\n",
125126 hweight8(cpu_data[n].kscratch_mask));
127+ seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
126128 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
127129
128130 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
arch/mips/kernel/process.c+4−56
@@ -21,7 +21,6 @@ · 20 unmodified lines
2121 #include <linux/mman.h>
2222 #include <linux/personality.h>
2323 #include <linux/sys.h>
24−#include <linux/user.h>
2524 #include <linux/init.h>
2625 #include <linux/completion.h>
2726 #include <linux/kallsyms.h>
@@ -36,6 +35,7 @@ · 8 unmodified lines
3635 #include <asm/pgtable.h>
3736 #include <asm/mipsregs.h>
3837 #include <asm/processor.h>
38+#include <asm/reg.h>
3939 #include <asm/uaccess.h>
4040 #include <asm/io.h>
4141 #include <asm/elf.h>
@@ -66,6 +66,7 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) · 24 unmodified lines
6666 clear_used_math();
6767 clear_fpu_owner();
6868 init_dsp();
69+ clear_thread_flag(TIF_USEDMSA);
6970 clear_thread_flag(TIF_MSA_CTX_LIVE);
7071 disable_msa();
7172 regs->cp0_epc = pc;
@@ -141,6 +142,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, · 69 unmodified lines
141142 childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
142143
143144 clear_tsk_thread_flag(p, TIF_USEDFPU);
145+ clear_tsk_thread_flag(p, TIF_USEDMSA);
146+ clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE);
144147
145148 #ifdef CONFIG_MIPS_MT_FPAFF
146149 clear_tsk_thread_flag(p, TIF_FPUBOUND);
@@ -152,61 +155,6 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, · 5 unmodified lines
152155 return 0;
153156 }
154157
155−/* Fill in the fpu structure for a core dump.. */
156−int dump_fpu(struct pt_regs *regs, elf_fpregset_t *r)
157−{
158− int i;
159−
160− for (i = 0; i < NUM_FPU_REGS; i++)
161− memcpy(&r[i], &current->thread.fpu.fpr[i], sizeof(*r));
162−
163− memcpy(&r[NUM_FPU_REGS], &current->thread.fpu.fcr31,
164− sizeof(current->thread.fpu.fcr31));
165−
166− return 1;
167−}
168−
169−void elf_dump_regs(elf_greg_t *gp, struct pt_regs *regs)
170−{
171− int i;
172−
173− for (i = 0; i < EF_R0; i++)
174− gp[i] = 0;
175− gp[EF_R0] = 0;
176− for (i = 1; i <= 31; i++)
177− gp[EF_R0 + i] = regs->regs[i];
178− gp[EF_R26] = 0;
179− gp[EF_R27] = 0;
180− gp[EF_LO] = regs->lo;
181− gp[EF_HI] = regs->hi;
182− gp[EF_CP0_EPC] = regs->cp0_epc;
183− gp[EF_CP0_BADVADDR] = regs->cp0_badvaddr;
184− gp[EF_CP0_STATUS] = regs->cp0_status;
185− gp[EF_CP0_CAUSE] = regs->cp0_cause;
186−#ifdef EF_UNUSED0
187− gp[EF_UNUSED0] = 0;
188−#endif
189−}
190−
191−int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
192−{
193− elf_dump_regs(*regs, task_pt_regs(tsk));
194− return 1;
195−}
196−
197−int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpr)
198−{
199− int i;
200−
201− for (i = 0; i < NUM_FPU_REGS; i++)
202− memcpy(&fpr[i], &t->thread.fpu.fpr[i], sizeof(*fpr));
203−
204− memcpy(&fpr[NUM_FPU_REGS], &t->thread.fpu.fcr31,
205− sizeof(t->thread.fpu.fcr31));
206−
207− return 1;
208−}
209−
210158 #ifdef CONFIG_CC_STACKPROTECTOR
211159 #include <linux/stackprotector.h>
212160 unsigned long __stack_chk_guard __read_mostly;
arch/mips/kernel/ptrace.c+177−46
@@ -24,7 +24,6 @@ · 23 unmodified lines
2424 #include <linux/ptrace.h>
2525 #include <linux/regset.h>
2626 #include <linux/smp.h>
27−#include <linux/user.h>
2827 #include <linux/security.h>
2928 #include <linux/tracehook.h>
3029 #include <linux/audit.h>
@@ -63,7 +62,7 @@ void ptrace_disable(struct task_struct *child) · 32 unmodified lines
6362 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
6463 * Registers are sign extended to fill the available space.
6564 */
66−int ptrace_getregs(struct task_struct *child, __s64 __user *data)
65+int ptrace_getregs(struct task_struct *child, struct user_pt_regs __user *data)
6766 {
6867 struct pt_regs *regs;
6968 int i;
@@ -74,13 +73,13 @@ int ptrace_getregs(struct task_struct *child, __s64 __user *data) · 4 unmodified lines
7473 regs = task_pt_regs(child);
7574
7675 for (i = 0; i < 32; i++)
77− __put_user((long)regs->regs[i], data + i);
78− __put_user((long)regs->lo, data + EF_LO - EF_R0);
79− __put_user((long)regs->hi, data + EF_HI - EF_R0);
80− __put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
81− __put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
82− __put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
83− __put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
76+ __put_user((long)regs->regs[i], (__s64 __user *)&data->regs[i]);
77+ __put_user((long)regs->lo, (__s64 __user *)&data->lo);
78+ __put_user((long)regs->hi, (__s64 __user *)&data->hi);
79+ __put_user((long)regs->cp0_epc, (__s64 __user *)&data->cp0_epc);
80+ __put_user((long)regs->cp0_badvaddr, (__s64 __user *)&data->cp0_badvaddr);
81+ __put_user((long)regs->cp0_status, (__s64 __user *)&data->cp0_status);
82+ __put_user((long)regs->cp0_cause, (__s64 __user *)&data->cp0_cause);
8483
8584 return 0;
8685 }
@@ -90,7 +89,7 @@ int ptrace_getregs(struct task_struct *child, __s64 __user *data) · 3 unmodified lines
9089 * the 64-bit format. On a 32-bit kernel only the lower order half
9190 * (according to endianness) will be used.
9291 */
93−int ptrace_setregs(struct task_struct *child, __s64 __user *data)
92+int ptrace_setregs(struct task_struct *child, struct user_pt_regs __user *data)
9493 {
9594 struct pt_regs *regs;
9695 int i;
@@ -101,10 +100,10 @@ int ptrace_setregs(struct task_struct *child, __s64 __user *data) · 4 unmodified lines
101100 regs = task_pt_regs(child);
102101
103102 for (i = 0; i < 32; i++)
104− __get_user(regs->regs[i], data + i);
105− __get_user(regs->lo, data + EF_LO - EF_R0);
106− __get_user(regs->hi, data + EF_HI - EF_R0);
107− __get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
103+ __get_user(regs->regs[i], (__s64 __user *)&data->regs[i]);
104+ __get_user(regs->lo, (__s64 __user *)&data->lo);
105+ __get_user(regs->hi, (__s64 __user *)&data->hi);
106+ __get_user(regs->cp0_epc, (__s64 __user *)&data->cp0_epc);
108107
109108 /* badvaddr, status, and cause may not be written. */
110109
@@ -129,7 +128,7 @@ int ptrace_getfpregs(struct task_struct *child, __u32 __user *data) · 18 unmodified lines
129128 }
130129
131130 __put_user(child->thread.fpu.fcr31, data + 64);
132− __put_user(current_cpu_data.fpu_id, data + 65);
131+ __put_user(boot_cpu_data.fpu_id, data + 65);
133132
134133 return 0;
135134 }
@@ -151,6 +150,7 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data) · 15 unmodified lines
151150 }
152151
153152 __get_user(child->thread.fpu.fcr31, data + 64);
153+ child->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
154154
155155 /* FIR may not be written. */
156156
@@ -246,36 +246,160 @@ int ptrace_set_watch_regs(struct task_struct *child, · 89 unmodified lines
246246
247247 /* regset get/set implementations */
248248
249−static int gpr_get(struct task_struct *target,
250− const struct user_regset *regset,
251− unsigned int pos, unsigned int count,
252− void *kbuf, void __user *ubuf)
249+#if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
250+
251+static int gpr32_get(struct task_struct *target,
252+ const struct user_regset *regset,
253+ unsigned int pos, unsigned int count,
254+ void *kbuf, void __user *ubuf)
253255 {
254256 struct pt_regs *regs = task_pt_regs(target);
257+ u32 uregs[ELF_NGREG] = {};
258+ unsigned i;
259+
260+ for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) {
261+ /* k0/k1 are copied as zero. */
262+ if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27)
263+ continue;
264+
265+ uregs[i] = regs->regs[i - MIPS32_EF_R0];
266+ }
255267
256− return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
257− regs, 0, sizeof(*regs));
268+ uregs[MIPS32_EF_LO] = regs->lo;
269+ uregs[MIPS32_EF_HI] = regs->hi;
270+ uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc;
271+ uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
272+ uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status;
273+ uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause;
274+
275+ return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0,
276+ sizeof(uregs));
258277 }
259278
260−static int gpr_set(struct task_struct *target,
261− const struct user_regset *regset,
262− unsigned int pos, unsigned int count,
263− const void *kbuf, const void __user *ubuf)
279+static int gpr32_set(struct task_struct *target,
280+ const struct user_regset *regset,
281+ unsigned int pos, unsigned int count,
282+ const void *kbuf, const void __user *ubuf)
264283 {
265− struct pt_regs newregs;
266− int ret;
284+ struct pt_regs *regs = task_pt_regs(target);
285+ u32 uregs[ELF_NGREG];
286+ unsigned start, num_regs, i;
287+ int err;
288+
289+ start = pos / sizeof(u32);
290+ num_regs = count / sizeof(u32);
291+
292+ if (start + num_regs > ELF_NGREG)
293+ return -EIO;
294+
295+ err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
296+ sizeof(uregs));
297+ if (err)
298+ return err;
299+
300+ for (i = start; i < num_regs; i++) {
301+ /*
302+ * Cast all values to signed here so that if this is a 64-bit
303+ * kernel, the supplied 32-bit values will be sign extended.
304+ */
305+ switch (i) {
306+ case MIPS32_EF_R1 ... MIPS32_EF_R25:
307+ /* k0/k1 are ignored. */
308+ case MIPS32_EF_R28 ... MIPS32_EF_R31:
309+ regs->regs[i - MIPS32_EF_R0] = (s32)uregs[i];
310+ break;
311+ case MIPS32_EF_LO:
312+ regs->lo = (s32)uregs[i];
313+ break;
314+ case MIPS32_EF_HI:
315+ regs->hi = (s32)uregs[i];
316+ break;
317+ case MIPS32_EF_CP0_EPC:
318+ regs->cp0_epc = (s32)uregs[i];
319+ break;
320+ }
321+ }
322+
323+ return 0;
324+}
325+
326+#endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
327+
328+#ifdef CONFIG_64BIT
329+
330+static int gpr64_get(struct task_struct *target,
331+ const struct user_regset *regset,
332+ unsigned int pos, unsigned int count,
333+ void *kbuf, void __user *ubuf)
334+{
335+ struct pt_regs *regs = task_pt_regs(target);
336+ u64 uregs[ELF_NGREG] = {};
337+ unsigned i;
338+
339+ for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) {
340+ /* k0/k1 are copied as zero. */
341+ if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27)
342+ continue;
343+
344+ uregs[i] = regs->regs[i - MIPS64_EF_R0];
345+ }
346+
347+ uregs[MIPS64_EF_LO] = regs->lo;
348+ uregs[MIPS64_EF_HI] = regs->hi;
349+ uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc;
350+ uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
351+ uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status;
352+ uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause;
353+
354+ return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0,
355+ sizeof(uregs));
356+}
267357
268− ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
269− &newregs,
270− 0, sizeof(newregs));
271− if (ret)
272− return ret;
358+static int gpr64_set(struct task_struct *target,
359+ const struct user_regset *regset,
360+ unsigned int pos, unsigned int count,
361+ const void *kbuf, const void __user *ubuf)
362+{
363+ struct pt_regs *regs = task_pt_regs(target);
364+ u64 uregs[ELF_NGREG];
365+ unsigned start, num_regs, i;
366+ int err;
367+
368+ start = pos / sizeof(u64);
369+ num_regs = count / sizeof(u64);
273370
274− *task_pt_regs(target) = newregs;
371+ if (start + num_regs > ELF_NGREG)
372+ return -EIO;
373+
374+ err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
375+ sizeof(uregs));
376+ if (err)
377+ return err;
378+
379+ for (i = start; i < num_regs; i++) {
380+ switch (i) {
381+ case MIPS64_EF_R1 ... MIPS64_EF_R25:
382+ /* k0/k1 are ignored. */
383+ case MIPS64_EF_R28 ... MIPS64_EF_R31:
384+ regs->regs[i - MIPS64_EF_R0] = uregs[i];
385+ break;
386+ case MIPS64_EF_LO:
387+ regs->lo = uregs[i];
388+ break;
389+ case MIPS64_EF_HI:
390+ regs->hi = uregs[i];
391+ break;
392+ case MIPS64_EF_CP0_EPC:
393+ regs->cp0_epc = uregs[i];
394+ break;
395+ }
396+ }
275397
276398 return 0;
277399 }
278400
401+#endif /* CONFIG_64BIT */
402+
279403 static int fpr_get(struct task_struct *target,
280404 const struct user_regset *regset,
281405 unsigned int pos, unsigned int count,
@@ -337,14 +461,16 @@ enum mips_regset { · 55 unmodified lines
337461 REGSET_FPR,
338462 };
339463
464+#if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
465+
340466 static const struct user_regset mips_regsets[] = {
341467 [REGSET_GPR] = {
342468 .core_note_type = NT_PRSTATUS,
343469 .n = ELF_NGREG,
344470 .size = sizeof(unsigned int),
345471 .align = sizeof(unsigned int),
346− .get = gpr_get,
347− .set = gpr_set,
472+ .get = gpr32_get,
473+ .set = gpr32_set,
348474 },
349475 [REGSET_FPR] = {
350476 .core_note_type = NT_PRFPREG,
@@ -364,14 +490,18 @@ static const struct user_regset_view user_mips_view = { · 13 unmodified lines
364490 .n = ARRAY_SIZE(mips_regsets),
365491 };
366492
493+#endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
494+
495+#ifdef CONFIG_64BIT
496+
367497 static const struct user_regset mips64_regsets[] = {
368498 [REGSET_GPR] = {
369499 .core_note_type = NT_PRSTATUS,
370500 .n = ELF_NGREG,
371501 .size = sizeof(unsigned long),
372502 .align = sizeof(unsigned long),
373− .get = gpr_get,
374− .set = gpr_set,
503+ .get = gpr64_get,
504+ .set = gpr64_set,
375505 },
376506 [REGSET_FPR] = {
377507 .core_note_type = NT_PRFPREG,
@@ -384,25 +514,26 @@ static const struct user_regset mips64_regsets[] = { · 6 unmodified lines
384514 };
385515
386516 static const struct user_regset_view user_mips64_view = {
387− .name = "mips",
517+ .name = "mips64",
388518 .e_machine = ELF_ARCH,
389519 .ei_osabi = ELF_OSABI,
390520 .regsets = mips64_regsets,
391− .n = ARRAY_SIZE(mips_regsets),
521+ .n = ARRAY_SIZE(mips64_regsets),
392522 };
393523
524+#endif /* CONFIG_64BIT */
525+
394526 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
395527 {
396528 #ifdef CONFIG_32BIT
397529 return &user_mips_view;
398−#endif
399−
530+#else
400531 #ifdef CONFIG_MIPS32_O32
401− if (test_thread_flag(TIF_32BIT_REGS))
402− return &user_mips_view;
532+ if (test_tsk_thread_flag(task, TIF_32BIT_REGS))
533+ return &user_mips_view;
403534 #endif
404−
405535 return &user_mips64_view;
536+#endif
406537 }
407538
408539 long arch_ptrace(struct task_struct *child, long request,
@@ -480,7 +611,7 @@ long arch_ptrace(struct task_struct *child, long request, · 71 unmodified lines
480611 break;
481612 case FPC_EIR:
482613 /* implementation / version register */
483− tmp = current_cpu_data.fpu_id;
614+ tmp = boot_cpu_data.fpu_id;
484615 break;
485616 case DSP_BASE ... DSP_BASE + 5: {
486617 dspreg_t *dregs;
@@ -565,7 +696,7 @@ long arch_ptrace(struct task_struct *child, long request, · 78 unmodified lines
565696 break;
566697 #endif
567698 case FPC_CSR:
568− child->thread.fpu.fcr31 = data;
699+ child->thread.fpu.fcr31 = data & ~FPU_CSR_ALL_X;
569700 break;
570701 case DSP_BASE ... DSP_BASE + 5: {
571702 dspreg_t *dregs;
arch/mips/kernel/ptrace32.c+6−4
@@ -22,7 +22,6 @@ · 21 unmodified lines
2222 #include <linux/errno.h>
2323 #include <linux/ptrace.h>
2424 #include <linux/smp.h>
25−#include <linux/user.h>
2625 #include <linux/security.h>
2726
2827 #include <asm/cpu.h>
@@ -32,6 +31,7 @@ · 3 unmodified lines
3231 #include <asm/mipsmtregs.h>
3332 #include <asm/pgtable.h>
3433 #include <asm/page.h>
34+#include <asm/reg.h>
3535 #include <asm/uaccess.h>
3636 #include <asm/bootinfo.h>
3737
@@ -129,7 +129,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, · 91 unmodified lines
129129 break;
130130 case FPC_EIR:
131131 /* implementation / version register */
132− tmp = current_cpu_data.fpu_id;
132+ tmp = boot_cpu_data.fpu_id;
133133 break;
134134 case DSP_BASE ... DSP_BASE + 5: {
135135 dspreg_t *dregs;
@@ -256,11 +256,13 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, · 120 unmodified lines
256256 }
257257
258258 case PTRACE_GETREGS:
259− ret = ptrace_getregs(child, (__s64 __user *) (__u64) data);
259+ ret = ptrace_getregs(child,
260+ (struct user_pt_regs __user *) (__u64) data);
260261 break;
261262
262263 case PTRACE_SETREGS:
263− ret = ptrace_setregs(child, (__s64 __user *) (__u64) data);
264+ ret = ptrace_setregs(child,
265+ (struct user_pt_regs __user *) (__u64) data);
264266 break;
265267
266268 case PTRACE_GETFPREGS:
arch/mips/kernel/r4k_switch.S+8−1
@@ -64,8 +64,10 @@ · 63 unmodified lines
6464 /* Check whether we're saving scalar or vector context. */
6565 bgtz a3, 1f
6666
67− /* Save 128b MSA vector context. */
67+ /* Save 128b MSA vector context + scalar FP control & status. */
68+ cfc1 t1, fcr31
6869 msa_save_all a0
70+ sw t1, THREAD_FCR31(a0)
6971 b 2f
7072
7173 1: /* Save 32b/64b scalar FP context. */
@@ -142,6 +144,11 @@ LEAF(_restore_msa) · 70 unmodified lines
142144 jr ra
143145 END(_restore_msa)
144146
147+LEAF(_init_msa_upper)
148+ msa_init_all_upper
149+ jr ra
150+ END(_init_msa_upper)
151+
145152 #endif
146153
147154 /*
arch/mips/kernel/rtlx-cmp.c+3−0
@@ -77,6 +77,9 @@ int __init rtlx_module_init(void) · 76 unmodified lines
7777 dev = device_create(mt_class, NULL, MKDEV(major, i), NULL,
7878 "%s%d", RTLX_MODULE_NAME, i);
7979 if (IS_ERR(dev)) {
80+ while (i--)
81+ device_destroy(mt_class, MKDEV(major, i));
82+
8083 err = PTR_ERR(dev);
8184 goto out_chrdev;
8285 }
arch/mips/kernel/rtlx-mt.c+3−0
@@ -103,6 +103,9 @@ int __init rtlx_module_init(void) · 102 unmodified lines
103103 dev = device_create(mt_class, NULL, MKDEV(major, i), NULL,
104104 "%s%d", RTLX_MODULE_NAME, i);
105105 if (IS_ERR(dev)) {
106+ while (i--)
107+ device_destroy(mt_class, MKDEV(major, i));
108+
106109 err = PTR_ERR(dev);
107110 goto out_chrdev;
108111 }
arch/mips/kernel/scall32-o32.S+2−4
@@ -67,8 +67,6 @@ NESTED(handle_sys, PT_SIZE, sp) · 66 unmodified lines
6767
6868 /*
6969 * Ok, copy the args from the luser stack to the kernel stack.
70− * t3 is the precomputed number of instruction bytes needed to
71− * load or store arguments 6-8.
7270 */
7371
7472 .set push
@@ -495,8 +493,8 @@ EXPORT(sys_call_table) · 420 unmodified lines
495493 PTR sys_tgkill
496494 PTR sys_utimes
497495 PTR sys_mbind
498− PTR sys_ni_syscall /* sys_get_mempolicy */
499− PTR sys_ni_syscall /* 4270 sys_set_mempolicy */
496+ PTR sys_get_mempolicy
497+ PTR sys_set_mempolicy /* 4270 */
500498 PTR sys_mq_open
501499 PTR sys_mq_unlink
502500 PTR sys_mq_timedsend
arch/mips/kernel/scall64-64.S+2−2
@@ -347,8 +347,8 @@ EXPORT(sys_call_table) · 346 unmodified lines
347347 PTR sys_tgkill /* 5225 */
348348 PTR sys_utimes
349349 PTR sys_mbind
350− PTR sys_ni_syscall /* sys_get_mempolicy */
351− PTR sys_ni_syscall /* sys_set_mempolicy */
350+ PTR sys_get_mempolicy
351+ PTR sys_set_mempolicy
352352 PTR sys_mq_open /* 5230 */
353353 PTR sys_mq_unlink
354354 PTR sys_mq_timedsend
arch/mips/kernel/scall64-n32.S+6−6
@@ -162,7 +162,7 @@ EXPORT(sysn32_call_table) · 161 unmodified lines
162162 PTR sys_getpeername
163163 PTR sys_socketpair
164164 PTR compat_sys_setsockopt
165− PTR sys_getsockopt
165+ PTR compat_sys_getsockopt
166166 PTR __sys_clone /* 6055 */
167167 PTR __sys_fork
168168 PTR compat_sys_execve
@@ -339,9 +339,9 @@ EXPORT(sysn32_call_table) · 170 unmodified lines
339339 PTR compat_sys_clock_nanosleep
340340 PTR sys_tgkill
341341 PTR compat_sys_utimes /* 6230 */
342− PTR sys_ni_syscall /* sys_mbind */
343− PTR sys_ni_syscall /* sys_get_mempolicy */
344− PTR sys_ni_syscall /* sys_set_mempolicy */
342+ PTR compat_sys_mbind
343+ PTR compat_sys_get_mempolicy
344+ PTR compat_sys_set_mempolicy
345345 PTR compat_sys_mq_open
346346 PTR sys_mq_unlink /* 6235 */
347347 PTR compat_sys_mq_timedsend
@@ -358,7 +358,7 @@ EXPORT(sysn32_call_table) · 10 unmodified lines
358358 PTR sys_inotify_init
359359 PTR sys_inotify_add_watch
360360 PTR sys_inotify_rm_watch
361− PTR sys_migrate_pages /* 6250 */
361+ PTR compat_sys_migrate_pages /* 6250 */
362362 PTR sys_openat
363363 PTR sys_mkdirat
364364 PTR sys_mknodat
@@ -379,7 +379,7 @@ EXPORT(sysn32_call_table) · 14 unmodified lines
379379 PTR sys_sync_file_range
380380 PTR sys_tee
381381 PTR compat_sys_vmsplice /* 6270 */
382− PTR sys_move_pages
382+ PTR compat_sys_move_pages
383383 PTR compat_sys_set_robust_list
384384 PTR compat_sys_get_robust_list
385385 PTR compat_sys_kexec_load
arch/mips/kernel/scall64-o32.S+4−4
@@ -473,9 +473,9 @@ EXPORT(sys32_call_table) · 472 unmodified lines
473473 PTR compat_sys_clock_nanosleep /* 4265 */
474474 PTR sys_tgkill
475475 PTR compat_sys_utimes
476− PTR sys_ni_syscall /* sys_mbind */
477− PTR sys_ni_syscall /* sys_get_mempolicy */
478− PTR sys_ni_syscall /* 4270 sys_set_mempolicy */
476+ PTR compat_sys_mbind
477+ PTR compat_sys_get_mempolicy
478+ PTR compat_sys_set_mempolicy /* 4270 */
479479 PTR compat_sys_mq_open
480480 PTR sys_mq_unlink
481481 PTR compat_sys_mq_timedsend
@@ -492,7 +492,7 @@ EXPORT(sys32_call_table) · 10 unmodified lines
492492 PTR sys_inotify_init
493493 PTR sys_inotify_add_watch /* 4285 */
494494 PTR sys_inotify_rm_watch
495− PTR sys_migrate_pages
495+ PTR compat_sys_migrate_pages
496496 PTR compat_sys_openat
497497 PTR sys_mkdirat
498498 PTR sys_mknodat /* 4290 */
arch/mips/kernel/setup.c+21−1
@@ -282,7 +282,7 @@ static unsigned long __init init_initrd(void) · 281 unmodified lines
282282 * Initialize the bootmem allocator. It also setup initrd related data
283283 * if needed.
284284 */
285−#ifdef CONFIG_SGI_IP27
285+#if defined(CONFIG_SGI_IP27) || (defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_NUMA))
286286
287287 static void __init bootmem_init(void)
288288 {
@@ -729,6 +729,25 @@ static void __init resource_init(void) · 440 unmodified lines
729729 }
730730 }
731731
732+#ifdef CONFIG_SMP
733+static void __init prefill_possible_map(void)
734+{
735+ int i, possible = num_possible_cpus();
736+
737+ if (possible > nr_cpu_ids)
738+ possible = nr_cpu_ids;
739+
740+ for (i = 0; i < possible; i++)
741+ set_cpu_possible(i, true);
742+ for (; i < NR_CPUS; i++)
743+ set_cpu_possible(i, false);
744+
745+ nr_cpu_ids = possible;
746+}
747+#else
748+static inline void prefill_possible_map(void) {}
749+#endif
750+
732751 void __init setup_arch(char **cmdline_p)
733752 {
734753 cpu_probe();
@@ -752,6 +771,7 @@ void __init setup_arch(char **cmdline_p) · 17 unmodified lines
752771
753772 resource_init();
754773 plat_smp_setup();
774+ prefill_possible_map();
755775
756776 cpu_cache_init();
757777 }
arch/mips/kernel/smp-cps.c+8−4
@@ -14,13 +14,14 @@ · 13 unmodified lines
1414 #include <linux/smp.h>
1515 #include <linux/types.h>
1616
17−#include <asm/cacheflush.h>
17+#include <asm/bcache.h>
1818 #include <asm/gic.h>
1919 #include <asm/mips-cm.h>
2020 #include <asm/mips-cpc.h>
2121 #include <asm/mips_mt.h>
2222 #include <asm/mipsregs.h>
2323 #include <asm/pm-cps.h>
24+#include <asm/r4kcache.h>
2425 #include <asm/smp-cps.h>
2526 #include <asm/time.h>
2627 #include <asm/uasm.h>
@@ -132,8 +133,11 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) · 105 unmodified lines
132133 entry_code = (u32 *)&mips_cps_core_entry;
133134 UASM_i_LA(&entry_code, 3, (long)mips_cm_base);
134135 uasm_i_addiu(&entry_code, 16, 0, cca);
135− dma_cache_wback_inv((unsigned long)&mips_cps_core_entry,
136− (void *)entry_code - (void *)&mips_cps_core_entry);
136+ blast_dcache_range((unsigned long)&mips_cps_core_entry,
137+ (unsigned long)entry_code);
138+ bc_wback_inv((unsigned long)&mips_cps_core_entry,
139+ (void *)entry_code - (void *)&mips_cps_core_entry);
140+ __sync();
137141
138142 /* Allocate core boot configuration structs */
139143 mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
@@ -360,7 +364,7 @@ void play_dead(void) · 220 unmodified lines
360364 static void wait_for_sibling_halt(void *ptr_cpu)
361365 {
362366 unsigned cpu = (unsigned)ptr_cpu;
363− unsigned vpe_id = cpu_data[cpu].vpe_id;
367+ unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
364368 unsigned halted;
365369 unsigned long flags;
366370
arch/mips/kernel/smp-mt.c+2−0
@@ -288,6 +288,7 @@ struct plat_smp_ops vsmp_smp_ops = { · 287 unmodified lines
288288 .prepare_cpus = vsmp_prepare_cpus,
289289 };
290290
291+#ifdef CONFIG_PROC_FS
291292 static int proc_cpuinfo_chain_call(struct notifier_block *nfb,
292293 unsigned long action_unused, void *data)
293294 {
@@ -309,3 +310,4 @@ static int __init proc_cpuinfo_notifier_init(void) · 15 unmodified lines
309310 }
310311
311312 subsys_initcall(proc_cpuinfo_notifier_init);
313+#endif
arch/mips/kernel/smp.c+25−1
@@ -59,9 +59,16 @@ EXPORT_SYMBOL(smp_num_siblings); · 58 unmodified lines
5959 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
6060 EXPORT_SYMBOL(cpu_sibling_map);
6161
62+/* representing the core map of multi-core chips of each logical CPU */
63+cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
64+EXPORT_SYMBOL(cpu_core_map);
65+
6266 /* representing cpus for which sibling maps can be computed */
6367 static cpumask_t cpu_sibling_setup_map;
6468
69+/* representing cpus for which core maps can be computed */
70+static cpumask_t cpu_core_setup_map;
71+
6572 cpumask_t cpu_coherent_mask;
6673
6774 static inline void set_cpu_sibling_map(int cpu)
@@ -72,7 +79,8 @@ static inline void set_cpu_sibling_map(int cpu) · 4 unmodified lines
7279
7380 if (smp_num_siblings > 1) {
7481 for_each_cpu_mask(i, cpu_sibling_setup_map) {
75− if (cpu_data[cpu].core == cpu_data[i].core) {
82+ if (cpu_data[cpu].package == cpu_data[i].package &&
83+ cpu_data[cpu].core == cpu_data[i].core) {
7684 cpu_set(i, cpu_sibling_map[cpu]);
7785 cpu_set(cpu, cpu_sibling_map[i]);
7886 }
@@ -81,6 +89,20 @@ static inline void set_cpu_sibling_map(int cpu) · 2 unmodified lines
8189 cpu_set(cpu, cpu_sibling_map[cpu]);
8290 }
8391
92+static inline void set_cpu_core_map(int cpu)
93+{
94+ int i;
95+
96+ cpu_set(cpu, cpu_core_setup_map);
97+
98+ for_each_cpu_mask(i, cpu_core_setup_map) {
99+ if (cpu_data[cpu].package == cpu_data[i].package) {
100+ cpu_set(i, cpu_core_map[cpu]);
101+ cpu_set(cpu, cpu_core_map[i]);
102+ }
103+ }
104+}
105+
84106 struct plat_smp_ops *mp_ops;
85107 EXPORT_SYMBOL(mp_ops);
86108
@@ -122,6 +144,7 @@ asmlinkage void start_secondary(void) · 35 unmodified lines
122144 set_cpu_online(cpu, true);
123145
124146 set_cpu_sibling_map(cpu);
147+ set_cpu_core_map(cpu);
125148
126149 cpu_set(cpu, cpu_callin_map);
127150
@@ -175,6 +198,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) · 47 unmodified lines
175198 current_thread_info()->cpu = 0;
176199 mp_ops->prepare_cpus(max_cpus);
177200 set_cpu_sibling_map(0);
201+ set_cpu_core_map(0);
178202 #ifndef CONFIG_HOTPLUG_CPU
179203 init_cpu_present(cpu_possible_mask);
180204 #endif
arch/mips/kernel/traps.c+52−9
@@ -90,6 +90,7 @@ extern asmlinkage void handle_mt(void); · 89 unmodified lines
9090 extern asmlinkage void handle_dsp(void);
9191 extern asmlinkage void handle_mcheck(void);
9292 extern asmlinkage void handle_reserved(void);
93+extern void tlb_do_page_fault_0(void);
9394
9495 void (*board_be_init)(void);
9596 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
@@ -1088,13 +1089,19 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action, · 992 unmodified lines
10881089
10891090 static int enable_restore_fp_context(int msa)
10901091 {
1091− int err, was_fpu_owner;
1092+ int err, was_fpu_owner, prior_msa;
10921093
10931094 if (!used_math()) {
10941095 /* First time FP context user. */
1096+ preempt_disable();
10951097 err = init_fpu();
1096− if (msa && !err)
1098+ if (msa && !err) {
10971099 enable_msa();
1100+ _init_msa_upper();
1101+ set_thread_flag(TIF_USEDMSA);
1102+ set_thread_flag(TIF_MSA_CTX_LIVE);
1103+ }
1104+ preempt_enable();
10981105 if (!err)
10991106 set_used_math();
11001107 return err;
@@ -1134,10 +1141,11 @@ static int enable_restore_fp_context(int msa) · 33 unmodified lines
11341141 * This task is using or has previously used MSA. Thus we require
11351142 * that Status.FR == 1.
11361143 */
1144+ preempt_disable();
11371145 was_fpu_owner = is_fpu_owner();
1138− err = own_fpu(0);
1146+ err = own_fpu_inatomic(0);
11391147 if (err)
1140− return err;
1148+ goto out;
11411149
11421150 enable_msa();
11431151 write_msa_csr(current->thread.fpu.msacsr);
@@ -1146,13 +1154,42 @@ static int enable_restore_fp_context(int msa) · 2 unmodified lines
11461154 /*
11471155 * If this is the first time that the task is using MSA and it has
11481156 * previously used scalar FP in this time slice then we already nave
1149− * FP context which we shouldn't clobber.
1157+ * FP context which we shouldn't clobber. We do however need to clear
1158+ * the upper 64b of each vector register so that this task has no
1159+ * opportunity to see data left behind by another.
11501160 */
1151− if (!test_and_set_thread_flag(TIF_MSA_CTX_LIVE) && was_fpu_owner)
1152− return 0;
1161+ prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1162+ if (!prior_msa && was_fpu_owner) {
1163+ _init_msa_upper();
1164+
1165+ goto out;
1166+ }
1167+
1168+ if (!prior_msa) {
1169+ /*
1170+ * Restore the least significant 64b of each vector register
1171+ * from the existing scalar FP context.
1172+ */
1173+ _restore_fp(current);
1174+
1175+ /*
1176+ * The task has not formerly used MSA, so clear the upper 64b
1177+ * of each vector register such that it cannot see data left
1178+ * behind by another task.
1179+ */
1180+ _init_msa_upper();
1181+ } else {
1182+ /* We need to restore the vector context. */
1183+ restore_msa(current);
1184+
1185+ /* Restore the scalar FP control & status register */
1186+ if (!was_fpu_owner)
1187+ asm volatile("ctc1 %0, $31" : : "r"(current->thread.fpu.fcr31));
1188+ }
1189+
1190+out:
1191+ preempt_enable();
11531192
1154− /* We need to restore the vector context. */
1155− restore_msa(current);
11561193 return 0;
11571194 }
11581195
@@ -2114,6 +2151,12 @@ void __init trap_init(void) · 955 unmodified lines
21142151 set_except_vector(15, handle_fpe);
21152152
21162153 set_except_vector(16, handle_ftlb);
2154+
2155+ if (cpu_has_rixiex) {
2156+ set_except_vector(19, tlb_do_page_fault_0);
2157+ set_except_vector(20, tlb_do_page_fault_0);
2158+ }
2159+
21172160 set_except_vector(21, handle_msa);
21182161 set_except_vector(22, handle_mdmx);
21192162
arch/mips/kernel/unaligned.c+0−1
@@ -690,7 +690,6 @@ static void emulate_load_store_insn(struct pt_regs *regs, · 689 unmodified lines
690690 case sdc1_op:
691691 die_if_kernel("Unaligned FP access in kernel code", regs);
692692 BUG_ON(!used_math());
693− BUG_ON(!is_fpu_owner());
694693
695694 lose_fpu(1); /* Save FPU state for the emulator. */
696695 res = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
arch/mips/loongson/Kconfig+5−4
@@ -60,8 +60,8 @@ config LEMOTE_MACH2F · 59 unmodified lines
6060 These family machines include fuloong2f mini PC, yeeloong2f notebook,
6161 LingLoong allinone PC and so forth.
6262
63−config LEMOTE_MACH3A
64− bool "Lemote Loongson 3A family machines"
63+config LOONGSON_MACH3X
64+ bool "Generic Loongson 3 family machines"
6565 select ARCH_SPARSEMEM_ENABLE
6666 select GENERIC_ISA_DMA_SUPPORT_BROKEN
6767 select BOOT_ELF32
@@ -79,6 +79,7 @@ config LEMOTE_MACH3A · 11 unmodified lines
7979 select SYS_HAS_EARLY_PRINTK
8080 select SYS_SUPPORTS_SMP
8181 select SYS_SUPPORTS_HOTPLUG_CPU
82+ select SYS_SUPPORTS_NUMA
8283 select SYS_SUPPORTS_64BIT_KERNEL
8384 select SYS_SUPPORTS_HIGHMEM
8485 select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -86,8 +87,8 @@ config LEMOTE_MACH3A · 1 unmodified line
8687 select ZONE_DMA32
8788 select LEFI_FIRMWARE_INTERFACE
8889 help
89− Lemote Loongson 3A family machines utilize the 3A revision of
90− Loongson processor and RS780/SBX00 chipset.
90+ Generic Loongson 3 family machines utilize the 3A/3B revision
91+ of Loongson processor and RS780/SBX00 chipset.
9192 endchoice
9293
9394 config CS5536
arch/mips/loongson/Platform+1−1
@@ -30,4 +30,4 @@ platform-$(CONFIG_MACH_LOONGSON) += loongson/ · 29 unmodified lines
3030 cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson -mno-branch-likely
3131 load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
3232 load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
33−load-$(CONFIG_CPU_LOONGSON3) += 0xffffffff80200000
33+load-$(CONFIG_LOONGSON_MACH3X) += 0xffffffff80200000
arch/mips/loongson/common/env.c+48−1
@@ -27,6 +27,12 @@ EXPORT_SYMBOL(cpu_clock_freq); · 26 unmodified lines
2727 struct efi_memory_map_loongson *loongson_memmap;
2828 struct loongson_system_configuration loongson_sysconf;
2929
30+u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
31+u64 loongson_freqctrl[MAX_PACKAGES];
32+
33+unsigned long long smp_group[4];
34+int cpuhotplug_workaround = 0;
35+
3036 #define parse_even_earlier(res, option, p) \
3137 do { \
3238 unsigned int tmp __maybe_unused; \
@@ -77,9 +83,47 @@ void __init prom_init_env(void) · 44 unmodified lines
7783
7884 cpu_clock_freq = ecpu->cpu_clock_freq;
7985 loongson_sysconf.cputype = ecpu->cputype;
86+ if (ecpu->cputype == Loongson_3A) {
87+ loongson_sysconf.cores_per_node = 4;
88+ loongson_sysconf.cores_per_package = 4;
89+ smp_group[0] = 0x900000003ff01000;
90+ smp_group[1] = 0x900010003ff01000;
91+ smp_group[2] = 0x900020003ff01000;
92+ smp_group[3] = 0x900030003ff01000;
93+ loongson_chipcfg[0] = 0x900000001fe00180;
94+ loongson_chipcfg[1] = 0x900010001fe00180;
95+ loongson_chipcfg[2] = 0x900020001fe00180;
96+ loongson_chipcfg[3] = 0x900030001fe00180;
97+ loongson_sysconf.ht_control_base = 0x90000EFDFB000000;
98+ } else if (ecpu->cputype == Loongson_3B) {
99+ loongson_sysconf.cores_per_node = 4; /* One chip has 2 nodes */
100+ loongson_sysconf.cores_per_package = 8;
101+ smp_group[0] = 0x900000003ff01000;
102+ smp_group[1] = 0x900010003ff05000;
103+ smp_group[2] = 0x900020003ff09000;
104+ smp_group[3] = 0x900030003ff0d000;
105+ loongson_chipcfg[0] = 0x900000001fe00180;
106+ loongson_chipcfg[1] = 0x900020001fe00180;
107+ loongson_chipcfg[2] = 0x900040001fe00180;
108+ loongson_chipcfg[3] = 0x900060001fe00180;
109+ loongson_freqctrl[0] = 0x900000001fe001d0;
110+ loongson_freqctrl[1] = 0x900020001fe001d0;
111+ loongson_freqctrl[2] = 0x900040001fe001d0;
112+ loongson_freqctrl[3] = 0x900060001fe001d0;
113+ loongson_sysconf.ht_control_base = 0x90001EFDFB000000;
114+ cpuhotplug_workaround = 1;
115+ } else {
116+ loongson_sysconf.cores_per_node = 1;
117+ loongson_sysconf.cores_per_package = 1;
118+ loongson_chipcfg[0] = 0x900000001fe00180;
119+ }
120+
80121 loongson_sysconf.nr_cpus = ecpu->nr_cpus;
81122 if (ecpu->nr_cpus > NR_CPUS || ecpu->nr_cpus == 0)
82123 loongson_sysconf.nr_cpus = NR_CPUS;
124+ loongson_sysconf.nr_nodes = (loongson_sysconf.nr_cpus +
125+ loongson_sysconf.cores_per_node - 1) /
126+ loongson_sysconf.cores_per_node;
83127
84128 loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
85129 loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
@@ -93,7 +137,6 @@ void __init prom_init_env(void) · 7 unmodified lines
93137 loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;
94138 loongson_sysconf.suspend_addr = boot_p->reset_system.DoSuspend;
95139
96− loongson_sysconf.ht_control_base = 0x90000EFDFB000000;
97140 loongson_sysconf.vgabios_addr = boot_p->efi.smbios.vga_bios;
98141 pr_debug("Shutdown Addr: %llx, Restart Addr: %llx, VBIOS Addr: %llx\n",
99142 loongson_sysconf.poweroff_addr, loongson_sysconf.restart_addr,
@@ -111,6 +154,10 @@ void __init prom_init_env(void) · 11 unmodified lines
111154 case PRID_REV_LOONGSON3A:
112155 cpu_clock_freq = 900000000;
113156 break;
157+ case PRID_REV_LOONGSON3B_R1:
158+ case PRID_REV_LOONGSON3B_R2:
159+ cpu_clock_freq = 1000000000;
160+ break;
114161 default:
115162 cpu_clock_freq = 100000000;
116163 break;
arch/mips/loongson/common/init.c+4−0
@@ -30,7 +30,11 @@ void __init prom_init(void) · 29 unmodified lines
3030 set_io_port_base((unsigned long)
3131 ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
3232
33+#ifdef CONFIG_NUMA
34+ prom_init_numa_memory();
35+#else
3336 prom_init_memory();
37+#endif
3438
3539 /*init the uart base address */
3640 prom_init_uart_base();
arch/mips/loongson/common/pm.c+4−4
@@ -79,7 +79,7 @@ int __weak wakeup_loongson(void) · 78 unmodified lines
7979 static void wait_for_wakeup_events(void)
8080 {
8181 while (!wakeup_loongson())
82− LOONGSON_CHIPCFG0 &= ~0x7;
82+ LOONGSON_CHIPCFG(0) &= ~0x7;
8383 }
8484
8585 /*
@@ -102,15 +102,15 @@ static void loongson_suspend_enter(void) · 16 unmodified lines
102102
103103 stop_perf_counters();
104104
105− cached_cpu_freq = LOONGSON_CHIPCFG0;
105+ cached_cpu_freq = LOONGSON_CHIPCFG(0);
106106
107107 /* Put CPU into wait mode */
108− LOONGSON_CHIPCFG0 &= ~0x7;
108+ LOONGSON_CHIPCFG(0) &= ~0x7;
109109
110110 /* wait for the given events to wakeup cpu from wait mode */
111111 wait_for_wakeup_events();
112112
113− LOONGSON_CHIPCFG0 = cached_cpu_freq;
113+ LOONGSON_CHIPCFG(0) = cached_cpu_freq;
114114 mmiowb();
115115 }
116116
arch/mips/loongson/lemote-2f/clock.c+2−2
@@ -114,9 +114,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate) · 113 unmodified lines
114114
115115 clk->rate = rate;
116116
117− regval = LOONGSON_CHIPCFG0;
117+ regval = LOONGSON_CHIPCFG(0);
118118 regval = (regval & ~0x7) | (pos->driver_data - 1);
119− LOONGSON_CHIPCFG0 = regval;
119+ LOONGSON_CHIPCFG(0) = regval;
120120
121121 return ret;
122122 }
arch/mips/loongson/lemote-2f/reset.c+1−1
@@ -28,7 +28,7 @@ static void reset_cpu(void) · 27 unmodified lines
2828 * reset cpu to full speed, this is needed when enabling cpu frequency
2929 * scalling
3030 */
31− LOONGSON_CHIPCFG0 |= 0x7;
31+ LOONGSON_CHIPCFG(0) |= 0x7;
3232 }
3333
3434 /* reset support for fuloong2f */
arch/mips/loongson/loongson-3/Makefile+3−1
@@ -1,6 +1,8 @@
11 #
22 # Makefile for Loongson-3 family machines
33 #
4−obj-y += irq.o
4+obj-y += irq.o cop2-ex.o
55
66 obj-$(CONFIG_SMP) += smp.o
7+
8+obj-$(CONFIG_NUMA) += numa.o
arch/mips/loongson/loongson-3/cop2-ex.c+63−0
@@ -0,0 +1,63 @@
1+/*
2+ * This file is subject to the terms and conditions of the GNU General Public
3+ * License. See the file "COPYING" in the main directory of this archive
4+ * for more details.
5+ *
6+ * Copyright (C) 2014 Lemote Corporation.
7+ * written by Huacai Chen <chenhc@lemote.com>
8+ *
9+ * based on arch/mips/cavium-octeon/cpu.c
10+ * Copyright (C) 2009 Wind River Systems,
11+ * written by Ralf Baechle <ralf@linux-mips.org>
12+ */
13+#include <linux/init.h>
14+#include <linux/sched.h>
15+#include <linux/notifier.h>
16+
17+#include <asm/fpu.h>
18+#include <asm/cop2.h>
19+#include <asm/current.h>
20+#include <asm/mipsregs.h>
21+
22+static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action,
23+ void *data)
24+{
25+ int fpu_enabled;
26+ int fr = !test_thread_flag(TIF_32BIT_FPREGS);
27+
28+ switch (action) {
29+ case CU2_EXCEPTION:
30+ preempt_disable();
31+ fpu_enabled = read_c0_status() & ST0_CU1;
32+ if (!fr)
33+ set_c0_status(ST0_CU1 | ST0_CU2);
34+ else
35+ set_c0_status(ST0_CU1 | ST0_CU2 | ST0_FR);
36+ enable_fpu_hazard();
37+ KSTK_STATUS(current) |= (ST0_CU1 | ST0_CU2);
38+ if (fr)
39+ KSTK_STATUS(current) |= ST0_FR;
40+ else
41+ KSTK_STATUS(current) &= ~ST0_FR;
42+ /* If FPU is enabled, we needn't init or restore fp */
43+ if(!fpu_enabled) {
44+ set_thread_flag(TIF_USEDFPU);
45+ if (!used_math()) {
46+ _init_fpu();
47+ set_used_math();
48+ } else
49+ _restore_fp(current);
50+ }
51+ preempt_enable();
52+
53+ return NOTIFY_STOP; /* Don't call default notifier */
54+ }
55+
56+ return NOTIFY_OK; /* Let default notifier send signals */
57+}
58+
59+static int __init loongson_cu2_setup(void)
60+{
61+ return cu2_notifier(loongson_cu2_call, 0);
62+}
63+early_initcall(loongson_cu2_setup);
arch/mips/loongson/loongson-3/irq.c+20−6
@@ -7,6 +7,8 @@ · 6 unmodified lines
77 #include <asm/i8259.h>
88 #include <asm/mipsregs.h>
99
10+#include "smp.h"
11+
1012 unsigned int ht_irq[] = {1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
1113
1214 static void ht_irqdispatch(void)
@@ -53,9 +55,15 @@ static inline void mask_loongson_irq(struct irq_data *d) · 40 unmodified lines
5355 /* Workaround: UART IRQ may deliver to any core */
5456 if (d->irq == LOONGSON_UART_IRQ) {
5557 int cpu = smp_processor_id();
56−
57− LOONGSON_INT_ROUTER_INTENCLR = 1 << 10;
58− LOONGSON_INT_ROUTER_LPC = 0x10 + (1<<cpu);
58+ int node_id = cpu / loongson_sysconf.cores_per_node;
59+ int core_id = cpu % loongson_sysconf.cores_per_node;
60+ u64 intenclr_addr = smp_group[node_id] |
61+ (u64)(&LOONGSON_INT_ROUTER_INTENCLR);
62+ u64 introuter_lpc_addr = smp_group[node_id] |
63+ (u64)(&LOONGSON_INT_ROUTER_LPC);
64+
65+ *(volatile u32 *)intenclr_addr = 1 << 10;
66+ *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
5967 }
6068 }
6169
@@ -64,9 +72,15 @@ static inline void unmask_loongson_irq(struct irq_data *d) · 2 unmodified lines
6472 /* Workaround: UART IRQ may deliver to any core */
6573 if (d->irq == LOONGSON_UART_IRQ) {
6674 int cpu = smp_processor_id();
67−
68− LOONGSON_INT_ROUTER_INTENSET = 1 << 10;
69− LOONGSON_INT_ROUTER_LPC = 0x10 + (1<<cpu);
75+ int node_id = cpu / loongson_sysconf.cores_per_node;
76+ int core_id = cpu % loongson_sysconf.cores_per_node;
77+ u64 intenset_addr = smp_group[node_id] |
78+ (u64)(&LOONGSON_INT_ROUTER_INTENSET);
79+ u64 introuter_lpc_addr = smp_group[node_id] |
80+ (u64)(&LOONGSON_INT_ROUTER_LPC);
81+
82+ *(volatile u32 *)intenset_addr = 1 << 10;
83+ *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
7084 }
7185
7286 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
arch/mips/loongson/loongson-3/numa.c+291−0
@@ -0,0 +1,291 @@
1+/*
2+ * Copyright (C) 2010 Loongson Inc. & Lemote Inc. &
3+ * Insititute of Computing Technology
4+ * Author: Xiang Gao, gaoxiang@ict.ac.cn
5+ * Huacai Chen, chenhc@lemote.com
6+ * Xiaofu Meng, Shuangshuang Zhang
7+ *
8+ * This program is free software; you can redistribute it and/or modify it
9+ * under the terms of the GNU General Public License as published by the
10+ * Free Software Foundation; either version 2 of the License, or (at your
11+ * option) any later version.
12+ */
13+#include <linux/init.h>
14+#include <linux/kernel.h>
15+#include <linux/mm.h>
16+#include <linux/mmzone.h>
17+#include <linux/module.h>
18+#include <linux/nodemask.h>
19+#include <linux/swap.h>
20+#include <linux/memblock.h>
21+#include <linux/bootmem.h>
22+#include <linux/pfn.h>
23+#include <linux/highmem.h>
24+#include <asm/page.h>
25+#include <asm/pgalloc.h>
26+#include <asm/sections.h>
27+#include <linux/bootmem.h>
28+#include <linux/init.h>
29+#include <linux/irq.h>
30+#include <asm/bootinfo.h>
31+#include <asm/mc146818-time.h>
32+#include <asm/time.h>
33+#include <asm/wbflush.h>
34+#include <boot_param.h>
35+
36+static struct node_data prealloc__node_data[MAX_NUMNODES];
37+unsigned char __node_distances[MAX_NUMNODES][MAX_NUMNODES];
38+struct node_data *__node_data[MAX_NUMNODES];
39+EXPORT_SYMBOL(__node_data);
40+
41+static void enable_lpa(void)
42+{
43+ unsigned long value;
44+
45+ value = __read_32bit_c0_register($16, 3);
46+ value |= 0x00000080;
47+ __write_32bit_c0_register($16, 3, value);
48+ value = __read_32bit_c0_register($16, 3);
49+ pr_info("CP0_Config3: CP0 16.3 (0x%lx)\n", value);
50+
51+ value = __read_32bit_c0_register($5, 1);
52+ value |= 0x20000000;
53+ __write_32bit_c0_register($5, 1, value);
54+ value = __read_32bit_c0_register($5, 1);
55+ pr_info("CP0_PageGrain: CP0 5.1 (0x%lx)\n", value);
56+}
57+
58+static void cpu_node_probe(void)
59+{
60+ int i;
61+
62+ nodes_clear(node_possible_map);
63+ nodes_clear(node_online_map);
64+ for (i = 0; i < loongson_sysconf.nr_nodes; i++) {
65+ node_set_state(num_online_nodes(), N_POSSIBLE);
66+ node_set_online(num_online_nodes());
67+ }
68+
69+ pr_info("NUMA: Discovered %d cpus on %d nodes\n",
70+ loongson_sysconf.nr_cpus, num_online_nodes());
71+}
72+
73+static int __init compute_node_distance(int row, int col)
74+{
75+ int package_row = row * loongson_sysconf.cores_per_node /
76+ loongson_sysconf.cores_per_package;
77+ int package_col = col * loongson_sysconf.cores_per_node /
78+ loongson_sysconf.cores_per_package;
79+
80+ if (col == row)
81+ return 0;
82+ else if (package_row == package_col)
83+ return 40;
84+ else
85+ return 100;
86+}
87+
88+static void __init init_topology_matrix(void)
89+{
90+ int row, col;
91+
92+ for (row = 0; row < MAX_NUMNODES; row++)
93+ for (col = 0; col < MAX_NUMNODES; col++)
94+ __node_distances[row][col] = -1;
95+
96+ for_each_online_node(row) {
97+ for_each_online_node(col) {
98+ __node_distances[row][col] =
99+ compute_node_distance(row, col);
100+ }
101+ }
102+}
103+
104+static unsigned long nid_to_addroffset(unsigned int nid)
105+{
106+ unsigned long result;
107+ switch (nid) {
108+ case 0:
109+ default:
110+ result = NODE0_ADDRSPACE_OFFSET;
111+ break;
112+ case 1:
113+ result = NODE1_ADDRSPACE_OFFSET;
114+ break;
115+ case 2:
116+ result = NODE2_ADDRSPACE_OFFSET;
117+ break;
118+ case 3:
119+ result = NODE3_ADDRSPACE_OFFSET;
120+ break;
121+ }
122+ return result;
123+}
124+
125+static void __init szmem(unsigned int node)
126+{
127+ u32 i, mem_type;
128+ static unsigned long num_physpages = 0;
129+ u64 node_id, node_psize, start_pfn, end_pfn, mem_start, mem_size;
130+
131+ /* Parse memory information and activate */
132+ for (i = 0; i < loongson_memmap->nr_map; i++) {
133+ node_id = loongson_memmap->map[i].node_id;
134+ if (node_id != node)
135+ continue;
136+
137+ mem_type = loongson_memmap->map[i].mem_type;
138+ mem_size = loongson_memmap->map[i].mem_size;
139+ mem_start = loongson_memmap->map[i].mem_start;
140+
141+ switch (mem_type) {
142+ case SYSTEM_RAM_LOW:
143+ start_pfn = ((node_id << 44) + mem_start) >> PAGE_SHIFT;
144+ node_psize = (mem_size << 20) >> PAGE_SHIFT;
145+ end_pfn = start_pfn + node_psize;
146+ num_physpages += node_psize;
147+ pr_info("Node%d: mem_type:%d, mem_start:0x%llx, mem_size:0x%llx MB\n",
148+ (u32)node_id, mem_type, mem_start, mem_size);
149+ pr_info(" start_pfn:0x%llx, end_pfn:0x%llx, num_physpages:0x%lx\n",
150+ start_pfn, end_pfn, num_physpages);
151+ add_memory_region((node_id << 44) + mem_start,
152+ (u64)mem_size << 20, BOOT_MEM_RAM);
153+ memblock_add_node(PFN_PHYS(start_pfn),
154+ PFN_PHYS(end_pfn - start_pfn), node);
155+ break;
156+ case SYSTEM_RAM_HIGH:
157+ start_pfn = ((node_id << 44) + mem_start) >> PAGE_SHIFT;
158+ node_psize = (mem_size << 20) >> PAGE_SHIFT;
159+ end_pfn = start_pfn + node_psize;
160+ num_physpages += node_psize;
161+ pr_info("Node%d: mem_type:%d, mem_start:0x%llx, mem_size:0x%llx MB\n",
162+ (u32)node_id, mem_type, mem_start, mem_size);
163+ pr_info(" start_pfn:0x%llx, end_pfn:0x%llx, num_physpages:0x%lx\n",
164+ start_pfn, end_pfn, num_physpages);
165+ add_memory_region((node_id << 44) + mem_start,
166+ (u64)mem_size << 20, BOOT_MEM_RAM);
167+ memblock_add_node(PFN_PHYS(start_pfn),
168+ PFN_PHYS(end_pfn - start_pfn), node);
169+ break;
170+ case MEM_RESERVED:
171+ pr_info("Node%d: mem_type:%d, mem_start:0x%llx, mem_size:0x%llx MB\n",
172+ (u32)node_id, mem_type, mem_start, mem_size);
173+ add_memory_region((node_id << 44) + mem_start,
174+ (u64)mem_size << 20, BOOT_MEM_RESERVED);
175+ memblock_reserve(((node_id << 44) + mem_start),
176+ mem_size << 20);
177+ break;
178+ }
179+ }
180+}
181+
182+static void __init node_mem_init(unsigned int node)
183+{
184+ unsigned long bootmap_size;
185+ unsigned long node_addrspace_offset;
186+ unsigned long start_pfn, end_pfn, freepfn;
187+
188+ node_addrspace_offset = nid_to_addroffset(node);
189+ pr_info("Node%d's addrspace_offset is 0x%lx\n",
190+ node, node_addrspace_offset);
191+
192+ get_pfn_range_for_nid(node, &start_pfn, &end_pfn);
193+ freepfn = start_pfn;
194+ if (node == 0)
195+ freepfn = PFN_UP(__pa_symbol(&_end)); /* kernel end address */
196+ pr_info("Node%d: start_pfn=0x%lx, end_pfn=0x%lx, freepfn=0x%lx\n",
197+ node, start_pfn, end_pfn, freepfn);
198+
199+ __node_data[node] = prealloc__node_data + node;
200+
201+ NODE_DATA(node)->bdata = &bootmem_node_data[node];
202+ NODE_DATA(node)->node_start_pfn = start_pfn;
203+ NODE_DATA(node)->node_spanned_pages = end_pfn - start_pfn;
204+
205+ bootmap_size = init_bootmem_node(NODE_DATA(node), freepfn,
206+ start_pfn, end_pfn);
207+ free_bootmem_with_active_regions(node, end_pfn);
208+ if (node == 0) /* used by finalize_initrd() */
209+ max_low_pfn = end_pfn;
210+
211+ /* This is reserved for the kernel and bdata->node_bootmem_map */
212+ reserve_bootmem_node(NODE_DATA(node), start_pfn << PAGE_SHIFT,
213+ ((freepfn - start_pfn) << PAGE_SHIFT) + bootmap_size,
214+ BOOTMEM_DEFAULT);
215+
216+ if (node == 0 && node_end_pfn(0) >= (0xffffffff >> PAGE_SHIFT)) {
217+ /* Reserve 0xff800000~0xffffffff for RS780E integrated GPU */
218+ reserve_bootmem_node(NODE_DATA(node),
219+ (node_addrspace_offset | 0xff800000),
220+ 8 << 20, BOOTMEM_DEFAULT);
221+ }
222+
223+ sparse_memory_present_with_active_regions(node);
224+}
225+
226+static __init void prom_meminit(void)
227+{
228+ unsigned int node, cpu;
229+
230+ cpu_node_probe();
231+ init_topology_matrix();
232+
233+ for (node = 0; node < loongson_sysconf.nr_nodes; node++) {
234+ if (node_online(node)) {
235+ szmem(node);
236+ node_mem_init(node);
237+ cpus_clear(__node_data[(node)]->cpumask);
238+ }
239+ }
240+ for (cpu = 0; cpu < loongson_sysconf.nr_cpus; cpu++) {
241+ node = cpu / loongson_sysconf.cores_per_node;
242+ if (node >= num_online_nodes())
243+ node = 0;
244+ pr_info("NUMA: set cpumask cpu %d on node %d\n", cpu, node);
245+ cpu_set(cpu, __node_data[(node)]->cpumask);
246+ }
247+}
248+
249+void __init paging_init(void)
250+{
251+ unsigned node;
252+ unsigned long zones_size[MAX_NR_ZONES] = {0, };
253+
254+ pagetable_init();
255+
256+ for_each_online_node(node) {
257+ unsigned long start_pfn, end_pfn;
258+
259+ get_pfn_range_for_nid(node, &start_pfn, &end_pfn);
260+
261+ if (end_pfn > max_low_pfn)
262+ max_low_pfn = end_pfn;
263+ }
264+#ifdef CONFIG_ZONE_DMA32
265+ zones_size[ZONE_DMA32] = MAX_DMA32_PFN;
266+#endif
267+ zones_size[ZONE_NORMAL] = max_low_pfn;
268+ free_area_init_nodes(zones_size);
269+}
270+
271+void __init mem_init(void)
272+{
273+ high_memory = (void *) __va(get_num_physpages() << PAGE_SHIFT);
274+ free_all_bootmem();
275+ setup_zero_pages(); /* This comes from node 0 */
276+ mem_init_print_info(NULL);
277+}
278+
279+/* All PCI device belongs to logical Node-0 */
280+int pcibus_to_node(struct pci_bus *bus)
281+{
282+ return 0;
283+}
284+EXPORT_SYMBOL(pcibus_to_node);
285+
286+void __init prom_init_numa_memory(void)
287+{
288+ enable_lpa();
289+ prom_meminit();
290+}
291+EXPORT_SYMBOL(prom_init_numa_memory);
arch/mips/loongson/loongson-3/smp.c+292−95
@@ -31,6 +31,12 @@ · 30 unmodified lines
3131 DEFINE_PER_CPU(int, cpu_state);
3232 DEFINE_PER_CPU(uint32_t, core0_c0count);
3333
34+static void *ipi_set0_regs[16];
35+static void *ipi_clear0_regs[16];
36+static void *ipi_status0_regs[16];
37+static void *ipi_en0_regs[16];
38+static void *ipi_mailbox_buf[16];
39+
3440 /* read a 32bit value from ipi register */
3541 #define loongson3_ipi_read32(addr) readl(addr)
3642 /* read a 64bit value from ipi register */
@@ -48,100 +54,185 @@ DEFINE_PER_CPU(uint32_t, core0_c0count); · 11 unmodified lines
4854 __wbflush(); \
4955 } while (0)
5056
51−static void *ipi_set0_regs[] = {
52− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0),
53− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0),
54− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0),
55− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0),
56− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0),
57− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0),
58− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0),
59− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0),
60− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0),
61− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0),
62− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0),
63− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0),
64− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0),
65− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0),
66− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0),
67− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0),
68−};
57+static void ipi_set0_regs_init(void)
58+{
59+ ipi_set0_regs[0] = (void *)
60+ (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0);
61+ ipi_set0_regs[1] = (void *)
62+ (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0);
63+ ipi_set0_regs[2] = (void *)
64+ (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0);
65+ ipi_set0_regs[3] = (void *)
66+ (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0);
67+ ipi_set0_regs[4] = (void *)
68+ (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0);
69+ ipi_set0_regs[5] = (void *)
70+ (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0);
71+ ipi_set0_regs[6] = (void *)
72+ (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0);
73+ ipi_set0_regs[7] = (void *)
74+ (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0);
75+ ipi_set0_regs[8] = (void *)
76+ (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0);
77+ ipi_set0_regs[9] = (void *)
78+ (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0);
79+ ipi_set0_regs[10] = (void *)
80+ (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0);
81+ ipi_set0_regs[11] = (void *)
82+ (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0);
83+ ipi_set0_regs[12] = (void *)
84+ (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0);
85+ ipi_set0_regs[13] = (void *)
86+ (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0);
87+ ipi_set0_regs[14] = (void *)
88+ (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0);
89+ ipi_set0_regs[15] = (void *)
90+ (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0);
91+}
6992
70−static void *ipi_clear0_regs[] = {
71− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0),
72− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0),
73− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0),
74− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0),
75− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0),
76− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0),
77− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0),
78− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0),
79− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0),
80− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0),
81− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0),
82− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0),
83− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0),
84− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0),
85− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0),
86− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0),
87−};
93+static void ipi_clear0_regs_init(void)
94+{
95+ ipi_clear0_regs[0] = (void *)
96+ (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0);
97+ ipi_clear0_regs[1] = (void *)
98+ (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0);
99+ ipi_clear0_regs[2] = (void *)
100+ (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0);
101+ ipi_clear0_regs[3] = (void *)
102+ (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0);
103+ ipi_clear0_regs[4] = (void *)
104+ (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0);
105+ ipi_clear0_regs[5] = (void *)
106+ (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0);
107+ ipi_clear0_regs[6] = (void *)
108+ (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0);
109+ ipi_clear0_regs[7] = (void *)
110+ (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0);
111+ ipi_clear0_regs[8] = (void *)
112+ (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0);
113+ ipi_clear0_regs[9] = (void *)
114+ (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0);
115+ ipi_clear0_regs[10] = (void *)
116+ (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0);
117+ ipi_clear0_regs[11] = (void *)
118+ (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0);
119+ ipi_clear0_regs[12] = (void *)
120+ (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0);
121+ ipi_clear0_regs[13] = (void *)
122+ (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0);
123+ ipi_clear0_regs[14] = (void *)
124+ (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0);
125+ ipi_clear0_regs[15] = (void *)
126+ (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0);
127+}
88128
89−static void *ipi_status0_regs[] = {
90− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0),
91− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0),
92− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0),
93− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0),
94− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0),
95− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0),
96− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0),
97− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0),
98− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0),
99− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0),
100− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0),
101− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0),
102− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0),
103− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0),
104− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0),
105− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0),
106−};
129+static void ipi_status0_regs_init(void)
130+{
131+ ipi_status0_regs[0] = (void *)
132+ (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0);
133+ ipi_status0_regs[1] = (void *)
134+ (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0);
135+ ipi_status0_regs[2] = (void *)
136+ (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0);
137+ ipi_status0_regs[3] = (void *)
138+ (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0);
139+ ipi_status0_regs[4] = (void *)
140+ (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0);
141+ ipi_status0_regs[5] = (void *)
142+ (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0);
143+ ipi_status0_regs[6] = (void *)
144+ (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0);
145+ ipi_status0_regs[7] = (void *)
146+ (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0);
147+ ipi_status0_regs[8] = (void *)
148+ (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0);
149+ ipi_status0_regs[9] = (void *)
150+ (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0);
151+ ipi_status0_regs[10] = (void *)
152+ (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0);
153+ ipi_status0_regs[11] = (void *)
154+ (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0);
155+ ipi_status0_regs[12] = (void *)
156+ (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0);
157+ ipi_status0_regs[13] = (void *)
158+ (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0);
159+ ipi_status0_regs[14] = (void *)
160+ (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0);
161+ ipi_status0_regs[15] = (void *)
162+ (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0);
163+}
107164
108−static void *ipi_en0_regs[] = {
109− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0),
110− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0),
111− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0),
112− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0),
113− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0),
114− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0),
115− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0),
116− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0),
117− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0),
118− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0),
119− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0),
120− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0),
121− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0),
122− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0),
123− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0),
124− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0),
125−};
165+static void ipi_en0_regs_init(void)
166+{
167+ ipi_en0_regs[0] = (void *)
168+ (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0);
169+ ipi_en0_regs[1] = (void *)
170+ (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0);
171+ ipi_en0_regs[2] = (void *)
172+ (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0);
173+ ipi_en0_regs[3] = (void *)
174+ (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0);
175+ ipi_en0_regs[4] = (void *)
176+ (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0);
177+ ipi_en0_regs[5] = (void *)
178+ (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0);
179+ ipi_en0_regs[6] = (void *)
180+ (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0);
181+ ipi_en0_regs[7] = (void *)
182+ (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0);
183+ ipi_en0_regs[8] = (void *)
184+ (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0);
185+ ipi_en0_regs[9] = (void *)
186+ (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0);
187+ ipi_en0_regs[10] = (void *)
188+ (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0);
189+ ipi_en0_regs[11] = (void *)
190+ (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0);
191+ ipi_en0_regs[12] = (void *)
192+ (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0);
193+ ipi_en0_regs[13] = (void *)
194+ (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0);
195+ ipi_en0_regs[14] = (void *)
196+ (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0);
197+ ipi_en0_regs[15] = (void *)
198+ (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0);
199+}
126200
127−static void *ipi_mailbox_buf[] = {
128− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF),
129− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF),
130− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF),
131− (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF),
132− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF),
133− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF),
134− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF),
135− (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF),
136− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF),
137− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF),
138− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF),
139− (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF),
140− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF),
141− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF),
142− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF),
143− (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF),
144−};
201+static void ipi_mailbox_buf_init(void)
202+{
203+ ipi_mailbox_buf[0] = (void *)
204+ (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF);
205+ ipi_mailbox_buf[1] = (void *)
206+ (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF);
207+ ipi_mailbox_buf[2] = (void *)
208+ (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF);
209+ ipi_mailbox_buf[3] = (void *)
210+ (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF);
211+ ipi_mailbox_buf[4] = (void *)
212+ (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF);
213+ ipi_mailbox_buf[5] = (void *)
214+ (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF);
215+ ipi_mailbox_buf[6] = (void *)
216+ (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF);
217+ ipi_mailbox_buf[7] = (void *)
218+ (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF);
219+ ipi_mailbox_buf[8] = (void *)
220+ (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF);
221+ ipi_mailbox_buf[9] = (void *)
222+ (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF);
223+ ipi_mailbox_buf[10] = (void *)
224+ (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF);
225+ ipi_mailbox_buf[11] = (void *)
226+ (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF);
227+ ipi_mailbox_buf[12] = (void *)
228+ (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF);
229+ ipi_mailbox_buf[13] = (void *)
230+ (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF);
231+ ipi_mailbox_buf[14] = (void *)
232+ (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF);
233+ ipi_mailbox_buf[15] = (void *)
234+ (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF);
235+}
145236
146237 /*
147238 * Simple enough, just poke the appropriate ipi register
@@ -203,6 +294,8 @@ static void loongson3_init_secondary(void) · 55 unmodified lines
203294 for (i = 0; i < loongson_sysconf.nr_cpus; i++)
204295 loongson3_ipi_write32(0xffffffff, ipi_en0_regs[i]);
205296
297+ cpu_data[cpu].package = cpu / loongson_sysconf.cores_per_package;
298+ cpu_data[cpu].core = cpu % loongson_sysconf.cores_per_package;
206299 per_cpu(cpu_state, cpu) = CPU_ONLINE;
207300
208301 i = 0;
@@ -246,6 +339,11 @@ static void __init loongson3_smp_setup(void) · 37 unmodified lines
246339 __cpu_number_map[i] = ++num;
247340 __cpu_logical_map[num] = i;
248341 }
342+ ipi_set0_regs_init();
343+ ipi_clear0_regs_init();
344+ ipi_status0_regs_init();
345+ ipi_en0_regs_init();
346+ ipi_mailbox_buf_init();
249347 pr_info("Detected %i available secondary CPU(s)\n", num);
250348 }
251349
@@ -313,7 +411,7 @@ static void loongson3_cpu_die(unsigned int cpu) · 61 unmodified lines
313411 * flush all L1 entries at first. Then, another core (usually Core 0) can
314412 * safely disable the clock of the target core. loongson3_play_dead() is
315413 * called via CKSEG1 (uncached and unmmaped) */
316−static void loongson3_play_dead(int *state_addr)
414+static void loongson3a_play_dead(int *state_addr)
317415 {
318416 register int val;
319417 register long cpuid, core, node, count;
@@ -375,6 +473,70 @@ static void loongson3_play_dead(int *state_addr) · 55 unmodified lines
375473 : "a1");
376474 }
377475
476+static void loongson3b_play_dead(int *state_addr)
477+{
478+ register int val;
479+ register long cpuid, core, node, count;
480+ register void *addr, *base, *initfunc;
481+
482+ __asm__ __volatile__(
483+ " .set push \n"
484+ " .set noreorder \n"
485+ " li %[addr], 0x80000000 \n" /* KSEG0 */
486+ "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
487+ " cache 0, 1(%[addr]) \n"
488+ " cache 0, 2(%[addr]) \n"
489+ " cache 0, 3(%[addr]) \n"
490+ " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
491+ " cache 1, 1(%[addr]) \n"
492+ " cache 1, 2(%[addr]) \n"
493+ " cache 1, 3(%[addr]) \n"
494+ " addiu %[sets], %[sets], -1 \n"
495+ " bnez %[sets], 1b \n"
496+ " addiu %[addr], %[addr], 0x20 \n"
497+ " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
498+ " sw %[val], (%[state_addr]) \n"
499+ " sync \n"
500+ " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
501+ " .set pop \n"
502+ : [addr] "=&r" (addr), [val] "=&r" (val)
503+ : [state_addr] "r" (state_addr),
504+ [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
505+
506+ __asm__ __volatile__(
507+ " .set push \n"
508+ " .set noreorder \n"
509+ " .set mips64 \n"
510+ " mfc0 %[cpuid], $15, 1 \n"
511+ " andi %[cpuid], 0x3ff \n"
512+ " dli %[base], 0x900000003ff01000 \n"
513+ " andi %[core], %[cpuid], 0x3 \n"
514+ " sll %[core], 8 \n" /* get core id */
515+ " or %[base], %[base], %[core] \n"
516+ " andi %[node], %[cpuid], 0xc \n"
517+ " dsll %[node], 42 \n" /* get node id */
518+ " or %[base], %[base], %[node] \n"
519+ " dsrl %[node], 30 \n" /* 15:14 */
520+ " or %[base], %[base], %[node] \n"
521+ "1: li %[count], 0x100 \n" /* wait for init loop */
522+ "2: bnez %[count], 2b \n" /* limit mailbox access */
523+ " addiu %[count], -1 \n"
524+ " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
525+ " beqz %[initfunc], 1b \n"
526+ " nop \n"
527+ " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
528+ " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
529+ " ld $a1, 0x38(%[base]) \n"
530+ " jr %[initfunc] \n" /* jump to initial PC */
531+ " nop \n"
532+ " .set pop \n"
533+ : [core] "=&r" (core), [node] "=&r" (node),
534+ [base] "=&r" (base), [cpuid] "=&r" (cpuid),
535+ [count] "=&r" (count), [initfunc] "=&r" (initfunc)
536+ : /* No Input */
537+ : "a1");
538+}
539+
378540 void play_dead(void)
379541 {
380542 int *state_addr;
@@ -382,13 +544,48 @@ void play_dead(void) · 1 unmodified line
382544 void (*play_dead_at_ckseg1)(int *);
383545
384546 idle_task_exit();
385− play_dead_at_ckseg1 =
386− (void *)CKSEG1ADDR((unsigned long)loongson3_play_dead);
547+ switch (loongson_sysconf.cputype) {
548+ case Loongson_3A:
549+ default:
550+ play_dead_at_ckseg1 =
551+ (void *)CKSEG1ADDR((unsigned long)loongson3a_play_dead);
552+ break;
553+ case Loongson_3B:
554+ play_dead_at_ckseg1 =
555+ (void *)CKSEG1ADDR((unsigned long)loongson3b_play_dead);
556+ break;
557+ }
387558 state_addr = &per_cpu(cpu_state, cpu);
388559 mb();
389560 play_dead_at_ckseg1(state_addr);
390561 }
391562
563+void loongson3_disable_clock(int cpu)
564+{
565+ uint64_t core_id = cpu_data[cpu].core;
566+ uint64_t package_id = cpu_data[cpu].package;
567+
568+ if (loongson_sysconf.cputype == Loongson_3A) {
569+ LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id));
570+ } else if (loongson_sysconf.cputype == Loongson_3B) {
571+ if (!cpuhotplug_workaround)
572+ LOONGSON_FREQCTRL(package_id) &= ~(1 << (core_id * 4 + 3));
573+ }
574+}
575+
576+void loongson3_enable_clock(int cpu)
577+{
578+ uint64_t core_id = cpu_data[cpu].core;
579+ uint64_t package_id = cpu_data[cpu].package;
580+
581+ if (loongson_sysconf.cputype == Loongson_3A) {
582+ LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id);
583+ } else if (loongson_sysconf.cputype == Loongson_3B) {
584+ if (!cpuhotplug_workaround)
585+ LOONGSON_FREQCTRL(package_id) |= 1 << (core_id * 4 + 3);
586+ }
587+}
588+
392589 #define CPU_POST_DEAD_FROZEN (CPU_POST_DEAD | CPU_TASKS_FROZEN)
393590 static int loongson3_cpu_callback(struct notifier_block *nfb,
394591 unsigned long action, void *hcpu)
@@ -399,12 +596,12 @@ static int loongson3_cpu_callback(struct notifier_block *nfb, · 4 unmodified lines
399596 case CPU_POST_DEAD:
400597 case CPU_POST_DEAD_FROZEN:
401598 pr_info("Disable clock for CPU#%d\n", cpu);
402− LOONGSON_CHIPCFG0 &= ~(1 << (12 + cpu));
599+ loongson3_disable_clock(cpu);
403600 break;
404601 case CPU_UP_PREPARE:
405602 case CPU_UP_PREPARE_FROZEN:
406603 pr_info("Enable clock for CPU#%d\n", cpu);
407− LOONGSON_CHIPCFG0 |= 1 << (12 + cpu);
604+ loongson3_enable_clock(cpu);
408605 break;
409606 }
410607
arch/mips/loongson/loongson-3/smp.h+19−18
@@ -1,29 +1,30 @@
11 #ifndef __LOONGSON_SMP_H_
22 #define __LOONGSON_SMP_H_
33
4−/* for Loongson-3A smp support */
4+/* for Loongson-3 smp support */
5+extern unsigned long long smp_group[4];
56
67 /* 4 groups(nodes) in maximum in numa case */
7−#define SMP_CORE_GROUP0_BASE 0x900000003ff01000
8−#define SMP_CORE_GROUP1_BASE 0x900010003ff01000
9−#define SMP_CORE_GROUP2_BASE 0x900020003ff01000
10−#define SMP_CORE_GROUP3_BASE 0x900030003ff01000
8+#define SMP_CORE_GROUP0_BASE (smp_group[0])
9+#define SMP_CORE_GROUP1_BASE (smp_group[1])
10+#define SMP_CORE_GROUP2_BASE (smp_group[2])
11+#define SMP_CORE_GROUP3_BASE (smp_group[3])
1112
1213 /* 4 cores in each group(node) */
13−#define SMP_CORE0_OFFSET 0x000
14−#define SMP_CORE1_OFFSET 0x100
15−#define SMP_CORE2_OFFSET 0x200
16−#define SMP_CORE3_OFFSET 0x300
14+#define SMP_CORE0_OFFSET 0x000
15+#define SMP_CORE1_OFFSET 0x100
16+#define SMP_CORE2_OFFSET 0x200
17+#define SMP_CORE3_OFFSET 0x300
1718
1819 /* ipi registers offsets */
19−#define STATUS0 0x00
20−#define EN0 0x04
21−#define SET0 0x08
22−#define CLEAR0 0x0c
23−#define STATUS1 0x10
24−#define MASK1 0x14
25−#define SET1 0x18
26−#define CLEAR1 0x1c
27−#define BUF 0x20
20+#define STATUS0 0x00
21+#define EN0 0x04
22+#define SET0 0x08
23+#define CLEAR0 0x0c
24+#define STATUS1 0x10
25+#define MASK1 0x14
26+#define SET1 0x18
27+#define CLEAR1 0x1c
28+#define BUF 0x20
2829
2930 #endif
arch/mips/math-emu/cp1emu.c+1−1
@@ -1827,7 +1827,7 @@ dcopuop: · 1826 unmodified lines
18271827 case -1:
18281828
18291829 if (cpu_has_mips_4_5_r)
1830− cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1830+ cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
18311831 else
18321832 cbit = FPU_CSR_COND;
18331833 if (rv.w)
arch/mips/mm/c-r4k.c+4−4
@@ -1230,19 +1230,19 @@ static void probe_pcache(void) · 1229 unmodified lines
12301230 case CPU_R14000:
12311231 break;
12321232
1233+ case CPU_74K:
1234+ case CPU_1074K:
1235+ alias_74k_erratum(c);
1236+ /* Fall through. */
12331237 case CPU_M14KC:
12341238 case CPU_M14KEC:
12351239 case CPU_24K:
12361240 case CPU_34K:
1237− case CPU_74K:
12381241 case CPU_1004K:
1239− case CPU_1074K:
12401242 case CPU_INTERAPTIV:
12411243 case CPU_P5600:
12421244 case CPU_PROAPTIV:
12431245 case CPU_M5150:
1244− if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K))
1245− alias_74k_erratum(c);
12461246 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
12471247 (c->icache.waysize > PAGE_SIZE))
12481248 c->icache.flags |= MIPS_CACHE_ALIASES;
arch/mips/mm/init.c+33−0
@@ -325,6 +325,38 @@ static inline void mem_init_free_highmem(void) · 324 unmodified lines
325325 #endif
326326 }
327327
328+unsigned __weak platform_maar_init(unsigned num_maars)
329+{
330+ return 0;
331+}
332+
333+static void maar_init(void)
334+{
335+ unsigned num_maars, used, i;
336+
337+ if (!cpu_has_maar)
338+ return;
339+
340+ /* Detect the number of MAARs */
341+ write_c0_maari(~0);
342+ back_to_back_c0_hazard();
343+ num_maars = read_c0_maari() + 1;
344+
345+ /* MAARs should be in pairs */
346+ WARN_ON(num_maars % 2);
347+
348+ /* Configure the required MAARs */
349+ used = platform_maar_init(num_maars / 2);
350+
351+ /* Disable any further MAARs */
352+ for (i = (used * 2); i < num_maars; i++) {
353+ write_c0_maari(i);
354+ back_to_back_c0_hazard();
355+ write_c0_maar(0);
356+ back_to_back_c0_hazard();
357+ }
358+}
359+
328360 void __init mem_init(void)
329361 {
330362 #ifdef CONFIG_HIGHMEM
@@ -337,6 +369,7 @@ void __init mem_init(void) · 6 unmodified lines
337369 #endif
338370 high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
339371
372+ maar_init();
340373 free_all_bootmem();
341374 setup_zero_pages(); /* Setup zeroed pages. */
342375 mem_init_free_highmem();
arch/mips/mm/tlb-r3k.c+1−1
@@ -158,7 +158,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) · 157 unmodified lines
158158 {
159159 int cpu = smp_processor_id();
160160
161− if (!vma || cpu_context(cpu, vma->vm_mm) != 0) {
161+ if (cpu_context(cpu, vma->vm_mm) != 0) {
162162 unsigned long flags;
163163 int oldpid, newpid, idx;
164164
arch/mips/mm/tlb-r4k.c+59−0
@@ -57,6 +57,7 @@ void local_flush_tlb_all(void) · 56 unmodified lines
5757 local_irq_save(flags);
5858 /* Save old context and create impossible VPN2 value */
5959 old_ctx = read_c0_entryhi();
60+ htw_stop();
6061 write_c0_entrylo0(0);
6162 write_c0_entrylo1(0);
6263
@@ -90,6 +91,7 @@ void local_flush_tlb_all(void) · 27 unmodified lines
9091 }
9192 tlbw_use_hazard();
9293 write_c0_entryhi(old_ctx);
94+ htw_start();
9395 flush_itlb();
9496 local_irq_restore(flags);
9597 }
@@ -131,6 +133,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, · 35 unmodified lines
131133 int oldpid = read_c0_entryhi();
132134 int newpid = cpu_asid(cpu, mm);
133135
136+ htw_stop();
134137 while (start < end) {
135138 int idx;
136139
@@ -151,6 +154,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, · 14 unmodified lines
151154 }
152155 tlbw_use_hazard();
153156 write_c0_entryhi(oldpid);
157+ htw_start();
154158 } else {
155159 drop_mmu_context(mm, cpu);
156160 }
@@ -174,6 +178,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) · 17 unmodified lines
174178 start &= (PAGE_MASK << 1);
175179 end += ((PAGE_SIZE << 1) - 1);
176180 end &= (PAGE_MASK << 1);
181+ htw_stop();
177182
178183 while (start < end) {
179184 int idx;
@@ -195,6 +200,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) · 15 unmodified lines
195200 }
196201 tlbw_use_hazard();
197202 write_c0_entryhi(pid);
203+ htw_start();
198204 } else {
199205 local_flush_tlb_all();
200206 }
@@ -214,6 +220,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) · 13 unmodified lines
214220 page &= (PAGE_MASK << 1);
215221 local_irq_save(flags);
216222 oldpid = read_c0_entryhi();
223+ htw_stop();
217224 write_c0_entryhi(page | newpid);
218225 mtc0_tlbw_hazard();
219226 tlb_probe();
@@ -231,6 +238,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) · 11 unmodified lines
231238
232239 finish:
233240 write_c0_entryhi(oldpid);
241+ htw_start();
234242 flush_itlb_vm(vma);
235243 local_irq_restore(flags);
236244 }
@@ -247,6 +255,7 @@ void local_flush_tlb_one(unsigned long page) · 10 unmodified lines
247255
248256 local_irq_save(flags);
249257 oldpid = read_c0_entryhi();
258+ htw_stop();
250259 page &= (PAGE_MASK << 1);
251260 write_c0_entryhi(page);
252261 mtc0_tlbw_hazard();
@@ -263,6 +272,7 @@ void local_flush_tlb_one(unsigned long page) · 10 unmodified lines
263272 tlbw_use_hazard();
264273 }
265274 write_c0_entryhi(oldpid);
275+ htw_start();
266276 flush_itlb();
267277 local_irq_restore(flags);
268278 }
@@ -351,6 +361,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, · 82 unmodified lines
351361 local_irq_save(flags);
352362 /* Save old context and create impossible VPN2 value */
353363 old_ctx = read_c0_entryhi();
364+ htw_stop();
354365 old_pagemask = read_c0_pagemask();
355366 wired = read_c0_wired();
356367 write_c0_wired(wired + 1);
@@ -366,6 +377,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, · 9 unmodified lines
366377
367378 write_c0_entryhi(old_ctx);
368379 tlbw_use_hazard(); /* What is the hazard here? */
380+ htw_start();
369381 write_c0_pagemask(old_pagemask);
370382 local_flush_tlb_all();
371383 local_irq_restore(flags);
@@ -391,6 +403,51 @@ int __init has_transparent_hugepage(void) · 19 unmodified lines
391403
392404 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
393405
406+/*
407+ * Used for loading TLB entries before trap_init() has started, when we
408+ * don't actually want to add a wired entry which remains throughout the
409+ * lifetime of the system
410+ */
411+
412+int temp_tlb_entry __cpuinitdata;
413+
414+__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
415+ unsigned long entryhi, unsigned long pagemask)
416+{
417+ int ret = 0;
418+ unsigned long flags;
419+ unsigned long wired;
420+ unsigned long old_pagemask;
421+ unsigned long old_ctx;
422+
423+ local_irq_save(flags);
424+ /* Save old context and create impossible VPN2 value */
425+ old_ctx = read_c0_entryhi();
426+ old_pagemask = read_c0_pagemask();
427+ wired = read_c0_wired();
428+ if (--temp_tlb_entry < wired) {
429+ printk(KERN_WARNING
430+ "No TLB space left for add_temporary_entry\n");
431+ ret = -ENOSPC;
432+ goto out;
433+ }
434+
435+ write_c0_index(temp_tlb_entry);
436+ write_c0_pagemask(pagemask);
437+ write_c0_entryhi(entryhi);
438+ write_c0_entrylo0(entrylo0);
439+ write_c0_entrylo1(entrylo1);
440+ mtc0_tlbw_hazard();
441+ tlb_write_indexed();
442+ tlbw_use_hazard();
443+
444+ write_c0_entryhi(old_ctx);
445+ write_c0_pagemask(old_pagemask);
446+out:
447+ local_irq_restore(flags);
448+ return ret;
449+}
450+
394451 static int ntlb;
395452 static int __init set_ntlb(char *str)
396453 {
@@ -431,6 +488,8 @@ static void r4k_tlb_configure(void) · 34 unmodified lines
431488 write_c0_pagegrain(pg);
432489 }
433490
491+ temp_tlb_entry = current_cpu_data.tlbsize - 1;
492+
434493 /* From this point on the ARC firmware is dead. */
435494 local_flush_tlb_all();
436495
arch/mips/mm/tlbex.c+96−2
@@ -429,6 +429,7 @@ static void build_r3000_tlb_refill_handler(void) · 428 unmodified lines
429429 (unsigned int)(p - tlb_handler));
430430
431431 memcpy((void *)ebase, tlb_handler, 0x80);
432+ local_flush_icache_range(ebase, ebase + 0x80);
432433
433434 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
434435 }
@@ -1299,6 +1300,7 @@ static void build_r4000_tlb_refill_handler(void) · 864 unmodified lines
12991300 }
13001301 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
13011302 uasm_l_tlb_huge_update(&l, p);
1303+ UASM_i_LW(&p, K0, 0, K1);
13021304 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
13031305 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
13041306 htlb_info.restore_scratch);
@@ -1415,6 +1417,7 @@ static void build_r4000_tlb_refill_handler(void) · 110 unmodified lines
14151417 final_len);
14161418
14171419 memcpy((void *)ebase, final_handler, 0x100);
1420+ local_flush_icache_range(ebase, ebase + 0x100);
14181421
14191422 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
14201423 }
@@ -1919,7 +1922,7 @@ static void build_r4000_tlb_load_handler(void) · 498 unmodified lines
19191922 if (m4kc_tlbp_war())
19201923 build_tlb_probe_entry(&p);
19211924
1922− if (cpu_has_rixi) {
1925+ if (cpu_has_rixi && !cpu_has_rixiex) {
19231926 /*
19241927 * If the page is not _PAGE_VALID, RI or XI could not
19251928 * have triggered it. Skip the expensive test..
@@ -1986,7 +1989,7 @@ static void build_r4000_tlb_load_handler(void) · 60 unmodified lines
19861989 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
19871990 build_tlb_probe_entry(&p);
19881991
1989− if (cpu_has_rixi) {
1992+ if (cpu_has_rixi && !cpu_has_rixiex) {
19901993 /*
19911994 * If the page is not _PAGE_VALID, RI or XI could not
19921995 * have triggered it. Skip the expensive test..
@@ -2194,6 +2197,94 @@ static void flush_tlb_handlers(void) · 201 unmodified lines
21942197 (unsigned long)tlbmiss_handler_setup_pgd_end);
21952198 }
21962199
2200+static void print_htw_config(void)
2201+{
2202+ unsigned long config;
2203+ unsigned int pwctl;
2204+ const int field = 2 * sizeof(unsigned long);
2205+
2206+ config = read_c0_pwfield();
2207+ pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
2208+ field, config,
2209+ (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
2210+ (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
2211+ (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
2212+ (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
2213+ (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2214+
2215+ config = read_c0_pwsize();
2216+ pr_debug("PWSize (0x%0*lx): GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
2217+ field, config,
2218+ (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2219+ (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2220+ (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
2221+ (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
2222+ (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2223+
2224+ pwctl = read_c0_pwctl();
2225+ pr_debug("PWCtl (0x%x): PWEn: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
2226+ pwctl,
2227+ (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
2228+ (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2229+ (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2230+ (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
2231+}
2232+
2233+static void config_htw_params(void)
2234+{
2235+ unsigned long pwfield, pwsize, ptei;
2236+ unsigned int config;
2237+
2238+ /*
2239+ * We are using 2-level page tables, so we only need to
2240+ * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2241+ * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2242+ * write values less than 0xc in these fields because the entire
2243+ * write will be dropped. As a result of which, we must preserve
2244+ * the original reset values and overwrite only what we really want.
2245+ */
2246+
2247+ pwfield = read_c0_pwfield();
2248+ /* re-initialize the GDI field */
2249+ pwfield &= ~MIPS_PWFIELD_GDI_MASK;
2250+ pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
2251+ /* re-initialize the PTI field including the even/odd bit */
2252+ pwfield &= ~MIPS_PWFIELD_PTI_MASK;
2253+ pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
2254+ /* Set the PTEI right shift */
2255+ ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
2256+ pwfield |= ptei;
2257+ write_c0_pwfield(pwfield);
2258+ /* Check whether the PTEI value is supported */
2259+ back_to_back_c0_hazard();
2260+ pwfield = read_c0_pwfield();
2261+ if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
2262+ != ptei) {
2263+ pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2264+ ptei);
2265+ /*
2266+ * Drop option to avoid HTW being enabled via another path
2267+ * (eg htw_reset())
2268+ */
2269+ current_cpu_data.options &= ~MIPS_CPU_HTW;
2270+ return;
2271+ }
2272+
2273+ pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2274+ pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
2275+ write_c0_pwsize(pwsize);
2276+
2277+ /* Make sure everything is set before we enable the HTW */
2278+ back_to_back_c0_hazard();
2279+
2280+ /* Enable HTW and disable the rest of the pwctl fields */
2281+ config = 1 << MIPS_PWCTL_PWEN_SHIFT;
2282+ write_c0_pwctl(config);
2283+ pr_info("Hardware Page Table Walker enabled\n");
2284+
2285+ print_htw_config();
2286+}
2287+
21972288 void build_tlb_refill_handler(void)
21982289 {
21992290 /*
@@ -2258,5 +2349,8 @@ void build_tlb_refill_handler(void) · 58 unmodified lines
22582349 }
22592350 if (cpu_has_local_ebase)
22602351 build_r4000_tlb_refill_handler();
2352+ if (cpu_has_htw)
2353+ config_htw_params();
2354+
22612355 }
22622356 }
arch/mips/mti-malta/malta-int.c+19−8
@@ -42,6 +42,10 @@ static unsigned int ipi_map[NR_CPUS]; · 41 unmodified lines
4242
4343 static DEFINE_RAW_SPINLOCK(mips_irq_lock);
4444
45+#ifdef CONFIG_MIPS_GIC_IPI
46+DECLARE_BITMAP(ipi_ints, GIC_NUM_INTRS);
47+#endif
48+
4549 static inline int mips_pcibios_iack(void)
4650 {
4751 int irq;
@@ -125,16 +129,22 @@ static void malta_hw0_irqdispatch(void) · 77 unmodified lines
125129
126130 static void malta_ipi_irqdispatch(void)
127131 {
128− int irq;
132+#ifdef CONFIG_MIPS_GIC_IPI
133+ unsigned long irq;
134+ DECLARE_BITMAP(pending, GIC_NUM_INTRS);
129135
130− if (gic_compare_int())
131− do_IRQ(MIPS_GIC_IRQ_BASE);
136+ gic_get_int_mask(pending, ipi_ints);
137+
138+ irq = find_first_bit(pending, GIC_NUM_INTRS);
132139
133− irq = gic_get_int();
134− if (irq < 0)
135− return; /* interrupt has already been cleared */
140+ while (irq < GIC_NUM_INTRS) {
141+ do_IRQ(MIPS_GIC_IRQ_BASE + irq);
136142
137− do_IRQ(MIPS_GIC_IRQ_BASE + irq);
143+ irq = find_next_bit(pending, GIC_NUM_INTRS, irq + 1);
144+ }
145+#endif
146+ if (gic_compare_int())
147+ do_IRQ(MIPS_GIC_IRQ_BASE);
138148 }
139149
140150 static void corehi_irqdispatch(void)
@@ -427,8 +437,9 @@ static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) · 286 unmodified lines
427437 gic_intr_map[intr].pin = cpupin;
428438 gic_intr_map[intr].polarity = GIC_POL_POS;
429439 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
430− gic_intr_map[intr].flags = GIC_FLAG_IPI;
440+ gic_intr_map[intr].flags = 0;
431441 ipi_map[cpu] |= (1 << (cpupin + 2));
442+ bitmap_set(ipi_ints, intr, 1);
432443 }
433444
434445 static void __init fill_ipi_map(void)
arch/mips/mti-malta/malta-memory.c+26−0
@@ -16,6 +16,7 @@ · 15 unmodified lines
1616 #include <linux/string.h>
1717
1818 #include <asm/bootinfo.h>
19+#include <asm/maar.h>
1920 #include <asm/sections.h>
2021 #include <asm/fw/fw.h>
2122
@@ -164,3 +165,28 @@ void __init prom_free_prom_memory(void) · 142 unmodified lines
164165 addr, addr + boot_mem_map.map[i].size);
165166 }
166167 }
168+
169+unsigned platform_maar_init(unsigned num_pairs)
170+{
171+ phys_addr_t mem_end = (physical_memsize & ~0xffffull) - 1;
172+ struct maar_config cfg[] = {
173+ /* DRAM preceding I/O */
174+ { 0x00000000, 0x0fffffff, MIPS_MAAR_S },
175+
176+ /* DRAM following I/O */
177+ { 0x20000000, mem_end, MIPS_MAAR_S },
178+
179+ /* DRAM alias in upper half of physical */
180+ { 0x80000000, 0x80000000 + mem_end, MIPS_MAAR_S },
181+ };
182+ unsigned i, num_cfg = ARRAY_SIZE(cfg);
183+
184+ /* If DRAM fits before I/O, drop the region following it */
185+ if (physical_memsize <= 0x10000000) {
186+ num_cfg--;
187+ for (i = 1; i < num_cfg; i++)
188+ cfg[i] = cfg[i + 1];
189+ }
190+
191+ return maar_config(cfg, num_cfg, num_pairs);
192+}
arch/mips/pci/Makefile+1−1
@@ -29,7 +29,7 @@ obj-$(CONFIG_LASAT) += pci-lasat.o · 28 unmodified lines
2929 obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
3030 obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
3131 obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
32−obj-$(CONFIG_LEMOTE_MACH3A) += fixup-loongson3.o ops-loongson3.o
32+obj-$(CONFIG_LOONGSON_MACH3X) += fixup-loongson3.o ops-loongson3.o
3333 obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o pci-malta.o
3434 obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
3535 obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
arch/mips/pci/ops-tx4927.c+0−2
@@ -199,8 +199,6 @@ static struct { · 198 unmodified lines
199199
200200 char *tx4927_pcibios_setup(char *str)
201201 {
202− unsigned long val;
203−
204202 if (!strncmp(str, "trdyto=", 7)) {
205203 u8 val = 0;
206204 if (kstrtou8(str + 7, 0, &val) == 0)
arch/mips/pci/pci-alchemy.c+23−1
@@ -7,6 +7,7 @@ · 6 unmodified lines
77 * Support for all devices (greater than 16) added by David Gathright.
88 */
99
10+#include <linux/clk.h>
1011 #include <linux/export.h>
1112 #include <linux/types.h>
1213 #include <linux/pci.h>
@@ -364,6 +365,7 @@ static int alchemy_pci_probe(struct platform_device *pdev) · 351 unmodified lines
364365 void __iomem *virt_io;
365366 unsigned long val;
366367 struct resource *r;
368+ struct clk *c;
367369 int ret;
368370
369371 /* need at least PCI IRQ mapping table */
@@ -393,11 +395,24 @@ static int alchemy_pci_probe(struct platform_device *pdev) · 23 unmodified lines
393395 goto out1;
394396 }
395397
398+ c = clk_get(&pdev->dev, "pci_clko");
399+ if (IS_ERR(c)) {
400+ dev_err(&pdev->dev, "unable to find PCI clock\n");
401+ ret = PTR_ERR(c);
402+ goto out2;
403+ }
404+
405+ ret = clk_prepare_enable(c);
406+ if (ret) {
407+ dev_err(&pdev->dev, "cannot enable PCI clock\n");
408+ goto out6;
409+ }
410+
396411 ctx->regs = ioremap_nocache(r->start, resource_size(r));
397412 if (!ctx->regs) {
398413 dev_err(&pdev->dev, "cannot map pci regs\n");
399414 ret = -ENODEV;
400− goto out2;
415+ goto out5;
401416 }
402417
403418 /* map parts of the PCI IO area */
@@ -465,12 +480,19 @@ static int alchemy_pci_probe(struct platform_device *pdev) · 61 unmodified lines
465480 register_syscore_ops(&alchemy_pci_pmops);
466481 register_pci_controller(&ctx->alchemy_pci_ctrl);
467482
483+ dev_info(&pdev->dev, "PCI controller at %ld MHz\n",
484+ clk_get_rate(c) / 1000000);
485+
468486 return 0;
469487
470488 out4:
471489 iounmap(virt_io);
472490 out3:
473491 iounmap(ctx->regs);
492+out5:
493+ clk_disable_unprepare(c);
494+out6:
495+ clk_put(c);
474496 out2:
475497 release_mem_region(r->start, resource_size(r));
476498 out1:
arch/mips/ralink/of.c+1−1
@@ -81,7 +81,7 @@ static int __init plat_of_setup(void) · 80 unmodified lines
8181 panic("device tree not present");
8282
8383 strlcpy(of_ids[0].compatible, soc_info.compatible, len);
84− strncpy(of_ids[1].compatible, "palmbus", len);
84+ strlcpy(of_ids[1].compatible, "palmbus", len);
8585
8686 if (of_platform_populate(NULL, of_ids, NULL, NULL))
8787 panic("failed to populate DT");
arch/mips/rb532/devices.c+5−23
@@ -223,6 +223,7 @@ static struct platform_device rb532_wdt = { · 222 unmodified lines
223223
224224 static struct plat_serial8250_port rb532_uart_res[] = {
225225 {
226+ .type = PORT_16550A,
226227 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
227228 .irq = UART0_IRQ,
228229 .regshift = 2,
@@ -250,28 +251,6 @@ static struct platform_device *rb532_devs[] = { · 21 unmodified lines
250251 &rb532_wdt
251252 };
252253
253−static void __init parse_mac_addr(char *macstr)
254−{
255− int i, h, l;
256−
257− for (i = 0; i < 6; i++) {
258− if (i != 5 && *(macstr + 2) != ':')
259− return;
260−
261− h = hex_to_bin(*macstr++);
262− if (h == -1)
263− return;
264−
265− l = hex_to_bin(*macstr++);
266− if (l == -1)
267− return;
268−
269− macstr++;
270− korina_dev0_data.mac[i] = (h << 4) + l;
271− }
272−}
273−
274−
275254 /* NAND definitions */
276255 #define NAND_CHIP_DELAY 25
277256
@@ -333,7 +312,10 @@ static int __init plat_setup_devices(void) · 55 unmodified lines
333312 static int __init setup_kmac(char *s)
334313 {
335314 printk(KERN_INFO "korina mac = %s\n", s);
336− parse_mac_addr(s);
315+ if (!mac_pton(s, korina_dev0_data.mac)) {
316+ printk(KERN_ERR "Invalid mac\n");
317+ return -EINVAL;
318+ }
337319 return 0;
338320 }
339321
arch/mips/sgi-ip22/ip22-gio.c+9−1
@@ -27,8 +27,14 @@ static struct { · 26 unmodified lines
2727 { .name = "SGI GR2/GR3", .id = 0x7f },
2828 };
2929
30+static void gio_bus_release(struct device *dev)
31+{
32+ kfree(dev);
33+}
34+
3035 static struct device gio_bus = {
3136 .init_name = "gio",
37+ .release = &gio_bus_release,
3238 };
3339
3440 /**
@@ -413,8 +419,10 @@ int __init ip22_gio_init(void) · 378 unmodified lines
413419 int ret;
414420
415421 ret = device_register(&gio_bus);
416− if (ret)
422+ if (ret) {
423+ put_device(&gio_bus);
417424 return ret;
425+ }
418426
419427 ret = bus_register(&gio_bus_type);
420428 if (!ret) {
arch/mips/txx9/generic/7segled.c+11−3
@@ -83,6 +83,11 @@ static struct bus_type tx_7segled_subsys = { · 82 unmodified lines
8383 .dev_name = "7segled",
8484 };
8585
86+static void tx_7segled_release(struct device *dev)
87+{
88+ kfree(dev);
89+}
90+
8691 static int __init tx_7segled_init_sysfs(void)
8792 {
8893 int error, i;
@@ -103,11 +108,14 @@ static int __init tx_7segled_init_sysfs(void) · 14 unmodified lines
103108 }
104109 dev->id = i;
105110 dev->bus = &tx_7segled_subsys;
111+ dev->release = &tx_7segled_release;
106112 error = device_register(dev);
107− if (!error) {
108− device_create_file(dev, &dev_attr_ascii);
109− device_create_file(dev, &dev_attr_raw);
113+ if (error) {
114+ put_device(dev);
115+ return error;
110116 }
117+ device_create_file(dev, &dev_attr_ascii);
118+ device_create_file(dev, &dev_attr_raw);
111119 }
112120 return error;
113121 }
arch/mips/txx9/generic/pci.c+2−2
@@ -268,7 +268,7 @@ static int txx9_i8259_irq_setup(int irq) · 267 unmodified lines
268268 return err;
269269 }
270270
271−static void quirk_slc90e66_bridge(struct pci_dev *dev)
271+static void __init_refok quirk_slc90e66_bridge(struct pci_dev *dev)
272272 {
273273 int irq; /* PCI/ISA Bridge interrupt */
274274 u8 reg_64;
@@ -331,7 +331,7 @@ static void quirk_slc90e66_ide(struct pci_dev *dev) · 56 unmodified lines
331331 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
332332 */
333333 dat |= 0x01;
334− pci_write_config_byte(dev, regs[i], dat);
334+ pci_write_config_byte(dev, 0x5c, dat);
335335 pci_read_config_byte(dev, 0x5c, &dat);
336336 printk(KERN_CONT " REG5C %02x", dat);
337337 printk(KERN_CONT "\n");
arch/mips/txx9/generic/setup.c+19−10
@@ -937,6 +937,14 @@ static ssize_t txx9_sram_write(struct file *filp, struct kobject *kobj, · 936 unmodified lines
937937 return size;
938938 }
939939
940+static void txx9_device_release(struct device *dev)
941+{
942+ struct txx9_sramc_dev *tdev;
943+
944+ tdev = container_of(dev, struct txx9_sramc_dev, dev);
945+ kfree(tdev);
946+}
947+
940948 void __init txx9_sramc_init(struct resource *r)
941949 {
942950 struct txx9_sramc_dev *dev;
@@ -951,8 +959,11 @@ void __init txx9_sramc_init(struct resource *r) · 8 unmodified lines
951959 return;
952960 size = resource_size(r);
953961 dev->base = ioremap(r->start, size);
954− if (!dev->base)
955− goto exit;
962+ if (!dev->base) {
963+ kfree(dev);
964+ return;
965+ }
966+ dev->dev.release = &txx9_device_release;
956967 dev->dev.bus = &txx9_sramc_subsys;
957968 sysfs_bin_attr_init(&dev->bindata_attr);
958969 dev->bindata_attr.attr.name = "bindata";
@@ -963,17 +974,15 @@ void __init txx9_sramc_init(struct resource *r) · 4 unmodified lines
963974 dev->bindata_attr.private = dev;
964975 err = device_register(&dev->dev);
965976 if (err)
966− goto exit;
977+ goto exit_put;
967978 err = sysfs_create_bin_file(&dev->dev.kobj, &dev->bindata_attr);
968979 if (err) {
969980 device_unregister(&dev->dev);
970− goto exit;
971− }
972− return;
973−exit:
974− if (dev) {
975− if (dev->base)
976− iounmap(dev->base);
981+ iounmap(dev->base);
977982 kfree(dev);
978983 }
984+ return;
985+exit_put:
986+ put_device(&dev->dev);
987+ return;
979988 }
drivers/cpufreq/loongson2_cpufreq.c+3−3
@@ -148,9 +148,9 @@ static void loongson2_cpu_wait(void) · 147 unmodified lines
148148 u32 cpu_freq;
149149
150150 spin_lock_irqsave(&loongson2_wait_lock, flags);
151− cpu_freq = LOONGSON_CHIPCFG0;
152− LOONGSON_CHIPCFG0 &= ~0x7; /* Put CPU into wait mode */
153− LOONGSON_CHIPCFG0 = cpu_freq; /* Restore CPU state */
151+ cpu_freq = LOONGSON_CHIPCFG(0);
152+ LOONGSON_CHIPCFG(0) &= ~0x7; /* Put CPU into wait mode */
153+ LOONGSON_CHIPCFG(0) = cpu_freq; /* Restore CPU state */
154154 spin_unlock_irqrestore(&loongson2_wait_lock, flags);
155155 local_irq_enable();
156156 }
drivers/mmc/host/au1xmmc.c+107−91
@@ -32,6 +32,7 @@ · 31 unmodified lines
3232 * (the low to high transition will not occur).
3333 */
3434
35+#include <linux/clk.h>
3536 #include <linux/module.h>
3637 #include <linux/init.h>
3738 #include <linux/platform_device.h>
@@ -90,7 +91,7 @@ struct au1xmmc_host { · 52 unmodified lines
9091 struct mmc_request *mrq;
9192
9293 u32 flags;
93− u32 iobase;
94+ void __iomem *iobase;
9495 u32 clock;
9596 u32 bus_width;
9697 u32 power_mode;
@@ -118,6 +119,7 @@ struct au1xmmc_host { · 21 unmodified lines
118119 struct au1xmmc_platform_data *platdata;
119120 struct platform_device *pdev;
120121 struct resource *ioarea;
122+ struct clk *clk;
121123 };
122124
123125 /* Status flags used by the host structure */
@@ -162,32 +164,33 @@ static inline int has_dbdma(void) · 38 unmodified lines
162164
163165 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
164166 {
165− u32 val = au_readl(HOST_CONFIG(host));
167+ u32 val = __raw_readl(HOST_CONFIG(host));
166168 val |= mask;
167− au_writel(val, HOST_CONFIG(host));
168− au_sync();
169+ __raw_writel(val, HOST_CONFIG(host));
170+ wmb(); /* drain writebuffer */
169171 }
170172
171173 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
172174 {
173− u32 val = au_readl(HOST_CONFIG2(host));
175+ u32 val = __raw_readl(HOST_CONFIG2(host));
174176
175− au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
176− au_sync_delay(1);
177+ __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
178+ wmb(); /* drain writebuffer */
179+ mdelay(1);
177180
178181 /* SEND_STOP will turn off clock control - this re-enables it */
179182 val &= ~SD_CONFIG2_DF;
180183
181− au_writel(val, HOST_CONFIG2(host));
182− au_sync();
184+ __raw_writel(val, HOST_CONFIG2(host));
185+ wmb(); /* drain writebuffer */
183186 }
184187
185188 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
186189 {
187− u32 val = au_readl(HOST_CONFIG(host));
190+ u32 val = __raw_readl(HOST_CONFIG(host));
188191 val &= ~mask;
189− au_writel(val, HOST_CONFIG(host));
190− au_sync();
192+ __raw_writel(val, HOST_CONFIG(host));
193+ wmb(); /* drain writebuffer */
191194 }
192195
193196 static inline void SEND_STOP(struct au1xmmc_host *host)
@@ -197,12 +200,13 @@ static inline void SEND_STOP(struct au1xmmc_host *host) · 3 unmodified lines
197200 WARN_ON(host->status != HOST_S_DATA);
198201 host->status = HOST_S_STOP;
199202
200− config2 = au_readl(HOST_CONFIG2(host));
201− au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
202− au_sync();
203+ config2 = __raw_readl(HOST_CONFIG2(host));
204+ __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
205+ wmb(); /* drain writebuffer */
203206
204207 /* Send the stop command */
205− au_writel(STOP_CMD, HOST_CMD(host));
208+ __raw_writel(STOP_CMD, HOST_CMD(host));
209+ wmb(); /* drain writebuffer */
206210 }
207211
208212 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
@@ -296,28 +300,28 @@ static int au1xmmc_send_command(struct au1xmmc_host *host, int wait, · 87 unmodified lines
296300 }
297301 }
298302
299− au_writel(cmd->arg, HOST_CMDARG(host));
300− au_sync();
303+ __raw_writel(cmd->arg, HOST_CMDARG(host));
304+ wmb(); /* drain writebuffer */
301305
302306 if (wait)
303307 IRQ_OFF(host, SD_CONFIG_CR);
304308
305− au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
306− au_sync();
309+ __raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
310+ wmb(); /* drain writebuffer */
307311
308312 /* Wait for the command to go on the line */
309− while (au_readl(HOST_CMD(host)) & SD_CMD_GO)
313+ while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO)
310314 /* nop */;
311315
312316 /* Wait for the command to come back */
313317 if (wait) {
314− u32 status = au_readl(HOST_STATUS(host));
318+ u32 status = __raw_readl(HOST_STATUS(host));
315319
316320 while (!(status & SD_STATUS_CR))
317− status = au_readl(HOST_STATUS(host));
321+ status = __raw_readl(HOST_STATUS(host));
318322
319323 /* Clear the CR status */
320− au_writel(SD_STATUS_CR, HOST_STATUS(host));
324+ __raw_writel(SD_STATUS_CR, HOST_STATUS(host));
321325
322326 IRQ_ON(host, SD_CONFIG_CR);
323327 }
@@ -339,11 +343,11 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) · 15 unmodified lines
339343 data = mrq->cmd->data;
340344
341345 if (status == 0)
342− status = au_readl(HOST_STATUS(host));
346+ status = __raw_readl(HOST_STATUS(host));
343347
344348 /* The transaction is really over when the SD_STATUS_DB bit is clear */
345349 while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
346− status = au_readl(HOST_STATUS(host));
350+ status = __raw_readl(HOST_STATUS(host));
347351
348352 data->error = 0;
349353 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
@@ -357,7 +361,7 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) · 7 unmodified lines
357361 data->error = -EILSEQ;
358362
359363 /* Clear the CRC bits */
360− au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
364+ __raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
361365
362366 data->bytes_xfered = 0;
363367
@@ -380,7 +384,7 @@ static void au1xmmc_tasklet_data(unsigned long param) · 16 unmodified lines
380384 {
381385 struct au1xmmc_host *host = (struct au1xmmc_host *)param;
382386
383− u32 status = au_readl(HOST_STATUS(host));
387+ u32 status = __raw_readl(HOST_STATUS(host));
384388 au1xmmc_data_complete(host, status);
385389 }
386390
@@ -412,15 +416,15 @@ static void au1xmmc_send_pio(struct au1xmmc_host *host) · 25 unmodified lines
412416 max = AU1XMMC_MAX_TRANSFER;
413417
414418 for (count = 0; count < max; count++) {
415− status = au_readl(HOST_STATUS(host));
419+ status = __raw_readl(HOST_STATUS(host));
416420
417421 if (!(status & SD_STATUS_TH))
418422 break;
419423
420424 val = *sg_ptr++;
421425
422− au_writel((unsigned long)val, HOST_TXPORT(host));
423− au_sync();
426+ __raw_writel((unsigned long)val, HOST_TXPORT(host));
427+ wmb(); /* drain writebuffer */
424428 }
425429
426430 host->pio.len -= count;
@@ -472,7 +476,7 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host) · 45 unmodified lines
472476 max = AU1XMMC_MAX_TRANSFER;
473477
474478 for (count = 0; count < max; count++) {
475− status = au_readl(HOST_STATUS(host));
479+ status = __raw_readl(HOST_STATUS(host));
476480
477481 if (!(status & SD_STATUS_NE))
478482 break;
@@ -494,7 +498,7 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host) · 15 unmodified lines
494498 break;
495499 }
496500
497− val = au_readl(HOST_RXPORT(host));
501+ val = __raw_readl(HOST_RXPORT(host));
498502
499503 if (sg_ptr)
500504 *sg_ptr++ = (unsigned char)(val & 0xFF);
@@ -537,10 +541,10 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) · 36 unmodified lines
537541
538542 if (cmd->flags & MMC_RSP_PRESENT) {
539543 if (cmd->flags & MMC_RSP_136) {
540− r[0] = au_readl(host->iobase + SD_RESP3);
541− r[1] = au_readl(host->iobase + SD_RESP2);
542− r[2] = au_readl(host->iobase + SD_RESP1);
543− r[3] = au_readl(host->iobase + SD_RESP0);
544+ r[0] = __raw_readl(host->iobase + SD_RESP3);
545+ r[1] = __raw_readl(host->iobase + SD_RESP2);
546+ r[2] = __raw_readl(host->iobase + SD_RESP1);
547+ r[3] = __raw_readl(host->iobase + SD_RESP0);
544548
545549 /* The CRC is omitted from the response, so really
546550 * we only got 120 bytes, but the engine expects
@@ -559,7 +563,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) · 12 unmodified lines
559563 * that means that the OSR data starts at bit 31,
560564 * so we can just read RESP0 and return that.
561565 */
562− cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
566+ cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0);
563567 }
564568 }
565569
@@ -586,7 +590,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) · 20 unmodified lines
586590 u32 mask = SD_STATUS_DB | SD_STATUS_NE;
587591
588592 while((status & mask) != mask)
589− status = au_readl(HOST_STATUS(host));
593+ status = __raw_readl(HOST_STATUS(host));
590594 }
591595
592596 au1xxx_dbdma_start(channel);
@@ -595,24 +599,17 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) · 2 unmodified lines
595599
596600 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
597601 {
598− unsigned int pbus = get_au1x00_speed();
599− unsigned int divisor;
602+ unsigned int pbus = clk_get_rate(host->clk);
603+ unsigned int divisor = ((pbus / rate) / 2) - 1;
600604 u32 config;
601605
602− /* From databook:
603− * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
604− */
605− pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
606− pbus /= 2;
607− divisor = ((pbus / rate) / 2) - 1;
608−
609− config = au_readl(HOST_CONFIG(host));
606+ config = __raw_readl(HOST_CONFIG(host));
610607
611608 config &= ~(SD_CONFIG_DIV);
612609 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
613610
614− au_writel(config, HOST_CONFIG(host));
615− au_sync();
611+ __raw_writel(config, HOST_CONFIG(host));
612+ wmb(); /* drain writebuffer */
616613 }
617614
618615 static int au1xmmc_prepare_data(struct au1xmmc_host *host,
@@ -636,7 +633,7 @@ static int au1xmmc_prepare_data(struct au1xmmc_host *host, · 17 unmodified lines
636633 if (host->dma.len == 0)
637634 return -ETIMEDOUT;
638635
639− au_writel(data->blksz - 1, HOST_BLKSIZE(host));
636+ __raw_writel(data->blksz - 1, HOST_BLKSIZE(host));
640637
641638 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
642639 int i;
@@ -723,31 +720,34 @@ static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) · 80 unmodified lines
723720 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
724721 {
725722 /* Apply the clock */
726− au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
727− au_sync_delay(1);
723+ __raw_writel(SD_ENABLE_CE, HOST_ENABLE(host));
724+ wmb(); /* drain writebuffer */
725+ mdelay(1);
728726
729− au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
730− au_sync_delay(5);
727+ __raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
728+ wmb(); /* drain writebuffer */
729+ mdelay(5);
731730
732− au_writel(~0, HOST_STATUS(host));
733− au_sync();
731+ __raw_writel(~0, HOST_STATUS(host));
732+ wmb(); /* drain writebuffer */
734733
735− au_writel(0, HOST_BLKSIZE(host));
736− au_writel(0x001fffff, HOST_TIMEOUT(host));
737− au_sync();
734+ __raw_writel(0, HOST_BLKSIZE(host));
735+ __raw_writel(0x001fffff, HOST_TIMEOUT(host));
736+ wmb(); /* drain writebuffer */
738737
739− au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
740− au_sync();
738+ __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
739+ wmb(); /* drain writebuffer */
741740
742− au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
743− au_sync_delay(1);
741+ __raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
742+ wmb(); /* drain writebuffer */
743+ mdelay(1);
744744
745− au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
746− au_sync();
745+ __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
746+ wmb(); /* drain writebuffer */
747747
748748 /* Configure interrupts */
749− au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
750− au_sync();
749+ __raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
750+ wmb(); /* drain writebuffer */
751751 }
752752
753753
@@ -767,7 +767,7 @@ static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) · 13 unmodified lines
767767 host->clock = ios->clock;
768768 }
769769
770− config2 = au_readl(HOST_CONFIG2(host));
770+ config2 = __raw_readl(HOST_CONFIG2(host));
771771 switch (ios->bus_width) {
772772 case MMC_BUS_WIDTH_8:
773773 config2 |= SD_CONFIG2_BB;
@@ -780,8 +780,8 @@ static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) · 6 unmodified lines
780780 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
781781 break;
782782 }
783− au_writel(config2, HOST_CONFIG2(host));
784− au_sync();
783+ __raw_writel(config2, HOST_CONFIG2(host));
784+ wmb(); /* drain writebuffer */
785785 }
786786
787787 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
@@ -793,7 +793,7 @@ static irqreturn_t au1xmmc_irq(int irq, void *dev_id) · 5 unmodified lines
793793 struct au1xmmc_host *host = dev_id;
794794 u32 status;
795795
796− status = au_readl(HOST_STATUS(host));
796+ status = __raw_readl(HOST_STATUS(host));
797797
798798 if (!(status & SD_STATUS_I))
799799 return IRQ_NONE; /* not ours */
@@ -839,8 +839,8 @@ static irqreturn_t au1xmmc_irq(int irq, void *dev_id) · 39 unmodified lines
839839 status);
840840 }
841841
842− au_writel(status, HOST_STATUS(host));
843− au_sync();
842+ __raw_writel(status, HOST_STATUS(host));
843+ wmb(); /* drain writebuffer */
844844
845845 return IRQ_HANDLED;
846846 }
@@ -976,7 +976,7 @@ static int au1xmmc_probe(struct platform_device *pdev) · 129 unmodified lines
976976 goto out1;
977977 }
978978
979− host->iobase = (unsigned long)ioremap(r->start, 0x3c);
979+ host->iobase = ioremap(r->start, 0x3c);
980980 if (!host->iobase) {
981981 dev_err(&pdev->dev, "cannot remap mmio\n");
982982 goto out2;
@@ -1025,6 +1025,16 @@ static int au1xmmc_probe(struct platform_device *pdev) · 42 unmodified lines
10251025 goto out3;
10261026 }
10271027
1028+ host->clk = clk_get(&pdev->dev, ALCHEMY_PERIPH_CLK);
1029+ if (IS_ERR(host->clk)) {
1030+ dev_err(&pdev->dev, "cannot find clock\n");
1031+ goto out_irq;
1032+ }
1033+ if (clk_prepare_enable(host->clk)) {
1034+ dev_err(&pdev->dev, "cannot enable clock\n");
1035+ goto out_clk;
1036+ }
1037+
10281038 host->status = HOST_S_IDLE;
10291039
10301040 /* board-specific carddetect setup, if any */
@@ -1075,7 +1085,7 @@ static int au1xmmc_probe(struct platform_device *pdev) · 44 unmodified lines
10751085
10761086 platform_set_drvdata(pdev, host);
10771087
1078− pr_info(DRIVER_NAME ": MMC Controller %d set up at %8.8X"
1088+ pr_info(DRIVER_NAME ": MMC Controller %d set up at %p"
10791089 " (mode=%s)\n", pdev->id, host->iobase,
10801090 host->flags & HOST_F_DMA ? "dma" : "pio");
10811091
@@ -1087,10 +1097,10 @@ out6: · 5 unmodified lines
10871097 led_classdev_unregister(host->platdata->led);
10881098 out5:
10891099 #endif
1090− au_writel(0, HOST_ENABLE(host));
1091− au_writel(0, HOST_CONFIG(host));
1092− au_writel(0, HOST_CONFIG2(host));
1093− au_sync();
1100+ __raw_writel(0, HOST_ENABLE(host));
1101+ __raw_writel(0, HOST_CONFIG(host));
1102+ __raw_writel(0, HOST_CONFIG2(host));
1103+ wmb(); /* drain writebuffer */
10941104
10951105 if (host->flags & HOST_F_DBDMA)
10961106 au1xmmc_dbdma_shutdown(host);
@@ -1101,7 +1111,10 @@ out5: · 4 unmodified lines
11011111 if (host->platdata && host->platdata->cd_setup &&
11021112 !(mmc->caps & MMC_CAP_NEEDS_POLL))
11031113 host->platdata->cd_setup(mmc, 0);
1104−
1114+out_clk:
1115+ clk_disable_unprepare(host->clk);
1116+ clk_put(host->clk);
1117+out_irq:
11051118 free_irq(host->irq, host);
11061119 out3:
11071120 iounmap((void *)host->iobase);
@@ -1130,10 +1143,10 @@ static int au1xmmc_remove(struct platform_device *pdev) · 22 unmodified lines
11301143 !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
11311144 host->platdata->cd_setup(host->mmc, 0);
11321145
1133− au_writel(0, HOST_ENABLE(host));
1134− au_writel(0, HOST_CONFIG(host));
1135− au_writel(0, HOST_CONFIG2(host));
1136− au_sync();
1146+ __raw_writel(0, HOST_ENABLE(host));
1147+ __raw_writel(0, HOST_CONFIG(host));
1148+ __raw_writel(0, HOST_CONFIG2(host));
1149+ wmb(); /* drain writebuffer */
11371150
11381151 tasklet_kill(&host->data_task);
11391152 tasklet_kill(&host->finish_task);
@@ -1143,6 +1156,9 @@ static int au1xmmc_remove(struct platform_device *pdev) · 3 unmodified lines
11431156
11441157 au1xmmc_set_power(host, 0);
11451158
1159+ clk_disable_unprepare(host->clk);
1160+ clk_put(host->clk);
1161+
11461162 free_irq(host->irq, host);
11471163 iounmap((void *)host->iobase);
11481164 release_resource(host->ioarea);
@@ -1158,11 +1174,11 @@ static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state) · 9 unmodified lines
11581174 {
11591175 struct au1xmmc_host *host = platform_get_drvdata(pdev);
11601176
1161− au_writel(0, HOST_CONFIG2(host));
1162− au_writel(0, HOST_CONFIG(host));
1163− au_writel(0xffffffff, HOST_STATUS(host));
1164− au_writel(0, HOST_ENABLE(host));
1165− au_sync();
1177+ __raw_writel(0, HOST_CONFIG2(host));
1178+ __raw_writel(0, HOST_CONFIG(host));
1179+ __raw_writel(0xffffffff, HOST_STATUS(host));
1180+ __raw_writel(0, HOST_ENABLE(host));
1181+ wmb(); /* drain writebuffer */
11661182
11671183 return 0;
11681184 }
drivers/mtd/nand/au1550nd.c+13−16
@@ -41,7 +41,7 @@ static u_char au_read_byte(struct mtd_info *mtd) · 40 unmodified lines
4141 {
4242 struct nand_chip *this = mtd->priv;
4343 u_char ret = readb(this->IO_ADDR_R);
44− au_sync();
44+ wmb(); /* drain writebuffer */
4545 return ret;
4646 }
4747
@@ -56,7 +56,7 @@ static void au_write_byte(struct mtd_info *mtd, u_char byte) · 8 unmodified lines
5656 {
5757 struct nand_chip *this = mtd->priv;
5858 writeb(byte, this->IO_ADDR_W);
59− au_sync();
59+ wmb(); /* drain writebuffer */
6060 }
6161
6262 /**
@@ -69,7 +69,7 @@ static u_char au_read_byte16(struct mtd_info *mtd) · 6 unmodified lines
6969 {
7070 struct nand_chip *this = mtd->priv;
7171 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
72− au_sync();
72+ wmb(); /* drain writebuffer */
7373 return ret;
7474 }
7575
@@ -84,7 +84,7 @@ static void au_write_byte16(struct mtd_info *mtd, u_char byte) · 8 unmodified lines
8484 {
8585 struct nand_chip *this = mtd->priv;
8686 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
87− au_sync();
87+ wmb(); /* drain writebuffer */
8888 }
8989
9090 /**
@@ -97,7 +97,7 @@ static u16 au_read_word(struct mtd_info *mtd) · 6 unmodified lines
9797 {
9898 struct nand_chip *this = mtd->priv;
9999 u16 ret = readw(this->IO_ADDR_R);
100− au_sync();
100+ wmb(); /* drain writebuffer */
101101 return ret;
102102 }
103103
@@ -116,7 +116,7 @@ static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len) · 12 unmodified lines
116116
117117 for (i = 0; i < len; i++) {
118118 writeb(buf[i], this->IO_ADDR_W);
119− au_sync();
119+ wmb(); /* drain writebuffer */
120120 }
121121 }
122122
@@ -135,7 +135,7 @@ static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len) · 12 unmodified lines
135135
136136 for (i = 0; i < len; i++) {
137137 buf[i] = readb(this->IO_ADDR_R);
138− au_sync();
138+ wmb(); /* drain writebuffer */
139139 }
140140 }
141141
@@ -156,7 +156,7 @@ static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len) · 14 unmodified lines
156156
157157 for (i = 0; i < len; i++) {
158158 writew(p[i], this->IO_ADDR_W);
159− au_sync();
159+ wmb(); /* drain writebuffer */
160160 }
161161
162162 }
@@ -178,7 +178,7 @@ static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len) · 15 unmodified lines
178178
179179 for (i = 0; i < len; i++) {
180180 p[i] = readw(this->IO_ADDR_R);
181− au_sync();
181+ wmb(); /* drain writebuffer */
182182 }
183183 }
184184
@@ -223,26 +223,23 @@ static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) · 38 unmodified lines
223223
224224 case NAND_CTL_SETNCE:
225225 /* assert (force assert) chip enable */
226− au_writel((1 << (4 + ctx->cs)), MEM_STNDCTL);
226+ alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
227227 break;
228228
229229 case NAND_CTL_CLRNCE:
230230 /* deassert chip enable */
231− au_writel(0, MEM_STNDCTL);
231+ alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
232232 break;
233233 }
234234
235235 this->IO_ADDR_R = this->IO_ADDR_W;
236236
237− /* Drain the writebuffer */
238− au_sync();
237+ wmb(); /* Drain the writebuffer */
239238 }
240239
241240 int au1550_device_ready(struct mtd_info *mtd)
242241 {
243− int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
244− au_sync();
245− return ret;
242+ return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
246243 }
247244
248245 /**
drivers/net/ethernet/amd/au1000_eth.c+137−12
@@ -89,6 +89,124 @@ MODULE_DESCRIPTION(DRV_DESC); · 88 unmodified lines
8989 MODULE_LICENSE("GPL");
9090 MODULE_VERSION(DRV_VERSION);
9191
92+/* AU1000 MAC registers and bits */
93+#define MAC_CONTROL 0x0
94+# define MAC_RX_ENABLE (1 << 2)
95+# define MAC_TX_ENABLE (1 << 3)
96+# define MAC_DEF_CHECK (1 << 5)
97+# define MAC_SET_BL(X) (((X) & 0x3) << 6)
98+# define MAC_AUTO_PAD (1 << 8)
99+# define MAC_DISABLE_RETRY (1 << 10)
100+# define MAC_DISABLE_BCAST (1 << 11)
101+# define MAC_LATE_COL (1 << 12)
102+# define MAC_HASH_MODE (1 << 13)
103+# define MAC_HASH_ONLY (1 << 15)
104+# define MAC_PASS_ALL (1 << 16)
105+# define MAC_INVERSE_FILTER (1 << 17)
106+# define MAC_PROMISCUOUS (1 << 18)
107+# define MAC_PASS_ALL_MULTI (1 << 19)
108+# define MAC_FULL_DUPLEX (1 << 20)
109+# define MAC_NORMAL_MODE 0
110+# define MAC_INT_LOOPBACK (1 << 21)
111+# define MAC_EXT_LOOPBACK (1 << 22)
112+# define MAC_DISABLE_RX_OWN (1 << 23)
113+# define MAC_BIG_ENDIAN (1 << 30)
114+# define MAC_RX_ALL (1 << 31)
115+#define MAC_ADDRESS_HIGH 0x4
116+#define MAC_ADDRESS_LOW 0x8
117+#define MAC_MCAST_HIGH 0xC
118+#define MAC_MCAST_LOW 0x10
119+#define MAC_MII_CNTRL 0x14
120+# define MAC_MII_BUSY (1 << 0)
121+# define MAC_MII_READ 0
122+# define MAC_MII_WRITE (1 << 1)
123+# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
124+# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
125+#define MAC_MII_DATA 0x18
126+#define MAC_FLOW_CNTRL 0x1C
127+# define MAC_FLOW_CNTRL_BUSY (1 << 0)
128+# define MAC_FLOW_CNTRL_ENABLE (1 << 1)
129+# define MAC_PASS_CONTROL (1 << 2)
130+# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
131+#define MAC_VLAN1_TAG 0x20
132+#define MAC_VLAN2_TAG 0x24
133+
134+/* Ethernet Controller Enable */
135+# define MAC_EN_CLOCK_ENABLE (1 << 0)
136+# define MAC_EN_RESET0 (1 << 1)
137+# define MAC_EN_TOSS (0 << 2)
138+# define MAC_EN_CACHEABLE (1 << 3)
139+# define MAC_EN_RESET1 (1 << 4)
140+# define MAC_EN_RESET2 (1 << 5)
141+# define MAC_DMA_RESET (1 << 6)
142+
143+/* Ethernet Controller DMA Channels */
144+/* offsets from MAC_TX_RING_ADDR address */
145+#define MAC_TX_BUFF0_STATUS 0x0
146+# define TX_FRAME_ABORTED (1 << 0)
147+# define TX_JAB_TIMEOUT (1 << 1)
148+# define TX_NO_CARRIER (1 << 2)
149+# define TX_LOSS_CARRIER (1 << 3)
150+# define TX_EXC_DEF (1 << 4)
151+# define TX_LATE_COLL_ABORT (1 << 5)
152+# define TX_EXC_COLL (1 << 6)
153+# define TX_UNDERRUN (1 << 7)
154+# define TX_DEFERRED (1 << 8)
155+# define TX_LATE_COLL (1 << 9)
156+# define TX_COLL_CNT_MASK (0xF << 10)
157+# define TX_PKT_RETRY (1 << 31)
158+#define MAC_TX_BUFF0_ADDR 0x4
159+# define TX_DMA_ENABLE (1 << 0)
160+# define TX_T_DONE (1 << 1)
161+# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
162+#define MAC_TX_BUFF0_LEN 0x8
163+#define MAC_TX_BUFF1_STATUS 0x10
164+#define MAC_TX_BUFF1_ADDR 0x14
165+#define MAC_TX_BUFF1_LEN 0x18
166+#define MAC_TX_BUFF2_STATUS 0x20
167+#define MAC_TX_BUFF2_ADDR 0x24
168+#define MAC_TX_BUFF2_LEN 0x28
169+#define MAC_TX_BUFF3_STATUS 0x30
170+#define MAC_TX_BUFF3_ADDR 0x34
171+#define MAC_TX_BUFF3_LEN 0x38
172+
173+/* offsets from MAC_RX_RING_ADDR */
174+#define MAC_RX_BUFF0_STATUS 0x0
175+# define RX_FRAME_LEN_MASK 0x3fff
176+# define RX_WDOG_TIMER (1 << 14)
177+# define RX_RUNT (1 << 15)
178+# define RX_OVERLEN (1 << 16)
179+# define RX_COLL (1 << 17)
180+# define RX_ETHER (1 << 18)
181+# define RX_MII_ERROR (1 << 19)
182+# define RX_DRIBBLING (1 << 20)
183+# define RX_CRC_ERROR (1 << 21)
184+# define RX_VLAN1 (1 << 22)
185+# define RX_VLAN2 (1 << 23)
186+# define RX_LEN_ERROR (1 << 24)
187+# define RX_CNTRL_FRAME (1 << 25)
188+# define RX_U_CNTRL_FRAME (1 << 26)
189+# define RX_MCAST_FRAME (1 << 27)
190+# define RX_BCAST_FRAME (1 << 28)
191+# define RX_FILTER_FAIL (1 << 29)
192+# define RX_PACKET_FILTER (1 << 30)
193+# define RX_MISSED_FRAME (1 << 31)
194+
195+# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
196+ RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
197+ RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
198+#define MAC_RX_BUFF0_ADDR 0x4
199+# define RX_DMA_ENABLE (1 << 0)
200+# define RX_T_DONE (1 << 1)
201+# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
202+# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
203+#define MAC_RX_BUFF1_STATUS 0x10
204+#define MAC_RX_BUFF1_ADDR 0x14
205+#define MAC_RX_BUFF2_STATUS 0x20
206+#define MAC_RX_BUFF2_ADDR 0x24
207+#define MAC_RX_BUFF3_STATUS 0x30
208+#define MAC_RX_BUFF3_ADDR 0x34
209+
92210 /*
93211 * Theory of operation
94212 *
@@ -152,10 +270,12 @@ static void au1000_enable_mac(struct net_device *dev, int force_reset) · 57 unmodified lines
152270
153271 if (force_reset || (!aup->mac_enabled)) {
154272 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
155− au_sync_delay(2);
273+ wmb(); /* drain writebuffer */
274+ mdelay(2);
156275 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
157276 | MAC_EN_CLOCK_ENABLE), aup->enable);
158− au_sync_delay(2);
277+ wmb(); /* drain writebuffer */
278+ mdelay(2);
159279
160280 aup->mac_enabled = 1;
161281 }
@@ -273,7 +393,8 @@ static void au1000_hard_stop(struct net_device *dev) · 111 unmodified lines
273393 reg = readl(&aup->mac->control);
274394 reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
275395 writel(reg, &aup->mac->control);
276− au_sync_delay(10);
396+ wmb(); /* drain writebuffer */
397+ mdelay(10);
277398 }
278399
279400 static void au1000_enable_rx_tx(struct net_device *dev)
@@ -286,7 +407,8 @@ static void au1000_enable_rx_tx(struct net_device *dev) · 6 unmodified lines
286407 reg = readl(&aup->mac->control);
287408 reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
288409 writel(reg, &aup->mac->control);
289− au_sync_delay(10);
410+ wmb(); /* drain writebuffer */
411+ mdelay(10);
290412 }
291413
292414 static void
@@ -336,7 +458,8 @@ au1000_adjust_link(struct net_device *dev) · 43 unmodified lines
336458 reg |= MAC_DISABLE_RX_OWN;
337459 }
338460 writel(reg, &aup->mac->control);
339− au_sync_delay(1);
461+ wmb(); /* drain writebuffer */
462+ mdelay(1);
340463
341464 au1000_enable_rx_tx(dev);
342465 aup->old_duplex = phydev->duplex;
@@ -500,9 +623,11 @@ static void au1000_reset_mac_unlocked(struct net_device *dev) · 157 unmodified lines
500623 au1000_hard_stop(dev);
501624
502625 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
503− au_sync_delay(2);
626+ wmb(); /* drain writebuffer */
627+ mdelay(2);
504628 writel(0, aup->enable);
505− au_sync_delay(2);
629+ wmb(); /* drain writebuffer */
630+ mdelay(2);
506631
507632 aup->tx_full = 0;
508633 for (i = 0; i < NUM_RX_DMA; i++) {
@@ -652,7 +777,7 @@ static int au1000_init(struct net_device *dev) · 143 unmodified lines
652777 for (i = 0; i < NUM_RX_DMA; i++)
653778 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
654779
655− au_sync();
780+ wmb(); /* drain writebuffer */
656781
657782 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
658783 #ifndef CONFIG_CPU_LITTLE_ENDIAN
@@ -669,7 +794,7 @@ static int au1000_init(struct net_device *dev) · 10 unmodified lines
669794
670795 writel(control, &aup->mac->control);
671796 writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
672− au_sync();
797+ wmb(); /* drain writebuffer */
673798
674799 spin_unlock_irqrestore(&aup->lock, flags);
675800 return 0;
@@ -760,7 +885,7 @@ static int au1000_rx(struct net_device *dev) · 84 unmodified lines
760885 }
761886 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
762887 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
763− au_sync();
888+ wmb(); /* drain writebuffer */
764889
765890 /* next descriptor */
766891 prxd = aup->rx_dma_ring[aup->rx_head];
@@ -808,7 +933,7 @@ static void au1000_tx_ack(struct net_device *dev) · 41 unmodified lines
808933 au1000_update_tx_stats(dev, ptxd->status);
809934 ptxd->buff_stat &= ~TX_T_DONE;
810935 ptxd->len = 0;
811− au_sync();
936+ wmb(); /* drain writebuffer */
812937
813938 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
814939 ptxd = aup->tx_dma_ring[aup->tx_tail];
@@ -939,7 +1064,7 @@ static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev) · 124 unmodified lines
9391064 ps->tx_bytes += ptxd->len;
9401065
9411066 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
942− au_sync();
1067+ wmb(); /* drain writebuffer */
9431068 dev_kfree_skb(skb);
9441069 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
9451070 return NETDEV_TX_OK;
drivers/net/irda/au1k_ir.c+46−2
@@ -18,6 +18,7 @@ · 17 unmodified lines
1818 * with this program; if not, see <http://www.gnu.org/licenses/>.
1919 */
2020
21+#include <linux/clk.h>
2122 #include <linux/module.h>
2223 #include <linux/netdevice.h>
2324 #include <linux/interrupt.h>
@@ -175,6 +176,7 @@ struct au1k_private { · 151 unmodified lines
175176
176177 struct resource *ioarea;
177178 struct au1k_irda_platform_data *platdata;
179+ struct clk *irda_clk;
178180 };
179181
180182 static int qos_mtt_bits = 0x07; /* 1 ms or more */
@@ -514,9 +516,39 @@ static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id) · 333 unmodified lines
514516 static int au1k_init(struct net_device *dev)
515517 {
516518 struct au1k_private *aup = netdev_priv(dev);
517− u32 enable, ring_address;
519+ u32 enable, ring_address, phyck;
520+ struct clk *c;
518521 int i;
519522
523+ c = clk_get(NULL, "irda_clk");
524+ if (IS_ERR(c))
525+ return PTR_ERR(c);
526+ i = clk_prepare_enable(c);
527+ if (i) {
528+ clk_put(c);
529+ return i;
530+ }
531+
532+ switch (clk_get_rate(c)) {
533+ case 40000000:
534+ phyck = IR_PHYCLK_40MHZ;
535+ break;
536+ case 48000000:
537+ phyck = IR_PHYCLK_48MHZ;
538+ break;
539+ case 56000000:
540+ phyck = IR_PHYCLK_56MHZ;
541+ break;
542+ case 64000000:
543+ phyck = IR_PHYCLK_64MHZ;
544+ break;
545+ default:
546+ clk_disable_unprepare(c);
547+ clk_put(c);
548+ return -EINVAL;
549+ }
550+ aup->irda_clk = c;
551+
520552 enable = IR_HC | IR_CE | IR_C;
521553 #ifndef CONFIG_CPU_LITTLE_ENDIAN
522554 enable |= IR_BE;
@@ -545,7 +577,7 @@ static int au1k_init(struct net_device *dev) · 22 unmodified lines
545577 irda_write(aup, IR_RING_SIZE,
546578 (RING_SIZE_64 << 8) | (RING_SIZE_64 << 12));
547579
548− irda_write(aup, IR_CONFIG_2, IR_PHYCLK_48MHZ | IR_ONE_PIN);
580+ irda_write(aup, IR_CONFIG_2, phyck | IR_ONE_PIN);
549581 irda_write(aup, IR_RING_ADDR_CMPR, 0);
550582
551583 au1k_irda_set_speed(dev, 9600);
@@ -619,6 +651,9 @@ static int au1k_irda_stop(struct net_device *dev) · 67 unmodified lines
619651 free_irq(aup->irq_tx, dev);
620652 free_irq(aup->irq_rx, dev);
621653
654+ clk_disable_unprepare(aup->irda_clk);
655+ clk_put(aup->irda_clk);
656+
622657 return 0;
623658 }
624659
@@ -853,6 +888,7 @@ static int au1k_irda_probe(struct platform_device *pdev) · 228 unmodified lines
853888 struct au1k_private *aup;
854889 struct net_device *dev;
855890 struct resource *r;
891+ struct clk *c;
856892 int err;
857893
858894 dev = alloc_irdadev(sizeof(struct au1k_private));
@@ -886,6 +922,14 @@ static int au1k_irda_probe(struct platform_device *pdev) · 27 unmodified lines
886922 if (!aup->ioarea)
887923 goto out;
888924
925+ /* bail out early if clock doesn't exist */
926+ c = clk_get(NULL, "irda_clk");
927+ if (IS_ERR(c)) {
928+ err = PTR_ERR(c);
929+ goto out;
930+ }
931+ clk_put(c);
932+
889933 aup->iobase = ioremap_nocache(r->start, resource_size(r));
890934 if (!aup->iobase)
891935 goto out2;
drivers/rtc/rtc-au1xxx.c+8−10
@@ -32,7 +32,7 @@ static int au1xtoy_rtc_read_time(struct device *dev, struct rtc_time *tm) · 31 unmodified lines
3232 {
3333 unsigned long t;
3434
35− t = au_readl(SYS_TOYREAD);
35+ t = alchemy_rdsys(AU1000_SYS_TOYREAD);
3636
3737 rtc_time_to_tm(t, tm);
3838
@@ -45,13 +45,12 @@ static int au1xtoy_rtc_set_time(struct device *dev, struct rtc_time *tm) · 6 unmodified lines
4545
4646 rtc_tm_to_time(tm, &t);
4747
48− au_writel(t, SYS_TOYWRITE);
49− au_sync();
48+ alchemy_wrsys(t, AU1000_SYS_TOYWRITE);
5049
5150 /* wait for the pending register write to succeed. This can
5251 * take up to 6 seconds...
5352 */
54− while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S)
53+ while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S)
5554 msleep(1);
5655
5756 return 0;
@@ -68,7 +67,7 @@ static int au1xtoy_rtc_probe(struct platform_device *pdev) · 10 unmodified lines
6867 unsigned long t;
6968 int ret;
7069
71− t = au_readl(SYS_COUNTER_CNTRL);
70+ t = alchemy_rdsys(AU1000_SYS_CNTRCTRL);
7271 if (!(t & CNTR_OK)) {
7372 dev_err(&pdev->dev, "counters not working; aborting.\n");
7473 ret = -ENODEV;
@@ -78,10 +77,10 @@ static int au1xtoy_rtc_probe(struct platform_device *pdev) · 3 unmodified lines
7877 ret = -ETIMEDOUT;
7978
8079 /* set counter0 tickrate to 1Hz if necessary */
81− if (au_readl(SYS_TOYTRIM) != 32767) {
80+ if (alchemy_rdsys(AU1000_SYS_TOYTRIM) != 32767) {
8281 /* wait until hardware gives access to TRIM register */
8382 t = 0x00100000;
84− while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S) && --t)
83+ while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T0S) && --t)
8584 msleep(1);
8685
8786 if (!t) {
@@ -93,12 +92,11 @@ static int au1xtoy_rtc_probe(struct platform_device *pdev) · 5 unmodified lines
9392 }
9493
9594 /* set 1Hz TOY tick rate */
96− au_writel(32767, SYS_TOYTRIM);
97− au_sync();
95+ alchemy_wrsys(32767, AU1000_SYS_TOYTRIM);
9896 }
9997
10098 /* wait until the hardware allows writes to the counter reg */
101− while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S)
99+ while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S)
102100 msleep(1);
103101
104102 rtcdev = devm_rtc_device_register(&pdev->dev, "rtc-au1xxx",
drivers/spi/spi-au1550.c+33−33
@@ -141,13 +141,13 @@ static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw) · 140 unmodified lines
141141 PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
142142 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
143143 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
144− au_sync();
144+ wmb(); /* drain writebuffer */
145145
146146 hw->regs->psc_spievent =
147147 PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
148148 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
149149 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
150− au_sync();
150+ wmb(); /* drain writebuffer */
151151 }
152152
153153 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
@@ -155,10 +155,10 @@ static void au1550_spi_reset_fifos(struct au1550_spi *hw) · 1 unmodified line
155155 u32 pcr;
156156
157157 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
158− au_sync();
158+ wmb(); /* drain writebuffer */
159159 do {
160160 pcr = hw->regs->psc_spipcr;
161− au_sync();
161+ wmb(); /* drain writebuffer */
162162 } while (pcr != 0);
163163 }
164164
@@ -188,9 +188,9 @@ static void au1550_spi_chipsel(struct spi_device *spi, int value) · 23 unmodified lines
188188 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
189189
190190 cfg = hw->regs->psc_spicfg;
191− au_sync();
191+ wmb(); /* drain writebuffer */
192192 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
193− au_sync();
193+ wmb(); /* drain writebuffer */
194194
195195 if (spi->mode & SPI_CPOL)
196196 cfg |= PSC_SPICFG_BI;
@@ -218,10 +218,10 @@ static void au1550_spi_chipsel(struct spi_device *spi, int value) · 21 unmodified lines
218218 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
219219
220220 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
221− au_sync();
221+ wmb(); /* drain writebuffer */
222222 do {
223223 stat = hw->regs->psc_spistat;
224− au_sync();
224+ wmb(); /* drain writebuffer */
225225 } while ((stat & PSC_SPISTAT_DR) == 0);
226226
227227 if (hw->pdata->activate_cs)
@@ -252,9 +252,9 @@ static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t) · 24 unmodified lines
252252 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
253253
254254 cfg = hw->regs->psc_spicfg;
255− au_sync();
255+ wmb(); /* drain writebuffer */
256256 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
257− au_sync();
257+ wmb(); /* drain writebuffer */
258258
259259 if (hw->usedma && bpw <= 8)
260260 cfg &= ~PSC_SPICFG_DD_DISABLE;
@@ -268,12 +268,12 @@ static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t) · 7 unmodified lines
268268 cfg |= au1550_spi_baudcfg(hw, hz);
269269
270270 hw->regs->psc_spicfg = cfg;
271− au_sync();
271+ wmb(); /* drain writebuffer */
272272
273273 if (cfg & PSC_SPICFG_DE_ENABLE) {
274274 do {
275275 stat = hw->regs->psc_spistat;
276− au_sync();
276+ wmb(); /* drain writebuffer */
277277 } while ((stat & PSC_SPISTAT_DR) == 0);
278278 }
279279
@@ -396,11 +396,11 @@ static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t) · 116 unmodified lines
396396
397397 /* by default enable nearly all events interrupt */
398398 hw->regs->psc_spimsk = PSC_SPIMSK_SD;
399− au_sync();
399+ wmb(); /* drain writebuffer */
400400
401401 /* start the transfer */
402402 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
403− au_sync();
403+ wmb(); /* drain writebuffer */
404404
405405 wait_for_completion(&hw->master_done);
406406
@@ -429,7 +429,7 @@ static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw) · 22 unmodified lines
429429
430430 stat = hw->regs->psc_spistat;
431431 evnt = hw->regs->psc_spievent;
432− au_sync();
432+ wmb(); /* drain writebuffer */
433433 if ((stat & PSC_SPISTAT_DI) == 0) {
434434 dev_err(hw->dev, "Unexpected IRQ!\n");
435435 return IRQ_NONE;
@@ -484,7 +484,7 @@ static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw) · 48 unmodified lines
484484 static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
485485 { \
486486 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
487− au_sync(); \
487+ wmb(); /* drain writebuffer */ \
488488 if (hw->rx) { \
489489 *(u##size *)hw->rx = (u##size)fifoword; \
490490 hw->rx += (size) / 8; \
@@ -504,7 +504,7 @@ static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \ · 13 unmodified lines
504504 if (hw->tx_count >= hw->len) \
505505 fifoword |= PSC_SPITXRX_LC; \
506506 hw->regs->psc_spitxrx = fifoword; \
507− au_sync(); \
507+ wmb(); /* drain writebuffer */ \
508508 }
509509
510510 AU1550_SPI_RX_WORD(8,0xff)
@@ -539,18 +539,18 @@ static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t) · 28 unmodified lines
539539 }
540540
541541 stat = hw->regs->psc_spistat;
542− au_sync();
542+ wmb(); /* drain writebuffer */
543543 if (stat & PSC_SPISTAT_TF)
544544 break;
545545 }
546546
547547 /* enable event interrupts */
548548 hw->regs->psc_spimsk = mask;
549− au_sync();
549+ wmb(); /* drain writebuffer */
550550
551551 /* start the transfer */
552552 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
553− au_sync();
553+ wmb(); /* drain writebuffer */
554554
555555 wait_for_completion(&hw->master_done);
556556
@@ -564,7 +564,7 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) · 7 unmodified lines
564564
565565 stat = hw->regs->psc_spistat;
566566 evnt = hw->regs->psc_spievent;
567− au_sync();
567+ wmb(); /* drain writebuffer */
568568 if ((stat & PSC_SPISTAT_DI) == 0) {
569569 dev_err(hw->dev, "Unexpected IRQ!\n");
570570 return IRQ_NONE;
@@ -594,7 +594,7 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) · 23 unmodified lines
594594 do {
595595 busy = 0;
596596 stat = hw->regs->psc_spistat;
597− au_sync();
597+ wmb(); /* drain writebuffer */
598598
599599 /*
600600 * Take care to not let the Rx FIFO overflow.
@@ -615,7 +615,7 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) · 14 unmodified lines
615615 } while (busy);
616616
617617 hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
618− au_sync();
618+ wmb(); /* drain writebuffer */
619619
620620 /*
621621 * Restart the SPI transmission in case of a transmit underflow.
@@ -634,9 +634,9 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) · 12 unmodified lines
634634 */
635635 if (evnt & PSC_SPIEVNT_TU) {
636636 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
637− au_sync();
637+ wmb(); /* drain writebuffer */
638638 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
639− au_sync();
639+ wmb(); /* drain writebuffer */
640640 }
641641
642642 if (hw->rx_count >= hw->len) {
@@ -690,19 +690,19 @@ static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw) · 47 unmodified lines
690690
691691 /* set up the PSC for SPI mode */
692692 hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
693− au_sync();
693+ wmb(); /* drain writebuffer */
694694 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
695− au_sync();
695+ wmb(); /* drain writebuffer */
696696
697697 hw->regs->psc_spicfg = 0;
698− au_sync();
698+ wmb(); /* drain writebuffer */
699699
700700 hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
701− au_sync();
701+ wmb(); /* drain writebuffer */
702702
703703 do {
704704 stat = hw->regs->psc_spistat;
705− au_sync();
705+ wmb(); /* drain writebuffer */
706706 } while ((stat & PSC_SPISTAT_SR) == 0);
707707
708708
@@ -717,16 +717,16 @@ static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw) · 8 unmodified lines
717717 #endif
718718
719719 hw->regs->psc_spicfg = cfg;
720− au_sync();
720+ wmb(); /* drain writebuffer */
721721
722722 au1550_spi_mask_ack_all(hw);
723723
724724 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
725− au_sync();
725+ wmb(); /* drain writebuffer */
726726
727727 do {
728728 stat = hw->regs->psc_spistat;
729− au_sync();
729+ wmb(); /* drain writebuffer */
730730 } while ((stat & PSC_SPISTAT_DR) == 0);
731731
732732 au1550_spi_reset_fifos(hw);
drivers/video/fbdev/au1100fb.c+24−15
@@ -41,6 +41,7 @@ · 40 unmodified lines
4141 * with this program; if not, write to the Free Software Foundation, Inc.,
4242 * 675 Mass Ave, Cambridge, MA 02139, USA.
4343 */
44+#include <linux/clk.h>
4445 #include <linux/module.h>
4546 #include <linux/kernel.h>
4647 #include <linux/errno.h>
@@ -113,7 +114,7 @@ static int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi) · 66 unmodified lines
113114 case VESA_NO_BLANKING:
114115 /* Turn on panel */
115116 fbdev->regs->lcd_control |= LCD_CONTROL_GO;
116− au_sync();
117+ wmb(); /* drain writebuffer */
117118 break;
118119
119120 case VESA_VSYNC_SUSPEND:
@@ -121,7 +122,7 @@ static int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi) · 1 unmodified line
121122 case VESA_POWERDOWN:
122123 /* Turn off panel */
123124 fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
124− au_sync();
125+ wmb(); /* drain writebuffer */
125126 break;
126127 default:
127128 break;
@@ -434,7 +435,7 @@ static int au1100fb_drv_probe(struct platform_device *dev) · 306 unmodified lines
434435 struct au1100fb_device *fbdev = NULL;
435436 struct resource *regs_res;
436437 unsigned long page;
437− u32 sys_clksrc;
438+ struct clk *c;
438439
439440 /* Allocate new device private */
440441 fbdev = devm_kzalloc(&dev->dev, sizeof(struct au1100fb_device),
@@ -473,6 +474,13 @@ static int au1100fb_drv_probe(struct platform_device *dev) · 32 unmodified lines
473474 print_dbg("Register memory map at %p", fbdev->regs);
474475 print_dbg("phys=0x%08x, size=%d", fbdev->regs_phys, fbdev->regs_len);
475476
477+ c = clk_get(NULL, "lcd_intclk");
478+ if (!IS_ERR(c)) {
479+ fbdev->lcdclk = c;
480+ clk_set_rate(c, 48000000);
481+ clk_prepare_enable(c);
482+ }
483+
476484 /* Allocate the framebuffer to the maximum screen size * nbr of video buffers */
477485 fbdev->fb_len = fbdev->panel->xres * fbdev->panel->yres *
478486 (fbdev->panel->bpp >> 3) * AU1100FB_NBR_VIDEO_BUFFERS;
@@ -506,10 +514,6 @@ static int au1100fb_drv_probe(struct platform_device *dev) · 27 unmodified lines
506514 print_dbg("Framebuffer memory map at %p", fbdev->fb_mem);
507515 print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024);
508516
509− /* Setup LCD clock to AUX (48 MHz) */
510− sys_clksrc = au_readl(SYS_CLKSRC) & ~(SYS_CS_ML_MASK | SYS_CS_DL | SYS_CS_CL);
511− au_writel((sys_clksrc | (1 << SYS_CS_ML_BIT)), SYS_CLKSRC);
512−
513517 /* load the panel info into the var struct */
514518 au1100fb_var.bits_per_pixel = fbdev->panel->bpp;
515519 au1100fb_var.xres = fbdev->panel->xres;
@@ -546,6 +550,10 @@ static int au1100fb_drv_probe(struct platform_device *dev) · 30 unmodified lines
546550 return 0;
547551
548552 failed:
553+ if (fbdev->lcdclk) {
554+ clk_disable_unprepare(fbdev->lcdclk);
555+ clk_put(fbdev->lcdclk);
556+ }
549557 if (fbdev->fb_mem) {
550558 dma_free_noncoherent(&dev->dev, fbdev->fb_len, fbdev->fb_mem,
551559 fbdev->fb_phys);
@@ -576,11 +584,15 @@ int au1100fb_drv_remove(struct platform_device *dev) · 24 unmodified lines
576584
577585 fb_dealloc_cmap(&fbdev->info.cmap);
578586
587+ if (fbdev->lcdclk) {
588+ clk_disable_unprepare(fbdev->lcdclk);
589+ clk_put(fbdev->lcdclk);
590+ }
591+
579592 return 0;
580593 }
581594
582595 #ifdef CONFIG_PM
583−static u32 sys_clksrc;
584596 static struct au1100fb_regs fbregs;
585597
586598 int au1100fb_drv_suspend(struct platform_device *dev, pm_message_t state)
@@ -590,14 +602,11 @@ int au1100fb_drv_suspend(struct platform_device *dev, pm_message_t state) · 3 unmodified lines
590602 if (!fbdev)
591603 return 0;
592604
593− /* Save the clock source state */
594− sys_clksrc = au_readl(SYS_CLKSRC);
595−
596605 /* Blank the LCD */
597606 au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info);
598607
599− /* Stop LCD clocking */
600− au_writel(sys_clksrc & ~SYS_CS_ML_MASK, SYS_CLKSRC);
608+ if (fbdev->lcdclk)
609+ clk_disable(fbdev->lcdclk);
601610
602611 memcpy(&fbregs, fbdev->regs, sizeof(struct au1100fb_regs));
603612
@@ -613,8 +622,8 @@ int au1100fb_drv_resume(struct platform_device *dev) · 9 unmodified lines
613622
614623 memcpy(fbdev->regs, &fbregs, sizeof(struct au1100fb_regs));
615624
616− /* Restart LCD clocking */
617− au_writel(sys_clksrc, SYS_CLKSRC);
625+ if (fbdev->lcdclk)
626+ clk_enable(fbdev->lcdclk);
618627
619628 /* Unblank the LCD */
620629 au1100fb_fb_blank(VESA_NO_BLANKING, &fbdev->info);
drivers/video/fbdev/au1100fb.h+1−0
@@ -109,6 +109,7 @@ struct au1100fb_device { · 108 unmodified lines
109109 size_t fb_len;
110110 dma_addr_t fb_phys;
111111 int panel_idx;
112+ struct clk *lcdclk;
112113 };
113114
114115 /********************************************************************/
drivers/video/fbdev/au1200fb.c+38−43
@@ -30,6 +30,7 @@ · 29 unmodified lines
3030 * 675 Mass Ave, Cambridge, MA 02139, USA.
3131 */
3232
33+#include <linux/clk.h>
3334 #include <linux/module.h>
3435 #include <linux/platform_device.h>
3536 #include <linux/kernel.h>
@@ -330,9 +331,8 @@ struct panel_settings · 294 unmodified lines
330331 uint32 mode_pwmhi;
331332 uint32 mode_outmask;
332333 uint32 mode_fifoctrl;
333− uint32 mode_toyclksrc;
334334 uint32 mode_backlight;
335− uint32 mode_auxpll;
335+ uint32 lcdclk;
336336 #define Xres min_xres
337337 #define Yres min_yres
338338 u32 min_xres; /* Minimum horizontal resolution */
@@ -379,9 +379,8 @@ static struct panel_settings known_lcd_panels[] = · 40 unmodified lines
379379 .mode_pwmhi = 0x00000000,
380380 .mode_outmask = 0x00FFFFFF,
381381 .mode_fifoctrl = 0x2f2f2f2f,
382− .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
383382 .mode_backlight = 0x00000000,
384− .mode_auxpll = 8, /* 96MHz AUXPLL */
383+ .lcdclk = 96,
385384 320, 320,
386385 240, 240,
387386 },
@@ -407,9 +406,8 @@ static struct panel_settings known_lcd_panels[] = · 19 unmodified lines
407406 .mode_pwmhi = 0x00000000,
408407 .mode_outmask = 0x00FFFFFF,
409408 .mode_fifoctrl = 0x2f2f2f2f,
410− .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
411409 .mode_backlight = 0x00000000,
412− .mode_auxpll = 8, /* 96MHz AUXPLL */
410+ .lcdclk = 96,
413411 640, 480,
414412 640, 480,
415413 },
@@ -435,9 +433,8 @@ static struct panel_settings known_lcd_panels[] = · 19 unmodified lines
435433 .mode_pwmhi = 0x00000000,
436434 .mode_outmask = 0x00FFFFFF,
437435 .mode_fifoctrl = 0x2f2f2f2f,
438− .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
439436 .mode_backlight = 0x00000000,
440− .mode_auxpll = 8, /* 96MHz AUXPLL */
437+ .lcdclk = 96,
441438 800, 800,
442439 600, 600,
443440 },
@@ -463,9 +460,8 @@ static struct panel_settings known_lcd_panels[] = · 19 unmodified lines
463460 .mode_pwmhi = 0x00000000,
464461 .mode_outmask = 0x00FFFFFF,
465462 .mode_fifoctrl = 0x2f2f2f2f,
466− .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
467463 .mode_backlight = 0x00000000,
468− .mode_auxpll = 6, /* 72MHz AUXPLL */
464+ .lcdclk = 72,
469465 1024, 1024,
470466 768, 768,
471467 },
@@ -491,9 +487,8 @@ static struct panel_settings known_lcd_panels[] = · 19 unmodified lines
491487 .mode_pwmhi = 0x00000000,
492488 .mode_outmask = 0x00FFFFFF,
493489 .mode_fifoctrl = 0x2f2f2f2f,
494− .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
495490 .mode_backlight = 0x00000000,
496− .mode_auxpll = 10, /* 120MHz AUXPLL */
491+ .lcdclk = 120,
497492 1280, 1280,
498493 1024, 1024,
499494 },
@@ -519,9 +514,8 @@ static struct panel_settings known_lcd_panels[] = · 19 unmodified lines
519514 .mode_pwmhi = 0x03400000, /* SCB 0x0 */
520515 .mode_outmask = 0x00FFFFFF,
521516 .mode_fifoctrl = 0x2f2f2f2f,
522− .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
523517 .mode_backlight = 0x00000000,
524− .mode_auxpll = 8, /* 96MHz AUXPLL */
518+ .lcdclk = 96,
525519 1024, 1024,
526520 768, 768,
527521 },
@@ -550,9 +544,8 @@ static struct panel_settings known_lcd_panels[] = · 22 unmodified lines
550544 .mode_pwmhi = 0x03400000,
551545 .mode_outmask = 0x00fcfcfc,
552546 .mode_fifoctrl = 0x2f2f2f2f,
553− .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
554547 .mode_backlight = 0x00000000,
555− .mode_auxpll = 8, /* 96MHz AUXPLL */
548+ .lcdclk = 96,
556549 640, 480,
557550 640, 480,
558551 },
@@ -581,9 +574,8 @@ static struct panel_settings known_lcd_panels[] = · 22 unmodified lines
581574 .mode_pwmhi = 0x03400000,
582575 .mode_outmask = 0x00fcfcfc,
583576 .mode_fifoctrl = 0x2f2f2f2f,
584− .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
585577 .mode_backlight = 0x00000000,
586− .mode_auxpll = 8, /* 96MHz AUXPLL */
578+ .lcdclk = 96, /* 96MHz AUXPLL */
587579 320, 320,
588580 240, 240,
589581 },
@@ -612,9 +604,8 @@ static struct panel_settings known_lcd_panels[] = · 22 unmodified lines
612604 .mode_pwmhi = 0x03400000,
613605 .mode_outmask = 0x00fcfcfc,
614606 .mode_fifoctrl = 0x2f2f2f2f,
615− .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
616607 .mode_backlight = 0x00000000,
617− .mode_auxpll = 8, /* 96MHz AUXPLL */
608+ .lcdclk = 96,
618609 856, 856,
619610 480, 480,
620611 },
@@ -646,9 +637,8 @@ static struct panel_settings known_lcd_panels[] = · 25 unmodified lines
646637 .mode_pwmhi = 0x00000000,
647638 .mode_outmask = 0x00FFFFFF,
648639 .mode_fifoctrl = 0x2f2f2f2f,
649− .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
650640 .mode_backlight = 0x00000000,
651− .mode_auxpll = (48/12) * 2,
641+ .lcdclk = 96,
652642 800, 800,
653643 480, 480,
654644 },
@@ -764,7 +754,7 @@ static int au1200_setlocation (struct au1200fb_device *fbdev, int plane, · 109 unmodified lines
764754
765755 /* Disable the window while making changes, then restore WINEN */
766756 winenable = lcd->winenable & (1 << plane);
767− au_sync();
757+ wmb(); /* drain writebuffer */
768758 lcd->winenable &= ~(1 << plane);
769759 lcd->window[plane].winctrl0 = winctrl0;
770760 lcd->window[plane].winctrl1 = winctrl1;
@@ -772,7 +762,7 @@ static int au1200_setlocation (struct au1200fb_device *fbdev, int plane, · 1 unmodified line
772762 lcd->window[plane].winbuf1 = fbdev->fb_phys;
773763 lcd->window[plane].winbufctrl = 0; /* select winbuf0 */
774764 lcd->winenable |= winenable;
775− au_sync();
765+ wmb(); /* drain writebuffer */
776766
777767 return 0;
778768 }
@@ -788,22 +778,21 @@ static void au1200_setpanel(struct panel_settings *newpanel, · 9 unmodified lines
788778 /* Make sure all windows disabled */
789779 winenable = lcd->winenable;
790780 lcd->winenable = 0;
791− au_sync();
781+ wmb(); /* drain writebuffer */
792782 /*
793783 * Ensure everything is disabled before reconfiguring
794784 */
795785 if (lcd->screen & LCD_SCREEN_SEN) {
796786 /* Wait for vertical sync period */
797787 lcd->intstatus = LCD_INT_SS;
798− while ((lcd->intstatus & LCD_INT_SS) == 0) {
799− au_sync();
800− }
788+ while ((lcd->intstatus & LCD_INT_SS) == 0)
789+ ;
801790
802791 lcd->screen &= ~LCD_SCREEN_SEN; /*disable the controller*/
803792
804793 do {
805794 lcd->intstatus = lcd->intstatus; /*clear interrupts*/
806− au_sync();
795+ wmb(); /* drain writebuffer */
807796 /*wait for controller to shut down*/
808797 } while ((lcd->intstatus & LCD_INT_SD) == 0);
809798
@@ -829,11 +818,17 @@ static void au1200_setpanel(struct panel_settings *newpanel, · 19 unmodified lines
829818 */
830819 if (!(panel->mode_clkcontrol & LCD_CLKCONTROL_EXT))
831820 {
832− uint32 sys_clksrc;
833− au_writel(panel->mode_auxpll, SYS_AUXPLL);
834− sys_clksrc = au_readl(SYS_CLKSRC) & ~0x0000001f;
835− sys_clksrc |= panel->mode_toyclksrc;
836− au_writel(sys_clksrc, SYS_CLKSRC);
821+ struct clk *c = clk_get(NULL, "lcd_intclk");
822+ long r, pc = panel->lcdclk * 1000000;
823+
824+ if (!IS_ERR(c)) {
825+ r = clk_round_rate(c, pc);
826+ if ((pc - r) < (pc / 10)) { /* 10% slack */
827+ clk_set_rate(c, r);
828+ clk_prepare_enable(c);
829+ }
830+ clk_put(c);
831+ }
837832 }
838833
839834 /*
@@ -847,7 +842,7 @@ static void au1200_setpanel(struct panel_settings *newpanel, · 7 unmodified lines
847842 lcd->pwmhi = panel->mode_pwmhi;
848843 lcd->outmask = panel->mode_outmask;
849844 lcd->fifoctrl = panel->mode_fifoctrl;
850− au_sync();
845+ wmb(); /* drain writebuffer */
851846
852847 /* fixme: Check window settings to make sure still valid
853848 * for new geometry */
@@ -863,7 +858,7 @@ static void au1200_setpanel(struct panel_settings *newpanel, · 9 unmodified lines
863858 * Re-enable screen now that it is configured
864859 */
865860 lcd->screen |= LCD_SCREEN_SEN;
866− au_sync();
861+ wmb(); /* drain writebuffer */
867862
868863 /* Call init of panel */
869864 if (pd->panel_init)
@@ -956,7 +951,7 @@ static void au1200_setmode(struct au1200fb_device *fbdev) · 86 unmodified lines
956951 | LCD_WINCTRL2_SCY_1
957952 ) ;
958953 lcd->winenable |= win->w[plane].mode_winenable;
959− au_sync();
954+ wmb(); /* drain writebuffer */
960955 }
961956
962957
@@ -1270,7 +1265,7 @@ static void set_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata) · 307 unmodified lines
12701265
12711266 if (pdata->flags & SCREEN_MASK)
12721267 lcd->colorkeymsk = pdata->mask;
1273− au_sync();
1268+ wmb(); /* drain writebuffer */
12741269 }
12751270
12761271 static void get_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata)
@@ -1288,7 +1283,7 @@ static void get_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata) · 11 unmodified lines
12881283 hi1 = (lcd->pwmhi >> 16) + 1;
12891284 divider = (lcd->pwmdiv & 0x3FFFF) + 1;
12901285 pdata->brightness = ((hi1 << 8) / divider) - 1;
1291− au_sync();
1286+ wmb(); /* drain writebuffer */
12921287 }
12931288
12941289 static void set_window(unsigned int plane,
@@ -1387,7 +1382,7 @@ static void set_window(unsigned int plane, · 92 unmodified lines
13871382 val |= (pdata->enable & 1) << plane;
13881383 lcd->winenable = val;
13891384 }
1390− au_sync();
1385+ wmb(); /* drain writebuffer */
13911386 }
13921387
13931388 static void get_window(unsigned int plane,
@@ -1414,7 +1409,7 @@ static void get_window(unsigned int plane, · 20 unmodified lines
14141409 pdata->ram_array_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_RAM) >> 21;
14151410
14161411 pdata->enable = (lcd->winenable >> plane) & 1;
1417− au_sync();
1412+ wmb(); /* drain writebuffer */
14181413 }
14191414
14201415 static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd,
@@ -1511,7 +1506,7 @@ static irqreturn_t au1200fb_handle_irq(int irq, void* dev_id) · 90 unmodified lines
15111506 {
15121507 /* Nothing to do for now, just clear any pending interrupt */
15131508 lcd->intstatus = lcd->intstatus;
1514− au_sync();
1509+ wmb(); /* drain writebuffer */
15151510
15161511 return IRQ_HANDLED;
15171512 }
@@ -1809,7 +1804,7 @@ static int au1200fb_drv_suspend(struct device *dev) · 291 unmodified lines
18091804 au1200_setpanel(NULL, pd);
18101805
18111806 lcd->outmask = 0;
1812− au_sync();
1807+ wmb(); /* drain writebuffer */
18131808
18141809 return 0;
18151810 }
drivers/watchdog/octeon-wdt-main.c+34−28
@@ -145,35 +145,39 @@ static void __init octeon_wdt_build_stage1(void) · 144 unmodified lines
145145
146146 uasm_i_mfc0(&p, K0, C0_STATUS);
147147 #ifdef CONFIG_HOTPLUG_CPU
148− uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI), label_enter_bootloader);
148+ if (octeon_bootloader_entry_addr)
149+ uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI),
150+ label_enter_bootloader);
149151 #endif
150152 /* Force 64-bit addressing enabled */
151153 uasm_i_ori(&p, K0, K0, ST0_UX | ST0_SX | ST0_KX);
152154 uasm_i_mtc0(&p, K0, C0_STATUS);
153155
154156 #ifdef CONFIG_HOTPLUG_CPU
155− uasm_i_mfc0(&p, K0, C0_EBASE);
156− /* Coreid number in K0 */
157− uasm_i_andi(&p, K0, K0, 0xf);
158− /* 8 * coreid in bits 16-31 */
159− uasm_i_dsll_safe(&p, K0, K0, 3 + 16);
160− uasm_i_ori(&p, K0, K0, 0x8001);
161− uasm_i_dsll_safe(&p, K0, K0, 16);
162− uasm_i_ori(&p, K0, K0, 0x0700);
163− uasm_i_drotr_safe(&p, K0, K0, 32);
164− /*
165− * Should result in: 0x8001,0700,0000,8*coreid which is
166− * CVMX_CIU_WDOGX(coreid) - 0x0500
167− *
168− * Now ld K0, CVMX_CIU_WDOGX(coreid)
169− */
170− uasm_i_ld(&p, K0, 0x500, K0);
171− /*
172− * If bit one set handle the NMI as a watchdog event.
173− * otherwise transfer control to bootloader.
174− */
175− uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader);
176− uasm_i_nop(&p);
157+ if (octeon_bootloader_entry_addr) {
158+ uasm_i_mfc0(&p, K0, C0_EBASE);
159+ /* Coreid number in K0 */
160+ uasm_i_andi(&p, K0, K0, 0xf);
161+ /* 8 * coreid in bits 16-31 */
162+ uasm_i_dsll_safe(&p, K0, K0, 3 + 16);
163+ uasm_i_ori(&p, K0, K0, 0x8001);
164+ uasm_i_dsll_safe(&p, K0, K0, 16);
165+ uasm_i_ori(&p, K0, K0, 0x0700);
166+ uasm_i_drotr_safe(&p, K0, K0, 32);
167+ /*
168+ * Should result in: 0x8001,0700,0000,8*coreid which is
169+ * CVMX_CIU_WDOGX(coreid) - 0x0500
170+ *
171+ * Now ld K0, CVMX_CIU_WDOGX(coreid)
172+ */
173+ uasm_i_ld(&p, K0, 0x500, K0);
174+ /*
175+ * If bit one set handle the NMI as a watchdog event.
176+ * otherwise transfer control to bootloader.
177+ */
178+ uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader);
179+ uasm_i_nop(&p);
180+ }
177181 #endif
178182
179183 /* Clear Dcache so cvmseg works right. */
@@ -194,11 +198,13 @@ static void __init octeon_wdt_build_stage1(void) · 14 unmodified lines
194198 uasm_i_dmfc0(&p, K0, C0_DESAVE);
195199
196200 #ifdef CONFIG_HOTPLUG_CPU
197− uasm_build_label(&l, p, label_enter_bootloader);
198− /* Jump to the bootloader and restore K0 */
199− UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr);
200− uasm_i_jr(&p, K0);
201− uasm_i_dmfc0(&p, K0, C0_DESAVE);
201+ if (octeon_bootloader_entry_addr) {
202+ uasm_build_label(&l, p, label_enter_bootloader);
203+ /* Jump to the bootloader and restore K0 */
204+ UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr);
205+ uasm_i_jr(&p, K0);
206+ uasm_i_dmfc0(&p, K0, C0_DESAVE);
207+ }
202208 #endif
203209 uasm_resolve_relocs(relocs, labels);
204210
sound/soc/au1x/psc-ac97.c+70−70
@@ -79,28 +79,28 @@ static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97, · 78 unmodified lines
7979 unsigned short retry, tmo;
8080 unsigned long data;
8181
82− au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
83− au_sync();
82+ __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
83+ wmb(); /* drain writebuffer */
8484
8585 retry = AC97_RW_RETRIES;
8686 do {
8787 mutex_lock(&pscdata->lock);
8888
89− au_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
89+ __raw_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
9090 AC97_CDC(pscdata));
91− au_sync();
91+ wmb(); /* drain writebuffer */
9292
9393 tmo = 20;
9494 do {
9595 udelay(21);
96− if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
96+ if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
9797 break;
9898 } while (--tmo);
9999
100− data = au_readl(AC97_CDC(pscdata));
100+ data = __raw_readl(AC97_CDC(pscdata));
101101
102− au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
103− au_sync();
102+ __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
103+ wmb(); /* drain writebuffer */
104104
105105 mutex_unlock(&pscdata->lock);
106106
@@ -119,26 +119,26 @@ static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg, · 12 unmodified lines
119119 struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
120120 unsigned int tmo, retry;
121121
122− au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
123− au_sync();
122+ __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
123+ wmb(); /* drain writebuffer */
124124
125125 retry = AC97_RW_RETRIES;
126126 do {
127127 mutex_lock(&pscdata->lock);
128128
129− au_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
129+ __raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
130130 AC97_CDC(pscdata));
131− au_sync();
131+ wmb(); /* drain writebuffer */
132132
133133 tmo = 20;
134134 do {
135135 udelay(21);
136− if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
136+ if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
137137 break;
138138 } while (--tmo);
139139
140− au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
141− au_sync();
140+ __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
141+ wmb(); /* drain writebuffer */
142142
143143 mutex_unlock(&pscdata->lock);
144144 } while (--retry && !tmo);
@@ -149,11 +149,11 @@ static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97) · 4 unmodified lines
149149 {
150150 struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
151151
152− au_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
153− au_sync();
152+ __raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
153+ wmb(); /* drain writebuffer */
154154 msleep(10);
155− au_writel(0, AC97_RST(pscdata));
156− au_sync();
155+ __raw_writel(0, AC97_RST(pscdata));
156+ wmb(); /* drain writebuffer */
157157 }
158158
159159 static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
@@ -162,25 +162,25 @@ static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97) · 2 unmodified lines
162162 int i;
163163
164164 /* disable PSC during cold reset */
165− au_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
166− au_sync();
167− au_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
168− au_sync();
165+ __raw_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
166+ wmb(); /* drain writebuffer */
167+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
168+ wmb(); /* drain writebuffer */
169169
170170 /* issue cold reset */
171− au_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
172− au_sync();
171+ __raw_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
172+ wmb(); /* drain writebuffer */
173173 msleep(500);
174− au_writel(0, AC97_RST(pscdata));
175− au_sync();
174+ __raw_writel(0, AC97_RST(pscdata));
175+ wmb(); /* drain writebuffer */
176176
177177 /* enable PSC */
178− au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
179− au_sync();
178+ __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
179+ wmb(); /* drain writebuffer */
180180
181181 /* wait for PSC to indicate it's ready */
182182 i = 1000;
183− while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
183+ while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
184184 msleep(1);
185185
186186 if (i == 0) {
@@ -189,12 +189,12 @@ static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97) · 2 unmodified lines
189189 }
190190
191191 /* enable the ac97 function */
192− au_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
193− au_sync();
192+ __raw_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
193+ wmb(); /* drain writebuffer */
194194
195195 /* wait for AC97 core to become ready */
196196 i = 1000;
197− while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
197+ while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
198198 msleep(1);
199199 if (i == 0)
200200 printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n");
@@ -218,8 +218,8 @@ static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream, · 17 unmodified lines
218218
219219 chans = params_channels(params);
220220
221− r = ro = au_readl(AC97_CFG(pscdata));
222− stat = au_readl(AC97_STAT(pscdata));
221+ r = ro = __raw_readl(AC97_CFG(pscdata));
222+ stat = __raw_readl(AC97_STAT(pscdata));
223223
224224 /* already active? */
225225 if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) {
@@ -252,28 +252,28 @@ static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream, · 26 unmodified lines
252252 mutex_lock(&pscdata->lock);
253253
254254 /* disable AC97 device controller first... */
255− au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
256− au_sync();
255+ __raw_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
256+ wmb(); /* drain writebuffer */
257257
258258 /* ...wait for it... */
259259 t = 100;
260− while ((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
260+ while ((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
261261 msleep(1);
262262
263263 if (!t)
264264 printk(KERN_ERR "PSC-AC97: can't disable!\n");
265265
266266 /* ...write config... */
267− au_writel(r, AC97_CFG(pscdata));
268− au_sync();
267+ __raw_writel(r, AC97_CFG(pscdata));
268+ wmb(); /* drain writebuffer */
269269
270270 /* ...enable the AC97 controller again... */
271− au_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
272− au_sync();
271+ __raw_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
272+ wmb(); /* drain writebuffer */
273273
274274 /* ...and wait for ready bit */
275275 t = 100;
276− while ((!(au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
276+ while ((!(__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
277277 msleep(1);
278278
279279 if (!t)
@@ -300,21 +300,21 @@ static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream, · 20 unmodified lines
300300 switch (cmd) {
301301 case SNDRV_PCM_TRIGGER_START:
302302 case SNDRV_PCM_TRIGGER_RESUME:
303− au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
304− au_sync();
305− au_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
306− au_sync();
303+ __raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
304+ wmb(); /* drain writebuffer */
305+ __raw_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
306+ wmb(); /* drain writebuffer */
307307 break;
308308 case SNDRV_PCM_TRIGGER_STOP:
309309 case SNDRV_PCM_TRIGGER_SUSPEND:
310− au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
311− au_sync();
310+ __raw_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
311+ wmb(); /* drain writebuffer */
312312
313− while (au_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
313+ while (__raw_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
314314 asm volatile ("nop");
315315
316− au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
317− au_sync();
316+ __raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
317+ wmb(); /* drain writebuffer */
318318
319319 break;
320320 default:
@@ -398,13 +398,13 @@ static int au1xpsc_ac97_drvprobe(struct platform_device *pdev) · 77 unmodified lines
398398 PSC_AC97CFG_DE_ENABLE;
399399
400400 /* preserve PSC clock source set up by platform */
401− sel = au_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
402− au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
403− au_sync();
404− au_writel(0, PSC_SEL(wd));
405− au_sync();
406− au_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd));
407− au_sync();
401+ sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
402+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
403+ wmb(); /* drain writebuffer */
404+ __raw_writel(0, PSC_SEL(wd));
405+ wmb(); /* drain writebuffer */
406+ __raw_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd));
407+ wmb(); /* drain writebuffer */
408408
409409 /* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */
410410 memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template,
@@ -433,10 +433,10 @@ static int au1xpsc_ac97_drvremove(struct platform_device *pdev) · 22 unmodified lines
433433 snd_soc_unregister_component(&pdev->dev);
434434
435435 /* disable PSC completely */
436− au_writel(0, AC97_CFG(wd));
437− au_sync();
438− au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
439− au_sync();
436+ __raw_writel(0, AC97_CFG(wd));
437+ wmb(); /* drain writebuffer */
438+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
439+ wmb(); /* drain writebuffer */
440440
441441 au1xpsc_ac97_workdata = NULL; /* MDEV */
442442
@@ -449,12 +449,12 @@ static int au1xpsc_ac97_drvsuspend(struct device *dev) · 6 unmodified lines
449449 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
450450
451451 /* save interesting registers and disable PSC */
452− wd->pm[0] = au_readl(PSC_SEL(wd));
452+ wd->pm[0] = __raw_readl(PSC_SEL(wd));
453453
454− au_writel(0, AC97_CFG(wd));
455− au_sync();
456− au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
457− au_sync();
454+ __raw_writel(0, AC97_CFG(wd));
455+ wmb(); /* drain writebuffer */
456+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
457+ wmb(); /* drain writebuffer */
458458
459459 return 0;
460460 }
@@ -464,8 +464,8 @@ static int au1xpsc_ac97_drvresume(struct device *dev) · 3 unmodified lines
464464 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
465465
466466 /* restore PSC clock config */
467− au_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
468− au_sync();
467+ __raw_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
468+ wmb(); /* drain writebuffer */
469469
470470 /* after this point the ac97 core will cold-reset the codec.
471471 * During cold-reset the PSC is reinitialized and the last
sound/soc/au1x/psc-i2s.c+50−50
@@ -120,10 +120,10 @@ static int au1xpsc_i2s_hw_params(struct snd_pcm_substream *substream, · 119 unmodified lines
120120 unsigned long stat;
121121
122122 /* check if the PSC is already streaming data */
123− stat = au_readl(I2S_STAT(pscdata));
123+ stat = __raw_readl(I2S_STAT(pscdata));
124124 if (stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB)) {
125125 /* reject parameters not currently set up in hardware */
126− cfgbits = au_readl(I2S_CFG(pscdata));
126+ cfgbits = __raw_readl(I2S_CFG(pscdata));
127127 if ((PSC_I2SCFG_GET_LEN(cfgbits) != params->msbits) ||
128128 (params_rate(params) != pscdata->rate))
129129 return -EINVAL;
@@ -149,33 +149,33 @@ static int au1xpsc_i2s_configure(struct au1xpsc_audio_data *pscdata) · 19 unmodified lines
149149 unsigned long tmo;
150150
151151 /* bring PSC out of sleep, and configure I2S unit */
152− au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
153− au_sync();
152+ __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
153+ wmb(); /* drain writebuffer */
154154
155155 tmo = 1000000;
156− while (!(au_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo)
156+ while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo)
157157 tmo--;
158158
159159 if (!tmo)
160160 goto psc_err;
161161
162− au_writel(0, I2S_CFG(pscdata));
163− au_sync();
164− au_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata));
165− au_sync();
162+ __raw_writel(0, I2S_CFG(pscdata));
163+ wmb(); /* drain writebuffer */
164+ __raw_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata));
165+ wmb(); /* drain writebuffer */
166166
167167 /* wait for I2S controller to become ready */
168168 tmo = 1000000;
169− while (!(au_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo)
169+ while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo)
170170 tmo--;
171171
172172 if (tmo)
173173 return 0;
174174
175175 psc_err:
176− au_writel(0, I2S_CFG(pscdata));
177− au_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
178− au_sync();
176+ __raw_writel(0, I2S_CFG(pscdata));
177+ __raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
178+ wmb(); /* drain writebuffer */
179179 return -ETIMEDOUT;
180180 }
181181
@@ -187,26 +187,26 @@ static int au1xpsc_i2s_start(struct au1xpsc_audio_data *pscdata, int stype) · 5 unmodified lines
187187 ret = 0;
188188
189189 /* if both TX and RX are idle, configure the PSC */
190− stat = au_readl(I2S_STAT(pscdata));
190+ stat = __raw_readl(I2S_STAT(pscdata));
191191 if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) {
192192 ret = au1xpsc_i2s_configure(pscdata);
193193 if (ret)
194194 goto out;
195195 }
196196
197− au_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata));
198− au_sync();
199− au_writel(I2SPCR_START(stype), I2S_PCR(pscdata));
200− au_sync();
197+ __raw_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata));
198+ wmb(); /* drain writebuffer */
199+ __raw_writel(I2SPCR_START(stype), I2S_PCR(pscdata));
200+ wmb(); /* drain writebuffer */
201201
202202 /* wait for start confirmation */
203203 tmo = 1000000;
204− while (!(au_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
204+ while (!(__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
205205 tmo--;
206206
207207 if (!tmo) {
208− au_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
209− au_sync();
208+ __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
209+ wmb(); /* drain writebuffer */
210210 ret = -ETIMEDOUT;
211211 }
212212 out:
@@ -217,21 +217,21 @@ static int au1xpsc_i2s_stop(struct au1xpsc_audio_data *pscdata, int stype) · 4 unmodified lines
217217 {
218218 unsigned long tmo, stat;
219219
220− au_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
221− au_sync();
220+ __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
221+ wmb(); /* drain writebuffer */
222222
223223 /* wait for stop confirmation */
224224 tmo = 1000000;
225− while ((au_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
225+ while ((__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
226226 tmo--;
227227
228228 /* if both TX and RX are idle, disable PSC */
229− stat = au_readl(I2S_STAT(pscdata));
229+ stat = __raw_readl(I2S_STAT(pscdata));
230230 if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) {
231− au_writel(0, I2S_CFG(pscdata));
232− au_sync();
233− au_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
234− au_sync();
231+ __raw_writel(0, I2S_CFG(pscdata));
232+ wmb(); /* drain writebuffer */
233+ __raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
234+ wmb(); /* drain writebuffer */
235235 }
236236 return 0;
237237 }
@@ -332,12 +332,12 @@ static int au1xpsc_i2s_drvprobe(struct platform_device *pdev) · 94 unmodified lines
332332 /* preserve PSC clock source set up by platform (dev.platform_data
333333 * is already occupied by soc layer)
334334 */
335− sel = au_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
336− au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
337− au_sync();
338− au_writel(PSC_SEL_PS_I2SMODE | sel, PSC_SEL(wd));
339− au_writel(0, I2S_CFG(wd));
340− au_sync();
335+ sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
336+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
337+ wmb(); /* drain writebuffer */
338+ __raw_writel(PSC_SEL_PS_I2SMODE | sel, PSC_SEL(wd));
339+ __raw_writel(0, I2S_CFG(wd));
340+ wmb(); /* drain writebuffer */
341341
342342 /* preconfigure: set max rx/tx fifo depths */
343343 wd->cfg |= PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8;
@@ -364,10 +364,10 @@ static int au1xpsc_i2s_drvremove(struct platform_device *pdev) · 20 unmodified lines
364364
365365 snd_soc_unregister_component(&pdev->dev);
366366
367− au_writel(0, I2S_CFG(wd));
368− au_sync();
369− au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
370− au_sync();
367+ __raw_writel(0, I2S_CFG(wd));
368+ wmb(); /* drain writebuffer */
369+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
370+ wmb(); /* drain writebuffer */
371371
372372 return 0;
373373 }
@@ -378,12 +378,12 @@ static int au1xpsc_i2s_drvsuspend(struct device *dev) · 4 unmodified lines
378378 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
379379
380380 /* save interesting register and disable PSC */
381− wd->pm[0] = au_readl(PSC_SEL(wd));
381+ wd->pm[0] = __raw_readl(PSC_SEL(wd));
382382
383− au_writel(0, I2S_CFG(wd));
384− au_sync();
385− au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
386− au_sync();
383+ __raw_writel(0, I2S_CFG(wd));
384+ wmb(); /* drain writebuffer */
385+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
386+ wmb(); /* drain writebuffer */
387387
388388 return 0;
389389 }
@@ -393,12 +393,12 @@ static int au1xpsc_i2s_drvresume(struct device *dev) · 3 unmodified lines
393393 struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
394394
395395 /* select I2S mode and PSC clock */
396− au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
397− au_sync();
398− au_writel(0, PSC_SEL(wd));
399− au_sync();
400− au_writel(wd->pm[0], PSC_SEL(wd));
401− au_sync();
396+ __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
397+ wmb(); /* drain writebuffer */
398+ __raw_writel(0, PSC_SEL(wd));
399+ wmb(); /* drain writebuffer */
400+ __raw_writel(wd->pm[0], PSC_SEL(wd));
401+ wmb(); /* drain writebuffer */
402402
403403 return 0;
404404 }
sound/soc/au1x/psc.h+11−11
@@ -27,16 +27,16 @@ struct au1xpsc_audio_data { · 26 unmodified lines
2727 };
2828
2929 /* easy access macros */
30−#define PSC_CTRL(x) ((unsigned long)((x)->mmio) + PSC_CTRL_OFFSET)
31−#define PSC_SEL(x) ((unsigned long)((x)->mmio) + PSC_SEL_OFFSET)
32−#define I2S_STAT(x) ((unsigned long)((x)->mmio) + PSC_I2SSTAT_OFFSET)
33−#define I2S_CFG(x) ((unsigned long)((x)->mmio) + PSC_I2SCFG_OFFSET)
34−#define I2S_PCR(x) ((unsigned long)((x)->mmio) + PSC_I2SPCR_OFFSET)
35−#define AC97_CFG(x) ((unsigned long)((x)->mmio) + PSC_AC97CFG_OFFSET)
36−#define AC97_CDC(x) ((unsigned long)((x)->mmio) + PSC_AC97CDC_OFFSET)
37−#define AC97_EVNT(x) ((unsigned long)((x)->mmio) + PSC_AC97EVNT_OFFSET)
38−#define AC97_PCR(x) ((unsigned long)((x)->mmio) + PSC_AC97PCR_OFFSET)
39−#define AC97_RST(x) ((unsigned long)((x)->mmio) + PSC_AC97RST_OFFSET)
40−#define AC97_STAT(x) ((unsigned long)((x)->mmio) + PSC_AC97STAT_OFFSET)
30+#define PSC_CTRL(x) ((x)->mmio + PSC_CTRL_OFFSET)
31+#define PSC_SEL(x) ((x)->mmio + PSC_SEL_OFFSET)
32+#define I2S_STAT(x) ((x)->mmio + PSC_I2SSTAT_OFFSET)
33+#define I2S_CFG(x) ((x)->mmio + PSC_I2SCFG_OFFSET)
34+#define I2S_PCR(x) ((x)->mmio + PSC_I2SPCR_OFFSET)
35+#define AC97_CFG(x) ((x)->mmio + PSC_AC97CFG_OFFSET)
36+#define AC97_CDC(x) ((x)->mmio + PSC_AC97CDC_OFFSET)
37+#define AC97_EVNT(x) ((x)->mmio + PSC_AC97EVNT_OFFSET)
38+#define AC97_PCR(x) ((x)->mmio + PSC_AC97PCR_OFFSET)
39+#define AC97_RST(x) ((x)->mmio + PSC_AC97RST_OFFSET)
40+#define AC97_STAT(x) ((x)->mmio + PSC_AC97STAT_OFFSET)
4141
4242 #endif