History

mfd: ezx-pcap: Remove unused driver

Support for the Motorola EZX phones based on Intel PXA processors was removed in 2022, but this driver remained present in the tree. As far as I can tell, the support was never quite functional upstream because the board files did not actually instantiate the SPI device for the PCAP. There are still also drivers for the various mfd cells: keys, touchscreen, regulator and rtc, all of which are obviously orphaned as well but can be removed separately as the Kconfig dependency now prevents them from being enabled.

Arnd Bergmann committed 6 months ago

Commit e6f00181 parent 7ee4fa24 files · +0 −752Browse files

Unified · Split

4 files
  1. drivers/mfd/Kconfig +0 −7
  2. drivers/mfd/Makefile +0 −1
  3. drivers/mfd/ezx-pcap.c +0 −491
  4. include/linux/mfd/ezx-pcap.h +0 −253
drivers/mfd/Kconfig+0−7
@@ -1199,13 +1199,6 @@ config MFD_OCELOT · 1198 unmodified lines
11991199
12001200 If unsure, say N.
12011201
1202−config EZX_PCAP
1203− bool "Motorola EZXPCAP Support"
1204− depends on SPI_MASTER
1205− help
1206− This enables the PCAP ASIC present on EZX Phones. This is
1207− needed for MMC, TouchScreen, Sound, USB, etc..
1208−
12091202 config MFD_CPCAP
12101203 tristate "Support for Motorola CPCAP"
12111204 depends on SPI
drivers/mfd/Makefile+0−1
@@ -131,7 +131,6 @@ obj-$(CONFIG_MFD_CORE) += mfd-core.o · 130 unmodified lines
131131 ocelot-soc-objs := ocelot-core.o ocelot-spi.o
132132 obj-$(CONFIG_MFD_OCELOT) += ocelot-soc.o
133133
134−obj-$(CONFIG_EZX_PCAP) += ezx-pcap.o
135134 obj-$(CONFIG_MFD_CPCAP) += motorola-cpcap.o
136135
137136 obj-$(CONFIG_MCP) += mcp-core.o
drivers/mfd/ezx-pcap.c+0−491
@@ -1,491 +0,0 @@
1−// SPDX-License-Identifier: GPL-2.0-only
2−/*
3− * Driver for Motorola PCAP2 as present in EZX phones
4− *
5− * Copyright (C) 2006 Harald Welte <laforge@openezx.org>
6− * Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
7− */
8−
9−#include <linux/module.h>
10−#include <linux/kernel.h>
11−#include <linux/platform_device.h>
12−#include <linux/interrupt.h>
13−#include <linux/irq.h>
14−#include <linux/mfd/ezx-pcap.h>
15−#include <linux/spi/spi.h>
16−#include <linux/gpio.h>
17−#include <linux/slab.h>
18−
19−#define PCAP_ADC_MAXQ 8
20−struct pcap_adc_request {
21− u8 bank;
22− u8 ch[2];
23− u32 flags;
24− void (*callback)(void *, u16[]);
25− void *data;
26−};
27−
28−struct pcap_chip {
29− struct spi_device *spi;
30−
31− /* IO */
32− u32 buf;
33− spinlock_t io_lock;
34−
35− /* IRQ */
36− unsigned int irq_base;
37− u32 msr;
38− struct work_struct isr_work;
39− struct work_struct msr_work;
40− struct workqueue_struct *workqueue;
41−
42− /* ADC */
43− struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
44− u8 adc_head;
45− u8 adc_tail;
46− spinlock_t adc_lock;
47−};
48−
49−/* IO */
50−static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data)
51−{
52− struct spi_transfer t;
53− struct spi_message m;
54− int status;
55−
56− memset(&t, 0, sizeof(t));
57− spi_message_init(&m);
58− t.len = sizeof(u32);
59− spi_message_add_tail(&t, &m);
60−
61− pcap->buf = *data;
62− t.tx_buf = (u8 *) &pcap->buf;
63− t.rx_buf = (u8 *) &pcap->buf;
64− status = spi_sync(pcap->spi, &m);
65−
66− if (status == 0)
67− *data = pcap->buf;
68−
69− return status;
70−}
71−
72−int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
73−{
74− unsigned long flags;
75− int ret;
76−
77− spin_lock_irqsave(&pcap->io_lock, flags);
78− value &= PCAP_REGISTER_VALUE_MASK;
79− value |= PCAP_REGISTER_WRITE_OP_BIT
80− | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
81− ret = ezx_pcap_putget(pcap, &value);
82− spin_unlock_irqrestore(&pcap->io_lock, flags);
83−
84− return ret;
85−}
86−EXPORT_SYMBOL_GPL(ezx_pcap_write);
87−
88−int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
89−{
90− unsigned long flags;
91− int ret;
92−
93− spin_lock_irqsave(&pcap->io_lock, flags);
94− *value = PCAP_REGISTER_READ_OP_BIT
95− | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
96−
97− ret = ezx_pcap_putget(pcap, value);
98− spin_unlock_irqrestore(&pcap->io_lock, flags);
99−
100− return ret;
101−}
102−EXPORT_SYMBOL_GPL(ezx_pcap_read);
103−
104−int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
105−{
106− unsigned long flags;
107− int ret;
108− u32 tmp = PCAP_REGISTER_READ_OP_BIT |
109− (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
110−
111− spin_lock_irqsave(&pcap->io_lock, flags);
112− ret = ezx_pcap_putget(pcap, &tmp);
113− if (ret)
114− goto out_unlock;
115−
116− tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);
117− tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT |
118− (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
119−
120− ret = ezx_pcap_putget(pcap, &tmp);
121−out_unlock:
122− spin_unlock_irqrestore(&pcap->io_lock, flags);
123−
124− return ret;
125−}
126−EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);
127−
128−/* IRQ */
129−int irq_to_pcap(struct pcap_chip *pcap, int irq)
130−{
131− return irq - pcap->irq_base;
132−}
133−EXPORT_SYMBOL_GPL(irq_to_pcap);
134−
135−int pcap_to_irq(struct pcap_chip *pcap, int irq)
136−{
137− return pcap->irq_base + irq;
138−}
139−EXPORT_SYMBOL_GPL(pcap_to_irq);
140−
141−static void pcap_mask_irq(struct irq_data *d)
142−{
143− struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
144−
145− pcap->msr |= 1 << irq_to_pcap(pcap, d->irq);
146− queue_work(pcap->workqueue, &pcap->msr_work);
147−}
148−
149−static void pcap_unmask_irq(struct irq_data *d)
150−{
151− struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
152−
153− pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq));
154− queue_work(pcap->workqueue, &pcap->msr_work);
155−}
156−
157−static struct irq_chip pcap_irq_chip = {
158− .name = "pcap",
159− .irq_disable = pcap_mask_irq,
160− .irq_mask = pcap_mask_irq,
161− .irq_unmask = pcap_unmask_irq,
162−};
163−
164−static void pcap_msr_work(struct work_struct *work)
165−{
166− struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);
167−
168− ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
169−}
170−
171−static void pcap_isr_work(struct work_struct *work)
172−{
173− struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
174− struct pcap_platform_data *pdata = dev_get_platdata(&pcap->spi->dev);
175− u32 msr, isr, int_sel, service;
176− int irq;
177−
178− do {
179− ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
180− ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
181−
182− /* We can't service/ack irqs that are assigned to port 2 */
183− if (!(pdata->config & PCAP_SECOND_PORT)) {
184− ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
185− isr &= ~int_sel;
186− }
187−
188− ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr);
189− ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
190−
191− service = isr & ~msr;
192− for (irq = pcap->irq_base; service; service >>= 1, irq++) {
193− if (service & 1)
194− generic_handle_irq_safe(irq);
195− }
196− ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
197− } while (gpio_get_value(pdata->gpio));
198−}
199−
200−static void pcap_irq_handler(struct irq_desc *desc)
201−{
202− struct pcap_chip *pcap = irq_desc_get_handler_data(desc);
203−
204− desc->irq_data.chip->irq_ack(&desc->irq_data);
205− queue_work(pcap->workqueue, &pcap->isr_work);
206−}
207−
208−/* ADC */
209−void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
210−{
211− unsigned long flags;
212− u32 tmp;
213−
214− spin_lock_irqsave(&pcap->adc_lock, flags);
215− ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
216− tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
217− tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
218− ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
219− spin_unlock_irqrestore(&pcap->adc_lock, flags);
220−}
221−EXPORT_SYMBOL_GPL(pcap_set_ts_bits);
222−
223−static void pcap_disable_adc(struct pcap_chip *pcap)
224−{
225− u32 tmp;
226−
227− ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
228− tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY);
229− ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
230−}
231−
232−static void pcap_adc_trigger(struct pcap_chip *pcap)
233−{
234− unsigned long flags;
235− u32 tmp;
236− u8 head;
237−
238− spin_lock_irqsave(&pcap->adc_lock, flags);
239− head = pcap->adc_head;
240− if (!pcap->adc_queue[head]) {
241− /* queue is empty, save power */
242− pcap_disable_adc(pcap);
243− spin_unlock_irqrestore(&pcap->adc_lock, flags);
244− return;
245− }
246− /* start conversion on requested bank, save TS_M bits */
247− ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
248− tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
249− tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;
250−
251− if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
252− tmp |= PCAP_ADC_AD_SEL1;
253−
254− ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
255− spin_unlock_irqrestore(&pcap->adc_lock, flags);
256− ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
257−}
258−
259−static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
260−{
261− struct pcap_chip *pcap = _pcap;
262− struct pcap_adc_request *req;
263− u16 res[2];
264− u32 tmp;
265−
266− spin_lock(&pcap->adc_lock);
267− req = pcap->adc_queue[pcap->adc_head];
268−
269− if (WARN(!req, "adc irq without pending request\n")) {
270− spin_unlock(&pcap->adc_lock);
271− return IRQ_HANDLED;
272− }
273−
274− /* read requested channels results */
275− ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
276− tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK);
277− tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
278− tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
279− ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
280− ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
281− res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
282− res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;
283−
284− pcap->adc_queue[pcap->adc_head] = NULL;
285− pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
286− spin_unlock(&pcap->adc_lock);
287−
288− /* pass the results and release memory */
289− req->callback(req->data, res);
290− kfree(req);
291−
292− /* trigger next conversion (if any) on queue */
293− pcap_adc_trigger(pcap);
294−
295− return IRQ_HANDLED;
296−}
297−
298−int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
299− void *callback, void *data)
300−{
301− struct pcap_adc_request *req;
302− unsigned long irq_flags;
303−
304− /* This will be freed after we have a result */
305− req = kmalloc_obj(struct pcap_adc_request);
306− if (!req)
307− return -ENOMEM;
308−
309− req->bank = bank;
310− req->flags = flags;
311− req->ch[0] = ch[0];
312− req->ch[1] = ch[1];
313− req->callback = callback;
314− req->data = data;
315−
316− spin_lock_irqsave(&pcap->adc_lock, irq_flags);
317− if (pcap->adc_queue[pcap->adc_tail]) {
318− spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);
319− kfree(req);
320− return -EBUSY;
321− }
322− pcap->adc_queue[pcap->adc_tail] = req;
323− pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
324− spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);
325−
326− /* start conversion */
327− pcap_adc_trigger(pcap);
328−
329− return 0;
330−}
331−EXPORT_SYMBOL_GPL(pcap_adc_async);
332−
333−/* subdevs */
334−static int pcap_remove_subdev(struct device *dev, void *unused)
335−{
336− platform_device_unregister(to_platform_device(dev));
337− return 0;
338−}
339−
340−static int pcap_add_subdev(struct pcap_chip *pcap,
341− struct pcap_subdev *subdev)
342−{
343− struct platform_device *pdev;
344− int ret;
345−
346− pdev = platform_device_alloc(subdev->name, subdev->id);
347− if (!pdev)
348− return -ENOMEM;
349−
350− pdev->dev.parent = &pcap->spi->dev;
351− pdev->dev.platform_data = subdev->platform_data;
352−
353− ret = platform_device_add(pdev);
354− if (ret)
355− platform_device_put(pdev);
356−
357− return ret;
358−}
359−
360−static void ezx_pcap_remove(struct spi_device *spi)
361−{
362− struct pcap_chip *pcap = spi_get_drvdata(spi);
363− unsigned long flags;
364− int i;
365−
366− /* remove all registered subdevs */
367− device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
368−
369− /* cleanup ADC */
370− spin_lock_irqsave(&pcap->adc_lock, flags);
371− for (i = 0; i < PCAP_ADC_MAXQ; i++)
372− kfree(pcap->adc_queue[i]);
373− spin_unlock_irqrestore(&pcap->adc_lock, flags);
374−
375− /* cleanup irqchip */
376− for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
377− irq_set_chip_and_handler(i, NULL, NULL);
378−}
379−
380−static int ezx_pcap_probe(struct spi_device *spi)
381−{
382− struct pcap_platform_data *pdata = dev_get_platdata(&spi->dev);
383− struct pcap_chip *pcap;
384− int i, adc_irq;
385− int ret;
386−
387− /* platform data is required */
388− if (!pdata)
389− return -ENODEV;
390−
391− pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL);
392− if (!pcap)
393− return -ENOMEM;
394−
395− spin_lock_init(&pcap->io_lock);
396− spin_lock_init(&pcap->adc_lock);
397− INIT_WORK(&pcap->isr_work, pcap_isr_work);
398− INIT_WORK(&pcap->msr_work, pcap_msr_work);
399− spi_set_drvdata(spi, pcap);
400−
401− /* setup spi */
402− spi->bits_per_word = 32;
403− spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
404− ret = spi_setup(spi);
405− if (ret)
406− return ret;
407−
408− pcap->spi = spi;
409−
410− /* setup irq */
411− pcap->irq_base = pdata->irq_base;
412− pcap->workqueue = devm_alloc_ordered_workqueue(&spi->dev, "pcapd", 0);
413− if (!pcap->workqueue)
414− return -ENOMEM;
415−
416− /* redirect interrupts to AP, except adcdone2 */
417− if (!(pdata->config & PCAP_SECOND_PORT))
418− ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
419− (1 << PCAP_IRQ_ADCDONE2));
420−
421− /* setup irq chip */
422− for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
423− irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
424− irq_set_chip_data(i, pcap);
425− irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
426− }
427−
428− /* mask/ack all PCAP interrupts */
429− ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
430− ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
431− pcap->msr = PCAP_MASK_ALL_INTERRUPT;
432−
433− irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
434− irq_set_chained_handler_and_data(spi->irq, pcap_irq_handler, pcap);
435− irq_set_irq_wake(spi->irq, 1);
436−
437− /* ADC */
438− adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
439− PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
440−
441− ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC",
442− pcap);
443− if (ret)
444− goto free_irqchip;
445−
446− /* setup subdevs */
447− for (i = 0; i < pdata->num_subdevs; i++) {
448− ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
449− if (ret)
450− goto remove_subdevs;
451− }
452−
453− /* board specific quirks */
454− if (pdata->init)
455− pdata->init(pcap);
456−
457− return 0;
458−
459−remove_subdevs:
460− device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
461−free_irqchip:
462− for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
463− irq_set_chip_and_handler(i, NULL, NULL);
464−
465− return ret;
466−}
467−
468−static struct spi_driver ezxpcap_driver = {
469− .probe = ezx_pcap_probe,
470− .remove = ezx_pcap_remove,
471− .driver = {
472− .name = "ezx-pcap",
473− },
474−};
475−
476−static int __init ezx_pcap_init(void)
477−{
478− return spi_register_driver(&ezxpcap_driver);
479−}
480−
481−static void __exit ezx_pcap_exit(void)
482−{
483− spi_unregister_driver(&ezxpcap_driver);
484−}
485−
486−subsys_initcall(ezx_pcap_init);
487−module_exit(ezx_pcap_exit);
488−
489−MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
490−MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
491−MODULE_ALIAS("spi:ezx-pcap");
include/linux/mfd/ezx-pcap.h+0−253
@@ -1,253 +0,0 @@
1−/* SPDX-License-Identifier: GPL-2.0 */
2−/*
3− * Copyright 2009 Daniel Ribeiro <drwyrm@gmail.com>
4− *
5− * For further information, please see http://wiki.openezx.org/PCAP2
6− */
7−
8−#ifndef EZX_PCAP_H
9−#define EZX_PCAP_H
10−
11−struct pcap_subdev {
12− int id;
13− const char *name;
14− void *platform_data;
15−};
16−
17−struct pcap_platform_data {
18− unsigned int irq_base;
19− unsigned int config;
20− int gpio;
21− void (*init) (void *); /* board specific init */
22− int num_subdevs;
23− struct pcap_subdev *subdevs;
24−};
25−
26−struct pcap_chip;
27−
28−int ezx_pcap_write(struct pcap_chip *, u8, u32);
29−int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
30−int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32);
31−int pcap_to_irq(struct pcap_chip *, int);
32−int irq_to_pcap(struct pcap_chip *, int);
33−int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
34−void pcap_set_ts_bits(struct pcap_chip *, u32);
35−
36−#define PCAP_SECOND_PORT 1
37−#define PCAP_CS_AH 2
38−
39−#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
40−#define PCAP_REGISTER_READ_OP_BIT 0x00000000
41−
42−#define PCAP_REGISTER_VALUE_MASK 0x01ffffff
43−#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
44−#define PCAP_REGISTER_ADDRESS_SHIFT 26
45−#define PCAP_REGISTER_NUMBER 32
46−#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
47−#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
48−
49−/* registers accessible by both pcap ports */
50−#define PCAP_REG_ISR 0x0 /* Interrupt Status */
51−#define PCAP_REG_MSR 0x1 /* Interrupt Mask */
52−#define PCAP_REG_PSTAT 0x2 /* Processor Status */
53−#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
54−#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
55−#define PCAP_REG_BATT 0x8 /* Battery Control */
56−#define PCAP_REG_ADC 0x9 /* AD Control */
57−#define PCAP_REG_ADR 0xa /* AD Result */
58−#define PCAP_REG_CODEC 0xb /* Audio Codec Control */
59−#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */
60−#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */
61−#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */
62−#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */
63−#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
64−#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */
65−#define PCAP_REG_GP 0x1b /* General Purpose */
66−#define PCAP_REG_TEST1 0x1c
67−#define PCAP_REG_TEST2 0x1d
68−#define PCAP_REG_VENDOR_TEST1 0x1e
69−#define PCAP_REG_VENDOR_TEST2 0x1f
70−
71−/* registers accessible by pcap port 1 only (a1200, e2 & e6) */
72−#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */
73−#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
74−#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
75−#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */
76−#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */
77−#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */
78−#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */
79−#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */
80−#define PCAP_REG_PWR 0x13 /* Power Control */
81−#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
82−#define PCAP_REG_VENDOR_REV 0x17
83−#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */
84−
85−/* PCAP2 Interrupts */
86−#define PCAP_NIRQS 23
87−#define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */
88−#define PCAP_IRQ_TS 1 /* Touch Screen */
89−#define PCAP_IRQ_1HZ 2 /* 1HZ timer */
90−#define PCAP_IRQ_WH 3 /* ADC above high limit */
91−#define PCAP_IRQ_WL 4 /* ADC below low limit */
92−#define PCAP_IRQ_TODA 5 /* Time of day alarm */
93−#define PCAP_IRQ_USB4V 6 /* USB above 4V */
94−#define PCAP_IRQ_ONOFF 7 /* On/Off button */
95−#define PCAP_IRQ_ONOFF2 8 /* On/Off button 2 */
96−#define PCAP_IRQ_USB1V 9 /* USB above 1V */
97−#define PCAP_IRQ_MOBPORT 10
98−#define PCAP_IRQ_MIC 11 /* Mic attach/HS button */
99−#define PCAP_IRQ_HS 12 /* Headset attach */
100−#define PCAP_IRQ_ST 13
101−#define PCAP_IRQ_PC 14 /* Power Cut */
102−#define PCAP_IRQ_WARM 15
103−#define PCAP_IRQ_EOL 16 /* Battery End Of Life */
104−#define PCAP_IRQ_CLK 17
105−#define PCAP_IRQ_SYSRST 18 /* System Reset */
106−#define PCAP_IRQ_DUMMY 19
107−#define PCAP_IRQ_ADCDONE2 20 /* ADC done port 2 */
108−#define PCAP_IRQ_SOFTRESET 21
109−#define PCAP_IRQ_MNEXB 22
110−
111−/* voltage regulators */
112−#define V1 0
113−#define V2 1
114−#define V3 2
115−#define V4 3
116−#define V5 4
117−#define V6 5
118−#define V7 6
119−#define V8 7
120−#define V9 8
121−#define V10 9
122−#define VAUX1 10
123−#define VAUX2 11
124−#define VAUX3 12
125−#define VAUX4 13
126−#define VSIM 14
127−#define VSIM2 15
128−#define VVIB 16
129−#define SW1 17
130−#define SW2 18
131−#define SW3 19
132−#define SW1S 20
133−#define SW2S 21
134−
135−#define PCAP_BATT_DAC_MASK 0x000000ff
136−#define PCAP_BATT_DAC_SHIFT 0
137−#define PCAP_BATT_B_FDBK (1 << 8)
138−#define PCAP_BATT_EXT_ISENSE (1 << 9)
139−#define PCAP_BATT_V_COIN_MASK 0x00003c00
140−#define PCAP_BATT_V_COIN_SHIFT 10
141−#define PCAP_BATT_I_COIN (1 << 14)
142−#define PCAP_BATT_COIN_CH_EN (1 << 15)
143−#define PCAP_BATT_EOL_SEL_MASK 0x000e0000
144−#define PCAP_BATT_EOL_SEL_SHIFT 17
145−#define PCAP_BATT_EOL_CMP_EN (1 << 20)
146−#define PCAP_BATT_BATT_DET_EN (1 << 21)
147−#define PCAP_BATT_THERMBIAS_CTRL (1 << 22)
148−
149−#define PCAP_ADC_ADEN (1 << 0)
150−#define PCAP_ADC_RAND (1 << 1)
151−#define PCAP_ADC_AD_SEL1 (1 << 2)
152−#define PCAP_ADC_AD_SEL2 (1 << 3)
153−#define PCAP_ADC_ADA1_MASK 0x00000070
154−#define PCAP_ADC_ADA1_SHIFT 4
155−#define PCAP_ADC_ADA2_MASK 0x00000380
156−#define PCAP_ADC_ADA2_SHIFT 7
157−#define PCAP_ADC_ATO_MASK 0x00003c00
158−#define PCAP_ADC_ATO_SHIFT 10
159−#define PCAP_ADC_ATOX (1 << 14)
160−#define PCAP_ADC_MTR1 (1 << 15)
161−#define PCAP_ADC_MTR2 (1 << 16)
162−#define PCAP_ADC_TS_M_MASK 0x000e0000
163−#define PCAP_ADC_TS_M_SHIFT 17
164−#define PCAP_ADC_TS_REF_LOWPWR (1 << 20)
165−#define PCAP_ADC_TS_REFENB (1 << 21)
166−#define PCAP_ADC_BATT_I_POLARITY (1 << 22)
167−#define PCAP_ADC_BATT_I_ADC (1 << 23)
168−
169−#define PCAP_ADC_BANK_0 0
170−#define PCAP_ADC_BANK_1 1
171−/* ADC bank 0 */
172−#define PCAP_ADC_CH_COIN 0
173−#define PCAP_ADC_CH_BATT 1
174−#define PCAP_ADC_CH_BPLUS 2
175−#define PCAP_ADC_CH_MOBPORTB 3
176−#define PCAP_ADC_CH_TEMPERATURE 4
177−#define PCAP_ADC_CH_CHARGER_ID 5
178−#define PCAP_ADC_CH_AD6 6
179−/* ADC bank 1 */
180−#define PCAP_ADC_CH_AD7 0
181−#define PCAP_ADC_CH_AD8 1
182−#define PCAP_ADC_CH_AD9 2
183−#define PCAP_ADC_CH_TS_X1 3
184−#define PCAP_ADC_CH_TS_X2 4
185−#define PCAP_ADC_CH_TS_Y1 5
186−#define PCAP_ADC_CH_TS_Y2 6
187−
188−#define PCAP_ADC_T_NOW 0
189−#define PCAP_ADC_T_IN_BURST 1
190−#define PCAP_ADC_T_OUT_BURST 2
191−
192−#define PCAP_ADC_ATO_IN_BURST 6
193−#define PCAP_ADC_ATO_OUT_BURST 0
194−
195−#define PCAP_ADC_TS_M_XY 1
196−#define PCAP_ADC_TS_M_PRESSURE 2
197−#define PCAP_ADC_TS_M_PLATE_X 3
198−#define PCAP_ADC_TS_M_PLATE_Y 4
199−#define PCAP_ADC_TS_M_STANDBY 5
200−#define PCAP_ADC_TS_M_NONTS 6
201−
202−#define PCAP_ADR_ADD1_MASK 0x000003ff
203−#define PCAP_ADR_ADD1_SHIFT 0
204−#define PCAP_ADR_ADD2_MASK 0x000ffc00
205−#define PCAP_ADR_ADD2_SHIFT 10
206−#define PCAP_ADR_ADINC1 (1 << 20)
207−#define PCAP_ADR_ADINC2 (1 << 21)
208−#define PCAP_ADR_ASC (1 << 22)
209−#define PCAP_ADR_ONESHOT (1 << 23)
210−
211−#define PCAP_BUSCTRL_FSENB (1 << 0)
212−#define PCAP_BUSCTRL_USB_SUSPEND (1 << 1)
213−#define PCAP_BUSCTRL_USB_PU (1 << 2)
214−#define PCAP_BUSCTRL_USB_PD (1 << 3)
215−#define PCAP_BUSCTRL_VUSB_EN (1 << 4)
216−#define PCAP_BUSCTRL_USB_PS (1 << 5)
217−#define PCAP_BUSCTRL_VUSB_MSTR_EN (1 << 6)
218−#define PCAP_BUSCTRL_VBUS_PD_ENB (1 << 7)
219−#define PCAP_BUSCTRL_CURRLIM (1 << 8)
220−#define PCAP_BUSCTRL_RS232ENB (1 << 9)
221−#define PCAP_BUSCTRL_RS232_DIR (1 << 10)
222−#define PCAP_BUSCTRL_SE0_CONN (1 << 11)
223−#define PCAP_BUSCTRL_USB_PDM (1 << 12)
224−#define PCAP_BUSCTRL_BUS_PRI_ADJ (1 << 24)
225−
226−/* leds */
227−#define PCAP_LED0 0
228−#define PCAP_LED1 1
229−#define PCAP_BL0 2
230−#define PCAP_BL1 3
231−#define PCAP_LED_3MA 0
232−#define PCAP_LED_4MA 1
233−#define PCAP_LED_5MA 2
234−#define PCAP_LED_9MA 3
235−#define PCAP_LED_T_MASK 0xf
236−#define PCAP_LED_C_MASK 0x3
237−#define PCAP_BL_MASK 0x1f
238−#define PCAP_BL0_SHIFT 0
239−#define PCAP_LED0_EN (1 << 5)
240−#define PCAP_LED1_EN (1 << 6)
241−#define PCAP_LED0_T_SHIFT 7
242−#define PCAP_LED1_T_SHIFT 11
243−#define PCAP_LED0_C_SHIFT 15
244−#define PCAP_LED1_C_SHIFT 17
245−#define PCAP_BL1_SHIFT 20
246−
247−/* RTC */
248−#define PCAP_RTC_DAY_MASK 0x3fff
249−#define PCAP_RTC_TOD_MASK 0xffff
250−#define PCAP_RTC_PC_MASK 0x7
251−#define SEC_PER_DAY 86400
252−
253−#endif

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