Pull RISC-V updates from Paul Walmsley: "Before v7.0 is released, fix a few issues with the CFI patchset, merged earlier in v7.0-rc, that primarily affect interfaces to non-kernel code: - Improve the prctl() interface for per-task indirect branch landing pad control to expand abbreviations and to resemble the speculation control prctl() interface - Expand the "LP" and "SS" abbreviations in the ptrace uapi header file to "branch landing pad" and "shadow stack", to improve readability - Fix a typo in a CFI-related macro name in the ptrace uapi header file - Ensure that the indirect branch tracking state and shadow stack state are unlocked immediately after an exec() on the new task so that libc subsequently can control it - While working in this area, clean up the kernel-internal, cross-architecture prctl() function names by expanding the abbreviations mentioned above" * tag 'riscv-for-linus-v7.0-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: prctl: cfi: change the branch landing pad prctl()s to be more descriptive riscv: ptrace: cfi: expand "SS" references to "shadow stack" in uapi headers prctl: rename branch landing pad implementation functions to be more explicit riscv: ptrace: expand "LP" references to "branch landing pads" in uapi headers riscv: cfi: clear CFI lock status in start_thread() riscv: ptrace: cfi: fix "PRACE" typo in uapi header
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| @@ -397,30 +397,23 @@ struct prctl_mm_map { · 396 unmodified lines | ||
| 397 | 397 | # define PR_RSEQ_SLICE_EXT_ENABLE 0x01 |
| 398 | 398 | |
| 399 | 399 | /* |
| 400 | − * Get the current indirect branch tracking configuration for the current | |
| 401 | − * thread, this will be the value configured via PR_SET_INDIR_BR_LP_STATUS. | |
| 400 | + * Get or set the control flow integrity (CFI) configuration for the | |
| 401 | + * current thread. | |
| 402 | + * | |
| 403 | + * Some per-thread control flow integrity settings are not yet | |
| 404 | + * controlled through this prctl(); see for example | |
| 405 | + * PR_{GET,SET,LOCK}_SHADOW_STACK_STATUS | |
| 402 | 406 | */ |
| 403 | −#define PR_GET_INDIR_BR_LP_STATUS 80 | |
| 404 | − | |
| 407 | +#define PR_GET_CFI 80 | |
| 408 | +#define PR_SET_CFI 81 | |
| 405 | 409 | /* |
| 406 | − * Set the indirect branch tracking configuration. PR_INDIR_BR_LP_ENABLE will | |
| 407 | − * enable cpu feature for user thread, to track all indirect branches and ensure | |
| 408 | − * they land on arch defined landing pad instruction. | |
| 409 | − * x86 - If enabled, an indirect branch must land on an ENDBRANCH instruction. | |
| 410 | − * arch64 - If enabled, an indirect branch must land on a BTI instruction. | |
| 411 | − * riscv - If enabled, an indirect branch must land on an lpad instruction. | |
| 412 | − * PR_INDIR_BR_LP_DISABLE will disable feature for user thread and indirect | |
| 413 | − * branches will no more be tracked by cpu to land on arch defined landing pad | |
| 414 | − * instruction. | |
| 415 | − */ | |
| 416 | −#define PR_SET_INDIR_BR_LP_STATUS 81 | |
| 417 | −# define PR_INDIR_BR_LP_ENABLE (1UL << 0) | |
| 418 | − | |
| 419 | −/* | |
| 420 | − * Prevent further changes to the specified indirect branch tracking | |
| 421 | − * configuration. All bits may be locked via this call, including | |
| 422 | − * undefined bits. | |
| 410 | + * Forward-edge CFI variants (excluding ARM64 BTI, which has its own | |
| 411 | + * prctl()s). | |
| 423 | 412 | */ |
| 424 | −#define PR_LOCK_INDIR_BR_LP_STATUS 82 | |
| 413 | +#define PR_CFI_BRANCH_LANDING_PADS 0 | |
| 414 | +/* Return and control values for PR_{GET,SET}_CFI */ | |
| 415 | +# define PR_CFI_ENABLE _BITUL(0) | |
| 416 | +# define PR_CFI_DISABLE _BITUL(1) | |
| 417 | +# define PR_CFI_LOCK _BITUL(2) | |
| 425 | 418 | |
| 426 | 419 | #endif /* _LINUX_PRCTL_H */ |