History

Merge tag 'drm-intel-next-2022-02-08' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Cross-subsystem Changes: ------------------------ dma-buf: - dma-buf-map: Rename to iosys-map (Lucas) Core Changes: ------------- drm: - Always include the debugfs_entry in drm_crtc (Ville) - Add orientation quirk for GPD Win Max (Anisse) Driver Changes: --------------- gvt: - Constify some pointers. (Rikard Falkeborn) - Use list_entry to access list members. (Guenter Roeck) - Fix cmd parser error for Passmark9. (Zhenyu Wang) i915: - Various clean-ups including headers and removing unused and unnecessary stuff\ (Jani, Hans, Andy, Ville) - Cleaning up on our registers definitions i915_reg.h (Matt) - More multi-FBC refactoring (Ville) - Baytrail backlight fix (Hans) - DG1 OPROM read through SPI controller (Clint) - ADL-N platform enabling (Tejas) - Fix slab-out-of-bounds access (Jani) - Add opregion mailbox #5 support for possible EDID override (Anisse) - Fix possible NULL dereferences (Harish) - Updates and fixes around display voltage swing values (Clint, Jose) - Fix RPM wekeref on PXP code (Juston) - Many register definitions clean-up, including planes registers (Ville) - More conversion towards display version over the old gen (Madhumitha, Ville) - DP MST ESI handling improvements (Jani) - drm device based logging conversions (Jani) - Prevent divide by zero (Dan) - Introduce ilk_pch_pre_enable for complete modeset abstraction (Ville) - Async flip optimization for DG2 (Stanislav) - Multiple DSC and bigjoiner fixes and improvements (Ville) - Fix ADL-P TypeC Phy ready status readout (Imre) - Fix up DP DFP 4:2:0 handling more display related fixes (Ville) - Display M/N cleanup (Ville) - Switch to use VGA definitions from video/vga.h (Jani) - Fixes and improvements to abstract CPU architecture (Lucas) - Disable unsused power wells left enabled by BIOS (Imre) - Allow !join_mbus cases for adlp+ dbuf configuration (Ville) - Populate pipe dbuf slices more accurately during readout (Ville) - Workaround broken BIOS DBUF configuration on TGL/RKL (Ville) - Fix trailing semicolon (Lucas) Signed-off-by: Dave Airlie <airlied@redhat.com>

Dave Airlie committed 4 years ago

Commit e7a09ce2 parents 53dbee4 7938f42273 files · +6341 −5854Browse files

Unified · Split

273 files
  1. Documentation/driver-api/device-io.rst +9 −0
  2. Documentation/driver-api/dma-buf.rst +0 −9
  3. Documentation/gpu/todo.rst +10 −10
  4. MAINTAINERS +8 −1
  5. arch/x86/kernel/early-quirks.c +1 −0
  6. drivers/dma-buf/dma-buf.c +11 −11
  7. drivers/dma-buf/heaps/cma_heap.c +5 −5
  8. drivers/dma-buf/heaps/system_heap.c +5 −5
  9. drivers/gpu/drm/ast/ast_drv.h +1 −1
  10. drivers/gpu/drm/ast/ast_mode.c +4 −4
  11. drivers/gpu/drm/drm_cache.c +9 −9
  12. drivers/gpu/drm/drm_client.c +5 −4
  13. drivers/gpu/drm/drm_fb_helper.c +6 −6
  14. drivers/gpu/drm/drm_gem.c +6 −6
  15. drivers/gpu/drm/drm_gem_cma_helper.c +5 −4
  16. drivers/gpu/drm/drm_gem_framebuffer_helper.c +8 −8
  17. drivers/gpu/drm/drm_gem_shmem_helper.c +9 −6
  18. drivers/gpu/drm/drm_gem_ttm_helper.c +2 −2
  19. drivers/gpu/drm/drm_gem_vram_helper.c +14 −11
  20. drivers/gpu/drm/drm_internal.h +3 −3
  21. drivers/gpu/drm/drm_mipi_dbi.c +4 −4
  22. drivers/gpu/drm/drm_panel_orientation_quirks.c +6 −0
  23. drivers/gpu/drm/drm_prime.c +2 −2
  24. drivers/gpu/drm/etnaviv/etnaviv_drv.h +1 −1
  25. drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c +4 −4
  26. drivers/gpu/drm/gud/gud_pipe.c +2 −2
  27. drivers/gpu/drm/hyperv/hyperv_drm_modeset.c +3 −2
  28. drivers/gpu/drm/i915/Makefile +2 −1
  29. drivers/gpu/drm/i915/display/g4x_dp.c +17 −1
  30. drivers/gpu/drm/i915/display/g4x_hdmi.h +1 −1
  31. drivers/gpu/drm/i915/display/i9xx_plane.c +52 −53
  32. drivers/gpu/drm/i915/display/icl_dsi.c +3 −4
  33. drivers/gpu/drm/i915/display/intel_atomic.c +2 −0
  34. drivers/gpu/drm/i915/display/intel_atomic_plane.c +5 −3
  35. drivers/gpu/drm/i915/display/intel_atomic_plane.h +1 −0
  36. drivers/gpu/drm/i915/display/intel_backlight.c +3 −0
  37. drivers/gpu/drm/i915/display/intel_bios.c +92 −123
  38. drivers/gpu/drm/i915/display/intel_bw.c +6 −8
  39. drivers/gpu/drm/i915/display/intel_cdclk.c +38 −27
  40. drivers/gpu/drm/i915/display/intel_cdclk.h +7 −2
  41. drivers/gpu/drm/i915/display/intel_combo_phy.c +1 −0
  42. drivers/gpu/drm/i915/display/intel_combo_phy_regs.h +162 −0
  43. drivers/gpu/drm/i915/display/intel_crt.h +1 −1
  44. drivers/gpu/drm/i915/display/intel_crtc.c +1 −0
  45. drivers/gpu/drm/i915/display/intel_cursor.c +12 −13
  46. drivers/gpu/drm/i915/display/intel_ddi.c +16 −127
  47. drivers/gpu/drm/i915/display/intel_ddi.h +1 −1
  48. drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +21 −21
  49. drivers/gpu/drm/i915/display/intel_de.h +0 −1
  50. drivers/gpu/drm/i915/display/intel_display.c +275 −296
  51. drivers/gpu/drm/i915/display/intel_display.h +27 −9
  52. drivers/gpu/drm/i915/display/intel_display_debugfs.c +5 −2
  53. drivers/gpu/drm/i915/display/intel_display_power.c +37 −8
  54. drivers/gpu/drm/i915/display/intel_display_power.h +1 −1
  55. drivers/gpu/drm/i915/display/intel_display_trace.h +1 −0
  56. drivers/gpu/drm/i915/display/intel_display_types.h +3 −19
  57. drivers/gpu/drm/i915/display/intel_dmc.c +7 −7
  58. drivers/gpu/drm/i915/display/intel_dmc.h +1 −1
  59. drivers/gpu/drm/i915/display/intel_dp.c +98 −67
  60. drivers/gpu/drm/i915/display/intel_dp.h +0 −2
  61. drivers/gpu/drm/i915/display/intel_dp_aux.c +4 −4
  62. drivers/gpu/drm/i915/display/intel_dp_aux.h +0 −4
  63. drivers/gpu/drm/i915/display/intel_dp_mst.c +0 −2
  64. drivers/gpu/drm/i915/display/intel_dpll_mgr.c +36 −0
  65. drivers/gpu/drm/i915/display/intel_dpll_mgr.h +1 −45
  66. drivers/gpu/drm/i915/display/intel_drrs.c +71 −44
  67. drivers/gpu/drm/i915/display/intel_dsb.h +1 −1
  68. drivers/gpu/drm/i915/display/intel_dsi_vbt.c +11 −18
  69. drivers/gpu/drm/i915/display/intel_dvo_dev.h +1 −1
  70. drivers/gpu/drm/i915/display/intel_fbc.c +143 −95
  71. drivers/gpu/drm/i915/display/intel_fbc.h +7 −0
  72. drivers/gpu/drm/i915/display/intel_gmbus.c +0 −7
  73. drivers/gpu/drm/i915/display/intel_gmbus.h +0 −1
  74. drivers/gpu/drm/i915/display/intel_hdcp.c +1 −2
  75. drivers/gpu/drm/i915/display/intel_hdmi.c +62 −38
  76. drivers/gpu/drm/i915/display/intel_hdmi.h +2 −4
  77. drivers/gpu/drm/i915/display/intel_hotplug.c +7 −7
  78. drivers/gpu/drm/i915/display/intel_lspcon.c +77 −67
  79. drivers/gpu/drm/i915/display/intel_lvds.h +1 −1
  80. drivers/gpu/drm/i915/display/intel_opregion.c +55 −1
  81. drivers/gpu/drm/i915/display/intel_opregion.h +10 −0
  82. drivers/gpu/drm/i915/display/intel_overlay.c +4 −0
  83. drivers/gpu/drm/i915/display/intel_pch_display.c +76 −12
  84. drivers/gpu/drm/i915/display/intel_pch_display.h +8 −0
  85. drivers/gpu/drm/i915/display/intel_pps.c +13 −9
  86. drivers/gpu/drm/i915/display/intel_sdvo.h +1 −1
  87. drivers/gpu/drm/i915/display/intel_snps_phy.c +16 −14
  88. drivers/gpu/drm/i915/display/intel_snps_phy_regs.h +75 −0
  89. drivers/gpu/drm/i915/display/intel_sprite.c +39 −26
  90. drivers/gpu/drm/i915/display/intel_tc.c +4 −1
  91. drivers/gpu/drm/i915/display/intel_tc_phy_regs.h +280 −0
  92. drivers/gpu/drm/i915/display/intel_vbt_defs.h +0 −26
  93. drivers/gpu/drm/i915/display/intel_vdsc.c +1 −6
  94. drivers/gpu/drm/i915/display/intel_vga.c +5 −4
  95. drivers/gpu/drm/i915/display/skl_universal_plane.c +107 −88
  96. drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c +5 −3
  97. drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +2 −0
  98. drivers/gpu/drm/i915/gem/i915_gem_stolen.c +1 −0
  99. drivers/gpu/drm/i915/gem/i915_gem_tiling.c +2 −0
  100. drivers/gpu/drm/i915/gem/i915_gem_tiling.h +18 −0
  101. drivers/gpu/drm/i915/gem/i915_gem_userptr.c +1 −0
  102. drivers/gpu/drm/i915/gem/i915_gem_userptr.h +14 −0
  103. drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +2 −1
  104. drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +2 −1
  105. drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c +3 −3
  106. drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c +3 −3
  107. drivers/gpu/drm/i915/gt/gen2_engine_cs.c +2 −0
  108. drivers/gpu/drm/i915/gt/gen6_engine_cs.c +1 −0
  109. drivers/gpu/drm/i915/gt/gen6_ppgtt.c +2 −0
  110. drivers/gpu/drm/i915/gt/gen7_renderclear.c +1 −0
  111. drivers/gpu/drm/i915/gt/gen8_engine_cs.c +2 −1
  112. drivers/gpu/drm/i915/gt/intel_engine.h +0 −1
  113. drivers/gpu/drm/i915/gt/intel_engine_cs.c +3 −1
  114. drivers/gpu/drm/i915/gt/intel_engine_regs.h +223 −0
  115. drivers/gpu/drm/i915/gt/intel_execlists_submission.c +2 −0
  116. drivers/gpu/drm/i915/gt/intel_ggtt.c +1 −0
  117. drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +2 −0
  118. drivers/gpu/drm/i915/gt/intel_gt.c +3 −1
  119. drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c +2 −0
  120. drivers/gpu/drm/i915/gt/intel_gt_irq.c +1 −1
  121. drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +5 −5
  122. drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c +1 −0
  123. drivers/gpu/drm/i915/gt/intel_gt_regs.h +1554 −0
  124. drivers/gpu/drm/i915/gt/intel_gtt.c +1 −0
  125. drivers/gpu/drm/i915/gt/intel_llc.c +5 −5
  126. drivers/gpu/drm/i915/gt/intel_lrc.c +2 −0
  127. drivers/gpu/drm/i915/gt/intel_lrc_reg.h +0 −15
  128. drivers/gpu/drm/i915/gt/intel_mocs.c +1 −1
  129. drivers/gpu/drm/i915/gt/intel_rc6.c +9 −7
  130. drivers/gpu/drm/i915/gt/intel_rc6.h +1 −1
  131. drivers/gpu/drm/i915/gt/intel_region_lmem.c +1 −0
  132. drivers/gpu/drm/i915/gt/intel_reset.c +4 −0
  133. drivers/gpu/drm/i915/gt/intel_ring.c +1 −0
  134. drivers/gpu/drm/i915/gt/intel_ring_submission.c +7 −5
  135. drivers/gpu/drm/i915/gt/intel_rps.c +5 −5
  136. drivers/gpu/drm/i915/gt/intel_sseu.c +2 −1
  137. drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c +1 −0
  138. drivers/gpu/drm/i915/gt/intel_workarounds.c +5 −3
  139. drivers/gpu/drm/i915/gt/intel_workarounds_types.h +1 −1
  140. drivers/gpu/drm/i915/gt/selftest_engine_pm.c +1 −0
  141. drivers/gpu/drm/i915/gt/selftest_gt_pm.c +1 −0
  142. drivers/gpu/drm/i915/gt/selftest_hangcheck.c +1 −0
  143. drivers/gpu/drm/i915/gt/selftest_llc.c +2 −3
  144. drivers/gpu/drm/i915/gt/selftest_rps.c +3 −3
  145. drivers/gpu/drm/i915/gt/selftest_timeline.c +1 −0
  146. drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h +0 −1
  147. drivers/gpu/drm/i915/gt/uc/intel_guc.c +2 −0
  148. drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +2 −0
  149. drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c +1 −0
  150. drivers/gpu/drm/i915/gt/uc/intel_guc_log.c +1 −0
  151. drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h +1 −1
  152. drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +2 −0
  153. drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +3 −1
  154. drivers/gpu/drm/i915/gt/uc/intel_huc.h +1 −1
  155. drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +1 −0
  156. drivers/gpu/drm/i915/gvt/aperture_gm.c +1 −0
  157. drivers/gpu/drm/i915/gvt/cmd_parser.c +3 −1
  158. drivers/gpu/drm/i915/gvt/display.c +9 −8
  159. drivers/gpu/drm/i915/gvt/dmabuf.c +6 −13
  160. drivers/gpu/drm/i915/gvt/edid.c +1 −0
  161. drivers/gpu/drm/i915/gvt/fb_decoder.c +25 −24
  162. drivers/gpu/drm/i915/gvt/gtt.c +36 −34
  163. drivers/gpu/drm/i915/gvt/gtt.h +2 −2
  164. drivers/gpu/drm/i915/gvt/gvt.h +1 −1
  165. drivers/gpu/drm/i915/gvt/handlers.c +20 −16
  166. drivers/gpu/drm/i915/gvt/interrupt.c +6 −5
  167. drivers/gpu/drm/i915/gvt/interrupt.h +2 −2
  168. drivers/gpu/drm/i915/gvt/mmio.c +3 −0
  169. drivers/gpu/drm/i915/gvt/mmio_context.c +4 −2
  170. drivers/gpu/drm/i915/gvt/mmio_context.h +1 −1
  171. drivers/gpu/drm/i915/gvt/reg.h +0 −1
  172. drivers/gpu/drm/i915/gvt/sched_policy.c +1 −1
  173. drivers/gpu/drm/i915/gvt/scheduler.c +2 −0
  174. drivers/gpu/drm/i915/gvt/scheduler.h +1 −1
  175. drivers/gpu/drm/i915/gvt/vgpu.c +2 −2
  176. drivers/gpu/drm/i915/i915_cmd_parser.c +42 −34
  177. drivers/gpu/drm/i915/i915_cmd_parser.h +26 −0
  178. drivers/gpu/drm/i915/i915_debugfs.c +1 −0
  179. drivers/gpu/drm/i915/i915_driver.c +3 −0
  180. drivers/gpu/drm/i915/i915_drv.h +16 −74
  181. drivers/gpu/drm/i915/i915_gem.c +1 −0
  182. drivers/gpu/drm/i915/i915_gem_evict.c +1 −0
  183. drivers/gpu/drm/i915/i915_gem_evict.h +24 −0
  184. drivers/gpu/drm/i915/i915_gem_gtt.c +1 −0
  185. drivers/gpu/drm/i915/i915_getparam.c +2 −0
  186. drivers/gpu/drm/i915/i915_getparam.h +15 −0
  187. drivers/gpu/drm/i915/i915_gpu_error.c +2 −0
  188. drivers/gpu/drm/i915/i915_ioc32.c +1 −0
  189. drivers/gpu/drm/i915/i915_ioctl.c +94 −0
  190. drivers/gpu/drm/i915/i915_ioctl.h +14 −0
  191. drivers/gpu/drm/i915/i915_irq.c +3 −5
  192. drivers/gpu/drm/i915/i915_mm.h +2 −2
  193. drivers/gpu/drm/i915/i915_pci.c +13 −11
  194. drivers/gpu/drm/i915/i915_perf.c +88 −49
  195. drivers/gpu/drm/i915/i915_perf_oa_regs.h +137 −0
  196. drivers/gpu/drm/i915/i915_perf_types.h +1 −1
  197. drivers/gpu/drm/i915/i915_pmu.c +2 −0
  198. drivers/gpu/drm/i915/i915_reg.h +506 −3596
  199. drivers/gpu/drm/i915/i915_reg_defs.h +101 −0
  200. drivers/gpu/drm/i915/i915_request.c +1 −0
  201. drivers/gpu/drm/i915/i915_suspend.c +1 −0
  202. drivers/gpu/drm/i915/i915_sysfs.c +1 −0
  203. drivers/gpu/drm/i915/i915_utils.h +0 −15
  204. drivers/gpu/drm/i915/i915_vma.c +2 −1
  205. drivers/gpu/drm/i915/intel_device_info.c +11 −2
  206. drivers/gpu/drm/i915/intel_device_info.h +4 −1
  207. drivers/gpu/drm/i915/intel_dram.c +3 −4
  208. drivers/gpu/drm/i915/intel_pci_config.h +85 −0
  209. drivers/gpu/drm/i915/intel_pcode.c +12 −20
  210. drivers/gpu/drm/i915/intel_pcode.h +5 −7
  211. drivers/gpu/drm/i915/intel_pm.c +256 −141
  212. drivers/gpu/drm/i915/intel_pm.h +1 −1
  213. drivers/gpu/drm/i915/intel_runtime_pm.c +1 −6
  214. drivers/gpu/drm/i915/intel_sbi.c +1 −0
  215. drivers/gpu/drm/i915/intel_uncore.c +2 −71
  216. drivers/gpu/drm/i915/intel_uncore.h +1 −1
  217. drivers/gpu/drm/i915/pxp/intel_pxp_irq.c +1 −0
  218. drivers/gpu/drm/i915/vlv_sideband.c +1 −0
  219. drivers/gpu/drm/i915/vlv_sideband.h +2 −0
  220. drivers/gpu/drm/i915/vlv_sideband_reg.h +180 −0
  221. drivers/gpu/drm/i915/vlv_suspend.c +2 −0
  222. drivers/gpu/drm/lima/lima_gem.c +2 −1
  223. drivers/gpu/drm/lima/lima_sched.c +2 −2
  224. drivers/gpu/drm/mediatek/mtk_drm_gem.c +4 −3
  225. drivers/gpu/drm/mediatek/mtk_drm_gem.h +3 −2
  226. drivers/gpu/drm/mgag200/mgag200_mode.c +2 −2
  227. drivers/gpu/drm/msm/msm_drv.h +2 −2
  228. drivers/gpu/drm/msm/msm_gem_prime.c +3 −3
  229. drivers/gpu/drm/panfrost/panfrost_perfcnt.c +7 −6
  230. drivers/gpu/drm/qxl/qxl_display.c +4 −4
  231. drivers/gpu/drm/qxl/qxl_draw.c +3 −3
  232. drivers/gpu/drm/qxl/qxl_drv.h +5 −5
  233. drivers/gpu/drm/qxl/qxl_object.c +4 −4
  234. drivers/gpu/drm/qxl/qxl_object.h +2 −2
  235. drivers/gpu/drm/qxl/qxl_prime.c +2 −2
  236. drivers/gpu/drm/radeon/radeon_gem.c +1 −0
  237. drivers/gpu/drm/rockchip/rockchip_drm_gem.c +5 −4
  238. drivers/gpu/drm/rockchip/rockchip_drm_gem.h +3 −2
  239. drivers/gpu/drm/tegra/gem.c +5 −5
  240. drivers/gpu/drm/tiny/cirrus.c +5 −3
  241. drivers/gpu/drm/tiny/gm12u320.c +4 −3
  242. drivers/gpu/drm/ttm/ttm_bo_util.c +8 −8
  243. drivers/gpu/drm/ttm/ttm_resource.c +21 −21
  244. drivers/gpu/drm/ttm/ttm_tt.c +4 −4
  245. drivers/gpu/drm/udl/udl_modeset.c +2 −1
  246. drivers/gpu/drm/vboxvideo/vbox_mode.c +2 −2
  247. drivers/gpu/drm/vkms/vkms_composer.c +2 −2
  248. drivers/gpu/drm/vkms/vkms_drv.h +3 −3
  249. drivers/gpu/drm/vkms/vkms_plane.c +1 −1
  250. drivers/gpu/drm/vkms/vkms_writeback.c +1 −1
  251. drivers/gpu/drm/xen/xen_drm_front_gem.c +4 −3
  252. drivers/gpu/drm/xen/xen_drm_front_gem.h +3 −3
  253. drivers/media/common/videobuf2/videobuf2-dma-contig.c +4 −4
  254. drivers/media/common/videobuf2/videobuf2-dma-sg.c +5 −4
  255. drivers/media/common/videobuf2/videobuf2-vmalloc.c +6 −5
  256. drivers/misc/fastrpc.c +2 −2
  257. include/drm/drm_cache.h +3 −3
  258. include/drm/drm_client.h +4 −3
  259. include/drm/drm_crtc.h +0 −2
  260. include/drm/drm_gem.h +3 −3
  261. include/drm/drm_gem_atomic_helper.h +3 −3
  262. include/drm/drm_gem_cma_helper.h +4 −2
  263. include/drm/drm_gem_framebuffer_helper.h +4 −4
  264. include/drm/drm_gem_shmem_helper.h +8 −4
  265. include/drm/drm_gem_ttm_helper.h +3 −3
  266. include/drm/drm_gem_vram_helper.h +5 −4
  267. include/drm/drm_prime.h +3 −3
  268. include/drm/i915_pciids.h +6 −0
  269. include/drm/ttm/ttm_bo_api.h +5 −5
  270. include/drm/ttm/ttm_kmap_iter.h +5 −5
  271. include/drm/ttm/ttm_resource.h +3 −3
  272. include/linux/dma-buf.h +6 −6
  273. include/linux/iosys-map.h +257 −0
Documentation/driver-api/device-io.rst+9−0
@@ -502,6 +502,15 @@ pcim_iomap() · 501 unmodified lines
502502 Not using these wrappers may make drivers unusable on certain platforms with
503503 stricter rules for mapping I/O memory.
504504
505+Generalizing Access to System and I/O Memory
506+============================================
507+
508+.. kernel-doc:: include/linux/iosys-map.h
509+ :doc: overview
510+
511+.. kernel-doc:: include/linux/iosys-map.h
512+ :internal:
513+
505514 Public Functions Provided
506515 =========================
507516
Documentation/driver-api/dma-buf.rst+0−9
@@ -128,15 +128,6 @@ Kernel Functions and Structures Reference · 127 unmodified lines
128128 .. kernel-doc:: include/linux/dma-buf.h
129129 :internal:
130130
131−Buffer Mapping Helpers
132−~~~~~~~~~~~~~~~~~~~~~~
133−
134−.. kernel-doc:: include/linux/dma-buf-map.h
135− :doc: overview
136−
137−.. kernel-doc:: include/linux/dma-buf-map.h
138− :internal:
139−
140131 Reservation Objects
141132 -------------------
142133
Documentation/gpu/todo.rst+10−10
@@ -222,7 +222,7 @@ Convert drivers to use drm_fbdev_generic_setup() · 221 unmodified lines
222222 Most drivers can use drm_fbdev_generic_setup(). Driver have to implement
223223 atomic modesetting and GEM vmap support. Historically, generic fbdev emulation
224224 expected the framebuffer in system memory or system-like memory. By employing
225−struct dma_buf_map, drivers with frambuffers in I/O memory can be supported
225+struct iosys_map, drivers with frambuffers in I/O memory can be supported
226226 as well.
227227
228228 Contact: Maintainer of the driver you plan to convert
@@ -234,7 +234,7 @@ Reimplement functions in drm_fbdev_fb_ops without fbdev · 5 unmodified lines
234234
235235 A number of callback functions in drm_fbdev_fb_ops could benefit from
236236 being rewritten without dependencies on the fbdev module. Some of the
237−helpers could further benefit from using struct dma_buf_map instead of
237+helpers could further benefit from using struct iosys_map instead of
238238 raw pointers.
239239
240240 Contact: Thomas Zimmermann <tzimmermann@suse.de>, Daniel Vetter
@@ -434,19 +434,19 @@ Contact: Emil Velikov, respective driver maintainers · 193 unmodified lines
434434
435435 Level: Intermediate
436436
437−Use struct dma_buf_map throughout codebase
438−------------------------------------------
437+Use struct iosys_map throughout codebase
438+----------------------------------------
439439
440−Pointers to shared device memory are stored in struct dma_buf_map. Each
440+Pointers to shared device memory are stored in struct iosys_map. Each
441441 instance knows whether it refers to system or I/O memory. Most of the DRM-wide
442−interface have been converted to use struct dma_buf_map, but implementations
442+interface have been converted to use struct iosys_map, but implementations
443443 often still use raw pointers.
444444
445−The task is to use struct dma_buf_map where it makes sense.
445+The task is to use struct iosys_map where it makes sense.
446446
447−* Memory managers should use struct dma_buf_map for dma-buf-imported buffers.
448−* TTM might benefit from using struct dma_buf_map internally.
449−* Framebuffer copying and blitting helpers should operate on struct dma_buf_map.
447+* Memory managers should use struct iosys_map for dma-buf-imported buffers.
448+* TTM might benefit from using struct iosys_map internally.
449+* Framebuffer copying and blitting helpers should operate on struct iosys_map.
450450
451451 Contact: Thomas Zimmermann <tzimmermann@suse.de>, Christian König, Daniel Vetter
452452
MAINTAINERS+8−1
@@ -5734,7 +5734,7 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 5733 unmodified lines
57345734 F: Documentation/driver-api/dma-buf.rst
57355735 F: drivers/dma-buf/
57365736 F: include/linux/*fence.h
5737−F: include/linux/dma-buf*
5737+F: include/linux/dma-buf.h
57385738 F: include/linux/dma-resv.h
57395739 K: \bdma_(?:buf|fence|resv)\b
57405740
@@ -10050,6 +10050,13 @@ F: include/linux/iova.h · 4309 unmodified lines
1005010050 F: include/linux/of_iommu.h
1005110051 F: include/uapi/linux/iommu.h
1005210052
10053+IOSYS-MAP HELPERS
10054+M: Thomas Zimmermann <tzimmermann@suse.de>
10055+L: dri-devel@lists.freedesktop.org
10056+S: Maintained
10057+T: git git://anongit.freedesktop.org/drm/drm-misc
10058+F: include/linux/iosys-map.h
10059+
1005310060 IO_URING
1005410061 M: Jens Axboe <axboe@kernel.dk>
1005510062 R: Pavel Begunkov <asml.silence@gmail.com>
arch/x86/kernel/early-quirks.c+1−0
@@ -555,6 +555,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { · 554 unmodified lines
555555 INTEL_RKL_IDS(&gen11_early_ops),
556556 INTEL_ADLS_IDS(&gen11_early_ops),
557557 INTEL_ADLP_IDS(&gen11_early_ops),
558+ INTEL_ADLN_IDS(&gen11_early_ops),
558559 INTEL_RPLS_IDS(&gen11_early_ops),
559560 };
560561
drivers/dma-buf/dma-buf.c+11−11
@@ -1047,8 +1047,8 @@ EXPORT_SYMBOL_NS_GPL(dma_buf_move_notify, DMA_BUF); · 1046 unmodified lines
10471047 *
10481048 * Interfaces::
10491049 *
1050− * void \*dma_buf_vmap(struct dma_buf \*dmabuf, struct dma_buf_map \*map)
1051− * void dma_buf_vunmap(struct dma_buf \*dmabuf, struct dma_buf_map \*map)
1050+ * void \*dma_buf_vmap(struct dma_buf \*dmabuf, struct iosys_map \*map)
1051+ * void dma_buf_vunmap(struct dma_buf \*dmabuf, struct iosys_map \*map)
10521052 *
10531053 * The vmap call can fail if there is no vmap support in the exporter, or if
10541054 * it runs out of vmalloc space. Note that the dma-buf layer keeps a reference
@@ -1260,12 +1260,12 @@ EXPORT_SYMBOL_NS_GPL(dma_buf_mmap, DMA_BUF); · 205 unmodified lines
12601260 *
12611261 * Returns 0 on success, or a negative errno code otherwise.
12621262 */
1263−int dma_buf_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map)
1263+int dma_buf_vmap(struct dma_buf *dmabuf, struct iosys_map *map)
12641264 {
1265− struct dma_buf_map ptr;
1265+ struct iosys_map ptr;
12661266 int ret = 0;
12671267
1268− dma_buf_map_clear(map);
1268+ iosys_map_clear(map);
12691269
12701270 if (WARN_ON(!dmabuf))
12711271 return -EINVAL;
@@ -1276,12 +1276,12 @@ int dma_buf_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 4 unmodified lines
12761276 mutex_lock(&dmabuf->lock);
12771277 if (dmabuf->vmapping_counter) {
12781278 dmabuf->vmapping_counter++;
1279− BUG_ON(dma_buf_map_is_null(&dmabuf->vmap_ptr));
1279+ BUG_ON(iosys_map_is_null(&dmabuf->vmap_ptr));
12801280 *map = dmabuf->vmap_ptr;
12811281 goto out_unlock;
12821282 }
12831283
1284− BUG_ON(dma_buf_map_is_set(&dmabuf->vmap_ptr));
1284+ BUG_ON(iosys_map_is_set(&dmabuf->vmap_ptr));
12851285
12861286 ret = dmabuf->ops->vmap(dmabuf, &ptr);
12871287 if (WARN_ON_ONCE(ret))
@@ -1303,20 +1303,20 @@ EXPORT_SYMBOL_NS_GPL(dma_buf_vmap, DMA_BUF); · 15 unmodified lines
13031303 * @dmabuf: [in] buffer to vunmap
13041304 * @map: [in] vmap pointer to vunmap
13051305 */
1306−void dma_buf_vunmap(struct dma_buf *dmabuf, struct dma_buf_map *map)
1306+void dma_buf_vunmap(struct dma_buf *dmabuf, struct iosys_map *map)
13071307 {
13081308 if (WARN_ON(!dmabuf))
13091309 return;
13101310
1311− BUG_ON(dma_buf_map_is_null(&dmabuf->vmap_ptr));
1311+ BUG_ON(iosys_map_is_null(&dmabuf->vmap_ptr));
13121312 BUG_ON(dmabuf->vmapping_counter == 0);
1313− BUG_ON(!dma_buf_map_is_equal(&dmabuf->vmap_ptr, map));
1313+ BUG_ON(!iosys_map_is_equal(&dmabuf->vmap_ptr, map));
13141314
13151315 mutex_lock(&dmabuf->lock);
13161316 if (--dmabuf->vmapping_counter == 0) {
13171317 if (dmabuf->ops->vunmap)
13181318 dmabuf->ops->vunmap(dmabuf, map);
1319− dma_buf_map_clear(&dmabuf->vmap_ptr);
1319+ iosys_map_clear(&dmabuf->vmap_ptr);
13201320 }
13211321 mutex_unlock(&dmabuf->lock);
13221322 }
drivers/dma-buf/heaps/cma_heap.c+5−5
@@ -202,7 +202,7 @@ static void *cma_heap_do_vmap(struct cma_heap_buffer *buffer) · 201 unmodified lines
202202 return vaddr;
203203 }
204204
205−static int cma_heap_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map)
205+static int cma_heap_vmap(struct dma_buf *dmabuf, struct iosys_map *map)
206206 {
207207 struct cma_heap_buffer *buffer = dmabuf->priv;
208208 void *vaddr;
@@ -211,7 +211,7 @@ static int cma_heap_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 2 unmodified lines
211211 mutex_lock(&buffer->lock);
212212 if (buffer->vmap_cnt) {
213213 buffer->vmap_cnt++;
214− dma_buf_map_set_vaddr(map, buffer->vaddr);
214+ iosys_map_set_vaddr(map, buffer->vaddr);
215215 goto out;
216216 }
217217
@@ -222,14 +222,14 @@ static int cma_heap_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 4 unmodified lines
222222 }
223223 buffer->vaddr = vaddr;
224224 buffer->vmap_cnt++;
225− dma_buf_map_set_vaddr(map, buffer->vaddr);
225+ iosys_map_set_vaddr(map, buffer->vaddr);
226226 out:
227227 mutex_unlock(&buffer->lock);
228228
229229 return ret;
230230 }
231231
232−static void cma_heap_vunmap(struct dma_buf *dmabuf, struct dma_buf_map *map)
232+static void cma_heap_vunmap(struct dma_buf *dmabuf, struct iosys_map *map)
233233 {
234234 struct cma_heap_buffer *buffer = dmabuf->priv;
235235
@@ -239,7 +239,7 @@ static void cma_heap_vunmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 3 unmodified lines
239239 buffer->vaddr = NULL;
240240 }
241241 mutex_unlock(&buffer->lock);
242− dma_buf_map_clear(map);
242+ iosys_map_clear(map);
243243 }
244244
245245 static void cma_heap_dma_buf_release(struct dma_buf *dmabuf)
drivers/dma-buf/heaps/system_heap.c+5−5
@@ -241,7 +241,7 @@ static void *system_heap_do_vmap(struct system_heap_buffer *buffer) · 240 unmodified lines
241241 return vaddr;
242242 }
243243
244−static int system_heap_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map)
244+static int system_heap_vmap(struct dma_buf *dmabuf, struct iosys_map *map)
245245 {
246246 struct system_heap_buffer *buffer = dmabuf->priv;
247247 void *vaddr;
@@ -250,7 +250,7 @@ static int system_heap_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 2 unmodified lines
250250 mutex_lock(&buffer->lock);
251251 if (buffer->vmap_cnt) {
252252 buffer->vmap_cnt++;
253− dma_buf_map_set_vaddr(map, buffer->vaddr);
253+ iosys_map_set_vaddr(map, buffer->vaddr);
254254 goto out;
255255 }
256256
@@ -262,14 +262,14 @@ static int system_heap_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 5 unmodified lines
262262
263263 buffer->vaddr = vaddr;
264264 buffer->vmap_cnt++;
265− dma_buf_map_set_vaddr(map, buffer->vaddr);
265+ iosys_map_set_vaddr(map, buffer->vaddr);
266266 out:
267267 mutex_unlock(&buffer->lock);
268268
269269 return ret;
270270 }
271271
272−static void system_heap_vunmap(struct dma_buf *dmabuf, struct dma_buf_map *map)
272+static void system_heap_vunmap(struct dma_buf *dmabuf, struct iosys_map *map)
273273 {
274274 struct system_heap_buffer *buffer = dmabuf->priv;
275275
@@ -279,7 +279,7 @@ static void system_heap_vunmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 3 unmodified lines
279279 buffer->vaddr = NULL;
280280 }
281281 mutex_unlock(&buffer->lock);
282− dma_buf_map_clear(map);
282+ iosys_map_clear(map);
283283 }
284284
285285 static void system_heap_dma_buf_release(struct dma_buf *dmabuf)
drivers/gpu/drm/ast/ast_drv.h+1−1
@@ -107,7 +107,7 @@ struct ast_cursor_plane { · 106 unmodified lines
107107
108108 struct {
109109 struct drm_gem_vram_object *gbo;
110− struct dma_buf_map map;
110+ struct iosys_map map;
111111 u64 off;
112112 } hwc[AST_DEFAULT_HWC_NUM];
113113
drivers/gpu/drm/ast/ast_mode.c+4−4
@@ -804,11 +804,11 @@ ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, · 803 unmodified lines
804804 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(new_state);
805805 struct drm_framebuffer *fb = new_state->fb;
806806 struct ast_private *ast = to_ast_private(plane->dev);
807− struct dma_buf_map dst_map =
807+ struct iosys_map dst_map =
808808 ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].map;
809809 u64 dst_off =
810810 ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].off;
811− struct dma_buf_map src_map = shadow_plane_state->data[0];
811+ struct iosys_map src_map = shadow_plane_state->data[0];
812812 unsigned int offset_x, offset_y;
813813 u16 x, y;
814814 u8 x_offset, y_offset;
@@ -886,7 +886,7 @@ static void ast_cursor_plane_destroy(struct drm_plane *plane) · 71 unmodified lines
886886 struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane);
887887 size_t i;
888888 struct drm_gem_vram_object *gbo;
889− struct dma_buf_map map;
889+ struct iosys_map map;
890890
891891 for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) {
892892 gbo = ast_cursor_plane->hwc[i].gbo;
@@ -913,7 +913,7 @@ static int ast_cursor_plane_init(struct ast_private *ast) · 20 unmodified lines
913913 struct drm_plane *cursor_plane = &ast_cursor_plane->base;
914914 size_t size, i;
915915 struct drm_gem_vram_object *gbo;
916− struct dma_buf_map map;
916+ struct iosys_map map;
917917 int ret;
918918 s64 off;
919919
drivers/gpu/drm/drm_cache.c+9−9
@@ -28,10 +28,10 @@ · 27 unmodified lines
2828 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
2929 */
3030
31−#include <linux/dma-buf-map.h>
31+#include <linux/cc_platform.h>
3232 #include <linux/export.h>
3333 #include <linux/highmem.h>
34−#include <linux/cc_platform.h>
34+#include <linux/iosys-map.h>
3535 #include <xen/xen.h>
3636
3737 #include <drm/drm_cache.h>
@@ -214,14 +214,14 @@ bool drm_need_swiotlb(int dma_bits) · 176 unmodified lines
214214 }
215215 EXPORT_SYMBOL(drm_need_swiotlb);
216216
217−static void memcpy_fallback(struct dma_buf_map *dst,
218− const struct dma_buf_map *src,
217+static void memcpy_fallback(struct iosys_map *dst,
218+ const struct iosys_map *src,
219219 unsigned long len)
220220 {
221221 if (!dst->is_iomem && !src->is_iomem) {
222222 memcpy(dst->vaddr, src->vaddr, len);
223223 } else if (!src->is_iomem) {
224− dma_buf_map_memcpy_to(dst, src->vaddr, len);
224+ iosys_map_memcpy_to(dst, src->vaddr, len);
225225 } else if (!dst->is_iomem) {
226226 memcpy_fromio(dst->vaddr, src->vaddr_iomem, len);
227227 } else {
@@ -305,8 +305,8 @@ static void __drm_memcpy_from_wc(void *dst, const void *src, unsigned long len) · 77 unmodified lines
305305 * Tries an arch optimized memcpy for prefetching reading out of a WC region,
306306 * and if no such beast is available, falls back to a normal memcpy.
307307 */
308−void drm_memcpy_from_wc(struct dma_buf_map *dst,
309− const struct dma_buf_map *src,
308+void drm_memcpy_from_wc(struct iosys_map *dst,
309+ const struct iosys_map *src,
310310 unsigned long len)
311311 {
312312 if (WARN_ON(in_interrupt())) {
@@ -343,8 +343,8 @@ void drm_memcpy_init_early(void) · 30 unmodified lines
343343 static_branch_enable(&has_movntdqa);
344344 }
345345 #else
346−void drm_memcpy_from_wc(struct dma_buf_map *dst,
347− const struct dma_buf_map *src,
346+void drm_memcpy_from_wc(struct iosys_map *dst,
347+ const struct iosys_map *src,
348348 unsigned long len)
349349 {
350350 WARN_ON(in_interrupt());
drivers/gpu/drm/drm_client.c+5−4
@@ -3,7 +3,7 @@ · 2 unmodified lines
33 * Copyright 2018 Noralf Trønnes
44 */
55
6−#include <linux/dma-buf-map.h>
6+#include <linux/iosys-map.h>
77 #include <linux/list.h>
88 #include <linux/module.h>
99 #include <linux/mutex.h>
@@ -309,9 +309,10 @@ err_delete: · 299 unmodified lines
309309 * 0 on success, or a negative errno code otherwise.
310310 */
311311 int
312−drm_client_buffer_vmap(struct drm_client_buffer *buffer, struct dma_buf_map *map_copy)
312+drm_client_buffer_vmap(struct drm_client_buffer *buffer,
313+ struct iosys_map *map_copy)
313314 {
314− struct dma_buf_map *map = &buffer->map;
315+ struct iosys_map *map = &buffer->map;
315316 int ret;
316317
317318 /*
@@ -342,7 +343,7 @@ EXPORT_SYMBOL(drm_client_buffer_vmap); · 24 unmodified lines
342343 */
343344 void drm_client_buffer_vunmap(struct drm_client_buffer *buffer)
344345 {
345− struct dma_buf_map *map = &buffer->map;
346+ struct iosys_map *map = &buffer->map;
346347
347348 drm_gem_vunmap(buffer->gem, map);
348349 }
drivers/gpu/drm/drm_fb_helper.c+6−6
@@ -373,7 +373,7 @@ static void drm_fb_helper_resume_worker(struct work_struct *work) · 372 unmodified lines
373373
374374 static void drm_fb_helper_damage_blit_real(struct drm_fb_helper *fb_helper,
375375 struct drm_clip_rect *clip,
376− struct dma_buf_map *dst)
376+ struct iosys_map *dst)
377377 {
378378 struct drm_framebuffer *fb = fb_helper->fb;
379379 unsigned int cpp = fb->format->cpp[0];
@@ -382,11 +382,11 @@ static void drm_fb_helper_damage_blit_real(struct drm_fb_helper *fb_helper, · 2 unmodified lines
382382 size_t len = (clip->x2 - clip->x1) * cpp;
383383 unsigned int y;
384384
385− dma_buf_map_incr(dst, offset); /* go to first pixel within clip rect */
385+ iosys_map_incr(dst, offset); /* go to first pixel within clip rect */
386386
387387 for (y = clip->y1; y < clip->y2; y++) {
388− dma_buf_map_memcpy_to(dst, src, len);
389− dma_buf_map_incr(dst, fb->pitches[0]);
388+ iosys_map_memcpy_to(dst, src, len);
389+ iosys_map_incr(dst, fb->pitches[0]);
390390 src += fb->pitches[0];
391391 }
392392 }
@@ -395,7 +395,7 @@ static int drm_fb_helper_damage_blit(struct drm_fb_helper *fb_helper, · 2 unmodified lines
395395 struct drm_clip_rect *clip)
396396 {
397397 struct drm_client_buffer *buffer = fb_helper->buffer;
398− struct dma_buf_map map, dst;
398+ struct iosys_map map, dst;
399399 int ret;
400400
401401 /*
@@ -2322,7 +2322,7 @@ static int drm_fb_helper_generic_probe(struct drm_fb_helper *fb_helper, · 1920 unmodified lines
23222322 struct drm_framebuffer *fb;
23232323 struct fb_info *fbi;
23242324 u32 format;
2325− struct dma_buf_map map;
2325+ struct iosys_map map;
23262326 int ret;
23272327
23282328 drm_dbg_kms(dev, "surface width(%d), height(%d) and bpp(%d)\n",
drivers/gpu/drm/drm_gem.c+6−6
@@ -36,7 +36,7 @@ · 35 unmodified lines
3636 #include <linux/pagemap.h>
3737 #include <linux/shmem_fs.h>
3838 #include <linux/dma-buf.h>
39−#include <linux/dma-buf-map.h>
39+#include <linux/iosys-map.h>
4040 #include <linux/mem_encrypt.h>
4141 #include <linux/pagevec.h>
4242
@@ -1165,7 +1165,7 @@ void drm_gem_unpin(struct drm_gem_object *obj) · 1122 unmodified lines
11651165 obj->funcs->unpin(obj);
11661166 }
11671167
1168−int drm_gem_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
1168+int drm_gem_vmap(struct drm_gem_object *obj, struct iosys_map *map)
11691169 {
11701170 int ret;
11711171
@@ -1175,23 +1175,23 @@ int drm_gem_vmap(struct drm_gem_object *obj, struct dma_buf_map *map) · 3 unmodified lines
11751175 ret = obj->funcs->vmap(obj, map);
11761176 if (ret)
11771177 return ret;
1178− else if (dma_buf_map_is_null(map))
1178+ else if (iosys_map_is_null(map))
11791179 return -ENOMEM;
11801180
11811181 return 0;
11821182 }
11831183 EXPORT_SYMBOL(drm_gem_vmap);
11841184
1185−void drm_gem_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map)
1185+void drm_gem_vunmap(struct drm_gem_object *obj, struct iosys_map *map)
11861186 {
1187− if (dma_buf_map_is_null(map))
1187+ if (iosys_map_is_null(map))
11881188 return;
11891189
11901190 if (obj->funcs->vunmap)
11911191 obj->funcs->vunmap(obj, map);
11921192
11931193 /* Always set the mapping to NULL. Callers may rely on this. */
1194− dma_buf_map_clear(map);
1194+ iosys_map_clear(map);
11951195 }
11961196 EXPORT_SYMBOL(drm_gem_vunmap);
11971197
drivers/gpu/drm/drm_gem_cma_helper.c+5−4
@@ -209,7 +209,7 @@ drm_gem_cma_create_with_handle(struct drm_file *file_priv, · 208 unmodified lines
209209 void drm_gem_cma_free(struct drm_gem_cma_object *cma_obj)
210210 {
211211 struct drm_gem_object *gem_obj = &cma_obj->base;
212− struct dma_buf_map map = DMA_BUF_MAP_INIT_VADDR(cma_obj->vaddr);
212+ struct iosys_map map = IOSYS_MAP_INIT_VADDR(cma_obj->vaddr);
213213
214214 if (gem_obj->import_attach) {
215215 if (cma_obj->vaddr)
@@ -480,9 +480,10 @@ EXPORT_SYMBOL_GPL(drm_gem_cma_prime_import_sg_table); · 264 unmodified lines
480480 * Returns:
481481 * 0 on success, or a negative error code otherwise.
482482 */
483−int drm_gem_cma_vmap(struct drm_gem_cma_object *cma_obj, struct dma_buf_map *map)
483+int drm_gem_cma_vmap(struct drm_gem_cma_object *cma_obj,
484+ struct iosys_map *map)
484485 {
485− dma_buf_map_set_vaddr(map, cma_obj->vaddr);
486+ iosys_map_set_vaddr(map, cma_obj->vaddr);
486487
487488 return 0;
488489 }
@@ -557,7 +558,7 @@ drm_gem_cma_prime_import_sg_table_vmap(struct drm_device *dev, · 68 unmodified lines
557558 {
558559 struct drm_gem_cma_object *cma_obj;
559560 struct drm_gem_object *obj;
560− struct dma_buf_map map;
561+ struct iosys_map map;
561562 int ret;
562563
563564 ret = dma_buf_vmap(attach->dmabuf, &map);
drivers/gpu/drm/drm_gem_framebuffer_helper.c+8−8
@@ -321,7 +321,7 @@ EXPORT_SYMBOL_GPL(drm_gem_fb_create_with_dirty); · 320 unmodified lines
321321 * @data: returns the data address for each BO, can be NULL
322322 *
323323 * This function maps all buffer objects of the given framebuffer into
324− * kernel address space and stores them in struct dma_buf_map. If the
324+ * kernel address space and stores them in struct iosys_map. If the
325325 * mapping operation fails for one of the BOs, the function unmaps the
326326 * already established mappings automatically.
327327 *
@@ -335,8 +335,8 @@ EXPORT_SYMBOL_GPL(drm_gem_fb_create_with_dirty); · 7 unmodified lines
335335 * 0 on success, or a negative errno code otherwise.
336336 */
337337 int drm_gem_fb_vmap(struct drm_framebuffer *fb,
338− struct dma_buf_map map[static DRM_FORMAT_MAX_PLANES],
339− struct dma_buf_map data[DRM_FORMAT_MAX_PLANES])
338+ struct iosys_map map[static DRM_FORMAT_MAX_PLANES],
339+ struct iosys_map data[DRM_FORMAT_MAX_PLANES])
340340 {
341341 struct drm_gem_object *obj;
342342 unsigned int i;
@@ -345,7 +345,7 @@ int drm_gem_fb_vmap(struct drm_framebuffer *fb, · 2 unmodified lines
345345 for (i = 0; i < DRM_FORMAT_MAX_PLANES; ++i) {
346346 obj = drm_gem_fb_get_obj(fb, i);
347347 if (!obj) {
348− dma_buf_map_clear(&map[i]);
348+ iosys_map_clear(&map[i]);
349349 continue;
350350 }
351351 ret = drm_gem_vmap(obj, &map[i]);
@@ -356,9 +356,9 @@ int drm_gem_fb_vmap(struct drm_framebuffer *fb, · 4 unmodified lines
356356 if (data) {
357357 for (i = 0; i < DRM_FORMAT_MAX_PLANES; ++i) {
358358 memcpy(&data[i], &map[i], sizeof(data[i]));
359− if (dma_buf_map_is_null(&data[i]))
359+ if (iosys_map_is_null(&data[i]))
360360 continue;
361− dma_buf_map_incr(&data[i], fb->offsets[i]);
361+ iosys_map_incr(&data[i], fb->offsets[i]);
362362 }
363363 }
364364
@@ -386,7 +386,7 @@ EXPORT_SYMBOL(drm_gem_fb_vmap); · 21 unmodified lines
386386 * See drm_gem_fb_vmap() for more information.
387387 */
388388 void drm_gem_fb_vunmap(struct drm_framebuffer *fb,
389− struct dma_buf_map map[static DRM_FORMAT_MAX_PLANES])
389+ struct iosys_map map[static DRM_FORMAT_MAX_PLANES])
390390 {
391391 unsigned int i = DRM_FORMAT_MAX_PLANES;
392392 struct drm_gem_object *obj;
@@ -396,7 +396,7 @@ void drm_gem_fb_vunmap(struct drm_framebuffer *fb, · 3 unmodified lines
396396 obj = drm_gem_fb_get_obj(fb, i);
397397 if (!obj)
398398 continue;
399− if (dma_buf_map_is_null(&map[i]))
399+ if (iosys_map_is_null(&map[i]))
400400 continue;
401401 drm_gem_vunmap(obj, &map[i]);
402402 }
drivers/gpu/drm/drm_gem_shmem_helper.c+9−6
@@ -286,13 +286,14 @@ void drm_gem_shmem_unpin(struct drm_gem_shmem_object *shmem) · 285 unmodified lines
286286 }
287287 EXPORT_SYMBOL(drm_gem_shmem_unpin);
288288
289−static int drm_gem_shmem_vmap_locked(struct drm_gem_shmem_object *shmem, struct dma_buf_map *map)
289+static int drm_gem_shmem_vmap_locked(struct drm_gem_shmem_object *shmem,
290+ struct iosys_map *map)
290291 {
291292 struct drm_gem_object *obj = &shmem->base;
292293 int ret = 0;
293294
294295 if (shmem->vmap_use_count++ > 0) {
295− dma_buf_map_set_vaddr(map, shmem->vaddr);
296+ iosys_map_set_vaddr(map, shmem->vaddr);
296297 return 0;
297298 }
298299
@@ -319,7 +320,7 @@ static int drm_gem_shmem_vmap_locked(struct drm_gem_shmem_object *shmem, struct · 20 unmodified lines
319320 if (!shmem->vaddr)
320321 ret = -ENOMEM;
321322 else
322− dma_buf_map_set_vaddr(map, shmem->vaddr);
323+ iosys_map_set_vaddr(map, shmem->vaddr);
323324 }
324325
325326 if (ret) {
@@ -353,7 +354,8 @@ err_zero_use: · 27 unmodified lines
353354 * Returns:
354355 * 0 on success or a negative error code on failure.
355356 */
356−int drm_gem_shmem_vmap(struct drm_gem_shmem_object *shmem, struct dma_buf_map *map)
357+int drm_gem_shmem_vmap(struct drm_gem_shmem_object *shmem,
358+ struct iosys_map *map)
357359 {
358360 int ret;
359361
@@ -368,7 +370,7 @@ int drm_gem_shmem_vmap(struct drm_gem_shmem_object *shmem, struct dma_buf_map *m · 8 unmodified lines
368370 EXPORT_SYMBOL(drm_gem_shmem_vmap);
369371
370372 static void drm_gem_shmem_vunmap_locked(struct drm_gem_shmem_object *shmem,
371− struct dma_buf_map *map)
373+ struct iosys_map *map)
372374 {
373375 struct drm_gem_object *obj = &shmem->base;
374376
@@ -400,7 +402,8 @@ static void drm_gem_shmem_vunmap_locked(struct drm_gem_shmem_object *shmem, · 25 unmodified lines
400402 * This function hides the differences between dma-buf imported and natively
401403 * allocated objects.
402404 */
403−void drm_gem_shmem_vunmap(struct drm_gem_shmem_object *shmem, struct dma_buf_map *map)
405+void drm_gem_shmem_vunmap(struct drm_gem_shmem_object *shmem,
406+ struct iosys_map *map)
404407 {
405408 mutex_lock(&shmem->vmap_lock);
406409 drm_gem_shmem_vunmap_locked(shmem, map);
drivers/gpu/drm/drm_gem_ttm_helper.c+2−2
@@ -61,7 +61,7 @@ EXPORT_SYMBOL(drm_gem_ttm_print_info); · 60 unmodified lines
6161 * 0 on success, or a negative errno code otherwise.
6262 */
6363 int drm_gem_ttm_vmap(struct drm_gem_object *gem,
64− struct dma_buf_map *map)
64+ struct iosys_map *map)
6565 {
6666 struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem);
6767
@@ -78,7 +78,7 @@ EXPORT_SYMBOL(drm_gem_ttm_vmap); · 10 unmodified lines
7878 * &drm_gem_object_funcs.vmap callback.
7979 */
8080 void drm_gem_ttm_vunmap(struct drm_gem_object *gem,
81− struct dma_buf_map *map)
81+ struct iosys_map *map)
8282 {
8383 struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem);
8484
drivers/gpu/drm/drm_gem_vram_helper.c+14−11
@@ -1,6 +1,6 @@
11 // SPDX-License-Identifier: GPL-2.0-or-later
22
3−#include <linux/dma-buf-map.h>
3+#include <linux/iosys-map.h>
44 #include <linux/module.h>
55
66 #include <drm/drm_debugfs.h>
@@ -116,7 +116,7 @@ static void drm_gem_vram_cleanup(struct drm_gem_vram_object *gbo) · 109 unmodified lines
116116 */
117117
118118 WARN_ON(gbo->vmap_use_count);
119− WARN_ON(dma_buf_map_is_set(&gbo->map));
119+ WARN_ON(iosys_map_is_set(&gbo->map));
120120
121121 drm_gem_object_release(&gbo->bo.base);
122122 }
@@ -365,7 +365,7 @@ int drm_gem_vram_unpin(struct drm_gem_vram_object *gbo) · 242 unmodified lines
365365 EXPORT_SYMBOL(drm_gem_vram_unpin);
366366
367367 static int drm_gem_vram_kmap_locked(struct drm_gem_vram_object *gbo,
368− struct dma_buf_map *map)
368+ struct iosys_map *map)
369369 {
370370 int ret;
371371
@@ -377,7 +377,7 @@ static int drm_gem_vram_kmap_locked(struct drm_gem_vram_object *gbo, · 5 unmodified lines
377377 * page mapping might still be around. Only vmap if the there's
378378 * no mapping present.
379379 */
380− if (dma_buf_map_is_null(&gbo->map)) {
380+ if (iosys_map_is_null(&gbo->map)) {
381381 ret = ttm_bo_vmap(&gbo->bo, &gbo->map);
382382 if (ret)
383383 return ret;
@@ -391,14 +391,14 @@ out: · 7 unmodified lines
391391 }
392392
393393 static void drm_gem_vram_kunmap_locked(struct drm_gem_vram_object *gbo,
394− struct dma_buf_map *map)
394+ struct iosys_map *map)
395395 {
396396 struct drm_device *dev = gbo->bo.base.dev;
397397
398398 if (drm_WARN_ON_ONCE(dev, !gbo->vmap_use_count))
399399 return;
400400
401− if (drm_WARN_ON_ONCE(dev, !dma_buf_map_is_equal(&gbo->map, map)))
401+ if (drm_WARN_ON_ONCE(dev, !iosys_map_is_equal(&gbo->map, map)))
402402 return; /* BUG: map not mapped from this BO */
403403
404404 if (--gbo->vmap_use_count > 0)
@@ -428,7 +428,7 @@ static void drm_gem_vram_kunmap_locked(struct drm_gem_vram_object *gbo, · 23 unmodified lines
428428 * Returns:
429429 * 0 on success, or a negative error code otherwise.
430430 */
431−int drm_gem_vram_vmap(struct drm_gem_vram_object *gbo, struct dma_buf_map *map)
431+int drm_gem_vram_vmap(struct drm_gem_vram_object *gbo, struct iosys_map *map)
432432 {
433433 int ret;
434434
@@ -463,7 +463,8 @@ EXPORT_SYMBOL(drm_gem_vram_vmap); · 28 unmodified lines
463463 * A call to drm_gem_vram_vunmap() unmaps and unpins a GEM VRAM buffer. See
464464 * the documentation for drm_gem_vram_vmap() for more information.
465465 */
466−void drm_gem_vram_vunmap(struct drm_gem_vram_object *gbo, struct dma_buf_map *map)
466+void drm_gem_vram_vunmap(struct drm_gem_vram_object *gbo,
467+ struct iosys_map *map)
467468 {
468469 int ret;
469470
@@ -567,7 +568,7 @@ static void drm_gem_vram_bo_driver_move_notify(struct drm_gem_vram_object *gbo) · 97 unmodified lines
567568 return;
568569
569570 ttm_bo_vunmap(bo, &gbo->map);
570− dma_buf_map_clear(&gbo->map); /* explicitly clear mapping for next vmap call */
571+ iosys_map_clear(&gbo->map); /* explicitly clear mapping for next vmap call */
571572 }
572573
573574 static int drm_gem_vram_bo_driver_move(struct drm_gem_vram_object *gbo,
@@ -802,7 +803,8 @@ static void drm_gem_vram_object_unpin(struct drm_gem_object *gem) · 228 unmodified lines
802803 * Returns:
803804 * 0 on success, or a negative error code otherwise.
804805 */
805−static int drm_gem_vram_object_vmap(struct drm_gem_object *gem, struct dma_buf_map *map)
806+static int drm_gem_vram_object_vmap(struct drm_gem_object *gem,
807+ struct iosys_map *map)
806808 {
807809 struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(gem);
808810
@@ -815,7 +817,8 @@ static int drm_gem_vram_object_vmap(struct drm_gem_object *gem, struct dma_buf_m · 6 unmodified lines
815817 * @gem: The GEM object to unmap
816818 * @map: Kernel virtual address where the VRAM GEM object was mapped
817819 */
818−static void drm_gem_vram_object_vunmap(struct drm_gem_object *gem, struct dma_buf_map *map)
820+static void drm_gem_vram_object_vunmap(struct drm_gem_object *gem,
821+ struct iosys_map *map)
819822 {
820823 struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(gem);
821824
drivers/gpu/drm/drm_internal.h+3−3
@@ -33,7 +33,7 @@ · 32 unmodified lines
3333
3434 struct dentry;
3535 struct dma_buf;
36−struct dma_buf_map;
36+struct iosys_map;
3737 struct drm_connector;
3838 struct drm_crtc;
3939 struct drm_framebuffer;
@@ -174,8 +174,8 @@ void drm_gem_print_info(struct drm_printer *p, unsigned int indent, · 134 unmodified lines
174174
175175 int drm_gem_pin(struct drm_gem_object *obj);
176176 void drm_gem_unpin(struct drm_gem_object *obj);
177−int drm_gem_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
178−void drm_gem_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
177+int drm_gem_vmap(struct drm_gem_object *obj, struct iosys_map *map);
178+void drm_gem_vunmap(struct drm_gem_object *obj, struct iosys_map *map);
179179
180180 int drm_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
181181 u32 handle);
drivers/gpu/drm/drm_mipi_dbi.c+4−4
@@ -201,8 +201,8 @@ int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb, · 200 unmodified lines
201201 struct drm_rect *clip, bool swap)
202202 {
203203 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
204− struct dma_buf_map map[DRM_FORMAT_MAX_PLANES];
205− struct dma_buf_map data[DRM_FORMAT_MAX_PLANES];
204+ struct iosys_map map[DRM_FORMAT_MAX_PLANES];
205+ struct iosys_map data[DRM_FORMAT_MAX_PLANES];
206206 void *src;
207207 int ret;
208208
@@ -258,8 +258,8 @@ static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev, · 49 unmodified lines
258258
259259 static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
260260 {
261− struct dma_buf_map map[DRM_FORMAT_MAX_PLANES];
262− struct dma_buf_map data[DRM_FORMAT_MAX_PLANES];
261+ struct iosys_map map[DRM_FORMAT_MAX_PLANES];
262+ struct iosys_map data[DRM_FORMAT_MAX_PLANES];
263263 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
264264 unsigned int height = rect->y2 - rect->y1;
265265 unsigned int width = rect->x2 - rect->x1;
drivers/gpu/drm/drm_panel_orientation_quirks.c+6−0
@@ -180,6 +180,12 @@ static const struct dmi_system_id orientation_data[] = { · 179 unmodified lines
180180 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "MicroPC"),
181181 },
182182 .driver_data = (void *)&lcd720x1280_rightside_up,
183+ }, { /* GPD Win Max */
184+ .matches = {
185+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "GPD"),
186+ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "G1619-01"),
187+ },
188+ .driver_data = (void *)&lcd800x1280_rightside_up,
183189 }, { /*
184190 * GPD Pocket, note that the the DMI data is less generic then
185191 * it seems, devices with a board-vendor of "AMI Corporation"
drivers/gpu/drm/drm_prime.c+2−2
@@ -674,7 +674,7 @@ EXPORT_SYMBOL(drm_gem_unmap_dma_buf); · 673 unmodified lines
674674 *
675675 * Returns 0 on success or a negative errno code otherwise.
676676 */
677−int drm_gem_dmabuf_vmap(struct dma_buf *dma_buf, struct dma_buf_map *map)
677+int drm_gem_dmabuf_vmap(struct dma_buf *dma_buf, struct iosys_map *map)
678678 {
679679 struct drm_gem_object *obj = dma_buf->priv;
680680
@@ -690,7 +690,7 @@ EXPORT_SYMBOL(drm_gem_dmabuf_vmap); · 9 unmodified lines
690690 * Releases a kernel virtual mapping. This can be used as the
691691 * &dma_buf_ops.vunmap callback. Calls into &drm_gem_object_funcs.vunmap for device specific handling.
692692 */
693−void drm_gem_dmabuf_vunmap(struct dma_buf *dma_buf, struct dma_buf_map *map)
693+void drm_gem_dmabuf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map)
694694 {
695695 struct drm_gem_object *obj = dma_buf->priv;
696696
drivers/gpu/drm/etnaviv/etnaviv_drv.h+1−1
@@ -49,7 +49,7 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data, · 48 unmodified lines
4949
5050 int etnaviv_gem_mmap_offset(struct drm_gem_object *obj, u64 *offset);
5151 struct sg_table *etnaviv_gem_prime_get_sg_table(struct drm_gem_object *obj);
52−int etnaviv_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
52+int etnaviv_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
5353 struct drm_gem_object *etnaviv_gem_prime_import_sg_table(struct drm_device *dev,
5454 struct dma_buf_attachment *attach, struct sg_table *sg);
5555 int etnaviv_gem_prime_pin(struct drm_gem_object *obj);
drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c+4−4
@@ -25,14 +25,14 @@ struct sg_table *etnaviv_gem_prime_get_sg_table(struct drm_gem_object *obj) · 24 unmodified lines
2525 return drm_prime_pages_to_sg(obj->dev, etnaviv_obj->pages, npages);
2626 }
2727
28−int etnaviv_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
28+int etnaviv_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map)
2929 {
3030 void *vaddr;
3131
3232 vaddr = etnaviv_gem_vmap(obj);
3333 if (!vaddr)
3434 return -ENOMEM;
35− dma_buf_map_set_vaddr(map, vaddr);
35+ iosys_map_set_vaddr(map, vaddr);
3636
3737 return 0;
3838 }
@@ -62,7 +62,7 @@ void etnaviv_gem_prime_unpin(struct drm_gem_object *obj) · 23 unmodified lines
6262
6363 static void etnaviv_gem_prime_release(struct etnaviv_gem_object *etnaviv_obj)
6464 {
65− struct dma_buf_map map = DMA_BUF_MAP_INIT_VADDR(etnaviv_obj->vaddr);
65+ struct iosys_map map = IOSYS_MAP_INIT_VADDR(etnaviv_obj->vaddr);
6666
6767 if (etnaviv_obj->vaddr)
6868 dma_buf_vunmap(etnaviv_obj->base.import_attach->dmabuf, &map);
@@ -77,7 +77,7 @@ static void etnaviv_gem_prime_release(struct etnaviv_gem_object *etnaviv_obj) · 8 unmodified lines
7777
7878 static void *etnaviv_gem_prime_vmap_impl(struct etnaviv_gem_object *etnaviv_obj)
7979 {
80− struct dma_buf_map map;
80+ struct iosys_map map;
8181 int ret;
8282
8383 lockdep_assert_held(&etnaviv_obj->lock);
drivers/gpu/drm/gud/gud_pipe.c+2−2
@@ -152,8 +152,8 @@ static int gud_prep_flush(struct gud_device *gdrm, struct drm_framebuffer *fb, · 151 unmodified lines
152152 {
153153 struct dma_buf_attachment *import_attach = fb->obj[0]->import_attach;
154154 u8 compression = gdrm->compression;
155− struct dma_buf_map map[DRM_FORMAT_MAX_PLANES];
156− struct dma_buf_map map_data[DRM_FORMAT_MAX_PLANES];
155+ struct iosys_map map[DRM_FORMAT_MAX_PLANES];
156+ struct iosys_map map_data[DRM_FORMAT_MAX_PLANES];
157157 void *vaddr, *buf;
158158 size_t pitch, len;
159159 int ret = 0;
drivers/gpu/drm/hyperv/hyperv_drm_modeset.c+3−2
@@ -19,7 +19,7 @@ · 18 unmodified lines
1919 #include "hyperv_drm.h"
2020
2121 static int hyperv_blit_to_vram_rect(struct drm_framebuffer *fb,
22− const struct dma_buf_map *map,
22+ const struct iosys_map *map,
2323 struct drm_rect *rect)
2424 {
2525 struct hyperv_drm_device *hv = to_hv(fb->dev);
@@ -38,7 +38,8 @@ static int hyperv_blit_to_vram_rect(struct drm_framebuffer *fb, · 12 unmodified lines
3838 return 0;
3939 }
4040
41−static int hyperv_blit_to_vram_fullscreen(struct drm_framebuffer *fb, const struct dma_buf_map *map)
41+static int hyperv_blit_to_vram_fullscreen(struct drm_framebuffer *fb,
42+ const struct iosys_map *map)
4243 {
4344 struct drm_rect fullscreen = {
4445 .x1 = 0,
drivers/gpu/drm/i915/Makefile+2−1
@@ -32,8 +32,9 @@ subdir-ccflags-y += -I$(srctree)/$(src) · 31 unmodified lines
3232 # core driver code
3333 i915-y += i915_driver.o \
3434 i915_config.o \
35− i915_irq.o \
3635 i915_getparam.o \
36+ i915_ioctl.o \
37+ i915_irq.o \
3738 i915_mitigations.o \
3839 i915_module.o \
3940 i915_params.o \
drivers/gpu/drm/i915/display/g4x_dp.c+17−1
@@ -18,6 +18,7 @@ · 17 unmodified lines
1818 #include "intel_fifo_underrun.h"
1919 #include "intel_hdmi.h"
2020 #include "intel_hotplug.h"
21+#include "intel_pch_display.h"
2122 #include "intel_pps.h"
2223 #include "vlv_sideband.h"
2324
@@ -333,6 +334,21 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder, · 309 unmodified lines
333334 return ret;
334335 }
335336
337+static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state)
338+{
339+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
340+
341+ if (crtc_state->has_pch_encoder) {
342+ intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n);
343+ intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2);
344+ } else {
345+ intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
346+ &crtc_state->dp_m_n);
347+ intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder,
348+ &crtc_state->dp_m2_n2);
349+ }
350+}
351+
336352 static void intel_dp_get_config(struct intel_encoder *encoder,
337353 struct intel_crtc_state *pipe_config)
338354 {
@@ -384,7 +400,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder, · 45 unmodified lines
384400 pipe_config->lane_count =
385401 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
386402
387− intel_dp_get_m_n(crtc, pipe_config);
403+ g4x_dp_get_m_n(pipe_config);
388404
389405 if (port == PORT_A) {
390406 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
drivers/gpu/drm/i915/display/g4x_hdmi.h+1−1
@@ -8,7 +8,7 @@ · 7 unmodified lines
88
99 #include <linux/types.h>
1010
11−#include "i915_reg.h"
11+#include "i915_reg_defs.h"
1212
1313 enum port;
1414 struct drm_i915_private;
drivers/gpu/drm/i915/display/i9xx_plane.c+52−53
@@ -125,7 +125,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv, · 124 unmodified lines
125125 enum i9xx_plane_id i9xx_plane)
126126 {
127127 if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
128− return dev_priv->fbc;
128+ return dev_priv->fbc[INTEL_FBC_A];
129129 else
130130 return NULL;
131131 }
@@ -155,51 +155,51 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, · 23 unmodified lines
155155 unsigned int rotation = plane_state->hw.rotation;
156156 u32 dspcntr;
157157
158− dspcntr = DISPLAY_PLANE_ENABLE;
158+ dspcntr = DISP_ENABLE;
159159
160160 if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
161161 IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
162− dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
162+ dspcntr |= DISP_TRICKLE_FEED_DISABLE;
163163
164164 switch (fb->format->format) {
165165 case DRM_FORMAT_C8:
166− dspcntr |= DISPPLANE_8BPP;
166+ dspcntr |= DISP_FORMAT_8BPP;
167167 break;
168168 case DRM_FORMAT_XRGB1555:
169− dspcntr |= DISPPLANE_BGRX555;
169+ dspcntr |= DISP_FORMAT_BGRX555;
170170 break;
171171 case DRM_FORMAT_ARGB1555:
172− dspcntr |= DISPPLANE_BGRA555;
172+ dspcntr |= DISP_FORMAT_BGRA555;
173173 break;
174174 case DRM_FORMAT_RGB565:
175− dspcntr |= DISPPLANE_BGRX565;
175+ dspcntr |= DISP_FORMAT_BGRX565;
176176 break;
177177 case DRM_FORMAT_XRGB8888:
178− dspcntr |= DISPPLANE_BGRX888;
178+ dspcntr |= DISP_FORMAT_BGRX888;
179179 break;
180180 case DRM_FORMAT_XBGR8888:
181− dspcntr |= DISPPLANE_RGBX888;
181+ dspcntr |= DISP_FORMAT_RGBX888;
182182 break;
183183 case DRM_FORMAT_ARGB8888:
184− dspcntr |= DISPPLANE_BGRA888;
184+ dspcntr |= DISP_FORMAT_BGRA888;
185185 break;
186186 case DRM_FORMAT_ABGR8888:
187− dspcntr |= DISPPLANE_RGBA888;
187+ dspcntr |= DISP_FORMAT_RGBA888;
188188 break;
189189 case DRM_FORMAT_XRGB2101010:
190− dspcntr |= DISPPLANE_BGRX101010;
190+ dspcntr |= DISP_FORMAT_BGRX101010;
191191 break;
192192 case DRM_FORMAT_XBGR2101010:
193− dspcntr |= DISPPLANE_RGBX101010;
193+ dspcntr |= DISP_FORMAT_RGBX101010;
194194 break;
195195 case DRM_FORMAT_ARGB2101010:
196− dspcntr |= DISPPLANE_BGRA101010;
196+ dspcntr |= DISP_FORMAT_BGRA101010;
197197 break;
198198 case DRM_FORMAT_ABGR2101010:
199− dspcntr |= DISPPLANE_RGBA101010;
199+ dspcntr |= DISP_FORMAT_RGBA101010;
200200 break;
201201 case DRM_FORMAT_XBGR16161616F:
202− dspcntr |= DISPPLANE_RGBX161616;
202+ dspcntr |= DISP_FORMAT_RGBX161616;
203203 break;
204204 default:
205205 MISSING_CASE(fb->format->format);
@@ -208,13 +208,13 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, · 2 unmodified lines
208208
209209 if (DISPLAY_VER(dev_priv) >= 4 &&
210210 fb->modifier == I915_FORMAT_MOD_X_TILED)
211− dspcntr |= DISPPLANE_TILED;
211+ dspcntr |= DISP_TILED;
212212
213213 if (rotation & DRM_MODE_ROTATE_180)
214− dspcntr |= DISPPLANE_ROTATE_180;
214+ dspcntr |= DISP_ROTATE_180;
215215
216216 if (rotation & DRM_MODE_REFLECT_X)
217− dspcntr |= DISPPLANE_MIRROR;
217+ dspcntr |= DISP_MIRROR;
218218
219219 return dspcntr;
220220 }
@@ -354,13 +354,13 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) · 133 unmodified lines
354354 u32 dspcntr = 0;
355355
356356 if (crtc_state->gamma_enable)
357− dspcntr |= DISPPLANE_GAMMA_ENABLE;
357+ dspcntr |= DISP_PIPE_GAMMA_ENABLE;
358358
359359 if (crtc_state->csc_enable)
360− dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
360+ dspcntr |= DISP_PIPE_CSC_ENABLE;
361361
362362 if (DISPLAY_VER(dev_priv) < 5)
363− dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
363+ dspcntr |= DISP_PIPE_SEL(crtc->pipe);
364364
365365 return dspcntr;
366366 }
@@ -437,9 +437,9 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane, · 70 unmodified lines
437437 * program whatever is there.
438438 */
439439 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
440− (crtc_y << 16) | crtc_x);
440+ DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x));
441441 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
442− ((crtc_h - 1) << 16) | (crtc_w - 1));
442+ DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1));
443443 }
444444
445445 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
@@ -474,20 +474,20 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, · 28 unmodified lines
474474 int crtc_h = drm_rect_height(&plane_state->uapi.dst);
475475
476476 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
477− (crtc_y << 16) | crtc_x);
477+ PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x));
478478 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
479− ((crtc_h - 1) << 16) | (crtc_w - 1));
479+ PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1));
480480 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
481481 }
482482
483483 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
484484 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
485− (y << 16) | x);
485+ DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
486486 } else if (DISPLAY_VER(dev_priv) >= 4) {
487487 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
488488 linear_offset);
489489 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
490− (y << 16) | x);
490+ DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
491491 }
492492
493493 /*
@@ -564,7 +564,7 @@ g4x_primary_async_flip(struct intel_plane *plane, · 70 unmodified lines
564564 unsigned long irqflags;
565565
566566 if (async_flip)
567− dspcntr |= DISPPLANE_ASYNC_FLIP;
567+ dspcntr |= DISP_ASYNC_FLIP;
568568
569569 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
570570 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
@@ -696,13 +696,12 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, · 125 unmodified lines
696696
697697 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
698698
699− ret = val & DISPLAY_PLANE_ENABLE;
699+ ret = val & DISP_ENABLE;
700700
701701 if (DISPLAY_VER(dev_priv) >= 5)
702702 *pipe = plane->pipe;
703703 else
704− *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
705− DISPPLANE_SEL_PIPE_SHIFT;
704+ *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val);
706705
707706 intel_display_power_put(dev_priv, power_domain, wakeref);
708707
@@ -958,32 +957,32 @@ fail: · 249 unmodified lines
958957 static int i9xx_format_to_fourcc(int format)
959958 {
960959 switch (format) {
961− case DISPPLANE_8BPP:
960+ case DISP_FORMAT_8BPP:
962961 return DRM_FORMAT_C8;
963− case DISPPLANE_BGRA555:
962+ case DISP_FORMAT_BGRA555:
964963 return DRM_FORMAT_ARGB1555;
965− case DISPPLANE_BGRX555:
964+ case DISP_FORMAT_BGRX555:
966965 return DRM_FORMAT_XRGB1555;
967− case DISPPLANE_BGRX565:
966+ case DISP_FORMAT_BGRX565:
968967 return DRM_FORMAT_RGB565;
969968 default:
970− case DISPPLANE_BGRX888:
969+ case DISP_FORMAT_BGRX888:
971970 return DRM_FORMAT_XRGB8888;
972− case DISPPLANE_RGBX888:
971+ case DISP_FORMAT_RGBX888:
973972 return DRM_FORMAT_XBGR8888;
974− case DISPPLANE_BGRA888:
973+ case DISP_FORMAT_BGRA888:
975974 return DRM_FORMAT_ARGB8888;
976− case DISPPLANE_RGBA888:
975+ case DISP_FORMAT_RGBA888:
977976 return DRM_FORMAT_ABGR8888;
978− case DISPPLANE_BGRX101010:
977+ case DISP_FORMAT_BGRX101010:
979978 return DRM_FORMAT_XRGB2101010;
980− case DISPPLANE_RGBX101010:
979+ case DISP_FORMAT_RGBX101010:
981980 return DRM_FORMAT_XBGR2101010;
982− case DISPPLANE_BGRA101010:
981+ case DISP_FORMAT_BGRA101010:
983982 return DRM_FORMAT_ARGB2101010;
984− case DISPPLANE_RGBA101010:
983+ case DISP_FORMAT_RGBA101010:
985984 return DRM_FORMAT_ABGR2101010;
986− case DISPPLANE_RGBX161616:
985+ case DISP_FORMAT_RGBX161616:
987986 return DRM_FORMAT_XBGR16161616F;
988987 }
989988 }
@@ -1021,26 +1020,26 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, · 31 unmodified lines
10211020 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
10221021
10231022 if (DISPLAY_VER(dev_priv) >= 4) {
1024− if (val & DISPPLANE_TILED) {
1023+ if (val & DISP_TILED) {
10251024 plane_config->tiling = I915_TILING_X;
10261025 fb->modifier = I915_FORMAT_MOD_X_TILED;
10271026 }
10281027
1029− if (val & DISPPLANE_ROTATE_180)
1028+ if (val & DISP_ROTATE_180)
10301029 plane_config->rotation = DRM_MODE_ROTATE_180;
10311030 }
10321031
10331032 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
1034− val & DISPPLANE_MIRROR)
1033+ val & DISP_MIRROR)
10351034 plane_config->rotation |= DRM_MODE_REFLECT_X;
10361035
1037− pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
1036+ pixel_format = val & DISP_FORMAT_MASK;
10381037 fourcc = i9xx_format_to_fourcc(pixel_format);
10391038 fb->format = drm_format_info(fourcc);
10401039
10411040 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
10421041 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
1043− base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
1042+ base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
10441043 } else if (DISPLAY_VER(dev_priv) >= 4) {
10451044 if (plane_config->tiling)
10461045 offset = intel_de_read(dev_priv,
@@ -1048,15 +1047,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, · 1 unmodified line
10481047 else
10491048 offset = intel_de_read(dev_priv,
10501049 DSPLINOFF(i9xx_plane));
1051− base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
1050+ base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
10521051 } else {
10531052 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
10541053 }
10551054 plane_config->base = base;
10561055
10571056 val = intel_de_read(dev_priv, PIPESRC(pipe));
1058− fb->width = ((val >> 16) & 0xfff) + 1;
1059− fb->height = ((val >> 0) & 0xfff) + 1;
1057+ fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
1058+ fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
10601059
10611060 val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
10621061 fb->pitches[0] = val & 0xffffffc0;
drivers/gpu/drm/i915/display/icl_dsi.c+3−4
@@ -32,6 +32,7 @@ · 31 unmodified lines
3232 #include "intel_atomic.h"
3333 #include "intel_backlight.h"
3434 #include "intel_combo_phy.h"
35+#include "intel_combo_phy_regs.h"
3536 #include "intel_connector.h"
3637 #include "intel_crtc.h"
3738 #include "intel_ddi.h"
@@ -1050,7 +1051,7 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) · 1012 unmodified lines
10501051
10511052 /* wait for transcoder to be enabled */
10521053 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
1053− I965_PIPECONF_ACTIVE, 10))
1054+ PIPECONF_STATE_ENABLE, 10))
10541055 drm_err(&dev_priv->drm,
10551056 "DSI transcoder not enabled\n");
10561057 }
@@ -1232,8 +1233,6 @@ static void gen11_dsi_pre_enable(struct intel_atomic_state *state, · 175 unmodified lines
12321233
12331234 intel_dsc_dsi_pps_write(encoder, pipe_config);
12341235
1235− intel_dsc_enable(pipe_config);
1236−
12371236 /* step6c: configure transcoder timings */
12381237 gen11_dsi_set_transcoder_timings(encoder, pipe_config);
12391238 }
@@ -1320,7 +1319,7 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) · 80 unmodified lines
13201319
13211320 /* wait for transcoder to be disabled */
13221321 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
1323− I965_PIPECONF_ACTIVE, 50))
1322+ PIPECONF_STATE_ENABLE, 50))
13241323 drm_err(&dev_priv->drm,
13251324 "DSI trancoder not disabled\n");
13261325 }
drivers/gpu/drm/i915/display/intel_atomic.c+2−0
@@ -34,6 +34,8 @@ · 33 unmodified lines
3434 #include <drm/drm_fourcc.h>
3535 #include <drm/drm_plane_helper.h>
3636
37+#include "i915_drv.h"
38+#include "i915_reg.h"
3739 #include "intel_atomic.h"
3840 #include "intel_cdclk.h"
3941 #include "intel_display_types.h"
drivers/gpu/drm/i915/display/intel_atomic_plane.c+5−3
@@ -109,6 +109,7 @@ intel_plane_duplicate_state(struct drm_plane *plane) · 108 unmodified lines
109109 intel_state->ggtt_vma = NULL;
110110 intel_state->dpt_vma = NULL;
111111 intel_state->flags = 0;
112+ intel_state->do_async_flip = false;
112113
113114 /* add reference to fb */
114115 if (intel_state->hw.fb)
@@ -491,7 +492,7 @@ void intel_plane_update_arm(struct intel_plane *plane, · 376 unmodified lines
491492
492493 trace_intel_plane_update_arm(&plane->base, crtc);
493494
494− if (crtc_state->uapi.async_flip && plane->async_flip)
495+ if (plane_state->do_async_flip)
495496 plane->async_flip(plane, crtc_state, plane_state, true);
496497 else
497498 plane->update_arm(plane, crtc_state, plane_state);
@@ -601,6 +602,7 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, · 103 unmodified lines
601602 int min_scale, int max_scale,
602603 bool can_position)
603604 {
605+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
604606 struct drm_framebuffer *fb = plane_state->hw.fb;
605607 struct drm_rect *src = &plane_state->uapi.src;
606608 struct drm_rect *dst = &plane_state->uapi.dst;
@@ -619,7 +621,7 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, · 12 unmodified lines
619621 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
620622 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
621623 if (hscale < 0 || vscale < 0) {
622− DRM_DEBUG_KMS("Invalid scaling of plane\n");
624+ drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n");
623625 drm_rect_debug_print("src: ", src, true);
624626 drm_rect_debug_print("dst: ", dst, false);
625627 return -ERANGE;
@@ -644,7 +646,7 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, · 18 unmodified lines
644646
645647 if (!can_position && plane_state->uapi.visible &&
646648 !drm_rect_equals(dst, &clip)) {
647− DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
649+ drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n");
648650 drm_rect_debug_print("dst: ", dst, false);
649651 drm_rect_debug_print("clip: ", &clip, false);
650652 return -EINVAL;
drivers/gpu/drm/i915/display/intel_atomic_plane.h+1−0
@@ -16,6 +16,7 @@ struct intel_crtc; · 15 unmodified lines
1616 struct intel_crtc_state;
1717 struct intel_plane;
1818 struct intel_plane_state;
19+enum plane_id;
1920
2021 unsigned int intel_adjusted_rate(const struct drm_rect *src,
2122 const struct drm_rect *dst,
drivers/gpu/drm/i915/display/intel_backlight.c+3−0
@@ -13,6 +13,7 @@ · 12 unmodified lines
1313 #include "intel_dp_aux_backlight.h"
1414 #include "intel_dsi_dcs_backlight.h"
1515 #include "intel_panel.h"
16+#include "intel_pci_config.h"
1617
1718 /**
1819 * scale - scale values from one range to another
@@ -433,6 +434,8 @@ static void ext_pwm_disable_backlight(const struct drm_connector_state *old_conn · 414 unmodified lines
433434 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
434435 struct intel_panel *panel = &connector->panel;
435436
437+ intel_backlight_set_pwm_level(old_conn_state, level);
438+
436439 panel->backlight.pwm_state.enabled = false;
437440 pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state);
438441 }
drivers/gpu/drm/i915/display/intel_bios.c+92−123
@@ -32,6 +32,7 @@ · 31 unmodified lines
3232 #include "display/intel_gmbus.h"
3333
3434 #include "i915_drv.h"
35+#include "i915_reg.h"
3536
3637 #define _INTEL_BIOS_PRIVATE
3738 #include "intel_vbt_defs.h"
@@ -905,26 +906,6 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb) · 867 unmodified lines
905906 i915->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
906907 psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
907908
908− switch (psr_table->lines_to_wait) {
909− case 0:
910− i915->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
911− break;
912− case 1:
913− i915->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
914− break;
915− case 2:
916− i915->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
917− break;
918− case 3:
919− i915->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
920− break;
921− default:
922− drm_dbg_kms(&i915->drm,
923− "VBT has unknown PSR lines to wait %u\n",
924− psr_table->lines_to_wait);
925− break;
926− }
927−
928909 /*
929910 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
930911 * Old decimal value is wake up time in multiples of 100 us.
@@ -2073,14 +2054,16 @@ static void parse_ddi_port(struct drm_i915_private *i915, · 1142 unmodified lines
20732054 i915->vbt.ports[port] = devdata;
20742055 }
20752056
2057+static bool has_ddi_port_info(struct drm_i915_private *i915)
2058+{
2059+ return DISPLAY_VER(i915) >= 5 || IS_G4X(i915);
2060+}
2061+
20762062 static void parse_ddi_ports(struct drm_i915_private *i915)
20772063 {
20782064 struct intel_bios_encoder_data *devdata;
20792065
2080− if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))
2081− return;
2082−
2083− if (i915->vbt.version < 155)
2066+ if (!has_ddi_port_info(i915))
20842067 return;
20852068
20862069 list_for_each_entry(devdata, &i915->vbt.display_devices, node)
@@ -2335,6 +2318,63 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t size) · 248 unmodified lines
23352318 return vbt;
23362319 }
23372320
2321+static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915)
2322+{
2323+ u32 count, data, found, store = 0;
2324+ u32 static_region, oprom_offset;
2325+ u32 oprom_size = 0x200000;
2326+ u16 vbt_size;
2327+ u32 *vbt;
2328+
2329+ static_region = intel_uncore_read(&i915->uncore, SPI_STATIC_REGIONS);
2330+ static_region &= OPTIONROM_SPI_REGIONID_MASK;
2331+ intel_uncore_write(&i915->uncore, PRIMARY_SPI_REGIONID, static_region);
2332+
2333+ oprom_offset = intel_uncore_read(&i915->uncore, OROM_OFFSET);
2334+ oprom_offset &= OROM_OFFSET_MASK;
2335+
2336+ for (count = 0; count < oprom_size; count += 4) {
2337+ intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, oprom_offset + count);
2338+ data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
2339+
2340+ if (data == *((const u32 *)"$VBT")) {
2341+ found = oprom_offset + count;
2342+ break;
2343+ }
2344+ }
2345+
2346+ if (count >= oprom_size)
2347+ goto err_not_found;
2348+
2349+ /* Get VBT size and allocate space for the VBT */
2350+ intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found +
2351+ offsetof(struct vbt_header, vbt_size));
2352+ vbt_size = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
2353+ vbt_size &= 0xffff;
2354+
2355+ vbt = kzalloc(round_up(vbt_size, 4), GFP_KERNEL);
2356+ if (!vbt)
2357+ goto err_not_found;
2358+
2359+ for (count = 0; count < vbt_size; count += 4) {
2360+ intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found + count);
2361+ data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
2362+ *(vbt + store++) = data;
2363+ }
2364+
2365+ if (!intel_bios_is_valid_vbt(vbt, vbt_size))
2366+ goto err_free_vbt;
2367+
2368+ drm_dbg_kms(&i915->drm, "Found valid VBT in SPI flash\n");
2369+
2370+ return (struct vbt_header *)vbt;
2371+
2372+err_free_vbt:
2373+ kfree(vbt);
2374+err_not_found:
2375+ return NULL;
2376+}
2377+
23382378 static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915)
23392379 {
23402380 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
@@ -2384,6 +2424,8 @@ static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915) · 43 unmodified lines
23842424
23852425 pci_unmap_rom(pdev, oprom);
23862426
2427+ drm_dbg_kms(&i915->drm, "Found valid VBT in PCI ROM\n");
2428+
23872429 return vbt;
23882430
23892431 err_free_vbt:
@@ -2418,17 +2460,23 @@ void intel_bios_init(struct drm_i915_private *i915) · 28 unmodified lines
24182460
24192461 init_vbt_defaults(i915);
24202462
2421− /* If the OpRegion does not have VBT, look in PCI ROM. */
2463+ /*
2464+ * If the OpRegion does not have VBT, look in SPI flash through MMIO or
2465+ * PCI mapping
2466+ */
2467+ if (!vbt && IS_DGFX(i915)) {
2468+ oprom_vbt = spi_oprom_get_vbt(i915);
2469+ vbt = oprom_vbt;
2470+ }
2471+
24222472 if (!vbt) {
24232473 oprom_vbt = oprom_get_vbt(i915);
2424− if (!oprom_vbt)
2425− goto out;
2426−
24272474 vbt = oprom_vbt;
2428−
2429− drm_dbg_kms(&i915->drm, "Found valid VBT in PCI ROM\n");
24302475 }
24312476
2477+ if (!vbt)
2478+ goto out;
2479+
24322480 bdb = get_bdb_header(vbt);
24332481 i915->vbt.version = bdb->version;
24342482
@@ -2596,37 +2644,10 @@ bool intel_bios_is_lvds_present(struct drm_i915_private *i915, u8 *i2c_pin) · 161 unmodified lines
25962644 */
25972645 bool intel_bios_is_port_present(struct drm_i915_private *i915, enum port port)
25982646 {
2599− const struct intel_bios_encoder_data *devdata;
2600− const struct child_device_config *child;
2601− static const struct {
2602− u16 dp, hdmi;
2603− } port_mapping[] = {
2604− [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, },
2605− [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
2606− [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
2607− [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
2608− [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
2609− };
2610−
2611− if (HAS_DDI(i915))
2612− return i915->vbt.ports[port];
2613−
2614− /* FIXME maybe deal with port A as well? */
2615− if (drm_WARN_ON(&i915->drm,
2616− port == PORT_A) || port >= ARRAY_SIZE(port_mapping))
2617− return false;
2618−
2619− list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
2620− child = &devdata->child;
2621−
2622− if ((child->dvo_port == port_mapping[port].dp ||
2623− child->dvo_port == port_mapping[port].hdmi) &&
2624− (child->device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING |
2625− DEVICE_TYPE_DISPLAYPORT_OUTPUT)))
2626− return true;
2627− }
2647+ if (WARN_ON(!has_ddi_port_info(i915)))
2648+ return true;
26282649
2629− return false;
2650+ return i915->vbt.ports[port];
26302651 }
26312652
26322653 /**
@@ -2638,40 +2659,18 @@ bool intel_bios_is_port_present(struct drm_i915_private *i915, enum port port) · 5 unmodified lines
26382659 */
26392660 bool intel_bios_is_port_edp(struct drm_i915_private *i915, enum port port)
26402661 {
2641− const struct intel_bios_encoder_data *devdata;
2642− const struct child_device_config *child;
2643− static const short port_mapping[] = {
2644− [PORT_B] = DVO_PORT_DPB,
2645− [PORT_C] = DVO_PORT_DPC,
2646− [PORT_D] = DVO_PORT_DPD,
2647− [PORT_E] = DVO_PORT_DPE,
2648− [PORT_F] = DVO_PORT_DPF,
2649− };
2650−
2651− if (HAS_DDI(i915)) {
2652− const struct intel_bios_encoder_data *devdata;
2653−
2654− devdata = intel_bios_encoder_data_lookup(i915, port);
2655−
2656− return devdata && intel_bios_encoder_supports_edp(devdata);
2657− }
2658−
2659− list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
2660− child = &devdata->child;
2661−
2662− if (child->dvo_port == port_mapping[port] &&
2663− (child->device_type & DEVICE_TYPE_eDP_BITS) ==
2664− (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
2665− return true;
2666− }
2662+ const struct intel_bios_encoder_data *devdata =
2663+ intel_bios_encoder_data_lookup(i915, port);
26672664
2668− return false;
2665+ return devdata && intel_bios_encoder_supports_edp(devdata);
26692666 }
26702667
2671−static bool child_dev_is_dp_dual_mode(const struct child_device_config *child)
2668+static bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata)
26722669 {
2673− if ((child->device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) !=
2674− (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS))
2670+ const struct child_device_config *child = &devdata->child;
2671+
2672+ if (!intel_bios_encoder_supports_dp(devdata) ||
2673+ !intel_bios_encoder_supports_hdmi(devdata))
26752674 return false;
26762675
26772676 if (dvo_port_type(child->dvo_port) == DVO_PORT_DPA)
@@ -2688,40 +2687,10 @@ static bool child_dev_is_dp_dual_mode(const struct child_device_config *child) · 10 unmodified lines
26882687 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *i915,
26892688 enum port port)
26902689 {
2691− static const struct {
2692− u16 dp, hdmi;
2693− } port_mapping[] = {
2694− /*
2695− * Buggy VBTs may declare DP ports as having
2696− * HDMI type dvo_port :( So let's check both.
2697− */
2698− [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, },
2699− [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
2700− [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
2701− [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
2702− [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
2703− };
2704− const struct intel_bios_encoder_data *devdata;
2705−
2706− if (HAS_DDI(i915)) {
2707− const struct intel_bios_encoder_data *devdata;
2708−
2709− devdata = intel_bios_encoder_data_lookup(i915, port);
2710−
2711− return devdata && child_dev_is_dp_dual_mode(&devdata->child);
2712− }
2713−
2714− if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
2715− return false;
2716−
2717− list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
2718− if ((devdata->child.dvo_port == port_mapping[port].dp ||
2719− devdata->child.dvo_port == port_mapping[port].hdmi) &&
2720− child_dev_is_dp_dual_mode(&devdata->child))
2721− return true;
2722− }
2690+ const struct intel_bios_encoder_data *devdata =
2691+ intel_bios_encoder_data_lookup(i915, port);
27232692
2724− return false;
2693+ return devdata && intel_bios_encoder_supports_dp_dual_mode(devdata);
27252694 }
27262695
27272696 /**
drivers/gpu/drm/i915/display/intel_bw.c+6−8
@@ -5,6 +5,7 @@ · 4 unmodified lines
55
66 #include <drm/drm_atomic_state_helper.h>
77
8+#include "i915_reg.h"
89 #include "intel_atomic.h"
910 #include "intel_bw.h"
1011 #include "intel_cdclk.h"
@@ -75,10 +76,9 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, · 64 unmodified lines
7576 u16 dclk;
7677 int ret;
7778
78− ret = sandybridge_pcode_read(dev_priv,
79− ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
80− ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
81− &val, &val2);
79+ ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
80+ ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
81+ &val, &val2);
8282 if (ret)
8383 return ret;
8484
@@ -102,10 +102,8 @@ static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv, · 17 unmodified lines
102102 int ret;
103103 int i;
104104
105− ret = sandybridge_pcode_read(dev_priv,
106− ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
107− ADL_PCODE_MEM_SS_READ_PSF_GV_INFO,
108− &val, NULL);
105+ ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
106+ ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
109107 if (ret)
110108 return ret;
111109
drivers/gpu/drm/i915/display/intel_cdclk.c+38−27
@@ -31,6 +31,7 @@ · 30 unmodified lines
3131 #include "intel_crtc.h"
3232 #include "intel_de.h"
3333 #include "intel_display_types.h"
34+#include "intel_pci_config.h"
3435 #include "intel_pcode.h"
3536 #include "intel_psr.h"
3637 #include "vlv_sideband.h"
@@ -63,6 +64,17 @@ · 26 unmodified lines
6364 * dividers can be programmed correctly.
6465 */
6566
67+struct intel_cdclk_funcs {
68+ void (*get_cdclk)(struct drm_i915_private *i915,
69+ struct intel_cdclk_config *cdclk_config);
70+ void (*set_cdclk)(struct drm_i915_private *i915,
71+ const struct intel_cdclk_config *cdclk_config,
72+ enum pipe pipe);
73+ int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
74+ int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
75+ u8 (*calc_voltage_level)(int cdclk);
76+};
77+
6678 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
6779 struct intel_cdclk_config *cdclk_config)
6880 {
@@ -793,8 +805,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, · 724 unmodified lines
793805 "trying to change cdclk frequency with cdclk not enabled\n"))
794806 return;
795807
796− ret = sandybridge_pcode_write(dev_priv,
797− BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
808+ ret = snb_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
798809 if (ret) {
799810 drm_err(&dev_priv->drm,
800811 "failed to inform pcode about cdclk change\n");
@@ -822,8 +833,8 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, · 21 unmodified lines
822833 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
823834 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
824835
825− sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
826− cdclk_config->voltage_level);
836+ snb_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
837+ cdclk_config->voltage_level);
827838
828839 intel_de_write(dev_priv, CDCLK_FREQ,
829840 DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
@@ -1126,8 +1137,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, · 296 unmodified lines
11261137 intel_de_posting_read(dev_priv, CDCLK_CTL);
11271138
11281139 /* inform PCU of the change */
1129− sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1130− cdclk_config->voltage_level);
1140+ snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1141+ cdclk_config->voltage_level);
11311142
11321143 intel_update_cdclk(dev_priv);
11331144 }
@@ -1145,7 +1156,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) · 11 unmodified lines
11451156 goto sanitize;
11461157
11471158 intel_update_cdclk(dev_priv);
1148− intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
1159+ intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
11491160
11501161 /* Is PLL enabled and locked ? */
11511162 if (dev_priv->cdclk.hw.vco == 0 ||
@@ -1614,7 +1625,7 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) · 462 unmodified lines
16141625 /* Timeout 200us */
16151626 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
16161627 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
1617− DRM_ERROR("timeout waiting for FREQ change request ack\n");
1628+ drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n");
16181629
16191630 val &= ~BXT_DE_PLL_FREQ_REQ;
16201631 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
@@ -1705,10 +1716,9 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, · 84 unmodified lines
17051716 * BSpec requires us to wait up to 150usec, but that leads to
17061717 * timeouts; the 2ms used here is based on experiment.
17071718 */
1708− ret = sandybridge_pcode_write_timeout(dev_priv,
1709− HSW_PCODE_DE_WRITE_FREQ_REQ,
1710− 0x80000000, 150, 2);
1711−
1719+ ret = snb_pcode_write_timeout(dev_priv,
1720+ HSW_PCODE_DE_WRITE_FREQ_REQ,
1721+ 0x80000000, 150, 2);
17121722 if (ret) {
17131723 drm_err(&dev_priv->drm,
17141724 "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
@@ -1769,8 +1779,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, · 54 unmodified lines
17691779 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
17701780
17711781 if (DISPLAY_VER(dev_priv) >= 11) {
1772− ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1773− cdclk_config->voltage_level);
1782+ ret = snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1783+ cdclk_config->voltage_level);
17741784 } else {
17751785 /*
17761786 * The timeout isn't specified, the 2ms used here is based on
@@ -1778,10 +1788,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, · 1 unmodified line
17781788 * FIXME: Waiting for the request completion could be delayed
17791789 * until the next PCODE request based on BSpec.
17801790 */
1781− ret = sandybridge_pcode_write_timeout(dev_priv,
1782− HSW_PCODE_DE_WRITE_FREQ_REQ,
1783− cdclk_config->voltage_level,
1784− 150, 2);
1791+ ret = snb_pcode_write_timeout(dev_priv,
1792+ HSW_PCODE_DE_WRITE_FREQ_REQ,
1793+ cdclk_config->voltage_level,
1794+ 150, 2);
17851795 }
17861796
17871797 if (ret) {
@@ -1807,7 +1817,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) · 19 unmodified lines
18071817 int cdclk, clock, vco;
18081818
18091819 intel_update_cdclk(dev_priv);
1810− intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
1820+ intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
18111821
18121822 if (dev_priv->cdclk.hw.vco == 0 ||
18131823 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
@@ -2047,13 +2057,14 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a, · 233 unmodified lines
20472057 a->voltage_level != b->voltage_level;
20482058 }
20492059
2050−void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
2060+void intel_cdclk_dump_config(struct drm_i915_private *i915,
2061+ const struct intel_cdclk_config *cdclk_config,
20512062 const char *context)
20522063 {
2053− DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2054− context, cdclk_config->cdclk, cdclk_config->vco,
2055− cdclk_config->ref, cdclk_config->bypass,
2056− cdclk_config->voltage_level);
2064+ drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2065+ context, cdclk_config->cdclk, cdclk_config->vco,
2066+ cdclk_config->ref, cdclk_config->bypass,
2067+ cdclk_config->voltage_level);
20572068 }
20582069
20592070 /**
@@ -2077,7 +2088,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, · 17 unmodified lines
20772088 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
20782089 return;
20792090
2080− intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
2091+ intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
20812092
20822093 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
20832094 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2120,8 +2131,8 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, · 36 unmodified lines
21202131 if (drm_WARN(&dev_priv->drm,
21212132 intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
21222133 "cdclk state doesn't match!\n")) {
2123− intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");
2124− intel_dump_cdclk_config(cdclk_config, "[sw state]");
2134+ intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "[hw state]");
2135+ intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]");
21252136 }
21262137 }
21272138
drivers/gpu/drm/i915/display/intel_cdclk.h+7−2
@@ -8,7 +8,6 @@ · 7 unmodified lines
88
99 #include <linux/types.h>
1010
11−#include "i915_drv.h"
1211 #include "intel_display.h"
1312 #include "intel_global_state.h"
1413
@@ -16,6 +15,11 @@ struct drm_i915_private; · 1 unmodified line
1615 struct intel_atomic_state;
1716 struct intel_crtc_state;
1817
18+struct intel_cdclk_config {
19+ unsigned int cdclk, vco, ref, bypass;
20+ u8 voltage_level;
21+};
22+
1923 struct intel_cdclk_state {
2024 struct intel_global_state base;
2125
@@ -58,7 +62,8 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, · 36 unmodified lines
5862 const struct intel_cdclk_config *b);
5963 void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
6064 void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
61−void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
65+void intel_cdclk_dump_config(struct drm_i915_private *i915,
66+ const struct intel_cdclk_config *cdclk_config,
6267 const char *context);
6368 int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
6469 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
drivers/gpu/drm/i915/display/intel_combo_phy.c+1−0
@@ -4,6 +4,7 @@ · 3 unmodified lines
44 */
55
66 #include "intel_combo_phy.h"
7+#include "intel_combo_phy_regs.h"
78 #include "intel_de.h"
89 #include "intel_display_types.h"
910
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h+162−0
@@ -0,0 +1,162 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2022 Intel Corporation
4+ */
5+
6+#ifndef __INTEL_COMBO_PHY_REGS__
7+#define __INTEL_COMBO_PHY_REGS__
8+
9+#include "i915_reg_defs.h"
10+
11+#define _ICL_COMBOPHY_A 0x162000
12+#define _ICL_COMBOPHY_B 0x6C000
13+#define _EHL_COMBOPHY_C 0x160000
14+#define _RKL_COMBOPHY_D 0x161000
15+#define _ADL_COMBOPHY_E 0x16B000
16+
17+#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
18+ _ICL_COMBOPHY_B, \
19+ _EHL_COMBOPHY_C, \
20+ _RKL_COMBOPHY_D, \
21+ _ADL_COMBOPHY_E)
22+
23+/* ICL Port CL_DW registers */
24+#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
25+ 4 * (dw))
26+
27+#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
28+#define CL_POWER_DOWN_ENABLE (1 << 4)
29+#define SUS_CLOCK_CONFIG (3 << 0)
30+
31+#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
32+#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
33+#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
34+#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
35+#define PWR_UP_ALL_LANES (0x0 << 4)
36+#define PWR_DOWN_LN_3_2_1 (0xe << 4)
37+#define PWR_DOWN_LN_3_2 (0xc << 4)
38+#define PWR_DOWN_LN_3 (0x8 << 4)
39+#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
40+#define PWR_DOWN_LN_1_0 (0x3 << 4)
41+#define PWR_DOWN_LN_3_1 (0xa << 4)
42+#define PWR_DOWN_LN_3_1_0 (0xb << 4)
43+#define PWR_DOWN_LN_MASK (0xf << 4)
44+#define PWR_DOWN_LN_SHIFT 4
45+#define EDP4K2K_MODE_OVRD_EN (1 << 3)
46+#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
47+
48+#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
49+#define ICL_LANE_ENABLE_AUX (1 << 0)
50+
51+/* ICL Port COMP_DW registers */
52+#define _ICL_PORT_COMP 0x100
53+#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
54+ _ICL_PORT_COMP + 4 * (dw))
55+
56+#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
57+#define COMP_INIT (1 << 31)
58+
59+#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
60+
61+#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
62+#define PROCESS_INFO_DOT_0 (0 << 26)
63+#define PROCESS_INFO_DOT_1 (1 << 26)
64+#define PROCESS_INFO_DOT_4 (2 << 26)
65+#define PROCESS_INFO_MASK (7 << 26)
66+#define PROCESS_INFO_SHIFT 26
67+#define VOLTAGE_INFO_0_85V (0 << 24)
68+#define VOLTAGE_INFO_0_95V (1 << 24)
69+#define VOLTAGE_INFO_1_05V (2 << 24)
70+#define VOLTAGE_INFO_MASK (3 << 24)
71+#define VOLTAGE_INFO_SHIFT 24
72+
73+#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
74+#define IREFGEN (1 << 24)
75+
76+#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
77+
78+#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
79+
80+/* ICL Port PCS registers */
81+#define _ICL_PORT_PCS_AUX 0x300
82+#define _ICL_PORT_PCS_GRP 0x600
83+#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
84+#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
85+ _ICL_PORT_PCS_AUX + 4 * (dw))
86+#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
87+ _ICL_PORT_PCS_GRP + 4 * (dw))
88+#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
89+ _ICL_PORT_PCS_LN(ln) + 4 * (dw))
90+#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
91+#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
92+#define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
93+#define DCC_MODE_SELECT_MASK (0x3 << 20)
94+#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
95+#define COMMON_KEEPER_EN (1 << 26)
96+#define LATENCY_OPTIM_MASK (0x3 << 2)
97+#define LATENCY_OPTIM_VAL(x) ((x) << 2)
98+
99+/* ICL Port TX registers */
100+#define _ICL_PORT_TX_AUX 0x380
101+#define _ICL_PORT_TX_GRP 0x680
102+#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
103+
104+#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
105+ _ICL_PORT_TX_AUX + 4 * (dw))
106+#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
107+ _ICL_PORT_TX_GRP + 4 * (dw))
108+#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
109+ _ICL_PORT_TX_LN(ln) + 4 * (dw))
110+
111+#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
112+#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
113+#define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
114+#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
115+#define SWING_SEL_UPPER_MASK (1 << 15)
116+#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
117+#define SWING_SEL_LOWER_MASK (0x7 << 11)
118+#define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
119+#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
120+#define RCOMP_SCALAR(x) ((x) << 0)
121+#define RCOMP_SCALAR_MASK (0xFF << 0)
122+
123+#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
124+#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
125+#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
126+#define LOADGEN_SELECT (1 << 31)
127+#define POST_CURSOR_1(x) ((x) << 12)
128+#define POST_CURSOR_1_MASK (0x3F << 12)
129+#define POST_CURSOR_2(x) ((x) << 6)
130+#define POST_CURSOR_2_MASK (0x3F << 6)
131+#define CURSOR_COEFF(x) ((x) << 0)
132+#define CURSOR_COEFF_MASK (0x3F << 0)
133+
134+#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
135+#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
136+#define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
137+#define TX_TRAINING_EN (1 << 31)
138+#define TAP2_DISABLE (1 << 30)
139+#define TAP3_DISABLE (1 << 29)
140+#define SCALING_MODE_SEL(x) ((x) << 18)
141+#define SCALING_MODE_SEL_MASK (0x7 << 18)
142+#define RTERM_SELECT(x) ((x) << 3)
143+#define RTERM_SELECT_MASK (0x7 << 3)
144+
145+#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
146+#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
147+#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
148+#define N_SCALAR(x) ((x) << 24)
149+#define N_SCALAR_MASK (0x7F << 24)
150+
151+#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
152+#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
153+#define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
154+#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
155+#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
156+#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
157+
158+#define _ICL_DPHY_CHKN_REG 0x194
159+#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
160+#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
161+
162+#endif /* __INTEL_COMBO_PHY_REGS__ */
drivers/gpu/drm/i915/display/intel_crt.h+1−1
@@ -6,7 +6,7 @@ · 5 unmodified lines
66 #ifndef __INTEL_CRT_H__
77 #define __INTEL_CRT_H__
88
9−#include "i915_reg.h"
9+#include "i915_reg_defs.h"
1010
1111 enum pipe;
1212 struct drm_encoder;
drivers/gpu/drm/i915/display/intel_crtc.c+1−0
@@ -12,6 +12,7 @@ · 11 unmodified lines
1212 #include <drm/drm_plane_helper.h>
1313 #include <drm/drm_vblank_work.h>
1414
15+#include "i915_irq.h"
1516 #include "i915_vgpu.h"
1617 #include "i9xx_plane.h"
1718 #include "icl_dsi.h"
drivers/gpu/drm/i915/display/intel_cursor.c+12−13
@@ -51,16 +51,16 @@ static u32 intel_cursor_position(const struct intel_plane_state *plane_state) · 50 unmodified lines
5151 u32 pos = 0;
5252
5353 if (x < 0) {
54− pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
54+ pos |= CURSOR_POS_X_SIGN;
5555 x = -x;
5656 }
57− pos |= x << CURSOR_X_SHIFT;
57+ pos |= CURSOR_POS_X(x);
5858
5959 if (y < 0) {
60− pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
60+ pos |= CURSOR_POS_Y_SIGN;
6161 y = -y;
6262 }
63− pos |= y << CURSOR_Y_SHIFT;
63+ pos |= CURSOR_POS_Y(y);
6464
6565 return pos;
6666 }
@@ -180,7 +180,7 @@ static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) · 113 unmodified lines
180180 u32 cntl = 0;
181181
182182 if (crtc_state->gamma_enable)
183− cntl |= CURSOR_GAMMA_ENABLE;
183+ cntl |= CURSOR_PIPE_GAMMA_ENABLE;
184184
185185 return cntl;
186186 }
@@ -264,7 +264,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane, · 77 unmodified lines
264264 cntl = plane_state->ctl |
265265 i845_cursor_ctl_crtc(crtc_state);
266266
267− size = (height << 12) | width;
267+ size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
268268
269269 base = intel_cursor_base(plane_state);
270270 pos = intel_cursor_position(plane_state);
@@ -280,7 +280,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane, · 9 unmodified lines
280280 plane->cursor.cntl != cntl) {
281281 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
282282 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
283− intel_de_write_fw(dev_priv, CURSIZE, size);
283+ intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
284284 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
285285 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
286286
@@ -340,13 +340,13 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) · 53 unmodified lines
340340 return cntl;
341341
342342 if (crtc_state->gamma_enable)
343− cntl = MCURSOR_GAMMA_ENABLE;
343+ cntl = MCURSOR_PIPE_GAMMA_ENABLE;
344344
345345 if (crtc_state->csc_enable)
346346 cntl |= MCURSOR_PIPE_CSC_ENABLE;
347347
348348 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
349− cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
349+ cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
350350
351351 return cntl;
352352 }
@@ -502,7 +502,7 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane, · 149 unmodified lines
502502 i9xx_cursor_ctl_crtc(crtc_state);
503503
504504 if (width != height)
505− fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
505+ fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
506506
507507 base = intel_cursor_base(plane_state);
508508 pos = intel_cursor_position(plane_state);
@@ -586,13 +586,12 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, · 77 unmodified lines
586586
587587 val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
588588
589− ret = val & MCURSOR_MODE;
589+ ret = val & MCURSOR_MODE_MASK;
590590
591591 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
592592 *pipe = plane->pipe;
593593 else
594− *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
595− MCURSOR_PIPE_SELECT_SHIFT;
594+ *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
596595
597596 intel_display_power_put(dev_priv, power_domain, wakeref);
598597
drivers/gpu/drm/i915/display/intel_ddi.c+16−127
@@ -32,6 +32,7 @@ · 31 unmodified lines
3232 #include "intel_audio.h"
3333 #include "intel_backlight.h"
3434 #include "intel_combo_phy.h"
35+#include "intel_combo_phy_regs.h"
3536 #include "intel_connector.h"
3637 #include "intel_crtc.h"
3738 #include "intel_ddi.h"
@@ -56,6 +57,7 @@ · 18 unmodified lines
5657 #include "intel_snps_phy.h"
5758 #include "intel_sprite.h"
5859 #include "intel_tc.h"
60+#include "intel_tc_phy_regs.h"
5961 #include "intel_vdsc.h"
6062 #include "intel_vrr.h"
6163 #include "skl_scaler.h"
@@ -2287,116 +2289,6 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) · 2225 unmodified lines
22872289 OVERLAP_PIXELS_MASK, dss1);
22882290 }
22892291
2290−static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
2291− struct intel_encoder *encoder,
2292− const struct intel_crtc_state *crtc_state,
2293− const struct drm_connector_state *conn_state)
2294−{
2295− struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2296− struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2297− struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2298− bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2299−
2300− intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2301− crtc_state->lane_count);
2302−
2303− /*
2304− * We only configure what the register value will be here. Actual
2305− * enabling happens during link training farther down.
2306− */
2307− intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2308−
2309− /*
2310− * 1. Enable Power Wells
2311− *
2312− * This was handled at the beginning of intel_atomic_commit_tail(),
2313− * before we called down into this function.
2314− */
2315−
2316− /* 2. Enable Panel Power if PPS is required */
2317− intel_pps_on(intel_dp);
2318−
2319− /*
2320− * 3. Enable the port PLL.
2321− */
2322− intel_ddi_enable_clock(encoder, crtc_state);
2323−
2324− /* 4. Enable IO power */
2325− if (!intel_tc_port_in_tbt_alt_mode(dig_port))
2326− dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2327− dig_port->ddi_io_power_domain);
2328−
2329− /*
2330− * 5. The rest of the below are substeps under the bspec's "Enable and
2331− * Train Display Port" step. Note that steps that are specific to
2332− * MST will be handled by intel_mst_pre_enable_dp() before/after it
2333− * calls into this function. Also intel_mst_pre_enable_dp() only calls
2334− * us when active_mst_links==0, so any steps designated for "single
2335− * stream or multi-stream master transcoder" can just be performed
2336− * unconditionally here.
2337− */
2338−
2339− /*
2340− * 5.a Configure Transcoder Clock Select to direct the Port clock to the
2341− * Transcoder.
2342− */
2343− intel_ddi_enable_pipe_clock(encoder, crtc_state);
2344−
2345− /* 5.b Configure transcoder for DP 2.0 128b/132b */
2346− intel_ddi_config_transcoder_dp2(encoder, crtc_state);
2347−
2348− /*
2349− * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2350− * Transport Select
2351− */
2352− intel_ddi_config_transcoder_func(encoder, crtc_state);
2353−
2354− /*
2355− * 5.d Configure & enable DP_TP_CTL with link training pattern 1
2356− * selected
2357− *
2358− * This will be handled by the intel_dp_start_link_train() farther
2359− * down this function.
2360− */
2361−
2362− /* 5.e Configure voltage swing and related IO settings */
2363− encoder->set_signal_levels(encoder, crtc_state);
2364−
2365− if (!is_mst)
2366− intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2367−
2368− intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2369− intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2370− /*
2371− * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2372− * in the FEC_CONFIGURATION register to 1 before initiating link
2373− * training
2374− */
2375− intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2376− intel_dp_check_frl_training(intel_dp);
2377− intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2378−
2379− /*
2380− * 5.h Follow DisplayPort specification training sequence (see notes for
2381− * failure handling)
2382− * 5.i If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2383− * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2384− * (timeout after 800 us)
2385− */
2386− intel_dp_start_link_train(intel_dp, crtc_state);
2387−
2388− /* 5.j Set DP_TP_CTL link training to Normal */
2389− if (!is_trans_port_sync_mode(crtc_state))
2390− intel_dp_stop_link_train(intel_dp, crtc_state);
2391−
2392− /* 5.k Configure and enable FEC if needed */
2393− intel_ddi_enable_fec(encoder, crtc_state);
2394−
2395− intel_dsc_dp_pps_write(encoder, crtc_state);
2396−
2397− intel_dsc_enable(crtc_state);
2398−}
2399−
24002292 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
24012293 struct intel_encoder *encoder,
24022294 const struct intel_crtc_state *crtc_state,
@@ -2470,6 +2362,9 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, · 67 unmodified lines
24702362 */
24712363 intel_ddi_enable_pipe_clock(encoder, crtc_state);
24722364
2365+ if (HAS_DP20(dev_priv))
2366+ intel_ddi_config_transcoder_dp2(encoder, crtc_state);
2367+
24732368 /*
24742369 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
24752370 * Transport Select
@@ -2530,9 +2425,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, · 54 unmodified lines
25302425 intel_ddi_enable_fec(encoder, crtc_state);
25312426
25322427 intel_dsc_dp_pps_write(encoder, crtc_state);
2533−
2534− if (!crtc_state->bigjoiner)
2535− intel_dsc_enable(crtc_state);
25362428 }
25372429
25382430 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2598,9 +2490,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, · 59 unmodified lines
25982490 intel_ddi_enable_pipe_clock(encoder, crtc_state);
25992491
26002492 intel_dsc_dp_pps_write(encoder, crtc_state);
2601−
2602− if (!crtc_state->bigjoiner)
2603− intel_dsc_enable(crtc_state);
26042493 }
26052494
26062495 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2610,9 +2499,7 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, · 3 unmodified lines
26102499 {
26112500 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
26122501
2613− if (IS_DG2(dev_priv))
2614− dg2_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2615− else if (DISPLAY_VER(dev_priv) >= 12)
2502+ if (DISPLAY_VER(dev_priv) >= 12)
26162503 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
26172504 else
26182505 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
@@ -2620,11 +2507,8 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, · 1 unmodified line
26202507 /* MST will call a setting of MSA after an allocating of Virtual Channel
26212508 * from MST encoder pre_enable callback.
26222509 */
2623− if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
2510+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
26242511 intel_ddi_set_dp_msa(crtc_state, conn_state);
2625−
2626− intel_dp_set_m_n(crtc_state, M1_N1);
2627− }
26282512 }
26292513
26302514 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
@@ -3471,7 +3355,11 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, · 840 unmodified lines
34713355 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
34723356 pipe_config->lane_count =
34733357 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3474− intel_dp_get_m_n(crtc, pipe_config);
3358+
3359+ intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3360+ &pipe_config->dp_m_n);
3361+ intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,
3362+ &pipe_config->dp_m2_n2);
34753363
34763364 if (DISPLAY_VER(dev_priv) >= 11) {
34773365 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
@@ -3508,7 +3396,8 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, · 30 unmodified lines
35083396 pipe_config->mst_master_transcoder =
35093397 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
35103398
3511− intel_dp_get_m_n(crtc, pipe_config);
3399+ intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3400+ &pipe_config->dp_m_n);
35123401
35133402 pipe_config->infoframes.enable |=
35143403 intel_hdmi_infoframes_enabled(encoder, pipe_config);
@@ -3797,8 +3686,8 @@ static bool m_n_equal(const struct intel_link_m_n *m_n_1, · 282 unmodified lines
37973686 const struct intel_link_m_n *m_n_2)
37983687 {
37993688 return m_n_1->tu == m_n_2->tu &&
3800− m_n_1->gmch_m == m_n_2->gmch_m &&
3801− m_n_1->gmch_n == m_n_2->gmch_n &&
3689+ m_n_1->data_m == m_n_2->data_m &&
3690+ m_n_1->data_n == m_n_2->data_n &&
38023691 m_n_1->link_m == m_n_2->link_m &&
38033692 m_n_1->link_n == m_n_2->link_n;
38043693 }
drivers/gpu/drm/i915/display/intel_ddi.h+1−1
@@ -6,7 +6,7 @@ · 5 unmodified lines
66 #ifndef __INTEL_DDI_H__
77 #define __INTEL_DDI_H__
88
9−#include "i915_reg.h"
9+#include "i915_reg_defs.h"
1010
1111 struct drm_connector_state;
1212 struct drm_i915_private;
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c+21−21
@@ -985,15 +985,15 @@ static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr2_hbr3 = { · 984 unmodified lines
985985 };
986986
987987 static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = {
988− { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */
989− { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */
990− { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */
991− { .snps = { 43, 0, 19 } }, /* VS 0, pre-emph 3 */
992− { .snps = { 39, 0, 0 } }, /* VS 1, pre-emph 0 */
993− { .snps = { 44, 0, 8 } }, /* VS 1, pre-emph 1 */
994− { .snps = { 47, 0, 15 } }, /* VS 1, pre-emph 2 */
995− { .snps = { 52, 0, 0 } }, /* VS 2, pre-emph 0 */
996− { .snps = { 51, 0, 10 } }, /* VS 2, pre-emph 1 */
988+ { .snps = { 25, 0, 0 } }, /* VS 0, pre-emph 0 */
989+ { .snps = { 32, 0, 6 } }, /* VS 0, pre-emph 1 */
990+ { .snps = { 35, 0, 10 } }, /* VS 0, pre-emph 2 */
991+ { .snps = { 43, 0, 17 } }, /* VS 0, pre-emph 3 */
992+ { .snps = { 35, 0, 0 } }, /* VS 1, pre-emph 0 */
993+ { .snps = { 45, 0, 8 } }, /* VS 1, pre-emph 1 */
994+ { .snps = { 48, 0, 14 } }, /* VS 1, pre-emph 2 */
995+ { .snps = { 47, 0, 0 } }, /* VS 2, pre-emph 0 */
996+ { .snps = { 55, 0, 7 } }, /* VS 2, pre-emph 1 */
997997 { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */
998998 };
999999
@@ -1005,21 +1005,21 @@ static const struct intel_ddi_buf_trans dg2_snps_trans = { · 5 unmodified lines
10051005
10061006 static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = {
10071007 { .snps = { 62, 0, 0 } }, /* preset 0 */
1008− { .snps = { 56, 0, 6 } }, /* preset 1 */
1009− { .snps = { 51, 0, 11 } }, /* preset 2 */
1010− { .snps = { 48, 0, 14 } }, /* preset 3 */
1011− { .snps = { 43, 0, 19 } }, /* preset 4 */
1008+ { .snps = { 55, 0, 7 } }, /* preset 1 */
1009+ { .snps = { 50, 0, 12 } }, /* preset 2 */
1010+ { .snps = { 44, 0, 18 } }, /* preset 3 */
1011+ { .snps = { 35, 0, 21 } }, /* preset 4 */
10121012 { .snps = { 59, 3, 0 } }, /* preset 5 */
10131013 { .snps = { 53, 3, 6 } }, /* preset 6 */
1014− { .snps = { 49, 3, 10 } }, /* preset 7 */
1015− { .snps = { 45, 3, 14 } }, /* preset 8 */
1016− { .snps = { 42, 3, 17 } }, /* preset 9 */
1014+ { .snps = { 48, 3, 11 } }, /* preset 7 */
1015+ { .snps = { 42, 5, 15 } }, /* preset 8 */
1016+ { .snps = { 37, 5, 20 } }, /* preset 9 */
10171017 { .snps = { 56, 6, 0 } }, /* preset 10 */
1018− { .snps = { 50, 6, 6 } }, /* preset 11 */
1019− { .snps = { 47, 6, 9 } }, /* preset 12 */
1020− { .snps = { 42, 6, 14 } }, /* preset 13 */
1021− { .snps = { 46, 8, 8 } }, /* preset 14 */
1022− { .snps = { 56, 3, 3 } }, /* preset 15 */
1018+ { .snps = { 48, 7, 7 } }, /* preset 11 */
1019+ { .snps = { 45, 7, 10 } }, /* preset 12 */
1020+ { .snps = { 39, 8, 15 } }, /* preset 13 */
1021+ { .snps = { 48, 14, 0 } }, /* preset 14 */
1022+ { .snps = { 45, 4, 4 } }, /* preset 15 */
10231023 };
10241024
10251025 static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
drivers/gpu/drm/i915/display/intel_de.h+0−1
@@ -7,7 +7,6 @@ · 6 unmodified lines
77 #define __INTEL_DE_H__
88
99 #include "i915_drv.h"
10−#include "i915_reg.h"
1110 #include "i915_trace.h"
1211 #include "intel_uncore.h"
1312
drivers/gpu/drm/i915/display/intel_display.c+275−296
@@ -118,9 +118,6 @@ · 117 unmodified lines
118118
119119 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
120120 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
121−static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
122− const struct intel_link_m_n *m_n,
123− const struct intel_link_m_n *m2_n2);
124121 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
125122 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
126123 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
@@ -353,16 +350,10 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, · 226 unmodified lines
353350 {
354351 i915_reg_t reg = PIPEDSL(pipe);
355352 u32 line1, line2;
356− u32 line_mask;
357353
358− if (DISPLAY_VER(dev_priv) == 2)
359− line_mask = DSL_LINEMASK_GEN2;
360− else
361− line_mask = DSL_LINEMASK_GEN3;
362−
363− line1 = intel_de_read(dev_priv, reg) & line_mask;
354+ line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
364355 msleep(5);
365− line2 = intel_de_read(dev_priv, reg) & line_mask;
356+ line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
366357
367358 return line1 != line2;
368359 }
@@ -397,13 +388,11 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) · 28 unmodified lines
397388
398389 if (DISPLAY_VER(dev_priv) >= 4) {
399390 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
400− i915_reg_t reg = PIPECONF(cpu_transcoder);
401391
402392 /* Wait for the Pipe State to go off */
403− if (intel_de_wait_for_clear(dev_priv, reg,
404− I965_PIPECONF_ACTIVE, 100))
405− drm_WARN(&dev_priv->drm, 1,
406− "pipe_off wait timed out\n");
393+ if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),
394+ PIPECONF_STATE_ENABLE, 100))
395+ drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
407396 } else {
408397 intel_wait_for_pipe_scanline_stopped(crtc);
409398 }
@@ -1118,8 +1107,8 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) · 708 unmodified lines
11181107 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
11191108
11201109 if (IS_BROADWELL(dev_priv)) {
1121− drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
1122− IPS_ENABLE | IPS_PCODE_CONTROL));
1110+ drm_WARN_ON(dev, snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
1111+ IPS_ENABLE | IPS_PCODE_CONTROL));
11231112 /* Quoting Art Runyan: "its not safe to expect any particular
11241113 * value in IPS_CTL bit 31 after enabling IPS through the
11251114 * mailbox." Moreover, the mailbox may return a bogus state,
@@ -1149,7 +1138,7 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state) · 23 unmodified lines
11491138
11501139 if (IS_BROADWELL(dev_priv)) {
11511140 drm_WARN_ON(dev,
1152− sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
1141+ snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
11531142 /*
11541143 * Wait for PCODE to finish disabling IPS. The BSpec specified
11551144 * 42ms timeout value leads to occasional timeouts so use 100ms
@@ -1369,7 +1358,8 @@ static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, · 213 unmodified lines
13691358 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13701359 if (plane->enable_flip_done &&
13711360 plane->pipe == crtc->pipe &&
1372− update_planes & BIT(plane->id))
1361+ update_planes & BIT(plane->id) &&
1362+ plane_state->do_async_flip)
13731363 plane->enable_flip_done(plane);
13741364 }
13751365 }
@@ -1387,7 +1377,8 @@ static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, · 11 unmodified lines
13871377 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13881378 if (plane->disable_flip_done &&
13891379 plane->pipe == crtc->pipe &&
1390− update_planes & BIT(plane->id))
1380+ update_planes & BIT(plane->id) &&
1381+ plane_state->do_async_flip)
13911382 plane->disable_flip_done(plane);
13921383 }
13931384 }
@@ -1817,6 +1808,26 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat · 423 unmodified lines
18171808 plane->disable_arm(plane, crtc_state);
18181809 }
18191810
1811+static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1812+{
1813+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1814+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1815+
1816+ if (crtc_state->has_pch_encoder) {
1817+ intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1818+ &crtc_state->fdi_m_n);
1819+ } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1820+ intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1821+ &crtc_state->dp_m_n);
1822+ intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1823+ &crtc_state->dp_m2_n2);
1824+ }
1825+
1826+ intel_set_transcoder_timings(crtc_state);
1827+
1828+ ilk_set_pipeconf(crtc_state);
1829+}
1830+
18201831 static void ilk_crtc_enable(struct intel_atomic_state *state,
18211832 struct intel_crtc *crtc)
18221833 {
@@ -1841,27 +1852,16 @@ static void ilk_crtc_enable(struct intel_atomic_state *state, · 18 unmodified lines
18411852 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
18421853 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
18431854
1844− if (intel_crtc_has_dp_encoder(new_crtc_state))
1845− intel_dp_set_m_n(new_crtc_state, M1_N1);
1855+ ilk_configure_cpu_transcoder(new_crtc_state);
18461856
1847− intel_set_transcoder_timings(new_crtc_state);
18481857 intel_set_pipe_src_size(new_crtc_state);
18491858
1850− if (new_crtc_state->has_pch_encoder)
1851− intel_cpu_transcoder_set_m_n(new_crtc_state,
1852− &new_crtc_state->fdi_m_n, NULL);
1853−
1854− ilk_set_pipeconf(new_crtc_state);
1855−
18561859 crtc->active = true;
18571860
18581861 intel_encoders_pre_enable(state, crtc);
18591862
18601863 if (new_crtc_state->has_pch_encoder) {
1861− /* Note: FDI PLL enabling _must_ be done before we enable the
1862− * cpu pipes, hence this is separate from all the other fdi/pch
1863− * enabling. */
1864− ilk_fdi_pll_enable(new_crtc_state);
1864+ ilk_pch_pre_enable(state, crtc);
18651865 } else {
18661866 assert_fdi_tx_disabled(dev_priv, pipe);
18671867 assert_fdi_rx_disabled(dev_priv, pipe);
@@ -1974,7 +1974,6 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) · 106 unmodified lines
19741974 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
19751975 const struct intel_crtc_state *crtc_state)
19761976 {
1977− struct drm_i915_private *dev_priv = to_i915(state->base.dev);
19781977 struct intel_crtc_state *master_crtc_state;
19791978 struct intel_crtc *master_crtc;
19801979 struct drm_connector_state *conn_state;
@@ -2004,12 +2003,33 @@ static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, · 23 unmodified lines
20042003
20052004 if (crtc_state->bigjoiner_slave)
20062005 intel_encoders_pre_enable(state, master_crtc);
2006+}
20072007
2008− /* need to enable VDSC, which we skipped in pre-enable */
2009− intel_dsc_enable(crtc_state);
2008+static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
2009+{
2010+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2011+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2012+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
20102013
2011− if (DISPLAY_VER(dev_priv) >= 13)
2012− intel_uncompressed_joiner_enable(crtc_state);
2014+ if (crtc_state->has_pch_encoder) {
2015+ intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
2016+ &crtc_state->fdi_m_n);
2017+ } else if (intel_crtc_has_dp_encoder(crtc_state)) {
2018+ intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
2019+ &crtc_state->dp_m_n);
2020+ intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
2021+ &crtc_state->dp_m2_n2);
2022+ }
2023+
2024+ intel_set_transcoder_timings(crtc_state);
2025+
2026+ if (cpu_transcoder != TRANSCODER_EDP)
2027+ intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
2028+ crtc_state->pixel_multiplier - 1);
2029+
2030+ hsw_set_frame_start_delay(crtc_state);
2031+
2032+ hsw_set_transconf(crtc_state);
20132033 }
20142034
20152035 static void hsw_crtc_enable(struct intel_atomic_state *state,
@@ -2036,25 +2056,17 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, · 20 unmodified lines
20362056 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
20372057 }
20382058
2059+ intel_dsc_enable(new_crtc_state);
2060+
2061+ if (DISPLAY_VER(dev_priv) >= 13)
2062+ intel_uncompressed_joiner_enable(new_crtc_state);
2063+
20392064 intel_set_pipe_src_size(new_crtc_state);
20402065 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
20412066 bdw_set_pipemisc(new_crtc_state);
20422067
2043− if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
2044− intel_set_transcoder_timings(new_crtc_state);
2045−
2046− if (cpu_transcoder != TRANSCODER_EDP)
2047− intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
2048− new_crtc_state->pixel_multiplier - 1);
2049−
2050− if (new_crtc_state->has_pch_encoder)
2051− intel_cpu_transcoder_set_m_n(new_crtc_state,
2052− &new_crtc_state->fdi_m_n, NULL);
2053−
2054− hsw_set_frame_start_delay(new_crtc_state);
2055−
2056− hsw_set_transconf(new_crtc_state);
2057− }
2068+ if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder))
2069+ hsw_configure_cpu_transcoder(new_crtc_state);
20582070
20592071 crtc->active = true;
20602072
@@ -2441,6 +2453,23 @@ static void modeset_put_crtc_power_domains(struct intel_crtc *crtc, · 380 unmodified lines
24412453 domains);
24422454 }
24432455
2456+static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
2457+{
2458+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2459+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2460+
2461+ if (intel_crtc_has_dp_encoder(crtc_state)) {
2462+ intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
2463+ &crtc_state->dp_m_n);
2464+ intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
2465+ &crtc_state->dp_m2_n2);
2466+ }
2467+
2468+ intel_set_transcoder_timings(crtc_state);
2469+
2470+ i9xx_set_pipeconf(crtc_state);
2471+}
2472+
24442473 static void valleyview_crtc_enable(struct intel_atomic_state *state,
24452474 struct intel_crtc *crtc)
24462475 {
@@ -2452,10 +2481,8 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state, · 5 unmodified lines
24522481 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
24532482 return;
24542483
2455− if (intel_crtc_has_dp_encoder(new_crtc_state))
2456− intel_dp_set_m_n(new_crtc_state, M1_N1);
2484+ i9xx_configure_cpu_transcoder(new_crtc_state);
24572485
2458− intel_set_transcoder_timings(new_crtc_state);
24592486 intel_set_pipe_src_size(new_crtc_state);
24602487
24612488 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
@@ -2463,8 +2490,6 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state, · 1 unmodified line
24632490 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
24642491 }
24652492
2466− i9xx_set_pipeconf(new_crtc_state);
2467−
24682493 crtc->active = true;
24692494
24702495 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -2504,14 +2529,10 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state, · 33 unmodified lines
25042529 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
25052530 return;
25062531
2507− if (intel_crtc_has_dp_encoder(new_crtc_state))
2508− intel_dp_set_m_n(new_crtc_state, M1_N1);
2532+ i9xx_configure_cpu_transcoder(new_crtc_state);
25092533
2510− intel_set_transcoder_timings(new_crtc_state);
25112534 intel_set_pipe_src_size(new_crtc_state);
25122535
2513− i9xx_set_pipeconf(new_crtc_state);
2514−
25152536 crtc->active = true;
25162537
25172538 if (DISPLAY_VER(dev_priv) != 2)
@@ -3085,7 +3106,7 @@ intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, · 567 unmodified lines
30853106 m_n->tu = 64;
30863107 compute_m_n(data_clock,
30873108 link_clock * nlanes * 8,
3088− &m_n->gmch_m, &m_n->gmch_n,
3109+ &m_n->data_m, &m_n->data_n,
30893110 constant_n);
30903111
30913112 compute_m_n(pixel_clock, link_clock,
@@ -3116,99 +3137,66 @@ static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) · 24 unmodified lines
31163137 }
31173138 }
31183139
3119−static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
3120− const struct intel_link_m_n *m_n)
3140+void intel_zero_m_n(struct intel_link_m_n *m_n)
31213141 {
3122− struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3123− struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3124− enum pipe pipe = crtc->pipe;
3142+ /* corresponds to 0 register value */
3143+ memset(m_n, 0, sizeof(*m_n));
3144+ m_n->tu = 1;
3145+}
31253146
3126− intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
3127− TU_SIZE(m_n->tu) | m_n->gmch_m);
3128− intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
3129− intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
3130− intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
3147+void intel_set_m_n(struct drm_i915_private *i915,
3148+ const struct intel_link_m_n *m_n,
3149+ i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3150+ i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3151+{
3152+ intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
3153+ intel_de_write(i915, data_n_reg, m_n->data_n);
3154+ intel_de_write(i915, link_m_reg, m_n->link_m);
3155+ /*
3156+ * On BDW+ writing LINK_N arms the double buffered update
3157+ * of all the M/N registers, so it must be written last.
3158+ */
3159+ intel_de_write(i915, link_n_reg, m_n->link_n);
31313160 }
31323161
3133−static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
3134− enum transcoder transcoder)
3162+bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
3163+ enum transcoder transcoder)
31353164 {
31363165 if (IS_HASWELL(dev_priv))
31373166 return transcoder == TRANSCODER_EDP;
31383167
3139− /*
3140− * Strictly speaking some registers are available before
3141− * gen7, but we only support DRRS on gen7+
3142− */
3143− return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv);
3168+ return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
31443169 }
31453170
3146−static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
3147− const struct intel_link_m_n *m_n,
3148− const struct intel_link_m_n *m2_n2)
3171+void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
3172+ enum transcoder transcoder,
3173+ const struct intel_link_m_n *m_n)
31493174 {
3150− struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
31513175 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
31523176 enum pipe pipe = crtc->pipe;
3153− enum transcoder transcoder = crtc_state->cpu_transcoder;
31543177
3155− if (DISPLAY_VER(dev_priv) >= 5) {
3156− intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
3157− TU_SIZE(m_n->tu) | m_n->gmch_m);
3158− intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
3159− m_n->gmch_n);
3160− intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
3161− m_n->link_m);
3162− intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
3163− m_n->link_n);
3164− /*
3165− * M2_N2 registers are set only if DRRS is supported
3166− * (to make sure the registers are not unnecessarily accessed).
3167− */
3168− if (m2_n2 && crtc_state->has_drrs &&
3169− transcoder_has_m2_n2(dev_priv, transcoder)) {
3170− intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
3171− TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
3172− intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
3173− m2_n2->gmch_n);
3174− intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
3175− m2_n2->link_m);
3176− intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
3177− m2_n2->link_n);
3178− }
3179− } else {
3180− intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
3181− TU_SIZE(m_n->tu) | m_n->gmch_m);
3182− intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
3183− intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
3184− intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
3185− }
3178+ if (DISPLAY_VER(dev_priv) >= 5)
3179+ intel_set_m_n(dev_priv, m_n,
3180+ PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3181+ PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
3182+ else
3183+ intel_set_m_n(dev_priv, m_n,
3184+ PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3185+ PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
31863186 }
31873187
3188−void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
3188+void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
3189+ enum transcoder transcoder,
3190+ const struct intel_link_m_n *m_n)
31893191 {
3190− const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
3191− struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
3192−
3193− if (m_n == M1_N1) {
3194− dp_m_n = &crtc_state->dp_m_n;
3195− dp_m2_n2 = &crtc_state->dp_m2_n2;
3196− } else if (m_n == M2_N2) {
3192+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
31973193
3198− /*
3199− * M2_N2 registers are not supported. Hence m2_n2 divider value
3200− * needs to be programmed into M1_N1.
3201− */
3202− dp_m_n = &crtc_state->dp_m2_n2;
3203− } else {
3204− drm_err(&i915->drm, "Unsupported divider value\n");
3194+ if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
32053195 return;
3206− }
32073196
3208− if (crtc_state->has_pch_encoder)
3209− intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
3210− else
3211− intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
3197+ intel_set_m_n(dev_priv, m_n,
3198+ PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3199+ PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
32123200 }
32133201
32143202 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
@@ -3279,7 +3267,8 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) · 64 unmodified lines
32793267 * always be the user's requested size.
32803268 */
32813269 intel_de_write(dev_priv, PIPESRC(pipe),
3282− ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
3270+ PIPESRC_WIDTH(crtc_state->pipe_src_w - 1) |
3271+ PIPESRC_HEIGHT(crtc_state->pipe_src_h - 1));
32833272 }
32843273
32853274 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
@@ -3350,8 +3339,8 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc, · 64 unmodified lines
33503339 u32 tmp;
33513340
33523341 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
3353− pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
3354− pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
3342+ pipe_config->pipe_src_w = REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1;
3343+ pipe_config->pipe_src_h = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1;
33553344 }
33563345
33573346 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
@@ -3379,13 +3368,13 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) · 21 unmodified lines
33793368
33803369 switch (crtc_state->pipe_bpp) {
33813370 case 18:
3382− pipeconf |= PIPECONF_6BPC;
3371+ pipeconf |= PIPECONF_BPC_6;
33833372 break;
33843373 case 24:
3385− pipeconf |= PIPECONF_8BPC;
3374+ pipeconf |= PIPECONF_BPC_8;
33863375 break;
33873376 case 30:
3388− pipeconf |= PIPECONF_10BPC;
3377+ pipeconf |= PIPECONF_BPC_10;
33893378 break;
33903379 default:
33913380 /* Case prevented by intel_choose_pipe_bpp_dither. */
@@ -3400,7 +3389,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) · 8 unmodified lines
34003389 else
34013390 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
34023391 } else {
3403− pipeconf |= PIPECONF_PROGRESSIVE;
3392+ pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;
34043393 }
34053394
34063395 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
@@ -3543,11 +3532,11 @@ static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) · 136 unmodified lines
35433532
35443533 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
35453534
3546− if (tmp & DISPPLANE_GAMMA_ENABLE)
3535+ if (tmp & DISP_PIPE_GAMMA_ENABLE)
35473536 crtc_state->gamma_enable = true;
35483537
35493538 if (!HAS_GMCH(dev_priv) &&
3550− tmp & DISPPLANE_PIPE_CSC_ENABLE)
3539+ tmp & DISP_PIPE_CSC_ENABLE)
35513540 crtc_state->csc_enable = true;
35523541 }
35533542
@@ -3578,16 +3567,17 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, · 24 unmodified lines
35783567 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
35793568 IS_CHERRYVIEW(dev_priv)) {
35803569 switch (tmp & PIPECONF_BPC_MASK) {
3581− case PIPECONF_6BPC:
3570+ case PIPECONF_BPC_6:
35823571 pipe_config->pipe_bpp = 18;
35833572 break;
3584− case PIPECONF_8BPC:
3573+ case PIPECONF_BPC_8:
35853574 pipe_config->pipe_bpp = 24;
35863575 break;
3587− case PIPECONF_10BPC:
3576+ case PIPECONF_BPC_10:
35883577 pipe_config->pipe_bpp = 30;
35893578 break;
35903579 default:
3580+ MISSING_CASE(tmp);
35913581 break;
35923582 }
35933583 }
@@ -3596,8 +3586,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, · 2 unmodified lines
35963586 (tmp & PIPECONF_COLOR_RANGE_SELECT))
35973587 pipe_config->limited_color_range = true;
35983588
3599− pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
3600− PIPECONF_GAMMA_MODE_SHIFT;
3589+ pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp);
36013590
36023591 if (IS_CHERRYVIEW(dev_priv))
36033592 pipe_config->cgm_mode = intel_de_read(dev_priv,
@@ -3684,16 +3673,16 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) · 80 unmodified lines
36843673
36853674 switch (crtc_state->pipe_bpp) {
36863675 case 18:
3687− val |= PIPECONF_6BPC;
3676+ val |= PIPECONF_BPC_6;
36883677 break;
36893678 case 24:
3690− val |= PIPECONF_8BPC;
3679+ val |= PIPECONF_BPC_8;
36913680 break;
36923681 case 30:
3693− val |= PIPECONF_10BPC;
3682+ val |= PIPECONF_BPC_10;
36943683 break;
36953684 case 36:
3696− val |= PIPECONF_12BPC;
3685+ val |= PIPECONF_BPC_12;
36973686 break;
36983687 default:
36993688 /* Case prevented by intel_choose_pipe_bpp_dither. */
@@ -3701,12 +3690,12 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) · 1 unmodified line
37013690 }
37023691
37033692 if (crtc_state->dither)
3704− val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
3693+ val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
37053694
37063695 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3707− val |= PIPECONF_INTERLACED_ILK;
3696+ val |= PIPECONF_INTERLACE_IF_ID_ILK;
37083697 else
3709− val |= PIPECONF_PROGRESSIVE;
3698+ val |= PIPECONF_INTERLACE_PF_PD_ILK;
37103699
37113700 /*
37123701 * This would end up with an odd purple hue over
@@ -3738,12 +3727,12 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) · 25 unmodified lines
37383727 u32 val = 0;
37393728
37403729 if (IS_HASWELL(dev_priv) && crtc_state->dither)
3741− val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
3730+ val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
37423731
37433732 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3744− val |= PIPECONF_INTERLACED_ILK;
3733+ val |= PIPECONF_INTERLACE_IF_ID_ILK;
37453734 else
3746− val |= PIPECONF_PROGRESSIVE;
3735+ val |= PIPECONF_INTERLACE_PF_PD_ILK;
37473736
37483737 if (IS_HASWELL(dev_priv) &&
37493738 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
@@ -3765,18 +3754,18 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) · 15 unmodified lines
37653754
37663755 switch (crtc_state->pipe_bpp) {
37673756 case 18:
3768− val |= PIPEMISC_6_BPC;
3757+ val |= PIPEMISC_BPC_6;
37693758 break;
37703759 case 24:
3771− val |= PIPEMISC_8_BPC;
3760+ val |= PIPEMISC_BPC_8;
37723761 break;
37733762 case 30:
3774− val |= PIPEMISC_10_BPC;
3763+ val |= PIPEMISC_BPC_10;
37753764 break;
37763765 case 36:
37773766 /* Port output 12BPC defined for ADLP+ */
37783767 if (DISPLAY_VER(dev_priv) > 12)
3779− val |= PIPEMISC_12_BPC_ADLP;
3768+ val |= PIPEMISC_BPC_12_ADLP;
37803769 break;
37813770 default:
37823771 MISSING_CASE(crtc_state->pipe_bpp);
@@ -3812,7 +3801,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) · 29 unmodified lines
38123801 }
38133802
38143803 intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
3815− PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
3804+ PIPE_MISC2_BUBBLE_COUNTER_MASK,
38163805 scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
38173806 PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
38183807 }
@@ -3828,11 +3817,11 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) · 9 unmodified lines
38283817 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
38293818
38303819 switch (tmp & PIPEMISC_BPC_MASK) {
3831− case PIPEMISC_6_BPC:
3820+ case PIPEMISC_BPC_6:
38323821 return 18;
3833− case PIPEMISC_8_BPC:
3822+ case PIPEMISC_BPC_8:
38343823 return 24;
3835− case PIPEMISC_10_BPC:
3824+ case PIPEMISC_BPC_10:
38363825 return 30;
38373826 /*
38383827 * PORT OUTPUT 12 BPC defined for ADLP+.
@@ -3844,7 +3833,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) · 5 unmodified lines
38443833 * on older platforms, need to find a workaround for 12 BPC
38453834 * MIPI DSI HW readout.
38463835 */
3847− case PIPEMISC_12_BPC_ADLP:
3836+ case PIPEMISC_BPC_12_ADLP:
38483837 if (DISPLAY_VER(dev_priv) > 12)
38493838 return 36;
38503839 fallthrough;
@@ -3865,83 +3854,47 @@ int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) · 14 unmodified lines
38653854 return DIV_ROUND_UP(bps, link_bw * 8);
38663855 }
38673856
3868−static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
3869− struct intel_link_m_n *m_n)
3857+void intel_get_m_n(struct drm_i915_private *i915,
3858+ struct intel_link_m_n *m_n,
3859+ i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3860+ i915_reg_t link_m_reg, i915_reg_t link_n_reg)
38703861 {
3871− struct drm_device *dev = crtc->base.dev;
3872− struct drm_i915_private *dev_priv = to_i915(dev);
3873− enum pipe pipe = crtc->pipe;
3874−
3875− m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
3876− m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
3877− m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
3878− & ~TU_SIZE_MASK;
3879− m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
3880− m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
3881− & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
3862+ m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3863+ m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3864+ m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3865+ m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3866+ m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
38823867 }
38833868
3884−static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
3885− enum transcoder transcoder,
3886− struct intel_link_m_n *m_n,
3887− struct intel_link_m_n *m2_n2)
3869+void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3870+ enum transcoder transcoder,
3871+ struct intel_link_m_n *m_n)
38883872 {
38893873 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
38903874 enum pipe pipe = crtc->pipe;
38913875
3892− if (DISPLAY_VER(dev_priv) >= 5) {
3893− m_n->link_m = intel_de_read(dev_priv,
3894− PIPE_LINK_M1(transcoder));
3895− m_n->link_n = intel_de_read(dev_priv,
3896− PIPE_LINK_N1(transcoder));
3897− m_n->gmch_m = intel_de_read(dev_priv,
3898− PIPE_DATA_M1(transcoder))
3899− & ~TU_SIZE_MASK;
3900− m_n->gmch_n = intel_de_read(dev_priv,
3901− PIPE_DATA_N1(transcoder));
3902− m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
3903− & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
3904−
3905− if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
3906− m2_n2->link_m = intel_de_read(dev_priv,
3907− PIPE_LINK_M2(transcoder));
3908− m2_n2->link_n = intel_de_read(dev_priv,
3909− PIPE_LINK_N2(transcoder));
3910− m2_n2->gmch_m = intel_de_read(dev_priv,
3911− PIPE_DATA_M2(transcoder))
3912− & ~TU_SIZE_MASK;
3913− m2_n2->gmch_n = intel_de_read(dev_priv,
3914− PIPE_DATA_N2(transcoder));
3915− m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
3916− & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
3917− }
3918− } else {
3919− m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
3920− m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
3921− m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
3922− & ~TU_SIZE_MASK;
3923− m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
3924− m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
3925− & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
3926− }
3927−}
3928−
3929−void intel_dp_get_m_n(struct intel_crtc *crtc,
3930− struct intel_crtc_state *pipe_config)
3931−{
3932− if (pipe_config->has_pch_encoder)
3933− intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
3876+ if (DISPLAY_VER(dev_priv) >= 5)
3877+ intel_get_m_n(dev_priv, m_n,
3878+ PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3879+ PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
39343880 else
3935− intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
3936− &pipe_config->dp_m_n,
3937− &pipe_config->dp_m2_n2);
3881+ intel_get_m_n(dev_priv, m_n,
3882+ PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3883+ PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
39383884 }
39393885
3940−void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
3941− struct intel_crtc_state *pipe_config)
3886+void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3887+ enum transcoder transcoder,
3888+ struct intel_link_m_n *m_n)
39423889 {
3943− intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
3944− &pipe_config->fdi_m_n, NULL);
3890+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3891+
3892+ if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3893+ return;
3894+
3895+ intel_get_m_n(dev_priv, m_n,
3896+ PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3897+ PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
39453898 }
39463899
39473900 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
@@ -4037,16 +3990,16 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, · 89 unmodified lines
40373990 goto out;
40383991
40393992 switch (tmp & PIPECONF_BPC_MASK) {
4040− case PIPECONF_6BPC:
3993+ case PIPECONF_BPC_6:
40413994 pipe_config->pipe_bpp = 18;
40423995 break;
4043− case PIPECONF_8BPC:
3996+ case PIPECONF_BPC_8:
40443997 pipe_config->pipe_bpp = 24;
40453998 break;
4046− case PIPECONF_10BPC:
3999+ case PIPECONF_BPC_10:
40474000 pipe_config->pipe_bpp = 30;
40484001 break;
4049− case PIPECONF_12BPC:
4002+ case PIPECONF_BPC_12:
40504003 pipe_config->pipe_bpp = 36;
40514004 break;
40524005 default:
@@ -4066,8 +4019,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, · 13 unmodified lines
40664019 break;
40674020 }
40684021
4069− pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
4070− PIPECONF_GAMMA_MODE_SHIFT;
4022+ pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
40714023
40724024 pipe_config->csc_mode = intel_de_read(dev_priv,
40734025 PIPE_CSC_MODE(crtc->pipe));
@@ -4380,13 +4332,13 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, · 306 unmodified lines
43804332 active = true;
43814333 }
43824334
4335+ if (!active)
4336+ goto out;
4337+
43834338 intel_dsc_get_config(pipe_config);
43844339 if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable)
43854340 intel_uncompressed_joiner_get_config(pipe_config);
43864341
4387− if (!active)
4388− goto out;
4389−
43904342 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
43914343 DISPLAY_VER(dev_priv) >= 11)
43924344 intel_get_transcoder_timings(crtc, pipe_config);
@@ -4908,6 +4860,28 @@ static bool needs_scaling(const struct intel_plane_state *state) · 515 unmodified lines
49084860 return (src_w != dst_w || src_h != dst_h);
49094861 }
49104862
4863+static bool intel_plane_do_async_flip(struct intel_plane *plane,
4864+ const struct intel_crtc_state *old_crtc_state,
4865+ const struct intel_crtc_state *new_crtc_state)
4866+{
4867+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
4868+
4869+ if (!plane->async_flip)
4870+ return false;
4871+
4872+ if (!new_crtc_state->uapi.async_flip)
4873+ return false;
4874+
4875+ /*
4876+ * In platforms after DISPLAY13, we might need to override
4877+ * first async flip in order to change watermark levels
4878+ * as part of optimization.
4879+ * So for those, we are checking if this is a first async flip.
4880+ * For platforms earlier than DISPLAY13 we always do async flip.
4881+ */
4882+ return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
4883+}
4884+
49114885 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
49124886 struct intel_crtc_state *new_crtc_state,
49134887 const struct intel_plane_state *old_plane_state,
@@ -5027,6 +5001,9 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat · 113 unmodified lines
50275001 needs_scaling(new_plane_state))))
50285002 new_crtc_state->disable_lp_wm = true;
50295003
5004+ if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
5005+ new_plane_state->do_async_flip = true;
5006+
50305007 return 0;
50315008 }
50325009
@@ -5491,9 +5468,9 @@ intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, · 458 unmodified lines
54915468 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
54925469
54935470 drm_dbg_kms(&i915->drm,
5494− "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
5471+ "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
54955472 id, lane_count,
5496− m_n->gmch_m, m_n->gmch_n,
5473+ m_n->data_m, m_n->data_n,
54975474 m_n->link_m, m_n->link_n, m_n->tu);
54985475 }
54995476
@@ -5658,11 +5635,11 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, · 158 unmodified lines
56585635
56595636 if (intel_crtc_has_dp_encoder(pipe_config)) {
56605637 intel_dump_m_n_config(pipe_config, "dp m_n",
5661− pipe_config->lane_count, &pipe_config->dp_m_n);
5662− if (pipe_config->has_drrs)
5663− intel_dump_m_n_config(pipe_config, "dp m2_n2",
5664− pipe_config->lane_count,
5665− &pipe_config->dp_m2_n2);
5638+ pipe_config->lane_count,
5639+ &pipe_config->dp_m_n);
5640+ intel_dump_m_n_config(pipe_config, "dp m2_n2",
5641+ pipe_config->lane_count,
5642+ &pipe_config->dp_m2_n2);
56665643 }
56675644
56685645 drm_dbg_kms(&dev_priv->drm,
@@ -6189,8 +6166,8 @@ intel_compare_link_m_n(const struct intel_link_m_n *m_n, · 520 unmodified lines
61896166 bool exact)
61906167 {
61916168 return m_n->tu == m2_n2->tu &&
6192− intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
6193− m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
6169+ intel_compare_m_n(m_n->data_m, m_n->data_n,
6170+ m2_n2->data_m, m2_n2->data_n, exact) &&
61946171 intel_compare_m_n(m_n->link_m, m_n->link_n,
61956172 m2_n2->link_m, m2_n2->link_n, exact);
61966173 }
@@ -6389,16 +6366,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, · 192 unmodified lines
63896366 &pipe_config->name,\
63906367 !fastset)) { \
63916368 pipe_config_mismatch(fastset, crtc, __stringify(name), \
6392− "(expected tu %i gmch %i/%i link %i/%i, " \
6393− "found tu %i, gmch %i/%i link %i/%i)", \
6369+ "(expected tu %i data %i/%i link %i/%i, " \
6370+ "found tu %i, data %i/%i link %i/%i)", \
63946371 current_config->name.tu, \
6395− current_config->name.gmch_m, \
6396− current_config->name.gmch_n, \
6372+ current_config->name.data_m, \
6373+ current_config->name.data_n, \
63976374 current_config->name.link_m, \
63986375 current_config->name.link_n, \
63996376 pipe_config->name.tu, \
6400− pipe_config->name.gmch_m, \
6401− pipe_config->name.gmch_n, \
6377+ pipe_config->name.data_m, \
6378+ pipe_config->name.data_n, \
64026379 pipe_config->name.link_m, \
64036380 pipe_config->name.link_n); \
64046381 ret = false; \
@@ -6416,22 +6393,22 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, · 11 unmodified lines
64166393 !intel_compare_link_m_n(&current_config->alt_name, \
64176394 &pipe_config->name, !fastset)) { \
64186395 pipe_config_mismatch(fastset, crtc, __stringify(name), \
6419− "(expected tu %i gmch %i/%i link %i/%i, " \
6420− "or tu %i gmch %i/%i link %i/%i, " \
6421− "found tu %i, gmch %i/%i link %i/%i)", \
6396+ "(expected tu %i data %i/%i link %i/%i, " \
6397+ "or tu %i data %i/%i link %i/%i, " \
6398+ "found tu %i, data %i/%i link %i/%i)", \
64226399 current_config->name.tu, \
6423− current_config->name.gmch_m, \
6424− current_config->name.gmch_n, \
6400+ current_config->name.data_m, \
6401+ current_config->name.data_n, \
64256402 current_config->name.link_m, \
64266403 current_config->name.link_n, \
64276404 current_config->alt_name.tu, \
6428− current_config->alt_name.gmch_m, \
6429− current_config->alt_name.gmch_n, \
6405+ current_config->alt_name.data_m, \
6406+ current_config->alt_name.data_n, \
64306407 current_config->alt_name.link_m, \
64316408 current_config->alt_name.link_n, \
64326409 pipe_config->name.tu, \
6433− pipe_config->name.gmch_m, \
6434− pipe_config->name.gmch_n, \
6410+ pipe_config->name.data_m, \
6411+ pipe_config->name.data_n, \
64356412 pipe_config->name.link_m, \
64366413 pipe_config->name.link_n); \
64376414 ret = false; \
@@ -6510,13 +6487,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, · 72 unmodified lines
65106487 PIPE_CONF_CHECK_I(lane_count);
65116488 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
65126489
6513− if (DISPLAY_VER(dev_priv) < 8) {
6514− PIPE_CONF_CHECK_M_N(dp_m_n);
6515−
6516− if (current_config->has_drrs)
6517− PIPE_CONF_CHECK_M_N(dp_m2_n2);
6518− } else
6490+ if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
65196491 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
6492+ } else {
6493+ PIPE_CONF_CHECK_M_N(dp_m_n);
6494+ PIPE_CONF_CHECK_M_N(dp_m2_n2);
6495+ }
65206496
65216497 PIPE_CONF_CHECK_X(output_types);
65226498
@@ -7600,6 +7576,7 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, · 1077 unmodified lines
76007576 struct intel_crtc_state *old_crtc_state,
76017577 struct intel_crtc_state *new_crtc_state)
76027578 {
7579+ struct drm_i915_private *i915 = to_i915(state->base.dev);
76037580 struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
76047581 struct intel_crtc *slave_crtc, *master_crtc;
76057582
@@ -7617,9 +7594,10 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, · 11 unmodified lines
76177594
76187595 slave_crtc = intel_dsc_get_bigjoiner_secondary(crtc);
76197596 if (!slave_crtc) {
7620− DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
7621− "CRTC + 1 to be used, doesn't exist\n",
7622− crtc->base.base.id, crtc->base.name);
7597+ drm_dbg_kms(&i915->drm,
7598+ "[CRTC:%d:%s] Big joiner configuration requires "
7599+ "CRTC + 1 to be used, doesn't exist\n",
7600+ crtc->base.base.id, crtc->base.name);
76237601 return -EINVAL;
76247602 }
76257603
@@ -7633,16 +7611,18 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, · 7 unmodified lines
76337611 if (slave_crtc_state->uapi.enable)
76347612 goto claimed;
76357613
7636− DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
7637− slave_crtc->base.base.id, slave_crtc->base.name);
7614+ drm_dbg_kms(&i915->drm,
7615+ "[CRTC:%d:%s] Used as slave for big joiner\n",
7616+ slave_crtc->base.base.id, slave_crtc->base.name);
76387617
76397618 return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
76407619
76417620 claimed:
7642− DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
7643− "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
7644− slave_crtc->base.base.id, slave_crtc->base.name,
7645− master_crtc->base.base.id, master_crtc->base.name);
7621+ drm_dbg_kms(&i915->drm,
7622+ "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
7623+ "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
7624+ slave_crtc->base.base.id, slave_crtc->base.name,
7625+ master_crtc->base.base.id, master_crtc->base.name);
76467626 return -EINVAL;
76477627 }
76487628
@@ -9478,7 +9458,7 @@ void intel_modeset_init_hw(struct drm_i915_private *i915) · 1829 unmodified lines
94789458 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
94799459
94809460 intel_update_cdclk(i915);
9481− intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
9461+ intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK");
94829462 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
94839463 }
94849464
@@ -9980,8 +9960,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) · 495 unmodified lines
99809960 udelay(150); /* wait for warmup */
99819961 }
99829962
9983− intel_de_write(dev_priv, PIPECONF(pipe),
9984− PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
9963+ intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE);
99859964 intel_de_posting_read(dev_priv, PIPECONF(pipe));
99869965
99879966 intel_wait_for_pipe_scanline_moving(crtc);
@@ -9995,18 +9974,15 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) · 7 unmodified lines
99959974 pipe_name(pipe));
99969975
99979976 drm_WARN_ON(&dev_priv->drm,
9998− intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
9999− DISPLAY_PLANE_ENABLE);
9977+ intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
100009978 drm_WARN_ON(&dev_priv->drm,
10001− intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
10002− DISPLAY_PLANE_ENABLE);
9979+ intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
100039980 drm_WARN_ON(&dev_priv->drm,
10004− intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
10005− DISPLAY_PLANE_ENABLE);
9981+ intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
100069982 drm_WARN_ON(&dev_priv->drm,
10007− intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
9983+ intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
100089984 drm_WARN_ON(&dev_priv->drm,
10009− intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
9985+ intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
100109986
100119987 intel_de_write(dev_priv, PIPECONF(pipe), 0);
100129988 intel_de_posting_read(dev_priv, PIPECONF(pipe));
@@ -10673,6 +10649,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev, · 660 unmodified lines
1067310649 vlv_wm_sanitize(dev_priv);
1067410650 } else if (DISPLAY_VER(dev_priv) >= 9) {
1067510651 skl_wm_get_hw_state(dev_priv);
10652+ skl_wm_sanitize(dev_priv);
1067610653 } else if (HAS_PCH_SPLIT(dev_priv)) {
1067710654 ilk_wm_get_hw_state(dev_priv);
1067810655 }
@@ -10688,6 +10665,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev, · 9 unmodified lines
1068810665 }
1068910666
1069010667 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
10668+
10669+ intel_power_domains_sanitize_state(dev_priv);
1069110670 }
1069210671
1069310672 void intel_display_resume(struct drm_device *dev)
drivers/gpu/drm/i915/display/intel_display.h+27−9
@@ -27,7 +27,8 @@ · 26 unmodified lines
2727
2828 #include <drm/drm_util.h>
2929
30−enum link_m_n_set;
30+#include "i915_reg_defs.h"
31+
3132 enum drm_scaling_filter;
3233 struct dpll;
3334 struct drm_connector;
@@ -317,8 +318,8 @@ enum aux_ch { · 283 unmodified lines
317318 /* Used by dp and fdi links */
318319 struct intel_link_m_n {
319320 u32 tu;
320− u32 gmch_m;
321− u32 gmch_n;
321+ u32 data_m;
322+ u32 data_n;
322323 u32 link_m;
323324 u32 link_n;
324325 };
@@ -605,12 +606,29 @@ bool intel_fuzzy_clock_check(int clock1, int clock2); · 280 unmodified lines
605606
606607 void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
607608 void intel_display_finish_reset(struct drm_i915_private *dev_priv);
608−void intel_dp_get_m_n(struct intel_crtc *crtc,
609− struct intel_crtc_state *pipe_config);
610−void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
611− enum link_m_n_set m_n);
612−void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
613− struct intel_crtc_state *pipe_config);
609+void intel_zero_m_n(struct intel_link_m_n *m_n);
610+void intel_set_m_n(struct drm_i915_private *i915,
611+ const struct intel_link_m_n *m_n,
612+ i915_reg_t data_m_reg, i915_reg_t data_n_reg,
613+ i915_reg_t link_m_reg, i915_reg_t link_n_reg);
614+void intel_get_m_n(struct drm_i915_private *i915,
615+ struct intel_link_m_n *m_n,
616+ i915_reg_t data_m_reg, i915_reg_t data_n_reg,
617+ i915_reg_t link_m_reg, i915_reg_t link_n_reg);
618+bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
619+ enum transcoder transcoder);
620+void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
621+ enum transcoder cpu_transcoder,
622+ const struct intel_link_m_n *m_n);
623+void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
624+ enum transcoder cpu_transcoder,
625+ const struct intel_link_m_n *m_n);
626+void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
627+ enum transcoder cpu_transcoder,
628+ struct intel_link_m_n *m_n);
629+void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
630+ enum transcoder cpu_transcoder,
631+ struct intel_link_m_n *m_n);
614632 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
615633 struct intel_crtc_state *pipe_config);
616634 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
drivers/gpu/drm/i915/display/intel_display_debugfs.c+5−2
@@ -2402,6 +2402,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector) · 2401 unmodified lines
24022402 */
24032403 void intel_crtc_debugfs_add(struct drm_crtc *crtc)
24042404 {
2405− if (crtc->debugfs_entry)
2406− crtc_updates_add(crtc);
2405+ if (!crtc->debugfs_entry)
2406+ return;
2407+
2408+ crtc_updates_add(crtc);
2409+ intel_fbc_crtc_debugfs_add(to_intel_crtc(crtc));
24072410 }
drivers/gpu/drm/i915/display/intel_display_power.c+37−8
@@ -7,6 +7,7 @@ · 6 unmodified lines
77 #include "i915_irq.h"
88 #include "intel_cdclk.h"
99 #include "intel_combo_phy.h"
10+#include "intel_combo_phy_regs.h"
1011 #include "intel_crt.h"
1112 #include "intel_de.h"
1213 #include "intel_display_power.h"
@@ -682,9 +683,8 @@ static void icl_tc_cold_exit(struct drm_i915_private *i915) · 669 unmodified lines
682683 int ret, tries = 0;
683684
684685 while (1) {
685− ret = sandybridge_pcode_write_timeout(i915,
686− ICL_PCODE_EXIT_TCCOLD,
687− 0, 250, 1);
686+ ret = snb_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,
687+ 250, 1);
688688 if (ret != -EAGAIN || ++tries == 3)
689689 break;
690690 msleep(1);
@@ -4052,8 +4052,7 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block) · 3361 unmodified lines
40524052 * Spec states that we should timeout the request after 200us
40534053 * but the function below will timeout after 500us
40544054 */
4055− ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,
4056− &high_val);
4055+ ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);
40574056 if (ret == 0) {
40584057 if (block &&
40594058 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
@@ -5468,8 +5467,7 @@ static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv) · 1408 unmodified lines
54685467 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
54695468 {
54705469 if (IS_HASWELL(dev_priv)) {
5471− if (sandybridge_pcode_write(dev_priv,
5472− GEN6_PCODE_WRITE_D_COMP, val))
5470+ if (snb_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
54735471 drm_dbg_kms(&dev_priv->drm,
54745472 "Failed to write to D_COMP\n");
54755473 } else {
@@ -5582,7 +5580,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) · 106 unmodified lines
55825580 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
55835581
55845582 intel_update_cdclk(dev_priv);
5585− intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
5583+ intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
55865584 }
55875585
55885586 /*
@@ -6215,6 +6213,37 @@ void intel_power_domains_driver_remove(struct drm_i915_private *i915) · 626 unmodified lines
62156213 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
62166214 }
62176215
6216+/**
6217+ * intel_power_domains_sanitize_state - sanitize power domains state
6218+ * @i915: i915 device instance
6219+ *
6220+ * Sanitize the power domains state during driver loading and system resume.
6221+ * The function will disable all display power wells that BIOS has enabled
6222+ * without a user for it (any user for a power well has taken a reference
6223+ * on it by the time this function is called, after the state of all the
6224+ * pipe, encoder, etc. HW resources have been sanitized).
6225+ */
6226+void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
6227+{
6228+ struct i915_power_domains *power_domains = &i915->power_domains;
6229+ struct i915_power_well *power_well;
6230+
6231+ mutex_lock(&power_domains->lock);
6232+
6233+ for_each_power_well_reverse(i915, power_well) {
6234+ if (power_well->desc->always_on || power_well->count ||
6235+ !power_well->desc->ops->is_enabled(i915, power_well))
6236+ continue;
6237+
6238+ drm_dbg_kms(&i915->drm,
6239+ "BIOS left unused %s power well enabled, disabling it\n",
6240+ power_well->desc->name);
6241+ intel_power_well_disable(i915, power_well);
6242+ }
6243+
6244+ mutex_unlock(&power_domains->lock);
6245+}
6246+
62186247 /**
62196248 * intel_power_domains_enable - enable toggling of display power wells
62206249 * @i915: i915 device instance
drivers/gpu/drm/i915/display/intel_display_power.h+1−1
@@ -7,7 +7,6 @@ · 6 unmodified lines
77 #define __INTEL_DISPLAY_POWER_H__
88
99 #include "intel_runtime_pm.h"
10−#include "i915_reg.h"
1110
1211 enum dpio_channel;
1312 enum dpio_phy;
@@ -219,6 +218,7 @@ void intel_power_domains_disable(struct drm_i915_private *dev_priv); · 205 unmodified lines
219218 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
220219 enum i915_drm_suspend_mode);
221220 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
221+void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv);
222222
223223 void intel_display_power_suspend_late(struct drm_i915_private *i915);
224224 void intel_display_power_resume_early(struct drm_i915_private *i915);
drivers/gpu/drm/i915/display/intel_display_trace.h+1−0
@@ -13,6 +13,7 @@ · 12 unmodified lines
1313 #include <linux/tracepoint.h>
1414
1515 #include "i915_drv.h"
16+#include "i915_irq.h"
1617 #include "intel_crtc.h"
1718 #include "intel_display_types.h"
1819
drivers/gpu/drm/i915/display/intel_display_types.h+3−19
@@ -634,6 +634,9 @@ struct intel_plane_state { · 633 unmodified lines
634634
635635 struct intel_fb_view view;
636636
637+ /* Indicates if async flip is required */
638+ bool do_async_flip;
639+
637640 /* Plane pxp decryption state */
638641 bool decrypt;
639642
@@ -1442,25 +1445,6 @@ struct intel_hdmi { · 802 unmodified lines
14421445 };
14431446
14441447 struct intel_dp_mst_encoder;
1445−/*
1446− * enum link_m_n_set:
1447− * When platform provides two set of M_N registers for dp, we can
1448− * program them and switch between them incase of DRRS.
1449− * But When only one such register is provided, we have to program the
1450− * required divider value on that registers itself based on the DRRS state.
1451− *
1452− * M1_N1 : Program dp_m_n on M1_N1 registers
1453− * dp_m2_n2 on M2_N2 registers (If supported)
1454− *
1455− * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1456− * M2_N2 registers are not supported
1457− */
1458−
1459−enum link_m_n_set {
1460− /* Sets the m1_n1 and m2_n2 */
1461− M1_N1 = 0,
1462− M2_N2
1463−};
14641448
14651449 struct intel_dp_compliance_data {
14661450 unsigned long edid;
drivers/gpu/drm/i915/display/intel_dmc.c+7−7
@@ -43,9 +43,9 @@ · 42 unmodified lines
4343 __stringify(major) "_" \
4444 __stringify(minor) ".bin"
4545
46−#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
46+#define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000
4747
48−#define GEN13_DMC_MAX_FW_SIZE 0x20000
48+#define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
4949
5050 #define ADLP_DMC_PATH DMC_PATH(adlp, 2, 14)
5151 #define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 14)
@@ -684,23 +684,23 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv) · 632 unmodified lines
684684 if (IS_ALDERLAKE_P(dev_priv)) {
685685 dmc->fw_path = ADLP_DMC_PATH;
686686 dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
687− dmc->max_fw_size = GEN13_DMC_MAX_FW_SIZE;
687+ dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
688688 } else if (IS_ALDERLAKE_S(dev_priv)) {
689689 dmc->fw_path = ADLS_DMC_PATH;
690690 dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
691− dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
691+ dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
692692 } else if (IS_DG1(dev_priv)) {
693693 dmc->fw_path = DG1_DMC_PATH;
694694 dmc->required_version = DG1_DMC_VERSION_REQUIRED;
695− dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
695+ dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
696696 } else if (IS_ROCKETLAKE(dev_priv)) {
697697 dmc->fw_path = RKL_DMC_PATH;
698698 dmc->required_version = RKL_DMC_VERSION_REQUIRED;
699− dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
699+ dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
700700 } else if (DISPLAY_VER(dev_priv) >= 12) {
701701 dmc->fw_path = TGL_DMC_PATH;
702702 dmc->required_version = TGL_DMC_VERSION_REQUIRED;
703− dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
703+ dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
704704 } else if (DISPLAY_VER(dev_priv) == 11) {
705705 dmc->fw_path = ICL_DMC_PATH;
706706 dmc->required_version = ICL_DMC_VERSION_REQUIRED;
drivers/gpu/drm/i915/display/intel_dmc.h+1−1
@@ -6,7 +6,7 @@ · 5 unmodified lines
66 #ifndef __INTEL_DMC_H__
77 #define __INTEL_DMC_H__
88
9−#include "i915_reg.h"
9+#include "i915_reg_defs.h"
1010 #include "intel_wakeref.h"
1111 #include <linux/workqueue.h>
1212
drivers/gpu/drm/i915/display/intel_dp.c+98−67
@@ -46,6 +46,7 @@ · 45 unmodified lines
4646 #include "intel_atomic.h"
4747 #include "intel_audio.h"
4848 #include "intel_backlight.h"
49+#include "intel_combo_phy_regs.h"
4950 #include "intel_connector.h"
5051 #include "intel_crtc.h"
5152 #include "intel_ddi.h"
@@ -72,8 +73,6 @@ · 20 unmodified lines
7273 #include "intel_vdsc.h"
7374 #include "intel_vrr.h"
7475
75−#define DP_DPRX_ESI_LEN 14
76−
7776 /* DP DSC throughput values used for slice count calculations KPixels/s */
7877 #define DP_DSC_PEAK_PIXEL_RATE 2720000
7978 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
@@ -705,7 +704,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, · 625 unmodified lines
705704 i915->max_cdclk_freq * 48 /
706705 intel_dp_mode_to_fec_clock(mode_clock);
707706
708− DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
707+ drm_dbg_kms(&i915->drm, "Max big joiner bpp: %u\n", max_bpp_bigjoiner);
709708 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
710709 }
711710
@@ -1167,14 +1166,13 @@ static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp, · 455 unmodified lines
11671166 return true;
11681167 }
11691168
1170−static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
1171− const struct intel_crtc_state *crtc_state,
1172− int bpc)
1169+static bool intel_dp_hdmi_bpc_possible(struct intel_dp *intel_dp,
1170+ const struct intel_crtc_state *crtc_state,
1171+ int bpc)
11731172 {
11741173
1175− return intel_hdmi_deep_color_possible(crtc_state, bpc,
1176− intel_dp->has_hdmi_sink,
1177− intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
1174+ return intel_hdmi_bpc_possible(crtc_state, bpc, intel_dp->has_hdmi_sink,
1175+ intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
11781176 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
11791177 }
11801178
@@ -1192,7 +1190,7 @@ static int intel_dp_max_bpp(struct intel_dp *intel_dp, · 11 unmodified lines
11921190
11931191 if (intel_dp->dfp.min_tmds_clock) {
11941192 for (; bpc >= 10; bpc -= 2) {
1195− if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
1193+ if (intel_dp_hdmi_bpc_possible(intel_dp, crtc_state, bpc))
11961194 break;
11971195 }
11981196 }
@@ -1897,7 +1895,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, · 698 unmodified lines
18971895
18981896 /* FIXME: abstract this better */
18991897 if (pipe_config->splitter.enable)
1900− pipe_config->dp_m_n.gmch_m *= pipe_config->splitter.link_count;
1898+ pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
19011899
19021900 if (!HAS_DDI(dev_priv))
19031901 g4x_dp_set_clock(encoder, pipe_config);
@@ -2813,11 +2811,22 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) · 909 unmodified lines
28132811 }
28142812
28152813 static bool
2816−intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2814+intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
28172815 {
2818− return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
2819− sink_irq_vector, DP_DPRX_ESI_LEN) ==
2820− DP_DPRX_ESI_LEN;
2816+ return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
2817+}
2818+
2819+static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
2820+{
2821+ int retry;
2822+
2823+ for (retry = 0; retry < 3; retry++) {
2824+ if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
2825+ &esi[1], 3) == 3)
2826+ return true;
2827+ }
2828+
2829+ return false;
28212830 }
28222831
28232832 bool
@@ -2909,7 +2918,8 @@ out: · 85 unmodified lines
29092918 }
29102919
29112920 static ssize_t
2912−intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
2921+intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
2922+ const struct hdmi_drm_infoframe *drm_infoframe,
29132923 struct dp_sdp *sdp,
29142924 size_t size)
29152925 {
@@ -2925,12 +2935,12 @@ intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_in · 9 unmodified lines
29252935
29262936 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
29272937 if (len < 0) {
2928− DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
2938+ drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
29292939 return -ENOSPC;
29302940 }
29312941
29322942 if (len != infoframe_size) {
2933− DRM_DEBUG_KMS("wrong static hdr metadata size\n");
2943+ drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
29342944 return -ENOSPC;
29352945 }
29362946
@@ -3003,7 +3013,8 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder, · 66 unmodified lines
30033013 sizeof(sdp));
30043014 break;
30053015 case HDMI_PACKET_TYPE_GAMUT_METADATA:
3006− len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
3016+ len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
3017+ &crtc_state->infoframes.drm.drm,
30073018 &sdp, sizeof(sdp));
30083019 break;
30093020 default:
@@ -3411,22 +3422,22 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, · 401 unmodified lines
34113422
34123423 switch (data->phy_pattern) {
34133424 case DP_PHY_TEST_PATTERN_NONE:
3414− DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
3425+ drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
34153426 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
34163427 break;
34173428 case DP_PHY_TEST_PATTERN_D10_2:
3418− DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
3429+ drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
34193430 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
34203431 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
34213432 break;
34223433 case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3423− DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
3434+ drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
34243435 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
34253436 DDI_DP_COMP_CTL_ENABLE |
34263437 DDI_DP_COMP_CTL_SCRAMBLED_0);
34273438 break;
34283439 case DP_PHY_TEST_PATTERN_PRBS7:
3429− DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
3440+ drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
34303441 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
34313442 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
34323443 break;
@@ -3436,7 +3447,8 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, · 3 unmodified lines
34363447 * current firmware of DPR-100 could not set it, so hardcoding
34373448 * now for complaince test.
34383449 */
3439− DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3450+ drm_dbg_kms(&dev_priv->drm,
3451+ "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
34403452 pattern_val = 0x3e0f83e0;
34413453 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
34423454 pattern_val = 0x0f83e0f8;
@@ -3453,7 +3465,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, · 10 unmodified lines
34533465 * current firmware of DPR-100 could not set it, so hardcoding
34543466 * now for complaince test.
34553467 */
3456− DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
3468+ drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
34573469 pattern_val = 0xFB;
34583470 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
34593471 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
@@ -3522,13 +3534,14 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, · 62 unmodified lines
35223534 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
35233535 const struct intel_crtc_state *crtc_state)
35243536 {
3537+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
35253538 struct drm_dp_phy_test_params *data =
35263539 &intel_dp->compliance.test_data.phytest;
35273540 u8 link_status[DP_LINK_STATUS_SIZE];
35283541
35293542 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
35303543 link_status) < 0) {
3531− DRM_DEBUG_KMS("failed to get link status\n");
3544+ drm_dbg_kms(&i915->drm, "failed to get link status\n");
35323545 return;
35333546 }
35343547
@@ -3553,11 +3566,12 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp, · 18 unmodified lines
35533566
35543567 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
35553568 {
3569+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
35563570 struct drm_dp_phy_test_params *data =
35573571 &intel_dp->compliance.test_data.phytest;
35583572
35593573 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3560− DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
3574+ drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
35613575 return DP_TEST_NAK;
35623576 }
35633577
@@ -3615,14 +3629,43 @@ update_status: · 51 unmodified lines
36153629 }
36163630
36173631 static void
3618−intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
3632+intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
36193633 {
3620− drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
3634+ bool handled = false;
36213635
3622− if (esi[1] & DP_CP_IRQ) {
3623− intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3624− *handled = true;
3625− }
3636+ drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3637+ if (handled)
3638+ ack[1] |= esi[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
3639+
3640+ if (esi[1] & DP_CP_IRQ) {
3641+ intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3642+ ack[1] |= DP_CP_IRQ;
3643+ }
3644+}
3645+
3646+static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
3647+{
3648+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3649+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3650+ u8 link_status[DP_LINK_STATUS_SIZE] = {};
3651+ const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
3652+
3653+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
3654+ esi_link_status_size) != esi_link_status_size) {
3655+ drm_err(&i915->drm,
3656+ "[ENCODER:%d:%s] Failed to read link status\n",
3657+ encoder->base.base.id, encoder->base.name);
3658+ return false;
3659+ }
3660+
3661+ if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3662+ drm_dbg_kms(&i915->drm,
3663+ "[ENCODER:%d:%s] channel EQ not ok, retraining\n",
3664+ encoder->base.base.id, encoder->base.name);
3665+ return false;
3666+ }
3667+
3668+ return true;
36263669 }
36273670
36283671 /**
@@ -3647,20 +3690,8 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) · 18 unmodified lines
36473690 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
36483691
36493692 for (;;) {
3650− /*
3651− * The +2 is because DP_DPRX_ESI_LEN is 14, but we then
3652− * pass in "esi+10" to drm_dp_channel_eq_ok(), which
3653− * takes a 6-byte array. So we actually need 16 bytes
3654− * here.
3655− *
3656− * Somebody who knows what the limits actually are
3657− * should check this, but for now this is at least
3658− * harmless and avoids a valid compiler warning about
3659− * using more of the array than we have allocated.
3660− */
3661− u8 esi[DP_DPRX_ESI_LEN+2] = {};
3662− bool handled;
3663− int retry;
3693+ u8 esi[4] = {};
3694+ u8 ack[4] = {};
36643695
36653696 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
36663697 drm_dbg_kms(&i915->drm,
@@ -3670,30 +3701,22 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) · 3 unmodified lines
36703701 break;
36713702 }
36723703
3673− /* check link status - esi[10] = 0x200c */
3704+ drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
3705+
36743706 if (intel_dp->active_mst_links > 0 && link_ok &&
3675− !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3676− drm_dbg_kms(&i915->drm,
3677− "channel EQ not ok, retraining\n");
3678− link_ok = false;
3707+ esi[3] & LINK_STATUS_CHANGED) {
3708+ if (!intel_dp_mst_link_status(intel_dp))
3709+ link_ok = false;
3710+ ack[3] |= LINK_STATUS_CHANGED;
36793711 }
36803712
3681− drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
3713+ intel_dp_mst_hpd_irq(intel_dp, esi, ack);
36823714
3683− intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
3684−
3685− if (!handled)
3715+ if (!memchr_inv(ack, 0, sizeof(ack)))
36863716 break;
36873717
3688− for (retry = 0; retry < 3; retry++) {
3689− int wret;
3690−
3691− wret = drm_dp_dpcd_write(&intel_dp->aux,
3692− DP_SINK_COUNT_ESI+1,
3693− &esi[1], 3);
3694− if (wret == 3)
3695− break;
3696− }
3718+ if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
3719+ drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
36973720 }
36983721
36993722 return link_ok;
@@ -4974,6 +4997,14 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, · 1274 unmodified lines
49744997
49754998 mutex_lock(&dev->mode_config.mutex);
49764999 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5000+ if (!edid) {
5001+ /* Fallback to EDID from ACPI OpRegion, if any */
5002+ edid = intel_opregion_get_edid(intel_connector);
5003+ if (edid)
5004+ drm_dbg_kms(&dev_priv->drm,
5005+ "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
5006+ connector->base.id, connector->name);
5007+ }
49775008 if (edid) {
49785009 if (drm_add_edid_modes(connector, edid)) {
49795010 drm_connector_update_edid_property(connector, edid);
@@ -5048,8 +5079,8 @@ static void intel_dp_modeset_retry_work_fn(struct work_struct *work) · 68 unmodified lines
50485079 intel_connector = container_of(work, typeof(*intel_connector),
50495080 modeset_retry_work);
50505081 connector = &intel_connector->base;
5051− DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5052− connector->name);
5082+ drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
5083+ connector->name);
50535084
50545085 /* Grab the locks before changing connector property*/
50555086 mutex_lock(&connector->dev->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_dp.h+0−2
@@ -8,8 +8,6 @@ · 7 unmodified lines
88
99 #include <linux/types.h>
1010
11−#include "i915_reg.h"
12−
1311 enum intel_output_format;
1412 enum pipe;
1513 enum port;
drivers/gpu/drm/i915/display/intel_dp_aux.c+4−4
@@ -10,7 +10,7 @@ · 9 unmodified lines
1010 #include "intel_pps.h"
1111 #include "intel_tc.h"
1212
13−u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
13+static u32 intel_dp_aux_pack(const u8 *src, int src_bytes)
1414 {
1515 int i;
1616 u32 v = 0;
@@ -22,7 +22,7 @@ u32 intel_dp_pack_aux(const u8 *src, int src_bytes) · 5 unmodified lines
2222 return v;
2323 }
2424
25−static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
25+static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes)
2626 {
2727 int i;
2828
@@ -267,7 +267,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, · 238 unmodified lines
267267 for (i = 0; i < send_bytes; i += 4)
268268 intel_uncore_write(uncore,
269269 ch_data[i >> 2],
270− intel_dp_pack_aux(send + i,
270+ intel_dp_aux_pack(send + i,
271271 send_bytes - i));
272272
273273 /* Send the command and wait for it to complete */
@@ -352,7 +352,7 @@ done: · 78 unmodified lines
352352 recv_bytes = recv_size;
353353
354354 for (i = 0; i < recv_bytes; i += 4)
355− intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
355+ intel_dp_aux_unpack(intel_uncore_read(uncore, ch_data[i >> 2]),
356356 recv + i, recv_bytes - i);
357357
358358 ret = recv_bytes;
drivers/gpu/drm/i915/display/intel_dp_aux.h+0−4
@@ -6,12 +6,8 @@ · 5 unmodified lines
66 #ifndef __INTEL_DP_AUX_H__
77 #define __INTEL_DP_AUX_H__
88
9−#include <linux/types.h>
10−
119 struct intel_dp;
1210
13−u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
14−
1511 void intel_dp_aux_fini(struct intel_dp *intel_dp);
1612 void intel_dp_aux_init(struct intel_dp *intel_dp);
1713
drivers/gpu/drm/i915/display/intel_dp_mst.c+0−2
@@ -522,8 +522,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, · 521 unmodified lines
522522 intel_ddi_enable_pipe_clock(encoder, pipe_config);
523523
524524 intel_ddi_set_dp_msa(pipe_config, conn_state);
525−
526− intel_dp_set_m_n(pipe_config, M1_N1);
527525 }
528526
529527 static void intel_mst_enable_dp(struct intel_atomic_state *state,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c+36−0
@@ -28,6 +28,7 @@ · 27 unmodified lines
2828 #include "intel_dpll_mgr.h"
2929 #include "intel_pch_refclk.h"
3030 #include "intel_tc.h"
31+#include "intel_tc_phy_regs.h"
3132
3233 /**
3334 * DOC: Display PLLs
@@ -49,6 +50,41 @@ · 15 unmodified lines
4950 * commit phase.
5051 */
5152
53+/* platform specific hooks for managing DPLLs */
54+struct intel_shared_dpll_funcs {
55+ /*
56+ * Hook for enabling the pll, called from intel_enable_shared_dpll() if
57+ * the pll is not already enabled.
58+ */
59+ void (*enable)(struct drm_i915_private *i915,
60+ struct intel_shared_dpll *pll);
61+
62+ /*
63+ * Hook for disabling the pll, called from intel_disable_shared_dpll()
64+ * only when it is safe to disable the pll, i.e., there are no more
65+ * tracked users for it.
66+ */
67+ void (*disable)(struct drm_i915_private *i915,
68+ struct intel_shared_dpll *pll);
69+
70+ /*
71+ * Hook for reading the values currently programmed to the DPLL
72+ * registers. This is used for initial hw state readout and state
73+ * verification after a mode set.
74+ */
75+ bool (*get_hw_state)(struct drm_i915_private *i915,
76+ struct intel_shared_dpll *pll,
77+ struct intel_dpll_hw_state *hw_state);
78+
79+ /*
80+ * Hook for calculating the pll's output frequency based on its passed
81+ * in state.
82+ */
83+ int (*get_freq)(struct drm_i915_private *i915,
84+ const struct intel_shared_dpll *pll,
85+ const struct intel_dpll_hw_state *pll_state);
86+};
87+
5288 struct intel_dpll_mgr {
5389 const struct dpll_info *dpll_info;
5490
drivers/gpu/drm/i915/display/intel_dpll_mgr.h+1−45
@@ -44,6 +44,7 @@ struct intel_crtc; · 43 unmodified lines
4444 struct intel_crtc_state;
4545 struct intel_encoder;
4646 struct intel_shared_dpll;
47+struct intel_shared_dpll_funcs;
4748
4849 /**
4950 * enum intel_dpll_id - possible DPLL ids
@@ -251,51 +252,6 @@ struct intel_shared_dpll_state { · 201 unmodified lines
251252 struct intel_dpll_hw_state hw_state;
252253 };
253254
254−/**
255− * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs
256− */
257−struct intel_shared_dpll_funcs {
258− /**
259− * @enable:
260− *
261− * Hook for enabling the pll, called from intel_enable_shared_dpll()
262− * if the pll is not already enabled.
263− */
264− void (*enable)(struct drm_i915_private *dev_priv,
265− struct intel_shared_dpll *pll);
266−
267− /**
268− * @disable:
269− *
270− * Hook for disabling the pll, called from intel_disable_shared_dpll()
271− * only when it is safe to disable the pll, i.e., there are no more
272− * tracked users for it.
273− */
274− void (*disable)(struct drm_i915_private *dev_priv,
275− struct intel_shared_dpll *pll);
276−
277− /**
278− * @get_hw_state:
279− *
280− * Hook for reading the values currently programmed to the DPLL
281− * registers. This is used for initial hw state readout and state
282− * verification after a mode set.
283− */
284− bool (*get_hw_state)(struct drm_i915_private *dev_priv,
285− struct intel_shared_dpll *pll,
286− struct intel_dpll_hw_state *hw_state);
287−
288− /**
289− * @get_freq:
290− *
291− * Hook for calculating the pll's output frequency based on its
292− * passed in state.
293− */
294− int (*get_freq)(struct drm_i915_private *i915,
295− const struct intel_shared_dpll *pll,
296− const struct intel_dpll_hw_state *pll_state);
297−};
298−
299255 /**
300256 * struct dpll_info - display PLL platform specific info
301257 */
drivers/gpu/drm/i915/display/intel_drrs.c+71−44
@@ -47,17 +47,13 @@ · 46 unmodified lines
4747 * requested by userspace.
4848 */
4949
50−void
51−intel_drrs_compute_config(struct intel_dp *intel_dp,
52− struct intel_crtc_state *pipe_config,
53− int output_bpp, bool constant_n)
50+static bool can_enable_drrs(struct intel_connector *connector,
51+ const struct intel_crtc_state *pipe_config)
5452 {
55− struct intel_connector *intel_connector = intel_dp->attached_connector;
56− struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
57− int pixel_clock;
53+ const struct drm_i915_private *i915 = to_i915(connector->base.dev);
5854
5955 if (pipe_config->vrr.enable)
60− return;
56+ return false;
6157
6258 /*
6359 * DRRS and PSR can't be enable together, so giving preference to PSR
@@ -66,15 +62,30 @@ intel_drrs_compute_config(struct intel_dp *intel_dp, · 2 unmodified lines
6662 * after intel_psr_compute_config().
6763 */
6864 if (pipe_config->has_psr)
69− return;
65+ return false;
7066
71− if (!intel_connector->panel.downclock_mode ||
72− dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
67+ return connector->panel.downclock_mode &&
68+ i915->drrs.type == SEAMLESS_DRRS_SUPPORT;
69+}
70+
71+void
72+intel_drrs_compute_config(struct intel_dp *intel_dp,
73+ struct intel_crtc_state *pipe_config,
74+ int output_bpp, bool constant_n)
75+{
76+ struct intel_connector *connector = intel_dp->attached_connector;
77+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
78+ int pixel_clock;
79+
80+ if (!can_enable_drrs(connector, pipe_config)) {
81+ if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
82+ intel_zero_m_n(&pipe_config->dp_m2_n2);
7383 return;
84+ }
7485
7586 pipe_config->has_drrs = true;
7687
77− pixel_clock = intel_connector->panel.downclock_mode->clock;
88+ pixel_clock = connector->panel.downclock_mode->clock;
7889 if (pipe_config->splitter.enable)
7990 pixel_clock /= pipe_config->splitter.link_count;
8091
@@ -84,7 +95,42 @@ intel_drrs_compute_config(struct intel_dp *intel_dp, · 3 unmodified lines
8495
8596 /* FIXME: abstract this better */
8697 if (pipe_config->splitter.enable)
87− pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
98+ pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
99+}
100+
101+static void
102+intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state,
103+ enum drrs_refresh_rate_type refresh_type)
104+{
105+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
106+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
107+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
108+ u32 val, bit;
109+
110+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
111+ bit = PIPECONF_EDP_RR_MODE_SWITCH_VLV;
112+ else
113+ bit = PIPECONF_EDP_RR_MODE_SWITCH;
114+
115+ val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
116+
117+ if (refresh_type == DRRS_LOW_RR)
118+ val |= bit;
119+ else
120+ val &= ~bit;
121+
122+ intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
123+}
124+
125+static void
126+intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state,
127+ enum drrs_refresh_rate_type refresh_type)
128+{
129+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
130+
131+ intel_cpu_transcoder_set_m1_n1(crtc, crtc_state->cpu_transcoder,
132+ refresh_type == DRRS_LOW_RR ?
133+ &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n);
88134 }
89135
90136 static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
@@ -120,37 +166,10 @@ static void intel_drrs_set_state(struct drm_i915_private *dev_priv, · 29 unmodified lines
120166 return;
121167 }
122168
123− if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
124− switch (refresh_type) {
125− case DRRS_HIGH_RR:
126− intel_dp_set_m_n(crtc_state, M1_N1);
127− break;
128− case DRRS_LOW_RR:
129− intel_dp_set_m_n(crtc_state, M2_N2);
130− break;
131− case DRRS_MAX_RR:
132− default:
133− drm_err(&dev_priv->drm,
134− "Unsupported refreshrate type\n");
135− }
136− } else if (DISPLAY_VER(dev_priv) > 6) {
137− i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
138− u32 val;
139−
140− val = intel_de_read(dev_priv, reg);
141− if (refresh_type == DRRS_LOW_RR) {
142− if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
143− val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
144− else
145− val |= PIPECONF_EDP_RR_MODE_SWITCH;
146− } else {
147− if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
148− val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
149− else
150− val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
151− }
152− intel_de_write(dev_priv, reg, val);
153− }
169+ if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv))
170+ intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_type);
171+ else if (DISPLAY_VER(dev_priv) > 6)
172+ intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_type);
154173
155174 dev_priv->drrs.refresh_rate_type = refresh_type;
156175
@@ -405,6 +424,7 @@ intel_drrs_init(struct intel_connector *connector, · 248 unmodified lines
405424 struct drm_display_mode *fixed_mode)
406425 {
407426 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
427+ struct intel_encoder *encoder = connector->encoder;
408428 struct drm_display_mode *downclock_mode = NULL;
409429
410430 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_drrs_downclock_work);
@@ -416,6 +436,13 @@ intel_drrs_init(struct intel_connector *connector, · 5 unmodified lines
416436 return NULL;
417437 }
418438
439+ if ((DISPLAY_VER(dev_priv) < 8 && !HAS_GMCH(dev_priv)) &&
440+ encoder->port != PORT_A) {
441+ drm_dbg_kms(&dev_priv->drm,
442+ "DRRS only supported on eDP port A\n");
443+ return NULL;
444+ }
445+
419446 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
420447 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
421448 return NULL;
drivers/gpu/drm/i915/display/intel_dsb.h+1−1
@@ -8,7 +8,7 @@ · 7 unmodified lines
88
99 #include <linux/types.h>
1010
11−#include "i915_reg.h"
11+#include "i915_reg_defs.h"
1212
1313 struct intel_crtc_state;
1414 struct i915_vma;
drivers/gpu/drm/i915/display/intel_dsi_vbt.c+11−18
@@ -39,6 +39,7 @@ · 38 unmodified lines
3939 #include <video/mipi_display.h>
4040
4141 #include "i915_drv.h"
42+#include "i915_reg.h"
4243 #include "intel_display_types.h"
4344 #include "intel_dsi.h"
4445 #include "intel_dsi_vbt.h"
@@ -426,24 +427,16 @@ static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, · 381 unmodified lines
426427 const u16 slave_addr)
427428 {
428429 struct drm_device *drm_dev = intel_dsi->base.base.dev;
429− struct device *dev = drm_dev->dev;
430− struct acpi_device *acpi_dev;
431− struct list_head resource_list;
432− struct i2c_adapter_lookup lookup;
433−
434− acpi_dev = ACPI_COMPANION(dev);
435− if (acpi_dev) {
436− memset(&lookup, 0, sizeof(lookup));
437− lookup.slave_addr = slave_addr;
438− lookup.intel_dsi = intel_dsi;
439− lookup.dev_handle = acpi_device_handle(acpi_dev);
440−
441− INIT_LIST_HEAD(&resource_list);
442− acpi_dev_get_resources(acpi_dev, &resource_list,
443− i2c_adapter_lookup,
444− &lookup);
445− acpi_dev_free_resource_list(&resource_list);
446− }
430+ struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev);
431+ struct i2c_adapter_lookup lookup = {
432+ .slave_addr = slave_addr,
433+ .intel_dsi = intel_dsi,
434+ .dev_handle = acpi_device_handle(adev),
435+ };
436+ LIST_HEAD(resource_list);
437+
438+ acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup);
439+ acpi_dev_free_resource_list(&resource_list);
447440 }
448441 #else
449442 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
drivers/gpu/drm/i915/display/intel_dvo_dev.h+1−1
@@ -27,7 +27,7 @@ · 26 unmodified lines
2727
2828 #include <drm/drm_crtc.h>
2929
30−#include "i915_reg.h"
30+#include "i915_reg_defs.h"
3131
3232 struct intel_dvo_device {
3333 const char *name;
drivers/gpu/drm/i915/display/intel_fbc.c+143−95
@@ -49,6 +49,14 @@ · 48 unmodified lines
4949 #include "intel_fbc.h"
5050 #include "intel_frontbuffer.h"
5151
52+#define for_each_fbc_id(__dev_priv, __fbc_id) \
53+ for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
54+ for_each_if(INTEL_INFO(__dev_priv)->display.fbc_mask & BIT(__fbc_id))
55+
56+#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
57+ for_each_fbc_id((__dev_priv), (__fbc_id)) \
58+ for_each_if((__fbc) = (__dev_priv)->fbc[(__fbc_id)])
59+
5260 struct intel_fbc_funcs {
5361 void (*activate)(struct intel_fbc *fbc);
5462 void (*deactivate)(struct intel_fbc *fbc);
@@ -85,6 +93,8 @@ struct intel_fbc { · 30 unmodified lines
8593 struct drm_mm_node compressed_fb;
8694 struct drm_mm_node compressed_llb;
8795
96+ enum intel_fbc_id id;
97+
8898 u8 limit;
8999
90100 bool false_color;
@@ -454,10 +464,10 @@ static void ilk_fbc_activate(struct intel_fbc *fbc) · 363 unmodified lines
454464 struct intel_fbc_state *fbc_state = &fbc->state;
455465 struct drm_i915_private *i915 = fbc->i915;
456466
457− intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
467+ intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
458468 fbc_state->fence_y_offset);
459469
460− intel_de_write(i915, ILK_DPFC_CONTROL,
470+ intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
461471 DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
462472 }
463473
@@ -467,28 +477,28 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc) · 3 unmodified lines
467477 u32 dpfc_ctl;
468478
469479 /* Disable compression */
470− dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL);
480+ dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
471481 if (dpfc_ctl & DPFC_CTL_EN) {
472482 dpfc_ctl &= ~DPFC_CTL_EN;
473− intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl);
483+ intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
474484 }
475485 }
476486
477487 static bool ilk_fbc_is_active(struct intel_fbc *fbc)
478488 {
479− return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
489+ return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
480490 }
481491
482492 static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
483493 {
484− return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
494+ return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
485495 }
486496
487497 static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
488498 {
489499 struct drm_i915_private *i915 = fbc->i915;
490500
491− intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
501+ intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fbc->compressed_fb.start);
492502 }
493503
494504 static const struct intel_fbc_funcs ilk_fbc_funcs = {
@@ -524,8 +534,8 @@ static void snb_fbc_nuke(struct intel_fbc *fbc) · 29 unmodified lines
524534 {
525535 struct drm_i915_private *i915 = fbc->i915;
526536
527− intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE);
528− intel_de_posting_read(i915, MSG_FBC_REND_STATE);
537+ intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
538+ intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
529539 }
530540
531541 static const struct intel_fbc_funcs snb_fbc_funcs = {
@@ -547,7 +557,7 @@ static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc) · 15 unmodified lines
547557 val |= FBC_STRIDE_OVERRIDE |
548558 FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
549559
550− intel_de_write(i915, GLK_FBC_STRIDE, val);
560+ intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
551561 }
552562
553563 static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
@@ -598,19 +608,19 @@ static void ivb_fbc_activate(struct intel_fbc *fbc) · 44 unmodified lines
598608 if (i915->ggtt.num_fences)
599609 snb_fbc_program_fence(fbc);
600610
601− intel_de_write(i915, ILK_DPFC_CONTROL,
611+ intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
602612 DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
603613 }
604614
605615 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
606616 {
607− return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) & DPFC_COMP_SEG_MASK_IVB;
617+ return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
608618 }
609619
610620 static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
611621 bool enable)
612622 {
613− intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL,
623+ intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
614624 DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
615625 }
616626
@@ -810,16 +820,16 @@ static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc) · 193 unmodified lines
810820
811821 void intel_fbc_cleanup(struct drm_i915_private *i915)
812822 {
813− struct intel_fbc *fbc = i915->fbc;
814−
815− if (!fbc)
816− return;
823+ struct intel_fbc *fbc;
824+ enum intel_fbc_id fbc_id;
817825
818− mutex_lock(&fbc->lock);
819− __intel_fbc_cleanup_cfb(fbc);
820− mutex_unlock(&fbc->lock);
826+ for_each_intel_fbc(i915, fbc, fbc_id) {
827+ mutex_lock(&fbc->lock);
828+ __intel_fbc_cleanup_cfb(fbc);
829+ mutex_unlock(&fbc->lock);
821830
822− kfree(fbc);
831+ kfree(fbc);
832+ }
823833 }
824834
825835 static bool stride_is_valid(const struct intel_plane_state *plane_state)
@@ -1305,15 +1315,10 @@ static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc) · 479 unmodified lines
13051315 return fbc->possible_framebuffer_bits;
13061316 }
13071317
1308−void intel_fbc_invalidate(struct drm_i915_private *i915,
1309− unsigned int frontbuffer_bits,
1310− enum fb_op_origin origin)
1318+static void __intel_fbc_invalidate(struct intel_fbc *fbc,
1319+ unsigned int frontbuffer_bits,
1320+ enum fb_op_origin origin)
13111321 {
1312− struct intel_fbc *fbc = i915->fbc;
1313−
1314− if (!fbc)
1315− return;
1316−
13171322 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
13181323 return;
13191324
@@ -1327,14 +1332,22 @@ void intel_fbc_invalidate(struct drm_i915_private *i915, · 7 unmodified lines
13271332 mutex_unlock(&fbc->lock);
13281333 }
13291334
1330−void intel_fbc_flush(struct drm_i915_private *i915,
1331− unsigned int frontbuffer_bits, enum fb_op_origin origin)
1335+void intel_fbc_invalidate(struct drm_i915_private *i915,
1336+ unsigned int frontbuffer_bits,
1337+ enum fb_op_origin origin)
13321338 {
1333− struct intel_fbc *fbc = i915->fbc;
1339+ struct intel_fbc *fbc;
1340+ enum intel_fbc_id fbc_id;
13341341
1335− if (!fbc)
1336− return;
1342+ for_each_intel_fbc(i915, fbc, fbc_id)
1343+ __intel_fbc_invalidate(fbc, frontbuffer_bits, origin);
1344+
1345+}
13371346
1347+static void __intel_fbc_flush(struct intel_fbc *fbc,
1348+ unsigned int frontbuffer_bits,
1349+ enum fb_op_origin origin)
1350+{
13381351 mutex_lock(&fbc->lock);
13391352
13401353 fbc->busy_bits &= ~frontbuffer_bits;
@@ -1354,6 +1367,17 @@ out: · 13 unmodified lines
13541367 mutex_unlock(&fbc->lock);
13551368 }
13561369
1370+void intel_fbc_flush(struct drm_i915_private *i915,
1371+ unsigned int frontbuffer_bits,
1372+ enum fb_op_origin origin)
1373+{
1374+ struct intel_fbc *fbc;
1375+ enum intel_fbc_id fbc_id;
1376+
1377+ for_each_intel_fbc(i915, fbc, fbc_id)
1378+ __intel_fbc_flush(fbc, frontbuffer_bits, origin);
1379+}
1380+
13571381 int intel_fbc_atomic_check(struct intel_atomic_state *state)
13581382 {
13591383 struct intel_plane_state *plane_state;
@@ -1483,15 +1507,15 @@ void intel_fbc_update(struct intel_atomic_state *state, · 123 unmodified lines
14831507 */
14841508 void intel_fbc_global_disable(struct drm_i915_private *i915)
14851509 {
1486− struct intel_fbc *fbc = i915->fbc;
1487−
1488− if (!fbc)
1489− return;
1510+ struct intel_fbc *fbc;
1511+ enum intel_fbc_id fbc_id;
14901512
1491− mutex_lock(&fbc->lock);
1492− if (fbc->state.plane)
1493− __intel_fbc_disable(fbc);
1494− mutex_unlock(&fbc->lock);
1513+ for_each_intel_fbc(i915, fbc, fbc_id) {
1514+ mutex_lock(&fbc->lock);
1515+ if (fbc->state.plane)
1516+ __intel_fbc_disable(fbc);
1517+ mutex_unlock(&fbc->lock);
1518+ }
14951519 }
14961520
14971521 static void intel_fbc_underrun_work_fn(struct work_struct *work)
@@ -1516,19 +1540,9 @@ out: · 18 unmodified lines
15161540 mutex_unlock(&fbc->lock);
15171541 }
15181542
1519−/*
1520− * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1521− * @i915: the i915 device
1522− *
1523− * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1524− * want to re-enable FBC after an underrun to increase test coverage.
1525− */
1526−void intel_fbc_reset_underrun(struct drm_i915_private *i915)
1543+static void __intel_fbc_reset_underrun(struct intel_fbc *fbc)
15271544 {
1528− struct intel_fbc *fbc = i915->fbc;
1529−
1530− if (!fbc)
1531− return;
1545+ struct drm_i915_private *i915 = fbc->i915;
15321546
15331547 cancel_work_sync(&fbc->underrun_work);
15341548
@@ -1544,6 +1558,38 @@ void intel_fbc_reset_underrun(struct drm_i915_private *i915) · 9 unmodified lines
15441558 mutex_unlock(&fbc->lock);
15451559 }
15461560
1561+/*
1562+ * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1563+ * @i915: the i915 device
1564+ *
1565+ * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1566+ * want to re-enable FBC after an underrun to increase test coverage.
1567+ */
1568+void intel_fbc_reset_underrun(struct drm_i915_private *i915)
1569+{
1570+ struct intel_fbc *fbc;
1571+ enum intel_fbc_id fbc_id;
1572+
1573+ for_each_intel_fbc(i915, fbc, fbc_id)
1574+ __intel_fbc_reset_underrun(fbc);
1575+}
1576+
1577+static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc)
1578+{
1579+ /*
1580+ * There's no guarantee that underrun_detected won't be set to true
1581+ * right after this check and before the work is scheduled, but that's
1582+ * not a problem since we'll check it again under the work function
1583+ * while FBC is locked. This check here is just to prevent us from
1584+ * unnecessarily scheduling the work, and it relies on the fact that we
1585+ * never switch underrun_detect back to false after it's true.
1586+ */
1587+ if (READ_ONCE(fbc->underrun_detected))
1588+ return;
1589+
1590+ schedule_work(&fbc->underrun_work);
1591+}
1592+
15471593 /**
15481594 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
15491595 * @i915: i915 device
@@ -1560,21 +1606,11 @@ void intel_fbc_reset_underrun(struct drm_i915_private *i915) · 10 unmodified lines
15601606 */
15611607 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915)
15621608 {
1563− struct intel_fbc *fbc = i915->fbc;
1564−
1565− if (!fbc)
1566− return;
1567−
1568− /* There's no guarantee that underrun_detected won't be set to true
1569− * right after this check and before the work is scheduled, but that's
1570− * not a problem since we'll check it again under the work function
1571− * while FBC is locked. This check here is just to prevent us from
1572− * unnecessarily scheduling the work, and it relies on the fact that we
1573− * never switch underrun_detect back to false after it's true. */
1574− if (READ_ONCE(fbc->underrun_detected))
1575− return;
1609+ struct intel_fbc *fbc;
1610+ enum intel_fbc_id fbc_id;
15761611
1577− schedule_work(&fbc->underrun_work);
1612+ for_each_intel_fbc(i915, fbc, fbc_id)
1613+ __intel_fbc_handle_fifo_underrun_irq(fbc);
15781614 }
15791615
15801616 /*
@@ -1622,7 +1658,8 @@ void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane) · 41 unmodified lines
16221658 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
16231659 }
16241660
1625−static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
1661+static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
1662+ enum intel_fbc_id fbc_id)
16261663 {
16271664 struct intel_fbc *fbc;
16281665
@@ -1630,6 +1667,7 @@ static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915) · 1 unmodified line
16301667 if (!fbc)
16311668 return NULL;
16321669
1670+ fbc->id = fbc_id;
16331671 fbc->i915 = i915;
16341672 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
16351673 mutex_init(&fbc->lock);
@@ -1658,32 +1696,35 @@ static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915) · 22 unmodified lines
16581696 */
16591697 void intel_fbc_init(struct drm_i915_private *i915)
16601698 {
1661− struct intel_fbc *fbc;
1699+ enum intel_fbc_id fbc_id;
16621700
16631701 if (!drm_mm_initialized(&i915->mm.stolen))
1664− mkwrite_device_info(i915)->display.has_fbc = false;
1702+ mkwrite_device_info(i915)->display.fbc_mask = 0;
16651703
16661704 if (need_fbc_vtd_wa(i915))
1667− mkwrite_device_info(i915)->display.has_fbc = false;
1705+ mkwrite_device_info(i915)->display.fbc_mask = 0;
16681706
16691707 i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
16701708 drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
16711709 i915->params.enable_fbc);
16721710
1673− if (!HAS_FBC(i915))
1674− return;
1711+ for_each_fbc_id(i915, fbc_id) {
1712+ struct intel_fbc *fbc;
16751713
1676− fbc = intel_fbc_create(i915);
1677− if (!fbc)
1678− return;
1714+ fbc = intel_fbc_create(i915, fbc_id);
1715+ if (!fbc)
1716+ continue;
16791717
1680− /* We still don't have any sort of hardware state readout for FBC, so
1681− * deactivate it in case the BIOS activated it to make sure software
1682− * matches the hardware state. */
1683− if (intel_fbc_hw_is_active(fbc))
1684− intel_fbc_hw_deactivate(fbc);
1718+ /*
1719+ * We still don't have any sort of hardware state readout
1720+ * for FBC, so deactivate it in case the BIOS activated it
1721+ * to make sure software matches the hardware state.
1722+ */
1723+ if (intel_fbc_hw_is_active(fbc))
1724+ intel_fbc_hw_deactivate(fbc);
16851725
1686− i915->fbc = fbc;
1726+ i915->fbc[fbc->id] = fbc;
1727+ }
16871728 }
16881729
16891730 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
@@ -1759,25 +1800,32 @@ DEFINE_SIMPLE_ATTRIBUTE(intel_fbc_debugfs_false_color_fops, · 69 unmodified lines
17591800 intel_fbc_debugfs_false_color_set,
17601801 "%llu\n");
17611802
1762−static void intel_fbc_debugfs_add(struct intel_fbc *fbc)
1803+static void intel_fbc_debugfs_add(struct intel_fbc *fbc,
1804+ struct dentry *parent)
17631805 {
1764− struct drm_i915_private *i915 = fbc->i915;
1765− struct drm_minor *minor = i915->drm.primary;
1766−
1767− debugfs_create_file("i915_fbc_status", 0444,
1768− minor->debugfs_root, fbc,
1769− &intel_fbc_debugfs_status_fops);
1806+ debugfs_create_file("i915_fbc_status", 0444, parent,
1807+ fbc, &intel_fbc_debugfs_status_fops);
17701808
17711809 if (fbc->funcs->set_false_color)
1772− debugfs_create_file("i915_fbc_false_color", 0644,
1773− minor->debugfs_root, fbc,
1774− &intel_fbc_debugfs_false_color_fops);
1810+ debugfs_create_file("i915_fbc_false_color", 0644, parent,
1811+ fbc, &intel_fbc_debugfs_false_color_fops);
17751812 }
17761813
1814+void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc)
1815+{
1816+ struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1817+
1818+ if (plane->fbc)
1819+ intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry);
1820+}
1821+
1822+/* FIXME: remove this once igt is on board with per-crtc stuff */
17771823 void intel_fbc_debugfs_register(struct drm_i915_private *i915)
17781824 {
1779− struct intel_fbc *fbc = i915->fbc;
1825+ struct drm_minor *minor = i915->drm.primary;
1826+ struct intel_fbc *fbc;
17801827
1828+ fbc = i915->fbc[INTEL_FBC_A];
17811829 if (fbc)
1782− intel_fbc_debugfs_add(fbc);
1830+ intel_fbc_debugfs_add(fbc, minor->debugfs_root);
17831831 }
drivers/gpu/drm/i915/display/intel_fbc.h+7−0
@@ -17,6 +17,12 @@ struct intel_fbc; · 16 unmodified lines
1717 struct intel_plane;
1818 struct intel_plane_state;
1919
20+enum intel_fbc_id {
21+ INTEL_FBC_A,
22+
23+ I915_MAX_FBCS,
24+};
25+
2026 int intel_fbc_atomic_check(struct intel_atomic_state *state);
2127 bool intel_fbc_pre_update(struct intel_atomic_state *state,
2228 struct intel_crtc *crtc);
@@ -36,6 +42,7 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv, · 13 unmodified lines
3642 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);
3743 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915);
3844 void intel_fbc_reset_underrun(struct drm_i915_private *i915);
45+void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
3946 void intel_fbc_debugfs_register(struct drm_i915_private *i915);
4047
4148 #endif /* __INTEL_FBC_H__ */
drivers/gpu/drm/i915/display/intel_gmbus.c+0−7
@@ -931,13 +931,6 @@ struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, · 930 unmodified lines
931931 return &dev_priv->gmbus[pin].adapter;
932932 }
933933
934−void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
935−{
936− struct intel_gmbus *bus = to_intel_gmbus(adapter);
937−
938− bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
939−}
940−
941934 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
942935 {
943936 struct intel_gmbus *bus = to_intel_gmbus(adapter);
drivers/gpu/drm/i915/display/intel_gmbus.h+0−1
@@ -41,7 +41,6 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter); · 40 unmodified lines
4141
4242 struct i2c_adapter *
4343 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
44−void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
4544 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
4645 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter);
4746 void intel_gmbus_reset(struct drm_i915_private *dev_priv);
drivers/gpu/drm/i915/display/intel_hdcp.c+1−2
@@ -297,8 +297,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) · 296 unmodified lines
297297 * Mailbox interface.
298298 */
299299 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
300− ret = sandybridge_pcode_write(dev_priv,
301− SKL_PCODE_LOAD_HDCP_KEYS, 1);
300+ ret = snb_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
302301 if (ret) {
303302 drm_err(&dev_priv->drm,
304303 "Failed to initiate HDCP key load (%d)\n",
drivers/gpu/drm/i915/display/intel_hdmi.c+62−38
@@ -2002,17 +2002,14 @@ intel_hdmi_mode_valid(struct drm_connector *connector, · 2001 unmodified lines
20022002 return intel_mode_valid_max_plane_size(dev_priv, mode, false);
20032003 }
20042004
2005−bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2006− int bpc, bool has_hdmi_sink, bool ycbcr420_output)
2005+bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2006+ int bpc, bool has_hdmi_sink, bool ycbcr420_output)
20072007 {
20082008 struct drm_atomic_state *state = crtc_state->uapi.state;
20092009 struct drm_connector_state *connector_state;
20102010 struct drm_connector *connector;
20112011 int i;
20122012
2013− if (crtc_state->pipe_bpp < bpc * 3)
2014− return false;
2015−
20162013 for_each_new_connector_in_state(state, connector, connector_state, i) {
20172014 if (connector_state->crtc != crtc_state->uapi.crtc)
20182015 continue;
@@ -2024,8 +2021,7 @@ bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, · 5 unmodified lines
20242021 return true;
20252022 }
20262023
2027−static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2028− int bpc)
2024+static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
20292025 {
20302026 struct drm_i915_private *dev_priv =
20312027 to_i915(crtc_state->uapi.crtc->dev);
@@ -2039,7 +2035,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, · 7 unmodified lines
20392035 * HDMI deep color affects the clocks, so it's only possible
20402036 * when not cloning with other encoder types.
20412037 */
2042− if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
2038+ if (bpc > 8 && crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
20432039 return false;
20442040
20452041 /* Display Wa_1405510057:icl,ehl */
@@ -2049,35 +2045,50 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, · 3 unmodified lines
20492045 adjusted_mode->crtc_hblank_start) % 8 == 2)
20502046 return false;
20512047
2052− return intel_hdmi_deep_color_possible(crtc_state, bpc,
2053− crtc_state->has_hdmi_sink,
2054− intel_hdmi_is_ycbcr420(crtc_state));
2048+ return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink,
2049+ intel_hdmi_is_ycbcr420(crtc_state));
20552050 }
20562051
20572052 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
20582053 struct intel_crtc_state *crtc_state,
2059− int clock)
2054+ int clock, bool respect_downstream_limits)
20602055 {
20612056 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
20622057 bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
20632058 int bpc;
20642059
2065− for (bpc = 12; bpc >= 10; bpc -= 2) {
2066− if (hdmi_deep_color_possible(crtc_state, bpc) &&
2067− hdmi_port_clock_valid(intel_hdmi,
2068− intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output),
2069− true, crtc_state->has_hdmi_sink) == MODE_OK)
2060+ /*
2061+ * pipe_bpp could already be below 8bpc due to FDI
2062+ * bandwidth constraints. HDMI minimum is 8bpc however.
2063+ */
2064+ bpc = max(crtc_state->pipe_bpp / 3, 8);
2065+
2066+ /*
2067+ * We will never exceed downstream TMDS clock limits while
2068+ * attempting deep color. If the user insists on forcing an
2069+ * out of spec mode they will have to be satisfied with 8bpc.
2070+ */
2071+ if (!respect_downstream_limits)
2072+ bpc = 8;
2073+
2074+ for (; bpc >= 8; bpc -= 2) {
2075+ int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
2076+
2077+ if (hdmi_bpc_possible(crtc_state, bpc) &&
2078+ hdmi_port_clock_valid(intel_hdmi, tmds_clock,
2079+ respect_downstream_limits,
2080+ crtc_state->has_hdmi_sink) == MODE_OK)
20702081 return bpc;
20712082 }
20722083
2073− return 8;
2084+ return -EINVAL;
20742085 }
20752086
20762087 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2077− struct intel_crtc_state *crtc_state)
2088+ struct intel_crtc_state *crtc_state,
2089+ bool respect_downstream_limits)
20782090 {
20792091 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2080− struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
20812092 const struct drm_display_mode *adjusted_mode =
20822093 &crtc_state->hw.adjusted_mode;
20832094 int bpc, clock = adjusted_mode->crtc_clock;
@@ -2085,31 +2096,25 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder, · 1 unmodified line
20852096 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
20862097 clock *= 2;
20872098
2088− bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
2099+ bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2100+ respect_downstream_limits);
2101+ if (bpc < 0)
2102+ return bpc;
20892103
2090− crtc_state->port_clock = intel_hdmi_tmds_clock(clock, bpc,
2091− intel_hdmi_is_ycbcr420(crtc_state));
2104+ crtc_state->port_clock =
2105+ intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state));
20922106
20932107 /*
20942108 * pipe_bpp could already be below 8bpc due to
20952109 * FDI bandwidth constraints. We shouldn't bump it
2096− * back up to 8bpc in that case.
2110+ * back up to the HDMI minimum 8bpc in that case.
20972111 */
2098− if (crtc_state->pipe_bpp > bpc * 3)
2099− crtc_state->pipe_bpp = bpc * 3;
2112+ crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
21002113
21012114 drm_dbg_kms(&i915->drm,
21022115 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
21032116 bpc, crtc_state->pipe_bpp);
21042117
2105− if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2106− false, crtc_state->has_hdmi_sink) != MODE_OK) {
2107− drm_dbg_kms(&i915->drm,
2108− "unsupported HDMI clock (%d kHz), rejecting mode\n",
2109− crtc_state->port_clock);
2110− return -EINVAL;
2111− }
2112−
21132118 return 0;
21142119 }
21152120
@@ -2170,7 +2175,8 @@ intel_hdmi_output_format(struct intel_connector *connector, · 54 unmodified lines
21702175
21712176 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
21722177 struct intel_crtc_state *crtc_state,
2173− const struct drm_connector_state *conn_state)
2178+ const struct drm_connector_state *conn_state,
2179+ bool respect_downstream_limits)
21742180 {
21752181 struct intel_connector *connector = to_intel_connector(conn_state->connector);
21762182 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
@@ -2187,7 +2193,7 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, · 10 unmodified lines
21872193 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
21882194 }
21892195
2190− ret = intel_hdmi_compute_clock(encoder, crtc_state);
2196+ ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
21912197 if (ret) {
21922198 if (intel_hdmi_is_ycbcr420(crtc_state) ||
21932199 !connector->base.ycbcr_420_allowed ||
@@ -2195,7 +2201,7 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, · 1 unmodified line
21952201 return ret;
21962202
21972203 crtc_state->output_format = intel_hdmi_output_format(connector, true);
2198− ret = intel_hdmi_compute_clock(encoder, crtc_state);
2204+ ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
21992205 }
22002206
22012207 return ret;
@@ -2231,9 +2237,19 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, · 29 unmodified lines
22312237 pipe_config->has_audio =
22322238 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
22332239
2234− ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state);
2240+ /*
2241+ * Try to respect downstream TMDS clock limits first, if
2242+ * that fails assume the user might know something we don't.
2243+ */
2244+ ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
22352245 if (ret)
2246+ ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2247+ if (ret) {
2248+ drm_dbg_kms(&dev_priv->drm,
2249+ "unsupported HDMI clock (%d kHz), rejecting mode\n",
2250+ pipe_config->hw.adjusted_mode.crtc_clock);
22362251 return ret;
2252+ }
22372253
22382254 if (intel_hdmi_is_ycbcr420(pipe_config)) {
22392255 ret = intel_panel_fitting(pipe_config, conn_state);
@@ -2359,6 +2375,14 @@ intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) · 119 unmodified lines
23592375 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
23602376 drm_dp_get_dual_mode_type_name(type),
23612377 hdmi->dp_dual_mode.max_tmds_clock);
2378+
2379+ /* Older VBTs are often buggy and can't be trusted :( Play it safe. */
2380+ if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
2381+ !intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2382+ drm_dbg_kms(&dev_priv->drm,
2383+ "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
2384+ hdmi->dp_dual_mode.max_tmds_clock = 0;
2385+ }
23622386 }
23632387
23642388 static bool
drivers/gpu/drm/i915/display/intel_hdmi.h+2−4
@@ -9,8 +9,6 @@ · 8 unmodified lines
99 #include <linux/hdmi.h>
1010 #include <linux/types.h>
1111
12−#include "i915_reg.h"
13−
1412 struct drm_connector;
1513 struct drm_encoder;
1614 struct drm_i915_private;
@@ -46,8 +44,8 @@ void intel_read_infoframe(struct intel_encoder *encoder, · 29 unmodified lines
4644 union hdmi_infoframe *frame);
4745 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
4846 const struct drm_connector_state *conn_state);
49−bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, int bpc,
50− bool has_hdmi_sink, bool ycbcr420_output);
47+bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
48+ int bpc, bool has_hdmi_sink, bool ycbcr420_output);
5149 int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
5250 int num_slices, int output_format, bool hdmi_all_bpp,
5351 int hdmi_max_chunk_bytes);
drivers/gpu/drm/i915/display/intel_hotplug.c+7−7
@@ -281,13 +281,13 @@ intel_encoder_hotplug(struct intel_encoder *encoder, · 280 unmodified lines
281281 ret = true;
282282
283283 if (ret) {
284− DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s (epoch counter %llu->%llu)\n",
285− connector->base.base.id,
286− connector->base.name,
287− drm_get_connector_status_name(old_status),
288− drm_get_connector_status_name(connector->base.status),
289− old_epoch_counter,
290− connector->base.epoch_counter);
284+ drm_dbg_kms(dev, "[CONNECTOR:%d:%s] status updated from %s to %s (epoch counter %llu->%llu)\n",
285+ connector->base.base.id,
286+ connector->base.name,
287+ drm_get_connector_status_name(old_status),
288+ drm_get_connector_status_name(connector->base.status),
289+ old_epoch_counter,
290+ connector->base.epoch_counter);
291291 return INTEL_HOTPLUG_CHANGED;
292292 }
293293 return INTEL_HOTPLUG_UNCHANGED;
drivers/gpu/drm/i915/display/intel_lspcon.c+77−67
@@ -78,11 +78,12 @@ static const char *lspcon_mode_name(enum drm_lspcon_mode mode) · 77 unmodified lines
7878 static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
7979 {
8080 struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
81+ struct drm_i915_private *i915 = dp_to_i915(dp);
8182 struct drm_dp_dpcd_ident *ident;
8283 u32 vendor_oui;
8384
8485 if (drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd))) {
85− DRM_ERROR("Can't read description\n");
86+ drm_err(&i915->drm, "Can't read description\n");
8687 return false;
8788 }
8889
@@ -93,16 +94,16 @@ static bool lspcon_detect_vendor(struct intel_lspcon *lspcon) · 4 unmodified lines
9394 switch (vendor_oui) {
9495 case LSPCON_VENDOR_MCA_OUI:
9596 lspcon->vendor = LSPCON_VENDOR_MCA;
96− DRM_DEBUG_KMS("Vendor: Mega Chips\n");
97+ drm_dbg_kms(&i915->drm, "Vendor: Mega Chips\n");
9798 break;
9899
99100 case LSPCON_VENDOR_PARADE_OUI:
100101 lspcon->vendor = LSPCON_VENDOR_PARADE;
101− DRM_DEBUG_KMS("Vendor: Parade Tech\n");
102+ drm_dbg_kms(&i915->drm, "Vendor: Parade Tech\n");
102103 break;
103104
104105 default:
105− DRM_ERROR("Invalid/Unknown vendor OUI\n");
106+ drm_err(&i915->drm, "Invalid/Unknown vendor OUI\n");
106107 return false;
107108 }
108109
@@ -119,21 +120,19 @@ static u32 get_hdr_status_reg(struct intel_lspcon *lspcon) · 10 unmodified lines
119120
120121 void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
121122 {
122− struct intel_digital_port *dig_port =
123− container_of(lspcon, struct intel_digital_port, lspcon);
124− struct drm_device *dev = dig_port->base.base.dev;
125− struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
123+ struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
124+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
126125 u8 hdr_caps;
127126 int ret;
128127
129− ret = drm_dp_dpcd_read(&dp->aux, get_hdr_status_reg(lspcon),
128+ ret = drm_dp_dpcd_read(&intel_dp->aux, get_hdr_status_reg(lspcon),
130129 &hdr_caps, 1);
131130
132131 if (ret < 0) {
133− drm_dbg_kms(dev, "HDR capability detection failed\n");
132+ drm_dbg_kms(&i915->drm, "HDR capability detection failed\n");
134133 lspcon->hdr_supported = false;
135134 } else if (hdr_caps & 0x1) {
136− drm_dbg_kms(dev, "LSPCON capable of HDR\n");
135+ drm_dbg_kms(&i915->drm, "LSPCON capable of HDR\n");
137136 lspcon->hdr_supported = true;
138137 }
139138 }
@@ -141,11 +140,12 @@ void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) · 1 unmodified line
141140 static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon)
142141 {
143142 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
143+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
144144 enum drm_lspcon_mode current_mode;
145145 struct i2c_adapter *adapter = &intel_dp->aux.ddc;
146146
147147 if (drm_lspcon_get_mode(intel_dp->aux.drm_dev, adapter, &current_mode)) {
148− DRM_DEBUG_KMS("Error reading LSPCON mode\n");
148+ drm_dbg_kms(&i915->drm, "Error reading LSPCON mode\n");
149149 return DRM_LSPCON_MODE_INVALID;
150150 }
151151 return current_mode;
@@ -154,22 +154,24 @@ static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) · 2 unmodified lines
154154 static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon,
155155 enum drm_lspcon_mode mode)
156156 {
157+ struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
158+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
157159 enum drm_lspcon_mode current_mode;
158160
159161 current_mode = lspcon_get_current_mode(lspcon);
160162 if (current_mode == mode)
161163 goto out;
162164
163− DRM_DEBUG_KMS("Waiting for LSPCON mode %s to settle\n",
164− lspcon_mode_name(mode));
165+ drm_dbg_kms(&i915->drm, "Waiting for LSPCON mode %s to settle\n",
166+ lspcon_mode_name(mode));
165167
166168 wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400);
167169 if (current_mode != mode)
168− DRM_ERROR("LSPCON mode hasn't settled\n");
170+ drm_err(&i915->drm, "LSPCON mode hasn't settled\n");
169171
170172 out:
171− DRM_DEBUG_KMS("Current LSPCON mode %s\n",
172− lspcon_mode_name(current_mode));
173+ drm_dbg_kms(&i915->drm, "Current LSPCON mode %s\n",
174+ lspcon_mode_name(current_mode));
173175
174176 return current_mode;
175177 }
@@ -178,44 +180,47 @@ static int lspcon_change_mode(struct intel_lspcon *lspcon, · 2 unmodified lines
178180 enum drm_lspcon_mode mode)
179181 {
180182 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
183+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
181184 int err;
182185 enum drm_lspcon_mode current_mode;
183186 struct i2c_adapter *adapter = &intel_dp->aux.ddc;
184187
185188 err = drm_lspcon_get_mode(intel_dp->aux.drm_dev, adapter, &current_mode);
186189 if (err) {
187− DRM_ERROR("Error reading LSPCON mode\n");
190+ drm_err(&i915->drm, "Error reading LSPCON mode\n");
188191 return err;
189192 }
190193
191194 if (current_mode == mode) {
192− DRM_DEBUG_KMS("Current mode = desired LSPCON mode\n");
195+ drm_dbg_kms(&i915->drm, "Current mode = desired LSPCON mode\n");
193196 return 0;
194197 }
195198
196199 err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, adapter, mode);
197200 if (err < 0) {
198− DRM_ERROR("LSPCON mode change failed\n");
201+ drm_err(&i915->drm, "LSPCON mode change failed\n");
199202 return err;
200203 }
201204
202205 lspcon->mode = mode;
203− DRM_DEBUG_KMS("LSPCON mode changed done\n");
206+ drm_dbg_kms(&i915->drm, "LSPCON mode changed done\n");
204207 return 0;
205208 }
206209
207210 static bool lspcon_wake_native_aux_ch(struct intel_lspcon *lspcon)
208211 {
212+ struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
213+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
209214 u8 rev;
210215
211216 if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV,
212217 &rev) != 1) {
213− DRM_DEBUG_KMS("Native AUX CH down\n");
218+ drm_dbg_kms(&i915->drm, "Native AUX CH down\n");
214219 return false;
215220 }
216221
217− DRM_DEBUG_KMS("Native AUX CH up, DPCD version: %d.%d\n",
218− rev >> 4, rev & 0xf);
222+ drm_dbg_kms(&i915->drm, "Native AUX CH up, DPCD version: %d.%d\n",
223+ rev >> 4, rev & 0xf);
219224
220225 return true;
221226 }
@@ -225,6 +230,7 @@ static bool lspcon_probe(struct intel_lspcon *lspcon) · 3 unmodified lines
225230 int retry;
226231 enum drm_dp_dual_mode_type adaptor_type;
227232 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
233+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
228234 struct i2c_adapter *adapter = &intel_dp->aux.ddc;
229235 enum drm_lspcon_mode expected_mode;
230236
@@ -242,13 +248,13 @@ static bool lspcon_probe(struct intel_lspcon *lspcon) · 11 unmodified lines
242248 }
243249
244250 if (adaptor_type != DRM_DP_DUAL_MODE_LSPCON) {
245− DRM_DEBUG_KMS("No LSPCON detected, found %s\n",
246− drm_dp_get_dual_mode_type_name(adaptor_type));
251+ drm_dbg_kms(&i915->drm, "No LSPCON detected, found %s\n",
252+ drm_dp_get_dual_mode_type_name(adaptor_type));
247253 return false;
248254 }
249255
250256 /* Yay ... got a LSPCON device */
251− DRM_DEBUG_KMS("LSPCON detected\n");
257+ drm_dbg_kms(&i915->drm, "LSPCON detected\n");
252258 lspcon->mode = lspcon_wait_mode(lspcon, expected_mode);
253259
254260 /*
@@ -258,7 +264,7 @@ static bool lspcon_probe(struct intel_lspcon *lspcon) · 3 unmodified lines
258264 */
259265 if (lspcon->mode != DRM_LSPCON_MODE_PCON) {
260266 if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON) < 0) {
261− DRM_ERROR("LSPCON mode change to PCON failed\n");
267+ drm_err(&i915->drm, "LSPCON mode change to PCON failed\n");
262268 return false;
263269 }
264270 }
@@ -268,13 +274,14 @@ static bool lspcon_probe(struct intel_lspcon *lspcon) · 3 unmodified lines
268274 static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon)
269275 {
270276 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
277+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
271278 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
272279 unsigned long start = jiffies;
273280
274281 while (1) {
275282 if (intel_digital_port_connected(&dig_port->base)) {
276− DRM_DEBUG_KMS("LSPCON recovering in PCON mode after %u ms\n",
277− jiffies_to_msecs(jiffies - start));
283+ drm_dbg_kms(&i915->drm, "LSPCON recovering in PCON mode after %u ms\n",
284+ jiffies_to_msecs(jiffies - start));
278285 return;
279286 }
280287
@@ -284,7 +291,7 @@ static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon) · 3 unmodified lines
284291 usleep_range(10000, 15000);
285292 }
286293
287− DRM_DEBUG_KMS("LSPCON DP descriptor mismatch after resume\n");
294+ drm_dbg_kms(&i915->drm, "LSPCON DP descriptor mismatch after resume\n");
288295 }
289296
290297 static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux)
@@ -301,7 +308,7 @@ static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux) · 10 unmodified lines
301308 ret = drm_dp_dpcd_read(aux, LSPCON_PARADE_AVI_IF_CTRL,
302309 &avi_if_ctrl, 1);
303310 if (ret < 0) {
304− DRM_ERROR("Failed to read AVI IF control\n");
311+ drm_err(aux->drm_dev, "Failed to read AVI IF control\n");
305312 return false;
306313 }
307314
@@ -309,7 +316,7 @@ static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux) · 1 unmodified line
309316 return true;
310317 }
311318
312− DRM_ERROR("Parade FW not ready to accept AVI IF\n");
319+ drm_err(aux->drm_dev, "Parade FW not ready to accept AVI IF\n");
313320 return false;
314321 }
315322
@@ -324,8 +331,8 @@ static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux, · 8 unmodified lines
324331
325332 while (block_count < 4) {
326333 if (!lspcon_parade_fw_ready(aux)) {
327− DRM_DEBUG_KMS("LSPCON FW not ready, block %d\n",
328− block_count);
334+ drm_dbg_kms(aux->drm_dev, "LSPCON FW not ready, block %d\n",
335+ block_count);
329336 return false;
330337 }
331338
@@ -333,8 +340,8 @@ static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux, · 1 unmodified line
333340 data = avi_buf + block_count * 8;
334341 ret = drm_dp_dpcd_write(aux, reg, data, 8);
335342 if (ret < 0) {
336− DRM_ERROR("Failed to write AVI IF block %d\n",
337− block_count);
343+ drm_err(aux->drm_dev, "Failed to write AVI IF block %d\n",
344+ block_count);
338345 return false;
339346 }
340347
@@ -348,15 +355,15 @@ static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux, · 7 unmodified lines
348355 avi_if_ctrl = LSPCON_PARADE_AVI_IF_KICKOFF | block_count;
349356 ret = drm_dp_dpcd_write(aux, reg, &avi_if_ctrl, 1);
350357 if (ret < 0) {
351− DRM_ERROR("Failed to update (0x%x), block %d\n",
352− reg, block_count);
358+ drm_err(aux->drm_dev, "Failed to update (0x%x), block %d\n",
359+ reg, block_count);
353360 return false;
354361 }
355362
356363 block_count++;
357364 }
358365
359− DRM_DEBUG_KMS("Wrote AVI IF blocks successfully\n");
366+ drm_dbg_kms(aux->drm_dev, "Wrote AVI IF blocks successfully\n");
360367 return true;
361368 }
362369
@@ -378,14 +385,14 @@ static bool _lspcon_write_avi_infoframe_parade(struct drm_dp_aux *aux, · 15 unmodified lines
378385 */
379386
380387 if (len > LSPCON_PARADE_AVI_IF_DATA_SIZE - 1) {
381− DRM_ERROR("Invalid length of infoframes\n");
388+ drm_err(aux->drm_dev, "Invalid length of infoframes\n");
382389 return false;
383390 }
384391
385392 memcpy(&avi_if[1], frame, len);
386393
387394 if (!_lspcon_parade_write_infoframe_blocks(aux, avi_if)) {
388− DRM_DEBUG_KMS("Failed to write infoframe blocks\n");
395+ drm_dbg_kms(aux->drm_dev, "Failed to write infoframe blocks\n");
389396 return false;
390397 }
391398
@@ -412,7 +419,7 @@ static bool _lspcon_write_avi_infoframe_mca(struct drm_dp_aux *aux, · 20 unmodified lines
412419 mdelay(50);
413420 continue;
414421 } else {
415− DRM_ERROR("DPCD write failed at:0x%x\n", reg);
422+ drm_err(aux->drm_dev, "DPCD write failed at:0x%x\n", reg);
416423 return false;
417424 }
418425 }
@@ -423,7 +430,7 @@ static bool _lspcon_write_avi_infoframe_mca(struct drm_dp_aux *aux, · 4 unmodified lines
423430 reg = LSPCON_MCA_AVI_IF_CTRL;
424431 ret = drm_dp_dpcd_read(aux, reg, &val, 1);
425432 if (ret < 0) {
426− DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
433+ drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
427434 return false;
428435 }
429436
@@ -433,19 +440,19 @@ static bool _lspcon_write_avi_infoframe_mca(struct drm_dp_aux *aux, · 3 unmodified lines
433440
434441 ret = drm_dp_dpcd_write(aux, reg, &val, 1);
435442 if (ret < 0) {
436− DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
443+ drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
437444 return false;
438445 }
439446
440447 val = 0;
441448 ret = drm_dp_dpcd_read(aux, reg, &val, 1);
442449 if (ret < 0) {
443− DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
450+ drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
444451 return false;
445452 }
446453
447454 if (val == LSPCON_MCA_AVI_IF_HANDLED)
448− DRM_DEBUG_KMS("AVI IF handled by FW\n");
455+ drm_dbg_kms(aux->drm_dev, "AVI IF handled by FW\n");
449456
450457 return true;
451458 }
@@ -457,6 +464,7 @@ void lspcon_write_infoframe(struct intel_encoder *encoder, · 5 unmodified lines
457464 {
458465 bool ret = true;
459466 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
467+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
460468 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
461469
462470 switch (type) {
@@ -469,7 +477,7 @@ void lspcon_write_infoframe(struct intel_encoder *encoder, · 6 unmodified lines
469477 frame, len);
470478 break;
471479 case HDMI_PACKET_TYPE_GAMUT_METADATA:
472− drm_dbg_kms(encoder->base.dev, "Update HDR metadata for lspcon\n");
480+ drm_dbg_kms(&i915->drm, "Update HDR metadata for lspcon\n");
473481 /* It uses the legacy hsw implementation for the same */
474482 hsw_write_infoframe(encoder, crtc_state, type, frame, len);
475483 break;
@@ -478,7 +486,7 @@ void lspcon_write_infoframe(struct intel_encoder *encoder, · 2 unmodified lines
478486 }
479487
480488 if (!ret) {
481− DRM_ERROR("Failed to write infoframes\n");
489+ drm_err(&i915->drm, "Failed to write infoframes\n");
482490 return;
483491 }
484492 }
@@ -504,11 +512,12 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, · 19 unmodified lines
504512 u8 buf[VIDEO_DIP_DATA_SIZE];
505513 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
506514 struct intel_lspcon *lspcon = &dig_port->lspcon;
515+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
507516 const struct drm_display_mode *adjusted_mode =
508517 &crtc_state->hw.adjusted_mode;
509518
510519 if (!lspcon->active) {
511− DRM_ERROR("Writing infoframes while LSPCON disabled ?\n");
520+ drm_err(&i915->drm, "Writing infoframes while LSPCON disabled ?\n");
512521 return;
513522 }
514523
@@ -518,7 +527,7 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, · 3 unmodified lines
518527 conn_state->connector,
519528 adjusted_mode);
520529 if (ret < 0) {
521− DRM_ERROR("couldn't fill AVI infoframe\n");
530+ drm_err(&i915->drm, "couldn't fill AVI infoframe\n");
522531 return;
523532 }
524533
@@ -559,7 +568,7 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, · 34 unmodified lines
559568
560569 ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf));
561570 if (ret < 0) {
562− DRM_ERROR("Failed to pack AVI IF\n");
571+ drm_err(&i915->drm, "Failed to pack AVI IF\n");
563572 return;
564573 }
565574
@@ -575,7 +584,7 @@ static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux) · 9 unmodified lines
575584
576585 ret = drm_dp_dpcd_read(aux, reg, &val, 1);
577586 if (ret < 0) {
578− DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
587+ drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
579588 return false;
580589 }
581590
@@ -590,7 +599,7 @@ static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux) · 8 unmodified lines
590599
591600 ret = drm_dp_dpcd_read(aux, reg, &val, 1);
592601 if (ret < 0) {
593− DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
602+ drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
594603 return false;
595604 }
596605
@@ -634,31 +643,32 @@ void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon) · 37 unmodified lines
634643
635644 bool lspcon_init(struct intel_digital_port *dig_port)
636645 {
637− struct intel_dp *dp = &dig_port->dp;
646+ struct intel_dp *intel_dp = &dig_port->dp;
638647 struct intel_lspcon *lspcon = &dig_port->lspcon;
639− struct drm_connector *connector = &dp->attached_connector->base;
648+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
649+ struct drm_connector *connector = &intel_dp->attached_connector->base;
640650
641651 lspcon->active = false;
642652 lspcon->mode = DRM_LSPCON_MODE_INVALID;
643653
644654 if (!lspcon_probe(lspcon)) {
645− DRM_ERROR("Failed to probe lspcon\n");
655+ drm_err(&i915->drm, "Failed to probe lspcon\n");
646656 return false;
647657 }
648658
649− if (drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd) != 0) {
650− DRM_ERROR("LSPCON DPCD read failed\n");
659+ if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) {
660+ drm_err(&i915->drm, "LSPCON DPCD read failed\n");
651661 return false;
652662 }
653663
654664 if (!lspcon_detect_vendor(lspcon)) {
655− DRM_ERROR("LSPCON vendor detection failed\n");
665+ drm_err(&i915->drm, "LSPCON vendor detection failed\n");
656666 return false;
657667 }
658668
659669 connector->ycbcr_420_allowed = true;
660670 lspcon->active = true;
661− DRM_DEBUG_KMS("Success: LSPCON init\n");
671+ drm_dbg_kms(&i915->drm, "Success: LSPCON init\n");
662672 return true;
663673 }
664674
@@ -674,16 +684,16 @@ void lspcon_resume(struct intel_digital_port *dig_port) · 9 unmodified lines
674684 {
675685 struct intel_lspcon *lspcon = &dig_port->lspcon;
676686 struct drm_device *dev = dig_port->base.base.dev;
677− struct drm_i915_private *dev_priv = to_i915(dev);
687+ struct drm_i915_private *i915 = to_i915(dev);
678688 enum drm_lspcon_mode expected_mode;
679689
680− if (!intel_bios_is_lspcon_present(dev_priv, dig_port->base.port))
690+ if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
681691 return;
682692
683693 if (!lspcon->active) {
684694 if (!lspcon_init(dig_port)) {
685− DRM_ERROR("LSPCON init failed on port %c\n",
686− port_name(dig_port->base.port));
695+ drm_err(&i915->drm, "LSPCON init failed on port %c\n",
696+ port_name(dig_port->base.port));
687697 return;
688698 }
689699 }
@@ -699,7 +709,7 @@ void lspcon_resume(struct intel_digital_port *dig_port) · 9 unmodified lines
699709 return;
700710
701711 if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON))
702− DRM_ERROR("LSPCON resume failed\n");
712+ drm_err(&i915->drm, "LSPCON resume failed\n");
703713 else
704− DRM_DEBUG_KMS("LSPCON resume success\n");
714+ drm_dbg_kms(&i915->drm, "LSPCON resume success\n");
705715 }
drivers/gpu/drm/i915/display/intel_lvds.h+1−1
@@ -8,7 +8,7 @@ · 7 unmodified lines
88
99 #include <linux/types.h>
1010
11−#include "i915_reg.h"
11+#include "i915_reg_defs.h"
1212
1313 enum pipe;
1414 struct drm_i915_private;
drivers/gpu/drm/i915/display/intel_opregion.c+55−1
@@ -35,6 +35,7 @@ · 34 unmodified lines
3535 #include "intel_backlight.h"
3636 #include "intel_display_types.h"
3737 #include "intel_opregion.h"
38+#include "intel_pci_config.h"
3839
3940 #define OPREGION_HEADER_OFFSET 0
4041 #define OPREGION_ACPI_OFFSET 0x100
@@ -195,6 +196,8 @@ struct opregion_asle_ext { · 154 unmodified lines
195196 #define ASLE_IUER_WINDOWS_BTN (1 << 1)
196197 #define ASLE_IUER_POWER_BTN (1 << 0)
197198
199+#define ASLE_PHED_EDID_VALID_MASK 0x3
200+
198201 /* Software System Control Interrupt (SWSCI) */
199202 #define SWSCI_SCIC_INDICATOR (1 << 0)
200203 #define SWSCI_SCIC_MAIN_FUNCTION_SHIFT 1
@@ -908,8 +911,10 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) · 707 unmodified lines
908911 opregion->asle->ardy = ASLE_ARDY_NOT_READY;
909912 }
910913
911− if (mboxes & MBOX_ASLE_EXT)
914+ if (mboxes & MBOX_ASLE_EXT) {
912915 drm_dbg(&dev_priv->drm, "ASLE extension supported\n");
916+ opregion->asle_ext = base + OPREGION_ASLE_EXT_OFFSET;
917+ }
913918
914919 if (intel_load_vbt_firmware(dev_priv) == 0)
915920 goto out;
@@ -1036,6 +1041,54 @@ intel_opregion_get_panel_type(struct drm_i915_private *dev_priv) · 120 unmodified lines
10361041 return ret - 1;
10371042 }
10381043
1044+/**
1045+ * intel_opregion_get_edid - Fetch EDID from ACPI OpRegion mailbox #5
1046+ * @intel_connector: eDP connector
1047+ *
1048+ * This reads the ACPI Opregion mailbox #5 to extract the EDID that is passed
1049+ * to it.
1050+ *
1051+ * Returns:
1052+ * The EDID in the OpRegion, or NULL if there is none or it's invalid.
1053+ *
1054+ */
1055+struct edid *intel_opregion_get_edid(struct intel_connector *intel_connector)
1056+{
1057+ struct drm_connector *connector = &intel_connector->base;
1058+ struct drm_i915_private *i915 = to_i915(connector->dev);
1059+ struct intel_opregion *opregion = &i915->opregion;
1060+ const void *in_edid;
1061+ const struct edid *edid;
1062+ struct edid *new_edid;
1063+ int len;
1064+
1065+ if (!opregion->asle_ext)
1066+ return NULL;
1067+
1068+ in_edid = opregion->asle_ext->bddc;
1069+
1070+ /* Validity corresponds to number of 128-byte blocks */
1071+ len = (opregion->asle_ext->phed & ASLE_PHED_EDID_VALID_MASK) * 128;
1072+ if (!len || !memchr_inv(in_edid, 0, len))
1073+ return NULL;
1074+
1075+ edid = in_edid;
1076+
1077+ if (len < EDID_LENGTH * (1 + edid->extensions)) {
1078+ drm_dbg_kms(&i915->drm, "Invalid EDID in ACPI OpRegion (Mailbox #5): too short\n");
1079+ return NULL;
1080+ }
1081+ new_edid = drm_edid_duplicate(edid);
1082+ if (!new_edid)
1083+ return NULL;
1084+ if (!drm_edid_is_valid(new_edid)) {
1085+ kfree(new_edid);
1086+ drm_dbg_kms(&i915->drm, "Invalid EDID in ACPI OpRegion (Mailbox #5)\n");
1087+ return NULL;
1088+ }
1089+ return new_edid;
1090+}
1091+
10391092 void intel_opregion_register(struct drm_i915_private *i915)
10401093 {
10411094 struct intel_opregion *opregion = &i915->opregion;
@@ -1129,6 +1182,7 @@ void intel_opregion_unregister(struct drm_i915_private *i915) · 87 unmodified lines
11291182 opregion->acpi = NULL;
11301183 opregion->swsci = NULL;
11311184 opregion->asle = NULL;
1185+ opregion->asle_ext = NULL;
11321186 opregion->vbt = NULL;
11331187 opregion->lid_state = NULL;
11341188 }
drivers/gpu/drm/i915/display/intel_opregion.h+10−0
@@ -29,12 +29,14 @@ · 28 unmodified lines
2929 #include <linux/pci.h>
3030
3131 struct drm_i915_private;
32+struct intel_connector;
3233 struct intel_encoder;
3334
3435 struct opregion_header;
3536 struct opregion_acpi;
3637 struct opregion_swsci;
3738 struct opregion_asle;
39+struct opregion_asle_ext;
3840
3941 struct intel_opregion {
4042 struct opregion_header *header;
@@ -43,6 +45,7 @@ struct intel_opregion { · 2 unmodified lines
4345 u32 swsci_gbda_sub_functions;
4446 u32 swsci_sbcb_sub_functions;
4547 struct opregion_asle *asle;
48+ struct opregion_asle_ext *asle_ext;
4649 void *rvda;
4750 void *vbt_firmware;
4851 const void *vbt;
@@ -71,6 +74,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, · 22 unmodified lines
7174 int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
7275 pci_power_t state);
7376 int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
77+struct edid *intel_opregion_get_edid(struct intel_connector *connector);
7478
7579 #else /* CONFIG_ACPI*/
7680
@@ -117,6 +121,12 @@ static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev) · 40 unmodified lines
117121 return -ENODEV;
118122 }
119123
124+static inline struct edid *
125+intel_opregion_get_edid(struct intel_connector *connector)
126+{
127+ return NULL;
128+}
129+
120130 #endif /* CONFIG_ACPI */
121131
122132 #endif
drivers/gpu/drm/i915/display/intel_overlay.c+4−0
@@ -38,6 +38,7 @@ · 37 unmodified lines
3838 #include "intel_display_types.h"
3939 #include "intel_frontbuffer.h"
4040 #include "intel_overlay.h"
41+#include "intel_pci_config.h"
4142
4243 /* Limits for overlay size. According to intel doc, the real limits are:
4344 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
@@ -959,6 +960,9 @@ static int check_overlay_dst(struct intel_overlay *overlay, · 915 unmodified lines
959960 const struct intel_crtc_state *pipe_config =
960961 overlay->crtc->config;
961962
963+ if (rec->dst_height == 0 || rec->dst_width == 0)
964+ return -EINVAL;
965+
962966 if (rec->dst_x < pipe_config->pipe_src_w &&
963967 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
964968 rec->dst_y < pipe_config->pipe_src_h &&
drivers/gpu/drm/i915/display/intel_pch_display.c+76−12
@@ -88,6 +88,50 @@ static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, · 87 unmodified lines
8888 pipe_name(pipe));
8989 }
9090
91+static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
92+ const struct intel_link_m_n *m_n)
93+{
94+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
95+ enum pipe pipe = crtc->pipe;
96+
97+ intel_set_m_n(dev_priv, m_n,
98+ PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
99+ PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
100+}
101+
102+static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
103+ const struct intel_link_m_n *m_n)
104+{
105+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
106+ enum pipe pipe = crtc->pipe;
107+
108+ intel_set_m_n(dev_priv, m_n,
109+ PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
110+ PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
111+}
112+
113+void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
114+ struct intel_link_m_n *m_n)
115+{
116+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
117+ enum pipe pipe = crtc->pipe;
118+
119+ intel_get_m_n(dev_priv, m_n,
120+ PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
121+ PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
122+}
123+
124+void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
125+ struct intel_link_m_n *m_n)
126+{
127+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
128+ enum pipe pipe = crtc->pipe;
129+
130+ intel_get_m_n(dev_priv, m_n,
131+ PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
132+ PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
133+}
134+
91135 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
92136 enum pipe pch_transcoder)
93137 {
@@ -157,20 +201,20 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) · 63 unmodified lines
157201 */
158202 val &= ~PIPECONF_BPC_MASK;
159203 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
160− val |= PIPECONF_8BPC;
204+ val |= PIPECONF_BPC_8;
161205 else
162206 val |= pipeconf_val & PIPECONF_BPC_MASK;
163207 }
164208
165209 val &= ~TRANS_INTERLACE_MASK;
166− if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
210+ if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {
167211 if (HAS_PCH_IBX(dev_priv) &&
168212 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
169− val |= TRANS_LEGACY_INTERLACED_ILK;
213+ val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
170214 else
171− val |= TRANS_INTERLACED;
215+ val |= TRANS_INTERLACE_INTERLACED;
172216 } else {
173− val |= TRANS_PROGRESSIVE;
217+ val |= TRANS_INTERLACE_PROGRESSIVE;
174218 }
175219
176220 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
@@ -211,6 +255,20 @@ static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) · 34 unmodified lines
211255 }
212256 }
213257
258+void ilk_pch_pre_enable(struct intel_atomic_state *state,
259+ struct intel_crtc *crtc)
260+{
261+ const struct intel_crtc_state *crtc_state =
262+ intel_atomic_get_new_crtc_state(state, crtc);
263+
264+ /*
265+ * Note: FDI PLL enabling _must_ be done before we enable the
266+ * cpu pipes, hence this is separate from all the other fdi/pch
267+ * enabling.
268+ */
269+ ilk_fdi_pll_enable(crtc_state);
270+}
271+
214272 /*
215273 * Enable PCH resources required for PCH ports:
216274 * - PCH PLLs
@@ -264,6 +322,10 @@ void ilk_pch_enable(struct intel_atomic_state *state, · 47 unmodified lines
264322
265323 /* set transcoder timing, panel must allow it */
266324 assert_pps_unlocked(dev_priv, pipe);
325+ if (intel_crtc_has_dp_encoder(crtc_state)) {
326+ intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n);
327+ intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2);
328+ }
267329 ilk_pch_transcoder_set_timings(crtc_state, pipe);
268330
269331 intel_fdi_normal_train(crtc);
@@ -279,7 +341,8 @@ void ilk_pch_enable(struct intel_atomic_state *state, · 9 unmodified lines
279341
280342 temp = intel_de_read(dev_priv, reg);
281343 temp &= ~(TRANS_DP_PORT_SEL_MASK |
282− TRANS_DP_SYNC_MASK |
344+ TRANS_DP_VSYNC_ACTIVE_HIGH |
345+ TRANS_DP_HSYNC_ACTIVE_HIGH |
283346 TRANS_DP_BPC_MASK);
284347 temp |= TRANS_DP_OUTPUT_ENABLE;
285348 temp |= bpc << 9; /* same format but at 11:9 */
@@ -371,7 +434,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) · 85 unmodified lines
371434 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
372435 FDI_DP_PORT_WIDTH_SHIFT) + 1;
373436
374− ilk_get_fdi_m_n_config(crtc, crtc_state);
437+ intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
438+ &crtc_state->fdi_m_n);
375439
376440 if (HAS_PCH_IBX(dev_priv)) {
377441 /*
@@ -422,11 +486,10 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, · 44 unmodified lines
422486 val = TRANS_ENABLE;
423487 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
424488
425− if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
426− PIPECONF_INTERLACED_ILK)
427− val |= TRANS_INTERLACED;
489+ if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)
490+ val |= TRANS_INTERLACE_INTERLACED;
428491 else
429− val |= TRANS_PROGRESSIVE;
492+ val |= TRANS_INTERLACE_PROGRESSIVE;
430493
431494 intel_de_write(dev_priv, LPT_TRANSCONF, val);
432495 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
@@ -495,7 +558,8 @@ void lpt_pch_get_config(struct intel_crtc_state *crtc_state) · 62 unmodified lines
495558 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
496559 FDI_DP_PORT_WIDTH_SHIFT) + 1;
497560
498− ilk_get_fdi_m_n_config(crtc, crtc_state);
561+ intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
562+ &crtc_state->fdi_m_n);
499563
500564 crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
501565 }
drivers/gpu/drm/i915/display/intel_pch_display.h+8−0
@@ -9,7 +9,10 @@ · 8 unmodified lines
99 struct intel_atomic_state;
1010 struct intel_crtc;
1111 struct intel_crtc_state;
12+struct intel_link_m_n;
1213
14+void ilk_pch_pre_enable(struct intel_atomic_state *state,
15+ struct intel_crtc *crtc);
1316 void ilk_pch_enable(struct intel_atomic_state *state,
1417 struct intel_crtc *crtc);
1518 void ilk_pch_disable(struct intel_atomic_state *state,
@@ -24,4 +27,9 @@ void lpt_pch_disable(struct intel_atomic_state *state, · 8 unmodified lines
2427 struct intel_crtc *crtc);
2528 void lpt_pch_get_config(struct intel_crtc_state *crtc_state);
2629
30+void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
31+ struct intel_link_m_n *m_n);
32+void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
33+ struct intel_link_m_n *m_n);
34+
2735 #endif
drivers/gpu/drm/i915/display/intel_pps.c+13−9
@@ -1131,16 +1131,20 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) · 1130 unmodified lines
11311131 }
11321132
11331133 static void
1134−intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
1134+intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name,
1135+ const struct edp_power_seq *seq)
11351136 {
1136− DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
1137− state_name,
1138− seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
1137+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1138+
1139+ drm_dbg_kms(&i915->drm, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
1140+ state_name,
1141+ seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
11391142 }
11401143
11411144 static void
11421145 intel_pps_verify_state(struct intel_dp *intel_dp)
11431146 {
1147+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
11441148 struct edp_power_seq hw;
11451149 struct edp_power_seq *sw = &intel_dp->pps.pps_delays;
11461150
@@ -1148,9 +1152,9 @@ intel_pps_verify_state(struct intel_dp *intel_dp) · 1 unmodified line
11481152
11491153 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
11501154 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
1151− DRM_ERROR("PPS state mismatch\n");
1152− intel_pps_dump_state("sw", sw);
1153− intel_pps_dump_state("hw", &hw);
1155+ drm_err(&i915->drm, "PPS state mismatch\n");
1156+ intel_pps_dump_state(intel_dp, "sw", sw);
1157+ intel_pps_dump_state(intel_dp, "hw", &hw);
11541158 }
11551159 }
11561160
@@ -1168,7 +1172,7 @@ static void pps_init_delays(struct intel_dp *intel_dp) · 11 unmodified lines
11681172
11691173 intel_pps_readout_hw_state(intel_dp, &cur);
11701174
1171− intel_pps_dump_state("cur", &cur);
1175+ intel_pps_dump_state(intel_dp, "cur", &cur);
11721176
11731177 vbt = dev_priv->vbt.edp.pps;
11741178 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
@@ -1200,7 +1204,7 @@ static void pps_init_delays(struct intel_dp *intel_dp) · 25 unmodified lines
12001204 * too. */
12011205 spec.t11_t12 = (510 + 100) * 10;
12021206
1203− intel_pps_dump_state("vbt", &vbt);
1207+ intel_pps_dump_state(intel_dp, "vbt", &vbt);
12041208
12051209 /* Use the max of the register settings and vbt. If both are
12061210 * unset, fall back to the spec limits. */
drivers/gpu/drm/i915/display/intel_sdvo.h+1−1
@@ -8,7 +8,7 @@ · 7 unmodified lines
88
99 #include <linux/types.h>
1010
11−#include "i915_reg.h"
11+#include "i915_reg_defs.h"
1212
1313 struct drm_i915_private;
1414 enum pipe;
drivers/gpu/drm/i915/display/intel_snps_phy.c+16−14
@@ -10,6 +10,7 @@ · 9 unmodified lines
1010 #include "intel_de.h"
1111 #include "intel_display_types.h"
1212 #include "intel_snps_phy.h"
13+#include "intel_snps_phy_regs.h"
1314
1415 /**
1516 * DOC: Synopsis PHY support
@@ -23,18 +24,18 @@ · 7 unmodified lines
2324 * since it is not handled by the shared DPLL framework as on other platforms.
2425 */
2526
26−void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv)
27+void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
2728 {
2829 enum phy phy;
2930
3031 for_each_phy_masked(phy, ~0) {
31− if (!intel_phy_is_snps(dev_priv, phy))
32+ if (!intel_phy_is_snps(i915, phy))
3233 continue;
3334
34− if (intel_de_wait_for_clear(dev_priv, ICL_PHY_MISC(phy),
35+ if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
3536 DG2_PHY_DP_TX_ACK_MASK, 25))
36− DRM_ERROR("SNPS PHY %c failed to calibrate after 25ms.\n",
37− phy);
37+ drm_err(&i915->drm, "SNPS PHY %c failed to calibrate after 25ms.\n",
38+ phy);
3839 }
3940 }
4041
@@ -775,6 +776,7 @@ intel_mpllb_tables_get(struct intel_crtc_state *crtc_state, · 734 unmodified lines
775776 int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
776777 struct intel_encoder *encoder)
777778 {
779+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
778780 const struct intel_mpllb_state * const *tables;
779781 int i;
780782
@@ -786,8 +788,8 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, · 5 unmodified lines
786788 * until we have a proper algorithm under a valid
787789 * license.
788790 */
789− DRM_DEBUG_KMS("Can't support HDMI link rate %d\n",
790− crtc_state->port_clock);
791+ drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n",
792+ crtc_state->port_clock);
791793 return -EINVAL;
792794 }
793795 }
@@ -854,7 +856,7 @@ void intel_mpllb_enable(struct intel_encoder *encoder, · 60 unmodified lines
854856 * dp_mpllb_state interface signal.
855857 */
856858 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5))
857− DRM_ERROR("Port %c PLL not locked\n", phy_name(phy));
859+ drm_dbg_kms(&dev_priv->drm, "Port %c PLL not locked\n", phy_name(phy));
858860
859861 /*
860862 * 11. If the frequency will result in a change to the voltage
@@ -867,8 +869,8 @@ void intel_mpllb_enable(struct intel_encoder *encoder, · 6 unmodified lines
867869
868870 void intel_mpllb_disable(struct intel_encoder *encoder)
869871 {
870− struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
871− enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
872+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
873+ enum phy phy = intel_port_to_phy(i915, encoder->port);
872874 i915_reg_t enable_reg = (phy <= PHY_D ?
873875 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
874876
@@ -881,21 +883,21 @@ void intel_mpllb_disable(struct intel_encoder *encoder) · 6 unmodified lines
881883 */
882884
883885 /* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */
884− intel_uncore_rmw(&dev_priv->uncore, enable_reg, PLL_ENABLE, 0);
886+ intel_uncore_rmw(&i915->uncore, enable_reg, PLL_ENABLE, 0);
885887
886888 /*
887889 * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0".
888890 * This will allow the PLL to stop running.
889891 */
890− intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_MPLLB_DIV(phy),
892+ intel_uncore_rmw(&i915->uncore, SNPS_PHY_MPLLB_DIV(phy),
891893 SNPS_PHY_MPLLB_FORCE_EN, 0);
892894
893895 /*
894896 * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
895897 * (dp_txX_ack) that the new transmitter setting request is completed.
896898 */
897− if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 5))
898− DRM_ERROR("Port %c PLL not locked\n", phy_name(phy));
899+ if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 5))
900+ drm_err(&i915->drm, "Port %c PLL not locked\n", phy_name(phy));
899901
900902 /*
901903 * 6. If the frequency will result in a change to the voltage
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h+75−0
@@ -0,0 +1,75 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2022 Intel Corporation
4+ */
5+
6+#ifndef __INTEL_SNPS_PHY_REGS__
7+#define __INTEL_SNPS_PHY_REGS__
8+
9+#include "i915_reg_defs.h"
10+
11+#define _SNPS_PHY_A_BASE 0x168000
12+#define _SNPS_PHY_B_BASE 0x169000
13+#define _SNPS_PHY(phy) _PHY(phy, \
14+ _SNPS_PHY_A_BASE, \
15+ _SNPS_PHY_B_BASE)
16+#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
17+ _SNPS_PHY_A_BASE + (reg))
18+#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
19+#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
20+ (reg) + (ln) * 0x10))
21+
22+#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
23+#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
24+#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
25+#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
26+#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
27+
28+#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
29+#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
30+#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
31+#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
32+#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
33+#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
34+#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
35+#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
36+#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
37+#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
38+#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
39+#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
40+
41+#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
42+#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
43+#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
44+#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
45+
46+#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
47+#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
48+#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
49+
50+#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
51+#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
52+#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
53+#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
54+
55+#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
56+#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
57+
58+#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
59+#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
60+#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
61+#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
62+#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
63+
64+#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
65+#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
66+
67+#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
68+#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
69+
70+#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
71+#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
72+#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
73+#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
74+
75+#endif /* __INTEL_SNPS_PHY_REGS__ */
drivers/gpu/drm/i915/display/intel_sprite.c+39−26
@@ -53,6 +53,7 @@ · 52 unmodified lines
5353
5454 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
5555 {
56+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
5657 const struct drm_framebuffer *fb = plane_state->hw.fb;
5758 struct drm_rect *src = &plane_state->uapi.src;
5859 u32 src_x, src_y, src_w, src_h, hsub, vsub;
@@ -94,14 +95,14 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) · 35 unmodified lines
9495 hsub = vsub = max(hsub, vsub);
9596
9697 if (src_x % hsub || src_w % hsub) {
97− DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
98− src_x, src_w, hsub, yesno(rotated));
98+ drm_dbg_kms(&i915->drm, "src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
99+ src_x, src_w, hsub, yesno(rotated));
99100 return -EINVAL;
100101 }
101102
102103 if (src_y % vsub || src_h % vsub) {
103− DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
104− src_y, src_h, vsub, yesno(rotated));
104+ drm_dbg_kms(&i915->drm, "src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
105+ src_y, src_h, vsub, yesno(rotated));
105106 return -EINVAL;
106107 }
107108
@@ -313,7 +314,7 @@ static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) · 205 unmodified lines
313314 u32 sprctl = 0;
314315
315316 if (crtc_state->gamma_enable)
316− sprctl |= SP_GAMMA_ENABLE;
317+ sprctl |= SP_PIPE_GAMMA_ENABLE;
317318
318319 return sprctl;
319320 }
@@ -436,9 +437,9 @@ vlv_sprite_update_noarm(struct intel_plane *plane, · 116 unmodified lines
436437 intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
437438 plane_state->view.color_plane[0].mapping_stride);
438439 intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
439− (crtc_y << 16) | crtc_x);
440+ SP_POS_Y(crtc_y) | SP_POS_X(crtc_x));
440441 intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
441− ((crtc_h - 1) << 16) | (crtc_w - 1));
442+ SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1));
442443
443444 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
444445 }
@@ -479,7 +480,8 @@ vlv_sprite_update_arm(struct intel_plane *plane, · 34 unmodified lines
479480 intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
480481
481482 intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);
482− intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x);
483+ intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id),
484+ SP_OFFSET_Y(y) | SP_OFFSET_X(x));
483485
484486 /*
485487 * The control register self-arms if the plane was previously
@@ -700,7 +702,7 @@ static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) · 214 unmodified lines
700702 u32 sprctl = 0;
701703
702704 if (crtc_state->gamma_enable)
703− sprctl |= SPRITE_GAMMA_ENABLE;
705+ sprctl |= SPRITE_PIPE_GAMMA_ENABLE;
704706
705707 if (crtc_state->csc_enable)
706708 sprctl |= SPRITE_PIPE_CSC_ENABLE;
@@ -770,7 +772,7 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state, · 63 unmodified lines
770772 }
771773
772774 if (!ivb_need_sprite_gamma(plane_state))
773− sprctl |= SPRITE_INT_GAMMA_DISABLE;
775+ sprctl |= SPRITE_PLANE_GAMMA_DISABLE;
774776
775777 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
776778 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
@@ -863,14 +865,18 @@ ivb_sprite_update_noarm(struct intel_plane *plane, · 86 unmodified lines
863865 unsigned long irqflags;
864866
865867 if (crtc_w != src_w || crtc_h != src_h)
866− sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
868+ sprscale = SPRITE_SCALE_ENABLE |
869+ SPRITE_SRC_WIDTH(src_w - 1) |
870+ SPRITE_SRC_HEIGHT(src_h - 1);
867871
868872 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
869873
870874 intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
871875 plane_state->view.color_plane[0].mapping_stride);
872− intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
873− intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
876+ intel_de_write_fw(dev_priv, SPRPOS(pipe),
877+ SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x));
878+ intel_de_write_fw(dev_priv, SPRSIZE(pipe),
879+ SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1));
874880 if (IS_IVYBRIDGE(dev_priv))
875881 intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
876882
@@ -907,10 +913,12 @@ ivb_sprite_update_arm(struct intel_plane *plane, · 30 unmodified lines
907913 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
908914 * register */
909915 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
910− intel_de_write_fw(dev_priv, SPROFFSET(pipe), (y << 16) | x);
916+ intel_de_write_fw(dev_priv, SPROFFSET(pipe),
917+ SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
911918 } else {
912919 intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset);
913− intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), (y << 16) | x);
920+ intel_de_write_fw(dev_priv, SPRTILEOFF(pipe),
921+ SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
914922 }
915923
916924 /*
@@ -1047,7 +1055,7 @@ static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) · 130 unmodified lines
10471055 u32 dvscntr = 0;
10481056
10491057 if (crtc_state->gamma_enable)
1050− dvscntr |= DVS_GAMMA_ENABLE;
1058+ dvscntr |= DVS_PIPE_GAMMA_ENABLE;
10511059
10521060 if (crtc_state->csc_enable)
10531061 dvscntr |= DVS_PIPE_CSC_ENABLE;
@@ -1199,14 +1207,18 @@ g4x_sprite_update_noarm(struct intel_plane *plane, · 145 unmodified lines
11991207 unsigned long irqflags;
12001208
12011209 if (crtc_w != src_w || crtc_h != src_h)
1202− dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
1210+ dvsscale = DVS_SCALE_ENABLE |
1211+ DVS_SRC_WIDTH(src_w - 1) |
1212+ DVS_SRC_HEIGHT(src_h - 1);
12031213
12041214 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
12051215
12061216 intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
12071217 plane_state->view.color_plane[0].mapping_stride);
1208− intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
1209− intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
1218+ intel_de_write_fw(dev_priv, DVSPOS(pipe),
1219+ DVS_POS_Y(crtc_y) | DVS_POS_X(crtc_x));
1220+ intel_de_write_fw(dev_priv, DVSSIZE(pipe),
1221+ DVS_HEIGHT(crtc_h - 1) | DVS_WIDTH(crtc_w - 1));
12101222 intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
12111223
12121224 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
@@ -1321,6 +1333,7 @@ static int · 108 unmodified lines
13211333 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
13221334 struct intel_plane_state *plane_state)
13231335 {
1336+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
13241337 const struct drm_framebuffer *fb = plane_state->hw.fb;
13251338 const struct drm_rect *src = &plane_state->uapi.src;
13261339 const struct drm_rect *dst = &plane_state->uapi.dst;
@@ -1346,7 +1359,7 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, · 19 unmodified lines
13461359
13471360 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
13481361 if (src_h & 1) {
1349− DRM_DEBUG_KMS("Source height must be even with interlaced modes\n");
1362+ drm_dbg_kms(&i915->drm, "Source height must be even with interlaced modes\n");
13501363 return -EINVAL;
13511364 }
13521365 min_height = 6;
@@ -1358,20 +1371,20 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, · 5 unmodified lines
13581371
13591372 if (src_w < min_width || src_h < min_height ||
13601373 src_w > 2048 || src_h > 2048) {
1361− DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
1362− src_w, src_h, min_width, min_height, 2048, 2048);
1374+ drm_dbg_kms(&i915->drm, "Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
1375+ src_w, src_h, min_width, min_height, 2048, 2048);
13631376 return -EINVAL;
13641377 }
13651378
13661379 if (width_bytes > 4096) {
1367− DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n",
1368− width_bytes, 4096);
1380+ drm_dbg_kms(&i915->drm, "Fetch width (%d) exceeds hardware max with scaling (%u)\n",
1381+ width_bytes, 4096);
13691382 return -EINVAL;
13701383 }
13711384
13721385 if (stride > 4096) {
1373− DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
1374− stride, 4096);
1386+ drm_dbg_kms(&i915->drm, "Stride (%u) exceeds hardware max with scaling (%u)\n",
1387+ stride, 4096);
13751388 return -EINVAL;
13761389 }
13771390
drivers/gpu/drm/i915/display/intel_tc.c+4−1
@@ -4,10 +4,12 @@ · 3 unmodified lines
44 */
55
66 #include "i915_drv.h"
7+#include "i915_reg.h"
78 #include "intel_display.h"
89 #include "intel_display_types.h"
910 #include "intel_dp_mst.h"
1011 #include "intel_tc.h"
12+#include "intel_tc_phy_regs.h"
1113
1214 static const char *tc_port_mode_name(enum tc_port_mode mode)
1315 {
@@ -345,10 +347,11 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port) · 331 unmodified lines
345347 static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port)
346348 {
347349 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
350+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
348351 struct intel_uncore *uncore = &i915->uncore;
349352 u32 val;
350353
351− val = intel_uncore_read(uncore, TCSS_DDI_STATUS(dig_port->tc_phy_fia_idx));
354+ val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));
352355 if (val == 0xffffffff) {
353356 drm_dbg_kms(&i915->drm,
354357 "Port %s: PHY in TCCOLD, assuming not complete\n",
drivers/gpu/drm/i915/display/intel_tc_phy_regs.h+280−0
@@ -0,0 +1,280 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2022 Intel Corporation
4+ */
5+
6+#ifndef __INTEL_TC_PHY_REGS__
7+#define __INTEL_TC_PHY_REGS__
8+
9+#include "i915_reg_defs.h"
10+
11+#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
12+ _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
13+
14+#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
15+#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
16+#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
17+#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
18+#define MG_TX1_LINK_PARAMS(ln, tc_port) \
19+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
20+ MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
21+ MG_TX_LINK_PARAMS_TX1LN1_PORT1)
22+
23+#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
24+#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
25+#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
26+#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
27+#define MG_TX2_LINK_PARAMS(ln, tc_port) \
28+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
29+ MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
30+ MG_TX_LINK_PARAMS_TX2LN1_PORT1)
31+#define CRI_USE_FS32 (1 << 5)
32+
33+#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
34+#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
35+#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
36+#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
37+#define MG_TX1_PISO_READLOAD(ln, tc_port) \
38+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
39+ MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
40+ MG_TX_PISO_READLOAD_TX1LN1_PORT1)
41+
42+#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
43+#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
44+#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
45+#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
46+#define MG_TX2_PISO_READLOAD(ln, tc_port) \
47+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
48+ MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
49+ MG_TX_PISO_READLOAD_TX2LN1_PORT1)
50+#define CRI_CALCINIT (1 << 1)
51+
52+#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
53+#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
54+#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
55+#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
56+#define MG_TX1_SWINGCTRL(ln, tc_port) \
57+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
58+ MG_TX_SWINGCTRL_TX1LN0_PORT2, \
59+ MG_TX_SWINGCTRL_TX1LN1_PORT1)
60+
61+#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
62+#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
63+#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
64+#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
65+#define MG_TX2_SWINGCTRL(ln, tc_port) \
66+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
67+ MG_TX_SWINGCTRL_TX2LN0_PORT2, \
68+ MG_TX_SWINGCTRL_TX2LN1_PORT1)
69+#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
70+#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
71+
72+#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
73+#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
74+#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
75+#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
76+#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
77+#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
78+#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
79+#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
80+#define MG_TX1_DRVCTRL(ln, tc_port) \
81+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
82+ MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
83+ MG_TX_DRVCTRL_TX1LN1_TXPORT1)
84+
85+#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
86+#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
87+#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
88+#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
89+#define MG_TX2_DRVCTRL(ln, tc_port) \
90+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
91+ MG_TX_DRVCTRL_TX2LN0_PORT2, \
92+ MG_TX_DRVCTRL_TX2LN1_PORT1)
93+#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
94+#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
95+#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
96+#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
97+#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
98+#define CRI_LOADGEN_SEL(x) ((x) << 12)
99+#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
100+
101+#define MG_CLKHUB_LN0_PORT1 0x16839C
102+#define MG_CLKHUB_LN1_PORT1 0x16879C
103+#define MG_CLKHUB_LN0_PORT2 0x16939C
104+#define MG_CLKHUB_LN1_PORT2 0x16979C
105+#define MG_CLKHUB(ln, tc_port) \
106+ MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
107+ MG_CLKHUB_LN0_PORT2, \
108+ MG_CLKHUB_LN1_PORT1)
109+#define CFG_LOW_RATE_LKREN_EN (1 << 11)
110+
111+#define MG_TX_DCC_TX1LN0_PORT1 0x168110
112+#define MG_TX_DCC_TX1LN1_PORT1 0x168510
113+#define MG_TX_DCC_TX1LN0_PORT2 0x169110
114+#define MG_TX_DCC_TX1LN1_PORT2 0x169510
115+#define MG_TX1_DCC(ln, tc_port) \
116+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
117+ MG_TX_DCC_TX1LN0_PORT2, \
118+ MG_TX_DCC_TX1LN1_PORT1)
119+#define MG_TX_DCC_TX2LN0_PORT1 0x168090
120+#define MG_TX_DCC_TX2LN1_PORT1 0x168490
121+#define MG_TX_DCC_TX2LN0_PORT2 0x169090
122+#define MG_TX_DCC_TX2LN1_PORT2 0x169490
123+#define MG_TX2_DCC(ln, tc_port) \
124+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
125+ MG_TX_DCC_TX2LN0_PORT2, \
126+ MG_TX_DCC_TX2LN1_PORT1)
127+#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
128+#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
129+#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
130+
131+#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
132+#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
133+#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
134+#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
135+#define MG_DP_MODE(ln, tc_port) \
136+ MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
137+ MG_DP_MODE_LN0_ACU_PORT2, \
138+ MG_DP_MODE_LN1_ACU_PORT1)
139+#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
140+#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
141+
142+#define FIA1_BASE 0x163000
143+#define FIA2_BASE 0x16E000
144+#define FIA3_BASE 0x16F000
145+#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
146+#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
147+
148+/* ICL PHY DFLEX registers */
149+#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
150+#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
151+#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
152+#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
153+#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
154+#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
155+#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
156+
157+#define _MG_REFCLKIN_CTL_PORT1 0x16892C
158+#define _MG_REFCLKIN_CTL_PORT2 0x16992C
159+#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
160+#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
161+#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
162+ _MG_REFCLKIN_CTL_PORT1, \
163+ _MG_REFCLKIN_CTL_PORT2)
164+
165+#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
166+#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
167+#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
168+#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
169+#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
170+#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
171+#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
172+ _MG_CLKTOP2_CORECLKCTL1_PORT1, \
173+ _MG_CLKTOP2_CORECLKCTL1_PORT2)
174+
175+#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
176+#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
177+#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
178+#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
179+#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
180+#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
181+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
182+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
183+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
184+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
185+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
186+#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
187+#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
188+#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
189+#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
190+ _MG_CLKTOP2_HSCLKCTL_PORT1, \
191+ _MG_CLKTOP2_HSCLKCTL_PORT2)
192+
193+#define _MG_PLL_DIV0_PORT1 0x168A00
194+#define _MG_PLL_DIV0_PORT2 0x169A00
195+#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
196+#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
197+#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
198+#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
199+#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
200+#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
201+#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
202+ _MG_PLL_DIV0_PORT2)
203+
204+#define _MG_PLL_DIV1_PORT1 0x168A04
205+#define _MG_PLL_DIV1_PORT2 0x169A04
206+#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
207+#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
208+#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
209+#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
210+#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
211+#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
212+#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
213+#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
214+#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
215+ _MG_PLL_DIV1_PORT2)
216+
217+#define _MG_PLL_LF_PORT1 0x168A08
218+#define _MG_PLL_LF_PORT2 0x169A08
219+#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
220+#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
221+#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
222+#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
223+#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
224+#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
225+#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
226+ _MG_PLL_LF_PORT2)
227+
228+#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
229+#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
230+#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
231+#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
232+#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
233+#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
234+#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
235+#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
236+#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
237+ _MG_PLL_FRAC_LOCK_PORT1, \
238+ _MG_PLL_FRAC_LOCK_PORT2)
239+
240+#define _MG_PLL_SSC_PORT1 0x168A10
241+#define _MG_PLL_SSC_PORT2 0x169A10
242+#define MG_PLL_SSC_EN (1 << 28)
243+#define MG_PLL_SSC_TYPE(x) ((x) << 26)
244+#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
245+#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
246+#define MG_PLL_SSC_FLLEN (1 << 9)
247+#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
248+#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
249+ _MG_PLL_SSC_PORT2)
250+
251+#define _MG_PLL_BIAS_PORT1 0x168A14
252+#define _MG_PLL_BIAS_PORT2 0x169A14
253+#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
254+#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
255+#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
256+#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
257+#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
258+#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
259+#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
260+#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
261+#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
262+#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
263+#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
264+#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
265+#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
266+#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
267+ _MG_PLL_BIAS_PORT2)
268+
269+#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
270+#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
271+#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
272+#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
273+#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
274+#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
275+#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
276+#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
277+ _MG_PLL_TDC_COLDST_BIAS_PORT1, \
278+ _MG_PLL_TDC_COLDST_BIAS_PORT2)
279+
280+#endif /* __INTEL_TC_PHY_REGS__ */
drivers/gpu/drm/i915/display/intel_vbt_defs.h+0−26
@@ -226,32 +226,6 @@ struct bdb_general_features { · 225 unmodified lines
226226 #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1)
227227 #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0)
228228
229−/*
230− * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the
231− * system, the other bits may or may not be set for eDP outputs.
232− */
233−#define DEVICE_TYPE_eDP_BITS \
234− (DEVICE_TYPE_INTERNAL_CONNECTOR | \
235− DEVICE_TYPE_MIPI_OUTPUT | \
236− DEVICE_TYPE_COMPOSITE_OUTPUT | \
237− DEVICE_TYPE_DUAL_CHANNEL | \
238− DEVICE_TYPE_LVDS_SIGNALING | \
239− DEVICE_TYPE_TMDS_DVI_SIGNALING | \
240− DEVICE_TYPE_VIDEO_SIGNALING | \
241− DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
242− DEVICE_TYPE_ANALOG_OUTPUT)
243−
244−#define DEVICE_TYPE_DP_DUAL_MODE_BITS \
245− (DEVICE_TYPE_INTERNAL_CONNECTOR | \
246− DEVICE_TYPE_MIPI_OUTPUT | \
247− DEVICE_TYPE_COMPOSITE_OUTPUT | \
248− DEVICE_TYPE_LVDS_SIGNALING | \
249− DEVICE_TYPE_TMDS_DVI_SIGNALING | \
250− DEVICE_TYPE_VIDEO_SIGNALING | \
251− DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
252− DEVICE_TYPE_DIGITAL_OUTPUT | \
253− DEVICE_TYPE_ANALOG_OUTPUT)
254−
255229 #define DEVICE_CFG_NONE 0x00
256230 #define DEVICE_CFG_12BIT_DVOB 0x01
257231 #define DEVICE_CFG_12BIT_DVOC 0x02
drivers/gpu/drm/i915/display/intel_vdsc.c+1−6
@@ -341,19 +341,14 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) · 340 unmodified lines
341341 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
342342 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
343343 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
344− enum pipe pipe = crtc->pipe;
345344
346345 if (!INTEL_INFO(i915)->display.has_dsc)
347346 return false;
348347
349− /* On TGL, DSC is supported on all Pipes */
350348 if (DISPLAY_VER(i915) >= 12)
351349 return true;
352350
353− if (DISPLAY_VER(i915) >= 11 &&
354− (pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP ||
355− cpu_transcoder == TRANSCODER_DSI_0 ||
356− cpu_transcoder == TRANSCODER_DSI_1))
351+ if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A)
357352 return true;
358353
359354 return false;
drivers/gpu/drm/i915/display/intel_vga.c+5−4
@@ -7,6 +7,7 @@ · 6 unmodified lines
77 #include <linux/vgaarb.h>
88
99 #include <drm/i915_drm.h>
10+#include <video/vga.h>
1011
1112 #include "i915_drv.h"
1213 #include "intel_de.h"
@@ -34,9 +35,9 @@ void intel_vga_disable(struct drm_i915_private *dev_priv) · 21 unmodified lines
3435
3536 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
3637 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
37− outb(SR01, VGA_SR_INDEX);
38− sr1 = inb(VGA_SR_DATA);
39− outb(sr1 | 1 << 5, VGA_SR_DATA);
38+ outb(0x01, VGA_SEQ_I);
39+ sr1 = inb(VGA_SEQ_D);
40+ outb(sr1 | VGA_SR01_SCREEN_OFF, VGA_SEQ_D);
4041 vga_put(pdev, VGA_RSRC_LEGACY_IO);
4142 udelay(300);
4243
@@ -92,7 +93,7 @@ void intel_vga_reset_io_mem(struct drm_i915_private *i915) · 49 unmodified lines
9293 * and error messages.
9394 */
9495 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
95− outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
96+ outb(inb(VGA_MIS_R), VGA_MIS_W);
9697 vga_put(pdev, VGA_RSRC_LEGACY_IO);
9798 }
9899
drivers/gpu/drm/i915/display/skl_universal_plane.c+107−88
@@ -961,6 +961,7 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, · 960 unmodified lines
961961 static u32 skl_surf_address(const struct intel_plane_state *plane_state,
962962 int color_plane)
963963 {
964+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
964965 const struct drm_framebuffer *fb = plane_state->hw.fb;
965966 u32 offset = plane_state->view.color_plane[color_plane].offset;
966967
@@ -969,11 +970,11 @@ static u32 skl_surf_address(const struct intel_plane_state *plane_state, · 2 unmodified lines
969970 * The DPT object contains only one vma, so the VMA's offset
970971 * within the DPT is always 0.
971972 */
972− WARN_ON(plane_state->dpt_vma->node.start);
973− WARN_ON(offset & 0x1fffff);
973+ drm_WARN_ON(&i915->drm, plane_state->dpt_vma->node.start);
974+ drm_WARN_ON(&i915->drm, offset & 0x1fffff);
974975 return offset >> 9;
975976 } else {
976− WARN_ON(offset & 0xfff);
977+ drm_WARN_ON(&i915->drm, offset & 0xfff);
977978 return offset;
978979 }
979980 }
@@ -992,6 +993,54 @@ static u32 skl_plane_surf(const struct intel_plane_state *plane_state, · 12 unmodified lines
992993 return plane_surf;
993994 }
994995
996+static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
997+ int color_plane)
998+{
999+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1000+ const struct drm_framebuffer *fb = plane_state->hw.fb;
1001+ int aux_plane = skl_main_to_aux_plane(fb, color_plane);
1002+ u32 aux_dist;
1003+
1004+ if (!aux_plane)
1005+ return 0;
1006+
1007+ aux_dist = skl_surf_address(plane_state, aux_plane) -
1008+ skl_surf_address(plane_state, color_plane);
1009+
1010+ if (DISPLAY_VER(i915) < 12)
1011+ aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
1012+
1013+ return aux_dist;
1014+}
1015+
1016+static u32 skl_plane_keyval(const struct intel_plane_state *plane_state)
1017+{
1018+ const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1019+
1020+ return key->min_value;
1021+}
1022+
1023+static u32 skl_plane_keymax(const struct intel_plane_state *plane_state)
1024+{
1025+ const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1026+ u8 alpha = plane_state->hw.alpha >> 8;
1027+
1028+ return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
1029+}
1030+
1031+static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)
1032+{
1033+ const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1034+ u8 alpha = plane_state->hw.alpha >> 8;
1035+ u32 keymsk;
1036+
1037+ keymsk = key->channel_mask & 0x7ffffff;
1038+ if (alpha < 0xff)
1039+ keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
1040+
1041+ return keymsk;
1042+}
1043+
9951044 static void icl_plane_csc_load_black(struct intel_plane *plane)
9961045 {
9971046 struct drm_i915_private *i915 = to_i915(plane->base.dev);
@@ -1016,15 +1065,24 @@ static void icl_plane_csc_load_black(struct intel_plane *plane) · 18 unmodified lines
10161065 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
10171066 }
10181067
1068+static int skl_plane_color_plane(const struct intel_plane_state *plane_state)
1069+{
1070+ /* Program the UV plane on planar master */
1071+ if (plane_state->planar_linked_plane && !plane_state->planar_slave)
1072+ return 1;
1073+ else
1074+ return 0;
1075+}
1076+
10191077 static void
1020−skl_program_plane_noarm(struct intel_plane *plane,
1021− const struct intel_crtc_state *crtc_state,
1022− const struct intel_plane_state *plane_state,
1023− int color_plane)
1078+skl_plane_update_noarm(struct intel_plane *plane,
1079+ const struct intel_crtc_state *crtc_state,
1080+ const struct intel_plane_state *plane_state)
10241081 {
10251082 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10261083 enum plane_id plane_id = plane->id;
10271084 enum pipe pipe = plane->pipe;
1085+ int color_plane = skl_plane_color_plane(plane_state);
10281086 u32 stride = skl_plane_stride(plane_state, color_plane);
10291087 const struct drm_framebuffer *fb = plane_state->hw.fb;
10301088 int crtc_x = plane_state->uapi.dst.x1;
@@ -1048,11 +1106,12 @@ skl_program_plane_noarm(struct intel_plane *plane, · 17 unmodified lines
10481106 if (plane_state->force_black)
10491107 icl_plane_csc_load_black(plane);
10501108
1051− intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);
1109+ intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
1110+ PLANE_STRIDE_(stride));
10521111 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
1053− (crtc_y << 16) | crtc_x);
1112+ PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
10541113 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
1055− ((src_h - 1) << 16) | (src_w - 1));
1114+ PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
10561115
10571116 if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
10581117 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
@@ -1076,21 +1135,17 @@ skl_program_plane_noarm(struct intel_plane *plane, · 17 unmodified lines
10761135 }
10771136
10781137 static void
1079−skl_program_plane_arm(struct intel_plane *plane,
1080− const struct intel_crtc_state *crtc_state,
1081− const struct intel_plane_state *plane_state,
1082− int color_plane)
1138+skl_plane_update_arm(struct intel_plane *plane,
1139+ const struct intel_crtc_state *crtc_state,
1140+ const struct intel_plane_state *plane_state)
10831141 {
10841142 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10851143 enum plane_id plane_id = plane->id;
10861144 enum pipe pipe = plane->pipe;
1087− const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1088− const struct drm_framebuffer *fb = plane_state->hw.fb;
1089− int aux_plane = skl_main_to_aux_plane(fb, color_plane);
1145+ int color_plane = skl_plane_color_plane(plane_state);
10901146 u32 x = plane_state->view.color_plane[color_plane].x;
10911147 u32 y = plane_state->view.color_plane[color_plane].y;
1092− u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
1093− u8 alpha = plane_state->hw.alpha >> 8;
1148+ u32 plane_color_ctl = 0;
10941149 u32 plane_ctl = plane_state->ctl;
10951150 unsigned long irqflags;
10961151
@@ -1100,36 +1155,22 @@ skl_program_plane_arm(struct intel_plane *plane, · 3 unmodified lines
11001155 plane_color_ctl = plane_state->color_ctl |
11011156 glk_plane_color_ctl_crtc(crtc_state);
11021157
1103− keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
1104−
1105− keymsk = key->channel_mask & 0x7ffffff;
1106− if (alpha < 0xff)
1107− keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
1108−
1109− if (aux_plane) {
1110− aux_dist = skl_surf_address(plane_state, aux_plane) -
1111− skl_surf_address(plane_state, color_plane);
1112−
1113− if (DISPLAY_VER(dev_priv) < 12)
1114− aux_dist |= skl_plane_stride(plane_state, aux_plane);
1115− }
1116−
11171158 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11181159
1119− intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
1120− key->min_value);
1121− intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
1122− intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
1160+ intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
1161+ intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
1162+ intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
11231163
11241164 intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
1125− (y << 16) | x);
1165+ PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
11261166
1127− intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
1167+ intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
1168+ skl_plane_aux_dist(plane_state, color_plane));
11281169
11291170 if (DISPLAY_VER(dev_priv) < 11)
11301171 intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
1131− (plane_state->view.color_plane[1].y << 16) |
1132− plane_state->view.color_plane[1].x);
1172+ PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
1173+ PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
11331174
11341175 if (DISPLAY_VER(dev_priv) >= 10)
11351176 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
@@ -1182,34 +1223,6 @@ skl_plane_async_flip(struct intel_plane *plane, · 46 unmodified lines
11821223 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11831224 }
11841225
1185−static void
1186−skl_plane_update_noarm(struct intel_plane *plane,
1187− const struct intel_crtc_state *crtc_state,
1188− const struct intel_plane_state *plane_state)
1189−{
1190− int color_plane = 0;
1191−
1192− if (plane_state->planar_linked_plane && !plane_state->planar_slave)
1193− /* Program the UV plane on planar master */
1194− color_plane = 1;
1195−
1196− skl_program_plane_noarm(plane, crtc_state, plane_state, color_plane);
1197−}
1198−
1199−static void
1200−skl_plane_update_arm(struct intel_plane *plane,
1201− const struct intel_crtc_state *crtc_state,
1202− const struct intel_plane_state *plane_state)
1203−{
1204− int color_plane = 0;
1205−
1206− if (plane_state->planar_linked_plane && !plane_state->planar_slave)
1207− /* Program the UV plane on planar master */
1208− color_plane = 1;
1209−
1210− skl_program_plane_arm(plane, crtc_state, plane_state, color_plane);
1211−}
1212−
12131226 static bool intel_format_is_p01x(u32 format)
12141227 {
12151228 switch (format) {
@@ -1338,6 +1351,7 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s · 122 unmodified lines
13381351
13391352 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
13401353 {
1354+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
13411355 const struct drm_framebuffer *fb = plane_state->hw.fb;
13421356 unsigned int rotation = plane_state->hw.rotation;
13431357 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
@@ -1347,7 +1361,7 @@ static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_s · 3 unmodified lines
13471361 src_w & 3 &&
13481362 (rotation == DRM_MODE_ROTATE_270 ||
13491363 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
1350− DRM_DEBUG_KMS("src width must be multiple of 4 for rotated planar YUV\n");
1364+ drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n");
13511365 return -EINVAL;
13521366 }
13531367
@@ -1816,20 +1830,27 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, · 462 unmodified lines
18161830 return 0;
18171831 }
18181832
1833+static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
1834+{
1835+ return pipe - PIPE_A + INTEL_FBC_A;
1836+}
1837+
18191838 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
1820− enum pipe pipe, enum plane_id plane_id)
1839+ enum intel_fbc_id fbc_id, enum plane_id plane_id)
18211840 {
1822− if (!HAS_FBC(dev_priv))
1841+ if ((INTEL_INFO(dev_priv)->display.fbc_mask & BIT(fbc_id)) == 0)
18231842 return false;
18241843
1825− return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
1844+ return plane_id == PLANE_PRIMARY;
18261845 }
18271846
18281847 static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
18291848 enum pipe pipe, enum plane_id plane_id)
18301849 {
1831− if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
1832− return dev_priv->fbc;
1850+ enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
1851+
1852+ if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id))
1853+ return dev_priv->fbc[fbc_id];
18331854 else
18341855 return NULL;
18351856 }
@@ -2282,16 +2303,17 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, · 446 unmodified lines
22822303 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
22832304
22842305 if (DISPLAY_VER(dev_priv) >= 11)
2285− pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
2306+ pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
22862307 else
2287− pixel_format = val & PLANE_CTL_FORMAT_MASK;
2308+ pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
22882309
22892310 if (DISPLAY_VER(dev_priv) >= 10) {
2290− alpha = intel_de_read(dev_priv,
2291− PLANE_COLOR_CTL(pipe, plane_id));
2292− alpha &= PLANE_COLOR_ALPHA_MASK;
2311+ u32 color_ctl;
2312+
2313+ color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
2314+ alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);
22932315 } else {
2294− alpha = val & PLANE_CTL_ALPHA_MASK;
2316+ alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
22952317 }
22962318
22972319 fourcc = skl_format_to_fourcc(pixel_format,
@@ -2355,22 +2377,19 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, · 57 unmodified lines
23552377 if (drm_rotation_90_or_270(plane_config->rotation))
23562378 goto error;
23572379
2358− base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
2380+ base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;
23592381 plane_config->base = base;
23602382
23612383 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
23622384
23632385 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
2364− fb->height = ((val >> 16) & 0xffff) + 1;
2365− fb->width = ((val >> 0) & 0xffff) + 1;
2386+ fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;
2387+ fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;
23662388
23672389 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
23682390 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
23692391
2370− if (DISPLAY_VER(dev_priv) >= 13)
2371− fb->pitches[0] = (val & PLANE_STRIDE_MASK_XELPD) * stride_mult;
2372− else
2373− fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
2392+ fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult;
23742393
23752394 aligned_height = intel_fb_align_height(fb, 0, fb->height);
23762395
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c+5−3
@@ -74,7 +74,8 @@ static void i915_gem_unmap_dma_buf(struct dma_buf_attachment *attachment, · 73 unmodified lines
7474 kfree(sg);
7575 }
7676
77−static int i915_gem_dmabuf_vmap(struct dma_buf *dma_buf, struct dma_buf_map *map)
77+static int i915_gem_dmabuf_vmap(struct dma_buf *dma_buf,
78+ struct iosys_map *map)
7879 {
7980 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
8081 void *vaddr;
@@ -83,12 +84,13 @@ static int i915_gem_dmabuf_vmap(struct dma_buf *dma_buf, struct dma_buf_map *map · 2 unmodified lines
8384 if (IS_ERR(vaddr))
8485 return PTR_ERR(vaddr);
8586
86− dma_buf_map_set_vaddr(map, vaddr);
87+ iosys_map_set_vaddr(map, vaddr);
8788
8889 return 0;
8990 }
9091
91−static void i915_gem_dmabuf_vunmap(struct dma_buf *dma_buf, struct dma_buf_map *map)
92+static void i915_gem_dmabuf_vunmap(struct dma_buf *dma_buf,
93+ struct iosys_map *map)
9294 {
9395 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
9496
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c+2−0
@@ -23,9 +23,11 @@ · 22 unmodified lines
2323
2424 #include "pxp/intel_pxp.h"
2525
26+#include "i915_cmd_parser.h"
2627 #include "i915_drv.h"
2728 #include "i915_gem_clflush.h"
2829 #include "i915_gem_context.h"
30+#include "i915_gem_evict.h"
2931 #include "i915_gem_ioctls.h"
3032 #include "i915_trace.h"
3133 #include "i915_user_extensions.h"
drivers/gpu/drm/i915/gem/i915_gem_stolen.c+1−0
@@ -14,6 +14,7 @@ · 13 unmodified lines
1414 #include "gem/i915_gem_region.h"
1515 #include "i915_drv.h"
1616 #include "i915_gem_stolen.h"
17+#include "i915_reg.h"
1718 #include "i915_vgpu.h"
1819
1920 /*
drivers/gpu/drm/i915/gem/i915_gem_tiling.c+2−0
@@ -12,6 +12,8 @@ · 11 unmodified lines
1212 #include "i915_gem_ioctls.h"
1313 #include "i915_gem_mman.h"
1414 #include "i915_gem_object.h"
15+#include "i915_gem_tiling.h"
16+#include "i915_reg.h"
1517
1618 /**
1719 * DOC: buffer object tiling
drivers/gpu/drm/i915/gem/i915_gem_tiling.h+18−0
@@ -0,0 +1,18 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2022 Intel Corporation
4+ */
5+
6+#ifndef __I915_GEM_TILING_H__
7+#define __I915_GEM_TILING_H__
8+
9+#include <linux/types.h>
10+
11+struct drm_i915_private;
12+
13+u32 i915_gem_fence_size(struct drm_i915_private *i915, u32 size,
14+ unsigned int tiling, unsigned int stride);
15+u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
16+ unsigned int tiling, unsigned int stride);
17+
18+#endif /* __I915_GEM_TILING_H__ */
drivers/gpu/drm/i915/gem/i915_gem_userptr.c+1−0
@@ -42,6 +42,7 @@ · 41 unmodified lines
4242 #include "i915_drv.h"
4343 #include "i915_gem_ioctls.h"
4444 #include "i915_gem_object.h"
45+#include "i915_gem_userptr.h"
4546 #include "i915_scatterlist.h"
4647
4748 #ifdef CONFIG_MMU_NOTIFIER
drivers/gpu/drm/i915/gem/i915_gem_userptr.h+14−0
@@ -0,0 +1,14 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2021 Intel Corporation
4+ */
5+
6+#ifndef __I915_GEM_USERPTR_H__
7+#define __I915_GEM_USERPTR_H__
8+
9+struct drm_i915_private;
10+
11+int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
12+void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
13+
14+#endif /* __I915_GEM_USERPTR_H__ */
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c+2−1
@@ -7,8 +7,9 @@ · 6 unmodified lines
77
88 #include "gt/intel_context.h"
99 #include "gt/intel_engine_user.h"
10−#include "gt/intel_gt.h"
1110 #include "gt/intel_gpu_commands.h"
11+#include "gt/intel_gt.h"
12+#include "gt/intel_gt_regs.h"
1213 #include "gem/i915_gem_lmem.h"
1314
1415 #include "selftests/igt_flush_test.h"
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c+2−1
@@ -8,6 +8,7 @@ · 7 unmodified lines
88
99 #include "gem/i915_gem_pm.h"
1010 #include "gt/intel_engine_pm.h"
11+#include "gt/intel_engine_regs.h"
1112 #include "gt/intel_gt.h"
1213 #include "gt/intel_gt_requests.h"
1314 #include "gt/intel_reset.h"
@@ -894,7 +895,7 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v · 880 unmodified lines
894895 return PTR_ERR(cmd);
895896
896897 *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
897− *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
898+ *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE));
898899 *cmd++ = lower_32_bits(vma->node.start);
899900 *cmd++ = upper_32_bits(vma->node.start);
900901 *cmd = MI_BATCH_BUFFER_END;
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c+3−3
@@ -266,7 +266,7 @@ static int igt_dmabuf_import(void *arg) · 265 unmodified lines
266266 struct drm_i915_gem_object *obj;
267267 struct dma_buf *dmabuf;
268268 void *obj_map, *dma_map;
269− struct dma_buf_map map;
269+ struct iosys_map map;
270270 u32 pattern[] = { 0, 0xaa, 0xcc, 0x55, 0xff };
271271 int err, i;
272272
@@ -349,7 +349,7 @@ static int igt_dmabuf_import_ownership(void *arg) · 76 unmodified lines
349349 struct drm_i915_private *i915 = arg;
350350 struct drm_i915_gem_object *obj;
351351 struct dma_buf *dmabuf;
352− struct dma_buf_map map;
352+ struct iosys_map map;
353353 void *ptr;
354354 int err;
355355
@@ -400,7 +400,7 @@ static int igt_dmabuf_export_vmap(void *arg) · 44 unmodified lines
400400 struct drm_i915_private *i915 = arg;
401401 struct drm_i915_gem_object *obj;
402402 struct dma_buf *dmabuf;
403− struct dma_buf_map map;
403+ struct iosys_map map;
404404 void *ptr;
405405 int err;
406406
drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c+3−3
@@ -61,7 +61,7 @@ static void mock_dmabuf_release(struct dma_buf *dma_buf) · 60 unmodified lines
6161 kfree(mock);
6262 }
6363
64−static int mock_dmabuf_vmap(struct dma_buf *dma_buf, struct dma_buf_map *map)
64+static int mock_dmabuf_vmap(struct dma_buf *dma_buf, struct iosys_map *map)
6565 {
6666 struct mock_dmabuf *mock = to_mock(dma_buf);
6767 void *vaddr;
@@ -69,12 +69,12 @@ static int mock_dmabuf_vmap(struct dma_buf *dma_buf, struct dma_buf_map *map) · 1 unmodified line
6969 vaddr = vm_map_ram(mock->pages, mock->npages, 0);
7070 if (!vaddr)
7171 return -ENOMEM;
72− dma_buf_map_set_vaddr(map, vaddr);
72+ iosys_map_set_vaddr(map, vaddr);
7373
7474 return 0;
7575 }
7676
77−static void mock_dmabuf_vunmap(struct dma_buf *dma_buf, struct dma_buf_map *map)
77+static void mock_dmabuf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map)
7878 {
7979 struct mock_dmabuf *mock = to_mock(dma_buf);
8080
drivers/gpu/drm/i915/gt/gen2_engine_cs.c+2−0
@@ -5,7 +5,9 @@ · 4 unmodified lines
55
66 #include "gen2_engine_cs.h"
77 #include "i915_drv.h"
8+#include "i915_reg.h"
89 #include "intel_engine.h"
10+#include "intel_engine_regs.h"
911 #include "intel_gpu_commands.h"
1012 #include "intel_gt.h"
1113 #include "intel_gt_irq.h"
drivers/gpu/drm/i915/gt/gen6_engine_cs.c+1−0
@@ -5,6 +5,7 @@ · 4 unmodified lines
55
66 #include "gen6_engine_cs.h"
77 #include "intel_engine.h"
8+#include "intel_engine_regs.h"
89 #include "intel_gpu_commands.h"
910 #include "intel_gt.h"
1011 #include "intel_gt_irq.h"
drivers/gpu/drm/i915/gt/gen6_ppgtt.c+2−0
@@ -9,6 +9,8 @@ · 8 unmodified lines
99 #include "i915_scatterlist.h"
1010 #include "i915_trace.h"
1111 #include "i915_vgpu.h"
12+#include "intel_gt_regs.h"
13+#include "intel_engine_regs.h"
1214 #include "intel_gt.h"
1315
1416 /* Write pde (index) from the page directory @pd to the page table @pt */
drivers/gpu/drm/i915/gt/gen7_renderclear.c+1−0
@@ -6,6 +6,7 @@ · 5 unmodified lines
66 #include "gen7_renderclear.h"
77 #include "i915_drv.h"
88 #include "intel_gpu_commands.h"
9+#include "intel_gt_regs.h"
910
1011 #define GT3_INLINE_DATA_DELAYS 0x1E00
1112 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
drivers/gpu/drm/i915/gt/gen8_engine_cs.c+2−1
@@ -5,8 +5,9 @@ · 4 unmodified lines
55
66 #include "gen8_engine_cs.h"
77 #include "i915_drv.h"
8−#include "intel_lrc.h"
98 #include "intel_gpu_commands.h"
9+#include "intel_gt_regs.h"
10+#include "intel_lrc.h"
1011 #include "intel_ring.h"
1112
1213 int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
drivers/gpu/drm/i915/gt/intel_engine.h+0−1
@@ -11,7 +11,6 @@ · 10 unmodified lines
1111 #include <linux/seqlock.h>
1212
1313 #include "i915_pmu.h"
14−#include "i915_reg.h"
1514 #include "i915_request.h"
1615 #include "i915_selftest.h"
1716 #include "intel_engine_types.h"
drivers/gpu/drm/i915/gt/intel_engine_cs.c+3−1
@@ -6,13 +6,15 @@ · 5 unmodified lines
66 #include <drm/drm_print.h>
77
88 #include "gem/i915_gem_context.h"
9+#include "gt/intel_gt_regs.h"
910
11+#include "i915_cmd_parser.h"
1012 #include "i915_drv.h"
11−
1213 #include "intel_breadcrumbs.h"
1314 #include "intel_context.h"
1415 #include "intel_engine.h"
1516 #include "intel_engine_pm.h"
17+#include "intel_engine_regs.h"
1618 #include "intel_engine_user.h"
1719 #include "intel_execlists_submission.h"
1820 #include "intel_gt.h"
drivers/gpu/drm/i915/gt/intel_engine_regs.h+223−0
@@ -0,0 +1,223 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2022 Intel Corporation
4+ */
5+
6+#ifndef __INTEL_ENGINE_REGS__
7+#define __INTEL_ENGINE_REGS__
8+
9+#include "i915_reg_defs.h"
10+
11+#define RING_TAIL(base) _MMIO((base) + 0x30)
12+#define TAIL_ADDR 0x001FFFF8
13+#define RING_HEAD(base) _MMIO((base) + 0x34)
14+#define HEAD_WRAP_COUNT 0xFFE00000
15+#define HEAD_WRAP_ONE 0x00200000
16+#define HEAD_ADDR 0x001FFFFC
17+#define RING_START(base) _MMIO((base) + 0x38)
18+#define RING_CTL(base) _MMIO((base) + 0x3c)
19+#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
20+#define RING_NR_PAGES 0x001FF000
21+#define RING_REPORT_MASK 0x00000006
22+#define RING_REPORT_64K 0x00000002
23+#define RING_REPORT_128K 0x00000004
24+#define RING_NO_REPORT 0x00000000
25+#define RING_VALID_MASK 0x00000001
26+#define RING_VALID 0x00000001
27+#define RING_INVALID 0x00000000
28+#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
29+#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
30+#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
31+#define RING_SYNC_0(base) _MMIO((base) + 0x40)
32+#define RING_SYNC_1(base) _MMIO((base) + 0x44)
33+#define RING_SYNC_2(base) _MMIO((base) + 0x48)
34+#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
35+#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
36+#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
37+#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
38+#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
39+#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
40+#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
41+#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
42+#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
43+#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
44+#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
45+#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
46+#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
47+#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
48+#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
49+#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
50+#define GEN6_BSD_GO_INDICATOR REG_BIT(4)
51+#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
52+#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
53+#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
54+#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
55+#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)
56+#define IDLE_TIME_MASK 0xFFFFF
57+#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
58+#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
59+#define RING_IPEIR(base) _MMIO((base) + 0x64)
60+#define RING_IPEHR(base) _MMIO((base) + 0x68)
61+#define RING_INSTDONE(base) _MMIO((base) + 0x6c)
62+#define RING_INSTPS(base) _MMIO((base) + 0x70)
63+#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
64+#define RING_ACTHD(base) _MMIO((base) + 0x74)
65+#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
66+#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
67+#define IPEIR(base) _MMIO((base) + 0x88)
68+#define IPEHR(base) _MMIO((base) + 0x8c)
69+#define RING_ID(base) _MMIO((base) + 0x8c)
70+#define RING_NOPID(base) _MMIO((base) + 0x94)
71+#define RING_HWSTAM(base) _MMIO((base) + 0x98)
72+#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
73+#define RING_IMR(base) _MMIO((base) + 0xa8)
74+#define RING_EIR(base) _MMIO((base) + 0xb0)
75+#define RING_EMR(base) _MMIO((base) + 0xb4)
76+#define RING_ESR(base) _MMIO((base) + 0xb8)
77+#define RING_INSTPM(base) _MMIO((base) + 0xc0)
78+#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)
79+#define ACTHD(base) _MMIO((base) + 0xc8)
80+#define GEN8_R_PWR_CLK_STATE(base) _MMIO((base) + 0xc8)
81+#define GEN8_RPCS_ENABLE (1 << 31)
82+#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
83+#define GEN8_RPCS_S_CNT_SHIFT 15
84+#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
85+#define GEN11_RPCS_S_CNT_SHIFT 12
86+#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
87+#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
88+#define GEN8_RPCS_SS_CNT_SHIFT 8
89+#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
90+#define GEN8_RPCS_EU_MAX_SHIFT 4
91+#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
92+#define GEN8_RPCS_EU_MIN_SHIFT 0
93+#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
94+
95+#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
96+#define RESET_CTL_CAT_ERROR REG_BIT(2)
97+#define RESET_CTL_READY_TO_RESET REG_BIT(1)
98+#define RESET_CTL_REQUEST_RESET REG_BIT(0)
99+#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
100+#define RING_BBSTATE(base) _MMIO((base) + 0x110)
101+#define RING_BB_PPGTT (1 << 5)
102+#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
103+#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
104+#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
105+#define RING_BBADDR(base) _MMIO((base) + 0x140)
106+#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
107+#define CCID(base) _MMIO((base) + 0x180)
108+#define CCID_EN BIT(0)
109+#define CCID_EXTENDED_STATE_RESTORE BIT(2)
110+#define CCID_EXTENDED_STATE_SAVE BIT(3)
111+#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
112+#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
113+#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
114+#define ECOSKPD(base) _MMIO((base) + 0x1d0)
115+#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
116+#define ECO_GATING_CX_ONLY REG_BIT(3)
117+#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
118+#define ECO_FLIP_DONE REG_BIT(0)
119+#define GEN6_BLITTER_LOCK_SHIFT 16
120+
121+#define BLIT_CCTL(base) _MMIO((base) + 0x204)
122+#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
123+#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
124+#define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
125+ BLIT_CCTL_SRC_MOCS_MASK)
126+#define BLIT_CCTL_MOCS(dst, src) \
127+ (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
128+ REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
129+
130+/*
131+ * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
132+ * The lsb of each can be considered a separate enabling bit for encryption.
133+ * 6:0 == default MOCS value for reads => 6:1 == table index for reads.
134+ * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
135+ * 15:14 == Reserved => 31:30 are set to 0.
136+ */
137+#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
138+#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
139+#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
140+ CMD_CCTL_READ_OVERRIDE_MASK)
141+#define CMD_CCTL_MOCS_OVERRIDE(write, read) \
142+ (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
143+ REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
144+
145+#define MI_PREDICATE_RESULT_2(base) _MMIO((base) + 0x3bc)
146+#define LOWER_SLICE_ENABLED (1 << 0)
147+#define LOWER_SLICE_DISABLED (0 << 0)
148+#define MI_PREDICATE_SRC0(base) _MMIO((base) + 0x400)
149+#define MI_PREDICATE_SRC0_UDW(base) _MMIO((base) + 0x400 + 4)
150+#define MI_PREDICATE_SRC1(base) _MMIO((base) + 0x408)
151+#define MI_PREDICATE_SRC1_UDW(base) _MMIO((base) + 0x408 + 4)
152+#define MI_PREDICATE_DATA(base) _MMIO((base) + 0x410)
153+#define MI_PREDICATE_RESULT(base) _MMIO((base) + 0x418)
154+#define MI_PREDICATE_RESULT_1(base) _MMIO((base) + 0x41c)
155+
156+#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
157+#define PP_DIR_DCLV_2G 0xffffffff
158+#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
159+#define RING_ELSP(base) _MMIO((base) + 0x230)
160+#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
161+#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
162+#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
163+#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
164+#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)
165+#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2)
166+#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
167+#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)
168+#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
169+#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
170+#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
171+#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
172+#define GFX_RUN_LIST_ENABLE (1 << 15)
173+#define GFX_INTERRUPT_STEERING (1 << 14)
174+#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
175+#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
176+#define GFX_REPLAY_MODE (1 << 11)
177+#define GFX_PSMI_GRANULARITY (1 << 10)
178+#define GFX_PPGTT_ENABLE (1 << 9)
179+#define GEN8_GFX_PPGTT_48B (1 << 7)
180+#define GFX_FORWARD_VBLANK_MASK (3 << 5)
181+#define GFX_FORWARD_VBLANK_NEVER (0 << 5)
182+#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
183+#define GFX_FORWARD_VBLANK_COND (2 << 5)
184+#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
185+#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
186+#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
187+#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
188+#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
189+#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
190+#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
191+#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
192+#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
193+#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
194+#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
195+#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
196+#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
197+#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
198+#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
199+#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
200+#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
201+#define RING_FORCE_TO_NONPRIV_MASK_VALID \
202+ (RING_FORCE_TO_NONPRIV_RANGE_MASK | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
203+#define RING_MAX_NONPRIV_SLOTS 12
204+
205+#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
206+#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
207+#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
208+#define EL_CTRL_LOAD REG_BIT(0)
209+
210+/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
211+#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
212+#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
213+
214+#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
215+
216+#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
217+#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
218+
219+#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
220+#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
221+
222+
223+#endif /* __INTEL_ENGINE_REGS__ */
drivers/gpu/drm/i915/gt/intel_execlists_submission.c+2−0
@@ -116,11 +116,13 @@ · 115 unmodified lines
116116 #include "intel_context.h"
117117 #include "intel_engine_heartbeat.h"
118118 #include "intel_engine_pm.h"
119+#include "intel_engine_regs.h"
119120 #include "intel_engine_stats.h"
120121 #include "intel_execlists_submission.h"
121122 #include "intel_gt.h"
122123 #include "intel_gt_irq.h"
123124 #include "intel_gt_pm.h"
125+#include "intel_gt_regs.h"
124126 #include "intel_gt_requests.h"
125127 #include "intel_lrc.h"
126128 #include "intel_lrc_reg.h"
drivers/gpu/drm/i915/gt/intel_ggtt.c+1−0
@@ -15,6 +15,7 @@ · 14 unmodified lines
1515 #include "gem/i915_gem_lmem.h"
1616
1717 #include "intel_gt.h"
18+#include "intel_gt_regs.h"
1819 #include "i915_drv.h"
1920 #include "i915_scatterlist.h"
2021 #include "i915_vgpu.h"
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c+2−0
@@ -4,9 +4,11 @@ · 3 unmodified lines
44 */
55
66 #include "i915_drv.h"
7+#include "i915_reg.h"
78 #include "i915_scatterlist.h"
89 #include "i915_pvinfo.h"
910 #include "i915_vgpu.h"
11+#include "intel_gt_regs.h"
1012
1113 /**
1214 * DOC: fence register handling
drivers/gpu/drm/i915/gt/intel_gt.c+3−1
@@ -10,10 +10,12 @@ · 9 unmodified lines
1010 #include "gem/i915_gem_lmem.h"
1111 #include "i915_drv.h"
1212 #include "intel_context.h"
13+#include "intel_engine_regs.h"
1314 #include "intel_gt.h"
1415 #include "intel_gt_buffer_pool.h"
1516 #include "intel_gt_clock_utils.h"
1617 #include "intel_gt_pm.h"
18+#include "intel_gt_regs.h"
1719 #include "intel_gt_requests.h"
1820 #include "intel_migrate.h"
1921 #include "intel_mocs.h"
@@ -207,7 +209,7 @@ int intel_gt_init_hw(struct intel_gt *gt) · 187 unmodified lines
207209
208210 if (IS_HASWELL(i915))
209211 intel_uncore_write(uncore,
210− MI_PREDICATE_RESULT_2,
212+ HSW_MI_PREDICATE_RESULT_2,
211213 IS_HSW_GT3(i915) ?
212214 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
213215
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c+2−0
@@ -4,8 +4,10 @@ · 3 unmodified lines
44 */
55
66 #include "i915_drv.h"
7+#include "i915_reg.h"
78 #include "intel_gt.h"
89 #include "intel_gt_clock_utils.h"
10+#include "intel_gt_regs.h"
911
1012 static u32 read_reference_ts_freq(struct intel_uncore *uncore)
1113 {
drivers/gpu/drm/i915/gt/intel_gt_irq.c+1−1
@@ -10,7 +10,7 @@ · 9 unmodified lines
1010 #include "intel_breadcrumbs.h"
1111 #include "intel_gt.h"
1212 #include "intel_gt_irq.h"
13−#include "intel_lrc_reg.h"
13+#include "intel_gt_regs.h"
1414 #include "intel_uncore.h"
1515 #include "intel_rps.h"
1616 #include "pxp/intel_pxp_irq.h"
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c+5−5
@@ -7,11 +7,13 @@ · 6 unmodified lines
77 #include <linux/seq_file.h>
88
99 #include "i915_drv.h"
10+#include "i915_reg.h"
1011 #include "intel_gt.h"
1112 #include "intel_gt_clock_utils.h"
1213 #include "intel_gt_debugfs.h"
1314 #include "intel_gt_pm.h"
1415 #include "intel_gt_pm_debugfs.h"
16+#include "intel_gt_regs.h"
1517 #include "intel_llc.h"
1618 #include "intel_pcode.h"
1719 #include "intel_rc6.h"
@@ -134,8 +136,7 @@ static int gen6_drpc(struct seq_file *m) · 116 unmodified lines
134136 }
135137
136138 if (GRAPHICS_VER(i915) <= 7)
137− sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
138− &rc6vids, NULL);
139+ snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
139140
140141 seq_printf(m, "RC1e Enabled: %s\n",
141142 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
@@ -557,9 +558,8 @@ static int llc_show(struct seq_file *m, void *data) · 415 unmodified lines
557558 wakeref = intel_runtime_pm_get(gt->uncore->rpm);
558559 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
559560 ia_freq = gpu_freq;
560− sandybridge_pcode_read(i915,
561− GEN6_PCODE_READ_MIN_FREQ_TABLE,
562− &ia_freq, NULL);
561+ snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
562+ &ia_freq, NULL);
563563 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
564564 intel_gpu_freq(rps,
565565 (gpu_freq *
drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c+1−0
@@ -8,6 +8,7 @@ · 7 unmodified lines
88 #include "intel_gt.h"
99 #include "intel_gt_irq.h"
1010 #include "intel_gt_pm_irq.h"
11+#include "intel_gt_regs.h"
1112
1213 static void write_pm_imr(struct intel_gt *gt)
1314 {
drivers/gpu/drm/i915/gt/intel_gt_regs.h+1554−0
@@ -0,0 +1,1554 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2022 Intel Corporation
4+ */
5+
6+#ifndef __INTEL_GT_REGS__
7+#define __INTEL_GT_REGS__
8+
9+#include "i915_reg_defs.h"
10+
11+#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
12+#define ILK_GRDOM_FULL (0 << 1)
13+#define ILK_GRDOM_RENDER (1 << 1)
14+#define ILK_GRDOM_MEDIA (3 << 1)
15+#define ILK_GRDOM_MASK (3 << 1)
16+#define ILK_GRDOM_RESET_ENABLE (1 << 0)
17+
18+#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
19+#define GEN6_MBC_SNPCR_SHIFT 21
20+#define GEN6_MBC_SNPCR_MASK (3 << 21)
21+#define GEN6_MBC_SNPCR_MAX (0 << 21)
22+#define GEN6_MBC_SNPCR_MED (1 << 21)
23+#define GEN6_MBC_SNPCR_LOW (2 << 21)
24+#define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */
25+
26+#define VLV_G3DCTL _MMIO(0x9024)
27+#define VLV_GSCKGCTL _MMIO(0x9028)
28+
29+#define FBC_LLC_READ_CTRL _MMIO(0x9044)
30+#define FBC_LLC_FULLY_OPEN REG_BIT(30)
31+
32+#define GEN6_MBCTL _MMIO(0x0907c)
33+#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
34+#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
35+#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
36+#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
37+#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
38+
39+#define GEN6_GDRST _MMIO(0x941c)
40+#define GEN6_GRDOM_FULL (1 << 0)
41+#define GEN6_GRDOM_RENDER (1 << 1)
42+#define GEN6_GRDOM_MEDIA (1 << 2)
43+#define GEN6_GRDOM_BLT (1 << 3)
44+#define GEN6_GRDOM_VECS (1 << 4)
45+#define GEN9_GRDOM_GUC (1 << 5)
46+#define GEN8_GRDOM_MEDIA2 (1 << 7)
47+/* GEN11 changed all bit defs except for FULL & RENDER */
48+#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
49+#define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
50+#define GEN11_GRDOM_BLT (1 << 2)
51+#define GEN11_GRDOM_GUC (1 << 3)
52+#define GEN11_GRDOM_MEDIA (1 << 5)
53+#define GEN11_GRDOM_MEDIA2 (1 << 6)
54+#define GEN11_GRDOM_MEDIA3 (1 << 7)
55+#define GEN11_GRDOM_MEDIA4 (1 << 8)
56+#define GEN11_GRDOM_MEDIA5 (1 << 9)
57+#define GEN11_GRDOM_MEDIA6 (1 << 10)
58+#define GEN11_GRDOM_MEDIA7 (1 << 11)
59+#define GEN11_GRDOM_MEDIA8 (1 << 12)
60+#define GEN11_GRDOM_VECS (1 << 13)
61+#define GEN11_GRDOM_VECS2 (1 << 14)
62+#define GEN11_GRDOM_VECS3 (1 << 15)
63+#define GEN11_GRDOM_VECS4 (1 << 16)
64+#define GEN11_GRDOM_SFC0 (1 << 17)
65+#define GEN11_GRDOM_SFC1 (1 << 18)
66+#define GEN11_GRDOM_SFC2 (1 << 19)
67+#define GEN11_GRDOM_SFC3 (1 << 20)
68+#define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1))
69+#define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance))
70+
71+#define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C)
72+#define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0)
73+#define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890)
74+#define GEN11_VCS_SFC_USAGE_BIT (1 << 0)
75+#define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1)
76+
77+#define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C)
78+#define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0)
79+#define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018)
80+#define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0)
81+#define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
82+#define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
83+
84+#define GEN12_HCP_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x2910)
85+#define GEN12_HCP_SFC_FORCED_LOCK_BIT REG_BIT(0)
86+#define GEN12_HCP_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x2914)
87+#define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1)
88+#define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0)
89+
90+#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
91+
92+#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
93+/* HSW only */
94+#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
95+#define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
96+#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
97+#define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
98+/* HSW+ */
99+#define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
100+#define HSW_RCS_CONTEXT_ENABLE (1 << 7)
101+#define HSW_RCS_INHIBIT (1 << 8)
102+/* Gen8 */
103+#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
104+#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
105+#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
106+#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
107+#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
108+#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
109+#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
110+#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
111+#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
112+#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
113+
114+#define GAM_ECOCHK _MMIO(0x4090)
115+#define BDW_DISABLE_HDC_INVALIDATION (1 << 25)
116+#define ECOCHK_SNB_BIT (1 << 10)
117+#define ECOCHK_DIS_TLB (1 << 8)
118+#define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6)
119+#define ECOCHK_PPGTT_CACHE64B (0x3 << 3)
120+#define ECOCHK_PPGTT_CACHE4B (0x0 << 3)
121+#define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4)
122+#define ECOCHK_PPGTT_LLC_IVB (0x1 << 3)
123+#define ECOCHK_PPGTT_UC_HSW (0x1 << 3)
124+#define ECOCHK_PPGTT_WT_HSW (0x2 << 3)
125+#define ECOCHK_PPGTT_WB_HSW (0x3 << 3)
126+
127+#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
128+
129+#define GAC_ECO_BITS _MMIO(0x14090)
130+#define ECOBITS_SNB_BIT (1 << 13)
131+#define ECOBITS_PPGTT_CACHE64B (3 << 8)
132+#define ECOBITS_PPGTT_CACHE4B (0 << 8)
133+
134+#define GEN12_GAMCNTRL_CTRL _MMIO(0xcf54)
135+#define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
136+#define GLOBAL_INVALIDATION_MODE REG_BIT(2)
137+
138+#define GEN12_GAMSTLB_CTRL _MMIO(0xcf4c)
139+#define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12)
140+#define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11)
141+#define TAG_BLOCK_CLKGATE_DIS REG_BIT(7)
142+
143+#define GEN12_MERT_MOD_CTRL _MMIO(0xcf28)
144+#define RENDER_MOD_CTRL _MMIO(0xcf2c)
145+#define COMP_MOD_CTRL _MMIO(0xcf30)
146+#define VDBX_MOD_CTRL _MMIO(0xcf34)
147+#define VEBX_MOD_CTRL _MMIO(0xcf38)
148+#define FORCE_MISS_FTLB REG_BIT(3)
149+
150+#define GAB_CTL _MMIO(0x24000)
151+#define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
152+
153+#define HSW_MI_PREDICATE_RESULT_2 _MMIO(0x2214)
154+
155+/*
156+ * Registers used only by the command parser
157+ */
158+#define BCS_SWCTRL _MMIO(0x22200)
159+#define BCS_SRC_Y REG_BIT(0)
160+#define BCS_DST_Y REG_BIT(1)
161+
162+#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
163+#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
164+#define HS_INVOCATION_COUNT _MMIO(0x2300)
165+#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
166+#define DS_INVOCATION_COUNT _MMIO(0x2308)
167+#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
168+#define IA_VERTICES_COUNT _MMIO(0x2310)
169+#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
170+#define IA_PRIMITIVES_COUNT _MMIO(0x2318)
171+#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
172+#define VS_INVOCATION_COUNT _MMIO(0x2320)
173+#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
174+#define GS_INVOCATION_COUNT _MMIO(0x2328)
175+#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
176+#define GS_PRIMITIVES_COUNT _MMIO(0x2330)
177+#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
178+#define CL_INVOCATION_COUNT _MMIO(0x2338)
179+#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
180+#define CL_PRIMITIVES_COUNT _MMIO(0x2340)
181+#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
182+#define PS_INVOCATION_COUNT _MMIO(0x2348)
183+#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
184+#define PS_DEPTH_COUNT _MMIO(0x2350)
185+#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
186+
187+/* There are the 4 64-bit counter registers, one for each stream output */
188+#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
189+#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
190+
191+#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
192+#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
193+
194+#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
195+#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
196+#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
197+#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
198+#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
199+#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
200+
201+#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
202+#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
203+#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
204+
205+#define GEN12_SQCM _MMIO(0x8724)
206+#define EN_32B_ACCESS REG_BIT(30)
207+
208+/*
209+ * Flexible, Aggregate EU Counter Registers.
210+ * Note: these aren't contiguous
211+ */
212+#define EU_PERF_CNTL0 _MMIO(0xe458)
213+#define EU_PERF_CNTL1 _MMIO(0xe558)
214+#define EU_PERF_CNTL2 _MMIO(0xe658)
215+#define EU_PERF_CNTL3 _MMIO(0xe758)
216+#define EU_PERF_CNTL4 _MMIO(0xe45c)
217+#define EU_PERF_CNTL5 _MMIO(0xe55c)
218+#define EU_PERF_CNTL6 _MMIO(0xe65c)
219+
220+#define RT_CTRL _MMIO(0xe530)
221+#define DIS_NULL_QUERY REG_BIT(10)
222+
223+/* RPM unit config (Gen8+) */
224+#define RPM_CONFIG0 _MMIO(0x0D00)
225+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
226+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
227+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
228+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
229+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
230+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
231+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
232+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
233+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
234+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
235+#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
236+#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
237+
238+#define RPM_CONFIG1 _MMIO(0x0D04)
239+#define GEN10_GT_NOA_ENABLE (1 << 9)
240+
241+/* GPM unit config (Gen9+) */
242+#define CTC_MODE _MMIO(0xA26C)
243+#define CTC_SOURCE_PARAMETER_MASK 1
244+#define CTC_SOURCE_CRYSTAL_CLOCK 0
245+#define CTC_SOURCE_DIVIDE_LOGIC 1
246+#define CTC_SHIFT_PARAMETER_SHIFT 1
247+#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
248+
249+/* RCP unit config (Gen8+) */
250+#define RCP_CONFIG _MMIO(0x0D08)
251+
252+#define MICRO_BP0_0 _MMIO(0x9800)
253+#define MICRO_BP0_2 _MMIO(0x9804)
254+#define MICRO_BP0_1 _MMIO(0x9808)
255+
256+#define MICRO_BP1_0 _MMIO(0x980C)
257+#define MICRO_BP1_2 _MMIO(0x9810)
258+#define MICRO_BP1_1 _MMIO(0x9814)
259+
260+#define MICRO_BP2_0 _MMIO(0x9818)
261+#define MICRO_BP2_2 _MMIO(0x981C)
262+#define MICRO_BP2_1 _MMIO(0x9820)
263+
264+#define MICRO_BP3_0 _MMIO(0x9824)
265+#define MICRO_BP3_2 _MMIO(0x9828)
266+#define MICRO_BP3_1 _MMIO(0x982C)
267+
268+#define MICRO_BP_TRIGGER _MMIO(0x9830)
269+#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
270+#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
271+#define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
272+
273+#define GAMTARBMODE _MMIO(0x04a08)
274+#define ARB_MODE_BWGTLB_DISABLE (1 << 9)
275+#define ARB_MODE_SWIZZLE_BDW (1 << 1)
276+#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
277+
278+#define _RING_FAULT_REG_RCS 0x4094
279+#define _RING_FAULT_REG_VCS 0x4194
280+#define _RING_FAULT_REG_BCS 0x4294
281+#define _RING_FAULT_REG_VECS 0x4394
282+#define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \
283+ _RING_FAULT_REG_RCS, \
284+ _RING_FAULT_REG_VCS, \
285+ _RING_FAULT_REG_VECS, \
286+ _RING_FAULT_REG_BCS))
287+#define GEN8_RING_FAULT_REG _MMIO(0x4094)
288+#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
289+#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
290+#define RING_FAULT_GTTSEL_MASK (1 << 11)
291+#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
292+#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
293+#define RING_FAULT_VALID (1 << 0)
294+#define DONE_REG _MMIO(0x40b0)
295+#define GEN12_GAM_DONE _MMIO(0xcf68)
296+#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
297+#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
298+#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
299+#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
300+#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
301+#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208)
302+#define GEN12_VD0_AUX_NV _MMIO(0x4218)
303+#define GEN12_VD1_AUX_NV _MMIO(0x4228)
304+#define GEN12_VD2_AUX_NV _MMIO(0x4298)
305+#define GEN12_VD3_AUX_NV _MMIO(0x42A8)
306+#define GEN12_VE0_AUX_NV _MMIO(0x4238)
307+#define GEN12_VE1_AUX_NV _MMIO(0x42B8)
308+#define AUX_INV REG_BIT(0)
309+#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
310+#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
311+
312+#define MISC_STATUS0 _MMIO(0xA500)
313+#define MISC_STATUS1 _MMIO(0xA504)
314+
315+#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
316+
317+#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
318+#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18)
319+
320+#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
321+#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
322+#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
323+
324+#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
325+#define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
326+#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)
327+#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24)
328+
329+#define GEN8_RTCR _MMIO(0x4260)
330+#define GEN8_M1TCR _MMIO(0x4264)
331+#define GEN8_M2TCR _MMIO(0x4268)
332+#define GEN8_BTCR _MMIO(0x426c)
333+#define GEN8_VTCR _MMIO(0x4270)
334+
335+#define IPEIR_I965 _MMIO(0x2064)
336+#define IPEHR_I965 _MMIO(0x2068)
337+#define GEN7_SC_INSTDONE _MMIO(0x7100)
338+#define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
339+#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
340+#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
341+#define GEN7_ROW_INSTDONE _MMIO(0xe164)
342+#define XEHPG_INSTDONE_GEOM_SVG _MMIO(0x666c)
343+#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
344+#define SF_MCR_SELECTOR _MMIO(0xfd8)
345+#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
346+#define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
347+#define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
348+#define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
349+#define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
350+#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
351+#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
352+#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
353+#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
354+/*
355+ * On GEN4, only the render ring INSTDONE exists and has a different
356+ * layout than the GEN7+ version.
357+ * The GEN2 counterpart of this register is GEN2_INSTDONE.
358+ */
359+#define INSTPS _MMIO(0x2070) /* 965+ only */
360+#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
361+#define ACTHD_I965 _MMIO(0x2074)
362+#define HWS_PGA _MMIO(0x2080)
363+#define HWS_ADDRESS_MASK 0xfffff000
364+#define HWS_START_ADDRESS_SHIFT 4
365+#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
366+#define PWRCTX_EN (1 << 0)
367+#define GEN2_INSTDONE _MMIO(0x2090)
368+#define NOPID _MMIO(0x2094)
369+#define HWSTAM _MMIO(0x2098)
370+
371+#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
372+#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
373+
374+#define ERROR_GEN6 _MMIO(0x40a0)
375+
376+#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
377+#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
378+#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
379+#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
380+#define FAULT_VA_HIGH_BITS (0xf << 0)
381+#define FAULT_GTT_SEL (1 << 4)
382+
383+#define GEN12_GFX_TLB_INV_CR _MMIO(0xced8)
384+#define GEN12_VD_TLB_INV_CR _MMIO(0xcedc)
385+#define GEN12_VE_TLB_INV_CR _MMIO(0xcee0)
386+#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)
387+
388+#define GEN12_AUX_ERR_DBG _MMIO(0x43f4)
389+
390+/* GM45+ chicken bits -- debug workaround bits that may be required
391+ * for various sorts of correct behavior. The top 16 bits of each are
392+ * the enables for writing to the corresponding low bit.
393+ */
394+#define _3D_CHICKEN _MMIO(0x2084)
395+#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
396+#define _3D_CHICKEN2 _MMIO(0x208c)
397+
398+#define FF_SLICE_CHICKEN _MMIO(0x2088)
399+#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
400+
401+/* Disables pipelining of read flushes past the SF-WIZ interface.
402+ * Required on all Ironlake steppings according to the B-Spec, but the
403+ * particular danger of not doing so is not specified.
404+ */
405+# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
406+#define _3D_CHICKEN3 _MMIO(0x2090)
407+#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
408+#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
409+#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
410+#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
411+#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */
412+#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
413+
414+#define MI_MODE _MMIO(0x209c)
415+# define VS_TIMER_DISPATCH (1 << 6)
416+# define MI_FLUSH_ENABLE (1 << 12)
417+# define TGL_NESTED_BB_EN (1 << 12)
418+# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
419+# define MODE_IDLE (1 << 9)
420+# define STOP_RING (1 << 8)
421+
422+#define GEN6_GT_MODE _MMIO(0x20d0)
423+#define GEN7_GT_MODE _MMIO(0x7008)
424+#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
425+#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
426+#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
427+#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
428+#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
429+#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
430+#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
431+#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
432+
433+/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
434+#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
435+#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
436+#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
437+
438+#define SCCGCTL94DC _MMIO(0x94dc)
439+#define CG3DDISURB REG_BIT(14)
440+
441+#define MLTICTXCTL _MMIO(0xb170)
442+#define TDONRENDER REG_BIT(2)
443+
444+#define L3SQCREG1_CCS0 _MMIO(0xb200)
445+#define FLUSHALLNONCOH REG_BIT(5)
446+
447+/* WaClearTdlStateAckDirtyBits */
448+#define GEN8_STATE_ACK _MMIO(0x20F0)
449+#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
450+#define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
451+#define GEN9_STATE_ACK_TDL0 (1 << 12)
452+#define GEN9_STATE_ACK_TDL1 (1 << 13)
453+#define GEN9_STATE_ACK_TDL2 (1 << 14)
454+#define GEN9_STATE_ACK_TDL3 (1 << 15)
455+#define GEN9_SUBSLICE_TDL_ACK_BITS \
456+ (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
457+ GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
458+
459+#define GFX_MODE _MMIO(0x2520)
460+
461+#define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
462+#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
463+#define CM0_IZ_OPT_DISABLE (1 << 6)
464+#define CM0_ZR_OPT_DISABLE (1 << 5)
465+#define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)
466+#define CM0_DEPTH_EVICT_DISABLE (1 << 4)
467+#define CM0_COLOR_EVICT_DISABLE (1 << 3)
468+#define CM0_DEPTH_WRITE_DISABLE (1 << 1)
469+#define CM0_RC_OP_FLUSH_DISABLE (1 << 0)
470+#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
471+#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
472+#define GFX_FLSH_CNTL_EN (1 << 0)
473+
474+#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
475+#define RC_OP_FLUSH_ENABLE (1 << 0)
476+#define HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
477+#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
478+#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6)
479+#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
480+#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
481+
482+#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
483+#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
484+
485+#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
486+#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
487+#define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
488+
489+/* Fuse readout registers for GT */
490+#define HSW_PAVP_FUSE1 _MMIO(0x911C)
491+#define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24)
492+#define HSW_F1_EU_DIS_MASK REG_GENMASK(17, 16)
493+#define HSW_F1_EU_DIS_10EUS 0
494+#define HSW_F1_EU_DIS_8EUS 1
495+#define HSW_F1_EU_DIS_6EUS 2
496+
497+#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
498+#define CHV_FGT_DISABLE_SS0 (1 << 10)
499+#define CHV_FGT_DISABLE_SS1 (1 << 11)
500+#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
501+#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
502+#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
503+#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
504+#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
505+#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
506+#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
507+#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
508+
509+#define GEN8_FUSE2 _MMIO(0x9120)
510+#define GEN8_F2_SS_DIS_SHIFT 21
511+#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
512+#define GEN8_F2_S_ENA_SHIFT 25
513+#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
514+
515+#define GEN9_F2_SS_DIS_SHIFT 20
516+#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
517+
518+#define GEN10_F2_S_ENA_SHIFT 22
519+#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
520+#define GEN10_F2_SS_DIS_SHIFT 18
521+#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
522+
523+#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
524+#define GEN10_L3BANK_PAIR_COUNT 4
525+#define GEN10_L3BANK_MASK 0x0F
526+/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
527+#define GEN12_MAX_MSLICES 4
528+#define GEN12_MEML3_EN_MASK 0x0F
529+
530+#define GEN8_EU_DISABLE0 _MMIO(0x9134)
531+#define GEN8_EU_DIS0_S0_MASK 0xffffff
532+#define GEN8_EU_DIS0_S1_SHIFT 24
533+#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
534+
535+#define GEN8_EU_DISABLE1 _MMIO(0x9138)
536+#define GEN8_EU_DIS1_S1_MASK 0xffff
537+#define GEN8_EU_DIS1_S2_SHIFT 16
538+#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
539+
540+#define GEN8_EU_DISABLE2 _MMIO(0x913c)
541+#define GEN8_EU_DIS2_S2_MASK 0xff
542+
543+#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
544+
545+#define GEN10_EU_DISABLE3 _MMIO(0x9140)
546+#define GEN10_EU_DIS_SS_MASK 0xff
547+
548+#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
549+#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
550+#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
551+#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
552+
553+#define GEN11_EU_DISABLE _MMIO(0x9134)
554+#define GEN11_EU_DIS_MASK 0xFF
555+
556+#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
557+#define GEN11_GT_S_ENA_MASK 0xFF
558+
559+#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
560+
561+#define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913C)
562+#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
563+
564+#define XEHP_EU_ENABLE _MMIO(0x9134)
565+#define XEHP_EU_ENA_MASK 0xFF
566+
567+#define CRSTANDVID _MMIO(0x11100)
568+#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
569+#define PXVFREQ_PX_MASK 0x7f000000
570+#define PXVFREQ_PX_SHIFT 24
571+#define VIDFREQ_BASE _MMIO(0x11110)
572+#define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
573+#define VIDFREQ2 _MMIO(0x11114)
574+#define VIDFREQ3 _MMIO(0x11118)
575+#define VIDFREQ4 _MMIO(0x1111c)
576+#define VIDFREQ_P0_MASK 0x1f000000
577+#define VIDFREQ_P0_SHIFT 24
578+#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
579+#define VIDFREQ_P0_CSCLK_SHIFT 20
580+#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
581+#define VIDFREQ_P0_CRCLK_SHIFT 16
582+#define VIDFREQ_P1_MASK 0x00001f00
583+#define VIDFREQ_P1_SHIFT 8
584+#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
585+#define VIDFREQ_P1_CSCLK_SHIFT 4
586+#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
587+#define INTTOEXT_BASE_ILK _MMIO(0x11300)
588+#define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
589+#define INTTOEXT_MAP3_SHIFT 24
590+#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
591+#define INTTOEXT_MAP2_SHIFT 16
592+#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
593+#define INTTOEXT_MAP1_SHIFT 8
594+#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
595+#define INTTOEXT_MAP0_SHIFT 0
596+#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
597+#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
598+#define MEMCTL_CMD_MASK 0xe000
599+#define MEMCTL_CMD_SHIFT 13
600+#define MEMCTL_CMD_RCLK_OFF 0
601+#define MEMCTL_CMD_RCLK_ON 1
602+#define MEMCTL_CMD_CHFREQ 2
603+#define MEMCTL_CMD_CHVID 3
604+#define MEMCTL_CMD_VMMOFF 4
605+#define MEMCTL_CMD_VMMON 5
606+#define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears
607+ when command complete */
608+#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
609+#define MEMCTL_FREQ_SHIFT 8
610+#define MEMCTL_SFCAVM (1 << 7)
611+#define MEMCTL_TGT_VID_MASK 0x007f
612+#define MEMIHYST _MMIO(0x1117c)
613+#define MEMINTREN _MMIO(0x11180) /* 16 bits */
614+#define MEMINT_RSEXIT_EN (1 << 8)
615+#define MEMINT_CX_SUPR_EN (1 << 7)
616+#define MEMINT_CONT_BUSY_EN (1 << 6)
617+#define MEMINT_AVG_BUSY_EN (1 << 5)
618+#define MEMINT_EVAL_CHG_EN (1 << 4)
619+#define MEMINT_MON_IDLE_EN (1 << 3)
620+#define MEMINT_UP_EVAL_EN (1 << 2)
621+#define MEMINT_DOWN_EVAL_EN (1 << 1)
622+#define MEMINT_SW_CMD_EN (1 << 0)
623+#define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
624+#define MEM_RSEXIT_MASK 0xc000
625+#define MEM_RSEXIT_SHIFT 14
626+#define MEM_CONT_BUSY_MASK 0x3000
627+#define MEM_CONT_BUSY_SHIFT 12
628+#define MEM_AVG_BUSY_MASK 0x0c00
629+#define MEM_AVG_BUSY_SHIFT 10
630+#define MEM_EVAL_CHG_MASK 0x0300
631+#define MEM_EVAL_BUSY_SHIFT 8
632+#define MEM_MON_IDLE_MASK 0x00c0
633+#define MEM_MON_IDLE_SHIFT 6
634+#define MEM_UP_EVAL_MASK 0x0030
635+#define MEM_UP_EVAL_SHIFT 4
636+#define MEM_DOWN_EVAL_MASK 0x000c
637+#define MEM_DOWN_EVAL_SHIFT 2
638+#define MEM_SW_CMD_MASK 0x0003
639+#define MEM_INT_STEER_GFX 0
640+#define MEM_INT_STEER_CMR 1
641+#define MEM_INT_STEER_SMI 2
642+#define MEM_INT_STEER_SCI 3
643+#define MEMINTRSTS _MMIO(0x11184)
644+#define MEMINT_RSEXIT (1 << 7)
645+#define MEMINT_CONT_BUSY (1 << 6)
646+#define MEMINT_AVG_BUSY (1 << 5)
647+#define MEMINT_EVAL_CHG (1 << 4)
648+#define MEMINT_MON_IDLE (1 << 3)
649+#define MEMINT_UP_EVAL (1 << 2)
650+#define MEMINT_DOWN_EVAL (1 << 1)
651+#define MEMINT_SW_CMD (1 << 0)
652+#define MEMMODECTL _MMIO(0x11190)
653+#define MEMMODE_BOOST_EN (1 << 31)
654+#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
655+#define MEMMODE_BOOST_FREQ_SHIFT 24
656+#define MEMMODE_IDLE_MODE_MASK 0x00030000
657+#define MEMMODE_IDLE_MODE_SHIFT 16
658+#define MEMMODE_IDLE_MODE_EVAL 0
659+#define MEMMODE_IDLE_MODE_CONT 1
660+#define MEMMODE_HWIDLE_EN (1 << 15)
661+#define MEMMODE_SWMODE_EN (1 << 14)
662+#define MEMMODE_RCLK_GATE (1 << 13)
663+#define MEMMODE_HW_UPDATE (1 << 12)
664+#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
665+#define MEMMODE_FSTART_SHIFT 8
666+#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
667+#define MEMMODE_FMAX_SHIFT 4
668+#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
669+#define RCBMAXAVG _MMIO(0x1119c)
670+#define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
671+#define SWMEMCMD_RENDER_OFF (0 << 13)
672+#define SWMEMCMD_RENDER_ON (1 << 13)
673+#define SWMEMCMD_SWFREQ (2 << 13)
674+#define SWMEMCMD_TARVID (3 << 13)
675+#define SWMEMCMD_VRM_OFF (4 << 13)
676+#define SWMEMCMD_VRM_ON (5 << 13)
677+#define CMDSTS (1 << 12)
678+#define SFCAVM (1 << 11)
679+#define SWFREQ_MASK 0x0380 /* P0-7 */
680+#define SWFREQ_SHIFT 7
681+#define TARVID_MASK 0x001f
682+#define MEMSTAT_CTG _MMIO(0x111a0)
683+#define RCBMINAVG _MMIO(0x111a0)
684+#define RCUPEI _MMIO(0x111b0)
685+#define RCDNEI _MMIO(0x111b4)
686+#define RSTDBYCTL _MMIO(0x111b8)
687+#define RS1EN (1 << 31)
688+#define RS2EN (1 << 30)
689+#define RS3EN (1 << 29)
690+#define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */
691+#define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */
692+#define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */
693+#define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */
694+#define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */
695+#define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */
696+#define RSX_STATUS_MASK (7 << 20)
697+#define RSX_STATUS_ON (0 << 20)
698+#define RSX_STATUS_RC1 (1 << 20)
699+#define RSX_STATUS_RC1E (2 << 20)
700+#define RSX_STATUS_RS1 (3 << 20)
701+#define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */
702+#define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */
703+#define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */
704+#define RSX_STATUS_RSVD2 (7 << 20)
705+#define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */
706+#define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */
707+#define JRSC (1 << 17) /* rsx coupled to cpu c-state */
708+#define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */
709+#define RS1CONTSAV_MASK (3 << 14)
710+#define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */
711+#define RS1CONTSAV_RSVD (1 << 14)
712+#define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */
713+#define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */
714+#define NORMSLEXLAT_MASK (3 << 12)
715+#define SLOW_RS123 (0 << 12)
716+#define SLOW_RS23 (1 << 12)
717+#define SLOW_RS3 (2 << 12)
718+#define NORMAL_RS123 (3 << 12)
719+#define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */
720+#define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
721+#define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
722+#define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */
723+#define RS_CSTATE_MASK (3 << 4)
724+#define RS_CSTATE_C367_RS1 (0 << 4)
725+#define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
726+#define RS_CSTATE_RSVD (2 << 4)
727+#define RS_CSTATE_C367_RS2 (3 << 4)
728+#define REDSAVES (1 << 3) /* no context save if was idle during rs0 */
729+#define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */
730+#define VIDCTL _MMIO(0x111c0)
731+#define VIDSTS _MMIO(0x111c8)
732+#define VIDSTART _MMIO(0x111cc) /* 8 bits */
733+#define MEMSTAT_ILK _MMIO(0x111f8)
734+#define MEMSTAT_VID_MASK 0x7f00
735+#define MEMSTAT_VID_SHIFT 8
736+#define MEMSTAT_PSTATE_MASK 0x00f8
737+#define MEMSTAT_PSTATE_SHIFT 3
738+#define MEMSTAT_MON_ACTV (1 << 2)
739+#define MEMSTAT_SRC_CTL_MASK 0x0003
740+#define MEMSTAT_SRC_CTL_CORE 0
741+#define MEMSTAT_SRC_CTL_TRB 1
742+#define MEMSTAT_SRC_CTL_THM 2
743+#define MEMSTAT_SRC_CTL_STDBY 3
744+#define RCPREVBSYTUPAVG _MMIO(0x113b8)
745+#define RCPREVBSYTDNAVG _MMIO(0x113bc)
746+#define PMMISC _MMIO(0x11214)
747+#define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */
748+#define SDEW _MMIO(0x1124c)
749+#define CSIEW0 _MMIO(0x11250)
750+#define CSIEW1 _MMIO(0x11254)
751+#define CSIEW2 _MMIO(0x11258)
752+#define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
753+#define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
754+#define MCHAFE _MMIO(0x112c0)
755+#define CSIEC _MMIO(0x112e0)
756+#define DMIEC _MMIO(0x112e4)
757+#define DDREC _MMIO(0x112e8)
758+#define PEG0EC _MMIO(0x112ec)
759+#define PEG1EC _MMIO(0x112f0)
760+#define GFXEC _MMIO(0x112f4)
761+#define RPPREVBSYTUPAVG _MMIO(0x113b8)
762+#define RPPREVBSYTDNAVG _MMIO(0x113bc)
763+#define ECR _MMIO(0x11600)
764+#define ECR_GPFE (1 << 31)
765+#define ECR_IMONE (1 << 30)
766+#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
767+#define OGW0 _MMIO(0x11608)
768+#define OGW1 _MMIO(0x1160c)
769+#define EG0 _MMIO(0x11610)
770+#define EG1 _MMIO(0x11614)
771+#define EG2 _MMIO(0x11618)
772+#define EG3 _MMIO(0x1161c)
773+#define EG4 _MMIO(0x11620)
774+#define EG5 _MMIO(0x11624)
775+#define EG6 _MMIO(0x11628)
776+#define EG7 _MMIO(0x1162c)
777+#define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
778+#define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
779+#define LCFUSE02 _MMIO(0x116c0)
780+#define LCFUSE_HIV_MASK 0x000000ff
781+
782+#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
783+#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
784+
785+/*
786+ * Logical Context regs
787+ */
788+/*
789+ * Notes on SNB/IVB/VLV context size:
790+ * - Power context is saved elsewhere (LLC or stolen)
791+ * - Ring/execlist context is saved on SNB, not on IVB
792+ * - Extended context size already includes render context size
793+ * - We always need to follow the extended context size.
794+ * SNB BSpec has comments indicating that we should use the
795+ * render context size instead if execlists are disabled, but
796+ * based on empirical testing that's just nonsense.
797+ * - Pipelined/VF state is saved on SNB/IVB respectively
798+ * - GT1 size just indicates how much of render context
799+ * doesn't need saving on GT1
800+ */
801+#define CXT_SIZE _MMIO(0x21a0)
802+#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
803+#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
804+#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
805+#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
806+#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
807+#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
808+ GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
809+ GEN6_CXT_PIPELINE_SIZE(cxt_reg))
810+#define GEN7_CXT_SIZE _MMIO(0x21a8)
811+#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
812+#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
813+#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
814+#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
815+#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
816+#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
817+#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
818+ GEN7_CXT_VFSTATE_SIZE(ctx_reg))
819+
820+enum {
821+ INTEL_ADVANCED_CONTEXT = 0,
822+ INTEL_LEGACY_32B_CONTEXT,
823+ INTEL_ADVANCED_AD_CONTEXT,
824+ INTEL_LEGACY_64B_CONTEXT
825+};
826+
827+enum {
828+ FAULT_AND_HANG = 0,
829+ FAULT_AND_HALT, /* Debug only */
830+ FAULT_AND_STREAM,
831+ FAULT_AND_CONTINUE /* Unsupported */
832+};
833+
834+#define CTX_GTT_ADDRESS_MASK GENMASK(31, 12)
835+#define GEN8_CTX_VALID (1 << 0)
836+#define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
837+#define GEN8_CTX_FORCE_RESTORE (1 << 2)
838+#define GEN8_CTX_L3LLC_COHERENT (1 << 5)
839+#define GEN8_CTX_PRIVILEGE (1 << 8)
840+#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
841+
842+#define GEN8_CTX_ID_SHIFT 32
843+#define GEN8_CTX_ID_WIDTH 21
844+#define GEN11_SW_CTX_ID_SHIFT 37
845+#define GEN11_SW_CTX_ID_WIDTH 11
846+#define GEN11_ENGINE_CLASS_SHIFT 61
847+#define GEN11_ENGINE_CLASS_WIDTH 3
848+#define GEN11_ENGINE_INSTANCE_SHIFT 48
849+#define GEN11_ENGINE_INSTANCE_WIDTH 6
850+
851+#define XEHP_SW_CTX_ID_SHIFT 39
852+#define XEHP_SW_CTX_ID_WIDTH 16
853+#define XEHP_SW_COUNTER_SHIFT 58
854+#define XEHP_SW_COUNTER_WIDTH 6
855+
856+#define UNSLCGCTL9440 _MMIO(0x9440)
857+#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
858+#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
859+#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
860+#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
861+#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
862+#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
863+#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
864+#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
865+#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
866+#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
867+#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
868+#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
869+
870+#define UNSLCGCTL9444 _MMIO(0x9444)
871+#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
872+#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
873+#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
874+#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
875+#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
876+#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
877+#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
878+#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
879+#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
880+#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
881+#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
882+#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
883+#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
884+#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
885+#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
886+#define LTCDD_CLKGATE_DIS REG_BIT(10)
887+
888+#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
889+#define SARBUNIT_CLKGATE_DIS (1 << 5)
890+#define RCCUNIT_CLKGATE_DIS (1 << 7)
891+#define MSCUNIT_CLKGATE_DIS (1 << 10)
892+#define NODEDSS_CLKGATE_DIS REG_BIT(12)
893+#define L3_CLKGATE_DIS REG_BIT(16)
894+#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
895+
896+#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
897+#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
898+#define GWUNIT_CLKGATE_DIS REG_BIT(16)
899+
900+#define SUBSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x9528)
901+#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
902+
903+#define SSMCGCTL9530 _MMIO(0x9530)
904+#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
905+
906+#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
907+#define VFUNIT_CLKGATE_DIS REG_BIT(20)
908+#define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */
909+#define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
910+#define GAMEDIA_CLKGATE_DIS REG_BIT(11)
911+#define HSUNIT_CLKGATE_DIS REG_BIT(8)
912+#define VSUNIT_CLKGATE_DIS REG_BIT(3)
913+
914+#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
915+#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
916+#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
917+
918+#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
919+#define CGPSF_CLKGATE_DIS (1 << 3)
920+
921+#define GEN11_GT_INTR_DW0 _MMIO(0x190018)
922+#define GEN11_CSME (31)
923+#define GEN11_GUNIT (28)
924+#define GEN11_GUC (25)
925+#define GEN11_WDPERF (20)
926+#define GEN11_KCR (19)
927+#define GEN11_GTPM (16)
928+#define GEN11_BCS (15)
929+#define GEN11_RCS0 (0)
930+
931+#define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
932+#define GEN11_VECS(x) (31 - (x))
933+#define GEN11_VCS(x) (x)
934+
935+#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
936+
937+#define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
938+#define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
939+#define GEN11_INTR_DATA_VALID (1 << 31)
940+#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
941+#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
942+#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
943+/* irq instances for OTHER_CLASS */
944+#define OTHER_GUC_INSTANCE 0
945+#define OTHER_GTPM_INSTANCE 1
946+#define OTHER_KCR_INSTANCE 4
947+
948+#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
949+
950+#define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
951+#define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
952+
953+#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
954+
955+#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
956+#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
957+#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
958+#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
959+#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
960+#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
961+
962+#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
963+#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
964+#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
965+#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
966+#define GEN12_VCS4_VCS5_INTR_MASK _MMIO(0x1900b0)
967+#define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4)
968+#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
969+#define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4)
970+#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
971+#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
972+#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
973+#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
974+
975+#define ENGINE1_MASK REG_GENMASK(31, 16)
976+#define ENGINE0_MASK REG_GENMASK(15, 0)
977+
978+#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
979+#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
980+
981+#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
982+#define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8)
983+#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
984+
985+#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
986+#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
987+#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
988+#define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
989+
990+#define GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON _MMIO(0x20EC)
991+#define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0)
992+
993+#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
994+#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
995+#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
996+#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
997+#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
998+#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
999+#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
1000+
1001+/* GEN7 chicken */
1002+#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
1003+ #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10)
1004+ #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
1005+
1006+#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
1007+ #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
1008+ #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
1009+ #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
1010+ #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
1011+
1012+#define GEN8_L3CNTLREG _MMIO(0x7034)
1013+ #define GEN8_ERRDETBCTRL (1 << 9)
1014+
1015+#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
1016+#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
1017+#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
1018+#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
1019+#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
1020+
1021+#define HIZ_CHICKEN _MMIO(0x7018)
1022+# define CHV_HZ_8X8_MODE_IN_1X REG_BIT(15)
1023+# define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
1024+# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE REG_BIT(3)
1025+
1026+#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
1027+#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
1028+
1029+#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
1030+#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
1031+
1032+#define GEN7_SARCHKMD _MMIO(0xB000)
1033+#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
1034+#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
1035+
1036+#define GEN7_L3SQCREG1 _MMIO(0xB010)
1037+#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
1038+
1039+#define GEN8_L3SQCREG1 _MMIO(0xB100)
1040+/*
1041+ * Note that on CHV the following has an off-by-one error wrt. to BSpec.
1042+ * Using the formula in BSpec leads to a hang, while the formula here works
1043+ * fine and matches the formulas for all other platforms. A BSpec change
1044+ * request has been filed to clarify this.
1045+ */
1046+#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
1047+#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
1048+#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
1049+
1050+#define GEN7_L3CNTLREG1 _MMIO(0xB01C)
1051+#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
1052+#define GEN7_L3AGDIS (1 << 19)
1053+#define GEN7_L3CNTLREG2 _MMIO(0xB020)
1054+#define GEN7_L3CNTLREG3 _MMIO(0xB024)
1055+
1056+#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
1057+#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
1058+#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
1059+#define GEN11_I2M_WRITE_DISABLE (1 << 28)
1060+
1061+#define GEN7_L3SQCREG4 _MMIO(0xb034)
1062+#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27)
1063+
1064+#define GEN11_SCRATCH2 _MMIO(0xb140)
1065+#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19)
1066+
1067+#define GEN8_L3SQCREG4 _MMIO(0xb118)
1068+#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
1069+#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
1070+#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
1071+#define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
1072+
1073+#define GEN11_L3SQCREG5 _MMIO(0xb158)
1074+#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
1075+
1076+#define XEHP_L3SCQREG7 _MMIO(0xb188)
1077+#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
1078+
1079+/* GEN8 chicken */
1080+#define HDC_CHICKEN0 _MMIO(0x7300)
1081+#define ICL_HDC_MODE _MMIO(0xE5F4)
1082+#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
1083+#define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
1084+#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11)
1085+#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5)
1086+#define HDC_FORCE_NON_COHERENT (1 << 4)
1087+#define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10)
1088+
1089+#define GEN12_HDC_CHICKEN0 _MMIO(0xE5F0)
1090+#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
1091+
1092+#define SARB_CHICKEN1 _MMIO(0xe90c)
1093+#define COMP_CKN_IN REG_GENMASK(30, 29)
1094+
1095+#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
1096+
1097+/* GEN9 chicken */
1098+#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
1099+#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
1100+
1101+#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
1102+#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
1103+
1104+/* WaCatErrorRejectionIssue */
1105+#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
1106+#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11)
1107+
1108+#define HSW_SCRATCH1 _MMIO(0xb038)
1109+#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27)
1110+
1111+#define BDW_SCRATCH1 _MMIO(0xb11c)
1112+#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
1113+
1114+#define VFLSKPD _MMIO(0x62a8)
1115+#define DIS_OVER_FETCH_CACHE REG_BIT(1)
1116+#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
1117+
1118+#define FF_MODE2 _MMIO(0x6604)
1119+#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
1120+#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
1121+#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
1122+#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
1123+
1124+#define RC6_LOCATION _MMIO(0xD40)
1125+#define RC6_CTX_IN_DRAM (1 << 0)
1126+#define RC6_CTX_BASE _MMIO(0xD48)
1127+#define RC6_CTX_BASE_MASK 0xFFFFFFF0
1128+#define FORCEWAKE _MMIO(0xA18C)
1129+#define FORCEWAKE_VLV _MMIO(0x1300b0)
1130+#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
1131+#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
1132+#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
1133+#define FORCEWAKE_ACK_HSW _MMIO(0x130044)
1134+#define FORCEWAKE_ACK _MMIO(0x130090)
1135+#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
1136+#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
1137+#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
1138+#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
1139+
1140+#define VLV_GTLC_PW_STATUS _MMIO(0x130094)
1141+#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
1142+#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
1143+#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
1144+#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
1145+#define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
1146+#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
1147+#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
1148+#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
1149+#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
1150+#define FORCEWAKE_GT_GEN9 _MMIO(0xa188)
1151+#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
1152+#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4)
1153+#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4)
1154+#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
1155+#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)
1156+#define FORCEWAKE_KERNEL BIT(0)
1157+#define FORCEWAKE_USER BIT(1)
1158+#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
1159+#define FORCEWAKE_MT_ACK _MMIO(0x130040)
1160+#define ECOBUS _MMIO(0xa180)
1161+#define FORCEWAKE_MT_ENABLE (1 << 5)
1162+#define VLV_SPAREG2H _MMIO(0xA194)
1163+#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
1164+#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
1165+#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
1166+
1167+#define GTFIFODBG _MMIO(0x120000)
1168+#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
1169+#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
1170+#define GT_FIFO_SBDROPERR (1 << 6)
1171+#define GT_FIFO_BLOBDROPERR (1 << 5)
1172+#define GT_FIFO_SB_READ_ABORTERR (1 << 4)
1173+#define GT_FIFO_DROPERR (1 << 3)
1174+#define GT_FIFO_OVFERR (1 << 2)
1175+#define GT_FIFO_IAWRERR (1 << 1)
1176+#define GT_FIFO_IARDERR (1 << 0)
1177+
1178+#define GTFIFOCTL _MMIO(0x120008)
1179+#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
1180+#define GT_FIFO_NUM_RESERVED_ENTRIES 20
1181+#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
1182+#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
1183+
1184+#define HSW_IDICR _MMIO(0x9008)
1185+#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
1186+
1187+#define GEN6_UCGCTL1 _MMIO(0x9400)
1188+# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
1189+# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
1190+# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
1191+# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
1192+
1193+#define GEN6_UCGCTL2 _MMIO(0x9404)
1194+# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
1195+# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
1196+# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
1197+# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
1198+# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
1199+# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
1200+
1201+#define GEN6_UCGCTL3 _MMIO(0x9408)
1202+# define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
1203+
1204+#define GEN7_UCGCTL4 _MMIO(0x940c)
1205+#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25)
1206+#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14)
1207+
1208+#define GEN6_RCGCTL1 _MMIO(0x9410)
1209+#define GEN6_RCGCTL2 _MMIO(0x9414)
1210+#define GEN6_RSTCTL _MMIO(0x9420)
1211+
1212+#define GEN8_UCGCTL6 _MMIO(0x9430)
1213+#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24)
1214+#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14)
1215+#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
1216+
1217+#define UNSLCGCTL9430 _MMIO(0x9430)
1218+#define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
1219+
1220+#define GEN6_GFXPAUSE _MMIO(0xA000)
1221+#define GEN6_RPNSWREQ _MMIO(0xA008)
1222+#define GEN6_TURBO_DISABLE (1 << 31)
1223+#define GEN6_FREQUENCY(x) ((x) << 25)
1224+#define HSW_FREQUENCY(x) ((x) << 24)
1225+#define GEN9_FREQUENCY(x) ((x) << 23)
1226+#define GEN6_OFFSET(x) ((x) << 19)
1227+#define GEN6_AGGRESSIVE_TURBO (0 << 15)
1228+#define GEN9_SW_REQ_UNSLICE_RATIO_SHIFT 23
1229+#define GEN9_IGNORE_SLICE_RATIO (0 << 0)
1230+
1231+#define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
1232+#define GEN6_RC_CONTROL _MMIO(0xA090)
1233+#define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16)
1234+#define GEN6_RC_CTL_RC6p_ENABLE (1 << 17)
1235+#define GEN6_RC_CTL_RC6_ENABLE (1 << 18)
1236+#define GEN6_RC_CTL_RC1e_ENABLE (1 << 20)
1237+#define GEN6_RC_CTL_RC7_ENABLE (1 << 22)
1238+#define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24)
1239+#define GEN7_RC_CTL_TO_MODE (1 << 28)
1240+#define GEN6_RC_CTL_EI_MODE(x) ((x) << 27)
1241+#define GEN6_RC_CTL_HW_ENABLE (1 << 31)
1242+#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
1243+#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
1244+#define GEN6_RPSTAT1 _MMIO(0xA01C)
1245+#define GEN6_CAGF_SHIFT 8
1246+#define HSW_CAGF_SHIFT 7
1247+#define GEN9_CAGF_SHIFT 23
1248+#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
1249+#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
1250+#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
1251+#define GEN6_RP_CONTROL _MMIO(0xA024)
1252+#define GEN6_RP_MEDIA_TURBO (1 << 11)
1253+#define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
1254+#define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9)
1255+#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9)
1256+#define GEN6_RP_MEDIA_HW_MODE (1 << 9)
1257+#define GEN6_RP_MEDIA_SW_MODE (0 << 9)
1258+#define GEN6_RP_MEDIA_IS_GFX (1 << 8)
1259+#define GEN6_RP_ENABLE (1 << 7)
1260+#define GEN6_RP_UP_IDLE_MIN (0x1 << 3)
1261+#define GEN6_RP_UP_BUSY_AVG (0x2 << 3)
1262+#define GEN6_RP_UP_BUSY_CONT (0x4 << 3)
1263+#define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0)
1264+#define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0)
1265+#define GEN6_RPSWCTL_SHIFT 9
1266+#define GEN9_RPSWCTL_ENABLE (0x2 << GEN6_RPSWCTL_SHIFT)
1267+#define GEN9_RPSWCTL_DISABLE (0x0 << GEN6_RPSWCTL_SHIFT)
1268+#define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
1269+#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
1270+#define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
1271+#define GEN6_RP_EI_MASK 0xffffff
1272+#define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
1273+#define GEN6_RP_CUR_UP _MMIO(0xA054)
1274+#define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
1275+#define GEN6_RP_PREV_UP _MMIO(0xA058)
1276+#define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
1277+#define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
1278+#define GEN6_RP_CUR_DOWN _MMIO(0xA060)
1279+#define GEN6_RP_PREV_DOWN _MMIO(0xA064)
1280+#define GEN6_RP_UP_EI _MMIO(0xA068)
1281+#define GEN6_RP_DOWN_EI _MMIO(0xA06C)
1282+#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
1283+#define GEN6_RPDEUHWTC _MMIO(0xA080)
1284+#define GEN6_RPDEUC _MMIO(0xA084)
1285+#define GEN6_RPDEUCSW _MMIO(0xA088)
1286+#define GEN6_RC_STATE _MMIO(0xA094)
1287+#define RC_SW_TARGET_STATE_SHIFT 16
1288+#define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
1289+#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
1290+#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
1291+#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
1292+#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
1293+#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
1294+#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
1295+#define GEN6_RC_SLEEP _MMIO(0xA0B0)
1296+#define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
1297+#define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
1298+#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
1299+#define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
1300+#define VLV_RCEDATA _MMIO(0xA0BC)
1301+#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
1302+#define GEN6_PMINTRMSK _MMIO(0xA168)
1303+#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
1304+#define ARAT_EXPIRED_INTRMSK (1 << 9)
1305+#define GEN8_MISC_CTRL0 _MMIO(0xA180)
1306+#define VLV_PWRDWNUPCTL _MMIO(0xA294)
1307+#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
1308+#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
1309+#define GEN9_PG_ENABLE _MMIO(0xA210)
1310+#define GEN9_RENDER_PG_ENABLE REG_BIT(0)
1311+#define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
1312+#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
1313+#define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n))
1314+#define VDN_MFX_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n))
1315+#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
1316+#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
1317+#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
1318+
1319+#define GEN6_PMISR _MMIO(0x44020)
1320+#define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
1321+#define GEN6_PMIIR _MMIO(0x44028)
1322+#define GEN6_PMIER _MMIO(0x4402C)
1323+#define GEN6_PM_MBOX_EVENT (1 << 25)
1324+#define GEN6_PM_THERMAL_EVENT (1 << 24)
1325+
1326+/*
1327+ * For Gen11 these are in the upper word of the GPM_WGBOXPERF
1328+ * registers. Shifting is handled on accessing the imr and ier.
1329+ */
1330+#define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6)
1331+#define GEN6_PM_RP_UP_THRESHOLD (1 << 5)
1332+#define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
1333+#define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
1334+#define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
1335+#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \
1336+ GEN6_PM_RP_UP_THRESHOLD | \
1337+ GEN6_PM_RP_DOWN_EI_EXPIRED | \
1338+ GEN6_PM_RP_DOWN_THRESHOLD | \
1339+ GEN6_PM_RP_DOWN_TIMEOUT)
1340+
1341+#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
1342+#define GEN7_GT_SCRATCH_REG_NUM 8
1343+
1344+#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
1345+#define VLV_GFX_CLK_STATUS_BIT (1 << 3)
1346+#define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2)
1347+
1348+#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
1349+#define VLV_COUNTER_CONTROL _MMIO(0x138104)
1350+#define VLV_COUNT_RANGE_HIGH (1 << 15)
1351+#define VLV_MEDIA_RC0_COUNT_EN (1 << 5)
1352+#define VLV_RENDER_RC0_COUNT_EN (1 << 4)
1353+#define VLV_MEDIA_RC6_COUNT_EN (1 << 1)
1354+#define VLV_RENDER_RC6_COUNT_EN (1 << 0)
1355+#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
1356+#define VLV_GT_RENDER_RC6 _MMIO(0x138108)
1357+#define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
1358+
1359+#define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
1360+#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
1361+#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
1362+#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
1363+
1364+#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
1365+#define GEN6_CORE_CPD_STATE_MASK (7 << 4)
1366+#define GEN6_RCn_MASK 7
1367+#define GEN6_RC0 0
1368+#define GEN6_RC3 2
1369+#define GEN6_RC6 3
1370+#define GEN6_RC7 4
1371+
1372+#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
1373+#define GEN8_LSLICESTAT_MASK 0x7
1374+
1375+#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
1376+#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
1377+#define CHV_SS_PG_ENABLE (1 << 1)
1378+#define CHV_EU08_PG_ENABLE (1 << 9)
1379+#define CHV_EU19_PG_ENABLE (1 << 17)
1380+#define CHV_EU210_PG_ENABLE (1 << 25)
1381+
1382+#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
1383+#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
1384+#define CHV_EU311_PG_ENABLE (1 << 1)
1385+
1386+#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
1387+#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
1388+ ((slice) % 3) * 0x4)
1389+#define GEN9_PGCTL_SLICE_ACK (1 << 0)
1390+#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
1391+#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
1392+
1393+#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
1394+#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
1395+ ((slice) % 3) * 0x8)
1396+#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
1397+#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
1398+ ((slice) % 3) * 0x8)
1399+#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
1400+#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
1401+#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
1402+#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
1403+#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
1404+#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
1405+#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
1406+#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
1407+
1408+#define GEN7_MISCCPCTL _MMIO(0x9424)
1409+#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
1410+#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
1411+#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
1412+#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6)
1413+
1414+#define GEN8_GARBCNTL _MMIO(0xB004)
1415+#define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
1416+#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
1417+#define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0)
1418+#define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0)
1419+
1420+#define GEN11_GLBLINVL _MMIO(0xB404)
1421+#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
1422+#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
1423+
1424+#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
1425+#define DFR_DISABLE (1 << 9)
1426+
1427+#define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
1428+#define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
1429+#define GEN11_HASH_CTRL_BIT0 (1 << 0)
1430+#define GEN11_HASH_CTRL_BIT4 (1 << 12)
1431+
1432+#define GEN11_LSN_UNSLCVC _MMIO(0xB43C)
1433+#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
1434+#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
1435+
1436+#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
1437+#define ENABLE_SMALLPL REG_BIT(15)
1438+#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
1439+
1440+#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
1441+#define GEN7_L3LOG_SIZE 0x80
1442+
1443+#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
1444+#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
1445+#define GEN7_MAX_PS_THREAD_DEP (8 << 12)
1446+#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
1447+#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
1448+#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
1449+
1450+#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
1451+#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
1452+#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
1453+
1454+#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
1455+#define FLOW_CONTROL_ENABLE REG_BIT(15)
1456+#define UGM_BACKUP_MODE REG_BIT(13)
1457+#define MDQ_ARBITRATION_MODE REG_BIT(12)
1458+#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
1459+#define STALL_DOP_GATING_DISABLE REG_BIT(5)
1460+#define THROTTLE_12_5 REG_GENMASK(4, 2)
1461+#define DISABLE_EARLY_EOT REG_BIT(1)
1462+
1463+#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
1464+#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
1465+#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
1466+#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
1467+#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
1468+
1469+#define LSC_CHICKEN_BIT_0 _MMIO(0xe7c8)
1470+#define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
1471+#define LSC_CHICKEN_BIT_0_UDW _MMIO(0xe7c8 + 4)
1472+#define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
1473+#define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
1474+#define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
1475+#define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
1476+#define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
1477+
1478+#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
1479+#define DOP_CLOCK_GATING_DISABLE (1 << 0)
1480+#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
1481+#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
1482+
1483+#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
1484+#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
1485+#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
1486+#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
1487+#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
1488+
1489+#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
1490+#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
1491+
1492+#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
1493+#define GEN8_ST_PO_DISABLE (1 << 13)
1494+
1495+#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
1496+#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
1497+#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
1498+#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
1499+#define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
1500+
1501+#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
1502+#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
1503+#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR REG_BIT(8)
1504+#define GEN9_ENABLE_YV12_BUGFIX REG_BIT(4)
1505+#define GEN9_ENABLE_GPGPU_PREEMPTION REG_BIT(2)
1506+
1507+/* MOCS (Memory Object Control State) registers */
1508+#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
1509+#define GEN9_LNCFCMOCS_REG_COUNT 32
1510+
1511+#define __GEN9_RCS0_MOCS0 0xc800
1512+#define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
1513+#define __GEN9_VCS0_MOCS0 0xc900
1514+#define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
1515+#define __GEN9_VCS1_MOCS0 0xca00
1516+#define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
1517+#define __GEN9_VECS0_MOCS0 0xcb00
1518+#define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
1519+#define __GEN9_BCS0_MOCS0 0xcc00
1520+#define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
1521+#define __GEN11_VCS2_MOCS0 0x10000
1522+#define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
1523+
1524+#define GEN9_SCRATCH_LNCF1 _MMIO(0xb008)
1525+#define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
1526+
1527+#define GEN9_SCRATCH1 _MMIO(0xb11c)
1528+#define EVICTION_PERF_FIX_ENABLE REG_BIT(8)
1529+
1530+#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
1531+#define PMFLUSHDONE_LNICRSDROP (1 << 20)
1532+#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
1533+#define PMFLUSHDONE_LNEBLK (1 << 22)
1534+
1535+#define XEHP_L3NODEARBCFG _MMIO(0xb0b4)
1536+#define XEHP_LNESPARE REG_BIT(19)
1537+
1538+#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
1539+
1540+/* gamt regs */
1541+#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
1542+#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
1543+#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
1544+#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
1545+#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
1546+
1547+#define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
1548+#define MMCD_PCLA (1 << 31)
1549+#define MMCD_HOTSPOT_EN (1 << 27)
1550+
1551+#define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731C)
1552+#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
1553+
1554+#endif /* __INTEL_GT_REGS__ */
drivers/gpu/drm/i915/gt/intel_gtt.c+1−0
@@ -13,6 +13,7 @@ · 12 unmodified lines
1313 #include "gem/i915_gem_lmem.h"
1414 #include "i915_trace.h"
1515 #include "intel_gt.h"
16+#include "intel_gt_regs.h"
1617 #include "intel_gtt.h"
1718
1819 struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)
drivers/gpu/drm/i915/gt/intel_llc.c+5−5
@@ -7,6 +7,7 @@ · 6 unmodified lines
77 #include <linux/cpufreq.h>
88
99 #include "i915_drv.h"
10+#include "i915_reg.h"
1011 #include "intel_gt.h"
1112 #include "intel_llc.h"
1213 #include "intel_pcode.h"
@@ -140,11 +141,10 @@ static void gen6_update_ring_freq(struct intel_llc *llc) · 127 unmodified lines
140141 unsigned int ia_freq, ring_freq;
141142
142143 calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
143− sandybridge_pcode_write(i915,
144− GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
145− ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
146− ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
147− gpu_freq);
144+ snb_pcode_write(i915, GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
145+ ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
146+ ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
147+ gpu_freq);
148148 }
149149 }
150150
drivers/gpu/drm/i915/gt/intel_lrc.c+2−0
@@ -9,8 +9,10 @@ · 8 unmodified lines
99 #include "i915_drv.h"
1010 #include "i915_perf.h"
1111 #include "intel_engine.h"
12+#include "intel_engine_regs.h"
1213 #include "intel_gpu_commands.h"
1314 #include "intel_gt.h"
15+#include "intel_gt_regs.h"
1416 #include "intel_lrc.h"
1517 #include "intel_lrc_reg.h"
1618 #include "intel_ring.h"
drivers/gpu/drm/i915/gt/intel_lrc_reg.h+0−15
@@ -53,21 +53,6 @@ · 52 unmodified lines
5353 #define GEN8_EXECLISTS_STATUS_BUF 0x370
5454 #define GEN11_EXECLISTS_STATUS_BUF2 0x3c0
5555
56−/* Execlists regs */
57−#define RING_ELSP(base) _MMIO((base) + 0x230)
58−#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
59−#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
60−#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
61−#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
62−#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)
63−#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2)
64−#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
65−#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)
66−#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
67−#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
68−#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
69−#define EL_CTRL_LOAD REG_BIT(0)
70−
7156 /*
7257 * The docs specify that the write pointer wraps around after 5h, "After status
7358 * is written out to the last available status QW at offset 5h, this pointer
drivers/gpu/drm/i915/gt/intel_mocs.c+1−1
@@ -7,7 +7,7 @@ · 6 unmodified lines
77
88 #include "intel_engine.h"
99 #include "intel_gt.h"
10−#include "intel_lrc_reg.h"
10+#include "intel_gt_regs.h"
1111 #include "intel_mocs.h"
1212 #include "intel_ring.h"
1313
drivers/gpu/drm/i915/gt/intel_rc6.c+9−7
@@ -6,9 +6,12 @@ · 5 unmodified lines
66 #include <linux/pm_runtime.h>
77
88 #include "i915_drv.h"
9+#include "i915_reg.h"
910 #include "i915_vgpu.h"
11+#include "intel_engine_regs.h"
1012 #include "intel_gt.h"
1113 #include "intel_gt_pm.h"
14+#include "intel_gt_regs.h"
1215 #include "intel_pcode.h"
1316 #include "intel_rc6.h"
1417
@@ -267,8 +270,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6) · 252 unmodified lines
267270 GEN6_RC_CTL_HW_ENABLE;
268271
269272 rc6vids = 0;
270− ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
271− &rc6vids, NULL);
273+ ret = snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
272274 if (GRAPHICS_VER(i915) == 6 && ret) {
273275 drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
274276 } else if (GRAPHICS_VER(i915) == 6 &&
@@ -278,7 +280,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6) · 3 unmodified lines
278280 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
279281 rc6vids &= 0xffff00;
280282 rc6vids |= GEN6_ENCODE_RC6_VID(450);
281− ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
283+ ret = snb_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
282284 if (ret)
283285 drm_err(&i915->drm,
284286 "Couldn't fix incorrect rc6 voltage\n");
@@ -449,10 +451,10 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6) · 164 unmodified lines
449451 enable_rc6 = false;
450452 }
451453
452− if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 &&
453− (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 &&
454− (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 &&
455− (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) {
454+ if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
455+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
456+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
457+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {
456458 drm_dbg(&i915->drm,
457459 "Engine Idle wait time not set properly.\n");
458460 enable_rc6 = false;
drivers/gpu/drm/i915/gt/intel_rc6.h+1−1
@@ -6,7 +6,7 @@ · 5 unmodified lines
66 #ifndef INTEL_RC6_H
77 #define INTEL_RC6_H
88
9−#include "i915_reg.h"
9+#include "i915_reg_defs.h"
1010
1111 struct intel_engine_cs;
1212 struct intel_rc6;
drivers/gpu/drm/i915/gt/intel_region_lmem.c+1−0
@@ -4,6 +4,7 @@ · 3 unmodified lines
44 */
55
66 #include "i915_drv.h"
7+#include "i915_reg.h"
78 #include "intel_memory_region.h"
89 #include "intel_region_lmem.h"
910 #include "intel_region_ttm.h"
drivers/gpu/drm/i915/gt/intel_reset.c+4−0
@@ -11,14 +11,18 @@ · 10 unmodified lines
1111
1212 #include "gem/i915_gem_context.h"
1313
14+#include "gt/intel_gt_regs.h"
15+
1416 #include "i915_drv.h"
1517 #include "i915_gpu_error.h"
1618 #include "i915_irq.h"
1719 #include "intel_breadcrumbs.h"
1820 #include "intel_engine_pm.h"
21+#include "intel_engine_regs.h"
1922 #include "intel_gt.h"
2023 #include "intel_gt_pm.h"
2124 #include "intel_gt_requests.h"
25+#include "intel_pci_config.h"
2226 #include "intel_reset.h"
2327
2428 #include "uc/intel_guc.h"
drivers/gpu/drm/i915/gt/intel_ring.c+1−0
@@ -9,6 +9,7 @@ · 8 unmodified lines
99 #include "i915_drv.h"
1010 #include "i915_vma.h"
1111 #include "intel_engine.h"
12+#include "intel_engine_regs.h"
1213 #include "intel_gpu_commands.h"
1314 #include "intel_ring.h"
1415 #include "intel_timeline.h"
drivers/gpu/drm/i915/gt/intel_ring_submission.c+7−5
@@ -11,8 +11,10 @@ · 10 unmodified lines
1111 #include "i915_mitigations.h"
1212 #include "intel_breadcrumbs.h"
1313 #include "intel_context.h"
14+#include "intel_engine_regs.h"
1415 #include "intel_gt.h"
1516 #include "intel_gt_irq.h"
17+#include "intel_gt_regs.h"
1618 #include "intel_reset.h"
1719 #include "intel_ring.h"
1820 #include "shmem_utils.h"
@@ -1002,15 +1004,15 @@ static void gen6_bsd_submit_request(struct i915_request *request) · 983 unmodified lines
10021004 /* Disable notification that the ring is IDLE. The GT
10031005 * will then assume that it is busy and bring it out of rc6.
10041006 */
1005− intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
1006− _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1007+ intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
1008+ _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
10071009
10081010 /* Clear the context id. Here be magic! */
10091011 intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);
10101012
10111013 /* Wait for the ring not to be idle, i.e. for it to wake up. */
10121014 if (__intel_wait_for_register_fw(uncore,
1013− GEN6_BSD_SLEEP_PSMI_CONTROL,
1015+ RING_PSMI_CTL(GEN6_BSD_RING_BASE),
10141016 GEN6_BSD_SLEEP_INDICATOR,
10151017 0,
10161018 1000, 0, NULL))
@@ -1023,8 +1025,8 @@ static void gen6_bsd_submit_request(struct i915_request *request) · 6 unmodified lines
10231025 /* Let the ring send IDLE messages to the GT again,
10241026 * and so let it sleep to conserve power when idle.
10251027 */
1026− intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
1027− _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1028+ intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
1029+ _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
10281030
10291031 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
10301032 }
drivers/gpu/drm/i915/gt/intel_rps.c+5−5
@@ -6,11 +6,13 @@ · 5 unmodified lines
66 #include <drm/i915_drm.h>
77
88 #include "i915_drv.h"
9+#include "i915_irq.h"
910 #include "intel_breadcrumbs.h"
1011 #include "intel_gt.h"
1112 #include "intel_gt_clock_utils.h"
1213 #include "intel_gt_irq.h"
1314 #include "intel_gt_pm_irq.h"
15+#include "intel_gt_regs.h"
1416 #include "intel_pcode.h"
1517 #include "intel_rps.h"
1618 #include "vlv_sideband.h"
@@ -1090,9 +1092,8 @@ static void gen6_rps_init(struct intel_rps *rps) · 1073 unmodified lines
10901092 IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
10911093 u32 ddcc_status = 0;
10921094
1093− if (sandybridge_pcode_read(i915,
1094− HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
1095− &ddcc_status, NULL) == 0)
1095+ if (snb_pcode_read(i915, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
1096+ &ddcc_status, NULL) == 0)
10961097 rps->efficient_freq =
10971098 clamp_t(u8,
10981099 (ddcc_status >> 8) & 0xff,
@@ -1940,8 +1941,7 @@ void intel_rps_init(struct intel_rps *rps) · 841 unmodified lines
19401941 if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
19411942 u32 params = 0;
19421943
1943− sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
1944− &params, NULL);
1944+ snb_pcode_read(i915, GEN6_READ_OC_PARAMS, &params, NULL);
19451945 if (params & BIT(31)) { /* OC supported */
19461946 drm_dbg(&i915->drm,
19471947 "Overclocking supported, max: %dMHz, overclock: %dMHz\n",
drivers/gpu/drm/i915/gt/intel_sseu.c+2−1
@@ -4,7 +4,8 @@ · 3 unmodified lines
44 */
55
66 #include "i915_drv.h"
7−#include "intel_lrc_reg.h"
7+#include "intel_engine_regs.h"
8+#include "intel_gt_regs.h"
89 #include "intel_sseu.h"
910
1011 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c+1−0
@@ -6,6 +6,7 @@ · 5 unmodified lines
66
77 #include "i915_drv.h"
88 #include "intel_gt_debugfs.h"
9+#include "intel_gt_regs.h"
910 #include "intel_sseu_debugfs.h"
1011
1112 static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
drivers/gpu/drm/i915/gt/intel_workarounds.c+5−3
@@ -6,8 +6,10 @@ · 5 unmodified lines
66 #include "i915_drv.h"
77 #include "intel_context.h"
88 #include "intel_engine_pm.h"
9+#include "intel_engine_regs.h"
910 #include "intel_gpu_commands.h"
1011 #include "intel_gt.h"
12+#include "intel_gt_regs.h"
1113 #include "intel_ring.h"
1214 #include "intel_workarounds.h"
1315
@@ -2208,7 +2210,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) · 2194 unmodified lines
22082210 * For DG1 this only applies to A0.
22092211 */
22102212 wa_masked_en(wal,
2211− GEN6_RC_SLEEP_PSMI_CONTROL,
2213+ RING_PSMI_CTL(RENDER_RING_BASE),
22122214 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
22132215 GEN8_RC_SEMA_IDLE_MSG_DISABLE);
22142216 }
@@ -2423,7 +2425,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) · 208 unmodified lines
24232425 if (GRAPHICS_VER(i915) == 7) {
24242426 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
24252427 wa_masked_en(wal,
2426− GFX_MODE_GEN7,
2428+ RING_MODE_GEN7(RENDER_RING_BASE),
24272429 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
24282430
24292431 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */
@@ -2536,7 +2538,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) · 106 unmodified lines
25362538 * they are already accustomed to from before contexts were
25372539 * enabled.
25382540 */
2539− wa_add(wal, ECOSKPD,
2541+ wa_add(wal, ECOSKPD(RENDER_RING_BASE),
25402542 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
25412543 0 /* XXX bit doesn't stick on Broadwater */,
25422544 true);
drivers/gpu/drm/i915/gt/intel_workarounds_types.h+1−1
@@ -8,7 +8,7 @@ · 7 unmodified lines
88
99 #include <linux/types.h>
1010
11−#include "i915_reg.h"
11+#include "i915_reg_defs.h"
1212
1313 struct i915_wa {
1414 i915_reg_t reg;
drivers/gpu/drm/i915/gt/selftest_engine_pm.c+1−0
@@ -6,6 +6,7 @@ · 5 unmodified lines
66 #include <linux/sort.h>
77
88 #include "i915_selftest.h"
9+#include "intel_engine_regs.h"
910 #include "intel_gpu_commands.h"
1011 #include "intel_gt_clock_utils.h"
1112 #include "selftest_engine.h"
drivers/gpu/drm/i915/gt/selftest_gt_pm.c+1−0
@@ -5,6 +5,7 @@ · 4 unmodified lines
55
66 #include <linux/sort.h>
77
8+#include "intel_engine_regs.h"
89 #include "intel_gt_clock_utils.h"
910
1011 #include "selftest_llc.h"
drivers/gpu/drm/i915/gt/selftest_hangcheck.c+1−0
@@ -7,6 +7,7 @@ · 6 unmodified lines
77
88 #include "gem/i915_gem_context.h"
99
10+#include "i915_gem_evict.h"
1011 #include "intel_gt.h"
1112 #include "intel_engine_heartbeat.h"
1213 #include "intel_engine_pm.h"
drivers/gpu/drm/i915/gt/selftest_llc.c+2−3
@@ -31,9 +31,8 @@ static int gen6_verify_ring_freq(struct intel_llc *llc) · 30 unmodified lines
3131 calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
3232
3333 val = gpu_freq;
34− if (sandybridge_pcode_read(i915,
35− GEN6_PCODE_READ_MIN_FREQ_TABLE,
36− &val, NULL)) {
34+ if (snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
35+ &val, NULL)) {
3736 pr_err("Failed to read freq table[%d], range [%d, %d]\n",
3837 gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq);
3938 err = -ENXIO;
drivers/gpu/drm/i915/gt/selftest_rps.c+3−3
@@ -8,6 +8,7 @@ · 7 unmodified lines
88
99 #include "intel_engine_heartbeat.h"
1010 #include "intel_engine_pm.h"
11+#include "intel_engine_regs.h"
1112 #include "intel_gpu_commands.h"
1213 #include "intel_gt_clock_utils.h"
1314 #include "intel_gt_pm.h"
@@ -518,9 +519,8 @@ static void show_pcu_config(struct intel_rps *rps) · 504 unmodified lines
518519 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
519520 int ia_freq = gpu_freq;
520521
521− sandybridge_pcode_read(i915,
522− GEN6_PCODE_READ_MIN_FREQ_TABLE,
523− &ia_freq, NULL);
522+ snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
523+ &ia_freq, NULL);
524524
525525 pr_info("%5d %5d %5d\n",
526526 gpu_freq * 50,
drivers/gpu/drm/i915/gt/selftest_timeline.c+1−0
@@ -8,6 +8,7 @@ · 7 unmodified lines
88 #include "intel_context.h"
99 #include "intel_engine_heartbeat.h"
1010 #include "intel_engine_pm.h"
11+#include "intel_engine_regs.h"
1112 #include "intel_gpu_commands.h"
1213 #include "intel_gt.h"
1314 #include "intel_gt_requests.h"
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h+0−1
@@ -7,7 +7,6 @@ · 6 unmodified lines
77 #define _GUC_ACTIONS_SLPC_ABI_H_
88
99 #include <linux/types.h>
10−#include "i915_reg.h"
1110
1211 /**
1312 * DOC: SLPC SHARED DATA STRUCTURE
drivers/gpu/drm/i915/gt/uc/intel_guc.c+2−0
@@ -7,11 +7,13 @@ · 6 unmodified lines
77 #include "gt/intel_gt.h"
88 #include "gt/intel_gt_irq.h"
99 #include "gt/intel_gt_pm_irq.h"
10+#include "gt/intel_gt_regs.h"
1011 #include "intel_guc.h"
1112 #include "intel_guc_slpc.h"
1213 #include "intel_guc_ads.h"
1314 #include "intel_guc_submission.h"
1415 #include "i915_drv.h"
16+#include "i915_irq.h"
1517
1618 /**
1719 * DOC: GuC
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c+2−0
@@ -5,7 +5,9 @@ · 4 unmodified lines
55
66 #include <linux/bsearch.h>
77
8+#include "gt/intel_engine_regs.h"
89 #include "gt/intel_gt.h"
10+#include "gt/intel_gt_regs.h"
911 #include "gt/intel_lrc.h"
1012 #include "gt/shmem_utils.h"
1113 #include "intel_guc_ads.h"
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c+1−0
@@ -10,6 +10,7 @@ · 9 unmodified lines
1010 */
1111
1212 #include "gt/intel_gt.h"
13+#include "gt/intel_gt_regs.h"
1314 #include "intel_guc_fw.h"
1415 #include "i915_drv.h"
1516
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c+1−0
@@ -7,6 +7,7 @@ · 6 unmodified lines
77
88 #include "gt/intel_gt.h"
99 #include "i915_drv.h"
10+#include "i915_irq.h"
1011 #include "i915_memcpy.h"
1112 #include "intel_guc_log.h"
1213
drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h+1−1
@@ -9,7 +9,7 @@ · 8 unmodified lines
99 #include <linux/compiler.h>
1010 #include <linux/types.h>
1111
12−#include "i915_reg.h"
12+#include "i915_reg_defs.h"
1313
1414 /* Definitions of GuC H/W registers, bits, etc */
1515
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c+2−0
@@ -4,8 +4,10 @@ · 3 unmodified lines
44 */
55
66 #include "i915_drv.h"
7+#include "i915_reg.h"
78 #include "intel_guc_slpc.h"
89 #include "gt/intel_gt.h"
10+#include "gt/intel_gt_regs.h"
911
1012 static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
1113 {
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c+3−1
@@ -9,13 +9,15 @@ · 8 unmodified lines
99 #include "gt/gen8_engine_cs.h"
1010 #include "gt/intel_breadcrumbs.h"
1111 #include "gt/intel_context.h"
12−#include "gt/intel_engine_pm.h"
1312 #include "gt/intel_engine_heartbeat.h"
13+#include "gt/intel_engine_pm.h"
14+#include "gt/intel_engine_regs.h"
1415 #include "gt/intel_gpu_commands.h"
1516 #include "gt/intel_gt.h"
1617 #include "gt/intel_gt_clock_utils.h"
1718 #include "gt/intel_gt_irq.h"
1819 #include "gt/intel_gt_pm.h"
20+#include "gt/intel_gt_regs.h"
1921 #include "gt/intel_gt_requests.h"
2022 #include "gt/intel_lrc.h"
2123 #include "gt/intel_lrc_reg.h"
drivers/gpu/drm/i915/gt/uc/intel_huc.h+1−1
@@ -6,7 +6,7 @@ · 5 unmodified lines
66 #ifndef _INTEL_HUC_H_
77 #define _INTEL_HUC_H_
88
9−#include "i915_reg.h"
9+#include "i915_reg_defs.h"
1010 #include "intel_uc_fw.h"
1111 #include "intel_huc_fw.h"
1212
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c+1−0
@@ -11,6 +11,7 @@ · 10 unmodified lines
1111 #include "intel_uc_fw.h"
1212 #include "intel_uc_fw_abi.h"
1313 #include "i915_drv.h"
14+#include "i915_reg.h"
1415
1516 static inline struct intel_gt *
1617 ____uc_fw_to_gt(struct intel_uc_fw *uc_fw, enum intel_uc_fw_type type)
drivers/gpu/drm/i915/gvt/aperture_gm.c+1−0
@@ -35,6 +35,7 @@ · 34 unmodified lines
3535 */
3636
3737 #include "i915_drv.h"
38+#include "i915_reg.h"
3839 #include "gt/intel_ggtt_fencing.h"
3940 #include "gvt.h"
4041
drivers/gpu/drm/i915/gvt/cmd_parser.c+3−1
@@ -37,7 +37,9 @@ · 36 unmodified lines
3737 #include <linux/slab.h>
3838
3939 #include "i915_drv.h"
40+#include "gt/intel_engine_regs.h"
4041 #include "gt/intel_gpu_commands.h"
42+#include "gt/intel_gt_regs.h"
4143 #include "gt/intel_lrc.h"
4244 #include "gt/intel_ring.h"
4345 #include "gt/intel_gt_requests.h"
@@ -1144,7 +1146,7 @@ struct cmd_interrupt_event { · 1100 unmodified lines
11441146 int mi_user_interrupt;
11451147 };
11461148
1147−static struct cmd_interrupt_event cmd_interrupt_events[] = {
1149+static const struct cmd_interrupt_event cmd_interrupt_events[] = {
11481150 [RCS0] = {
11491151 .pipe_control_notify = RCS_PIPE_CONTROL,
11501152 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
drivers/gpu/drm/i915/gvt/display.c+9−8
@@ -33,6 +33,7 @@ · 32 unmodified lines
3333 */
3434
3535 #include "i915_drv.h"
36+#include "i915_reg.h"
3637 #include "gvt.h"
3738
3839 static int get_edp_pipe(struct intel_vgpu *vgpu)
@@ -184,10 +185,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) · 145 unmodified lines
184185
185186 for_each_pipe(dev_priv, pipe) {
186187 vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
187− ~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
188− vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
188+ ~(PIPECONF_ENABLE | PIPECONF_STATE_ENABLE);
189+ vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
189190 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
190− vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
191+ vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
191192 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
192193 }
193194
@@ -245,7 +246,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) · 51 unmodified lines
245246 * setup_virtual_dp_monitor.
246247 */
247248 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
248− vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;
249+ vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE;
249250
250251 /*
251252 * Golden M/N are calculated based on:
@@ -253,7 +254,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) · 1 unmodified line
253254 * DP link clk 1620 MHz and non-constant_n.
254255 * TODO: calculate DP link symbol clk and stream clk m/n.
255256 */
256− vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
257+ vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
257258 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
258259 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
259260 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
@@ -387,7 +388,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) · 127 unmodified lines
387388 * DP link clk 1620 MHz and non-constant_n.
388389 * TODO: calculate DP link symbol clk and stream clk m/n.
389390 */
390− vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
391+ vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
391392 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
392393 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
393394 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
@@ -496,9 +497,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) · 102 unmodified lines
496497
497498 /* Disable Primary/Sprite/Cursor plane */
498499 for_each_pipe(dev_priv, pipe) {
499− vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
500+ vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
500501 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
501− vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
502+ vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
502503 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
503504 }
504505
drivers/gpu/drm/i915/gvt/dmabuf.c+6−13
@@ -32,6 +32,7 @@ · 31 unmodified lines
3232 #include <linux/vfio.h>
3333
3434 #include "i915_drv.h"
35+#include "i915_reg.h"
3536 #include "gvt.h"
3637
3738 #define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12))
@@ -148,8 +149,7 @@ static void dmabuf_gem_object_free(struct kref *kref) · 110 unmodified lines
148149
149150 if (vgpu && vgpu->active && !list_empty(&vgpu->dmabuf_obj_list_head)) {
150151 list_for_each(pos, &vgpu->dmabuf_obj_list_head) {
151− dmabuf_obj = container_of(pos,
152− struct intel_vgpu_dmabuf_obj, list);
152+ dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj, list);
153153 if (dmabuf_obj == obj) {
154154 list_del(pos);
155155 intel_gvt_hypervisor_put_vfio_device(vgpu);
@@ -357,10 +357,8 @@ pick_dmabuf_by_info(struct intel_vgpu *vgpu, · 201 unmodified lines
357357 struct intel_vgpu_dmabuf_obj *ret = NULL;
358358
359359 list_for_each(pos, &vgpu->dmabuf_obj_list_head) {
360− dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
361− list);
362− if ((dmabuf_obj == NULL) ||
363− (dmabuf_obj->info == NULL))
360+ dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj, list);
361+ if (!dmabuf_obj->info)
364362 continue;
365363
366364 fb_info = (struct intel_vgpu_fb_info *)dmabuf_obj->info;
@@ -387,11 +385,7 @@ pick_dmabuf_by_num(struct intel_vgpu *vgpu, u32 id) · 20 unmodified lines
387385 struct intel_vgpu_dmabuf_obj *ret = NULL;
388386
389387 list_for_each(pos, &vgpu->dmabuf_obj_list_head) {
390− dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
391− list);
392− if (!dmabuf_obj)
393− continue;
394−
388+ dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj, list);
395389 if (dmabuf_obj->dmabuf_id == id) {
396390 ret = dmabuf_obj;
397391 break;
@@ -600,8 +594,7 @@ void intel_vgpu_dmabuf_cleanup(struct intel_vgpu *vgpu) · 202 unmodified lines
600594
601595 mutex_lock(&vgpu->dmabuf_lock);
602596 list_for_each_safe(pos, n, &vgpu->dmabuf_obj_list_head) {
603− dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj,
604− list);
597+ dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj, list);
605598 dmabuf_obj->vgpu = NULL;
606599
607600 idr_remove(&vgpu->object_idr, dmabuf_obj->dmabuf_id);
drivers/gpu/drm/i915/gvt/edid.c+1−0
@@ -33,6 +33,7 @@ · 32 unmodified lines
3333 */
3434
3535 #include "i915_drv.h"
36+#include "i915_reg.h"
3637 #include "gvt.h"
3738
3839 #define GMBUS1_TOTAL_BYTES_SHIFT 16
drivers/gpu/drm/i915/gvt/fb_decoder.c+25−24
@@ -37,15 +37,16 @@ · 36 unmodified lines
3737 #include "i915_drv.h"
3838 #include "gvt.h"
3939 #include "i915_pvinfo.h"
40+#include "i915_reg.h"
4041
4142 #define PRIMARY_FORMAT_NUM 16
4243 struct pixel_format {
43− int drm_format; /* Pixel format in DRM definition */
44− int bpp; /* Bits per pixel, 0 indicates invalid */
45− char *desc; /* The description */
44+ int drm_format; /* Pixel format in DRM definition */
45+ int bpp; /* Bits per pixel, 0 indicates invalid */
46+ const char *desc; /* The description */
4647 };
4748
48−static struct pixel_format bdw_pixel_formats[] = {
49+static const struct pixel_format bdw_pixel_formats[] = {
4950 {DRM_FORMAT_C8, 8, "8-bit Indexed"},
5051 {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
5152 {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
@@ -58,7 +59,7 @@ static struct pixel_format bdw_pixel_formats[] = { · 6 unmodified lines
5859 {0, 0, NULL},
5960 };
6061
61−static struct pixel_format skl_pixel_formats[] = {
62+static const struct pixel_format skl_pixel_formats[] = {
6263 {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
6364 {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
6465 {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
@@ -83,22 +84,22 @@ static int bdw_format_to_drm(int format) · 18 unmodified lines
8384 int bdw_pixel_formats_index = 6;
8485
8586 switch (format) {
86− case DISPPLANE_8BPP:
87+ case DISP_FORMAT_8BPP:
8788 bdw_pixel_formats_index = 0;
8889 break;
89− case DISPPLANE_BGRX565:
90+ case DISP_FORMAT_BGRX565:
9091 bdw_pixel_formats_index = 1;
9192 break;
92− case DISPPLANE_BGRX888:
93+ case DISP_FORMAT_BGRX888:
9394 bdw_pixel_formats_index = 2;
9495 break;
95− case DISPPLANE_RGBX101010:
96+ case DISP_FORMAT_RGBX101010:
9697 bdw_pixel_formats_index = 3;
9798 break;
98− case DISPPLANE_BGRX101010:
99+ case DISP_FORMAT_BGRX101010:
99100 bdw_pixel_formats_index = 4;
100101 break;
101− case DISPPLANE_RGBX888:
102+ case DISP_FORMAT_RGBX888:
102103 bdw_pixel_formats_index = 5;
103104 break;
104105
@@ -211,14 +212,14 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, · 106 unmodified lines
211212 return -ENODEV;
212213
213214 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
214− plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
215+ plane->enabled = !!(val & DISP_ENABLE);
215216 if (!plane->enabled)
216217 return -ENODEV;
217218
218219 if (GRAPHICS_VER(dev_priv) >= 9) {
219220 plane->tiled = val & PLANE_CTL_TILED_MASK;
220221 fmt = skl_format_to_drm(
221− val & PLANE_CTL_FORMAT_MASK,
222+ val & PLANE_CTL_FORMAT_MASK_SKL,
222223 val & PLANE_CTL_ORDER_RGBX,
223224 val & PLANE_CTL_ALPHA_MASK,
224225 val & PLANE_CTL_YUV422_ORDER_MASK);
@@ -231,8 +232,8 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, · 6 unmodified lines
231232 plane->bpp = skl_pixel_formats[fmt].bpp;
232233 plane->drm_format = skl_pixel_formats[fmt].drm_format;
233234 } else {
234− plane->tiled = val & DISPPLANE_TILED;
235− fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
235+ plane->tiled = val & DISP_TILED;
236+ fmt = bdw_format_to_drm(val & DISP_FORMAT_MASK);
236237 plane->bpp = bdw_pixel_formats[fmt].bpp;
237238 plane->drm_format = bdw_pixel_formats[fmt].drm_format;
238239 }
@@ -278,14 +279,14 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, · 39 unmodified lines
278279
279280 #define CURSOR_FORMAT_NUM (1 << 6)
280281 struct cursor_mode_format {
281− int drm_format; /* Pixel format in DRM definition */
282− u8 bpp; /* Bits per pixel; 0 indicates invalid */
283− u32 width; /* In pixel */
284− u32 height; /* In lines */
285− char *desc; /* The description */
282+ int drm_format; /* Pixel format in DRM definition */
283+ u8 bpp; /* Bits per pixel; 0 indicates invalid */
284+ u32 width; /* In pixel */
285+ u32 height; /* In lines */
286+ const char *desc; /* The description */
286287 };
287288
288−static struct cursor_mode_format cursor_pixel_formats[] = {
289+static const struct cursor_mode_format cursor_pixel_formats[] = {
289290 {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
290291 {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
291292 {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
@@ -342,7 +343,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, · 50 unmodified lines
342343 return -ENODEV;
343344
344345 val = vgpu_vreg_t(vgpu, CURCNTR(pipe));
345− mode = val & MCURSOR_MODE;
346+ mode = val & MCURSOR_MODE_MASK;
346347 plane->enabled = (mode != MCURSOR_MODE_DISABLE);
347348 if (!plane->enabled)
348349 return -ENODEV;
@@ -391,7 +392,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, · 42 unmodified lines
391392
392393 #define SPRITE_FORMAT_NUM (1 << 3)
393394
394−static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
395+static const struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
395396 [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
396397 [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
397398 [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
@@ -430,7 +431,7 @@ int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, · 32 unmodified lines
430431 yuv_order = (val & SPRITE_YUV_ORDER_MASK) >>
431432 _SPRITE_YUV_ORDER_SHIFT;
432433
433− fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT;
434+ fmt = (val & SPRITE_FORMAT_MASK) >> _SPRITE_FMT_SHIFT;
434435 if (!sprite_pixel_formats[fmt].bpp) {
435436 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
436437 return -EINVAL;
drivers/gpu/drm/i915/gvt/gtt.c+36−34
@@ -38,6 +38,8 @@ · 37 unmodified lines
3838 #include "i915_pvinfo.h"
3939 #include "trace.h"
4040
41+#include "gt/intel_gt_regs.h"
42+
4143 #if defined(VERBOSE_DEBUG)
4244 #define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
4345 #else
@@ -185,7 +187,7 @@ struct gtt_type_table_entry { · 141 unmodified lines
185187 .pse_entry_type = pse_type, \
186188 }
187189
188−static struct gtt_type_table_entry gtt_type_table[] = {
190+static const struct gtt_type_table_entry gtt_type_table[] = {
189191 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
190192 GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
191193 GTT_TYPE_INVALID,
@@ -499,7 +501,7 @@ DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3)); · 307 unmodified lines
499501 DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
500502 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
501503
502−static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
504+static const struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
503505 .get_entry = gtt_get_entry64,
504506 .set_entry = gtt_set_entry64,
505507 .clear_present = gtt_entry_clear_present,
@@ -516,7 +518,7 @@ static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = { · 10 unmodified lines
516518 .set_pfn = gen8_gtt_set_pfn,
517519 };
518520
519−static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
521+static const struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
520522 .gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
521523 .gma_to_pte_index = gen8_gma_to_pte_index,
522524 .gma_to_pde_index = gen8_gma_to_pde_index,
@@ -526,7 +528,7 @@ static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = { · 3 unmodified lines
526528 };
527529
528530 /* Update entry type per pse and ips bit. */
529−static void update_entry_type_for_real(struct intel_gvt_gtt_pte_ops *pte_ops,
531+static void update_entry_type_for_real(const struct intel_gvt_gtt_pte_ops *pte_ops,
530532 struct intel_gvt_gtt_entry *entry, bool ips)
531533 {
532534 switch (entry->type) {
@@ -553,7 +555,7 @@ static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm, · 20 unmodified lines
553555 struct intel_gvt_gtt_entry *entry, unsigned long index,
554556 bool guest)
555557 {
556− struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
558+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
557559
558560 GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
559561
@@ -580,7 +582,7 @@ static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm, · 20 unmodified lines
580582 struct intel_gvt_gtt_entry *entry, unsigned long index,
581583 bool guest)
582584 {
583− struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
585+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
584586
585587 pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
586588 mm->ppgtt_mm.shadow_pdps,
@@ -596,7 +598,7 @@ static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm, · 9 unmodified lines
596598 static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
597599 struct intel_gvt_gtt_entry *entry, unsigned long index)
598600 {
599− struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
601+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
600602
601603 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
602604
@@ -608,7 +610,7 @@ static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm, · 5 unmodified lines
608610 static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
609611 struct intel_gvt_gtt_entry *entry, unsigned long index)
610612 {
611− struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
613+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
612614
613615 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
614616
@@ -619,7 +621,7 @@ static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm, · 4 unmodified lines
619621 static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
620622 struct intel_gvt_gtt_entry *entry, unsigned long index)
621623 {
622− struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
624+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
623625
624626 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
625627
@@ -629,7 +631,7 @@ static void ggtt_get_host_entry(struct intel_vgpu_mm *mm, · 3 unmodified lines
629631 static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
630632 struct intel_gvt_gtt_entry *entry, unsigned long index)
631633 {
632− struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
634+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
633635 unsigned long offset = index;
634636
635637 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
@@ -655,7 +657,7 @@ static inline int ppgtt_spt_get_entry( · 19 unmodified lines
655657 bool guest)
656658 {
657659 struct intel_gvt *gvt = spt->vgpu->gvt;
658− struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
660+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
659661 int ret;
660662
661663 e->type = get_entry_type(type);
@@ -684,7 +686,7 @@ static inline int ppgtt_spt_set_entry( · 22 unmodified lines
684686 bool guest)
685687 {
686688 struct intel_gvt *gvt = spt->vgpu->gvt;
687− struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
689+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
688690
689691 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
690692 return -EINVAL;
@@ -947,7 +949,7 @@ static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu, · 256 unmodified lines
947949 struct intel_gvt_gtt_entry *e)
948950 {
949951 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
950− struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
952+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
951953 struct intel_vgpu_ppgtt_spt *s;
952954 enum intel_gvt_gtt_type cur_pt_type;
953955
@@ -984,7 +986,7 @@ static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt, · 30 unmodified lines
984986 struct intel_gvt_gtt_entry *entry)
985987 {
986988 struct intel_vgpu *vgpu = spt->vgpu;
987− struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
989+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
988990 unsigned long pfn;
989991 int type;
990992
@@ -1072,7 +1074,7 @@ static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt); · 81 unmodified lines
10721074 static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
10731075 struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
10741076 {
1075− struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1077+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
10761078 struct intel_vgpu_ppgtt_spt *spt = NULL;
10771079 bool ips = false;
10781080 int ret;
@@ -1136,7 +1138,7 @@ err: · 57 unmodified lines
11361138 static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
11371139 struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
11381140 {
1139− struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
1141+ const struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
11401142
11411143 se->type = ge->type;
11421144 se->val64 = ge->val64;
@@ -1159,7 +1161,7 @@ static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se, · 16 unmodified lines
11591161 static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
11601162 struct intel_gvt_gtt_entry *entry)
11611163 {
1162− struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1164+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
11631165 unsigned long pfn;
11641166
11651167 if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M))
@@ -1176,7 +1178,7 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu, · 10 unmodified lines
11761178 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
11771179 struct intel_gvt_gtt_entry *se)
11781180 {
1179− struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1181+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
11801182 struct intel_vgpu_ppgtt_spt *sub_spt;
11811183 struct intel_gvt_gtt_entry sub_se;
11821184 unsigned long start_gfn;
@@ -1223,7 +1225,7 @@ static int split_64KB_gtt_entry(struct intel_vgpu *vgpu, · 40 unmodified lines
12231225 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
12241226 struct intel_gvt_gtt_entry *se)
12251227 {
1226− struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1228+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
12271229 struct intel_gvt_gtt_entry entry = *se;
12281230 unsigned long start_gfn;
12291231 dma_addr_t dma_addr;
@@ -1254,7 +1256,7 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu, · 24 unmodified lines
12541256 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
12551257 struct intel_gvt_gtt_entry *ge)
12561258 {
1257− struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
1259+ const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
12581260 struct intel_gvt_gtt_entry se = *ge;
12591261 unsigned long gfn, page_size = PAGE_SIZE;
12601262 dma_addr_t dma_addr;
@@ -1308,7 +1310,7 @@ static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt) · 47 unmodified lines
13081310 {
13091311 struct intel_vgpu *vgpu = spt->vgpu;
13101312 struct intel_gvt *gvt = vgpu->gvt;
1311− struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1313+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
13121314 struct intel_vgpu_ppgtt_spt *s;
13131315 struct intel_gvt_gtt_entry se, ge;
13141316 unsigned long gfn, i;
@@ -1351,7 +1353,7 @@ static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt, · 36 unmodified lines
13511353 struct intel_gvt_gtt_entry *se, unsigned long index)
13521354 {
13531355 struct intel_vgpu *vgpu = spt->vgpu;
1354− struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1356+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
13551357 int ret;
13561358
13571359 trace_spt_guest_change(spt->vgpu->id, "remove", spt,
@@ -1432,7 +1434,7 @@ static int sync_oos_page(struct intel_vgpu *vgpu, · 74 unmodified lines
14321434 {
14331435 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
14341436 struct intel_gvt *gvt = vgpu->gvt;
1435− struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1437+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
14361438 struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
14371439 struct intel_gvt_gtt_entry old, new;
14381440 int index;
@@ -1603,7 +1605,7 @@ static int ppgtt_handle_guest_write_page_table( · 164 unmodified lines
16031605 {
16041606 struct intel_vgpu *vgpu = spt->vgpu;
16051607 int type = spt->shadow_page.type;
1606− struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1608+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
16071609 struct intel_gvt_gtt_entry old_se;
16081610 int new_present;
16091611 int i, ret;
@@ -1720,7 +1722,7 @@ static int ppgtt_handle_guest_write_page_table_bytes( · 110 unmodified lines
17201722 u64 pa, void *p_data, int bytes)
17211723 {
17221724 struct intel_vgpu *vgpu = spt->vgpu;
1723− struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1725+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
17241726 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
17251727 struct intel_gvt_gtt_entry we, se;
17261728 unsigned long index;
@@ -1785,7 +1787,7 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm) · 58 unmodified lines
17851787 struct intel_vgpu *vgpu = mm->vgpu;
17861788 struct intel_gvt *gvt = vgpu->gvt;
17871789 struct intel_gvt_gtt *gtt = &gvt->gtt;
1788− struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1790+ const struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
17891791 struct intel_gvt_gtt_entry se;
17901792 int index;
17911793
@@ -1815,7 +1817,7 @@ static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm) · 23 unmodified lines
18151817 struct intel_vgpu *vgpu = mm->vgpu;
18161818 struct intel_gvt *gvt = vgpu->gvt;
18171819 struct intel_gvt_gtt *gtt = &gvt->gtt;
1818− struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1820+ const struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
18191821 struct intel_vgpu_ppgtt_spt *spt;
18201822 struct intel_gvt_gtt_entry ge, se;
18211823 int index, ret;
@@ -2067,7 +2069,7 @@ static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm *mm, · 245 unmodified lines
20672069 struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
20682070 {
20692071 struct intel_vgpu *vgpu = mm->vgpu;
2070− struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2072+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
20712073 struct intel_vgpu_ppgtt_spt *s;
20722074
20732075 s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
@@ -2096,8 +2098,8 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) · 22 unmodified lines
20962098 {
20972099 struct intel_vgpu *vgpu = mm->vgpu;
20982100 struct intel_gvt *gvt = vgpu->gvt;
2099− struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
2100− struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
2101+ const struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
2102+ const struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
21012103 unsigned long gpa = INTEL_GVT_INVALID_ADDR;
21022104 unsigned long gma_index[4];
21032105 struct intel_gvt_gtt_entry e;
@@ -2221,7 +2223,7 @@ int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, unsigned int off, · 117 unmodified lines
22212223 static void ggtt_invalidate_pte(struct intel_vgpu *vgpu,
22222224 struct intel_gvt_gtt_entry *entry)
22232225 {
2224− struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2226+ const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
22252227 unsigned long pfn;
22262228
22272229 pfn = pte_ops->get_pfn(entry);
@@ -2236,7 +2238,7 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, · 8 unmodified lines
22362238 struct intel_gvt *gvt = vgpu->gvt;
22372239 const struct intel_gvt_device_info *info = &gvt->device_info;
22382240 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
2239− struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
2241+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
22402242 unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
22412243 unsigned long gma, gfn;
22422244 struct intel_gvt_gtt_entry e = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
@@ -2391,7 +2393,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu, · 148 unmodified lines
23912393 {
23922394 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
23932395 struct intel_vgpu_gtt *gtt = &vgpu->gtt;
2394− struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2396+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
23952397 int page_entry_num = I915_GTT_PAGE_SIZE >>
23962398 vgpu->gvt->device_info.gtt_entry_size_shift;
23972399 void *scratch_pt;
@@ -2822,7 +2824,7 @@ void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu) · 424 unmodified lines
28222824 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
28232825 {
28242826 struct intel_gvt *gvt = vgpu->gvt;
2825− struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2827+ const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
28262828 struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
28272829 struct intel_gvt_gtt_entry old_entry;
28282830 u32 index;
drivers/gpu/drm/i915/gvt/gtt.h+2−2
@@ -91,8 +91,8 @@ struct intel_gvt_gtt_gma_ops { · 90 unmodified lines
9191 };
9292
9393 struct intel_gvt_gtt {
94− struct intel_gvt_gtt_pte_ops *pte_ops;
95− struct intel_gvt_gtt_gma_ops *gma_ops;
94+ const struct intel_gvt_gtt_pte_ops *pte_ops;
95+ const struct intel_gvt_gtt_gma_ops *gma_ops;
9696 int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
9797 void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
9898 struct list_head oos_page_use_list_head;
drivers/gpu/drm/i915/gvt/gvt.h+1−1
@@ -272,7 +272,7 @@ struct intel_gvt_mmio { · 271 unmodified lines
272272 /* Value of command write of this reg needs to be patched */
273273 #define F_CMD_WRITE_PATCH (1 << 8)
274274
275− struct gvt_mmio_block *mmio_block;
275+ const struct gvt_mmio_block *mmio_block;
276276 unsigned int num_mmio_block;
277277
278278 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
drivers/gpu/drm/i915/gvt/handlers.c+20−16
@@ -37,9 +37,12 @@ · 36 unmodified lines
3737 */
3838
3939 #include "i915_drv.h"
40+#include "i915_reg.h"
4041 #include "gvt.h"
4142 #include "i915_pvinfo.h"
4243 #include "display/intel_display_types.h"
44+#include "display/intel_fbc.h"
45+#include "gt/intel_gt_regs.h"
4346
4447 /* XXX FIXME i915 has changed PP_XXX definition */
4548 #define PCH_PP_STATUS _MMIO(0xc7200)
@@ -701,11 +704,11 @@ static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, · 655 unmodified lines
701704 data = vgpu_vreg(vgpu, offset);
702705
703706 if (data & PIPECONF_ENABLE) {
704− vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
707+ vgpu_vreg(vgpu, offset) |= PIPECONF_STATE_ENABLE;
705708 vgpu_update_refresh_rate(vgpu);
706709 vgpu_update_vblank_emulation(vgpu, true);
707710 } else {
708− vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
711+ vgpu_vreg(vgpu, offset) &= ~PIPECONF_STATE_ENABLE;
709712 vgpu_update_vblank_emulation(vgpu, false);
710713 }
711714 return 0;
@@ -2647,12 +2650,12 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) · 1935 unmodified lines
26472650 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
26482651 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
26492652
2650− MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2651− MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2652− MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2653− MMIO_D(ILK_DPFC_STATUS, D_ALL);
2654− MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2655− MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2653+ MMIO_D(ILK_DPFC_CB_BASE(INTEL_FBC_A), D_ALL);
2654+ MMIO_D(ILK_DPFC_CONTROL(INTEL_FBC_A), D_ALL);
2655+ MMIO_D(ILK_DPFC_RECOMP_CTL(INTEL_FBC_A), D_ALL);
2656+ MMIO_D(ILK_DPFC_STATUS(INTEL_FBC_A), D_ALL);
2657+ MMIO_D(ILK_DPFC_FENCE_YOFF(INTEL_FBC_A), D_ALL);
2658+ MMIO_D(ILK_DPFC_CHICKEN(INTEL_FBC_A), D_ALL);
26562659 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
26572660
26582661 MMIO_D(IPS_CTL, D_ALL);
@@ -2876,9 +2879,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) · 217 unmodified lines
28762879
28772880 MMIO_D(_MMIO(0x3c), D_ALL);
28782881 MMIO_D(_MMIO(0x860), D_ALL);
2879− MMIO_D(ECOSKPD, D_ALL);
2882+ MMIO_D(ECOSKPD(RENDER_RING_BASE), D_ALL);
28802883 MMIO_D(_MMIO(0x121d0), D_ALL);
2881− MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2884+ MMIO_D(ECOSKPD(BLT_RING_BASE), D_ALL);
28822885 MMIO_D(_MMIO(0x41d0), D_ALL);
28832886 MMIO_D(GAC_ECO_BITS, D_ALL);
28842887 MMIO_D(_MMIO(0x6200), D_ALL);
@@ -3436,6 +3439,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) · 551 unmodified lines
34363439
34373440 MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
34383441 MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
3442+ MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
34393443
34403444 return 0;
34413445 }
@@ -3627,11 +3631,11 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt) · 185 unmodified lines
36273631 return 0;
36283632 }
36293633
3630−static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
3631− unsigned int offset)
3634+static const struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
3635+ unsigned int offset)
36323636 {
36333637 unsigned long device = intel_gvt_get_device_type(gvt);
3634− struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3638+ const struct gvt_mmio_block *block = gvt->mmio.mmio_block;
36353639 int num = gvt->mmio.num_mmio_block;
36363640 int i;
36373641
@@ -3670,7 +3674,7 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) · 32 unmodified lines
36703674 * accessible (should have no F_CMD_ACCESS flag).
36713675 * otherwise, need to update cmd_reg_handler in cmd_parser.c
36723676 */
3673−static struct gvt_mmio_block mmio_blocks[] = {
3677+static const struct gvt_mmio_block mmio_blocks[] = {
36743678 {D_SKL_PLUS, _MMIO(DMC_MMIO_START_RANGE), 0x3000, NULL, NULL},
36753679 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
36763680 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
@@ -3753,7 +3757,7 @@ int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, · 76 unmodified lines
37533757 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
37543758 void *data)
37553759 {
3756− struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3760+ const struct gvt_mmio_block *block = gvt->mmio.mmio_block;
37573761 struct intel_gvt_mmio_info *e;
37583762 int i, j, ret;
37593763
@@ -3871,7 +3875,7 @@ int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, · 111 unmodified lines
38713875 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
38723876 struct intel_gvt *gvt = vgpu->gvt;
38733877 struct intel_gvt_mmio_info *mmio_info;
3874− struct gvt_mmio_block *mmio_block;
3878+ const struct gvt_mmio_block *mmio_block;
38753879 gvt_mmio_func func;
38763880 int ret;
38773881
drivers/gpu/drm/i915/gvt/interrupt.c+6−5
@@ -30,6 +30,7 @@ · 29 unmodified lines
3030 */
3131
3232 #include "i915_drv.h"
33+#include "i915_reg.h"
3334 #include "gvt.h"
3435 #include "trace.h"
3536
@@ -176,7 +177,7 @@ int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu, · 140 unmodified lines
176177 unsigned int reg, void *p_data, unsigned int bytes)
177178 {
178179 struct intel_gvt *gvt = vgpu->gvt;
179− struct intel_gvt_irq_ops *ops = gvt->irq.ops;
180+ const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
180181 u32 imr = *(u32 *)p_data;
181182
182183 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
@@ -206,7 +207,7 @@ int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu, · 23 unmodified lines
206207 unsigned int reg, void *p_data, unsigned int bytes)
207208 {
208209 struct intel_gvt *gvt = vgpu->gvt;
209− struct intel_gvt_irq_ops *ops = gvt->irq.ops;
210+ const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
210211 u32 ier = *(u32 *)p_data;
211212 u32 virtual_ier = vgpu_vreg(vgpu, reg);
212213
@@ -246,7 +247,7 @@ int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu, · 33 unmodified lines
246247 {
247248 struct intel_gvt *gvt = vgpu->gvt;
248249 struct drm_i915_private *i915 = gvt->gt->i915;
249− struct intel_gvt_irq_ops *ops = gvt->irq.ops;
250+ const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
250251 struct intel_gvt_irq_info *info;
251252 u32 ier = *(u32 *)p_data;
252253
@@ -604,7 +605,7 @@ static void gen8_init_irq( · 351 unmodified lines
604605 SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU);
605606 }
606607
607−static struct intel_gvt_irq_ops gen8_irq_ops = {
608+static const struct intel_gvt_irq_ops gen8_irq_ops = {
608609 .init_irq = gen8_init_irq,
609610 .check_pending_irq = gen8_check_pending_irq,
610611 };
@@ -626,7 +627,7 @@ void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu, · 15 unmodified lines
626627 struct intel_gvt *gvt = vgpu->gvt;
627628 struct intel_gvt_irq *irq = &gvt->irq;
628629 gvt_event_virt_handler_t handler;
629− struct intel_gvt_irq_ops *ops = gvt->irq.ops;
630+ const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
630631
631632 handler = get_event_virt_handler(irq, event);
632633 drm_WARN_ON(&i915->drm, !handler);
drivers/gpu/drm/i915/gvt/interrupt.h+2−2
@@ -35,7 +35,7 @@ · 34 unmodified lines
3535 #include <linux/hrtimer.h>
3636 #include <linux/kernel.h>
3737
38−#include "i915_reg.h"
38+#include "i915_reg_defs.h"
3939
4040 enum intel_gvt_event_type {
4141 RCS_MI_USER_INTERRUPT = 0,
@@ -203,7 +203,7 @@ struct intel_gvt_irq_map { · 161 unmodified lines
203203
204204 /* structure containing device specific IRQ state */
205205 struct intel_gvt_irq {
206− struct intel_gvt_irq_ops *ops;
206+ const struct intel_gvt_irq_ops *ops;
207207 struct intel_gvt_irq_info *info[INTEL_GVT_IRQ_INFO_MAX];
208208 DECLARE_BITMAP(irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX);
209209 struct intel_gvt_event_info events[INTEL_GVT_EVENT_MAX];
drivers/gpu/drm/i915/gvt/mmio.c+3−0
@@ -34,8 +34,11 @@ · 33 unmodified lines
3434 */
3535
3636 #include "i915_drv.h"
37+#include "i915_reg.h"
3738 #include "gvt.h"
3839
40+#include "gt/intel_gt_regs.h"
41+
3942 /**
4043 * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
4144 * @vgpu: a vGPU
drivers/gpu/drm/i915/gvt/mmio_context.c+4−2
@@ -35,7 +35,9 @@ · 34 unmodified lines
3535
3636 #include "i915_drv.h"
3737 #include "gt/intel_context.h"
38+#include "gt/intel_engine_regs.h"
3839 #include "gt/intel_gpu_commands.h"
40+#include "gt/intel_gt_regs.h"
3941 #include "gt/intel_ring.h"
4042 #include "gvt.h"
4143 #include "trace.h"
@@ -44,7 +46,7 @@ · 2 unmodified lines
4446
4547 /* Raw offset is appened to each line for convenience. */
4648 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
47− {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
49+ {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
4850 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
4951 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
5052 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
@@ -76,7 +78,7 @@ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = { · 25 unmodified lines
7678 };
7779
7880 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
79− {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
81+ {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
8082 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
8183 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
8284 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
drivers/gpu/drm/i915/gvt/mmio_context.h+1−1
@@ -38,9 +38,9 @@ · 37 unmodified lines
3838
3939 #include <linux/types.h>
4040
41+#include "gt/intel_engine_regs.h"
4142 #include "gt/intel_engine_types.h"
4243 #include "gt/intel_lrc_reg.h"
43−#include "i915_reg.h"
4444
4545 struct i915_request;
4646 struct intel_context;
drivers/gpu/drm/i915/gvt/reg.h+0−1
@@ -62,7 +62,6 @@ · 61 unmodified lines
6262
6363 #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
6464
65−#define PLANE_CTL_ASYNC_FLIP (1 << 9)
6665 #define REG50080_FLIP_TYPE_MASK 0x3
6766 #define REG50080_FLIP_TYPE_ASYNC 0x1
6867
drivers/gpu/drm/i915/gvt/sched_policy.c+1−1
@@ -368,7 +368,7 @@ static void tbs_sched_stop_schedule(struct intel_vgpu *vgpu) · 367 unmodified lines
368368 vgpu_data->active = false;
369369 }
370370
371−static struct intel_gvt_sched_policy_ops tbs_schedule_ops = {
371+static const struct intel_gvt_sched_policy_ops tbs_schedule_ops = {
372372 .init = tbs_sched_init,
373373 .clean = tbs_sched_clean,
374374 .init_vgpu = tbs_sched_init_vgpu,
drivers/gpu/drm/i915/gvt/scheduler.c+2−0
@@ -38,11 +38,13 @@ · 37 unmodified lines
3838 #include "gem/i915_gem_pm.h"
3939 #include "gt/intel_context.h"
4040 #include "gt/intel_execlists_submission.h"
41+#include "gt/intel_gt_regs.h"
4142 #include "gt/intel_lrc.h"
4243 #include "gt/intel_ring.h"
4344
4445 #include "i915_drv.h"
4546 #include "i915_gem_gtt.h"
47+#include "i915_perf_oa_regs.h"
4648 #include "gvt.h"
4749
4850 #define RING_CTX_OFF(x) \
drivers/gpu/drm/i915/gvt/scheduler.h+1−1
@@ -56,7 +56,7 @@ struct intel_gvt_workload_scheduler { · 55 unmodified lines
5656 wait_queue_head_t waitq[I915_NUM_ENGINES];
5757
5858 void *sched_data;
59− struct intel_gvt_sched_policy_ops *sched_ops;
59+ const struct intel_gvt_sched_policy_ops *sched_ops;
6060 };
6161
6262 #define INDIRECT_CTX_ADDR_MASK 0xffffffc0
drivers/gpu/drm/i915/gvt/vgpu.c+2−2
@@ -77,7 +77,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu) · 76 unmodified lines
7777 #define VGPU_WEIGHT(vgpu_num) \
7878 (VGPU_MAX_WEIGHT / (vgpu_num))
7979
80−static struct {
80+static const struct {
8181 unsigned int low_mm;
8282 unsigned int high_mm;
8383 unsigned int fence;
@@ -88,7 +88,7 @@ static struct { · 4 unmodified lines
8888 */
8989 unsigned int weight;
9090 enum intel_vgpu_edid edid;
91− char *name;
91+ const char *name;
9292 } vgpu_types[] = {
9393 /* Fixed vGPU type table */
9494 { MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
drivers/gpu/drm/i915/i915_cmd_parser.c+42−34
@@ -26,10 +26,14 @@ · 25 unmodified lines
2626 */
2727
2828 #include "gt/intel_engine.h"
29+#include "gt/intel_engine_regs.h"
2930 #include "gt/intel_gpu_commands.h"
31+#include "gt/intel_gt_regs.h"
3032
33+#include "i915_cmd_parser.h"
3134 #include "i915_drv.h"
3235 #include "i915_memcpy.h"
36+#include "i915_reg.h"
3337
3438 /**
3539 * DOC: batch buffer command parser
@@ -591,6 +595,10 @@ struct drm_i915_reg_descriptor { · 555 unmodified lines
591595 { .addr = _reg(idx) }, \
592596 { .addr = _reg ## _UDW(idx) }
593597
598+#define REG64_BASE_IDX(_reg, base, idx) \
599+ { .addr = _reg(base, idx) }, \
600+ { .addr = _reg ## _UDW(base, idx) }
601+
594602 static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
595603 REG64(GPGPU_THREADS_DISPATCHED),
596604 REG64(HS_INVOCATION_COUNT),
@@ -605,8 +613,8 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = { · 8 unmodified lines
605613 REG64(PS_INVOCATION_COUNT),
606614 REG64(PS_DEPTH_COUNT),
607615 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
608− REG64(MI_PREDICATE_SRC0),
609− REG64(MI_PREDICATE_SRC1),
616+ REG64_IDX(MI_PREDICATE_SRC0, RENDER_RING_BASE),
617+ REG64_IDX(MI_PREDICATE_SRC1, RENDER_RING_BASE),
610618 REG32(GEN7_3DPRIM_END_OFFSET),
611619 REG32(GEN7_3DPRIM_START_VERTEX),
612620 REG32(GEN7_3DPRIM_VERTEX_COUNT),
@@ -636,22 +644,22 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = { · 23 unmodified lines
636644 };
637645
638646 static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
639− REG64_IDX(HSW_CS_GPR, 0),
640− REG64_IDX(HSW_CS_GPR, 1),
641− REG64_IDX(HSW_CS_GPR, 2),
642− REG64_IDX(HSW_CS_GPR, 3),
643− REG64_IDX(HSW_CS_GPR, 4),
644− REG64_IDX(HSW_CS_GPR, 5),
645− REG64_IDX(HSW_CS_GPR, 6),
646− REG64_IDX(HSW_CS_GPR, 7),
647− REG64_IDX(HSW_CS_GPR, 8),
648− REG64_IDX(HSW_CS_GPR, 9),
649− REG64_IDX(HSW_CS_GPR, 10),
650− REG64_IDX(HSW_CS_GPR, 11),
651− REG64_IDX(HSW_CS_GPR, 12),
652− REG64_IDX(HSW_CS_GPR, 13),
653− REG64_IDX(HSW_CS_GPR, 14),
654− REG64_IDX(HSW_CS_GPR, 15),
647+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0),
648+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1),
649+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2),
650+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3),
651+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4),
652+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5),
653+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6),
654+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 7),
655+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 8),
656+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 9),
657+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 10),
658+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 11),
659+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 12),
660+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 13),
661+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 14),
662+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 15),
655663 REG32(HSW_SCRATCH1,
656664 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
657665 .value = 0),
@@ -674,22 +682,22 @@ static const struct drm_i915_reg_descriptor gen9_blt_regs[] = { · 16 unmodified lines
674682 REG32(BCS_SWCTRL),
675683 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
676684 REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),
677− REG64_IDX(BCS_GPR, 0),
678− REG64_IDX(BCS_GPR, 1),
679− REG64_IDX(BCS_GPR, 2),
680− REG64_IDX(BCS_GPR, 3),
681− REG64_IDX(BCS_GPR, 4),
682− REG64_IDX(BCS_GPR, 5),
683− REG64_IDX(BCS_GPR, 6),
684− REG64_IDX(BCS_GPR, 7),
685− REG64_IDX(BCS_GPR, 8),
686− REG64_IDX(BCS_GPR, 9),
687− REG64_IDX(BCS_GPR, 10),
688− REG64_IDX(BCS_GPR, 11),
689− REG64_IDX(BCS_GPR, 12),
690− REG64_IDX(BCS_GPR, 13),
691− REG64_IDX(BCS_GPR, 14),
692− REG64_IDX(BCS_GPR, 15),
685+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0),
686+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1),
687+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2),
688+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3),
689+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4),
690+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 5),
691+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 6),
692+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 7),
693+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 8),
694+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 9),
695+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 10),
696+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 11),
697+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 12),
698+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 13),
699+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 14),
700+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 15),
693701 };
694702
695703 #undef REG64
drivers/gpu/drm/i915/i915_cmd_parser.h+26−0
@@ -0,0 +1,26 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2021 Intel Corporation
4+ */
5+
6+#ifndef __I915_CMD_PARSER_H__
7+#define __I915_CMD_PARSER_H__
8+
9+#include <linux/types.h>
10+
11+struct drm_i915_private;
12+struct intel_engine_cs;
13+struct i915_vma;
14+
15+int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
16+int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
17+void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
18+int intel_engine_cmd_parser(struct intel_engine_cs *engine,
19+ struct i915_vma *batch,
20+ unsigned long batch_offset,
21+ unsigned long batch_length,
22+ struct i915_vma *shadow,
23+ bool trampoline);
24+#define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
25+
26+#endif /* __I915_CMD_PARSER_H__ */
drivers/gpu/drm/i915/i915_debugfs.c+1−0
@@ -38,6 +38,7 @@ · 37 unmodified lines
3838 #include "gt/intel_gt_debugfs.h"
3939 #include "gt/intel_gt_pm.h"
4040 #include "gt/intel_gt_pm_debugfs.h"
41+#include "gt/intel_gt_regs.h"
4142 #include "gt/intel_gt_requests.h"
4243 #include "gt/intel_rc6.h"
4344 #include "gt/intel_reset.h"
drivers/gpu/drm/i915/i915_driver.c+3−0
@@ -74,7 +74,9 @@ · 73 unmodified lines
7474 #include "i915_debugfs.h"
7575 #include "i915_driver.h"
7676 #include "i915_drv.h"
77+#include "i915_getparam.h"
7778 #include "i915_ioc32.h"
79+#include "i915_ioctl.h"
7880 #include "i915_irq.h"
7981 #include "i915_memcpy.h"
8082 #include "i915_perf.h"
@@ -86,6 +88,7 @@ · 5 unmodified lines
8688 #include "intel_dram.h"
8789 #include "intel_gvt.h"
8890 #include "intel_memory_region.h"
91+#include "intel_pci_config.h"
8992 #include "intel_pcode.h"
9093 #include "intel_pm.h"
9194 #include "intel_region_ttm.h"
drivers/gpu/drm/i915/i915_drv.h+16−74
@@ -61,15 +61,16 @@ · 60 unmodified lines
6161 #include <drm/ttm/ttm_device.h>
6262
6363 #include "i915_params.h"
64−#include "i915_reg.h"
6564 #include "i915_utils.h"
6665
6766 #include "display/intel_bios.h"
67+#include "display/intel_cdclk.h"
6868 #include "display/intel_display.h"
6969 #include "display/intel_display_power.h"
7070 #include "display/intel_dmc.h"
7171 #include "display/intel_dpll_mgr.h"
7272 #include "display/intel_dsb.h"
73+#include "display/intel_fbc.h"
7374 #include "display/intel_frontbuffer.h"
7475 #include "display/intel_global_state.h"
7576 #include "display/intel_gmbus.h"
@@ -104,7 +105,6 @@ · 28 unmodified lines
104105 #include "i915_scheduler.h"
105106 #include "gt/intel_timeline.h"
106107 #include "i915_vma.h"
107−#include "i915_irq.h"
108108
109109
110110 /* General customization:
@@ -290,6 +290,7 @@ struct intel_connector; · 179 unmodified lines
290290 struct intel_encoder;
291291 struct intel_atomic_state;
292292 struct intel_cdclk_config;
293+struct intel_cdclk_funcs;
293294 struct intel_cdclk_state;
294295 struct intel_cdclk_vals;
295296 struct intel_initial_plane_config;
@@ -338,17 +339,6 @@ struct intel_color_funcs { · 42 unmodified lines
338339 void (*read_luts)(struct intel_crtc_state *crtc_state);
339340 };
340341
341−struct intel_cdclk_funcs {
342− void (*get_cdclk)(struct drm_i915_private *dev_priv,
343− struct intel_cdclk_config *cdclk_config);
344− void (*set_cdclk)(struct drm_i915_private *dev_priv,
345− const struct intel_cdclk_config *cdclk_config,
346− enum pipe pipe);
347− int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
348− int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
349− u8 (*calc_voltage_level)(int cdclk);
350−};
351−
352342 struct intel_hotplug_funcs {
353343 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
354344 };
@@ -523,13 +513,6 @@ i915_fence_timeout(const struct drm_i915_private *i915) · 168 unmodified lines
523513 /* Amount of PSF GV points, BSpec precisely defines this */
524514 #define I915_NUM_PSF_GV_POINTS 3
525515
526−enum psr_lines_to_wait {
527− PSR_0_LINES_TO_WAIT = 0,
528− PSR_1_LINE_TO_WAIT,
529− PSR_4_LINES_TO_WAIT,
530− PSR_8_LINES_TO_WAIT
531−};
532−
533516 struct intel_vbt_data {
534517 /* bdb version */
535518 u16 version;
@@ -569,7 +552,6 @@ struct intel_vbt_data { · 33 unmodified lines
569552 bool full_link;
570553 bool require_aux_wakeup;
571554 int idle_frames;
572− enum psr_lines_to_wait lines_to_wait;
573555 int tp1_wakeup_time_us;
574556 int tp2_tp3_wakeup_time_us;
575557 int psr2_tp2_tp3_wakeup_time_us;
@@ -625,11 +607,6 @@ struct i915_virtual_gpu { · 49 unmodified lines
625607 u32 caps;
626608 };
627609
628−struct intel_cdclk_config {
629− unsigned int cdclk, vco, ref, bypass;
630− u8 voltage_level;
631−};
632−
633610 struct i915_selftest_stash {
634611 atomic_t counter;
635612 struct ida mock_region_instances;
@@ -749,7 +726,7 @@ struct drm_i915_private { · 113 unmodified lines
749726 u32 pipestat_irq_mask[I915_MAX_PIPES];
750727
751728 struct i915_hotplug hotplug;
752− struct intel_fbc *fbc;
729+ struct intel_fbc *fbc[I915_MAX_FBCS];
753730 struct i915_drrs drrs;
754731 struct intel_opregion opregion;
755732 struct intel_vbt_data vbt;
@@ -1288,6 +1265,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 532 unmodified lines
12881265 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
12891266 #define IS_ADLS_RPLS(dev_priv) \
12901267 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL_S)
1268+#define IS_ADLP_N(dev_priv) \
1269+ IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
12911270 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
12921271 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
12931272 #define IS_BDW_ULT(dev_priv) \
@@ -1485,8 +1464,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 191 unmodified lines
14851464 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
14861465 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
14871466
1488−#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
1489−#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
1467+#define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
1468+#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
14901469 IS_GEMINILAKE(dev_priv) || \
14911470 IS_KABYLAKE(dev_priv))
14921471
@@ -1498,9 +1477,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 5 unmodified lines
14981477 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
14991478 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
15001479
1501−#define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
1502−#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
1503−#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7)
1480+#define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
1481+#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.fbc_mask != 0)
1482+#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
15041483
15051484 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
15061485
@@ -1513,7 +1492,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 6 unmodified lines
15131492 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
15141493 #define HAS_PSR_HW_TRACKING(dev_priv) \
15151494 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1516−#define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
1495+#define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12)
15171496 #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
15181497
15191498 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
@@ -1524,7 +1503,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 4 unmodified lines
15241503
15251504 #define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
15261505
1527−#define HAS_MSO(i915) (GRAPHICS_VER(i915) >= 12)
1506+#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
15281507
15291508 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
15301509 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
@@ -1557,7 +1536,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 26 unmodified lines
15571536
15581537 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
15591538
1560−#define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10))
1539+#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
15611540
15621541 /* DPF == dynamic parity feature */
15631542 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
@@ -1571,7 +1550,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 7 unmodified lines
15711550
15721551 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.pipe_mask != 0)
15731552
1574−#define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 11)
1553+#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
15751554
15761555 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
15771556
@@ -1601,7 +1580,7 @@ i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p); · 23 unmodified lines
16011580
16021581 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
16031582 {
1604− return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active(dev_priv);
1583+ return DISPLAY_VER(dev_priv) >= 6 && intel_vtd_active(dev_priv);
16051584 }
16061585
16071586 static inline bool
@@ -1616,13 +1595,7 @@ intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915) · 8 unmodified lines
16161595 return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915);
16171596 }
16181597
1619−/* i915_getparam.c */
1620−int i915_getparam_ioctl(struct drm_device *dev, void *data,
1621− struct drm_file *file_priv);
1622−
16231598 /* i915_gem.c */
1624−int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1625−void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
16261599 void i915_gem_init_early(struct drm_i915_private *dev_priv);
16271600 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
16281601
@@ -1734,17 +1707,6 @@ i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id) · 105 unmodified lines
17341707 return vm;
17351708 }
17361709
1737−/* i915_gem_evict.c */
1738−int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1739− u64 min_size, u64 alignment,
1740− unsigned long color,
1741− u64 start, u64 end,
1742− unsigned flags);
1743−int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1744− struct drm_mm_node *node,
1745− unsigned int flags);
1746−int i915_gem_evict_vm(struct i915_address_space *vm);
1747−
17481710 /* i915_gem_internal.c */
17491711 struct drm_i915_gem_object *
17501712 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
@@ -1763,25 +1725,8 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec · 12 unmodified lines
17631725 i915_gem_object_is_tiled(obj);
17641726 }
17651727
1766−u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1767− unsigned int tiling, unsigned int stride);
1768−u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1769− unsigned int tiling, unsigned int stride);
1770−
17711728 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
17721729
1773−/* i915_cmd_parser.c */
1774−int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1775−int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1776−void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1777−int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1778− struct i915_vma *batch,
1779− unsigned long batch_offset,
1780− unsigned long batch_length,
1781− struct i915_vma *shadow,
1782− bool trampoline);
1783−#define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1784−
17851730 /* intel_device_info.c */
17861731 static inline struct intel_device_info *
17871732 mkwrite_device_info(struct drm_i915_private *dev_priv)
@@ -1789,9 +1734,6 @@ mkwrite_device_info(struct drm_i915_private *dev_priv) · 1 unmodified line
17891734 return (struct intel_device_info *)INTEL_INFO(dev_priv);
17901735 }
17911736
1792−int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1793− struct drm_file *file);
1794−
17951737 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
17961738 {
17971739 if (GRAPHICS_VER(i915) >= 11)
drivers/gpu/drm/i915/i915_gem.c+1−0
@@ -45,6 +45,7 @@ · 44 unmodified lines
4545 #include "gem/i915_gem_ioctls.h"
4646 #include "gem/i915_gem_mman.h"
4747 #include "gem/i915_gem_region.h"
48+#include "gem/i915_gem_userptr.h"
4849 #include "gt/intel_engine_user.h"
4950 #include "gt/intel_gt.h"
5051 #include "gt/intel_gt_pm.h"
drivers/gpu/drm/i915/i915_gem_evict.c+1−0
@@ -31,6 +31,7 @@ · 30 unmodified lines
3131 #include "gt/intel_gt_requests.h"
3232
3333 #include "i915_drv.h"
34+#include "i915_gem_evict.h"
3435 #include "i915_trace.h"
3536
3637 I915_SELFTEST_DECLARE(static struct igt_evict_ctl {
drivers/gpu/drm/i915/i915_gem_evict.h+24−0
@@ -0,0 +1,24 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2021 Intel Corporation
4+ */
5+
6+#ifndef __I915_GEM_EVICT_H__
7+#define __I915_GEM_EVICT_H__
8+
9+#include <linux/types.h>
10+
11+struct drm_mm_node;
12+struct i915_address_space;
13+
14+int __must_check i915_gem_evict_something(struct i915_address_space *vm,
15+ u64 min_size, u64 alignment,
16+ unsigned long color,
17+ u64 start, u64 end,
18+ unsigned flags);
19+int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
20+ struct drm_mm_node *node,
21+ unsigned int flags);
22+int i915_gem_evict_vm(struct i915_address_space *vm);
23+
24+#endif /* __I915_GEM_EVICT_H__ */
drivers/gpu/drm/i915/i915_gem_gtt.c+1−0
@@ -20,6 +20,7 @@ · 19 unmodified lines
2020 #include "gt/intel_gt_requests.h"
2121
2222 #include "i915_drv.h"
23+#include "i915_gem_evict.h"
2324 #include "i915_scatterlist.h"
2425 #include "i915_trace.h"
2526 #include "i915_vgpu.h"
drivers/gpu/drm/i915/i915_getparam.c+2−0
@@ -5,7 +5,9 @@ · 4 unmodified lines
55 #include "gem/i915_gem_mman.h"
66 #include "gt/intel_engine_user.h"
77
8+#include "i915_cmd_parser.h"
89 #include "i915_drv.h"
10+#include "i915_getparam.h"
911 #include "i915_perf.h"
1012
1113 int i915_getparam_ioctl(struct drm_device *dev, void *data,
drivers/gpu/drm/i915/i915_getparam.h+15−0
@@ -0,0 +1,15 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2021 Intel Corporation
4+ */
5+
6+#ifndef __I915_GETPARAM_H__
7+#define __I915_GETPARAM_H__
8+
9+struct drm_device;
10+struct drm_file;
11+
12+int i915_getparam_ioctl(struct drm_device *dev, void *data,
13+ struct drm_file *file_priv);
14+
15+#endif /* __I915_GETPARAM_H__ */
drivers/gpu/drm/i915/i915_gpu_error.c+2−0
@@ -41,8 +41,10 @@ · 40 unmodified lines
4141
4242 #include "gem/i915_gem_context.h"
4343 #include "gem/i915_gem_lmem.h"
44+#include "gt/intel_engine_regs.h"
4445 #include "gt/intel_gt.h"
4546 #include "gt/intel_gt_pm.h"
47+#include "gt/intel_gt_regs.h"
4648
4749 #include "i915_drv.h"
4850 #include "i915_gpu_error.h"
drivers/gpu/drm/i915/i915_ioc32.c+1−0
@@ -31,6 +31,7 @@ · 30 unmodified lines
3131 #include <drm/drm_ioctl.h>
3232
3333 #include "i915_drv.h"
34+#include "i915_getparam.h"
3435 #include "i915_ioc32.h"
3536
3637 struct drm_i915_getparam32 {
drivers/gpu/drm/i915/i915_ioctl.c+94−0
@@ -0,0 +1,94 @@
1+// SPDX-License-Identifier: MIT
2+/*
3+ * Copyright © 2022 Intel Corporation
4+ */
5+
6+#include "gt/intel_engine_regs.h"
7+
8+#include "i915_drv.h"
9+#include "i915_gem.h"
10+#include "i915_ioctl.h"
11+#include "i915_reg.h"
12+#include "intel_runtime_pm.h"
13+#include "intel_uncore.h"
14+
15+/*
16+ * This file is for small ioctl functions that are out of place everywhere else,
17+ * and not big enough to warrant a file of their own.
18+ *
19+ * This is not the dumping ground for random ioctls.
20+ */
21+
22+struct reg_whitelist {
23+ i915_reg_t offset_ldw;
24+ i915_reg_t offset_udw;
25+ u8 min_graphics_ver;
26+ u8 max_graphics_ver;
27+ u8 size;
28+};
29+
30+static const struct reg_whitelist reg_read_whitelist[] = {
31+ {
32+ .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
33+ .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
34+ .min_graphics_ver = 4,
35+ .max_graphics_ver = 12,
36+ .size = 8
37+ }
38+};
39+
40+int i915_reg_read_ioctl(struct drm_device *dev,
41+ void *data, struct drm_file *unused)
42+{
43+ struct drm_i915_private *i915 = to_i915(dev);
44+ struct intel_uncore *uncore = &i915->uncore;
45+ struct drm_i915_reg_read *reg = data;
46+ struct reg_whitelist const *entry;
47+ intel_wakeref_t wakeref;
48+ unsigned int flags;
49+ int remain;
50+ int ret = 0;
51+
52+ entry = reg_read_whitelist;
53+ remain = ARRAY_SIZE(reg_read_whitelist);
54+ while (remain) {
55+ u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
56+
57+ GEM_BUG_ON(!is_power_of_2(entry->size));
58+ GEM_BUG_ON(entry->size > 8);
59+ GEM_BUG_ON(entry_offset & (entry->size - 1));
60+
61+ if (IS_GRAPHICS_VER(i915, entry->min_graphics_ver, entry->max_graphics_ver) &&
62+ entry_offset == (reg->offset & -entry->size))
63+ break;
64+ entry++;
65+ remain--;
66+ }
67+
68+ if (!remain)
69+ return -EINVAL;
70+
71+ flags = reg->offset & (entry->size - 1);
72+
73+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
74+ if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
75+ reg->val = intel_uncore_read64_2x32(uncore,
76+ entry->offset_ldw,
77+ entry->offset_udw);
78+ else if (entry->size == 8 && flags == 0)
79+ reg->val = intel_uncore_read64(uncore,
80+ entry->offset_ldw);
81+ else if (entry->size == 4 && flags == 0)
82+ reg->val = intel_uncore_read(uncore, entry->offset_ldw);
83+ else if (entry->size == 2 && flags == 0)
84+ reg->val = intel_uncore_read16(uncore,
85+ entry->offset_ldw);
86+ else if (entry->size == 1 && flags == 0)
87+ reg->val = intel_uncore_read8(uncore,
88+ entry->offset_ldw);
89+ else
90+ ret = -EINVAL;
91+ }
92+
93+ return ret;
94+}
drivers/gpu/drm/i915/i915_ioctl.h+14−0
@@ -0,0 +1,14 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2022 Intel Corporation
4+ */
5+
6+#ifndef __I915_IOCTL_H__
7+#define __I915_IOCTL_H__
8+
9+struct drm_device;
10+struct drm_file;
11+
12+int i915_reg_read_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
13+
14+#endif /* __I915_IOCTL_H__ */
drivers/gpu/drm/i915/i915_irq.c+3−5
@@ -46,6 +46,7 @@ · 45 unmodified lines
4646 #include "gt/intel_gt.h"
4747 #include "gt/intel_gt_irq.h"
4848 #include "gt/intel_gt_pm_irq.h"
49+#include "gt/intel_gt_regs.h"
4950 #include "gt/intel_rps.h"
5051
5152 #include "i915_drv.h"
@@ -836,10 +837,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) · 784 unmodified lines
836837 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
837838 vtotal /= 2;
838839
839− if (DISPLAY_VER(dev_priv) == 2)
840− position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
841− else
842− position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
840+ position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
843841
844842 /*
845843 * On HSW, the DSL reg (0x70000) appears to return 0 if we
@@ -858,7 +856,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) · 12 unmodified lines
858856
859857 for (i = 0; i < 100; i++) {
860858 udelay(1);
861− temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
859+ temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
862860 if (temp != position) {
863861 position = temp;
864862 break;
drivers/gpu/drm/i915/i915_mm.h+2−2
@@ -6,6 +6,7 @@ · 5 unmodified lines
66 #ifndef __I915_MM_H__
77 #define __I915_MM_H__
88
9+#include <linux/bug.h>
910 #include <linux/types.h>
1011
1112 struct vm_area_struct;
@@ -22,8 +23,7 @@ int remap_io_mapping(struct vm_area_struct *vma, · 10 unmodified lines
2223 unsigned long addr, unsigned long pfn, unsigned long size,
2324 struct io_mapping *iomap)
2425 {
25− pr_err("Architecture has no %s() and shouldn't be calling this function\n", __func__);
26− WARN_ON_ONCE(1);
26+ WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
2727 return 0;
2828 }
2929 #endif
drivers/gpu/drm/i915/i915_pci.c+13−11
@@ -28,6 +28,7 @@ · 27 unmodified lines
2828 #include "i915_driver.h"
2929 #include "i915_drv.h"
3030 #include "i915_pci.h"
31+#include "i915_reg.h"
3132
3233 #define PLATFORM(x) .platform = (x)
3334 #define GEN(x) \
@@ -214,13 +215,13 @@ static const struct intel_device_info i845g_info = { · 180 unmodified lines
214215 static const struct intel_device_info i85x_info = {
215216 I830_FEATURES,
216217 PLATFORM(INTEL_I85X),
217− .display.has_fbc = 1,
218+ .display.fbc_mask = BIT(INTEL_FBC_A),
218219 };
219220
220221 static const struct intel_device_info i865g_info = {
221222 I845_FEATURES,
222223 PLATFORM(INTEL_I865G),
223− .display.has_fbc = 1,
224+ .display.fbc_mask = BIT(INTEL_FBC_A),
224225 };
225226
226227 #define GEN3_FEATURES \
@@ -258,7 +259,7 @@ static const struct intel_device_info i915gm_info = { · 31 unmodified lines
258259 .display.has_overlay = 1,
259260 .display.overlay_needs_physical = 1,
260261 .display.supports_tv = 1,
261− .display.has_fbc = 1,
262+ .display.fbc_mask = BIT(INTEL_FBC_A),
262263 .hws_needs_physical = 1,
263264 .unfenced_needs_alignment = 1,
264265 };
@@ -283,7 +284,7 @@ static const struct intel_device_info i945gm_info = { · 18 unmodified lines
283284 .display.has_overlay = 1,
284285 .display.overlay_needs_physical = 1,
285286 .display.supports_tv = 1,
286− .display.has_fbc = 1,
287+ .display.fbc_mask = BIT(INTEL_FBC_A),
287288 .hws_needs_physical = 1,
288289 .unfenced_needs_alignment = 1,
289290 };
@@ -342,7 +343,7 @@ static const struct intel_device_info i965gm_info = { · 52 unmodified lines
342343 GEN4_FEATURES,
343344 PLATFORM(INTEL_I965GM),
344345 .is_mobile = 1,
345− .display.has_fbc = 1,
346+ .display.fbc_mask = BIT(INTEL_FBC_A),
346347 .display.has_overlay = 1,
347348 .display.supports_tv = 1,
348349 .hws_needs_physical = 1,
@@ -360,7 +361,7 @@ static const struct intel_device_info gm45_info = { · 11 unmodified lines
360361 GEN4_FEATURES,
361362 PLATFORM(INTEL_GM45),
362363 .is_mobile = 1,
363− .display.has_fbc = 1,
364+ .display.fbc_mask = BIT(INTEL_FBC_A),
364365 .display.supports_tv = 1,
365366 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
366367 .gpu_reset_clobbers_display = false,
@@ -393,7 +394,7 @@ static const struct intel_device_info ilk_m_info = { · 26 unmodified lines
393394 PLATFORM(INTEL_IRONLAKE),
394395 .is_mobile = 1,
395396 .has_rps = true,
396− .display.has_fbc = 1,
397+ .display.fbc_mask = BIT(INTEL_FBC_A),
397398 };
398399
399400 #define GEN6_FEATURES \
@@ -401,7 +402,7 @@ static const struct intel_device_info ilk_m_info = { · 1 unmodified line
401402 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
402403 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
403404 .display.has_hotplug = 1, \
404− .display.has_fbc = 1, \
405+ .display.fbc_mask = BIT(INTEL_FBC_A), \
405406 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
406407 .has_coherent_ggtt = true, \
407408 .has_llc = 1, \
@@ -452,7 +453,7 @@ static const struct intel_device_info snb_m_gt2_info = { · 44 unmodified lines
452453 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
453454 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
454455 .display.has_hotplug = 1, \
455− .display.has_fbc = 1, \
456+ .display.fbc_mask = BIT(INTEL_FBC_A), \
456457 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
457458 .has_coherent_ggtt = true, \
458459 .has_llc = 1, \
@@ -693,7 +694,7 @@ static const struct intel_device_info skl_gt4_info = { · 234 unmodified lines
693694 .has_64bit_reloc = 1, \
694695 .display.has_ddi = 1, \
695696 .display.has_fpga_dbg = 1, \
696− .display.has_fbc = 1, \
697+ .display.fbc_mask = BIT(INTEL_FBC_A), \
697698 .display.has_hdcp = 1, \
698699 .display.has_psr = 1, \
699700 .display.has_psr_hw_tracking = 1, \
@@ -948,7 +949,7 @@ static const struct intel_device_info adl_s_info = { · 248 unmodified lines
948949 .display.has_dp_mst = 1, \
949950 .display.has_dsb = 1, \
950951 .display.has_dsc = 1, \
951− .display.has_fbc = 1, \
952+ .display.fbc_mask = BIT(INTEL_FBC_A), \
952953 .display.has_fpga_dbg = 1, \
953954 .display.has_hdcp = 1, \
954955 .display.has_hotplug = 1, \
@@ -1131,6 +1132,7 @@ static const struct pci_device_id pciidlist[] = { · 176 unmodified lines
11311132 INTEL_RKL_IDS(&rkl_info),
11321133 INTEL_ADLS_IDS(&adl_s_info),
11331134 INTEL_ADLP_IDS(&adl_p_info),
1135+ INTEL_ADLN_IDS(&adl_p_info),
11341136 INTEL_DG1_IDS(&dg1_info),
11351137 INTEL_RPLS_IDS(&adl_s_info),
11361138 {0, 0, 0}
drivers/gpu/drm/i915/i915_perf.c+88−49
@@ -197,16 +197,19 @@ · 196 unmodified lines
197197
198198 #include "gem/i915_gem_context.h"
199199 #include "gt/intel_engine_pm.h"
200+#include "gt/intel_engine_regs.h"
200201 #include "gt/intel_engine_user.h"
201202 #include "gt/intel_execlists_submission.h"
202203 #include "gt/intel_gpu_commands.h"
203204 #include "gt/intel_gt.h"
204205 #include "gt/intel_gt_clock_utils.h"
206+#include "gt/intel_gt_regs.h"
205207 #include "gt/intel_lrc.h"
206208 #include "gt/intel_ring.h"
207209
208210 #include "i915_drv.h"
209211 #include "i915_perf.h"
212+#include "i915_perf_oa_regs.h"
210213
211214 /* HW requires this to be a power of two, between 128k and 16M, though driver
212215 * is currently generally designed assuming the largest 16M size is used such
@@ -1682,7 +1685,7 @@ retry: · 1469 unmodified lines
16821685 stream, cs, true /* save */, CS_GPR(i),
16831686 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
16841687 cs = save_restore_register(
1685− stream, cs, true /* save */, MI_PREDICATE_RESULT_1,
1688+ stream, cs, true /* save */, MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
16861689 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
16871690
16881691 /* First timestamp snapshot location. */
@@ -1736,7 +1739,7 @@ retry: · 47 unmodified lines
17361739 */
17371740 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
17381741 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
1739− *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
1742+ *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
17401743
17411744 /* Restart from the beginning if we had timestamps roll over. */
17421745 *cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1773,7 +1776,7 @@ retry: · 30 unmodified lines
17731776 */
17741777 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
17751778 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
1776− *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
1779+ *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
17771780
17781781 /* Predicate the jump. */
17791782 *cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1789,7 +1792,7 @@ retry: · 9 unmodified lines
17891792 stream, cs, false /* restore */, CS_GPR(i),
17901793 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
17911794 cs = save_restore_register(
1792− stream, cs, false /* restore */, MI_PREDICATE_RESULT_1,
1795+ stream, cs, false /* restore */, MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
17931796 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
17941797
17951798 /* And return to the ring. */
@@ -2418,7 +2421,7 @@ gen12_configure_all_contexts(struct i915_perf_stream *stream, · 622 unmodified lines
24182421 {
24192422 struct flex regs[] = {
24202423 {
2421− GEN8_R_PWR_CLK_STATE,
2424+ GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
24222425 CTX_R_PWR_CLK_STATE,
24232426 },
24242427 };
@@ -2438,7 +2441,7 @@ lrc_configure_all_contexts(struct i915_perf_stream *stream, · 13 unmodified lines
24382441 #define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
24392442 struct flex regs[] = {
24402443 {
2441− GEN8_R_PWR_CLK_STATE,
2444+ GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
24422445 CTX_R_PWR_CLK_STATE,
24432446 },
24442447 {
@@ -3862,80 +3865,116 @@ static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr) · 1417 unmodified lines
38623865 return false;
38633866 }
38643867
3865−#define ADDR_IN_RANGE(addr, start, end) \
3866− ((addr) >= (start) && \
3867− (addr) <= (end))
3868+static bool reg_in_range_table(u32 addr, const struct i915_range *table)
3869+{
3870+ while (table->start || table->end) {
3871+ if (addr >= table->start && addr <= table->end)
3872+ return true;
38683873
3869−#define REG_IN_RANGE(addr, start, end) \
3870− ((addr) >= i915_mmio_reg_offset(start) && \
3871− (addr) <= i915_mmio_reg_offset(end))
3874+ table++;
3875+ }
3876+
3877+ return false;
3878+}
38723879
38733880 #define REG_EQUAL(addr, mmio) \
38743881 ((addr) == i915_mmio_reg_offset(mmio))
38753882
3876−static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
3877−{
3878− return REG_IN_RANGE(addr, OASTARTTRIG1, OASTARTTRIG8) ||
3879− REG_IN_RANGE(addr, OAREPORTTRIG1, OAREPORTTRIG8) ||
3880− REG_IN_RANGE(addr, OACEC0_0, OACEC7_1);
3881−}
3883+static const struct i915_range gen7_oa_b_counters[] = {
3884+ { .start = 0x2710, .end = 0x272c }, /* OASTARTTRIG[1-8] */
3885+ { .start = 0x2740, .end = 0x275c }, /* OAREPORTTRIG[1-8] */
3886+ { .start = 0x2770, .end = 0x27ac }, /* OACEC[0-7][0-1] */
3887+ {}
3888+};
3889+
3890+static const struct i915_range gen12_oa_b_counters[] = {
3891+ { .start = 0x2b2c, .end = 0x2b2c }, /* GEN12_OAG_OA_PESS */
3892+ { .start = 0xd900, .end = 0xd91c }, /* GEN12_OAG_OASTARTTRIG[1-8] */
3893+ { .start = 0xd920, .end = 0xd93c }, /* GEN12_OAG_OAREPORTTRIG1[1-8] */
3894+ { .start = 0xd940, .end = 0xd97c }, /* GEN12_OAG_CEC[0-7][0-1] */
3895+ { .start = 0xdc00, .end = 0xdc3c }, /* GEN12_OAG_SCEC[0-7][0-1] */
3896+ { .start = 0xdc40, .end = 0xdc40 }, /* GEN12_OAG_SPCTR_CNF */
3897+ { .start = 0xdc44, .end = 0xdc44 }, /* GEN12_OAA_DBG_REG */
3898+ {}
3899+};
3900+
3901+static const struct i915_range gen7_oa_mux_regs[] = {
3902+ { .start = 0x91b8, .end = 0x91cc }, /* OA_PERFCNT[1-2], OA_PERFMATRIX */
3903+ { .start = 0x9800, .end = 0x9888 }, /* MICRO_BP0_0 - NOA_WRITE */
3904+ { .start = 0xe180, .end = 0xe180 }, /* HALF_SLICE_CHICKEN2 */
3905+ {}
3906+};
38823907
3883−static bool gen7_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3908+static const struct i915_range hsw_oa_mux_regs[] = {
3909+ { .start = 0x09e80, .end = 0x09ea4 }, /* HSW_MBVID2_NOA[0-9] */
3910+ { .start = 0x09ec0, .end = 0x09ec0 }, /* HSW_MBVID2_MISR0 */
3911+ { .start = 0x25100, .end = 0x2ff90 },
3912+ {}
3913+};
3914+
3915+static const struct i915_range chv_oa_mux_regs[] = {
3916+ { .start = 0x182300, .end = 0x1823a4 },
3917+ {}
3918+};
3919+
3920+static const struct i915_range gen8_oa_mux_regs[] = {
3921+ { .start = 0x0d00, .end = 0x0d2c }, /* RPM_CONFIG[0-1], NOA_CONFIG[0-8] */
3922+ { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
3923+ {}
3924+};
3925+
3926+static const struct i915_range gen11_oa_mux_regs[] = {
3927+ { .start = 0x91c8, .end = 0x91dc }, /* OA_PERFCNT[3-4] */
3928+ {}
3929+};
3930+
3931+static const struct i915_range gen12_oa_mux_regs[] = {
3932+ { .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
3933+ { .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
3934+ { .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
3935+ { .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */
3936+ { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
3937+ {}
3938+};
3939+
3940+static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
38843941 {
3885− return REG_EQUAL(addr, HALF_SLICE_CHICKEN2) ||
3886− REG_IN_RANGE(addr, MICRO_BP0_0, NOA_WRITE) ||
3887− REG_IN_RANGE(addr, OA_PERFCNT1_LO, OA_PERFCNT2_HI) ||
3888− REG_IN_RANGE(addr, OA_PERFMATRIX_LO, OA_PERFMATRIX_HI);
3942+ return reg_in_range_table(addr, gen7_oa_b_counters);
38893943 }
38903944
38913945 static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
38923946 {
3893− return gen7_is_valid_mux_addr(perf, addr) ||
3894− REG_EQUAL(addr, WAIT_FOR_RC6_EXIT) ||
3895− REG_IN_RANGE(addr, RPM_CONFIG0, NOA_CONFIG(8));
3947+ return reg_in_range_table(addr, gen7_oa_mux_regs) ||
3948+ reg_in_range_table(addr, gen8_oa_mux_regs);
38963949 }
38973950
38983951 static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
38993952 {
3900− return gen8_is_valid_mux_addr(perf, addr) ||
3901− REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||
3902− REG_IN_RANGE(addr, OA_PERFCNT3_LO, OA_PERFCNT4_HI);
3953+ return reg_in_range_table(addr, gen7_oa_mux_regs) ||
3954+ reg_in_range_table(addr, gen8_oa_mux_regs) ||
3955+ reg_in_range_table(addr, gen11_oa_mux_regs);
39033956 }
39043957
39053958 static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
39063959 {
3907− return gen7_is_valid_mux_addr(perf, addr) ||
3908− ADDR_IN_RANGE(addr, 0x25100, 0x2FF90) ||
3909− REG_IN_RANGE(addr, HSW_MBVID2_NOA0, HSW_MBVID2_NOA9) ||
3910− REG_EQUAL(addr, HSW_MBVID2_MISR0);
3960+ return reg_in_range_table(addr, gen7_oa_mux_regs) ||
3961+ reg_in_range_table(addr, hsw_oa_mux_regs);
39113962 }
39123963
39133964 static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
39143965 {
3915− return gen7_is_valid_mux_addr(perf, addr) ||
3916− ADDR_IN_RANGE(addr, 0x182300, 0x1823A4);
3966+ return reg_in_range_table(addr, gen7_oa_mux_regs) ||
3967+ reg_in_range_table(addr, chv_oa_mux_regs);
39173968 }
39183969
39193970 static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
39203971 {
3921− return REG_IN_RANGE(addr, GEN12_OAG_OASTARTTRIG1, GEN12_OAG_OASTARTTRIG8) ||
3922− REG_IN_RANGE(addr, GEN12_OAG_OAREPORTTRIG1, GEN12_OAG_OAREPORTTRIG8) ||
3923− REG_IN_RANGE(addr, GEN12_OAG_CEC0_0, GEN12_OAG_CEC7_1) ||
3924− REG_IN_RANGE(addr, GEN12_OAG_SCEC0_0, GEN12_OAG_SCEC7_1) ||
3925− REG_EQUAL(addr, GEN12_OAA_DBG_REG) ||
3926− REG_EQUAL(addr, GEN12_OAG_OA_PESS) ||
3927− REG_EQUAL(addr, GEN12_OAG_SPCTR_CNF);
3972+ return reg_in_range_table(addr, gen12_oa_b_counters);
39283973 }
39293974
39303975 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
39313976 {
3932− return REG_EQUAL(addr, NOA_WRITE) ||
3933− REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||
3934− REG_EQUAL(addr, GDT_CHICKEN_BITS) ||
3935− REG_EQUAL(addr, WAIT_FOR_RC6_EXIT) ||
3936− REG_EQUAL(addr, RPM_CONFIG0) ||
3937− REG_EQUAL(addr, RPM_CONFIG1) ||
3938− REG_IN_RANGE(addr, NOA_CONFIG(0), NOA_CONFIG(8));
3977+ return reg_in_range_table(addr, gen12_oa_mux_regs);
39393978 }
39403979
39413980 static u32 mask_reg_value(u32 reg, u32 val)
drivers/gpu/drm/i915/i915_perf_oa_regs.h+137−0
@@ -0,0 +1,137 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2022 Intel Corporation
4+ */
5+
6+#ifndef __INTEL_PERF_OA_REGS__
7+#define __INTEL_PERF_OA_REGS__
8+
9+#include "i915_reg_defs.h"
10+
11+#define GEN7_OACONTROL _MMIO(0x2360)
12+#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
13+#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
14+#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
15+#define GEN7_OACONTROL_TIMER_ENABLE (1 << 5)
16+#define GEN7_OACONTROL_FORMAT_A13 (0 << 2)
17+#define GEN7_OACONTROL_FORMAT_A29 (1 << 2)
18+#define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2)
19+#define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2)
20+#define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2)
21+#define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2)
22+#define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2)
23+#define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2)
24+#define GEN7_OACONTROL_FORMAT_SHIFT 2
25+#define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1)
26+#define GEN7_OACONTROL_ENABLE (1 << 0)
27+
28+#define GEN8_OACTXID _MMIO(0x2364)
29+
30+#define GEN8_OA_DEBUG _MMIO(0x2B04)
31+#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
32+#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
33+#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
34+#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
35+
36+#define GEN8_OACONTROL _MMIO(0x2B00)
37+#define GEN8_OA_REPORT_FORMAT_A12 (0 << 2)
38+#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2)
39+#define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2)
40+#define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2)
41+#define GEN8_OA_REPORT_FORMAT_SHIFT 2
42+#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1)
43+#define GEN8_OA_COUNTER_ENABLE (1 << 0)
44+
45+#define GEN8_OACTXCONTROL _MMIO(0x2360)
46+#define GEN8_OA_TIMER_PERIOD_MASK 0x3F
47+#define GEN8_OA_TIMER_PERIOD_SHIFT 2
48+#define GEN8_OA_TIMER_ENABLE (1 << 1)
49+#define GEN8_OA_COUNTER_RESUME (1 << 0)
50+
51+#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
52+#define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3)
53+#define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2)
54+#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1)
55+#define GEN7_OABUFFER_RESUME (1 << 0)
56+
57+#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
58+#define GEN8_OABUFFER _MMIO(0x2b14)
59+#define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
60+
61+#define GEN7_OASTATUS1 _MMIO(0x2364)
62+#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
63+#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
64+#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
65+#define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
66+
67+#define GEN7_OASTATUS2 _MMIO(0x2368)
68+#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
69+#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
70+
71+#define GEN8_OASTATUS _MMIO(0x2b08)
72+#define GEN8_OASTATUS_TAIL_POINTER_WRAP (1 << 17)
73+#define GEN8_OASTATUS_HEAD_POINTER_WRAP (1 << 16)
74+#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
75+#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
76+#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1)
77+#define GEN8_OASTATUS_REPORT_LOST (1 << 0)
78+
79+#define GEN8_OAHEADPTR _MMIO(0x2B0C)
80+#define GEN8_OAHEADPTR_MASK 0xffffffc0
81+#define GEN8_OATAILPTR _MMIO(0x2B10)
82+#define GEN8_OATAILPTR_MASK 0xffffffc0
83+
84+#define OABUFFER_SIZE_128K (0 << 3)
85+#define OABUFFER_SIZE_256K (1 << 3)
86+#define OABUFFER_SIZE_512K (2 << 3)
87+#define OABUFFER_SIZE_1M (3 << 3)
88+#define OABUFFER_SIZE_2M (4 << 3)
89+#define OABUFFER_SIZE_4M (5 << 3)
90+#define OABUFFER_SIZE_8M (6 << 3)
91+#define OABUFFER_SIZE_16M (7 << 3)
92+
93+#define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
94+
95+/* Gen12 OAR unit */
96+#define GEN12_OAR_OACONTROL _MMIO(0x2960)
97+#define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
98+#define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0)
99+
100+#define GEN12_OACTXCONTROL _MMIO(0x2360)
101+#define GEN12_OAR_OASTATUS _MMIO(0x2968)
102+
103+/* Gen12 OAG unit */
104+#define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
105+#define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
106+#define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
107+#define GEN12_OAG_OATAILPTR_MASK 0xffffffc0
108+
109+#define GEN12_OAG_OABUFFER _MMIO(0xdb08)
110+#define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7)
111+#define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3)
112+#define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */
113+
114+#define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
115+#define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2
116+#define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1)
117+#define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0)
118+
119+#define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
120+#define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2
121+#define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0)
122+
123+#define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
124+#define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
125+#define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
126+#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
127+#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
128+
129+#define GEN12_OAG_OASTATUS _MMIO(0xdafc)
130+#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
131+#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
132+#define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0)
133+
134+#define GDT_CHICKEN_BITS _MMIO(0x9840)
135+#define GT_NOA_ENABLE 0x00000080
136+
137+#endif /* __INTEL_PERF_OA_REGS__ */
drivers/gpu/drm/i915/i915_perf_types.h+1−1
@@ -18,7 +18,7 @@ · 17 unmodified lines
1818 #include <uapi/drm/i915_drm.h>
1919
2020 #include "gt/intel_sseu.h"
21−#include "i915_reg.h"
21+#include "i915_reg_defs.h"
2222 #include "intel_wakeref.h"
2323
2424 struct drm_i915_private;
drivers/gpu/drm/i915/i915_pmu.c+2−0
@@ -8,8 +8,10 @@ · 7 unmodified lines
88
99 #include "gt/intel_engine.h"
1010 #include "gt/intel_engine_pm.h"
11+#include "gt/intel_engine_regs.h"
1112 #include "gt/intel_engine_user.h"
1213 #include "gt/intel_gt_pm.h"
14+#include "gt/intel_gt_regs.h"
1315 #include "gt/intel_rc6.h"
1416 #include "gt/intel_rps.h"
1517
drivers/gpu/drm/i915/i915_reg.h+506−3596
@@ -25,8 +25,7 @@ · 24 unmodified lines
2525 #ifndef _I915_REG_H_
2626 #define _I915_REG_H_
2727
28−#include <linux/bitfield.h>
29−#include <linux/bits.h>
28+#include "i915_reg_defs.h"
3029
3130 /**
3231 * DOC: The i915 register macro definition style guide
@@ -116,92 +115,6 @@ · 83 unmodified lines
116115 * #define GEN8_BAR _MMIO(0xb888)
117116 */
118117
119−/**
120− * REG_BIT() - Prepare a u32 bit value
121− * @__n: 0-based bit number
122− *
123− * Local wrapper for BIT() to force u32, with compile time checks.
124− *
125− * @return: Value with bit @__n set.
126− */
127−#define REG_BIT(__n) \
128− ((u32)(BIT(__n) + \
129− BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
130− ((__n) < 0 || (__n) > 31))))
131−
132−/**
133− * REG_GENMASK() - Prepare a continuous u32 bitmask
134− * @__high: 0-based high bit
135− * @__low: 0-based low bit
136− *
137− * Local wrapper for GENMASK() to force u32, with compile time checks.
138− *
139− * @return: Continuous bitmask from @__high to @__low, inclusive.
140− */
141−#define REG_GENMASK(__high, __low) \
142− ((u32)(GENMASK(__high, __low) + \
143− BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
144− __is_constexpr(__low) && \
145− ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
146−
147−/*
148− * Local integer constant expression version of is_power_of_2().
149− */
150−#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
151−
152−/**
153− * REG_FIELD_PREP() - Prepare a u32 bitfield value
154− * @__mask: shifted mask defining the field's length and position
155− * @__val: value to put in the field
156− *
157− * Local copy of FIELD_PREP() to generate an integer constant expression, force
158− * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
159− *
160− * @return: @__val masked and shifted into the field defined by @__mask.
161− */
162−#define REG_FIELD_PREP(__mask, __val) \
163− ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
164− BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
165− BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
166− BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
167− BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
168−
169−/**
170− * REG_FIELD_GET() - Extract a u32 bitfield value
171− * @__mask: shifted mask defining the field's length and position
172− * @__val: value to extract the bitfield value from
173− *
174− * Local wrapper for FIELD_GET() to force u32 and for consistency with
175− * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
176− *
177− * @return: Masked and shifted value of the field defined by @__mask in @__val.
178− */
179−#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
180−
181−typedef struct {
182− u32 reg;
183−} i915_reg_t;
184−
185−#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
186−
187−#define INVALID_MMIO_REG _MMIO(0)
188−
189−static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
190−{
191− return reg.reg;
192−}
193−
194−static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
195−{
196− return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
197−}
198−
199−static inline bool i915_mmio_reg_valid(i915_reg_t reg)
200−{
201− return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
202−}
203−
204−#define VLV_DISPLAY_BASE 0x180000
205118 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
206119 #define BXT_MIPI_BASE 0x60000
207120
@@ -275,247 +188,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 67 unmodified lines
275188 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
276189 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
277190
278−/* PCI config space */
279−
280−#define MCHBAR_I915 0x44
281−#define MCHBAR_I965 0x48
282−#define MCHBAR_SIZE (4 * 4096)
283−
284−#define DEVEN 0x54
285−#define DEVEN_MCHBAR_EN (1 << 28)
286−
287−/* BSM in include/drm/i915_drm.h */
288−
289−#define HPLLCC 0xc0 /* 85x only */
290−#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
291−#define GC_CLOCK_133_200 (0 << 0)
292−#define GC_CLOCK_100_200 (1 << 0)
293−#define GC_CLOCK_100_133 (2 << 0)
294−#define GC_CLOCK_133_266 (3 << 0)
295−#define GC_CLOCK_133_200_2 (4 << 0)
296−#define GC_CLOCK_133_266_2 (5 << 0)
297−#define GC_CLOCK_166_266 (6 << 0)
298−#define GC_CLOCK_166_250 (7 << 0)
299−
300−#define I915_GDRST 0xc0 /* PCI config register */
301−#define GRDOM_FULL (0 << 2)
302−#define GRDOM_RENDER (1 << 2)
303−#define GRDOM_MEDIA (3 << 2)
304−#define GRDOM_MASK (3 << 2)
305−#define GRDOM_RESET_STATUS (1 << 1)
306−#define GRDOM_RESET_ENABLE (1 << 0)
307−
308−/* BSpec only has register offset, PCI device and bit found empirically */
309−#define I830_CLOCK_GATE 0xc8 /* device 0 */
310−#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
311−
312−#define GCDGMBUS 0xcc
313−
314−#define GCFGC2 0xda
315−#define GCFGC 0xf0 /* 915+ only */
316−#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
317−#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
318−#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
319−#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
320−#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
321−#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
322−#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
323−#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
324−#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
325−#define GC_DISPLAY_CLOCK_MASK (7 << 4)
326−#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
327−#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
328−#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
329−#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
330−#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
331−#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
332−#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
333−#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
334−#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
335−#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
336−#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
337−#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
338−#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
339−#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
340−#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
341−#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
342−#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
343−#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
344−#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
345−
346−#define ASLE 0xe4
347−#define ASLS 0xfc
348−
349−#define SWSCI 0xe8
350−#define SWSCI_SCISEL (1 << 15)
351−#define SWSCI_GSSCIE (1 << 0)
352−
353−#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
354−
355−
356−#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
357−#define ILK_GRDOM_FULL (0 << 1)
358−#define ILK_GRDOM_RENDER (1 << 1)
359−#define ILK_GRDOM_MEDIA (3 << 1)
360−#define ILK_GRDOM_MASK (3 << 1)
361−#define ILK_GRDOM_RESET_ENABLE (1 << 0)
362−
363−#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
364−#define GEN6_MBC_SNPCR_SHIFT 21
365−#define GEN6_MBC_SNPCR_MASK (3 << 21)
366−#define GEN6_MBC_SNPCR_MAX (0 << 21)
367−#define GEN6_MBC_SNPCR_MED (1 << 21)
368−#define GEN6_MBC_SNPCR_LOW (2 << 21)
369−#define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */
370−
371−#define VLV_G3DCTL _MMIO(0x9024)
372−#define VLV_GSCKGCTL _MMIO(0x9028)
373−
374−#define FBC_LLC_READ_CTRL _MMIO(0x9044)
375−#define FBC_LLC_FULLY_OPEN REG_BIT(30)
376−
377−#define GEN6_MBCTL _MMIO(0x0907c)
378−#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
379−#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
380−#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
381−#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
382−#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
383−
384−#define GEN6_GDRST _MMIO(0x941c)
385−#define GEN6_GRDOM_FULL (1 << 0)
386−#define GEN6_GRDOM_RENDER (1 << 1)
387−#define GEN6_GRDOM_MEDIA (1 << 2)
388−#define GEN6_GRDOM_BLT (1 << 3)
389−#define GEN6_GRDOM_VECS (1 << 4)
390−#define GEN9_GRDOM_GUC (1 << 5)
391−#define GEN8_GRDOM_MEDIA2 (1 << 7)
392−/* GEN11 changed all bit defs except for FULL & RENDER */
393−#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
394−#define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
395−#define GEN11_GRDOM_BLT (1 << 2)
396−#define GEN11_GRDOM_GUC (1 << 3)
397−#define GEN11_GRDOM_MEDIA (1 << 5)
398−#define GEN11_GRDOM_MEDIA2 (1 << 6)
399−#define GEN11_GRDOM_MEDIA3 (1 << 7)
400−#define GEN11_GRDOM_MEDIA4 (1 << 8)
401−#define GEN11_GRDOM_MEDIA5 (1 << 9)
402−#define GEN11_GRDOM_MEDIA6 (1 << 10)
403−#define GEN11_GRDOM_MEDIA7 (1 << 11)
404−#define GEN11_GRDOM_MEDIA8 (1 << 12)
405−#define GEN11_GRDOM_VECS (1 << 13)
406−#define GEN11_GRDOM_VECS2 (1 << 14)
407−#define GEN11_GRDOM_VECS3 (1 << 15)
408−#define GEN11_GRDOM_VECS4 (1 << 16)
409−#define GEN11_GRDOM_SFC0 (1 << 17)
410−#define GEN11_GRDOM_SFC1 (1 << 18)
411−#define GEN11_GRDOM_SFC2 (1 << 19)
412−#define GEN11_GRDOM_SFC3 (1 << 20)
413−
414−#define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1))
415−#define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance))
416−
417−#define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C)
418−#define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0)
419−#define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890)
420−#define GEN11_VCS_SFC_USAGE_BIT (1 << 0)
421−#define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1)
422−
423−#define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C)
424−#define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0)
425−#define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018)
426−#define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0)
427−#define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
428−#define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
429−
430−#define GEN12_HCP_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x2910)
431−#define GEN12_HCP_SFC_FORCED_LOCK_BIT REG_BIT(0)
432−#define GEN12_HCP_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x2914)
433−#define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1)
434−#define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0)
435−
436−#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
437−#define GEN12_SFC_DONE_MAX 4
438−
439−#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
440−#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
441−#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
442−#define PP_DIR_DCLV_2G 0xffffffff
443−
444−#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
445−#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
446−
447−#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
448−#define GEN8_RPCS_ENABLE (1 << 31)
449−#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
450−#define GEN8_RPCS_S_CNT_SHIFT 15
451−#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
452−#define GEN11_RPCS_S_CNT_SHIFT 12
453−#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
454−#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
455−#define GEN8_RPCS_SS_CNT_SHIFT 8
456−#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
457−#define GEN8_RPCS_EU_MAX_SHIFT 4
458−#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
459−#define GEN8_RPCS_EU_MIN_SHIFT 0
460−#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
461−
462−#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
463−/* HSW only */
464−#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
465−#define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
466−#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
467−#define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
468−/* HSW+ */
469−#define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
470−#define HSW_RCS_CONTEXT_ENABLE (1 << 7)
471−#define HSW_RCS_INHIBIT (1 << 8)
472−/* Gen8 */
473−#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
474−#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
475−#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
476−#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
477−#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
478−#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
479−#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
480−#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
481−#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
482−#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
483−
484−#define GAM_ECOCHK _MMIO(0x4090)
485−#define BDW_DISABLE_HDC_INVALIDATION (1 << 25)
486−#define ECOCHK_SNB_BIT (1 << 10)
487−#define ECOCHK_DIS_TLB (1 << 8)
488−#define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6)
489−#define ECOCHK_PPGTT_CACHE64B (0x3 << 3)
490−#define ECOCHK_PPGTT_CACHE4B (0x0 << 3)
491−#define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4)
492−#define ECOCHK_PPGTT_LLC_IVB (0x1 << 3)
493−#define ECOCHK_PPGTT_UC_HSW (0x1 << 3)
494−#define ECOCHK_PPGTT_WT_HSW (0x2 << 3)
495−#define ECOCHK_PPGTT_WB_HSW (0x3 << 3)
496−
497−#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
498−
499−#define GAC_ECO_BITS _MMIO(0x14090)
500−#define ECOBITS_SNB_BIT (1 << 13)
501−#define ECOBITS_PPGTT_CACHE64B (3 << 8)
502−#define ECOBITS_PPGTT_CACHE4B (0 << 8)
503−
504−#define GEN12_GAMCNTRL_CTRL _MMIO(0xcf54)
505−#define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
506−#define GLOBAL_INVALIDATION_MODE REG_BIT(2)
507−
508−#define GEN12_GAMSTLB_CTRL _MMIO(0xcf4c)
509−#define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12)
510−#define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11)
511−#define TAG_BLOCK_CLKGATE_DIS REG_BIT(7)
512−
513−#define GEN12_MERT_MOD_CTRL _MMIO(0xcf28)
514−#define FORCE_MISS_FTLB REG_BIT(3)
515−
516−#define GAB_CTL _MMIO(0x24000)
517−#define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
518−
519191 #define GU_CNTL _MMIO(0x101010)
520192 #define LMEM_INIT REG_BIT(7)
521193
@@ -538,671 +210,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 16 unmodified lines
538210 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
539211 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
540212
541−/* VGA stuff */
542−
543−#define VGA_ST01_MDA 0x3ba
544−#define VGA_ST01_CGA 0x3da
545−
546213 #define _VGA_MSR_WRITE _MMIO(0x3c2)
547−#define VGA_MSR_WRITE 0x3c2
548−#define VGA_MSR_READ 0x3cc
549−#define VGA_MSR_MEM_EN (1 << 1)
550−#define VGA_MSR_CGA_MODE (1 << 0)
551−
552−#define VGA_SR_INDEX 0x3c4
553−#define SR01 1
554−#define VGA_SR_DATA 0x3c5
555−
556−#define VGA_AR_INDEX 0x3c0
557−#define VGA_AR_VID_EN (1 << 5)
558−#define VGA_AR_DATA_WRITE 0x3c0
559−#define VGA_AR_DATA_READ 0x3c1
560−
561−#define VGA_GR_INDEX 0x3ce
562−#define VGA_GR_DATA 0x3cf
563−/* GR05 */
564−#define VGA_GR_MEM_READ_MODE_SHIFT 3
565−#define VGA_GR_MEM_READ_MODE_PLANE 1
566−/* GR06 */
567−#define VGA_GR_MEM_MODE_MASK 0xc
568−#define VGA_GR_MEM_MODE_SHIFT 2
569−#define VGA_GR_MEM_A0000_AFFFF 0
570−#define VGA_GR_MEM_A0000_BFFFF 1
571−#define VGA_GR_MEM_B0000_B7FFF 2
572−#define VGA_GR_MEM_B0000_BFFFF 3
573−
574−#define VGA_DACMASK 0x3c6
575−#define VGA_DACRX 0x3c7
576−#define VGA_DACWX 0x3c8
577−#define VGA_DACDATA 0x3c9
578−
579−#define VGA_CR_INDEX_MDA 0x3b4
580−#define VGA_CR_DATA_MDA 0x3b5
581−#define VGA_CR_INDEX_CGA 0x3d4
582−#define VGA_CR_DATA_CGA 0x3d5
583−
584−#define MI_PREDICATE_SRC0 _MMIO(0x2400)
585−#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
586−#define MI_PREDICATE_SRC1 _MMIO(0x2408)
587−#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
588−#define MI_PREDICATE_DATA _MMIO(0x2410)
589−#define MI_PREDICATE_RESULT _MMIO(0x2418)
590−#define MI_PREDICATE_RESULT_1 _MMIO(0x241c)
591−#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
592−#define LOWER_SLICE_ENABLED (1 << 0)
593−#define LOWER_SLICE_DISABLED (0 << 0)
594−
595−/*
596− * Registers used only by the command parser
597− */
598−#define BCS_SWCTRL _MMIO(0x22200)
599−#define BCS_SRC_Y REG_BIT(0)
600−#define BCS_DST_Y REG_BIT(1)
601−
602−/* There are 16 GPR registers */
603−#define BCS_GPR(n) _MMIO(0x22600 + (n) * 8)
604−#define BCS_GPR_UDW(n) _MMIO(0x22600 + (n) * 8 + 4)
605−
606−#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
607−#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
608−#define HS_INVOCATION_COUNT _MMIO(0x2300)
609−#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
610−#define DS_INVOCATION_COUNT _MMIO(0x2308)
611−#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
612−#define IA_VERTICES_COUNT _MMIO(0x2310)
613−#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
614−#define IA_PRIMITIVES_COUNT _MMIO(0x2318)
615−#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
616−#define VS_INVOCATION_COUNT _MMIO(0x2320)
617−#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
618−#define GS_INVOCATION_COUNT _MMIO(0x2328)
619−#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
620−#define GS_PRIMITIVES_COUNT _MMIO(0x2330)
621−#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
622−#define CL_INVOCATION_COUNT _MMIO(0x2338)
623−#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
624−#define CL_PRIMITIVES_COUNT _MMIO(0x2340)
625−#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
626−#define PS_INVOCATION_COUNT _MMIO(0x2348)
627−#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
628−#define PS_DEPTH_COUNT _MMIO(0x2350)
629−#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
630−
631−/* There are the 4 64-bit counter registers, one for each stream output */
632−#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
633−#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
634−
635−#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
636−#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
637−
638−#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
639−#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
640−#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
641−#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
642−#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
643−#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
644−
645−#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
646−#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
647−#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
648−
649−/* There are the 16 64-bit CS General Purpose Registers */
650−#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
651−#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
652−
653−#define GEN7_OACONTROL _MMIO(0x2360)
654−#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
655−#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
656−#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
657−#define GEN7_OACONTROL_TIMER_ENABLE (1 << 5)
658−#define GEN7_OACONTROL_FORMAT_A13 (0 << 2)
659−#define GEN7_OACONTROL_FORMAT_A29 (1 << 2)
660−#define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2)
661−#define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2)
662−#define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2)
663−#define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2)
664−#define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2)
665−#define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2)
666−#define GEN7_OACONTROL_FORMAT_SHIFT 2
667−#define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1)
668−#define GEN7_OACONTROL_ENABLE (1 << 0)
669−
670−#define GEN8_OACTXID _MMIO(0x2364)
671−
672−#define GEN8_OA_DEBUG _MMIO(0x2B04)
673−#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
674−#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
675−#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
676−#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
677−
678−#define GEN8_OACONTROL _MMIO(0x2B00)
679−#define GEN8_OA_REPORT_FORMAT_A12 (0 << 2)
680−#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2)
681−#define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2)
682−#define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2)
683−#define GEN8_OA_REPORT_FORMAT_SHIFT 2
684−#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1)
685−#define GEN8_OA_COUNTER_ENABLE (1 << 0)
686−
687−#define GEN8_OACTXCONTROL _MMIO(0x2360)
688−#define GEN8_OA_TIMER_PERIOD_MASK 0x3F
689−#define GEN8_OA_TIMER_PERIOD_SHIFT 2
690−#define GEN8_OA_TIMER_ENABLE (1 << 1)
691−#define GEN8_OA_COUNTER_RESUME (1 << 0)
692−
693−#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
694−#define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3)
695−#define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2)
696−#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1)
697−#define GEN7_OABUFFER_RESUME (1 << 0)
698−
699−#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
700−#define GEN8_OABUFFER _MMIO(0x2b14)
701−#define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
702−
703−#define GEN7_OASTATUS1 _MMIO(0x2364)
704−#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
705−#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
706−#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
707−#define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
708−
709−#define GEN7_OASTATUS2 _MMIO(0x2368)
710−#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
711−#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
712−
713−#define GEN8_OASTATUS _MMIO(0x2b08)
714−#define GEN8_OASTATUS_TAIL_POINTER_WRAP (1 << 17)
715−#define GEN8_OASTATUS_HEAD_POINTER_WRAP (1 << 16)
716−#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
717−#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
718−#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1)
719−#define GEN8_OASTATUS_REPORT_LOST (1 << 0)
720−
721−#define GEN8_OAHEADPTR _MMIO(0x2B0C)
722−#define GEN8_OAHEADPTR_MASK 0xffffffc0
723−#define GEN8_OATAILPTR _MMIO(0x2B10)
724−#define GEN8_OATAILPTR_MASK 0xffffffc0
725−
726−#define OABUFFER_SIZE_128K (0 << 3)
727−#define OABUFFER_SIZE_256K (1 << 3)
728−#define OABUFFER_SIZE_512K (2 << 3)
729−#define OABUFFER_SIZE_1M (3 << 3)
730−#define OABUFFER_SIZE_2M (4 << 3)
731−#define OABUFFER_SIZE_4M (5 << 3)
732−#define OABUFFER_SIZE_8M (6 << 3)
733−#define OABUFFER_SIZE_16M (7 << 3)
734−
735−#define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
736−
737−#define GEN12_SQCM _MMIO(0x8724)
738−#define EN_32B_ACCESS REG_BIT(30)
739−
740−/* Gen12 OAR unit */
741−#define GEN12_OAR_OACONTROL _MMIO(0x2960)
742−#define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
743−#define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0)
744−
745−#define GEN12_OACTXCONTROL _MMIO(0x2360)
746−#define GEN12_OAR_OASTATUS _MMIO(0x2968)
747−
748−/* Gen12 OAG unit */
749−#define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
750−#define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
751−#define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
752−#define GEN12_OAG_OATAILPTR_MASK 0xffffffc0
753−
754−#define GEN12_OAG_OABUFFER _MMIO(0xdb08)
755−#define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7)
756−#define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3)
757−#define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */
758−
759−#define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
760−#define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2
761−#define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1)
762−#define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0)
763−
764−#define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
765−#define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2
766−#define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0)
767−
768−#define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
769−#define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
770−#define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
771−#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
772−#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
773−
774−#define GEN12_OAG_OASTATUS _MMIO(0xdafc)
775−#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
776−#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
777−#define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0)
778−
779−/*
780− * Flexible, Aggregate EU Counter Registers.
781− * Note: these aren't contiguous
782− */
783−#define EU_PERF_CNTL0 _MMIO(0xe458)
784−#define EU_PERF_CNTL1 _MMIO(0xe558)
785−#define EU_PERF_CNTL2 _MMIO(0xe658)
786−#define EU_PERF_CNTL3 _MMIO(0xe758)
787−#define EU_PERF_CNTL4 _MMIO(0xe45c)
788−#define EU_PERF_CNTL5 _MMIO(0xe55c)
789−#define EU_PERF_CNTL6 _MMIO(0xe65c)
790−
791−#define RT_CTRL _MMIO(0xe530)
792−#define DIS_NULL_QUERY REG_BIT(10)
793−
794−/*
795− * OA Boolean state
796− */
797−
798−#define OASTARTTRIG1 _MMIO(0x2710)
799−#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
800−#define OASTARTTRIG1_THRESHOLD_MASK 0xffff
801−
802−#define OASTARTTRIG2 _MMIO(0x2714)
803−#define OASTARTTRIG2_INVERT_A_0 (1 << 0)
804−#define OASTARTTRIG2_INVERT_A_1 (1 << 1)
805−#define OASTARTTRIG2_INVERT_A_2 (1 << 2)
806−#define OASTARTTRIG2_INVERT_A_3 (1 << 3)
807−#define OASTARTTRIG2_INVERT_A_4 (1 << 4)
808−#define OASTARTTRIG2_INVERT_A_5 (1 << 5)
809−#define OASTARTTRIG2_INVERT_A_6 (1 << 6)
810−#define OASTARTTRIG2_INVERT_A_7 (1 << 7)
811−#define OASTARTTRIG2_INVERT_A_8 (1 << 8)
812−#define OASTARTTRIG2_INVERT_A_9 (1 << 9)
813−#define OASTARTTRIG2_INVERT_A_10 (1 << 10)
814−#define OASTARTTRIG2_INVERT_A_11 (1 << 11)
815−#define OASTARTTRIG2_INVERT_A_12 (1 << 12)
816−#define OASTARTTRIG2_INVERT_A_13 (1 << 13)
817−#define OASTARTTRIG2_INVERT_A_14 (1 << 14)
818−#define OASTARTTRIG2_INVERT_A_15 (1 << 15)
819−#define OASTARTTRIG2_INVERT_B_0 (1 << 16)
820−#define OASTARTTRIG2_INVERT_B_1 (1 << 17)
821−#define OASTARTTRIG2_INVERT_B_2 (1 << 18)
822−#define OASTARTTRIG2_INVERT_B_3 (1 << 19)
823−#define OASTARTTRIG2_INVERT_C_0 (1 << 20)
824−#define OASTARTTRIG2_INVERT_C_1 (1 << 21)
825−#define OASTARTTRIG2_INVERT_D_0 (1 << 22)
826−#define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23)
827−#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24)
828−#define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28)
829−#define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29)
830−#define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30)
831−#define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31)
832−
833−#define OASTARTTRIG3 _MMIO(0x2718)
834−#define OASTARTTRIG3_NOA_SELECT_MASK 0xf
835−#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
836−#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
837−#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
838−#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
839−#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
840−#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
841−#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
842−#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
843−
844−#define OASTARTTRIG4 _MMIO(0x271c)
845−#define OASTARTTRIG4_NOA_SELECT_MASK 0xf
846−#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
847−#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
848−#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
849−#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
850−#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
851−#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
852−#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
853−#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
854−
855−#define OASTARTTRIG5 _MMIO(0x2720)
856−#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
857−#define OASTARTTRIG5_THRESHOLD_MASK 0xffff
858−
859−#define OASTARTTRIG6 _MMIO(0x2724)
860−#define OASTARTTRIG6_INVERT_A_0 (1 << 0)
861−#define OASTARTTRIG6_INVERT_A_1 (1 << 1)
862−#define OASTARTTRIG6_INVERT_A_2 (1 << 2)
863−#define OASTARTTRIG6_INVERT_A_3 (1 << 3)
864−#define OASTARTTRIG6_INVERT_A_4 (1 << 4)
865−#define OASTARTTRIG6_INVERT_A_5 (1 << 5)
866−#define OASTARTTRIG6_INVERT_A_6 (1 << 6)
867−#define OASTARTTRIG6_INVERT_A_7 (1 << 7)
868−#define OASTARTTRIG6_INVERT_A_8 (1 << 8)
869−#define OASTARTTRIG6_INVERT_A_9 (1 << 9)
870−#define OASTARTTRIG6_INVERT_A_10 (1 << 10)
871−#define OASTARTTRIG6_INVERT_A_11 (1 << 11)
872−#define OASTARTTRIG6_INVERT_A_12 (1 << 12)
873−#define OASTARTTRIG6_INVERT_A_13 (1 << 13)
874−#define OASTARTTRIG6_INVERT_A_14 (1 << 14)
875−#define OASTARTTRIG6_INVERT_A_15 (1 << 15)
876−#define OASTARTTRIG6_INVERT_B_0 (1 << 16)
877−#define OASTARTTRIG6_INVERT_B_1 (1 << 17)
878−#define OASTARTTRIG6_INVERT_B_2 (1 << 18)
879−#define OASTARTTRIG6_INVERT_B_3 (1 << 19)
880−#define OASTARTTRIG6_INVERT_C_0 (1 << 20)
881−#define OASTARTTRIG6_INVERT_C_1 (1 << 21)
882−#define OASTARTTRIG6_INVERT_D_0 (1 << 22)
883−#define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23)
884−#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24)
885−#define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28)
886−#define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29)
887−#define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30)
888−#define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31)
889−
890−#define OASTARTTRIG7 _MMIO(0x2728)
891−#define OASTARTTRIG7_NOA_SELECT_MASK 0xf
892−#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
893−#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
894−#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
895−#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
896−#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
897−#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
898−#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
899−#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
900−
901−#define OASTARTTRIG8 _MMIO(0x272c)
902−#define OASTARTTRIG8_NOA_SELECT_MASK 0xf
903−#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
904−#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
905−#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
906−#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
907−#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
908−#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
909−#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
910−#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
911−
912−#define OAREPORTTRIG1 _MMIO(0x2740)
913−#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
914−#define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
915−
916−#define OAREPORTTRIG2 _MMIO(0x2744)
917−#define OAREPORTTRIG2_INVERT_A_0 (1 << 0)
918−#define OAREPORTTRIG2_INVERT_A_1 (1 << 1)
919−#define OAREPORTTRIG2_INVERT_A_2 (1 << 2)
920−#define OAREPORTTRIG2_INVERT_A_3 (1 << 3)
921−#define OAREPORTTRIG2_INVERT_A_4 (1 << 4)
922−#define OAREPORTTRIG2_INVERT_A_5 (1 << 5)
923−#define OAREPORTTRIG2_INVERT_A_6 (1 << 6)
924−#define OAREPORTTRIG2_INVERT_A_7 (1 << 7)
925−#define OAREPORTTRIG2_INVERT_A_8 (1 << 8)
926−#define OAREPORTTRIG2_INVERT_A_9 (1 << 9)
927−#define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
928−#define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
929−#define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
930−#define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
931−#define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
932−#define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
933−#define OAREPORTTRIG2_INVERT_B_0 (1 << 16)
934−#define OAREPORTTRIG2_INVERT_B_1 (1 << 17)
935−#define OAREPORTTRIG2_INVERT_B_2 (1 << 18)
936−#define OAREPORTTRIG2_INVERT_B_3 (1 << 19)
937−#define OAREPORTTRIG2_INVERT_C_0 (1 << 20)
938−#define OAREPORTTRIG2_INVERT_C_1 (1 << 21)
939−#define OAREPORTTRIG2_INVERT_D_0 (1 << 22)
940−#define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23)
941−#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
942−
943−#define OAREPORTTRIG3 _MMIO(0x2748)
944−#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
945−#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
946−#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
947−#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
948−#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
949−#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
950−#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
951−#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
952−#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
953−
954−#define OAREPORTTRIG4 _MMIO(0x274c)
955−#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
956−#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
957−#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
958−#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
959−#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
960−#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
961−#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
962−#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
963−#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
964−
965−#define OAREPORTTRIG5 _MMIO(0x2750)
966−#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
967−#define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
968−
969−#define OAREPORTTRIG6 _MMIO(0x2754)
970−#define OAREPORTTRIG6_INVERT_A_0 (1 << 0)
971−#define OAREPORTTRIG6_INVERT_A_1 (1 << 1)
972−#define OAREPORTTRIG6_INVERT_A_2 (1 << 2)
973−#define OAREPORTTRIG6_INVERT_A_3 (1 << 3)
974−#define OAREPORTTRIG6_INVERT_A_4 (1 << 4)
975−#define OAREPORTTRIG6_INVERT_A_5 (1 << 5)
976−#define OAREPORTTRIG6_INVERT_A_6 (1 << 6)
977−#define OAREPORTTRIG6_INVERT_A_7 (1 << 7)
978−#define OAREPORTTRIG6_INVERT_A_8 (1 << 8)
979−#define OAREPORTTRIG6_INVERT_A_9 (1 << 9)
980−#define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
981−#define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
982−#define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
983−#define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
984−#define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
985−#define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
986−#define OAREPORTTRIG6_INVERT_B_0 (1 << 16)
987−#define OAREPORTTRIG6_INVERT_B_1 (1 << 17)
988−#define OAREPORTTRIG6_INVERT_B_2 (1 << 18)
989−#define OAREPORTTRIG6_INVERT_B_3 (1 << 19)
990−#define OAREPORTTRIG6_INVERT_C_0 (1 << 20)
991−#define OAREPORTTRIG6_INVERT_C_1 (1 << 21)
992−#define OAREPORTTRIG6_INVERT_D_0 (1 << 22)
993−#define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23)
994−#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
995−
996−#define OAREPORTTRIG7 _MMIO(0x2758)
997−#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
998−#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
999−#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
1000−#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
1001−#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
1002−#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
1003−#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
1004−#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
1005−#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
1006−
1007−#define OAREPORTTRIG8 _MMIO(0x275c)
1008−#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
1009−#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
1010−#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
1011−#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
1012−#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
1013−#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
1014−#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
1015−#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
1016−#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
1017−
1018−/* Same layout as OASTARTTRIGX */
1019−#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
1020−#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
1021−#define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
1022−#define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
1023−#define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
1024−#define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
1025−#define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
1026−#define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
1027−
1028−/* Same layout as OAREPORTTRIGX */
1029−#define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
1030−#define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
1031−#define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
1032−#define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
1033−#define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
1034−#define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
1035−#define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
1036−#define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
1037−
1038−/* CECX_0 */
1039−#define OACEC_COMPARE_LESS_OR_EQUAL 6
1040−#define OACEC_COMPARE_NOT_EQUAL 5
1041−#define OACEC_COMPARE_LESS_THAN 4
1042−#define OACEC_COMPARE_GREATER_OR_EQUAL 3
1043−#define OACEC_COMPARE_EQUAL 2
1044−#define OACEC_COMPARE_GREATER_THAN 1
1045−#define OACEC_COMPARE_ANY_EQUAL 0
1046−
1047−#define OACEC_COMPARE_VALUE_MASK 0xffff
1048−#define OACEC_COMPARE_VALUE_SHIFT 3
1049−
1050−#define OACEC_SELECT_NOA (0 << 19)
1051−#define OACEC_SELECT_PREV (1 << 19)
1052−#define OACEC_SELECT_BOOLEAN (2 << 19)
1053−
1054−/* 11-bit array 0: pass-through, 1: negated */
1055−#define GEN12_OASCEC_NEGATE_MASK 0x7ff
1056−#define GEN12_OASCEC_NEGATE_SHIFT 21
1057−
1058−/* CECX_1 */
1059−#define OACEC_MASK_MASK 0xffff
1060−#define OACEC_CONSIDERATIONS_MASK 0xffff
1061−#define OACEC_CONSIDERATIONS_SHIFT 16
1062−
1063−#define OACEC0_0 _MMIO(0x2770)
1064−#define OACEC0_1 _MMIO(0x2774)
1065−#define OACEC1_0 _MMIO(0x2778)
1066−#define OACEC1_1 _MMIO(0x277c)
1067−#define OACEC2_0 _MMIO(0x2780)
1068−#define OACEC2_1 _MMIO(0x2784)
1069−#define OACEC3_0 _MMIO(0x2788)
1070−#define OACEC3_1 _MMIO(0x278c)
1071−#define OACEC4_0 _MMIO(0x2790)
1072−#define OACEC4_1 _MMIO(0x2794)
1073−#define OACEC5_0 _MMIO(0x2798)
1074−#define OACEC5_1 _MMIO(0x279c)
1075−#define OACEC6_0 _MMIO(0x27a0)
1076−#define OACEC6_1 _MMIO(0x27a4)
1077−#define OACEC7_0 _MMIO(0x27a8)
1078−#define OACEC7_1 _MMIO(0x27ac)
1079−
1080−/* Same layout as CECX_Y */
1081−#define GEN12_OAG_CEC0_0 _MMIO(0xd940)
1082−#define GEN12_OAG_CEC0_1 _MMIO(0xd944)
1083−#define GEN12_OAG_CEC1_0 _MMIO(0xd948)
1084−#define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
1085−#define GEN12_OAG_CEC2_0 _MMIO(0xd950)
1086−#define GEN12_OAG_CEC2_1 _MMIO(0xd954)
1087−#define GEN12_OAG_CEC3_0 _MMIO(0xd958)
1088−#define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
1089−#define GEN12_OAG_CEC4_0 _MMIO(0xd960)
1090−#define GEN12_OAG_CEC4_1 _MMIO(0xd964)
1091−#define GEN12_OAG_CEC5_0 _MMIO(0xd968)
1092−#define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
1093−#define GEN12_OAG_CEC6_0 _MMIO(0xd970)
1094−#define GEN12_OAG_CEC6_1 _MMIO(0xd974)
1095−#define GEN12_OAG_CEC7_0 _MMIO(0xd978)
1096−#define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
1097−
1098−/* Same layout as CECX_Y + negate 11-bit array */
1099−#define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
1100−#define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
1101−#define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
1102−#define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
1103−#define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
1104−#define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
1105−#define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
1106−#define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
1107−#define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
1108−#define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
1109−#define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
1110−#define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
1111−#define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
1112−#define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
1113−#define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
1114−#define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
1115−
1116−/* OA perf counters */
1117−#define OA_PERFCNT1_LO _MMIO(0x91B8)
1118−#define OA_PERFCNT1_HI _MMIO(0x91BC)
1119−#define OA_PERFCNT2_LO _MMIO(0x91C0)
1120−#define OA_PERFCNT2_HI _MMIO(0x91C4)
1121−#define OA_PERFCNT3_LO _MMIO(0x91C8)
1122−#define OA_PERFCNT3_HI _MMIO(0x91CC)
1123−#define OA_PERFCNT4_LO _MMIO(0x91D8)
1124−#define OA_PERFCNT4_HI _MMIO(0x91DC)
1125−
1126−#define OA_PERFMATRIX_LO _MMIO(0x91C8)
1127−#define OA_PERFMATRIX_HI _MMIO(0x91CC)
1128−
1129−/* RPM unit config (Gen8+) */
1130−#define RPM_CONFIG0 _MMIO(0x0D00)
1131−#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
1132−#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1133−#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
1134−#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
1135−#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
1136−#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1137−#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
1138−#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
1139−#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
1140−#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
1141−#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
1142−#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
1143−
1144−#define RPM_CONFIG1 _MMIO(0x0D04)
1145−#define GEN10_GT_NOA_ENABLE (1 << 9)
1146−
1147−/* GPM unit config (Gen9+) */
1148−#define CTC_MODE _MMIO(0xA26C)
1149−#define CTC_SOURCE_PARAMETER_MASK 1
1150−#define CTC_SOURCE_CRYSTAL_CLOCK 0
1151−#define CTC_SOURCE_DIVIDE_LOGIC 1
1152−#define CTC_SHIFT_PARAMETER_SHIFT 1
1153−#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1154−
1155−/* RCP unit config (Gen8+) */
1156−#define RCP_CONFIG _MMIO(0x0D08)
1157−
1158−/* NOA (HSW) */
1159−#define HSW_MBVID2_NOA0 _MMIO(0x9E80)
1160−#define HSW_MBVID2_NOA1 _MMIO(0x9E84)
1161−#define HSW_MBVID2_NOA2 _MMIO(0x9E88)
1162−#define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
1163−#define HSW_MBVID2_NOA4 _MMIO(0x9E90)
1164−#define HSW_MBVID2_NOA5 _MMIO(0x9E94)
1165−#define HSW_MBVID2_NOA6 _MMIO(0x9E98)
1166−#define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
1167−#define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
1168−#define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
1169−
1170−#define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
1171−
1172−/* NOA (Gen8+) */
1173−#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
1174−
1175−#define MICRO_BP0_0 _MMIO(0x9800)
1176−#define MICRO_BP0_2 _MMIO(0x9804)
1177−#define MICRO_BP0_1 _MMIO(0x9808)
1178−
1179−#define MICRO_BP1_0 _MMIO(0x980C)
1180−#define MICRO_BP1_2 _MMIO(0x9810)
1181−#define MICRO_BP1_1 _MMIO(0x9814)
1182−
1183−#define MICRO_BP2_0 _MMIO(0x9818)
1184−#define MICRO_BP2_2 _MMIO(0x981C)
1185−#define MICRO_BP2_1 _MMIO(0x9820)
1186−
1187−#define MICRO_BP3_0 _MMIO(0x9824)
1188−#define MICRO_BP3_2 _MMIO(0x9828)
1189−#define MICRO_BP3_1 _MMIO(0x982C)
1190−
1191−#define MICRO_BP_TRIGGER _MMIO(0x9830)
1192−#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
1193−#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
1194−#define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
1195−
1196−#define GEN12_OAA_DBG_REG _MMIO(0xdc44)
1197−#define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
1198−#define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
1199−
1200−#define GDT_CHICKEN_BITS _MMIO(0x9840)
1201−#define GT_NOA_ENABLE 0x00000080
1202−
1203−#define NOA_DATA _MMIO(0x986C)
1204−#define NOA_WRITE _MMIO(0x9888)
1205−#define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
1206214
1207215 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
1208216 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
@@ -1244,177 +252,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 35 unmodified lines
1244252 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1245253 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
1246254
1247−/* See configdb bunit SB addr map */
1248−#define BUNIT_REG_BISOC 0x11
1249−
1250−/* PUNIT_REG_*SSPM0 */
1251−#define _SSPM0_SSC(val) ((val) << 0)
1252−#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
1253−#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
1254−#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
1255−#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
1256−#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
1257−#define _SSPM0_SSS(val) ((val) << 24)
1258−#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
1259−#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
1260−#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
1261−#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
1262−#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
1263−
1264−/* PUNIT_REG_*SSPM1 */
1265−#define SSPM1_FREQSTAT_SHIFT 24
1266−#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
1267−#define SSPM1_FREQGUAR_SHIFT 8
1268−#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
1269−#define SSPM1_FREQ_SHIFT 0
1270−#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
1271−
1272−#define PUNIT_REG_VEDSSPM0 0x32
1273−#define PUNIT_REG_VEDSSPM1 0x33
1274−
1275−#define PUNIT_REG_DSPSSPM 0x36
1276−#define DSPFREQSTAT_SHIFT_CHV 24
1277−#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1278−#define DSPFREQGUAR_SHIFT_CHV 8
1279−#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
1280−#define DSPFREQSTAT_SHIFT 30
1281−#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
1282−#define DSPFREQGUAR_SHIFT 14
1283−#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
1284−#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
1285−#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
1286−#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
1287−#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
1288−#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
1289−#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
1290−#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
1291−#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
1292−#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
1293−#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
1294−#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
1295−#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
1296−#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
1297−#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1298−#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
1299−
1300−#define PUNIT_REG_ISPSSPM0 0x39
1301−#define PUNIT_REG_ISPSSPM1 0x3a
1302−
1303−#define PUNIT_REG_PWRGT_CTRL 0x60
1304−#define PUNIT_REG_PWRGT_STATUS 0x61
1305−#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
1306−#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
1307−#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
1308−#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
1309−#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
1310−
1311−#define PUNIT_PWGT_IDX_RENDER 0
1312−#define PUNIT_PWGT_IDX_MEDIA 1
1313−#define PUNIT_PWGT_IDX_DISP2D 3
1314−#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
1315−#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
1316−#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
1317−#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
1318−#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
1319−#define PUNIT_PWGT_IDX_DPIO_RX0 10
1320−#define PUNIT_PWGT_IDX_DPIO_RX1 11
1321−#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
1322−
1323−#define PUNIT_REG_GPU_LFM 0xd3
1324−#define PUNIT_REG_GPU_FREQ_REQ 0xd4
1325−#define PUNIT_REG_GPU_FREQ_STS 0xd8
1326−#define GPLLENABLE (1 << 4)
1327−#define GENFREQSTATUS (1 << 0)
1328−#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
1329−#define PUNIT_REG_CZ_TIMESTAMP 0xce
1330−
1331−#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
1332−#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
1333−
1334−#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
1335−#define FB_GFX_FREQ_FUSE_MASK 0xff
1336−#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
1337−#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
1338−#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
1339−
1340−#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
1341−#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
1342−
1343−#define PUNIT_REG_DDR_SETUP2 0x139
1344−#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
1345−#define FORCE_DDR_LOW_FREQ (1 << 1)
1346−#define FORCE_DDR_HIGH_FREQ (1 << 0)
1347−
1348−#define PUNIT_GPU_STATUS_REG 0xdb
1349−#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1350−#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
1351−#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
1352−#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
1353−
1354−#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
1355−#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
1356−#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
1357−
1358−#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
1359−#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
1360−#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
1361−#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
1362−#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
1363−#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
1364−#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
1365−#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
1366−#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
1367−#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
1368−
1369−#define VLV_TURBO_SOC_OVERRIDE 0x04
1370−#define VLV_OVERRIDE_EN 1
1371−#define VLV_SOC_TDP_EN (1 << 1)
1372−#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
1373−#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
1374−
1375−/* vlv2 north clock has */
1376−#define CCK_FUSE_REG 0x8
1377−#define CCK_FUSE_HPLL_FREQ_MASK 0x3
1378−#define CCK_REG_DSI_PLL_FUSE 0x44
1379−#define CCK_REG_DSI_PLL_CONTROL 0x48
1380−#define DSI_PLL_VCO_EN (1 << 31)
1381−#define DSI_PLL_LDO_GATE (1 << 30)
1382−#define DSI_PLL_P1_POST_DIV_SHIFT 17
1383−#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
1384−#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
1385−#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
1386−#define DSI_PLL_MUX_MASK (3 << 9)
1387−#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
1388−#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
1389−#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
1390−#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
1391−#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
1392−#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
1393−#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
1394−#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
1395−#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
1396−#define DSI_PLL_LOCK (1 << 0)
1397−#define CCK_REG_DSI_PLL_DIVIDER 0x4c
1398−#define DSI_PLL_LFSR (1 << 31)
1399−#define DSI_PLL_FRACTION_EN (1 << 30)
1400−#define DSI_PLL_FRAC_COUNTER_SHIFT 27
1401−#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
1402−#define DSI_PLL_USYNC_CNT_SHIFT 18
1403−#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
1404−#define DSI_PLL_N1_DIV_SHIFT 16
1405−#define DSI_PLL_N1_DIV_MASK (3 << 16)
1406−#define DSI_PLL_M1_DIV_SHIFT 0
1407−#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
1408−#define CCK_CZ_CLOCK_CONTROL 0x62
1409−#define CCK_GPLL_CLOCK_CONTROL 0x67
1410−#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
1411−#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
1412−#define CCK_TRUNK_FORCE_ON (1 << 17)
1413−#define CCK_TRUNK_FORCE_OFF (1 << 16)
1414−#define CCK_FREQUENCY_STATUS (0x1f << 8)
1415−#define CCK_FREQUENCY_STATUS_SHIFT 8
1416−#define CCK_FREQUENCY_VALUES (0x1f << 0)
1417−
1418255 /* DPIO registers */
1419256 #define DPIO_DEVFN 0
1420257
@@ -1905,402 +742,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 484 unmodified lines
1905742 #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1906743 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1907744
1908−/*
1909− * ICL Port/COMBO-PHY Registers
1910− */
1911−#define _ICL_COMBOPHY_A 0x162000
1912−#define _ICL_COMBOPHY_B 0x6C000
1913−#define _EHL_COMBOPHY_C 0x160000
1914−#define _RKL_COMBOPHY_D 0x161000
1915−#define _ADL_COMBOPHY_E 0x16B000
1916−
1917−#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
1918− _ICL_COMBOPHY_B, \
1919− _EHL_COMBOPHY_C, \
1920− _RKL_COMBOPHY_D, \
1921− _ADL_COMBOPHY_E)
1922−
1923−/* ICL Port CL_DW registers */
1924−#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
1925− 4 * (dw))
1926−
1927−#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
1928−#define CL_POWER_DOWN_ENABLE (1 << 4)
1929−#define SUS_CLOCK_CONFIG (3 << 0)
1930−
1931−#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
1932−#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
1933−#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
1934−#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
1935−#define PWR_UP_ALL_LANES (0x0 << 4)
1936−#define PWR_DOWN_LN_3_2_1 (0xe << 4)
1937−#define PWR_DOWN_LN_3_2 (0xc << 4)
1938−#define PWR_DOWN_LN_3 (0x8 << 4)
1939−#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
1940−#define PWR_DOWN_LN_1_0 (0x3 << 4)
1941−#define PWR_DOWN_LN_3_1 (0xa << 4)
1942−#define PWR_DOWN_LN_3_1_0 (0xb << 4)
1943−#define PWR_DOWN_LN_MASK (0xf << 4)
1944−#define PWR_DOWN_LN_SHIFT 4
1945−#define EDP4K2K_MODE_OVRD_EN (1 << 3)
1946−#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
1947−
1948−#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
1949−#define ICL_LANE_ENABLE_AUX (1 << 0)
1950−
1951−/* ICL Port COMP_DW registers */
1952−#define _ICL_PORT_COMP 0x100
1953−#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
1954− _ICL_PORT_COMP + 4 * (dw))
1955−
1956−#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
1957−#define COMP_INIT (1 << 31)
1958−
1959−#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
1960−
1961−#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
1962−#define PROCESS_INFO_DOT_0 (0 << 26)
1963−#define PROCESS_INFO_DOT_1 (1 << 26)
1964−#define PROCESS_INFO_DOT_4 (2 << 26)
1965−#define PROCESS_INFO_MASK (7 << 26)
1966−#define PROCESS_INFO_SHIFT 26
1967−#define VOLTAGE_INFO_0_85V (0 << 24)
1968−#define VOLTAGE_INFO_0_95V (1 << 24)
1969−#define VOLTAGE_INFO_1_05V (2 << 24)
1970−#define VOLTAGE_INFO_MASK (3 << 24)
1971−#define VOLTAGE_INFO_SHIFT 24
1972−
1973−#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
1974−#define IREFGEN (1 << 24)
1975−
1976−#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
1977−
1978−#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
1979−
1980−/* ICL Port PCS registers */
1981−#define _ICL_PORT_PCS_AUX 0x300
1982−#define _ICL_PORT_PCS_GRP 0x600
1983−#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
1984−#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
1985− _ICL_PORT_PCS_AUX + 4 * (dw))
1986−#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
1987− _ICL_PORT_PCS_GRP + 4 * (dw))
1988−#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
1989− _ICL_PORT_PCS_LN(ln) + 4 * (dw))
1990−#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
1991−#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
1992−#define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
1993−#define DCC_MODE_SELECT_MASK (0x3 << 20)
1994−#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
1995−#define COMMON_KEEPER_EN (1 << 26)
1996−#define LATENCY_OPTIM_MASK (0x3 << 2)
1997−#define LATENCY_OPTIM_VAL(x) ((x) << 2)
1998−
1999−/* ICL Port TX registers */
2000−#define _ICL_PORT_TX_AUX 0x380
2001−#define _ICL_PORT_TX_GRP 0x680
2002−#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
2003−
2004−#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
2005− _ICL_PORT_TX_AUX + 4 * (dw))
2006−#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
2007− _ICL_PORT_TX_GRP + 4 * (dw))
2008−#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
2009− _ICL_PORT_TX_LN(ln) + 4 * (dw))
2010−
2011−#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
2012−#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
2013−#define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
2014−#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
2015−#define SWING_SEL_UPPER_MASK (1 << 15)
2016−#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
2017−#define SWING_SEL_LOWER_MASK (0x7 << 11)
2018−#define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
2019−#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
2020−#define RCOMP_SCALAR(x) ((x) << 0)
2021−#define RCOMP_SCALAR_MASK (0xFF << 0)
2022−
2023−#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
2024−#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
2025−#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
2026−#define LOADGEN_SELECT (1 << 31)
2027−#define POST_CURSOR_1(x) ((x) << 12)
2028−#define POST_CURSOR_1_MASK (0x3F << 12)
2029−#define POST_CURSOR_2(x) ((x) << 6)
2030−#define POST_CURSOR_2_MASK (0x3F << 6)
2031−#define CURSOR_COEFF(x) ((x) << 0)
2032−#define CURSOR_COEFF_MASK (0x3F << 0)
2033−
2034−#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
2035−#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
2036−#define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
2037−#define TX_TRAINING_EN (1 << 31)
2038−#define TAP2_DISABLE (1 << 30)
2039−#define TAP3_DISABLE (1 << 29)
2040−#define SCALING_MODE_SEL(x) ((x) << 18)
2041−#define SCALING_MODE_SEL_MASK (0x7 << 18)
2042−#define RTERM_SELECT(x) ((x) << 3)
2043−#define RTERM_SELECT_MASK (0x7 << 3)
2044−
2045−#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
2046−#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
2047−#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
2048−#define N_SCALAR(x) ((x) << 24)
2049−#define N_SCALAR_MASK (0x7F << 24)
2050−
2051−#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
2052−#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
2053−#define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
2054−#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
2055−#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
2056−#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
2057−
2058−#define _ICL_DPHY_CHKN_REG 0x194
2059−#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
2060−#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
2061−
2062−#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
2063− _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
2064−
2065−#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
2066−#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
2067−#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
2068−#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
2069−#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
2070−#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
2071−#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
2072−#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
2073−#define MG_TX1_LINK_PARAMS(ln, tc_port) \
2074− MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
2075− MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
2076− MG_TX_LINK_PARAMS_TX1LN1_PORT1)
2077−
2078−#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
2079−#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
2080−#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
2081−#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
2082−#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
2083−#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
2084−#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
2085−#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
2086−#define MG_TX2_LINK_PARAMS(ln, tc_port) \
2087− MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
2088− MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
2089− MG_TX_LINK_PARAMS_TX2LN1_PORT1)
2090−#define CRI_USE_FS32 (1 << 5)
2091−
2092−#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
2093−#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
2094−#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
2095−#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
2096−#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
2097−#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
2098−#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
2099−#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
2100−#define MG_TX1_PISO_READLOAD(ln, tc_port) \
2101− MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
2102− MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
2103− MG_TX_PISO_READLOAD_TX1LN1_PORT1)
2104−
2105−#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
2106−#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
2107−#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
2108−#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
2109−#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
2110−#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
2111−#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
2112−#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
2113−#define MG_TX2_PISO_READLOAD(ln, tc_port) \
2114− MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
2115− MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
2116− MG_TX_PISO_READLOAD_TX2LN1_PORT1)
2117−#define CRI_CALCINIT (1 << 1)
2118−
2119−#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
2120−#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
2121−#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
2122−#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
2123−#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
2124−#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
2125−#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
2126−#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
2127−#define MG_TX1_SWINGCTRL(ln, tc_port) \
2128− MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
2129− MG_TX_SWINGCTRL_TX1LN0_PORT2, \
2130− MG_TX_SWINGCTRL_TX1LN1_PORT1)
2131−
2132−#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
2133−#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
2134−#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
2135−#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
2136−#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
2137−#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
2138−#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
2139−#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
2140−#define MG_TX2_SWINGCTRL(ln, tc_port) \
2141− MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
2142− MG_TX_SWINGCTRL_TX2LN0_PORT2, \
2143− MG_TX_SWINGCTRL_TX2LN1_PORT1)
2144−#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
2145−#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
2146−
2147−#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
2148−#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
2149−#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
2150−#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
2151−#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
2152−#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
2153−#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
2154−#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
2155−#define MG_TX1_DRVCTRL(ln, tc_port) \
2156− MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
2157− MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
2158− MG_TX_DRVCTRL_TX1LN1_TXPORT1)
2159−
2160−#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
2161−#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
2162−#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
2163−#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
2164−#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
2165−#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
2166−#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
2167−#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
2168−#define MG_TX2_DRVCTRL(ln, tc_port) \
2169− MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
2170− MG_TX_DRVCTRL_TX2LN0_PORT2, \
2171− MG_TX_DRVCTRL_TX2LN1_PORT1)
2172−#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
2173−#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
2174−#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
2175−#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
2176−#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
2177−#define CRI_LOADGEN_SEL(x) ((x) << 12)
2178−#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
2179−
2180−#define MG_CLKHUB_LN0_PORT1 0x16839C
2181−#define MG_CLKHUB_LN1_PORT1 0x16879C
2182−#define MG_CLKHUB_LN0_PORT2 0x16939C
2183−#define MG_CLKHUB_LN1_PORT2 0x16979C
2184−#define MG_CLKHUB_LN0_PORT3 0x16A39C
2185−#define MG_CLKHUB_LN1_PORT3 0x16A79C
2186−#define MG_CLKHUB_LN0_PORT4 0x16B39C
2187−#define MG_CLKHUB_LN1_PORT4 0x16B79C
2188−#define MG_CLKHUB(ln, tc_port) \
2189− MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
2190− MG_CLKHUB_LN0_PORT2, \
2191− MG_CLKHUB_LN1_PORT1)
2192−#define CFG_LOW_RATE_LKREN_EN (1 << 11)
2193−
2194−#define MG_TX_DCC_TX1LN0_PORT1 0x168110
2195−#define MG_TX_DCC_TX1LN1_PORT1 0x168510
2196−#define MG_TX_DCC_TX1LN0_PORT2 0x169110
2197−#define MG_TX_DCC_TX1LN1_PORT2 0x169510
2198−#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
2199−#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
2200−#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
2201−#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
2202−#define MG_TX1_DCC(ln, tc_port) \
2203− MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
2204− MG_TX_DCC_TX1LN0_PORT2, \
2205− MG_TX_DCC_TX1LN1_PORT1)
2206−#define MG_TX_DCC_TX2LN0_PORT1 0x168090
2207−#define MG_TX_DCC_TX2LN1_PORT1 0x168490
2208−#define MG_TX_DCC_TX2LN0_PORT2 0x169090
2209−#define MG_TX_DCC_TX2LN1_PORT2 0x169490
2210−#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
2211−#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
2212−#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
2213−#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
2214−#define MG_TX2_DCC(ln, tc_port) \
2215− MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
2216− MG_TX_DCC_TX2LN0_PORT2, \
2217− MG_TX_DCC_TX2LN1_PORT1)
2218−#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
2219−#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
2220−#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
2221−
2222−#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
2223−#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
2224−#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
2225−#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
2226−#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
2227−#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
2228−#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
2229−#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
2230−#define MG_DP_MODE(ln, tc_port) \
2231− MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
2232− MG_DP_MODE_LN0_ACU_PORT2, \
2233− MG_DP_MODE_LN1_ACU_PORT1)
2234−#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
2235−#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
2236−
2237−/*
2238− * DG2 SNPS PHY registers (TC1 = PHY_E)
2239− */
2240−#define _SNPS_PHY_A_BASE 0x168000
2241−#define _SNPS_PHY_B_BASE 0x169000
2242−#define _SNPS_PHY(phy) _PHY(phy, \
2243− _SNPS_PHY_A_BASE, \
2244− _SNPS_PHY_B_BASE)
2245−#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
2246− _SNPS_PHY_A_BASE + (reg))
2247−#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
2248−#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
2249− (reg) + (ln) * 0x10))
2250−
2251−#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
2252−#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
2253−#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
2254−#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
2255−#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
2256−
2257−#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
2258−#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
2259−#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
2260−#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
2261−#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
2262−#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
2263−#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
2264−#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
2265−#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
2266−#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
2267−#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
2268−#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
2269−
2270−#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
2271−#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
2272−#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
2273−#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
2274−
2275−#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
2276−#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
2277−#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
2278−
2279−#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
2280−#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
2281−#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
2282−#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
2283−
2284−#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
2285−#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
2286−
2287−#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
2288−#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
2289−#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
2290−#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
2291−#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
2292−
2293−#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
2294−#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
2295−
2296−#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
2297−#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
2298−
2299−#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
2300−#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
2301−#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
2302−#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
2303−
2304745 /* The spec defines this only for BXT PHY0, but lets assume that this
2305746 * would exist for PHY1 too if it had a second channel.
2306747 */
@@ -2309,21 +750,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 2 unmodified lines
2309750 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2310751 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2311752
2312−#define FIA1_BASE 0x163000
2313−#define FIA2_BASE 0x16E000
2314−#define FIA3_BASE 0x16F000
2315−#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
2316−#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
2317−
2318−/* ICL PHY DFLEX registers */
2319−#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
2320−#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
2321−#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
2322−#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
2323−#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
2324−#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
2325−#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
2326−
2327753 /* BXT PHY Ref registers */
2328754 #define _PORT_REF_DW3_A 0x16218C
2329755 #define _PORT_REF_DW3_BC 0x6C18C
@@ -2549,64 +975,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 219 unmodified lines
2549975 #define XEHP_VEBOX3_RING_BASE 0x1e8000
2550976 #define XEHP_VEBOX4_RING_BASE 0x1f8000
2551977 #define BLT_RING_BASE 0x22000
2552−#define RING_TAIL(base) _MMIO((base) + 0x30)
2553−#define RING_HEAD(base) _MMIO((base) + 0x34)
2554−#define RING_START(base) _MMIO((base) + 0x38)
2555−#define RING_CTL(base) _MMIO((base) + 0x3c)
2556−#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
2557−#define RING_SYNC_0(base) _MMIO((base) + 0x40)
2558−#define RING_SYNC_1(base) _MMIO((base) + 0x44)
2559−#define RING_SYNC_2(base) _MMIO((base) + 0x48)
2560−#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2561−#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2562−#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
2563−#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
2564−#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
2565−#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
2566−#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2567−#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2568−#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
2569−#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
2570−#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
2571−#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
2572−#define GEN6_NOSYNC INVALID_MMIO_REG
2573−#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
2574−#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
2575−#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
2576−#define RING_ID(base) _MMIO((base) + 0x8c)
2577−#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
2578−
2579−#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)
2580−/*
2581− * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
2582− * The lsb of each can be considered a separate enabling bit for encryption.
2583− * 6:0 == default MOCS value for reads => 6:1 == table index for reads.
2584− * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
2585− * 15:14 == Reserved => 31:30 are set to 0.
2586− */
2587−#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
2588−#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
2589−#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
2590− CMD_CCTL_READ_OVERRIDE_MASK)
2591−#define CMD_CCTL_MOCS_OVERRIDE(write, read) \
2592− (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
2593− REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
2594−
2595−#define BLIT_CCTL(base) _MMIO((base) + 0x204)
2596−#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
2597−#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
2598−#define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
2599− BLIT_CCTL_SRC_MOCS_MASK)
2600−#define BLIT_CCTL_MOCS(dst, src) \
2601− (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
2602− REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
2603−
2604−#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
2605−#define RESET_CTL_CAT_ERROR REG_BIT(2)
2606−#define RESET_CTL_READY_TO_RESET REG_BIT(1)
2607−#define RESET_CTL_REQUEST_RESET REG_BIT(0)
2608−
2609−#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
978+
979+
2610980
2611981 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
2612982 #define GTT_CACHE_EN_ALL 0xF0007FFF
@@ -2623,189 +993,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 10 unmodified lines
2623993 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
2624994 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
2625995
2626−#define GAMTARBMODE _MMIO(0x04a08)
2627−#define ARB_MODE_BWGTLB_DISABLE (1 << 9)
2628−#define ARB_MODE_SWIZZLE_BDW (1 << 1)
2629−#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
2630−
2631−#define _RING_FAULT_REG_RCS 0x4094
2632−#define _RING_FAULT_REG_VCS 0x4194
2633−#define _RING_FAULT_REG_BCS 0x4294
2634−#define _RING_FAULT_REG_VECS 0x4394
2635−#define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \
2636− _RING_FAULT_REG_RCS, \
2637− _RING_FAULT_REG_VCS, \
2638− _RING_FAULT_REG_VECS, \
2639− _RING_FAULT_REG_BCS))
2640−#define GEN8_RING_FAULT_REG _MMIO(0x4094)
2641−#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
2642−#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
2643−#define RING_FAULT_GTTSEL_MASK (1 << 11)
2644−#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2645−#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2646−#define RING_FAULT_VALID (1 << 0)
2647−#define DONE_REG _MMIO(0x40b0)
2648−#define GEN12_GAM_DONE _MMIO(0xcf68)
2649−#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2650−#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
2651−#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
2652−#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
2653−#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
2654−#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208)
2655−#define GEN12_VD0_AUX_NV _MMIO(0x4218)
2656−#define GEN12_VD1_AUX_NV _MMIO(0x4228)
2657−#define GEN12_VD2_AUX_NV _MMIO(0x4298)
2658−#define GEN12_VD3_AUX_NV _MMIO(0x42A8)
2659−#define GEN12_VE0_AUX_NV _MMIO(0x4238)
2660−#define GEN12_VE1_AUX_NV _MMIO(0x42B8)
2661−#define AUX_INV REG_BIT(0)
2662−#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2663−#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
2664−#define RING_ACTHD(base) _MMIO((base) + 0x74)
2665−#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
2666−#define RING_NOPID(base) _MMIO((base) + 0x94)
2667−#define RING_IMR(base) _MMIO((base) + 0xa8)
2668−#define RING_HWSTAM(base) _MMIO((base) + 0x98)
2669−#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
2670−#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
2671−#define TAIL_ADDR 0x001FFFF8
2672−#define HEAD_WRAP_COUNT 0xFFE00000
2673−#define HEAD_WRAP_ONE 0x00200000
2674−#define HEAD_ADDR 0x001FFFFC
2675−#define RING_NR_PAGES 0x001FF000
2676−#define RING_REPORT_MASK 0x00000006
2677−#define RING_REPORT_64K 0x00000002
2678−#define RING_REPORT_128K 0x00000004
2679−#define RING_NO_REPORT 0x00000000
2680−#define RING_VALID_MASK 0x00000001
2681−#define RING_VALID 0x00000001
2682−#define RING_INVALID 0x00000000
2683−#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
2684−#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
2685−#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
2686−
2687−#define GUCPMTIMESTAMP _MMIO(0xC3E8)
2688−
2689−/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
2690−#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
2691−#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
2692−
2693−#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2694−#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
2695−#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
2696−#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
2697−#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
2698−#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
2699−#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
2700−#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
2701−#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
2702−#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
2703−#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
2704−#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
2705−#define RING_FORCE_TO_NONPRIV_MASK_VALID \
2706− (RING_FORCE_TO_NONPRIV_RANGE_MASK \
2707− | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
2708−#define RING_MAX_NONPRIV_SLOTS 12
2709−
2710−#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
2711−
2712−#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2713−#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18)
2714−
2715−#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2716−#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2717−#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
2718−
2719−#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2720−#define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
2721−#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)
2722−#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24)
2723−
2724−#define GEN8_RTCR _MMIO(0x4260)
2725−#define GEN8_M1TCR _MMIO(0x4264)
2726−#define GEN8_M2TCR _MMIO(0x4268)
2727−#define GEN8_BTCR _MMIO(0x426c)
2728−#define GEN8_VTCR _MMIO(0x4270)
2729−
2730−#if 0
2731−#define PRB0_TAIL _MMIO(0x2030)
2732−#define PRB0_HEAD _MMIO(0x2034)
2733−#define PRB0_START _MMIO(0x2038)
2734−#define PRB0_CTL _MMIO(0x203c)
2735−#define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
2736−#define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
2737−#define PRB1_START _MMIO(0x2048) /* 915+ only */
2738−#define PRB1_CTL _MMIO(0x204c) /* 915+ only */
2739−#endif
2740−#define IPEIR_I965 _MMIO(0x2064)
2741−#define IPEHR_I965 _MMIO(0x2068)
2742−#define GEN7_SC_INSTDONE _MMIO(0x7100)
2743−#define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
2744−#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
2745−#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2746−#define GEN7_ROW_INSTDONE _MMIO(0xe164)
2747−#define XEHPG_INSTDONE_GEOM_SVG _MMIO(0x666c)
2748−#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
2749−#define SF_MCR_SELECTOR _MMIO(0xfd8)
2750−#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
2751−#define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
2752−#define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
2753−#define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2754−#define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
2755−#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
2756−#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
2757−#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
2758−#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
2759−#define RING_IPEIR(base) _MMIO((base) + 0x64)
2760−#define RING_IPEHR(base) _MMIO((base) + 0x68)
2761−#define RING_EIR(base) _MMIO((base) + 0xb0)
2762−#define RING_EMR(base) _MMIO((base) + 0xb4)
2763−#define RING_ESR(base) _MMIO((base) + 0xb8)
2764−/*
2765− * On GEN4, only the render ring INSTDONE exists and has a different
2766− * layout than the GEN7+ version.
2767− * The GEN2 counterpart of this register is GEN2_INSTDONE.
2768− */
2769−#define RING_INSTDONE(base) _MMIO((base) + 0x6c)
2770−#define RING_INSTPS(base) _MMIO((base) + 0x70)
2771−#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
2772−#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
2773−#define RING_INSTPM(base) _MMIO((base) + 0xc0)
2774−#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
2775−#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
2776−#define INSTPS _MMIO(0x2070) /* 965+ only */
2777−#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2778−#define ACTHD_I965 _MMIO(0x2074)
2779−#define HWS_PGA _MMIO(0x2080)
2780−#define HWS_ADDRESS_MASK 0xfffff000
2781−#define HWS_START_ADDRESS_SHIFT 4
2782−#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
2783−#define PWRCTX_EN (1 << 0)
2784−#define IPEIR(base) _MMIO((base) + 0x88)
2785−#define IPEHR(base) _MMIO((base) + 0x8c)
2786−#define GEN2_INSTDONE _MMIO(0x2090)
2787−#define NOPID _MMIO(0x2094)
2788−#define HWSTAM _MMIO(0x2098)
2789−#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
2790−#define RING_BBSTATE(base) _MMIO((base) + 0x110)
2791−#define RING_BB_PPGTT (1 << 5)
2792−#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
2793−#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
2794−#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
2795−#define RING_BBADDR(base) _MMIO((base) + 0x140)
2796−#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
2797−#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
2798−#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
2799−#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
2800−#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
2801−
2802−#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
2803−#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
2804−
2805−#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
2806−#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
2807−
2808−#define ERROR_GEN6 _MMIO(0x40a0)
2809996 #define GEN7_ERR_INT _MMIO(0x44040)
2810997 #define ERR_INT_POISON (1 << 31)
2811998 #define ERR_INT_MMIO_UNCLAIMED (1 << 13)
@@ -2818,20 +1005,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 6 unmodified lines
28181005 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
28191006 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
28201007
2821−#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2822−#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
2823−#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
2824−#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
2825−#define FAULT_VA_HIGH_BITS (0xf << 0)
2826−#define FAULT_GTT_SEL (1 << 4)
2827−
2828−#define GEN12_GFX_TLB_INV_CR _MMIO(0xced8)
2829−#define GEN12_VD_TLB_INV_CR _MMIO(0xcedc)
2830−#define GEN12_VE_TLB_INV_CR _MMIO(0xcee0)
2831−#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)
2832−
2833−#define GEN12_AUX_ERR_DBG _MMIO(0x43f4)
2834−
28351008 #define FPGA_DBG _MMIO(0x42300)
28361009 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
28371010
@@ -2859,95 +1032,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 21 unmodified lines
28591032 #define DERRMR_PIPEC_VBLANK (1 << 21)
28601033 #define DERRMR_PIPEC_HBLANK (1 << 22)
28611034
2862−
2863−/* GM45+ chicken bits -- debug workaround bits that may be required
2864− * for various sorts of correct behavior. The top 16 bits of each are
2865− * the enables for writing to the corresponding low bit.
2866− */
2867−#define _3D_CHICKEN _MMIO(0x2084)
2868−#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
2869−#define _3D_CHICKEN2 _MMIO(0x208c)
2870−
2871−#define FF_SLICE_CHICKEN _MMIO(0x2088)
2872−#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
2873−
2874−/* Disables pipelining of read flushes past the SF-WIZ interface.
2875− * Required on all Ironlake steppings according to the B-Spec, but the
2876− * particular danger of not doing so is not specified.
2877− */
2878−# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
2879−#define _3D_CHICKEN3 _MMIO(0x2090)
2880−#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
2881−#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
2882−#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
2883−#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
2884−#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */
2885−#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
2886−
2887−#define MI_MODE _MMIO(0x209c)
2888−# define VS_TIMER_DISPATCH (1 << 6)
2889−# define MI_FLUSH_ENABLE (1 << 12)
2890−# define TGL_NESTED_BB_EN (1 << 12)
2891−# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
2892−# define MODE_IDLE (1 << 9)
2893−# define STOP_RING (1 << 8)
2894−
2895−#define GEN6_GT_MODE _MMIO(0x20d0)
2896−#define GEN7_GT_MODE _MMIO(0x7008)
2897−#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
2898−#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
2899−#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
2900−#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
2901−#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
2902−#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
2903−#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
2904−#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
2905−
2906−/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2907−#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2908−#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2909−#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
2910−
2911−#define SCCGCTL94DC _MMIO(0x94dc)
2912−#define CG3DDISURB REG_BIT(14)
2913−
2914−#define MLTICTXCTL _MMIO(0xb170)
2915−#define TDONRENDER REG_BIT(2)
2916−
2917−#define L3SQCREG1_CCS0 _MMIO(0xb200)
2918−#define FLUSHALLNONCOH REG_BIT(5)
2919−
2920−/* WaClearTdlStateAckDirtyBits */
2921−#define GEN8_STATE_ACK _MMIO(0x20F0)
2922−#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
2923−#define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
2924−#define GEN9_STATE_ACK_TDL0 (1 << 12)
2925−#define GEN9_STATE_ACK_TDL1 (1 << 13)
2926−#define GEN9_STATE_ACK_TDL2 (1 << 14)
2927−#define GEN9_STATE_ACK_TDL3 (1 << 15)
2928−#define GEN9_SUBSLICE_TDL_ACK_BITS \
2929− (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2930− GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2931−
2932−#define GFX_MODE _MMIO(0x2520)
2933−#define GFX_MODE_GEN7 _MMIO(0x229c)
2934−#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
2935−#define GFX_RUN_LIST_ENABLE (1 << 15)
2936−#define GFX_INTERRUPT_STEERING (1 << 14)
2937−#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
2938−#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
2939−#define GFX_REPLAY_MODE (1 << 11)
2940−#define GFX_PSMI_GRANULARITY (1 << 10)
2941−#define GFX_PPGTT_ENABLE (1 << 9)
2942−#define GEN8_GFX_PPGTT_48B (1 << 7)
2943−
2944−#define GFX_FORWARD_VBLANK_MASK (3 << 5)
2945−#define GFX_FORWARD_VBLANK_NEVER (0 << 5)
2946−#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
2947−#define GFX_FORWARD_VBLANK_COND (2 << 5)
2948−
2949−#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
2950−
29511035 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
29521036 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
29531037 #define SCPD0 _MMIO(0x209c) /* 915+ only */
@@ -2987,7 +1071,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 33 unmodified lines
29871071 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
29881072 #define INSTPM_TLB_INVALIDATE (1 << 9)
29891073 #define INSTPM_SYNC_FLUSH (1 << 5)
2990−#define ACTHD(base) _MMIO((base) + 0xc8)
29911074 #define MEM_MODE _MMIO(0x20cc)
29921075 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
29931076 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
@@ -3114,132 +1197,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 120 unmodified lines
31141197 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
31151198 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
31161199
3117−#define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
3118−#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
3119−#define CM0_IZ_OPT_DISABLE (1 << 6)
3120−#define CM0_ZR_OPT_DISABLE (1 << 5)
3121−#define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)
3122−#define CM0_DEPTH_EVICT_DISABLE (1 << 4)
3123−#define CM0_COLOR_EVICT_DISABLE (1 << 3)
3124−#define CM0_DEPTH_WRITE_DISABLE (1 << 1)
3125−#define CM0_RC_OP_FLUSH_DISABLE (1 << 0)
3126−#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
3127−#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
3128−#define GFX_FLSH_CNTL_EN (1 << 0)
3129−#define ECOSKPD _MMIO(0x21d0)
3130−#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
3131−#define ECO_GATING_CX_ONLY (1 << 3)
3132−#define ECO_FLIP_DONE (1 << 0)
3133−
3134−#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
3135−#define RC_OP_FLUSH_ENABLE (1 << 0)
3136−#define HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
3137−#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
3138−#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6)
3139−#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
3140−#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
3141−
3142−#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
3143−#define GEN6_BLITTER_LOCK_SHIFT 16
3144−#define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
3145−
3146−#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
3147−#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
3148−#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
3149−#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
3150−#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
3151−
3152−#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
3153−#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
3154−
3155−#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
3156−#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
3157−#define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
3158−
3159−/* Fuse readout registers for GT */
3160−#define HSW_PAVP_FUSE1 _MMIO(0x911C)
3161−#define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24)
3162−#define HSW_F1_EU_DIS_MASK REG_GENMASK(17, 16)
3163−#define HSW_F1_EU_DIS_10EUS 0
3164−#define HSW_F1_EU_DIS_8EUS 1
3165−#define HSW_F1_EU_DIS_6EUS 2
3166−
3167−#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
3168−#define CHV_FGT_DISABLE_SS0 (1 << 10)
3169−#define CHV_FGT_DISABLE_SS1 (1 << 11)
3170−#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
3171−#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
3172−#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
3173−#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
3174−#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
3175−#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
3176−#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
3177−#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
3178−
3179−#define GEN8_FUSE2 _MMIO(0x9120)
3180−#define GEN8_F2_SS_DIS_SHIFT 21
3181−#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
3182−#define GEN8_F2_S_ENA_SHIFT 25
3183−#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
3184−
3185−#define GEN9_F2_SS_DIS_SHIFT 20
3186−#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
3187−
3188−#define GEN10_F2_S_ENA_SHIFT 22
3189−#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
3190−#define GEN10_F2_SS_DIS_SHIFT 18
3191−#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
3192−
3193−#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
3194−#define GEN10_L3BANK_PAIR_COUNT 4
3195−#define GEN10_L3BANK_MASK 0x0F
3196−/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
3197−#define GEN12_MAX_MSLICES 4
3198−#define GEN12_MEML3_EN_MASK 0x0F
3199−
3200−#define GEN8_EU_DISABLE0 _MMIO(0x9134)
3201−#define GEN8_EU_DIS0_S0_MASK 0xffffff
3202−#define GEN8_EU_DIS0_S1_SHIFT 24
3203−#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
3204−
3205−#define GEN8_EU_DISABLE1 _MMIO(0x9138)
3206−#define GEN8_EU_DIS1_S1_MASK 0xffff
3207−#define GEN8_EU_DIS1_S2_SHIFT 16
3208−#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
3209−
3210−#define GEN8_EU_DISABLE2 _MMIO(0x913c)
3211−#define GEN8_EU_DIS2_S2_MASK 0xff
3212−
3213−#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
3214−
3215−#define GEN10_EU_DISABLE3 _MMIO(0x9140)
3216−#define GEN10_EU_DIS_SS_MASK 0xff
3217−
3218−#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
3219−#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
3220−#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
3221−#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
3222−
3223−#define GEN11_EU_DISABLE _MMIO(0x9134)
3224−#define GEN11_EU_DIS_MASK 0xFF
3225−
3226−#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
3227−#define GEN11_GT_S_ENA_MASK 0xFF
3228−
3229−#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
3230−
3231−#define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913C)
3232−#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
3233−
3234−#define XEHP_EU_ENABLE _MMIO(0x9134)
3235−#define XEHP_EU_ENA_MASK 0xFF
3236−
3237−#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
3238−#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
3239−#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
3240−#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
3241−#define GEN6_BSD_GO_INDICATOR (1 << 4)
3242−
32431200 /* On modern GEN architectures interrupt control consists of two sets
32441201 * of registers. The first set pertains to the ring generating the
32451202 * interrupt. The second control is for the functional block generating the
@@ -3397,10 +1354,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 151 unmodified lines
33971354 #define FBC_LL_SIZE (1536)
33981355
33991356 /* Framebuffer compression for GM45+ */
3400−#define DPFC_CB_BASE _MMIO(0x3200)
3401−#define ILK_DPFC_CB_BASE _MMIO(0x43200)
3402−#define DPFC_CONTROL _MMIO(0x3208)
3403−#define ILK_DPFC_CONTROL _MMIO(0x43208)
1357+#define DPFC_CB_BASE _MMIO(0x3200)
1358+#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
1359+#define DPFC_CONTROL _MMIO(0x3208)
1360+#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
34041361 #define DPFC_CTL_EN REG_BIT(31)
34051362 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
34061363 #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
@@ -3418,28 +1375,28 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 11 unmodified lines
34181375 #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
34191376 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
34201377 #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
3421−#define DPFC_RECOMP_CTL _MMIO(0x320c)
3422−#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
1378+#define DPFC_RECOMP_CTL _MMIO(0x320c)
1379+#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
34231380 #define DPFC_RECOMP_STALL_EN REG_BIT(27)
34241381 #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
34251382 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
3426−#define DPFC_STATUS _MMIO(0x3210)
3427−#define ILK_DPFC_STATUS _MMIO(0x43210)
1383+#define DPFC_STATUS _MMIO(0x3210)
1384+#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
34281385 #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
34291386 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
3430−#define DPFC_STATUS2 _MMIO(0x3214)
3431−#define ILK_DPFC_STATUS2 _MMIO(0x43214)
1387+#define DPFC_STATUS2 _MMIO(0x3214)
1388+#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
34321389 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
3433−#define DPFC_FENCE_YOFF _MMIO(0x3218)
3434−#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
3435−#define DPFC_CHICKEN _MMIO(0x3224)
3436−#define ILK_DPFC_CHICKEN _MMIO(0x43224)
1390+#define DPFC_FENCE_YOFF _MMIO(0x3218)
1391+#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
1392+#define DPFC_CHICKEN _MMIO(0x3224)
1393+#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
34371394 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
34381395 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
34391396 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
34401397 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
34411398
3442−#define GLK_FBC_STRIDE _MMIO(0x43228)
1399+#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
34431400 #define FBC_STRIDE_OVERRIDE REG_BIT(15)
34441401 #define FBC_STRIDE_MASK REG_GENMASK(14, 0)
34451402 #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
@@ -3482,9 +1439,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 36 unmodified lines
34821439 #define IPS_CTL _MMIO(0x43408)
34831440 #define IPS_ENABLE (1 << 31)
34841441
3485−#define MSG_FBC_REND_STATE _MMIO(0x50380)
1442+#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
34861443 #define FBC_REND_NUKE REG_BIT(2)
3487−#define FBC_REND_CACHE_CLEAN REG_BIT(1)
1444+#define FBC_REND_CACHE_CLEAN REG_BIT(1)
34881445
34891446 /*
34901447 * GPIO regs
@@ -3973,227 +1930,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 482 unmodified lines
39731930 #define TSFS_SLOPE_SHIFT 8
39741931 #define TSFS_INTR_MASK 0x000000ff
39751932
3976−#define CRSTANDVID _MMIO(0x11100)
3977−#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3978−#define PXVFREQ_PX_MASK 0x7f000000
3979−#define PXVFREQ_PX_SHIFT 24
3980−#define VIDFREQ_BASE _MMIO(0x11110)
3981−#define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3982−#define VIDFREQ2 _MMIO(0x11114)
3983−#define VIDFREQ3 _MMIO(0x11118)
3984−#define VIDFREQ4 _MMIO(0x1111c)
3985−#define VIDFREQ_P0_MASK 0x1f000000
3986−#define VIDFREQ_P0_SHIFT 24
3987−#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
3988−#define VIDFREQ_P0_CSCLK_SHIFT 20
3989−#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
3990−#define VIDFREQ_P0_CRCLK_SHIFT 16
3991−#define VIDFREQ_P1_MASK 0x00001f00
3992−#define VIDFREQ_P1_SHIFT 8
3993−#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
3994−#define VIDFREQ_P1_CSCLK_SHIFT 4
3995−#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
3996−#define INTTOEXT_BASE_ILK _MMIO(0x11300)
3997−#define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3998−#define INTTOEXT_MAP3_SHIFT 24
3999−#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
4000−#define INTTOEXT_MAP2_SHIFT 16
4001−#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
4002−#define INTTOEXT_MAP1_SHIFT 8
4003−#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
4004−#define INTTOEXT_MAP0_SHIFT 0
4005−#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
4006−#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
4007−#define MEMCTL_CMD_MASK 0xe000
4008−#define MEMCTL_CMD_SHIFT 13
4009−#define MEMCTL_CMD_RCLK_OFF 0
4010−#define MEMCTL_CMD_RCLK_ON 1
4011−#define MEMCTL_CMD_CHFREQ 2
4012−#define MEMCTL_CMD_CHVID 3
4013−#define MEMCTL_CMD_VMMOFF 4
4014−#define MEMCTL_CMD_VMMON 5
4015−#define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears
4016− when command complete */
4017−#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
4018−#define MEMCTL_FREQ_SHIFT 8
4019−#define MEMCTL_SFCAVM (1 << 7)
4020−#define MEMCTL_TGT_VID_MASK 0x007f
4021−#define MEMIHYST _MMIO(0x1117c)
4022−#define MEMINTREN _MMIO(0x11180) /* 16 bits */
4023−#define MEMINT_RSEXIT_EN (1 << 8)
4024−#define MEMINT_CX_SUPR_EN (1 << 7)
4025−#define MEMINT_CONT_BUSY_EN (1 << 6)
4026−#define MEMINT_AVG_BUSY_EN (1 << 5)
4027−#define MEMINT_EVAL_CHG_EN (1 << 4)
4028−#define MEMINT_MON_IDLE_EN (1 << 3)
4029−#define MEMINT_UP_EVAL_EN (1 << 2)
4030−#define MEMINT_DOWN_EVAL_EN (1 << 1)
4031−#define MEMINT_SW_CMD_EN (1 << 0)
4032−#define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
4033−#define MEM_RSEXIT_MASK 0xc000
4034−#define MEM_RSEXIT_SHIFT 14
4035−#define MEM_CONT_BUSY_MASK 0x3000
4036−#define MEM_CONT_BUSY_SHIFT 12
4037−#define MEM_AVG_BUSY_MASK 0x0c00
4038−#define MEM_AVG_BUSY_SHIFT 10
4039−#define MEM_EVAL_CHG_MASK 0x0300
4040−#define MEM_EVAL_BUSY_SHIFT 8
4041−#define MEM_MON_IDLE_MASK 0x00c0
4042−#define MEM_MON_IDLE_SHIFT 6
4043−#define MEM_UP_EVAL_MASK 0x0030
4044−#define MEM_UP_EVAL_SHIFT 4
4045−#define MEM_DOWN_EVAL_MASK 0x000c
4046−#define MEM_DOWN_EVAL_SHIFT 2
4047−#define MEM_SW_CMD_MASK 0x0003
4048−#define MEM_INT_STEER_GFX 0
4049−#define MEM_INT_STEER_CMR 1
4050−#define MEM_INT_STEER_SMI 2
4051−#define MEM_INT_STEER_SCI 3
4052−#define MEMINTRSTS _MMIO(0x11184)
4053−#define MEMINT_RSEXIT (1 << 7)
4054−#define MEMINT_CONT_BUSY (1 << 6)
4055−#define MEMINT_AVG_BUSY (1 << 5)
4056−#define MEMINT_EVAL_CHG (1 << 4)
4057−#define MEMINT_MON_IDLE (1 << 3)
4058−#define MEMINT_UP_EVAL (1 << 2)
4059−#define MEMINT_DOWN_EVAL (1 << 1)
4060−#define MEMINT_SW_CMD (1 << 0)
4061−#define MEMMODECTL _MMIO(0x11190)
4062−#define MEMMODE_BOOST_EN (1 << 31)
4063−#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
4064−#define MEMMODE_BOOST_FREQ_SHIFT 24
4065−#define MEMMODE_IDLE_MODE_MASK 0x00030000
4066−#define MEMMODE_IDLE_MODE_SHIFT 16
4067−#define MEMMODE_IDLE_MODE_EVAL 0
4068−#define MEMMODE_IDLE_MODE_CONT 1
4069−#define MEMMODE_HWIDLE_EN (1 << 15)
4070−#define MEMMODE_SWMODE_EN (1 << 14)
4071−#define MEMMODE_RCLK_GATE (1 << 13)
4072−#define MEMMODE_HW_UPDATE (1 << 12)
4073−#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
4074−#define MEMMODE_FSTART_SHIFT 8
4075−#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
4076−#define MEMMODE_FMAX_SHIFT 4
4077−#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
4078−#define RCBMAXAVG _MMIO(0x1119c)
4079−#define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
4080−#define SWMEMCMD_RENDER_OFF (0 << 13)
4081−#define SWMEMCMD_RENDER_ON (1 << 13)
4082−#define SWMEMCMD_SWFREQ (2 << 13)
4083−#define SWMEMCMD_TARVID (3 << 13)
4084−#define SWMEMCMD_VRM_OFF (4 << 13)
4085−#define SWMEMCMD_VRM_ON (5 << 13)
4086−#define CMDSTS (1 << 12)
4087−#define SFCAVM (1 << 11)
4088−#define SWFREQ_MASK 0x0380 /* P0-7 */
4089−#define SWFREQ_SHIFT 7
4090−#define TARVID_MASK 0x001f
4091−#define MEMSTAT_CTG _MMIO(0x111a0)
4092−#define RCBMINAVG _MMIO(0x111a0)
4093−#define RCUPEI _MMIO(0x111b0)
4094−#define RCDNEI _MMIO(0x111b4)
4095−#define RSTDBYCTL _MMIO(0x111b8)
4096−#define RS1EN (1 << 31)
4097−#define RS2EN (1 << 30)
4098−#define RS3EN (1 << 29)
4099−#define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */
4100−#define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */
4101−#define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */
4102−#define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */
4103−#define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */
4104−#define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */
4105−#define RSX_STATUS_MASK (7 << 20)
4106−#define RSX_STATUS_ON (0 << 20)
4107−#define RSX_STATUS_RC1 (1 << 20)
4108−#define RSX_STATUS_RC1E (2 << 20)
4109−#define RSX_STATUS_RS1 (3 << 20)
4110−#define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */
4111−#define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */
4112−#define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */
4113−#define RSX_STATUS_RSVD2 (7 << 20)
4114−#define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */
4115−#define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */
4116−#define JRSC (1 << 17) /* rsx coupled to cpu c-state */
4117−#define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */
4118−#define RS1CONTSAV_MASK (3 << 14)
4119−#define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */
4120−#define RS1CONTSAV_RSVD (1 << 14)
4121−#define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */
4122−#define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */
4123−#define NORMSLEXLAT_MASK (3 << 12)
4124−#define SLOW_RS123 (0 << 12)
4125−#define SLOW_RS23 (1 << 12)
4126−#define SLOW_RS3 (2 << 12)
4127−#define NORMAL_RS123 (3 << 12)
4128−#define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */
4129−#define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
4130−#define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
4131−#define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */
4132−#define RS_CSTATE_MASK (3 << 4)
4133−#define RS_CSTATE_C367_RS1 (0 << 4)
4134−#define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
4135−#define RS_CSTATE_RSVD (2 << 4)
4136−#define RS_CSTATE_C367_RS2 (3 << 4)
4137−#define REDSAVES (1 << 3) /* no context save if was idle during rs0 */
4138−#define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */
4139−#define VIDCTL _MMIO(0x111c0)
4140−#define VIDSTS _MMIO(0x111c8)
4141−#define VIDSTART _MMIO(0x111cc) /* 8 bits */
4142−#define MEMSTAT_ILK _MMIO(0x111f8)
4143−#define MEMSTAT_VID_MASK 0x7f00
4144−#define MEMSTAT_VID_SHIFT 8
4145−#define MEMSTAT_PSTATE_MASK 0x00f8
4146−#define MEMSTAT_PSTATE_SHIFT 3
4147−#define MEMSTAT_MON_ACTV (1 << 2)
4148−#define MEMSTAT_SRC_CTL_MASK 0x0003
4149−#define MEMSTAT_SRC_CTL_CORE 0
4150−#define MEMSTAT_SRC_CTL_TRB 1
4151−#define MEMSTAT_SRC_CTL_THM 2
4152−#define MEMSTAT_SRC_CTL_STDBY 3
4153−#define RCPREVBSYTUPAVG _MMIO(0x113b8)
4154−#define RCPREVBSYTDNAVG _MMIO(0x113bc)
4155−#define PMMISC _MMIO(0x11214)
4156−#define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */
4157−#define SDEW _MMIO(0x1124c)
4158−#define CSIEW0 _MMIO(0x11250)
4159−#define CSIEW1 _MMIO(0x11254)
4160−#define CSIEW2 _MMIO(0x11258)
4161−#define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
4162−#define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
4163−#define MCHAFE _MMIO(0x112c0)
4164−#define CSIEC _MMIO(0x112e0)
4165−#define DMIEC _MMIO(0x112e4)
4166−#define DDREC _MMIO(0x112e8)
4167−#define PEG0EC _MMIO(0x112ec)
4168−#define PEG1EC _MMIO(0x112f0)
4169−#define GFXEC _MMIO(0x112f4)
4170−#define RPPREVBSYTUPAVG _MMIO(0x113b8)
4171−#define RPPREVBSYTDNAVG _MMIO(0x113bc)
4172−#define ECR _MMIO(0x11600)
4173−#define ECR_GPFE (1 << 31)
4174−#define ECR_IMONE (1 << 30)
4175−#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
4176−#define OGW0 _MMIO(0x11608)
4177−#define OGW1 _MMIO(0x1160c)
4178−#define EG0 _MMIO(0x11610)
4179−#define EG1 _MMIO(0x11614)
4180−#define EG2 _MMIO(0x11618)
4181−#define EG3 _MMIO(0x1161c)
4182−#define EG4 _MMIO(0x11620)
4183−#define EG5 _MMIO(0x11624)
4184−#define EG6 _MMIO(0x11628)
4185−#define EG7 _MMIO(0x1162c)
4186−#define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
4187−#define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
4188−#define LCFUSE02 _MMIO(0x116c0)
4189−#define LCFUSE_HIV_MASK 0x000000ff
41901933 #define CSIPLL0 _MMIO(0x12c10)
41911934 #define DDRMPLL1 _MMIO(0X12c20)
41921935 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
41931936
4194−#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
4195−#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
4196−
41971937 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
41981938 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
41991939 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
@@ -4205,81 +1945,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) · 5 unmodified lines
42051945 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
42061946 #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
42071947
4208−/*
4209− * Logical Context regs
4210− */
4211−#define CCID(base) _MMIO((base) + 0x180)
4212−#define CCID_EN BIT(0)
4213−#define CCID_EXTENDED_STATE_RESTORE BIT(2)
4214−#define CCID_EXTENDED_STATE_SAVE BIT(3)
4215−/*
4216− * Notes on SNB/IVB/VLV context size:
4217− * - Power context is saved elsewhere (LLC or stolen)
4218− * - Ring/execlist context is saved on SNB, not on IVB
4219− * - Extended context size already includes render context size
4220− * - We always need to follow the extended context size.
4221− * SNB BSpec has comments indicating that we should use the
4222− * render context size instead if execlists are disabled, but
4223− * based on empirical testing that's just nonsense.
4224− * - Pipelined/VF state is saved on SNB/IVB respectively
4225− * - GT1 size just indicates how much of render context
4226− * doesn't need saving on GT1
4227− */
4228−#define CXT_SIZE _MMIO(0x21a0)
4229−#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
4230−#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
4231−#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
4232−#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
4233−#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
4234−#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
4235− GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
4236− GEN6_CXT_PIPELINE_SIZE(cxt_reg))
4237−#define GEN7_CXT_SIZE _MMIO(0x21a8)
4238−#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
4239−#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
4240−#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
4241−#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
4242−#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
4243−#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
4244−#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
4245− GEN7_CXT_VFSTATE_SIZE(ctx_reg))
4246−
4247−enum {
4248− INTEL_ADVANCED_CONTEXT = 0,
4249− INTEL_LEGACY_32B_CONTEXT,
4250− INTEL_ADVANCED_AD_CONTEXT,
4251− INTEL_LEGACY_64B_CONTEXT
4252−};
4253−
4254−enum {
4255− FAULT_AND_HANG = 0,
4256− FAULT_AND_HALT, /* Debug only */
4257− FAULT_AND_STREAM,
4258− FAULT_AND_CONTINUE /* Unsupported */
4259−};
4260−
4261−#define CTX_GTT_ADDRESS_MASK GENMASK(31, 12)
4262−#define GEN8_CTX_VALID (1 << 0)
4263−#define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
4264−#define GEN8_CTX_FORCE_RESTORE (1 << 2)
4265−#define GEN8_CTX_L3LLC_COHERENT (1 << 5)
4266−#define GEN8_CTX_PRIVILEGE (1 << 8)
4267−#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
4268−
4269−#define GEN8_CTX_ID_SHIFT 32
4270−#define GEN8_CTX_ID_WIDTH 21
4271−#define GEN11_SW_CTX_ID_SHIFT 37
4272−#define GEN11_SW_CTX_ID_WIDTH 11
4273−#define GEN11_ENGINE_CLASS_SHIFT 61
4274−#define GEN11_ENGINE_CLASS_WIDTH 3
4275−#define GEN11_ENGINE_INSTANCE_SHIFT 48
4276−#define GEN11_ENGINE_INSTANCE_WIDTH 6
4277−
4278−#define XEHP_SW_CTX_ID_SHIFT 39
4279−#define XEHP_SW_CTX_ID_WIDTH 16
4280−#define XEHP_SW_COUNTER_SHIFT 58
4281−#define XEHP_SW_COUNTER_WIDTH 6
4282−
42831948 #define CHV_CLK_CTL1 _MMIO(0x101100)
42841949 #define VLV_CLK_CTL2 _MMIO(0x101104)
42851950 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
@@ -4330,75 +1995,6 @@ enum { · 44 unmodified lines
43301995 #define CLKGATE_DIS_PSL(pipe) \
43311996 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
43321997
4333−/*
4334− * GEN10 clock gating regs
4335− */
4336−
4337−#define UNSLCGCTL9440 _MMIO(0x9440)
4338−#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
4339−#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
4340−#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
4341−#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
4342−#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
4343−#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
4344−#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
4345−#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
4346−#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
4347−#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
4348−#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
4349−#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
4350−
4351−#define UNSLCGCTL9444 _MMIO(0x9444)
4352−#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
4353−#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
4354−#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
4355−#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
4356−#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
4357−#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
4358−#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
4359−#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
4360−#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
4361−#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
4362−#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
4363−#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
4364−#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
4365−#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
4366−#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
4367−#define LTCDD_CLKGATE_DIS REG_BIT(10)
4368−
4369−#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
4370−#define SARBUNIT_CLKGATE_DIS (1 << 5)
4371−#define RCCUNIT_CLKGATE_DIS (1 << 7)
4372−#define MSCUNIT_CLKGATE_DIS (1 << 10)
4373−#define NODEDSS_CLKGATE_DIS REG_BIT(12)
4374−#define L3_CLKGATE_DIS REG_BIT(16)
4375−#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
4376−
4377−#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
4378−#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
4379−#define GWUNIT_CLKGATE_DIS REG_BIT(16)
4380−
4381−#define SUBSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x9528)
4382−#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
4383−
4384−#define SSMCGCTL9530 _MMIO(0x9530)
4385−#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
4386−
4387−#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
4388−#define VFUNIT_CLKGATE_DIS REG_BIT(20)
4389−#define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */
4390−#define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
4391−#define GAMEDIA_CLKGATE_DIS REG_BIT(11)
4392−#define HSUNIT_CLKGATE_DIS REG_BIT(8)
4393−#define VSUNIT_CLKGATE_DIS REG_BIT(3)
4394−
4395−#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
4396−#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
4397−#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
4398−
4399−#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
4400−#define CGPSF_CLKGATE_DIS (1 << 3)
4401−
44021998 /*
44031999 * Display engine regs
44042000 */
@@ -4493,6 +2089,10 @@ enum { · 88 unmodified lines
44932089 #define _VSYNC_A 0x60014
44942090 #define _EXITLINE_A 0x60018
44952091 #define _PIPEASRC 0x6001c
2092+#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
2093+#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
2094+#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
2095+#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
44962096 #define _BCLRPAT_A 0x60020
44972097 #define _VSYNCSHIFT_A 0x60028
44982098 #define _PIPE_MULT_A 0x6002c
@@ -6143,16 +3743,14 @@ enum { · 1644 unmodified lines
61433743 #define _PIPEB_DATA_M_G4X 0x71050
61443744
61453745 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
6146−#define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */
6147−#define TU_SIZE_SHIFT 25
6148−#define TU_SIZE_MASK (0x3f << 25)
3746+#define TU_SIZE_MASK REG_GENMASK(30, 25)
3747+#define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
61493748
6150−#define DATA_LINK_M_N_MASK (0xffffff)
3749+#define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
61513750 #define DATA_LINK_N_MAX (0x800000)
61523751
61533752 #define _PIPEA_DATA_N_G4X 0x70054
61543753 #define _PIPEB_DATA_N_G4X 0x71054
6155−#define PIPE_GMCH_DATA_N_MASK (0xffffff)
61563754
61573755 /*
61583756 * Computing Link M and N values for the Display Port link
@@ -6167,11 +3765,8 @@ enum { · 8 unmodified lines
61673765
61683766 #define _PIPEA_LINK_M_G4X 0x70060
61693767 #define _PIPEB_LINK_M_G4X 0x71060
6170−#define PIPEA_DP_LINK_M_MASK (0xffffff)
6171−
61723768 #define _PIPEA_LINK_N_G4X 0x70064
61733769 #define _PIPEB_LINK_N_G4X 0x71064
6174−#define PIPEA_DP_LINK_N_MASK (0xffffff)
61753770
61763771 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
61773772 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
@@ -6182,65 +3777,61 @@ enum { · 4 unmodified lines
61823777
61833778 /* Pipe A */
61843779 #define _PIPEADSL 0x70000
6185−#define DSL_LINEMASK_GEN2 0x00000fff
6186−#define DSL_LINEMASK_GEN3 0x00001fff
3780+#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
3781+#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
61873782 #define _PIPEACONF 0x70008
6188−#define PIPECONF_ENABLE (1 << 31)
6189−#define PIPECONF_DISABLE 0
6190−#define PIPECONF_DOUBLE_WIDE (1 << 30)
6191−#define I965_PIPECONF_ACTIVE (1 << 30)
6192−#define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
6193−#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
6194−#define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3 */
6195−#define PIPECONF_SINGLE_WIDE 0
6196−#define PIPECONF_PIPE_UNLOCKED 0
6197−#define PIPECONF_PIPE_LOCKED (1 << 25)
6198−#define PIPECONF_FORCE_BORDER (1 << 25)
6199−#define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */
6200−#define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */
6201−#define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */
6202−#define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */
6203−#define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */
6204−#define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */
6205−#define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */
6206−#define PIPECONF_GAMMA_MODE_SHIFT 24
6207−#define PIPECONF_INTERLACE_MASK (7 << 21)
6208−#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
6209−/* Note that pre-gen3 does not support interlaced display directly. Panel
6210− * fitting must be disabled on pre-ilk for interlaced. */
6211−#define PIPECONF_PROGRESSIVE (0 << 21)
6212−#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
6213−#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
6214−#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
6215−#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
6216−/* Ironlake and later have a complete new set of values for interlaced. PFIT
6217− * means panel fitter required, PF means progressive fetch, DBL means power
6218− * saving pixel doubling. */
6219−#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
6220−#define PIPECONF_INTERLACED_ILK (3 << 21)
6221−#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
6222−#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
6223−#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
6224−#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
6225−#define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
6226−#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
6227−#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
6228−#define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11) /* ilk-ivb */
6229−#define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11) /* ilk-ivb */
6230−#define PIPECONF_OUTPUT_COLORSPACE_YUV601 (1 << 11) /* ilk-ivb */
6231−#define PIPECONF_OUTPUT_COLORSPACE_YUV709 (2 << 11) /* ilk-ivb */
6232−#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /* hsw only */
6233−#define PIPECONF_BPC_MASK (0x7 << 5)
6234−#define PIPECONF_8BPC (0 << 5)
6235−#define PIPECONF_10BPC (1 << 5)
6236−#define PIPECONF_6BPC (2 << 5)
6237−#define PIPECONF_12BPC (3 << 5)
6238−#define PIPECONF_DITHER_EN (1 << 4)
6239−#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
6240−#define PIPECONF_DITHER_TYPE_SP (0 << 2)
6241−#define PIPECONF_DITHER_TYPE_ST1 (1 << 2)
6242−#define PIPECONF_DITHER_TYPE_ST2 (2 << 2)
6243−#define PIPECONF_DITHER_TYPE_TEMP (3 << 2)
3783+#define PIPECONF_ENABLE REG_BIT(31)
3784+#define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
3785+#define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */
3786+#define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
3787+#define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
3788+#define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
3789+#define PIPECONF_PIPE_LOCKED REG_BIT(25)
3790+#define PIPECONF_FORCE_BORDER REG_BIT(25)
3791+#define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
3792+#define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
3793+#define PIPECONF_GAMMA_MODE_8BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0)
3794+#define PIPECONF_GAMMA_MODE_10BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1)
3795+#define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
3796+#define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
3797+#define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
3798+#define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
3799+#define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0)
3800+#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */
3801+#define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */
3802+#define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6)
3803+#define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */
3804+/*
3805+ * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
3806+ * DBL=power saving pixel doubling, PF-ID* requires panel fitter
3807+ */
3808+#define PIPECONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
3809+#define PIPECONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
3810+#define PIPECONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0)
3811+#define PIPECONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1)
3812+#define PIPECONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3)
3813+#define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
3814+#define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
3815+#define PIPECONF_EDP_RR_MODE_SWITCH REG_BIT(20)
3816+#define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16)
3817+#define PIPECONF_EDP_RR_MODE_SWITCH_VLV REG_BIT(14)
3818+#define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13)
3819+#define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
3820+#define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
3821+#define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
3822+#define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
3823+#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
3824+#define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
3825+#define PIPECONF_BPC_8 REG_FIELD_PREP(PIPECONF_BPC_MASK, 0)
3826+#define PIPECONF_BPC_10 REG_FIELD_PREP(PIPECONF_BPC_MASK, 1)
3827+#define PIPECONF_BPC_6 REG_FIELD_PREP(PIPECONF_BPC_MASK, 2)
3828+#define PIPECONF_BPC_12 REG_FIELD_PREP(PIPECONF_BPC_MASK, 3)
3829+#define PIPECONF_DITHER_EN REG_BIT(4)
3830+#define PIPECONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
3831+#define PIPECONF_DITHER_TYPE_SP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0)
3832+#define PIPECONF_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1)
3833+#define PIPECONF_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2)
3834+#define PIPECONF_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3)
62443835 #define _PIPEASTAT 0x70024
62453836 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
62463837 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
@@ -6325,38 +3916,41 @@ enum { · 78 unmodified lines
63253916
63263917 #define _PIPE_MISC_A 0x70030
63273918 #define _PIPE_MISC_B 0x71030
6328−#define PIPEMISC_YUV420_ENABLE (1 << 27) /* glk+ */
6329−#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
6330−#define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */
6331−#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
6332−#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
3919+#define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
3920+#define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
3921+#define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
3922+#define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
3923+#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
63333924 /*
63343925 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
63353926 * valid values of: 6, 8, 10 BPC.
63363927 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
63373928 * 6, 8, 10, 12 BPC.
63383929 */
6339−#define PIPEMISC_BPC_MASK (7 << 5)
6340−#define PIPEMISC_8_BPC (0 << 5)
6341−#define PIPEMISC_10_BPC (1 << 5)
6342−#define PIPEMISC_6_BPC (2 << 5)
6343−#define PIPEMISC_12_BPC_ADLP (4 << 5) /* adlp+ */
6344−#define PIPEMISC_DITHER_ENABLE (1 << 4)
6345−#define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
6346−#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
3930+#define PIPEMISC_BPC_MASK REG_GENMASK(7, 5)
3931+#define PIPEMISC_BPC_8 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
3932+#define PIPEMISC_BPC_10 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
3933+#define PIPEMISC_BPC_6 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
3934+#define PIPEMISC_BPC_12_ADLP REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
3935+#define PIPEMISC_DITHER_ENABLE REG_BIT(4)
3936+#define PIPEMISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
3937+#define PIPEMISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)
3938+#define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
3939+#define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
3940+#define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
63473941 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
63483942
63493943 #define _PIPE_MISC2_A 0x7002C
63503944 #define _PIPE_MISC2_B 0x7102C
6351−#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN (0x50 << 24)
6352−#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS (0x14 << 24)
6353−#define PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK (0xff << 24)
3945+#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
3946+#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
3947+#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
63543948 #define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A)
63553949
63563950 /* Skylake+ pipe bottom (background) color */
63573951 #define _SKL_BOTTOM_COLOR_A 0x70034
6358−#define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
6359−#define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30)
3952+#define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31)
3953+#define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
63603954 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
63613955
63623956 #define _ICL_PIPE_A_STATUS 0x70058
@@ -6773,44 +4367,50 @@ enum { · 410 unmodified lines
67734367 /* Cursor A & B regs */
67744368 #define _CURACNTR 0x70080
67754369 /* Old style CUR*CNTR flags (desktop 8xx) */
6776−#define CURSOR_ENABLE 0x80000000
6777−#define CURSOR_GAMMA_ENABLE 0x40000000
6778−#define CURSOR_STRIDE_SHIFT 28
6779−#define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
6780−#define CURSOR_FORMAT_SHIFT 24
6781−#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
6782−#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
6783−#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
6784−#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
6785−#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
6786−#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
4370+#define CURSOR_ENABLE REG_BIT(31)
4371+#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
4372+#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
4373+#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
4374+#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
4375+#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
4376+#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
4377+#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
4378+#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
4379+#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
67874380 /* New style CUR*CNTR flags */
6788−#define MCURSOR_MODE 0x27
6789−#define MCURSOR_MODE_DISABLE 0x00
6790−#define MCURSOR_MODE_128_32B_AX 0x02
6791−#define MCURSOR_MODE_256_32B_AX 0x03
6792−#define MCURSOR_MODE_64_32B_AX 0x07
6793−#define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6794−#define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6795−#define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
67964381 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
67974382 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
6798−#define MCURSOR_PIPE_SELECT_MASK (0x3 << 28)
6799−#define MCURSOR_PIPE_SELECT_SHIFT 28
6800−#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
6801−#define MCURSOR_GAMMA_ENABLE (1 << 26)
6802−#define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6803−#define MCURSOR_ROTATE_180 (1 << 15)
6804−#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
4383+#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
4384+#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
4385+#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
4386+#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
4387+#define MCURSOR_ROTATE_180 REG_BIT(15)
4388+#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
4389+#define MCURSOR_MODE_MASK 0x27
4390+#define MCURSOR_MODE_DISABLE 0x00
4391+#define MCURSOR_MODE_128_32B_AX 0x02
4392+#define MCURSOR_MODE_256_32B_AX 0x03
4393+#define MCURSOR_MODE_64_32B_AX 0x07
4394+#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
4395+#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
4396+#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
68054397 #define _CURABASE 0x70084
68064398 #define _CURAPOS 0x70088
6807−#define CURSOR_POS_MASK 0x007FF
6808−#define CURSOR_POS_SIGN 0x8000
6809−#define CURSOR_X_SHIFT 0
6810−#define CURSOR_Y_SHIFT 16
6811−#define CURSIZE _MMIO(0x700a0) /* 845/865 */
4399+#define CURSOR_POS_Y_SIGN REG_BIT(31)
4400+#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
4401+#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
4402+#define CURSOR_POS_X_SIGN REG_BIT(15)
4403+#define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
4404+#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
4405+#define _CURASIZE 0x700a0 /* 845/865 */
4406+#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
4407+#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
4408+#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
4409+#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
68124410 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
6813−#define CUR_FBC_CTL_EN (1 << 31)
4411+#define CUR_FBC_EN REG_BIT(31)
4412+#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
4413+#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
68144414 #define _CURASURFLIVE 0x700ac /* g4x+ */
68154415 #define _CURBCNTR 0x700c0
68164416 #define _CURBBASE 0x700c4
@@ -6823,6 +4423,7 @@ enum { · 6 unmodified lines
68234423 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
68244424 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
68254425 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
4426+#define CURSIZE(pipe) _CURSOR2(pipe, _CURASIZE)
68264427 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
68274428 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
68284429
@@ -6836,49 +4437,54 @@ enum { · 7 unmodified lines
68364437 /* Display A control */
68374438 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */
68384439 #define _DSPACNTR 0x70180
6839−#define DISPLAY_PLANE_ENABLE (1 << 31)
6840−#define DISPLAY_PLANE_DISABLE 0
6841−#define DISPPLANE_GAMMA_ENABLE (1 << 30)
6842−#define DISPPLANE_GAMMA_DISABLE 0
6843−#define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
6844−#define DISPPLANE_YUV422 (0x0 << 26)
6845−#define DISPPLANE_8BPP (0x2 << 26)
6846−#define DISPPLANE_BGRA555 (0x3 << 26)
6847−#define DISPPLANE_BGRX555 (0x4 << 26)
6848−#define DISPPLANE_BGRX565 (0x5 << 26)
6849−#define DISPPLANE_BGRX888 (0x6 << 26)
6850−#define DISPPLANE_BGRA888 (0x7 << 26)
6851−#define DISPPLANE_RGBX101010 (0x8 << 26)
6852−#define DISPPLANE_RGBA101010 (0x9 << 26)
6853−#define DISPPLANE_BGRX101010 (0xa << 26)
6854−#define DISPPLANE_BGRA101010 (0xb << 26)
6855−#define DISPPLANE_RGBX161616 (0xc << 26)
6856−#define DISPPLANE_RGBX888 (0xe << 26)
6857−#define DISPPLANE_RGBA888 (0xf << 26)
6858−#define DISPPLANE_STEREO_ENABLE (1 << 25)
6859−#define DISPPLANE_STEREO_DISABLE 0
6860−#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6861−#define DISPPLANE_SEL_PIPE_SHIFT 24
6862−#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
6863−#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6864−#define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
6865−#define DISPPLANE_SRC_KEY_DISABLE 0
6866−#define DISPPLANE_LINE_DOUBLE (1 << 20)
6867−#define DISPPLANE_NO_LINE_DOUBLE 0
6868−#define DISPPLANE_STEREO_POLARITY_FIRST 0
6869−#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
6870−#define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */
6871−#define DISPPLANE_ROTATE_180 (1 << 15)
6872−#define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
6873−#define DISPPLANE_TILED (1 << 10)
6874−#define DISPPLANE_ASYNC_FLIP (1 << 9) /* g4x+ */
6875−#define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
4440+#define DISP_ENABLE REG_BIT(31)
4441+#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
4442+#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
4443+#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
4444+#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
4445+#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
4446+#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
4447+#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
4448+#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
4449+#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
4450+#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
4451+#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
4452+#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
4453+#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
4454+#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
4455+#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
4456+#define DISP_STEREO_ENABLE REG_BIT(25)
4457+#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
4458+#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
4459+#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
4460+#define DISP_SRC_KEY_ENABLE REG_BIT(22)
4461+#define DISP_LINE_DOUBLE REG_BIT(20)
4462+#define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
4463+#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
4464+#define DISP_ROTATE_180 REG_BIT(15)
4465+#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
4466+#define DISP_TILED REG_BIT(10)
4467+#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
4468+#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
68764469 #define _DSPAADDR 0x70184
68774470 #define _DSPASTRIDE 0x70188
68784471 #define _DSPAPOS 0x7018C /* reserved */
4472+#define DISP_POS_Y_MASK REG_GENMASK(31, 0)
4473+#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
4474+#define DISP_POS_X_MASK REG_GENMASK(15, 0)
4475+#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
68794476 #define _DSPASIZE 0x70190
4477+#define DISP_HEIGHT_MASK REG_GENMASK(31, 0)
4478+#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
4479+#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
4480+#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
68804481 #define _DSPASURF 0x7019C /* 965+ only */
4482+#define DISP_ADDR_MASK REG_GENMASK(31, 12)
68814483 #define _DSPATILEOFF 0x701A4 /* 965+ only */
4484+#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
4485+#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
4486+#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
4487+#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
68824488 #define _DSPAOFFSET 0x701A4 /* HSW */
68834489 #define _DSPASURFLIVE 0x701AC
68844490 #define _DSPAGAMC 0x701E0
@@ -6898,15 +4504,28 @@ enum { · 13 unmodified lines
68984504
68994505 /* CHV pipe B blender and primary plane */
69004506 #define _CHV_BLEND_A 0x60a00
6901−#define CHV_BLEND_LEGACY (0 << 30)
6902−#define CHV_BLEND_ANDROID (1 << 30)
6903−#define CHV_BLEND_MPO (2 << 30)
6904−#define CHV_BLEND_MASK (3 << 30)
4507+#define CHV_BLEND_MASK REG_GENMASK(31, 30)
4508+#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
4509+#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
4510+#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
69054511 #define _CHV_CANVAS_A 0x60a04
4512+#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
4513+#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
4514+#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
69064515 #define _PRIMPOS_A 0x60a08
4516+#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
4517+#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
4518+#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
4519+#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
69074520 #define _PRIMSIZE_A 0x60a0c
4521+#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
4522+#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
4523+#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
4524+#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
69084525 #define _PRIMCNSTALPHA_A 0x60a10
6909−#define PRIM_CONST_ALPHA_ENABLE (1 << 31)
4526+#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
4527+#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
4528+#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
69104529
69114530 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
69124531 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
@@ -6947,10 +4566,8 @@ enum { · 34 unmodified lines
69474566
69484567 /* Display B control */
69494568 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
6950−#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
6951−#define DISPPLANE_ALPHA_TRANS_DISABLE 0
6952−#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6953−#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
4569+#define DISP_ALPHA_TRANS_ENABLE REG_BIT(15)
4570+#define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0)
69544571 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
69554572 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
69564573 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
@@ -6966,46 +4583,63 @@ enum { · 9 unmodified lines
69664583
69674584 /* Sprite A control */
69684585 #define _DVSACNTR 0x72180
6969−#define DVS_ENABLE (1 << 31)
6970−#define DVS_GAMMA_ENABLE (1 << 30)
6971−#define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
6972−#define DVS_PIXFORMAT_MASK (3 << 25)
6973−#define DVS_FORMAT_YUV422 (0 << 25)
6974−#define DVS_FORMAT_RGBX101010 (1 << 25)
6975−#define DVS_FORMAT_RGBX888 (2 << 25)
6976−#define DVS_FORMAT_RGBX161616 (3 << 25)
6977−#define DVS_PIPE_CSC_ENABLE (1 << 24)
6978−#define DVS_SOURCE_KEY (1 << 22)
6979−#define DVS_RGB_ORDER_XBGR (1 << 20)
6980−#define DVS_YUV_FORMAT_BT709 (1 << 18)
6981−#define DVS_YUV_ORDER_MASK (3 << 16)
6982−#define DVS_YUV_ORDER_YUYV (0 << 16)
6983−#define DVS_YUV_ORDER_UYVY (1 << 16)
6984−#define DVS_YUV_ORDER_YVYU (2 << 16)
6985−#define DVS_YUV_ORDER_VYUY (3 << 16)
6986−#define DVS_ROTATE_180 (1 << 15)
6987−#define DVS_DEST_KEY (1 << 2)
6988−#define DVS_TRICKLE_FEED_DISABLE (1 << 14)
6989−#define DVS_TILED (1 << 10)
4586+#define DVS_ENABLE REG_BIT(31)
4587+#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
4588+#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
4589+#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
4590+#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
4591+#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
4592+#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
4593+#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
4594+#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
4595+#define DVS_SOURCE_KEY REG_BIT(22)
4596+#define DVS_RGB_ORDER_XBGR REG_BIT(20)
4597+#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
4598+#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
4599+#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
4600+#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
4601+#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
4602+#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
4603+#define DVS_ROTATE_180 REG_BIT(15)
4604+#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
4605+#define DVS_TILED REG_BIT(10)
4606+#define DVS_DEST_KEY REG_BIT(2)
69904607 #define _DVSALINOFF 0x72184
69914608 #define _DVSASTRIDE 0x72188
69924609 #define _DVSAPOS 0x7218c
4610+#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
4611+#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
4612+#define DVS_POS_X_MASK REG_GENMASK(15, 0)
4613+#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
69934614 #define _DVSASIZE 0x72190
4615+#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
4616+#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
4617+#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
4618+#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
69944619 #define _DVSAKEYVAL 0x72194
69954620 #define _DVSAKEYMSK 0x72198
69964621 #define _DVSASURF 0x7219c
4622+#define DVS_ADDR_MASK REG_GENMASK(31, 12)
69974623 #define _DVSAKEYMAXVAL 0x721a0
69984624 #define _DVSATILEOFF 0x721a4
4625+#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
4626+#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
4627+#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
4628+#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
69994629 #define _DVSASURFLIVE 0x721ac
70004630 #define _DVSAGAMC_G4X 0x721e0 /* g4x */
70014631 #define _DVSASCALE 0x72204
7002−#define DVS_SCALE_ENABLE (1 << 31)
7003−#define DVS_FILTER_MASK (3 << 29)
7004−#define DVS_FILTER_MEDIUM (0 << 29)
7005−#define DVS_FILTER_ENHANCING (1 << 29)
7006−#define DVS_FILTER_SOFTENING (2 << 29)
7007−#define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
7008−#define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
4632+#define DVS_SCALE_ENABLE REG_BIT(31)
4633+#define DVS_FILTER_MASK REG_GENMASK(30, 29)
4634+#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
4635+#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
4636+#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
4637+#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
4638+#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
4639+#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
4640+#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
4641+#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
4642+#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
70094643 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
70104644 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
70114645
@@ -7042,50 +4676,67 @@ enum { · 30 unmodified lines
70424676 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
70434677
70444678 #define _SPRA_CTL 0x70280
7045−#define SPRITE_ENABLE (1 << 31)
7046−#define SPRITE_GAMMA_ENABLE (1 << 30)
7047−#define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
7048−#define SPRITE_PIXFORMAT_MASK (7 << 25)
7049−#define SPRITE_FORMAT_YUV422 (0 << 25)
7050−#define SPRITE_FORMAT_RGBX101010 (1 << 25)
7051−#define SPRITE_FORMAT_RGBX888 (2 << 25)
7052−#define SPRITE_FORMAT_RGBX161616 (3 << 25)
7053−#define SPRITE_FORMAT_YUV444 (4 << 25)
7054−#define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */
7055−#define SPRITE_PIPE_CSC_ENABLE (1 << 24)
7056−#define SPRITE_SOURCE_KEY (1 << 22)
7057−#define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
7058−#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
7059−#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
7060−#define SPRITE_YUV_ORDER_MASK (3 << 16)
7061−#define SPRITE_YUV_ORDER_YUYV (0 << 16)
7062−#define SPRITE_YUV_ORDER_UYVY (1 << 16)
7063−#define SPRITE_YUV_ORDER_YVYU (2 << 16)
7064−#define SPRITE_YUV_ORDER_VYUY (3 << 16)
7065−#define SPRITE_ROTATE_180 (1 << 15)
7066−#define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
7067−#define SPRITE_INT_GAMMA_DISABLE (1 << 13)
7068−#define SPRITE_TILED (1 << 10)
7069−#define SPRITE_DEST_KEY (1 << 2)
4679+#define SPRITE_ENABLE REG_BIT(31)
4680+#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
4681+#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
4682+#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
4683+#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
4684+#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
4685+#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
4686+#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
4687+#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
4688+#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
4689+#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
4690+#define SPRITE_SOURCE_KEY REG_BIT(22)
4691+#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
4692+#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
4693+#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
4694+#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
4695+#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
4696+#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
4697+#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
4698+#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
4699+#define SPRITE_ROTATE_180 REG_BIT(15)
4700+#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
4701+#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
4702+#define SPRITE_TILED REG_BIT(10)
4703+#define SPRITE_DEST_KEY REG_BIT(2)
70704704 #define _SPRA_LINOFF 0x70284
70714705 #define _SPRA_STRIDE 0x70288
70724706 #define _SPRA_POS 0x7028c
4707+#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
4708+#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
4709+#define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
4710+#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
70734711 #define _SPRA_SIZE 0x70290
4712+#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
4713+#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
4714+#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
4715+#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
70744716 #define _SPRA_KEYVAL 0x70294
70754717 #define _SPRA_KEYMSK 0x70298
70764718 #define _SPRA_SURF 0x7029c
4719+#define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
70774720 #define _SPRA_KEYMAX 0x702a0
70784721 #define _SPRA_TILEOFF 0x702a4
4722+#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
4723+#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
4724+#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
4725+#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
70794726 #define _SPRA_OFFSET 0x702a4
70804727 #define _SPRA_SURFLIVE 0x702ac
70814728 #define _SPRA_SCALE 0x70304
7082−#define SPRITE_SCALE_ENABLE (1 << 31)
7083−#define SPRITE_FILTER_MASK (3 << 29)
7084−#define SPRITE_FILTER_MEDIUM (0 << 29)
7085−#define SPRITE_FILTER_ENHANCING (1 << 29)
7086−#define SPRITE_FILTER_SOFTENING (2 << 29)
7087−#define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
7088−#define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
4729+#define SPRITE_SCALE_ENABLE REG_BIT(31)
4730+#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
4731+#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
4732+#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
4733+#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
4734+#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
4735+#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
4736+#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
4737+#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
4738+#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
4739+#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
70894740 #define _SPRA_GAMC 0x70400
70904741 #define _SPRA_GAMC16 0x70440
70914742 #define _SPRA_GAMC17 0x7044c
@@ -7125,48 +4776,67 @@ enum { · 33 unmodified lines
71254776 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
71264777
71274778 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
7128−#define SP_ENABLE (1 << 31)
7129−#define SP_GAMMA_ENABLE (1 << 30)
7130−#define SP_PIXFORMAT_MASK (0xf << 26)
7131−#define SP_FORMAT_YUV422 (0x0 << 26)
7132−#define SP_FORMAT_8BPP (0x2 << 26)
7133−#define SP_FORMAT_BGR565 (0x5 << 26)
7134−#define SP_FORMAT_BGRX8888 (0x6 << 26)
7135−#define SP_FORMAT_BGRA8888 (0x7 << 26)
7136−#define SP_FORMAT_RGBX1010102 (0x8 << 26)
7137−#define SP_FORMAT_RGBA1010102 (0x9 << 26)
7138−#define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */
7139−#define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */
7140−#define SP_FORMAT_RGBX8888 (0xe << 26)
7141−#define SP_FORMAT_RGBA8888 (0xf << 26)
7142−#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
7143−#define SP_SOURCE_KEY (1 << 22)
7144−#define SP_YUV_FORMAT_BT709 (1 << 18)
7145−#define SP_YUV_ORDER_MASK (3 << 16)
7146−#define SP_YUV_ORDER_YUYV (0 << 16)
7147−#define SP_YUV_ORDER_UYVY (1 << 16)
7148−#define SP_YUV_ORDER_YVYU (2 << 16)
7149−#define SP_YUV_ORDER_VYUY (3 << 16)
7150−#define SP_ROTATE_180 (1 << 15)
7151−#define SP_TILED (1 << 10)
7152−#define SP_MIRROR (1 << 8) /* CHV pipe B */
4779+#define SP_ENABLE REG_BIT(31)
4780+#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
4781+#define SP_FORMAT_MASK REG_GENMASK(29, 26)
4782+#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
4783+#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
4784+#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
4785+#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
4786+#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
4787+#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
4788+#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
4789+#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
4790+#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
4791+#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
4792+#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
4793+#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
4794+#define SP_SOURCE_KEY REG_BIT(22)
4795+#define SP_YUV_FORMAT_BT709 REG_BIT(18)
4796+#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
4797+#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
4798+#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
4799+#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
4800+#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
4801+#define SP_ROTATE_180 REG_BIT(15)
4802+#define SP_TILED REG_BIT(10)
4803+#define SP_MIRROR REG_BIT(8) /* CHV pipe B */
71534804 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
71544805 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
71554806 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
4807+#define SP_POS_Y_MASK REG_GENMASK(31, 16)
4808+#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
4809+#define SP_POS_X_MASK REG_GENMASK(15, 0)
4810+#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
71564811 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
4812+#define SP_HEIGHT_MASK REG_GENMASK(31, 16)
4813+#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
4814+#define SP_WIDTH_MASK REG_GENMASK(15, 0)
4815+#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
71574816 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
71584817 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
71594818 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
4819+#define SP_ADDR_MASK REG_GENMASK(31, 12)
71604820 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
71614821 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
4822+#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
4823+#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
4824+#define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
4825+#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
71624826 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
7163−#define SP_CONST_ALPHA_ENABLE (1 << 31)
4827+#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
4828+#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
4829+#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
71644830 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
7165−#define SP_CONTRAST(x) ((x) << 18) /* u3.6 */
7166−#define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */
4831+#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
4832+#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
4833+#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
4834+#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
71674835 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
7168−#define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */
7169−#define SP_SH_COS(x) (x) /* u3.7 */
4836+#define SP_SH_SIN_MASK REG_GENMASK(26, 16)
4837+#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
4838+#define SP_SH_COS_MASK REG_GENMASK(9, 0)
4839+#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
71704840 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
71714841
71724842 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
@@ -7217,112 +4887,135 @@ enum { · 44 unmodified lines
72174887 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
72184888 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
72194889 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
7220−#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
7221−#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
4890+#define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
4891+#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
4892+#define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
4893+#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
72224894
72234895 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
72244896 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
72254897 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
72264898 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
72274899 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
7228−#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
7229−#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
4900+#define SPCSC_C1_MASK REG_GENMASK(30, 16)
4901+#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
4902+#define SPCSC_C0_MASK REG_GENMASK(14, 0)
4903+#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
72304904
72314905 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
72324906 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
72334907 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
7234−#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
7235−#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
4908+#define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
4909+#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
4910+#define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
4911+#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
72364912
72374913 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
72384914 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
72394915 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
7240−#define SPCSC_OMAX(x) ((x) << 16) /* u10 */
7241−#define SPCSC_OMIN(x) ((x) << 0) /* u10 */
4916+#define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
4917+#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
4918+#define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
4919+#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
72424920
72434921 /* Skylake plane registers */
72444922
72454923 #define _PLANE_CTL_1_A 0x70180
72464924 #define _PLANE_CTL_2_A 0x70280
72474925 #define _PLANE_CTL_3_A 0x70380
7248−#define PLANE_CTL_ENABLE (1 << 31)
4926+#define PLANE_CTL_ENABLE REG_BIT(31)
72494927 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
72504928 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
7251−#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
7252−#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
4929+#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
4930+#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
72534931 /*
72544932 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
72554933 * expanded to include bit 23 as well. However, the shift-24 based values
72564934 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
72574935 */
7258−#define PLANE_CTL_FORMAT_MASK (0xf << 24)
7259−#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
7260−#define PLANE_CTL_FORMAT_NV12 (1 << 24)
7261−#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
7262−#define PLANE_CTL_FORMAT_P010 (3 << 24)
7263−#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
7264−#define PLANE_CTL_FORMAT_P012 (5 << 24)
7265−#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
7266−#define PLANE_CTL_FORMAT_P016 (7 << 24)
7267−#define PLANE_CTL_FORMAT_XYUV (8 << 24)
7268−#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
7269−#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
7270−#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
7271−#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
7272−#define PLANE_CTL_FORMAT_Y210 (1 << 23)
7273−#define PLANE_CTL_FORMAT_Y212 (3 << 23)
7274−#define PLANE_CTL_FORMAT_Y216 (5 << 23)
7275−#define PLANE_CTL_FORMAT_Y410 (7 << 23)
7276−#define PLANE_CTL_FORMAT_Y412 (9 << 23)
7277−#define PLANE_CTL_FORMAT_Y416 (0xb << 23)
7278−#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
7279−#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
7280−#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
7281−#define PLANE_CTL_ORDER_BGRX (0 << 20)
7282−#define PLANE_CTL_ORDER_RGBX (1 << 20)
7283−#define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
7284−#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
7285−#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
7286−#define PLANE_CTL_YUV422_ORDER_YUYV (0 << 16)
7287−#define PLANE_CTL_YUV422_ORDER_UYVY (1 << 16)
7288−#define PLANE_CTL_YUV422_ORDER_YVYU (2 << 16)
7289−#define PLANE_CTL_YUV422_ORDER_VYUY (3 << 16)
7290−#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
7291−#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
7292−#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
7293−#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
7294−#define PLANE_CTL_TILED_MASK (0x7 << 10)
7295−#define PLANE_CTL_TILED_LINEAR (0 << 10)
7296−#define PLANE_CTL_TILED_X (1 << 10)
7297−#define PLANE_CTL_TILED_Y (4 << 10)
7298−#define PLANE_CTL_TILED_YF (5 << 10)
7299−#define PLANE_CTL_ASYNC_FLIP (1 << 9)
7300−#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
7301−#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
7302−#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
7303−#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
7304−#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
7305−#define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
7306−#define PLANE_CTL_ROTATE_MASK 0x3
7307−#define PLANE_CTL_ROTATE_0 0x0
7308−#define PLANE_CTL_ROTATE_90 0x1
7309−#define PLANE_CTL_ROTATE_180 0x2
7310−#define PLANE_CTL_ROTATE_270 0x3
4936+#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
4937+#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
4938+#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
4939+#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
4940+#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
4941+#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
4942+#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
4943+#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
4944+#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
4945+#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
4946+#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
4947+#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
4948+#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
4949+#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
4950+#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
4951+#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
4952+#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
4953+#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
4954+#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
4955+#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
4956+#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
4957+#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
4958+#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
4959+#define PLANE_CTL_ORDER_RGBX REG_BIT(20)
4960+#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
4961+#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
4962+#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
4963+#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
4964+#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
4965+#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
4966+#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
4967+#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
4968+#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
4969+#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
4970+#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
4971+#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
4972+#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
4973+#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
4974+#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
4975+#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
4976+#define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
4977+#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
4978+#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
4979+#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
4980+#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
4981+#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
4982+#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
4983+#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
4984+#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
4985+#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
4986+#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
4987+#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
73114988 #define _PLANE_STRIDE_1_A 0x70188
73124989 #define _PLANE_STRIDE_2_A 0x70288
73134990 #define _PLANE_STRIDE_3_A 0x70388
4991+#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
4992+#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
73144993 #define _PLANE_POS_1_A 0x7018c
73154994 #define _PLANE_POS_2_A 0x7028c
73164995 #define _PLANE_POS_3_A 0x7038c
4996+#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
4997+#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
4998+#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
4999+#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
73175000 #define _PLANE_SIZE_1_A 0x70190
73185001 #define _PLANE_SIZE_2_A 0x70290
73195002 #define _PLANE_SIZE_3_A 0x70390
5003+#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
5004+#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
5005+#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
5006+#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
73205007 #define _PLANE_SURF_1_A 0x7019c
73215008 #define _PLANE_SURF_2_A 0x7029c
73225009 #define _PLANE_SURF_3_A 0x7039c
5010+#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
5011+#define PLANE_SURF_DECRYPT REG_BIT(2)
73235012 #define _PLANE_OFFSET_1_A 0x701a4
73245013 #define _PLANE_OFFSET_2_A 0x702a4
73255014 #define _PLANE_OFFSET_3_A 0x703a4
5015+#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
5016+#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
5017+#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
5018+#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
73265019 #define _PLANE_KEYVAL_1_A 0x70194
73275020 #define _PLANE_KEYVAL_2_A 0x70294
73285021 #define _PLANE_KEYMSK_1_A 0x70198
@@ -7334,42 +5027,49 @@ enum { · 5 unmodified lines
73345027 #define _PLANE_CC_VAL_1_A 0x701b4
73355028 #define _PLANE_CC_VAL_2_A 0x702b4
73365029 #define _PLANE_AUX_DIST_1_A 0x701c0
5030+#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
5031+#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
5032+#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
73375033 #define _PLANE_AUX_DIST_2_A 0x702c0
73385034 #define _PLANE_AUX_OFFSET_1_A 0x701c4
73395035 #define _PLANE_AUX_OFFSET_2_A 0x702c4
73405036 #define _PLANE_CUS_CTL_1_A 0x701c8
73415037 #define _PLANE_CUS_CTL_2_A 0x702c8
7342−#define PLANE_CUS_ENABLE (1 << 31)
7343−#define PLANE_CUS_Y_PLANE_4_RKL (0 << 30)
7344−#define PLANE_CUS_Y_PLANE_5_RKL (1 << 30)
7345−#define PLANE_CUS_Y_PLANE_6_ICL (0 << 30)
7346−#define PLANE_CUS_Y_PLANE_7_ICL (1 << 30)
7347−#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
7348−#define PLANE_CUS_HPHASE_0 (0 << 16)
7349−#define PLANE_CUS_HPHASE_0_25 (1 << 16)
7350−#define PLANE_CUS_HPHASE_0_5 (2 << 16)
7351−#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
7352−#define PLANE_CUS_VPHASE_0 (0 << 12)
7353−#define PLANE_CUS_VPHASE_0_25 (1 << 12)
7354−#define PLANE_CUS_VPHASE_0_5 (2 << 12)
5038+#define PLANE_CUS_ENABLE REG_BIT(31)
5039+#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
5040+#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
5041+#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
5042+#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
5043+#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
5044+#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
5045+#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
5046+#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
5047+#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
5048+#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
5049+#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
5050+#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
5051+#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
5052+#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
5053+#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
73555054 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
73565055 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
73575056 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
7358−#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
7359−#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
5057+#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
5058+#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
5059+#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
73605060 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
7361−#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
7362−#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
7363−#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
7364−#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17)
7365−#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
7366−#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
7367−#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
7368−#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
7369−#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
7370−#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
7371−#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
7372−#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
5061+#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
5062+#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
5063+#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
5064+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
5065+#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
5066+#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
5067+#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
5068+#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
5069+#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
5070+#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
5071+#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
5072+#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
73735073 #define _PLANE_BUF_CFG_1_A 0x7027c
73745074 #define _PLANE_BUF_CFG_2_A 0x7037c
73755075 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
@@ -7452,8 +5152,6 @@ enum { · 76 unmodified lines
74525152 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
74535153 #define PLANE_STRIDE(pipe, plane) \
74545154 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
7455−#define PLANE_STRIDE_MASK REG_GENMASK(10, 0)
7456−#define PLANE_STRIDE_MASK_XELPD REG_GENMASK(11, 0)
74575155
74585156 #define _PLANE_POS_1_B 0x7118c
74595157 #define _PLANE_POS_2_B 0x7128c
@@ -7481,7 +5179,6 @@ enum { · 21 unmodified lines
74815179 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
74825180 #define PLANE_SURF(pipe, plane) \
74835181 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
7484−#define PLANE_SURF_DECRYPT REG_BIT(2)
74855182
74865183 #define _PLANE_OFFSET_1_B 0x711a4
74875184 #define _PLANE_OFFSET_2_B 0x712a4
@@ -7513,8 +5210,11 @@ enum { · 25 unmodified lines
75135210
75145211 #define _PLANE_BUF_CFG_1_B 0x7127c
75155212 #define _PLANE_BUF_CFG_2_B 0x7137c
7516−#define DDB_ENTRY_MASK 0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
7517−#define DDB_ENTRY_END_SHIFT 16
5213+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
5214+#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
5215+#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
5216+#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
5217+#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
75185218 #define _PLANE_BUF_CFG_1(pipe) \
75195219 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
75205220 #define _PLANE_BUF_CFG_2(pipe) \
@@ -7669,24 +5369,13 @@ enum { · 148 unmodified lines
76695369
76705370
76715371 #define _PIPEA_DATA_M1 0x60030
7672−#define PIPE_DATA_M1_OFFSET 0
76735372 #define _PIPEA_DATA_N1 0x60034
7674−#define PIPE_DATA_N1_OFFSET 0
7675−
76765373 #define _PIPEA_DATA_M2 0x60038
7677−#define PIPE_DATA_M2_OFFSET 0
76785374 #define _PIPEA_DATA_N2 0x6003c
7679−#define PIPE_DATA_N2_OFFSET 0
7680−
76815375 #define _PIPEA_LINK_M1 0x60040
7682−#define PIPE_LINK_M1_OFFSET 0
76835376 #define _PIPEA_LINK_N1 0x60044
7684−#define PIPE_LINK_N1_OFFSET 0
7685−
76865377 #define _PIPEA_LINK_M2 0x60048
7687−#define PIPE_LINK_M2_OFFSET 0
76885378 #define _PIPEA_LINK_N2 0x6004c
7689−#define PIPE_LINK_N2_OFFSET 0
76905379
76915380 /* PIPEB timing regs are same start from 0x61000 */
76925381
@@ -8198,63 +5887,6 @@ enum { · 505 unmodified lines
81985887 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
81995888 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
82005889
8201−#define GEN11_GT_INTR_DW0 _MMIO(0x190018)
8202−#define GEN11_CSME (31)
8203−#define GEN11_GUNIT (28)
8204−#define GEN11_GUC (25)
8205−#define GEN11_WDPERF (20)
8206−#define GEN11_KCR (19)
8207−#define GEN11_GTPM (16)
8208−#define GEN11_BCS (15)
8209−#define GEN11_RCS0 (0)
8210−
8211−#define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
8212−#define GEN11_VECS(x) (31 - (x))
8213−#define GEN11_VCS(x) (x)
8214−
8215−#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
8216−
8217−#define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
8218−#define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
8219−#define GEN11_INTR_DATA_VALID (1 << 31)
8220−#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
8221−#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
8222−#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
8223−/* irq instances for OTHER_CLASS */
8224−#define OTHER_GUC_INSTANCE 0
8225−#define OTHER_GTPM_INSTANCE 1
8226−#define OTHER_KCR_INSTANCE 4
8227−
8228−#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
8229−
8230−#define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
8231−#define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
8232−
8233−#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
8234−
8235−#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
8236−#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
8237−#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
8238−#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
8239−#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
8240−#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
8241−
8242−#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
8243−#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
8244−#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
8245−#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
8246−#define GEN12_VCS4_VCS5_INTR_MASK _MMIO(0x1900b0)
8247−#define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4)
8248−#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
8249−#define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4)
8250−#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
8251−#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
8252−#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
8253−#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
8254−
8255−#define ENGINE1_MASK REG_GENMASK(31, 16)
8256−#define ENGINE0_MASK REG_GENMASK(15, 0)
8257−
82585890 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
82595891 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
82605892 #define ILK_ELPIN_409_SELECT (1 << 25)
@@ -8441,142 +6073,6 @@ enum { · 180 unmodified lines
84416073 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
84426074 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
84436075
8444−#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
8445−#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
8446−
8447−#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
8448−#define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8)
8449−#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
8450−
8451−#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
8452−#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
8453−#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
8454−#define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
8455−
8456−#define GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON _MMIO(0x20EC)
8457−#define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0)
8458−
8459−#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
8460−#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
8461−#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
8462−#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
8463−#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
8464−#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
8465−#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
8466−
8467−/* GEN7 chicken */
8468−#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
8469− #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10)
8470− #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
8471−
8472−#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
8473− #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
8474− #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
8475− #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
8476− #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
8477−
8478−#define GEN8_L3CNTLREG _MMIO(0x7034)
8479− #define GEN8_ERRDETBCTRL (1 << 9)
8480−
8481−#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
8482−#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
8483−#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
8484−#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
8485−#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
8486−
8487−#define HIZ_CHICKEN _MMIO(0x7018)
8488−# define CHV_HZ_8X8_MODE_IN_1X REG_BIT(15)
8489−# define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
8490−# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE REG_BIT(3)
8491−
8492−#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
8493−#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
8494−
8495−#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
8496−#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
8497−
8498−#define GEN7_SARCHKMD _MMIO(0xB000)
8499−#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
8500−#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
8501−
8502−#define GEN7_L3SQCREG1 _MMIO(0xB010)
8503−#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
8504−
8505−#define GEN8_L3SQCREG1 _MMIO(0xB100)
8506−/*
8507− * Note that on CHV the following has an off-by-one error wrt. to BSpec.
8508− * Using the formula in BSpec leads to a hang, while the formula here works
8509− * fine and matches the formulas for all other platforms. A BSpec change
8510− * request has been filed to clarify this.
8511− */
8512−#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
8513−#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
8514−#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
8515−
8516−#define GEN7_L3CNTLREG1 _MMIO(0xB01C)
8517−#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
8518−#define GEN7_L3AGDIS (1 << 19)
8519−#define GEN7_L3CNTLREG2 _MMIO(0xB020)
8520−#define GEN7_L3CNTLREG3 _MMIO(0xB024)
8521−
8522−#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
8523−#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
8524−#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
8525−#define GEN11_I2M_WRITE_DISABLE (1 << 28)
8526−
8527−#define GEN7_L3SQCREG4 _MMIO(0xb034)
8528−#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27)
8529−
8530−#define GEN11_SCRATCH2 _MMIO(0xb140)
8531−#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19)
8532−
8533−#define GEN8_L3SQCREG4 _MMIO(0xb118)
8534−#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
8535−#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
8536−#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
8537−#define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
8538−
8539−#define GEN11_L3SQCREG5 _MMIO(0xb158)
8540−#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
8541−
8542−#define XEHP_L3SCQREG7 _MMIO(0xb188)
8543−#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
8544−
8545−/* GEN8 chicken */
8546−#define HDC_CHICKEN0 _MMIO(0x7300)
8547−#define ICL_HDC_MODE _MMIO(0xE5F4)
8548−#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
8549−#define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
8550−#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11)
8551−#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5)
8552−#define HDC_FORCE_NON_COHERENT (1 << 4)
8553−#define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10)
8554−
8555−#define GEN12_HDC_CHICKEN0 _MMIO(0xE5F0)
8556−#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
8557−
8558−#define SARB_CHICKEN1 _MMIO(0xe90c)
8559−#define COMP_CKN_IN REG_GENMASK(30, 29)
8560−
8561−#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
8562−
8563−/* GEN9 chicken */
8564−#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
8565−#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
8566−
8567−#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
8568−#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
8569−
8570−/* WaCatErrorRejectionIssue */
8571−#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
8572−#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11)
8573−
8574−#define HSW_SCRATCH1 _MMIO(0xb038)
8575−#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27)
8576−
8577−#define BDW_SCRATCH1 _MMIO(0xb11c)
8578−#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
8579−
85806076 /*GEN11 chicken */
85816077 #define _PIPEA_CHICKEN 0x70038
85826078 #define _PIPEB_CHICKEN 0x71038
@@ -8589,16 +6085,6 @@ enum { · 6 unmodified lines
85896085 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
85906086 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
85916087
8592−#define VFLSKPD _MMIO(0x62a8)
8593−#define DIS_OVER_FETCH_CACHE REG_BIT(1)
8594−#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
8595−
8596−#define FF_MODE2 _MMIO(0x6604)
8597−#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
8598−#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
8599−#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
8600−#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
8601−
86026088 /* PCH */
86036089
86046090 #define PCH_DISPLAY_BASE 0xc0000u
@@ -9013,22 +6499,19 @@ enum { · 408 unmodified lines
90136499 #define _PCH_TRANSBCONF 0xf1008
90146500 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
90156501 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
9016−#define TRANS_DISABLE (0 << 31)
9017−#define TRANS_ENABLE (1 << 31)
9018−#define TRANS_STATE_MASK (1 << 30)
9019−#define TRANS_STATE_DISABLE (0 << 30)
9020−#define TRANS_STATE_ENABLE (1 << 30)
9021−#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
9022−#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
9023−#define TRANS_INTERLACE_MASK (7 << 21)
9024−#define TRANS_PROGRESSIVE (0 << 21)
9025−#define TRANS_INTERLACED (3 << 21)
9026−#define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
9027−#define TRANS_8BPC (0 << 5)
9028−#define TRANS_10BPC (1 << 5)
9029−#define TRANS_6BPC (2 << 5)
9030−#define TRANS_12BPC (3 << 5)
9031−
6502+#define TRANS_ENABLE REG_BIT(31)
6503+#define TRANS_STATE_ENABLE REG_BIT(30)
6504+#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
6505+#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
6506+#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
6507+#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
6508+#define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
6509+#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
6510+#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
6511+#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
6512+#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
6513+#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
6514+#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
90326515 #define _TRANSA_CHICKEN1 0xf0060
90336516 #define _TRANSB_CHICKEN1 0xf1060
90346517 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
@@ -9238,22 +6721,19 @@ enum { · 203 unmodified lines
92386721 #define _TRANS_DP_CTL_B 0xe1300
92396722 #define _TRANS_DP_CTL_C 0xe2300
92406723 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
9241−#define TRANS_DP_OUTPUT_ENABLE (1 << 31)
9242−#define TRANS_DP_PORT_SEL_MASK (3 << 29)
9243−#define TRANS_DP_PORT_SEL_NONE (3 << 29)
9244−#define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
9245−#define TRANS_DP_AUDIO_ONLY (1 << 26)
9246−#define TRANS_DP_ENH_FRAMING (1 << 18)
9247−#define TRANS_DP_8BPC (0 << 9)
9248−#define TRANS_DP_10BPC (1 << 9)
9249−#define TRANS_DP_6BPC (2 << 9)
9250−#define TRANS_DP_12BPC (3 << 9)
9251−#define TRANS_DP_BPC_MASK (3 << 9)
9252−#define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4)
9253−#define TRANS_DP_VSYNC_ACTIVE_LOW 0
9254−#define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3)
9255−#define TRANS_DP_HSYNC_ACTIVE_LOW 0
9256−#define TRANS_DP_SYNC_MASK (3 << 3)
6724+#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
6725+#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
6726+#define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
6727+#define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
6728+#define TRANS_DP_AUDIO_ONLY REG_BIT(26)
6729+#define TRANS_DP_ENH_FRAMING REG_BIT(18)
6730+#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
6731+#define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
6732+#define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
6733+#define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
6734+#define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
6735+#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
6736+#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
92576737
92586738 #define _TRANS_DP2_CTL_A 0x600a0
92596739 #define _TRANS_DP2_CTL_B 0x610a0
@@ -9312,261 +6792,16 @@ enum { · 52 unmodified lines
93126792
93136793 #define VLV_PMWGICZ _MMIO(0x1300a4)
93146794
9315−#define RC6_LOCATION _MMIO(0xD40)
9316−#define RC6_CTX_IN_DRAM (1 << 0)
9317−#define RC6_CTX_BASE _MMIO(0xD48)
9318−#define RC6_CTX_BASE_MASK 0xFFFFFFF0
9319−#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
9320−#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
9321−#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
9322−#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
9323−#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
9324−#define IDLE_TIME_MASK 0xFFFFF
9325−#define FORCEWAKE _MMIO(0xA18C)
9326−#define FORCEWAKE_VLV _MMIO(0x1300b0)
9327−#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
9328−#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
9329−#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
9330−#define FORCEWAKE_ACK_HSW _MMIO(0x130044)
9331−#define FORCEWAKE_ACK _MMIO(0x130090)
9332−#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
9333−#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
9334−#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
9335−#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
9336−
9337−#define VLV_GTLC_PW_STATUS _MMIO(0x130094)
9338−#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
9339−#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
9340−#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
9341−#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
9342−#define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
9343−#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
9344−#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
9345−#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
9346−#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
9347−#define FORCEWAKE_GT_GEN9 _MMIO(0xa188)
9348−#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
9349−#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4)
9350−#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4)
9351−#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
9352−#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)
9353−#define FORCEWAKE_KERNEL BIT(0)
9354−#define FORCEWAKE_USER BIT(1)
9355−#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
9356−#define FORCEWAKE_MT_ACK _MMIO(0x130040)
9357−#define ECOBUS _MMIO(0xa180)
9358−#define FORCEWAKE_MT_ENABLE (1 << 5)
9359−#define VLV_SPAREG2H _MMIO(0xA194)
9360−#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
9361−#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
9362−#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
9363−
9364−#define GTFIFODBG _MMIO(0x120000)
9365−#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
9366−#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
9367−#define GT_FIFO_SBDROPERR (1 << 6)
9368−#define GT_FIFO_BLOBDROPERR (1 << 5)
9369−#define GT_FIFO_SB_READ_ABORTERR (1 << 4)
9370−#define GT_FIFO_DROPERR (1 << 3)
9371−#define GT_FIFO_OVFERR (1 << 2)
9372−#define GT_FIFO_IAWRERR (1 << 1)
9373−#define GT_FIFO_IARDERR (1 << 0)
9374−
9375−#define GTFIFOCTL _MMIO(0x120008)
9376−#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
9377−#define GT_FIFO_NUM_RESERVED_ENTRIES 20
9378−#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
9379−#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
9380−
9381−#define HSW_IDICR _MMIO(0x9008)
9382−#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
93836795 #define HSW_EDRAM_CAP _MMIO(0x120010)
93846796 #define EDRAM_ENABLED 0x1
93856797 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
93866798 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
93876799 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
93886800
9389−#define GEN6_UCGCTL1 _MMIO(0x9400)
9390−# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
9391−# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
9392−# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
9393−# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
9394−
9395−#define GEN6_UCGCTL2 _MMIO(0x9404)
9396−# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
9397−# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
9398−# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
9399−# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
9400−# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
9401−# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
9402−
9403−#define GEN6_UCGCTL3 _MMIO(0x9408)
9404−# define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
9405−
9406−#define GEN7_UCGCTL4 _MMIO(0x940c)
9407−#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25)
9408−#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14)
9409−
9410−#define GEN6_RCGCTL1 _MMIO(0x9410)
9411−#define GEN6_RCGCTL2 _MMIO(0x9414)
9412−#define GEN6_RSTCTL _MMIO(0x9420)
9413−
9414−#define GEN8_UCGCTL6 _MMIO(0x9430)
9415−#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24)
9416−#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14)
9417−#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
9418−
9419−#define UNSLCGCTL9430 _MMIO(0x9430)
9420−#define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
9421−
9422−#define GEN6_GFXPAUSE _MMIO(0xA000)
9423−#define GEN6_RPNSWREQ _MMIO(0xA008)
9424−#define GEN6_TURBO_DISABLE (1 << 31)
9425−#define GEN6_FREQUENCY(x) ((x) << 25)
9426−#define HSW_FREQUENCY(x) ((x) << 24)
9427−#define GEN9_FREQUENCY(x) ((x) << 23)
9428−#define GEN6_OFFSET(x) ((x) << 19)
9429−#define GEN6_AGGRESSIVE_TURBO (0 << 15)
9430−#define GEN9_SW_REQ_UNSLICE_RATIO_SHIFT 23
9431−#define GEN9_IGNORE_SLICE_RATIO (0 << 0)
9432−
9433−#define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
9434−#define GEN6_RC_CONTROL _MMIO(0xA090)
9435−#define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16)
9436−#define GEN6_RC_CTL_RC6p_ENABLE (1 << 17)
9437−#define GEN6_RC_CTL_RC6_ENABLE (1 << 18)
9438−#define GEN6_RC_CTL_RC1e_ENABLE (1 << 20)
9439−#define GEN6_RC_CTL_RC7_ENABLE (1 << 22)
9440−#define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24)
9441−#define GEN7_RC_CTL_TO_MODE (1 << 28)
9442−#define GEN6_RC_CTL_EI_MODE(x) ((x) << 27)
9443−#define GEN6_RC_CTL_HW_ENABLE (1 << 31)
9444−#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
9445−#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
9446−#define GEN6_RPSTAT1 _MMIO(0xA01C)
9447−#define GEN6_CAGF_SHIFT 8
9448−#define HSW_CAGF_SHIFT 7
9449−#define GEN9_CAGF_SHIFT 23
9450−#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
9451−#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
9452−#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
9453−#define GEN6_RP_CONTROL _MMIO(0xA024)
9454−#define GEN6_RP_MEDIA_TURBO (1 << 11)
9455−#define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
9456−#define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9)
9457−#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9)
9458−#define GEN6_RP_MEDIA_HW_MODE (1 << 9)
9459−#define GEN6_RP_MEDIA_SW_MODE (0 << 9)
9460−#define GEN6_RP_MEDIA_IS_GFX (1 << 8)
9461−#define GEN6_RP_ENABLE (1 << 7)
9462−#define GEN6_RP_UP_IDLE_MIN (0x1 << 3)
9463−#define GEN6_RP_UP_BUSY_AVG (0x2 << 3)
9464−#define GEN6_RP_UP_BUSY_CONT (0x4 << 3)
9465−#define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0)
9466−#define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0)
9467−#define GEN6_RPSWCTL_SHIFT 9
9468−#define GEN9_RPSWCTL_ENABLE (0x2 << GEN6_RPSWCTL_SHIFT)
9469−#define GEN9_RPSWCTL_DISABLE (0x0 << GEN6_RPSWCTL_SHIFT)
9470−#define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
9471−#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
9472−#define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
9473−#define GEN6_RP_EI_MASK 0xffffff
9474−#define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
9475−#define GEN6_RP_CUR_UP _MMIO(0xA054)
9476−#define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
9477−#define GEN6_RP_PREV_UP _MMIO(0xA058)
9478−#define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
9479−#define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
9480−#define GEN6_RP_CUR_DOWN _MMIO(0xA060)
9481−#define GEN6_RP_PREV_DOWN _MMIO(0xA064)
9482−#define GEN6_RP_UP_EI _MMIO(0xA068)
9483−#define GEN6_RP_DOWN_EI _MMIO(0xA06C)
9484−#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
9485−#define GEN6_RPDEUHWTC _MMIO(0xA080)
9486−#define GEN6_RPDEUC _MMIO(0xA084)
9487−#define GEN6_RPDEUCSW _MMIO(0xA088)
9488−#define GEN6_RC_STATE _MMIO(0xA094)
9489−#define RC_SW_TARGET_STATE_SHIFT 16
9490−#define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
9491−#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
9492−#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
9493−#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
9494−#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
9495−#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
9496−#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
9497−#define GEN6_RC_SLEEP _MMIO(0xA0B0)
9498−#define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
9499−#define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
9500−#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
9501−#define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
9502−#define VLV_RCEDATA _MMIO(0xA0BC)
9503−#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
9504−#define GEN6_PMINTRMSK _MMIO(0xA168)
9505−#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
9506−#define ARAT_EXPIRED_INTRMSK (1 << 9)
9507−#define GEN8_MISC_CTRL0 _MMIO(0xA180)
9508−#define VLV_PWRDWNUPCTL _MMIO(0xA294)
9509−#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
9510−#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
9511−#define GEN9_PG_ENABLE _MMIO(0xA210)
9512−#define GEN9_RENDER_PG_ENABLE REG_BIT(0)
9513−#define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
9514−#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
9515−#define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n))
9516−#define VDN_MFX_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n))
9517−#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
9518−#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
9519−#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
9520−
95216801 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
95226802 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
95236803 #define PIXEL_OVERLAP_CNT_SHIFT 30
95246804
9525−#define GEN6_PMISR _MMIO(0x44020)
9526−#define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
9527−#define GEN6_PMIIR _MMIO(0x44028)
9528−#define GEN6_PMIER _MMIO(0x4402C)
9529−#define GEN6_PM_MBOX_EVENT (1 << 25)
9530−#define GEN6_PM_THERMAL_EVENT (1 << 24)
9531−
9532−/*
9533− * For Gen11 these are in the upper word of the GPM_WGBOXPERF
9534− * registers. Shifting is handled on accessing the imr and ier.
9535− */
9536−#define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6)
9537−#define GEN6_PM_RP_UP_THRESHOLD (1 << 5)
9538−#define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
9539−#define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
9540−#define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
9541−#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \
9542− GEN6_PM_RP_UP_THRESHOLD | \
9543− GEN6_PM_RP_DOWN_EI_EXPIRED | \
9544− GEN6_PM_RP_DOWN_THRESHOLD | \
9545− GEN6_PM_RP_DOWN_TIMEOUT)
9546−
9547−#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
9548−#define GEN7_GT_SCRATCH_REG_NUM 8
9549−
9550−#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
9551−#define VLV_GFX_CLK_STATUS_BIT (1 << 3)
9552−#define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2)
9553−
9554−#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
9555−#define VLV_COUNTER_CONTROL _MMIO(0x138104)
9556−#define VLV_COUNT_RANGE_HIGH (1 << 15)
9557−#define VLV_MEDIA_RC0_COUNT_EN (1 << 5)
9558−#define VLV_RENDER_RC0_COUNT_EN (1 << 4)
9559−#define VLV_MEDIA_RC6_COUNT_EN (1 << 1)
9560−#define VLV_RENDER_RC6_COUNT_EN (1 << 0)
9561−#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
9562−#define VLV_GT_RENDER_RC6 _MMIO(0x138108)
9563−#define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
9564−
9565−#define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
9566−#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
9567−#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
9568−#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
9569−
95706805 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
95716806 #define GEN6_PCODE_READY (1 << 31)
95726807 #define GEN6_PCODE_ERROR_MASK 0xFF
@@ -9633,82 +6868,6 @@ enum { · 60 unmodified lines
96336868 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
96346869 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
96356870
9636−#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
9637−#define GEN6_CORE_CPD_STATE_MASK (7 << 4)
9638−#define GEN6_RCn_MASK 7
9639−#define GEN6_RC0 0
9640−#define GEN6_RC3 2
9641−#define GEN6_RC6 3
9642−#define GEN6_RC7 4
9643−
9644−#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
9645−#define GEN8_LSLICESTAT_MASK 0x7
9646−
9647−#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
9648−#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
9649−#define CHV_SS_PG_ENABLE (1 << 1)
9650−#define CHV_EU08_PG_ENABLE (1 << 9)
9651−#define CHV_EU19_PG_ENABLE (1 << 17)
9652−#define CHV_EU210_PG_ENABLE (1 << 25)
9653−
9654−#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
9655−#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
9656−#define CHV_EU311_PG_ENABLE (1 << 1)
9657−
9658−#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
9659−#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
9660− ((slice) % 3) * 0x4)
9661−#define GEN9_PGCTL_SLICE_ACK (1 << 0)
9662−#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
9663−#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
9664−
9665−#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
9666−#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
9667− ((slice) % 3) * 0x8)
9668−#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
9669−#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
9670− ((slice) % 3) * 0x8)
9671−#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
9672−#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
9673−#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
9674−#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
9675−#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
9676−#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
9677−#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
9678−#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
9679−
9680−#define GEN7_MISCCPCTL _MMIO(0x9424)
9681−#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
9682−#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
9683−#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
9684−#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6)
9685−
9686−#define GEN8_GARBCNTL _MMIO(0xB004)
9687−#define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
9688−#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
9689−#define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0)
9690−#define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0)
9691−
9692−#define GEN11_GLBLINVL _MMIO(0xB404)
9693−#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
9694−#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
9695−
9696−#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
9697−#define DFR_DISABLE (1 << 9)
9698−
9699−#define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
9700−#define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
9701−#define GEN11_HASH_CTRL_BIT0 (1 << 0)
9702−#define GEN11_HASH_CTRL_BIT4 (1 << 12)
9703−
9704−#define GEN11_LSN_UNSLCVC _MMIO(0xB43C)
9705−#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
9706−#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
9707−
9708−#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
9709−#define ENABLE_SMALLPL REG_BIT(15)
9710−#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
9711−
97126871 /* IVYBRIDGE DPF */
97136872 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
97146873 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
@@ -9723,73 +6882,6 @@ enum { · 8 unmodified lines
97236882 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
97246883 #define GEN7_L3CDERRST1_ENABLE (1 << 7)
97256884
9726−#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
9727−#define GEN7_L3LOG_SIZE 0x80
9728−
9729−#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
9730−#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
9731−#define GEN7_MAX_PS_THREAD_DEP (8 << 12)
9732−#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
9733−#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
9734−#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
9735−
9736−#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
9737−#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
9738−#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
9739−
9740−#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
9741−#define FLOW_CONTROL_ENABLE REG_BIT(15)
9742−#define UGM_BACKUP_MODE REG_BIT(13)
9743−#define MDQ_ARBITRATION_MODE REG_BIT(12)
9744−#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
9745−#define STALL_DOP_GATING_DISABLE REG_BIT(5)
9746−#define THROTTLE_12_5 REG_GENMASK(4, 2)
9747−#define DISABLE_EARLY_EOT REG_BIT(1)
9748−
9749−#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
9750−#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
9751−#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
9752−#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
9753−#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
9754−
9755−#define LSC_CHICKEN_BIT_0 _MMIO(0xe7c8)
9756−#define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
9757−#define LSC_CHICKEN_BIT_0_UDW _MMIO(0xe7c8 + 4)
9758−#define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
9759−#define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
9760−#define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
9761−#define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
9762−#define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
9763−
9764−#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
9765−#define DOP_CLOCK_GATING_DISABLE (1 << 0)
9766−#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
9767−#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
9768−
9769−#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
9770−#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
9771−#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
9772−#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
9773−#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
9774−
9775−#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
9776−#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
9777−
9778−#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
9779−#define GEN8_ST_PO_DISABLE (1 << 13)
9780−
9781−#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
9782−#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
9783−#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
9784−#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
9785−#define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
9786−
9787−#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
9788−#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
9789−#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR REG_BIT(8)
9790−#define GEN9_ENABLE_YV12_BUGFIX REG_BIT(4)
9791−#define GEN9_ENABLE_GPGPU_PREEMPTION REG_BIT(2)
9792−
97936885 /* Audio */
97946886 #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
97956887 #define INTEL_AUDIO_DEVCL 0x808629FB
@@ -10838,149 +7930,6 @@ enum skl_power_gate { · 1042 unmodified lines
108387930 PORTTC1_PLL_ENABLE, \
108397931 PORTTC2_PLL_ENABLE)
108407932
10841−#define _MG_REFCLKIN_CTL_PORT1 0x16892C
10842−#define _MG_REFCLKIN_CTL_PORT2 0x16992C
10843−#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
10844−#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
10845−#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
10846−#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
10847−#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
10848− _MG_REFCLKIN_CTL_PORT1, \
10849− _MG_REFCLKIN_CTL_PORT2)
10850−
10851−#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
10852−#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
10853−#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
10854−#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
10855−#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
10856−#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
10857−#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
10858−#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
10859−#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
10860− _MG_CLKTOP2_CORECLKCTL1_PORT1, \
10861− _MG_CLKTOP2_CORECLKCTL1_PORT2)
10862−
10863−#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
10864−#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
10865−#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
10866−#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
10867−#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
10868−#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
10869−#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
10870−#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
10871−#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
10872−#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
10873−#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
10874−#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
10875−#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
10876−#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
10877−#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
10878−#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
10879−#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
10880− _MG_CLKTOP2_HSCLKCTL_PORT1, \
10881− _MG_CLKTOP2_HSCLKCTL_PORT2)
10882−
10883−#define _MG_PLL_DIV0_PORT1 0x168A00
10884−#define _MG_PLL_DIV0_PORT2 0x169A00
10885−#define _MG_PLL_DIV0_PORT3 0x16AA00
10886−#define _MG_PLL_DIV0_PORT4 0x16BA00
10887−#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
10888−#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
10889−#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
10890−#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
10891−#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
10892−#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
10893−#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
10894− _MG_PLL_DIV0_PORT2)
10895−
10896−#define _MG_PLL_DIV1_PORT1 0x168A04
10897−#define _MG_PLL_DIV1_PORT2 0x169A04
10898−#define _MG_PLL_DIV1_PORT3 0x16AA04
10899−#define _MG_PLL_DIV1_PORT4 0x16BA04
10900−#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
10901−#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
10902−#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
10903−#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
10904−#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
10905−#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
10906−#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
10907−#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
10908−#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
10909− _MG_PLL_DIV1_PORT2)
10910−
10911−#define _MG_PLL_LF_PORT1 0x168A08
10912−#define _MG_PLL_LF_PORT2 0x169A08
10913−#define _MG_PLL_LF_PORT3 0x16AA08
10914−#define _MG_PLL_LF_PORT4 0x16BA08
10915−#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
10916−#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
10917−#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
10918−#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
10919−#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
10920−#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
10921−#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
10922− _MG_PLL_LF_PORT2)
10923−
10924−#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
10925−#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
10926−#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
10927−#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
10928−#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
10929−#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
10930−#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
10931−#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
10932−#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
10933−#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
10934−#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
10935− _MG_PLL_FRAC_LOCK_PORT1, \
10936− _MG_PLL_FRAC_LOCK_PORT2)
10937−
10938−#define _MG_PLL_SSC_PORT1 0x168A10
10939−#define _MG_PLL_SSC_PORT2 0x169A10
10940−#define _MG_PLL_SSC_PORT3 0x16AA10
10941−#define _MG_PLL_SSC_PORT4 0x16BA10
10942−#define MG_PLL_SSC_EN (1 << 28)
10943−#define MG_PLL_SSC_TYPE(x) ((x) << 26)
10944−#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
10945−#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
10946−#define MG_PLL_SSC_FLLEN (1 << 9)
10947−#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
10948−#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
10949− _MG_PLL_SSC_PORT2)
10950−
10951−#define _MG_PLL_BIAS_PORT1 0x168A14
10952−#define _MG_PLL_BIAS_PORT2 0x169A14
10953−#define _MG_PLL_BIAS_PORT3 0x16AA14
10954−#define _MG_PLL_BIAS_PORT4 0x16BA14
10955−#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
10956−#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
10957−#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
10958−#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
10959−#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
10960−#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
10961−#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
10962−#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
10963−#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
10964−#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
10965−#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
10966−#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
10967−#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
10968−#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
10969− _MG_PLL_BIAS_PORT2)
10970−
10971−#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
10972−#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
10973−#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
10974−#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
10975−#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
10976−#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
10977−#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
10978−#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
10979−#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
10980−#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
10981− _MG_PLL_TDC_COLDST_BIAS_PORT1, \
10982− _MG_PLL_TDC_COLDST_BIAS_PORT2)
10983−
109847933 #define _ICL_DPLL0_CFGCR0 0x164000
109857934 #define _ICL_DPLL1_CFGCR0 0x164080
109867935 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
@@ -12598,39 +9547,6 @@ enum skl_power_gate { · 1611 unmodified lines
125989547 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
125999548 #define READ_DATA_VALID(n) (1 << (n))
126009549
12601−/* MOCS (Memory Object Control State) registers */
12602−#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
12603−#define GEN9_LNCFCMOCS_REG_COUNT 32
12604−
12605−#define __GEN9_RCS0_MOCS0 0xc800
12606−#define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
12607−#define __GEN9_VCS0_MOCS0 0xc900
12608−#define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
12609−#define __GEN9_VCS1_MOCS0 0xca00
12610−#define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
12611−#define __GEN9_VECS0_MOCS0 0xcb00
12612−#define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
12613−#define __GEN9_BCS0_MOCS0 0xcc00
12614−#define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
12615−#define __GEN11_VCS2_MOCS0 0x10000
12616−#define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
12617−
12618−#define GEN9_SCRATCH_LNCF1 _MMIO(0xb008)
12619−#define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
12620−
12621−#define GEN9_SCRATCH1 _MMIO(0xb11c)
12622−#define EVICTION_PERF_FIX_ENABLE REG_BIT(8)
12623−
12624−#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
12625−#define PMFLUSHDONE_LNICRSDROP (1 << 20)
12626−#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
12627−#define PMFLUSHDONE_LNEBLK (1 << 22)
12628−
12629−#define XEHP_L3NODEARBCFG _MMIO(0xb0b4)
12630−#define XEHP_LNESPARE REG_BIT(19)
12631−
12632−#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
12633−
126349550 #define GEN12_GSMBASE _MMIO(0x108100)
126359551 #define GEN12_DSMBASE _MMIO(0x1080C0)
126369552
@@ -12639,17 +9555,6 @@ enum skl_power_gate { · 2 unmodified lines
126399555 #define SGGI_DIS REG_BIT(15)
126409556 #define SGR_DIS REG_BIT(13)
126419557
12642−/* gamt regs */
12643−#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
12644−#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
12645−#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
12646−#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
12647−#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
12648−
12649−#define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
12650−#define MMCD_PCLA (1 << 31)
12651−#define MMCD_HOTSPOT_EN (1 << 27)
12652−
126539558 #define _ICL_PHY_MISC_A 0x64C00
126549559 #define _ICL_PHY_MISC_B 0x64C04
126559560 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
@@ -12993,6 +9898,14 @@ enum skl_power_gate { · 337 unmodified lines
129939898 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
129949899 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
129959900
9901+#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
9902+#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
9903+#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
9904+#define SPI_STATIC_REGIONS _MMIO(0x102090)
9905+#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
9906+#define OROM_OFFSET _MMIO(0x1020c0)
9907+#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
9908+
129969909 /* This register controls the Display State Buffer (DSB) engines. */
129979910 #define _DSBSL_INSTANCE_BASE 0x70B00
129989911 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
@@ -13015,7 +9928,4 @@ enum skl_power_gate { · 16 unmodified lines
130159928 #define CLKGATE_DIS_MISC _MMIO(0x46534)
130169929 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
130179930
13018−#define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731C)
13019−#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
13020−
130219931 #endif /* _I915_REG_H_ */
drivers/gpu/drm/i915/i915_reg_defs.h+101−0
@@ -0,0 +1,101 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2022 Intel Corporation
4+ */
5+
6+#ifndef __I915_REG_DEFS__
7+#define __I915_REG_DEFS__
8+
9+#include <linux/bitfield.h>
10+#include <linux/bits.h>
11+
12+/**
13+ * REG_BIT() - Prepare a u32 bit value
14+ * @__n: 0-based bit number
15+ *
16+ * Local wrapper for BIT() to force u32, with compile time checks.
17+ *
18+ * @return: Value with bit @__n set.
19+ */
20+#define REG_BIT(__n) \
21+ ((u32)(BIT(__n) + \
22+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
23+ ((__n) < 0 || (__n) > 31))))
24+
25+/**
26+ * REG_GENMASK() - Prepare a continuous u32 bitmask
27+ * @__high: 0-based high bit
28+ * @__low: 0-based low bit
29+ *
30+ * Local wrapper for GENMASK() to force u32, with compile time checks.
31+ *
32+ * @return: Continuous bitmask from @__high to @__low, inclusive.
33+ */
34+#define REG_GENMASK(__high, __low) \
35+ ((u32)(GENMASK(__high, __low) + \
36+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
37+ __is_constexpr(__low) && \
38+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
39+
40+/*
41+ * Local integer constant expression version of is_power_of_2().
42+ */
43+#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
44+
45+/**
46+ * REG_FIELD_PREP() - Prepare a u32 bitfield value
47+ * @__mask: shifted mask defining the field's length and position
48+ * @__val: value to put in the field
49+ *
50+ * Local copy of FIELD_PREP() to generate an integer constant expression, force
51+ * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
52+ *
53+ * @return: @__val masked and shifted into the field defined by @__mask.
54+ */
55+#define REG_FIELD_PREP(__mask, __val) \
56+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
57+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
58+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
59+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
60+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
61+
62+/**
63+ * REG_FIELD_GET() - Extract a u32 bitfield value
64+ * @__mask: shifted mask defining the field's length and position
65+ * @__val: value to extract the bitfield value from
66+ *
67+ * Local wrapper for FIELD_GET() to force u32 and for consistency with
68+ * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
69+ *
70+ * @return: Masked and shifted value of the field defined by @__mask in @__val.
71+ */
72+#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
73+
74+typedef struct {
75+ u32 reg;
76+} i915_reg_t;
77+
78+#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
79+
80+#define INVALID_MMIO_REG _MMIO(0)
81+
82+static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
83+{
84+ return reg.reg;
85+}
86+
87+static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
88+{
89+ return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
90+}
91+
92+static inline bool i915_mmio_reg_valid(i915_reg_t reg)
93+{
94+ return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
95+}
96+
97+#define VLV_DISPLAY_BASE 0x180000
98+
99+#define GEN12_SFC_DONE_MAX 4
100+
101+#endif /* __I915_REG_DEFS__ */
drivers/gpu/drm/i915/i915_request.c+1−0
@@ -36,6 +36,7 @@ · 35 unmodified lines
3636 #include "gt/intel_context.h"
3737 #include "gt/intel_engine.h"
3838 #include "gt/intel_engine_heartbeat.h"
39+#include "gt/intel_engine_regs.h"
3940 #include "gt/intel_gpu_commands.h"
4041 #include "gt/intel_reset.h"
4142 #include "gt/intel_ring.h"
drivers/gpu/drm/i915/i915_suspend.c+1−0
@@ -32,6 +32,7 @@ · 31 unmodified lines
3232 #include "i915_drv.h"
3333 #include "i915_reg.h"
3434 #include "i915_suspend.h"
35+#include "intel_pci_config.h"
3536
3637 static void intel_save_swf(struct drm_i915_private *dev_priv)
3738 {
drivers/gpu/drm/i915/i915_sysfs.c+1−0
@@ -30,6 +30,7 @@ · 29 unmodified lines
3030 #include <linux/stat.h>
3131 #include <linux/sysfs.h>
3232
33+#include "gt/intel_gt_regs.h"
3334 #include "gt/intel_rc6.h"
3435 #include "gt/intel_rps.h"
3536 #include "gt/sysfs_engines.h"
drivers/gpu/drm/i915/i915_utils.h+0−15
@@ -37,21 +37,6 @@ struct timer_list; · 36 unmodified lines
3737
3838 #define FDO_BUG_URL "https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs"
3939
40−#undef WARN_ON
41−/* Many gcc seem to no see through this and fall over :( */
42−#if 0
43−#define WARN_ON(x) ({ \
44− bool __i915_warn_cond = (x); \
45− if (__builtin_constant_p(__i915_warn_cond)) \
46− BUILD_BUG_ON(__i915_warn_cond); \
47− WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
48−#else
49−#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
50−#endif
51−
52−#undef WARN_ON_ONCE
53−#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
54−
5540 #define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
5641 __stringify(x), (long)(x))
5742
drivers/gpu/drm/i915/i915_vma.c+2−1
@@ -26,14 +26,15 @@ · 25 unmodified lines
2626 #include <drm/drm_gem.h>
2727
2828 #include "display/intel_frontbuffer.h"
29−
3029 #include "gem/i915_gem_lmem.h"
30+#include "gem/i915_gem_tiling.h"
3131 #include "gt/intel_engine.h"
3232 #include "gt/intel_engine_heartbeat.h"
3333 #include "gt/intel_gt.h"
3434 #include "gt/intel_gt_requests.h"
3535
3636 #include "i915_drv.h"
37+#include "i915_gem_evict.h"
3738 #include "i915_sw_fence_work.h"
3839 #include "i915_trace.h"
3940 #include "i915_vma.h"
drivers/gpu/drm/i915/intel_device_info.c+11−2
@@ -114,7 +114,7 @@ void intel_device_info_print_static(const struct intel_device_info *info, · 113 unmodified lines
114114 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
115115 #undef PRINT_FLAG
116116
117−#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
117+#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name))
118118 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
119119 #undef PRINT_FLAG
120120 }
@@ -170,6 +170,10 @@ static const u16 subplatform_portf_ids[] = { · 49 unmodified lines
170170 INTEL_ICL_PORT_F_IDS(0),
171171 };
172172
173+static const u16 subplatform_n_ids[] = {
174+ INTEL_ADLN_IDS(0),
175+};
176+
173177 static const u16 subplatform_rpls_ids[] = {
174178 INTEL_RPLS_IDS(0),
175179 };
@@ -210,6 +214,9 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915) · 34 unmodified lines
210214 } else if (find_devid(devid, subplatform_portf_ids,
211215 ARRAY_SIZE(subplatform_portf_ids))) {
212216 mask = BIT(INTEL_SUBPLATFORM_PORTF);
217+ } else if (find_devid(devid, subplatform_n_ids,
218+ ARRAY_SIZE(subplatform_n_ids))) {
219+ mask = BIT(INTEL_SUBPLATFORM_N);
213220 } else if (find_devid(devid, subplatform_rpls_ids,
214221 ARRAY_SIZE(subplatform_rpls_ids))) {
215222 mask = BIT(INTEL_SUBPLATFORM_RPL_S);
@@ -328,6 +335,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) · 112 unmodified lines
328335 "Display fused off, disabling\n");
329336 info->display.pipe_mask = 0;
330337 info->display.cpu_transcoder_mask = 0;
338+ info->display.fbc_mask = 0;
331339 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
332340 drm_info(&dev_priv->drm, "PipeC fused off\n");
333341 info->display.pipe_mask &= ~BIT(PIPE_C);
@@ -339,6 +347,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) · 5 unmodified lines
339347 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
340348 info->display.pipe_mask &= ~BIT(PIPE_A);
341349 info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
350+ info->display.fbc_mask &= ~BIT(INTEL_FBC_A);
342351 }
343352 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
344353 info->display.pipe_mask &= ~BIT(PIPE_B);
@@ -359,7 +368,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) · 14 unmodified lines
359368 info->display.has_hdcp = 0;
360369
361370 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
362− info->display.has_fbc = 0;
371+ info->display.fbc_mask = 0;
363372
364373 if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
365374 info->display.has_dmc = 0;
drivers/gpu/drm/i915/intel_device_info.h+4−1
@@ -113,6 +113,9 @@ enum intel_platform { · 112 unmodified lines
113113 /* ADL-S */
114114 #define INTEL_SUBPLATFORM_RPL_S 0
115115
116+/* ADL-P */
117+#define INTEL_SUBPLATFORM_N 0
118+
116119 enum intel_ppgtt_type {
117120 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
118121 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
@@ -156,7 +159,6 @@ enum intel_ppgtt_type { · 37 unmodified lines
156159 func(has_dp_mst); \
157160 func(has_dsb); \
158161 func(has_dsc); \
159− func(has_fbc); \
160162 func(has_fpga_dbg); \
161163 func(has_gmch); \
162164 func(has_hdcp); \
@@ -206,6 +208,7 @@ struct intel_device_info { · 43 unmodified lines
206208
207209 u8 pipe_mask;
208210 u8 cpu_transcoder_mask;
211+ u8 fbc_mask;
209212 u8 abox_mask;
210213
211214 #define DEFINE_FLAG(name) u8 name:1
drivers/gpu/drm/i915/intel_dram.c+3−4
@@ -4,6 +4,7 @@ · 3 unmodified lines
44 */
55
66 #include "i915_drv.h"
7+#include "i915_reg.h"
78 #include "intel_dram.h"
89 #include "intel_pcode.h"
910
@@ -389,10 +390,8 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv) · 379 unmodified lines
389390 u32 val = 0;
390391 int ret;
391392
392− ret = sandybridge_pcode_read(dev_priv,
393− ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
394− ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
395− &val, NULL);
393+ ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
394+ ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
396395 if (ret)
397396 return ret;
398397
drivers/gpu/drm/i915/intel_pci_config.h+85−0
@@ -0,0 +1,85 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2022 Intel Corporation
4+ */
5+
6+#ifndef __INTEL_PCI_CONFIG_H__
7+#define __INTEL_PCI_CONFIG_H__
8+
9+/* BSM in include/drm/i915_drm.h */
10+
11+#define MCHBAR_I915 0x44
12+#define MCHBAR_I965 0x48
13+#define MCHBAR_SIZE (4 * 4096)
14+
15+#define DEVEN 0x54
16+#define DEVEN_MCHBAR_EN (1 << 28)
17+
18+#define HPLLCC 0xc0 /* 85x only */
19+#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
20+#define GC_CLOCK_133_200 (0 << 0)
21+#define GC_CLOCK_100_200 (1 << 0)
22+#define GC_CLOCK_100_133 (2 << 0)
23+#define GC_CLOCK_133_266 (3 << 0)
24+#define GC_CLOCK_133_200_2 (4 << 0)
25+#define GC_CLOCK_133_266_2 (5 << 0)
26+#define GC_CLOCK_166_266 (6 << 0)
27+#define GC_CLOCK_166_250 (7 << 0)
28+
29+#define I915_GDRST 0xc0
30+#define GRDOM_FULL (0 << 2)
31+#define GRDOM_RENDER (1 << 2)
32+#define GRDOM_MEDIA (3 << 2)
33+#define GRDOM_MASK (3 << 2)
34+#define GRDOM_RESET_STATUS (1 << 1)
35+#define GRDOM_RESET_ENABLE (1 << 0)
36+
37+/* BSpec only has register offset, PCI device and bit found empirically */
38+#define I830_CLOCK_GATE 0xc8 /* device 0 */
39+#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
40+
41+#define GCDGMBUS 0xcc
42+
43+#define GCFGC2 0xda
44+#define GCFGC 0xf0 /* 915+ only */
45+#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
46+#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
47+#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
48+#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
49+#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
50+#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
51+#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
52+#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
53+#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
54+#define GC_DISPLAY_CLOCK_MASK (7 << 4)
55+#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
56+#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
57+#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
58+#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
59+#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
60+#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
61+#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
62+#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
63+#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
64+#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
65+#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
66+#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
67+#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
68+#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
69+#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
70+#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
71+#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
72+#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
73+#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
74+
75+#define ASLE 0xe4
76+#define ASLS 0xfc
77+
78+#define SWSCI 0xe8
79+#define SWSCI_SCISEL (1 << 15)
80+#define SWSCI_GSSCIE (1 << 0)
81+
82+/* legacy/combination backlight modes, also called LBB */
83+#define LBPC 0xf4
84+
85+#endif /* __INTEL_PCI_CONFIG_H__ */
drivers/gpu/drm/i915/intel_pcode.c+12−20
@@ -4,6 +4,7 @@ · 3 unmodified lines
44 */
55
66 #include "i915_drv.h"
7+#include "i915_reg.h"
78 #include "intel_pcode.h"
89
910 static int gen6_check_mailbox_status(u32 mbox)
@@ -51,11 +52,10 @@ static int gen7_check_mailbox_status(u32 mbox) · 41 unmodified lines
5152 }
5253 }
5354
54−static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
55− u32 mbox, u32 *val, u32 *val1,
56− int fast_timeout_us,
57− int slow_timeout_ms,
58− bool is_read)
55+static int __snb_pcode_rw(struct drm_i915_private *i915, u32 mbox,
56+ u32 *val, u32 *val1,
57+ int fast_timeout_us, int slow_timeout_ms,
58+ bool is_read)
5959 {
6060 struct intel_uncore *uncore = &i915->uncore;
6161
@@ -94,15 +94,12 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915, · 32 unmodified lines
9494 return gen6_check_mailbox_status(mbox);
9595 }
9696
97−int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
98− u32 *val, u32 *val1)
97+int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
9998 {
10099 int err;
101100
102101 mutex_lock(&i915->sb_lock);
103− err = __sandybridge_pcode_rw(i915, mbox, val, val1,
104− 500, 20,
105− true);
102+ err = __snb_pcode_rw(i915, mbox, val, val1, 500, 20, true);
106103 mutex_unlock(&i915->sb_lock);
107104
108105 if (err) {
@@ -114,17 +111,14 @@ int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox, · 5 unmodified lines
114111 return err;
115112 }
116113
117−int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
118− u32 mbox, u32 val,
119− int fast_timeout_us,
120− int slow_timeout_ms)
114+int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
115+ int fast_timeout_us, int slow_timeout_ms)
121116 {
122117 int err;
123118
124119 mutex_lock(&i915->sb_lock);
125− err = __sandybridge_pcode_rw(i915, mbox, &val, NULL,
126− fast_timeout_us, slow_timeout_ms,
127− false);
120+ err = __snb_pcode_rw(i915, mbox, &val, NULL,
121+ fast_timeout_us, slow_timeout_ms, false);
128122 mutex_unlock(&i915->sb_lock);
129123
130124 if (err) {
@@ -140,9 +134,7 @@ static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox, · 9 unmodified lines
140134 u32 request, u32 reply_mask, u32 reply,
141135 u32 *status)
142136 {
143− *status = __sandybridge_pcode_rw(i915, mbox, &request, NULL,
144− 500, 0,
145− true);
137+ *status = __snb_pcode_rw(i915, mbox, &request, NULL, 500, 0, true);
146138
147139 return *status || ((request & reply_mask) == reply);
148140 }
drivers/gpu/drm/i915/intel_pcode.h+5−7
@@ -10,13 +10,11 @@ · 9 unmodified lines
1010
1111 struct drm_i915_private;
1212
13−int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
14− u32 *val, u32 *val1);
15−int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
16− u32 val, int fast_timeout_us,
17− int slow_timeout_ms);
18−#define sandybridge_pcode_write(i915, mbox, val) \
19− sandybridge_pcode_write_timeout(i915, mbox, val, 500, 0)
13+int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1);
14+int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
15+ int fast_timeout_us, int slow_timeout_ms);
16+#define snb_pcode_write(i915, mbox, val) \
17+ snb_pcode_write_timeout(i915, mbox, val, 500, 0)
2018
2119 int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
2220 u32 reply_mask, u32 reply, int timeout_base_ms);
drivers/gpu/drm/i915/intel_pm.c+256−141
@@ -43,6 +43,8 @@ · 42 unmodified lines
4343 #include "display/intel_sprite.h"
4444 #include "display/skl_universal_plane.h"
4545
46+#include "gt/intel_engine_regs.h"
47+#include "gt/intel_gt_regs.h"
4648 #include "gt/intel_llc.h"
4749
4850 #include "i915_drv.h"
@@ -78,8 +80,6 @@ struct intel_wm_config { · 29 unmodified lines
7880
7981 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
8082 {
81− enum pipe pipe;
82−
8383 if (HAS_LLC(dev_priv)) {
8484 /*
8585 * WaCompressedResourceDisplayNewHashMode:skl,kbl
@@ -93,16 +93,6 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) · 7 unmodified lines
9393 SKL_DE_COMPRESSED_HASH_MODE);
9494 }
9595
96− for_each_pipe(dev_priv, pipe) {
97− /*
98− * "Plane N strech max must be programmed to 11b (x1)
99− * when Async flips are enabled on that plane."
100− */
101− if (!IS_GEMINILAKE(dev_priv) && intel_vtd_active(dev_priv))
102− intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
103− SKL_PLANE1_STRETCH_MAX_MASK, SKL_PLANE1_STRETCH_MAX_X1);
104− }
105−
10696 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
10797 intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
10898 intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
@@ -160,8 +150,9 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) · 51 unmodified lines
160150 * WaFbcHighMemBwCorruptionAvoidance:bxt
161151 * Display WA #0883: bxt
162152 */
163− intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
164− DPFC_DISABLE_DUMMY0);
153+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
154+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
155+ DPFC_DISABLE_DUMMY0);
165156 }
166157
167158 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -876,7 +867,7 @@ static bool intel_crtc_active(struct intel_crtc *crtc) · 708 unmodified lines
876867 * crtc->state->active once we have proper CRTC states wired up
877868 * for atomic.
878869 */
879− return crtc->active && crtc->base.primary->state->fb &&
870+ return crtc && crtc->active && crtc->base.primary->state->fb &&
880871 crtc->config->hw.adjusted_mode.crtc_clock;
881872 }
882873
@@ -915,15 +906,13 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv) · 32 unmodified lines
915906
916907 crtc = single_enabled_crtc(dev_priv);
917908 if (crtc) {
918− const struct drm_display_mode *pipe_mode =
919− &crtc->config->hw.pipe_mode;
920909 const struct drm_framebuffer *fb =
921910 crtc->base.primary->state->fb;
911+ int pixel_rate = crtc->config->pixel_rate;
922912 int cpp = fb->format->cpp[0];
923− int clock = pipe_mode->crtc_clock;
924913
925914 /* Display SR */
926− wm = intel_calculate_wm(clock, &pnv_display_wm,
915+ wm = intel_calculate_wm(pixel_rate, &pnv_display_wm,
927916 pnv_display_wm.fifo_size,
928917 cpp, latency->display_sr);
929918 reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
@@ -933,7 +922,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv) · 3 unmodified lines
933922 drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
934923
935924 /* cursor SR */
936− wm = intel_calculate_wm(clock, &pnv_cursor_wm,
925+ wm = intel_calculate_wm(pixel_rate, &pnv_cursor_wm,
937926 pnv_display_wm.fifo_size,
938927 4, latency->cursor_sr);
939928 reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
@@ -942,7 +931,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv) · 2 unmodified lines
942931 intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
943932
944933 /* Display HPLL off SR */
945− wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
934+ wm = intel_calculate_wm(pixel_rate, &pnv_display_hplloff_wm,
946935 pnv_display_hplloff_wm.fifo_size,
947936 cpp, latency->display_hpll_disable);
948937 reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
@@ -951,7 +940,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv) · 2 unmodified lines
951940 intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
952941
953942 /* cursor HPLL off SR */
954− wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
943+ wm = intel_calculate_wm(pixel_rate, &pnv_cursor_hplloff_wm,
955944 pnv_display_hplloff_wm.fifo_size,
956945 4, latency->cursor_hpll_disable);
957946 reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
@@ -1154,7 +1143,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state, · 196 unmodified lines
11541143 const struct drm_display_mode *pipe_mode =
11551144 &crtc_state->hw.pipe_mode;
11561145 unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
1157− unsigned int clock, htotal, cpp, width, wm;
1146+ unsigned int pixel_rate, htotal, cpp, width, wm;
11581147
11591148 if (latency == 0)
11601149 return USHRT_MAX;
@@ -1175,21 +1164,20 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state, · 14 unmodified lines
11751164 level != G4X_WM_LEVEL_NORMAL)
11761165 cpp = max(cpp, 4u);
11771166
1178− clock = pipe_mode->crtc_clock;
1167+ pixel_rate = crtc_state->pixel_rate;
11791168 htotal = pipe_mode->crtc_htotal;
1180−
1181− width = drm_rect_width(&plane_state->uapi.dst);
1169+ width = drm_rect_width(&plane_state->uapi.src) >> 16;
11821170
11831171 if (plane->id == PLANE_CURSOR) {
1184− wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1172+ wm = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
11851173 } else if (plane->id == PLANE_PRIMARY &&
11861174 level == G4X_WM_LEVEL_NORMAL) {
1187− wm = intel_wm_method1(clock, cpp, latency);
1175+ wm = intel_wm_method1(pixel_rate, cpp, latency);
11881176 } else {
11891177 unsigned int small, large;
11901178
1191− small = intel_wm_method1(clock, cpp, latency);
1192− large = intel_wm_method2(clock, htotal, width, cpp, latency);
1179+ small = intel_wm_method1(pixel_rate, cpp, latency);
1180+ large = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
11931181
11941182 wm = min(small, large);
11951183 }
@@ -1674,7 +1662,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state, · 478 unmodified lines
16741662 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16751663 const struct drm_display_mode *pipe_mode =
16761664 &crtc_state->hw.pipe_mode;
1677− unsigned int clock, htotal, cpp, width, wm;
1665+ unsigned int pixel_rate, htotal, cpp, width, wm;
16781666
16791667 if (dev_priv->wm.pri_latency[level] == 0)
16801668 return USHRT_MAX;
@@ -1683,9 +1671,9 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state, · 2 unmodified lines
16831671 return 0;
16841672
16851673 cpp = plane_state->hw.fb->format->cpp[0];
1686− clock = pipe_mode->crtc_clock;
1674+ pixel_rate = crtc_state->pixel_rate;
16871675 htotal = pipe_mode->crtc_htotal;
1688− width = crtc_state->pipe_src_w;
1676+ width = drm_rect_width(&plane_state->uapi.src) >> 16;
16891677
16901678 if (plane->id == PLANE_CURSOR) {
16911679 /*
@@ -1696,7 +1684,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state, · 4 unmodified lines
16961684 */
16971685 wm = 63;
16981686 } else {
1699− wm = vlv_wm_method2(clock, htotal, width, cpp,
1687+ wm = vlv_wm_method2(pixel_rate, htotal, width, cpp,
17001688 dev_priv->wm.pri_latency[level] * 10);
17011689 }
17021690
@@ -2277,14 +2265,14 @@ static void i965_update_wm(struct drm_i915_private *dev_priv) · 574 unmodified lines
22772265 &crtc->config->hw.pipe_mode;
22782266 const struct drm_framebuffer *fb =
22792267 crtc->base.primary->state->fb;
2280− int clock = pipe_mode->crtc_clock;
2268+ int pixel_rate = crtc->config->pixel_rate;
22812269 int htotal = pipe_mode->crtc_htotal;
2282− int hdisplay = crtc->config->pipe_src_w;
2270+ int width = drm_rect_width(&crtc->base.primary->state->src) >> 16;
22832271 int cpp = fb->format->cpp[0];
22842272 int entries;
22852273
2286− entries = intel_wm_method2(clock, htotal,
2287− hdisplay, cpp, sr_latency_ns / 100);
2274+ entries = intel_wm_method2(pixel_rate, htotal,
2275+ width, cpp, sr_latency_ns / 100);
22882276 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
22892277 srwm = I965_FIFO_SIZE - entries;
22902278 if (srwm < 0)
@@ -2294,7 +2282,7 @@ static void i965_update_wm(struct drm_i915_private *dev_priv) · 3 unmodified lines
22942282 "self-refresh entries: %d, wm: %d\n",
22952283 entries, srwm);
22962284
2297− entries = intel_wm_method2(clock, htotal,
2285+ entries = intel_wm_method2(pixel_rate, htotal,
22982286 crtc->base.cursor->state->crtc_w, 4,
22992287 sr_latency_ns / 100);
23002288 entries = DIV_ROUND_UP(entries,
@@ -2358,7 +2346,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv) · 57 unmodified lines
23582346 int cwm, srwm = 1;
23592347 int fifo_size;
23602348 int planea_wm, planeb_wm;
2361− struct intel_crtc *crtc, *enabled = NULL;
2349+ struct intel_crtc *crtc;
23622350
23632351 if (IS_I945GM(dev_priv))
23642352 wm_info = &i945_wm_info;
@@ -2373,8 +2361,6 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv) · 8 unmodified lines
23732361 fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
23742362 crtc = intel_crtc_for_plane(dev_priv, PLANE_A);
23752363 if (intel_crtc_active(crtc)) {
2376− const struct drm_display_mode *pipe_mode =
2377− &crtc->config->hw.pipe_mode;
23782364 const struct drm_framebuffer *fb =
23792365 crtc->base.primary->state->fb;
23802366 int cpp;
@@ -2384,10 +2370,9 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv) · 3 unmodified lines
23842370 else
23852371 cpp = fb->format->cpp[0];
23862372
2387− planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
2373+ planea_wm = intel_calculate_wm(crtc->config->pixel_rate,
23882374 wm_info, fifo_size, cpp,
23892375 pessimal_latency_ns);
2390− enabled = crtc;
23912376 } else {
23922377 planea_wm = fifo_size - wm_info->guard_size;
23932378 if (planea_wm > (long)wm_info->max_wm)
@@ -2403,8 +2388,6 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv) · 9 unmodified lines
24032388 fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
24042389 crtc = intel_crtc_for_plane(dev_priv, PLANE_B);
24052390 if (intel_crtc_active(crtc)) {
2406− const struct drm_display_mode *pipe_mode =
2407− &crtc->config->hw.pipe_mode;
24082391 const struct drm_framebuffer *fb =
24092392 crtc->base.primary->state->fb;
24102393 int cpp;
@@ -2414,13 +2397,9 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv) · 3 unmodified lines
24142397 else
24152398 cpp = fb->format->cpp[0];
24162399
2417− planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
2400+ planeb_wm = intel_calculate_wm(crtc->config->pixel_rate,
24182401 wm_info, fifo_size, cpp,
24192402 pessimal_latency_ns);
2420− if (enabled == NULL)
2421− enabled = crtc;
2422− else
2423− enabled = NULL;
24242403 } else {
24252404 planeb_wm = fifo_size - wm_info->guard_size;
24262405 if (planeb_wm > (long)wm_info->max_wm)
@@ -2430,14 +2409,15 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv) · 3 unmodified lines
24302409 drm_dbg_kms(&dev_priv->drm,
24312410 "FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
24322411
2433− if (IS_I915GM(dev_priv) && enabled) {
2412+ crtc = single_enabled_crtc(dev_priv);
2413+ if (IS_I915GM(dev_priv) && crtc) {
24342414 struct drm_i915_gem_object *obj;
24352415
2436− obj = intel_fb_obj(enabled->base.primary->state->fb);
2416+ obj = intel_fb_obj(crtc->base.primary->state->fb);
24372417
24382418 /* self-refresh seems busted with untiled */
24392419 if (!i915_gem_object_is_tiled(obj))
2440− enabled = NULL;
2420+ crtc = NULL;
24412421 }
24422422
24432423 /*
@@ -2449,16 +2429,16 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv) · 5 unmodified lines
24492429 intel_set_memory_cxsr(dev_priv, false);
24502430
24512431 /* Calc sr entries for one plane configs */
2452− if (HAS_FW_BLC(dev_priv) && enabled) {
2432+ if (HAS_FW_BLC(dev_priv) && crtc) {
24532433 /* self-refresh has much higher latency */
24542434 static const int sr_latency_ns = 6000;
24552435 const struct drm_display_mode *pipe_mode =
2456− &enabled->config->hw.pipe_mode;
2436+ &crtc->config->hw.pipe_mode;
24572437 const struct drm_framebuffer *fb =
2458− enabled->base.primary->state->fb;
2459− int clock = pipe_mode->crtc_clock;
2438+ crtc->base.primary->state->fb;
2439+ int pixel_rate = crtc->config->pixel_rate;
24602440 int htotal = pipe_mode->crtc_htotal;
2461− int hdisplay = enabled->config->pipe_src_w;
2441+ int width = drm_rect_width(&crtc->base.primary->state->src) >> 16;
24622442 int cpp;
24632443 int entries;
24642444
@@ -2467,7 +2447,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv) · 2 unmodified lines
24672447 else
24682448 cpp = fb->format->cpp[0];
24692449
2470− entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2450+ entries = intel_wm_method2(pixel_rate, htotal, width, cpp,
24712451 sr_latency_ns / 100);
24722452 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
24732453 drm_dbg_kms(&dev_priv->drm,
@@ -2497,14 +2477,13 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv) · 23 unmodified lines
24972477 intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
24982478 intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
24992479
2500− if (enabled)
2480+ if (crtc)
25012481 intel_set_memory_cxsr(dev_priv, true);
25022482 }
25032483
25042484 static void i845_update_wm(struct drm_i915_private *dev_priv)
25052485 {
25062486 struct intel_crtc *crtc;
2507− const struct drm_display_mode *pipe_mode;
25082487 u32 fwater_lo;
25092488 int planea_wm;
25102489
@@ -2512,8 +2491,7 @@ static void i845_update_wm(struct drm_i915_private *dev_priv) · 1 unmodified line
25122491 if (crtc == NULL)
25132492 return;
25142493
2515− pipe_mode = &crtc->config->hw.pipe_mode;
2516− planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
2494+ planea_wm = intel_calculate_wm(crtc->config->pixel_rate,
25172495 &i845_wm_info,
25182496 i845_get_fifo_size(dev_priv, PLANE_A),
25192497 4, pessimal_latency_ns);
@@ -2604,7 +2582,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state, · 84 unmodified lines
26042582
26052583 method2 = ilk_wm_method2(crtc_state->pixel_rate,
26062584 crtc_state->hw.pipe_mode.crtc_htotal,
2607− drm_rect_width(&plane_state->uapi.dst),
2585+ drm_rect_width(&plane_state->uapi.src) >> 16,
26082586 cpp, mem_value);
26092587
26102588 return min(method1, method2);
@@ -2632,7 +2610,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state, · 21 unmodified lines
26322610 method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
26332611 method2 = ilk_wm_method2(crtc_state->pixel_rate,
26342612 crtc_state->hw.pipe_mode.crtc_htotal,
2635− drm_rect_width(&plane_state->uapi.dst),
2613+ drm_rect_width(&plane_state->uapi.src) >> 16,
26362614 cpp, mem_value);
26372615 return min(method1, method2);
26382616 }
@@ -2657,7 +2635,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state, · 18 unmodified lines
26572635
26582636 return ilk_wm_method2(crtc_state->pixel_rate,
26592637 crtc_state->hw.pipe_mode.crtc_htotal,
2660− drm_rect_width(&plane_state->uapi.dst),
2638+ drm_rect_width(&plane_state->uapi.src) >> 16,
26612639 cpp, mem_value);
26622640 }
26632641
@@ -2673,7 +2651,7 @@ static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state, · 9 unmodified lines
26732651
26742652 cpp = plane_state->hw.fb->format->cpp[0];
26752653
2676− return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.dst),
2654+ return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.src) >> 16,
26772655 cpp);
26782656 }
26792657
@@ -2888,9 +2866,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, · 208 unmodified lines
28882866
28892867 /* read the first set of memory latencies[0:3] */
28902868 val = 0; /* data0 to be programmed to 0 for first set */
2891− ret = sandybridge_pcode_read(dev_priv,
2892− GEN9_PCODE_READ_MEM_LATENCY,
2893− &val, NULL);
2869+ ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
2870+ &val, NULL);
28942871
28952872 if (ret) {
28962873 drm_err(&dev_priv->drm,
@@ -2908,9 +2885,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, · 11 unmodified lines
29082885
29092886 /* read the second set of memory latencies[4:7] */
29102887 val = 1; /* data0 to be programmed to 1 for second set */
2911− ret = sandybridge_pcode_read(dev_priv,
2912− GEN9_PCODE_READ_MEM_LATENCY,
2913− &val, NULL);
2888+ ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
2889+ &val, NULL);
29142890 if (ret) {
29152891 drm_err(&dev_priv->drm,
29162892 "SKL Mailbox read error = %d\n", ret);
@@ -3700,9 +3676,9 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv) · 783 unmodified lines
37003676 u32 val = 0;
37013677 int ret;
37023678
3703− ret = sandybridge_pcode_read(dev_priv,
3704− GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
3705− &val, NULL);
3679+ ret = snb_pcode_read(dev_priv,
3680+ GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
3681+ &val, NULL);
37063682 if (!ret) {
37073683 dev_priv->sagv_block_time_us = val;
37083684 return;
@@ -3749,8 +3725,8 @@ intel_enable_sagv(struct drm_i915_private *dev_priv) · 40 unmodified lines
37493725 return 0;
37503726
37513727 drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
3752− ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3753− GEN9_SAGV_ENABLE);
3728+ ret = snb_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3729+ GEN9_SAGV_ENABLE);
37543730
37553731 /* We don't need to wait for SAGV when enabling */
37563732
@@ -4252,7 +4228,9 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state, · 495 unmodified lines
42524228 u64 modifier, unsigned int rotation,
42534229 u32 plane_pixel_rate, struct skl_wm_params *wp,
42544230 int color_plane);
4231+
42554232 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
4233+ struct intel_plane *plane,
42564234 int level,
42574235 unsigned int latency,
42584236 const struct skl_wm_params *wp,
@@ -4263,6 +4241,7 @@ static unsigned int · 4 unmodified lines
42634241 skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
42644242 int num_active)
42654243 {
4244+ struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->cursor);
42664245 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
42674246 int level, max_level = ilk_wm_max_level(dev_priv);
42684247 struct skl_wm_level wm = {};
@@ -4279,7 +4258,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state, · 10 unmodified lines
42794258 for (level = 0; level <= max_level; level++) {
42804259 unsigned int latency = dev_priv->wm.skl_latency[level];
42814260
4282− skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
4261+ skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);
42834262 if (wm.min_ddb_alloc == U16_MAX)
42844263 break;
42854264
@@ -4292,11 +4271,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state, · 6 unmodified lines
42924271 static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
42934272 struct skl_ddb_entry *entry, u32 reg)
42944273 {
4295− entry->start = reg & DDB_ENTRY_MASK;
4296− entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
4297−
4274+ entry->start = REG_FIELD_GET(PLANE_BUF_START_MASK, reg);
4275+ entry->end = REG_FIELD_GET(PLANE_BUF_END_MASK, reg);
42984276 if (entry->end)
4299− entry->end += 1;
4277+ entry->end++;
43004278 }
43014279
43024280 static void
@@ -4320,7 +4298,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv, · 17 unmodified lines
43204298
43214299 /* No DDB allocated for disabled planes */
43224300 if (val & PLANE_CTL_ENABLE)
4323− fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
4301+ fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK_SKL,
43244302 val & PLANE_CTL_ORDER_RGBX,
43254303 val & PLANE_CTL_ALPHA_MASK);
43264304
@@ -4717,6 +4695,10 @@ static const struct dbuf_slice_conf_entry dg2_allowed_dbufs[] = { · 390 unmodified lines
47174695 };
47184696
47194697 static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
4698+ /*
4699+ * Keep the join_mbus cases first so check_mbus_joined()
4700+ * will prefer them over the !join_mbus cases.
4701+ */
47204702 {
47214703 .active_pipes = BIT(PIPE_A),
47224704 .dbuf_mask = {
@@ -4731,6 +4713,20 @@ static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = { · 8 unmodified lines
47314713 },
47324714 .join_mbus = true,
47334715 },
4716+ {
4717+ .active_pipes = BIT(PIPE_A),
4718+ .dbuf_mask = {
4719+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4720+ },
4721+ .join_mbus = false,
4722+ },
4723+ {
4724+ .active_pipes = BIT(PIPE_B),
4725+ .dbuf_mask = {
4726+ [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4727+ },
4728+ .join_mbus = false,
4729+ },
47344730 {
47354731 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
47364732 .dbuf_mask = {
@@ -4847,13 +4843,14 @@ static bool adlp_check_mbus_joined(u8 active_pipes) · 110 unmodified lines
48474843 return check_mbus_joined(active_pipes, adlp_allowed_dbufs);
48484844 }
48494845
4850−static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes,
4846+static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus,
48514847 const struct dbuf_slice_conf_entry *dbuf_slices)
48524848 {
48534849 int i;
48544850
48554851 for (i = 0; i < dbuf_slices[i].active_pipes; i++) {
4856− if (dbuf_slices[i].active_pipes == active_pipes)
4852+ if (dbuf_slices[i].active_pipes == active_pipes &&
4853+ dbuf_slices[i].join_mbus == join_mbus)
48574854 return dbuf_slices[i].dbuf_mask[pipe];
48584855 }
48594856 return 0;
@@ -4864,7 +4861,7 @@ static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, · 4 unmodified lines
48644861 * returns correspondent DBuf slice mask as stated in BSpec for particular
48654862 * platform.
48664863 */
4867−static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
4864+static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)
48684865 {
48694866 /*
48704867 * FIXME: For ICL this is still a bit unclear as prev BSpec revision
@@ -4878,37 +4875,41 @@ static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes) · 7 unmodified lines
48784875 * still here - we will need it once those additional constraints
48794876 * pop up.
48804877 */
4881− return compute_dbuf_slices(pipe, active_pipes, icl_allowed_dbufs);
4878+ return compute_dbuf_slices(pipe, active_pipes, join_mbus,
4879+ icl_allowed_dbufs);
48824880 }
48834881
4884−static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
4882+static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)
48854883 {
4886− return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs);
4884+ return compute_dbuf_slices(pipe, active_pipes, join_mbus,
4885+ tgl_allowed_dbufs);
48874886 }
48884887
4889−static u32 adlp_compute_dbuf_slices(enum pipe pipe, u32 active_pipes)
4888+static u8 adlp_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)
48904889 {
4891− return compute_dbuf_slices(pipe, active_pipes, adlp_allowed_dbufs);
4890+ return compute_dbuf_slices(pipe, active_pipes, join_mbus,
4891+ adlp_allowed_dbufs);
48924892 }
48934893
4894−static u32 dg2_compute_dbuf_slices(enum pipe pipe, u32 active_pipes)
4894+static u8 dg2_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)
48954895 {
4896− return compute_dbuf_slices(pipe, active_pipes, dg2_allowed_dbufs);
4896+ return compute_dbuf_slices(pipe, active_pipes, join_mbus,
4897+ dg2_allowed_dbufs);
48974898 }
48984899
4899−static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
4900+static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool join_mbus)
49004901 {
49014902 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
49024903 enum pipe pipe = crtc->pipe;
49034904
49044905 if (IS_DG2(dev_priv))
4905− return dg2_compute_dbuf_slices(pipe, active_pipes);
4906+ return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus);
49064907 else if (IS_ALDERLAKE_P(dev_priv))
4907− return adlp_compute_dbuf_slices(pipe, active_pipes);
4908+ return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus);
49084909 else if (DISPLAY_VER(dev_priv) == 12)
4909− return tgl_compute_dbuf_slices(pipe, active_pipes);
4910+ return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus);
49104911 else if (DISPLAY_VER(dev_priv) == 11)
4911− return icl_compute_dbuf_slices(pipe, active_pipes);
4912+ return icl_compute_dbuf_slices(pipe, active_pipes, join_mbus);
49124913 /*
49134914 * For anything else just return one slice yet.
49144915 * Should be extended for other platforms.
@@ -4916,6 +4917,28 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes) · 1 unmodified line
49164917 return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
49174918 }
49184919
4920+static bool
4921+use_min_ddb(const struct intel_crtc_state *crtc_state,
4922+ struct intel_plane *plane)
4923+{
4924+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
4925+
4926+ return DISPLAY_VER(i915) >= 13 &&
4927+ crtc_state->uapi.async_flip &&
4928+ plane->async_flip;
4929+}
4930+
4931+static bool
4932+use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
4933+ struct intel_plane *plane)
4934+{
4935+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
4936+
4937+ return DISPLAY_VER(i915) >= 13 &&
4938+ crtc_state->uapi.async_flip &&
4939+ plane->async_flip;
4940+}
4941+
49194942 static u64
49204943 skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
49214944 const struct intel_plane_state *plane_state,
@@ -4934,6 +4957,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state, · 12 unmodified lines
49344957 if (plane->id == PLANE_CURSOR)
49354958 return 0;
49364959
4960+ /*
4961+ * We calculate extra ddb based on ratio plane rate/total data rate
4962+ * in case, in some cases we should not allocate extra ddb for the plane,
4963+ * so do not count its data rate, if this is the case.
4964+ */
4965+ if (use_min_ddb(crtc_state, plane))
4966+ return 0;
4967+
49374968 if (color_plane == 1 &&
49384969 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
49394970 return 0;
@@ -5508,6 +5539,7 @@ static int skl_wm_max_lines(struct drm_i915_private *dev_priv) · 568 unmodified lines
55085539 }
55095540
55105541 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
5542+ struct intel_plane *plane,
55115543 int level,
55125544 unsigned int latency,
55135545 const struct skl_wm_params *wp,
@@ -5519,7 +5551,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, · 5 unmodified lines
55195551 uint_fixed_16_16_t selected_result;
55205552 u32 blocks, lines, min_ddb_alloc = 0;
55215553
5522− if (latency == 0) {
5554+ if (latency == 0 ||
5555+ (use_minimal_wm0_only(crtc_state, plane) && level > 0)) {
55235556 /* reject it */
55245557 result->min_ddb_alloc = U16_MAX;
55255558 return;
@@ -5635,6 +5668,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, · 109 unmodified lines
56355668
56365669 static void
56375670 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
5671+ struct intel_plane *plane,
56385672 const struct skl_wm_params *wm_params,
56395673 struct skl_wm_level *levels)
56405674 {
@@ -5646,7 +5680,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state, · 5 unmodified lines
56465680 struct skl_wm_level *result = &levels[level];
56475681 unsigned int latency = dev_priv->wm.skl_latency[level];
56485682
5649− skl_compute_plane_wm(crtc_state, level, latency,
5683+ skl_compute_plane_wm(crtc_state, plane, level, latency,
56505684 wm_params, result_prev, result);
56515685
56525686 result_prev = result;
@@ -5654,6 +5688,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state, · 1 unmodified line
56545688 }
56555689
56565690 static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
5691+ struct intel_plane *plane,
56575692 const struct skl_wm_params *wm_params,
56585693 struct skl_plane_wm *plane_wm)
56595694 {
@@ -5662,7 +5697,7 @@ static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state, · 2 unmodified lines
56625697 struct skl_wm_level *levels = plane_wm->wm;
56635698 unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;
56645699
5665− skl_compute_plane_wm(crtc_state, 0, latency,
5700+ skl_compute_plane_wm(crtc_state, plane, 0, latency,
56665701 wm_params, &levels[0],
56675702 sagv_wm);
56685703 }
@@ -5732,11 +5767,11 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv, · 63 unmodified lines
57325767
57335768 static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
57345769 const struct intel_plane_state *plane_state,
5735− enum plane_id plane_id, int color_plane)
5770+ struct intel_plane *plane, int color_plane)
57365771 {
57375772 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
57385773 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5739− struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5774+ struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
57405775 struct skl_wm_params wm_params;
57415776 int ret;
57425777
@@ -5745,13 +5780,13 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state, · 2 unmodified lines
57455780 if (ret)
57465781 return ret;
57475782
5748− skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
5783+ skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm);
57495784
57505785 skl_compute_transition_wm(dev_priv, &wm->trans_wm,
57515786 &wm->wm[0], &wm_params);
57525787
57535788 if (DISPLAY_VER(dev_priv) >= 12) {
5754− tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
5789+ tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm);
57555790
57565791 skl_compute_transition_wm(dev_priv, &wm->sagv.trans_wm,
57575792 &wm->sagv.wm0, &wm_params);
@@ -5762,9 +5797,9 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state, · 4 unmodified lines
57625797
57635798 static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
57645799 const struct intel_plane_state *plane_state,
5765− enum plane_id plane_id)
5800+ struct intel_plane *plane)
57665801 {
5767− struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5802+ struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
57685803 struct skl_wm_params wm_params;
57695804 int ret;
57705805
@@ -5776,7 +5811,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state, · 5 unmodified lines
57765811 if (ret)
57775812 return ret;
57785813
5779− skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
5814+ skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm);
57805815
57815816 return 0;
57825817 }
@@ -5796,13 +5831,13 @@ static int skl_build_plane_wm(struct intel_crtc_state *crtc_state, · 13 unmodified lines
57965831 return 0;
57975832
57985833 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5799− plane_id, 0);
5834+ plane, 0);
58005835 if (ret)
58015836 return ret;
58025837
58035838 if (fb->format->is_yuv && fb->format->num_planes > 1) {
58045839 ret = skl_build_plane_wm_uv(crtc_state, plane_state,
5805− plane_id);
5840+ plane);
58065841 if (ret)
58075842 return ret;
58085843 }
@@ -5827,7 +5862,6 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, · 18 unmodified lines
58275862
58285863 if (plane_state->planar_linked_plane) {
58295864 const struct drm_framebuffer *fb = plane_state->hw.fb;
5830− enum plane_id y_plane_id = plane_state->planar_linked_plane->id;
58315865
58325866 drm_WARN_ON(&dev_priv->drm,
58335867 !intel_wm_plane_visible(crtc_state, plane_state));
@@ -5835,17 +5869,17 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, · 1 unmodified line
58355869 fb->format->num_planes == 1);
58365870
58375871 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5838− y_plane_id, 0);
5872+ plane_state->planar_linked_plane, 0);
58395873 if (ret)
58405874 return ret;
58415875
58425876 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5843− plane_id, 1);
5877+ plane, 1);
58445878 if (ret)
58455879 return ret;
58465880 } else if (intel_wm_plane_visible(crtc_state, plane_state)) {
58475881 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5848− plane_id, 0);
5882+ plane, 0);
58495883 if (ret)
58505884 return ret;
58515885 }
@@ -5891,7 +5925,8 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, · 39 unmodified lines
58915925 {
58925926 if (entry->end)
58935927 intel_de_write_fw(dev_priv, reg,
5894− (entry->end - 1) << 16 | entry->start);
5928+ PLANE_BUF_END(entry->end - 1) |
5929+ PLANE_BUF_START(entry->start));
58955930 else
58965931 intel_de_write_fw(dev_priv, reg, 0);
58975932 }
@@ -6127,11 +6162,16 @@ skl_compute_ddb(struct intel_atomic_state *state) · 229 unmodified lines
61276162 return ret;
61286163 }
61296164
6165+ if (IS_ALDERLAKE_P(dev_priv))
6166+ new_dbuf_state->joined_mbus =
6167+ adlp_check_mbus_joined(new_dbuf_state->active_pipes);
6168+
61306169 for_each_intel_crtc(&dev_priv->drm, crtc) {
61316170 enum pipe pipe = crtc->pipe;
61326171
61336172 new_dbuf_state->slices[pipe] =
6134− skl_compute_dbuf_slices(crtc, new_dbuf_state->active_pipes);
6173+ skl_compute_dbuf_slices(crtc, new_dbuf_state->active_pipes,
6174+ new_dbuf_state->joined_mbus);
61356175
61366176 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe])
61376177 continue;
@@ -6143,9 +6183,6 @@ skl_compute_ddb(struct intel_atomic_state *state) · 5 unmodified lines
61436183
61446184 new_dbuf_state->enabled_slices = intel_dbuf_enabled_slices(new_dbuf_state);
61456185
6146− if (IS_ALDERLAKE_P(dev_priv))
6147− new_dbuf_state->joined_mbus = adlp_check_mbus_joined(new_dbuf_state->active_pipes);
6148−
61496186 if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices ||
61506187 old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
61516188 ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
@@ -6626,6 +6663,7 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) · 474 unmodified lines
66266663 enum pipe pipe = crtc->pipe;
66276664 unsigned int mbus_offset;
66286665 enum plane_id plane_id;
6666+ u8 slices;
66296667
66306668 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
66316669 crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;
@@ -6645,19 +6683,22 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) · 13 unmodified lines
66456683 skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_uv);
66466684 }
66476685
6648− dbuf_state->slices[pipe] =
6649− skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes);
6650−
66516686 dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
66526687
66536688 /*
66546689 * Used for checking overlaps, so we need absolute
66556690 * offsets instead of MBUS relative offsets.
66566691 */
6657− mbus_offset = mbus_ddb_offset(dev_priv, dbuf_state->slices[pipe]);
6692+ slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes,
6693+ dbuf_state->joined_mbus);
6694+ mbus_offset = mbus_ddb_offset(dev_priv, slices);
66586695 crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;
66596696 crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;
66606697
6698+ /* The slices actually used by the planes on the pipe */
6699+ dbuf_state->slices[pipe] =
6700+ skl_ddb_dbuf_slice_mask(dev_priv, &crtc_state->wm.skl.ddb);
6701+
66616702 drm_dbg_kms(&dev_priv->drm,
66626703 "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n",
66636704 crtc->base.base.id, crtc->base.name,
@@ -6669,6 +6710,74 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) · 5 unmodified lines
66696710 dbuf_state->enabled_slices = dev_priv->dbuf.enabled_slices;
66706711 }
66716712
6713+static bool skl_dbuf_is_misconfigured(struct drm_i915_private *i915)
6714+{
6715+ const struct intel_dbuf_state *dbuf_state =
6716+ to_intel_dbuf_state(i915->dbuf.obj.state);
6717+ struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
6718+ struct intel_crtc *crtc;
6719+
6720+ for_each_intel_crtc(&i915->drm, crtc) {
6721+ const struct intel_crtc_state *crtc_state =
6722+ to_intel_crtc_state(crtc->base.state);
6723+
6724+ entries[crtc->pipe] = crtc_state->wm.skl.ddb;
6725+ }
6726+
6727+ for_each_intel_crtc(&i915->drm, crtc) {
6728+ const struct intel_crtc_state *crtc_state =
6729+ to_intel_crtc_state(crtc->base.state);
6730+ u8 slices;
6731+
6732+ slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes,
6733+ dbuf_state->joined_mbus);
6734+ if (dbuf_state->slices[crtc->pipe] & ~slices)
6735+ return true;
6736+
6737+ if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries,
6738+ I915_MAX_PIPES, crtc->pipe))
6739+ return true;
6740+ }
6741+
6742+ return false;
6743+}
6744+
6745+void skl_wm_sanitize(struct drm_i915_private *i915)
6746+{
6747+ struct intel_crtc *crtc;
6748+
6749+ /*
6750+ * On TGL/RKL (at least) the BIOS likes to assign the planes
6751+ * to the wrong DBUF slices. This will cause an infinite loop
6752+ * in skl_commit_modeset_enables() as it can't find a way to
6753+ * transition between the old bogus DBUF layout to the new
6754+ * proper DBUF layout without DBUF allocation overlaps between
6755+ * the planes (which cannot be allowed or else the hardware
6756+ * may hang). If we detect a bogus DBUF layout just turn off
6757+ * all the planes so that skl_commit_modeset_enables() can
6758+ * simply ignore them.
6759+ */
6760+ if (!skl_dbuf_is_misconfigured(i915))
6761+ return;
6762+
6763+ drm_dbg_kms(&i915->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n");
6764+
6765+ for_each_intel_crtc(&i915->drm, crtc) {
6766+ struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6767+ const struct intel_plane_state *plane_state =
6768+ to_intel_plane_state(plane->base.state);
6769+ struct intel_crtc_state *crtc_state =
6770+ to_intel_crtc_state(crtc->base.state);
6771+
6772+ if (plane_state->uapi.visible)
6773+ intel_plane_disable_noatomic(crtc, plane);
6774+
6775+ drm_WARN_ON(&i915->drm, crtc_state->active_planes != 0);
6776+
6777+ memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb));
6778+ }
6779+}
6780+
66726781 static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
66736782 {
66746783 struct drm_device *dev = crtc->base.dev;
@@ -7220,7 +7329,7 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) · 545 unmodified lines
72207329 for_each_pipe(dev_priv, pipe) {
72217330 intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe),
72227331 intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) |
7223− DISPPLANE_TRICKLE_FEED_DISABLE);
7332+ DISP_TRICKLE_FEED_DISABLE);
72247333
72257334 intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(pipe)));
72267335 intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe));
@@ -7451,8 +7560,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, · 224 unmodified lines
74517560 static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
74527561 {
74537562 /* Wa_1409120013:icl,ehl */
7454− intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
7455− DPFC_CHICKEN_COMP_DUMMY_PIXEL);
7563+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
7564+ DPFC_CHICKEN_COMP_DUMMY_PIXEL);
74567565
74577566 /*Wa_14010594013:icl, ehl */
74587567 intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
@@ -7464,7 +7573,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) · 5 unmodified lines
74647573 /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */
74657574 if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
74667575 IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
7467− intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
7576+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
74687577 DPFC_CHICKEN_COMP_DUMMY_PIXEL);
74697578
74707579 /* Wa_1409825376:tgl (pre-prod)*/
@@ -7549,8 +7658,9 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv) · 78 unmodified lines
75497658 * WaFbcNukeOnHostModify:cfl
75507659 * Display WA #0873: cfl
75517660 */
7552− intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
7553− DPFC_NUKE_ON_ANY_MODIFICATION);
7661+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
7662+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
7663+ DPFC_NUKE_ON_ANY_MODIFICATION);
75547664 }
75557665
75567666 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7582,8 +7692,9 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv) · 25 unmodified lines
75827692 * WaFbcNukeOnHostModify:kbl
75837693 * Display WA #0873: kbl
75847694 */
7585− intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
7586− DPFC_NUKE_ON_ANY_MODIFICATION);
7695+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
7696+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
7697+ DPFC_NUKE_ON_ANY_MODIFICATION);
75877698 }
75887699
75897700 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7609,15 +7720,17 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv) · 19 unmodified lines
76097720 * WaFbcNukeOnHostModify:skl
76107721 * Display WA #0873: skl
76117722 */
7612− intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
7613− DPFC_NUKE_ON_ANY_MODIFICATION);
7723+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
7724+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
7725+ DPFC_NUKE_ON_ANY_MODIFICATION);
76147726
76157727 /*
76167728 * WaFbcHighMemBwCorruptionAvoidance:skl
76177729 * Display WA #0883: skl
76187730 */
7619− intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
7620− DPFC_DISABLE_DUMMY0);
7731+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
7732+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
7733+ DPFC_DISABLE_DUMMY0);
76217734 }
76227735
76237736 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7649,7 +7762,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) · 25 unmodified lines
76497762 intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
76507763 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
76517764
7652− intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
7765+ intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
76537766 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
76547767
76557768 /* WaDisableSDEUnitClockGating:bdw */
@@ -7790,7 +7903,7 @@ static void chv_init_clock_gating(struct drm_i915_private *dev_priv) · 134 unmodified lines
77907903 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
77917904
77927905 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7793− intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
7906+ intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
77947907 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
77957908
77967909 /* WaDisableCSUnitClockGating:chv */
@@ -7863,10 +7976,12 @@ static void gen3_init_clock_gating(struct drm_i915_private *dev_priv) · 66 unmodified lines
78637976 intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
78647977
78657978 if (IS_PINEVIEW(dev_priv))
7866− intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7979+ intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
7980+ _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
78677981
78687982 /* IIR "flip pending" means done if this bit is set */
7869− intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7983+ intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
7984+ _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
78707985
78717986 /* interrupts should cause a wake up from C3 */
78727987 intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
drivers/gpu/drm/i915/intel_pm.h+1−1
@@ -12,7 +12,6 @@ · 11 unmodified lines
1212 #include "display/intel_global_state.h"
1313
1414 #include "i915_drv.h"
15−#include "i915_reg.h"
1615
1716 struct drm_device;
1817 struct drm_i915_private;
@@ -47,6 +46,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, · 28 unmodified lines
4746 struct skl_pipe_wm *out);
4847 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
4948 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
49+void skl_wm_sanitize(struct drm_i915_private *dev_priv);
5050 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
5151 const struct intel_bw_state *bw_state);
5252 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
drivers/gpu/drm/i915/intel_runtime_pm.c+1−6
@@ -68,9 +68,7 @@ static noinline depot_stack_handle_t __save_depot_stack(void) · 67 unmodified lines
6868 static void init_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm)
6969 {
7070 spin_lock_init(&rpm->debug.lock);
71−
72− if (rpm->available)
73− stack_depot_init();
71+ stack_depot_init();
7472 }
7573
7674 static noinline depot_stack_handle_t
@@ -79,9 +77,6 @@ track_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm) · 2 unmodified lines
7977 depot_stack_handle_t stack, *stacks;
8078 unsigned long flags;
8179
82− if (!rpm->available)
83− return -1;
84−
8580 stack = __save_depot_stack();
8681 if (!stack)
8782 return -1;
drivers/gpu/drm/i915/intel_sbi.c+1−0
@@ -7,6 +7,7 @@ · 6 unmodified lines
77
88 #include "i915_drv.h"
99 #include "intel_sbi.h"
10+#include "i915_reg.h"
1011
1112 /* SBI access */
1213 static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
drivers/gpu/drm/i915/intel_uncore.c+2−71
@@ -23,7 +23,8 @@ · 22 unmodified lines
2323
2424 #include <linux/pm_runtime.h>
2525
26−#include "gt/intel_lrc_reg.h" /* for shadow reg list */
26+#include "gt/intel_engine_regs.h"
27+#include "gt/intel_gt_regs.h"
2728
2829 #include "i915_drv.h"
2930 #include "i915_iosf_mbi.h"
@@ -2273,76 +2274,6 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore) · 2243 unmodified lines
22732274 }
22742275 }
22752276
2276−static const struct reg_whitelist {
2277− i915_reg_t offset_ldw;
2278− i915_reg_t offset_udw;
2279− u8 min_graphics_ver;
2280− u8 max_graphics_ver;
2281− u8 size;
2282−} reg_read_whitelist[] = { {
2283− .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
2284− .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
2285− .min_graphics_ver = 4,
2286− .max_graphics_ver = 12,
2287− .size = 8
2288−} };
2289−
2290−int i915_reg_read_ioctl(struct drm_device *dev,
2291− void *data, struct drm_file *file)
2292−{
2293− struct drm_i915_private *i915 = to_i915(dev);
2294− struct intel_uncore *uncore = &i915->uncore;
2295− struct drm_i915_reg_read *reg = data;
2296− struct reg_whitelist const *entry;
2297− intel_wakeref_t wakeref;
2298− unsigned int flags;
2299− int remain;
2300− int ret = 0;
2301−
2302− entry = reg_read_whitelist;
2303− remain = ARRAY_SIZE(reg_read_whitelist);
2304− while (remain) {
2305− u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
2306−
2307− GEM_BUG_ON(!is_power_of_2(entry->size));
2308− GEM_BUG_ON(entry->size > 8);
2309− GEM_BUG_ON(entry_offset & (entry->size - 1));
2310−
2311− if (IS_GRAPHICS_VER(i915, entry->min_graphics_ver, entry->max_graphics_ver) &&
2312− entry_offset == (reg->offset & -entry->size))
2313− break;
2314− entry++;
2315− remain--;
2316− }
2317−
2318− if (!remain)
2319− return -EINVAL;
2320−
2321− flags = reg->offset & (entry->size - 1);
2322−
2323− with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
2324− if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
2325− reg->val = intel_uncore_read64_2x32(uncore,
2326− entry->offset_ldw,
2327− entry->offset_udw);
2328− else if (entry->size == 8 && flags == 0)
2329− reg->val = intel_uncore_read64(uncore,
2330− entry->offset_ldw);
2331− else if (entry->size == 4 && flags == 0)
2332− reg->val = intel_uncore_read(uncore, entry->offset_ldw);
2333− else if (entry->size == 2 && flags == 0)
2334− reg->val = intel_uncore_read16(uncore,
2335− entry->offset_ldw);
2336− else if (entry->size == 1 && flags == 0)
2337− reg->val = intel_uncore_read8(uncore,
2338− entry->offset_ldw);
2339− else
2340− ret = -EINVAL;
2341− }
2342−
2343− return ret;
2344−}
2345−
23462277 /**
23472278 * __intel_wait_for_register_fw - wait until register matches expected state
23482279 * @uncore: the struct intel_uncore
drivers/gpu/drm/i915/intel_uncore.h+1−1
@@ -30,7 +30,7 @@ · 29 unmodified lines
3030 #include <linux/hrtimer.h>
3131 #include <linux/io-64-nonatomic-lo-hi.h>
3232
33−#include "i915_reg.h"
33+#include "i915_reg_defs.h"
3434
3535 struct drm_i915_private;
3636 struct intel_runtime_pm;
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c+1−0
@@ -7,6 +7,7 @@ · 6 unmodified lines
77 #include "intel_pxp_irq.h"
88 #include "intel_pxp_session.h"
99 #include "gt/intel_gt_irq.h"
10+#include "gt/intel_gt_regs.h"
1011 #include "gt/intel_gt_types.h"
1112 #include "i915_irq.h"
1213 #include "i915_reg.h"
drivers/gpu/drm/i915/vlv_sideband.c+1−0
@@ -5,6 +5,7 @@ · 4 unmodified lines
55
66 #include "i915_drv.h"
77 #include "i915_iosf_mbi.h"
8+#include "i915_reg.h"
89 #include "vlv_sideband.h"
910
1011 /*
drivers/gpu/drm/i915/vlv_sideband.h+2−0
@@ -9,6 +9,8 @@ · 8 unmodified lines
99 #include <linux/bitops.h>
1010 #include <linux/types.h>
1111
12+#include "vlv_sideband_reg.h"
13+
1214 enum pipe;
1315 struct drm_i915_private;
1416
drivers/gpu/drm/i915/vlv_sideband_reg.h+180−0
@@ -0,0 +1,180 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2022 Intel Corporation
4+ */
5+
6+#ifndef _VLV_SIDEBAND_REG_H_
7+#define _VLV_SIDEBAND_REG_H_
8+
9+/* See configdb bunit SB addr map */
10+#define BUNIT_REG_BISOC 0x11
11+
12+/* PUNIT_REG_*SSPM0 */
13+#define _SSPM0_SSC(val) ((val) << 0)
14+#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
15+#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
16+#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
17+#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
18+#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
19+#define _SSPM0_SSS(val) ((val) << 24)
20+#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
21+#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
22+#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
23+#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
24+#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
25+
26+/* PUNIT_REG_*SSPM1 */
27+#define SSPM1_FREQSTAT_SHIFT 24
28+#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
29+#define SSPM1_FREQGUAR_SHIFT 8
30+#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
31+#define SSPM1_FREQ_SHIFT 0
32+#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
33+
34+#define PUNIT_REG_VEDSSPM0 0x32
35+#define PUNIT_REG_VEDSSPM1 0x33
36+
37+#define PUNIT_REG_DSPSSPM 0x36
38+#define DSPFREQSTAT_SHIFT_CHV 24
39+#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
40+#define DSPFREQGUAR_SHIFT_CHV 8
41+#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
42+#define DSPFREQSTAT_SHIFT 30
43+#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
44+#define DSPFREQGUAR_SHIFT 14
45+#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
46+#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
47+#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
48+#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
49+#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
50+#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
51+#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
52+#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
53+#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
54+#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
55+#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
56+#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
57+#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
58+#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
59+#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
60+#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
61+
62+#define PUNIT_REG_ISPSSPM0 0x39
63+#define PUNIT_REG_ISPSSPM1 0x3a
64+
65+#define PUNIT_REG_PWRGT_CTRL 0x60
66+#define PUNIT_REG_PWRGT_STATUS 0x61
67+#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
68+#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
69+#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
70+#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
71+#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
72+
73+#define PUNIT_PWGT_IDX_RENDER 0
74+#define PUNIT_PWGT_IDX_MEDIA 1
75+#define PUNIT_PWGT_IDX_DISP2D 3
76+#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
77+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
78+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
79+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
80+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
81+#define PUNIT_PWGT_IDX_DPIO_RX0 10
82+#define PUNIT_PWGT_IDX_DPIO_RX1 11
83+#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
84+
85+#define PUNIT_REG_GPU_LFM 0xd3
86+#define PUNIT_REG_GPU_FREQ_REQ 0xd4
87+#define PUNIT_REG_GPU_FREQ_STS 0xd8
88+#define GPLLENABLE (1 << 4)
89+#define GENFREQSTATUS (1 << 0)
90+#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
91+#define PUNIT_REG_CZ_TIMESTAMP 0xce
92+
93+#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
94+#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
95+
96+#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
97+#define FB_GFX_FREQ_FUSE_MASK 0xff
98+#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
99+#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
100+#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
101+
102+#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
103+#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
104+
105+#define PUNIT_REG_DDR_SETUP2 0x139
106+#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
107+#define FORCE_DDR_LOW_FREQ (1 << 1)
108+#define FORCE_DDR_HIGH_FREQ (1 << 0)
109+
110+#define PUNIT_GPU_STATUS_REG 0xdb
111+#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
112+#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
113+#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
114+#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
115+
116+#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
117+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
118+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
119+
120+#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
121+#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
122+#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
123+#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
124+#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
125+#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
126+#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
127+#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
128+#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
129+#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
130+
131+#define VLV_TURBO_SOC_OVERRIDE 0x04
132+#define VLV_OVERRIDE_EN 1
133+#define VLV_SOC_TDP_EN (1 << 1)
134+#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
135+#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
136+
137+/* vlv2 north clock has */
138+#define CCK_FUSE_REG 0x8
139+#define CCK_FUSE_HPLL_FREQ_MASK 0x3
140+#define CCK_REG_DSI_PLL_FUSE 0x44
141+#define CCK_REG_DSI_PLL_CONTROL 0x48
142+#define DSI_PLL_VCO_EN (1 << 31)
143+#define DSI_PLL_LDO_GATE (1 << 30)
144+#define DSI_PLL_P1_POST_DIV_SHIFT 17
145+#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
146+#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
147+#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
148+#define DSI_PLL_MUX_MASK (3 << 9)
149+#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
150+#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
151+#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
152+#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
153+#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
154+#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
155+#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
156+#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
157+#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
158+#define DSI_PLL_LOCK (1 << 0)
159+#define CCK_REG_DSI_PLL_DIVIDER 0x4c
160+#define DSI_PLL_LFSR (1 << 31)
161+#define DSI_PLL_FRACTION_EN (1 << 30)
162+#define DSI_PLL_FRAC_COUNTER_SHIFT 27
163+#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
164+#define DSI_PLL_USYNC_CNT_SHIFT 18
165+#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
166+#define DSI_PLL_N1_DIV_SHIFT 16
167+#define DSI_PLL_N1_DIV_MASK (3 << 16)
168+#define DSI_PLL_M1_DIV_SHIFT 0
169+#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
170+#define CCK_CZ_CLOCK_CONTROL 0x62
171+#define CCK_GPLL_CLOCK_CONTROL 0x67
172+#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
173+#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
174+#define CCK_TRUNK_FORCE_ON (1 << 17)
175+#define CCK_TRUNK_FORCE_OFF (1 << 16)
176+#define CCK_FREQUENCY_STATUS (0x1f << 8)
177+#define CCK_FREQUENCY_STATUS_SHIFT 8
178+#define CCK_FREQUENCY_VALUES (0x1f << 0)
179+
180+#endif /* _VLV_SIDEBAND_REG_H_ */
drivers/gpu/drm/i915/vlv_suspend.c+2−0
@@ -14,6 +14,8 @@ · 13 unmodified lines
1414 #include "intel_pm.h"
1515 #include "vlv_suspend.h"
1616
17+#include "gt/intel_gt_regs.h"
18+
1719 struct vlv_s0ix_state {
1820 /* GAM */
1921 u32 wr_watermark;
drivers/gpu/drm/lima/lima_gem.c+2−1
@@ -2,6 +2,7 @@ · 1 unmodified line
22 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
33
44 #include <linux/mm.h>
5+#include <linux/iosys-map.h>
56 #include <linux/sync_file.h>
67 #include <linux/pagemap.h>
78 #include <linux/shmem_fs.h>
@@ -182,7 +183,7 @@ static int lima_gem_pin(struct drm_gem_object *obj) · 174 unmodified lines
182183 return drm_gem_shmem_pin(&bo->base);
183184 }
184185
185−static int lima_gem_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
186+static int lima_gem_vmap(struct drm_gem_object *obj, struct iosys_map *map)
186187 {
187188 struct lima_bo *bo = to_lima_bo(obj);
188189
drivers/gpu/drm/lima/lima_sched.c+2−2
@@ -1,7 +1,7 @@
11 // SPDX-License-Identifier: GPL-2.0 OR MIT
22 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
33
4−#include <linux/dma-buf-map.h>
4+#include <linux/iosys-map.h>
55 #include <linux/kthread.h>
66 #include <linux/slab.h>
77 #include <linux/vmalloc.h>
@@ -284,7 +284,7 @@ static void lima_sched_build_error_task_list(struct lima_sched_task *task) · 276 unmodified lines
284284 struct lima_dump_chunk_buffer *buffer_chunk;
285285 u32 size, task_size, mem_size;
286286 int i;
287− struct dma_buf_map map;
287+ struct iosys_map map;
288288 int ret;
289289
290290 mutex_lock(&dev->error_task_list_lock);
drivers/gpu/drm/mediatek/mtk_drm_gem.c+4−3
@@ -220,7 +220,7 @@ struct drm_gem_object *mtk_gem_prime_import_sg_table(struct drm_device *dev, · 219 unmodified lines
220220 return &mtk_gem->base;
221221 }
222222
223−int mtk_drm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
223+int mtk_drm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map)
224224 {
225225 struct mtk_drm_gem_obj *mtk_gem = to_mtk_gem_obj(obj);
226226 struct sg_table *sgt = NULL;
@@ -247,12 +247,13 @@ int mtk_drm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map) · 20 unmodified lines
247247
248248 out:
249249 kfree(sgt);
250− dma_buf_map_set_vaddr(map, mtk_gem->kvaddr);
250+ iosys_map_set_vaddr(map, mtk_gem->kvaddr);
251251
252252 return 0;
253253 }
254254
255−void mtk_drm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map)
255+void mtk_drm_gem_prime_vunmap(struct drm_gem_object *obj,
256+ struct iosys_map *map)
256257 {
257258 struct mtk_drm_gem_obj *mtk_gem = to_mtk_gem_obj(obj);
258259 void *vaddr = map->vaddr;
drivers/gpu/drm/mediatek/mtk_drm_gem.h+3−2
@@ -42,7 +42,8 @@ int mtk_drm_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, · 41 unmodified lines
4242 struct sg_table *mtk_gem_prime_get_sg_table(struct drm_gem_object *obj);
4343 struct drm_gem_object *mtk_gem_prime_import_sg_table(struct drm_device *dev,
4444 struct dma_buf_attachment *attach, struct sg_table *sg);
45−int mtk_drm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
46−void mtk_drm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
45+int mtk_drm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
46+void mtk_drm_gem_prime_vunmap(struct drm_gem_object *obj,
47+ struct iosys_map *map);
4748
4849 #endif
drivers/gpu/drm/mgag200/mgag200_mode.c+2−2
@@ -9,7 +9,7 @@ · 8 unmodified lines
99 */
1010
1111 #include <linux/delay.h>
12−#include <linux/dma-buf-map.h>
12+#include <linux/iosys-map.h>
1313
1414 #include <drm/drm_atomic_helper.h>
1515 #include <drm/drm_atomic_state_helper.h>
@@ -848,7 +848,7 @@ mgag200_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe, · 832 unmodified lines
848848
849849 static void
850850 mgag200_handle_damage(struct mga_device *mdev, struct drm_framebuffer *fb,
851− struct drm_rect *clip, const struct dma_buf_map *map)
851+ struct drm_rect *clip, const struct iosys_map *map)
852852 {
853853 void __iomem *dst = mdev->vram;
854854 void *vmap = map->vaddr; /* TODO: Use mapping abstraction properly */
drivers/gpu/drm/msm/msm_drv.h+2−2
@@ -309,8 +309,8 @@ void msm_gem_shrinker_init(struct drm_device *dev); · 308 unmodified lines
309309 void msm_gem_shrinker_cleanup(struct drm_device *dev);
310310
311311 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
312−int msm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
313−void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
312+int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
313+void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map);
314314 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
315315 struct dma_buf_attachment *attach, struct sg_table *sg);
316316 int msm_gem_prime_pin(struct drm_gem_object *obj);
drivers/gpu/drm/msm/msm_gem_prime.c+3−3
@@ -22,19 +22,19 @@ struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj) · 21 unmodified lines
2222 return drm_prime_pages_to_sg(obj->dev, msm_obj->pages, npages);
2323 }
2424
25−int msm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
25+int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map)
2626 {
2727 void *vaddr;
2828
2929 vaddr = msm_gem_get_vaddr(obj);
3030 if (IS_ERR(vaddr))
3131 return PTR_ERR(vaddr);
32− dma_buf_map_set_vaddr(map, vaddr);
32+ iosys_map_set_vaddr(map, vaddr);
3333
3434 return 0;
3535 }
3636
37−void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map)
37+void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map)
3838 {
3939 msm_gem_put_vaddr(obj);
4040 }
drivers/gpu/drm/panfrost/panfrost_perfcnt.c+7−6
@@ -1,16 +1,17 @@
11 // SPDX-License-Identifier: GPL-2.0
22 /* Copyright 2019 Collabora Ltd */
33
4−#include <drm/drm_file.h>
5−#include <drm/drm_gem_shmem_helper.h>
6−#include <drm/panfrost_drm.h>
74 #include <linux/completion.h>
8−#include <linux/dma-buf-map.h>
95 #include <linux/iopoll.h>
6+#include <linux/iosys-map.h>
107 #include <linux/pm_runtime.h>
118 #include <linux/slab.h>
129 #include <linux/uaccess.h>
1310
11+#include <drm/drm_file.h>
12+#include <drm/drm_gem_shmem_helper.h>
13+#include <drm/panfrost_drm.h>
14+
1415 #include "panfrost_device.h"
1516 #include "panfrost_features.h"
1617 #include "panfrost_gem.h"
@@ -73,7 +74,7 @@ static int panfrost_perfcnt_enable_locked(struct panfrost_device *pfdev, · 56 unmodified lines
7374 {
7475 struct panfrost_file_priv *user = file_priv->driver_priv;
7576 struct panfrost_perfcnt *perfcnt = pfdev->perfcnt;
76− struct dma_buf_map map;
77+ struct iosys_map map;
7778 struct drm_gem_shmem_object *bo;
7879 u32 cfg, as;
7980 int ret;
@@ -181,7 +182,7 @@ static int panfrost_perfcnt_disable_locked(struct panfrost_device *pfdev, · 101 unmodified lines
181182 {
182183 struct panfrost_file_priv *user = file_priv->driver_priv;
183184 struct panfrost_perfcnt *perfcnt = pfdev->perfcnt;
184− struct dma_buf_map map = DMA_BUF_MAP_INIT_VADDR(perfcnt->buf);
185+ struct iosys_map map = IOSYS_MAP_INIT_VADDR(perfcnt->buf);
185186
186187 if (user != perfcnt->user)
187188 return -EINVAL;
drivers/gpu/drm/qxl/qxl_display.c+4−4
@@ -25,7 +25,7 @@ · 24 unmodified lines
2525
2626 #include <linux/crc32.h>
2727 #include <linux/delay.h>
28−#include <linux/dma-buf-map.h>
28+#include <linux/iosys-map.h>
2929
3030 #include <drm/drm_drv.h>
3131 #include <drm/drm_atomic.h>
@@ -566,8 +566,8 @@ static struct qxl_bo *qxl_create_cursor(struct qxl_device *qdev, · 534 unmodified lines
566566 {
567567 static const u32 size = 64 * 64 * 4;
568568 struct qxl_bo *cursor_bo;
569− struct dma_buf_map cursor_map;
570− struct dma_buf_map user_map;
569+ struct iosys_map cursor_map;
570+ struct iosys_map user_map;
571571 struct qxl_cursor cursor;
572572 int ret;
573573
@@ -1183,7 +1183,7 @@ int qxl_create_monitors_object(struct qxl_device *qdev) · 609 unmodified lines
11831183 {
11841184 int ret;
11851185 struct drm_gem_object *gobj;
1186− struct dma_buf_map map;
1186+ struct iosys_map map;
11871187 int monitors_config_size = sizeof(struct qxl_monitors_config) +
11881188 qxl_num_crtc * sizeof(struct qxl_head);
11891189
drivers/gpu/drm/qxl/qxl_draw.c+3−3
@@ -20,7 +20,7 @@ · 19 unmodified lines
2020 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
2121 */
2222
23−#include <linux/dma-buf-map.h>
23+#include <linux/iosys-map.h>
2424
2525 #include <drm/drm_fourcc.h>
2626
@@ -44,7 +44,7 @@ static struct qxl_rect *drawable_set_clipping(struct qxl_device *qdev, · 17 unmodified lines
4444 unsigned int num_clips,
4545 struct qxl_bo *clips_bo)
4646 {
47− struct dma_buf_map map;
47+ struct iosys_map map;
4848 struct qxl_clip_rects *dev_clips;
4949 int ret;
5050
@@ -146,7 +146,7 @@ void qxl_draw_dirty_fb(struct qxl_device *qdev, · 95 unmodified lines
146146 int stride = fb->pitches[0];
147147 /* depth is not actually interesting, we don't mask with it */
148148 int depth = fb->format->cpp[0] * 8;
149− struct dma_buf_map surface_map;
149+ struct iosys_map surface_map;
150150 uint8_t *surface_base;
151151 struct qxl_release *release;
152152 struct qxl_bo *clips_bo;
drivers/gpu/drm/qxl/qxl_drv.h+5−5
@@ -30,7 +30,7 @@ · 29 unmodified lines
3030 * Definitions taken from spice-protocol, plus kernel driver specific bits.
3131 */
3232
33−#include <linux/dma-buf-map.h>
33+#include <linux/iosys-map.h>
3434 #include <linux/dma-fence.h>
3535 #include <linux/firmware.h>
3636 #include <linux/platform_device.h>
@@ -50,7 +50,7 @@ · 13 unmodified lines
5050
5151 #include "qxl_dev.h"
5252
53−struct dma_buf_map;
53+struct iosys_map;
5454
5555 #define DRIVER_AUTHOR "Dave Airlie"
5656
@@ -81,7 +81,7 @@ struct qxl_bo { · 24 unmodified lines
8181 /* Protected by tbo.reserved */
8282 struct ttm_place placements[3];
8383 struct ttm_placement placement;
84− struct dma_buf_map map;
84+ struct iosys_map map;
8585 void *kptr;
8686 unsigned int map_count;
8787 int type;
@@ -431,9 +431,9 @@ struct sg_table *qxl_gem_prime_get_sg_table(struct drm_gem_object *obj); · 343 unmodified lines
431431 struct drm_gem_object *qxl_gem_prime_import_sg_table(
432432 struct drm_device *dev, struct dma_buf_attachment *attach,
433433 struct sg_table *sgt);
434−int qxl_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
434+int qxl_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
435435 void qxl_gem_prime_vunmap(struct drm_gem_object *obj,
436− struct dma_buf_map *map);
436+ struct iosys_map *map);
437437
438438 /* qxl_irq.c */
439439 int qxl_irq_init(struct qxl_device *qdev);
drivers/gpu/drm/qxl/qxl_object.c+4−4
@@ -23,7 +23,7 @@ · 22 unmodified lines
2323 * Alon Levy
2424 */
2525
26−#include <linux/dma-buf-map.h>
26+#include <linux/iosys-map.h>
2727 #include <linux/io-mapping.h>
2828
2929 #include "qxl_drv.h"
@@ -158,7 +158,7 @@ int qxl_bo_create(struct qxl_device *qdev, unsigned long size, · 128 unmodified lines
158158 return 0;
159159 }
160160
161−int qxl_bo_vmap_locked(struct qxl_bo *bo, struct dma_buf_map *map)
161+int qxl_bo_vmap_locked(struct qxl_bo *bo, struct iosys_map *map)
162162 {
163163 int r;
164164
@@ -184,7 +184,7 @@ out: · 19 unmodified lines
184184 return 0;
185185 }
186186
187−int qxl_bo_vmap(struct qxl_bo *bo, struct dma_buf_map *map)
187+int qxl_bo_vmap(struct qxl_bo *bo, struct iosys_map *map)
188188 {
189189 int r;
190190
@@ -210,7 +210,7 @@ void *qxl_bo_kmap_atomic_page(struct qxl_device *qdev, · 19 unmodified lines
210210 void *rptr;
211211 int ret;
212212 struct io_mapping *map;
213− struct dma_buf_map bo_map;
213+ struct iosys_map bo_map;
214214
215215 if (bo->tbo.resource->mem_type == TTM_PL_VRAM)
216216 map = qdev->vram_mapping;
drivers/gpu/drm/qxl/qxl_object.h+2−2
@@ -59,8 +59,8 @@ extern int qxl_bo_create(struct qxl_device *qdev, · 58 unmodified lines
5959 u32 priority,
6060 struct qxl_surface *surf,
6161 struct qxl_bo **bo_ptr);
62−int qxl_bo_vmap(struct qxl_bo *bo, struct dma_buf_map *map);
63−int qxl_bo_vmap_locked(struct qxl_bo *bo, struct dma_buf_map *map);
62+int qxl_bo_vmap(struct qxl_bo *bo, struct iosys_map *map);
63+int qxl_bo_vmap_locked(struct qxl_bo *bo, struct iosys_map *map);
6464 int qxl_bo_vunmap(struct qxl_bo *bo);
6565 void qxl_bo_vunmap_locked(struct qxl_bo *bo);
6666 void *qxl_bo_kmap_atomic_page(struct qxl_device *qdev, struct qxl_bo *bo, int page_offset);
drivers/gpu/drm/qxl/qxl_prime.c+2−2
@@ -54,7 +54,7 @@ struct drm_gem_object *qxl_gem_prime_import_sg_table( · 53 unmodified lines
5454 return ERR_PTR(-ENOSYS);
5555 }
5656
57−int qxl_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
57+int qxl_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map)
5858 {
5959 struct qxl_bo *bo = gem_to_qxl_bo(obj);
6060 int ret;
@@ -67,7 +67,7 @@ int qxl_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map) · 6 unmodified lines
6767 }
6868
6969 void qxl_gem_prime_vunmap(struct drm_gem_object *obj,
70− struct dma_buf_map *map)
70+ struct iosys_map *map)
7171 {
7272 struct qxl_bo *bo = gem_to_qxl_bo(obj);
7373
drivers/gpu/drm/radeon/radeon_gem.c+1−0
@@ -26,6 +26,7 @@ · 25 unmodified lines
2626 * Jerome Glisse
2727 */
2828
29+#include <linux/iosys-map.h>
2930 #include <linux/pci.h>
3031
3132 #include <drm/drm_device.h>
drivers/gpu/drm/rockchip/rockchip_drm_gem.c+5−4
@@ -510,7 +510,7 @@ err_free_rk_obj: · 509 unmodified lines
510510 return ERR_PTR(ret);
511511 }
512512
513−int rockchip_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
513+int rockchip_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map)
514514 {
515515 struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj);
516516
@@ -519,18 +519,19 @@ int rockchip_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map) · 2 unmodified lines
519519 pgprot_writecombine(PAGE_KERNEL));
520520 if (!vaddr)
521521 return -ENOMEM;
522− dma_buf_map_set_vaddr(map, vaddr);
522+ iosys_map_set_vaddr(map, vaddr);
523523 return 0;
524524 }
525525
526526 if (rk_obj->dma_attrs & DMA_ATTR_NO_KERNEL_MAPPING)
527527 return -ENOMEM;
528− dma_buf_map_set_vaddr(map, rk_obj->kvaddr);
528+ iosys_map_set_vaddr(map, rk_obj->kvaddr);
529529
530530 return 0;
531531 }
532532
533−void rockchip_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map)
533+void rockchip_gem_prime_vunmap(struct drm_gem_object *obj,
534+ struct iosys_map *map)
534535 {
535536 struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj);
536537
drivers/gpu/drm/rockchip/rockchip_drm_gem.h+3−2
@@ -31,8 +31,9 @@ struct drm_gem_object * · 30 unmodified lines
3131 rockchip_gem_prime_import_sg_table(struct drm_device *dev,
3232 struct dma_buf_attachment *attach,
3333 struct sg_table *sg);
34−int rockchip_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
35−void rockchip_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
34+int rockchip_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
35+void rockchip_gem_prime_vunmap(struct drm_gem_object *obj,
36+ struct iosys_map *map);
3637
3738 struct rockchip_gem_object *
3839 rockchip_gem_create_object(struct drm_device *drm, unsigned int size,
drivers/gpu/drm/tegra/gem.c+5−5
@@ -174,7 +174,7 @@ static void tegra_bo_unpin(struct host1x_bo_mapping *map) · 173 unmodified lines
174174 static void *tegra_bo_mmap(struct host1x_bo *bo)
175175 {
176176 struct tegra_bo *obj = host1x_to_tegra_bo(bo);
177− struct dma_buf_map map;
177+ struct iosys_map map;
178178 int ret;
179179
180180 if (obj->vaddr) {
@@ -191,7 +191,7 @@ static void *tegra_bo_mmap(struct host1x_bo *bo) · 10 unmodified lines
191191 static void tegra_bo_munmap(struct host1x_bo *bo, void *addr)
192192 {
193193 struct tegra_bo *obj = host1x_to_tegra_bo(bo);
194− struct dma_buf_map map = DMA_BUF_MAP_INIT_VADDR(addr);
194+ struct iosys_map map = IOSYS_MAP_INIT_VADDR(addr);
195195
196196 if (obj->vaddr)
197197 return;
@@ -699,17 +699,17 @@ static int tegra_gem_prime_mmap(struct dma_buf *buf, struct vm_area_struct *vma) · 501 unmodified lines
699699 return __tegra_gem_mmap(gem, vma);
700700 }
701701
702−static int tegra_gem_prime_vmap(struct dma_buf *buf, struct dma_buf_map *map)
702+static int tegra_gem_prime_vmap(struct dma_buf *buf, struct iosys_map *map)
703703 {
704704 struct drm_gem_object *gem = buf->priv;
705705 struct tegra_bo *bo = to_tegra_bo(gem);
706706
707− dma_buf_map_set_vaddr(map, bo->vaddr);
707+ iosys_map_set_vaddr(map, bo->vaddr);
708708
709709 return 0;
710710 }
711711
712−static void tegra_gem_prime_vunmap(struct dma_buf *buf, struct dma_buf_map *map)
712+static void tegra_gem_prime_vunmap(struct dma_buf *buf, struct iosys_map *map)
713713 {
714714 }
715715
drivers/gpu/drm/tiny/cirrus.c+5−3
@@ -16,7 +16,7 @@ · 15 unmodified lines
1616 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
1717 */
1818
19−#include <linux/dma-buf-map.h>
19+#include <linux/iosys-map.h>
2020 #include <linux/module.h>
2121 #include <linux/pci.h>
2222
@@ -313,7 +313,8 @@ static int cirrus_mode_set(struct cirrus_device *cirrus, · 290 unmodified lines
313313 return 0;
314314 }
315315
316−static int cirrus_fb_blit_rect(struct drm_framebuffer *fb, const struct dma_buf_map *map,
316+static int cirrus_fb_blit_rect(struct drm_framebuffer *fb,
317+ const struct iosys_map *map,
317318 struct drm_rect *rect)
318319 {
319320 struct cirrus_device *cirrus = to_cirrus(fb->dev);
@@ -345,7 +346,8 @@ static int cirrus_fb_blit_rect(struct drm_framebuffer *fb, const struct dma_buf_ · 25 unmodified lines
345346 return 0;
346347 }
347348
348−static int cirrus_fb_blit_fullscreen(struct drm_framebuffer *fb, const struct dma_buf_map *map)
349+static int cirrus_fb_blit_fullscreen(struct drm_framebuffer *fb,
350+ const struct iosys_map *map)
349351 {
350352 struct drm_rect fullscreen = {
351353 .x1 = 0,
drivers/gpu/drm/tiny/gm12u320.c+4−3
@@ -95,7 +95,7 @@ struct gm12u320_device { · 94 unmodified lines
9595 struct drm_rect rect;
9696 int frame;
9797 int draw_status_timeout;
98− struct dma_buf_map src_map;
98+ struct iosys_map src_map;
9999 } fb_update;
100100 };
101101
@@ -395,7 +395,8 @@ err: · 293 unmodified lines
395395 GM12U320_ERR("Frame update error: %d\n", ret);
396396 }
397397
398−static void gm12u320_fb_mark_dirty(struct drm_framebuffer *fb, const struct dma_buf_map *map,
398+static void gm12u320_fb_mark_dirty(struct drm_framebuffer *fb,
399+ const struct iosys_map *map,
399400 struct drm_rect *dirty)
400401 {
401402 struct gm12u320_device *gm12u320 = to_gm12u320(fb->dev);
@@ -438,7 +439,7 @@ static void gm12u320_stop_fb_update(struct gm12u320_device *gm12u320) · 36 unmodified lines
438439 mutex_lock(&gm12u320->fb_update.lock);
439440 old_fb = gm12u320->fb_update.fb;
440441 gm12u320->fb_update.fb = NULL;
441− dma_buf_map_clear(&gm12u320->fb_update.src_map);
442+ iosys_map_clear(&gm12u320->fb_update.src_map);
442443 mutex_unlock(&gm12u320->fb_update.lock);
443444
444445 drm_framebuffer_put(old_fb);
drivers/gpu/drm/ttm/ttm_bo_util.c+8−8
@@ -33,7 +33,7 @@ · 32 unmodified lines
3333 #include <drm/ttm/ttm_placement.h>
3434 #include <drm/drm_cache.h>
3535 #include <drm/drm_vma_manager.h>
36−#include <linux/dma-buf-map.h>
36+#include <linux/iosys-map.h>
3737 #include <linux/io.h>
3838 #include <linux/highmem.h>
3939 #include <linux/wait.h>
@@ -93,7 +93,7 @@ void ttm_move_memcpy(bool clear, · 53 unmodified lines
9393 {
9494 const struct ttm_kmap_iter_ops *dst_ops = dst_iter->ops;
9595 const struct ttm_kmap_iter_ops *src_ops = src_iter->ops;
96− struct dma_buf_map src_map, dst_map;
96+ struct iosys_map src_map, dst_map;
9797 pgoff_t i;
9898
9999 /* Single TTM move. NOP */
@@ -390,7 +390,7 @@ void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map) · 290 unmodified lines
390390 }
391391 EXPORT_SYMBOL(ttm_bo_kunmap);
392392
393−int ttm_bo_vmap(struct ttm_buffer_object *bo, struct dma_buf_map *map)
393+int ttm_bo_vmap(struct ttm_buffer_object *bo, struct iosys_map *map)
394394 {
395395 struct ttm_resource *mem = bo->resource;
396396 int ret;
@@ -418,7 +418,7 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct dma_buf_map *map) · 21 unmodified lines
418418 if (!vaddr_iomem)
419419 return -ENOMEM;
420420
421− dma_buf_map_set_vaddr_iomem(map, vaddr_iomem);
421+ iosys_map_set_vaddr_iomem(map, vaddr_iomem);
422422
423423 } else {
424424 struct ttm_operation_ctx ctx = {
@@ -442,25 +442,25 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct dma_buf_map *map) · 17 unmodified lines
442442 if (!vaddr)
443443 return -ENOMEM;
444444
445− dma_buf_map_set_vaddr(map, vaddr);
445+ iosys_map_set_vaddr(map, vaddr);
446446 }
447447
448448 return 0;
449449 }
450450 EXPORT_SYMBOL(ttm_bo_vmap);
451451
452−void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct dma_buf_map *map)
452+void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct iosys_map *map)
453453 {
454454 struct ttm_resource *mem = bo->resource;
455455
456− if (dma_buf_map_is_null(map))
456+ if (iosys_map_is_null(map))
457457 return;
458458
459459 if (!map->is_iomem)
460460 vunmap(map->vaddr);
461461 else if (!mem->bus.addr)
462462 iounmap(map->vaddr_iomem);
463− dma_buf_map_clear(map);
463+ iosys_map_clear(map);
464464
465465 ttm_mem_io_free(bo->bdev, bo->resource);
466466 }
drivers/gpu/drm/ttm/ttm_resource.c+21−21
@@ -22,7 +22,7 @@ · 21 unmodified lines
2222 * Authors: Christian König
2323 */
2424
25−#include <linux/dma-buf-map.h>
25+#include <linux/iosys-map.h>
2626 #include <linux/io-mapping.h>
2727 #include <linux/scatterlist.h>
2828
@@ -244,7 +244,7 @@ void ttm_resource_manager_debug(struct ttm_resource_manager *man, · 215 unmodified lines
244244 EXPORT_SYMBOL(ttm_resource_manager_debug);
245245
246246 static void ttm_kmap_iter_iomap_map_local(struct ttm_kmap_iter *iter,
247− struct dma_buf_map *dmap,
247+ struct iosys_map *dmap,
248248 pgoff_t i)
249249 {
250250 struct ttm_kmap_iter_iomap *iter_io =
@@ -271,11 +271,11 @@ retry: · 20 unmodified lines
271271 addr = io_mapping_map_local_wc(iter_io->iomap, iter_io->cache.offs +
272272 (((resource_size_t)i - iter_io->cache.i)
273273 << PAGE_SHIFT));
274− dma_buf_map_set_vaddr_iomem(dmap, addr);
274+ iosys_map_set_vaddr_iomem(dmap, addr);
275275 }
276276
277277 static void ttm_kmap_iter_iomap_unmap_local(struct ttm_kmap_iter *iter,
278− struct dma_buf_map *map)
278+ struct iosys_map *map)
279279 {
280280 io_mapping_unmap_local(map->vaddr_iomem);
281281 }
@@ -326,14 +326,14 @@ EXPORT_SYMBOL(ttm_kmap_iter_iomap_init); · 44 unmodified lines
326326 */
327327
328328 static void ttm_kmap_iter_linear_io_map_local(struct ttm_kmap_iter *iter,
329− struct dma_buf_map *dmap,
329+ struct iosys_map *dmap,
330330 pgoff_t i)
331331 {
332332 struct ttm_kmap_iter_linear_io *iter_io =
333333 container_of(iter, typeof(*iter_io), base);
334334
335335 *dmap = iter_io->dmap;
336− dma_buf_map_incr(dmap, i * PAGE_SIZE);
336+ iosys_map_incr(dmap, i * PAGE_SIZE);
337337 }
338338
339339 static const struct ttm_kmap_iter_ops ttm_kmap_iter_linear_io_ops = {
@@ -369,7 +369,7 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, · 29 unmodified lines
369369 }
370370
371371 if (mem->bus.addr) {
372− dma_buf_map_set_vaddr(&iter_io->dmap, mem->bus.addr);
372+ iosys_map_set_vaddr(&iter_io->dmap, mem->bus.addr);
373373 iter_io->needs_unmap = false;
374374 } else {
375375 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
@@ -377,23 +377,23 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, · 1 unmodified line
377377 iter_io->needs_unmap = true;
378378 memset(&iter_io->dmap, 0, sizeof(iter_io->dmap));
379379 if (mem->bus.caching == ttm_write_combined)
380− dma_buf_map_set_vaddr_iomem(&iter_io->dmap,
381− ioremap_wc(mem->bus.offset,
382− bus_size));
380+ iosys_map_set_vaddr_iomem(&iter_io->dmap,
381+ ioremap_wc(mem->bus.offset,
382+ bus_size));
383383 else if (mem->bus.caching == ttm_cached)
384− dma_buf_map_set_vaddr(&iter_io->dmap,
385− memremap(mem->bus.offset, bus_size,
386− MEMREMAP_WB |
387− MEMREMAP_WT |
388− MEMREMAP_WC));
384+ iosys_map_set_vaddr(&iter_io->dmap,
385+ memremap(mem->bus.offset, bus_size,
386+ MEMREMAP_WB |
387+ MEMREMAP_WT |
388+ MEMREMAP_WC));
389389
390390 /* If uncached requested or if mapping cached or wc failed */
391− if (dma_buf_map_is_null(&iter_io->dmap))
392− dma_buf_map_set_vaddr_iomem(&iter_io->dmap,
393− ioremap(mem->bus.offset,
394− bus_size));
391+ if (iosys_map_is_null(&iter_io->dmap))
392+ iosys_map_set_vaddr_iomem(&iter_io->dmap,
393+ ioremap(mem->bus.offset,
394+ bus_size));
395395
396− if (dma_buf_map_is_null(&iter_io->dmap)) {
396+ if (iosys_map_is_null(&iter_io->dmap)) {
397397 ret = -ENOMEM;
398398 goto out_io_free;
399399 }
@@ -422,7 +422,7 @@ ttm_kmap_iter_linear_io_fini(struct ttm_kmap_iter_linear_io *iter_io, · 22 unmodified lines
422422 struct ttm_device *bdev,
423423 struct ttm_resource *mem)
424424 {
425− if (iter_io->needs_unmap && dma_buf_map_is_set(&iter_io->dmap)) {
425+ if (iter_io->needs_unmap && iosys_map_is_set(&iter_io->dmap)) {
426426 if (iter_io->dmap.is_iomem)
427427 iounmap(iter_io->dmap.vaddr_iomem);
428428 else
drivers/gpu/drm/ttm/ttm_tt.c+4−4
@@ -406,18 +406,18 @@ void ttm_tt_mgr_init(unsigned long num_pages, unsigned long num_dma32_pages) · 405 unmodified lines
406406 }
407407
408408 static void ttm_kmap_iter_tt_map_local(struct ttm_kmap_iter *iter,
409− struct dma_buf_map *dmap,
409+ struct iosys_map *dmap,
410410 pgoff_t i)
411411 {
412412 struct ttm_kmap_iter_tt *iter_tt =
413413 container_of(iter, typeof(*iter_tt), base);
414414
415− dma_buf_map_set_vaddr(dmap, kmap_local_page_prot(iter_tt->tt->pages[i],
416− iter_tt->prot));
415+ iosys_map_set_vaddr(dmap, kmap_local_page_prot(iter_tt->tt->pages[i],
416+ iter_tt->prot));
417417 }
418418
419419 static void ttm_kmap_iter_tt_unmap_local(struct ttm_kmap_iter *iter,
420− struct dma_buf_map *map)
420+ struct iosys_map *map)
421421 {
422422 kunmap_local(map->vaddr);
423423 }
drivers/gpu/drm/udl/udl_modeset.c+2−1
@@ -264,7 +264,8 @@ static int udl_aligned_damage_clip(struct drm_rect *clip, int x, int y, · 263 unmodified lines
264264 return 0;
265265 }
266266
267−static int udl_handle_damage(struct drm_framebuffer *fb, const struct dma_buf_map *map,
267+static int udl_handle_damage(struct drm_framebuffer *fb,
268+ const struct iosys_map *map,
268269 int x, int y, int width, int height)
269270 {
270271 struct drm_device *dev = fb->dev;
drivers/gpu/drm/vboxvideo/vbox_mode.c+2−2
@@ -10,7 +10,7 @@ · 9 unmodified lines
1010 * Hans de Goede <hdegoede@redhat.com>
1111 */
1212
13−#include <linux/dma-buf-map.h>
13+#include <linux/iosys-map.h>
1414 #include <linux/export.h>
1515
1616 #include <drm/drm_atomic.h>
@@ -398,7 +398,7 @@ static void vbox_cursor_atomic_update(struct drm_plane *plane, · 381 unmodified lines
398398 u32 height = new_state->crtc_h;
399399 struct drm_shadow_plane_state *shadow_plane_state =
400400 to_drm_shadow_plane_state(new_state);
401− struct dma_buf_map map = shadow_plane_state->data[0];
401+ struct iosys_map map = shadow_plane_state->data[0];
402402 u8 *src = map.vaddr; /* TODO: Use mapping abstraction properly */
403403 size_t data_size, mask_size;
404404 u32 flags;
drivers/gpu/drm/vkms/vkms_composer.c+2−2
@@ -157,7 +157,7 @@ static void compose_plane(struct vkms_composer *primary_composer, · 156 unmodified lines
157157 void *vaddr;
158158 void (*pixel_blend)(const u8 *p_src, u8 *p_dst);
159159
160− if (WARN_ON(dma_buf_map_is_null(&primary_composer->map[0])))
160+ if (WARN_ON(iosys_map_is_null(&primary_composer->map[0])))
161161 return;
162162
163163 vaddr = plane_composer->map[0].vaddr;
@@ -187,7 +187,7 @@ static int compose_active_planes(void **vaddr_out, · 23 unmodified lines
187187 }
188188 }
189189
190− if (WARN_ON(dma_buf_map_is_null(&primary_composer->map[0])))
190+ if (WARN_ON(iosys_map_is_null(&primary_composer->map[0])))
191191 return -EINVAL;
192192
193193 vaddr = primary_composer->map[0].vaddr;
drivers/gpu/drm/vkms/vkms_drv.h+3−3
@@ -23,14 +23,14 @@ · 22 unmodified lines
2323 #define NUM_OVERLAY_PLANES 8
2424
2525 struct vkms_writeback_job {
26− struct dma_buf_map map[DRM_FORMAT_MAX_PLANES];
27− struct dma_buf_map data[DRM_FORMAT_MAX_PLANES];
26+ struct iosys_map map[DRM_FORMAT_MAX_PLANES];
27+ struct iosys_map data[DRM_FORMAT_MAX_PLANES];
2828 };
2929
3030 struct vkms_composer {
3131 struct drm_framebuffer fb;
3232 struct drm_rect src, dst;
33− struct dma_buf_map map[4];
33+ struct iosys_map map[4];
3434 unsigned int offset;
3535 unsigned int pitch;
3636 unsigned int cpp;
drivers/gpu/drm/vkms/vkms_plane.c+1−1
@@ -1,6 +1,6 @@
11 // SPDX-License-Identifier: GPL-2.0+
22
3−#include <linux/dma-buf-map.h>
3+#include <linux/iosys-map.h>
44
55 #include <drm/drm_atomic.h>
66 #include <drm/drm_atomic_helper.h>
drivers/gpu/drm/vkms/vkms_writeback.c+1−1
@@ -1,6 +1,6 @@
11 // SPDX-License-Identifier: GPL-2.0+
22
3−#include <linux/dma-buf-map.h>
3+#include <linux/iosys-map.h>
44
55 #include <drm/drm_atomic.h>
66 #include <drm/drm_fourcc.h>
drivers/gpu/drm/xen/xen_drm_front_gem.c+4−3
@@ -280,7 +280,8 @@ xen_drm_front_gem_import_sg_table(struct drm_device *dev, · 279 unmodified lines
280280 return &xen_obj->base;
281281 }
282282
283−int xen_drm_front_gem_prime_vmap(struct drm_gem_object *gem_obj, struct dma_buf_map *map)
283+int xen_drm_front_gem_prime_vmap(struct drm_gem_object *gem_obj,
284+ struct iosys_map *map)
284285 {
285286 struct xen_gem_object *xen_obj = to_xen_gem_obj(gem_obj);
286287 void *vaddr;
@@ -293,13 +294,13 @@ int xen_drm_front_gem_prime_vmap(struct drm_gem_object *gem_obj, struct dma_buf_ · 6 unmodified lines
293294 VM_MAP, PAGE_KERNEL);
294295 if (!vaddr)
295296 return -ENOMEM;
296− dma_buf_map_set_vaddr(map, vaddr);
297+ iosys_map_set_vaddr(map, vaddr);
297298
298299 return 0;
299300 }
300301
301302 void xen_drm_front_gem_prime_vunmap(struct drm_gem_object *gem_obj,
302− struct dma_buf_map *map)
303+ struct iosys_map *map)
303304 {
304305 vunmap(map->vaddr);
305306 }
drivers/gpu/drm/xen/xen_drm_front_gem.h+3−3
@@ -12,7 +12,7 @@ · 11 unmodified lines
1212 #define __XEN_DRM_FRONT_GEM_H
1313
1414 struct dma_buf_attachment;
15−struct dma_buf_map;
15+struct iosys_map;
1616 struct drm_device;
1717 struct drm_gem_object;
1818 struct sg_table;
@@ -32,9 +32,9 @@ struct page **xen_drm_front_gem_get_pages(struct drm_gem_object *obj); · 13 unmodified lines
3232 void xen_drm_front_gem_free_object_unlocked(struct drm_gem_object *gem_obj);
3333
3434 int xen_drm_front_gem_prime_vmap(struct drm_gem_object *gem_obj,
35− struct dma_buf_map *map);
35+ struct iosys_map *map);
3636
3737 void xen_drm_front_gem_prime_vunmap(struct drm_gem_object *gem_obj,
38− struct dma_buf_map *map);
38+ struct iosys_map *map);
3939
4040 #endif /* __XEN_DRM_FRONT_GEM_H */
drivers/media/common/videobuf2/videobuf2-dma-contig.c+4−4
@@ -99,7 +99,7 @@ static void *vb2_dc_vaddr(struct vb2_buffer *vb, void *buf_priv) · 98 unmodified lines
9999 return buf->vaddr;
100100
101101 if (buf->db_attach) {
102− struct dma_buf_map map;
102+ struct iosys_map map;
103103
104104 if (!dma_buf_vmap(buf->db_attach->dmabuf, &map))
105105 buf->vaddr = map.vaddr;
@@ -446,7 +446,7 @@ vb2_dc_dmabuf_ops_end_cpu_access(struct dma_buf *dbuf, · 340 unmodified lines
446446 return 0;
447447 }
448448
449−static int vb2_dc_dmabuf_ops_vmap(struct dma_buf *dbuf, struct dma_buf_map *map)
449+static int vb2_dc_dmabuf_ops_vmap(struct dma_buf *dbuf, struct iosys_map *map)
450450 {
451451 struct vb2_dc_buf *buf;
452452 void *vaddr;
@@ -456,7 +456,7 @@ static int vb2_dc_dmabuf_ops_vmap(struct dma_buf *dbuf, struct dma_buf_map *map) · 3 unmodified lines
456456 if (!vaddr)
457457 return -EINVAL;
458458
459− dma_buf_map_set_vaddr(map, vaddr);
459+ iosys_map_set_vaddr(map, vaddr);
460460
461461 return 0;
462462 }
@@ -737,7 +737,7 @@ static void vb2_dc_unmap_dmabuf(void *mem_priv) · 274 unmodified lines
737737 {
738738 struct vb2_dc_buf *buf = mem_priv;
739739 struct sg_table *sgt = buf->dma_sgt;
740− struct dma_buf_map map = DMA_BUF_MAP_INIT_VADDR(buf->vaddr);
740+ struct iosys_map map = IOSYS_MAP_INIT_VADDR(buf->vaddr);
741741
742742 if (WARN_ON(!buf->db_attach)) {
743743 pr_err("trying to unpin a not attached buffer\n");
drivers/media/common/videobuf2/videobuf2-dma-sg.c+5−4
@@ -303,7 +303,7 @@ static void vb2_dma_sg_put_userptr(void *buf_priv) · 302 unmodified lines
303303 static void *vb2_dma_sg_vaddr(struct vb2_buffer *vb, void *buf_priv)
304304 {
305305 struct vb2_dma_sg_buf *buf = buf_priv;
306− struct dma_buf_map map;
306+ struct iosys_map map;
307307 int ret;
308308
309309 BUG_ON(!buf);
@@ -492,11 +492,12 @@ vb2_dma_sg_dmabuf_ops_end_cpu_access(struct dma_buf *dbuf, · 182 unmodified lines
492492 return 0;
493493 }
494494
495−static int vb2_dma_sg_dmabuf_ops_vmap(struct dma_buf *dbuf, struct dma_buf_map *map)
495+static int vb2_dma_sg_dmabuf_ops_vmap(struct dma_buf *dbuf,
496+ struct iosys_map *map)
496497 {
497498 struct vb2_dma_sg_buf *buf = dbuf->priv;
498499
499− dma_buf_map_set_vaddr(map, buf->vaddr);
500+ iosys_map_set_vaddr(map, buf->vaddr);
500501
501502 return 0;
502503 }
@@ -581,7 +582,7 @@ static void vb2_dma_sg_unmap_dmabuf(void *mem_priv) · 78 unmodified lines
581582 {
582583 struct vb2_dma_sg_buf *buf = mem_priv;
583584 struct sg_table *sgt = buf->dma_sgt;
584− struct dma_buf_map map = DMA_BUF_MAP_INIT_VADDR(buf->vaddr);
585+ struct iosys_map map = IOSYS_MAP_INIT_VADDR(buf->vaddr);
585586
586587 if (WARN_ON(!buf->db_attach)) {
587588 pr_err("trying to unpin a not attached buffer\n");
drivers/media/common/videobuf2/videobuf2-vmalloc.c+6−5
@@ -312,11 +312,12 @@ static void vb2_vmalloc_dmabuf_ops_release(struct dma_buf *dbuf) · 311 unmodified lines
312312 vb2_vmalloc_put(dbuf->priv);
313313 }
314314
315−static int vb2_vmalloc_dmabuf_ops_vmap(struct dma_buf *dbuf, struct dma_buf_map *map)
315+static int vb2_vmalloc_dmabuf_ops_vmap(struct dma_buf *dbuf,
316+ struct iosys_map *map)
316317 {
317318 struct vb2_vmalloc_buf *buf = dbuf->priv;
318319
319− dma_buf_map_set_vaddr(map, buf->vaddr);
320+ iosys_map_set_vaddr(map, buf->vaddr);
320321
321322 return 0;
322323 }
@@ -372,7 +373,7 @@ static struct dma_buf *vb2_vmalloc_get_dmabuf(struct vb2_buffer *vb, · 49 unmodified lines
372373 static int vb2_vmalloc_map_dmabuf(void *mem_priv)
373374 {
374375 struct vb2_vmalloc_buf *buf = mem_priv;
375− struct dma_buf_map map;
376+ struct iosys_map map;
376377 int ret;
377378
378379 ret = dma_buf_vmap(buf->dbuf, &map);
@@ -386,7 +387,7 @@ static int vb2_vmalloc_map_dmabuf(void *mem_priv) · 7 unmodified lines
386387 static void vb2_vmalloc_unmap_dmabuf(void *mem_priv)
387388 {
388389 struct vb2_vmalloc_buf *buf = mem_priv;
389− struct dma_buf_map map = DMA_BUF_MAP_INIT_VADDR(buf->vaddr);
390+ struct iosys_map map = IOSYS_MAP_INIT_VADDR(buf->vaddr);
390391
391392 dma_buf_vunmap(buf->dbuf, &map);
392393 buf->vaddr = NULL;
@@ -395,7 +396,7 @@ static void vb2_vmalloc_unmap_dmabuf(void *mem_priv) · 2 unmodified lines
395396 static void vb2_vmalloc_detach_dmabuf(void *mem_priv)
396397 {
397398 struct vb2_vmalloc_buf *buf = mem_priv;
398− struct dma_buf_map map = DMA_BUF_MAP_INIT_VADDR(buf->vaddr);
399+ struct iosys_map map = IOSYS_MAP_INIT_VADDR(buf->vaddr);
399400
400401 if (buf->vaddr)
401402 dma_buf_vunmap(buf->dbuf, &map);
drivers/misc/fastrpc.c+2−2
@@ -587,11 +587,11 @@ static void fastrpc_dma_buf_detatch(struct dma_buf *dmabuf, · 586 unmodified lines
587587 kfree(a);
588588 }
589589
590−static int fastrpc_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map)
590+static int fastrpc_vmap(struct dma_buf *dmabuf, struct iosys_map *map)
591591 {
592592 struct fastrpc_buf *buf = dmabuf->priv;
593593
594− dma_buf_map_set_vaddr(map, buf->virt);
594+ iosys_map_set_vaddr(map, buf->virt);
595595
596596 return 0;
597597 }
include/drm/drm_cache.h+3−3
@@ -35,7 +35,7 @@ · 34 unmodified lines
3535
3636 #include <linux/scatterlist.h>
3737
38−struct dma_buf_map;
38+struct iosys_map;
3939
4040 void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
4141 void drm_clflush_sg(struct sg_table *st);
@@ -74,7 +74,7 @@ static inline bool drm_arch_can_wc_memory(void) · 32 unmodified lines
7474
7575 void drm_memcpy_init_early(void);
7676
77−void drm_memcpy_from_wc(struct dma_buf_map *dst,
78− const struct dma_buf_map *src,
77+void drm_memcpy_from_wc(struct iosys_map *dst,
78+ const struct iosys_map *src,
7979 unsigned long len);
8080 #endif
include/drm/drm_client.h+4−3
@@ -3,7 +3,7 @@ · 2 unmodified lines
33 #ifndef _DRM_CLIENT_H_
44 #define _DRM_CLIENT_H_
55
6−#include <linux/dma-buf-map.h>
6+#include <linux/iosys-map.h>
77 #include <linux/lockdep.h>
88 #include <linux/mutex.h>
99 #include <linux/types.h>
@@ -144,7 +144,7 @@ struct drm_client_buffer { · 134 unmodified lines
144144 /**
145145 * @map: Virtual address for the buffer
146146 */
147− struct dma_buf_map map;
147+ struct iosys_map map;
148148
149149 /**
150150 * @fb: DRM framebuffer
@@ -156,7 +156,8 @@ struct drm_client_buffer * · 5 unmodified lines
156156 drm_client_framebuffer_create(struct drm_client_dev *client, u32 width, u32 height, u32 format);
157157 void drm_client_framebuffer_delete(struct drm_client_buffer *buffer);
158158 int drm_client_framebuffer_flush(struct drm_client_buffer *buffer, struct drm_rect *rect);
159−int drm_client_buffer_vmap(struct drm_client_buffer *buffer, struct dma_buf_map *map);
159+int drm_client_buffer_vmap(struct drm_client_buffer *buffer,
160+ struct iosys_map *map);
160161 void drm_client_buffer_vunmap(struct drm_client_buffer *buffer);
161162
162163 int drm_client_modeset_create(struct drm_client_dev *client);
include/drm/drm_crtc.h+0−2
@@ -1145,14 +1145,12 @@ struct drm_crtc { · 1144 unmodified lines
11451145 */
11461146 spinlock_t commit_lock;
11471147
1148−#ifdef CONFIG_DEBUG_FS
11491148 /**
11501149 * @debugfs_entry:
11511150 *
11521151 * Debugfs directory for this CRTC.
11531152 */
11541153 struct dentry *debugfs_entry;
1155−#endif
11561154
11571155 /**
11581156 * @crc:
include/drm/drm_gem.h+3−3
@@ -39,7 +39,7 @@ · 38 unmodified lines
3939
4040 #include <drm/drm_vma_manager.h>
4141
42−struct dma_buf_map;
42+struct iosys_map;
4343 struct drm_gem_object;
4444
4545 /**
@@ -139,7 +139,7 @@ struct drm_gem_object_funcs { · 93 unmodified lines
139139 *
140140 * This callback is optional.
141141 */
142− int (*vmap)(struct drm_gem_object *obj, struct dma_buf_map *map);
142+ int (*vmap)(struct drm_gem_object *obj, struct iosys_map *map);
143143
144144 /**
145145 * @vunmap:
@@ -149,7 +149,7 @@ struct drm_gem_object_funcs { · 3 unmodified lines
149149 *
150150 * This callback is optional.
151151 */
152− void (*vunmap)(struct drm_gem_object *obj, struct dma_buf_map *map);
152+ void (*vunmap)(struct drm_gem_object *obj, struct iosys_map *map);
153153
154154 /**
155155 * @mmap:
include/drm/drm_gem_atomic_helper.h+3−3
@@ -3,7 +3,7 @@ · 2 unmodified lines
33 #ifndef __DRM_GEM_ATOMIC_HELPER_H__
44 #define __DRM_GEM_ATOMIC_HELPER_H__
55
6−#include <linux/dma-buf-map.h>
6+#include <linux/iosys-map.h>
77
88 #include <drm/drm_fourcc.h>
99 #include <drm/drm_plane.h>
@@ -59,7 +59,7 @@ struct drm_shadow_plane_state { · 49 unmodified lines
5959 * The memory mappings stored in map should be established in the plane's
6060 * prepare_fb callback and removed in the cleanup_fb callback.
6161 */
62− struct dma_buf_map map[DRM_FORMAT_MAX_PLANES];
62+ struct iosys_map map[DRM_FORMAT_MAX_PLANES];
6363
6464 /**
6565 * @data: Address of each framebuffer BO's data
@@ -67,7 +67,7 @@ struct drm_shadow_plane_state { · 1 unmodified line
6767 * The address of the data stored in each mapping. This is different
6868 * for framebuffers with non-zero offset fields.
6969 */
70− struct dma_buf_map data[DRM_FORMAT_MAX_PLANES];
70+ struct iosys_map data[DRM_FORMAT_MAX_PLANES];
7171 };
7272
7373 /**
include/drm/drm_gem_cma_helper.h+4−2
@@ -38,7 +38,8 @@ void drm_gem_cma_free(struct drm_gem_cma_object *cma_obj); · 37 unmodified lines
3838 void drm_gem_cma_print_info(const struct drm_gem_cma_object *cma_obj,
3939 struct drm_printer *p, unsigned int indent);
4040 struct sg_table *drm_gem_cma_get_sg_table(struct drm_gem_cma_object *cma_obj);
41−int drm_gem_cma_vmap(struct drm_gem_cma_object *cma_obj, struct dma_buf_map *map);
41+int drm_gem_cma_vmap(struct drm_gem_cma_object *cma_obj,
42+ struct iosys_map *map);
4243 int drm_gem_cma_mmap(struct drm_gem_cma_object *cma_obj, struct vm_area_struct *vma);
4344
4445 extern const struct vm_operations_struct drm_gem_cma_vm_ops;
@@ -106,7 +107,8 @@ static inline struct sg_table *drm_gem_cma_object_get_sg_table(struct drm_gem_ob · 61 unmodified lines
106107 * Returns:
107108 * 0 on success or a negative error code on failure.
108109 */
109−static inline int drm_gem_cma_object_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
110+static inline int drm_gem_cma_object_vmap(struct drm_gem_object *obj,
111+ struct iosys_map *map)
110112 {
111113 struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(obj);
112114
include/drm/drm_gem_framebuffer_helper.h+4−4
@@ -2,7 +2,7 @@ · 1 unmodified line
22 #define __DRM_GEM_FB_HELPER_H__
33
44 #include <linux/dma-buf.h>
5−#include <linux/dma-buf-map.h>
5+#include <linux/iosys-map.h>
66
77 #include <drm/drm_fourcc.h>
88
@@ -40,10 +40,10 @@ drm_gem_fb_create_with_dirty(struct drm_device *dev, struct drm_file *file, · 31 unmodified lines
4040 const struct drm_mode_fb_cmd2 *mode_cmd);
4141
4242 int drm_gem_fb_vmap(struct drm_framebuffer *fb,
43− struct dma_buf_map map[static DRM_FORMAT_MAX_PLANES],
44− struct dma_buf_map data[DRM_FORMAT_MAX_PLANES]);
43+ struct iosys_map map[static DRM_FORMAT_MAX_PLANES],
44+ struct iosys_map data[DRM_FORMAT_MAX_PLANES]);
4545 void drm_gem_fb_vunmap(struct drm_framebuffer *fb,
46− struct dma_buf_map map[static DRM_FORMAT_MAX_PLANES]);
46+ struct iosys_map map[static DRM_FORMAT_MAX_PLANES]);
4747 int drm_gem_fb_begin_cpu_access(struct drm_framebuffer *fb, enum dma_data_direction dir);
4848 void drm_gem_fb_end_cpu_access(struct drm_framebuffer *fb, enum dma_data_direction dir);
4949
include/drm/drm_gem_shmem_helper.h+8−4
@@ -113,8 +113,10 @@ int drm_gem_shmem_get_pages(struct drm_gem_shmem_object *shmem); · 112 unmodified lines
113113 void drm_gem_shmem_put_pages(struct drm_gem_shmem_object *shmem);
114114 int drm_gem_shmem_pin(struct drm_gem_shmem_object *shmem);
115115 void drm_gem_shmem_unpin(struct drm_gem_shmem_object *shmem);
116−int drm_gem_shmem_vmap(struct drm_gem_shmem_object *shmem, struct dma_buf_map *map);
117−void drm_gem_shmem_vunmap(struct drm_gem_shmem_object *shmem, struct dma_buf_map *map);
116+int drm_gem_shmem_vmap(struct drm_gem_shmem_object *shmem,
117+ struct iosys_map *map);
118+void drm_gem_shmem_vunmap(struct drm_gem_shmem_object *shmem,
119+ struct iosys_map *map);
118120 int drm_gem_shmem_mmap(struct drm_gem_shmem_object *shmem, struct vm_area_struct *vma);
119121
120122 int drm_gem_shmem_madvise(struct drm_gem_shmem_object *shmem, int madv);
@@ -226,7 +228,8 @@ static inline struct sg_table *drm_gem_shmem_object_get_sg_table(struct drm_gem_ · 105 unmodified lines
226228 * Returns:
227229 * 0 on success or a negative error code on failure.
228230 */
229−static inline int drm_gem_shmem_object_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
231+static inline int drm_gem_shmem_object_vmap(struct drm_gem_object *obj,
232+ struct iosys_map *map)
230233 {
231234 struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
232235
@@ -241,7 +244,8 @@ static inline int drm_gem_shmem_object_vmap(struct drm_gem_object *obj, struct d · 8 unmodified lines
241244 * This function wraps drm_gem_shmem_vunmap(). Drivers that employ the shmem helpers should
242245 * use it as their &drm_gem_object_funcs.vunmap handler.
243246 */
244−static inline void drm_gem_shmem_object_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map)
247+static inline void drm_gem_shmem_object_vunmap(struct drm_gem_object *obj,
248+ struct iosys_map *map)
245249 {
246250 struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
247251
include/drm/drm_gem_ttm_helper.h+3−3
@@ -10,7 +10,7 @@ · 9 unmodified lines
1010 #include <drm/ttm/ttm_bo_api.h>
1111 #include <drm/ttm/ttm_bo_driver.h>
1212
13−struct dma_buf_map;
13+struct iosys_map;
1414
1515 #define drm_gem_ttm_of_gem(gem_obj) \
1616 container_of(gem_obj, struct ttm_buffer_object, base)
@@ -18,9 +18,9 @@ struct dma_buf_map; · 1 unmodified line
1818 void drm_gem_ttm_print_info(struct drm_printer *p, unsigned int indent,
1919 const struct drm_gem_object *gem);
2020 int drm_gem_ttm_vmap(struct drm_gem_object *gem,
21− struct dma_buf_map *map);
21+ struct iosys_map *map);
2222 void drm_gem_ttm_vunmap(struct drm_gem_object *gem,
23− struct dma_buf_map *map);
23+ struct iosys_map *map);
2424 int drm_gem_ttm_mmap(struct drm_gem_object *gem,
2525 struct vm_area_struct *vma);
2626
include/drm/drm_gem_vram_helper.h+5−4
@@ -12,7 +12,7 @@ · 11 unmodified lines
1212 #include <drm/ttm/ttm_bo_driver.h>
1313
1414 #include <linux/container_of.h>
15−#include <linux/dma-buf-map.h>
15+#include <linux/iosys-map.h>
1616
1717 struct drm_mode_create_dumb;
1818 struct drm_plane;
@@ -51,7 +51,7 @@ struct vm_area_struct; · 32 unmodified lines
5151 */
5252 struct drm_gem_vram_object {
5353 struct ttm_buffer_object bo;
54− struct dma_buf_map map;
54+ struct iosys_map map;
5555
5656 /**
5757 * @vmap_use_count:
@@ -97,8 +97,9 @@ void drm_gem_vram_put(struct drm_gem_vram_object *gbo); · 39 unmodified lines
9797 s64 drm_gem_vram_offset(struct drm_gem_vram_object *gbo);
9898 int drm_gem_vram_pin(struct drm_gem_vram_object *gbo, unsigned long pl_flag);
9999 int drm_gem_vram_unpin(struct drm_gem_vram_object *gbo);
100−int drm_gem_vram_vmap(struct drm_gem_vram_object *gbo, struct dma_buf_map *map);
101−void drm_gem_vram_vunmap(struct drm_gem_vram_object *gbo, struct dma_buf_map *map);
100+int drm_gem_vram_vmap(struct drm_gem_vram_object *gbo, struct iosys_map *map);
101+void drm_gem_vram_vunmap(struct drm_gem_vram_object *gbo,
102+ struct iosys_map *map);
102103
103104 int drm_gem_vram_fill_create_dumb(struct drm_file *file,
104105 struct drm_device *dev,
include/drm/drm_prime.h+3−3
@@ -54,7 +54,7 @@ struct device; · 53 unmodified lines
5454 struct dma_buf_export_info;
5555 struct dma_buf;
5656 struct dma_buf_attachment;
57−struct dma_buf_map;
57+struct iosys_map;
5858
5959 enum dma_data_direction;
6060
@@ -83,8 +83,8 @@ struct sg_table *drm_gem_map_dma_buf(struct dma_buf_attachment *attach, · 22 unmodified lines
8383 void drm_gem_unmap_dma_buf(struct dma_buf_attachment *attach,
8484 struct sg_table *sgt,
8585 enum dma_data_direction dir);
86−int drm_gem_dmabuf_vmap(struct dma_buf *dma_buf, struct dma_buf_map *map);
87−void drm_gem_dmabuf_vunmap(struct dma_buf *dma_buf, struct dma_buf_map *map);
86+int drm_gem_dmabuf_vmap(struct dma_buf *dma_buf, struct iosys_map *map);
87+void drm_gem_dmabuf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map);
8888
8989 int drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
9090 int drm_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma);
include/drm/i915_pciids.h+6−0
@@ -666,6 +666,12 @@ · 665 unmodified lines
666666 INTEL_VGA_DEVICE(0x46C2, info), \
667667 INTEL_VGA_DEVICE(0x46C3, info)
668668
669+/* ADL-N */
670+#define INTEL_ADLN_IDS(info) \
671+ INTEL_VGA_DEVICE(0x46D0, info), \
672+ INTEL_VGA_DEVICE(0x46D1, info), \
673+ INTEL_VGA_DEVICE(0x46D2, info)
674+
669675 /* RPL-S */
670676 #define INTEL_RPLS_IDS(info) \
671677 INTEL_VGA_DEVICE(0xA780, info), \
include/drm/ttm/ttm_bo_api.h+5−5
@@ -47,7 +47,7 @@ struct ttm_global; · 46 unmodified lines
4747
4848 struct ttm_device;
4949
50−struct dma_buf_map;
50+struct iosys_map;
5151
5252 struct drm_mm_node;
5353
@@ -481,17 +481,17 @@ void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map); · 427 unmodified lines
481481 * ttm_bo_vmap
482482 *
483483 * @bo: The buffer object.
484− * @map: pointer to a struct dma_buf_map representing the map.
484+ * @map: pointer to a struct iosys_map representing the map.
485485 *
486486 * Sets up a kernel virtual mapping, using ioremap or vmap to the
487487 * data in the buffer object. The parameter @map returns the virtual
488− * address as struct dma_buf_map. Unmap the buffer with ttm_bo_vunmap().
488+ * address as struct iosys_map. Unmap the buffer with ttm_bo_vunmap().
489489 *
490490 * Returns
491491 * -ENOMEM: Out of memory.
492492 * -EINVAL: Invalid range.
493493 */
494−int ttm_bo_vmap(struct ttm_buffer_object *bo, struct dma_buf_map *map);
494+int ttm_bo_vmap(struct ttm_buffer_object *bo, struct iosys_map *map);
495495
496496 /**
497497 * ttm_bo_vunmap
@@ -501,7 +501,7 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct dma_buf_map *map); · 3 unmodified lines
501501 *
502502 * Unmaps a kernel map set up by ttm_bo_vmap().
503503 */
504−void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct dma_buf_map *map);
504+void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct iosys_map *map);
505505
506506 /**
507507 * ttm_bo_mmap_obj - mmap memory backed by a ttm buffer object.
include/drm/ttm/ttm_kmap_iter.h+5−5
@@ -8,7 +8,7 @@ · 7 unmodified lines
88 #include <linux/types.h>
99
1010 struct ttm_kmap_iter;
11−struct dma_buf_map;
11+struct iosys_map;
1212
1313 /**
1414 * struct ttm_kmap_iter_ops - Ops structure for a struct
@@ -24,22 +24,22 @@ struct ttm_kmap_iter_ops { · 9 unmodified lines
2424 * kmap_local semantics.
2525 * @res_iter: Pointer to the struct ttm_kmap_iter representing
2626 * the resource.
27− * @dmap: The struct dma_buf_map holding the virtual address after
27+ * @dmap: The struct iosys_map holding the virtual address after
2828 * the operation.
2929 * @i: The location within the resource to map. PAGE_SIZE granularity.
3030 */
3131 void (*map_local)(struct ttm_kmap_iter *res_iter,
32− struct dma_buf_map *dmap, pgoff_t i);
32+ struct iosys_map *dmap, pgoff_t i);
3333 /**
3434 * unmap_local() - Unmap a PAGE_SIZE part of the resource previously
3535 * mapped using kmap_local.
3636 * @res_iter: Pointer to the struct ttm_kmap_iter representing
3737 * the resource.
38− * @dmap: The struct dma_buf_map holding the virtual address after
38+ * @dmap: The struct iosys_map holding the virtual address after
3939 * the operation.
4040 */
4141 void (*unmap_local)(struct ttm_kmap_iter *res_iter,
42− struct dma_buf_map *dmap);
42+ struct iosys_map *dmap);
4343 bool maps_tt;
4444 };
4545
include/drm/ttm/ttm_resource.h+3−3
@@ -27,7 +27,7 @@ · 26 unmodified lines
2727
2828 #include <linux/types.h>
2929 #include <linux/mutex.h>
30−#include <linux/dma-buf-map.h>
30+#include <linux/iosys-map.h>
3131 #include <linux/dma-fence.h>
3232 #include <drm/drm_print.h>
3333 #include <drm/ttm/ttm_caching.h>
@@ -41,7 +41,7 @@ struct ttm_resource; · 7 unmodified lines
4141 struct ttm_place;
4242 struct ttm_buffer_object;
4343 struct ttm_placement;
44−struct dma_buf_map;
44+struct iosys_map;
4545 struct io_mapping;
4646 struct sg_table;
4747 struct scatterlist;
@@ -210,7 +210,7 @@ struct ttm_kmap_iter_iomap { · 162 unmodified lines
210210 */
211211 struct ttm_kmap_iter_linear_io {
212212 struct ttm_kmap_iter base;
213− struct dma_buf_map dmap;
213+ struct iosys_map dmap;
214214 bool needs_unmap;
215215 };
216216
include/linux/dma-buf.h+6−6
@@ -13,7 +13,7 @@ · 12 unmodified lines
1313 #ifndef __DMA_BUF_H__
1414 #define __DMA_BUF_H__
1515
16−#include <linux/dma-buf-map.h>
16+#include <linux/iosys-map.h>
1717 #include <linux/file.h>
1818 #include <linux/err.h>
1919 #include <linux/scatterlist.h>
@@ -283,8 +283,8 @@ struct dma_buf_ops { · 263 unmodified lines
283283 */
284284 int (*mmap)(struct dma_buf *, struct vm_area_struct *vma);
285285
286− int (*vmap)(struct dma_buf *dmabuf, struct dma_buf_map *map);
287− void (*vunmap)(struct dma_buf *dmabuf, struct dma_buf_map *map);
286+ int (*vmap)(struct dma_buf *dmabuf, struct iosys_map *map);
287+ void (*vunmap)(struct dma_buf *dmabuf, struct iosys_map *map);
288288 };
289289
290290 /**
@@ -347,7 +347,7 @@ struct dma_buf { · 56 unmodified lines
347347 * @vmap_ptr:
348348 * The current vmap ptr if @vmapping_counter > 0. Protected by @lock.
349349 */
350− struct dma_buf_map vmap_ptr;
350+ struct iosys_map vmap_ptr;
351351
352352 /**
353353 * @exp_name:
@@ -628,6 +628,6 @@ int dma_buf_end_cpu_access(struct dma_buf *dma_buf, · 274 unmodified lines
628628
629629 int dma_buf_mmap(struct dma_buf *, struct vm_area_struct *,
630630 unsigned long);
631−int dma_buf_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map);
632−void dma_buf_vunmap(struct dma_buf *dmabuf, struct dma_buf_map *map);
631+int dma_buf_vmap(struct dma_buf *dmabuf, struct iosys_map *map);
632+void dma_buf_vunmap(struct dma_buf *dmabuf, struct iosys_map *map);
633633 #endif /* __DMA_BUF_H__ */
include/linux/iosys-map.h+257−0
@@ -0,0 +1,257 @@
1+/* SPDX-License-Identifier: GPL-2.0-only */
2+/*
3+ * Pointer abstraction for IO/system memory
4+ */
5+
6+#ifndef __IOSYS_MAP_H__
7+#define __IOSYS_MAP_H__
8+
9+#include <linux/io.h>
10+#include <linux/string.h>
11+
12+/**
13+ * DOC: overview
14+ *
15+ * When accessing a memory region, depending on its location, users may have to
16+ * access it with I/O operations or memory load/store operations. For example,
17+ * copying to system memory could be done with memcpy(), copying to I/O memory
18+ * would be done with memcpy_toio().
19+ *
20+ * .. code-block:: c
21+ *
22+ * void *vaddr = ...; // pointer to system memory
23+ * memcpy(vaddr, src, len);
24+ *
25+ * void *vaddr_iomem = ...; // pointer to I/O memory
26+ * memcpy_toio(vaddr, _iomem, src, len);
27+ *
28+ * The user of such pointer may not have information about the mapping of that
29+ * region or may want to have a single code path to handle operations on that
30+ * buffer, regardless if it's located in system or IO memory. The type
31+ * :c:type:`struct iosys_map <iosys_map>` and its helpers abstract that so the
32+ * buffer can be passed around to other drivers or have separate duties inside
33+ * the same driver for allocation, read and write operations.
34+ *
35+ * Open-coding access to :c:type:`struct iosys_map <iosys_map>` is considered
36+ * bad style. Rather then accessing its fields directly, use one of the provided
37+ * helper functions, or implement your own. For example, instances of
38+ * :c:type:`struct iosys_map <iosys_map>` can be initialized statically with
39+ * IOSYS_MAP_INIT_VADDR(), or at runtime with iosys_map_set_vaddr(). These
40+ * helpers will set an address in system memory.
41+ *
42+ * .. code-block:: c
43+ *
44+ * struct iosys_map map = IOSYS_MAP_INIT_VADDR(0xdeadbeaf);
45+ *
46+ * iosys_map_set_vaddr(&map, 0xdeadbeaf);
47+ *
48+ * To set an address in I/O memory, use iosys_map_set_vaddr_iomem().
49+ *
50+ * .. code-block:: c
51+ *
52+ * iosys_map_set_vaddr_iomem(&map, 0xdeadbeaf);
53+ *
54+ * Instances of struct iosys_map do not have to be cleaned up, but
55+ * can be cleared to NULL with iosys_map_clear(). Cleared mappings
56+ * always refer to system memory.
57+ *
58+ * .. code-block:: c
59+ *
60+ * iosys_map_clear(&map);
61+ *
62+ * Test if a mapping is valid with either iosys_map_is_set() or
63+ * iosys_map_is_null().
64+ *
65+ * .. code-block:: c
66+ *
67+ * if (iosys_map_is_set(&map) != iosys_map_is_null(&map))
68+ * // always true
69+ *
70+ * Instances of :c:type:`struct iosys_map <iosys_map>` can be compared for
71+ * equality with iosys_map_is_equal(). Mappings that point to different memory
72+ * spaces, system or I/O, are never equal. That's even true if both spaces are
73+ * located in the same address space, both mappings contain the same address
74+ * value, or both mappings refer to NULL.
75+ *
76+ * .. code-block:: c
77+ *
78+ * struct iosys_map sys_map; // refers to system memory
79+ * struct iosys_map io_map; // refers to I/O memory
80+ *
81+ * if (iosys_map_is_equal(&sys_map, &io_map))
82+ * // always false
83+ *
84+ * A set up instance of struct iosys_map can be used to access or manipulate the
85+ * buffer memory. Depending on the location of the memory, the provided helpers
86+ * will pick the correct operations. Data can be copied into the memory with
87+ * iosys_map_memcpy_to(). The address can be manipulated with iosys_map_incr().
88+ *
89+ * .. code-block:: c
90+ *
91+ * const void *src = ...; // source buffer
92+ * size_t len = ...; // length of src
93+ *
94+ * iosys_map_memcpy_to(&map, src, len);
95+ * iosys_map_incr(&map, len); // go to first byte after the memcpy
96+ */
97+
98+/**
99+ * struct iosys_map - Pointer to IO/system memory
100+ * @vaddr_iomem: The buffer's address if in I/O memory
101+ * @vaddr: The buffer's address if in system memory
102+ * @is_iomem: True if the buffer is located in I/O memory, or false
103+ * otherwise.
104+ */
105+struct iosys_map {
106+ union {
107+ void __iomem *vaddr_iomem;
108+ void *vaddr;
109+ };
110+ bool is_iomem;
111+};
112+
113+/**
114+ * IOSYS_MAP_INIT_VADDR - Initializes struct iosys_map to an address in system memory
115+ * @vaddr_: A system-memory address
116+ */
117+#define IOSYS_MAP_INIT_VADDR(vaddr_) \
118+ { \
119+ .vaddr = (vaddr_), \
120+ .is_iomem = false, \
121+ }
122+
123+/**
124+ * iosys_map_set_vaddr - Sets a iosys mapping structure to an address in system memory
125+ * @map: The iosys_map structure
126+ * @vaddr: A system-memory address
127+ *
128+ * Sets the address and clears the I/O-memory flag.
129+ */
130+static inline void iosys_map_set_vaddr(struct iosys_map *map, void *vaddr)
131+{
132+ map->vaddr = vaddr;
133+ map->is_iomem = false;
134+}
135+
136+/**
137+ * iosys_map_set_vaddr_iomem - Sets a iosys mapping structure to an address in I/O memory
138+ * @map: The iosys_map structure
139+ * @vaddr_iomem: An I/O-memory address
140+ *
141+ * Sets the address and the I/O-memory flag.
142+ */
143+static inline void iosys_map_set_vaddr_iomem(struct iosys_map *map,
144+ void __iomem *vaddr_iomem)
145+{
146+ map->vaddr_iomem = vaddr_iomem;
147+ map->is_iomem = true;
148+}
149+
150+/**
151+ * iosys_map_is_equal - Compares two iosys mapping structures for equality
152+ * @lhs: The iosys_map structure
153+ * @rhs: A iosys_map structure to compare with
154+ *
155+ * Two iosys mapping structures are equal if they both refer to the same type of memory
156+ * and to the same address within that memory.
157+ *
158+ * Returns:
159+ * True is both structures are equal, or false otherwise.
160+ */
161+static inline bool iosys_map_is_equal(const struct iosys_map *lhs,
162+ const struct iosys_map *rhs)
163+{
164+ if (lhs->is_iomem != rhs->is_iomem)
165+ return false;
166+ else if (lhs->is_iomem)
167+ return lhs->vaddr_iomem == rhs->vaddr_iomem;
168+ else
169+ return lhs->vaddr == rhs->vaddr;
170+}
171+
172+/**
173+ * iosys_map_is_null - Tests for a iosys mapping to be NULL
174+ * @map: The iosys_map structure
175+ *
176+ * Depending on the state of struct iosys_map.is_iomem, tests if the
177+ * mapping is NULL.
178+ *
179+ * Returns:
180+ * True if the mapping is NULL, or false otherwise.
181+ */
182+static inline bool iosys_map_is_null(const struct iosys_map *map)
183+{
184+ if (map->is_iomem)
185+ return !map->vaddr_iomem;
186+ return !map->vaddr;
187+}
188+
189+/**
190+ * iosys_map_is_set - Tests if the iosys mapping has been set
191+ * @map: The iosys_map structure
192+ *
193+ * Depending on the state of struct iosys_map.is_iomem, tests if the
194+ * mapping has been set.
195+ *
196+ * Returns:
197+ * True if the mapping is been set, or false otherwise.
198+ */
199+static inline bool iosys_map_is_set(const struct iosys_map *map)
200+{
201+ return !iosys_map_is_null(map);
202+}
203+
204+/**
205+ * iosys_map_clear - Clears a iosys mapping structure
206+ * @map: The iosys_map structure
207+ *
208+ * Clears all fields to zero, including struct iosys_map.is_iomem, so
209+ * mapping structures that were set to point to I/O memory are reset for
210+ * system memory. Pointers are cleared to NULL. This is the default.
211+ */
212+static inline void iosys_map_clear(struct iosys_map *map)
213+{
214+ if (map->is_iomem) {
215+ map->vaddr_iomem = NULL;
216+ map->is_iomem = false;
217+ } else {
218+ map->vaddr = NULL;
219+ }
220+}
221+
222+/**
223+ * iosys_map_memcpy_to - Memcpy into iosys mapping
224+ * @dst: The iosys_map structure
225+ * @src: The source buffer
226+ * @len: The number of byte in src
227+ *
228+ * Copies data into a iosys mapping. The source buffer is in system
229+ * memory. Depending on the buffer's location, the helper picks the correct
230+ * method of accessing the memory.
231+ */
232+static inline void iosys_map_memcpy_to(struct iosys_map *dst, const void *src,
233+ size_t len)
234+{
235+ if (dst->is_iomem)
236+ memcpy_toio(dst->vaddr_iomem, src, len);
237+ else
238+ memcpy(dst->vaddr, src, len);
239+}
240+
241+/**
242+ * iosys_map_incr - Increments the address stored in a iosys mapping
243+ * @map: The iosys_map structure
244+ * @incr: The number of bytes to increment
245+ *
246+ * Increments the address stored in a iosys mapping. Depending on the
247+ * buffer's location, the correct value will be updated.
248+ */
249+static inline void iosys_map_incr(struct iosys_map *map, size_t incr)
250+{
251+ if (map->is_iomem)
252+ map->vaddr_iomem += incr;
253+ else
254+ map->vaddr += incr;
255+}
256+
257+#endif /* __IOSYS_MAP_H__ */

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