The information which is currently provided as a response to the "HL_INFO_HW_IDLE" IOCTL is merely a general boolean value. This patch extends it and provides also a bitmask that indicates which of the device engines are busy.
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| @@ -45,6 +45,30 @@ enum goya_queue_id { · 44 unmodified lines | ||
| 45 | 45 | GOYA_QUEUE_ID_SIZE |
| 46 | 46 | }; |
| 47 | 47 | |
| 48 | +/* | |
| 49 | + * Engine Numbering | |
| 50 | + * | |
| 51 | + * Used in the "busy_engines_mask" field in `struct hl_info_hw_idle' | |
| 52 | + */ | |
| 53 | + | |
| 54 | +enum goya_engine_id { | |
| 55 | + GOYA_ENGINE_ID_DMA_0 = 0, | |
| 56 | + GOYA_ENGINE_ID_DMA_1, | |
| 57 | + GOYA_ENGINE_ID_DMA_2, | |
| 58 | + GOYA_ENGINE_ID_DMA_3, | |
| 59 | + GOYA_ENGINE_ID_DMA_4, | |
| 60 | + GOYA_ENGINE_ID_MME_0, | |
| 61 | + GOYA_ENGINE_ID_TPC_0, | |
| 62 | + GOYA_ENGINE_ID_TPC_1, | |
| 63 | + GOYA_ENGINE_ID_TPC_2, | |
| 64 | + GOYA_ENGINE_ID_TPC_3, | |
| 65 | + GOYA_ENGINE_ID_TPC_4, | |
| 66 | + GOYA_ENGINE_ID_TPC_5, | |
| 67 | + GOYA_ENGINE_ID_TPC_6, | |
| 68 | + GOYA_ENGINE_ID_TPC_7, | |
| 69 | + GOYA_ENGINE_ID_SIZE | |
| 70 | +}; | |
| 71 | + | |
| 48 | 72 | enum hl_device_status { |
| 49 | 73 | HL_DEVICE_STATUS_OPERATIONAL, |
| 50 | 74 | HL_DEVICE_STATUS_IN_RESET, |
| @@ -86,7 +110,11 @@ struct hl_info_dram_usage { · 35 unmodified lines | ||
| 86 | 110 | |
| 87 | 111 | struct hl_info_hw_idle { |
| 88 | 112 | __u32 is_idle; |
| 89 | − __u32 pad; | |
| 113 | + /* | |
| 114 | + * Bitmask of busy engines. | |
| 115 | + * Bits definition is according to `enum <chip>_enging_id'. | |
| 116 | + */ | |
| 117 | + __u32 busy_engines_mask; | |
| 90 | 118 | }; |
| 91 | 119 | |
| 92 | 120 | struct hl_info_device_status { |