lael-labs/linux

Documentation/arm64/tagged-address-abi.rst+18−8

@@ -45,14 +45,24 @@ how the user addresses are used by the kernel: · 44 unmodified lines
45		45
46	1. User addresses not accessed by the kernel but used for address space	46	1. User addresses not accessed by the kernel but used for address space
47	management (e.g. ``mprotect()``, ``madvise()``). The use of valid	47	management (e.g. ``mprotect()``, ``madvise()``). The use of valid
48	tagged pointers in this context is allowed with the exception of	48	tagged pointers in this context is allowed with these exceptions:
49	``brk()``, ``mmap()`` and the ``new_address`` argument to	49
50	``mremap()`` as these have the potential to alias with existing	50	- ``brk()``, ``mmap()`` and the ``new_address`` argument to
51	user addresses.	51	``mremap()`` as these have the potential to alias with existing
52		52	user addresses.
53	NOTE: This behaviour changed in v5.6 and so some earlier kernels may	53
54	incorrectly accept valid tagged pointers for the ``brk()``,	54	NOTE: This behaviour changed in v5.6 and so some earlier kernels may
55	``mmap()`` and ``mremap()`` system calls.	55	incorrectly accept valid tagged pointers for the ``brk()``,
		56	``mmap()`` and ``mremap()`` system calls.
		57
		58	- The ``range.start``, ``start`` and ``dst`` arguments to the
		59	``UFFDIO_*`` ``ioctl()``s used on a file descriptor obtained from
		60	``userfaultfd()``, as fault addresses subsequently obtained by reading
		61	the file descriptor will be untagged, which may otherwise confuse
		62	tag-unaware programs.
		63
		64	NOTE: This behaviour changed in v5.14 and so some earlier kernels may
		65	incorrectly accept valid tagged pointers for this system call.
56		66
57	2. User addresses accessed by the kernel (e.g. ``write()``). This ABI	67	2. User addresses accessed by the kernel (e.g. ``write()``). This ABI
58	relaxation is disabled by default and the application thread needs to	68	relaxation is disabled by default and the application thread needs to

Documentation/devicetree/bindings/net/imx-dwmac.txt+0−56

@@ -1,56 +0,0 @@
1	IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP.
2
3	This file documents platform glue layer for IMX.
4	Please see stmmac.txt for the other unchanged properties.
5
6	The device node has following properties.
7
8	Required properties:
9	- compatible: Should be "nxp,imx8mp-dwmac-eqos" to select glue layer
10	and "snps,dwmac-5.10a" to select IP version.
11	- clocks: Must contain a phandle for each entry in clock-names.
12	- clock-names: Should be "stmmaceth" for the host clock.
13	Should be "pclk" for the MAC apb clock.
14	Should be "ptp_ref" for the MAC timer clock.
15	Should be "tx" for the MAC RGMII TX clock:
16	Should be "mem" for EQOS MEM clock.
17	- "mem" clock is required for imx8dxl platform.
18	- "mem" clock is not required for imx8mp platform.
19	- interrupt-names: Should contain a list of interrupt names corresponding to
20	the interrupts in the interrupts property, if available.
21	Should be "macirq" for the main MAC IRQ
22	Should be "eth_wake_irq" for the IT which wake up system
23	- intf_mode: Should be phandle/offset pair. The phandle to the syscon node which
24	encompases the GPR register, and the offset of the GPR register.
25	- required for imx8mp platform.
26	- is optional for imx8dxl platform.
27
28	Optional properties:
29	- intf_mode: is optional for imx8dxl platform.
30	- snps,rmii_refclk_ext: to select RMII reference clock from external.
31
32	Example:
33	eqos: ethernet@30bf0000 {
34	compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
35	reg = <0x30bf0000 0x10000>;
36	interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
37	<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
38	interrupt-names = "eth_wake_irq", "macirq";
39	clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
40	<&clk IMX8MP_CLK_QOS_ENET_ROOT>,
41	<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
42	<&clk IMX8MP_CLK_ENET_QOS>;
43	clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
44	assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
45	<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
46	<&clk IMX8MP_CLK_ENET_QOS>;
47	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
48	<&clk IMX8MP_SYS_PLL2_100M>,
49	<&clk IMX8MP_SYS_PLL2_125M>;
50	assigned-clock-rates = <0>, <100000000>, <125000000>;
51	nvmem-cells = <&eth_mac0>;
52	nvmem-cell-names = "mac-address";
53	nvmem_macaddr_swap;
54	intf_mode = <&gpr 0x4>;
55	status = "disabled";
56	};

Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml+93−0

@@ -0,0 +1,93 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NXP i.MX8 DWMAC glue layer Device Tree Bindings
	8
	9	maintainers:
	10	- Joakim Zhang <qiangqing.zhang@nxp.com>
	11
	12	# We need a select here so we don't match all nodes with 'snps,dwmac'
	13	select:
	14	properties:
	15	compatible:
	16	contains:
	17	enum:
	18	- nxp,imx8mp-dwmac-eqos
	19	- nxp,imx8dxl-dwmac-eqos
	20	required:
	21	- compatible
	22
	23	allOf:
	24	- $ref: "snps,dwmac.yaml#"
	25
	26	properties:
	27	compatible:
	28	oneOf:
	29	- items:
	30	- enum:
	31	- nxp,imx8mp-dwmac-eqos
	32	- nxp,imx8dxl-dwmac-eqos
	33	- const: snps,dwmac-5.10a
	34
	35	clocks:
	36	minItems: 3
	37	maxItems: 5
	38	items:
	39	- description: MAC host clock
	40	- description: MAC apb clock
	41	- description: MAC timer clock
	42	- description: MAC RGMII TX clock
	43	- description: EQOS MEM clock
	44
	45	clock-names:
	46	minItems: 3
	47	maxItems: 5
	48	contains:
	49	enum:
	50	- stmmaceth
	51	- pclk
	52	- ptp_ref
	53	- tx
	54	- mem
	55
	56	intf_mode:
	57	$ref: /schemas/types.yaml#/definitions/phandle-array
	58	description:
	59	Should be phandle/offset pair. The phandle to the syscon node which
	60	encompases the GPR register, and the offset of the GPR register.
	61
	62	snps,rmii_refclk_ext:
	63	$ref: /schemas/types.yaml#/definitions/flag
	64	description:
	65	To select RMII reference clock from external.
	66
	67	required:
	68	- compatible
	69	- clocks
	70	- clock-names
	71
	72	unevaluatedProperties: false
	73
	74	examples:
	75	- \|
	76	#include <dt-bindings/interrupt-controller/arm-gic.h>
	77	#include <dt-bindings/interrupt-controller/irq.h>
	78	#include <dt-bindings/clock/imx8mp-clock.h>
	79
	80	eqos: ethernet@30bf0000 {
	81	compatible = "nxp,imx8mp-dwmac-eqos","snps,dwmac-5.10a";
	82	reg = <0x30bf0000 0x10000>;
	83	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	84	<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
	85	interrupt-names = "macirq", "eth_wake_irq";
	86	clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
	87	<&clk IMX8MP_CLK_QOS_ENET_ROOT>,
	88	<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
	89	<&clk IMX8MP_CLK_ENET_QOS>;
	90	clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
	91	phy-mode = "rgmii";
	92	status = "disabled";
	93	};

Documentation/devicetree/bindings/net/snps,dwmac.yaml+3−0

           - snps,dwmac-4.00
           - snps,dwmac-4.10a
           - snps,dwmac-4.20a
+          - snps,dwmac-5.10a
           - snps,dwxgmac
           - snps,dwxgmac-2.10
         - snps,dwmac-4.00
         - snps,dwmac-4.10a
         - snps,dwmac-4.20a
+        - snps,dwmac-5.10a
         - snps,dwxgmac
         - snps,dwxgmac-2.10
               - snps,dwmac-4.00
               - snps,dwmac-4.10a
               - snps,dwmac-4.20a
+              - snps,dwmac-5.10a
               - snps,dwxgmac
               - snps,dwxgmac-2.10
               - st,spear600-gmac

Documentation/devicetree/bindings/regulator/fixed-regulator.yaml+2−0

     maxItems: 1
   power-domains:
+    deprecated: true
     description:
       Power domain to use for enable control. This binding is only
       available if the compatible is chosen to regulator-fixed-domain.
     maxItems: 1
   required-opps:
+    deprecated: true
     description:
       Performance state to use for enable control. This binding is only
       available if the compatible is chosen to regulator-fixed-domain. The

Documentation/devicetree/bindings/sound/renesas,rsnd.yaml+1−1

@@ -114,7 +114,7 @@ properties: · 113 unmodified lines
114		114
115	ports:	115	ports:
116	$ref: /schemas/graph.yaml#/properties/ports	116	$ref: /schemas/graph.yaml#/properties/ports
117	properties:	117	patternProperties:
118	port(@[0-9a-f]+)?:	118	port(@[0-9a-f]+)?:
119	$ref: audio-graph-port.yaml#	119	$ref: audio-graph-port.yaml#
120	unevaluatedProperties: false	120	unevaluatedProperties: false

Documentation/networking/af_xdp.rst+3−3

@@ -243,8 +243,8 @@ Configuration Flags and Socket Options · 242 unmodified lines
243	These are the various configuration flags that can be used to control	243	These are the various configuration flags that can be used to control
244	and monitor the behavior of AF_XDP sockets.	244	and monitor the behavior of AF_XDP sockets.
245		245
246	XDP_COPY and XDP_ZERO_COPY bind flags	246	XDP_COPY and XDP_ZEROCOPY bind flags
247	-------------------------------------	247	------------------------------------
248		248
249	When you bind to a socket, the kernel will first try to use zero-copy	249	When you bind to a socket, the kernel will first try to use zero-copy
250	copy. If zero-copy is not supported, it will fall back on using copy	250	copy. If zero-copy is not supported, it will fall back on using copy
@@ -252,7 +252,7 @@ mode, i.e. copying all packets out to user space. But if you would · 1 unmodified line
252	like to force a certain mode, you can use the following flags. If you	252	like to force a certain mode, you can use the following flags. If you
253	pass the XDP_COPY flag to the bind call, the kernel will force the	253	pass the XDP_COPY flag to the bind call, the kernel will force the
254	socket into copy mode. If it cannot use copy mode, the bind call will	254	socket into copy mode. If it cannot use copy mode, the bind call will
255	fail with an error. Conversely, the XDP_ZERO_COPY flag will force the	255	fail with an error. Conversely, the XDP_ZEROCOPY flag will force the
256	socket into zero-copy mode or fail.	256	socket into zero-copy mode or fail.
257		257
258	XDP_SHARED_UMEM bind flag	258	XDP_SHARED_UMEM bind flag

Documentation/networking/ip-sysctl.rst+1−1

@@ -826,7 +826,7 @@ tcp_fastopen_blackhole_timeout_sec - INTEGER · 825 unmodified lines
826	initial value when the blackhole issue goes away.	826	initial value when the blackhole issue goes away.
827	0 to disable the blackhole detection.	827	0 to disable the blackhole detection.
828		828
829	By default, it is set to 1hr.	829	By default, it is set to 0 (feature is disabled).
830		830
831	tcp_fastopen_key - list of comma separated 32-digit hexadecimal INTEGERs	831	tcp_fastopen_key - list of comma separated 32-digit hexadecimal INTEGERs
832	The list consists of a primary key and an optional backup key. The	832	The list consists of a primary key and an optional backup key. The

Documentation/trace/histogram.rst+1−1

@@ -191,7 +191,7 @@ Documentation written by Tom Zanussi · 190 unmodified lines
191	with the event, in nanoseconds. May be	191	with the event, in nanoseconds. May be
192	modified by .usecs to have timestamps	192	modified by .usecs to have timestamps
193	interpreted as microseconds.	193	interpreted as microseconds.
194	cpu int the cpu on which the event occurred.	194	common_cpu int the cpu on which the event occurred.
195	====================== ==== =======================================	195	====================== ==== =======================================
196		196
197	Extended error information	197	Extended error information

MAINTAINERS+22−5

 F:	include/uapi/linux/wmi.h
 ACRN HYPERVISOR SERVICE MODULE
-M:	Shuo Liu <shuo.a.liu@intel.com>
+M:	Fei Li <fei1.li@intel.com>
 L:	acrn-dev@lists.projectacrn.org (subscribers-only)
 S:	Supported
 W:	https://projectacrn.org
 F:	drivers/input/touchscreen/goodix.c
 GOOGLE ETHERNET DRIVERS
-M:	Catherine Sullivan <csully@google.com>
+M:	Jeroen de Borst <jeroendb@google.com>
-R:	Sagi Shahar <sagis@google.com>
+R:	Catherine Sullivan <csully@google.com>
-R:	Jon Olson <jonolson@google.com>
+R:	David Awogbemila <awogbemila@google.com>
 L:	netdev@vger.kernel.org
 S:	Supported
 F:	Documentation/networking/device_drivers/ethernet/google/gve.rst
 T:	git git://linuxtv.org/media_tree.git
 F:	drivers/media/radio/radio-maxiradio*
+MCAB MICROCHIP CAN BUS ANALYZER TOOL DRIVER
+R:	Yasushi SHOJI <yashi@spacecubics.com>
+L:	linux-can@vger.kernel.org
+S:	Maintained
+F:	drivers/net/can/usb/mcba_usb.c
 MCAN MMIO DEVICE DRIVER
 M:	Chandrasekar Ramakrishnan <rcsekar@samsung.com>
 L:	linux-can@vger.kernel.org
 MEDIATEK SWITCH DRIVER
 M:	Sean Wang <sean.wang@mediatek.com>
 M:	Landen Chao <Landen.Chao@mediatek.com>
+M:	DENG Qingfang <dqfext@gmail.com>
 L:	netdev@vger.kernel.org
 S:	Maintained
 F:	drivers/net/dsa/mt7530.*
 L:	amd-gfx@lists.freedesktop.org
 S:	Supported
 T:	git https://gitlab.freedesktop.org/agd5f/linux.git
+B:	https://gitlab.freedesktop.org/drm/amd/-/issues
+C:	irc://irc.oftc.net/radeon
 F:	drivers/gpu/drm/amd/
 F:	drivers/gpu/drm/radeon/
 F:	include/uapi/drm/amdgpu_drm.h
 L:	linux-usb@vger.kernel.org
 S:	Maintained
 F:	Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml
-F:	drivers/phy/hisilicon/phy-kirin970-usb3.c
+F:	drivers/phy/hisilicon/phy-hi3670-usb3.c
 USB ISP116X DRIVER
 M:	Olav Kongas <ok@artecdesign.ee>
 S:	Supported
 F:	drivers/ptp/ptp_vmw.c
+VMWARE VMCI DRIVER
+M:	Jorgen Hansen <jhansen@vmware.com>
+M:	Vishnu Dasa <vdasa@vmware.com>
+L:	linux-kernel@vger.kernel.org
+L:	pv-drivers@vmware.com (private)
+S:	Maintained
+F:	drivers/misc/vmw_vmci/
 VMWARE VMMOUSE SUBDRIVER
 M:	"VMware Graphics" <linux-graphics-maintainer@vmware.com>
 M:	"VMware, Inc." <pv-drivers@vmware.com>

Makefile+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2	VERSION = 5	2	VERSION = 5
3	PATCHLEVEL = 14	3	PATCHLEVEL = 14
4	SUBLEVEL = 0	4	SUBLEVEL = 0
5	EXTRAVERSION = -rc2	5	EXTRAVERSION = -rc4
6	NAME = Opossums on Parade	6	NAME = Opossums on Parade
7		7
8	# DOCUMENTATION	8	# DOCUMENTATION

arch/alpha/Kconfig+1−2

 	select PCI_SYSCALL if PCI
 	select HAVE_AOUT
 	select HAVE_ASM_MODVERSIONS
-	select HAVE_IDE
 	select HAVE_PCSPKR_PLATFORM
 	select HAVE_PERF_EVENTS
 	select NEED_DMA_MAP_STATE
 	  will run faster if you say N here.
 	  See also the SMP-HOWTO available at
-	  <http://www.tldp.org/docs.html#howto>.
+	  <https://www.tldp.org/docs.html#howto>.
 	  If you don't know what to do here, say N.

arch/alpha/boot/bootp.c+1−1

@@ -23,7 +23,7 @@ · 22 unmodified lines
23	#include "ksize.h"	23	#include "ksize.h"
24		24
25	extern unsigned long switch_to_osf_pal(unsigned long nr,	25	extern unsigned long switch_to_osf_pal(unsigned long nr,
26	struct pcb_struct * pcb_va, struct pcb_struct * pcb_pa,	26	struct pcb_struct pcb_va, struct pcb_struct pcb_pa,
27	unsigned long *vptb);	27	unsigned long *vptb);
28		28
29	extern void move_stack(unsigned long new_stack);	29	extern void move_stack(unsigned long new_stack);

arch/alpha/boot/bootpz.c+1−1

@@ -200,7 +200,7 @@ extern char _end; · 199 unmodified lines
200	START_ADDR KSEG address of the entry point of kernel code.	200	START_ADDR KSEG address of the entry point of kernel code.
201		201
202	ZERO_PGE KSEG address of page full of zeroes, but	202	ZERO_PGE KSEG address of page full of zeroes, but
203	upon entry to kerne cvan be expected	203	upon entry to kernel, it can be expected
204	to hold the parameter list and possible	204	to hold the parameter list and possible
205	INTRD information.	205	INTRD information.
206		206

arch/alpha/boot/misc.c+1−1

@@ -30,7 +30,7 @@ extern long srm_printk(const char *, ...) · 29 unmodified lines
30	__attribute__ ((format (printf, 1, 2)));	30	__attribute__ ((format (printf, 1, 2)));
31		31
32	/*	32	/*
33	* gzip delarations	33	* gzip declarations
34	*/	34	*/
35	#define OF(args) args	35	#define OF(args) args
36	#define STATIC static	36	#define STATIC static

arch/alpha/configs/defconfig+1−0

@@ -70,3 +70,4 @@ CONFIG_DEBUG_INFO=y · 69 unmodified lines
70	CONFIG_ALPHA_LEGACY_START_ADDRESS=y	70	CONFIG_ALPHA_LEGACY_START_ADDRESS=y
71	CONFIG_MATHEMU=y	71	CONFIG_MATHEMU=y
72	CONFIG_CRYPTO_HMAC=y	72	CONFIG_CRYPTO_HMAC=y
		73	CONFIG_DEVTMPFS=y

arch/alpha/include/asm/compiler.h+0−11

@@ -4,15 +4,4 @@ · 3 unmodified lines
4		4
5	#include <uapi/asm/compiler.h>	5	#include <uapi/asm/compiler.h>
6		6
7	/* Some idiots over in <linux/compiler.h> thought inline should imply
8	always_inline. This breaks stuff. We'll include this file whenever
9	we run into such problems. */
10
11	#include <linux/compiler.h>
12	#undef inline
13	#undef __inline__
14	#undef __inline
15	#undef __always_inline
16	#define __always_inline inline __attribute__((always_inline))
17
18	#endif /* __ALPHA_COMPILER_H */	7	#endif /* __ALPHA_COMPILER_H */

arch/alpha/include/asm/syscall.h+6−0

@@ -9,4 +9,10 @@ static inline int syscall_get_arch(struct task_struct *task) · 8 unmodified lines
9	return AUDIT_ARCH_ALPHA;	9	return AUDIT_ARCH_ALPHA;
10	}	10	}
11		11
		12	static inline long syscall_get_return_value(struct task_struct *task,
		13	struct pt_regs *regs)
		14	{
		15	return regs->r0;
		16	}
		17
12	#endif /* _ASM_ALPHA_SYSCALL_H */	18	#endif /* _ASM_ALPHA_SYSCALL_H */

arch/alpha/kernel/osf_sys.c+2−2

@@ -834,7 +834,7 @@ SYSCALL_DEFINE5(osf_setsysinfo, unsigned long, op, void __user *, buffer, · 833 unmodified lines
834	return -EFAULT;	834	return -EFAULT;
835	state = &current_thread_info()->ieee_state;	835	state = &current_thread_info()->ieee_state;
836		836
837	/* Update softare trap enable bits. */	837	/* Update software trap enable bits. */
838	state = (state & ~IEEE_SW_MASK) \| (swcr & IEEE_SW_MASK);	838	state = (state & ~IEEE_SW_MASK) \| (swcr & IEEE_SW_MASK);
839		839
840	/* Update the real fpcr. */	840	/* Update the real fpcr. */
@@ -854,7 +854,7 @@ SYSCALL_DEFINE5(osf_setsysinfo, unsigned long, op, void __user *, buffer, · 13 unmodified lines
854	state = &current_thread_info()->ieee_state;	854	state = &current_thread_info()->ieee_state;
855	exc &= IEEE_STATUS_MASK;	855	exc &= IEEE_STATUS_MASK;
856		856
857	/* Update softare trap enable bits. */	857	/* Update software trap enable bits. */
858	swcr = (*state & IEEE_SW_MASK) \| exc;	858	swcr = (*state & IEEE_SW_MASK) \| exc;
859	*state \|= exc;	859	*state \|= exc;
860		860

arch/alpha/kernel/perf_event.c+1−1

@@ -574,7 +574,7 @@ static void alpha_pmu_start(struct perf_event *event, int flags) · 573 unmodified lines
574	* Check that CPU performance counters are supported.	574	* Check that CPU performance counters are supported.
575	* - currently support EV67 and later CPUs.	575	* - currently support EV67 and later CPUs.
576	* - actually some later revisions of the EV6 have the same PMC model as the	576	* - actually some later revisions of the EV6 have the same PMC model as the
577	* EV67 but we don't do suffiently deep CPU detection to detect them.	577	* EV67 but we don't do sufficiently deep CPU detection to detect them.
578	* Bad luck to the very few people who might have one, I guess.	578	* Bad luck to the very few people who might have one, I guess.
579	*/	579	*/
580	static int supported_cpu(void)	580	static int supported_cpu(void)

arch/alpha/kernel/process.c+1−1

@@ -256,7 +256,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, · 255 unmodified lines
256	childstack->r26 = (unsigned long) ret_from_kernel_thread;	256	childstack->r26 = (unsigned long) ret_from_kernel_thread;
257	childstack->r9 = usp; /* function */	257	childstack->r9 = usp; /* function */
258	childstack->r10 = kthread_arg;	258	childstack->r10 = kthread_arg;
259	childregs->hae = alpha_mv.hae_cache,	259	childregs->hae = alpha_mv.hae_cache;
260	childti->pcb.usp = 0;	260	childti->pcb.usp = 0;
261	return 0;	261	return 0;
262	}	262	}

arch/alpha/kernel/setup.c+7−6

 		       i, cluster->usage, cluster->start_pfn,
 		       cluster->start_pfn + cluster->numpages);
-		/* Bit 0 is console/PALcode reserved.  Bit 1 is
-		   non-volatile memory -- we might want to mark
-		   this for later.  */
-		if (cluster->usage & 3)
-			continue;
 		end = cluster->start_pfn + cluster->numpages;
 		if (end > max_low_pfn)
 			max_low_pfn = end;
 		memblock_add(PFN_PHYS(cluster->start_pfn),
 			     cluster->numpages << PAGE_SHIFT);
+		/* Bit 0 is console/PALcode reserved.  Bit 1 is
+		   non-volatile memory -- we might want to mark
+		   this for later.  */
+		if (cluster->usage & 3)
+			memblock_reserve(PFN_PHYS(cluster->start_pfn),
+				         cluster->numpages << PAGE_SHIFT);
 	}
 	/*

arch/alpha/kernel/smp.c+1−1

@@ -582,7 +582,7 @@ void · 581 unmodified lines
582	smp_send_stop(void)	582	smp_send_stop(void)
583	{	583	{
584	cpumask_t to_whom;	584	cpumask_t to_whom;
585	cpumask_copy(&to_whom, cpu_possible_mask);	585	cpumask_copy(&to_whom, cpu_online_mask);
586	cpumask_clear_cpu(smp_processor_id(), &to_whom);	586	cpumask_clear_cpu(smp_processor_id(), &to_whom);
587	#ifdef DEBUG_IPI_MSG	587	#ifdef DEBUG_IPI_MSG
588	if (hard_smp_processor_id() != boot_cpu_id)	588	if (hard_smp_processor_id() != boot_cpu_id)

arch/alpha/kernel/sys_nautilus.c+1−1

@@ -212,7 +212,7 @@ nautilus_init_pci(void) · 211 unmodified lines
212		212
213	/* Use default IO. */	213	/* Use default IO. */
214	pci_add_resource(&bridge->windows, &ioport_resource);	214	pci_add_resource(&bridge->windows, &ioport_resource);
215	/* Irongate PCI memory aperture, calculate requred size before	215	/* Irongate PCI memory aperture, calculate required size before
216	setting it up. */	216	setting it up. */
217	pci_add_resource(&bridge->windows, &irongate_mem);	217	pci_add_resource(&bridge->windows, &irongate_mem);
218		218

arch/alpha/kernel/traps.c+1−1

@@ -730,7 +730,7 @@ do_entUnaUser(void __user * va, unsigned long opcode, · 729 unmodified lines
730	long error;	730	long error;
731		731
732	/* Check the UAC bits to decide what the user wants us to do	732	/* Check the UAC bits to decide what the user wants us to do
733	with the unaliged access. */	733	with the unaligned access. */
734		734
735	if (!(current_thread_info()->status & TS_UAC_NOPRINT)) {	735	if (!(current_thread_info()->status & TS_UAC_NOPRINT)) {
736	if (__ratelimit(&ratelimit)) {	736	if (__ratelimit(&ratelimit)) {

arch/alpha/math-emu/math.c+6−2

 long do_alpha_fp_emul_imprecise(struct pt_regs *, unsigned long);
 long do_alpha_fp_emul(unsigned long);
-int init_module(void)
+static int alpha_fp_emul_init_module(void)
 {
 	save_emul_imprecise = alpha_fp_emul_imprecise;
 	save_emul = alpha_fp_emul;
 	alpha_fp_emul = do_alpha_fp_emul;
 	return 0;
 }
+module_init(alpha_fp_emul_init_module);
-void cleanup_module(void)
+static void alpha_fp_emul_cleanup_module(void)
 {
 	alpha_fp_emul_imprecise = save_emul_imprecise;
 	alpha_fp_emul = save_emul;
 }
+module_exit(alpha_fp_emul_cleanup_module);
 #undef  alpha_fp_emul_imprecise
 #define alpha_fp_emul_imprecise		do_alpha_fp_emul_imprecise
 egress:
 	return si_code;
 }
+EXPORT_SYMBOL(__udiv_qrnnd);

arch/arm/Kconfig+0−6

 	select HAVE_FUNCTION_TRACER if !XIP_KERNEL
 	select HAVE_GCC_PLUGINS
 	select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
-	select HAVE_IDE if PCI || ISA || PCMCIA
 	select HAVE_IRQ_TIME_ACCOUNTING
 	select HAVE_KERNEL_GZIP
 	select HAVE_KERNEL_LZ4
 	bool "FootBridge"
 	select CPU_SA110
 	select FOOTBRIDGE
-	select HAVE_IDE
 	select NEED_MACH_IO_H if !MMU
 	select NEED_MACH_MEMORY_H
 	help
 	select GENERIC_IRQ_MULTI_HANDLER
 	select GPIO_PXA
 	select GPIOLIB
-	select HAVE_IDE
 	select IRQ_DOMAIN
 	select PLAT_PXA
 	select SPARSE_IRQ
 	select ARM_HAS_SG_CHAIN
 	select CPU_SA110
 	select FIQ
-	select HAVE_IDE
 	select HAVE_PATA_PLATFORM
 	select ISA_DMA_API
 	select LEGACY_TIMER_TICK
 	select CPU_SA1100
 	select GENERIC_IRQ_MULTI_HANDLER
 	select GPIOLIB
-	select HAVE_IDE
 	select IRQ_DOMAIN
 	select ISA
 	select NEED_MACH_MEMORY_H
 	select GENERIC_IRQ_CHIP
 	select GENERIC_IRQ_MULTI_HANDLER
 	select GPIOLIB
-	select HAVE_IDE
 	select HAVE_LEGACY_CLK
 	select IRQ_DOMAIN
 	select NEED_MACH_IO_H if PCCARD

arch/arm/mach-davinci/Kconfig+0−1

@@ -9,7 +9,6 @@ menuconfig ARCH_DAVINCI · 8 unmodified lines
9	select PM_GENERIC_DOMAINS_OF if PM && OF	9	select PM_GENERIC_DOMAINS_OF if PM && OF
10	select REGMAP_MMIO	10	select REGMAP_MMIO
11	select RESET_CONTROLLER	11	select RESET_CONTROLLER
12	select HAVE_IDE
13	select PINCTRL_SINGLE	12	select PINCTRL_SINGLE
14		13
15	if ARCH_DAVINCI	14	if ARCH_DAVINCI

arch/arm/mach-rpc/riscpc.c+1−0

@@ -49,6 +49,7 @@ static int __init parse_tag_acorn(const struct tag *tag) · 48 unmodified lines
49	fallthrough; /* ??? */	49	fallthrough; /* ??? */
50	case 256:	50	case 256:
51	vram_size += PAGE_SIZE * 256;	51	vram_size += PAGE_SIZE * 256;
		52	break;
52	default:	53	default:
53	break;	54	break;
54	}	55	}

arch/arm/net/bpf_jit_32.c+3−0

 		rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
 		emit_ldx_r(dst, rn, off, ctx, BPF_SIZE(code));
 		break;
+	/* speculation barrier */
+	case BPF_ST | BPF_NOSPEC:
+		break;
 	/* ST: *(size *)(dst + off) = imm */
 	case BPF_ST | BPF_MEM | BPF_W:
 	case BPF_ST | BPF_MEM | BPF_H:

arch/arm64/boot/dts/freescale/imx8mp.dtsi+5−5

@@ -579,7 +579,7 @@ · 578 unmodified lines
579	};	579	};
580		580
581	flexcan1: can@308c0000 {	581	flexcan1: can@308c0000 {
582	compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";	582	compatible = "fsl,imx8mp-flexcan";
583	reg = <0x308c0000 0x10000>;	583	reg = <0x308c0000 0x10000>;
584	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;	584	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
585	clocks = <&clk IMX8MP_CLK_IPG_ROOT>,	585	clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
@@ -594,7 +594,7 @@ · 8 unmodified lines
594	};	594	};
595		595
596	flexcan2: can@308d0000 {	596	flexcan2: can@308d0000 {
597	compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";	597	compatible = "fsl,imx8mp-flexcan";
598	reg = <0x308d0000 0x10000>;	598	reg = <0x308d0000 0x10000>;
599	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;	599	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
600	clocks = <&clk IMX8MP_CLK_IPG_ROOT>,	600	clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
@@ -821,9 +821,9 @@ · 220 unmodified lines
821	eqos: ethernet@30bf0000 {	821	eqos: ethernet@30bf0000 {
822	compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";	822	compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
823	reg = <0x30bf0000 0x10000>;	823	reg = <0x30bf0000 0x10000>;
824	interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,	824	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
825	<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;	825	<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
826	interrupt-names = "eth_wake_irq", "macirq";	826	interrupt-names = "macirq", "eth_wake_irq";
827	clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,	827	clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
828	<&clk IMX8MP_CLK_QOS_ENET_ROOT>,	828	<&clk IMX8MP_CLK_QOS_ENET_ROOT>,
829	<&clk IMX8MP_CLK_ENET_QOS_TIMER>,	829	<&clk IMX8MP_CLK_ENET_QOS_TIMER>,

arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi+2−2

@@ -1063,7 +1063,7 @@ · 1062 unmodified lines
1063	status = "okay";	1063	status = "okay";
1064	extcon = <&usb2_id>;	1064	extcon = <&usb2_id>;
1065		1065
1066	usb@7600000 {	1066	dwc3@7600000 {
1067	extcon = <&usb2_id>;	1067	extcon = <&usb2_id>;
1068	dr_mode = "otg";	1068	dr_mode = "otg";
1069	maximum-speed = "high-speed";	1069	maximum-speed = "high-speed";
@@ -1074,7 +1074,7 @@ · 4 unmodified lines
1074	status = "okay";	1074	status = "okay";
1075	extcon = <&usb3_id>;	1075	extcon = <&usb3_id>;
1076		1076
1077	usb@6a00000 {	1077	dwc3@6a00000 {
1078	extcon = <&usb3_id>;	1078	extcon = <&usb3_id>;
1079	dr_mode = "otg";	1079	dr_mode = "otg";
1080	};	1080	};

arch/arm64/boot/dts/qcom/ipq8074.dtsi+2−2

@@ -443,7 +443,7 @@ · 442 unmodified lines
443	resets = <&gcc GCC_USB0_BCR>;	443	resets = <&gcc GCC_USB0_BCR>;
444	status = "disabled";	444	status = "disabled";
445		445
446	dwc_0: usb@8a00000 {	446	dwc_0: dwc3@8a00000 {
447	compatible = "snps,dwc3";	447	compatible = "snps,dwc3";
448	reg = <0x8a00000 0xcd00>;	448	reg = <0x8a00000 0xcd00>;
449	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;	449	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
@@ -484,7 +484,7 @@ · 34 unmodified lines
484	resets = <&gcc GCC_USB1_BCR>;	484	resets = <&gcc GCC_USB1_BCR>;
485	status = "disabled";	485	status = "disabled";
486		486
487	dwc_1: usb@8c00000 {	487	dwc_1: dwc3@8c00000 {
488	compatible = "snps,dwc3";	488	compatible = "snps,dwc3";
489	reg = <0x8c00000 0xcd00>;	489	reg = <0x8c00000 0xcd00>;
490	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;	490	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/qcom/msm8996.dtsi+2−2

@@ -2566,7 +2566,7 @@ · 2565 unmodified lines
2566	power-domains = <&gcc USB30_GDSC>;	2566	power-domains = <&gcc USB30_GDSC>;
2567	status = "disabled";	2567	status = "disabled";
2568		2568
2569	usb@6a00000 {	2569	dwc3@6a00000 {
2570	compatible = "snps,dwc3";	2570	compatible = "snps,dwc3";
2571	reg = <0x06a00000 0xcc00>;	2571	reg = <0x06a00000 0xcc00>;
2572	interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;	2572	interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
@@ -2873,7 +2873,7 @@ · 300 unmodified lines
2873	qcom,select-utmi-as-pipe-clk;	2873	qcom,select-utmi-as-pipe-clk;
2874	status = "disabled";	2874	status = "disabled";
2875		2875
2876	usb@7600000 {	2876	dwc3@7600000 {
2877	compatible = "snps,dwc3";	2877	compatible = "snps,dwc3";
2878	reg = <0x07600000 0xcc00>;	2878	reg = <0x07600000 0xcc00>;
2879	interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;	2879	interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/qcom/msm8998.dtsi+1−1

@@ -1964,7 +1964,7 @@ · 1963 unmodified lines
1964		1964
1965	resets = <&gcc GCC_USB_30_BCR>;	1965	resets = <&gcc GCC_USB_30_BCR>;
1966		1966
1967	usb3_dwc3: usb@a800000 {	1967	usb3_dwc3: dwc3@a800000 {
1968	compatible = "snps,dwc3";	1968	compatible = "snps,dwc3";
1969	reg = <0x0a800000 0xcd00>;	1969	reg = <0x0a800000 0xcd00>;
1970	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;	1970	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/qcom/qcs404-evb.dtsi+1−1

@@ -337,7 +337,7 @@ · 336 unmodified lines
337	&usb3 {	337	&usb3 {
338	status = "okay";	338	status = "okay";
339		339
340	usb@7580000 {	340	dwc3@7580000 {
341	dr_mode = "host";	341	dr_mode = "host";
342	};	342	};
343	};	343	};

arch/arm64/boot/dts/qcom/qcs404.dtsi+2−2

@@ -544,7 +544,7 @@ · 543 unmodified lines
544	assigned-clock-rates = <19200000>, <200000000>;	544	assigned-clock-rates = <19200000>, <200000000>;
545	status = "disabled";	545	status = "disabled";
546		546
547	usb@7580000 {	547	dwc3@7580000 {
548	compatible = "snps,dwc3";	548	compatible = "snps,dwc3";
549	reg = <0x07580000 0xcd00>;	549	reg = <0x07580000 0xcd00>;
550	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;	550	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -573,7 +573,7 @@ · 22 unmodified lines
573	assigned-clock-rates = <19200000>, <133333333>;	573	assigned-clock-rates = <19200000>, <133333333>;
574	status = "disabled";	574	status = "disabled";
575		575
576	usb@78c0000 {	576	dwc3@78c0000 {
577	compatible = "snps,dwc3";	577	compatible = "snps,dwc3";
578	reg = <0x078c0000 0xcc00>;	578	reg = <0x078c0000 0xcc00>;
579	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;	579	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/qcom/sc7180.dtsi+1−1

@@ -2756,7 +2756,7 @@ · 2755 unmodified lines
2756	<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;	2756	<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2757	interconnect-names = "usb-ddr", "apps-usb";	2757	interconnect-names = "usb-ddr", "apps-usb";
2758		2758
2759	usb_1_dwc3: usb@a600000 {	2759	usb_1_dwc3: dwc3@a600000 {
2760	compatible = "snps,dwc3";	2760	compatible = "snps,dwc3";
2761	reg = <0 0x0a600000 0 0xe000>;	2761	reg = <0 0x0a600000 0 0xe000>;
2762	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;	2762	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/qcom/sdm845.dtsi+2−2

@@ -3781,7 +3781,7 @@ · 3780 unmodified lines
3781	<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;	3781	<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3782	interconnect-names = "usb-ddr", "apps-usb";	3782	interconnect-names = "usb-ddr", "apps-usb";
3783		3783
3784	usb_1_dwc3: usb@a600000 {	3784	usb_1_dwc3: dwc3@a600000 {
3785	compatible = "snps,dwc3";	3785	compatible = "snps,dwc3";
3786	reg = <0 0x0a600000 0 0xcd00>;	3786	reg = <0 0x0a600000 0 0xcd00>;
3787	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;	3787	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
@@ -3829,7 +3829,7 @@ · 41 unmodified lines
3829	<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;	3829	<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3830	interconnect-names = "usb-ddr", "apps-usb";	3830	interconnect-names = "usb-ddr", "apps-usb";
3831		3831
3832	usb_2_dwc3: usb@a800000 {	3832	usb_2_dwc3: dwc3@a800000 {
3833	compatible = "snps,dwc3";	3833	compatible = "snps,dwc3";
3834	reg = <0 0x0a800000 0 0xcd00>;	3834	reg = <0 0x0a800000 0 0xcd00>;
3835	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;	3835	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/qcom/sm8150.dtsi+1−1

@@ -2344,7 +2344,7 @@ · 2343 unmodified lines
2344		2344
2345	resets = <&gcc GCC_USB30_PRIM_BCR>;	2345	resets = <&gcc GCC_USB30_PRIM_BCR>;
2346		2346
2347	usb_1_dwc3: usb@a600000 {	2347	usb_1_dwc3: dwc3@a600000 {
2348	compatible = "snps,dwc3";	2348	compatible = "snps,dwc3";
2349	reg = <0 0x0a600000 0 0xcd00>;	2349	reg = <0 0x0a600000 0 0xcd00>;
2350	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;	2350	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/include/asm/cpufeature.h+15−12

 {
 	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SHIFT);
-	return val == ID_AA64PFR0_EL1_32BIT_64BIT;
+	return val == ID_AA64PFR0_ELx_32BIT_64BIT;
 }
 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
 {
 	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
-	return val == ID_AA64PFR0_EL0_32BIT_64BIT;
+	return val == ID_AA64PFR0_ELx_32BIT_64BIT;
 }
 static inline bool id_aa64pfr0_sve(u64 pfr0)
 	val = cpuid_feature_extract_unsigned_field(mmfr0,
 						ID_AA64MMFR0_TGRAN4_SHIFT);
-	return val == ID_AA64MMFR0_TGRAN4_SUPPORTED;
+	return (val >= ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN) &&
+	       (val <= ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX);
 }
 static inline bool system_supports_64kb_granule(void)
 	val = cpuid_feature_extract_unsigned_field(mmfr0,
 						ID_AA64MMFR0_TGRAN64_SHIFT);
-	return val == ID_AA64MMFR0_TGRAN64_SUPPORTED;
+	return (val >= ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN) &&
+	       (val <= ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX);
 }
 static inline bool system_supports_16kb_granule(void)
 	val = cpuid_feature_extract_unsigned_field(mmfr0,
 						ID_AA64MMFR0_TGRAN16_SHIFT);
-	return val == ID_AA64MMFR0_TGRAN16_SUPPORTED;
+	return (val >= ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN) &&
+	       (val <= ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX);
 }
 static inline bool system_supports_mixed_endian_el0(void)
 static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)
 {
 	switch (parange) {
-	case 0: return 32;
+	case ID_AA64MMFR0_PARANGE_32: return 32;
-	case 1: return 36;
+	case ID_AA64MMFR0_PARANGE_36: return 36;
-	case 2: return 40;
+	case ID_AA64MMFR0_PARANGE_40: return 40;
-	case 3: return 42;
+	case ID_AA64MMFR0_PARANGE_42: return 42;
-	case 4: return 44;
+	case ID_AA64MMFR0_PARANGE_44: return 44;
-	case 5: return 48;
+	case ID_AA64MMFR0_PARANGE_48: return 48;
-	case 6: return 52;
+	case ID_AA64MMFR0_PARANGE_52: return 52;
 	/*
 	 * A future PE could use a value unknown to the kernel.
 	 * However, by the "D10.1.4 Principles of the ID scheme

arch/arm64/include/asm/kvm_arm.h+38−16

 #include <asm/types.h>
 /* Hyp Configuration Register (HCR) bits */
+#define HCR_TID5	(UL(1) << 58)
+#define HCR_DCT		(UL(1) << 57)
 #define HCR_ATA_SHIFT	56
 #define HCR_ATA		(UL(1) << HCR_ATA_SHIFT)
+#define HCR_AMVOFFEN	(UL(1) << 51)
+#define HCR_FIEN	(UL(1) << 47)
 #define HCR_FWB		(UL(1) << 46)
 #define HCR_API		(UL(1) << 41)
 #define HCR_APK		(UL(1) << 40)
 #define HCR_TVM		(UL(1) << 26)
 #define HCR_TTLB	(UL(1) << 25)
 #define HCR_TPU		(UL(1) << 24)
-#define HCR_TPC		(UL(1) << 23)
+#define HCR_TPC		(UL(1) << 23) /* HCR_TPCP if FEAT_DPB */
 #define HCR_TSW		(UL(1) << 22)
-#define HCR_TAC		(UL(1) << 21)
+#define HCR_TACR	(UL(1) << 21)
 #define HCR_TIDCP	(UL(1) << 20)
 #define HCR_TSC		(UL(1) << 19)
 #define HCR_TID3	(UL(1) << 18)
 #define HCR_PTW		(UL(1) << 2)
 #define HCR_SWIO	(UL(1) << 1)
 #define HCR_VM		(UL(1) << 0)
+#define HCR_RES0	((UL(1) << 48) | (UL(1) << 39))
 /*
  * The bits we set in HCR:
  * TLOR:	Trap LORegion register accesses
  * RW:		64bit by default, can be overridden for 32bit VMs
- * TAC:		Trap ACTLR
+ * TACR:	Trap ACTLR
  * TSC:		Trap SMC
  * TSW:		Trap cache operations by set/way
  * TWE:		Trap WFE
  * PTW:		Take a stage2 fault if a stage1 walk steps in device memory
  */
 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
-			 HCR_BSU_IS | HCR_FB | HCR_TAC | \
+			 HCR_BSU_IS | HCR_FB | HCR_TACR | \
 			 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
 			 HCR_FMO | HCR_IMO | HCR_PTW )
 #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
 #define CPTR_EL2_TTA	(1 << 20)
 #define CPTR_EL2_TFP	(1 << CPTR_EL2_TFP_SHIFT)
 #define CPTR_EL2_TZ	(1 << 8)
-#define CPTR_EL2_RES1	0x000032ff /* known RES1 bits in CPTR_EL2 */
+#define CPTR_NVHE_EL2_RES1	0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */
-#define CPTR_EL2_DEFAULT	CPTR_EL2_RES1
+#define CPTR_EL2_DEFAULT	CPTR_NVHE_EL2_RES1
+#define CPTR_NVHE_EL2_RES0	(GENMASK(63, 32) |	\
+				 GENMASK(29, 21) |	\
+				 GENMASK(19, 14) |	\
+				 BIT(11))
 /* Hyp Debug Configuration Register bits */
 #define MDCR_EL2_E2TB_MASK	(UL(0x3))
 #define MDCR_EL2_E2TB_SHIFT	(UL(24))
-#define MDCR_EL2_TTRF		(1 << 19)
+#define MDCR_EL2_HPMFZS		(UL(1) << 36)
-#define MDCR_EL2_TPMS		(1 << 14)
+#define MDCR_EL2_HPMFZO		(UL(1) << 29)
+#define MDCR_EL2_MTPME		(UL(1) << 28)
+#define MDCR_EL2_TDCC		(UL(1) << 27)
+#define MDCR_EL2_HCCD		(UL(1) << 23)
+#define MDCR_EL2_TTRF		(UL(1) << 19)
+#define MDCR_EL2_HPMD		(UL(1) << 17)
+#define MDCR_EL2_TPMS		(UL(1) << 14)
 #define MDCR_EL2_E2PB_MASK	(UL(0x3))
 #define MDCR_EL2_E2PB_SHIFT	(UL(12))
-#define MDCR_EL2_TDRA		(1 << 11)
+#define MDCR_EL2_TDRA		(UL(1) << 11)
-#define MDCR_EL2_TDOSA		(1 << 10)
+#define MDCR_EL2_TDOSA		(UL(1) << 10)
-#define MDCR_EL2_TDA		(1 << 9)
+#define MDCR_EL2_TDA		(UL(1) << 9)
-#define MDCR_EL2_TDE		(1 << 8)
+#define MDCR_EL2_TDE		(UL(1) << 8)
-#define MDCR_EL2_HPME		(1 << 7)
+#define MDCR_EL2_HPME		(UL(1) << 7)
-#define MDCR_EL2_TPM		(1 << 6)
+#define MDCR_EL2_TPM		(UL(1) << 6)
-#define MDCR_EL2_TPMCR		(1 << 5)
+#define MDCR_EL2_TPMCR		(UL(1) << 5)
-#define MDCR_EL2_HPMN_MASK	(0x1F)
+#define MDCR_EL2_HPMN_MASK	(UL(0x1F))
+#define MDCR_EL2_RES0		(GENMASK(63, 37) |	\
+				 GENMASK(35, 30) |	\
+				 GENMASK(25, 24) |	\
+				 GENMASK(22, 20) |	\
+				 BIT(18) |		\
+				 GENMASK(16, 15))
 /* For compatibility with fault code shared with 32-bit */
 #define FSC_FAULT	ESR_ELx_FSC_FAULT

arch/arm64/include/asm/kvm_asm.h+3−4

 #define __KVM_HOST_SMCCC_FUNC___vgic_v3_save_aprs		13
 #define __KVM_HOST_SMCCC_FUNC___vgic_v3_restore_aprs		14
 #define __KVM_HOST_SMCCC_FUNC___pkvm_init			15
-#define __KVM_HOST_SMCCC_FUNC___pkvm_create_mappings		16
+#define __KVM_HOST_SMCCC_FUNC___pkvm_host_share_hyp		16
 #define __KVM_HOST_SMCCC_FUNC___pkvm_create_private_mapping	17
 #define __KVM_HOST_SMCCC_FUNC___pkvm_cpu_set_vector		18
 #define __KVM_HOST_SMCCC_FUNC___pkvm_prot_finalize		19
-#define __KVM_HOST_SMCCC_FUNC___pkvm_mark_hyp			20
+#define __KVM_HOST_SMCCC_FUNC___kvm_adjust_pc			20
-#define __KVM_HOST_SMCCC_FUNC___kvm_adjust_pc			21
 #ifndef __ASSEMBLY__
 extern void __vgic_v3_write_vmcr(u32 vmcr);
 extern void __vgic_v3_init_lrs(void);
-extern u32 __kvm_get_mdcr_el2(void);
+extern u64 __kvm_get_mdcr_el2(void);
 #define __KVM_EXTABLE(from, to)						\
 	"	.pushsection	__kvm_ex_table, \"a\"\n"		\

arch/arm64/include/asm/kvm_host.h+13−4

 extern unsigned int kvm_sve_max_vl;
 int kvm_arm_init_sve(void);
-int __attribute_const__ kvm_target_cpu(void);
+u32 __attribute_const__ kvm_target_cpu(void);
 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
 	PMCNTENSET_EL0,	/* Count Enable Set Register */
 	PMINTENSET_EL1,	/* Interrupt Enable Set Register */
 	PMOVSSET_EL0,	/* Overflow Flag Status Set Register */
-	PMSWINC_EL0,	/* Software Increment Register */
 	PMUSERENR_EL0,	/* User Enable Register */
 	/* Pointer Authentication Registers in a strict increasing order. */
 	/* Stage 2 paging state used by the hardware on next switch */
 	struct kvm_s2_mmu *hw_mmu;
-	/* HYP configuration */
+	/* Values of trap registers for the guest. */
 	u64 hcr_el2;
-	u32 mdcr_el2;
+	u64 mdcr_el2;
+	u64 cptr_el2;
+	/* Values of trap registers for the host before guest entry. */
+	u64 mdcr_el2_host;
 	/* Exception Information */
 	struct kvm_vcpu_fault_info fault;
 	u64 wfi_exit_stat;
 	u64 mmio_exit_user;
 	u64 mmio_exit_kernel;
+	u64 signal_exits;
 	u64 exits;
 };
 int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type);
+static inline bool kvm_vm_is_protected(struct kvm *kvm)
+{
+	return false;
+}
 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);

arch/arm64/include/asm/kvm_hyp.h+1−1

@@ -95,7 +95,7 @@ void __sve_restore_state(void sve_pffr, u32 fpsr); · 94 unmodified lines
95		95
96	#ifndef __KVM_NVHE_HYPERVISOR__	96	#ifndef __KVM_NVHE_HYPERVISOR__
97	void activate_traps_vhe_load(struct kvm_vcpu *vcpu);	97	void activate_traps_vhe_load(struct kvm_vcpu *vcpu);
98	void deactivate_traps_vhe_put(void);	98	void deactivate_traps_vhe_put(struct kvm_vcpu *vcpu);
99	#endif	99	#endif
100		100
101	u64 __guest_enter(struct kvm_vcpu *vcpu);	101	u64 __guest_enter(struct kvm_vcpu *vcpu);

arch/arm64/include/asm/kvm_mmu.h+9−8

 #define kvm_phys_to_vttbr(addr)		phys_to_ttbr(addr)
+/*
+ * When this is (directly or indirectly) used on the TLB invalidation
+ * path, we rely on a previously issued DSB so that page table updates
+ * and VMID reads are correctly ordered.
+ */
 static __always_inline u64 kvm_get_vttbr(struct kvm_s2_mmu *mmu)
 {
 	struct kvm_vmid *vmid = &mmu->vmid;
 	u64 cnp = system_supports_cnp() ? VTTBR_CNP_BIT : 0;
 	baddr = mmu->pgd_phys;
-	vmid_field = (u64)vmid->vmid << VTTBR_VMID_SHIFT;
+	vmid_field = (u64)READ_ONCE(vmid->vmid) << VTTBR_VMID_SHIFT;
 	return kvm_phys_to_vttbr(baddr) | vmid_field | cnp;
 }
  * Must be called from hyp code running at EL2 with an updated VTTBR
  * and interrupts disabled.
  */
-static __always_inline void __load_stage2(struct kvm_s2_mmu *mmu, unsigned long vtcr)
+static __always_inline void __load_stage2(struct kvm_s2_mmu *mmu,
+					  struct kvm_arch *arch)
 {
-	write_sysreg(vtcr, vtcr_el2);
+	write_sysreg(arch->vtcr, vtcr_el2);
 	write_sysreg(kvm_get_vttbr(mmu), vttbr_el2);
 	/*
 	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
 }
-static __always_inline void __load_guest_stage2(struct kvm_s2_mmu *mmu)
-{
-	__load_stage2(mmu, kern_hyp_va(mmu->arch)->vtcr);
-}
 static inline struct kvm *kvm_s2_mmu_to_kvm(struct kvm_s2_mmu *mmu)
 {
 	return container_of(mmu->arch, struct kvm, arch);

arch/arm64/include/asm/kvm_pgtable.h+122−46

@@ -25,6 +25,46 @@ static inline u64 kvm_get_parange(u64 mmfr0) · 24 unmodified lines
25		25
26	typedef u64 kvm_pte_t;	26	typedef u64 kvm_pte_t;
27		27
		28	#define KVM_PTE_VALID BIT(0)
		29
		30	#define KVM_PTE_ADDR_MASK GENMASK(47, PAGE_SHIFT)
		31	#define KVM_PTE_ADDR_51_48 GENMASK(15, 12)
		32
		33	static inline bool kvm_pte_valid(kvm_pte_t pte)
		34	{
		35	return pte & KVM_PTE_VALID;
		36	}
		37
		38	static inline u64 kvm_pte_to_phys(kvm_pte_t pte)
		39	{
		40	u64 pa = pte & KVM_PTE_ADDR_MASK;
		41
		42	if (PAGE_SHIFT == 16)
		43	pa \|= FIELD_GET(KVM_PTE_ADDR_51_48, pte) << 48;
		44
		45	return pa;
		46	}
		47
		48	static inline u64 kvm_granule_shift(u32 level)
		49	{
		50	/* Assumes KVM_PGTABLE_MAX_LEVELS is 4 */
		51	return ARM64_HW_PGTABLE_LEVEL_SHIFT(level);
		52	}
		53
		54	static inline u64 kvm_granule_size(u32 level)
		55	{
		56	return BIT(kvm_granule_shift(level));
		57	}
		58
		59	static inline bool kvm_level_supports_block_mapping(u32 level)
		60	{
		61	/*
		62	* Reject invalid block mappings and don't bother with 4TB mappings for
		63	* 52-bit PAs.
		64	*/
		65	return !(level == 0 \|\| (PAGE_SIZE != SZ_4K && level == 1));
		66	}
		67
28	/**	68	/**
29	* struct kvm_pgtable_mm_ops - Memory management callbacks.	69	* struct kvm_pgtable_mm_ops - Memory management callbacks.
30	* @zalloc_page: Allocate a single zeroed memory page.	70	* @zalloc_page: Allocate a single zeroed memory page.
@@ -75,31 +115,16 @@ enum kvm_pgtable_stage2_flags { · 44 unmodified lines
75	KVM_PGTABLE_S2_IDMAP = BIT(1),	115	KVM_PGTABLE_S2_IDMAP = BIT(1),
76	};	116	};
77		117
78	/**
79	* struct kvm_pgtable - KVM page-table.
80	* @ia_bits: Maximum input address size, in bits.
81	* @start_level: Level at which the page-table walk starts.
82	* @pgd: Pointer to the first top-level entry of the page-table.
83	* @mm_ops: Memory management callbacks.
84	* @mmu: Stage-2 KVM MMU struct. Unused for stage-1 page-tables.
85	*/
86	struct kvm_pgtable {
87	u32 ia_bits;
88	u32 start_level;
89	kvm_pte_t *pgd;
90	struct kvm_pgtable_mm_ops *mm_ops;
91
92	/* Stage-2 only */
93	struct kvm_s2_mmu *mmu;
94	enum kvm_pgtable_stage2_flags flags;
95	};
96
97	/**	118	/**
98	* enum kvm_pgtable_prot - Page-table permissions and attributes.	119	* enum kvm_pgtable_prot - Page-table permissions and attributes.
99	* @KVM_PGTABLE_PROT_X: Execute permission.	120	* @KVM_PGTABLE_PROT_X: Execute permission.
100	* @KVM_PGTABLE_PROT_W: Write permission.	121	* @KVM_PGTABLE_PROT_W: Write permission.
101	* @KVM_PGTABLE_PROT_R: Read permission.	122	* @KVM_PGTABLE_PROT_R: Read permission.
102	* @KVM_PGTABLE_PROT_DEVICE: Device attributes.	123	* @KVM_PGTABLE_PROT_DEVICE: Device attributes.
		124	* @KVM_PGTABLE_PROT_SW0: Software bit 0.
		125	* @KVM_PGTABLE_PROT_SW1: Software bit 1.
		126	* @KVM_PGTABLE_PROT_SW2: Software bit 2.
		127	* @KVM_PGTABLE_PROT_SW3: Software bit 3.
103	*/	128	*/
104	enum kvm_pgtable_prot {	129	enum kvm_pgtable_prot {
105	KVM_PGTABLE_PROT_X = BIT(0),	130	KVM_PGTABLE_PROT_X = BIT(0),
@@ -107,21 +132,48 @@ enum kvm_pgtable_prot { · 1 unmodified line
107	KVM_PGTABLE_PROT_R = BIT(2),	132	KVM_PGTABLE_PROT_R = BIT(2),
108		133
109	KVM_PGTABLE_PROT_DEVICE = BIT(3),	134	KVM_PGTABLE_PROT_DEVICE = BIT(3),
		135
		136	KVM_PGTABLE_PROT_SW0 = BIT(55),
		137	KVM_PGTABLE_PROT_SW1 = BIT(56),
		138	KVM_PGTABLE_PROT_SW2 = BIT(57),
		139	KVM_PGTABLE_PROT_SW3 = BIT(58),
110	};	140	};
111		141
112	#define PAGE_HYP (KVM_PGTABLE_PROT_R \| KVM_PGTABLE_PROT_W)	142	#define KVM_PGTABLE_PROT_RW (KVM_PGTABLE_PROT_R \| KVM_PGTABLE_PROT_W)
		143	#define KVM_PGTABLE_PROT_RWX (KVM_PGTABLE_PROT_RW \| KVM_PGTABLE_PROT_X)
		144
		145	#define PKVM_HOST_MEM_PROT KVM_PGTABLE_PROT_RWX
		146	#define PKVM_HOST_MMIO_PROT KVM_PGTABLE_PROT_RW
		147
		148	#define PAGE_HYP KVM_PGTABLE_PROT_RW
113	#define PAGE_HYP_EXEC (KVM_PGTABLE_PROT_R \| KVM_PGTABLE_PROT_X)	149	#define PAGE_HYP_EXEC (KVM_PGTABLE_PROT_R \| KVM_PGTABLE_PROT_X)
114	#define PAGE_HYP_RO (KVM_PGTABLE_PROT_R)	150	#define PAGE_HYP_RO (KVM_PGTABLE_PROT_R)
115	#define PAGE_HYP_DEVICE (PAGE_HYP \| KVM_PGTABLE_PROT_DEVICE)	151	#define PAGE_HYP_DEVICE (PAGE_HYP \| KVM_PGTABLE_PROT_DEVICE)
116		152
		153	typedef bool (*kvm_pgtable_force_pte_cb_t)(u64 addr, u64 end,
		154	enum kvm_pgtable_prot prot);
		155
117	/**	156	/**
118	* struct kvm_mem_range - Range of Intermediate Physical Addresses	157	* struct kvm_pgtable - KVM page-table.
119	* @start: Start of the range.	158	* @ia_bits: Maximum input address size, in bits.
120	* @end: End of the range.	159	* @start_level: Level at which the page-table walk starts.
		160	* @pgd: Pointer to the first top-level entry of the page-table.
		161	* @mm_ops: Memory management callbacks.
		162	* @mmu: Stage-2 KVM MMU struct. Unused for stage-1 page-tables.
		163	* @flags: Stage-2 page-table flags.
		164	* @force_pte_cb: Function that returns true if page level mappings must
		165	* be used instead of block mappings.
121	*/	166	*/
122	struct kvm_mem_range {	167	struct kvm_pgtable {
123	u64 start;	168	u32 ia_bits;
124	u64 end;	169	u32 start_level;
		170	kvm_pte_t *pgd;
		171	struct kvm_pgtable_mm_ops *mm_ops;
		172
		173	/* Stage-2 only */
		174	struct kvm_s2_mmu *mmu;
		175	enum kvm_pgtable_stage2_flags flags;
		176	kvm_pgtable_force_pte_cb_t force_pte_cb;
125	};	177	};
126		178
127	/**	179	/**
@@ -216,21 +268,24 @@ int kvm_pgtable_hyp_map(struct kvm_pgtable *pgt, u64 addr, u64 size, u64 phys, · 88 unmodified lines
216	u64 kvm_get_vtcr(u64 mmfr0, u64 mmfr1, u32 phys_shift);	268	u64 kvm_get_vtcr(u64 mmfr0, u64 mmfr1, u32 phys_shift);
217		269
218	/**	270	/**
219	* kvm_pgtable_stage2_init_flags() - Initialise a guest stage-2 page-table.	271	* __kvm_pgtable_stage2_init() - Initialise a guest stage-2 page-table.
220	* @pgt: Uninitialised page-table structure to initialise.	272	* @pgt: Uninitialised page-table structure to initialise.
221	* @arch: Arch-specific KVM structure representing the guest virtual	273	* @arch: Arch-specific KVM structure representing the guest virtual
222	* machine.	274	* machine.
223	* @mm_ops: Memory management callbacks.	275	* @mm_ops: Memory management callbacks.
224	* @flags: Stage-2 configuration flags.	276	* @flags: Stage-2 configuration flags.
		277	* @force_pte_cb: Function that returns true if page level mappings must
		278	* be used instead of block mappings.
225	*	279	*
226	* Return: 0 on success, negative error code on failure.	280	* Return: 0 on success, negative error code on failure.
227	*/	281	*/
228	int kvm_pgtable_stage2_init_flags(struct kvm_pgtable pgt, struct kvm_arch arch,	282	int __kvm_pgtable_stage2_init(struct kvm_pgtable pgt, struct kvm_arch arch,
229	struct kvm_pgtable_mm_ops *mm_ops,	283	struct kvm_pgtable_mm_ops *mm_ops,
230	enum kvm_pgtable_stage2_flags flags);	284	enum kvm_pgtable_stage2_flags flags,
		285	kvm_pgtable_force_pte_cb_t force_pte_cb);
231		286
232	#define kvm_pgtable_stage2_init(pgt, arch, mm_ops) \	287	#define kvm_pgtable_stage2_init(pgt, arch, mm_ops) \
233	kvm_pgtable_stage2_init_flags(pgt, arch, mm_ops, 0)	288	__kvm_pgtable_stage2_init(pgt, arch, mm_ops, 0, NULL)
234		289
235	/**	290	/**
236	* kvm_pgtable_stage2_destroy() - Destroy an unused guest stage-2 page-table.	291	* kvm_pgtable_stage2_destroy() - Destroy an unused guest stage-2 page-table.
@@ -374,7 +429,8 @@ kvm_pte_t kvm_pgtable_stage2_mkold(struct kvm_pgtable *pgt, u64 addr); · 137 unmodified lines
374	* If there is a valid, leaf page-table entry used to translate @addr, then	429	* If there is a valid, leaf page-table entry used to translate @addr, then
375	* relax the permissions in that entry according to the read, write and	430	* relax the permissions in that entry according to the read, write and
376	* execute permissions specified by @prot. No permissions are removed, and	431	* execute permissions specified by @prot. No permissions are removed, and
377	* TLB invalidation is performed after updating the entry.	432	* TLB invalidation is performed after updating the entry. Software bits cannot
		433	* be set or cleared using kvm_pgtable_stage2_relax_perms().
378	*	434	*
379	* Return: 0 on success, negative error code on failure.	435	* Return: 0 on success, negative error code on failure.
380	*/	436	*/
@@ -433,22 +489,42 @@ int kvm_pgtable_walk(struct kvm_pgtable *pgt, u64 addr, u64 size, · 52 unmodified lines
433	struct kvm_pgtable_walker *walker);	489	struct kvm_pgtable_walker *walker);
434		490
435	/**	491	/**
436	* kvm_pgtable_stage2_find_range() - Find a range of Intermediate Physical	492	* kvm_pgtable_get_leaf() - Walk a page-table and retrieve the leaf entry
437	* Addresses with compatible permission	493	* with its level.
438	* attributes.	494	* @pgt: Page-table structure initialised by kvm_pgtable_*_init()
439	* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().	495	* or a similar initialiser.
440	* @addr: Address that must be covered by the range.	496	* @addr: Input address for the start of the walk.
441	* @prot: Protection attributes that the range must be compatible with.	497	* @ptep: Pointer to storage for the retrieved PTE.
442	* @range: Range structure used to limit the search space at call time and	498	* @level: Pointer to storage for the level of the retrieved PTE.
443	* that will hold the result.	499	*
		500	* The offset of @addr within a page is ignored.
444	*	501	*
445	* The offset of @addr within a page is ignored. An IPA is compatible with @prot	502	* The walker will walk the page-table entries corresponding to the input
446	* iff its corresponding stage-2 page-table entry has default ownership and, if	503	* address specified, retrieving the leaf corresponding to this address.
447	* valid, is mapped with protection attributes identical to @prot.	504	* Invalid entries are treated as leaf entries.
448	*	505	*
449	* Return: 0 on success, negative error code on failure.	506	* Return: 0 on success, negative error code on failure.
450	*/	507	*/
451	int kvm_pgtable_stage2_find_range(struct kvm_pgtable *pgt, u64 addr,	508	int kvm_pgtable_get_leaf(struct kvm_pgtable *pgt, u64 addr,
452	enum kvm_pgtable_prot prot,	509	kvm_pte_t ptep, u32 level);
453	struct kvm_mem_range *range);	510
		511	/**
		512	* kvm_pgtable_stage2_pte_prot() - Retrieve the protection attributes of a
		513	* stage-2 Page-Table Entry.
		514	* @pte: Page-table entry
		515	*
		516	* Return: protection attributes of the page-table entry in the enum
		517	* kvm_pgtable_prot format.
		518	*/
		519	enum kvm_pgtable_prot kvm_pgtable_stage2_pte_prot(kvm_pte_t pte);
		520
		521	/**
		522	* kvm_pgtable_hyp_pte_prot() - Retrieve the protection attributes of a stage-1
		523	* Page-Table Entry.
		524	* @pte: Page-table entry
		525	*
		526	* Return: protection attributes of the page-table entry in the enum
		527	* kvm_pgtable_prot format.
		528	*/
		529	enum kvm_pgtable_prot kvm_pgtable_hyp_pte_prot(kvm_pte_t pte);
454	#endif /* __ARM64_KVM_PGTABLE_H__ */	530	#endif /* __ARM64_KVM_PGTABLE_H__ */

arch/arm64/include/asm/sysreg.h+38−16

@@ -784,14 +784,13 @@ · 783 unmodified lines
784	#define ID_AA64PFR0_AMU 0x1	784	#define ID_AA64PFR0_AMU 0x1
785	#define ID_AA64PFR0_SVE 0x1	785	#define ID_AA64PFR0_SVE 0x1
786	#define ID_AA64PFR0_RAS_V1 0x1	786	#define ID_AA64PFR0_RAS_V1 0x1
		787	#define ID_AA64PFR0_RAS_V1P1 0x2
787	#define ID_AA64PFR0_FP_NI 0xf	788	#define ID_AA64PFR0_FP_NI 0xf
788	#define ID_AA64PFR0_FP_SUPPORTED 0x0	789	#define ID_AA64PFR0_FP_SUPPORTED 0x0
789	#define ID_AA64PFR0_ASIMD_NI 0xf	790	#define ID_AA64PFR0_ASIMD_NI 0xf
790	#define ID_AA64PFR0_ASIMD_SUPPORTED 0x0	791	#define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
791	#define ID_AA64PFR0_EL1_64BIT_ONLY 0x1	792	#define ID_AA64PFR0_ELx_64BIT_ONLY 0x1
792	#define ID_AA64PFR0_EL1_32BIT_64BIT 0x2	793	#define ID_AA64PFR0_ELx_32BIT_64BIT 0x2
793	#define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
794	#define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
795		794
796	/* id_aa64pfr1 */	795	/* id_aa64pfr1 */
797	#define ID_AA64PFR1_MPAMFRAC_SHIFT 16	796	#define ID_AA64PFR1_MPAMFRAC_SHIFT 16
@@ -847,15 +846,29 @@ · 49 unmodified lines
847	#define ID_AA64MMFR0_ASID_SHIFT 4	846	#define ID_AA64MMFR0_ASID_SHIFT 4
848	#define ID_AA64MMFR0_PARANGE_SHIFT 0	847	#define ID_AA64MMFR0_PARANGE_SHIFT 0
849		848
850	#define ID_AA64MMFR0_TGRAN4_NI 0xf	849	#define ID_AA64MMFR0_ASID_8 0x0
851	#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0	850	#define ID_AA64MMFR0_ASID_16 0x2
852	#define ID_AA64MMFR0_TGRAN64_NI 0xf	851
853	#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0	852	#define ID_AA64MMFR0_TGRAN4_NI 0xf
854	#define ID_AA64MMFR0_TGRAN16_NI 0x0	853	#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0
855	#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1	854	#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7
		855	#define ID_AA64MMFR0_TGRAN64_NI 0xf
		856	#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 0x0
		857	#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 0x7
		858	#define ID_AA64MMFR0_TGRAN16_NI 0x0
		859	#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 0x1
		860	#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 0xf
		861
		862	#define ID_AA64MMFR0_PARANGE_32 0x0
		863	#define ID_AA64MMFR0_PARANGE_36 0x1
		864	#define ID_AA64MMFR0_PARANGE_40 0x2
		865	#define ID_AA64MMFR0_PARANGE_42 0x3
		866	#define ID_AA64MMFR0_PARANGE_44 0x4
856	#define ID_AA64MMFR0_PARANGE_48 0x5	867	#define ID_AA64MMFR0_PARANGE_48 0x5
857	#define ID_AA64MMFR0_PARANGE_52 0x6	868	#define ID_AA64MMFR0_PARANGE_52 0x6
858		869
		870	#define ARM64_MIN_PARANGE_BITS 32
		871
859	#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0	872	#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0
860	#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE 0x1	873	#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE 0x1
861	#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN 0x2	874	#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN 0x2
@@ -900,6 +913,7 @@ · 38 unmodified lines
900	#define ID_AA64MMFR2_CNP_SHIFT 0	913	#define ID_AA64MMFR2_CNP_SHIFT 0
901		914
902	/* id_aa64dfr0 */	915	/* id_aa64dfr0 */
		916	#define ID_AA64DFR0_MTPMU_SHIFT 48
903	#define ID_AA64DFR0_TRBE_SHIFT 44	917	#define ID_AA64DFR0_TRBE_SHIFT 44
904	#define ID_AA64DFR0_TRACE_FILT_SHIFT 40	918	#define ID_AA64DFR0_TRACE_FILT_SHIFT 40
905	#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36	919	#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
@@ -1028,16 +1042,19 @@ · 122 unmodified lines
1028		1042
1029	#if defined(CONFIG_ARM64_4K_PAGES)	1043	#if defined(CONFIG_ARM64_4K_PAGES)
1030	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT	1044	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
1031	#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN4_SUPPORTED	1045	#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN
1032	#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0x7	1046	#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX
		1047	#define ID_AA64MMFR0_TGRAN_2_SHIFT ID_AA64MMFR0_TGRAN4_2_SHIFT
1033	#elif defined(CONFIG_ARM64_16K_PAGES)	1048	#elif defined(CONFIG_ARM64_16K_PAGES)
1034	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT	1049	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
1035	#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN16_SUPPORTED	1050	#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN
1036	#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0xF	1051	#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX
		1052	#define ID_AA64MMFR0_TGRAN_2_SHIFT ID_AA64MMFR0_TGRAN16_2_SHIFT
1037	#elif defined(CONFIG_ARM64_64K_PAGES)	1053	#elif defined(CONFIG_ARM64_64K_PAGES)
1038	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT	1054	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
1039	#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN64_SUPPORTED	1055	#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN
1040	#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0x7	1056	#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX
		1057	#define ID_AA64MMFR0_TGRAN_2_SHIFT ID_AA64MMFR0_TGRAN64_2_SHIFT
1041	#endif	1058	#endif
1042		1059
1043	#define MVFR2_FPMISC_SHIFT 4	1060	#define MVFR2_FPMISC_SHIFT 4
@@ -1153,6 +1170,11 @@ · 109 unmodified lines
1153	#define ICH_VTR_A3V_SHIFT 21	1170	#define ICH_VTR_A3V_SHIFT 21
1154	#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)	1171	#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
1155		1172
		1173	#define ARM64_FEATURE_FIELD_BITS 4
		1174
		1175	/* Create a mask for the feature bits of the specified feature. */
		1176	#define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
		1177
1156	#ifdef __ASSEMBLY__	1178	#ifdef __ASSEMBLY__
1157		1179
1158	.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30	1180	.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30

arch/arm64/kernel/cpufeature.c+4−4

@@ -239,8 +239,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { · 238 unmodified lines
239	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),	239	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
240	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),	240	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
241	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),	241	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
242	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),	242	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
243	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),	243	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
244	ARM64_FTR_END,	244	ARM64_FTR_END,
245	};	245	};
246		246
@@ -1956,7 +1956,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { · 1709 unmodified lines
1956	.sys_reg = SYS_ID_AA64PFR0_EL1,	1956	.sys_reg = SYS_ID_AA64PFR0_EL1,
1957	.sign = FTR_UNSIGNED,	1957	.sign = FTR_UNSIGNED,
1958	.field_pos = ID_AA64PFR0_EL0_SHIFT,	1958	.field_pos = ID_AA64PFR0_EL0_SHIFT,
1959	.min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,	1959	.min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
1960	},	1960	},
1961	#ifdef CONFIG_KVM	1961	#ifdef CONFIG_KVM
1962	{	1962	{
@@ -1967,7 +1967,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { · 4 unmodified lines
1967	.sys_reg = SYS_ID_AA64PFR0_EL1,	1967	.sys_reg = SYS_ID_AA64PFR0_EL1,
1968	.sign = FTR_UNSIGNED,	1968	.sign = FTR_UNSIGNED,
1969	.field_pos = ID_AA64PFR0_EL1_SHIFT,	1969	.field_pos = ID_AA64PFR0_EL1_SHIFT,
1970	.min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,	1970	.min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
1971	},	1971	},
1972	{	1972	{
1973	.desc = "Protected KVM",	1973	.desc = "Protected KVM",

arch/arm64/kernel/smccc-call.S+6−3

 EXPORT_SYMBOL(__arm_smccc_sve_check)
 	.macro SMCCC instr
+	stp     x29, x30, [sp, #-16]!
+	mov	x29, sp
 alternative_if ARM64_SVE
 	bl	__arm_smccc_sve_check
 alternative_else_nop_endif
 	\instr	#0
-	ldr	x4, [sp]
+	ldr	x4, [sp, #16]
 	stp	x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
 	stp	x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS]
-	ldr	x4, [sp, #8]
+	ldr	x4, [sp, #24]
 	cbz	x4, 1f /* no quirk structure */
 	ldr	x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS]
 	cmp	x9, #ARM_SMCCC_QUIRK_QCOM_A6
 	b.ne	1f
 	str	x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS]
-1:	ret
+1:	ldp     x29, x30, [sp], #16
+	ret
 	.endm
 /*

arch/arm64/kernel/vmlinux.lds.S+2−2

 	/* everything from this point to __init_begin will be marked RO NX */
 	RO_DATA(PAGE_SIZE)
+	HYPERVISOR_DATA_SECTIONS
 	idmap_pg_dir = .;
 	. += IDMAP_DIR_SIZE;
 	idmap_pg_end = .;
 	_sdata = .;
 	RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_ALIGN)
-	HYPERVISOR_DATA_SECTIONS
 	/*
 	 * Data written with the MMU off but read with the MMU on requires
 	 * cache lines to be invalidated, discarding up to a Cache Writeback

arch/arm64/kvm/Kconfig+10−0

 	select HAVE_KVM_ARCH_TLB_FLUSH_ALL
 	select KVM_MMIO
 	select KVM_GENERIC_DIRTYLOG_READ_PROTECT
+	select KVM_XFER_TO_GUEST_WORK
 	select SRCU
 	select KVM_VFIO
 	select HAVE_KVM_EVENTFD
 source "virt/kvm/Kconfig"
+config NVHE_EL2_DEBUG
+	bool "Debug mode for non-VHE EL2 object"
+	help
+	  Say Y here to enable the debug mode for the non-VHE KVM EL2 object.
+	  Failure reports will BUG() in the hypervisor. This is intended for
+	  local EL2 hypervisor development.
+	  If unsure, say N.
 endif # KVM
 endif # VIRTUALIZATION

arch/arm64/kvm/arm.c+71−102

@@ -6,6 +6,7 @@ · 5 unmodified lines
6		6
7	#include <linux/bug.h>	7	#include <linux/bug.h>
8	#include <linux/cpu_pm.h>	8	#include <linux/cpu_pm.h>
		9	#include <linux/entry-kvm.h>
9	#include <linux/errno.h>	10	#include <linux/errno.h>
10	#include <linux/err.h>	11	#include <linux/err.h>
11	#include <linux/kvm_host.h>	12	#include <linux/kvm_host.h>
@@ -15,6 +16,7 @@ · 3 unmodified lines
15	#include <linux/fs.h>	16	#include <linux/fs.h>
16	#include <linux/mman.h>	17	#include <linux/mman.h>
17	#include <linux/sched.h>	18	#include <linux/sched.h>
		19	#include <linux/kmemleak.h>
18	#include <linux/kvm.h>	20	#include <linux/kvm.h>
19	#include <linux/kvm_irqfd.h>	21	#include <linux/kvm_irqfd.h>
20	#include <linux/irqbypass.h>	22	#include <linux/irqbypass.h>
@@ -42,10 +44,6 @@ · 21 unmodified lines
42	#include <kvm/arm_pmu.h>	44	#include <kvm/arm_pmu.h>
43	#include <kvm/arm_psci.h>	45	#include <kvm/arm_psci.h>
44		46
45	#ifdef REQUIRES_VIRT
46	__asm__(".arch_extension virt");
47	#endif
48
49	static enum kvm_mode kvm_mode = KVM_MODE_DEFAULT;	47	static enum kvm_mode kvm_mode = KVM_MODE_DEFAULT;
50	DEFINE_STATIC_KEY_FALSE(kvm_protected_mode_initialized);	48	DEFINE_STATIC_KEY_FALSE(kvm_protected_mode_initialized);
51		49
@@ -94,10 +92,14 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, · 42 unmodified lines
94	kvm->arch.return_nisv_io_abort_to_user = true;	92	kvm->arch.return_nisv_io_abort_to_user = true;
95	break;	93	break;
96	case KVM_CAP_ARM_MTE:	94	case KVM_CAP_ARM_MTE:
97	if (!system_supports_mte() \|\| kvm->created_vcpus)	95	mutex_lock(&kvm->lock);
98	return -EINVAL;	96	if (!system_supports_mte() \|\| kvm->created_vcpus) {
99	r = 0;	97	r = -EINVAL;
100	kvm->arch.mte_enabled = true;	98	} else {
		99	r = 0;
		100	kvm->arch.mte_enabled = true;
		101	}
		102	mutex_unlock(&kvm->lock);
101	break;	103	break;
102	default:	104	default:
103	r = -EINVAL;	105	r = -EINVAL;
@@ -571,7 +573,7 @@ static void update_vmid(struct kvm_vmid *vmid) · 467 unmodified lines
571	kvm_call_hyp(__kvm_flush_vm_context);	573	kvm_call_hyp(__kvm_flush_vm_context);
572	}	574	}
573		575
574	vmid->vmid = kvm_next_vmid;	576	WRITE_ONCE(vmid->vmid, kvm_next_vmid);
575	kvm_next_vmid++;	577	kvm_next_vmid++;
576	kvm_next_vmid &= (1 << kvm_get_vmid_bits()) - 1;	578	kvm_next_vmid &= (1 << kvm_get_vmid_bits()) - 1;
577		579
@@ -714,6 +716,45 @@ static bool vcpu_mode_is_bad_32bit(struct kvm_vcpu *vcpu) · 136 unmodified lines
714	static_branch_unlikely(&arm64_mismatched_32bit_el0);	716	static_branch_unlikely(&arm64_mismatched_32bit_el0);
715	}	717	}
716		718
		719	/**
		720	* kvm_vcpu_exit_request - returns true if the VCPU should not enter the guest
		721	* @vcpu: The VCPU pointer
		722	* @ret: Pointer to write optional return code
		723	*
		724	* Returns: true if the VCPU needs to return to a preemptible + interruptible
		725	* and skip guest entry.
		726	*
		727	* This function disambiguates between two different types of exits: exits to a
		728	* preemptible + interruptible kernel context and exits to userspace. For an
		729	* exit to userspace, this function will write the return code to ret and return
		730	* true. For an exit to preemptible + interruptible kernel context (i.e. check
		731	* for pending work and re-enter), return true without writing to ret.
		732	*/
		733	static bool kvm_vcpu_exit_request(struct kvm_vcpu vcpu, int ret)
		734	{
		735	struct kvm_run *run = vcpu->run;
		736
		737	/*
		738	* If we're using a userspace irqchip, then check if we need
		739	* to tell a userspace irqchip about timer or PMU level
		740	* changes and if so, exit to userspace (the actual level
		741	* state gets updated in kvm_timer_update_run and
		742	* kvm_pmu_update_run below).
		743	*/
		744	if (static_branch_unlikely(&userspace_irqchip_in_use)) {
		745	if (kvm_timer_should_notify_user(vcpu) \|\|
		746	kvm_pmu_should_notify_user(vcpu)) {
		747	*ret = -EINTR;
		748	run->exit_reason = KVM_EXIT_INTR;
		749	return true;
		750	}
		751	}
		752
		753	return kvm_request_pending(vcpu) \|\|
		754	need_new_vmid_gen(&vcpu->arch.hw_mmu->vmid) \|\|
		755	xfer_to_guest_mode_work_pending();
		756	}
		757
717	/**	758	/**
718	* kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code	759	* kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code
719	* @vcpu: The VCPU pointer	760	* @vcpu: The VCPU pointer
@@ -757,7 +798,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) · 37 unmodified lines
757	/*	798	/*
758	* Check conditions before entering the guest	799	* Check conditions before entering the guest
759	*/	800	*/
760	cond_resched();	801	ret = xfer_to_guest_mode_handle_work(vcpu);
		802	if (!ret)
		803	ret = 1;
761		804
762	update_vmid(&vcpu->arch.hw_mmu->vmid);	805	update_vmid(&vcpu->arch.hw_mmu->vmid);
763		806
@@ -776,30 +819,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) · 12 unmodified lines
776		819
777	kvm_vgic_flush_hwstate(vcpu);	820	kvm_vgic_flush_hwstate(vcpu);
778		821
779	/*
780	* Exit if we have a signal pending so that we can deliver the
781	* signal to user space.
782	*/
783	if (signal_pending(current)) {
784	ret = -EINTR;
785	run->exit_reason = KVM_EXIT_INTR;
786	}
787
788	/*
789	* If we're using a userspace irqchip, then check if we need
790	* to tell a userspace irqchip about timer or PMU level
791	* changes and if so, exit to userspace (the actual level
792	* state gets updated in kvm_timer_update_run and
793	* kvm_pmu_update_run below).
794	*/
795	if (static_branch_unlikely(&userspace_irqchip_in_use)) {
796	if (kvm_timer_should_notify_user(vcpu) \|\|
797	kvm_pmu_should_notify_user(vcpu)) {
798	ret = -EINTR;
799	run->exit_reason = KVM_EXIT_INTR;
800	}
801	}
802
803	/*	822	/*
804	* Ensure we set mode to IN_GUEST_MODE after we disable	823	* Ensure we set mode to IN_GUEST_MODE after we disable
805	* interrupts and before the final VCPU requests check.	824	* interrupts and before the final VCPU requests check.
@@ -808,8 +827,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) · 2 unmodified lines
808	*/	827	*/
809	smp_store_mb(vcpu->mode, IN_GUEST_MODE);	828	smp_store_mb(vcpu->mode, IN_GUEST_MODE);
810		829
811	if (ret <= 0 \|\| need_new_vmid_gen(&vcpu->arch.hw_mmu->vmid) \|\|	830	if (ret <= 0 \|\| kvm_vcpu_exit_request(vcpu, &ret)) {
812	kvm_request_pending(vcpu)) {
813	vcpu->mode = OUTSIDE_GUEST_MODE;	831	vcpu->mode = OUTSIDE_GUEST_MODE;
814	isb(); /* Ensure work in x_flush_hwstate is committed */	832	isb(); /* Ensure work in x_flush_hwstate is committed */
815	kvm_pmu_sync_hwstate(vcpu);	833	kvm_pmu_sync_hwstate(vcpu);
@@ -1035,7 +1053,7 @@ static int kvm_vcpu_set_target(struct kvm_vcpu *vcpu, · 219 unmodified lines
1035	const struct kvm_vcpu_init *init)	1053	const struct kvm_vcpu_init *init)
1036	{	1054	{
1037	unsigned int i, ret;	1055	unsigned int i, ret;
1038	int phys_target = kvm_target_cpu();	1056	u32 phys_target = kvm_target_cpu();
1039		1057
1040	if (init->target != phys_target)	1058	if (init->target != phys_target)
1041	return -EINVAL;	1059	return -EINVAL;
@@ -1104,6 +1122,7 @@ static int kvm_arch_vcpu_ioctl_vcpu_init(struct kvm_vcpu *vcpu, · 62 unmodified lines
1104	}	1122	}
1105		1123
1106	vcpu_reset_hcr(vcpu);	1124	vcpu_reset_hcr(vcpu);
		1125	vcpu->arch.cptr_el2 = CPTR_EL2_DEFAULT;
1107		1126
1108	/*	1127	/*
1109	* Handle the "start in power-off" case.	1128	* Handle the "start in power-off" case.
@@ -1215,6 +1234,14 @@ long kvm_arch_vcpu_ioctl(struct file *filp, · 105 unmodified lines
1215	if (copy_from_user(&reg, argp, sizeof(reg)))	1234	if (copy_from_user(&reg, argp, sizeof(reg)))
1216	break;	1235	break;
1217		1236
		1237	/*
		1238	* We could owe a reset due to PSCI. Handle the pending reset
		1239	* here to ensure userspace register accesses are ordered after
		1240	* the reset.
		1241	*/
		1242	if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu))
		1243	kvm_reset_vcpu(vcpu);
		1244
1218	if (ioctl == KVM_SET_ONE_REG)	1245	if (ioctl == KVM_SET_ONE_REG)
1219	r = kvm_arm_set_reg(vcpu, &reg);	1246	r = kvm_arm_set_reg(vcpu, &reg);
1220	else	1247	else
@@ -1696,11 +1723,6 @@ static bool init_psci_relay(void) · 475 unmodified lines
1696	return true;	1723	return true;
1697	}	1724	}
1698		1725
1699	static int init_common_resources(void)
1700	{
1701	return kvm_set_ipa_limit();
1702	}
1703
1704	static int init_subsystems(void)	1726	static int init_subsystems(void)
1705	{	1727	{
1706	int err = 0;	1728	int err = 0;
@@ -1954,56 +1976,17 @@ static void _kvm_host_prot_finalize(void *discard) · 247 unmodified lines
1954	WARN_ON(kvm_call_hyp_nvhe(__pkvm_prot_finalize));	1976	WARN_ON(kvm_call_hyp_nvhe(__pkvm_prot_finalize));
1955	}	1977	}
1956		1978
1957	static inline int pkvm_mark_hyp(phys_addr_t start, phys_addr_t end)
1958	{
1959	return kvm_call_hyp_nvhe(__pkvm_mark_hyp, start, end);
1960	}
1961
1962	#define pkvm_mark_hyp_section(__section) \
1963	pkvm_mark_hyp(__pa_symbol(__section##_start), \
1964	__pa_symbol(__section##_end))
1965
1966	static int finalize_hyp_mode(void)	1979	static int finalize_hyp_mode(void)
1967	{	1980	{
1968	int cpu, ret;
1969
1970	if (!is_protected_kvm_enabled())	1981	if (!is_protected_kvm_enabled())
1971	return 0;	1982	return 0;
1972		1983
1973	ret = pkvm_mark_hyp_section(__hyp_idmap_text);	1984	/*
1974	if (ret)	1985	* Exclude HYP BSS from kmemleak so that it doesn't get peeked
1975	return ret;	1986	* at, which would end badly once the section is inaccessible.
1976		1987	* None of other sections should ever be introspected.
1977	ret = pkvm_mark_hyp_section(__hyp_text);	1988	*/
1978	if (ret)	1989	kmemleak_free_part(__hyp_bss_start, __hyp_bss_end - __hyp_bss_start);
1979	return ret;
1980
1981	ret = pkvm_mark_hyp_section(__hyp_rodata);
1982	if (ret)
1983	return ret;
1984
1985	ret = pkvm_mark_hyp_section(__hyp_bss);
1986	if (ret)
1987	return ret;
1988
1989	ret = pkvm_mark_hyp(hyp_mem_base, hyp_mem_base + hyp_mem_size);
1990	if (ret)
1991	return ret;
1992
1993	for_each_possible_cpu(cpu) {
1994	phys_addr_t start = virt_to_phys((void *)kvm_arm_hyp_percpu_base[cpu]);
1995	phys_addr_t end = start + (PAGE_SIZE << nvhe_percpu_order());
1996
1997	ret = pkvm_mark_hyp(start, end);
1998	if (ret)
1999	return ret;
2000
2001	start = virt_to_phys((void *)per_cpu(kvm_arm_hyp_stack_page, cpu));
2002	end = start + PAGE_SIZE;
2003	ret = pkvm_mark_hyp(start, end);
2004	if (ret)
2005	return ret;
2006	}
2007		1990
2008	/*	1991	/*
2009	* Flip the static key upfront as that may no longer be possible	1992	* Flip the static key upfront as that may no longer be possible
@@ -2015,11 +1998,6 @@ static int finalize_hyp_mode(void) · 5 unmodified lines
2015	return 0;	1998	return 0;
2016	}	1999	}
2017		2000
2018	static void check_kvm_target_cpu(void *ret)
2019	{
2020	(int )ret = kvm_target_cpu();
2021	}
2022
2023	struct kvm_vcpu kvm_mpidr_to_vcpu(struct kvm kvm, unsigned long mpidr)	2001	struct kvm_vcpu kvm_mpidr_to_vcpu(struct kvm kvm, unsigned long mpidr)
2024	{	2002	{
2025	struct kvm_vcpu *vcpu;	2003	struct kvm_vcpu *vcpu;
@@ -2079,7 +2057,6 @@ void kvm_arch_irq_bypass_start(struct irq_bypass_consumer *cons) · 53 unmodified lines
2079	int kvm_arch_init(void *opaque)	2057	int kvm_arch_init(void *opaque)
2080	{	2058	{
2081	int err;	2059	int err;
2082	int ret, cpu;
2083	bool in_hyp_mode;	2060	bool in_hyp_mode;
2084		2061
2085	if (!is_hyp_mode_available()) {	2062	if (!is_hyp_mode_available()) {
@@ -2094,15 +2071,7 @@ int kvm_arch_init(void *opaque) · 8 unmodified lines
2094	kvm_info("Guests without required CPU erratum workarounds can deadlock system!\n" \	2071	kvm_info("Guests without required CPU erratum workarounds can deadlock system!\n" \
2095	"Only trusted guests should be used on this system.\n");	2072	"Only trusted guests should be used on this system.\n");
2096		2073
2097	for_each_online_cpu(cpu) {	2074	err = kvm_set_ipa_limit();
2098	smp_call_function_single(cpu, check_kvm_target_cpu, &ret, 1);
2099	if (ret < 0) {
2100	kvm_err("Error, CPU %d not supported!\n", cpu);
2101	return -ENODEV;
2102	}
2103	}
2104
2105	err = init_common_resources();
2106	if (err)	2075	if (err)
2107	return err;	2076	return err;
2108		2077

arch/arm64/kvm/debug.c+1−1

@@ -21,7 +21,7 @@ · 20 unmodified lines
21	DBG_MDSCR_KDE \| \	21	DBG_MDSCR_KDE \| \
22	DBG_MDSCR_MDE)	22	DBG_MDSCR_MDE)
23		23
24	static DEFINE_PER_CPU(u32, mdcr_el2);	24	static DEFINE_PER_CPU(u64, mdcr_el2);
25		25
26	/**	26	/**
27	* save/restore_guest_debug_regs	27	* save/restore_guest_debug_regs

arch/arm64/kvm/guest.c+3−2

 	STATS_DESC_COUNTER(VCPU, wfi_exit_stat),
 	STATS_DESC_COUNTER(VCPU, mmio_exit_user),
 	STATS_DESC_COUNTER(VCPU, mmio_exit_kernel),
+	STATS_DESC_COUNTER(VCPU, signal_exits),
 	STATS_DESC_COUNTER(VCPU, exits)
 };
 	return 0;
 }
-int __attribute_const__ kvm_target_cpu(void)
+u32 __attribute_const__ kvm_target_cpu(void)
 {
 	unsigned long implementor = read_cpuid_implementor();
 	unsigned long part_number = read_cpuid_part_number();
 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init)
 {
-	int target = kvm_target_cpu();
+	u32 target = kvm_target_cpu();
 	if (target < 0)
 		return -ENODEV;

arch/arm64/kvm/handle_exit.c+17−26

  * guest and host are using the same debug facilities it will be up to
  * userspace to re-inject the correct exception for guest delivery.
  *
- * @return: 0 (while setting vcpu->run->exit_reason), -1 for error
+ * @return: 0 (while setting vcpu->run->exit_reason)
  */
 static int kvm_handle_guest_debug(struct kvm_vcpu *vcpu)
 {
 	struct kvm_run *run = vcpu->run;
 	u32 esr = kvm_vcpu_get_esr(vcpu);
-	int ret = 0;
 	run->exit_reason = KVM_EXIT_DEBUG;
 	run->debug.arch.hsr = esr;
-	switch (ESR_ELx_EC(esr)) {
+	if (ESR_ELx_EC(esr) == ESR_ELx_EC_WATCHPT_LOW)
-	case ESR_ELx_EC_WATCHPT_LOW:
 		run->debug.arch.far = vcpu->arch.fault.far_el2;
-		fallthrough;
-	case ESR_ELx_EC_SOFTSTP_LOW:
-	case ESR_ELx_EC_BREAKPT_LOW:
-	case ESR_ELx_EC_BKPT32:
-	case ESR_ELx_EC_BRK64:
-		break;
-	default:
-		kvm_err("%s: un-handled case esr: %#08x\n",
-			__func__, (unsigned int) esr);
-		ret = -1;
-		break;
-	}
-	return ret;
+	return 0;
 }
 static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu)
 		kvm_handle_guest_serror(vcpu, kvm_vcpu_get_esr(vcpu));
 }
-void __noreturn __cold nvhe_hyp_panic_handler(u64 esr, u64 spsr, u64 elr,
+void __noreturn __cold nvhe_hyp_panic_handler(u64 esr, u64 spsr,
+					      u64 elr_virt, u64 elr_phys,
 					      u64 par, uintptr_t vcpu,
 					      u64 far, u64 hpfar) {
-	u64 elr_in_kimg = __phys_to_kimg(__hyp_pa(elr));
+	u64 elr_in_kimg = __phys_to_kimg(elr_phys);
-	u64 hyp_offset = elr_in_kimg - kaslr_offset() - elr;
+	u64 hyp_offset = elr_in_kimg - kaslr_offset() - elr_virt;
 	u64 mode = spsr & PSR_MODE_MASK;
 	/*
 		kvm_err("Invalid host exception to nVHE hyp!\n");
 	} else if (ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 &&
 		   (esr & ESR_ELx_BRK64_ISS_COMMENT_MASK) == BUG_BRK_IMM) {
-		struct bug_entry *bug = find_bug(elr_in_kimg);
 		const char *file = NULL;
 		unsigned int line = 0;
 		/* All hyp bugs, including warnings, are treated as fatal. */
-		if (bug)
+		if (!is_protected_kvm_enabled() ||
-			bug_get_file_line(bug, &file, &line);
+		    IS_ENABLED(CONFIG_NVHE_EL2_DEBUG)) {
+			struct bug_entry *bug = find_bug(elr_in_kimg);
+			if (bug)
+				bug_get_file_line(bug, &file, &line);
+		}
 		if (file)
 			kvm_err("nVHE hyp BUG at: %s:%u!\n", file, line);
 		else
-			kvm_err("nVHE hyp BUG at: %016llx!\n", elr + hyp_offset);
+			kvm_err("nVHE hyp BUG at: %016llx!\n", elr_virt + hyp_offset);
 	} else {
-		kvm_err("nVHE hyp panic at: %016llx!\n", elr + hyp_offset);
+		kvm_err("nVHE hyp panic at: %016llx!\n", elr_virt + hyp_offset);
 	}
 	/*
 	kvm_err("Hyp Offset: 0x%llx\n", hyp_offset);
 	panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%016lx\n",
-	      spsr, elr, esr, far, hpfar, par, vcpu);
+	      spsr, elr_virt, esr, far, hpfar, par, vcpu);
 }

arch/arm64/kvm/hyp/include/hyp/switch.h+5−1

 		write_sysreg(0, pmselr_el0);
 		write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
 	}
+	vcpu->arch.mdcr_el2_host = read_sysreg(mdcr_el2);
 	write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
 }
-static inline void __deactivate_traps_common(void)
+static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
 {
+	write_sysreg(vcpu->arch.mdcr_el2_host, mdcr_el2);
 	write_sysreg(0, hstr_el2);
 	if (kvm_arm_support_pmu_v3())
 		write_sysreg(0, pmuserenr_el0);

arch/arm64/kvm/hyp/include/nvhe/mem_protect.h+33−2

@@ -12,6 +12,32 @@ · 11 unmodified lines
12	#include <asm/virt.h>	12	#include <asm/virt.h>
13	#include <nvhe/spinlock.h>	13	#include <nvhe/spinlock.h>
14		14
		15	/*
		16	* SW bits 0-1 are reserved to track the memory ownership state of each page:
		17	* 00: The page is owned exclusively by the page-table owner.
		18	* 01: The page is owned by the page-table owner, but is shared
		19	* with another entity.
		20	* 10: The page is shared with, but not owned by the page-table owner.
		21	* 11: Reserved for future use (lending).
		22	*/
		23	enum pkvm_page_state {
		24	PKVM_PAGE_OWNED = 0ULL,
		25	PKVM_PAGE_SHARED_OWNED = KVM_PGTABLE_PROT_SW0,
		26	PKVM_PAGE_SHARED_BORROWED = KVM_PGTABLE_PROT_SW1,
		27	};
		28
		29	#define PKVM_PAGE_STATE_PROT_MASK (KVM_PGTABLE_PROT_SW0 \| KVM_PGTABLE_PROT_SW1)
		30	static inline enum kvm_pgtable_prot pkvm_mkstate(enum kvm_pgtable_prot prot,
		31	enum pkvm_page_state state)
		32	{
		33	return (prot & ~PKVM_PAGE_STATE_PROT_MASK) \| state;
		34	}
		35
		36	static inline enum pkvm_page_state pkvm_getstate(enum kvm_pgtable_prot prot)
		37	{
		38	return prot & PKVM_PAGE_STATE_PROT_MASK;
		39	}
		40
15	struct host_kvm {	41	struct host_kvm {
16	struct kvm_arch arch;	42	struct kvm_arch arch;
17	struct kvm_pgtable pgt;	43	struct kvm_pgtable pgt;
@@ -20,16 +46,21 @@ struct host_kvm { · 2 unmodified lines
20	};	46	};
21	extern struct host_kvm host_kvm;	47	extern struct host_kvm host_kvm;
22		48
		49	extern const u8 pkvm_hyp_id;
		50
23	int __pkvm_prot_finalize(void);	51	int __pkvm_prot_finalize(void);
24	int __pkvm_mark_hyp(phys_addr_t start, phys_addr_t end);	52	int __pkvm_host_share_hyp(u64 pfn);
25		53
		54	bool addr_is_memory(phys_addr_t phys);
		55	int host_stage2_idmap_locked(phys_addr_t addr, u64 size, enum kvm_pgtable_prot prot);
		56	int host_stage2_set_owner_locked(phys_addr_t addr, u64 size, u8 owner_id);
26	int kvm_host_prepare_stage2(void *pgt_pool_base);	57	int kvm_host_prepare_stage2(void *pgt_pool_base);
27	void handle_host_mem_abort(struct kvm_cpu_context *host_ctxt);	58	void handle_host_mem_abort(struct kvm_cpu_context *host_ctxt);
28		59
29	static __always_inline void __load_host_stage2(void)	60	static __always_inline void __load_host_stage2(void)
30	{	61	{
31	if (static_branch_likely(&kvm_protected_mode_initialized))	62	if (static_branch_likely(&kvm_protected_mode_initialized))
32	__load_stage2(&host_kvm.arch.mmu, host_kvm.arch.vtcr);	63	__load_stage2(&host_kvm.arch.mmu, &host_kvm.arch);
33	else	64	else
34	write_sysreg(0, vttbr_el2);	65	write_sysreg(0, vttbr_el2);
35	}	66	}

arch/arm64/kvm/hyp/include/nvhe/mm.h+1−2

@@ -23,8 +23,7 @@ int hyp_map_vectors(void); · 22 unmodified lines
23	int hyp_back_vmemmap(phys_addr_t phys, unsigned long size, phys_addr_t back);	23	int hyp_back_vmemmap(phys_addr_t phys, unsigned long size, phys_addr_t back);
24	int pkvm_cpu_set_vector(enum arm64_hyp_spectre_vector slot);	24	int pkvm_cpu_set_vector(enum arm64_hyp_spectre_vector slot);
25	int pkvm_create_mappings(void from, void to, enum kvm_pgtable_prot prot);	25	int pkvm_create_mappings(void from, void to, enum kvm_pgtable_prot prot);
26	int __pkvm_create_mappings(unsigned long start, unsigned long size,	26	int pkvm_create_mappings_locked(void from, void to, enum kvm_pgtable_prot prot);
27	unsigned long phys, enum kvm_pgtable_prot prot);
28	unsigned long __pkvm_create_private_mapping(phys_addr_t phys, size_t size,	27	unsigned long __pkvm_create_private_mapping(phys_addr_t phys, size_t size,
29	enum kvm_pgtable_prot prot);	28	enum kvm_pgtable_prot prot);
30		29

arch/arm64/kvm/hyp/include/nvhe/spinlock.h+25−0

@@ -15,6 +15,7 @@ · 14 unmodified lines
15		15
16	#include <asm/alternative.h>	16	#include <asm/alternative.h>
17	#include <asm/lse.h>	17	#include <asm/lse.h>
		18	#include <asm/rwonce.h>
18		19
19	typedef union hyp_spinlock {	20	typedef union hyp_spinlock {
20	u32 __val;	21	u32 __val;
@@ -89,4 +90,28 @@ static inline void hyp_spin_unlock(hyp_spinlock_t *lock) · 68 unmodified lines
89	: "memory");	90	: "memory");
90	}	91	}
91		92
		93	static inline bool hyp_spin_is_locked(hyp_spinlock_t *lock)
		94	{
		95	hyp_spinlock_t lockval = READ_ONCE(*lock);
		96
		97	return lockval.owner != lockval.next;
		98	}
		99
		100	#ifdef CONFIG_NVHE_EL2_DEBUG
		101	static inline void hyp_assert_lock_held(hyp_spinlock_t *lock)
		102	{
		103	/*
		104	* The __pkvm_init() path accesses protected data-structures without
		105	* holding locks as the other CPUs are guaranteed to not enter EL2
		106	* concurrently at this point in time. The point by which EL2 is
		107	* initialized on all CPUs is reflected in the pkvm static key, so
		108	* wait until it is set before checking the lock state.
		109	*/
		110	if (static_branch_likely(&kvm_protected_mode_initialized))
		111	BUG_ON(!hyp_spin_is_locked(lock));
		112	}
		113	#else
		114	static inline void hyp_assert_lock_held(hyp_spinlock_t *lock) { }
		115	#endif
		116
92	#endif /* __ARM64_KVM_NVHE_SPINLOCK_H__ */	117	#endif /* __ARM64_KVM_NVHE_SPINLOCK_H__ */

arch/arm64/kvm/hyp/nvhe/debug-sr.c+1−1

@@ -109,7 +109,7 @@ void __debug_switch_to_host(struct kvm_vcpu *vcpu) · 108 unmodified lines
109	__debug_switch_to_host_common(vcpu);	109	__debug_switch_to_host_common(vcpu);
110	}	110	}
111		111
112	u32 __kvm_get_mdcr_el2(void)	112	u64 __kvm_get_mdcr_el2(void)
113	{	113	{
114	return read_sysreg(mdcr_el2);	114	return read_sysreg(mdcr_el2);
115	}	115	}

arch/arm64/kvm/hyp/nvhe/host.S+17−4

 #include <linux/linkage.h>
 #include <asm/assembler.h>
+#include <asm/kvm_arm.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmu.h>
 	mov	x29, x0
+#ifdef CONFIG_NVHE_EL2_DEBUG
+	/* Ensure host stage-2 is disabled */
+	mrs	x0, hcr_el2
+	bic	x0, x0, #HCR_VM
+	msr	hcr_el2, x0
+	isb
+	tlbi	vmalls12e1
+	dsb	nsh
+#endif
 	/* Load the panic arguments into x0-7 */
 	mrs	x0, esr_el2
-	get_vcpu_ptr x4, x5
+	mov	x4, x3
-	mrs	x5, far_el2
+	mov	x3, x2
-	mrs	x6, hpfar_el2
+	hyp_pa	x3, x6
-	mov	x7, xzr			// Unused argument
+	get_vcpu_ptr x5, x6
+	mrs	x6, far_el2
+	mrs	x7, hpfar_el2
 	/* Enter the host, conditionally restoring the host context. */
 	cbz	x29, __host_enter_without_restoring

arch/arm64/kvm/hyp/nvhe/hyp-main.c+4−16

 	cpu_reg(host_ctxt, 1) = pkvm_cpu_set_vector(slot);
 }
-static void handle___pkvm_create_mappings(struct kvm_cpu_context *host_ctxt)
+static void handle___pkvm_host_share_hyp(struct kvm_cpu_context *host_ctxt)
 {
-	DECLARE_REG(unsigned long, start, host_ctxt, 1);
+	DECLARE_REG(u64, pfn, host_ctxt, 1);
-	DECLARE_REG(unsigned long, size, host_ctxt, 2);
-	DECLARE_REG(unsigned long, phys, host_ctxt, 3);
-	DECLARE_REG(enum kvm_pgtable_prot, prot, host_ctxt, 4);
-	cpu_reg(host_ctxt, 1) = __pkvm_create_mappings(start, size, phys, prot);
+	cpu_reg(host_ctxt, 1) = __pkvm_host_share_hyp(pfn);
 }
 static void handle___pkvm_create_private_mapping(struct kvm_cpu_context *host_ctxt)
 {
 	cpu_reg(host_ctxt, 1) = __pkvm_prot_finalize();
 }
-static void handle___pkvm_mark_hyp(struct kvm_cpu_context *host_ctxt)
-{
-	DECLARE_REG(phys_addr_t, start, host_ctxt, 1);
-	DECLARE_REG(phys_addr_t, end, host_ctxt, 2);
-	cpu_reg(host_ctxt, 1) = __pkvm_mark_hyp(start, end);
-}
 typedef void (*hcall_t)(struct kvm_cpu_context *);
 #define HANDLE_FUNC(x)	[__KVM_HOST_SMCCC_FUNC_##x] = (hcall_t)handle_##x
 	HANDLE_FUNC(__vgic_v3_restore_aprs),
 	HANDLE_FUNC(__pkvm_init),
 	HANDLE_FUNC(__pkvm_cpu_set_vector),
-	HANDLE_FUNC(__pkvm_create_mappings),
+	HANDLE_FUNC(__pkvm_host_share_hyp),
 	HANDLE_FUNC(__pkvm_create_private_mapping),
 	HANDLE_FUNC(__pkvm_prot_finalize),
-	HANDLE_FUNC(__pkvm_mark_hyp),
 };
 static void handle_host_hcall(struct kvm_cpu_context *host_ctxt)

arch/arm64/kvm/hyp/nvhe/mem_protect.c+205−39

@@ -31,7 +31,7 @@ static struct hyp_pool host_s2_pool; · 30 unmodified lines
31	u64 id_aa64mmfr0_el1_sys_val;	31	u64 id_aa64mmfr0_el1_sys_val;
32	u64 id_aa64mmfr1_el1_sys_val;	32	u64 id_aa64mmfr1_el1_sys_val;
33		33
34	static const u8 pkvm_hyp_id = 1;	34	const u8 pkvm_hyp_id = 1;
35		35
36	static void *host_s2_zalloc_pages_exact(size_t size)	36	static void *host_s2_zalloc_pages_exact(size_t size)
37	{	37	{
@@ -89,6 +89,8 @@ static void prepare_host_vtcr(void) · 51 unmodified lines
89	id_aa64mmfr1_el1_sys_val, phys_shift);	89	id_aa64mmfr1_el1_sys_val, phys_shift);
90	}	90	}
91		91
		92	static bool host_stage2_force_pte_cb(u64 addr, u64 end, enum kvm_pgtable_prot prot);
		93
92	int kvm_host_prepare_stage2(void *pgt_pool_base)	94	int kvm_host_prepare_stage2(void *pgt_pool_base)
93	{	95	{
94	struct kvm_s2_mmu *mmu = &host_kvm.arch.mmu;	96	struct kvm_s2_mmu *mmu = &host_kvm.arch.mmu;
@@ -101,16 +103,17 @@ int kvm_host_prepare_stage2(void *pgt_pool_base) · 6 unmodified lines
101	if (ret)	103	if (ret)
102	return ret;	104	return ret;
103		105
104	ret = kvm_pgtable_stage2_init_flags(&host_kvm.pgt, &host_kvm.arch,	106	ret = __kvm_pgtable_stage2_init(&host_kvm.pgt, &host_kvm.arch,
105	&host_kvm.mm_ops, KVM_HOST_S2_FLAGS);	107	&host_kvm.mm_ops, KVM_HOST_S2_FLAGS,
		108	host_stage2_force_pte_cb);
106	if (ret)	109	if (ret)
107	return ret;	110	return ret;
108		111
109	mmu->pgd_phys = __hyp_pa(host_kvm.pgt.pgd);	112	mmu->pgd_phys = __hyp_pa(host_kvm.pgt.pgd);
110	mmu->arch = &host_kvm.arch;	113	mmu->arch = &host_kvm.arch;
111	mmu->pgt = &host_kvm.pgt;	114	mmu->pgt = &host_kvm.pgt;
112	mmu->vmid.vmid_gen = 0;	115	WRITE_ONCE(mmu->vmid.vmid_gen, 0);
113	mmu->vmid.vmid = 0;	116	WRITE_ONCE(mmu->vmid.vmid, 0);
114		117
115	return 0;	118	return 0;
116	}	119	}
@@ -126,7 +129,7 @@ int __pkvm_prot_finalize(void) · 9 unmodified lines
126	kvm_flush_dcache_to_poc(params, sizeof(*params));	129	kvm_flush_dcache_to_poc(params, sizeof(*params));
127		130
128	write_sysreg(params->hcr_el2, hcr_el2);	131	write_sysreg(params->hcr_el2, hcr_el2);
129	__load_stage2(&host_kvm.arch.mmu, host_kvm.arch.vtcr);	132	__load_stage2(&host_kvm.arch.mmu, &host_kvm.arch);
130		133
131	/*	134	/*
132	* Make sure to have an ISB before the TLB maintenance below but only	135	* Make sure to have an ISB before the TLB maintenance below but only
@@ -159,6 +162,11 @@ static int host_stage2_unmap_dev_all(void) · 26 unmodified lines
159	return kvm_pgtable_stage2_unmap(pgt, addr, BIT(pgt->ia_bits) - addr);	162	return kvm_pgtable_stage2_unmap(pgt, addr, BIT(pgt->ia_bits) - addr);
160	}	163	}
161		164
		165	struct kvm_mem_range {
		166	u64 start;
		167	u64 end;
		168	};
		169
162	static bool find_mem_range(phys_addr_t addr, struct kvm_mem_range *range)	170	static bool find_mem_range(phys_addr_t addr, struct kvm_mem_range *range)
163	{	171	{
164	int cur, left = 0, right = hyp_memblock_nr;	172	int cur, left = 0, right = hyp_memblock_nr;
@@ -189,16 +197,26 @@ static bool find_mem_range(phys_addr_t addr, struct kvm_mem_range *range) · 24 unmodified lines
189	return false;	197	return false;
190	}	198	}
191		199
		200	bool addr_is_memory(phys_addr_t phys)
		201	{
		202	struct kvm_mem_range range;
		203
		204	return find_mem_range(phys, &range);
		205	}
		206
		207	static bool is_in_mem_range(u64 addr, struct kvm_mem_range *range)
		208	{
		209	return range->start <= addr && addr < range->end;
		210	}
		211
192	static bool range_is_memory(u64 start, u64 end)	212	static bool range_is_memory(u64 start, u64 end)
193	{	213	{
194	struct kvm_mem_range r1, r2;	214	struct kvm_mem_range r;
195		215
196	if (!find_mem_range(start, &r1) \|\| !find_mem_range(end, &r2))	216	if (!find_mem_range(start, &r))
197	return false;
198	if (r1.start != r2.start)
199	return false;	217	return false;
200		218
201	return true;	219	return is_in_mem_range(end - 1, &r);
202	}	220	}
203		221
204	static inline int __host_stage2_idmap(u64 start, u64 end,	222	static inline int __host_stage2_idmap(u64 start, u64 end,
@@ -208,60 +226,208 @@ static inline int __host_stage2_idmap(u64 start, u64 end, · 3 unmodified lines
208	prot, &host_s2_pool);	226	prot, &host_s2_pool);
209	}	227	}
210		228
		229	/*
		230	* The pool has been provided with enough pages to cover all of memory with
		231	* page granularity, but it is difficult to know how much of the MMIO range
		232	* we will need to cover upfront, so we may need to 'recycle' the pages if we
		233	* run out.
		234	*/
		235	#define host_stage2_try(fn, ...) \
		236	({ \
		237	int __ret; \
		238	hyp_assert_lock_held(&host_kvm.lock); \
		239	__ret = fn(__VA_ARGS__); \
		240	if (__ret == -ENOMEM) { \
		241	__ret = host_stage2_unmap_dev_all(); \
		242	if (!__ret) \
		243	__ret = fn(__VA_ARGS__); \
		244	} \
		245	__ret; \
		246	})
		247
		248	static inline bool range_included(struct kvm_mem_range *child,
		249	struct kvm_mem_range *parent)
		250	{
		251	return parent->start <= child->start && child->end <= parent->end;
		252	}
		253
		254	static int host_stage2_adjust_range(u64 addr, struct kvm_mem_range *range)
		255	{
		256	struct kvm_mem_range cur;
		257	kvm_pte_t pte;
		258	u32 level;
		259	int ret;
		260
		261	hyp_assert_lock_held(&host_kvm.lock);
		262	ret = kvm_pgtable_get_leaf(&host_kvm.pgt, addr, &pte, &level);
		263	if (ret)
		264	return ret;
		265
		266	if (kvm_pte_valid(pte))
		267	return -EAGAIN;
		268
		269	if (pte)
		270	return -EPERM;
		271
		272	do {
		273	u64 granule = kvm_granule_size(level);
		274	cur.start = ALIGN_DOWN(addr, granule);
		275	cur.end = cur.start + granule;
		276	level++;
		277	} while ((level < KVM_PGTABLE_MAX_LEVELS) &&
		278	!(kvm_level_supports_block_mapping(level) &&
		279	range_included(&cur, range)));
		280
		281	*range = cur;
		282
		283	return 0;
		284	}
		285
		286	int host_stage2_idmap_locked(phys_addr_t addr, u64 size,
		287	enum kvm_pgtable_prot prot)
		288	{
		289	hyp_assert_lock_held(&host_kvm.lock);
		290
		291	return host_stage2_try(__host_stage2_idmap, addr, addr + size, prot);
		292	}
		293
		294	int host_stage2_set_owner_locked(phys_addr_t addr, u64 size, u8 owner_id)
		295	{
		296	hyp_assert_lock_held(&host_kvm.lock);
		297
		298	return host_stage2_try(kvm_pgtable_stage2_set_owner, &host_kvm.pgt,
		299	addr, size, &host_s2_pool, owner_id);
		300	}
		301
		302	static bool host_stage2_force_pte_cb(u64 addr, u64 end, enum kvm_pgtable_prot prot)
		303	{
		304	/*
		305	* Block mappings must be used with care in the host stage-2 as a
		306	* kvm_pgtable_stage2_map() operation targeting a page in the range of
		307	* an existing block will delete the block under the assumption that
		308	* mappings in the rest of the block range can always be rebuilt lazily.
		309	* That assumption is correct for the host stage-2 with RWX mappings
		310	* targeting memory or RW mappings targeting MMIO ranges (see
		311	* host_stage2_idmap() below which implements some of the host memory
		312	* abort logic). However, this is not safe for any other mappings where
		313	* the host stage-2 page-table is in fact the only place where this
		314	* state is stored. In all those cases, it is safer to use page-level
		315	* mappings, hence avoiding to lose the state because of side-effects in
		316	* kvm_pgtable_stage2_map().
		317	*/
		318	if (range_is_memory(addr, end))
		319	return prot != PKVM_HOST_MEM_PROT;
		320	else
		321	return prot != PKVM_HOST_MMIO_PROT;
		322	}
		323
211	static int host_stage2_idmap(u64 addr)	324	static int host_stage2_idmap(u64 addr)
212	{	325	{
213	enum kvm_pgtable_prot prot = KVM_PGTABLE_PROT_R \| KVM_PGTABLE_PROT_W;
214	struct kvm_mem_range range;	326	struct kvm_mem_range range;
215	bool is_memory = find_mem_range(addr, &range);	327	bool is_memory = find_mem_range(addr, &range);
		328	enum kvm_pgtable_prot prot;
216	int ret;	329	int ret;
217		330
218	if (is_memory)	331	prot = is_memory ? PKVM_HOST_MEM_PROT : PKVM_HOST_MMIO_PROT;
219	prot \|= KVM_PGTABLE_PROT_X;
220		332
221	hyp_spin_lock(&host_kvm.lock);	333	hyp_spin_lock(&host_kvm.lock);
222	ret = kvm_pgtable_stage2_find_range(&host_kvm.pgt, addr, prot, &range);	334	ret = host_stage2_adjust_range(addr, &range);
223	if (ret)	335	if (ret)
224	goto unlock;	336	goto unlock;
225		337
226	ret = __host_stage2_idmap(range.start, range.end, prot);	338	ret = host_stage2_idmap_locked(range.start, range.end - range.start, prot);
227	if (ret != -ENOMEM)	339	unlock:
		340	hyp_spin_unlock(&host_kvm.lock);
		341
		342	return ret;
		343	}
		344
		345	static inline bool check_prot(enum kvm_pgtable_prot prot,
		346	enum kvm_pgtable_prot required,
		347	enum kvm_pgtable_prot denied)
		348	{
		349	return (prot & (required \| denied)) == required;
		350	}
		351
		352	int __pkvm_host_share_hyp(u64 pfn)
		353	{
		354	phys_addr_t addr = hyp_pfn_to_phys(pfn);
		355	enum kvm_pgtable_prot prot, cur;
		356	void *virt = __hyp_va(addr);
		357	enum pkvm_page_state state;
		358	kvm_pte_t pte;
		359	int ret;
		360
		361	if (!addr_is_memory(addr))
		362	return -EINVAL;
		363
		364	hyp_spin_lock(&host_kvm.lock);
		365	hyp_spin_lock(&pkvm_pgd_lock);
		366
		367	ret = kvm_pgtable_get_leaf(&host_kvm.pgt, addr, &pte, NULL);
		368	if (ret)
228	goto unlock;	369	goto unlock;
		370	if (!pte)
		371	goto map_shared;
229		372
230	/*	373	/*
231	* The pool has been provided with enough pages to cover all of memory	374	* Check attributes in the host stage-2 PTE. We need the page to be:
232	* with page granularity, but it is difficult to know how much of the	375	* - mapped RWX as we're sharing memory;
233	* MMIO range we will need to cover upfront, so we may need to 'recycle'	376	* - not borrowed, as that implies absence of ownership.
234	* the pages if we run out.	377	* Otherwise, we can't let it got through
235	*/	378	*/
236	ret = host_stage2_unmap_dev_all();	379	cur = kvm_pgtable_stage2_pte_prot(pte);
237	if (ret)	380	prot = pkvm_mkstate(0, PKVM_PAGE_SHARED_BORROWED);
		381	if (!check_prot(cur, PKVM_HOST_MEM_PROT, prot)) {
		382	ret = -EPERM;
238	goto unlock;	383	goto unlock;
		384	}
239		385
240	ret = __host_stage2_idmap(range.start, range.end, prot);	386	state = pkvm_getstate(cur);
		387	if (state == PKVM_PAGE_OWNED)
		388	goto map_shared;
241		389
242	unlock:	390	/*
243	hyp_spin_unlock(&host_kvm.lock);	391	* Tolerate double-sharing the same page, but this requires
		392	* cross-checking the hypervisor stage-1.
		393	*/
		394	if (state != PKVM_PAGE_SHARED_OWNED) {
		395	ret = -EPERM;
		396	goto unlock;
		397	}
244		398
245	return ret;	399	ret = kvm_pgtable_get_leaf(&pkvm_pgtable, (u64)virt, &pte, NULL);
246	}	400	if (ret)
		401	goto unlock;
247		402
248	int __pkvm_mark_hyp(phys_addr_t start, phys_addr_t end)	403	/*
249	{	404	* If the page has been shared with the hypervisor, it must be
250	int ret;	405	* already mapped as SHARED_BORROWED in its stage-1.
		406	*/
		407	cur = kvm_pgtable_hyp_pte_prot(pte);
		408	prot = pkvm_mkstate(PAGE_HYP, PKVM_PAGE_SHARED_BORROWED);
		409	if (!check_prot(cur, prot, ~prot))
		410	ret = -EPERM;
		411	goto unlock;
251		412
		413	map_shared:
252	/*	414	/*
253	* host_stage2_unmap_dev_all() currently relies on MMIO mappings being	415	* If the page is not yet shared, adjust mappings in both page-tables
254	* non-persistent, so don't allow changing page ownership in MMIO range.	416	* while both locks are held.
255	*/	417	*/
256	if (!range_is_memory(start, end))	418	prot = pkvm_mkstate(PAGE_HYP, PKVM_PAGE_SHARED_BORROWED);
257	return -EINVAL;	419	ret = pkvm_create_mappings_locked(virt, virt + PAGE_SIZE, prot);
		420	BUG_ON(ret);
258		421
259	hyp_spin_lock(&host_kvm.lock);	422	prot = pkvm_mkstate(PKVM_HOST_MEM_PROT, PKVM_PAGE_SHARED_OWNED);
260	ret = kvm_pgtable_stage2_set_owner(&host_kvm.pgt, start, end - start,	423	ret = host_stage2_idmap_locked(addr, PAGE_SIZE, prot);
261	&host_s2_pool, pkvm_hyp_id);	424	BUG_ON(ret);
		425
		426	unlock:
		427	hyp_spin_unlock(&pkvm_pgd_lock);
262	hyp_spin_unlock(&host_kvm.lock);	428	hyp_spin_unlock(&host_kvm.lock);
263		429
264	return ret != -EAGAIN ? ret : 0;	430	return ret;
265	}	431	}
266		432
267	void handle_host_mem_abort(struct kvm_cpu_context *host_ctxt)	433	void handle_host_mem_abort(struct kvm_cpu_context *host_ctxt)

arch/arm64/kvm/hyp/nvhe/mm.c+18−4

 struct memblock_region hyp_memory[HYP_MEMBLOCK_REGIONS];
 unsigned int hyp_memblock_nr;
-int __pkvm_create_mappings(unsigned long start, unsigned long size,
+static int __pkvm_create_mappings(unsigned long start, unsigned long size,
-			  unsigned long phys, enum kvm_pgtable_prot prot)
+				  unsigned long phys, enum kvm_pgtable_prot prot)
 {
 	int err;
 	return addr;
 }
-int pkvm_create_mappings(void *from, void *to, enum kvm_pgtable_prot prot)
+int pkvm_create_mappings_locked(void *from, void *to, enum kvm_pgtable_prot prot)
 {
 	unsigned long start = (unsigned long)from;
 	unsigned long end = (unsigned long)to;
 	unsigned long virt_addr;
 	phys_addr_t phys;
+	hyp_assert_lock_held(&pkvm_pgd_lock);
 	start = start & PAGE_MASK;
 	end = PAGE_ALIGN(end);
 		int err;
 		phys = hyp_virt_to_phys((void *)virt_addr);
-		err = __pkvm_create_mappings(virt_addr, PAGE_SIZE, phys, prot);
+		err = kvm_pgtable_hyp_map(&pkvm_pgtable, virt_addr, PAGE_SIZE,
+					  phys, prot);
 		if (err)
 			return err;
 	}
 	return 0;
 }
+int pkvm_create_mappings(void *from, void *to, enum kvm_pgtable_prot prot)
+{
+	int ret;
+	hyp_spin_lock(&pkvm_pgd_lock);
+	ret = pkvm_create_mappings_locked(from, to, prot);
+	hyp_spin_unlock(&pkvm_pgd_lock);
+	return ret;
+}
 int hyp_back_vmemmap(phys_addr_t phys, unsigned long size, phys_addr_t back)
 {
 	unsigned long start, end;

arch/arm64/kvm/hyp/nvhe/setup.c+74−8

@@ -58,6 +58,7 @@ static int recreate_hyp_mappings(phys_addr_t phys, unsigned long size, · 57 unmodified lines
58	{	58	{
59	void start, end, *virt = hyp_phys_to_virt(phys);	59	void start, end, *virt = hyp_phys_to_virt(phys);
60	unsigned long pgt_size = hyp_s1_pgtable_pages() << PAGE_SHIFT;	60	unsigned long pgt_size = hyp_s1_pgtable_pages() << PAGE_SHIFT;
		61	enum kvm_pgtable_prot prot;
61	int ret, i;	62	int ret, i;
62		63
63	/* Recreate the hyp page-table using the early page allocator */	64	/* Recreate the hyp page-table using the early page allocator */
@@ -83,10 +84,6 @@ static int recreate_hyp_mappings(phys_addr_t phys, unsigned long size, · 19 unmodified lines
83	if (ret)	84	if (ret)
84	return ret;	85	return ret;
85		86
86	ret = pkvm_create_mappings(__start_rodata, __end_rodata, PAGE_HYP_RO);
87	if (ret)
88	return ret;
89
90	ret = pkvm_create_mappings(__hyp_rodata_start, __hyp_rodata_end, PAGE_HYP_RO);	87	ret = pkvm_create_mappings(__hyp_rodata_start, __hyp_rodata_end, PAGE_HYP_RO);
91	if (ret)	88	if (ret)
92	return ret;	89	return ret;
@@ -95,10 +92,6 @@ static int recreate_hyp_mappings(phys_addr_t phys, unsigned long size, · 2 unmodified lines
95	if (ret)	92	if (ret)
96	return ret;	93	return ret;
97		94
98	ret = pkvm_create_mappings(__hyp_bss_end, __bss_stop, PAGE_HYP_RO);
99	if (ret)
100	return ret;
101
102	ret = pkvm_create_mappings(virt, virt + size, PAGE_HYP);	95	ret = pkvm_create_mappings(virt, virt + size, PAGE_HYP);
103	if (ret)	96	if (ret)
104	return ret;	97	return ret;
@@ -117,6 +110,24 @@ static int recreate_hyp_mappings(phys_addr_t phys, unsigned long size, · 12 unmodified lines
117	return ret;	110	return ret;
118	}	111	}
119		112
		113	/*
		114	* Map the host's .bss and .rodata sections RO in the hypervisor, but
		115	* transfer the ownership from the host to the hypervisor itself to
		116	* make sure it can't be donated or shared with another entity.
		117	*
		118	* The ownership transition requires matching changes in the host
		119	* stage-2. This will be done later (see finalize_host_mappings()) once
		120	* the hyp_vmemmap is addressable.
		121	*/
		122	prot = pkvm_mkstate(PAGE_HYP_RO, PKVM_PAGE_SHARED_OWNED);
		123	ret = pkvm_create_mappings(__start_rodata, __end_rodata, prot);
		124	if (ret)
		125	return ret;
		126
		127	ret = pkvm_create_mappings(__hyp_bss_end, __bss_stop, prot);
		128	if (ret)
		129	return ret;
		130
120	return 0;	131	return 0;
121	}	132	}
122		133
@@ -148,6 +159,57 @@ static void hpool_put_page(void *addr) · 25 unmodified lines
148	hyp_put_page(&hpool, addr);	159	hyp_put_page(&hpool, addr);
149	}	160	}
150		161
		162	static int finalize_host_mappings_walker(u64 addr, u64 end, u32 level,
		163	kvm_pte_t *ptep,
		164	enum kvm_pgtable_walk_flags flag,
		165	void * const arg)
		166	{
		167	enum kvm_pgtable_prot prot;
		168	enum pkvm_page_state state;
		169	kvm_pte_t pte = *ptep;
		170	phys_addr_t phys;
		171
		172	if (!kvm_pte_valid(pte))
		173	return 0;
		174
		175	if (level != (KVM_PGTABLE_MAX_LEVELS - 1))
		176	return -EINVAL;
		177
		178	phys = kvm_pte_to_phys(pte);
		179	if (!addr_is_memory(phys))
		180	return 0;
		181
		182	/*
		183	* Adjust the host stage-2 mappings to match the ownership attributes
		184	* configured in the hypervisor stage-1.
		185	*/
		186	state = pkvm_getstate(kvm_pgtable_hyp_pte_prot(pte));
		187	switch (state) {
		188	case PKVM_PAGE_OWNED:
		189	return host_stage2_set_owner_locked(phys, PAGE_SIZE, pkvm_hyp_id);
		190	case PKVM_PAGE_SHARED_OWNED:
		191	prot = pkvm_mkstate(PKVM_HOST_MEM_PROT, PKVM_PAGE_SHARED_BORROWED);
		192	break;
		193	case PKVM_PAGE_SHARED_BORROWED:
		194	prot = pkvm_mkstate(PKVM_HOST_MEM_PROT, PKVM_PAGE_SHARED_OWNED);
		195	break;
		196	default:
		197	return -EINVAL;
		198	}
		199
		200	return host_stage2_idmap_locked(phys, PAGE_SIZE, prot);
		201	}
		202
		203	static int finalize_host_mappings(void)
		204	{
		205	struct kvm_pgtable_walker walker = {
		206	.cb = finalize_host_mappings_walker,
		207	.flags = KVM_PGTABLE_WALK_LEAF,
		208	};
		209
		210	return kvm_pgtable_walk(&pkvm_pgtable, 0, BIT(pkvm_pgtable.ia_bits), &walker);
		211	}
		212
151	void __noreturn __pkvm_init_finalise(void)	213	void __noreturn __pkvm_init_finalise(void)
152	{	214	{
153	struct kvm_host_data *host_data = this_cpu_ptr(&kvm_host_data);	215	struct kvm_host_data *host_data = this_cpu_ptr(&kvm_host_data);
@@ -167,6 +229,10 @@ void __noreturn __pkvm_init_finalise(void) · 13 unmodified lines
167	if (ret)	229	if (ret)
168	goto out;	230	goto out;
169		231
		232	ret = finalize_host_mappings();
		233	if (ret)
		234	goto out;
		235
170	pkvm_pgtable_mm_ops = (struct kvm_pgtable_mm_ops) {	236	pkvm_pgtable_mm_ops = (struct kvm_pgtable_mm_ops) {
171	.zalloc_page = hyp_zalloc_hyp_page,	237	.zalloc_page = hyp_zalloc_hyp_page,
172	.phys_to_virt = hyp_phys_to_virt,	238	.phys_to_virt = hyp_phys_to_virt,

arch/arm64/kvm/hyp/nvhe/switch.c+6−11

 	___activate_traps(vcpu);
 	__activate_traps_common(vcpu);
-	val = CPTR_EL2_DEFAULT;
+	val = vcpu->arch.cptr_el2;
 	val |= CPTR_EL2_TTA | CPTR_EL2_TAM;
 	if (!update_fp_enabled(vcpu)) {
 		val |= CPTR_EL2_TFP | CPTR_EL2_TZ;
 static void __deactivate_traps(struct kvm_vcpu *vcpu)
 {
 	extern char __kvm_hyp_host_vector[];
-	u64 mdcr_el2, cptr;
+	u64 cptr;
 	___deactivate_traps(vcpu);
-	mdcr_el2 = read_sysreg(mdcr_el2);
 	if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
 		u64 val;
 		isb();
 	}
-	__deactivate_traps_common();
+	__deactivate_traps_common(vcpu);
-	mdcr_el2 &= MDCR_EL2_HPMN_MASK;
-	mdcr_el2 |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
-	mdcr_el2 |= MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT;
-	write_sysreg(mdcr_el2, mdcr_el2);
 	write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2);
 	cptr = CPTR_EL2_DEFAULT;
 {
 	struct kvm_cpu_context *host_ctxt;
 	struct kvm_cpu_context *guest_ctxt;
+	struct kvm_s2_mmu *mmu;
 	bool pmu_switch_needed;
 	u64 exit_code;
 	__sysreg32_restore_state(vcpu);
 	__sysreg_restore_state_nvhe(guest_ctxt);
-	__load_guest_stage2(kern_hyp_va(vcpu->arch.hw_mmu));
+	mmu = kern_hyp_va(vcpu->arch.hw_mmu);
+	__load_stage2(mmu, kern_hyp_va(mmu->arch));
 	__activate_traps(vcpu);
 	__hyp_vgic_restore_state(vcpu);

arch/arm64/kvm/hyp/nvhe/tlb.c+2−2

@@ -34,12 +34,12 @@ static void __tlb_switch_to_guest(struct kvm_s2_mmu *mmu, · 33 unmodified lines
34	}	34	}
35		35
36	/*	36	/*
37	* __load_guest_stage2() includes an ISB only when the AT	37	* __load_stage2() includes an ISB only when the AT
38	* workaround is applied. Take care of the opposite condition,	38	* workaround is applied. Take care of the opposite condition,
39	* ensuring that we always have an ISB, but not two ISBs back	39	* ensuring that we always have an ISB, but not two ISBs back
40	* to back.	40	* to back.
41	*/	41	*/
42	__load_guest_stage2(mmu);	42	__load_stage2(mmu, kern_hyp_va(mmu->arch));
43	asm(ALTERNATIVE("isb", "nop", ARM64_WORKAROUND_SPECULATIVE_AT));	43	asm(ALTERNATIVE("isb", "nop", ARM64_WORKAROUND_SPECULATIVE_AT));
44	}	44	}
45		45

arch/arm64/kvm/hyp/pgtable.c+124−123

@@ -11,16 +11,12 @@ · 10 unmodified lines
11	#include <asm/kvm_pgtable.h>	11	#include <asm/kvm_pgtable.h>
12	#include <asm/stage2_pgtable.h>	12	#include <asm/stage2_pgtable.h>
13		13
14	#define KVM_PTE_VALID BIT(0)
15		14
16	#define KVM_PTE_TYPE BIT(1)	15	#define KVM_PTE_TYPE BIT(1)
17	#define KVM_PTE_TYPE_BLOCK 0	16	#define KVM_PTE_TYPE_BLOCK 0
18	#define KVM_PTE_TYPE_PAGE 1	17	#define KVM_PTE_TYPE_PAGE 1
19	#define KVM_PTE_TYPE_TABLE 1	18	#define KVM_PTE_TYPE_TABLE 1
20		19
21	#define KVM_PTE_ADDR_MASK GENMASK(47, PAGE_SHIFT)
22	#define KVM_PTE_ADDR_51_48 GENMASK(15, 12)
23
24	#define KVM_PTE_LEAF_ATTR_LO GENMASK(11, 2)	20	#define KVM_PTE_LEAF_ATTR_LO GENMASK(11, 2)
25		21
26	#define KVM_PTE_LEAF_ATTR_LO_S1_ATTRIDX GENMASK(4, 2)	22	#define KVM_PTE_LEAF_ATTR_LO_S1_ATTRIDX GENMASK(4, 2)
@@ -40,6 +36,8 @@ · 13 unmodified lines
40		36
41	#define KVM_PTE_LEAF_ATTR_HI GENMASK(63, 51)	37	#define KVM_PTE_LEAF_ATTR_HI GENMASK(63, 51)
42		38
		39	#define KVM_PTE_LEAF_ATTR_HI_SW GENMASK(58, 55)
		40
43	#define KVM_PTE_LEAF_ATTR_HI_S1_XN BIT(54)	41	#define KVM_PTE_LEAF_ATTR_HI_S1_XN BIT(54)
44		42
45	#define KVM_PTE_LEAF_ATTR_HI_S2_XN BIT(54)	43	#define KVM_PTE_LEAF_ATTR_HI_S2_XN BIT(54)
@@ -48,9 +46,7 @@ · 2 unmodified lines
48	KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W \| \	46	KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W \| \
49	KVM_PTE_LEAF_ATTR_HI_S2_XN)	47	KVM_PTE_LEAF_ATTR_HI_S2_XN)
50		48
51	#define KVM_PTE_LEAF_ATTR_S2_IGNORED GENMASK(58, 55)	49	#define KVM_INVALID_PTE_OWNER_MASK GENMASK(9, 2)
52
53	#define KVM_INVALID_PTE_OWNER_MASK GENMASK(63, 56)
54	#define KVM_MAX_OWNER_ID 1	50	#define KVM_MAX_OWNER_ID 1
55		51
56	struct kvm_pgtable_walk_data {	52	struct kvm_pgtable_walk_data {
@@ -61,17 +57,6 @@ struct kvm_pgtable_walk_data { · 4 unmodified lines
61	u64 end;	57	u64 end;
62	};	58	};
63		59
64	static u64 kvm_granule_shift(u32 level)
65	{
66	/* Assumes KVM_PGTABLE_MAX_LEVELS is 4 */
67	return ARM64_HW_PGTABLE_LEVEL_SHIFT(level);
68	}
69
70	static u64 kvm_granule_size(u32 level)
71	{
72	return BIT(kvm_granule_shift(level));
73	}
74
75	#define KVM_PHYS_INVALID (-1ULL)	60	#define KVM_PHYS_INVALID (-1ULL)
76		61
77	static bool kvm_phys_is_valid(u64 phys)	62	static bool kvm_phys_is_valid(u64 phys)
@@ -79,15 +64,6 @@ static bool kvm_phys_is_valid(u64 phys) · 1 unmodified line
79	return phys < BIT(id_aa64mmfr0_parange_to_phys_shift(ID_AA64MMFR0_PARANGE_MAX));	64	return phys < BIT(id_aa64mmfr0_parange_to_phys_shift(ID_AA64MMFR0_PARANGE_MAX));
80	}	65	}
81		66
82	static bool kvm_level_supports_block_mapping(u32 level)
83	{
84	/*
85	* Reject invalid block mappings and don't bother with 4TB mappings for
86	* 52-bit PAs.
87	*/
88	return !(level == 0 \|\| (PAGE_SIZE != SZ_4K && level == 1));
89	}
90
91	static bool kvm_block_mapping_supported(u64 addr, u64 end, u64 phys, u32 level)	67	static bool kvm_block_mapping_supported(u64 addr, u64 end, u64 phys, u32 level)
92	{	68	{
93	u64 granule = kvm_granule_size(level);	69	u64 granule = kvm_granule_size(level);
@@ -135,11 +111,6 @@ static u32 kvm_pgd_pages(u32 ia_bits, u32 start_level) · 41 unmodified lines
135	return __kvm_pgd_page_idx(&pgt, -1ULL) + 1;	111	return __kvm_pgd_page_idx(&pgt, -1ULL) + 1;
136	}	112	}
137		113
138	static bool kvm_pte_valid(kvm_pte_t pte)
139	{
140	return pte & KVM_PTE_VALID;
141	}
142
143	static bool kvm_pte_table(kvm_pte_t pte, u32 level)	114	static bool kvm_pte_table(kvm_pte_t pte, u32 level)
144	{	115	{
145	if (level == KVM_PGTABLE_MAX_LEVELS - 1)	116	if (level == KVM_PGTABLE_MAX_LEVELS - 1)
@@ -151,16 +122,6 @@ static bool kvm_pte_table(kvm_pte_t pte, u32 level) · 5 unmodified lines
151	return FIELD_GET(KVM_PTE_TYPE, pte) == KVM_PTE_TYPE_TABLE;	122	return FIELD_GET(KVM_PTE_TYPE, pte) == KVM_PTE_TYPE_TABLE;
152	}	123	}
153		124
154	static u64 kvm_pte_to_phys(kvm_pte_t pte)
155	{
156	u64 pa = pte & KVM_PTE_ADDR_MASK;
157
158	if (PAGE_SHIFT == 16)
159	pa \|= FIELD_GET(KVM_PTE_ADDR_51_48, pte) << 48;
160
161	return pa;
162	}
163
164	static kvm_pte_t kvm_phys_to_pte(u64 pa)	125	static kvm_pte_t kvm_phys_to_pte(u64 pa)
165	{	126	{
166	kvm_pte_t pte = pa & KVM_PTE_ADDR_MASK;	127	kvm_pte_t pte = pa & KVM_PTE_ADDR_MASK;
@@ -326,6 +287,45 @@ int kvm_pgtable_walk(struct kvm_pgtable *pgt, u64 addr, u64 size, · 159 unmodified lines
326	return _kvm_pgtable_walk(&walk_data);	287	return _kvm_pgtable_walk(&walk_data);
327	}	288	}
328		289
		290	struct leaf_walk_data {
		291	kvm_pte_t pte;
		292	u32 level;
		293	};
		294
		295	static int leaf_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep,
		296	enum kvm_pgtable_walk_flags flag, void * const arg)
		297	{
		298	struct leaf_walk_data *data = arg;
		299
		300	data->pte = *ptep;
		301	data->level = level;
		302
		303	return 0;
		304	}
		305
		306	int kvm_pgtable_get_leaf(struct kvm_pgtable *pgt, u64 addr,
		307	kvm_pte_t ptep, u32 level)
		308	{
		309	struct leaf_walk_data data;
		310	struct kvm_pgtable_walker walker = {
		311	.cb = leaf_walker,
		312	.flags = KVM_PGTABLE_WALK_LEAF,
		313	.arg = &data,
		314	};
		315	int ret;
		316
		317	ret = kvm_pgtable_walk(pgt, ALIGN_DOWN(addr, PAGE_SIZE),
		318	PAGE_SIZE, &walker);
		319	if (!ret) {
		320	if (ptep)
		321	*ptep = data.pte;
		322	if (level)
		323	*level = data.level;
		324	}
		325
		326	return ret;
		327	}
		328
329	struct hyp_map_data {	329	struct hyp_map_data {
330	u64 phys;	330	u64 phys;
331	kvm_pte_t attr;	331	kvm_pte_t attr;
@@ -357,11 +357,47 @@ static int hyp_set_prot_attr(enum kvm_pgtable_prot prot, kvm_pte_t *ptep) · 25 unmodified lines
357	attr \|= FIELD_PREP(KVM_PTE_LEAF_ATTR_LO_S1_AP, ap);	357	attr \|= FIELD_PREP(KVM_PTE_LEAF_ATTR_LO_S1_AP, ap);
358	attr \|= FIELD_PREP(KVM_PTE_LEAF_ATTR_LO_S1_SH, sh);	358	attr \|= FIELD_PREP(KVM_PTE_LEAF_ATTR_LO_S1_SH, sh);
359	attr \|= KVM_PTE_LEAF_ATTR_LO_S1_AF;	359	attr \|= KVM_PTE_LEAF_ATTR_LO_S1_AF;
		360	attr \|= prot & KVM_PTE_LEAF_ATTR_HI_SW;
360	*ptep = attr;	361	*ptep = attr;
361		362
362	return 0;	363	return 0;
363	}	364	}
364		365
		366	enum kvm_pgtable_prot kvm_pgtable_hyp_pte_prot(kvm_pte_t pte)
		367	{
		368	enum kvm_pgtable_prot prot = pte & KVM_PTE_LEAF_ATTR_HI_SW;
		369	u32 ap;
		370
		371	if (!kvm_pte_valid(pte))
		372	return prot;
		373
		374	if (!(pte & KVM_PTE_LEAF_ATTR_HI_S1_XN))
		375	prot \|= KVM_PGTABLE_PROT_X;
		376
		377	ap = FIELD_GET(KVM_PTE_LEAF_ATTR_LO_S1_AP, pte);
		378	if (ap == KVM_PTE_LEAF_ATTR_LO_S1_AP_RO)
		379	prot \|= KVM_PGTABLE_PROT_R;
		380	else if (ap == KVM_PTE_LEAF_ATTR_LO_S1_AP_RW)
		381	prot \|= KVM_PGTABLE_PROT_RW;
		382
		383	return prot;
		384	}
		385
		386	static bool hyp_pte_needs_update(kvm_pte_t old, kvm_pte_t new)
		387	{
		388	/*
		389	* Tolerate KVM recreating the exact same mapping, or changing software
		390	* bits if the existing mapping was valid.
		391	*/
		392	if (old == new)
		393	return false;
		394
		395	if (!kvm_pte_valid(old))
		396	return true;
		397
		398	return !WARN_ON((old ^ new) & ~KVM_PTE_LEAF_ATTR_HI_SW);
		399	}
		400
365	static bool hyp_map_walker_try_leaf(u64 addr, u64 end, u32 level,	401	static bool hyp_map_walker_try_leaf(u64 addr, u64 end, u32 level,
366	kvm_pte_t ptep, struct hyp_map_data data)	402	kvm_pte_t ptep, struct hyp_map_data data)
367	{	403	{
@@ -371,9 +407,8 @@ static bool hyp_map_walker_try_leaf(u64 addr, u64 end, u32 level, · 3 unmodified lines
371	if (!kvm_block_mapping_supported(addr, end, phys, level))	407	if (!kvm_block_mapping_supported(addr, end, phys, level))
372	return false;	408	return false;
373		409
374	/* Tolerate KVM recreating the exact same mapping */
375	new = kvm_init_valid_leaf_pte(phys, data->attr, level);	410	new = kvm_init_valid_leaf_pte(phys, data->attr, level);
376	if (old != new && !WARN_ON(kvm_pte_valid(old)))	411	if (hyp_pte_needs_update(old, new))
377	smp_store_release(ptep, new);	412	smp_store_release(ptep, new);
378		413
379	data->phys += granule;	414	data->phys += granule;
@@ -438,6 +473,8 @@ int kvm_pgtable_hyp_init(struct kvm_pgtable *pgt, u32 va_bits, · 58 unmodified lines
438	pgt->start_level = KVM_PGTABLE_MAX_LEVELS - levels;	473	pgt->start_level = KVM_PGTABLE_MAX_LEVELS - levels;
439	pgt->mm_ops = mm_ops;	474	pgt->mm_ops = mm_ops;
440	pgt->mmu = NULL;	475	pgt->mmu = NULL;
		476	pgt->force_pte_cb = NULL;
		477
441	return 0;	478	return 0;
442	}	479	}
443		480
@@ -475,6 +512,9 @@ struct stage2_map_data { · 31 unmodified lines
475	void *memcache;	512	void *memcache;
476		513
477	struct kvm_pgtable_mm_ops *mm_ops;	514	struct kvm_pgtable_mm_ops *mm_ops;
		515
		516	/* Force mappings to page granularity */
		517	bool force_pte;
478	};	518	};
479		519
480	u64 kvm_get_vtcr(u64 mmfr0, u64 mmfr1, u32 phys_shift)	520	u64 kvm_get_vtcr(u64 mmfr0, u64 mmfr1, u32 phys_shift)
@@ -539,11 +579,29 @@ static int stage2_set_prot_attr(struct kvm_pgtable *pgt, enum kvm_pgtable_prot p · 58 unmodified lines
539		579
540	attr \|= FIELD_PREP(KVM_PTE_LEAF_ATTR_LO_S2_SH, sh);	580	attr \|= FIELD_PREP(KVM_PTE_LEAF_ATTR_LO_S2_SH, sh);
541	attr \|= KVM_PTE_LEAF_ATTR_LO_S2_AF;	581	attr \|= KVM_PTE_LEAF_ATTR_LO_S2_AF;
		582	attr \|= prot & KVM_PTE_LEAF_ATTR_HI_SW;
542	*ptep = attr;	583	*ptep = attr;
543		584
544	return 0;	585	return 0;
545	}	586	}
546		587
		588	enum kvm_pgtable_prot kvm_pgtable_stage2_pte_prot(kvm_pte_t pte)
		589	{
		590	enum kvm_pgtable_prot prot = pte & KVM_PTE_LEAF_ATTR_HI_SW;
		591
		592	if (!kvm_pte_valid(pte))
		593	return prot;
		594
		595	if (pte & KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R)
		596	prot \|= KVM_PGTABLE_PROT_R;
		597	if (pte & KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W)
		598	prot \|= KVM_PGTABLE_PROT_W;
		599	if (!(pte & KVM_PTE_LEAF_ATTR_HI_S2_XN))
		600	prot \|= KVM_PGTABLE_PROT_X;
		601
		602	return prot;
		603	}
		604
547	static bool stage2_pte_needs_update(kvm_pte_t old, kvm_pte_t new)	605	static bool stage2_pte_needs_update(kvm_pte_t old, kvm_pte_t new)
548	{	606	{
549	if (!kvm_pte_valid(old) \|\| !kvm_pte_valid(new))	607	if (!kvm_pte_valid(old) \|\| !kvm_pte_valid(new))
@@ -588,6 +646,15 @@ static bool stage2_pte_executable(kvm_pte_t pte) · 38 unmodified lines
588	return !(pte & KVM_PTE_LEAF_ATTR_HI_S2_XN);	646	return !(pte & KVM_PTE_LEAF_ATTR_HI_S2_XN);
589	}	647	}
590		648
		649	static bool stage2_leaf_mapping_allowed(u64 addr, u64 end, u32 level,
		650	struct stage2_map_data *data)
		651	{
		652	if (data->force_pte && (level < (KVM_PGTABLE_MAX_LEVELS - 1)))
		653	return false;
		654
		655	return kvm_block_mapping_supported(addr, end, data->phys, level);
		656	}
		657
591	static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level,	658	static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level,
592	kvm_pte_t *ptep,	659	kvm_pte_t *ptep,
593	struct stage2_map_data *data)	660	struct stage2_map_data *data)
@@ -597,7 +664,7 @@ static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level, · 3 unmodified lines
597	struct kvm_pgtable *pgt = data->mmu->pgt;	664	struct kvm_pgtable *pgt = data->mmu->pgt;
598	struct kvm_pgtable_mm_ops *mm_ops = data->mm_ops;	665	struct kvm_pgtable_mm_ops *mm_ops = data->mm_ops;
599		666
600	if (!kvm_block_mapping_supported(addr, end, phys, level))	667	if (!stage2_leaf_mapping_allowed(addr, end, level, data))
601	return -E2BIG;	668	return -E2BIG;
602		669
603	if (kvm_phys_is_valid(phys))	670	if (kvm_phys_is_valid(phys))
@@ -641,7 +708,7 @@ static int stage2_map_walk_table_pre(u64 addr, u64 end, u32 level, · 37 unmodified lines
641	if (data->anchor)	708	if (data->anchor)
642	return 0;	709	return 0;
643		710
644	if (!kvm_block_mapping_supported(addr, end, data->phys, level))	711	if (!stage2_leaf_mapping_allowed(addr, end, level, data))
645	return 0;	712	return 0;
646		713
647	data->childp = kvm_pte_follow(*ptep, data->mm_ops);	714	data->childp = kvm_pte_follow(*ptep, data->mm_ops);
@@ -771,6 +838,7 @@ int kvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size, · 123 unmodified lines
771	.mmu = pgt->mmu,	838	.mmu = pgt->mmu,
772	.memcache = mc,	839	.memcache = mc,
773	.mm_ops = pgt->mm_ops,	840	.mm_ops = pgt->mm_ops,
		841	.force_pte = pgt->force_pte_cb && pgt->force_pte_cb(addr, addr + size, prot),
774	};	842	};
775	struct kvm_pgtable_walker walker = {	843	struct kvm_pgtable_walker walker = {
776	.cb = stage2_map_walker,	844	.cb = stage2_map_walker,
@@ -802,6 +870,7 @@ int kvm_pgtable_stage2_set_owner(struct kvm_pgtable *pgt, u64 addr, u64 size, · 25 unmodified lines
802	.memcache = mc,	870	.memcache = mc,
803	.mm_ops = pgt->mm_ops,	871	.mm_ops = pgt->mm_ops,
804	.owner_id = owner_id,	872	.owner_id = owner_id,
		873	.force_pte = true,
805	};	874	};
806	struct kvm_pgtable_walker walker = {	875	struct kvm_pgtable_walker walker = {
807	.cb = stage2_map_walker,	876	.cb = stage2_map_walker,
@@ -995,6 +1064,9 @@ int kvm_pgtable_stage2_relax_perms(struct kvm_pgtable *pgt, u64 addr, · 187 unmodified lines
995	u32 level;	1064	u32 level;
996	kvm_pte_t set = 0, clr = 0;	1065	kvm_pte_t set = 0, clr = 0;
997		1066
		1067	if (prot & KVM_PTE_LEAF_ATTR_HI_SW)
		1068	return -EINVAL;
		1069
998	if (prot & KVM_PGTABLE_PROT_R)	1070	if (prot & KVM_PGTABLE_PROT_R)
999	set \|= KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R;	1071	set \|= KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R;
1000		1072
@@ -1043,9 +1115,11 @@ int kvm_pgtable_stage2_flush(struct kvm_pgtable *pgt, u64 addr, u64 size) · 42 unmodified lines
1043	return kvm_pgtable_walk(pgt, addr, size, &walker);	1115	return kvm_pgtable_walk(pgt, addr, size, &walker);
1044	}	1116	}
1045		1117
1046	int kvm_pgtable_stage2_init_flags(struct kvm_pgtable pgt, struct kvm_arch arch,	1118
1047	struct kvm_pgtable_mm_ops *mm_ops,	1119	int __kvm_pgtable_stage2_init(struct kvm_pgtable pgt, struct kvm_arch arch,
1048	enum kvm_pgtable_stage2_flags flags)	1120	struct kvm_pgtable_mm_ops *mm_ops,
		1121	enum kvm_pgtable_stage2_flags flags,
		1122	kvm_pgtable_force_pte_cb_t force_pte_cb)
1049	{	1123	{
1050	size_t pgd_sz;	1124	size_t pgd_sz;
1051	u64 vtcr = arch->vtcr;	1125	u64 vtcr = arch->vtcr;
@@ -1063,6 +1137,7 @@ int kvm_pgtable_stage2_init_flags(struct kvm_pgtable pgt, struct kvm_arch arch · 11 unmodified lines
1063	pgt->mm_ops = mm_ops;	1137	pgt->mm_ops = mm_ops;
1064	pgt->mmu = &arch->mmu;	1138	pgt->mmu = &arch->mmu;
1065	pgt->flags = flags;	1139	pgt->flags = flags;
		1140	pgt->force_pte_cb = force_pte_cb;
1066		1141
1067	/* Ensure zeroed PGD pages are visible to the hardware walker */	1142	/* Ensure zeroed PGD pages are visible to the hardware walker */
1068	dsb(ishst);	1143	dsb(ishst);
@@ -1102,77 +1177,3 @@ void kvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt) · 33 unmodified lines
1102	pgt->mm_ops->free_pages_exact(pgt->pgd, pgd_sz);	1177	pgt->mm_ops->free_pages_exact(pgt->pgd, pgd_sz);
1103	pgt->pgd = NULL;	1178	pgt->pgd = NULL;
1104	}	1179	}
1105
1106	#define KVM_PTE_LEAF_S2_COMPAT_MASK (KVM_PTE_LEAF_ATTR_S2_PERMS \| \
1107	KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR \| \
1108	KVM_PTE_LEAF_ATTR_S2_IGNORED)
1109
1110	static int stage2_check_permission_walker(u64 addr, u64 end, u32 level,
1111	kvm_pte_t *ptep,
1112	enum kvm_pgtable_walk_flags flag,
1113	void * const arg)
1114	{
1115	kvm_pte_t old_attr, pte = ptep, new_attr = arg;
1116
1117	/*
1118	* Compatible mappings are either invalid and owned by the page-table
1119	* owner (whose id is 0), or valid with matching permission attributes.
1120	*/
1121	if (kvm_pte_valid(pte)) {
1122	old_attr = pte & KVM_PTE_LEAF_S2_COMPAT_MASK;
1123	if (old_attr != *new_attr)
1124	return -EEXIST;
1125	} else if (pte) {
1126	return -EEXIST;
1127	}
1128
1129	return 0;
1130	}
1131
1132	int kvm_pgtable_stage2_find_range(struct kvm_pgtable *pgt, u64 addr,
1133	enum kvm_pgtable_prot prot,
1134	struct kvm_mem_range *range)
1135	{
1136	kvm_pte_t attr;
1137	struct kvm_pgtable_walker check_perm_walker = {
1138	.cb = stage2_check_permission_walker,
1139	.flags = KVM_PGTABLE_WALK_LEAF,
1140	.arg = &attr,
1141	};
1142	u64 granule, start, end;
1143	u32 level;
1144	int ret;
1145
1146	ret = stage2_set_prot_attr(pgt, prot, &attr);
1147	if (ret)
1148	return ret;
1149	attr &= KVM_PTE_LEAF_S2_COMPAT_MASK;
1150
1151	for (level = pgt->start_level; level < KVM_PGTABLE_MAX_LEVELS; level++) {
1152	granule = kvm_granule_size(level);
1153	start = ALIGN_DOWN(addr, granule);
1154	end = start + granule;
1155
1156	if (!kvm_level_supports_block_mapping(level))
1157	continue;
1158
1159	if (start < range->start \|\| range->end < end)
1160	continue;
1161
1162	/*
1163	* Check the presence of existing mappings with incompatible
1164	* permissions within the current block range, and try one level
1165	* deeper if one is found.
1166	*/
1167	ret = kvm_pgtable_walk(pgt, start, granule, &check_perm_walker);
1168	if (ret != -EEXIST)
1169	break;
1170	}
1171
1172	if (!ret) {
1173	range->start = start;
1174	range->end = end;
1175	}
1176
1177	return ret;
1178	}

arch/arm64/kvm/hyp/vhe/debug-sr.c+1−1

@@ -20,7 +20,7 @@ void __debug_switch_to_host(struct kvm_vcpu *vcpu) · 19 unmodified lines
20	__debug_switch_to_host_common(vcpu);	20	__debug_switch_to_host_common(vcpu);
21	}	21	}
22		22
23	u32 __kvm_get_mdcr_el2(void)	23	u64 __kvm_get_mdcr_el2(void)
24	{	24	{
25	return read_sysreg(mdcr_el2);	25	return read_sysreg(mdcr_el2);
26	}	26	}

arch/arm64/kvm/hyp/vhe/switch.c+5−13

 	__activate_traps_common(vcpu);
 }
-void deactivate_traps_vhe_put(void)
+void deactivate_traps_vhe_put(struct kvm_vcpu *vcpu)
 {
-	u64 mdcr_el2 = read_sysreg(mdcr_el2);
+	__deactivate_traps_common(vcpu);
-	mdcr_el2 &= MDCR_EL2_HPMN_MASK |
-		    MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT |
-		    MDCR_EL2_TPMS;
-	write_sysreg(mdcr_el2, mdcr_el2);
-	__deactivate_traps_common();
 }
 /* Switch to the guest for VHE systems running in EL2 */
 	 *
 	 * We have already configured the guest's stage 1 translation in
 	 * kvm_vcpu_load_sysregs_vhe above.  We must now call
-	 * __load_guest_stage2 before __activate_traps, because
+	 * __load_stage2 before __activate_traps, because
-	 * __load_guest_stage2 configures stage 2 translation, and
+	 * __load_stage2 configures stage 2 translation, and
 	 * __activate_traps clear HCR_EL2.TGE (among other things).
 	 */
-	__load_guest_stage2(vcpu->arch.hw_mmu);
+	__load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch);
 	__activate_traps(vcpu);
 	__kvm_adjust_pc(vcpu);

arch/arm64/kvm/hyp/vhe/sysreg-sr.c+1−1

@@ -101,7 +101,7 @@ void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu) · 100 unmodified lines
101	struct kvm_cpu_context *host_ctxt;	101	struct kvm_cpu_context *host_ctxt;
102		102
103	host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;	103	host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
104	deactivate_traps_vhe_put();	104	deactivate_traps_vhe_put(vcpu);
105		105
106	__sysreg_save_el1_state(guest_ctxt);	106	__sysreg_save_el1_state(guest_ctxt);
107	__sysreg_save_user_state(guest_ctxt);	107	__sysreg_save_user_state(guest_ctxt);

arch/arm64/kvm/hyp/vhe/tlb.c+2−2

@@ -50,10 +50,10 @@ static void __tlb_switch_to_guest(struct kvm_s2_mmu *mmu, · 49 unmodified lines
50	*	50	*
51	* ARM erratum 1165522 requires some special handling (again),	51	* ARM erratum 1165522 requires some special handling (again),
52	* as we need to make sure both stages of translation are in	52	* as we need to make sure both stages of translation are in
53	* place before clearing TGE. __load_guest_stage2() already	53	* place before clearing TGE. __load_stage2() already
54	* has an ISB in order to deal with this.	54	* has an ISB in order to deal with this.
55	*/	55	*/
56	__load_guest_stage2(mmu);	56	__load_stage2(mmu, mmu->arch);
57	val = read_sysreg(hcr_el2);	57	val = read_sysreg(hcr_el2);
58	val &= ~HCR_TGE;	58	val &= ~HCR_TGE;
59	write_sysreg(val, hcr_el2);	59	write_sysreg(val, hcr_el2);

arch/arm64/kvm/mmu.c+63−12

 {
 	int err;
-	if (!kvm_host_owns_hyp_mappings()) {
+	if (WARN_ON(!kvm_host_owns_hyp_mappings()))
-		return kvm_call_hyp_nvhe(__pkvm_create_mappings,
+		return -EINVAL;
-					 start, size, phys, prot);
-	}
 	mutex_lock(&kvm_hyp_pgd_mutex);
 	err = kvm_pgtable_hyp_map(hyp_pgtable, start, size, phys, prot);
 	}
 }
+static int pkvm_share_hyp(phys_addr_t start, phys_addr_t end)
+{
+	phys_addr_t addr;
+	int ret;
+	for (addr = ALIGN_DOWN(start, PAGE_SIZE); addr < end; addr += PAGE_SIZE) {
+		ret = kvm_call_hyp_nvhe(__pkvm_host_share_hyp,
+					__phys_to_pfn(addr));
+		if (ret)
+			return ret;
+	}
+	return 0;
+}
 /**
  * create_hyp_mappings - duplicate a kernel virtual address range in Hyp mode
  * @from:	The virtual kernel start address of the range
 	if (is_kernel_in_hyp_mode())
 		return 0;
+	if (!kvm_host_owns_hyp_mappings()) {
+		if (WARN_ON(prot != PAGE_HYP))
+			return -EPERM;
+		return pkvm_share_hyp(kvm_kaddr_to_phys(from),
+				      kvm_kaddr_to_phys(to));
+	}
 	start = start & PAGE_MASK;
 	end = PAGE_ALIGN(end);
 	return 0;
 }
+static struct kvm_pgtable_mm_ops kvm_user_mm_ops = {
+	/* We shouldn't need any other callback to walk the PT */
+	.phys_to_virt		= kvm_host_va,
+};
+static int get_user_mapping_size(struct kvm *kvm, u64 addr)
+{
+	struct kvm_pgtable pgt = {
+		.pgd		= (kvm_pte_t *)kvm->mm->pgd,
+		.ia_bits	= VA_BITS,
+		.start_level	= (KVM_PGTABLE_MAX_LEVELS -
+				   CONFIG_PGTABLE_LEVELS),
+		.mm_ops		= &kvm_user_mm_ops,
+	};
+	kvm_pte_t pte = 0;	/* Keep GCC quiet... */
+	u32 level = ~0;
+	int ret;
+	ret = kvm_pgtable_get_leaf(&pgt, addr, &pte, &level);
+	VM_BUG_ON(ret);
+	VM_BUG_ON(level >= KVM_PGTABLE_MAX_LEVELS);
+	VM_BUG_ON(!(pte & PTE_VALID));
+	return BIT(ARM64_HW_PGTABLE_LEVEL_SHIFT(level));
+}
 static struct kvm_pgtable_mm_ops kvm_s2_mm_ops = {
 	.zalloc_page		= stage2_memcache_zalloc_page,
 	.zalloc_pages_exact	= kvm_host_zalloc_pages_exact,
 	mmu->arch = &kvm->arch;
 	mmu->pgt = pgt;
 	mmu->pgd_phys = __pa(pgt->pgd);
-	mmu->vmid.vmid_gen = 0;
+	WRITE_ONCE(mmu->vmid.vmid_gen, 0);
 	return 0;
 out_destroy_pgtable:
  * Returns the size of the mapping.
  */
 static unsigned long
-transparent_hugepage_adjust(struct kvm_memory_slot *memslot,
+transparent_hugepage_adjust(struct kvm *kvm, struct kvm_memory_slot *memslot,
 			    unsigned long hva, kvm_pfn_t *pfnp,
 			    phys_addr_t *ipap)
 {
 	 * sure that the HVA and IPA are sufficiently aligned and that the
 	 * block map is contained within the memslot.
 	 */
-	if (kvm_is_transparent_hugepage(pfn) &&
+	if (fault_supports_stage2_huge_mapping(memslot, hva, PMD_SIZE) &&
-	    fault_supports_stage2_huge_mapping(memslot, hva, PMD_SIZE)) {
+	    get_user_mapping_size(kvm, hva) >= PMD_SIZE) {
 		/*
 		 * The address we faulted on is backed by a transparent huge
 		 * page.  However, because we map the compound huge page and
 		*ipap &= PMD_MASK;
 		kvm_release_pfn_clean(pfn);
 		pfn &= ~(PTRS_PER_PMD - 1);
-		kvm_get_pfn(pfn);
+		get_page(pfn_to_page(pfn));
 		*pfnp = pfn;
 		return PMD_SIZE;
 	 * If we are not forced to use page mapping, check if we are
 	 * backed by a THP and thus use block mapping if possible.
 	 */
-	if (vma_pagesize == PAGE_SIZE && !(force_pte || device))
+	if (vma_pagesize == PAGE_SIZE && !(force_pte || device)) {
-		vma_pagesize = transparent_hugepage_adjust(memslot, hva,
+		if (fault_status == FSC_PERM && fault_granule > PAGE_SIZE)
-							   &pfn, &fault_ipa);
+			vma_pagesize = fault_granule;
+		else
+			vma_pagesize = transparent_hugepage_adjust(kvm, memslot,
+								   hva, &pfn,
+								   &fault_ipa);
+	}
 	if (fault_status != FSC_PERM && !device && kvm_has_mte(kvm)) {
 		/* Check the VMM hasn't introduced a new VM_SHARED VMA */

arch/arm64/kvm/perf.c+1−1

@@ -50,7 +50,7 @@ static struct perf_guest_info_callbacks kvm_guest_cbs = { · 49 unmodified lines
50		50
51	int kvm_perf_init(void)	51	int kvm_perf_init(void)
52	{	52	{
53	if (kvm_pmu_probe_pmuver() != 0xf && !is_protected_kvm_enabled())	53	if (kvm_pmu_probe_pmuver() != ID_AA64DFR0_PMUVER_IMP_DEF && !is_protected_kvm_enabled())
54	static_branch_enable(&kvm_arm_pmu_available);	54	static_branch_enable(&kvm_arm_pmu_available);
55		55
56	return perf_register_guest_info_callbacks(&kvm_guest_cbs);	56	return perf_register_guest_info_callbacks(&kvm_guest_cbs);

arch/arm64/kvm/pmu-emul.c+7−7

 		reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
 		reg &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
 		reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
-		reg &= kvm_pmu_valid_counter_mask(vcpu);
 	}
 	return reg;
  */
 void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
 {
-	unsigned long mask = kvm_pmu_valid_counter_mask(vcpu);
 	int i;
 	if (val & ARMV8_PMU_PMCR_E) {
 		kvm_pmu_enable_counter_mask(vcpu,
-		       __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask);
+		       __vcpu_sys_reg(vcpu, PMCNTENSET_EL0));
 	} else {
-		kvm_pmu_disable_counter_mask(vcpu, mask);
+		kvm_pmu_disable_counter_mask(vcpu,
+		       __vcpu_sys_reg(vcpu, PMCNTENSET_EL0));
 	}
 	if (val & ARMV8_PMU_PMCR_C)
 		kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
 	if (val & ARMV8_PMU_PMCR_P) {
+		unsigned long mask = kvm_pmu_valid_counter_mask(vcpu);
 		mask &= ~BIT(ARMV8_PMU_CYCLE_IDX);
 		for_each_set_bit(i, &mask, 32)
 			kvm_pmu_set_counter_value(vcpu, i, 0);
 	struct perf_event_attr attr = { };
 	struct perf_event *event;
 	struct arm_pmu *pmu;
-	int pmuver = 0xf;
+	int pmuver = ID_AA64DFR0_PMUVER_IMP_DEF;
 	/*
 	 * Create a dummy event that only counts user cycles. As we'll never
 	if (IS_ERR(event)) {
 		pr_err_once("kvm: pmu event creation failed %ld\n",
 			    PTR_ERR(event));
-		return 0xf;
+		return ID_AA64DFR0_PMUVER_IMP_DEF;
 	}
 	if (event->pmu) {
 	if (!vcpu->kvm->arch.pmuver)
 		vcpu->kvm->arch.pmuver = kvm_pmu_probe_pmuver();
-	if (vcpu->kvm->arch.pmuver == 0xf)
+	if (vcpu->kvm->arch.pmuver == ID_AA64DFR0_PMUVER_IMP_DEF)
 		return -ENODEV;
 	switch (attr->attr) {

arch/arm64/kvm/psci.c+12−3

 	kvm_vcpu_kick(vcpu);
 }
+static inline bool kvm_psci_valid_affinity(struct kvm_vcpu *vcpu,
+					   unsigned long affinity)
+{
+	return !(affinity & ~MPIDR_HWID_BITMASK);
+}
 static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
 {
 	struct vcpu_reset_state *reset_state;
 	struct kvm_vcpu *vcpu = NULL;
 	unsigned long cpu_id;
-	cpu_id = smccc_get_arg1(source_vcpu) & MPIDR_HWID_BITMASK;
+	cpu_id = smccc_get_arg1(source_vcpu);
-	if (vcpu_mode_is_32bit(source_vcpu))
+	if (!kvm_psci_valid_affinity(source_vcpu, cpu_id))
-		cpu_id &= ~((u32) 0);
+		return PSCI_RET_INVALID_PARAMS;
 	vcpu = kvm_mpidr_to_vcpu(kvm, cpu_id);
 	target_affinity = smccc_get_arg1(vcpu);
 	lowest_affinity_level = smccc_get_arg2(vcpu);
+	if (!kvm_psci_valid_affinity(vcpu, target_affinity))
+		return PSCI_RET_INVALID_PARAMS;
 	/* Determine target affinity mask */
 	target_affinity_mask = psci_affinity_mask(lowest_affinity_level);
 	if (!target_affinity_mask)

arch/arm64/kvm/reset.c+21−22

  */
 int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
 {
+	struct vcpu_reset_state reset_state;
 	int ret;
 	bool loaded;
 	u32 pstate;
+	mutex_lock(&vcpu->kvm->lock);
+	reset_state = vcpu->arch.reset_state;
+	WRITE_ONCE(vcpu->arch.reset_state.reset, false);
+	mutex_unlock(&vcpu->kvm->lock);
 	/* Reset PMU outside of the non-preemptible section */
 	kvm_pmu_vcpu_reset(vcpu);
 	 * Additional reset state handling that PSCI may have imposed on us.
 	 * Must be done after all the sys_reg reset.
 	 */
-	if (vcpu->arch.reset_state.reset) {
+	if (reset_state.reset) {
-		unsigned long target_pc = vcpu->arch.reset_state.pc;
+		unsigned long target_pc = reset_state.pc;
 		/* Gracefully handle Thumb2 entry point */
 		if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
 		}
 		/* Propagate caller endianness */
-		if (vcpu->arch.reset_state.be)
+		if (reset_state.be)
 			kvm_vcpu_set_be(vcpu);
 		*vcpu_pc(vcpu) = target_pc;
-		vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0);
+		vcpu_set_reg(vcpu, 0, reset_state.r0);
-		vcpu->arch.reset_state.reset = false;
 	}
 	/* Reset timer */
 int kvm_set_ipa_limit(void)
 {
-	unsigned int parange, tgran_2;
+	unsigned int parange;
 	u64 mmfr0;
 	mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
 	parange = cpuid_feature_extract_unsigned_field(mmfr0,
 				ID_AA64MMFR0_PARANGE_SHIFT);
+	/*
+	 * IPA size beyond 48 bits could not be supported
+	 * on either 4K or 16K page size. Hence let's cap
+	 * it to 48 bits, in case it's reported as larger
+	 * on the system.
+	 */
+	if (PAGE_SIZE != SZ_64K)
+		parange = min(parange, (unsigned int)ID_AA64MMFR0_PARANGE_48);
 	/*
 	 * Check with ARMv8.5-GTG that our PAGE_SIZE is supported at
 	 * Stage-2. If not, things will stop very quickly.
 	 */
-	switch (PAGE_SIZE) {
+	switch (cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_TGRAN_2_SHIFT)) {
-	default:
-	case SZ_4K:
-		tgran_2 = ID_AA64MMFR0_TGRAN4_2_SHIFT;
-		break;
-	case SZ_16K:
-		tgran_2 = ID_AA64MMFR0_TGRAN16_2_SHIFT;
-		break;
-	case SZ_64K:
-		tgran_2 = ID_AA64MMFR0_TGRAN64_2_SHIFT;
-		break;
-	}
-	switch (cpuid_feature_extract_unsigned_field(mmfr0, tgran_2)) {
 	case ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE:
 		kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");
 		return -EINVAL;
 	phys_shift = KVM_VM_TYPE_ARM_IPA_SIZE(type);
 	if (phys_shift) {
 		if (phys_shift > kvm_ipa_limit ||
-		    phys_shift < 32)
+		    phys_shift < ARM64_MIN_PARANGE_BITS)
 			return -EINVAL;
 	} else {
 		phys_shift = KVM_PHYS_SHIFT;

arch/arm64/kvm/sys_regs.c+81−53

  * 64bit interface.
  */
-#define reg_to_encoding(x)						\
-	sys_reg((u32)(x)->Op0, (u32)(x)->Op1,				\
-		(u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
 static bool read_from_write_only(struct kvm_vcpu *vcpu,
 				 struct sys_reg_params *params,
 				 const struct sys_reg_desc *r)
 /*
  * We want to avoid world-switching all the DBG registers all the
  * time:
  *
  * - If we've touched any debug register, it is likely that we're
  *   going to touch more of them. It then makes sense to disable the
  *   traps and start doing the save/restore dance
  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
  *   then mandatory to save/restore the registers, as the guest
  *   depends on them.
  *
  * For this, we use a DIRTY bit, indicating the guest has modified the
  * debug registers, used as follow:
  *
 	return REG_HIDDEN;
 }
+static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+	u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
+	/* No PMU available, any PMU reg may UNDEF... */
+	if (!kvm_arm_support_pmu_v3())
+		return;
+	n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
+	n &= ARMV8_PMU_PMCR_N_MASK;
+	if (n)
+		mask |= GENMASK(n - 1, 0);
+	reset_unknown(vcpu, r);
+	__vcpu_sys_reg(vcpu, r->reg) &= mask;
+}
+static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+	reset_unknown(vcpu, r);
+	__vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
+}
+static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+	reset_unknown(vcpu, r);
+	__vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK;
+}
+static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+	reset_unknown(vcpu, r);
+	__vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
+}
 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 {
 	u64 pmcr, val;
 			kvm_pmu_disable_counter_mask(vcpu, val);
 		}
 	} else {
-		p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
+		p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
 	}
 	return true;
 			/* accessing PMINTENCLR_EL1 */
 			__vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
 	} else {
-		p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
+		p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
 	}
 	return true;
 			/* accessing PMOVSCLR_EL0 */
 			__vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
 	} else {
-		p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
+		p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
 	}
 	return true;
 	  trap_wcr, reset_wcr, 0, 0,  get_wcr, set_wcr }
 #define PMU_SYS_REG(r)						\
-	SYS_DESC(r), .reset = reset_unknown, .visibility = pmu_visibility
+	SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility
 /* Macro to expand the PMEVCNTRn_EL0 register */
 #define PMU_PMEVCNTR_EL0(n)						\
 	{ PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)),				\
+	  .reset = reset_pmevcntr,					\
 	  .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
 /* Macro to expand the PMEVTYPERn_EL0 register */
 #define PMU_PMEVTYPER_EL0(n)						\
 	{ PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)),				\
+	  .reset = reset_pmevtyper,					\
 	  .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 	return true;
 }
-#define FEATURE(x)	(GENMASK_ULL(x##_SHIFT + 3, x##_SHIFT))
 /* Read a sanitised cpufeature ID register by sys_reg_desc */
 static u64 read_id_reg(const struct kvm_vcpu *vcpu,
 		struct sys_reg_desc const *r, bool raz)
 	switch (id) {
 	case SYS_ID_AA64PFR0_EL1:
 		if (!vcpu_has_sve(vcpu))
-			val &= ~FEATURE(ID_AA64PFR0_SVE);
+			val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE);
-		val &= ~FEATURE(ID_AA64PFR0_AMU);
+		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_AMU);
-		val &= ~FEATURE(ID_AA64PFR0_CSV2);
+		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2);
-		val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
+		val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
-		val &= ~FEATURE(ID_AA64PFR0_CSV3);
+		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3);
-		val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
+		val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
 		break;
 	case SYS_ID_AA64PFR1_EL1:
-		val &= ~FEATURE(ID_AA64PFR1_MTE);
+		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);
 		if (kvm_has_mte(vcpu->kvm)) {
 			u64 pfr, mte;
 			pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
 			mte = cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR1_MTE_SHIFT);
-			val |= FIELD_PREP(FEATURE(ID_AA64PFR1_MTE), mte);
+			val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR1_MTE), mte);
 		}
 		break;
 	case SYS_ID_AA64ISAR1_EL1:
 		if (!vcpu_has_ptrauth(vcpu))
-			val &= ~(FEATURE(ID_AA64ISAR1_APA) |
+			val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) |
-				 FEATURE(ID_AA64ISAR1_API) |
+				 ARM64_FEATURE_MASK(ID_AA64ISAR1_API) |
-				 FEATURE(ID_AA64ISAR1_GPA) |
+				 ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) |
-				 FEATURE(ID_AA64ISAR1_GPI));
+				 ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI));
 		break;
 	case SYS_ID_AA64DFR0_EL1:
 		/* Limit debug to ARMv8.0 */
-		val &= ~FEATURE(ID_AA64DFR0_DEBUGVER);
+		val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER);
-		val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6);
+		val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6);
 		/* Limit guests to PMUv3 for ARMv8.4 */
 		val = cpuid_feature_cap_perfmon_field(val,
 						      ID_AA64DFR0_PMUVER_SHIFT,
 						      kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0);
 		/* Hide SPE from guests */
-		val &= ~FEATURE(ID_AA64DFR0_PMSVER);
+		val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER);
 		break;
 	case SYS_ID_DFR0_EL1:
 		/* Limit guests to PMUv3 for ARMv8.4 */
 	return __set_id_reg(vcpu, rd, uaddr, true);
 }
+static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
+		      const struct kvm_one_reg *reg, void __user *uaddr)
+{
+	int err;
+	u64 val;
+	/* Perform the access even if we are going to ignore the value */
+	err = reg_from_user(&val, uaddr, sys_reg_to_index(rd));
+	if (err)
+		return err;
+	return 0;
+}
 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 		       const struct sys_reg_desc *r)
 {
 	  .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
 	{ PMU_SYS_REG(SYS_PMOVSCLR_EL0),
 	  .access = access_pmovs, .reg = PMOVSSET_EL0 },
+	/*
+	 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
+	 * previously (and pointlessly) advertised in the past...
+	 */
 	{ PMU_SYS_REG(SYS_PMSWINC_EL0),
-	  .access = access_pmswinc, .reg = PMSWINC_EL0 },
+	  .get_user = get_raz_id_reg, .set_user = set_wi_reg,
+	  .access = access_pmswinc, .reset = NULL },
 	{ PMU_SYS_REG(SYS_PMSELR_EL0),
-	  .access = access_pmselr, .reg = PMSELR_EL0 },
+	  .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
 	{ PMU_SYS_REG(SYS_PMCEID0_EL0),
 	  .access = access_pmceid, .reset = NULL },
 	{ PMU_SYS_REG(SYS_PMCEID1_EL0),
 	  .access = access_pmceid, .reset = NULL },
 	{ PMU_SYS_REG(SYS_PMCCNTR_EL0),
-	  .access = access_pmu_evcntr, .reg = PMCCNTR_EL0 },
+	  .access = access_pmu_evcntr, .reset = reset_unknown, .reg = PMCCNTR_EL0 },
 	{ PMU_SYS_REG(SYS_PMXEVTYPER_EL0),
 	  .access = access_pmu_evtyper, .reset = NULL },
 	{ PMU_SYS_REG(SYS_PMXEVCNTR_EL0),
 	return 0;
 }
-static int match_sys_reg(const void *key, const void *elt)
-{
-	const unsigned long pval = (unsigned long)key;
-	const struct sys_reg_desc *r = elt;
-	return pval - reg_to_encoding(r);
-}
-static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
-					 const struct sys_reg_desc table[],
-					 unsigned int num)
-{
-	unsigned long pval = reg_to_encoding(params);
-	return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
-}
 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
 {
 	kvm_inject_undefined(vcpu);
 	trace_kvm_handle_sys_reg(esr);
-	params.Op0 = (esr >> 20) & 3;
+	params = esr_sys64_to_params(esr);
-	params.Op1 = (esr >> 14) & 0x7;
-	params.CRn = (esr >> 10) & 0xf;
-	params.CRm = (esr >> 1) & 0xf;
-	params.Op2 = (esr >> 17) & 0x7;
 	params.regval = vcpu_get_reg(vcpu, Rt);
-	params.is_write = !(esr & 1);
 	ret = emulate_sys_reg(vcpu, &params);

arch/arm64/kvm/sys_regs.h+31−0

@@ -11,6 +11,12 @@ · 10 unmodified lines
11	#ifndef __ARM64_KVM_SYS_REGS_LOCAL_H__	11	#ifndef __ARM64_KVM_SYS_REGS_LOCAL_H__
12	#define __ARM64_KVM_SYS_REGS_LOCAL_H__	12	#define __ARM64_KVM_SYS_REGS_LOCAL_H__
13		13
		14	#include <linux/bsearch.h>
		15
		16	#define reg_to_encoding(x) \
		17	sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
		18	(u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
		19
14	struct sys_reg_params {	20	struct sys_reg_params {
15	u8 Op0;	21	u8 Op0;
16	u8 Op1;	22	u8 Op1;
@@ -21,6 +27,14 @@ struct sys_reg_params { · 4 unmodified lines
21	bool is_write;	27	bool is_write;
22	};	28	};
23		29
		30	#define esr_sys64_to_params(esr) \
		31	((struct sys_reg_params){ .Op0 = ((esr) >> 20) & 3, \
		32	.Op1 = ((esr) >> 14) & 0x7, \
		33	.CRn = ((esr) >> 10) & 0xf, \
		34	.CRm = ((esr) >> 1) & 0xf, \
		35	.Op2 = ((esr) >> 17) & 0x7, \
		36	.is_write = !((esr) & 1) })
		37
24	struct sys_reg_desc {	38	struct sys_reg_desc {
25	/* Sysreg string for debug */	39	/* Sysreg string for debug */
26	const char *name;	40	const char *name;
@@ -152,6 +166,23 @@ static inline int cmp_sys_reg(const struct sys_reg_desc *i1, · 125 unmodified lines
152	return i1->Op2 - i2->Op2;	166	return i1->Op2 - i2->Op2;
153	}	167	}
154		168
		169	static inline int match_sys_reg(const void key, const void elt)
		170	{
		171	const unsigned long pval = (unsigned long)key;
		172	const struct sys_reg_desc *r = elt;
		173
		174	return pval - reg_to_encoding(r);
		175	}
		176
		177	static inline const struct sys_reg_desc *
		178	find_reg(const struct sys_reg_params *params, const struct sys_reg_desc table[],
		179	unsigned int num)
		180	{
		181	unsigned long pval = reg_to_encoding(params);
		182
		183	return __inline_bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
		184	}
		185
155	const struct sys_reg_desc *find_reg_by_id(u64 id,	186	const struct sys_reg_desc *find_reg_by_id(u64 id,
156	struct sys_reg_params *params,	187	struct sys_reg_params *params,
157	const struct sys_reg_desc table[],	188	const struct sys_reg_desc table[],

arch/arm64/kvm/trace_handle_exit.h+7−3

 	TP_printk("flags: 0x%08x", __entry->guest_debug)
 );
+/*
+ * The dreg32 name is a leftover from a distant past. This will really
+ * output a 64bit value...
+ */
 TRACE_EVENT(kvm_arm_set_dreg32,
-	TP_PROTO(const char *name, __u32 value),
+	TP_PROTO(const char *name, __u64 value),
 	TP_ARGS(name, value),
 	TP_STRUCT__entry(
 		__field(const char *, name)
-		__field(__u32, value)
+		__field(__u64, value)
 	),
 	TP_fast_assign(
 		__entry->value = value;
 	),
-	TP_printk("%s: 0x%08x", __entry->name, __entry->value)
+	TP_printk("%s: 0x%llx", __entry->name, __entry->value)
 );
 TRACE_DEFINE_SIZEOF(__u64);

arch/arm64/kvm/vgic/vgic-mmio-v2.c+2−2

@@ -282,7 +282,7 @@ static unsigned long vgic_mmio_read_vcpuif(struct kvm_vcpu *vcpu, · 281 unmodified lines
282	case GIC_CPU_PRIMASK:	282	case GIC_CPU_PRIMASK:
283	/*	283	/*
284	* Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the	284	* Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the
285	* the PMR field as GICH_VMCR.VMPriMask rather than	285	* PMR field as GICH_VMCR.VMPriMask rather than
286	* GICC_PMR.Priority, so we expose the upper five bits of	286	* GICC_PMR.Priority, so we expose the upper five bits of
287	* priority mask to userspace using the lower bits in the	287	* priority mask to userspace using the lower bits in the
288	* unsigned long.	288	* unsigned long.
@@ -329,7 +329,7 @@ static void vgic_mmio_write_vcpuif(struct kvm_vcpu *vcpu, · 40 unmodified lines
329	case GIC_CPU_PRIMASK:	329	case GIC_CPU_PRIMASK:
330	/*	330	/*
331	* Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the	331	* Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the
332	* the PMR field as GICH_VMCR.VMPriMask rather than	332	* PMR field as GICH_VMCR.VMPriMask rather than
333	* GICC_PMR.Priority, so we expose the upper five bits of	333	* GICC_PMR.Priority, so we expose the upper five bits of
334	* priority mask to userspace using the lower bits in the	334	* priority mask to userspace using the lower bits in the
335	* unsigned long.	335	* unsigned long.

arch/arm64/kvm/vgic/vgic-v2.c+5−31

@@ -60,6 +60,7 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu) · 59 unmodified lines
60	u32 val = cpuif->vgic_lr[lr];	60	u32 val = cpuif->vgic_lr[lr];
61	u32 cpuid, intid = val & GICH_LR_VIRTUALID;	61	u32 cpuid, intid = val & GICH_LR_VIRTUALID;
62	struct vgic_irq *irq;	62	struct vgic_irq *irq;
		63	bool deactivated;
63		64
64	/* Extract the source vCPU id from the LR */	65	/* Extract the source vCPU id from the LR */
65	cpuid = val & GICH_LR_PHYSID_CPUID;	66	cpuid = val & GICH_LR_PHYSID_CPUID;
@@ -75,7 +76,8 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu) · 9 unmodified lines
75		76
76	raw_spin_lock(&irq->irq_lock);	77	raw_spin_lock(&irq->irq_lock);
77		78
78	/* Always preserve the active bit */	79	/* Always preserve the active bit, note deactivation */
		80	deactivated = irq->active && !(val & GICH_LR_ACTIVE_BIT);
79	irq->active = !!(val & GICH_LR_ACTIVE_BIT);	81	irq->active = !!(val & GICH_LR_ACTIVE_BIT);
80		82
81	if (irq->active && vgic_irq_is_sgi(intid))	83	if (irq->active && vgic_irq_is_sgi(intid))
@@ -96,36 +98,8 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu) · 14 unmodified lines
96	if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE))	98	if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE))
97	irq->pending_latch = false;	99	irq->pending_latch = false;
98		100
99	/*	101	/* Handle resampling for mapped interrupts if required */
100	* Level-triggered mapped IRQs are special because we only	102	vgic_irq_handle_resampling(irq, deactivated, val & GICH_LR_PENDING_BIT);
101	* observe rising edges as input to the VGIC.
102	*
103	* If the guest never acked the interrupt we have to sample
104	* the physical line and set the line level, because the
105	* device state could have changed or we simply need to
106	* process the still pending interrupt later.
107	*
108	* If this causes us to lower the level, we have to also clear
109	* the physical active state, since we will otherwise never be
110	* told when the interrupt becomes asserted again.
111	*
112	* Another case is when the interrupt requires a helping hand
113	* on deactivation (no HW deactivation, for example).
114	*/
115	if (vgic_irq_is_mapped_level(irq)) {
116	bool resample = false;
117
118	if (val & GICH_LR_PENDING_BIT) {
119	irq->line_level = vgic_get_phys_line_level(irq);
120	resample = !irq->line_level;
121	} else if (vgic_irq_needs_resampling(irq) &&
122	!(irq->active \|\| irq->pending_latch)) {
123	resample = true;
124	}
125
126	if (resample)
127	vgic_irq_set_phys_active(irq, false);
128	}
129		103
130	raw_spin_unlock(&irq->irq_lock);	104	raw_spin_unlock(&irq->irq_lock);
131	vgic_put_irq(vcpu->kvm, irq);	105	vgic_put_irq(vcpu->kvm, irq);

arch/arm64/kvm/vgic/vgic-v3.c+5−31

@@ -46,6 +46,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) · 45 unmodified lines
46	u32 intid, cpuid;	46	u32 intid, cpuid;
47	struct vgic_irq *irq;	47	struct vgic_irq *irq;
48	bool is_v2_sgi = false;	48	bool is_v2_sgi = false;
		49	bool deactivated;
49		50
50	cpuid = val & GICH_LR_PHYSID_CPUID;	51	cpuid = val & GICH_LR_PHYSID_CPUID;
51	cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;	52	cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
@@ -68,7 +69,8 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) · 16 unmodified lines
68		69
69	raw_spin_lock(&irq->irq_lock);	70	raw_spin_lock(&irq->irq_lock);
70		71
71	/* Always preserve the active bit */	72	/* Always preserve the active bit, note deactivation */
		73	deactivated = irq->active && !(val & ICH_LR_ACTIVE_BIT);
72	irq->active = !!(val & ICH_LR_ACTIVE_BIT);	74	irq->active = !!(val & ICH_LR_ACTIVE_BIT);
73		75
74	if (irq->active && is_v2_sgi)	76	if (irq->active && is_v2_sgi)
@@ -89,36 +91,8 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) · 14 unmodified lines
89	if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE))	91	if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE))
90	irq->pending_latch = false;	92	irq->pending_latch = false;
91		93
92	/*	94	/* Handle resampling for mapped interrupts if required */
93	* Level-triggered mapped IRQs are special because we only	95	vgic_irq_handle_resampling(irq, deactivated, val & ICH_LR_PENDING_BIT);
94	* observe rising edges as input to the VGIC.
95	*
96	* If the guest never acked the interrupt we have to sample
97	* the physical line and set the line level, because the
98	* device state could have changed or we simply need to
99	* process the still pending interrupt later.
100	*
101	* If this causes us to lower the level, we have to also clear
102	* the physical active state, since we will otherwise never be
103	* told when the interrupt becomes asserted again.
104	*
105	* Another case is when the interrupt requires a helping hand
106	* on deactivation (no HW deactivation, for example).
107	*/
108	if (vgic_irq_is_mapped_level(irq)) {
109	bool resample = false;
110
111	if (val & ICH_LR_PENDING_BIT) {
112	irq->line_level = vgic_get_phys_line_level(irq);
113	resample = !irq->line_level;
114	} else if (vgic_irq_needs_resampling(irq) &&
115	!(irq->active \|\| irq->pending_latch)) {
116	resample = true;
117	}
118
119	if (resample)
120	vgic_irq_set_phys_active(irq, false);
121	}
122		96
123	raw_spin_unlock(&irq->irq_lock);	97	raw_spin_unlock(&irq->irq_lock);
124	vgic_put_irq(vcpu->kvm, irq);	98	vgic_put_irq(vcpu->kvm, irq);

arch/arm64/kvm/vgic/vgic.c+38−1

@@ -106,7 +106,6 @@ struct vgic_irq vgic_get_irq(struct kvm kvm, struct kvm_vcpu *vcpu, · 105 unmodified lines
106	if (intid >= VGIC_MIN_LPI)	106	if (intid >= VGIC_MIN_LPI)
107	return vgic_get_lpi(kvm, intid);	107	return vgic_get_lpi(kvm, intid);
108		108
109	WARN(1, "Looking up struct vgic_irq for reserved INTID");
110	return NULL;	109	return NULL;
111	}	110	}
112		111
@@ -1022,3 +1021,41 @@ bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid) · 909 unmodified lines
1022		1021
1023	return map_is_active;	1022	return map_is_active;
1024	}	1023	}
		1024
		1025	/*
		1026	* Level-triggered mapped IRQs are special because we only observe rising
		1027	* edges as input to the VGIC.
		1028	*
		1029	* If the guest never acked the interrupt we have to sample the physical
		1030	* line and set the line level, because the device state could have changed
		1031	* or we simply need to process the still pending interrupt later.
		1032	*
		1033	* We could also have entered the guest with the interrupt active+pending.
		1034	* On the next exit, we need to re-evaluate the pending state, as it could
		1035	* otherwise result in a spurious interrupt by injecting a now potentially
		1036	* stale pending state.
		1037	*
		1038	* If this causes us to lower the level, we have to also clear the physical
		1039	* active state, since we will otherwise never be told when the interrupt
		1040	* becomes asserted again.
		1041	*
		1042	* Another case is when the interrupt requires a helping hand on
		1043	* deactivation (no HW deactivation, for example).
		1044	*/
		1045	void vgic_irq_handle_resampling(struct vgic_irq *irq,
		1046	bool lr_deactivated, bool lr_pending)
		1047	{
		1048	if (vgic_irq_is_mapped_level(irq)) {
		1049	bool resample = false;
		1050
		1051	if (unlikely(vgic_irq_needs_resampling(irq))) {
		1052	resample = !(irq->active \|\| irq->pending_latch);
		1053	} else if (lr_pending \|\| (lr_deactivated && irq->line_level)) {
		1054	irq->line_level = vgic_get_phys_line_level(irq);
		1055	resample = !irq->line_level;
		1056	}
		1057
		1058	if (resample)
		1059	vgic_irq_set_phys_active(irq, false);
		1060	}
		1061	}

arch/arm64/kvm/vgic/vgic.h+2−0

@@ -169,6 +169,8 @@ void vgic_irq_set_phys_active(struct vgic_irq *irq, bool active); · 168 unmodified lines
169	bool vgic_queue_irq_unlock(struct kvm kvm, struct vgic_irq irq,	169	bool vgic_queue_irq_unlock(struct kvm kvm, struct vgic_irq irq,
170	unsigned long flags);	170	unsigned long flags);
171	void vgic_kick_vcpus(struct kvm *kvm);	171	void vgic_kick_vcpus(struct kvm *kvm);
		172	void vgic_irq_handle_resampling(struct vgic_irq *irq,
		173	bool lr_deactivated, bool lr_pending);
172		174
173	int vgic_check_ioaddr(struct kvm kvm, phys_addr_t ioaddr,	175	int vgic_check_ioaddr(struct kvm kvm, phys_addr_t ioaddr,
174	phys_addr_t addr, phys_addr_t alignment);	176	phys_addr_t addr, phys_addr_t alignment);

arch/arm64/mm/mmu.c+8−12

 	return dt_virt;
 }
-#if CONFIG_PGTABLE_LEVELS > 3
 int pud_set_huge(pud_t *pudp, phys_addr_t phys, pgprot_t prot)
 {
 	pud_t new_pud = pfn_pud(__phys_to_pfn(phys), mk_pud_sect_prot(prot));
 	return 1;
 }
-int pud_clear_huge(pud_t *pudp)
-{
-	if (!pud_sect(READ_ONCE(*pudp)))
-		return 0;
-	pud_clear(pudp);
-	return 1;
-}
-#endif
-#if CONFIG_PGTABLE_LEVELS > 2
 int pmd_set_huge(pmd_t *pmdp, phys_addr_t phys, pgprot_t prot)
 {
 	pmd_t new_pmd = pfn_pmd(__phys_to_pfn(phys), mk_pmd_sect_prot(prot));
 	return 1;
 }
+int pud_clear_huge(pud_t *pudp)
+{
+	if (!pud_sect(READ_ONCE(*pudp)))
+		return 0;
+	pud_clear(pudp);
+	return 1;
+}
 int pmd_clear_huge(pmd_t *pmdp)
 {
 	if (!pmd_sect(READ_ONCE(*pmdp)))
 	pmd_clear(pmdp);
 	return 1;
 }
-#endif
 int pmd_free_pte_page(pmd_t *pmdp, unsigned long addr)
 {

arch/arm64/net/bpf_jit_comp.c+13−0

@@ -823,6 +823,19 @@ emit_cond_jmp: · 822 unmodified lines
823	return ret;	823	return ret;
824	break;	824	break;
825		825
		826	/* speculation barrier */
		827	case BPF_ST \| BPF_NOSPEC:
		828	/*
		829	* Nothing required here.
		830	*
		831	* In case of arm64, we rely on the firmware mitigation of
		832	* Speculative Store Bypass as controlled via the ssbd kernel
		833	* parameter. Whenever the mitigation is enabled, it works
		834	* for all of the kernel code with no need to provide any
		835	* additional instructions.
		836	*/
		837	break;
		838
826	/* ST: (size )(dst + off) = imm */	839	/* ST: (size )(dst + off) = imm */
827	case BPF_ST \| BPF_MEM \| BPF_W:	840	case BPF_ST \| BPF_MEM \| BPF_W:
828	case BPF_ST \| BPF_MEM \| BPF_H:	841	case BPF_ST \| BPF_MEM \| BPF_H:

arch/h8300/Kconfig.cpu+0−1

@@ -44,7 +44,6 @@ config H8300_H8MAX · 43 unmodified lines
44	bool "H8MAX"	44	bool "H8MAX"
45	select H83069	45	select H83069
46	select RAMKERNEL	46	select RAMKERNEL
47	select HAVE_IDE
48	help	47	help
49	H8MAX Evaluation Board Support	48	H8MAX Evaluation Board Support
50	More Information. (Japanese Only)	49	More Information. (Japanese Only)

arch/ia64/Kconfig+0−1

@@ -25,7 +25,6 @@ config IA64 · 24 unmodified lines
25	select HAVE_ASM_MODVERSIONS	25	select HAVE_ASM_MODVERSIONS
26	select HAVE_UNSTABLE_SCHED_CLOCK	26	select HAVE_UNSTABLE_SCHED_CLOCK
27	select HAVE_EXIT_THREAD	27	select HAVE_EXIT_THREAD
28	select HAVE_IDE
29	select HAVE_KPROBES	28	select HAVE_KPROBES
30	select HAVE_KRETPROBES	29	select HAVE_KRETPROBES
31	select HAVE_FTRACE_MCOUNT_RECORD	30	select HAVE_FTRACE_MCOUNT_RECORD

arch/m68k/Kconfig+0−1

@@ -23,7 +23,6 @@ config M68K · 22 unmodified lines
23	select HAVE_DEBUG_BUGVERBOSE	23	select HAVE_DEBUG_BUGVERBOSE
24	select HAVE_EFFICIENT_UNALIGNED_ACCESS if !CPU_HAS_NO_UNALIGNED	24	select HAVE_EFFICIENT_UNALIGNED_ACCESS if !CPU_HAS_NO_UNALIGNED
25	select HAVE_FUTEX_CMPXCHG if MMU && FUTEX	25	select HAVE_FUTEX_CMPXCHG if MMU && FUTEX
26	select HAVE_IDE
27	select HAVE_MOD_ARCH_SPECIFIC	26	select HAVE_MOD_ARCH_SPECIFIC
28	select HAVE_UID16	27	select HAVE_UID16
29	select MMU_GATHER_NO_RANGE if MMU	28	select MMU_GATHER_NO_RANGE if MMU

arch/m68k/Kconfig.machine+1−0

@@ -33,6 +33,7 @@ config MAC · 32 unmodified lines
33	depends on MMU	33	depends on MMU
34	select MMU_MOTOROLA if MMU	34	select MMU_MOTOROLA if MMU
35	select HAVE_ARCH_NVRAM_OPS	35	select HAVE_ARCH_NVRAM_OPS
		36	select HAVE_PATA_PLATFORM
36	select LEGACY_TIMER_TICK	37	select LEGACY_TIMER_TICK
37	help	38	help
38	This option enables support for the Apple Macintosh series of	39	This option enables support for the Apple Macintosh series of

arch/m68k/coldfire/m525x.c+1−1

@@ -26,7 +26,7 @@ DEFINE_CLK(pll, "pll.0", MCF_CLK); · 25 unmodified lines
26	DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);	26	DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
27		27
28	static struct clk_lookup m525x_clk_lookup[] = {	28	static struct clk_lookup m525x_clk_lookup[] = {
29	CLKDEV_INIT(NULL, "pll.0", &pll),	29	CLKDEV_INIT(NULL, "pll.0", &clk_pll),
30	CLKDEV_INIT(NULL, "sys.0", &clk_sys),	30	CLKDEV_INIT(NULL, "sys.0", &clk_sys),
31	CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),	31	CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
32	CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),	32	CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),

arch/mips/Kconfig+0−1

@@ -71,7 +71,6 @@ config MIPS · 70 unmodified lines
71	select HAVE_FUNCTION_TRACER	71	select HAVE_FUNCTION_TRACER
72	select HAVE_GCC_PLUGINS	72	select HAVE_GCC_PLUGINS
73	select HAVE_GENERIC_VDSO	73	select HAVE_GENERIC_VDSO
74	select HAVE_IDE
75	select HAVE_IOREMAP_PROT	74	select HAVE_IOREMAP_PROT
76	select HAVE_IRQ_EXIT_ON_IRQ_STACK	75	select HAVE_IRQ_EXIT_ON_IRQ_STACK
77	select HAVE_IRQ_TIME_ACCOUNTING	76	select HAVE_IRQ_TIME_ACCOUNTING

arch/mips/net/ebpf_jit.c+3−0

@@ -1355,6 +1355,9 @@ jeq_common: · 1354 unmodified lines
1355	}	1355	}
1356	break;	1356	break;
1357		1357
		1358	case BPF_ST \| BPF_NOSPEC: /* speculation barrier */
		1359	break;
		1360
1358	case BPF_ST \| BPF_B \| BPF_MEM:	1361	case BPF_ST \| BPF_B \| BPF_MEM:
1359	case BPF_ST \| BPF_H \| BPF_MEM:	1362	case BPF_ST \| BPF_H \| BPF_MEM:
1360	case BPF_ST \| BPF_W \| BPF_MEM:	1363	case BPF_ST \| BPF_W \| BPF_MEM:

arch/nds32/mm/mmap.c+1−1

@@ -59,7 +59,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, · 58 unmodified lines
59		59
60	vma = find_vma(mm, addr);	60	vma = find_vma(mm, addr);
61	if (TASK_SIZE - len >= addr &&	61	if (TASK_SIZE - len >= addr &&
62	(!vma \|\| addr + len <= vma->vm_start))	62	(!vma \|\| addr + len <= vm_start_gap(vma)))
63	return addr;	63	return addr;
64	}	64	}
65		65

arch/parisc/Kconfig+0−1

@@ -3,7 +3,6 @@ config PARISC · 2 unmodified lines
3	def_bool y	3	def_bool y
4	select ARCH_32BIT_OFF_T if !64BIT	4	select ARCH_32BIT_OFF_T if !64BIT
5	select ARCH_MIGHT_HAVE_PC_PARPORT	5	select ARCH_MIGHT_HAVE_PC_PARPORT
6	select HAVE_IDE
7	select HAVE_FUNCTION_TRACER	6	select HAVE_FUNCTION_TRACER
8	select HAVE_FUNCTION_GRAPH_TRACER	7	select HAVE_FUNCTION_GRAPH_TRACER
9	select HAVE_SYSCALL_TRACEPOINTS	8	select HAVE_SYSCALL_TRACEPOINTS

arch/powerpc/Kconfig+0−1

@@ -220,7 +220,6 @@ config PPC · 219 unmodified lines
220	select HAVE_HARDLOCKUP_DETECTOR_ARCH if PPC_BOOK3S_64 && SMP	220	select HAVE_HARDLOCKUP_DETECTOR_ARCH if PPC_BOOK3S_64 && SMP
221	select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI && !HAVE_HARDLOCKUP_DETECTOR_ARCH	221	select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI && !HAVE_HARDLOCKUP_DETECTOR_ARCH
222	select HAVE_HW_BREAKPOINT if PERF_EVENTS && (PPC_BOOK3S \|\| PPC_8xx)	222	select HAVE_HW_BREAKPOINT if PERF_EVENTS && (PPC_BOOK3S \|\| PPC_8xx)
223	select HAVE_IDE
224	select HAVE_IOREMAP_PROT	223	select HAVE_IOREMAP_PROT
225	select HAVE_IRQ_EXIT_ON_IRQ_STACK	224	select HAVE_IRQ_EXIT_ON_IRQ_STACK
226	select HAVE_IRQ_TIME_ACCOUNTING	225	select HAVE_IRQ_TIME_ACCOUNTING

arch/powerpc/kernel/vdso64/Makefile+7−0

@@ -27,6 +27,13 @@ KASAN_SANITIZE := n · 26 unmodified lines
27		27
28	ccflags-y := -shared -fno-common -fno-builtin -nostdlib \	28	ccflags-y := -shared -fno-common -fno-builtin -nostdlib \
29	-Wl,-soname=linux-vdso64.so.1 -Wl,--hash-style=both	29	-Wl,-soname=linux-vdso64.so.1 -Wl,--hash-style=both
		30
		31	# Go prior to 1.16.x assumes r30 is not clobbered by any VDSO code. That used to be true
		32	# by accident when the VDSO was hand-written asm code, but may not be now that the VDSO is
		33	# compiler generated. To avoid breaking Go tell GCC not to use r30. Impact on code
		34	# generation is minimal, it will just use r29 instead.
		35	ccflags-y += $(call cc-option, -ffixed-r30)
		36
30	asflags-y := -D__VDSO64__ -s	37	asflags-y := -D__VDSO64__ -s
31		38
32	targets += vdso64.lds	39	targets += vdso64.lds

arch/powerpc/kvm/book3s_hv.c+2−0

 		HFSCR_DSCR | HFSCR_VECVSX | HFSCR_FP | HFSCR_PREFIX;
 	if (cpu_has_feature(CPU_FTR_HVMODE)) {
 		vcpu->arch.hfscr &= mfspr(SPRN_HFSCR);
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 		if (cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
 			vcpu->arch.hfscr |= HFSCR_TM;
+#endif
 	}
 	if (cpu_has_feature(CPU_FTR_TM_COMP))
 		vcpu->arch.hfscr |= HFSCR_TM;

arch/powerpc/kvm/book3s_hv_nested.c+20−0

@@ -302,6 +302,9 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu) · 301 unmodified lines
302	if (vcpu->kvm->arch.l1_ptcr == 0)	302	if (vcpu->kvm->arch.l1_ptcr == 0)
303	return H_NOT_AVAILABLE;	303	return H_NOT_AVAILABLE;
304		304
		305	if (MSR_TM_TRANSACTIONAL(vcpu->arch.shregs.msr))
		306	return H_BAD_MODE;
		307
305	/* copy parameters in */	308	/* copy parameters in */
306	hv_ptr = kvmppc_get_gpr(vcpu, 4);	309	hv_ptr = kvmppc_get_gpr(vcpu, 4);
307	regs_ptr = kvmppc_get_gpr(vcpu, 5);	310	regs_ptr = kvmppc_get_gpr(vcpu, 5);
@@ -322,6 +325,23 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu) · 14 unmodified lines
322	if (l2_hv.vcpu_token >= NR_CPUS)	325	if (l2_hv.vcpu_token >= NR_CPUS)
323	return H_PARAMETER;	326	return H_PARAMETER;
324		327
		328	/*
		329	* L1 must have set up a suspended state to enter the L2 in a
		330	* transactional state, and only in that case. These have to be
		331	* filtered out here to prevent causing a TM Bad Thing in the
		332	* host HRFID. We could synthesize a TM Bad Thing back to the L1
		333	* here but there doesn't seem like much point.
		334	*/
		335	if (MSR_TM_SUSPENDED(vcpu->arch.shregs.msr)) {
		336	if (!MSR_TM_ACTIVE(l2_regs.msr))
		337	return H_BAD_MODE;
		338	} else {
		339	if (l2_regs.msr & MSR_TS_MASK)
		340	return H_BAD_MODE;
		341	if (WARN_ON_ONCE(vcpu->arch.shregs.msr & MSR_TS_MASK))
		342	return H_BAD_MODE;
		343	}
		344
325	/* translate lpid */	345	/* translate lpid */
326	l2 = kvmhv_get_nested(vcpu->kvm, l2_hv.lpid, true);	346	l2 = kvmhv_get_nested(vcpu->kvm, l2_hv.lpid, true);
327	if (!l2)	347	if (!l2)

arch/powerpc/kvm/book3s_hv_p9_entry.c+22−3

 	 */
 	mtspr(SPRN_HDEC, hdec);
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+tm_return_to_guest:
+#endif
 	mtspr(SPRN_DAR, vcpu->arch.shregs.dar);
 	mtspr(SPRN_DSISR, vcpu->arch.shregs.dsisr);
 	mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0);
 		 * is in real suspend mode and is trying to transition to
 		 * transactional mode.
 		 */
-		if (local_paca->kvm_hstate.fake_suspend &&
+		if (!local_paca->kvm_hstate.fake_suspend &&
 				(vcpu->arch.shregs.msr & MSR_TS_S)) {
 			if (kvmhv_p9_tm_emulation_early(vcpu)) {
-				/* Prevent it being handled again. */
+				/*
-				trap = 0;
+				 * Go straight back into the guest with the
+				 * new NIP/MSR as set by TM emulation.
+				 */
+				mtspr(SPRN_HSRR0, vcpu->arch.regs.nip);
+				mtspr(SPRN_HSRR1, vcpu->arch.shregs.msr);
+				/*
+				 * tm_return_to_guest re-loads SRR0/1, DAR,
+				 * DSISR after RI is cleared, in case they had
+				 * been clobbered by a MCE.
+				 */
+				__mtmsrd(0, 1); /* clear RI */
+				goto tm_return_to_guest;
 			}
 		}
 #endif
 	 * If we are in real mode, only switch MMU on after the MMU is
 	 * switched to host, to avoid the P9_RADIX_PREFETCH_BUG.
 	 */
+	if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) &&
+	    vcpu->arch.shregs.msr & MSR_TS_MASK)
+		msr |= MSR_TS_S;
 	__mtmsrd(msr, 0);
 	end_timing(vcpu);

arch/powerpc/kvm/book3s_rtas.c+22−3

@@ -242,6 +242,17 @@ int kvmppc_rtas_hcall(struct kvm_vcpu *vcpu) · 241 unmodified lines
242	* value so we can restore it on the way out.	242	* value so we can restore it on the way out.
243	*/	243	*/
244	orig_rets = args.rets;	244	orig_rets = args.rets;
		245	if (be32_to_cpu(args.nargs) >= ARRAY_SIZE(args.args)) {
		246	/*
		247	* Don't overflow our args array: ensure there is room for
		248	* at least rets[0] (even if the call specifies 0 nret).
		249	*
		250	* Each handler must then check for the correct nargs and nret
		251	* values, but they may always return failure in rets[0].
		252	*/
		253	rc = -EINVAL;
		254	goto fail;
		255	}
245	args.rets = &args.args[be32_to_cpu(args.nargs)];	256	args.rets = &args.args[be32_to_cpu(args.nargs)];
246		257
247	mutex_lock(&vcpu->kvm->arch.rtas_token_lock);	258	mutex_lock(&vcpu->kvm->arch.rtas_token_lock);
@@ -269,9 +280,17 @@ int kvmppc_rtas_hcall(struct kvm_vcpu *vcpu) · 21 unmodified lines
269	fail:	280	fail:
270	/*	281	/*
271	* We only get here if the guest has called RTAS with a bogus	282	* We only get here if the guest has called RTAS with a bogus
272	* args pointer. That means we can't get to the args, and so we	283	* args pointer or nargs/nret values that would overflow the
273	* can't fail the RTAS call. So fail right out to userspace,	284	* array. That means we can't get to the args, and so we can't
274	* which should kill the guest.	285	* fail the RTAS call. So fail right out to userspace, which
		286	* should kill the guest.
		287	*
		288	* SLOF should actually pass the hcall return value from the
		289	* rtas handler call in r3, so enter_rtas could be modified to
		290	* return a failure indication in r3 and we could return such
		291	* errors to the guest rather than failing to host userspace.
		292	* However old guests that don't test for failure could then
		293	* continue silently after errors, so for now we won't do this.
275	*/	294	*/
276	return rc;	295	return rc;
277	}	296	}

arch/powerpc/kvm/powerpc.c+2−2

 	{
 		struct kvm_enable_cap cap;
 		r = -EFAULT;
-		vcpu_load(vcpu);
 		if (copy_from_user(&cap, argp, sizeof(cap)))
 			goto out;
+		vcpu_load(vcpu);
 		r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
 		vcpu_put(vcpu);
 		break;
 	case KVM_DIRTY_TLB: {
 		struct kvm_dirty_tlb dirty;
 		r = -EFAULT;
-		vcpu_load(vcpu);
 		if (copy_from_user(&dirty, argp, sizeof(dirty)))
 			goto out;
+		vcpu_load(vcpu);
 		r = kvm_vcpu_ioctl_dirty_tlb(vcpu, &dirty);
 		vcpu_put(vcpu);
 		break;

arch/powerpc/mm/nohash/8xx.c+10−0

@@ -240,3 +240,13 @@ void __init setup_kuap(bool disabled) · 239 unmodified lines
240	mtspr(SPRN_MD_AP, MD_APG_KUAP);	240	mtspr(SPRN_MD_AP, MD_APG_KUAP);
241	}	241	}
242	#endif	242	#endif
		243
		244	int pud_clear_huge(pud_t *pud)
		245	{
		246	return 0;
		247	}
		248
		249	int pmd_clear_huge(pmd_t *pmd)
		250	{
		251	return 0;
		252	}

arch/powerpc/net/bpf_jit_comp32.c+6−0

 			}
 			break;
+		/*
+		 * BPF_ST NOSPEC (speculation barrier)
+		 */
+		case BPF_ST | BPF_NOSPEC:
+			break;
 		/*
 		 * BPF_ST(X)
 		 */

arch/powerpc/net/bpf_jit_comp64.c+6−0

 			}
 			break;
+		/*
+		 * BPF_ST NOSPEC (speculation barrier)
+		 */
+		case BPF_ST | BPF_NOSPEC:
+			break;
 		/*
 		 * BPF_ST(X)
 		 */

arch/powerpc/platforms/pasemi/idle.c+1−0

@@ -42,6 +42,7 @@ static int pasemi_system_reset_exception(struct pt_regs *regs) · 41 unmodified lines
42	switch (regs->msr & SRR1_WAKEMASK) {	42	switch (regs->msr & SRR1_WAKEMASK) {
43	case SRR1_WAKEDEC:	43	case SRR1_WAKEDEC:
44	set_dec(1);	44	set_dec(1);
		45	break;
45	case SRR1_WAKEEE:	46	case SRR1_WAKEEE:
46	/*	47	/*
47	* Handle these when interrupts get re-enabled and we take	48	* Handle these when interrupts get re-enabled and we take

arch/powerpc/platforms/pseries/setup.c+1−1

@@ -77,7 +77,7 @@ · 76 unmodified lines
77	#include "../../../../drivers/pci/pci.h"	77	#include "../../../../drivers/pci/pci.h"
78		78
79	DEFINE_STATIC_KEY_FALSE(shared_processor);	79	DEFINE_STATIC_KEY_FALSE(shared_processor);
80	EXPORT_SYMBOL_GPL(shared_processor);	80	EXPORT_SYMBOL(shared_processor);
81		81
82	int CMO_PrPSP = -1;	82	int CMO_PrPSP = -1;
83	int CMO_SecPSP = -1;	83	int CMO_SecPSP = -1;

arch/riscv/include/asm/efi.h+2−2

@@ -27,10 +27,10 @@ int efi_set_mapping_permissions(struct mm_struct mm, efi_memory_desc_t md); · 26 unmodified lines
27		27
28	#define ARCH_EFI_IRQ_FLAGS_MASK (SR_IE \| SR_SPIE)	28	#define ARCH_EFI_IRQ_FLAGS_MASK (SR_IE \| SR_SPIE)
29		29
30	/* Load initrd at enough distance from DRAM start */	30	/* Load initrd anywhere in system RAM */
31	static inline unsigned long efi_get_max_initrd_addr(unsigned long image_addr)	31	static inline unsigned long efi_get_max_initrd_addr(unsigned long image_addr)
32	{	32	{
33	return image_addr + SZ_256M;	33	return ULONG_MAX;
34	}	34	}
35		35
36	#define alloc_screen_info(x...) (&screen_info)	36	#define alloc_screen_info(x...) (&screen_info)

arch/riscv/kernel/stacktrace.c+5−1

 {
 	unsigned long pc = 0;
-	if (likely(task && task != current && !task_is_running(task)))
+	if (likely(task && task != current && !task_is_running(task))) {
+		if (!try_get_task_stack(task))
+			return 0;
 		walk_stackframe(task, NULL, save_wchan, &pc);
+		put_task_stack(task);
+	}
 	return pc;
 }

arch/riscv/lib/uaccess.S+13−14

 	 * t0 - end of uncopied dst
 	 */
 	add	t0, a0, a2
-	bgtu	a0, t0, 5f
 	/*
 	 * Use byte copy only if too small.
+	 * SZREG holds 4 for RV32 and 8 for RV64
 	 */
-	li	a3, 8*SZREG /* size must be larger than size in word_copy */
+	li	a3, 9*SZREG /* size must be larger than size in word_copy */
 	bltu	a2, a3, .Lbyte_copy_tail
 	/*
-	 * Copy first bytes until dst is align to word boundary.
+	 * Copy first bytes until dst is aligned to word boundary.
 	 * a0 - start of dst
 	 * t1 - start of aligned dst
 	 */
 	addi	t1, a0, SZREG-1
 	andi	t1, t1, ~(SZREG-1)
 	/* dst is already aligned, skip */
-	beq	a0, t1, .Lskip_first_bytes
+	beq	a0, t1, .Lskip_align_dst
 1:
 	/* a5 - one byte for copying data */
 	fixup lb      a5, 0(a1), 10f
 	addi	a0, a0, 1	/* dst */
 	bltu	a0, t1, 1b	/* t1 - start of aligned dst */
-.Lskip_first_bytes:
+.Lskip_align_dst:
 	/*
 	 * Now dst is aligned.
 	 * Use shift-copy if src is misaligned.
 	 *
 	 * a0 - start of aligned dst
 	 * a1 - start of aligned src
-	 * a3 - a1 & mask:(SZREG-1)
 	 * t0 - end of aligned dst
 	 */
-	addi	t0, t0, -(8*SZREG-1) /* not to over run */
+	addi	t0, t0, -(8*SZREG) /* not to over run */
 2:
 	fixup REG_L   a4,        0(a1), 10f
 	fixup REG_L   a5,    SZREG(a1), 10f
 	addi	a1, a1, 8*SZREG
 	bltu	a0, t0, 2b
-	addi	t0, t0, 8*SZREG-1 /* revert to original value */
+	addi	t0, t0, 8*SZREG /* revert to original value */
 	j	.Lbyte_copy_tail
 .Lshift_copy:
 	 * For misaligned copy we still perform aligned word copy, but
 	 * we need to use the value fetched from the previous iteration and
 	 * do some shifts.
-	 * This is safe because reading less than a word size.
+	 * This is safe because reading is less than a word size.
 	 *
 	 * a0 - start of aligned dst
 	 * a1 - start of src
 	 */
 	/* calculating aligned word boundary for dst */
 	andi	t1, t0, ~(SZREG-1)
-	/* Converting unaligned src to aligned arc */
+	/* Converting unaligned src to aligned src */
 	andi	a1, a1, ~(SZREG-1)
 	/*
 	 * t3 - prev shift
 	 * t4 - current shift
 	 */
-	slli	t3, a3, LGREG
+	slli	t3, a3, 3 /* converting bytes in a3 to bits */
 	li	a5, SZREG*8
 	sub	t4, a5, t3
-	/* Load the first word to combine with seceond word */
+	/* Load the first word to combine with second word */
 	fixup REG_L   a5, 0(a1), 10f
 3:
 	 * a1 - start of remaining src
 	 * t0 - end of remaining dst
 	 */
-	bgeu	a0, t0, 5f
+	bgeu	a0, t0, .Lout_copy_user  /* check if end of copy */
 4:
 	fixup lb      a5, 0(a1), 10f
 	addi	a1, a1, 1	/* src */
 	addi	a0, a0, 1	/* dst */
 	bltu	a0, t0, 4b	/* t0 - end of dst */
-5:
+.Lout_copy_user:
 	/* Disable access to user memory */
 	csrc CSR_STATUS, t6
 	li	a0, 0

arch/riscv/mm/init.c+28−4

 }
 /*
- * The default maximal physical memory size is -PAGE_OFFSET,
+ * The default maximal physical memory size is -PAGE_OFFSET for 32-bit kernel,
- * limit the memory size via mem.
+ * whereas for 64-bit kernel, the end of the virtual address space is occupied
+ * by the modules/BPF/kernel mappings which reduces the available size of the
+ * linear mapping.
+ * Limit the memory size via mem.
  */
+#ifdef CONFIG_64BIT
+static phys_addr_t memory_limit = -PAGE_OFFSET - SZ_4G;
+#else
 static phys_addr_t memory_limit = -PAGE_OFFSET;
+#endif
 static int __init early_mem(char *p)
 {
 {
 	phys_addr_t vmlinux_end = __pa_symbol(&_end);
 	phys_addr_t vmlinux_start = __pa_symbol(&_start);
-	phys_addr_t max_mapped_addr = __pa(~(ulong)0);
+	phys_addr_t __maybe_unused max_mapped_addr;
 	phys_addr_t dram_end;
 #ifdef CONFIG_XIP_KERNEL
 	memblock_reserve(vmlinux_start, vmlinux_end - vmlinux_start);
 	dram_end = memblock_end_of_DRAM();
+#ifndef CONFIG_64BIT
 	/*
 	 * memblock allocator is not aware of the fact that last 4K bytes of
 	 * the addressable memory can not be mapped because of IS_ERR_VALUE
 	 * macro. Make sure that last 4k bytes are not usable by memblock
-	 * if end of dram is equal to maximum addressable memory.
+	 * if end of dram is equal to maximum addressable memory.  For 64-bit
+	 * kernel, this problem can't happen here as the end of the virtual
+	 * address space is occupied by the kernel mapping then this check must
+	 * be done in create_kernel_page_table.
 	 */
+	max_mapped_addr = __pa(~(ulong)0);
 	if (max_mapped_addr == (dram_end - 1))
 		memblock_set_current_limit(max_mapped_addr - 4096);
+#endif
 	min_low_pfn = PFN_UP(memblock_start_of_DRAM());
 	max_low_pfn = max_pfn = PFN_DOWN(dram_end);
 	BUG_ON((PAGE_OFFSET % PGDIR_SIZE) != 0);
 	BUG_ON((kernel_map.phys_addr % map_size) != 0);
+#ifdef CONFIG_64BIT
+	/*
+	 * The last 4K bytes of the addressable memory can not be mapped because
+	 * of IS_ERR_VALUE macro.
+	 */
+	BUG_ON((kernel_map.virt_addr + kernel_map.size) > ADDRESS_SPACE_END - SZ_4K);
+#endif
 	pt_ops.alloc_pte = alloc_pte_early;
 	pt_ops.get_pte_virt = get_pte_virt_early;
 #ifndef __PAGETABLE_PMD_FOLDED
 		if (start <= __pa(PAGE_OFFSET) &&
 		    __pa(PAGE_OFFSET) < end)
 			start = __pa(PAGE_OFFSET);
+		if (end >= __pa(PAGE_OFFSET) + memory_limit)
+			end = __pa(PAGE_OFFSET) + memory_limit;
 		map_size = best_map_size(start, end - start);
 		for (pa = start; pa < end; pa += map_size) {

arch/riscv/net/bpf_jit_comp32.c+4−0

 			return -1;
 		break;
+	/* speculation barrier */
+	case BPF_ST | BPF_NOSPEC:
+		break;
 	case BPF_ST | BPF_MEM | BPF_B:
 	case BPF_ST | BPF_MEM | BPF_H:
 	case BPF_ST | BPF_MEM | BPF_W:

arch/riscv/net/bpf_jit_comp64.c+4−0

 		emit_ld(rd, 0, RV_REG_T1, ctx);
 		break;
+	/* speculation barrier */
+	case BPF_ST | BPF_NOSPEC:
+		break;
 	/* ST: *(size *)(dst + off) = imm */
 	case BPF_ST | BPF_MEM | BPF_B:
 		emit_imm(RV_REG_T1, imm, ctx);

arch/s390/boot/text_dma.S+4−15

 #include <asm/errno.h>
 #include <asm/sigp.h>
-#ifdef CC_USING_EXPOLINE
-	.pushsection .dma.text.__s390_indirect_jump_r14,"axG"
-__dma__s390_indirect_jump_r14:
-	larl	%r1,0f
-	ex	0,0(%r1)
-	j	.
-0:	br	%r14
-	.popsection
-#endif
 	.section .dma.text,"ax"
 /*
  * Simplified version of expoline thunk. The normal thunks can not be used here,
  * affects a few functions that are not performance-relevant.
  */
 	.macro BR_EX_DMA_r14
-#ifdef CC_USING_EXPOLINE
+	larl	%r1,0f
-	jg	__dma__s390_indirect_jump_r14
+	ex	0,0(%r1)
-#else
+	j	.
-	br	%r14
+0:	br	%r14
-#endif
 	.endm
 /*

arch/s390/configs/debug_defconfig+18−9

 CONFIG_AUDIT=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_BPF_JIT=y
+CONFIG_BPF_JIT_ALWAYS_ON=y
+CONFIG_BPF_LSM=y
 CONFIG_PREEMPT=y
+CONFIG_SCHED_CORE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
 CONFIG_TASKSTATS=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_CGROUP_PERF=y
 CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_MISC=y
 CONFIG_NAMESPACES=y
 CONFIG_USER_NS=y
 CONFIG_CHECKPOINT_RESTORE=y
 CONFIG_SCHED_AUTOGROUP=y
 CONFIG_EXPERT=y
 # CONFIG_SYSFS_SYSCALL is not set
-CONFIG_BPF_LSM=y
-CONFIG_BPF_SYSCALL=y
 CONFIG_USERFAULTFD=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_PROFILING=y
 CONFIG_BLK_WBT=y
 CONFIG_BLK_CGROUP_IOLATENCY=y
 CONFIG_BLK_CGROUP_IOCOST=y
+CONFIG_BLK_CGROUP_IOPRIO=y
 CONFIG_BLK_INLINE_ENCRYPTION=y
 CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_FRONTSWAP=y
 CONFIG_CMA_DEBUG=y
 CONFIG_CMA_DEBUGFS=y
+CONFIG_CMA_SYSFS=y
 CONFIG_CMA_AREAS=7
 CONFIG_MEM_SOFT_DIRTY=y
 CONFIG_ZSWAP=y
 CONFIG_MPTCP=y
 CONFIG_NETFILTER=y
 CONFIG_BRIDGE_NETFILTER=m
+CONFIG_NETFILTER_NETLINK_HOOK=m
 CONFIG_NF_CONNTRACK=m
 CONFIG_NF_CONNTRACK_SECMARK=y
 CONFIG_NF_CONNTRACK_EVENTS=y
 CONFIG_IP_VS_PE_SIP=m
 CONFIG_NFT_FIB_IPV4=m
 CONFIG_NF_TABLES_ARP=y
+CONFIG_NF_LOG_IPV4=m
 CONFIG_IP_NF_IPTABLES=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
 CONFIG_VIRTIO_VSOCKETS=m
 CONFIG_NETLINK_DIAG=m
 CONFIG_CGROUP_NET_PRIO=y
-CONFIG_BPF_JIT=y
 CONFIG_NET_PKTGEN=m
 CONFIG_PCI=y
-CONFIG_PCI_IOV=y
 # CONFIG_PCIEASPM is not set
 CONFIG_PCI_DEBUG=y
+CONFIG_PCI_IOV=y
 CONFIG_HOTPLUG_PCI=y
 CONFIG_HOTPLUG_PCI_S390=y
 CONFIG_DEVTMPFS=y
 CONFIG_MD_FAULTY=m
 CONFIG_MD_CLUSTER=m
 CONFIG_BCACHE=m
-CONFIG_BLK_DEV_DM=m
+CONFIG_BLK_DEV_DM=y
 CONFIG_DM_UNSTRIPED=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MULTIPATH_HST=m
 CONFIG_DM_MULTIPATH_IOA=m
 CONFIG_DM_DELAY=m
+CONFIG_DM_INIT=y
 CONFIG_DM_UEVENT=y
 CONFIG_DM_FLAKEY=m
 CONFIG_DM_VERITY=m
 # CONFIG_NET_VENDOR_GOOGLE is not set
 # CONFIG_NET_VENDOR_HUAWEI is not set
 # CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICROSOFT is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
 CONFIG_MLX4_EN=m
 CONFIG_MLX5_CORE=m
 CONFIG_LEGACY_PTY_COUNT=0
 CONFIG_VIRTIO_CONSOLE=m
 CONFIG_HW_RANDOM_VIRTIO=m
-CONFIG_RAW_DRIVER=m
 CONFIG_HANGCHECK_TIMER=m
 CONFIG_TN3270_FS=y
 CONFIG_PPS=m
 CONFIG_VFIO=m
 CONFIG_VFIO_PCI=m
 CONFIG_VFIO_MDEV=m
-CONFIG_VFIO_MDEV_DEVICE=m
 CONFIG_VIRTIO_PCI=m
 CONFIG_VIRTIO_BALLOON=m
 CONFIG_VIRTIO_INPUT=y
 CONFIG_CUSE=m
 CONFIG_VIRTIO_FS=m
 CONFIG_OVERLAY_FS=m
+CONFIG_NETFS_STATS=y
 CONFIG_FSCACHE=m
 CONFIG_CACHEFILES=m
 CONFIG_ISO9660_FS=y
 CONFIG_NFSD_V4=y
 CONFIG_NFSD_V4_SECURITY_LABEL=y
 CONFIG_CIFS=m
-CONFIG_CIFS_STATS2=y
 CONFIG_CIFS_WEAK_PW_HASH=y
 CONFIG_CIFS_UPCALL=y
 CONFIG_CIFS_XATTR=y
 CONFIG_SECURITY_SELINUX_DISABLE=y
 CONFIG_SECURITY_LOCKDOWN_LSM=y
 CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y
+CONFIG_SECURITY_LANDLOCK=y
 CONFIG_INTEGRITY_SIGNATURE=y
 CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
 CONFIG_IMA=y
 CONFIG_CRYPTO_TEST=m
 CONFIG_CRYPTO_DH=m
 CONFIG_CRYPTO_ECDH=m
+CONFIG_CRYPTO_ECDSA=m
 CONFIG_CRYPTO_ECRDSA=m
 CONFIG_CRYPTO_SM2=m
 CONFIG_CRYPTO_CURVE25519=m
 CONFIG_FAIL_FUNCTION=y
 CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
 CONFIG_LKDTM=m
-CONFIG_TEST_LIST_SORT=y
 CONFIG_TEST_MIN_HEAP=y
 CONFIG_TEST_SORT=y
 CONFIG_KPROBES_SANITY_TEST=y
 CONFIG_ATOMIC64_SELFTEST=y
 CONFIG_TEST_BITOPS=m
 CONFIG_TEST_BPF=m
+CONFIG_TEST_LIVEPATCH=m

arch/s390/configs/defconfig+19−8

 CONFIG_AUDIT=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_BPF_JIT=y
+CONFIG_BPF_JIT_ALWAYS_ON=y
+CONFIG_BPF_LSM=y
+CONFIG_SCHED_CORE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
 CONFIG_TASKSTATS=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_CGROUP_PERF=y
 CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_MISC=y
 CONFIG_NAMESPACES=y
 CONFIG_USER_NS=y
 CONFIG_CHECKPOINT_RESTORE=y
 CONFIG_SCHED_AUTOGROUP=y
 CONFIG_EXPERT=y
 # CONFIG_SYSFS_SYSCALL is not set
-CONFIG_BPF_LSM=y
-CONFIG_BPF_SYSCALL=y
 CONFIG_USERFAULTFD=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_PROFILING=y
 CONFIG_BLK_WBT=y
 CONFIG_BLK_CGROUP_IOLATENCY=y
 CONFIG_BLK_CGROUP_IOCOST=y
+CONFIG_BLK_CGROUP_IOPRIO=y
 CONFIG_BLK_INLINE_ENCRYPTION=y
 CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_CLEANCACHE=y
 CONFIG_FRONTSWAP=y
+CONFIG_CMA_SYSFS=y
 CONFIG_CMA_AREAS=7
 CONFIG_MEM_SOFT_DIRTY=y
 CONFIG_ZSWAP=y
 CONFIG_MPTCP=y
 CONFIG_NETFILTER=y
 CONFIG_BRIDGE_NETFILTER=m
+CONFIG_NETFILTER_NETLINK_HOOK=m
 CONFIG_NF_CONNTRACK=m
 CONFIG_NF_CONNTRACK_SECMARK=y
 CONFIG_NF_CONNTRACK_EVENTS=y
 CONFIG_IP_VS_PE_SIP=m
 CONFIG_NFT_FIB_IPV4=m
 CONFIG_NF_TABLES_ARP=y
+CONFIG_NF_LOG_IPV4=m
 CONFIG_IP_NF_IPTABLES=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
 CONFIG_VIRTIO_VSOCKETS=m
 CONFIG_NETLINK_DIAG=m
 CONFIG_CGROUP_NET_PRIO=y
-CONFIG_BPF_JIT=y
 CONFIG_NET_PKTGEN=m
 CONFIG_PCI=y
-CONFIG_PCI_IOV=y
 # CONFIG_PCIEASPM is not set
+CONFIG_PCI_IOV=y
 CONFIG_HOTPLUG_PCI=y
 CONFIG_HOTPLUG_PCI_S390=y
 CONFIG_UEVENT_HELPER=y
 CONFIG_MD_FAULTY=m
 CONFIG_MD_CLUSTER=m
 CONFIG_BCACHE=m
-CONFIG_BLK_DEV_DM=m
+CONFIG_BLK_DEV_DM=y
 CONFIG_DM_UNSTRIPED=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MULTIPATH_HST=m
 CONFIG_DM_MULTIPATH_IOA=m
 CONFIG_DM_DELAY=m
+CONFIG_DM_INIT=y
 CONFIG_DM_UEVENT=y
 CONFIG_DM_FLAKEY=m
 CONFIG_DM_VERITY=m
 # CONFIG_NET_VENDOR_GOOGLE is not set
 # CONFIG_NET_VENDOR_HUAWEI is not set
 # CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICROSOFT is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
 CONFIG_MLX4_EN=m
 CONFIG_MLX5_CORE=m
 CONFIG_LEGACY_PTY_COUNT=0
 CONFIG_VIRTIO_CONSOLE=m
 CONFIG_HW_RANDOM_VIRTIO=m
-CONFIG_RAW_DRIVER=m
 CONFIG_HANGCHECK_TIMER=m
 CONFIG_TN3270_FS=y
 # CONFIG_PTP_1588_CLOCK is not set
 CONFIG_VFIO=m
 CONFIG_VFIO_PCI=m
 CONFIG_VFIO_MDEV=m
-CONFIG_VFIO_MDEV_DEVICE=m
 CONFIG_VIRTIO_PCI=m
 CONFIG_VIRTIO_BALLOON=m
 CONFIG_VIRTIO_INPUT=y
 CONFIG_CUSE=m
 CONFIG_VIRTIO_FS=m
 CONFIG_OVERLAY_FS=m
+CONFIG_NETFS_STATS=y
 CONFIG_FSCACHE=m
 CONFIG_CACHEFILES=m
 CONFIG_ISO9660_FS=y
 CONFIG_NFSD_V4=y
 CONFIG_NFSD_V4_SECURITY_LABEL=y
 CONFIG_CIFS=m
-CONFIG_CIFS_STATS2=y
 CONFIG_CIFS_WEAK_PW_HASH=y
 CONFIG_CIFS_UPCALL=y
 CONFIG_CIFS_XATTR=y
 CONFIG_SECURITY_SELINUX_DISABLE=y
 CONFIG_SECURITY_LOCKDOWN_LSM=y
 CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y
+CONFIG_SECURITY_LANDLOCK=y
 CONFIG_INTEGRITY_SIGNATURE=y
 CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
 CONFIG_IMA=y
 CONFIG_CRYPTO_TEST=m
 CONFIG_CRYPTO_DH=m
 CONFIG_CRYPTO_ECDH=m
+CONFIG_CRYPTO_ECDSA=m
 CONFIG_CRYPTO_ECRDSA=m
 CONFIG_CRYPTO_SM2=m
 CONFIG_CRYPTO_CURVE25519=m
 CONFIG_DMA_CMA=y
 CONFIG_CMA_SIZE_MBYTES=0
 CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_INFO_DWARF4=y
 CONFIG_GDB_SCRIPTS=y
 CONFIG_PERCPU_TEST=m
 CONFIG_ATOMIC64_SELFTEST=y
 CONFIG_TEST_BPF=m
+CONFIG_TEST_LIVEPATCH=m

arch/s390/configs/zfcpdump_defconfig+1−2

 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 # CONFIG_COMPACTION is not set
 # CONFIG_MIGRATION is not set
-# CONFIG_BOUNCE is not set
 CONFIG_NET=y
 # CONFIG_IUCV is not set
+# CONFIG_PCPU_DEV_REFCNT is not set
 # CONFIG_ETHTOOL_NETLINK is not set
 CONFIG_DEVTMPFS=y
 CONFIG_BLK_DEV_RAM=y
 # CONFIG_SERIO is not set
 # CONFIG_HVC_IUCV is not set
 # CONFIG_HW_RANDOM_S390 is not set
-CONFIG_RAW_DRIVER=y
 # CONFIG_HMC_DRV is not set
 # CONFIG_S390_TAPE is not set
 # CONFIG_VMCP is not set

arch/s390/include/asm/ftrace.h+1−0

@@ -19,6 +19,7 @@ void ftrace_caller(void); · 18 unmodified lines
19		19
20	extern char ftrace_graph_caller_end;	20	extern char ftrace_graph_caller_end;
21	extern unsigned long ftrace_plt;	21	extern unsigned long ftrace_plt;
		22	extern void *ftrace_func;
22		23
23	struct dyn_arch_ftrace { };	24	struct dyn_arch_ftrace { };
24		25

arch/s390/kernel/ftrace.c+2−0

  * trampoline (ftrace_plt), which clobbers also r1.
  */
+void *ftrace_func __read_mostly = ftrace_stub;
 unsigned long ftrace_plt;
 int ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr,
 int ftrace_update_ftrace_func(ftrace_func_t func)
 {
+	ftrace_func = func;
 	return 0;
 }

arch/s390/kernel/mcount.S+2−2

@@ -59,13 +59,13 @@ ENTRY(ftrace_caller) · 58 unmodified lines
59	#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES	59	#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
60	aghik %r2,%r0,-MCOUNT_INSN_SIZE	60	aghik %r2,%r0,-MCOUNT_INSN_SIZE
61	lgrl %r4,function_trace_op	61	lgrl %r4,function_trace_op
62	lgrl %r1,ftrace_trace_function	62	lgrl %r1,ftrace_func
63	#else	63	#else
64	lgr %r2,%r0	64	lgr %r2,%r0
65	aghi %r2,-MCOUNT_INSN_SIZE	65	aghi %r2,-MCOUNT_INSN_SIZE
66	larl %r4,function_trace_op	66	larl %r4,function_trace_op
67	lg %r4,0(%r4)	67	lg %r4,0(%r4)
68	larl %r1,ftrace_trace_function	68	larl %r1,ftrace_func
69	lg %r1,0(%r1)	69	lg %r1,0(%r1)
70	#endif	70	#endif
71	lgr %r3,%r14	71	lgr %r3,%r14

arch/s390/kernel/perf_cpum_cf.c+1−1

@@ -745,7 +745,7 @@ static int __init cpumf_pmu_init(void) · 744 unmodified lines
745	if (!cf_dbg) {	745	if (!cf_dbg) {
746	pr_err("Registration of s390dbf(cpum_cf) failed\n");	746	pr_err("Registration of s390dbf(cpum_cf) failed\n");
747	return -ENOMEM;	747	return -ENOMEM;
748	};	748	}
749	debug_register_view(cf_dbg, &debug_sprintf_view);	749	debug_register_view(cf_dbg, &debug_sprintf_view);
750		750
751	cpumf_pmu.attr_groups = cpumf_cf_event_group();	751	cpumf_pmu.attr_groups = cpumf_cf_event_group();

arch/s390/kernel/vdso32/Makefile+1−0

@@ -29,6 +29,7 @@ $(targets:%=$(obj)/%.dbg): KBUILD_CFLAGS = $(KBUILD_CFLAGS_32) · 28 unmodified lines
29	$(targets:%=$(obj)/%.dbg): KBUILD_AFLAGS = $(KBUILD_AFLAGS_32)	29	$(targets:%=$(obj)/%.dbg): KBUILD_AFLAGS = $(KBUILD_AFLAGS_32)
30		30
31	obj-y += vdso32_wrapper.o	31	obj-y += vdso32_wrapper.o
		32	targets += vdso32.lds
32	CPPFLAGS_vdso32.lds += -P -C -U$(ARCH)	33	CPPFLAGS_vdso32.lds += -P -C -U$(ARCH)
33		34
34	# Disable gcov profiling, ubsan and kasan for VDSO code	35	# Disable gcov profiling, ubsan and kasan for VDSO code

arch/s390/net/bpf_jit_comp.c+6−1

 {
 	u32 r1 = reg2hex[b1];
-	if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
+	if (r1 >= 6 && r1 <= 15 && !jit->seen_reg[r1])
 		jit->seen_reg[r1] = 1;
 }
 			break;
 		}
 		break;
+	/*
+	 * BPF_NOSPEC (speculation barrier)
+	 */
+	case BPF_ST | BPF_NOSPEC:
+		break;
 	/*
 	 * BPF_ST(X)
 	 */

arch/sh/Kconfig+0−1

@@ -39,7 +39,6 @@ config SUPERH · 38 unmodified lines
39	select HAVE_FUTEX_CMPXCHG if FUTEX	39	select HAVE_FUTEX_CMPXCHG if FUTEX
40	select HAVE_FTRACE_MCOUNT_RECORD	40	select HAVE_FTRACE_MCOUNT_RECORD
41	select HAVE_HW_BREAKPOINT	41	select HAVE_HW_BREAKPOINT
42	select HAVE_IDE if HAS_IOPORT_MAP
43	select HAVE_IOREMAP_PROT if MMU && !X2TLB	42	select HAVE_IOREMAP_PROT if MMU && !X2TLB
44	select HAVE_KERNEL_BZIP2	43	select HAVE_KERNEL_BZIP2
45	select HAVE_KERNEL_GZIP	44	select HAVE_KERNEL_GZIP

arch/sparc/Kconfig+0−1

@@ -19,7 +19,6 @@ config SPARC · 18 unmodified lines
19	select OF	19	select OF
20	select OF_PROMTREE	20	select OF_PROMTREE
21	select HAVE_ASM_MODVERSIONS	21	select HAVE_ASM_MODVERSIONS
22	select HAVE_IDE
23	select HAVE_ARCH_KGDB if !SMP \|\| SPARC64	22	select HAVE_ARCH_KGDB if !SMP \|\| SPARC64
24	select HAVE_ARCH_TRACEHOOK	23	select HAVE_ARCH_TRACEHOOK
25	select HAVE_ARCH_SECCOMP if SPARC64	24	select HAVE_ARCH_SECCOMP if SPARC64

arch/sparc/net/bpf_jit_comp_64.c+3−0

 			return 1;
 		break;
 	}
+	/* speculation barrier */
+	case BPF_ST | BPF_NOSPEC:
+		break;
 	/* ST: *(size *)(dst + off) = imm */
 	case BPF_ST | BPF_MEM | BPF_W:
 	case BPF_ST | BPF_MEM | BPF_H:

arch/x86/Kconfig+0−1

@@ -202,7 +202,6 @@ config X86 · 201 unmodified lines
202	select HAVE_FUNCTION_TRACER	202	select HAVE_FUNCTION_TRACER
203	select HAVE_GCC_PLUGINS	203	select HAVE_GCC_PLUGINS
204	select HAVE_HW_BREAKPOINT	204	select HAVE_HW_BREAKPOINT
205	select HAVE_IDE
206	select HAVE_IOREMAP_PROT	205	select HAVE_IOREMAP_PROT
207	select HAVE_IRQ_EXIT_ON_IRQ_STACK if X86_64	206	select HAVE_IRQ_EXIT_ON_IRQ_STACK if X86_64
208	select HAVE_IRQ_TIME_ACCOUNTING	207	select HAVE_IRQ_TIME_ACCOUNTING

arch/x86/kernel/cpu/mshyperv.c+1−1

@@ -237,7 +237,7 @@ static void __init hv_smp_prepare_cpus(unsigned int max_cpus) · 236 unmodified lines
237	for_each_present_cpu(i) {	237	for_each_present_cpu(i) {
238	if (i == 0)	238	if (i == 0)
239	continue;	239	continue;
240	ret = hv_call_add_logical_proc(numa_cpu_node(i), i, i);	240	ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i));
241	BUG_ON(ret);	241	BUG_ON(ret);
242	}	242	}
243		243

arch/x86/kernel/jump_label.c+4−3

 	return (struct jump_label_patch){.code = code, .size = size};
 }
-static inline void __jump_label_transform(struct jump_entry *entry,
+static __always_inline void
-					  enum jump_label_type type,
+__jump_label_transform(struct jump_entry *entry,
-					  int init)
+		       enum jump_label_type type,
+		       int init)
 {
 	const struct jump_label_patch jlp = __jump_label_patch(entry, type);

arch/x86/mm/pgtable.c+15−19

 }
 #endif
-#if CONFIG_PGTABLE_LEVELS > 3
 /**
  * pud_set_huge - setup kernel PUD mapping
  *
 	return 1;
 }
-/**
- * pud_clear_huge - clear kernel PUD mapping when it is set
- *
- * Returns 1 on success and 0 on failure (no PUD map is found).
- */
-int pud_clear_huge(pud_t *pud)
-{
-	if (pud_large(*pud)) {
-		pud_clear(pud);
-		return 1;
-	}
-	return 0;
-}
-#endif
-#if CONFIG_PGTABLE_LEVELS > 2
 /**
  * pmd_set_huge - setup kernel PMD mapping
  *
 	return 1;
 }
+/**
+ * pud_clear_huge - clear kernel PUD mapping when it is set
+ *
+ * Returns 1 on success and 0 on failure (no PUD map is found).
+ */
+int pud_clear_huge(pud_t *pud)
+{
+	if (pud_large(*pud)) {
+		pud_clear(pud);
+		return 1;
+	}
+	return 0;
+}
 /**
  * pmd_clear_huge - clear kernel PMD mapping when it is set
  *
 	return 0;
 }
-#endif
 #ifdef CONFIG_X86_64
 /**

arch/x86/net/bpf_jit_comp.c+7−0

@@ -1219,6 +1219,13 @@ static int do_jit(struct bpf_prog bpf_prog, int addrs, u8 *image, · 1218 unmodified lines
1219	}	1219	}
1220	break;	1220	break;
1221		1221
		1222	/* speculation barrier */
		1223	case BPF_ST \| BPF_NOSPEC:
		1224	if (boot_cpu_has(X86_FEATURE_XMM2))
		1225	/* Emit 'lfence' */
		1226	EMIT3(0x0F, 0xAE, 0xE8);
		1227	break;
		1228
1222	/* ST: (u8)(dst_reg + off) = imm */	1229	/* ST: (u8)(dst_reg + off) = imm */
1223	case BPF_ST \| BPF_MEM \| BPF_B:	1230	case BPF_ST \| BPF_MEM \| BPF_B:
1224	if (is_ereg(dst_reg))	1231	if (is_ereg(dst_reg))

arch/x86/net/bpf_jit_comp32.c+6−0

 			i++;
 			break;
 		}
+		/* speculation barrier */
+		case BPF_ST | BPF_NOSPEC:
+			if (boot_cpu_has(X86_FEATURE_XMM2))
+				/* Emit 'lfence' */
+				EMIT3(0x0F, 0xAE, 0xE8);
+			break;
 		/* ST: *(u8*)(dst_reg + off) = imm */
 		case BPF_ST | BPF_MEM | BPF_H:
 		case BPF_ST | BPF_MEM | BPF_B:

arch/xtensa/Kconfig+0−1

@@ -327,7 +327,6 @@ config XTENSA_PLATFORM_ISS · 326 unmodified lines
327		327
328	config XTENSA_PLATFORM_XT2000	328	config XTENSA_PLATFORM_XT2000
329	bool "XT2000"	329	bool "XT2000"
330	select HAVE_IDE
331	help	330	help
332	XT2000 is the name of Tensilica's feature-rich emulation platform.	331	XT2000 is the name of Tensilica's feature-rich emulation platform.
333	This hardware is capable of running a full Linux distribution.	332	This hardware is capable of running a full Linux distribution.

block/blk-iocost.c+6−5

 		return -1;
 	iocg_commit_bio(ctx->iocg, wait->bio, wait->abs_cost, cost);
+	wait->committed = true;
 	/*
 	 * autoremove_wake_function() removes the wait entry only when it
-	 * actually changed the task state.  We want the wait always
+	 * actually changed the task state. We want the wait always removed.
-	 * removed.  Remove explicitly and use default_wake_function().
+	 * Remove explicitly and use default_wake_function(). Note that the
+	 * order of operations is important as finish_wait() tests whether
+	 * @wq_entry is removed without grabbing the lock.
 	 */
-	list_del_init(&wq_entry->entry);
-	wait->committed = true;
 	default_wake_function(wq_entry, mode, flags, key);
+	list_del_init_careful(&wq_entry->entry);
 	return 0;
 }

block/blk-mq-sched.c+4−13

 	percpu_ref_put(&q->q_usage_counter);
 }
-static void blk_mq_sched_free_tags(struct blk_mq_tag_set *set,
-				   struct blk_mq_hw_ctx *hctx,
-				   unsigned int hctx_idx)
-{
-	if (hctx->sched_tags) {
-		blk_mq_free_rqs(set, hctx->sched_tags, hctx_idx);
-		blk_mq_free_rq_map(hctx->sched_tags, set->flags);
-		hctx->sched_tags = NULL;
-	}
-}
 static int blk_mq_sched_alloc_tags(struct request_queue *q,
 				   struct blk_mq_hw_ctx *hctx,
 				   unsigned int hctx_idx)
 		return -ENOMEM;
 	ret = blk_mq_alloc_rqs(set, hctx->sched_tags, hctx_idx, q->nr_requests);
-	if (ret)
+	if (ret) {
-		blk_mq_sched_free_tags(set, hctx, hctx_idx);
+		blk_mq_free_rq_map(hctx->sched_tags, set->flags);
+		hctx->sched_tags = NULL;
+	}
 	return ret;
 }

block/genhd.c+1−2

 	disk_release_events(disk);
 	kfree(disk->random);
 	xa_destroy(&disk->part_tbl);
-	bdput(disk->part0);
 	if (test_bit(GD_QUEUE_REF, &disk->state) && disk->queue)
 		blk_put_queue(disk->queue);
-	kfree(disk);
+	bdput(disk->part0);	/* frees the disk */
 }
 struct class block_class = {
 	.name		= "block",

drivers/acpi/Kconfig+1−1

@@ -370,7 +370,7 @@ config ACPI_TABLE_UPGRADE · 369 unmodified lines
370	config ACPI_TABLE_OVERRIDE_VIA_BUILTIN_INITRD	370	config ACPI_TABLE_OVERRIDE_VIA_BUILTIN_INITRD
371	bool "Override ACPI tables from built-in initrd"	371	bool "Override ACPI tables from built-in initrd"
372	depends on ACPI_TABLE_UPGRADE	372	depends on ACPI_TABLE_UPGRADE
373	depends on INITRAMFS_SOURCE!="" && INITRAMFS_COMPRESSION=""	373	depends on INITRAMFS_SOURCE!="" && INITRAMFS_COMPRESSION_NONE
374	help	374	help
375	This option provides functionality to override arbitrary ACPI tables	375	This option provides functionality to override arbitrary ACPI tables
376	from built-in uncompressed initrd.	376	from built-in uncompressed initrd.

drivers/acpi/dptf/dptf_pch_fivr.c+43−8

@@ -9,6 +9,42 @@ · 8 unmodified lines
9	#include <linux/module.h>	9	#include <linux/module.h>
10	#include <linux/platform_device.h>	10	#include <linux/platform_device.h>
11		11
		12	struct pch_fivr_resp {
		13	u64 status;
		14	u64 result;
		15	};
		16
		17	static int pch_fivr_read(acpi_handle handle, char method, struct pch_fivr_resp fivr_resp)
		18	{
		19	struct acpi_buffer resp = { sizeof(struct pch_fivr_resp), fivr_resp};
		20	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
		21	struct acpi_buffer format = { sizeof("NN"), "NN" };
		22	union acpi_object *obj;
		23	acpi_status status;
		24	int ret = -EFAULT;
		25
		26	status = acpi_evaluate_object(handle, method, NULL, &buffer);
		27	if (ACPI_FAILURE(status))
		28	return ret;
		29
		30	obj = buffer.pointer;
		31	if (!obj \|\| obj->type != ACPI_TYPE_PACKAGE)
		32	goto release_buffer;
		33
		34	status = acpi_extract_package(obj, &format, &resp);
		35	if (ACPI_FAILURE(status))
		36	goto release_buffer;
		37
		38	if (fivr_resp->status)
		39	goto release_buffer;
		40
		41	ret = 0;
		42
		43	release_buffer:
		44	kfree(buffer.pointer);
		45	return ret;
		46	}
		47
12	/*	48	/*
13	* Presentation of attributes which are defined for INT1045	49	* Presentation of attributes which are defined for INT1045
14	* They are:	50	* They are:
@@ -23,15 +59,14 @@ static ssize_t name##_show(struct device *dev,\ · 8 unmodified lines
23	char *buf)\	59	char *buf)\
24	{\	60	{\
25	struct acpi_device *acpi_dev = dev_get_drvdata(dev);\	61	struct acpi_device *acpi_dev = dev_get_drvdata(dev);\
26	unsigned long long val;\	62	struct pch_fivr_resp fivr_resp;\
27	acpi_status status;\	63	int status;\
28	\	64	\
29	status = acpi_evaluate_integer(acpi_dev->handle, #method,\	65	status = pch_fivr_read(acpi_dev->handle, #method, &fivr_resp);\
30	NULL, &val);\	66	if (status)\
31	if (ACPI_SUCCESS(status))\	67	return status;\
32	return sprintf(buf, "%d\n", (int)val);\	68	\
33	else\	69	return sprintf(buf, "%llu\n", fivr_resp.result);\
34	return -EINVAL;\
35	}	70	}
36		71
37	#define PCH_FIVR_STORE(name, method) \	72	#define PCH_FIVR_STORE(name, method) \

drivers/acpi/resource.c+1−8

 	}
 }
-static bool irq_is_legacy(struct acpi_resource_irq *irq)
-{
-	return irq->triggering == ACPI_EDGE_SENSITIVE &&
-		irq->polarity == ACPI_ACTIVE_HIGH &&
-		irq->shareable == ACPI_EXCLUSIVE;
-}
 /**
  * acpi_dev_resource_interrupt - Extract ACPI interrupt resource information.
  * @ares: Input ACPI resource object.
 		}
 		acpi_dev_get_irqresource(res, irq->interrupts[index],
 					 irq->triggering, irq->polarity,
-					 irq->shareable, irq_is_legacy(irq));
+					 irq->shareable, true);
 		break;
 	case ACPI_RESOURCE_TYPE_EXTENDED_IRQ:
 		ext_irq = &ares->data.extended_irq;

drivers/acpi/utils.c+3−4

  * Return the next match of ACPI device if another matching device was present
  * at the moment of invocation, or NULL otherwise.
  *
- * FIXME: The function does not tolerate the sudden disappearance of @adev, e.g.
- * in the case of a hotplug event. That said, the caller should ensure that
- * this will never happen.
- *
  * The caller is responsible for invoking acpi_dev_put() on the returned device.
+ * On the other hand the function invokes  acpi_dev_put() on the given @adev
+ * assuming that its reference counter had been increased beforehand.
  *
  * See additional information in acpi_dev_present() as well.
  */
 	match.hrv = hrv;
 	dev = bus_find_device(&acpi_bus_type, start, &match, acpi_dev_match_cb);
+	acpi_dev_put(adev);
 	return dev ? to_acpi_device(dev) : NULL;
 }
 EXPORT_SYMBOL(acpi_dev_get_next_match_dev);

drivers/acpi/x86/s2idle.c+8−2

 		 * AMDI0006:
 		 * - should use rev_id 0x0
 		 * - function mask = 0x3: Should use Microsoft method
+		 * AMDI0007:
+		 * - Should use rev_id 0x2
+		 * - Should only use AMD method
 		 */
 		const char *hid = acpi_device_hid(adev);
-		rev_id = 0;
+		rev_id = strcmp(hid, "AMDI0007") ? 0 : 2;
 		lps0_dsm_func_mask = validate_dsm(adev->handle,
 					ACPI_LPS0_DSM_UUID_AMD, rev_id, &lps0_dsm_guid);
 		lps0_dsm_func_mask_microsoft = validate_dsm(adev->handle,
-					ACPI_LPS0_DSM_UUID_MICROSOFT, rev_id,
+					ACPI_LPS0_DSM_UUID_MICROSOFT, 0,
 					&lps0_dsm_guid_microsoft);
 		if (lps0_dsm_func_mask > 0x3 && (!strcmp(hid, "AMD0004") ||
 						 !strcmp(hid, "AMDI0005"))) {
 			lps0_dsm_func_mask = (lps0_dsm_func_mask << 1) | 0x1;
 			acpi_handle_debug(adev->handle, "_DSM UUID %s: Adjusted function mask: 0x%x\n",
 					  ACPI_LPS0_DSM_UUID_AMD, lps0_dsm_func_mask);
+		} else if (lps0_dsm_func_mask_microsoft > 0 && !strcmp(hid, "AMDI0007")) {
+			lps0_dsm_func_mask_microsoft = -EINVAL;
+			acpi_handle_debug(adev->handle, "_DSM Using AMD method\n");
 		}
 	} else {
 		rev_id = 1;

drivers/ata/libata-sff.c+27−8

 }
 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
+static void ata_pio_xfer(struct ata_queued_cmd *qc, struct page *page,
+		unsigned int offset, size_t xfer_size)
+{
+	bool do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
+	unsigned char *buf;
+	buf = kmap_atomic(page);
+	qc->ap->ops->sff_data_xfer(qc, buf + offset, xfer_size, do_write);
+	kunmap_atomic(buf);
+	if (!do_write && !PageSlab(page))
+		flush_dcache_page(page);
+}
 /**
  *	ata_pio_sector - Transfer a sector of data.
  *	@qc: Command on going
  */
 static void ata_pio_sector(struct ata_queued_cmd *qc)
 {
-	int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
 	struct ata_port *ap = qc->ap;
 	struct page *page;
 	unsigned int offset;
-	unsigned char *buf;
 	if (!qc->cursg) {
 		qc->curbytes = qc->nbytes;
 	DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
-	/* do the actual data transfer */
+	/*
-	buf = kmap_atomic(page);
+	 * Split the transfer when it splits a page boundary.  Note that the
-	ap->ops->sff_data_xfer(qc, buf + offset, qc->sect_size, do_write);
+	 * split still has to be dword aligned like all ATA data transfers.
-	kunmap_atomic(buf);
+	 */
+	WARN_ON_ONCE(offset % 4);
+	if (offset + qc->sect_size > PAGE_SIZE) {
+		unsigned int split_len = PAGE_SIZE - offset;
-	if (!do_write && !PageSlab(page))
+		ata_pio_xfer(qc, page, offset, split_len);
-		flush_dcache_page(page);
+		ata_pio_xfer(qc, nth_page(page, 1), 0,
+			     qc->sect_size - split_len);
+	} else {
+		ata_pio_xfer(qc, page, offset, qc->sect_size);
+	}
 	qc->curbytes += qc->sect_size;
 	qc->cursg_ofs += qc->sect_size;

drivers/base/auxiliary.c+7−1

 int __auxiliary_driver_register(struct auxiliary_driver *auxdrv,
 				struct module *owner, const char *modname)
 {
+	int ret;
 	if (WARN_ON(!auxdrv->probe) || WARN_ON(!auxdrv->id_table))
 		return -EINVAL;
 	auxdrv->driver.bus = &auxiliary_bus_type;
 	auxdrv->driver.mod_name = modname;
-	return driver_register(&auxdrv->driver);
+	ret = driver_register(&auxdrv->driver);
+	if (ret)
+		kfree(auxdrv->driver.name);
+	return ret;
 }
 EXPORT_SYMBOL_GPL(__auxiliary_driver_register);

drivers/base/core.c+4−2

 		return;
 	}
-	snprintf(buf, len, "supplier:%s:%s", dev_bus_name(sup), dev_name(sup));
+	if (device_is_registered(con)) {
-	sysfs_remove_link(&con->kobj, buf);
+		snprintf(buf, len, "supplier:%s:%s", dev_bus_name(sup), dev_name(sup));
+		sysfs_remove_link(&con->kobj, buf);
+	}
 	snprintf(buf, len, "consumer:%s:%s", dev_bus_name(con), dev_name(con));
 	sysfs_remove_link(&sup->kobj, buf);
 	kfree(buf);

drivers/block/loop.c+97−31

 static DEFINE_IDR(loop_index_idr);
 static DEFINE_MUTEX(loop_ctl_mutex);
+static DEFINE_MUTEX(loop_validate_mutex);
+/**
+ * loop_global_lock_killable() - take locks for safe loop_validate_file() test
+ *
+ * @lo: struct loop_device
+ * @global: true if @lo is about to bind another "struct loop_device", false otherwise
+ *
+ * Returns 0 on success, -EINTR otherwise.
+ *
+ * Since loop_validate_file() traverses on other "struct loop_device" if
+ * is_loop_device() is true, we need a global lock for serializing concurrent
+ * loop_configure()/loop_change_fd()/__loop_clr_fd() calls.
+ */
+static int loop_global_lock_killable(struct loop_device *lo, bool global)
+{
+	int err;
+	if (global) {
+		err = mutex_lock_killable(&loop_validate_mutex);
+		if (err)
+			return err;
+	}
+	err = mutex_lock_killable(&lo->lo_mutex);
+	if (err && global)
+		mutex_unlock(&loop_validate_mutex);
+	return err;
+}
+/**
+ * loop_global_unlock() - release locks taken by loop_global_lock_killable()
+ *
+ * @lo: struct loop_device
+ * @global: true if @lo was about to bind another "struct loop_device", false otherwise
+ */
+static void loop_global_unlock(struct loop_device *lo, bool global)
+{
+	mutex_unlock(&lo->lo_mutex);
+	if (global)
+		mutex_unlock(&loop_validate_mutex);
+}
 static int max_part;
 static int part_shift;
 	while (is_loop_device(f)) {
 		struct loop_device *l;
+		lockdep_assert_held(&loop_validate_mutex);
 		if (f->f_mapping->host->i_rdev == bdev->bd_dev)
 			return -EBADF;
 		l = I_BDEV(f->f_mapping->host)->bd_disk->private_data;
-		if (l->lo_state != Lo_bound) {
+		if (l->lo_state != Lo_bound)
 			return -EINVAL;
-		}
+		/* Order wrt setting lo->lo_backing_file in loop_configure(). */
+		rmb();
 		f = l->lo_backing_file;
 	}
 	if (!S_ISREG(inode->i_mode) && !S_ISBLK(inode->i_mode))
 static int loop_change_fd(struct loop_device *lo, struct block_device *bdev,
 			  unsigned int arg)
 {
-	struct file	*file = NULL, *old_file;
+	struct file *file = fget(arg);
-	int		error;
+	struct file *old_file;
-	bool		partscan;
+	int error;
+	bool partscan;
+	bool is_loop;
-	error = mutex_lock_killable(&lo->lo_mutex);
+	if (!file)
+		return -EBADF;
+	is_loop = is_loop_device(file);
+	error = loop_global_lock_killable(lo, is_loop);
 	if (error)
-		return error;
+		goto out_putf;
 	error = -ENXIO;
 	if (lo->lo_state != Lo_bound)
 		goto out_err;
 	if (!(lo->lo_flags & LO_FLAGS_READ_ONLY))
 		goto out_err;
-	error = -EBADF;
-	file = fget(arg);
-	if (!file)
-		goto out_err;
 	error = loop_validate_file(file, bdev);
 	if (error)
 		goto out_err;
 	loop_update_dio(lo);
 	blk_mq_unfreeze_queue(lo->lo_queue);
 	partscan = lo->lo_flags & LO_FLAGS_PARTSCAN;
-	mutex_unlock(&lo->lo_mutex);
+	loop_global_unlock(lo, is_loop);
+	/*
+	 * Flush loop_validate_file() before fput(), for l->lo_backing_file
+	 * might be pointing at old_file which might be the last reference.
+	 */
+	if (!is_loop) {
+		mutex_lock(&loop_validate_mutex);
+		mutex_unlock(&loop_validate_mutex);
+	}
 	/*
 	 * We must drop file reference outside of lo_mutex as dropping
 	 * the file ref can take open_mutex which creates circular locking
 	return 0;
 out_err:
-	mutex_unlock(&lo->lo_mutex);
+	loop_global_unlock(lo, is_loop);
-	if (file)
+out_putf:
-		fput(file);
+	fput(file);
 	return error;
 }
 			  struct block_device *bdev,
 			  const struct loop_config *config)
 {
-	struct file	*file;
+	struct file *file = fget(config->fd);
-	struct inode	*inode;
+	struct inode *inode;
 	struct address_space *mapping;
-	int		error;
+	int error;
-	loff_t		size;
+	loff_t size;
-	bool		partscan;
+	bool partscan;
-	unsigned short  bsize;
+	unsigned short bsize;
+	bool is_loop;
+	if (!file)
+		return -EBADF;
+	is_loop = is_loop_device(file);
 	/* This is safe, since we have a reference from open(). */
 	__module_get(THIS_MODULE);
-	error = -EBADF;
-	file = fget(config->fd);
-	if (!file)
-		goto out;
 	/*
 	 * If we don't hold exclusive handle for the device, upgrade to it
 	 * here to avoid changing device under exclusive owner.
 			goto out_putf;
 	}
-	error = mutex_lock_killable(&lo->lo_mutex);
+	error = loop_global_lock_killable(lo, is_loop);
 	if (error)
 		goto out_bdev;
 	size = get_loop_size(lo, file);
 	loop_set_size(lo, size);
+	/* Order wrt reading lo_state in loop_validate_file(). */
+	wmb();
 	lo->lo_state = Lo_bound;
 	if (part_shift)
 		lo->lo_flags |= LO_FLAGS_PARTSCAN;
 	 * put /dev/loopXX inode. Later in __loop_clr_fd() we bdput(bdev).
 	 */
 	bdgrab(bdev);
-	mutex_unlock(&lo->lo_mutex);
+	loop_global_unlock(lo, is_loop);
 	if (partscan)
 		loop_reread_partitions(lo);
 	if (!(mode & FMODE_EXCL))
 	return 0;
 out_unlock:
-	mutex_unlock(&lo->lo_mutex);
+	loop_global_unlock(lo, is_loop);
 out_bdev:
 	if (!(mode & FMODE_EXCL))
 		bd_abort_claiming(bdev, loop_configure);
 out_putf:
 	fput(file);
-out:
 	/* This is safe: open() is still holding a reference. */
 	module_put(THIS_MODULE);
 	return error;
 	int lo_number;
 	struct loop_worker *pos, *worker;
+	/*
+	 * Flush loop_configure() and loop_change_fd(). It is acceptable for
+	 * loop_validate_file() to succeed, for actual clear operation has not
+	 * started yet.
+	 */
+	mutex_lock(&loop_validate_mutex);
+	mutex_unlock(&loop_validate_mutex);
+	/*
+	 * loop_validate_file() now fails because l->lo_state != Lo_bound
+	 * became visible.
+	 */
 	mutex_lock(&lo->lo_mutex);
 	if (WARN_ON_ONCE(lo->lo_state != Lo_rundown)) {
 		err = -ENXIO;

drivers/block/rbd.c+13−20

@@ -4100,8 +4100,6 @@ again: · 4099 unmodified lines
4100		4100
4101	static bool rbd_quiesce_lock(struct rbd_device *rbd_dev)	4101	static bool rbd_quiesce_lock(struct rbd_device *rbd_dev)
4102	{	4102	{
4103	bool need_wait;
4104
4105	dout("%s rbd_dev %p\n", __func__, rbd_dev);	4103	dout("%s rbd_dev %p\n", __func__, rbd_dev);
4106	lockdep_assert_held_write(&rbd_dev->lock_rwsem);	4104	lockdep_assert_held_write(&rbd_dev->lock_rwsem);
4107		4105
@@ -4113,11 +4111,11 @@ static bool rbd_quiesce_lock(struct rbd_device *rbd_dev) · 5 unmodified lines
4113	*/	4111	*/
4114	rbd_dev->lock_state = RBD_LOCK_STATE_RELEASING;	4112	rbd_dev->lock_state = RBD_LOCK_STATE_RELEASING;
4115	rbd_assert(!completion_done(&rbd_dev->releasing_wait));	4113	rbd_assert(!completion_done(&rbd_dev->releasing_wait));
4116	need_wait = !list_empty(&rbd_dev->running_list);	4114	if (list_empty(&rbd_dev->running_list))
4117	downgrade_write(&rbd_dev->lock_rwsem);	4115	return true;
4118	if (need_wait)	4116
4119	wait_for_completion(&rbd_dev->releasing_wait);	4117	up_write(&rbd_dev->lock_rwsem);
4120	up_read(&rbd_dev->lock_rwsem);	4118	wait_for_completion(&rbd_dev->releasing_wait);
4121		4119
4122	down_write(&rbd_dev->lock_rwsem);	4120	down_write(&rbd_dev->lock_rwsem);
4123	if (rbd_dev->lock_state != RBD_LOCK_STATE_RELEASING)	4121	if (rbd_dev->lock_state != RBD_LOCK_STATE_RELEASING)
@@ -4203,15 +4201,11 @@ static void rbd_handle_acquired_lock(struct rbd_device *rbd_dev, u8 struct_v, · 79 unmodified lines
4203	if (!rbd_cid_equal(&cid, &rbd_empty_cid)) {	4201	if (!rbd_cid_equal(&cid, &rbd_empty_cid)) {
4204	down_write(&rbd_dev->lock_rwsem);	4202	down_write(&rbd_dev->lock_rwsem);
4205	if (rbd_cid_equal(&cid, &rbd_dev->owner_cid)) {	4203	if (rbd_cid_equal(&cid, &rbd_dev->owner_cid)) {
4206	/*	4204	dout("%s rbd_dev %p cid %llu-%llu == owner_cid\n",
4207	* we already know that the remote client is	4205	__func__, rbd_dev, cid.gid, cid.handle);
4208	* the owner	4206	} else {
4209	*/	4207	rbd_set_owner_cid(rbd_dev, &cid);
4210	up_write(&rbd_dev->lock_rwsem);
4211	return;
4212	}	4208	}
4213
4214	rbd_set_owner_cid(rbd_dev, &cid);
4215	downgrade_write(&rbd_dev->lock_rwsem);	4209	downgrade_write(&rbd_dev->lock_rwsem);
4216	} else {	4210	} else {
4217	down_read(&rbd_dev->lock_rwsem);	4211	down_read(&rbd_dev->lock_rwsem);
@@ -4236,14 +4230,12 @@ static void rbd_handle_released_lock(struct rbd_device *rbd_dev, u8 struct_v, · 18 unmodified lines
4236	if (!rbd_cid_equal(&cid, &rbd_empty_cid)) {	4230	if (!rbd_cid_equal(&cid, &rbd_empty_cid)) {
4237	down_write(&rbd_dev->lock_rwsem);	4231	down_write(&rbd_dev->lock_rwsem);
4238	if (!rbd_cid_equal(&cid, &rbd_dev->owner_cid)) {	4232	if (!rbd_cid_equal(&cid, &rbd_dev->owner_cid)) {
4239	dout("%s rbd_dev %p unexpected owner, cid %llu-%llu != owner_cid %llu-%llu\n",	4233	dout("%s rbd_dev %p cid %llu-%llu != owner_cid %llu-%llu\n",
4240	__func__, rbd_dev, cid.gid, cid.handle,	4234	__func__, rbd_dev, cid.gid, cid.handle,
4241	rbd_dev->owner_cid.gid, rbd_dev->owner_cid.handle);	4235	rbd_dev->owner_cid.gid, rbd_dev->owner_cid.handle);
4242	up_write(&rbd_dev->lock_rwsem);	4236	} else {
4243	return;	4237	rbd_set_owner_cid(rbd_dev, &rbd_empty_cid);
4244	}	4238	}
4245
4246	rbd_set_owner_cid(rbd_dev, &rbd_empty_cid);
4247	downgrade_write(&rbd_dev->lock_rwsem);	4239	downgrade_write(&rbd_dev->lock_rwsem);
4248	} else {	4240	} else {
4249	down_read(&rbd_dev->lock_rwsem);	4241	down_read(&rbd_dev->lock_rwsem);
@@ -4951,6 +4943,7 @@ static int rbd_init_disk(struct rbd_device *rbd_dev) · 701 unmodified lines
4951	disk->minors = RBD_MINORS_PER_MAJOR;	4943	disk->minors = RBD_MINORS_PER_MAJOR;
4952	}	4944	}
4953	disk->fops = &rbd_bd_ops;	4945	disk->fops = &rbd_bd_ops;
		4946	disk->private_data = rbd_dev;
4954		4947
4955	blk_queue_flag_set(QUEUE_FLAG_NONROT, q);	4948	blk_queue_flag_set(QUEUE_FLAG_NONROT, q);
4956	/* QUEUE_FLAG_ADD_RANDOM is off by default for blk-mq */	4949	/* QUEUE_FLAG_ADD_RANDOM is off by default for blk-mq */

drivers/bus/mhi/core/main.c+12−5

@@ -773,11 +773,18 @@ static void mhi_process_cmd_completion(struct mhi_controller *mhi_cntrl, · 772 unmodified lines
773	cmd_pkt = mhi_to_virtual(mhi_ring, ptr);	773	cmd_pkt = mhi_to_virtual(mhi_ring, ptr);
774		774
775	chan = MHI_TRE_GET_CMD_CHID(cmd_pkt);	775	chan = MHI_TRE_GET_CMD_CHID(cmd_pkt);
776	mhi_chan = &mhi_cntrl->mhi_chan[chan];	776
777	write_lock_bh(&mhi_chan->lock);	777	if (chan < mhi_cntrl->max_chan &&
778	mhi_chan->ccs = MHI_TRE_GET_EV_CODE(tre);	778	mhi_cntrl->mhi_chan[chan].configured) {
779	complete(&mhi_chan->completion);	779	mhi_chan = &mhi_cntrl->mhi_chan[chan];
780	write_unlock_bh(&mhi_chan->lock);	780	write_lock_bh(&mhi_chan->lock);
		781	mhi_chan->ccs = MHI_TRE_GET_EV_CODE(tre);
		782	complete(&mhi_chan->completion);
		783	write_unlock_bh(&mhi_chan->lock);
		784	} else {
		785	dev_err(&mhi_cntrl->mhi_dev->dev,
		786	"Completion packet for invalid channel ID: %d\n", chan);
		787	}
781		788
782	mhi_del_ring_element(mhi_cntrl, mhi_ring);	789	mhi_del_ring_element(mhi_cntrl, mhi_ring);
783	}	790	}

drivers/bus/mhi/pci_generic.c+36−9

@@ -32,6 +32,8 @@ · 31 unmodified lines
32	* @edl: emergency download mode firmware path (if any)	32	* @edl: emergency download mode firmware path (if any)
33	* @bar_num: PCI base address register to use for MHI MMIO register space	33	* @bar_num: PCI base address register to use for MHI MMIO register space
34	* @dma_data_width: DMA transfer word size (32 or 64 bits)	34	* @dma_data_width: DMA transfer word size (32 or 64 bits)
		35	* @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
		36	* of inband wake support (such as sdx24)
35	*/	37	*/
36	struct mhi_pci_dev_info {	38	struct mhi_pci_dev_info {
37	const struct mhi_controller_config *config;	39	const struct mhi_controller_config *config;
@@ -40,6 +42,7 @@ struct mhi_pci_dev_info { · 2 unmodified lines
40	const char *edl;	42	const char *edl;
41	unsigned int bar_num;	43	unsigned int bar_num;
42	unsigned int dma_data_width;	44	unsigned int dma_data_width;
		45	bool sideband_wake;
43	};	46	};
44		47
45	#define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \	48	#define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
@@ -72,6 +75,22 @@ struct mhi_pci_dev_info { · 26 unmodified lines
72	.doorbell_mode_switch = false, \	75	.doorbell_mode_switch = false, \
73	}	76	}
74		77
		78	#define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \
		79	{ \
		80	.num = ch_num, \
		81	.name = ch_name, \
		82	.num_elements = el_count, \
		83	.event_ring = ev_ring, \
		84	.dir = DMA_FROM_DEVICE, \
		85	.ee_mask = BIT(MHI_EE_AMSS), \
		86	.pollcfg = 0, \
		87	.doorbell = MHI_DB_BRST_DISABLE, \
		88	.lpm_notify = false, \
		89	.offload_channel = false, \
		90	.doorbell_mode_switch = false, \
		91	.auto_queue = true, \
		92	}
		93
75	#define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \	94	#define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \
76	{ \	95	{ \
77	.num_elements = el_count, \	96	.num_elements = el_count, \
@@ -210,7 +229,7 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { · 132 unmodified lines
210	MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0),	229	MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0),
211	MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0),	230	MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0),
212	MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0),	231	MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0),
213	MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0),	232	MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0),
214	MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),	233	MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
215	MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),	234	MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
216	MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2),	235	MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2),
@@ -242,7 +261,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { · 25 unmodified lines
242	.edl = "qcom/sdx65m/edl.mbn",	261	.edl = "qcom/sdx65m/edl.mbn",
243	.config = &modem_qcom_v1_mhiv_config,	262	.config = &modem_qcom_v1_mhiv_config,
244	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,	263	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
245	.dma_data_width = 32	264	.dma_data_width = 32,
		265	.sideband_wake = false,
246	};	266	};
247		267
248	static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {	268	static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
@@ -251,7 +271,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { · 2 unmodified lines
251	.edl = "qcom/sdx55m/edl.mbn",	271	.edl = "qcom/sdx55m/edl.mbn",
252	.config = &modem_qcom_v1_mhiv_config,	272	.config = &modem_qcom_v1_mhiv_config,
253	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,	273	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
254	.dma_data_width = 32	274	.dma_data_width = 32,
		275	.sideband_wake = false,
255	};	276	};
256		277
257	static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = {	278	static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = {
@@ -259,7 +280,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { · 1 unmodified line
259	.edl = "qcom/prog_firehose_sdx24.mbn",	280	.edl = "qcom/prog_firehose_sdx24.mbn",
260	.config = &modem_qcom_v1_mhiv_config,	281	.config = &modem_qcom_v1_mhiv_config,
261	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,	282	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
262	.dma_data_width = 32	283	.dma_data_width = 32,
		284	.sideband_wake = true,
263	};	285	};
264		286
265	static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = {	287	static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = {
@@ -301,7 +323,8 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { · 35 unmodified lines
301	.edl = "qcom/prog_firehose_sdx24.mbn",	323	.edl = "qcom/prog_firehose_sdx24.mbn",
302	.config = &modem_quectel_em1xx_config,	324	.config = &modem_quectel_em1xx_config,
303	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,	325	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
304	.dma_data_width = 32	326	.dma_data_width = 32,
		327	.sideband_wake = true,
305	};	328	};
306		329
307	static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {	330	static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
@@ -339,7 +362,8 @@ static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { · 31 unmodified lines
339	.edl = "qcom/sdx55m/edl.mbn",	362	.edl = "qcom/sdx55m/edl.mbn",
340	.config = &modem_foxconn_sdx55_config,	363	.config = &modem_foxconn_sdx55_config,
341	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,	364	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
342	.dma_data_width = 32	365	.dma_data_width = 32,
		366	.sideband_wake = false,
343	};	367	};
344		368
345	static const struct pci_device_id mhi_pci_id_table[] = {	369	static const struct pci_device_id mhi_pci_id_table[] = {
@@ -640,9 +664,12 @@ static int mhi_pci_probe(struct pci_dev pdev, const struct pci_device_id id) · 294 unmodified lines
640	mhi_cntrl->status_cb = mhi_pci_status_cb;	664	mhi_cntrl->status_cb = mhi_pci_status_cb;
641	mhi_cntrl->runtime_get = mhi_pci_runtime_get;	665	mhi_cntrl->runtime_get = mhi_pci_runtime_get;
642	mhi_cntrl->runtime_put = mhi_pci_runtime_put;	666	mhi_cntrl->runtime_put = mhi_pci_runtime_put;
643	mhi_cntrl->wake_get = mhi_pci_wake_get_nop;	667
644	mhi_cntrl->wake_put = mhi_pci_wake_put_nop;	668	if (info->sideband_wake) {
645	mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop;	669	mhi_cntrl->wake_get = mhi_pci_wake_get_nop;
		670	mhi_cntrl->wake_put = mhi_pci_wake_put_nop;
		671	mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop;
		672	}
646		673
647	err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width));	674	err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width));
648	if (err)	675	if (err)

drivers/firmware/efi/dev-path-parser.c+0−1

@@ -34,7 +34,6 @@ static long __init parse_acpi_path(const struct efi_dev_path *node, · 33 unmodified lines
34	break;	34	break;
35	if (!adev->pnp.unique_id && node->acpi.uid == 0)	35	if (!adev->pnp.unique_id && node->acpi.uid == 0)
36	break;	36	break;
37	acpi_dev_put(adev);
38	}	37	}
39	if (!adev)	38	if (!adev)
40	return -ENODEV;	39	return -ENODEV;

drivers/firmware/efi/efi.c+12−1

 static int efi_mem_reserve_iomem(phys_addr_t addr, u64 size)
 {
 	struct resource *res, *parent;
+	int ret;
 	res = kzalloc(sizeof(struct resource), GFP_ATOMIC);
 	if (!res)
 	/* we expect a conflict with a 'System RAM' region */
 	parent = request_resource_conflict(&iomem_resource, res);
-	return parent ? request_resource(parent, res) : 0;
+	ret = parent ? request_resource(parent, res) : 0;
+	/*
+	 * Given that efi_mem_reserve_iomem() can be called at any
+	 * time, only call memblock_reserve() if the architecture
+	 * keeps the infrastructure around.
+	 */
+	if (IS_ENABLED(CONFIG_ARCH_KEEP_MEMBLOCK) && !ret)
+		memblock_reserve(addr, size);
+	return ret;
 }
 int __ref efi_mem_reserve_persistent(phys_addr_t addr, u64 size)

drivers/firmware/efi/libstub/efi-stub-helper.c+2−2

@@ -630,8 +630,8 @@ efi_status_t efi_load_initrd_cmdline(efi_loaded_image_t *image, · 629 unmodified lines
630	* @image: EFI loaded image protocol	630	* @image: EFI loaded image protocol
631	* @load_addr: pointer to loaded initrd	631	* @load_addr: pointer to loaded initrd
632	* @load_size: size of loaded initrd	632	* @load_size: size of loaded initrd
633	* @soft_limit: preferred size of allocated memory for loading the initrd	633	* @soft_limit: preferred address for loading the initrd
634	* @hard_limit: minimum size of allocated memory	634	* @hard_limit: upper limit address for loading the initrd
635	*	635	*
636	* Return: status code	636	* Return: status code
637	*/	637	*/

drivers/firmware/efi/mokvar-table.c+4−1

@@ -180,7 +180,10 @@ void __init efi_mokvar_table_init(void) · 179 unmodified lines
180	pr_err("EFI MOKvar config table is not valid\n");	180	pr_err("EFI MOKvar config table is not valid\n");
181	return;	181	return;
182	}	182	}
183	efi_mem_reserve(efi.mokvar_table, map_size_needed);	183
		184	if (md.type == EFI_BOOT_SERVICES_DATA)
		185	efi_mem_reserve(efi.mokvar_table, map_size_needed);
		186
184	efi_mokvar_table_size = map_size_needed;	187	efi_mokvar_table_size = map_size_needed;
185	}	188	}
186		189

drivers/firmware/efi/tpm.c+5−3

 	tbl_size = sizeof(*log_tbl) + log_tbl->size;
 	memblock_reserve(efi.tpm_log, tbl_size);
-	if (efi.tpm_final_log == EFI_INVALID_TABLE_ADDR ||
+	if (efi.tpm_final_log == EFI_INVALID_TABLE_ADDR) {
-	    log_tbl->version != EFI_TCG2_EVENT_LOG_FORMAT_TCG_2) {
+		pr_info("TPM Final Events table not present\n");
-		pr_warn(FW_BUG "TPM Final Events table missing or invalid\n");
+		goto out;
+	} else if (log_tbl->version != EFI_TCG2_EVENT_LOG_FORMAT_TCG_2) {
+		pr_warn(FW_BUG "TPM Final Events table invalid\n");
 		goto out;
 	}

drivers/gpu/drm/amd/amdgpu/amdgpu.h+7−0

@@ -619,6 +619,13 @@ struct amdgpu_video_codec_info { · 618 unmodified lines
619	u32 max_level;	619	u32 max_level;
620	};	620	};
621		621
		622	#define codec_info_build(type, width, height, level) \
		623	.codec_type = type,\
		624	.max_width = width,\
		625	.max_height = height,\
		626	.max_pixels_per_frame = height * width,\
		627	.max_level = level,
		628
622	struct amdgpu_video_codecs {	629	struct amdgpu_video_codecs {
623	const u32 codec_count;	630	const u32 codec_count;
624	const struct amdgpu_video_codec_info *codec_array;	631	const struct amdgpu_video_codec_info *codec_array;

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c+2−1

 #include <linux/slab.h>
 #include <linux/power_supply.h>
 #include <linux/pm_runtime.h>
+#include <linux/suspend.h>
 #include <acpi/video.h>
 #include <acpi/actbl.h>
 #if defined(CONFIG_AMD_PMC) || defined(CONFIG_AMD_PMC_MODULE)
 	if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) {
 		if (adev->flags & AMD_IS_APU)
-			return true;
+			return pm_suspend_target_state == PM_SUSPEND_TO_IDLE;
 	}
 #endif
 	return false;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+2−6

 	r = amdgpu_device_get_job_timeout_settings(adev);
 	if (r) {
 		dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
-		goto failed_unmap;
+		return r;
 	}
 	/* early init functions */
 	r = amdgpu_device_ip_early_init(adev);
 	if (r)
-		goto failed_unmap;
+		return r;
 	/* doorbell bar mapping and doorbell index init*/
 	amdgpu_device_doorbell_init(adev);
 failed:
 	amdgpu_vf_error_trans_all(adev);
-failed_unmap:
-	iounmap(adev->rmmio);
-	adev->rmmio = NULL;
 	return r;
 }

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+4−0

 	/* Van Gogh */
 	{0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
+	/* Yellow Carp */
+	{0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
+	{0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
 	/* Navy_Flounder */
 	{0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
 	{0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c+9−0

@@ -255,6 +255,15 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str · 254 unmodified lines
255	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)	255	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
256	return -EPERM;	256	return -EPERM;
257		257
		258	/* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings
		259	* for debugger access to invisible VRAM. Should have used MAP_SHARED
		260	* instead. Clearing VM_MAYWRITE prevents the mapping from ever
		261	* becoming writable and makes is_cow_mapping(vm_flags) false.
		262	*/
		263	if (is_cow_mapping(vma->vm_flags) &&
		264	!(vma->vm_flags & (VM_READ \| VM_WRITE \| VM_EXEC)))
		265	vma->vm_flags &= ~VM_MAYWRITE;
		266
258	return drm_gem_ttm_mmap(obj, vma);	267	return drm_gem_ttm_mmap(obj, vma);
259	}	268	}
260		269

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c+3−0

 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
 };
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)

drivers/gpu/drm/amd/amdgpu/nv.c+50−198

@@ -64,32 +64,13 @@ · 63 unmodified lines
64	#include "smuio_v11_0.h"	64	#include "smuio_v11_0.h"
65	#include "smuio_v11_0_6.h"	65	#include "smuio_v11_0_6.h"
66		66
67	#define codec_info_build(type, width, height, level) \
68	.codec_type = type,\
69	.max_width = width,\
70	.max_height = height,\
71	.max_pixels_per_frame = height * width,\
72	.max_level = level,
73
74	static const struct amd_ip_funcs nv_common_ip_funcs;	67	static const struct amd_ip_funcs nv_common_ip_funcs;
75		68
76	/* Navi */	69	/* Navi */
77	static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =	70	static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
78	{	71	{
79	{	72	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
80	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,	73	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
81	.max_width = 4096,
82	.max_height = 2304,
83	.max_pixels_per_frame = 4096 * 2304,
84	.max_level = 0,
85	},
86	{
87	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
88	.max_width = 4096,
89	.max_height = 2304,
90	.max_pixels_per_frame = 4096 * 2304,
91	.max_level = 0,
92	},
93	};	74	};
94		75
95	static const struct amdgpu_video_codecs nv_video_codecs_encode =	76	static const struct amdgpu_video_codecs nv_video_codecs_encode =
@@ -101,55 +82,13 @@ static const struct amdgpu_video_codecs nv_video_codecs_encode = · 5 unmodified lines
101	/* Navi1x */	82	/* Navi1x */
102	static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =	83	static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
103	{	84	{
104	{	85	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
105	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,	86	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
106	.max_width = 4096,	87	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
107	.max_height = 4096,	88	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
108	.max_pixels_per_frame = 4096 * 4096,	89	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
109	.max_level = 3,	90	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
110	},	91	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
111	{
112	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
113	.max_width = 4096,
114	.max_height = 4096,
115	.max_pixels_per_frame = 4096 * 4096,
116	.max_level = 5,
117	},
118	{
119	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
120	.max_width = 4096,
121	.max_height = 4096,
122	.max_pixels_per_frame = 4096 * 4096,
123	.max_level = 52,
124	},
125	{
126	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
127	.max_width = 4096,
128	.max_height = 4096,
129	.max_pixels_per_frame = 4096 * 4096,
130	.max_level = 4,
131	},
132	{
133	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
134	.max_width = 8192,
135	.max_height = 4352,
136	.max_pixels_per_frame = 8192 * 4352,
137	.max_level = 186,
138	},
139	{
140	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
141	.max_width = 4096,
142	.max_height = 4096,
143	.max_pixels_per_frame = 4096 * 4096,
144	.max_level = 0,
145	},
146	{
147	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
148	.max_width = 8192,
149	.max_height = 4352,
150	.max_pixels_per_frame = 8192 * 4352,
151	.max_level = 0,
152	},
153	};	92	};
154		93
155	static const struct amdgpu_video_codecs nv_video_codecs_decode =	94	static const struct amdgpu_video_codecs nv_video_codecs_decode =
@@ -161,62 +100,14 @@ static const struct amdgpu_video_codecs nv_video_codecs_decode = · 5 unmodified lines
161	/* Sienna Cichlid */	100	/* Sienna Cichlid */
162	static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =	101	static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
163	{	102	{
164	{	103	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
165	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,	104	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
166	.max_width = 4096,	105	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
167	.max_height = 4096,	106	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
168	.max_pixels_per_frame = 4096 * 4096,	107	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
169	.max_level = 3,	108	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
170	},	109	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
171	{	110	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
172	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
173	.max_width = 4096,
174	.max_height = 4096,
175	.max_pixels_per_frame = 4096 * 4096,
176	.max_level = 5,
177	},
178	{
179	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
180	.max_width = 4096,
181	.max_height = 4096,
182	.max_pixels_per_frame = 4096 * 4096,
183	.max_level = 52,
184	},
185	{
186	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
187	.max_width = 4096,
188	.max_height = 4096,
189	.max_pixels_per_frame = 4096 * 4096,
190	.max_level = 4,
191	},
192	{
193	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
194	.max_width = 8192,
195	.max_height = 4352,
196	.max_pixels_per_frame = 8192 * 4352,
197	.max_level = 186,
198	},
199	{
200	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
201	.max_width = 4096,
202	.max_height = 4096,
203	.max_pixels_per_frame = 4096 * 4096,
204	.max_level = 0,
205	},
206	{
207	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
208	.max_width = 8192,
209	.max_height = 4352,
210	.max_pixels_per_frame = 8192 * 4352,
211	.max_level = 0,
212	},
213	{
214	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
215	.max_width = 8192,
216	.max_height = 4352,
217	.max_pixels_per_frame = 8192 * 4352,
218	.max_level = 0,
219	},
220	};	111	};
221		112
222	static const struct amdgpu_video_codecs sc_video_codecs_decode =	113	static const struct amdgpu_video_codecs sc_video_codecs_decode =
@@ -228,80 +119,20 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode = · 5 unmodified lines
228	/* SRIOV Sienna Cichlid, not const since data is controlled by host */	119	/* SRIOV Sienna Cichlid, not const since data is controlled by host */
229	static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =	120	static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
230	{	121	{
231	{	122	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
232	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,	123	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
233	.max_width = 4096,
234	.max_height = 2304,
235	.max_pixels_per_frame = 4096 * 2304,
236	.max_level = 0,
237	},
238	{
239	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
240	.max_width = 4096,
241	.max_height = 2304,
242	.max_pixels_per_frame = 4096 * 2304,
243	.max_level = 0,
244	},
245	};	124	};
246		125
247	static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =	126	static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
248	{	127	{
249	{	128	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
250	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,	129	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
251	.max_width = 4096,	130	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
252	.max_height = 4096,	131	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
253	.max_pixels_per_frame = 4096 * 4096,	132	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
254	.max_level = 3,	133	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
255	},	134	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
256	{	135	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
257	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
258	.max_width = 4096,
259	.max_height = 4096,
260	.max_pixels_per_frame = 4096 * 4096,
261	.max_level = 5,
262	},
263	{
264	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
265	.max_width = 4096,
266	.max_height = 4096,
267	.max_pixels_per_frame = 4096 * 4096,
268	.max_level = 52,
269	},
270	{
271	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
272	.max_width = 4096,
273	.max_height = 4096,
274	.max_pixels_per_frame = 4096 * 4096,
275	.max_level = 4,
276	},
277	{
278	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
279	.max_width = 8192,
280	.max_height = 4352,
281	.max_pixels_per_frame = 8192 * 4352,
282	.max_level = 186,
283	},
284	{
285	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
286	.max_width = 4096,
287	.max_height = 4096,
288	.max_pixels_per_frame = 4096 * 4096,
289	.max_level = 0,
290	},
291	{
292	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
293	.max_width = 8192,
294	.max_height = 4352,
295	.max_pixels_per_frame = 8192 * 4352,
296	.max_level = 0,
297	},
298	{
299	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
300	.max_width = 8192,
301	.max_height = 4352,
302	.max_pixels_per_frame = 8192 * 4352,
303	.max_level = 0,
304	},
305	};	136	};
306		137
307	static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =	138	static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
@@ -333,6 +164,19 @@ static const struct amdgpu_video_codecs bg_video_codecs_encode = { · 25 unmodified lines
333	.codec_array = NULL,	164	.codec_array = NULL,
334	};	165	};
335		166
		167	/* Yellow Carp*/
		168	static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
		169	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
		170	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
		171	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
		172	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
		173	};
		174
		175	static const struct amdgpu_video_codecs yc_video_codecs_decode = {
		176	.codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
		177	.codec_array = yc_video_codecs_decode_array,
		178	};
		179
336	static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,	180	static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
337	const struct amdgpu_video_codecs **codecs)	181	const struct amdgpu_video_codecs **codecs)
338	{	182	{
@@ -353,12 +197,17 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, · 14 unmodified lines
353	case CHIP_NAVY_FLOUNDER:	197	case CHIP_NAVY_FLOUNDER:
354	case CHIP_DIMGREY_CAVEFISH:	198	case CHIP_DIMGREY_CAVEFISH:
355	case CHIP_VANGOGH:	199	case CHIP_VANGOGH:
356	case CHIP_YELLOW_CARP:
357	if (encode)	200	if (encode)
358	*codecs = &nv_video_codecs_encode;	201	*codecs = &nv_video_codecs_encode;
359	else	202	else
360	*codecs = &sc_video_codecs_decode;	203	*codecs = &sc_video_codecs_decode;
361	return 0;	204	return 0;
		205	case CHIP_YELLOW_CARP:
		206	if (encode)
		207	*codecs = &nv_video_codecs_encode;
		208	else
		209	*codecs = &yc_video_codecs_decode;
		210	return 0;
362	case CHIP_BEIGE_GOBY:	211	case CHIP_BEIGE_GOBY:
363	if (encode)	212	if (encode)
364	*codecs = &bg_video_codecs_encode;	213	*codecs = &bg_video_codecs_encode;
@@ -1387,7 +1236,10 @@ static int nv_common_early_init(void *handle) · 1022 unmodified lines
1387	AMD_PG_SUPPORT_VCN \|	1236	AMD_PG_SUPPORT_VCN \|
1388	AMD_PG_SUPPORT_VCN_DPG \|	1237	AMD_PG_SUPPORT_VCN_DPG \|
1389	AMD_PG_SUPPORT_JPEG;	1238	AMD_PG_SUPPORT_JPEG;
1390	adev->external_rev_id = adev->rev_id + 0x01;	1239	if (adev->pdev->device == 0x1681)
		1240	adev->external_rev_id = adev->rev_id + 0x19;
		1241	else
		1242	adev->external_rev_id = adev->rev_id + 0x01;
1391	break;	1243	break;
1392	default:	1244	default:
1393	/* FIXME: not supported yet */	1245	/* FIXME: not supported yet */

drivers/gpu/drm/amd/amdgpu/psp_v12_0.c+3−4

 	err = psp_init_asd_microcode(psp, chip_name);
 	if (err)
-		goto out;
+		return err;
 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 	err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 	} else {
 		err = amdgpu_ucode_validate(adev->psp.ta_fw);
 		if (err)
-			goto out2;
+			goto out;
 		ta_hdr = (const struct ta_firmware_header_v1_0 *)
 				 adev->psp.ta_fw->data;
 	return 0;
-out2:
+out:
 	release_firmware(adev->psp.ta_fw);
 	adev->psp.ta_fw = NULL;
-out:
 	if (err) {
 		dev_err(adev->dev,
 			"psp v12.0: Failed to load firmware \"%s\"\n",

drivers/gpu/drm/amd/amdgpu/soc15.c+22−154

@@ -88,20 +88,8 @@ · 87 unmodified lines
88	/* Vega, Raven, Arcturus */	88	/* Vega, Raven, Arcturus */
89	static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =	89	static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
90	{	90	{
91	{	91	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
92	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,	92	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
93	.max_width = 4096,
94	.max_height = 2304,
95	.max_pixels_per_frame = 4096 * 2304,
96	.max_level = 0,
97	},
98	{
99	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
100	.max_width = 4096,
101	.max_height = 2304,
102	.max_pixels_per_frame = 4096 * 2304,
103	.max_level = 0,
104	},
105	};	93	};
106		94
107	static const struct amdgpu_video_codecs vega_video_codecs_encode =	95	static const struct amdgpu_video_codecs vega_video_codecs_encode =
@@ -113,48 +101,12 @@ static const struct amdgpu_video_codecs vega_video_codecs_encode = · 5 unmodified lines
113	/* Vega */	101	/* Vega */
114	static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =	102	static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
115	{	103	{
116	{	104	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
117	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,	105	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
118	.max_width = 4096,	106	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
119	.max_height = 4096,	107	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
120	.max_pixels_per_frame = 4096 * 4096,	108	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
121	.max_level = 3,	109	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
122	},
123	{
124	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
125	.max_width = 4096,
126	.max_height = 4096,
127	.max_pixels_per_frame = 4096 * 4096,
128	.max_level = 5,
129	},
130	{
131	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
132	.max_width = 4096,
133	.max_height = 4096,
134	.max_pixels_per_frame = 4096 * 4096,
135	.max_level = 52,
136	},
137	{
138	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
139	.max_width = 4096,
140	.max_height = 4096,
141	.max_pixels_per_frame = 4096 * 4096,
142	.max_level = 4,
143	},
144	{
145	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
146	.max_width = 4096,
147	.max_height = 4096,
148	.max_pixels_per_frame = 4096 * 4096,
149	.max_level = 186,
150	},
151	{
152	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
153	.max_width = 4096,
154	.max_height = 4096,
155	.max_pixels_per_frame = 4096 * 4096,
156	.max_level = 0,
157	},
158	};	110	};
159		111
160	static const struct amdgpu_video_codecs vega_video_codecs_decode =	112	static const struct amdgpu_video_codecs vega_video_codecs_decode =
@@ -166,55 +118,13 @@ static const struct amdgpu_video_codecs vega_video_codecs_decode = · 5 unmodified lines
166	/* Raven */	118	/* Raven */
167	static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =	119	static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
168	{	120	{
169	{	121	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
170	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,	122	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
171	.max_width = 4096,	123	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
172	.max_height = 4096,	124	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
173	.max_pixels_per_frame = 4096 * 4096,	125	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
174	.max_level = 3,	126	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
175	},	127	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
176	{
177	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
178	.max_width = 4096,
179	.max_height = 4096,
180	.max_pixels_per_frame = 4096 * 4096,
181	.max_level = 5,
182	},
183	{
184	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
185	.max_width = 4096,
186	.max_height = 4096,
187	.max_pixels_per_frame = 4096 * 4096,
188	.max_level = 52,
189	},
190	{
191	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
192	.max_width = 4096,
193	.max_height = 4096,
194	.max_pixels_per_frame = 4096 * 4096,
195	.max_level = 4,
196	},
197	{
198	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
199	.max_width = 4096,
200	.max_height = 4096,
201	.max_pixels_per_frame = 4096 * 4096,
202	.max_level = 186,
203	},
204	{
205	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
206	.max_width = 4096,
207	.max_height = 4096,
208	.max_pixels_per_frame = 4096 * 4096,
209	.max_level = 0,
210	},
211	{
212	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
213	.max_width = 4096,
214	.max_height = 4096,
215	.max_pixels_per_frame = 4096 * 4096,
216	.max_level = 0,
217	},
218	};	128	};
219		129
220	static const struct amdgpu_video_codecs rv_video_codecs_decode =	130	static const struct amdgpu_video_codecs rv_video_codecs_decode =
@@ -226,55 +136,13 @@ static const struct amdgpu_video_codecs rv_video_codecs_decode = · 5 unmodified lines
226	/* Renoir, Arcturus */	136	/* Renoir, Arcturus */
227	static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =	137	static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
228	{	138	{
229	{	139	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
230	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,	140	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
231	.max_width = 4096,	141	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
232	.max_height = 4096,	142	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
233	.max_pixels_per_frame = 4096 * 4096,	143	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
234	.max_level = 3,	144	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
235	},	145	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
236	{
237	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
238	.max_width = 4096,
239	.max_height = 4096,
240	.max_pixels_per_frame = 4096 * 4096,
241	.max_level = 5,
242	},
243	{
244	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
245	.max_width = 4096,
246	.max_height = 4096,
247	.max_pixels_per_frame = 4096 * 4096,
248	.max_level = 52,
249	},
250	{
251	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
252	.max_width = 4096,
253	.max_height = 4096,
254	.max_pixels_per_frame = 4096 * 4096,
255	.max_level = 4,
256	},
257	{
258	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
259	.max_width = 8192,
260	.max_height = 4352,
261	.max_pixels_per_frame = 4096 * 4096,
262	.max_level = 186,
263	},
264	{
265	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
266	.max_width = 4096,
267	.max_height = 4096,
268	.max_pixels_per_frame = 4096 * 4096,
269	.max_level = 0,
270	},
271	{
272	.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
273	.max_width = 8192,
274	.max_height = 4352,
275	.max_pixels_per_frame = 4096 * 4096,
276	.max_level = 0,
277	},
278	};	146	};
279		147
280	static const struct amdgpu_video_codecs rn_video_codecs_decode =	148	static const struct amdgpu_video_codecs rn_video_codecs_decode =

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+2−2

@@ -2429,9 +2429,9 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) · 2428 unmodified lines
2429	max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll;	2429	max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll;
2430	min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;	2430	min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;
2431		2431
2432	if (caps->ext_caps->bits.oled == 1 \|\|	2432	if (caps->ext_caps->bits.oled == 1 /*\|\|
2433	caps->ext_caps->bits.sdr_aux_backlight_control == 1 \|\|	2433	caps->ext_caps->bits.sdr_aux_backlight_control == 1 \|\|
2434	caps->ext_caps->bits.hdr_aux_backlight_control == 1)	2434	caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
2435	caps->aux_support = true;	2435	caps->aux_support = true;
2436		2436
2437	if (amdgpu_backlight == 0)	2437	if (amdgpu_backlight == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c+1−1

@@ -197,7 +197,7 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct · 196 unmodified lines
197		197
198	REG_UPDATE(DENTIST_DISPCLK_CNTL,	198	REG_UPDATE(DENTIST_DISPCLK_CNTL,
199	DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);	199	DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
200	// REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100);	200	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 1000);
201	REG_UPDATE(DENTIST_DISPCLK_CNTL,	201	REG_UPDATE(DENTIST_DISPCLK_CNTL,
202	DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);	202	DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
203	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);	203	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c+4−0

 			&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
 			&num_levels);
+	/* SOCCLK */
+	dcn3_init_single_clock(clk_mgr, PPCLK_SOCCLK,
+					&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
+					&num_levels);
 	// DPREFCLK ???
 	/* DISPCLK */

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c+50−9

 #include "dc_dmub_srv.h"
+#include "yellow_carp_offset.h"
+#define regCLK1_CLK_PLL_REQ			0x0237
+#define regCLK1_CLK_PLL_REQ_BASE_IDX		0
+#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT	0x0
+#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT	0xc
+#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT	0x10
+#define CLK1_CLK_PLL_REQ__FbMult_int_MASK	0x000001FFL
+#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK	0x0000F000L
+#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK	0xFFFF0000L
+#define REG(reg_name) \
+	(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
 #define TO_CLK_MGR_DCN31(clk_mgr)\
 	container_of(clk_mgr, struct clk_mgr_dcn31, base)
 	 * also if safe to lower is false, we just go in the higher state
 	 */
 	if (safe_to_lower) {
-		if (new_clocks->z9_support == DCN_Z9_SUPPORT_ALLOW &&
+		if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_ALLOW &&
-				new_clocks->z9_support != clk_mgr_base->clks.z9_support) {
+				new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
 			dcn31_smu_set_Z9_support(clk_mgr, true);
-			clk_mgr_base->clks.z9_support = new_clocks->z9_support;
+			clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
 		}
 		if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
 			}
 		}
 	} else {
-		if (new_clocks->z9_support == DCN_Z9_SUPPORT_DISALLOW &&
+		if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
-				new_clocks->z9_support != clk_mgr_base->clks.z9_support) {
+				new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
 			dcn31_smu_set_Z9_support(clk_mgr, false);
-			clk_mgr_base->clks.z9_support = new_clocks->z9_support;
+			clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
 		}
 		if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
 {
-	return 0;
+	/* get FbMult value */
+	struct fixed31_32 pll_req;
+	unsigned int fbmult_frac_val = 0;
+	unsigned int fbmult_int_val = 0;
+	/*
+	 * Register value of fbmult is in 8.16 format, we are converting to 31.32
+	 * to leverage the fix point operations available in driver
+	 */
+	REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
+	REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
+	pll_req = dc_fixpt_from_int(fbmult_int_val);
+	/*
+	 * since fractional part is only 16 bit in register definition but is 32 bit
+	 * in our fix point definiton, need to shift left by 16 to obtain correct value
+	 */
+	pll_req.value |= fbmult_frac_val << 16;
+	/* multiply by REFCLK period */
+	pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
+	/* integer part is now VCO frequency in kHz */
+	return dc_fixpt_floor(pll_req);
 }
 static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 	clk_mgr->clks.p_state_change_support = true;
 	clk_mgr->clks.prev_p_state_change_support = true;
 	clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
-	clk_mgr->clks.z9_support = DCN_Z9_SUPPORT_UNKNOWN;
+	clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
 }
 static bool dcn31_are_clock_states_equal(struct dc_clocks *a,
 		return false;
 	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
 		return false;
-	else if (a->z9_support != b->z9_support)
+	else if (a->zstate_support != b->zstate_support)
 		return false;
 	else if (a->dtbclk_en != b->dtbclk_en)
 		return false;
 	clk_mgr->base.dprefclk_ss_percentage = 0;
 	clk_mgr->base.dprefclk_ss_divider = 1000;
 	clk_mgr->base.ss_on_dprefclk = false;
+	clk_mgr->base.dfs_ref_freq_khz = 48000;
 	clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(
 				clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h+0−54

@@ -27,60 +27,6 @@ · 26 unmodified lines
27	#define __DCN31_CLK_MGR_H__	27	#define __DCN31_CLK_MGR_H__
28	#include "clk_mgr_internal.h"	28	#include "clk_mgr_internal.h"
29		29
30	//CLK1_CLK_PLL_REQ
31	#ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT
32	#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
33	#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
34	#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
35	#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
36	#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
37	#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
38	//CLK1_CLK0_DFS_CNTL
39	#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT 0x0
40	#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK 0x0000007FL
41	/DPREF clock related/
42	#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
43	#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
44	#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
45	#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
46	#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
47	#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
48	#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
49	#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
50
51	//CLK3_0_CLK3_CLK_PLL_REQ
52	#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
53	#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
54	#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
55	#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
56	#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
57	#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
58
59	#define mmCLK0_CLK3_DFS_CNTL 0x16C60
60	#define mmCLK00_CLK0_CLK3_DFS_CNTL 0x16C60
61	#define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E60
62	#define mmCLK02_CLK0_CLK3_DFS_CNTL 0x17060
63	#define mmCLK03_CLK0_CLK3_DFS_CNTL 0x17260
64
65	#define mmCLK0_CLK_PLL_REQ 0x16C10
66	#define mmCLK00_CLK0_CLK_PLL_REQ 0x16C10
67	#define mmCLK01_CLK0_CLK_PLL_REQ 0x16E10
68	#define mmCLK02_CLK0_CLK_PLL_REQ 0x17010
69	#define mmCLK03_CLK0_CLK_PLL_REQ 0x17210
70
71	#define mmCLK1_CLK_PLL_REQ 0x1B00D
72	#define mmCLK10_CLK1_CLK_PLL_REQ 0x1B00D
73	#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D
74	#define mmCLK12_CLK1_CLK_PLL_REQ 0x1B40D
75	#define mmCLK13_CLK1_CLK_PLL_REQ 0x1B60D
76
77	#define mmCLK2_CLK_PLL_REQ 0x17E0D
78
79	/AMCLK/
80	#define mmCLK11_CLK1_CLK0_DFS_CNTL 0x1B23F
81	#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D
82	#endif
83
84	struct dcn31_watermarks;	30	struct dcn31_watermarks;
85		31
86	struct dcn31_smu_watermark_set {	32	struct dcn31_smu_watermark_set {

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+6−6

 					 */
 					panel_mode = DP_PANEL_MODE_DEFAULT;
 				}
-			} else
+			}
-				panel_mode = DP_PANEL_MODE_DEFAULT;
 		}
 #endif
 		}
 	}
-	if (link->dpcd_caps.panel_mode_edp) {
+	if (link->dpcd_caps.panel_mode_edp &&
+		(link->connector_signal == SIGNAL_TYPE_EDP ||
+		 (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
+		  link->is_internal_display))) {
 		return DP_PANEL_MODE_EDP;
 	}
 {
 	uint32_t default_backlight;
-	if (link &&
+	if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {
-		(link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
-		link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
 		if (!dc_link_read_default_bl_aux(link, &default_backlight))
 			default_backlight = 150000;
 		// if < 5 nits or > 5000, it might be wrong readback

drivers/gpu/drm/amd/display/dc/core/dc_resource.c+1−1

@@ -1062,7 +1062,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 1061 unmodified lines
1062	* so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3	1062	* so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3
1063	* did not show such problems, so this seems to be the exception.	1063	* did not show such problems, so this seems to be the exception.
1064	*/	1064	*/
1065	if (plane_state->ctx->dce_version != DCE_VERSION_11_0)	1065	if (plane_state->ctx->dce_version > DCE_VERSION_11_0)
1066	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;	1066	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
1067	else	1067	else
1068	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;	1068	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;

drivers/gpu/drm/amd/display/dc/dc.h+5−5

@@ -354,10 +354,10 @@ enum dcn_pwr_state { · 353 unmodified lines
354	};	354	};
355		355
356	#if defined(CONFIG_DRM_AMD_DC_DCN)	356	#if defined(CONFIG_DRM_AMD_DC_DCN)
357	enum dcn_z9_support_state {	357	enum dcn_zstate_support_state {
358	DCN_Z9_SUPPORT_UNKNOWN,	358	DCN_ZSTATE_SUPPORT_UNKNOWN,
359	DCN_Z9_SUPPORT_ALLOW,	359	DCN_ZSTATE_SUPPORT_ALLOW,
360	DCN_Z9_SUPPORT_DISALLOW,	360	DCN_ZSTATE_SUPPORT_DISALLOW,
361	};	361	};
362	#endif	362	#endif
363	/*	363	/*
@@ -378,7 +378,7 @@ struct dc_clocks { · 14 unmodified lines
378	int dramclk_khz;	378	int dramclk_khz;
379	bool p_state_change_support;	379	bool p_state_change_support;
380	#if defined(CONFIG_DRM_AMD_DC_DCN)	380	#if defined(CONFIG_DRM_AMD_DC_DCN)
381	enum dcn_z9_support_state z9_support;	381	enum dcn_zstate_support_state zstate_support;
382	bool dtbclk_en;	382	bool dtbclk_en;
383	#endif	383	#endif
384	enum dcn_pwr_state pwr_state;	384	enum dcn_pwr_state pwr_state;

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h+3−1

 	uint32_t ODM_MEM_PWR_CTRL3;
 	uint32_t DMU_MEM_PWR_CNTL;
 	uint32_t MMHUBBUB_MEM_PWR_CNTL;
+	uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
 };
  /* set field name */
 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
 	type DOMAIN_POWER_FORCEON;\
 	type DOMAIN_POWER_GATE;\
 	type DOMAIN_PGFSM_PWR_STATUS;\
-	type HPO_HDMISTREAMCLK_G_GATE_DIS;
+	type HPO_HDMISTREAMCLK_G_GATE_DIS;\
+	type DISABLE_HOSTVM_FORCE_ALLOW_PSTATE;
 struct dce_hwseq_shift {
 	HWSEQ_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c+6−1

 	const struct line_buffer_params *lb_params,
 	enum lb_memory_config mem_size_config)
 {
+	uint32_t max_partitions = 63; /* Currently hardcoded on all ASICs before DCN 3.2 */
 	/* LB */
 	if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
 		/* DSCL caps: pixel data processed in fixed format */
 			LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
 	}
+	if (dpp->base.caps->max_lb_partitions == 31)
+		max_partitions = 31;
 	REG_SET_2(LB_MEMORY_CTRL, 0,
 		MEMORY_CONFIG, mem_size_config,
-		LB_MAX_PARTITIONS, 63);
+		LB_MAX_PARTITIONS, max_partitions);
 }
 static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c+36−14

 				- timing->v_border_bottom;
 		pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
 		pipes[pipe_cnt].pipe.dest.vtotal = v_total;
-		pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
+		pipes[pipe_cnt].pipe.dest.hactive =
-		pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
+			timing->h_addressable + timing->h_border_left + timing->h_border_right;
+		pipes[pipe_cnt].pipe.dest.vactive =
+			timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
 		pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
 		pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
 		if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
 	return false;
 }
+static enum dcn_zstate_support_state  decide_zstate_support(struct dc *dc, struct dc_state *context)
+{
+	int plane_count;
+	int i;
+	plane_count = 0;
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		if (context->res_ctx.pipe_ctx[i].plane_state)
+			plane_count++;
+	}
+	/*
+	 * Zstate is allowed in following scenarios:
+	 * 	1. Single eDP with PSR enabled
+	 * 	2. 0 planes (No memory requests)
+	 * 	3. Single eDP without PSR but > 5ms stutter period
+	 */
+	if (plane_count == 0)
+		return DCN_ZSTATE_SUPPORT_ALLOW;
+	else if (context->stream_count == 1 &&  context->streams[0]->signal == SIGNAL_TYPE_EDP) {
+		struct dc_link *link = context->streams[0]->sink->link;
+		if ((link->link_index == 0 && link->psr_settings.psr_feature_enabled)
+				|| context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
+			return DCN_ZSTATE_SUPPORT_ALLOW;
+		else
+			return DCN_ZSTATE_SUPPORT_DISALLOW;
+	} else
+		return DCN_ZSTATE_SUPPORT_DISALLOW;
+}
 void dcn20_calculate_dlg_params(
 		struct dc *dc, struct dc_state *context,
 		display_e2e_pipe_params_st *pipes,
 		int vlevel)
 {
 	int i, pipe_idx;
-	int plane_count;
 	/* Writeback MCIF_WB arbitration parameters */
 	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
 							!= dm_dram_clock_change_unsupported;
 	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
-	context->bw_ctx.bw.dcn.clk.z9_support = (context->bw_ctx.dml.vba.StutterPeriod > 5000.0) ?
+	context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);
-			DCN_Z9_SUPPORT_ALLOW : DCN_Z9_SUPPORT_DISALLOW;
-	plane_count = 0;
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		if (context->res_ctx.pipe_ctx[i].plane_state)
-			plane_count++;
-	}
-	if (plane_count == 0)
-		context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW;
 	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c+1−0

@@ -109,6 +109,7 @@ struct _vcs_dpi_ip_params_st dcn2_1_ip = { · 108 unmodified lines
109	.max_page_table_levels = 4,	109	.max_page_table_levels = 4,
110	.pte_chunk_size_kbytes = 2,	110	.pte_chunk_size_kbytes = 2,
111	.meta_chunk_size_kbytes = 2,	111	.meta_chunk_size_kbytes = 2,
		112	.min_meta_chunk_size_bytes = 256,
112	.writeback_chunk_size_kbytes = 2,	113	.writeback_chunk_size_kbytes = 2,
113	.line_buffer_size_bits = 789504,	114	.line_buffer_size_bits = 789504,
114	.is_line_buffer_bpp_fixed = 0,	115	.is_line_buffer_bpp_fixed = 0,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c+0−16

@@ -383,13 +383,6 @@ bool dpp3_get_optimal_number_of_taps( · 382 unmodified lines
383	int min_taps_y, min_taps_c;	383	int min_taps_y, min_taps_c;
384	enum lb_memory_config lb_config;	384	enum lb_memory_config lb_config;
385		385
386	/* Some ASICs does not support FP16 scaling, so we reject modes require this*/
387	if (scl_data->viewport.width != scl_data->h_active &&
388	scl_data->viewport.height != scl_data->v_active &&
389	dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
390	scl_data->format == PIXEL_FORMAT_FP16)
391	return false;
392
393	if (scl_data->viewport.width > scl_data->h_active &&	386	if (scl_data->viewport.width > scl_data->h_active &&
394	dpp->ctx->dc->debug.max_downscale_src_width != 0 &&	387	dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
395	scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)	388	scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
@@ -1440,15 +1433,6 @@ bool dpp3_construct( · 1044 unmodified lines
1440	dpp->tf_shift = tf_shift;	1433	dpp->tf_shift = tf_shift;
1441	dpp->tf_mask = tf_mask;	1434	dpp->tf_mask = tf_mask;
1442		1435
1443	dpp->lb_pixel_depth_supported =
1444	LB_PIXEL_DEPTH_18BPP \|
1445	LB_PIXEL_DEPTH_24BPP \|
1446	LB_PIXEL_DEPTH_30BPP \|
1447	LB_PIXEL_DEPTH_36BPP;
1448
1449	dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
1450	dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /0x1404/
1451
1452	return true;	1436	return true;
1453	}	1437	}
1454		1438

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h+1−2

 	SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \
 	SRI(CURSOR_CONTROL, CURSOR0_, id),\
 	SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
+	SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \
 	SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
 #define DPP_REG_LIST_DCN30(id)\
 	SRI(CM_SHAPER_LUT_DATA, CM, id),\
 	SRI(CM_MEM_PWR_CTRL2, CM, id), \
 	SRI(CM_MEM_PWR_STATUS2, CM, id), \
-	SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \
-	SRI(DSCL_MEM_PWR_CTRL, DSCL, id), \
 	SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM, id),\
 	SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM, id),\
 	SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM, id),\

drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c+10−3

 			dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
 			dcn3_02_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
 			dcn3_02_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
-			dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz;
+			/* Populate from bw_params for DTBCLK, SOCCLK */
+			if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
+				dcn3_02_soc.clock_limits[i].dtbclk_mhz  = dcn3_02_soc.clock_limits[i-1].dtbclk_mhz;
+			else
+				dcn3_02_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
+			if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
+				dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz;
+			else
+				dcn3_02_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
 			/* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */
-			/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
+			/* FCLK, PHYCLK_D18, DSCCLK */
 			dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz;
-			dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[0].socclk_mhz;
 			dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz;
 		}
 		/* re-init DML with updated bb */

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c+10−3

 			dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
 			dcn3_03_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
 			dcn3_03_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
-			dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz;
+			/* Populate from bw_params for DTBCLK, SOCCLK */
+			if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
+				dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[i-1].dtbclk_mhz;
+			else
+				dcn3_03_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
+			if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
+				dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[i-1].socclk_mhz;
+			else
+				dcn3_03_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
 			/* These clocks cannot come from bw_params, always fill from dcn3_03_soc[1] */
-			/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
+			/* FCLK, PHYCLK_D18, DSCCLK */
 			dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz;
-			dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[0].socclk_mhz;
 			dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz;
 		}
 		/* re-init DML with updated bb */

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c+18−0

@@ -47,6 +47,7 @@ · 46 unmodified lines
47	#include "dce/dmub_outbox.h"	47	#include "dce/dmub_outbox.h"
48	#include "dc_link_dp.h"	48	#include "dc_link_dp.h"
49	#include "inc/link_dpcd.h"	49	#include "inc/link_dpcd.h"
		50	#include "dcn10/dcn10_hw_sequencer.h"
50		51
51	#define DC_LOGGER_INIT(logger)	52	#define DC_LOGGER_INIT(logger)
52		53
@@ -594,3 +595,20 @@ bool dcn31_is_abm_supported(struct dc *dc, · 541 unmodified lines
594	}	595	}
595	return false;	596	return false;
596	}	597	}
		598
		599	static void apply_riommu_invalidation_wa(struct dc *dc)
		600	{
		601	struct dce_hwseq *hws = dc->hwseq;
		602
		603	if (!hws->wa.early_riommu_invalidation)
		604	return;
		605
		606	REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, 0);
		607	}
		608
		609	void dcn31_init_pipes(struct dc dc, struct dc_state context)
		610	{
		611	dcn10_init_pipes(dc, context);
		612	apply_riommu_invalidation_wa(dc);
		613
		614	}

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h+1−0

@@ -52,5 +52,6 @@ void dcn31_reset_hw_ctx_wrap( · 51 unmodified lines
52	struct dc_state *context);	52	struct dc_state *context);
53	bool dcn31_is_abm_supported(struct dc *dc,	53	bool dcn31_is_abm_supported(struct dc *dc,
54	struct dc_state context, struct dc_stream_state stream);	54	struct dc_state context, struct dc_stream_state stream);
		55	void dcn31_init_pipes(struct dc dc, struct dc_state context);
55		56
56	#endif /* __DC_HWSS_DCN31_H__ */	57	#endif /* __DC_HWSS_DCN31_H__ */

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c+1−2

 	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
 	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
 	.calc_vupdate_position = dcn10_calc_vupdate_position,
-	.apply_idle_power_optimizations = dcn30_apply_idle_power_optimizations,
 	.set_backlight_level = dcn21_set_backlight_level,
 	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
 	.set_pipe = dcn21_set_pipe,
 };
 static const struct hwseq_private_funcs dcn31_private_funcs = {
-	.init_pipes = dcn10_init_pipes,
+	.init_pipes = dcn31_init_pipes,
 	.update_plane_addr = dcn20_update_plane_addr,
 	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
 	.update_mpcc = dcn20_update_mpcc,

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c+4−0

 	.sr_exit_z8_time_us = 402.0,
 	.sr_enter_plus_exit_z8_time_us = 520.0,
 	.writeback_latency_us = 12.0,
+	.dram_channel_width_bytes = 4,
 	.round_trip_ping_latency_dcfclk_cycles = 106,
 	.urgent_latency_pixel_data_only_us = 4.0,
 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 #define HWSEQ_DCN31_REG_LIST()\
 	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+	SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
 	SR(DIO_MEM_PWR_CTRL), \
 	SR(ODM_MEM_PWR_CTRL3), \
 	SR(DMU_MEM_PWR_CNTL), \
 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
 	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 		hws->regs = &hwseq_reg;
 		hws->shifts = &hwseq_shift;
 		hws->masks = &hwseq_mask;
+		hws->wa.early_riommu_invalidation = true;
 	}
 	return hws;
 }

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c+4−1

 	else
 		*DestinationLinesForPrefetch = dst_y_prefetch_equ;
+	// Limit to prevent overflow in DST_Y_PREFETCH register
+	*DestinationLinesForPrefetch = dml_min(*DestinationLinesForPrefetch, 63.75);
 	dml_print("DML: VStartup: %d\n", VStartup);
 	dml_print("DML: TCalc: %f\n", TCalc);
 	dml_print("DML: TWait: %f\n", TWait);
 				}
 			} while ((locals->PrefetchSupported[i][j] != true || locals->VRatioInPrefetchSupported[i][j] != true)
 					&& (mode_lib->vba.NextMaxVStartup != mode_lib->vba.MaxMaxVStartup[0][0]
-						|| mode_lib->vba.NextPrefetchMode < mode_lib->vba.MaxPrefetchMode));
+						|| mode_lib->vba.NextPrefetchMode <= mode_lib->vba.MaxPrefetchMode));
 			if (locals->PrefetchSupported[i][j] == true && locals->VRatioInPrefetchSupported[i][j] == true) {
 				mode_lib->vba.BandwidthAvailableForImmediateFlip = locals->ReturnBWPerState[i][0];

drivers/gpu/drm/amd/display/dc/inc/hw/transform.h+3−0

@@ -289,6 +289,9 @@ struct dpp_caps { · 288 unmodified lines
289	/* DSCL processing pixel data in fixed or float format */	289	/* DSCL processing pixel data in fixed or float format */
290	enum dscl_data_processing_format dscl_data_proc_format;	290	enum dscl_data_processing_format dscl_data_proc_format;
291		291
		292	/* max LB partitions */
		293	unsigned int max_lb_partitions;
		294
292	/* Calculates the number of partitions in the line buffer.	295	/* Calculates the number of partitions in the line buffer.
293	* The implementation of this function is overloaded for	296	* The implementation of this function is overloaded for
294	* different versions of DSCL LB.	297	* different versions of DSCL LB.

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h+1−0

@@ -41,6 +41,7 @@ struct dce_hwseq_wa { · 40 unmodified lines
41	bool DEGVIDCN10_254;	41	bool DEGVIDCN10_254;
42	bool DEGVIDCN21;	42	bool DEGVIDCN21;
43	bool disallow_self_refresh_during_multi_plane_transition;	43	bool disallow_self_refresh_during_multi_plane_transition;
		44	bool early_riommu_invalidation;
44	};	45	};
45		46
46	struct hwseq_wa_state {	47	struct hwseq_wa_state {

drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h+2−1

@@ -101,7 +101,8 @@ · 100 unmodified lines
101	#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow 0x41	101	#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow 0x41
102		102
103	#define PPSMC_MSG_GfxDriverResetRecovery 0x42	103	#define PPSMC_MSG_GfxDriverResetRecovery 0x42
104	#define PPSMC_Message_Count 0x43	104	#define PPSMC_MSG_BoardPowerCalibration 0x43
		105	#define PPSMC_Message_Count 0x44
105		106
106	//PPSMC Reset Types	107	//PPSMC Reset Types
107	#define PPSMC_RESET_TYPE_WARM_RESET 0x00	108	#define PPSMC_RESET_TYPE_WARM_RESET 0x00

drivers/gpu/drm/amd/pm/inc/smu_types.h+2−1

@@ -225,7 +225,8 @@ · 224 unmodified lines
225	__SMU_DUMMY_MAP(DisableDeterminism), \	225	__SMU_DUMMY_MAP(DisableDeterminism), \
226	__SMU_DUMMY_MAP(SetUclkDpmMode), \	226	__SMU_DUMMY_MAP(SetUclkDpmMode), \
227	__SMU_DUMMY_MAP(LightSBR), \	227	__SMU_DUMMY_MAP(LightSBR), \
228	__SMU_DUMMY_MAP(GfxDriverResetRecovery),	228	__SMU_DUMMY_MAP(GfxDriverResetRecovery), \
		229	__SMU_DUMMY_MAP(BoardPowerCalibration),
229		230
230	#undef __SMU_DUMMY_MAP	231	#undef __SMU_DUMMY_MAP
231	#define __SMU_DUMMY_MAP(type) SMU_MSG_##type	232	#define __SMU_DUMMY_MAP(type) SMU_MSG_##type

drivers/gpu/drm/amd/pm/inc/smu_v11_0.h+1−1

@@ -34,7 +34,7 @@ · 33 unmodified lines
34	#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE	34	#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE
35	#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x03	35	#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x03
36	#define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF	36	#define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF
37	#define SMU11_DRIVER_IF_VERSION_Beige_Goby 0x9	37	#define SMU11_DRIVER_IF_VERSION_Beige_Goby 0xD
38		38
39	/* MP Apertures */	39	/* MP Apertures */
40	#define MP0_Public 0x03800000	40	#define MP0_Public 0x03800000

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c+36−10

@@ -134,6 +134,7 @@ static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT · 133 unmodified lines
134	MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),	134	MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
135	MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0),	135	MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0),
136	MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),	136	MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
		137	MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0),
137	};	138	};
138		139
139	static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {	140	static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
@@ -440,6 +441,39 @@ static int aldebaran_setup_pptable(struct smu_context *smu) · 300 unmodified lines
440	return ret;	441	return ret;
441	}	442	}
442		443
		444	static bool aldebaran_is_primary(struct smu_context *smu)
		445	{
		446	struct amdgpu_device *adev = smu->adev;
		447
		448	if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
		449	return adev->smuio.funcs->get_die_id(adev) == 0;
		450
		451	return true;
		452	}
		453
		454	static int aldebaran_run_board_btc(struct smu_context *smu)
		455	{
		456	u32 smu_version;
		457	int ret;
		458
		459	if (!aldebaran_is_primary(smu))
		460	return 0;
		461
		462	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
		463	if (ret) {
		464	dev_err(smu->adev->dev, "Failed to get smu version!\n");
		465	return ret;
		466	}
		467	if (smu_version <= 0x00441d00)
		468	return 0;
		469
		470	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL);
		471	if (ret)
		472	dev_err(smu->adev->dev, "Board power calibration failed!\n");
		473
		474	return ret;
		475	}
		476
443	static int aldebaran_run_btc(struct smu_context *smu)	477	static int aldebaran_run_btc(struct smu_context *smu)
444	{	478	{
445	int ret;	479	int ret;
@@ -447,6 +481,8 @@ static int aldebaran_run_btc(struct smu_context *smu) · 1 unmodified line
447	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);	481	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
448	if (ret)	482	if (ret)
449	dev_err(smu->adev->dev, "RunDcBtc failed!\n");	483	dev_err(smu->adev->dev, "RunDcBtc failed!\n");
		484	else
		485	ret = aldebaran_run_board_btc(smu);
450		486
451	return ret;	487	return ret;
452	}	488	}
@@ -524,16 +560,6 @@ static int aldebaran_freqs_in_same_level(int32_t frequency1, · 71 unmodified lines
524	return (abs(frequency1 - frequency2) <= EPSILON);	560	return (abs(frequency1 - frequency2) <= EPSILON);
525	}	561	}
526		562
527	static bool aldebaran_is_primary(struct smu_context *smu)
528	{
529	struct amdgpu_device *adev = smu->adev;
530
531	if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
532	return adev->smuio.funcs->get_die_id(adev) == 0;
533
534	return true;
535	}
536
537	static int aldebaran_get_smu_metrics_data(struct smu_context *smu,	563	static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
538	MetricsMember_t member,	564	MetricsMember_t member,
539	uint32_t *value)	565	uint32_t *value)

drivers/gpu/drm/drm_ioctl.c+3−0

@@ -834,6 +834,9 @@ long drm_ioctl(struct file *filp, · 833 unmodified lines
834	if (drm_dev_is_unplugged(dev))	834	if (drm_dev_is_unplugged(dev))
835	return -ENODEV;	835	return -ENODEV;
836		836
		837	if (DRM_IOCTL_TYPE(cmd) != DRM_IOCTL_BASE)
		838	return -ENOTTY;
		839
837	is_driver_ioctl = nr >= DRM_COMMAND_BASE && nr < DRM_COMMAND_END;	840	is_driver_ioctl = nr >= DRM_COMMAND_BASE && nr < DRM_COMMAND_END;
838		841
839	if (is_driver_ioctl) {	842	if (is_driver_ioctl) {

drivers/gpu/drm/i915/display/intel_bios.c+2−1

@@ -2166,7 +2166,8 @@ static void · 2165 unmodified lines
2166	init_vbt_missing_defaults(struct drm_i915_private *i915)	2166	init_vbt_missing_defaults(struct drm_i915_private *i915)
2167	{	2167	{
2168	enum port port;	2168	enum port port;
2169	int ports = PORT_A \| PORT_B \| PORT_C \| PORT_D \| PORT_E \| PORT_F;	2169	int ports = BIT(PORT_A) \| BIT(PORT_B) \| BIT(PORT_C) \|
		2170	BIT(PORT_D) \| BIT(PORT_E) \| BIT(PORT_F);
2170		2171
2171	if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))	2172	if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))
2172	return;	2173	return;

drivers/gpu/drm/i915/display/intel_display.c+7−1

 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
 		vlv_dsi_init(dev_priv);
-	} else if (DISPLAY_VER(dev_priv) >= 9) {
+	} else if (DISPLAY_VER(dev_priv) == 10) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
 		intel_ddi_init(dev_priv, PORT_D);
 		intel_ddi_init(dev_priv, PORT_E);
 		intel_ddi_init(dev_priv, PORT_F);
+	} else if (DISPLAY_VER(dev_priv) >= 9) {
+		intel_ddi_init(dev_priv, PORT_A);
+		intel_ddi_init(dev_priv, PORT_B);
+		intel_ddi_init(dev_priv, PORT_C);
+		intel_ddi_init(dev_priv, PORT_D);
+		intel_ddi_init(dev_priv, PORT_E);
 	} else if (HAS_DDI(dev_priv)) {
 		u32 found;

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c+13−214

@@ -25,10 +25,8 @@ · 24 unmodified lines
25	#include "i915_gem_clflush.h"	25	#include "i915_gem_clflush.h"
26	#include "i915_gem_context.h"	26	#include "i915_gem_context.h"
27	#include "i915_gem_ioctls.h"	27	#include "i915_gem_ioctls.h"
28	#include "i915_sw_fence_work.h"
29	#include "i915_trace.h"	28	#include "i915_trace.h"
30	#include "i915_user_extensions.h"	29	#include "i915_user_extensions.h"
31	#include "i915_memcpy.h"
32		30
33	struct eb_vma {	31	struct eb_vma {
34	struct i915_vma *vma;	32	struct i915_vma *vma;
@@ -1456,6 +1454,10 @@ static u32 reloc_gpu(struct i915_execbuffer eb, · 1421 unmodified lines
1456	int err;	1454	int err;
1457	struct intel_engine_cs *engine = eb->engine;	1455	struct intel_engine_cs *engine = eb->engine;
1458		1456
		1457	/* If we need to copy for the cmdparser, we will stall anyway */
		1458	if (eb_use_cmdparser(eb))
		1459	return ERR_PTR(-EWOULDBLOCK);
		1460
1459	if (!reloc_can_use_engine(engine)) {	1461	if (!reloc_can_use_engine(engine)) {
1460	engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0];	1462	engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0];
1461	if (!engine)	1463	if (!engine)
@@ -2372,217 +2374,6 @@ shadow_batch_pin(struct i915_execbuffer *eb, · 910 unmodified lines
2372	return vma;	2374	return vma;
2373	}	2375	}
2374		2376
2375	struct eb_parse_work {
2376	struct dma_fence_work base;
2377	struct intel_engine_cs *engine;
2378	struct i915_vma *batch;
2379	struct i915_vma *shadow;
2380	struct i915_vma *trampoline;
2381	unsigned long batch_offset;
2382	unsigned long batch_length;
2383	unsigned long *jump_whitelist;
2384	const void *batch_map;
2385	void *shadow_map;
2386	};
2387
2388	static int __eb_parse(struct dma_fence_work *work)
2389	{
2390	struct eb_parse_work pw = container_of(work, typeof(pw), base);
2391	int ret;
2392	bool cookie;
2393
2394	cookie = dma_fence_begin_signalling();
2395	ret = intel_engine_cmd_parser(pw->engine,
2396	pw->batch,
2397	pw->batch_offset,
2398	pw->batch_length,
2399	pw->shadow,
2400	pw->jump_whitelist,
2401	pw->shadow_map,
2402	pw->batch_map);
2403	dma_fence_end_signalling(cookie);
2404
2405	return ret;
2406	}
2407
2408	static void __eb_parse_release(struct dma_fence_work *work)
2409	{
2410	struct eb_parse_work pw = container_of(work, typeof(pw), base);
2411
2412	if (!IS_ERR_OR_NULL(pw->jump_whitelist))
2413	kfree(pw->jump_whitelist);
2414
2415	if (pw->batch_map)
2416	i915_gem_object_unpin_map(pw->batch->obj);
2417	else
2418	i915_gem_object_unpin_pages(pw->batch->obj);
2419
2420	i915_gem_object_unpin_map(pw->shadow->obj);
2421
2422	if (pw->trampoline)
2423	i915_active_release(&pw->trampoline->active);
2424	i915_active_release(&pw->shadow->active);
2425	i915_active_release(&pw->batch->active);
2426	}
2427
2428	static const struct dma_fence_work_ops eb_parse_ops = {
2429	.name = "eb_parse",
2430	.work = __eb_parse,
2431	.release = __eb_parse_release,
2432	};
2433
2434	static inline int
2435	__parser_mark_active(struct i915_vma *vma,
2436	struct intel_timeline *tl,
2437	struct dma_fence *fence)
2438	{
2439	struct intel_gt_buffer_pool_node *node = vma->private;
2440
2441	return i915_active_ref(&node->active, tl->fence_context, fence);
2442	}
2443
2444	static int
2445	parser_mark_active(struct eb_parse_work pw, struct intel_timeline tl)
2446	{
2447	int err;
2448
2449	mutex_lock(&tl->mutex);
2450
2451	err = __parser_mark_active(pw->shadow, tl, &pw->base.dma);
2452	if (err)
2453	goto unlock;
2454
2455	if (pw->trampoline) {
2456	err = __parser_mark_active(pw->trampoline, tl, &pw->base.dma);
2457	if (err)
2458	goto unlock;
2459	}
2460
2461	unlock:
2462	mutex_unlock(&tl->mutex);
2463	return err;
2464	}
2465
2466	static int eb_parse_pipeline(struct i915_execbuffer *eb,
2467	struct i915_vma *shadow,
2468	struct i915_vma *trampoline)
2469	{
2470	struct eb_parse_work *pw;
2471	struct drm_i915_gem_object *batch = eb->batch->vma->obj;
2472	bool needs_clflush;
2473	int err;
2474
2475	GEM_BUG_ON(overflows_type(eb->batch_start_offset, pw->batch_offset));
2476	GEM_BUG_ON(overflows_type(eb->batch_len, pw->batch_length));
2477
2478	pw = kzalloc(sizeof(*pw), GFP_KERNEL);
2479	if (!pw)
2480	return -ENOMEM;
2481
2482	err = i915_active_acquire(&eb->batch->vma->active);
2483	if (err)
2484	goto err_free;
2485
2486	err = i915_active_acquire(&shadow->active);
2487	if (err)
2488	goto err_batch;
2489
2490	if (trampoline) {
2491	err = i915_active_acquire(&trampoline->active);
2492	if (err)
2493	goto err_shadow;
2494	}
2495
2496	pw->shadow_map = i915_gem_object_pin_map(shadow->obj, I915_MAP_WB);
2497	if (IS_ERR(pw->shadow_map)) {
2498	err = PTR_ERR(pw->shadow_map);
2499	goto err_trampoline;
2500	}
2501
2502	needs_clflush =
2503	!(batch->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ);
2504
2505	pw->batch_map = ERR_PTR(-ENODEV);
2506	if (needs_clflush && i915_has_memcpy_from_wc())
2507	pw->batch_map = i915_gem_object_pin_map(batch, I915_MAP_WC);
2508
2509	if (IS_ERR(pw->batch_map)) {
2510	err = i915_gem_object_pin_pages(batch);
2511	if (err)
2512	goto err_unmap_shadow;
2513	pw->batch_map = NULL;
2514	}
2515
2516	pw->jump_whitelist =
2517	intel_engine_cmd_parser_alloc_jump_whitelist(eb->batch_len,
2518	trampoline);
2519	if (IS_ERR(pw->jump_whitelist)) {
2520	err = PTR_ERR(pw->jump_whitelist);
2521	goto err_unmap_batch;
2522	}
2523
2524	dma_fence_work_init(&pw->base, &eb_parse_ops);
2525
2526	pw->engine = eb->engine;
2527	pw->batch = eb->batch->vma;
2528	pw->batch_offset = eb->batch_start_offset;
2529	pw->batch_length = eb->batch_len;
2530	pw->shadow = shadow;
2531	pw->trampoline = trampoline;
2532
2533	/* Mark active refs early for this worker, in case we get interrupted */
2534	err = parser_mark_active(pw, eb->context->timeline);
2535	if (err)
2536	goto err_commit;
2537
2538	err = dma_resv_reserve_shared(pw->batch->resv, 1);
2539	if (err)
2540	goto err_commit;
2541
2542	err = dma_resv_reserve_shared(shadow->resv, 1);
2543	if (err)
2544	goto err_commit;
2545
2546	/* Wait for all writes (and relocs) into the batch to complete */
2547	err = i915_sw_fence_await_reservation(&pw->base.chain,
2548	pw->batch->resv, NULL, false,
2549	0, I915_FENCE_GFP);
2550	if (err < 0)
2551	goto err_commit;
2552
2553	/* Keep the batch alive and unwritten as we parse */
2554	dma_resv_add_shared_fence(pw->batch->resv, &pw->base.dma);
2555
2556	/* Force execution to wait for completion of the parser */
2557	dma_resv_add_excl_fence(shadow->resv, &pw->base.dma);
2558
2559	dma_fence_work_commit_imm(&pw->base);
2560	return 0;
2561
2562	err_commit:
2563	i915_sw_fence_set_error_once(&pw->base.chain, err);
2564	dma_fence_work_commit_imm(&pw->base);
2565	return err;
2566
2567	err_unmap_batch:
2568	if (pw->batch_map)
2569	i915_gem_object_unpin_map(batch);
2570	else
2571	i915_gem_object_unpin_pages(batch);
2572	err_unmap_shadow:
2573	i915_gem_object_unpin_map(shadow->obj);
2574	err_trampoline:
2575	if (trampoline)
2576	i915_active_release(&trampoline->active);
2577	err_shadow:
2578	i915_active_release(&shadow->active);
2579	err_batch:
2580	i915_active_release(&eb->batch->vma->active);
2581	err_free:
2582	kfree(pw);
2583	return err;
2584	}
2585
2586	static struct i915_vma eb_dispatch_secure(struct i915_execbuffer eb, struct i915_vma *vma)	2377	static struct i915_vma eb_dispatch_secure(struct i915_execbuffer eb, struct i915_vma *vma)
2587	{	2378	{
2588	/*	2379	/*
@@ -2672,7 +2463,15 @@ static int eb_parse(struct i915_execbuffer *eb) · 83 unmodified lines
2672	goto err_trampoline;	2463	goto err_trampoline;
2673	}	2464	}
2674		2465
2675	err = eb_parse_pipeline(eb, shadow, trampoline);	2466	err = dma_resv_reserve_shared(shadow->resv, 1);
		2467	if (err)
		2468	goto err_trampoline;
		2469
		2470	err = intel_engine_cmd_parser(eb->engine,
		2471	eb->batch->vma,
		2472	eb->batch_start_offset,
		2473	eb->batch_len,
		2474	shadow, trampoline);
2676	if (err)	2475	if (err)
2677	goto err_unpin_batch;	2476	goto err_unpin_batch;
2678		2477

drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c+4−0

@@ -125,6 +125,10 @@ static int igt_gpu_reloc(void *arg) · 124 unmodified lines
125	intel_gt_pm_get(&eb.i915->gt);	125	intel_gt_pm_get(&eb.i915->gt);
126		126
127	for_each_uabi_engine(eb.engine, eb.i915) {	127	for_each_uabi_engine(eb.engine, eb.i915) {
		128	if (intel_engine_requires_cmd_parser(eb.engine) \|\|
		129	intel_engine_using_cmd_parser(eb.engine))
		130	continue;
		131
128	reloc_cache_init(&eb.reloc_cache, eb.i915);	132	reloc_cache_init(&eb.reloc_cache, eb.i915);
129	memset(map, POISON_INUSE, 4096);	133	memset(map, POISON_INUSE, 4096);
130		134

drivers/gpu/drm/i915/gvt/handlers.c+15−0

@@ -1977,6 +1977,21 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, · 1976 unmodified lines
1977	if (drm_WARN_ON(&i915->drm, !engine))	1977	if (drm_WARN_ON(&i915->drm, !engine))
1978	return -EINVAL;	1978	return -EINVAL;
1979		1979
		1980	/*
		1981	* Due to d3_entered is used to indicate skipping PPGTT invalidation on
		1982	* vGPU reset, it's set on D0->D3 on PCI config write, and cleared after
		1983	* vGPU reset if in resuming.
		1984	* In S0ix exit, the device power state also transite from D3 to D0 as
		1985	* S3 resume, but no vGPU reset (triggered by QEMU devic model). After
		1986	* S0ix exit, all engines continue to work. However the d3_entered
		1987	* remains set which will break next vGPU reset logic (miss the expected
		1988	* PPGTT invalidation).
		1989	* Engines can only work in D0. Thus the 1st elsp write gives GVT a
		1990	* chance to clear d3_entered.
		1991	*/
		1992	if (vgpu->d3_entered)
		1993	vgpu->d3_entered = false;
		1994
1980	execlist = &vgpu->submission.execlist[engine->id];	1995	execlist = &vgpu->submission.execlist[engine->id];
1981		1996
1982	execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;	1997	execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;

drivers/gpu/drm/i915/i915_cmd_parser.c+74−62

@@ -1145,19 +1145,41 @@ find_reg(const struct intel_engine_cs *engine, u32 addr) · 1144 unmodified lines
1145	static u32 copy_batch(struct drm_i915_gem_object dst_obj,	1145	static u32 copy_batch(struct drm_i915_gem_object dst_obj,
1146	struct drm_i915_gem_object *src_obj,	1146	struct drm_i915_gem_object *src_obj,
1147	unsigned long offset, unsigned long length,	1147	unsigned long offset, unsigned long length,
1148	void dst, const void src)	1148	bool *needs_clflush_after)
1149	{	1149	{
1150	bool needs_clflush =	1150	unsigned int src_needs_clflush;
1151	!(src_obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ);	1151	unsigned int dst_needs_clflush;
1152		1152	void dst, src;
1153	if (src) {	1153	int ret;
1154	GEM_BUG_ON(!needs_clflush);	1154
1155	i915_unaligned_memcpy_from_wc(dst, src + offset, length);	1155	ret = i915_gem_object_prepare_write(dst_obj, &dst_needs_clflush);
1156	} else {	1156	if (ret)
1157	struct scatterlist *sg;	1157	return ERR_PTR(ret);
		1158
		1159	dst = i915_gem_object_pin_map(dst_obj, I915_MAP_WB);
		1160	i915_gem_object_finish_access(dst_obj);
		1161	if (IS_ERR(dst))
		1162	return dst;
		1163
		1164	ret = i915_gem_object_prepare_read(src_obj, &src_needs_clflush);
		1165	if (ret) {
		1166	i915_gem_object_unpin_map(dst_obj);
		1167	return ERR_PTR(ret);
		1168	}
		1169
		1170	src = ERR_PTR(-ENODEV);
		1171	if (src_needs_clflush && i915_has_memcpy_from_wc()) {
		1172	src = i915_gem_object_pin_map(src_obj, I915_MAP_WC);
		1173	if (!IS_ERR(src)) {
		1174	i915_unaligned_memcpy_from_wc(dst,
		1175	src + offset,
		1176	length);
		1177	i915_gem_object_unpin_map(src_obj);
		1178	}
		1179	}
		1180	if (IS_ERR(src)) {
		1181	unsigned long x, n, remain;
1158	void *ptr;	1182	void *ptr;
1159	unsigned int x, sg_ofs;
1160	unsigned long remain;
1161		1183
1162	/*	1184	/*
1163	* We can avoid clflushing partial cachelines before the write	1185	* We can avoid clflushing partial cachelines before the write
@@ -1168,40 +1190,34 @@ static u32 copy_batch(struct drm_i915_gem_object dst_obj, · 4 unmodified lines
1168	* validate up to the end of the batch.	1190	* validate up to the end of the batch.
1169	*/	1191	*/
1170	remain = length;	1192	remain = length;
1171	if (!(dst_obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))	1193	if (dst_needs_clflush & CLFLUSH_BEFORE)
1172	remain = round_up(remain,	1194	remain = round_up(remain,
1173	boot_cpu_data.x86_clflush_size);	1195	boot_cpu_data.x86_clflush_size);
1174		1196
1175	ptr = dst;	1197	ptr = dst;
1176	x = offset_in_page(offset);	1198	x = offset_in_page(offset);
1177	sg = i915_gem_object_get_sg(src_obj, offset >> PAGE_SHIFT, &sg_ofs, false);	1199	for (n = offset >> PAGE_SHIFT; remain; n++) {
1178		1200	int len = min(remain, PAGE_SIZE - x);
1179	while (remain) {	1201
1180	unsigned long sg_max = sg->length >> PAGE_SHIFT;	1202	src = kmap_atomic(i915_gem_object_get_page(src_obj, n));
1181		1203	if (src_needs_clflush)
1182	for (; remain && sg_ofs < sg_max; sg_ofs++) {	1204	drm_clflush_virt_range(src + x, len);
1183	unsigned long len = min(remain, PAGE_SIZE - x);	1205	memcpy(ptr, src + x, len);
1184	void *map;	1206	kunmap_atomic(src);
1185		1207
1186	map = kmap_atomic(nth_page(sg_page(sg), sg_ofs));	1208	ptr += len;
1187	if (needs_clflush)	1209	remain -= len;
1188	drm_clflush_virt_range(map + x, len);	1210	x = 0;
1189	memcpy(ptr, map + x, len);
1190	kunmap_atomic(map);
1191
1192	ptr += len;
1193	remain -= len;
1194	x = 0;
1195	}
1196
1197	sg_ofs = 0;
1198	sg = sg_next(sg);
1199	}	1211	}
1200	}	1212	}
1201		1213
		1214	i915_gem_object_finish_access(src_obj);
		1215
1202	memset32(dst + length, 0, (dst_obj->base.size - length) / sizeof(u32));	1216	memset32(dst + length, 0, (dst_obj->base.size - length) / sizeof(u32));
1203		1217
1204	/* dst_obj is returned with vmap pinned */	1218	/* dst_obj is returned with vmap pinned */
		1219	*needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER;
		1220
1205	return dst;	1221	return dst;
1206	}	1222	}
1207		1223
@@ -1360,6 +1376,9 @@ static int check_bbstart(u32 *cmd, u32 offset, u32 length, · 152 unmodified lines
1360	if (target_cmd_index == offset)	1376	if (target_cmd_index == offset)
1361	return 0;	1377	return 0;
1362		1378
		1379	if (IS_ERR(jump_whitelist))
		1380	return PTR_ERR(jump_whitelist);
		1381
1363	if (!test_bit(target_cmd_index, jump_whitelist)) {	1382	if (!test_bit(target_cmd_index, jump_whitelist)) {
1364	DRM_DEBUG("CMD: BB_START to 0x%llx not a previously executed cmd\n",	1383	DRM_DEBUG("CMD: BB_START to 0x%llx not a previously executed cmd\n",
1365	jump_target);	1384	jump_target);
@@ -1369,28 +1388,10 @@ static int check_bbstart(u32 *cmd, u32 offset, u32 length, · 3 unmodified lines
1369	return 0;	1388	return 0;
1370	}	1389	}
1371		1390
1372	/**	1391	static unsigned long *alloc_whitelist(u32 batch_length)
1373	* intel_engine_cmd_parser_alloc_jump_whitelist() - preallocate jump whitelist for intel_engine_cmd_parser()
1374	* @batch_length: length of the commands in batch_obj
1375	* @trampoline: Whether jump trampolines are used.
1376	*
1377	* Preallocates a jump whitelist for parsing the cmd buffer in intel_engine_cmd_parser().
1378	* This has to be preallocated, because the command parser runs in signaling context,
1379	* and may not allocate any memory.
1380	*
1381	* Return: NULL or pointer to a jump whitelist, or ERR_PTR() on failure. Use
1382	* IS_ERR() to check for errors. Must bre freed() with kfree().
1383	*
1384	* NULL is a valid value, meaning no allocation was required.
1385	*/
1386	unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length,
1387	bool trampoline)
1388	{	1392	{
1389	unsigned long *jmp;	1393	unsigned long *jmp;
1390		1394
1391	if (trampoline)
1392	return NULL;
1393
1394	/*	1395	/*
1395	* We expect batch_length to be less than 256KiB for known users,	1396	* We expect batch_length to be less than 256KiB for known users,
1396	* i.e. we need at most an 8KiB bitmap allocation which should be	1397	* i.e. we need at most an 8KiB bitmap allocation which should be
@@ -1415,9 +1416,7 @@ unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length, · 18 unmodified lines
1415	* @batch_offset: byte offset in the batch at which execution starts	1416	* @batch_offset: byte offset in the batch at which execution starts
1416	* @batch_length: length of the commands in batch_obj	1417	* @batch_length: length of the commands in batch_obj
1417	* @shadow: validated copy of the batch buffer in question	1418	* @shadow: validated copy of the batch buffer in question
1418	* @jump_whitelist: buffer preallocated with intel_engine_cmd_parser_alloc_jump_whitelist()	1419	* @trampoline: true if we need to trampoline into privileged execution
1419	* @shadow_map: mapping to @shadow vma
1420	* @batch_map: mapping to @batch vma
1421	*	1420	*
1422	* Parses the specified batch buffer looking for privilege violations as	1421	* Parses the specified batch buffer looking for privilege violations as
1423	* described in the overview.	1422	* described in the overview.
@@ -1425,21 +1424,21 @@ unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length, · 1 unmodified line
1425	* Return: non-zero if the parser finds violations or otherwise fails; -EACCES	1424	* Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1426	* if the batch appears legal but should use hardware parsing	1425	* if the batch appears legal but should use hardware parsing
1427	*/	1426	*/
		1427
1428	int intel_engine_cmd_parser(struct intel_engine_cs *engine,	1428	int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1429	struct i915_vma *batch,	1429	struct i915_vma *batch,
1430	unsigned long batch_offset,	1430	unsigned long batch_offset,
1431	unsigned long batch_length,	1431	unsigned long batch_length,
1432	struct i915_vma *shadow,	1432	struct i915_vma *shadow,
1433	unsigned long *jump_whitelist,	1433	bool trampoline)
1434	void *shadow_map,
1435	const void *batch_map)
1436	{	1434	{
1437	u32 cmd, batch_end, offset = 0;	1435	u32 cmd, batch_end, offset = 0;
1438	struct drm_i915_cmd_descriptor default_desc = noop_desc;	1436	struct drm_i915_cmd_descriptor default_desc = noop_desc;
1439	const struct drm_i915_cmd_descriptor *desc = &default_desc;	1437	const struct drm_i915_cmd_descriptor *desc = &default_desc;
		1438	bool needs_clflush_after = false;
		1439	unsigned long *jump_whitelist;
1440	u64 batch_addr, shadow_addr;	1440	u64 batch_addr, shadow_addr;
1441	int ret = 0;	1441	int ret = 0;
1442	bool trampoline = !jump_whitelist;
1443		1442
1444	GEM_BUG_ON(!IS_ALIGNED(batch_offset, sizeof(*cmd)));	1443	GEM_BUG_ON(!IS_ALIGNED(batch_offset, sizeof(*cmd)));
1445	GEM_BUG_ON(!IS_ALIGNED(batch_length, sizeof(*cmd)));	1444	GEM_BUG_ON(!IS_ALIGNED(batch_length, sizeof(*cmd)));
@@ -1447,8 +1446,18 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, · 1 unmodified line
1447	batch->size));	1446	batch->size));
1448	GEM_BUG_ON(!batch_length);	1447	GEM_BUG_ON(!batch_length);
1449		1448
1450	cmd = copy_batch(shadow->obj, batch->obj, batch_offset, batch_length,	1449	cmd = copy_batch(shadow->obj, batch->obj,
1451	shadow_map, batch_map);	1450	batch_offset, batch_length,
		1451	&needs_clflush_after);
		1452	if (IS_ERR(cmd)) {
		1453	DRM_DEBUG("CMD: Failed to copy batch\n");
		1454	return PTR_ERR(cmd);
		1455	}
		1456
		1457	jump_whitelist = NULL;
		1458	if (!trampoline)
		1459	/* Defer failure until attempted use */
		1460	jump_whitelist = alloc_whitelist(batch_length);
1452		1461
1453	shadow_addr = gen8_canonical_addr(shadow->node.start);	1462	shadow_addr = gen8_canonical_addr(shadow->node.start);
1454	batch_addr = gen8_canonical_addr(batch->node.start + batch_offset);	1463	batch_addr = gen8_canonical_addr(batch->node.start + batch_offset);
@@ -1549,6 +1558,9 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, · 94 unmodified lines
1549		1558
1550	i915_gem_object_flush_map(shadow->obj);	1559	i915_gem_object_flush_map(shadow->obj);
1551		1560
		1561	if (!IS_ERR_OR_NULL(jump_whitelist))
		1562	kfree(jump_whitelist);
		1563	i915_gem_object_unpin_map(shadow->obj);
1552	return ret;	1564	return ret;
1553	}	1565	}
1554		1566

drivers/gpu/drm/i915/i915_drv.h+1−6

 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
-unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length,
-							    bool trampoline);
 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
 			    struct i915_vma *batch,
 			    unsigned long batch_offset,
 			    unsigned long batch_length,
 			    struct i915_vma *shadow,
-			    unsigned long *jump_whitelist,
+			    bool trampoline);
-			    void *shadow_map,
-			    const void *batch_map);
 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
 /* intel_device_info.c */

drivers/gpu/drm/i915/i915_request.c+2−6

 	do {
 		fence = *child++;
-		if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
+		if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
-			i915_sw_fence_set_error_once(&rq->submit, fence->error);
 			continue;
-		}
 		if (fence->context == rq->fence.context)
 			continue;
 	do {
 		fence = *child++;
-		if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
+		if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
-			i915_sw_fence_set_error_once(&rq->submit, fence->error);
 			continue;
-		}
 		/*
 		 * Requests on the same timeline are explicitly ordered, along

drivers/gpu/drm/i915/intel_device_info.c+5−4

@@ -325,7 +325,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) · 324 unmodified lines
325	info->pipe_mask &= ~BIT(PIPE_C);	325	info->pipe_mask &= ~BIT(PIPE_C);
326	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);	326	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
327	}	327	}
328	} else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) {	328	} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
329	u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);	329	u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
330		330
331	if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {	331	if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
@@ -340,7 +340,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) · 8 unmodified lines
340	info->pipe_mask &= ~BIT(PIPE_C);	340	info->pipe_mask &= ~BIT(PIPE_C);
341	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);	341	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
342	}	342	}
343	if (GRAPHICS_VER(dev_priv) >= 12 &&	343
		344	if (DISPLAY_VER(dev_priv) >= 12 &&
344	(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {	345	(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
345	info->pipe_mask &= ~BIT(PIPE_D);	346	info->pipe_mask &= ~BIT(PIPE_D);
346	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);	347	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
@@ -352,10 +353,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) · 5 unmodified lines
352	if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)	353	if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
353	info->display.has_fbc = 0;	354	info->display.has_fbc = 0;
354		355
355	if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))	356	if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
356	info->display.has_dmc = 0;	357	info->display.has_dmc = 0;
357		358
358	if (GRAPHICS_VER(dev_priv) >= 10 &&	359	if (DISPLAY_VER(dev_priv) >= 10 &&
359	(dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))	360	(dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
360	info->display.has_dsc = 0;	361	info->display.has_dsc = 0;
361	}	362	}

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c+1−1

@@ -296,7 +296,7 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = { · 295 unmodified lines
296	static const struct dpu_mdp_cfg sm8250_mdp[] = {	296	static const struct dpu_mdp_cfg sm8250_mdp[] = {
297	{	297	{
298	.name = "top_0", .id = MDP_TOP,	298	.name = "top_0", .id = MDP_TOP,
299	.base = 0x0, .len = 0x45C,	299	.base = 0x0, .len = 0x494,
300	.features = 0,	300	.features = 0,
301	.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */	301	.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
302	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {	302	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {

drivers/gpu/drm/msm/dp/dp_catalog.c+1−0

@@ -771,6 +771,7 @@ int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog) · 770 unmodified lines
771	dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY,	771	dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY,
772	dp_catalog->width_blanking);	772	dp_catalog->width_blanking);
773	dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_catalog->dp_active);	773	dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_catalog->dp_active);
		774	dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0);
774	return 0;	775	return 0;
775	}	776	}
776		777

drivers/gpu/drm/msm/dp/dp_ctrl.c+1−1

@@ -1526,7 +1526,7 @@ static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) · 1525 unmodified lines
1526	* running. Add the global reset just before disabling the	1526	* running. Add the global reset just before disabling the
1527	* link clocks and core clocks.	1527	* link clocks and core clocks.
1528	*/	1528	*/
1529	ret = dp_ctrl_off(&ctrl->dp_ctrl);	1529	ret = dp_ctrl_off_link_stream(&ctrl->dp_ctrl);
1530	if (ret) {	1530	if (ret) {
1531	DRM_ERROR("failed to disable DP controller\n");	1531	DRM_ERROR("failed to disable DP controller\n");
1532	return ret;	1532	return ret;

drivers/gpu/drm/msm/dp/dp_display.c+5−0

 		goto end;
 	}
+	dp->aux->drm_dev = drm;
 	rc = dp_aux_register(dp->aux);
 	if (rc) {
 		DRM_ERROR("DRM DP AUX register failed\n");
 	else
 		dp->dp_display.is_connected = false;
+	dp_display_handle_plugged_change(g_dp_display,
+				dp->dp_display.is_connected);
 	mutex_unlock(&dp->event_mutex);
 	return 0;

drivers/gpu/drm/msm/msm_iommu.c+10−1

 	.tlb_add_page = msm_iommu_tlb_add_page,
 };
+static int msm_fault_handler(struct iommu_domain *domain, struct device *dev,
+		unsigned long iova, int flags, void *arg);
 struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent)
 {
 	struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(parent->dev);
 	if (!ttbr1_cfg)
 		return ERR_PTR(-ENODEV);
+	/*
+	 * Defer setting the fault handler until we have a valid adreno_smmu
+	 * to avoid accidentially installing a GPU specific fault handler for
+	 * the display's iommu
+	 */
+	iommu_set_fault_handler(iommu->domain, msm_fault_handler, iommu);
 	pagetable = kzalloc(sizeof(*pagetable), GFP_KERNEL);
 	if (!pagetable)
 		return ERR_PTR(-ENOMEM);
 	iommu->domain = domain;
 	msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU);
-	iommu_set_fault_handler(domain, msm_fault_handler, iommu);
 	atomic_set(&iommu->pagetables, 0);

drivers/gpu/drm/nouveau/nouveau_bo.c+6−0

 	 */
 	if (bo->base.dev)
 		drm_gem_object_release(&bo->base);
+	else
+		dma_resv_fini(&bo->base._resv);
 	kfree(nvbo);
 }
 	if (IS_ERR(nvbo))
 		return PTR_ERR(nvbo);
+	nvbo->bo.base.size = size;
+	dma_resv_init(&nvbo->bo.base._resv);
+	drm_vma_node_reset(&nvbo->bo.base.vma_node);
 	ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
 	if (ret)
 		return ret;

drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c+0−1

@@ -447,7 +447,6 @@ static int rpi_touchscreen_remove(struct i2c_client *i2c) · 446 unmodified lines
447	drm_panel_remove(&ts->base);	447	drm_panel_remove(&ts->base);
448		448
449	mipi_dsi_device_unregister(ts->dsi);	449	mipi_dsi_device_unregister(ts->dsi);
450	kfree(ts->dsi);
451		450
452	return 0;	451	return 0;
453	}	452	}

drivers/gpu/drm/panel/panel-simple.c+1−1

@@ -4166,7 +4166,7 @@ static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode · 4165 unmodified lines
4166	static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {	4166	static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4167	.modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,	4167	.modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4168	.num_modes = 1,	4168	.num_modes = 1,
4169	.bpc = 6,	4169	.bpc = 8,
4170	.size = {	4170	.size = {
4171	.width = 154,	4171	.width = 154,
4172	.height = 90,	4172	.height = 90,

drivers/gpu/drm/ttm/ttm_bo.c+3−0

@@ -102,6 +102,9 @@ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo, · 101 unmodified lines
102	return;	102	return;
103	}	103	}
104		104
		105	if (!mem)
		106	return;
		107
105	man = ttm_manager_type(bdev, mem->mem_type);	108	man = ttm_manager_type(bdev, mem->mem_type);
106	list_move_tail(&bo->lru, &man->lru[bo->priority]);	109	list_move_tail(&bo->lru, &man->lru[bo->priority]);
107		110

drivers/gpu/drm/ttm/ttm_bo_util.c+3−0

@@ -63,6 +63,9 @@ int ttm_mem_io_reserve(struct ttm_device *bdev, · 62 unmodified lines
63	void ttm_mem_io_free(struct ttm_device *bdev,	63	void ttm_mem_io_free(struct ttm_device *bdev,
64	struct ttm_resource *mem)	64	struct ttm_resource *mem)
65	{	65	{
		66	if (!mem)
		67	return;
		68
66	if (!mem->bus.offset && !mem->bus.addr)	69	if (!mem->bus.offset && !mem->bus.addr)
67	return;	70	return;
68		71

drivers/gpu/drm/ttm/ttm_device.c+14−0

 struct ttm_global ttm_glob;
 EXPORT_SYMBOL(ttm_glob);
+struct dentry *ttm_debugfs_root;
 static void ttm_global_release(void)
 {
 	struct ttm_global *glob = &ttm_glob;
 		goto out;
 	ttm_pool_mgr_fini();
+	debugfs_remove(ttm_debugfs_root);
 	__free_page(glob->dummy_read_page);
 	memset(glob, 0, sizeof(*glob));
 	si_meminfo(&si);
+	ttm_debugfs_root = debugfs_create_dir("ttm", NULL);
+	if (IS_ERR(ttm_debugfs_root)) {
+		ret = PTR_ERR(ttm_debugfs_root);
+		ttm_debugfs_root = NULL;
+		goto out;
+	}
 	/* Limit the number of pages in the pool to about 50% of the total
 	 * system memory.
 	 */
 	debugfs_create_atomic_t("buffer_objects", 0444, ttm_debugfs_root,
 				&glob->bo_count);
 out:
+	if (ret && ttm_debugfs_root)
+		debugfs_remove(ttm_debugfs_root);
+	if (ret)
+		--ttm_glob_use_count;
 	mutex_unlock(&ttm_global_mutex);
 	return ret;
 }

drivers/gpu/drm/ttm/ttm_module.c+0−16

@@ -72,22 +72,6 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp) · 71 unmodified lines
72	return tmp;	72	return tmp;
73	}	73	}
74		74
75	struct dentry *ttm_debugfs_root;
76
77	static int __init ttm_init(void)
78	{
79	ttm_debugfs_root = debugfs_create_dir("ttm", NULL);
80	return 0;
81	}
82
83	static void __exit ttm_exit(void)
84	{
85	debugfs_remove(ttm_debugfs_root);
86	}
87
88	module_init(ttm_init);
89	module_exit(ttm_exit);
90
91	MODULE_AUTHOR("Thomas Hellstrom, Jerome Glisse");	75	MODULE_AUTHOR("Thomas Hellstrom, Jerome Glisse");
92	MODULE_DESCRIPTION("TTM memory manager subsystem (for DRM device)");	76	MODULE_DESCRIPTION("TTM memory manager subsystem (for DRM device)");
93	MODULE_LICENSE("GPL and additional rights");	77	MODULE_LICENSE("GPL and additional rights");

drivers/gpu/drm/vc4/vc4_hdmi.c+33−16

 	vc4_hdmi_cec_update_clk_div(vc4_hdmi);
 	if (vc4_hdmi->variant->external_irq_controller) {
-		ret = devm_request_threaded_irq(&pdev->dev,
+		ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
-						platform_get_irq_byname(pdev, "cec-rx"),
+					   vc4_cec_irq_handler_rx_bare,
-						vc4_cec_irq_handler_rx_bare,
+					   vc4_cec_irq_handler_rx_thread, 0,
-						vc4_cec_irq_handler_rx_thread, 0,
+					   "vc4 hdmi cec rx", vc4_hdmi);
-						"vc4 hdmi cec rx", vc4_hdmi);
 		if (ret)
 			goto err_delete_cec_adap;
-		ret = devm_request_threaded_irq(&pdev->dev,
+		ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
-						platform_get_irq_byname(pdev, "cec-tx"),
+					   vc4_cec_irq_handler_tx_bare,
-						vc4_cec_irq_handler_tx_bare,
+					   vc4_cec_irq_handler_tx_thread, 0,
-						vc4_cec_irq_handler_tx_thread, 0,
+					   "vc4 hdmi cec tx", vc4_hdmi);
-						"vc4 hdmi cec tx", vc4_hdmi);
 		if (ret)
-			goto err_delete_cec_adap;
+			goto err_remove_cec_rx_handler;
 	} else {
 		HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
-		ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
+		ret = request_threaded_irq(platform_get_irq(pdev, 0),
-						vc4_cec_irq_handler,
+					   vc4_cec_irq_handler,
-						vc4_cec_irq_handler_thread, 0,
+					   vc4_cec_irq_handler_thread, 0,
-						"vc4 hdmi cec", vc4_hdmi);
+					   "vc4 hdmi cec", vc4_hdmi);
 		if (ret)
 			goto err_delete_cec_adap;
 	}
 	ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
 	if (ret < 0)
-		goto err_delete_cec_adap;
+		goto err_remove_handlers;
 	return 0;
+err_remove_handlers:
+	if (vc4_hdmi->variant->external_irq_controller)
+		free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
+	else
+		free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
+err_remove_cec_rx_handler:
+	if (vc4_hdmi->variant->external_irq_controller)
+		free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
 err_delete_cec_adap:
 	cec_delete_adapter(vc4_hdmi->cec_adap);
 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
 {
+	struct platform_device *pdev = vc4_hdmi->pdev;
+	if (vc4_hdmi->variant->external_irq_controller) {
+		free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
+		free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
+	} else {
+		free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
+	}
 	cec_unregister_adapter(vc4_hdmi->cec_adap);
 }
 #else

drivers/hid/Kconfig+1−1

@@ -576,7 +576,7 @@ config HID_LOGITECH_HIDPP · 575 unmodified lines
576	depends on HID_LOGITECH	576	depends on HID_LOGITECH
577	select POWER_SUPPLY	577	select POWER_SUPPLY
578	help	578	help
579	Support for Logitech devices relyingon the HID++ Logitech specification	579	Support for Logitech devices relying on the HID++ Logitech specification
580		580
581	Say Y if you want support for Logitech devices relying on the HID++	581	Say Y if you want support for Logitech devices relying on the HID++
582	specification. Such devices are the various Logitech Touchpads (T650,	582	specification. Such devices are the various Logitech Touchpads (T650,

drivers/hid/amd-sfh-hid/amd_sfh_pcie.c+1−1

@@ -58,7 +58,7 @@ static void amd_stop_sensor_v2(struct amd_mp2_dev *privdata, u16 sensor_idx) · 57 unmodified lines
58	cmd_base.cmd_v2.sensor_id = sensor_idx;	58	cmd_base.cmd_v2.sensor_id = sensor_idx;
59	cmd_base.cmd_v2.length = 16;	59	cmd_base.cmd_v2.length = 16;
60		60
61	writeq(0x0, privdata->mmio + AMD_C2P_MSG2);	61	writeq(0x0, privdata->mmio + AMD_C2P_MSG1);
62	writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);	62	writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
63	}	63	}
64		64

drivers/hid/hid-apple.c+2−0

 			APPLE_RDESC_JIS },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_REVB_ANSI),
 		.driver_data = APPLE_HAS_FN },
+	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_REVB_ANSI),
+		.driver_data = APPLE_HAS_FN },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_REVB_ISO),
 		.driver_data = APPLE_HAS_FN },
 	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_REVB_ISO),

drivers/hid/hid-asus.c+0−3

 {
 	struct asus_kbd_leds *led = container_of(led_cdev, struct asus_kbd_leds,
 						 cdev);
-	if (led->brightness == brightness)
-		return;
 	led->brightness = brightness;
 	schedule_work(&led->work);
 }

drivers/hid/hid-ft260.c+9−18

 	int ret;
 	ret = ft260_get_system_config(hdev, &cfg);
-	if (ret)
+	if (ret < 0)
 		return ret;
 	ft260_dbg("interface:  0x%02x\n", interface);
 	switch (cfg.chip_mode) {
 	case FT260_MODE_ALL:
 	case FT260_MODE_BOTH:
-		if (interface == 1) {
+		if (interface == 1)
 			hid_info(hdev, "uart interface is not supported\n");
-			return 0;
+		else
-		}
+			ret = 1;
-		ret = 1;
 		break;
 	case FT260_MODE_UART:
-		if (interface == 0) {
+		hid_info(hdev, "uart interface is not supported\n");
-			hid_info(hdev, "uart is unsupported on interface 0\n");
-			ret = 0;
-		}
 		break;
 	case FT260_MODE_I2C:
-		if (interface == 1) {
+		ret = 1;
-			hid_info(hdev, "i2c is unsupported on interface 1\n");
-			ret = 0;
-		}
 		break;
 	}
 	return ret;
 	if (ret < 0)
 		return ret;
-	return scnprintf(buf, PAGE_SIZE, "%hi\n", *field);
+	return scnprintf(buf, PAGE_SIZE, "%d\n", *field);
 }
 static int ft260_word_show(struct hid_device *hdev, int id, u8 *cfg, int len,
 	if (ret < 0)
 		return ret;
-	return scnprintf(buf, PAGE_SIZE, "%hi\n", le16_to_cpu(*field));
+	return scnprintf(buf, PAGE_SIZE, "%d\n", le16_to_cpu(*field));
 }
 #define FT260_ATTR_SHOW(name, reptype, id, type, func)			       \
 static void ft260_remove(struct hid_device *hdev)
 {
-	int ret;
 	struct ft260_device *dev = hid_get_drvdata(hdev);
-	ret = ft260_is_interface_enabled(hdev);
+	if (!dev)
-	if (ret <= 0)
 		return;
 	sysfs_remove_group(&hdev->dev.kobj, &ft260_attr_group);

drivers/hid/intel-ish-hid/ishtp-hid-client.c+14−1

 	}
 }
+static void hid_ishtp_cl_resume_handler(struct work_struct *work)
+{
+	struct ishtp_cl_data *client_data = container_of(work, struct ishtp_cl_data, resume_work);
+	struct ishtp_cl *hid_ishtp_cl = client_data->hid_ishtp_cl;
+	if (ishtp_wait_resume(ishtp_get_ishtp_device(hid_ishtp_cl))) {
+		client_data->suspended = false;
+		wake_up_interruptible(&client_data->ishtp_resume_wait);
+	}
+}
 ishtp_print_log ishtp_hid_print_trace;
 /**
 	init_waitqueue_head(&client_data->ishtp_resume_wait);
 	INIT_WORK(&client_data->work, hid_ishtp_cl_reset_handler);
+	INIT_WORK(&client_data->resume_work, hid_ishtp_cl_resume_handler);
 	ishtp_hid_print_trace = ishtp_trace_callback(cl_device);
 	hid_ishtp_trace(client_data, "%s hid_ishtp_cl %p\n", __func__,
 			hid_ishtp_cl);
-	client_data->suspended = false;
+	schedule_work(&client_data->resume_work);
 	return 0;
 }

drivers/hid/intel-ish-hid/ishtp-hid.h+1−0

@@ -135,6 +135,7 @@ struct ishtp_cl_data { · 134 unmodified lines
135	int multi_packet_cnt;	135	int multi_packet_cnt;
136		136
137	struct work_struct work;	137	struct work_struct work;
		138	struct work_struct resume_work;
138	struct ishtp_cl_device *cl_device;	139	struct ishtp_cl_device *cl_device;
139	};	140	};
140		141

drivers/hid/intel-ish-hid/ishtp/bus.c+22−7

@@ -314,13 +314,6 @@ static int ishtp_cl_device_resume(struct device *dev) · 313 unmodified lines
314	if (!device)	314	if (!device)
315	return 0;	315	return 0;
316		316
317	/*
318	* When ISH needs hard reset, it is done asynchrnously, hence bus
319	* resume will be called before full ISH resume
320	*/
321	if (device->ishtp_dev->resume_flag)
322	return 0;
323
324	driver = to_ishtp_cl_driver(dev->driver);	317	driver = to_ishtp_cl_driver(dev->driver);
325	if (driver && driver->driver.pm) {	318	if (driver && driver->driver.pm) {
326	if (driver->driver.pm->resume)	319	if (driver->driver.pm->resume)
@@ -849,6 +842,28 @@ struct device ishtp_device(struct ishtp_cl_device device) · 522 unmodified lines
849	}	842	}
850	EXPORT_SYMBOL(ishtp_device);	843	EXPORT_SYMBOL(ishtp_device);
851		844
		845	/**
		846	* ishtp_wait_resume() - Wait for IPC resume
		847	*
		848	* Wait for IPC resume
		849	*
		850	* Return: resume complete or not
		851	*/
		852	bool ishtp_wait_resume(struct ishtp_device *dev)
		853	{
		854	/* 50ms to get resume response */
		855	#define WAIT_FOR_RESUME_ACK_MS 50
		856
		857	/* Waiting to get resume response */
		858	if (dev->resume_flag)
		859	wait_event_interruptible_timeout(dev->resume_wait,
		860	!dev->resume_flag,
		861	msecs_to_jiffies(WAIT_FOR_RESUME_ACK_MS));
		862
		863	return (!dev->resume_flag);
		864	}
		865	EXPORT_SYMBOL_GPL(ishtp_wait_resume);
		866
852	/**	867	/**
853	* ishtp_get_pci_device() - Return PCI device dev pointer	868	* ishtp_get_pci_device() - Return PCI device dev pointer
854	* This interface is used to return PCI device pointer	869	* This interface is used to return PCI device pointer

drivers/hid/usbhid/Kconfig+1−1

@@ -38,7 +38,7 @@ config USB_HIDDEV · 37 unmodified lines
38	help	38	help
39	Say Y here if you want to support HID devices (from the USB	39	Say Y here if you want to support HID devices (from the USB
40	specification standpoint) that aren't strictly user interface	40	specification standpoint) that aren't strictly user interface
41	devices, like monitor controls and Uninterruptable Power Supplies.	41	devices, like monitor controls and Uninterruptible Power Supplies.
42		42
43	This module supports these devices separately using a separate	43	This module supports these devices separately using a separate
44	event interface on /dev/usb/hiddevX (char 180:96 to 180:111).	44	event interface on /dev/usb/hiddevX (char 180:96 to 180:111).

drivers/hid/wacom_wac.c+4−1

 		int slot;
 		slot = input_mt_get_slot_by_key(input, hid_data->id);
+		if (slot < 0)
+			return;
 		input_mt_slot(input, slot);
 		input_mt_report_slot_state(input, MT_TOOL_FINGER, prox);
 	}
 		    wacom_wac->shared->touch->product == 0xF6) {
 			input_dev->evbit[0] |= BIT_MASK(EV_SW);
 			__set_bit(SW_MUTE_DEVICE, input_dev->swbit);
-			wacom_wac->shared->has_mute_touch_switch = true;
+			wacom_wac->has_mute_touch_switch = true;
 		}
 		fallthrough;

drivers/hv/channel_mgmt.c+64−32

 	 */
 	mutex_lock(&vmbus_connection.channel_mutex);
+	list_for_each_entry(channel, &vmbus_connection.chn_list, listentry) {
+		if (guid_equal(&channel->offermsg.offer.if_type,
+			       &newchannel->offermsg.offer.if_type) &&
+		    guid_equal(&channel->offermsg.offer.if_instance,
+			       &newchannel->offermsg.offer.if_instance)) {
+			fnew = false;
+			newchannel->primary_channel = channel;
+			break;
+		}
+	}
 	init_vp_index(newchannel);
 	/* Remember the channels that should be cleaned up upon suspend. */
 	 */
 	atomic_dec(&vmbus_connection.offer_in_progress);
-	list_for_each_entry(channel, &vmbus_connection.chn_list, listentry) {
-		if (guid_equal(&channel->offermsg.offer.if_type,
-			       &newchannel->offermsg.offer.if_type) &&
-		    guid_equal(&channel->offermsg.offer.if_instance,
-			       &newchannel->offermsg.offer.if_instance)) {
-			fnew = false;
-			break;
-		}
-	}
 	if (fnew) {
 		list_add_tail(&newchannel->listentry,
 			      &vmbus_connection.chn_list);
 		/*
 		 * Process the sub-channel.
 		 */
-		newchannel->primary_channel = channel;
 		list_add_tail(&newchannel->sc_list, &channel->sc_list);
 	}
 	queue_work(wq, &newchannel->add_channel_work);
 }
+/*
+ * Check if CPUs used by other channels of the same device.
+ * It should only be called by init_vp_index().
+ */
+static bool hv_cpuself_used(u32 cpu, struct vmbus_channel *chn)
+{
+	struct vmbus_channel *primary = chn->primary_channel;
+	struct vmbus_channel *sc;
+	lockdep_assert_held(&vmbus_connection.channel_mutex);
+	if (!primary)
+		return false;
+	if (primary->target_cpu == cpu)
+		return true;
+	list_for_each_entry(sc, &primary->sc_list, sc_list)
+		if (sc != chn && sc->target_cpu == cpu)
+			return true;
+	return false;
+}
 /*
  * We use this state to statically distribute the channel interrupt load.
  */
 static void init_vp_index(struct vmbus_channel *channel)
 {
 	bool perf_chn = hv_is_perf_channel(channel);
+	u32 i, ncpu = num_online_cpus();
 	cpumask_var_t available_mask;
 	struct cpumask *alloced_mask;
 	u32 target_cpu;
 		return;
 	}
-	while (true) {
+	for (i = 1; i <= ncpu + 1; i++) {
-		numa_node = next_numa_node_id++;
+		while (true) {
-		if (numa_node == nr_node_ids) {
+			numa_node = next_numa_node_id++;
-			next_numa_node_id = 0;
+			if (numa_node == nr_node_ids) {
-			continue;
+				next_numa_node_id = 0;
+				continue;
+			}
+			if (cpumask_empty(cpumask_of_node(numa_node)))
+				continue;
+			break;
+		}
+		alloced_mask = &hv_context.hv_numa_map[numa_node];
+		if (cpumask_weight(alloced_mask) ==
+		    cpumask_weight(cpumask_of_node(numa_node))) {
+			/*
+			 * We have cycled through all the CPUs in the node;
+			 * reset the alloced map.
+			 */
+			cpumask_clear(alloced_mask);
 		}
-		if (cpumask_empty(cpumask_of_node(numa_node)))
-			continue;
-		break;
-	}
-	alloced_mask = &hv_context.hv_numa_map[numa_node];
-	if (cpumask_weight(alloced_mask) ==
+		cpumask_xor(available_mask, alloced_mask,
-	    cpumask_weight(cpumask_of_node(numa_node))) {
+			    cpumask_of_node(numa_node));
-		/*
-		 * We have cycled through all the CPUs in the node;
-		 * reset the alloced map.
-		 */
-		cpumask_clear(alloced_mask);
-	}
-	cpumask_xor(available_mask, alloced_mask, cpumask_of_node(numa_node));
+		target_cpu = cpumask_first(available_mask);
+		cpumask_set_cpu(target_cpu, alloced_mask);
-	target_cpu = cpumask_first(available_mask);
+		if (channel->offermsg.offer.sub_channel_index >= ncpu ||
-	cpumask_set_cpu(target_cpu, alloced_mask);
+		    i > ncpu || !hv_cpuself_used(target_cpu, channel))
+			break;
+	}
 	channel->target_cpu = target_cpu;

drivers/i2c/busses/i2c-mpc.c+2−2

@@ -635,8 +635,8 @@ static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) · 634 unmodified lines
635		635
636	status = readb(i2c->base + MPC_I2C_SR);	636	status = readb(i2c->base + MPC_I2C_SR);
637	if (status & CSR_MIF) {	637	if (status & CSR_MIF) {
638	/* Read again to allow register to stabilise */	638	/* Wait up to 100us for transfer to properly complete */
639	status = readb(i2c->base + MPC_I2C_SR);	639	readb_poll_timeout(i2c->base + MPC_I2C_SR, status, !(status & CSR_MCF), 0, 100);
640	writeb(0, i2c->base + MPC_I2C_SR);	640	writeb(0, i2c->base + MPC_I2C_SR);
641	mpc_i2c_do_intr(i2c, status);	641	mpc_i2c_do_intr(i2c, status);
642	return IRQ_HANDLED;	642	return IRQ_HANDLED;

drivers/infiniband/hw/bnxt_re/main.c+3−1

 	if (!chip_ctx)
 		return -ENOMEM;
 	chip_ctx->chip_num = bp->chip_num;
+	chip_ctx->hw_stats_size = bp->hw_ring_stats_size;
 	rdev->chip_ctx = chip_ctx;
 	/* rest members to follow eventually */
 				       dma_addr_t dma_map,
 				       u32 *fw_stats_ctx_id)
 {
+	struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx;
 	struct hwrm_stat_ctx_alloc_output resp = {0};
 	struct hwrm_stat_ctx_alloc_input req = {0};
 	struct bnxt_en_dev *en_dev = rdev->en_dev;
 	bnxt_re_init_hwrm_hdr(rdev, (void *)&req, HWRM_STAT_CTX_ALLOC, -1, -1);
 	req.update_period_ms = cpu_to_le32(1000);
 	req.stats_dma_addr = cpu_to_le64(dma_map);
-	req.stats_dma_length = cpu_to_le16(sizeof(struct ctx_hw_stats_ext));
+	req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size);
 	req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE;
 	bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
 			    sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);

drivers/infiniband/hw/bnxt_re/qplib_res.c+4−6

 static void bnxt_qplib_free_stats_ctx(struct pci_dev *pdev,
 				      struct bnxt_qplib_stats *stats);
 static int bnxt_qplib_alloc_stats_ctx(struct pci_dev *pdev,
+				      struct bnxt_qplib_chip_ctx *cctx,
 				      struct bnxt_qplib_stats *stats);
 /* PBL */
 		goto fail;
 stats_alloc:
 	/* Stats */
-	rc = bnxt_qplib_alloc_stats_ctx(res->pdev, &ctx->stats);
+	rc = bnxt_qplib_alloc_stats_ctx(res->pdev, res->cctx, &ctx->stats);
 	if (rc)
 		goto fail;
 }
 static int bnxt_qplib_alloc_stats_ctx(struct pci_dev *pdev,
+				      struct bnxt_qplib_chip_ctx *cctx,
 				      struct bnxt_qplib_stats *stats)
 {
 	memset(stats, 0, sizeof(*stats));
 	stats->fw_id = -1;
-	/* 128 byte aligned context memory is required only for 57500.
+	stats->size = cctx->hw_stats_size;
-	 * However making this unconditional, it does not harm previous
-	 * generation.
-	 */
-	stats->size = ALIGN(sizeof(struct ctx_hw_stats), 128);
 	stats->dma = dma_alloc_coherent(&pdev->dev, stats->size,
 					&stats->dma_map, GFP_KERNEL);
 	if (!stats->dma) {

drivers/infiniband/hw/bnxt_re/qplib_res.h+1−0

@@ -54,6 +54,7 @@ struct bnxt_qplib_chip_ctx { · 53 unmodified lines
54	u16 chip_num;	54	u16 chip_num;
55	u8 chip_rev;	55	u8 chip_rev;
56	u8 chip_metal;	56	u8 chip_metal;
		57	u16 hw_stats_size;
57	struct bnxt_qplib_drv_modes modes;	58	struct bnxt_qplib_drv_modes modes;
58	};	59	};
59		60

drivers/infiniband/hw/irdma/ctrl.c+5−8

  * parses fpm commit info and copy base value
  * of hmc objects in hmc_info
  */
-static enum irdma_status_code
+static void
 irdma_sc_parse_fpm_commit_buf(struct irdma_sc_dev *dev, __le64 *buf,
 			      struct irdma_hmc_obj_info *info, u32 *sd)
 {
 	else
 		*sd = (u32)(size >> 21);
-	return 0;
 }
 /**
  * @dev: sc device struct
  * @count: allocate count
  */
-enum irdma_status_code irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count)
+void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count)
 {
 	writel(count, dev->hw_regs[IRDMA_AEQALLOC]);
-	return 0;
 }
 /**
 	ret_code = irdma_sc_commit_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id,
 					   &commit_fpm_mem, true, wait_type);
 	if (!ret_code)
-		ret_code = irdma_sc_parse_fpm_commit_buf(dev, dev->fpm_commit_buf,
+		irdma_sc_parse_fpm_commit_buf(dev, dev->fpm_commit_buf,
-							 hmc_info->hmc_obj,
+					      hmc_info->hmc_obj,
-							 &hmc_info->sd_table.sd_cnt);
+					      &hmc_info->sd_table.sd_cnt);
 	print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16,
 			     8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE,
 			     false);

drivers/infiniband/hw/irdma/hw.c+2−9

  * irdma_set_hw_rsrc - set hw memory resources.
  * @rf: RDMA PCI function
  */
-static u32 irdma_set_hw_rsrc(struct irdma_pci_f *rf)
+static void irdma_set_hw_rsrc(struct irdma_pci_f *rf)
 {
 	rf->allocated_qps = (void *)(rf->mem_rsrc +
 		   (sizeof(struct irdma_arp_entry) * rf->arp_table_size));
 	spin_lock_init(&rf->arp_lock);
 	spin_lock_init(&rf->qptable_lock);
 	spin_lock_init(&rf->qh_list_lock);
-	return 0;
 }
 /**
 	rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc;
-	ret = irdma_set_hw_rsrc(rf);
+	irdma_set_hw_rsrc(rf);
-	if (ret)
-		goto set_hw_rsrc_fail;
 	set_bit(0, rf->allocated_mrs);
 	set_bit(0, rf->allocated_qps);
 	return 0;
-set_hw_rsrc_fail:
-	kfree(rf->mem_rsrc);
-	rf->mem_rsrc = NULL;
 mem_rsrc_kzalloc_fail:
 	kfree(rf->allocated_ws_nodes);
 	rf->allocated_ws_nodes = NULL;

drivers/infiniband/hw/irdma/main.c+6−3

 	pr_debug("INIT: Gen2 PF[%d] device remove success\n", PCI_FUNC(pf->pdev->devfn));
 }
-static void irdma_fill_device_info(struct irdma_device *iwdev, struct ice_pf *pf)
+static void irdma_fill_device_info(struct irdma_device *iwdev, struct ice_pf *pf,
+				   struct ice_vsi *vsi)
 {
 	struct irdma_pci_f *rf = iwdev->rf;
-	struct ice_vsi *vsi = ice_get_main_vsi(pf);
 	rf->cdev = pf;
 	rf->gen_ops.register_qset = irdma_lan_register_qset;
 							    struct iidc_auxiliary_dev,
 							    adev);
 	struct ice_pf *pf = iidc_adev->pf;
+	struct ice_vsi *vsi = ice_get_main_vsi(pf);
 	struct iidc_qos_params qos_info = {};
 	struct irdma_device *iwdev;
 	struct irdma_pci_f *rf;
 	struct irdma_l2params l2params = {};
 	int err;
+	if (!vsi)
+		return -EIO;
 	iwdev = ib_alloc_device(irdma_device, ibdev);
 	if (!iwdev)
 		return -ENOMEM;
 		return -ENOMEM;
 	}
-	irdma_fill_device_info(iwdev, pf);
+	irdma_fill_device_info(iwdev, pf, vsi);
 	rf = iwdev->rf;
 	if (irdma_ctrl_init_hw(rf)) {

drivers/infiniband/hw/irdma/type.h+1−2

@@ -1222,8 +1222,7 @@ enum irdma_status_code irdma_sc_aeq_init(struct irdma_sc_aeq *aeq, · 1221 unmodified lines
1222	struct irdma_aeq_init_info *info);	1222	struct irdma_aeq_init_info *info);
1223	enum irdma_status_code irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq,	1223	enum irdma_status_code irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq,
1224	struct irdma_aeqe_info *info);	1224	struct irdma_aeqe_info *info);
1225	enum irdma_status_code irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev,	1225	void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count);
1226	u32 count);
1227		1226
1228	void irdma_sc_pd_init(struct irdma_sc_dev dev, struct irdma_sc_pd pd, u32 pd_id,	1227	void irdma_sc_pd_init(struct irdma_sc_dev dev, struct irdma_sc_pd pd, u32 pd_id,
1229	int abi_ver);	1228	int abi_ver);

drivers/infiniband/hw/irdma/uk.c+1−4

 enum irdma_status_code irdma_uk_post_receive(struct irdma_qp_uk *qp,
 					     struct irdma_post_rq_info *info)
 {
-	u32 total_size = 0, wqe_idx, i, byte_off;
+	u32 wqe_idx, i, byte_off;
 	u32 addl_frag_cnt;
 	__le64 *wqe;
 	u64 hdr;
 	if (qp->max_rq_frag_cnt < info->num_sges)
 		return IRDMA_ERR_INVALID_FRAG_COUNT;
-	for (i = 0; i < info->num_sges; i++)
-		total_size += info->sg_list[i].len;
 	wqe = irdma_qp_get_next_recv_wqe(qp, &wqe_idx);
 	if (!wqe)
 		return IRDMA_ERR_QP_TOOMANY_WRS_POSTED;

drivers/infiniband/hw/irdma/verbs.c+2−4

  * @iwqp: qp ptr
  * @init_info: initialize info to return
  */
-static int irdma_setup_virt_qp(struct irdma_device *iwdev,
+static void irdma_setup_virt_qp(struct irdma_device *iwdev,
 			       struct irdma_qp *iwqp,
 			       struct irdma_qp_init_info *init_info)
 {
 		init_info->sq_pa = qpmr->sq_pbl.addr;
 		init_info->rq_pa = qpmr->rq_pbl.addr;
 	}
-	return 0;
 }
 /**
 			}
 		}
 		init_info.qp_uk_init_info.abi_ver = iwpd->sc_pd.abi_ver;
-		err_code = irdma_setup_virt_qp(iwdev, iwqp, &init_info);
+		irdma_setup_virt_qp(iwdev, iwqp, &init_info);
 	} else {
 		init_info.qp_uk_init_info.abi_ver = IRDMA_ABI_VER;
 		err_code = irdma_setup_kmode_qp(iwdev, iwqp, &init_info, init_attr);

drivers/infiniband/sw/rxe/rxe_mr.c+17−10

 	int			num_buf;
 	void			*vaddr;
 	int err;
+	int i;
 	umem = ib_umem_get(pd->ibpd.device, start, length, access);
 	if (IS_ERR(umem)) {
-		pr_warn("err %d from rxe_umem_get\n",
+		pr_warn("%s: Unable to pin memory region err = %d\n",
-			(int)PTR_ERR(umem));
+			__func__, (int)PTR_ERR(umem));
 		err = PTR_ERR(umem);
-		goto err1;
+		goto err_out;
 	}
 	mr->umem = umem;
 	err = rxe_mr_alloc(mr, num_buf);
 	if (err) {
-		pr_warn("err %d from rxe_mr_alloc\n", err);
+		pr_warn("%s: Unable to allocate memory for map\n",
-		ib_umem_release(umem);
+				__func__);
-		goto err1;
+		goto err_release_umem;
 	}
 	mr->page_shift = PAGE_SHIFT;
 			vaddr = page_address(sg_page_iter_page(&sg_iter));
 			if (!vaddr) {
-				pr_warn("null vaddr\n");
+				pr_warn("%s: Unable to get virtual address\n",
-				ib_umem_release(umem);
+						__func__);
 				err = -ENOMEM;
-				goto err1;
+				goto err_cleanup_map;
 			}
 			buf->addr = (uintptr_t)vaddr;
 	return 0;
-err1:
+err_cleanup_map:
+	for (i = 0; i < mr->num_map; i++)
+		kfree(mr->map[i]);
+	kfree(mr->map);
+err_release_umem:
+	ib_umem_release(umem);
+err_out:
 	return err;
 }

drivers/media/pci/intel/ipu3/cio2-bridge.c+2−4

 	int ret;
 	for_each_acpi_dev_match(adev, cfg->hid, NULL, -1) {
-		if (!adev->status.enabled) {
+		if (!adev->status.enabled)
-			acpi_dev_put(adev);
 			continue;
-		}
 		if (bridge->n_sensors >= CIO2_NUM_PORTS) {
 			acpi_dev_put(adev);
 		}
 		sensor = &bridge->sensors[bridge->n_sensors];
-		sensor->adev = adev;
 		strscpy(sensor->name, cfg->hid, sizeof(sensor->name));
 		ret = cio2_bridge_read_acpi_buffer(adev, "SSDB",
 			goto err_free_swnodes;
 		}
+		sensor->adev = acpi_dev_get(adev);
 		adev->fwnode.secondary = fwnode;
 		dev_info(&cio2->dev, "Found supported sensor %s\n",

drivers/media/pci/ngene/ngene-core.c+1−1

@@ -385,7 +385,7 @@ static int ngene_command_config_free_buf(struct ngene dev, u8 config) · 384 unmodified lines
385		385
386	com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;	386	com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
387	com.cmd.hdr.Length = 6;	387	com.cmd.hdr.Length = 6;
388	memcpy(&com.cmd.ConfigureBuffers.config, config, 6);	388	memcpy(&com.cmd.ConfigureFreeBuffers.config, config, 6);
389	com.in_len = 6;	389	com.in_len = 6;
390	com.out_len = 0;	390	com.out_len = 0;
391		391

drivers/media/pci/ngene/ngene.h+8−6

@@ -407,12 +407,14 @@ enum _BUFFER_CONFIGS { · 406 unmodified lines
407		407
408	struct FW_CONFIGURE_FREE_BUFFERS {	408	struct FW_CONFIGURE_FREE_BUFFERS {
409	struct FW_HEADER hdr;	409	struct FW_HEADER hdr;
410	u8 UVI1_BufferLength;	410	struct {
411	u8 UVI2_BufferLength;	411	u8 UVI1_BufferLength;
412	u8 TVO_BufferLength;	412	u8 UVI2_BufferLength;
413	u8 AUD1_BufferLength;	413	u8 TVO_BufferLength;
414	u8 AUD2_BufferLength;	414	u8 AUD1_BufferLength;
415	u8 TVA_BufferLength;	415	u8 AUD2_BufferLength;
		416	u8 TVA_BufferLength;
		417	} __packed config;
416	} __attribute__ ((__packed__));	418	} __attribute__ ((__packed__));
417		419
418	struct FW_CONFIGURE_UART {	420	struct FW_CONFIGURE_UART {

drivers/misc/eeprom/at24.c+7−10

 	}
 	/*
-	 * If the 'label' property is not present for the AT24 EEPROM,
+	 * We initialize nvmem_config.id to NVMEM_DEVID_AUTO even if the
-	 * then nvmem_config.id is initialised to NVMEM_DEVID_AUTO,
+	 * label property is set as some platform can have multiple eeproms
-	 * and this will append the 'devid' to the name of the NVMEM
+	 * with same label and we can not register each of those with same
-	 * device. This is purely legacy and the AT24 driver has always
+	 * label. Failing to register those eeproms trigger cascade failure
-	 * defaulted to this. However, if the 'label' property is
+	 * on such platform.
-	 * present then this means that the name is specified by the
-	 * firmware and this name should be used verbatim and so it is
-	 * not necessary to append the 'devid'.
 	 */
+	nvmem_config.id = NVMEM_DEVID_AUTO;
 	if (device_property_present(dev, "label")) {
-		nvmem_config.id = NVMEM_DEVID_NONE;
 		err = device_property_read_string(dev, "label",
 						  &nvmem_config.name);
 		if (err)
 			return err;
 	} else {
-		nvmem_config.id = NVMEM_DEVID_AUTO;
 		nvmem_config.name = dev_name(dev);
 	}

drivers/mmc/core/block.c+21−14

@@ -28,6 +28,7 @@ · 27 unmodified lines
28	#include <linux/errno.h>	28	#include <linux/errno.h>
29	#include <linux/hdreg.h>	29	#include <linux/hdreg.h>
30	#include <linux/kdev_t.h>	30	#include <linux/kdev_t.h>
		31	#include <linux/kref.h>
31	#include <linux/blkdev.h>	32	#include <linux/blkdev.h>
32	#include <linux/cdev.h>	33	#include <linux/cdev.h>
33	#include <linux/mutex.h>	34	#include <linux/mutex.h>
@@ -111,7 +112,7 @@ struct mmc_blk_data { · 77 unmodified lines
111	#define MMC_BLK_CMD23 (1 << 0) /* Can do SET_BLOCK_COUNT for multiblock */	112	#define MMC_BLK_CMD23 (1 << 0) /* Can do SET_BLOCK_COUNT for multiblock */
112	#define MMC_BLK_REL_WR (1 << 1) /* MMC Reliable write support */	113	#define MMC_BLK_REL_WR (1 << 1) /* MMC Reliable write support */
113		114
114	unsigned int usage;	115	struct kref kref;
115	unsigned int read_only;	116	unsigned int read_only;
116	unsigned int part_type;	117	unsigned int part_type;
117	unsigned int reset_done;	118	unsigned int reset_done;
@@ -181,10 +182,8 @@ static struct mmc_blk_data mmc_blk_get(struct gendisk disk) · 63 unmodified lines
181		182
182	mutex_lock(&open_lock);	183	mutex_lock(&open_lock);
183	md = disk->private_data;	184	md = disk->private_data;
184	if (md && md->usage == 0)	185	if (md && !kref_get_unless_zero(&md->kref))
185	md = NULL;	186	md = NULL;
186	if (md)
187	md->usage++;
188	mutex_unlock(&open_lock);	187	mutex_unlock(&open_lock);
189		188
190	return md;	189	return md;
@@ -196,18 +195,25 @@ static inline int mmc_get_devidx(struct gendisk *disk) · 5 unmodified lines
196	return devidx;	195	return devidx;
197	}	196	}
198		197
199	static void mmc_blk_put(struct mmc_blk_data *md)	198	static void mmc_blk_kref_release(struct kref *ref)
200	{	199	{
201	mutex_lock(&open_lock);	200	struct mmc_blk_data *md = container_of(ref, struct mmc_blk_data, kref);
202	md->usage--;	201	int devidx;
203	if (md->usage == 0) {
204	int devidx = mmc_get_devidx(md->disk);
205		202
206	ida_simple_remove(&mmc_blk_ida, devidx);	203	devidx = mmc_get_devidx(md->disk);
207	put_disk(md->disk);	204	ida_simple_remove(&mmc_blk_ida, devidx);
208	kfree(md);	205
209	}	206	mutex_lock(&open_lock);
		207	md->disk->private_data = NULL;
210	mutex_unlock(&open_lock);	208	mutex_unlock(&open_lock);
		209
		210	put_disk(md->disk);
		211	kfree(md);
		212	}
		213
		214	static void mmc_blk_put(struct mmc_blk_data *md)
		215	{
		216	kref_put(&md->kref, mmc_blk_kref_release);
211	}	217	}
212		218
213	static ssize_t power_ro_lock_show(struct device *dev,	219	static ssize_t power_ro_lock_show(struct device *dev,
@@ -2327,7 +2333,8 @@ static struct mmc_blk_data mmc_blk_alloc_req(struct mmc_card card, · 2113 unmodified lines
2327		2333
2328	INIT_LIST_HEAD(&md->part);	2334	INIT_LIST_HEAD(&md->part);
2329	INIT_LIST_HEAD(&md->rpmbs);	2335	INIT_LIST_HEAD(&md->rpmbs);
2330	md->usage = 1;	2336	kref_init(&md->kref);
		2337
2331	md->queue.blkdata = md;	2338	md->queue.blkdata = md;
2332		2339
2333	md->disk->major = MMC_BLOCK_MAJOR;	2340	md->disk->major = MMC_BLOCK_MAJOR;

drivers/mmc/core/host.c+10−10

 {
 	struct mmc_host *host = cls_dev_to_mmc_host(dev);
 	wakeup_source_unregister(host->ws);
-	ida_simple_remove(&mmc_host_ida, host->index);
+	if (of_alias_get_id(host->parent->of_node, "mmc") < 0)
+		ida_simple_remove(&mmc_host_ida, host->index);
 	kfree(host);
 }
  */
 struct mmc_host *mmc_alloc_host(int extra, struct device *dev)
 {
-	int err;
+	int index;
 	struct mmc_host *host;
 	int alias_id, min_idx, max_idx;
 	alias_id = of_alias_get_id(dev->of_node, "mmc");
 	if (alias_id >= 0) {
-		min_idx = alias_id;
+		index = alias_id;
-		max_idx = alias_id + 1;
 	} else {
 		min_idx = mmc_first_nonreserved_index();
 		max_idx = 0;
-	}
-	err = ida_simple_get(&mmc_host_ida, min_idx, max_idx, GFP_KERNEL);
+		index = ida_simple_get(&mmc_host_ida, min_idx, max_idx, GFP_KERNEL);
-	if (err < 0) {
+		if (index < 0) {
-		kfree(host);
+			kfree(host);
-		return NULL;
+			return NULL;
+		}
 	}
-	host->index = err;
+	host->index = index;
 	dev_set_name(&host->class_dev, "mmc%d", host->index);
 	host->ws = wakeup_source_register(NULL, dev_name(&host->class_dev));

drivers/net/bonding/bond_main.c+2−0

 		return bond_event_changename(event_bond);
 	case NETDEV_UNREGISTER:
 		bond_remove_proc_entry(event_bond);
+#ifdef CONFIG_XFRM_OFFLOAD
 		xfrm_dev_state_flush(dev_net(bond_dev), bond_dev, true);
+#endif /* CONFIG_XFRM_OFFLOAD */
 		break;
 	case NETDEV_REGISTER:
 		bond_create_proc_entry(event_bond);

drivers/net/can/spi/hi311x.c+1−1

@@ -218,7 +218,7 @@ static int hi3110_spi_trans(struct spi_device *spi, int len) · 217 unmodified lines
218	return ret;	218	return ret;
219	}	219	}
220		220
221	static u8 hi3110_cmd(struct spi_device *spi, u8 command)	221	static int hi3110_cmd(struct spi_device *spi, u8 command)
222	{	222	{
223	struct hi3110_priv *priv = spi_get_drvdata(spi);	223	struct hi3110_priv *priv = spi_get_drvdata(spi);
224		224

drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c+1−0

@@ -2300,6 +2300,7 @@ static irqreturn_t mcp251xfd_irq(int irq, void *dev_id) · 2299 unmodified lines
2300	err, priv->regs_status.intf);	2300	err, priv->regs_status.intf);
2301	mcp251xfd_dump(priv);	2301	mcp251xfd_dump(priv);
2302	mcp251xfd_chip_interrupts_disable(priv);	2302	mcp251xfd_chip_interrupts_disable(priv);
		2303	mcp251xfd_timestamp_stop(priv);
2303		2304
2304	return handled;	2305	return handled;
2305	}	2306	}

drivers/net/can/usb/ems_usb.c+13−1

 	unsigned int free_slots; /* remember number of available slots */
 	struct ems_cpc_msg active_params; /* active controller parameters */
+	void *rxbuf[MAX_RX_URBS];
+	dma_addr_t rxbuf_dma[MAX_RX_URBS];
 };
 static void ems_usb_read_interrupt_callback(struct urb *urb)
 	for (i = 0; i < MAX_RX_URBS; i++) {
 		struct urb *urb = NULL;
 		u8 *buf = NULL;
+		dma_addr_t buf_dma;
 		/* create a URB, and a buffer for it */
 		urb = usb_alloc_urb(0, GFP_KERNEL);
 		}
 		buf = usb_alloc_coherent(dev->udev, RX_BUFFER_SIZE, GFP_KERNEL,
-					 &urb->transfer_dma);
+					 &buf_dma);
 		if (!buf) {
 			netdev_err(netdev, "No memory left for USB buffer\n");
 			usb_free_urb(urb);
 			break;
 		}
+		urb->transfer_dma = buf_dma;
 		usb_fill_bulk_urb(urb, dev->udev, usb_rcvbulkpipe(dev->udev, 2),
 				  buf, RX_BUFFER_SIZE,
 				  ems_usb_read_bulk_callback, dev);
 			break;
 		}
+		dev->rxbuf[i] = buf;
+		dev->rxbuf_dma[i] = buf_dma;
 		/* Drop reference, USB core will take care of freeing it */
 		usb_free_urb(urb);
 	}
 	usb_kill_anchored_urbs(&dev->rx_submitted);
+	for (i = 0; i < MAX_RX_URBS; ++i)
+		usb_free_coherent(dev->udev, RX_BUFFER_SIZE,
+				  dev->rxbuf[i], dev->rxbuf_dma[i]);
 	usb_kill_anchored_urbs(&dev->tx_submitted);
 	atomic_set(&dev->active_tx_urbs, 0);

drivers/net/can/usb/esd_usb2.c+15−1

 	int net_count;
 	u32 version;
 	int rxinitdone;
+	void *rxbuf[MAX_RX_URBS];
+	dma_addr_t rxbuf_dma[MAX_RX_URBS];
 };
 struct esd_usb2_net_priv {
 	for (i = 0; i < MAX_RX_URBS; i++) {
 		struct urb *urb = NULL;
 		u8 *buf = NULL;
+		dma_addr_t buf_dma;
 		/* create a URB, and a buffer for it */
 		urb = usb_alloc_urb(0, GFP_KERNEL);
 		}
 		buf = usb_alloc_coherent(dev->udev, RX_BUFFER_SIZE, GFP_KERNEL,
-					 &urb->transfer_dma);
+					 &buf_dma);
 		if (!buf) {
 			dev_warn(dev->udev->dev.parent,
 				 "No memory left for USB buffer\n");
 			goto freeurb;
 		}
+		urb->transfer_dma = buf_dma;
 		usb_fill_bulk_urb(urb, dev->udev,
 				  usb_rcvbulkpipe(dev->udev, 1),
 				  buf, RX_BUFFER_SIZE,
 			usb_unanchor_urb(urb);
 			usb_free_coherent(dev->udev, RX_BUFFER_SIZE, buf,
 					  urb->transfer_dma);
+			goto freeurb;
 		}
+		dev->rxbuf[i] = buf;
+		dev->rxbuf_dma[i] = buf_dma;
 freeurb:
 		/* Drop reference, USB core will take care of freeing it */
 		usb_free_urb(urb);
 	int i, j;
 	usb_kill_anchored_urbs(&dev->rx_submitted);
+	for (i = 0; i < MAX_RX_URBS; ++i)
+		usb_free_coherent(dev->udev, RX_BUFFER_SIZE,
+				  dev->rxbuf[i], dev->rxbuf_dma[i]);
 	for (i = 0; i < dev->net_count; i++) {
 		priv = dev->nets[i];
 		if (priv) {

drivers/net/can/usb/mcba_usb.c+2−0

@@ -653,6 +653,8 @@ static int mcba_usb_start(struct mcba_priv *priv) · 652 unmodified lines
653	break;	653	break;
654	}	654	}
655		655
		656	urb->transfer_dma = buf_dma;
		657
656	usb_fill_bulk_urb(urb, priv->udev,	658	usb_fill_bulk_urb(urb, priv->udev,
657	usb_rcvbulkpipe(priv->udev, MCBA_USB_EP_IN),	659	usb_rcvbulkpipe(priv->udev, MCBA_USB_EP_IN),
658	buf, MCBA_USB_RX_BUFF_SIZE,	660	buf, MCBA_USB_RX_BUFF_SIZE,

drivers/net/can/usb/peak_usb/pcan_usb.c+6−4

 #define PCAN_USB_BERR_MASK	(PCAN_USB_ERR_RXERR | PCAN_USB_ERR_TXERR)
 /* identify bus event packets with rx/tx error counters */
-#define PCAN_USB_ERR_CNT		0x80
+#define PCAN_USB_ERR_CNT_DEC		0x00	/* counters are decreasing */
+#define PCAN_USB_ERR_CNT_INC		0x80	/* counters are increasing */
 /* private to PCAN-USB adapter */
 struct pcan_usb {
 	/* acccording to the content of the packet */
 	switch (ir) {
-	case PCAN_USB_ERR_CNT:
+	case PCAN_USB_ERR_CNT_DEC:
+	case PCAN_USB_ERR_CNT_INC:
 		/* save rx/tx error counters from in the device context */
-		pdev->bec.rxerr = mc->ptr[0];
+		pdev->bec.rxerr = mc->ptr[1];
-		pdev->bec.txerr = mc->ptr[1];
+		pdev->bec.txerr = mc->ptr[2];
 		break;
 	default:

drivers/net/can/usb/usb_8dev.c+13−2

@@ -137,7 +137,8 @@ struct usb_8dev_priv { · 136 unmodified lines
137	u8 *cmd_msg_buffer;	137	u8 *cmd_msg_buffer;
138		138
139	struct mutex usb_8dev_cmd_lock;	139	struct mutex usb_8dev_cmd_lock;
140		140	void *rxbuf[MAX_RX_URBS];
		141	dma_addr_t rxbuf_dma[MAX_RX_URBS];
141	};	142	};
142		143
143	/* tx frame */	144	/* tx frame */
@@ -733,6 +734,7 @@ static int usb_8dev_start(struct usb_8dev_priv *priv) · 589 unmodified lines
733	for (i = 0; i < MAX_RX_URBS; i++) {	734	for (i = 0; i < MAX_RX_URBS; i++) {
734	struct urb *urb = NULL;	735	struct urb *urb = NULL;
735	u8 *buf;	736	u8 *buf;
		737	dma_addr_t buf_dma;
736		738
737	/* create a URB, and a buffer for it */	739	/* create a URB, and a buffer for it */
738	urb = usb_alloc_urb(0, GFP_KERNEL);	740	urb = usb_alloc_urb(0, GFP_KERNEL);
@@ -742,7 +744,7 @@ static int usb_8dev_start(struct usb_8dev_priv *priv) · 3 unmodified lines
742	}	744	}
743		745
744	buf = usb_alloc_coherent(priv->udev, RX_BUFFER_SIZE, GFP_KERNEL,	746	buf = usb_alloc_coherent(priv->udev, RX_BUFFER_SIZE, GFP_KERNEL,
745	&urb->transfer_dma);	747	&buf_dma);
746	if (!buf) {	748	if (!buf) {
747	netdev_err(netdev, "No memory left for USB buffer\n");	749	netdev_err(netdev, "No memory left for USB buffer\n");
748	usb_free_urb(urb);	750	usb_free_urb(urb);
@@ -750,6 +752,8 @@ static int usb_8dev_start(struct usb_8dev_priv *priv) · 1 unmodified line
750	break;	752	break;
751	}	753	}
752		754
		755	urb->transfer_dma = buf_dma;
		756
753	usb_fill_bulk_urb(urb, priv->udev,	757	usb_fill_bulk_urb(urb, priv->udev,
754	usb_rcvbulkpipe(priv->udev,	758	usb_rcvbulkpipe(priv->udev,
755	USB_8DEV_ENDP_DATA_RX),	759	USB_8DEV_ENDP_DATA_RX),
@@ -767,6 +771,9 @@ static int usb_8dev_start(struct usb_8dev_priv *priv) · 11 unmodified lines
767	break;	771	break;
768	}	772	}
769		773
		774	priv->rxbuf[i] = buf;
		775	priv->rxbuf_dma[i] = buf_dma;
		776
770	/* Drop reference, USB core will take care of freeing it */	777	/* Drop reference, USB core will take care of freeing it */
771	usb_free_urb(urb);	778	usb_free_urb(urb);
772	}	779	}
@@ -836,6 +843,10 @@ static void unlink_all_urbs(struct usb_8dev_priv *priv) · 63 unmodified lines
836		843
837	usb_kill_anchored_urbs(&priv->rx_submitted);	844	usb_kill_anchored_urbs(&priv->rx_submitted);
838		845
		846	for (i = 0; i < MAX_RX_URBS; ++i)
		847	usb_free_coherent(priv->udev, RX_BUFFER_SIZE,
		848	priv->rxbuf[i], priv->rxbuf_dma[i]);
		849
839	usb_kill_anchored_urbs(&priv->tx_submitted);	850	usb_kill_anchored_urbs(&priv->tx_submitted);
840	atomic_set(&priv->active_tx_urbs, 0);	851	atomic_set(&priv->active_tx_urbs, 0);
841		852

drivers/net/dsa/mt7530.c+2−0

@@ -366,6 +366,8 @@ mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, · 365 unmodified lines
366	int i;	366	int i;
367		367
368	reg[1] \|= vid & CVID_MASK;	368	reg[1] \|= vid & CVID_MASK;
		369	if (vid > 1)
		370	reg[1] \|= ATA2_IVL;
369	reg[2] \|= (aging & AGE_TIMER_MASK) << AGE_TIMER;	371	reg[2] \|= (aging & AGE_TIMER_MASK) << AGE_TIMER;
370	reg[2] \|= (port_mask & PORT_MAP_MASK) << PORT_MAP;	372	reg[2] \|= (port_mask & PORT_MAP_MASK) << PORT_MAP;
371	/* STATIC_ENT indicate that entry is static wouldn't	373	/* STATIC_ENT indicate that entry is static wouldn't

drivers/net/dsa/mt7530.h+1−0

@@ -79,6 +79,7 @@ enum mt753x_bpdu_port_fw { · 78 unmodified lines
79	#define STATIC_EMP 0	79	#define STATIC_EMP 0
80	#define STATIC_ENT 3	80	#define STATIC_ENT 3
81	#define MT7530_ATA2 0x78	81	#define MT7530_ATA2 0x78
		82	#define ATA2_IVL BIT(15)
82		83
83	/* Register for address table write data */	84	/* Register for address table write data */
84	#define MT7530_ATWD 0x7c	85	#define MT7530_ATWD 0x7c

drivers/net/dsa/mv88e6xxx/Kconfig+1−1

@@ -12,7 +12,7 @@ config NET_DSA_MV88E6XXX · 11 unmodified lines
12	config NET_DSA_MV88E6XXX_PTP	12	config NET_DSA_MV88E6XXX_PTP
13	bool "PTP support for Marvell 88E6xxx"	13	bool "PTP support for Marvell 88E6xxx"
14	default n	14	default n
15	depends on PTP_1588_CLOCK	15	depends on NET_DSA_MV88E6XXX && PTP_1588_CLOCK
16	help	16	help
17	Say Y to enable PTP hardware timestamping on Marvell 88E6xxx switch	17	Say Y to enable PTP hardware timestamping on Marvell 88E6xxx switch
18	chips that support it.	18	chips that support it.

drivers/net/dsa/mv88e6xxx/chip.c+1−1

@@ -2155,7 +2155,7 @@ static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, · 2154 unmodified lines
2155	int i, err;	2155	int i, err;
2156		2156
2157	if (!vid)	2157	if (!vid)
2158	return -EOPNOTSUPP;	2158	return 0;
2159		2159
2160	err = mv88e6xxx_vtu_get(chip, vid, &vlan);	2160	err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2161	if (err)	2161	if (err)

drivers/net/dsa/sja1105/sja1105_main.c+6−0

 		if (dsa_is_cpu_port(ds, port))
 			v->pvid = true;
 		list_add(&v->list, &priv->dsa_8021q_vlans);
+		v = kmemdup(v, sizeof(*v), GFP_KERNEL);
+		if (!v)
+			return -ENOMEM;
+		list_add(&v->list, &priv->bridge_vlans);
 	}
 	((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid;

drivers/net/ethernet/broadcom/bnxt/bnxt.c+64−26

 	if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
 	    (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
-		u16 vlan_proto = tpa_info->metadata >>
+		__be16 vlan_proto = htons(tpa_info->metadata >>
-			RX_CMP_FLAGS2_METADATA_TPID_SFT;
+					  RX_CMP_FLAGS2_METADATA_TPID_SFT);
 		u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
-		__vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
+		if (eth_type_vlan(vlan_proto)) {
+			__vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
+		} else {
+			dev_kfree_skb(skb);
+			return NULL;
+		}
 	}
 	skb_checksum_none_assert(skb);
 	    (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
 		u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
 		u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
-		u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
+		__be16 vlan_proto = htons(meta_data >>
+					  RX_CMP_FLAGS2_METADATA_TPID_SFT);
-		__vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
+		if (eth_type_vlan(vlan_proto)) {
+			__vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
+		} else {
+			dev_kfree_skb(skb);
+			goto next_rx;
+		}
 	}
 	skb_checksum_none_assert(skb);
 		bp->flags &= ~BNXT_FLAG_WOL_CAP;
 		if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
 			bp->flags |= BNXT_FLAG_WOL_CAP;
-		if (flags & FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED)
+		if (flags & FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED) {
 			__bnxt_hwrm_ptp_qcfg(bp);
+		} else {
+			kfree(bp->ptp_cfg);
+			bp->ptp_cfg = NULL;
+		}
 	} else {
 #ifdef CONFIG_BNXT_SRIOV
 		struct bnxt_vf_info *vf = &bp->vf;
 		}
 	}
-	bnxt_ptp_start(bp);
 	rc = bnxt_init_nic(bp, irq_re_init);
 	if (rc) {
 		netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
 {
 	int rc = 0;
+	if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
+		netdev_err(bp->dev, "A previous firmware reset has not completed, aborting half open\n");
+		rc = -ENODEV;
+		goto half_open_err;
+	}
 	rc = bnxt_alloc_mem(bp, false);
 	if (rc) {
 		netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
 	rc = bnxt_hwrm_if_change(bp, true);
 	if (rc)
 		return rc;
+	if (bnxt_ptp_init(bp)) {
+		netdev_warn(dev, "PTP initialization failed.\n");
+		kfree(bp->ptp_cfg);
+		bp->ptp_cfg = NULL;
+	}
 	rc = __bnxt_open_nic(bp, true, true);
 	if (rc) {
 		bnxt_hwrm_if_change(bp, false);
+		bnxt_ptp_clear(bp);
 	} else {
 		if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) {
 			if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
 {
 	struct bnxt *bp = netdev_priv(dev);
+	bnxt_ptp_clear(bp);
 	bnxt_hwmon_close(bp);
 	bnxt_close_nic(bp, true, true);
 	bnxt_hwrm_shutdown_link(bp);
 		bnxt_clear_int_mode(bp);
 		pci_disable_device(bp->pdev);
 	}
+	bnxt_ptp_clear(bp);
 	__bnxt_close_nic(bp, true, false);
 	bnxt_vf_reps_free(bp);
 	bnxt_clear_int_mode(bp);
 			  (bp->fw_reset_max_dsecs * HZ / 10));
 }
+static void bnxt_fw_reset_abort(struct bnxt *bp, int rc)
+{
+	clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
+	if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) {
+		bnxt_ulp_start(bp, rc);
+		bnxt_dl_health_status_update(bp, false);
+	}
+	bp->fw_reset_state = 0;
+	dev_close(bp->dev);
+}
 static void bnxt_fw_reset_task(struct work_struct *work)
 {
 	struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work);
-	int rc;
+	int rc = 0;
 	if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
 		netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n");
 		}
 		bp->fw_reset_timestamp = jiffies;
 		rtnl_lock();
+		if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
+			bnxt_fw_reset_abort(bp, rc);
+			rtnl_unlock();
+			return;
+		}
 		bnxt_fw_reset_close(bp);
 		if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
 			bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
 			if (val == 0xffff) {
 				if (bnxt_fw_reset_timeout(bp)) {
 					netdev_err(bp->dev, "Firmware reset aborted, PCI config space invalid\n");
+					rc = -ETIMEDOUT;
 					goto fw_reset_abort;
 				}
 				bnxt_queue_fw_reset_work(bp, HZ / 1000);
 		clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
 		if (pci_enable_device(bp->pdev)) {
 			netdev_err(bp->dev, "Cannot re-enable PCI device\n");
+			rc = -ENODEV;
 			goto fw_reset_abort;
 		}
 		pci_set_master(bp->pdev);
 		}
 		rc = bnxt_open(bp->dev);
 		if (rc) {
-			netdev_err(bp->dev, "bnxt_open_nic() failed\n");
+			netdev_err(bp->dev, "bnxt_open() failed during FW reset\n");
-			clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
+			bnxt_fw_reset_abort(bp, rc);
-			dev_close(bp->dev);
+			rtnl_unlock();
+			return;
 		}
 		bp->fw_reset_state = 0;
 		/* Make sure fw_reset_state is 0 before clearing the flag */
 		smp_mb__before_atomic();
 		clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
-		bnxt_ulp_start(bp, rc);
+		bnxt_ulp_start(bp, 0);
-		if (!rc)
+		bnxt_reenable_sriov(bp);
-			bnxt_reenable_sriov(bp);
 		bnxt_vf_reps_alloc(bp);
 		bnxt_vf_reps_open(bp);
 		bnxt_dl_health_recovery_done(bp);
 		netdev_err(bp->dev, "fw_health_status 0x%x\n", sts);
 	}
 fw_reset_abort:
-	clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
-	if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF)
-		bnxt_dl_health_status_update(bp, false);
-	bp->fw_reset_state = 0;
 	rtnl_lock();
-	dev_close(bp->dev);
+	bnxt_fw_reset_abort(bp, rc);
 	rtnl_unlock();
 }
 	if (BNXT_PF(bp))
 		devlink_port_type_clear(&bp->dl_port);
-	bnxt_ptp_clear(bp);
 	pci_disable_pcie_error_reporting(pdev);
 	unregister_netdev(dev);
 	clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
 				   rc);
 	}
-	if (bnxt_ptp_init(bp)) {
-		netdev_warn(dev, "PTP initialization failed.\n");
-		kfree(bp->ptp_cfg);
-		bp->ptp_cfg = NULL;
-	}
 	bnxt_inv_fw_health_reg(bp);
 	bnxt_dl_register(bp);
 	if (netif_running(netdev))
 		bnxt_close(netdev);
-	pci_disable_device(pdev);
+	if (pci_is_enabled(pdev))
+		pci_disable_device(pdev);
 	bnxt_free_ctx_mem(bp);
 	kfree(bp->ctx);
 	bp->ctx = NULL;

drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.c+9−1

 static int bnxt_ets_validate(struct bnxt *bp, struct ieee_ets *ets, u8 *tc)
 {
 	int total_ets_bw = 0;
+	bool zero = false;
 	u8 max_tc = 0;
 	int i;
 			break;
 		case IEEE_8021QAZ_TSA_ETS:
 			total_ets_bw += ets->tc_tx_bw[i];
+			zero = zero || !ets->tc_tx_bw[i];
 			break;
 		default:
 			return -ENOTSUPP;
 		}
 	}
-	if (total_ets_bw > 100)
+	if (total_ets_bw > 100) {
+		netdev_warn(bp->dev, "rejecting ETS config exceeding available bandwidth\n");
 		return -EINVAL;
+	}
+	if (zero && total_ets_bw == 100) {
+		netdev_warn(bp->dev, "rejecting ETS config starving a TC\n");
+		return -EINVAL;
+	}
 	if (max_tc >= bp->max_tc)
 		*tc = bp->max_tc;

drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c+14−17

@@ -353,6 +353,12 @@ static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info) · 352 unmodified lines
353		353
354	bnxt_ptp_get_current_time(bp);	354	bnxt_ptp_get_current_time(bp);
355	ptp->next_period = now + HZ;	355	ptp->next_period = now + HZ;
		356	if (time_after_eq(now, ptp->next_overflow_check)) {
		357	spin_lock_bh(&ptp->ptp_lock);
		358	timecounter_read(&ptp->tc);
		359	spin_unlock_bh(&ptp->ptp_lock);
		360	ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD;
		361	}
356	return HZ;	362	return HZ;
357	}	363	}
358		364
@@ -385,22 +391,6 @@ int bnxt_get_rx_ts_p5(struct bnxt bp, u64 ts, u32 pkt_ts) · 26 unmodified lines
385	return 0;	391	return 0;
386	}	392	}
387		393
388	void bnxt_ptp_start(struct bnxt *bp)
389	{
390	struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
391
392	if (!ptp)
393	return;
394
395	if (bp->flags & BNXT_FLAG_CHIP_P5) {
396	spin_lock_bh(&ptp->ptp_lock);
397	ptp->current_time = bnxt_refclk_read(bp, NULL);
398	WRITE_ONCE(ptp->old_time, ptp->current_time);
399	spin_unlock_bh(&ptp->ptp_lock);
400	ptp_schedule_worker(ptp->ptp_clock, 0);
401	}
402	}
403
404	static const struct ptp_clock_info bnxt_ptp_caps = {	394	static const struct ptp_clock_info bnxt_ptp_caps = {
405	.owner = THIS_MODULE,	395	.owner = THIS_MODULE,
406	.name = "bnxt clock",	396	.name = "bnxt clock",
@@ -439,6 +429,7 @@ int bnxt_ptp_init(struct bnxt *bp) · 32 unmodified lines
439	ptp->cc.shift = 0;	429	ptp->cc.shift = 0;
440	ptp->cc.mult = 1;	430	ptp->cc.mult = 1;
441		431
		432	ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD;
442	timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));	433	timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
443		434
444	ptp->ptp_info = bnxt_ptp_caps;	435	ptp->ptp_info = bnxt_ptp_caps;
@@ -450,7 +441,13 @@ int bnxt_ptp_init(struct bnxt *bp) · 5 unmodified lines
450	bnxt_unmap_ptp_regs(bp);	441	bnxt_unmap_ptp_regs(bp);
451	return err;	442	return err;
452	}	443	}
453		444	if (bp->flags & BNXT_FLAG_CHIP_P5) {
		445	spin_lock_bh(&ptp->ptp_lock);
		446	ptp->current_time = bnxt_refclk_read(bp, NULL);
		447	WRITE_ONCE(ptp->old_time, ptp->current_time);
		448	spin_unlock_bh(&ptp->ptp_lock);
		449	ptp_schedule_worker(ptp->ptp_clock, 0);
		450	}
454	return 0;	451	return 0;
455	}	452	}
456		453

drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h+4−1

 	u64			current_time;
 	u64			old_time;
 	unsigned long		next_period;
+	unsigned long		next_overflow_check;
+	/* 48-bit PHC overflows in 78 hours.  Check overflow every 19 hours. */
+	#define BNXT_PHC_OVERFLOW_PERIOD	(19 * 3600 * HZ)
 	u16			tx_seqid;
 	struct bnxt		*bp;
 	atomic_t		tx_avail;
 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr);
 int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb);
 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts);
-void bnxt_ptp_start(struct bnxt *bp);
 int bnxt_ptp_init(struct bnxt *bp);
 void bnxt_ptp_clear(struct bnxt *bp);
 #endif

drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c+5−4

 		if (!edev)
 			return ERR_PTR(-ENOMEM);
 		edev->en_ops = &bnxt_en_ops_tbl;
-		if (bp->flags & BNXT_FLAG_ROCEV1_CAP)
-			edev->flags |= BNXT_EN_FLAG_ROCEV1_CAP;
-		if (bp->flags & BNXT_FLAG_ROCEV2_CAP)
-			edev->flags |= BNXT_EN_FLAG_ROCEV2_CAP;
 		edev->net = dev;
 		edev->pdev = bp->pdev;
 		edev->l2_db_size = bp->db_size;
 		edev->l2_db_size_nc = bp->db_size;
 		bp->edev = edev;
 	}
+	edev->flags &= ~BNXT_EN_FLAG_ROCE_CAP;
+	if (bp->flags & BNXT_FLAG_ROCEV1_CAP)
+		edev->flags |= BNXT_EN_FLAG_ROCEV1_CAP;
+	if (bp->flags & BNXT_FLAG_ROCEV2_CAP)
+		edev->flags |= BNXT_EN_FLAG_ROCEV2_CAP;
 	return bp->edev;
 }
 EXPORT_SYMBOL(bnxt_ulp_probe);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c+1−1

@@ -420,7 +420,7 @@ static int cn23xx_pf_setup_global_input_regs(struct octeon_device *oct) · 419 unmodified lines
420	* bits 32:47 indicate the PVF num.	420	* bits 32:47 indicate the PVF num.
421	*/	421	*/
422	for (q_no = 0; q_no < ern; q_no++) {	422	for (q_no = 0; q_no < ern; q_no++) {
423	reg_val = oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS;	423	reg_val = (u64)oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS;
424		424
425	/* for VF assigned queues. */	425	/* for VF assigned queues. */
426	if (q_no < oct->sriov_info.pf_srn) {	426	if (q_no < oct->sriov_info.pf_srn) {

drivers/net/ethernet/dec/tulip/winbond-840.c+2−5

 	int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
 	void __iomem *ioaddr;
-	i = pci_enable_device(pdev);
+	i = pcim_enable_device(pdev);
 	if (i) return i;
 	pci_set_master(pdev);
 	ioaddr = pci_iomap(pdev, TULIP_BAR, netdev_res_size);
 	if (!ioaddr)
-		goto err_out_free_res;
+		goto err_out_netdev;
 	for (i = 0; i < 3; i++)
 		((__le16 *)dev->dev_addr)[i] = cpu_to_le16(eeprom_read(ioaddr, i));
 err_out_cleardev:
 	pci_iounmap(pdev, ioaddr);
-err_out_free_res:
-	pci_release_regions(pdev);
 err_out_netdev:
 	free_netdev (dev);
 	return -ENODEV;
 	if (dev) {
 		struct netdev_private *np = netdev_priv(dev);
 		unregister_netdev(dev);
-		pci_release_regions(pdev);
 		pci_iounmap(pdev, np->base_addr);
 		free_netdev(dev);
 	}

drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c+8−8

 	if (err)
 		return err;
-	err = dpaa2_switch_seed_bp(ethsw);
-	if (err)
-		goto err_free_dpbp;
 	err = dpaa2_switch_alloc_rings(ethsw);
 	if (err)
-		goto err_drain_dpbp;
+		goto err_free_dpbp;
 	err = dpaa2_switch_setup_dpio(ethsw);
 	if (err)
 		goto err_destroy_rings;
+	err = dpaa2_switch_seed_bp(ethsw);
+	if (err)
+		goto err_deregister_dpio;
 	err = dpsw_ctrl_if_enable(ethsw->mc_io, 0, ethsw->dpsw_handle);
 	if (err) {
 		dev_err(ethsw->dev, "dpsw_ctrl_if_enable err %d\n", err);
-		goto err_deregister_dpio;
+		goto err_drain_dpbp;
 	}
 	return 0;
+err_drain_dpbp:
+	dpaa2_switch_drain_bp(ethsw);
 err_deregister_dpio:
 	dpaa2_switch_free_dpio(ethsw);
 err_destroy_rings:
 	dpaa2_switch_destroy_rings(ethsw);
-err_drain_dpbp:
-	dpaa2_switch_drain_bp(ethsw);
 err_free_dpbp:
 	dpaa2_switch_free_dpbp(ethsw);

drivers/net/ethernet/freescale/fman/mac.c+1−0

@@ -524,6 +524,7 @@ static void setup_memac(struct mac_device *mac_dev) · 523 unmodified lines
524	\| SUPPORTED_Autoneg \	524	\| SUPPORTED_Autoneg \
525	\| SUPPORTED_Pause \	525	\| SUPPORTED_Pause \
526	\| SUPPORTED_Asym_Pause \	526	\| SUPPORTED_Asym_Pause \
		527	\| SUPPORTED_FIBRE \
527	\| SUPPORTED_MII)	528	\| SUPPORTED_MII)
528		529
529	static DEFINE_MUTEX(eth_lock);	530	static DEFINE_MUTEX(eth_lock);

drivers/net/ethernet/hisilicon/hip04_eth.c+3−3

drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h+5−2

 	u32 origin_mbx_msg;
 	bool received_resp;
 	int resp_status;
+	u16 match_id;
 	u8 additional_info[HCLGE_MBX_MAX_RESP_DATA_SIZE];
 };
 	u8 mbx_need_resp;
 	u8 rsv1[1];
 	u8 msg_len;
-	u8 rsv2[3];
+	u8 rsv2;
+	u16 match_id;
 	struct hclge_vf_to_pf_msg msg;
 };
 	u8 dest_vfid;
 	u8 rsv[3];
 	u8 msg_len;
-	u8 rsv1[3];
+	u8 rsv1;
+	u16 match_id;
 	struct hclge_pf_to_vf_msg msg;
 };

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c+6−2

 	if (ret)
 		return ret;
-	if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps))
+	if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) {
 		ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id,
 							!enable);
-	else if (!vport->vport_id)
+	} else if (!vport->vport_id) {
+		if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
+			enable = false;
 		ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
 						 HCLGE_FILTER_FE_INGRESS,
 						 enable, 0);
+	}
 	return ret;
 }

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c+1−0

@@ -47,6 +47,7 @@ static int hclge_gen_resp_to_vf(struct hclge_vport *vport, · 46 unmodified lines
47		47
48	resp_pf_to_vf->dest_vfid = vf_to_pf_req->mbx_src_vfid;	48	resp_pf_to_vf->dest_vfid = vf_to_pf_req->mbx_src_vfid;
49	resp_pf_to_vf->msg_len = vf_to_pf_req->msg_len;	49	resp_pf_to_vf->msg_len = vf_to_pf_req->msg_len;
		50	resp_pf_to_vf->match_id = vf_to_pf_req->match_id;
50		51
51	resp_pf_to_vf->msg.code = HCLGE_MBX_PF_VF_RESP;	52	resp_pf_to_vf->msg.code = HCLGE_MBX_PF_VF_RESP;
52	resp_pf_to_vf->msg.vf_mbx_msg_code = vf_to_pf_req->msg.code;	53	resp_pf_to_vf->msg.vf_mbx_msg_code = vf_to_pf_req->msg.code;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c+29−7

 #include "hclge_main.h"
 #include "hnae3.h"
+static int hclge_ptp_get_cycle(struct hclge_dev *hdev)
+{
+	struct hclge_ptp *ptp = hdev->ptp;
+	ptp->cycle.quo = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG) &
+			 HCLGE_PTP_CYCLE_QUO_MASK;
+	ptp->cycle.numer = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG);
+	ptp->cycle.den = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG);
+	if (ptp->cycle.den == 0) {
+		dev_err(&hdev->pdev->dev, "invalid ptp cycle denominator!\n");
+		return -EINVAL;
+	}
+	return 0;
+}
 static int hclge_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 {
 	struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp);
+	struct hclge_ptp_cycle *cycle = &hdev->ptp->cycle;
 	u64 adj_val, adj_base, diff;
 	unsigned long flags;
 	bool is_neg = false;
 		is_neg = true;
 	}
-	adj_base = HCLGE_PTP_CYCLE_ADJ_BASE * HCLGE_PTP_CYCLE_ADJ_UNIT;
+	adj_base = (u64)cycle->quo * (u64)cycle->den + (u64)cycle->numer;
 	adj_val = adj_base * ppb;
 	diff = div_u64(adj_val, 1000000000ULL);
 	/* This clock cycle is defined by three part: quotient, numerator
 	 * and denominator. For example, 2.5ns, the quotient is 2,
-	 * denominator is fixed to HCLGE_PTP_CYCLE_ADJ_UNIT, and numerator
+	 * denominator is fixed to ptp->cycle.den, and numerator
-	 * is 0.5 * HCLGE_PTP_CYCLE_ADJ_UNIT.
+	 * is 0.5 * ptp->cycle.den.
 	 */
-	quo = div_u64_rem(adj_val, HCLGE_PTP_CYCLE_ADJ_UNIT, &numerator);
+	quo = div_u64_rem(adj_val, cycle->den, &numerator);
 	spin_lock_irqsave(&hdev->ptp->lock, flags);
-	writel(quo, hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG);
+	writel(quo & HCLGE_PTP_CYCLE_QUO_MASK,
+	       hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG);
 	writel(numerator, hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG);
-	writel(HCLGE_PTP_CYCLE_ADJ_UNIT,
+	writel(cycle->den, hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG);
-	       hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG);
 	writel(HCLGE_PTP_CYCLE_ADJ_EN,
 	       hdev->ptp->io_base + HCLGE_PTP_CYCLE_CFG_REG);
 	spin_unlock_irqrestore(&hdev->ptp->lock, flags);
 		ret = hclge_ptp_create_clock(hdev);
 		if (ret)
 			return ret;
+		ret = hclge_ptp_get_cycle(hdev);
+		if (ret)
+			return ret;
 	}
 	ret = hclge_ptp_int_en(hdev, true);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h+8−2

 #define HCLGE_PTP_TIME_ADJ_REG		0x60
 #define HCLGE_PTP_TIME_ADJ_EN		BIT(0)
 #define HCLGE_PTP_CYCLE_QUO_REG		0x64
+#define HCLGE_PTP_CYCLE_QUO_MASK	GENMASK(7, 0)
 #define HCLGE_PTP_CYCLE_DEN_REG		0x68
 #define HCLGE_PTP_CYCLE_NUM_REG		0x6C
 #define HCLGE_PTP_CYCLE_CFG_REG		0x70
 #define HCLGE_PTP_CUR_TIME_SEC_L_REG	0x78
 #define HCLGE_PTP_CUR_TIME_NSEC_REG	0x7C
-#define HCLGE_PTP_CYCLE_ADJ_BASE	2
 #define HCLGE_PTP_CYCLE_ADJ_MAX		500000000
-#define HCLGE_PTP_CYCLE_ADJ_UNIT	100000000
 #define HCLGE_PTP_SEC_H_OFFSET		32u
 #define HCLGE_PTP_SEC_L_MASK		GENMASK(31, 0)
 #define HCLGE_PTP_FLAG_TX_EN		1
 #define HCLGE_PTP_FLAG_RX_EN		2
+struct hclge_ptp_cycle {
+	u32 quo;
+	u32 numer;
+	u32 den;
+};
 struct hclge_ptp {
 	struct hclge_dev *hdev;
 	struct ptp_clock *clock;
 	spinlock_t lock;	/* protects ptp registers */
 	u32 ptp_cfg;
 	u32 last_tx_seqid;
+	struct hclge_ptp_cycle cycle;
 	unsigned long tx_start;
 	unsigned long tx_cnt;
 	unsigned long tx_skipped;

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c+10−0

@@ -2641,6 +2641,16 @@ static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) · 2640 unmodified lines
2641		2641
2642	static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)	2642	static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
2643	{	2643	{
		2644	struct hnae3_handle *nic = &hdev->nic;
		2645	int ret;
		2646
		2647	ret = hclgevf_en_hw_strip_rxvtag(nic, true);
		2648	if (ret) {
		2649	dev_err(&hdev->pdev->dev,
		2650	"failed to enable rx vlan offload, ret = %d\n", ret);
		2651	return ret;
		2652	}
		2653
2644	return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,	2654	return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
2645	false);	2655	false);
2646	}	2656	}

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c+19−0

 	return resp_code ? -resp_code : 0;
 }
+#define HCLGEVF_MBX_MATCH_ID_START	1
 static void hclgevf_reset_mbx_resp_status(struct hclgevf_dev *hdev)
 {
 	/* this function should be called with mbx_resp.mbx_mutex held
 	hdev->mbx_resp.received_resp  = false;
 	hdev->mbx_resp.origin_mbx_msg = 0;
 	hdev->mbx_resp.resp_status    = 0;
+	hdev->mbx_resp.match_id++;
+	/* Update match_id and ensure the value of match_id is not zero */
+	if (hdev->mbx_resp.match_id == 0)
+		hdev->mbx_resp.match_id = HCLGEVF_MBX_MATCH_ID_START;
 	memset(hdev->mbx_resp.additional_info, 0, HCLGE_MBX_MAX_RESP_DATA_SIZE);
 }
 	if (need_resp) {
 		mutex_lock(&hdev->mbx_resp.mbx_mutex);
 		hclgevf_reset_mbx_resp_status(hdev);
+		req->match_id = hdev->mbx_resp.match_id;
 		status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 		if (status) {
 			dev_err(&hdev->pdev->dev,
 				resp->additional_info[i] = *temp;
 				temp++;
 			}
+			/* If match_id is not zero, it means PF support
+			 * match_id. If the match_id is right, VF get the
+			 * right response, otherwise ignore the response.
+			 * Driver will clear hdev->mbx_resp when send
+			 * next message which need response.
+			 */
+			if (req->match_id) {
+				if (req->match_id == resp->match_id)
+					resp->received_resp = true;
+			} else {
+				resp->received_resp = true;
+			}
 			break;
 		case HCLGE_MBX_LINK_STAT_CHANGE:
 		case HCLGE_MBX_ASSERTING_RESET:

drivers/net/ethernet/ibm/ibmvnic.c+1−1

 		tx_send_failed++;
 		tx_dropped++;
 		ret = NETDEV_TX_OK;
-		ibmvnic_tx_scrq_flush(adapter, tx_scrq);
 		goto out;
 	}
 		dev_kfree_skb_any(skb);
 		tx_send_failed++;
 		tx_dropped++;
+		ibmvnic_tx_scrq_flush(adapter, tx_scrq);
 		ret = NETDEV_TX_OK;
 		goto out;
 	}

drivers/net/ethernet/intel/i40e/i40e_ethtool.c+5−1

 	default:
 		/* if we got here and link is up something bad is afoot */
 		netdev_info(netdev,
-			    "WARNING: Link is up but PHY type 0x%x is not recognized.\n",
+			    "WARNING: Link is up but PHY type 0x%x is not recognized, or incorrect cable is in use\n",
 			    hw_link_info->phy_type);
 	}
 					dev_warn(&pf->pdev->dev,
 						 "Device configuration forbids SW from starting the LLDP agent.\n");
 					return -EINVAL;
+				case I40E_AQ_RC_EAGAIN:
+					dev_warn(&pf->pdev->dev,
+						 "Stop FW LLDP agent command is still being processed, please try again in a second.\n");
+					return -EBUSY;
 				default:
 					dev_warn(&pf->pdev->dev,
 						 "Starting FW LLDP agent failed: error: %s, %s\n",

drivers/net/ethernet/intel/i40e/i40e_main.c+37−24

@@ -4454,11 +4454,10 @@ int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, · 4453 unmodified lines
4454	}	4454	}
4455		4455
4456	/**	4456	/**
4457	* i40e_vsi_control_tx - Start or stop a VSI's rings	4457	* i40e_vsi_enable_tx - Start a VSI's rings
4458	* @vsi: the VSI being configured	4458	* @vsi: the VSI being configured
4459	* @enable: start or stop the rings
4460	**/	4459	**/
4461	static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)	4460	static int i40e_vsi_enable_tx(struct i40e_vsi *vsi)
4462	{	4461	{
4463	struct i40e_pf *pf = vsi->back;	4462	struct i40e_pf *pf = vsi->back;
4464	int i, pf_q, ret = 0;	4463	int i, pf_q, ret = 0;
@@ -4467,7 +4466,7 @@ static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable) · 2 unmodified lines
4467	for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {	4466	for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4468	ret = i40e_control_wait_tx_q(vsi->seid, pf,	4467	ret = i40e_control_wait_tx_q(vsi->seid, pf,
4469	pf_q,	4468	pf_q,
4470	false /is xdp/, enable);	4469	false /is xdp/, true);
4471	if (ret)	4470	if (ret)
4472	break;	4471	break;
4473		4472
@@ -4476,7 +4475,7 @@ static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable) · 2 unmodified lines
4476		4475
4477	ret = i40e_control_wait_tx_q(vsi->seid, pf,	4476	ret = i40e_control_wait_tx_q(vsi->seid, pf,
4478	pf_q + vsi->alloc_queue_pairs,	4477	pf_q + vsi->alloc_queue_pairs,
4479	true /is xdp/, enable);	4478	true /is xdp/, true);
4480	if (ret)	4479	if (ret)
4481	break;	4480	break;
4482	}	4481	}
@@ -4574,32 +4573,25 @@ int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable) · 91 unmodified lines
4574	}	4573	}
4575		4574
4576	/**	4575	/**
4577	* i40e_vsi_control_rx - Start or stop a VSI's rings	4576	* i40e_vsi_enable_rx - Start a VSI's rings
4578	* @vsi: the VSI being configured	4577	* @vsi: the VSI being configured
4579	* @enable: start or stop the rings
4580	**/	4578	**/
4581	static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)	4579	static int i40e_vsi_enable_rx(struct i40e_vsi *vsi)
4582	{	4580	{
4583	struct i40e_pf *pf = vsi->back;	4581	struct i40e_pf *pf = vsi->back;
4584	int i, pf_q, ret = 0;	4582	int i, pf_q, ret = 0;
4585		4583
4586	pf_q = vsi->base_queue;	4584	pf_q = vsi->base_queue;
4587	for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {	4585	for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4588	ret = i40e_control_wait_rx_q(pf, pf_q, enable);	4586	ret = i40e_control_wait_rx_q(pf, pf_q, true);
4589	if (ret) {	4587	if (ret) {
4590	dev_info(&pf->pdev->dev,	4588	dev_info(&pf->pdev->dev,
4591	"VSI seid %d Rx ring %d %sable timeout\n",	4589	"VSI seid %d Rx ring %d enable timeout\n",
4592	vsi->seid, pf_q, (enable ? "en" : "dis"));	4590	vsi->seid, pf_q);
4593	break;	4591	break;
4594	}	4592	}
4595	}	4593	}
4596		4594
4597	/* Due to HW errata, on Rx disable only, the register can indicate done
4598	* before it really is. Needs 50ms to be sure
4599	*/
4600	if (!enable)
4601	mdelay(50);
4602
4603	return ret;	4595	return ret;
4604	}	4596	}
4605		4597
@@ -4612,29 +4604,47 @@ int i40e_vsi_start_rings(struct i40e_vsi *vsi) · 6 unmodified lines
4612	int ret = 0;	4604	int ret = 0;
4613		4605
4614	/* do rx first for enable and last for disable */	4606	/* do rx first for enable and last for disable */
4615	ret = i40e_vsi_control_rx(vsi, true);	4607	ret = i40e_vsi_enable_rx(vsi);
4616	if (ret)	4608	if (ret)
4617	return ret;	4609	return ret;
4618	ret = i40e_vsi_control_tx(vsi, true);	4610	ret = i40e_vsi_enable_tx(vsi);
4619		4611
4620	return ret;	4612	return ret;
4621	}	4613	}
4622		4614
		4615	#define I40E_DISABLE_TX_GAP_MSEC 50
		4616
4623	/**	4617	/**
4624	* i40e_vsi_stop_rings - Stop a VSI's rings	4618	* i40e_vsi_stop_rings - Stop a VSI's rings
4625	* @vsi: the VSI being configured	4619	* @vsi: the VSI being configured
4626	**/	4620	**/
4627	void i40e_vsi_stop_rings(struct i40e_vsi *vsi)	4621	void i40e_vsi_stop_rings(struct i40e_vsi *vsi)
4628	{	4622	{
		4623	struct i40e_pf *pf = vsi->back;
		4624	int pf_q, err, q_end;
		4625
4629	/* When port TX is suspended, don't wait */	4626	/* When port TX is suspended, don't wait */
4630	if (test_bit(__I40E_PORT_SUSPENDED, vsi->back->state))	4627	if (test_bit(__I40E_PORT_SUSPENDED, vsi->back->state))
4631	return i40e_vsi_stop_rings_no_wait(vsi);	4628	return i40e_vsi_stop_rings_no_wait(vsi);
4632		4629
4633	/* do rx first for enable and last for disable	4630	q_end = vsi->base_queue + vsi->num_queue_pairs;
4634	* Ignore return value, we need to shutdown whatever we can	4631	for (pf_q = vsi->base_queue; pf_q < q_end; pf_q++)
4635	*/	4632	i40e_pre_tx_queue_cfg(&pf->hw, (u32)pf_q, false);
4636	i40e_vsi_control_tx(vsi, false);	4633
4637	i40e_vsi_control_rx(vsi, false);	4634	for (pf_q = vsi->base_queue; pf_q < q_end; pf_q++) {
		4635	err = i40e_control_wait_rx_q(pf, pf_q, false);
		4636	if (err)
		4637	dev_info(&pf->pdev->dev,
		4638	"VSI seid %d Rx ring %d dissable timeout\n",
		4639	vsi->seid, pf_q);
		4640	}
		4641
		4642	msleep(I40E_DISABLE_TX_GAP_MSEC);
		4643	pf_q = vsi->base_queue;
		4644	for (pf_q = vsi->base_queue; pf_q < q_end; pf_q++)
		4645	wr32(&pf->hw, I40E_QTX_ENA(pf_q), 0);
		4646
		4647	i40e_vsi_wait_queues_disabled(vsi);
4638	}	4648	}
4639		4649
4640	/**	4650	/**
@@ -7280,6 +7290,8 @@ static int i40e_validate_mqprio_qopt(struct i40e_vsi *vsi, · 2639 unmodified lines
7280	}	7290	}
7281	if (vsi->num_queue_pairs <	7291	if (vsi->num_queue_pairs <
7282	(mqprio_qopt->qopt.offset[i] + mqprio_qopt->qopt.count[i])) {	7292	(mqprio_qopt->qopt.offset[i] + mqprio_qopt->qopt.count[i])) {
		7293	dev_err(&vsi->back->pdev->dev,
		7294	"Failed to create traffic channel, insufficient number of queues.\n");
7283	return -EINVAL;	7295	return -EINVAL;
7284	}	7296	}
7285	if (sum_max_rate > i40e_get_link_speed(vsi)) {	7297	if (sum_max_rate > i40e_get_link_speed(vsi)) {
@@ -13261,6 +13273,7 @@ static const struct net_device_ops i40e_netdev_ops = { · 5975 unmodified lines
13261	.ndo_poll_controller = i40e_netpoll,	13273	.ndo_poll_controller = i40e_netpoll,
13262	#endif	13274	#endif
13263	.ndo_setup_tc = __i40e_setup_tc,	13275	.ndo_setup_tc = __i40e_setup_tc,
		13276	.ndo_select_queue = i40e_lan_select_queue,
13264	.ndo_set_features = i40e_set_features,	13277	.ndo_set_features = i40e_set_features,
13265	.ndo_set_vf_mac = i40e_ndo_set_vf_mac,	13278	.ndo_set_vf_mac = i40e_ndo_set_vf_mac,
13266	.ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,	13279	.ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,

drivers/net/ethernet/intel/i40e/i40e_txrx.c+50−0

@@ -3631,6 +3631,56 @@ dma_error: · 3630 unmodified lines
3631	return -1;	3631	return -1;
3632	}	3632	}
3633		3633
		3634	static u16 i40e_swdcb_skb_tx_hash(struct net_device *dev,
		3635	const struct sk_buff *skb,
		3636	u16 num_tx_queues)
		3637	{
		3638	u32 jhash_initval_salt = 0xd631614b;
		3639	u32 hash;
		3640
		3641	if (skb->sk && skb->sk->sk_hash)
		3642	hash = skb->sk->sk_hash;
		3643	else
		3644	hash = (__force u16)skb->protocol ^ skb->hash;
		3645
		3646	hash = jhash_1word(hash, jhash_initval_salt);
		3647
		3648	return (u16)(((u64)hash * num_tx_queues) >> 32);
		3649	}
		3650
		3651	u16 i40e_lan_select_queue(struct net_device *netdev,
		3652	struct sk_buff *skb,
		3653	struct net_device __always_unused *sb_dev)
		3654	{
		3655	struct i40e_netdev_priv *np = netdev_priv(netdev);
		3656	struct i40e_vsi *vsi = np->vsi;
		3657	struct i40e_hw *hw;
		3658	u16 qoffset;
		3659	u16 qcount;
		3660	u8 tclass;
		3661	u16 hash;
		3662	u8 prio;
		3663
		3664	/* is DCB enabled at all? */
		3665	if (vsi->tc_config.numtc == 1)
		3666	return i40e_swdcb_skb_tx_hash(netdev, skb,
		3667	netdev->real_num_tx_queues);
		3668
		3669	prio = skb->priority;
		3670	hw = &vsi->back->hw;
		3671	tclass = hw->local_dcbx_config.etscfg.prioritytable[prio];
		3672	/* sanity check */
		3673	if (unlikely(!(vsi->tc_config.enabled_tc & BIT(tclass))))
		3674	tclass = 0;
		3675
		3676	/* select a queue assigned for the given TC */
		3677	qcount = vsi->tc_config.tc_info[tclass].qcount;
		3678	hash = i40e_swdcb_skb_tx_hash(netdev, skb, qcount);
		3679
		3680	qoffset = vsi->tc_config.tc_info[tclass].qoffset;
		3681	return qoffset + hash;
		3682	}
		3683
3634	/**	3684	/**
3635	* i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring	3685	* i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring
3636	* @xdpf: data to transmit	3686	* @xdpf: data to transmit

drivers/net/ethernet/intel/i40e/i40e_txrx.h+2−0

@@ -451,6 +451,8 @@ static inline unsigned int i40e_rx_pg_order(struct i40e_ring *ring) · 450 unmodified lines
451		451
452	bool i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count);	452	bool i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count);
453	netdev_tx_t i40e_lan_xmit_frame(struct sk_buff skb, struct net_device netdev);	453	netdev_tx_t i40e_lan_xmit_frame(struct sk_buff skb, struct net_device netdev);
		454	u16 i40e_lan_select_queue(struct net_device netdev, struct sk_buff skb,
		455	struct net_device *sb_dev);
454	void i40e_clean_tx_ring(struct i40e_ring *tx_ring);	456	void i40e_clean_tx_ring(struct i40e_ring *tx_ring);
455	void i40e_clean_rx_ring(struct i40e_ring *rx_ring);	457	void i40e_clean_rx_ring(struct i40e_ring *rx_ring);
456	int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring);	458	int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring);

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c+2−1

@@ -1825,7 +1825,8 @@ static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, · 1824 unmodified lines
1825	struct sk_buff *skb)	1825	struct sk_buff *skb)
1826	{	1826	{
1827	if (ring_uses_build_skb(rx_ring)) {	1827	if (ring_uses_build_skb(rx_ring)) {
1828	unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK;	1828	unsigned long mask = (unsigned long)ixgbe_rx_pg_size(rx_ring) - 1;
		1829	unsigned long offset = (unsigned long)(skb->data) & mask;
1829		1830
1830	dma_sync_single_range_for_cpu(rx_ring->dev,	1831	dma_sync_single_range_for_cpu(rx_ring->dev,
1831	IXGBE_CB(skb)->dma,	1832	IXGBE_CB(skb)->dma,

drivers/net/ethernet/marvell/octeontx2/af/Makefile+1−1

@@ -10,4 +10,4 @@ obj-$(CONFIG_OCTEONTX2_AF) += rvu_af.o · 9 unmodified lines
10	rvu_mbox-y := mbox.o rvu_trace.o	10	rvu_mbox-y := mbox.o rvu_trace.o
11	rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \	11	rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \
12	rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \	12	rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \
13	rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o	13	rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o

drivers/net/ethernet/marvell/octeontx2/af/cgx.c+1−1

@@ -1504,8 +1504,8 @@ static int cgx_lmac_init(struct cgx *cgx) · 1503 unmodified lines
1504		1504
1505	/* Add reference */	1505	/* Add reference */
1506	cgx->lmac_idmap[lmac->lmac_id] = lmac;	1506	cgx->lmac_idmap[lmac->lmac_id] = lmac;
1507	cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true);
1508	set_bit(lmac->lmac_id, &cgx->lmac_bmap);	1507	set_bit(lmac->lmac_id, &cgx->lmac_bmap);
		1508	cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true);
1509	}	1509	}
1510		1510
1511	return cgx_lmac_verify_fwi_version(cgx);	1511	return cgx_lmac_verify_fwi_version(cgx);

drivers/net/ethernet/marvell/octeontx2/af/npc.h+3−0

  * Software assigns pkind for each incoming port such as CGX
  * Ethernet interfaces, LBK interfaces, etc.
  */
+#define NPC_UNRESERVED_PKIND_COUNT NPC_RX_VLAN_EXDSA_PKIND
 enum npc_pkind_type {
+	NPC_RX_LBK_PKIND = 0ULL,
 	NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
 	NPC_RX_CHLEN24B_PKIND = 57ULL,
 	NPC_RX_CPT_HDR_PKIND,

drivers/net/ethernet/marvell/octeontx2/af/rvu.c+13−3

 	/* Get numVFs attached to this PF and first HWVF */
 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
-	*numvfs = (cfg >> 12) & 0xFF;
+	if (numvfs)
-	*hwvf = cfg & 0xFFF;
+		*numvfs = (cfg >> 12) & 0xFF;
+	if (hwvf)
+		*hwvf = cfg & 0xFFF;
 }
 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc)
 	return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc);
 }
-static int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc)
+int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc)
 {
 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
 	int blkaddr = BLKADDR_NIX0, vf;
 	if (!vfs)
 		return 0;
+	/* LBK channel number 63 is used for switching packets between
+	 * CGX mapped VFs. Hence limit LBK pairs till 62 only.
+	 */
+	if (vfs > 62)
+		vfs = 62;
 	/* Save VFs number for reference in VF interrupts handlers.
 	 * Since interrupts might start arriving during SRIOV enablement
 	 * ordinary API cannot be used to get number of enabled VFs.
 	/* Initialize debugfs */
 	rvu_dbg_init(rvu);
+	mutex_init(&rvu->rswitch.switch_lock);
 	return 0;
 err_dl:
 	rvu_unregister_dl(rvu);

drivers/net/ethernet/marvell/octeontx2/af/rvu.h+21−0

 	size_t				kpus;
 };
+#define RVU_SWITCH_LBK_CHAN	63
+struct rvu_switch {
+	struct mutex switch_lock; /* Serialize flow installation */
+	u32 used_entries;
+	u16 *entry2pcifunc;
+	u16 mode;
+	u16 start_entry;
+};
 struct rvu {
 	void __iomem		*afreg_base;
 	void __iomem		*pfreg_base;
 	/* CGX */
 #define PF_CGXMAP_BASE		1 /* PF 0 is reserved for RVU PF */
+	u16			cgx_mapped_vfs; /* maximum CGX mapped VFs */
 	u8			cgx_mapped_pfs;
 	u8			cgx_cnt_max;	 /* CGX port count max */
 	u8			*pf2cgxlmac_map; /* pf to cgx_lmac map */
 	struct rvu_debugfs	rvu_dbg;
 #endif
 	struct rvu_devlink	*rvu_dl;
+	/* RVU switch implementation over NPC with DMAC rules */
+	struct rvu_switch	rswitch;
 };
 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
 			struct nix_cn10k_aq_enq_req *aq_req,
 			struct nix_cn10k_aq_enq_rsp *aq_rsp,
 			u16 pcifunc, u8 ctype, u32 qidx);
+int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc);
 /* NPC APIs */
 int rvu_npc_init(struct rvu *rvu);
 static inline void rvu_dbg_init(struct rvu *rvu) {}
 static inline void rvu_dbg_exit(struct rvu *rvu) {}
 #endif
+/* RVU Switch */
+void rvu_switch_enable(struct rvu *rvu);
+void rvu_switch_disable(struct rvu *rvu);
+void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc);
 #endif /* RVU_H */

drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c+3−0

 	unsigned long lmac_bmap;
 	int size, free_pkind;
 	int cgx, lmac, iter;
+	int numvfs, hwvfs;
 	if (!cgx_cnt_max)
 		return 0;
 			pkind->pfchan_map[free_pkind] = ((pf) & 0x3F) << 16;
 			rvu_map_cgx_nix_block(rvu, pf, cgx, lmac);
 			rvu->cgx_mapped_pfs++;
+			rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvfs);
+			rvu->cgx_mapped_vfs += numvfs;
 			pf++;
 		}
 	}

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c+1−4

 	int entry_acnt, entry_ecnt;
 	int cntr_acnt, cntr_ecnt;
-	/* Skip PF0 */
-	if (!pcifunc)
-		return;
 	rvu_npc_get_mcam_entry_alloc_info(rvu, pcifunc, blkaddr,
 					  &entry_acnt, &entry_ecnt);
 	rvu_npc_get_mcam_counter_alloc_info(rvu, pcifunc, blkaddr,
 static void rvu_dbg_npc_mcam_show_action(struct seq_file *s,
 					 struct rvu_npc_mcam_rule *rule)
 {
-	if (rule->intf == NIX_INTF_TX) {
+	if (is_npc_intf_tx(rule->intf)) {
 		switch (rule->tx_action.op) {
 		case NIX_TX_ACTIONOP_DROP:
 			seq_puts(s, "\taction: Drop\n");

drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c+41−7

 	rvu_nix_health_reporters_destroy(rvu_dl);
 }
+static int rvu_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
+{
+	struct rvu_devlink *rvu_dl = devlink_priv(devlink);
+	struct rvu *rvu = rvu_dl->rvu;
+	struct rvu_switch *rswitch;
+	rswitch = &rvu->rswitch;
+	*mode = rswitch->mode;
+	return 0;
+}
+static int rvu_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
+					struct netlink_ext_ack *extack)
+{
+	struct rvu_devlink *rvu_dl = devlink_priv(devlink);
+	struct rvu *rvu = rvu_dl->rvu;
+	struct rvu_switch *rswitch;
+	rswitch = &rvu->rswitch;
+	switch (mode) {
+	case DEVLINK_ESWITCH_MODE_LEGACY:
+	case DEVLINK_ESWITCH_MODE_SWITCHDEV:
+		if (rswitch->mode == mode)
+			return 0;
+		rswitch->mode = mode;
+		if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
+			rvu_switch_enable(rvu);
+		else
+			rvu_switch_disable(rvu);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
 static int rvu_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
 				struct netlink_ext_ack *extack)
 {
 static const struct devlink_ops rvu_devlink_ops = {
 	.info_get = rvu_devlink_info_get,
+	.eswitch_mode_get = rvu_devlink_eswitch_mode_get,
+	.eswitch_mode_set = rvu_devlink_eswitch_mode_set,
 };
 int rvu_register_dl(struct rvu *rvu)
 	struct devlink *dl;
 	int err;
-	rvu_dl = kzalloc(sizeof(*rvu_dl), GFP_KERNEL);
-	if (!rvu_dl)
-		return -ENOMEM;
 	dl = devlink_alloc(&rvu_devlink_ops, sizeof(struct rvu_devlink));
 	if (!dl) {
 		dev_warn(rvu->dev, "devlink_alloc failed\n");
-		kfree(rvu_dl);
 		return -ENOMEM;
 	}
 	if (err) {
 		dev_err(rvu->dev, "devlink register failed with error %d\n", err);
 		devlink_free(dl);
-		kfree(rvu_dl);
 		return err;
 	}
+	rvu_dl = devlink_priv(dl);
 	rvu_dl->dl = dl;
 	rvu_dl->rvu = rvu;
 	rvu->rvu_dl = rvu_dl;
 	rvu_health_reporters_destroy(rvu);
 	devlink_unregister(dl);
 	devlink_free(dl);
-	kfree(rvu_dl);
 }

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c+50−3

 {
 	int err;
-	/*Sync all in flight RX packets to LLC/DRAM */
+	/* Sync all in flight RX packets to LLC/DRAM */
 	rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0));
 	err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true);
 	if (err)
-		dev_err(rvu->dev, "NIX RX software sync failed\n");
+		dev_err(rvu->dev, "SYNC1: NIX RX software sync failed\n");
+	/* SW_SYNC ensures all existing transactions are finished and pkts
+	 * are written to LLC/DRAM, queues should be teared down after
+	 * successful SW_SYNC. Due to a HW errata, in some rare scenarios
+	 * an existing transaction might end after SW_SYNC operation. To
+	 * ensure operation is fully done, do the SW_SYNC twice.
+	 */
+	rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0));
+	err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true);
+	if (err)
+		dev_err(rvu->dev, "SYNC2: NIX RX software sync failed\n");
 }
 static bool is_valid_txschq(struct rvu *rvu, int blkaddr,
 					rvu_nix_chan_lbk(rvu, lbkid, vf + 1);
 		pfvf->rx_chan_cnt = 1;
 		pfvf->tx_chan_cnt = 1;
+		rvu_npc_set_pkind(rvu, NPC_RX_LBK_PKIND, pfvf);
 		rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf,
 					      pfvf->rx_chan_base,
 					      pfvf->rx_chan_cnt);
 	pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq], NIX_TXSCHQ_CFG_DONE);
 }
+static void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr,
+			       u16 pcifunc, struct nix_txsch *txsch)
+{
+	struct rvu_hwinfo *hw = rvu->hw;
+	int lbk_link_start, lbk_links;
+	u8 pf = rvu_get_pf(pcifunc);
+	int schq;
+	if (!is_pf_cgxmapped(rvu, pf))
+		return;
+	lbk_link_start = hw->cgx_links;
+	for (schq = 0; schq < txsch->schq.max; schq++) {
+		if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc)
+			continue;
+		/* Enable all LBK links with channel 63 by default so that
+		 * packets can be sent to LBK with a NPC TX MCAM rule
+		 */
+		lbk_links = hw->lbk_links;
+		while (lbk_links--)
+			rvu_write64(rvu, blkaddr,
+				    NIX_AF_TL3_TL2X_LINKX_CFG(schq,
+							      lbk_link_start +
+							      lbk_links),
+				    BIT_ULL(12) | RVU_SWITCH_LBK_CHAN);
+	}
+}
 int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu,
 				    struct nix_txschq_config *req,
 				    struct msg_rsp *rsp)
 		rvu_write64(rvu, blkaddr, reg, regval);
 	}
+	rvu_nix_tx_tl2_cfg(rvu, blkaddr, pcifunc,
+			   &nix_hw->txsch[NIX_TXSCH_LVL_TL2]);
 	return 0;
 }
 	if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && from_vf)
 		ether_addr_copy(pfvf->default_mac, req->mac_addr);
+	rvu_switch_update_rules(rvu, pcifunc);
 	return 0;
 }
 		vlan = &nix_hw->txvlan;
 		kfree(vlan->rsrc.bmap);
 		mutex_destroy(&vlan->rsrc_lock);
-		devm_kfree(rvu->dev, vlan->entry2pfvf_map);
 		mcast = &nix_hw->mcast;
 		qmem_free(rvu->dev, mcast->mce_ctx);
 	pfvf = rvu_get_pfvf(rvu, pcifunc);
 	set_bit(NIXLF_INITIALIZED, &pfvf->flags);
+	rvu_switch_update_rules(rvu, pcifunc);
 	return rvu_cgx_start_stop_io(rvu, pcifunc, true);
 }

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c+43−15

 	owner = mcam->entry2pfvf_map[index];
 	target_func = (entry->action >> 4) & 0xffff;
 	/* do nothing when target is LBK/PF or owner is not PF */
-	if (is_afvf(target_func) || (owner & RVU_PFVF_FUNC_MASK) ||
+	if (is_pffunc_af(owner) || is_afvf(target_func) ||
+	    (owner & RVU_PFVF_FUNC_MASK) ||
 	    !(target_func & RVU_PFVF_FUNC_MASK))
 		return;
 {
 	int bank = npc_get_bank(mcam, index);
 	int kw = 0, actbank, actindex;
+	u8 tx_intf_mask = ~intf & 0x3;
+	u8 tx_intf = intf;
 	u64 cam0, cam1;
 	actbank = bank; /* Save bank id, to set action later on */
 	 */
 	for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
 		/* Interface should be set in all banks */
+		if (is_npc_intf_tx(intf)) {
+			/* Last bit must be set and rest don't care
+			 * for TX interfaces
+			 */
+			tx_intf_mask = 0x1;
+			tx_intf = intf & tx_intf_mask;
+			tx_intf_mask = ~tx_intf & tx_intf_mask;
+		}
 		rvu_write64(rvu, blkaddr,
 			    NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1),
-			    intf);
+			    tx_intf);
 		rvu_write64(rvu, blkaddr,
 			    NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0),
-			    ~intf & 0x3);
+			    tx_intf_mask);
 		/* Set the match key */
 		npc_get_keyword(entry, kw, &cam0, &cam1);
 	eth_broadcast_addr((u8 *)&req.mask.dmac);
 	req.features = BIT_ULL(NPC_DMAC);
 	req.channel = chan;
+	req.chan_mask = 0xFFFU;
 	req.intf = pfvf->nix_rx_intf;
 	req.op = action.op;
 	req.hdr.pcifunc = 0; /* AF is requester */
 	eth_broadcast_addr((u8 *)&req.mask.dmac);
 	req.features = BIT_ULL(NPC_DMAC);
 	req.channel = chan;
+	req.chan_mask = 0xFFFU;
 	req.intf = pfvf->nix_rx_intf;
 	req.entry = index;
 	req.hdr.pcifunc = 0; /* AF is requester */
 {
 	struct rvu_hwinfo *hw = rvu->hw;
 	int num_pkinds, num_kpus, idx;
-	struct npc_pkind *pkind;
 	/* Disable all KPUs and their entries */
 	for (idx = 0; idx < hw->npc_kpus; idx++) {
 	 * Check HW max count to avoid configuring junk or
 	 * writing to unsupported CSR addresses.
 	 */
-	pkind = &hw->pkind;
 	num_pkinds = rvu->kpu.pkinds;
-	num_pkinds = min_t(int, pkind->rsrc.max, num_pkinds);
+	num_pkinds = min_t(int, hw->npc_pkinds, num_pkinds);
 	for (idx = 0; idx < num_pkinds; idx++)
 		npc_config_kpuaction(rvu, blkaddr, &rvu->kpu.ikpu[idx], 0, idx, true);
 	int nixlf_count = rvu_get_nixlf_count(rvu);
 	struct npc_mcam *mcam = &rvu->hw->mcam;
 	int rsvd, err;
+	u16 index;
+	int cntr;
 	u64 cfg;
 	/* Actual number of MCAM entries vary by entry size */
 	if (!mcam->entry2target_pffunc)
 		goto free_mem;
+	for (index = 0; index < mcam->bmap_entries; index++) {
+		mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP;
+		mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP;
+	}
+	for (cntr = 0; cntr < mcam->counters.max; cntr++)
+		mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP;
 	mutex_init(&mcam->lock);
 	return 0;
 	if (npc_const1 & BIT_ULL(63))
 		npc_const2 = rvu_read64(rvu, blkaddr, NPC_AF_CONST2);
-	pkind->rsrc.max = (npc_const1 >> 12) & 0xFFULL;
+	pkind->rsrc.max = NPC_UNRESERVED_PKIND_COUNT;
+	hw->npc_pkinds = (npc_const1 >> 12) & 0xFFULL;
 	hw->npc_kpu_entries = npc_const1 & 0xFFFULL;
 	hw->npc_kpus = (npc_const >> 8) & 0x1FULL;
 	hw->npc_intfs = npc_const & 0xFULL;
 	err = rvu_alloc_bitmap(&pkind->rsrc);
 	if (err)
 		return err;
+	/* Reserve PKIND#0 for LBKs. Power reset value of LBK_CH_PKIND is '0',
+	 * no need to configure PKIND for all LBKs separately.
+	 */
+	rvu_alloc_rsrc(&pkind->rsrc);
 	/* Allocate mem for pkind to PF and channel mapping info */
 	pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max,
 	}
 	/* Alloc request from PFFUNC with no NIXLF attached should be denied */
-	if (!is_nixlf_attached(rvu, pcifunc))
+	if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc))
 		return NPC_MCAM_ALLOC_DENIED;
 	return npc_mcam_alloc_entries(mcam, pcifunc, req, rsp);
 		return NPC_MCAM_INVALID_REQ;
 	/* Free request from PFFUNC with no NIXLF attached, ignore */
-	if (!is_nixlf_attached(rvu, pcifunc))
+	if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc))
 		return NPC_MCAM_INVALID_REQ;
 	mutex_lock(&mcam->lock);
 	if (rc)
 		goto exit;
-	mcam->entry2pfvf_map[req->entry] = 0;
+	mcam->entry2pfvf_map[req->entry] = NPC_MCAM_INVALID_MAP;
 	mcam->entry2target_pffunc[req->entry] = 0x0;
 	npc_mcam_clear_bit(mcam, req->entry);
 	npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
 	else
 		nix_intf = pfvf->nix_rx_intf;
-	if (npc_mcam_verify_channel(rvu, pcifunc, req->intf, channel)) {
+	if (!is_pffunc_af(pcifunc) &&
+	    npc_mcam_verify_channel(rvu, pcifunc, req->intf, channel)) {
 		rc = NPC_MCAM_INVALID_REQ;
 		goto exit;
 	}
-	if (npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf,
+	if (!is_pffunc_af(pcifunc) &&
-				    pcifunc)) {
+	    npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf, pcifunc)) {
 		rc = NPC_MCAM_INVALID_REQ;
 		goto exit;
 	}
 		return NPC_MCAM_INVALID_REQ;
 	/* If the request is from a PFFUNC with no NIXLF attached, ignore */
-	if (!is_nixlf_attached(rvu, pcifunc))
+	if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc))
 		return NPC_MCAM_INVALID_REQ;
 	/* Since list of allocated counter IDs needs to be sent to requester,
 	if (rc) {
 		/* Free allocated MCAM entry */
 		mutex_lock(&mcam->lock);
-		mcam->entry2pfvf_map[entry] = 0;
+		mcam->entry2pfvf_map[entry] = NPC_MCAM_INVALID_MAP;
 		npc_mcam_clear_bit(mcam, entry);
 		mutex_unlock(&mcam->lock);
 		return rc;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c+21−8

@@ -910,14 +910,17 @@ static void rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, · 909 unmodified lines
910		910
911	static void npc_update_rx_entry(struct rvu rvu, struct rvu_pfvf pfvf,	911	static void npc_update_rx_entry(struct rvu rvu, struct rvu_pfvf pfvf,
912	struct mcam_entry *entry,	912	struct mcam_entry *entry,
913	struct npc_install_flow_req *req, u16 target)	913	struct npc_install_flow_req *req,
		914	u16 target, bool pf_set_vfs_mac)
914	{	915	{
		916	struct rvu_switch *rswitch = &rvu->rswitch;
915	struct nix_rx_action action;	917	struct nix_rx_action action;
916	u64 chan_mask;
917		918
918	chan_mask = req->chan_mask ? req->chan_mask : ~0ULL;	919	if (rswitch->mode == DEVLINK_ESWITCH_MODE_SWITCHDEV && pf_set_vfs_mac)
919	npc_update_entry(rvu, NPC_CHAN, entry, req->channel, 0, chan_mask, 0,	920	req->chan_mask = 0x0; /* Do not care channel */
920	NIX_INTF_RX);	921
		922	npc_update_entry(rvu, NPC_CHAN, entry, req->channel, 0, req->chan_mask,
		923	0, NIX_INTF_RX);
921		924
922	(u64 )&action = 0x00;	925	(u64 )&action = 0x00;
923	action.pf_func = target;	926	action.pf_func = target;
@@ -949,9 +952,16 @@ static void npc_update_tx_entry(struct rvu rvu, struct rvu_pfvf pfvf, · 25 unmodified lines
949	struct npc_install_flow_req *req, u16 target)	952	struct npc_install_flow_req *req, u16 target)
950	{	953	{
951	struct nix_tx_action action;	954	struct nix_tx_action action;
		955	u64 mask = ~0ULL;
		956
		957	/* If AF is installing then do not care about
		958	* PF_FUNC in Send Descriptor
		959	*/
		960	if (is_pffunc_af(req->hdr.pcifunc))
		961	mask = 0;
952		962
953	npc_update_entry(rvu, NPC_PF_FUNC, entry, (__force u16)htons(target),	963	npc_update_entry(rvu, NPC_PF_FUNC, entry, (__force u16)htons(target),
954	0, ~0ULL, 0, NIX_INTF_TX);	964	0, mask, 0, NIX_INTF_TX);
955		965
956	(u64 )&action = 0x00;	966	(u64 )&action = 0x00;
957	action.op = req->op;	967	action.op = req->op;
@@ -1002,7 +1012,7 @@ static int npc_install_flow(struct rvu *rvu, int blkaddr, u16 target, · 44 unmodified lines
1002	req->intf);	1012	req->intf);
1003		1013
1004	if (is_npc_intf_rx(req->intf))	1014	if (is_npc_intf_rx(req->intf))
1005	npc_update_rx_entry(rvu, pfvf, entry, req, target);	1015	npc_update_rx_entry(rvu, pfvf, entry, req, target, pf_set_vfs_mac);
1006	else	1016	else
1007	npc_update_tx_entry(rvu, pfvf, entry, req, target);	1017	npc_update_tx_entry(rvu, pfvf, entry, req, target);
1008		1018
@@ -1164,7 +1174,9 @@ int rvu_mbox_handler_npc_install_flow(struct rvu *rvu, · 155 unmodified lines
1164	if (err)	1174	if (err)
1165	return err;	1175	return err;
1166		1176
1167	if (npc_mcam_verify_channel(rvu, target, req->intf, req->channel))	1177	/* Skip channel validation if AF is installing */
		1178	if (!is_pffunc_af(req->hdr.pcifunc) &&
		1179	npc_mcam_verify_channel(rvu, target, req->intf, req->channel))
1168	return -EINVAL;	1180	return -EINVAL;
1169		1181
1170	pfvf = rvu_get_pfvf(rvu, target);	1182	pfvf = rvu_get_pfvf(rvu, target);
@@ -1180,6 +1192,7 @@ int rvu_mbox_handler_npc_install_flow(struct rvu *rvu, · 9 unmodified lines
1180	eth_broadcast_addr((u8 *)&req->mask.dmac);	1192	eth_broadcast_addr((u8 *)&req->mask.dmac);
1181	}	1193	}
1182		1194
		1195	/* Proceed if NIXLF is attached or not for TX rules */
1183	err = nix_get_nixlf(rvu, target, &nixlf, NULL);	1196	err = nix_get_nixlf(rvu, target, &nixlf, NULL);
1184	if (err && is_npc_intf_rx(req->intf) && !pf_set_vfs_mac)	1197	if (err && is_npc_intf_rx(req->intf) && !pf_set_vfs_mac)
1185	return -EINVAL;	1198	return -EINVAL;

drivers/net/ethernet/marvell/octeontx2/af/rvu_switch.c+259−0

@@ -0,0 +1,259 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/* Marvell OcteonTx2 RVU Admin Function driver
	3	*
	4	* Copyright (C) 2021 Marvell.
	5	*/
	6
	7	#include <linux/bitfield.h>
	8	#include "rvu.h"
	9
	10	static int rvu_switch_install_rx_rule(struct rvu *rvu, u16 pcifunc,
	11	u16 chan_mask)
	12	{
	13	struct npc_install_flow_req req = { 0 };
	14	struct npc_install_flow_rsp rsp = { 0 };
	15	struct rvu_pfvf *pfvf;
	16
	17	pfvf = rvu_get_pfvf(rvu, pcifunc);
	18	/* If the pcifunc is not initialized then nothing to do.
	19	* This same function will be called again via rvu_switch_update_rules
	20	* after pcifunc is initialized.
	21	*/
	22	if (!test_bit(NIXLF_INITIALIZED, &pfvf->flags))
	23	return 0;
	24
	25	ether_addr_copy(req.packet.dmac, pfvf->mac_addr);
	26	eth_broadcast_addr((u8 *)&req.mask.dmac);
	27	req.hdr.pcifunc = 0; /* AF is requester */
	28	req.vf = pcifunc;
	29	req.features = BIT_ULL(NPC_DMAC);
	30	req.channel = pfvf->rx_chan_base;
	31	req.chan_mask = chan_mask;
	32	req.intf = pfvf->nix_rx_intf;
	33	req.op = NIX_RX_ACTION_DEFAULT;
	34	req.default_rule = 1;
	35
	36	return rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
	37	}
	38
	39	static int rvu_switch_install_tx_rule(struct rvu *rvu, u16 pcifunc, u16 entry)
	40	{
	41	struct npc_install_flow_req req = { 0 };
	42	struct npc_install_flow_rsp rsp = { 0 };
	43	struct rvu_pfvf *pfvf;
	44	u8 lbkid;
	45
	46	pfvf = rvu_get_pfvf(rvu, pcifunc);
	47	/* If the pcifunc is not initialized then nothing to do.
	48	* This same function will be called again via rvu_switch_update_rules
	49	* after pcifunc is initialized.
	50	*/
	51	if (!test_bit(NIXLF_INITIALIZED, &pfvf->flags))
	52	return 0;
	53
	54	lbkid = pfvf->nix_blkaddr == BLKADDR_NIX0 ? 0 : 1;
	55	ether_addr_copy(req.packet.dmac, pfvf->mac_addr);
	56	eth_broadcast_addr((u8 *)&req.mask.dmac);
	57	req.hdr.pcifunc = 0; /* AF is requester */
	58	req.vf = pcifunc;
	59	req.entry = entry;
	60	req.features = BIT_ULL(NPC_DMAC);
	61	req.intf = pfvf->nix_tx_intf;
	62	req.op = NIX_TX_ACTIONOP_UCAST_CHAN;
	63	req.index = (lbkid << 8) \| RVU_SWITCH_LBK_CHAN;
	64	req.set_cntr = 1;
	65
	66	return rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
	67	}
	68
	69	static int rvu_switch_install_rules(struct rvu *rvu)
	70	{
	71	struct rvu_switch *rswitch = &rvu->rswitch;
	72	u16 start = rswitch->start_entry;
	73	struct rvu_hwinfo *hw = rvu->hw;
	74	u16 pcifunc, entry = 0;
	75	int pf, vf, numvfs;
	76	int err;
	77
	78	for (pf = 1; pf < hw->total_pfs; pf++) {
	79	if (!is_pf_cgxmapped(rvu, pf))
	80	continue;
	81
	82	pcifunc = pf << 10;
	83	/* rvu_get_nix_blkaddr sets up the corresponding NIX block
	84	* address and NIX RX and TX interfaces for a pcifunc.
	85	* Generally it is called during attach call of a pcifunc but it
	86	* is called here since we are pre-installing rules before
	87	* nixlfs are attached
	88	*/
	89	rvu_get_nix_blkaddr(rvu, pcifunc);
	90
	91	/* MCAM RX rule for a PF/VF already exists as default unicast
	92	* rules installed by AF. Hence change the channel in those
	93	* rules to ignore channel so that packets with the required
	94	* DMAC received from LBK(by other PF/VFs in system) or from
	95	* external world (from wire) are accepted.
	96	*/
	97	err = rvu_switch_install_rx_rule(rvu, pcifunc, 0x0);
	98	if (err) {
	99	dev_err(rvu->dev, "RX rule for PF%d failed(%d)\n",
	100	pf, err);
	101	return err;
	102	}
	103
	104	err = rvu_switch_install_tx_rule(rvu, pcifunc, start + entry);
	105	if (err) {
	106	dev_err(rvu->dev, "TX rule for PF%d failed(%d)\n",
	107	pf, err);
	108	return err;
	109	}
	110
	111	rswitch->entry2pcifunc[entry++] = pcifunc;
	112
	113	rvu_get_pf_numvfs(rvu, pf, &numvfs, NULL);
	114	for (vf = 0; vf < numvfs; vf++) {
	115	pcifunc = pf << 10 \| ((vf + 1) & 0x3FF);
	116	rvu_get_nix_blkaddr(rvu, pcifunc);
	117
	118	err = rvu_switch_install_rx_rule(rvu, pcifunc, 0x0);
	119	if (err) {
	120	dev_err(rvu->dev,
	121	"RX rule for PF%dVF%d failed(%d)\n",
	122	pf, vf, err);
	123	return err;
	124	}
	125
	126	err = rvu_switch_install_tx_rule(rvu, pcifunc,
	127	start + entry);
	128	if (err) {
	129	dev_err(rvu->dev,
	130	"TX rule for PF%dVF%d failed(%d)\n",
	131	pf, vf, err);
	132	return err;
	133	}
	134
	135	rswitch->entry2pcifunc[entry++] = pcifunc;
	136	}
	137	}
	138
	139	return 0;
	140	}
	141
	142	void rvu_switch_enable(struct rvu *rvu)
	143	{
	144	struct npc_mcam_alloc_entry_req alloc_req = { 0 };
	145	struct npc_mcam_alloc_entry_rsp alloc_rsp = { 0 };
	146	struct npc_delete_flow_req uninstall_req = { 0 };
	147	struct npc_mcam_free_entry_req free_req = { 0 };
	148	struct rvu_switch *rswitch = &rvu->rswitch;
	149	struct msg_rsp rsp;
	150	int ret;
	151
	152	alloc_req.contig = true;
	153	alloc_req.count = rvu->cgx_mapped_pfs + rvu->cgx_mapped_vfs;
	154	ret = rvu_mbox_handler_npc_mcam_alloc_entry(rvu, &alloc_req,
	155	&alloc_rsp);
	156	if (ret) {
	157	dev_err(rvu->dev,
	158	"Unable to allocate MCAM entries\n");
	159	goto exit;
	160	}
	161
	162	if (alloc_rsp.count != alloc_req.count) {
	163	dev_err(rvu->dev,
	164	"Unable to allocate %d MCAM entries, got %d\n",
	165	alloc_req.count, alloc_rsp.count);
	166	goto free_entries;
	167	}
	168
	169	rswitch->entry2pcifunc = kcalloc(alloc_req.count, sizeof(u16),
	170	GFP_KERNEL);
	171	if (!rswitch->entry2pcifunc)
	172	goto free_entries;
	173
	174	rswitch->used_entries = alloc_rsp.count;
	175	rswitch->start_entry = alloc_rsp.entry;
	176
	177	ret = rvu_switch_install_rules(rvu);
	178	if (ret)
	179	goto uninstall_rules;
	180
	181	return;
	182
	183	uninstall_rules:
	184	uninstall_req.start = rswitch->start_entry;
	185	uninstall_req.end = rswitch->start_entry + rswitch->used_entries - 1;
	186	rvu_mbox_handler_npc_delete_flow(rvu, &uninstall_req, &rsp);
	187	kfree(rswitch->entry2pcifunc);
	188	free_entries:
	189	free_req.all = 1;
	190	rvu_mbox_handler_npc_mcam_free_entry(rvu, &free_req, &rsp);
	191	exit:
	192	return;
	193	}
	194
	195	void rvu_switch_disable(struct rvu *rvu)
	196	{
	197	struct npc_delete_flow_req uninstall_req = { 0 };
	198	struct npc_mcam_free_entry_req free_req = { 0 };
	199	struct rvu_switch *rswitch = &rvu->rswitch;
	200	struct rvu_hwinfo *hw = rvu->hw;
	201	int pf, vf, numvfs;
	202	struct msg_rsp rsp;
	203	u16 pcifunc;
	204	int err;
	205
	206	if (!rswitch->used_entries)
	207	return;
	208
	209	for (pf = 1; pf < hw->total_pfs; pf++) {
	210	if (!is_pf_cgxmapped(rvu, pf))
	211	continue;
	212
	213	pcifunc = pf << 10;
	214	err = rvu_switch_install_rx_rule(rvu, pcifunc, 0xFFF);
	215	if (err)
	216	dev_err(rvu->dev,
	217	"Reverting RX rule for PF%d failed(%d)\n",
	218	pf, err);
	219
	220	rvu_get_pf_numvfs(rvu, pf, &numvfs, NULL);
	221	for (vf = 0; vf < numvfs; vf++) {
	222	pcifunc = pf << 10 \| ((vf + 1) & 0x3FF);
	223	err = rvu_switch_install_rx_rule(rvu, pcifunc, 0xFFF);
	224	if (err)
	225	dev_err(rvu->dev,
	226	"Reverting RX rule for PF%dVF%d failed(%d)\n",
	227	pf, vf, err);
	228	}
	229	}
	230
	231	uninstall_req.start = rswitch->start_entry;
	232	uninstall_req.end = rswitch->start_entry + rswitch->used_entries - 1;
	233	free_req.all = 1;
	234	rvu_mbox_handler_npc_delete_flow(rvu, &uninstall_req, &rsp);
	235	rvu_mbox_handler_npc_mcam_free_entry(rvu, &free_req, &rsp);
	236	rswitch->used_entries = 0;
	237	kfree(rswitch->entry2pcifunc);
	238	}
	239
	240	void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc)
	241	{
	242	struct rvu_switch *rswitch = &rvu->rswitch;
	243	u32 max = rswitch->used_entries;
	244	u16 entry;
	245
	246	if (!rswitch->used_entries)
	247	return;
	248
	249	for (entry = 0; entry < max; entry++) {
	250	if (rswitch->entry2pcifunc[entry] == pcifunc)
	251	break;
	252	}
	253
	254	if (entry >= max)
	255	return;
	256
	257	rvu_switch_install_tx_rule(rvu, pcifunc, rswitch->start_entry + entry);
	258	rvu_switch_install_rx_rule(rvu, pcifunc, 0x0);
	259	}

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c+8−6

 		aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt);
 		aq->cq.drop_ena = 1;
-		/* Enable receive CQ backpressure */
+		if (!is_otx2_lbkvf(pfvf->pdev)) {
-		aq->cq.bp_ena = 1;
+			/* Enable receive CQ backpressure */
-		aq->cq.bpid = pfvf->bpid[0];
+			aq->cq.bp_ena = 1;
+			aq->cq.bpid = pfvf->bpid[0];
-		/* Set backpressure level is same as cq pass level */
+			/* Set backpressure level is same as cq pass level */
-		aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
+			aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
+		}
 	}
 	/* Fill AQ info */
 	aq->aura.fc_hyst_bits = 0; /* Store count on all updates */
 	/* Enable backpressure for RQ aura */
-	if (aura_id < pfvf->hw.rqpool_cnt) {
+	if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) {
 		aq->aura.bp_ena = 0;
 		aq->aura.nix0_bpid = pfvf->bpid[0];
 		/* Set backpressure level for RQ's Aura */

drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c+3−4

 	err = otx2_set_real_num_queues(dev, channel->tx_count,
 				       channel->rx_count);
 	if (err)
-		goto fail;
+		return err;
 	pfvf->hw.rx_queues = channel->rx_count;
 	pfvf->hw.tx_queues = channel->tx_count;
 	pfvf->qset.cq_cnt = pfvf->hw.tx_queues +  pfvf->hw.rx_queues;
-fail:
 	if (if_up)
-		dev->netdev_ops->ndo_open(dev);
+		err = dev->netdev_ops->ndo_open(dev);
 	netdev_info(dev, "Setting num Tx rings to %d, Rx rings to %d success\n",
 		    pfvf->hw.tx_queues, pfvf->hw.rx_queues);
 	qs->rqe_cnt = rx_count;
 	if (if_up)
-		netdev->netdev_ops->ndo_open(netdev);
+		return netdev->netdev_ops->ndo_open(netdev);
 	return 0;
 }

drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c+5−0

 err_tx_stop_queues:
 	netif_tx_stop_all_queues(netdev);
 	netif_carrier_off(netdev);
+	pf->flags |= OTX2_FLAG_INTF_DOWN;
 err_free_cints:
 	otx2_free_cints(pf, qidx);
 	vec = pci_irq_vector(pf->pdev,
 	struct otx2_rss_info *rss;
 	int qidx, vec, wrk;
+	/* If the DOWN flag is set resources are already freed */
+	if (pf->flags & OTX2_FLAG_INTF_DOWN)
+		return 0;
 	netif_carrier_off(netdev);
 	netif_tx_stop_all_queues(netdev);

drivers/net/ethernet/mellanox/mlx4/main.c+1−0

@@ -3535,6 +3535,7 @@ slave_start: · 3534 unmodified lines
3535		3535
3536	if (!SRIOV_VALID_STATE(dev->flags)) {	3536	if (!SRIOV_VALID_STATE(dev->flags)) {
3537	mlx4_err(dev, "Invalid SRIOV state\n");	3537	mlx4_err(dev, "Invalid SRIOV state\n");
		3538	err = -EINVAL;
3538	goto err_close;	3539	goto err_close;
3539	}	3540	}
3540	}	3541	}

drivers/net/ethernet/mellanox/mlx5/core/dev.c+1−4

 	return 1;
 }
-/* This function is called with two flows:
+/* Must be called with intf_mutex held */
- * 1. During initialization of mlx5_core_dev and we don't need to lock it.
- * 2. During LAG configure stage and caller holds &mlx5_intf_mutex.
- */
 struct mlx5_core_dev *mlx5_get_next_phys_dev(struct mlx5_core_dev *dev)
 {
 	struct auxiliary_device *adev;

drivers/net/ethernet/mellanox/mlx5/core/en/params.c+10−1

 	param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
 }
+static u8 rq_end_pad_mode(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
+{
+	bool ro = pcie_relaxed_ordering_enabled(mdev->pdev) &&
+		MLX5_CAP_GEN(mdev, relaxed_ordering_write);
+	return ro && params->lro_en ?
+		MLX5_WQ_END_PAD_MODE_NONE : MLX5_WQ_END_PAD_MODE_ALIGN;
+}
 int mlx5e_build_rq_param(struct mlx5_core_dev *mdev,
 			 struct mlx5e_params *params,
 			 struct mlx5e_xsk_param *xsk,
 	}
 	MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
-	MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
+	MLX5_SET(wq, wq, end_padding_mode, rq_end_pad_mode(mdev, params));
 	MLX5_SET(wq, wq, log_wq_stride,
 		 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
 	MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.hw_objs.pdn);

drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c+5−2

 		params->log_sq_size = orig->log_sq_size;
 		mlx5e_ptp_build_sq_param(c->mdev, params, &cparams->txq_sq_param);
 	}
-	if (test_bit(MLX5E_PTP_STATE_RX, c->state))
+	/* RQ */
+	if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
+		params->vlan_strip_disable = orig->vlan_strip_disable;
 		mlx5e_ptp_build_rq_param(c->mdev, c->netdev, c->priv->q_counter, cparams);
+	}
 }
 static int mlx5e_init_ptp_rq(struct mlx5e_ptp *c, struct mlx5e_params *params,
 	int err;
 	rq->wq_type      = params->rq_wq_type;
-	rq->pdev         = mdev->device;
+	rq->pdev         = c->pdev;
 	rq->netdev       = priv->netdev;
 	rq->priv         = priv;
 	rq->clock        = &mdev->clock;

drivers/net/ethernet/mellanox/mlx5/core/en/trap.c+1−1

@@ -37,7 +37,7 @@ static void mlx5e_init_trap_rq(struct mlx5e_trap t, struct mlx5e_params params · 36 unmodified lines
37	struct mlx5e_priv *priv = t->priv;	37	struct mlx5e_priv *priv = t->priv;
38		38
39	rq->wq_type = params->rq_wq_type;	39	rq->wq_type = params->rq_wq_type;
40	rq->pdev = mdev->device;	40	rq->pdev = t->pdev;
41	rq->netdev = priv->netdev;	41	rq->netdev = priv->netdev;
42	rq->priv = priv;	42	rq->priv = priv;
43	rq->clock = &mdev->clock;	43	rq->clock = &mdev->clock;

drivers/net/ethernet/mellanox/mlx5/core/en_main.c+26−12

 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
 {
-	int err = 0;
+	int err;
 	int i;
 	for (i = 0; i < chs->num; i++) {
 		if (err)
 			return err;
 	}
+	if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
+		return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
 	return 0;
 }
 	return 0;
 }
+static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
+						       netdev_features_t features)
+{
+	features &= ~NETIF_F_HW_TLS_RX;
+	if (netdev->features & NETIF_F_HW_TLS_RX)
+		netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
+	features &= ~NETIF_F_HW_TLS_TX;
+	if (netdev->features & NETIF_F_HW_TLS_TX)
+		netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
+	features &= ~NETIF_F_NTUPLE;
+	if (netdev->features & NETIF_F_NTUPLE)
+		netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
+	return features;
+}
 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
 					    netdev_features_t features)
 {
 			netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
 	}
-	if (mlx5e_is_uplink_rep(priv)) {
+	if (mlx5e_is_uplink_rep(priv))
-		features &= ~NETIF_F_HW_TLS_RX;
+		features = mlx5e_fix_uplink_rep_features(netdev, features);
-		if (netdev->features & NETIF_F_HW_TLS_RX)
-			netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
-		features &= ~NETIF_F_HW_TLS_TX;
-		if (netdev->features & NETIF_F_HW_TLS_TX)
-			netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
-	}
 	mutex_unlock(&priv->state_lock);
 	if (MLX5_CAP_ETH(mdev, scatter_fcs))
 		netdev->hw_features |= NETIF_F_RXFCS;
+	if (mlx5_qos_is_supported(mdev))
+		netdev->hw_features |= NETIF_F_HW_TC;
 	netdev->features          = netdev->hw_features;
 	/* Defaults */
 		netdev->hw_features	 |= NETIF_F_NTUPLE;
 #endif
 	}
-	if (mlx5_qos_is_supported(mdev))
-		netdev->features |= NETIF_F_HW_TC;
 	netdev->features         |= NETIF_F_HIGHDMA;
 	netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c+31−2

@@ -452,12 +452,32 @@ static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv, · 451 unmodified lines
452	static	452	static
453	struct mlx5_core_dev mlx5e_hairpin_get_mdev(struct net net, int ifindex)	453	struct mlx5_core_dev mlx5e_hairpin_get_mdev(struct net net, int ifindex)
454	{	454	{
		455	struct mlx5_core_dev *mdev;
455	struct net_device *netdev;	456	struct net_device *netdev;
456	struct mlx5e_priv *priv;	457	struct mlx5e_priv *priv;
457		458
458	netdev = __dev_get_by_index(net, ifindex);	459	netdev = dev_get_by_index(net, ifindex);
		460	if (!netdev)
		461	return ERR_PTR(-ENODEV);
		462
459	priv = netdev_priv(netdev);	463	priv = netdev_priv(netdev);
460	return priv->mdev;	464	mdev = priv->mdev;
		465	dev_put(netdev);
		466
		467	/* Mirred tc action holds a refcount on the ifindex net_device (see
		468	* net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
		469	* after dev_put(netdev), while we're in the context of adding a tc flow.
		470	*
		471	* The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
		472	* stored in a hairpin object, which exists until all flows, that refer to it, get
		473	* removed.
		474	*
		475	* On the other hand, after a hairpin object has been created, the peer net_device may
		476	* be removed/unbound while there are still some hairpin flows that are using it. This
		477	* case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
		478	* NETDEV_UNREGISTER event of the peer net_device.
		479	*/
		480	return mdev;
461	}	481	}
462		482
463	static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)	483	static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
@@ -666,6 +686,10 @@ mlx5e_hairpin_create(struct mlx5e_priv priv, struct mlx5_hairpin_params params · 202 unmodified lines
666		686
667	func_mdev = priv->mdev;	687	func_mdev = priv->mdev;
668	peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);	688	peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
		689	if (IS_ERR(peer_mdev)) {
		690	err = PTR_ERR(peer_mdev);
		691	goto create_pair_err;
		692	}
669		693
670	pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);	694	pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
671	if (IS_ERR(pair)) {	695	if (IS_ERR(pair)) {
@@ -804,6 +828,11 @@ static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv, · 132 unmodified lines
804	int err;	828	int err;
805		829
806	peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);	830	peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
		831	if (IS_ERR(peer_mdev)) {
		832	NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
		833	return PTR_ERR(peer_mdev);
		834	}
		835
807	if (!MLX5_CAP_GEN(priv->mdev, hairpin) \|\| !MLX5_CAP_GEN(peer_mdev, hairpin)) {	836	if (!MLX5_CAP_GEN(priv->mdev, hairpin) \|\| !MLX5_CAP_GEN(peer_mdev, hairpin)) {
808	NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");	837	NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
809	return -EOPNOTSUPP;	838	return -EOPNOTSUPP;

drivers/net/ethernet/mellanox/mlx5/core/eswitch.h+1−1

@@ -636,7 +636,7 @@ struct esw_vport_tbl_namespace { · 635 unmodified lines
636	};	636	};
637		637
638	struct mlx5_vport_tbl_attr {	638	struct mlx5_vport_tbl_attr {
639	u16 chain;	639	u32 chain;
640	u16 prio;	640	u16 prio;
641	u16 vport;	641	u16 vport;
642	const struct esw_vport_tbl_namespace *vport_ns;	642	const struct esw_vport_tbl_namespace *vport_ns;

drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c+7−3

 {
 	dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
 	dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport;
-	dest[dest_idx].vport.vhca_id =
+	if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
-		MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
+		dest[dest_idx].vport.vhca_id =
-	if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
+			MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
 		dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
+	}
 	if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP) {
 		if (pkt_reformat) {
 			flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
 	switch (event) {
 	case ESW_OFFLOADS_DEVCOM_PAIR:
+		if (mlx5_get_next_phys_dev(esw->dev) != peer_esw->dev)
+			break;
 		if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
 		    mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
 			break;

drivers/net/ethernet/mellanox/mlx5/core/fs_core.c+6−4

 static int connect_flow_table(struct mlx5_core_dev *dev, struct mlx5_flow_table *ft,
 			      struct fs_prio *prio)
 {
-	struct mlx5_flow_table *next_ft;
+	struct mlx5_flow_table *next_ft, *first_ft;
 	int err = 0;
 	/* Connect_prev_fts and update_root_ft_create are mutually exclusive */
-	if (list_empty(&prio->node.children)) {
+	first_ft = list_first_entry_or_null(&prio->node.children,
+					    struct mlx5_flow_table, node.list);
+	if (!first_ft || first_ft->level > ft->level) {
 		err = connect_prev_fts(dev, ft, prio);
 		if (err)
 			return err;
-		next_ft = find_next_chained_ft(prio);
+		next_ft = first_ft ? first_ft : find_next_chained_ft(prio);
 		err = connect_fwd_rules(dev, ft, next_ft);
 		if (err)
 			return err;
 				node.list) == ft))
 		return 0;
-	next_ft = find_next_chained_ft(prio);
+	next_ft = find_next_ft(ft);
 	err = connect_fwd_rules(dev, next_ft, ft);
 	if (err)
 		return err;

drivers/net/ethernet/mellanox/mlx5/core/health.c+10−2

 	}
 	fw_reporter_ctx.err_synd = health->synd;
 	fw_reporter_ctx.miss_counter = health->miss_counter;
-	devlink_health_report(health->fw_fatal_reporter,
+	if (devlink_health_report(health->fw_fatal_reporter,
-			      "FW fatal error reported", &fw_reporter_ctx);
+				  "FW fatal error reported", &fw_reporter_ctx) == -ECANCELED) {
+		/* If recovery wasn't performed, due to grace period,
+		 * unload the driver. This ensures that the driver
+		 * closes all its resources and it is not subjected to
+		 * requests from the kernel.
+		 */
+		mlx5_core_err(dev, "Driver is in error state. Unloading\n");
+		mlx5_unload_one(dev);
+	}
 }
 static const struct devlink_health_reporter_ops mlx5_fw_fatal_reporter_ops = {

drivers/net/ethernet/microchip/sparx5/Kconfig+1−0

@@ -3,6 +3,7 @@ config SPARX5_SWITCH · 2 unmodified lines
3	depends on NET_SWITCHDEV	3	depends on NET_SWITCHDEV
4	depends on HAS_IOMEM	4	depends on HAS_IOMEM
5	depends on OF	5	depends on OF
		6	depends on ARCH_SPARX5 \|\| COMPILE_TEST
6	select PHYLINK	7	select PHYLINK
7	select PHY_SPARX5_SERDES	8	select PHY_SPARX5_SERDES
8	select RESET_CONTROLLER	9	select RESET_CONTROLLER

drivers/net/ethernet/pensando/ionic/ionic_lif.c+96−101

@@ -29,7 +29,7 @@ static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { · 28 unmodified lines
29	*/	29	*/
30	};	30	};
31		31
32	static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode);	32	static void ionic_lif_rx_mode(struct ionic_lif *lif);
33	static int ionic_lif_addr_add(struct ionic_lif lif, const u8 addr);	33	static int ionic_lif_addr_add(struct ionic_lif lif, const u8 addr);
34	static int ionic_lif_addr_del(struct ionic_lif lif, const u8 addr);	34	static int ionic_lif_addr_del(struct ionic_lif lif, const u8 addr);
35	static void ionic_link_status_check(struct ionic_lif *lif);	35	static void ionic_link_status_check(struct ionic_lif *lif);
@@ -53,7 +53,19 @@ static void ionic_dim_work(struct work_struct *work) · 17 unmodified lines
53	cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix);	53	cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
54	qcq = container_of(dim, struct ionic_qcq, dim);	54	qcq = container_of(dim, struct ionic_qcq, dim);
55	new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec);	55	new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec);
56	qcq->intr.dim_coal_hw = new_coal ? new_coal : 1;	56	new_coal = new_coal ? new_coal : 1;
		57
		58	if (qcq->intr.dim_coal_hw != new_coal) {
		59	unsigned int qi = qcq->cq.bound_q->index;
		60	struct ionic_lif *lif = qcq->q.lif;
		61
		62	qcq->intr.dim_coal_hw = new_coal;
		63
		64	ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
		65	lif->rxqcqs[qi]->intr.index,
		66	qcq->intr.dim_coal_hw);
		67	}
		68
57	dim->state = DIM_START_MEASURE;	69	dim->state = DIM_START_MEASURE;
58	}	70	}
59		71
@@ -77,7 +89,7 @@ static void ionic_lif_deferred_work(struct work_struct *work) · 17 unmodified lines
77		89
78	switch (w->type) {	90	switch (w->type) {
79	case IONIC_DW_TYPE_RX_MODE:	91	case IONIC_DW_TYPE_RX_MODE:
80	ionic_lif_rx_mode(lif, w->rx_mode);	92	ionic_lif_rx_mode(lif);
81	break;	93	break;
82	case IONIC_DW_TYPE_RX_ADDR_ADD:	94	case IONIC_DW_TYPE_RX_ADDR_ADD:
83	ionic_lif_addr_add(lif, w->addr);	95	ionic_lif_addr_add(lif, w->addr);
@@ -1301,10 +1313,8 @@ static int ionic_lif_addr_del(struct ionic_lif lif, const u8 addr) · 1217 unmodified lines
1301	return 0;	1313	return 0;
1302	}	1314	}
1303		1315
1304	static int ionic_lif_addr(struct ionic_lif lif, const u8 addr, bool add,	1316	static int ionic_lif_addr(struct ionic_lif lif, const u8 addr, bool add)
1305	bool can_sleep)
1306	{	1317	{
1307	struct ionic_deferred_work *work;
1308	unsigned int nmfilters;	1318	unsigned int nmfilters;
1309	unsigned int nufilters;	1319	unsigned int nufilters;
1310		1320
@@ -1330,97 +1340,46 @@ static int ionic_lif_addr(struct ionic_lif lif, const u8 addr, bool add, · 19 unmodified lines
1330	lif->nucast--;	1340	lif->nucast--;
1331	}	1341	}
1332		1342
1333	if (!can_sleep) {	1343	netdev_dbg(lif->netdev, "rx_filter %s %pM\n",
1334	work = kzalloc(sizeof(*work), GFP_ATOMIC);	1344	add ? "add" : "del", addr);
1335	if (!work)	1345	if (add)
1336	return -ENOMEM;	1346	return ionic_lif_addr_add(lif, addr);
1337	work->type = add ? IONIC_DW_TYPE_RX_ADDR_ADD :	1347	else
1338	IONIC_DW_TYPE_RX_ADDR_DEL;	1348	return ionic_lif_addr_del(lif, addr);
1339	memcpy(work->addr, addr, ETH_ALEN);
1340	netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n",
1341	add ? "add" : "del", addr);
1342	ionic_lif_deferred_enqueue(&lif->deferred, work);
1343	} else {
1344	netdev_dbg(lif->netdev, "rx_filter %s %pM\n",
1345	add ? "add" : "del", addr);
1346	if (add)
1347	return ionic_lif_addr_add(lif, addr);
1348	else
1349	return ionic_lif_addr_del(lif, addr);
1350	}
1351		1349
1352	return 0;	1350	return 0;
1353	}	1351	}
1354		1352
1355	static int ionic_addr_add(struct net_device netdev, const u8 addr)	1353	static int ionic_addr_add(struct net_device netdev, const u8 addr)
1356	{	1354	{
1357	return ionic_lif_addr(netdev_priv(netdev), addr, ADD_ADDR, CAN_SLEEP);	1355	return ionic_lif_addr(netdev_priv(netdev), addr, ADD_ADDR);
1358	}
1359
1360	static int ionic_ndo_addr_add(struct net_device netdev, const u8 addr)
1361	{
1362	return ionic_lif_addr(netdev_priv(netdev), addr, ADD_ADDR, CAN_NOT_SLEEP);
1363	}	1356	}
1364		1357
1365	static int ionic_addr_del(struct net_device netdev, const u8 addr)	1358	static int ionic_addr_del(struct net_device netdev, const u8 addr)
1366	{	1359	{
1367	return ionic_lif_addr(netdev_priv(netdev), addr, DEL_ADDR, CAN_SLEEP);	1360	return ionic_lif_addr(netdev_priv(netdev), addr, DEL_ADDR);
1368	}	1361	}
1369		1362
1370	static int ionic_ndo_addr_del(struct net_device netdev, const u8 addr)	1363	static void ionic_lif_rx_mode(struct ionic_lif *lif)
1371	{	1364	{
1372	return ionic_lif_addr(netdev_priv(netdev), addr, DEL_ADDR, CAN_NOT_SLEEP);	1365	struct net_device *netdev = lif->netdev;
1373	}	1366	unsigned int nfilters;
1374		1367	unsigned int nd_flags;
1375	static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode)
1376	{
1377	struct ionic_admin_ctx ctx = {
1378	.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1379	.cmd.rx_mode_set = {
1380	.opcode = IONIC_CMD_RX_MODE_SET,
1381	.lif_index = cpu_to_le16(lif->index),
1382	.rx_mode = cpu_to_le16(rx_mode),
1383	},
1384	};
1385	char buf[128];	1368	char buf[128];
1386	int err;	1369	u16 rx_mode;
1387	int i;	1370	int i;
1388	#define REMAIN(__x) (sizeof(buf) - (__x))	1371	#define REMAIN(__x) (sizeof(buf) - (__x))
1389		1372
1390	i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:",	1373	mutex_lock(&lif->config_lock);
1391	lif->rx_mode, rx_mode);
1392	if (rx_mode & IONIC_RX_MODE_F_UNICAST)
1393	i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST");
1394	if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
1395	i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST");
1396	if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
1397	i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST");
1398	if (rx_mode & IONIC_RX_MODE_F_PROMISC)
1399	i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC");
1400	if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
1401	i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI");
1402	netdev_dbg(lif->netdev, "lif%d %s\n", lif->index, buf);
1403
1404	err = ionic_adminq_post_wait(lif, &ctx);
1405	if (err)
1406	netdev_warn(lif->netdev, "set rx_mode 0x%04x failed: %d\n",
1407	rx_mode, err);
1408	else
1409	lif->rx_mode = rx_mode;
1410	}
1411		1374
1412	static void ionic_set_rx_mode(struct net_device *netdev, bool can_sleep)	1375	/* grab the flags once for local use */
1413	{	1376	nd_flags = netdev->flags;
1414	struct ionic_lif *lif = netdev_priv(netdev);
1415	struct ionic_deferred_work *work;
1416	unsigned int nfilters;
1417	unsigned int rx_mode;
1418		1377
1419	rx_mode = IONIC_RX_MODE_F_UNICAST;	1378	rx_mode = IONIC_RX_MODE_F_UNICAST;
1420	rx_mode \|= (netdev->flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0;	1379	rx_mode \|= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0;
1421	rx_mode \|= (netdev->flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0;	1380	rx_mode \|= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0;
1422	rx_mode \|= (netdev->flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0;	1381	rx_mode \|= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0;
1423	rx_mode \|= (netdev->flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0;	1382	rx_mode \|= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0;
1424		1383
1425	/* sync unicast addresses	1384	/* sync unicast addresses
1426	* next check to see if we're in an overflow state	1385	* next check to see if we're in an overflow state
@@ -1429,49 +1388,83 @@ static void ionic_set_rx_mode(struct net_device *netdev, bool can_sleep) · 2 unmodified lines
1429	* we remove our overflow flag and check the netdev flags	1388	* we remove our overflow flag and check the netdev flags
1430	* to see if we can disable NIC PROMISC	1389	* to see if we can disable NIC PROMISC
1431	*/	1390	*/
1432	if (can_sleep)	1391	__dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del);
1433	__dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del);
1434	else
1435	__dev_uc_sync(netdev, ionic_ndo_addr_add, ionic_ndo_addr_del);
1436	nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters);	1392	nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters);
1437	if (netdev_uc_count(netdev) + 1 > nfilters) {	1393	if (netdev_uc_count(netdev) + 1 > nfilters) {
1438	rx_mode \|= IONIC_RX_MODE_F_PROMISC;	1394	rx_mode \|= IONIC_RX_MODE_F_PROMISC;
1439	lif->uc_overflow = true;	1395	lif->uc_overflow = true;
1440	} else if (lif->uc_overflow) {	1396	} else if (lif->uc_overflow) {
1441	lif->uc_overflow = false;	1397	lif->uc_overflow = false;
1442	if (!(netdev->flags & IFF_PROMISC))	1398	if (!(nd_flags & IFF_PROMISC))
1443	rx_mode &= ~IONIC_RX_MODE_F_PROMISC;	1399	rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
1444	}	1400	}
1445		1401
1446	/* same for multicast */	1402	/* same for multicast */
1447	if (can_sleep)	1403	__dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del);
1448	__dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del);
1449	else
1450	__dev_mc_sync(netdev, ionic_ndo_addr_add, ionic_ndo_addr_del);
1451	nfilters = le32_to_cpu(lif->identity->eth.max_mcast_filters);	1404	nfilters = le32_to_cpu(lif->identity->eth.max_mcast_filters);
1452	if (netdev_mc_count(netdev) > nfilters) {	1405	if (netdev_mc_count(netdev) > nfilters) {
1453	rx_mode \|= IONIC_RX_MODE_F_ALLMULTI;	1406	rx_mode \|= IONIC_RX_MODE_F_ALLMULTI;
1454	lif->mc_overflow = true;	1407	lif->mc_overflow = true;
1455	} else if (lif->mc_overflow) {	1408	} else if (lif->mc_overflow) {
1456	lif->mc_overflow = false;	1409	lif->mc_overflow = false;
1457	if (!(netdev->flags & IFF_ALLMULTI))	1410	if (!(nd_flags & IFF_ALLMULTI))
1458	rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;	1411	rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
1459	}	1412	}
1460		1413
		1414	i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:",
		1415	lif->rx_mode, rx_mode);
		1416	if (rx_mode & IONIC_RX_MODE_F_UNICAST)
		1417	i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST");
		1418	if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
		1419	i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST");
		1420	if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
		1421	i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST");
		1422	if (rx_mode & IONIC_RX_MODE_F_PROMISC)
		1423	i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC");
		1424	if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
		1425	i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI");
		1426	if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER)
		1427	i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER");
		1428	netdev_dbg(netdev, "lif%d %s\n", lif->index, buf);
		1429
1461	if (lif->rx_mode != rx_mode) {	1430	if (lif->rx_mode != rx_mode) {
1462	if (!can_sleep) {	1431	struct ionic_admin_ctx ctx = {
1463	work = kzalloc(sizeof(*work), GFP_ATOMIC);	1432	.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1464	if (!work) {	1433	.cmd.rx_mode_set = {
1465	netdev_err(lif->netdev, "rxmode change dropped\n");	1434	.opcode = IONIC_CMD_RX_MODE_SET,
1466	return;	1435	.lif_index = cpu_to_le16(lif->index),
1467	}	1436	},
1468	work->type = IONIC_DW_TYPE_RX_MODE;	1437	};
1469	work->rx_mode = rx_mode;	1438	int err;
1470	netdev_dbg(lif->netdev, "deferred: rx_mode\n");	1439
1471	ionic_lif_deferred_enqueue(&lif->deferred, work);	1440	ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode);
1472	} else {	1441	err = ionic_adminq_post_wait(lif, &ctx);
1473	ionic_lif_rx_mode(lif, rx_mode);	1442	if (err)
		1443	netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n",
		1444	rx_mode, err);
		1445	else
		1446	lif->rx_mode = rx_mode;
		1447	}
		1448
		1449	mutex_unlock(&lif->config_lock);
		1450	}
		1451
		1452	static void ionic_set_rx_mode(struct net_device *netdev, bool can_sleep)
		1453	{
		1454	struct ionic_lif *lif = netdev_priv(netdev);
		1455	struct ionic_deferred_work *work;
		1456
		1457	if (!can_sleep) {
		1458	work = kzalloc(sizeof(*work), GFP_ATOMIC);
		1459	if (!work) {
		1460	netdev_err(lif->netdev, "rxmode change dropped\n");
		1461	return;
1474	}	1462	}
		1463	work->type = IONIC_DW_TYPE_RX_MODE;
		1464	netdev_dbg(lif->netdev, "deferred: rx_mode\n");
		1465	ionic_lif_deferred_enqueue(&lif->deferred, work);
		1466	} else {
		1467	ionic_lif_rx_mode(lif);
1475	}	1468	}
1476	}	1469	}
1477		1470
@@ -3058,6 +3051,7 @@ void ionic_lif_deinit(struct ionic_lif *lif) · 1580 unmodified lines
3058	ionic_lif_qcq_deinit(lif, lif->notifyqcq);	3051	ionic_lif_qcq_deinit(lif, lif->notifyqcq);
3059	ionic_lif_qcq_deinit(lif, lif->adminqcq);	3052	ionic_lif_qcq_deinit(lif, lif->adminqcq);
3060		3053
		3054	mutex_destroy(&lif->config_lock);
3061	mutex_destroy(&lif->queue_lock);	3055	mutex_destroy(&lif->queue_lock);
3062	ionic_lif_reset(lif);	3056	ionic_lif_reset(lif);
3063	}	3057	}
@@ -3185,7 +3179,7 @@ static int ionic_station_set(struct ionic_lif *lif) · 121 unmodified lines
3185	*/	3179	*/
3186	if (!ether_addr_equal(ctx.comp.lif_getattr.mac,	3180	if (!ether_addr_equal(ctx.comp.lif_getattr.mac,
3187	netdev->dev_addr))	3181	netdev->dev_addr))
3188	ionic_lif_addr(lif, netdev->dev_addr, ADD_ADDR, CAN_SLEEP);	3182	ionic_lif_addr(lif, netdev->dev_addr, ADD_ADDR);
3189	} else {	3183	} else {
3190	/* Update the netdev mac with the device's mac */	3184	/* Update the netdev mac with the device's mac */
3191	memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len);	3185	memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len);
@@ -3202,7 +3196,7 @@ static int ionic_station_set(struct ionic_lif *lif) · 10 unmodified lines
3202		3196
3203	netdev_dbg(lif->netdev, "adding station MAC addr %pM\n",	3197	netdev_dbg(lif->netdev, "adding station MAC addr %pM\n",
3204	netdev->dev_addr);	3198	netdev->dev_addr);
3205	ionic_lif_addr(lif, netdev->dev_addr, ADD_ADDR, CAN_SLEEP);	3199	ionic_lif_addr(lif, netdev->dev_addr, ADD_ADDR);
3206		3200
3207	return 0;	3201	return 0;
3208	}	3202	}
@@ -3225,6 +3219,7 @@ int ionic_lif_init(struct ionic_lif *lif) · 16 unmodified lines
3225		3219
3226	lif->hw_index = le16_to_cpu(comp.hw_index);	3220	lif->hw_index = le16_to_cpu(comp.hw_index);
3227	mutex_init(&lif->queue_lock);	3221	mutex_init(&lif->queue_lock);
		3222	mutex_init(&lif->config_lock);
3228		3223
3229	/* now that we have the hw_index we can figure out our doorbell page */	3224	/* now that we have the hw_index we can figure out our doorbell page */
3230	lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif);	3225	lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif);

drivers/net/ethernet/pensando/ionic/ionic_lif.h+4−7

 	struct list_head list;
 	enum ionic_deferred_work_type type;
 	union {
-		unsigned int rx_mode;
 		u8 addr[ETH_ALEN];
 		u8 fw_status;
 	};
 	unsigned int index;
 	unsigned int hw_index;
 	struct mutex queue_lock;	/* lock for queue structures */
+	struct mutex config_lock;	/* lock for config actions */
 	spinlock_t adminq_lock;		/* lock for AdminQ operations */
 	struct ionic_qcq *adminqcq;
 	struct ionic_qcq *notifyqcq;
 	unsigned int nrxq_descs;
 	u32 rx_copybreak;
 	u64 rxq_features;
-	unsigned int rx_mode;
+	u16 rx_mode;
 	u64 hw_features;
 	bool registered;
 	bool mc_overflow;
 int ionic_lif_size(struct ionic *ionic);
 #if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
-int ionic_lif_hwstamp_replay(struct ionic_lif *lif);
+void ionic_lif_hwstamp_replay(struct ionic_lif *lif);
 int ionic_lif_hwstamp_set(struct ionic_lif *lif, struct ifreq *ifr);
 int ionic_lif_hwstamp_get(struct ionic_lif *lif, struct ifreq *ifr);
 ktime_t ionic_lif_phc_ktime(struct ionic_lif *lif, u64 counter);
 void ionic_lif_alloc_phc(struct ionic_lif *lif);
 void ionic_lif_free_phc(struct ionic_lif *lif);
 #else
-static inline int ionic_lif_hwstamp_replay(struct ionic_lif *lif)
+static inline void ionic_lif_hwstamp_replay(struct ionic_lif *lif) {}
-{
-	return -EOPNOTSUPP;
-}
 static inline int ionic_lif_hwstamp_set(struct ionic_lif *lif, struct ifreq *ifr)
 {

drivers/net/ethernet/pensando/ionic/ionic_phc.c+7−3

 	struct hwtstamp_config config;
 	int err;
+	if (!lif->phc || !lif->phc->ptp)
+		return -EOPNOTSUPP;
 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 		return -EFAULT;
 	return 0;
 }
-int ionic_lif_hwstamp_replay(struct ionic_lif *lif)
+void ionic_lif_hwstamp_replay(struct ionic_lif *lif)
 {
 	int err;
+	if (!lif->phc || !lif->phc->ptp)
+		return;
 	err = ionic_lif_hwstamp_set_ts_config(lif, NULL);
 	if (err)
 		netdev_info(lif->netdev, "hwstamp replay failed: %d\n", err);
-	return err;
 }
 int ionic_lif_hwstamp_get(struct ionic_lif *lif, struct ifreq *ifr)

drivers/net/ethernet/pensando/ionic/ionic_txrx.c+25−16

 		}
 	}
-	if (likely(netdev->features & NETIF_F_RXCSUM)) {
+	if (likely(netdev->features & NETIF_F_RXCSUM) &&
-		if (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) {
+	    (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC)) {
-			skb->ip_summed = CHECKSUM_COMPLETE;
+		skb->ip_summed = CHECKSUM_COMPLETE;
-			skb->csum = (__force __wsum)le16_to_cpu(comp->csum);
+		skb->csum = (__force __wsum)le16_to_cpu(comp->csum);
-			stats->csum_complete++;
+		stats->csum_complete++;
-		}
 	} else {
 		stats->csum_none++;
 	}
 	q->tail_idx = 0;
 }
-static void ionic_dim_update(struct ionic_qcq *qcq)
+static void ionic_dim_update(struct ionic_qcq *qcq, int napi_mode)
 {
 	struct dim_sample dim_sample;
 	struct ionic_lif *lif;
 	unsigned int qi;
+	u64 pkts, bytes;
 	if (!qcq->intr.dim_coal_hw)
 		return;
 	lif = qcq->q.lif;
 	qi = qcq->cq.bound_q->index;
-	ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
+	switch (napi_mode) {
-			     lif->rxqcqs[qi]->intr.index,
+	case IONIC_LIF_F_TX_DIM_INTR:
-			     qcq->intr.dim_coal_hw);
+		pkts = lif->txqstats[qi].pkts;
+		bytes = lif->txqstats[qi].bytes;
+		break;
+	case IONIC_LIF_F_RX_DIM_INTR:
+		pkts = lif->rxqstats[qi].pkts;
+		bytes = lif->rxqstats[qi].bytes;
+		break;
+	default:
+		pkts = lif->txqstats[qi].pkts + lif->rxqstats[qi].pkts;
+		bytes = lif->txqstats[qi].bytes + lif->rxqstats[qi].bytes;
+		break;
+	}
 	dim_update_sample(qcq->cq.bound_intr->rearm_count,
-			  lif->txqstats[qi].pkts,
+			  pkts, bytes, &dim_sample);
-			  lif->txqstats[qi].bytes,
-			  &dim_sample);
 	net_dim(&qcq->dim, dim_sample);
 }
 				     ionic_tx_service, NULL, NULL);
 	if (work_done < budget && napi_complete_done(napi, work_done)) {
-		ionic_dim_update(qcq);
+		ionic_dim_update(qcq, IONIC_LIF_F_TX_DIM_INTR);
 		flags |= IONIC_INTR_CRED_UNMASK;
 		cq->bound_intr->rearm_count++;
 	}
 		ionic_rx_fill(cq->bound_q);
 	if (work_done < budget && napi_complete_done(napi, work_done)) {
-		ionic_dim_update(qcq);
+		ionic_dim_update(qcq, IONIC_LIF_F_RX_DIM_INTR);
 		flags |= IONIC_INTR_CRED_UNMASK;
 		cq->bound_intr->rearm_count++;
 	}
 		ionic_rx_fill(rxcq->bound_q);
 	if (rx_work_done < budget && napi_complete_done(napi, rx_work_done)) {
-		ionic_dim_update(qcq);
+		ionic_dim_update(qcq, 0);
 		flags |= IONIC_INTR_CRED_UNMASK;
 		rxcq->bound_intr->rearm_count++;
 	}

drivers/net/ethernet/qlogic/qede/qede_filter.c+2−2

@@ -831,7 +831,7 @@ int qede_configure_vlan_filters(struct qede_dev *edev) · 830 unmodified lines
831	int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)	831	int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
832	{	832	{
833	struct qede_dev *edev = netdev_priv(dev);	833	struct qede_dev *edev = netdev_priv(dev);
834	struct qede_vlan *vlan = NULL;	834	struct qede_vlan *vlan;
835	int rc = 0;	835	int rc = 0;
836		836
837	DP_VERBOSE(edev, NETIF_MSG_IFDOWN, "Removing vlan 0x%04x\n", vid);	837	DP_VERBOSE(edev, NETIF_MSG_IFDOWN, "Removing vlan 0x%04x\n", vid);
@@ -842,7 +842,7 @@ int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) · 4 unmodified lines
842	if (vlan->vid == vid)	842	if (vlan->vid == vid)
843	break;	843	break;
844		844
845	if (!vlan \|\| (vlan->vid != vid)) {	845	if (list_entry_is_head(vlan, &edev->vlan_list, list)) {
846	DP_VERBOSE(edev, (NETIF_MSG_IFUP \| NETIF_MSG_IFDOWN),	846	DP_VERBOSE(edev, (NETIF_MSG_IFUP \| NETIF_MSG_IFDOWN),
847	"Vlan isn't configured\n");	847	"Vlan isn't configured\n");
848	goto out;	848	goto out;

drivers/net/ethernet/qlogic/qla3xxx.c+3−3

@@ -154,7 +154,7 @@ static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev) · 153 unmodified lines
154	"driver lock acquired\n");	154	"driver lock acquired\n");
155	return 1;	155	return 1;
156	}	156	}
157	ssleep(1);	157	mdelay(1000);
158	} while (++i < 10);	158	} while (++i < 10);
159		159
160	netdev_err(qdev->ndev, "Timed out waiting for driver lock...\n");	160	netdev_err(qdev->ndev, "Timed out waiting for driver lock...\n");
@@ -3274,7 +3274,7 @@ static int ql_adapter_reset(struct ql3_adapter *qdev) · 3113 unmodified lines
3274	if ((value & ISP_CONTROL_SR) == 0)	3274	if ((value & ISP_CONTROL_SR) == 0)
3275	break;	3275	break;
3276		3276
3277	ssleep(1);	3277	mdelay(1000);
3278	} while ((--max_wait_time));	3278	} while ((--max_wait_time));
3279		3279
3280	/*	3280	/*
@@ -3310,7 +3310,7 @@ static int ql_adapter_reset(struct ql3_adapter *qdev) · 29 unmodified lines
3310	ispControlStatus);	3310	ispControlStatus);
3311	if ((value & ISP_CONTROL_FSR) == 0)	3311	if ((value & ISP_CONTROL_FSR) == 0)
3312	break;	3312	break;
3313	ssleep(1);	3313	mdelay(1000);
3314	} while ((--max_wait_time));	3314	} while ((--max_wait_time));
3315	}	3315	}
3316	if (max_wait_time == 0)	3316	if (max_wait_time == 0)

drivers/net/ethernet/realtek/r8169_main.c+2−1

@@ -5084,7 +5084,8 @@ static int r8169_mdio_register(struct rtl8169_private *tp) · 5083 unmodified lines
5084	new_bus->priv = tp;	5084	new_bus->priv = tp;
5085	new_bus->parent = &pdev->dev;	5085	new_bus->parent = &pdev->dev;
5086	new_bus->irq[0] = PHY_MAC_INTERRUPT;	5086	new_bus->irq[0] = PHY_MAC_INTERRUPT;
5087	snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));	5087	snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
		5088	pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5088		5089
5089	new_bus->read = r8169_mdio_read_reg;	5090	new_bus->read = r8169_mdio_read_reg;
5090	new_bus->write = r8169_mdio_write_reg;	5091	new_bus->write = r8169_mdio_write_reg;

drivers/net/ethernet/renesas/ravb.h+1−1

@@ -864,7 +864,7 @@ enum GECMR_BIT { · 863 unmodified lines
864		864
865	/* The Ethernet AVB descriptor definitions. */	865	/* The Ethernet AVB descriptor definitions. */
866	struct ravb_desc {	866	struct ravb_desc {
867	__le16 ds; /* Descriptor size */	867	__le16 ds; /* Descriptor size */
868	u8 cc; /* Content control MSBs (reserved) */	868	u8 cc; /* Content control MSBs (reserved) */
869	u8 die_dt; /* Descriptor interrupt enable and type */	869	u8 die_dt; /* Descriptor interrupt enable and type */
870	__le32 dptr; /* Descriptor pointer */	870	__le32 dptr; /* Descriptor pointer */

drivers/net/ethernet/renesas/ravb_main.c+1−1

@@ -920,7 +920,7 @@ static int ravb_poll(struct napi_struct *napi, int budget) · 919 unmodified lines
920	if (ravb_rx(ndev, &quota, q))	920	if (ravb_rx(ndev, &quota, q))
921	goto out;	921	goto out;
922		922
923	/* Processing RX Descriptor Ring */	923	/* Processing TX Descriptor Ring */
924	spin_lock_irqsave(&priv->lock, flags);	924	spin_lock_irqsave(&priv->lock, flags);
925	/* Clear TX interrupt */	925	/* Clear TX interrupt */
926	ravb_write(ndev, ~(mask \| TIS_RESERVED), TIS);	926	ravb_write(ndev, ~(mask \| TIS_RESERVED), TIS);

drivers/net/ethernet/sis/sis900.c+2−5

 #endif
 	/* setup various bits in PCI command register */
-	ret = pci_enable_device(pci_dev);
+	ret = pcim_enable_device(pci_dev);
 	if(ret) return ret;
 	i = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32));
 	ioaddr = pci_iomap(pci_dev, 0, 0);
 	if (!ioaddr) {
 		ret = -ENOMEM;
-		goto err_out_cleardev;
+		goto err_out;
 	}
 	sis_priv = netdev_priv(net_dev);
 			  sis_priv->tx_ring_dma);
 err_out_unmap:
 	pci_iounmap(pci_dev, ioaddr);
-err_out_cleardev:
-	pci_release_regions(pci_dev);
  err_out:
 	free_netdev(net_dev);
 	return ret;
 			  sis_priv->tx_ring_dma);
 	pci_iounmap(pci_dev, sis_priv->ioaddr);
 	free_netdev(net_dev);
-	pci_release_regions(pci_dev);
 }
 static int __maybe_unused sis900_suspend(struct device *dev)

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c+2−0

 	.config_l3_filter = dwmac4_config_l3_filter,
 	.config_l4_filter = dwmac4_config_l4_filter,
 	.est_configure = dwmac5_est_configure,
+	.est_irq_status = dwmac5_est_irq_status,
 	.fpe_configure = dwmac5_fpe_configure,
 	.fpe_send_mpacket = dwmac5_fpe_send_mpacket,
 	.fpe_irq_status = dwmac5_fpe_irq_status,
 	.config_l3_filter = dwmac4_config_l3_filter,
 	.config_l4_filter = dwmac4_config_l4_filter,
 	.est_configure = dwmac5_est_configure,
+	.est_irq_status = dwmac5_est_irq_status,
 	.fpe_configure = dwmac5_fpe_configure,
 	.fpe_send_mpacket = dwmac5_fpe_send_mpacket,
 	.fpe_irq_status = dwmac5_fpe_irq_status,

drivers/net/ethernet/sun/niu.c+2−1

 		err = niu_pci_vpd_scan_props(np, here, end);
 		if (err < 0)
 			return err;
+		/* ret == 1 is not an error */
 		if (err == 1)
-			return -EINVAL;
+			return 0;
 	}
 	return 0;
 }

drivers/net/ethernet/xscale/ptp_ixp46x.c+2−0

@@ -14,6 +14,8 @@ · 13 unmodified lines
14	#include <linux/kernel.h>	14	#include <linux/kernel.h>
15	#include <linux/ptp_clock_kernel.h>	15	#include <linux/ptp_clock_kernel.h>
16	#include <linux/soc/ixp4xx/cpu.h>	16	#include <linux/soc/ixp4xx/cpu.h>
		17	#include <linux/module.h>
		18	#include <mach/ixp4xx-regs.h>
17		19
18	#include "ixp46x_ts.h"	20	#include "ixp46x_ts.h"
19		21

drivers/net/phy/broadcom.c+1−1

@@ -288,7 +288,7 @@ static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev) · 287 unmodified lines
288	if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {	288	if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {
289	if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E \|\|	289	if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E \|\|
290	BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 \|\|	290	BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 \|\|
291	BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E)	291	BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811)
292	val \|= BCM54XX_SHD_SCR3_RXCTXC_DIS;	292	val \|= BCM54XX_SHD_SCR3_RXCTXC_DIS;
293	else	293	else
294	val \|= BCM54XX_SHD_SCR3_TRDDAPD;	294	val \|= BCM54XX_SHD_SCR3_TRDDAPD;

drivers/net/usb/hso.c+23−10

@@ -2495,7 +2495,7 @@ static struct hso_device hso_create_net_device(struct usb_interface interface, · 2494 unmodified lines
2495	hso_net_init);	2495	hso_net_init);
2496	if (!net) {	2496	if (!net) {
2497	dev_err(&interface->dev, "Unable to create ethernet device\n");	2497	dev_err(&interface->dev, "Unable to create ethernet device\n");
2498	goto exit;	2498	goto err_hso_dev;
2499	}	2499	}
2500		2500
2501	hso_net = netdev_priv(net);	2501	hso_net = netdev_priv(net);
@@ -2508,13 +2508,13 @@ static struct hso_device hso_create_net_device(struct usb_interface interface, · 6 unmodified lines
2508	USB_DIR_IN);	2508	USB_DIR_IN);
2509	if (!hso_net->in_endp) {	2509	if (!hso_net->in_endp) {
2510	dev_err(&interface->dev, "Can't find BULK IN endpoint\n");	2510	dev_err(&interface->dev, "Can't find BULK IN endpoint\n");
2511	goto exit;	2511	goto err_net;
2512	}	2512	}
2513	hso_net->out_endp = hso_get_ep(interface, USB_ENDPOINT_XFER_BULK,	2513	hso_net->out_endp = hso_get_ep(interface, USB_ENDPOINT_XFER_BULK,
2514	USB_DIR_OUT);	2514	USB_DIR_OUT);
2515	if (!hso_net->out_endp) {	2515	if (!hso_net->out_endp) {
2516	dev_err(&interface->dev, "Can't find BULK OUT endpoint\n");	2516	dev_err(&interface->dev, "Can't find BULK OUT endpoint\n");
2517	goto exit;	2517	goto err_net;
2518	}	2518	}
2519	SET_NETDEV_DEV(net, &interface->dev);	2519	SET_NETDEV_DEV(net, &interface->dev);
2520	SET_NETDEV_DEVTYPE(net, &hso_type);	2520	SET_NETDEV_DEVTYPE(net, &hso_type);
@@ -2523,18 +2523,18 @@ static struct hso_device hso_create_net_device(struct usb_interface interface, · 2 unmodified lines
2523	for (i = 0; i < MUX_BULK_RX_BUF_COUNT; i++) {	2523	for (i = 0; i < MUX_BULK_RX_BUF_COUNT; i++) {
2524	hso_net->mux_bulk_rx_urb_pool[i] = usb_alloc_urb(0, GFP_KERNEL);	2524	hso_net->mux_bulk_rx_urb_pool[i] = usb_alloc_urb(0, GFP_KERNEL);
2525	if (!hso_net->mux_bulk_rx_urb_pool[i])	2525	if (!hso_net->mux_bulk_rx_urb_pool[i])
2526	goto exit;	2526	goto err_mux_bulk_rx;
2527	hso_net->mux_bulk_rx_buf_pool[i] = kzalloc(MUX_BULK_RX_BUF_SIZE,	2527	hso_net->mux_bulk_rx_buf_pool[i] = kzalloc(MUX_BULK_RX_BUF_SIZE,
2528	GFP_KERNEL);	2528	GFP_KERNEL);
2529	if (!hso_net->mux_bulk_rx_buf_pool[i])	2529	if (!hso_net->mux_bulk_rx_buf_pool[i])
2530	goto exit;	2530	goto err_mux_bulk_rx;
2531	}	2531	}
2532	hso_net->mux_bulk_tx_urb = usb_alloc_urb(0, GFP_KERNEL);	2532	hso_net->mux_bulk_tx_urb = usb_alloc_urb(0, GFP_KERNEL);
2533	if (!hso_net->mux_bulk_tx_urb)	2533	if (!hso_net->mux_bulk_tx_urb)
2534	goto exit;	2534	goto err_mux_bulk_rx;
2535	hso_net->mux_bulk_tx_buf = kzalloc(MUX_BULK_TX_BUF_SIZE, GFP_KERNEL);	2535	hso_net->mux_bulk_tx_buf = kzalloc(MUX_BULK_TX_BUF_SIZE, GFP_KERNEL);
2536	if (!hso_net->mux_bulk_tx_buf)	2536	if (!hso_net->mux_bulk_tx_buf)
2537	goto exit;	2537	goto err_free_tx_urb;
2538		2538
2539	add_net_device(hso_dev);	2539	add_net_device(hso_dev);
2540		2540
@@ -2542,7 +2542,7 @@ static struct hso_device hso_create_net_device(struct usb_interface interface, · 1 unmodified line
2542	result = register_netdev(net);	2542	result = register_netdev(net);
2543	if (result) {	2543	if (result) {
2544	dev_err(&interface->dev, "Failed to register device\n");	2544	dev_err(&interface->dev, "Failed to register device\n");
2545	goto exit;	2545	goto err_free_tx_buf;
2546	}	2546	}
2547		2547
2548	hso_log_port(hso_dev);	2548	hso_log_port(hso_dev);
@@ -2550,8 +2550,21 @@ static struct hso_device hso_create_net_device(struct usb_interface interface, · 1 unmodified line
2550	hso_create_rfkill(hso_dev, interface);	2550	hso_create_rfkill(hso_dev, interface);
2551		2551
2552	return hso_dev;	2552	return hso_dev;
2553	exit:	2553
2554	hso_free_net_device(hso_dev, true);	2554	err_free_tx_buf:
		2555	remove_net_device(hso_dev);
		2556	kfree(hso_net->mux_bulk_tx_buf);
		2557	err_free_tx_urb:
		2558	usb_free_urb(hso_net->mux_bulk_tx_urb);
		2559	err_mux_bulk_rx:
		2560	for (i = 0; i < MUX_BULK_RX_BUF_COUNT; i++) {
		2561	usb_free_urb(hso_net->mux_bulk_rx_urb_pool[i]);
		2562	kfree(hso_net->mux_bulk_rx_buf_pool[i]);
		2563	}
		2564	err_net:
		2565	free_netdev(net);
		2566	err_hso_dev:
		2567	kfree(hso_dev);
2555	return NULL;	2568	return NULL;
2556	}	2569	}
2557		2570

drivers/net/usb/r8152.c+20−10

 rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
 		  u32 advertising);
-static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
+static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
+				     bool in_resume)
 {
 	struct r8152 *tp = netdev_priv(netdev);
 	struct sockaddr *addr = p;
 	if (!is_valid_ether_addr(addr->sa_data))
 		goto out1;
-	ret = usb_autopm_get_interface(tp->intf);
+	if (!in_resume) {
-	if (ret < 0)
+		ret = usb_autopm_get_interface(tp->intf);
-		goto out1;
+		if (ret < 0)
+			goto out1;
+	}
 	mutex_lock(&tp->control);
 	mutex_unlock(&tp->control);
-	usb_autopm_put_interface(tp->intf);
+	if (!in_resume)
+		usb_autopm_put_interface(tp->intf);
 out1:
 	return ret;
 }
+static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
+{
+	return __rtl8152_set_mac_address(netdev, p, false);
+}
 /* Devices containing proper chips can support a persistent
  * host system provided MAC address.
  * Examples of this are Dell TB15 and Dell WD15 docks
 	return ret;
 }
-static int set_ethernet_addr(struct r8152 *tp)
+static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
 {
 	struct net_device *dev = tp->netdev;
 	struct sockaddr sa;
 	if (tp->version == RTL_VER_01)
 		ether_addr_copy(dev->dev_addr, sa.sa_data);
 	else
-		ret = rtl8152_set_mac_address(dev, &sa);
+		ret = __rtl8152_set_mac_address(dev, &sa, in_resume);
 	return ret;
 }
 		tp->rtl_ops.down(tp);
 		mutex_unlock(&tp->control);
+	}
+	if (!res)
 		usb_autopm_put_interface(tp->intf);
-	}
 	free_all_mem(tp);
 	clear_bit(SELECTIVE_SUSPEND, &tp->flags);
 	tp->rtl_ops.init(tp);
 	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
-	set_ethernet_addr(tp);
+	set_ethernet_addr(tp, true);
 	return rtl8152_resume(intf);
 }
 	tp->rtl_fw.retry = true;
 #endif
 	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
-	set_ethernet_addr(tp);
+	set_ethernet_addr(tp, false);
 	usb_set_intfdata(intf, tp);

drivers/net/wireless/virt_wifi.c+32−20

 /* Assigned at module init. Guaranteed locally-administered and unicast. */
 static u8 fake_router_bssid[ETH_ALEN] __ro_after_init = {};
+static void virt_wifi_inform_bss(struct wiphy *wiphy)
+{
+	u64 tsf = div_u64(ktime_get_boottime_ns(), 1000);
+	struct cfg80211_bss *informed_bss;
+	static const struct {
+		u8 tag;
+		u8 len;
+		u8 ssid[8];
+	} __packed ssid = {
+		.tag = WLAN_EID_SSID,
+		.len = 8,
+		.ssid = "VirtWifi",
+	};
+	informed_bss = cfg80211_inform_bss(wiphy, &channel_5ghz,
+					   CFG80211_BSS_FTYPE_PRESP,
+					   fake_router_bssid, tsf,
+					   WLAN_CAPABILITY_ESS, 0,
+					   (void *)&ssid, sizeof(ssid),
+					   DBM_TO_MBM(-50), GFP_KERNEL);
+	cfg80211_put_bss(wiphy, informed_bss);
+}
 /* Called with the rtnl lock held. */
 static int virt_wifi_scan(struct wiphy *wiphy,
 			  struct cfg80211_scan_request *request)
 /* Acquires and releases the rdev BSS lock. */
 static void virt_wifi_scan_result(struct work_struct *work)
 {
-	struct {
-		u8 tag;
-		u8 len;
-		u8 ssid[8];
-	} __packed ssid = {
-		.tag = WLAN_EID_SSID, .len = 8, .ssid = "VirtWifi",
-	};
-	struct cfg80211_bss *informed_bss;
 	struct virt_wifi_wiphy_priv *priv =
 		container_of(work, struct virt_wifi_wiphy_priv,
 			     scan_result.work);
 	struct wiphy *wiphy = priv_to_wiphy(priv);
 	struct cfg80211_scan_info scan_info = { .aborted = false };
-	u64 tsf = div_u64(ktime_get_boottime_ns(), 1000);
-	informed_bss = cfg80211_inform_bss(wiphy, &channel_5ghz,
+	virt_wifi_inform_bss(wiphy);
-					   CFG80211_BSS_FTYPE_PRESP,
-					   fake_router_bssid, tsf,
-					   WLAN_CAPABILITY_ESS, 0,
-					   (void *)&ssid, sizeof(ssid),
-					   DBM_TO_MBM(-50), GFP_KERNEL);
-	cfg80211_put_bss(wiphy, informed_bss);
 	/* Schedules work which acquires and releases the rtnl lock. */
 	cfg80211_scan_done(priv->scan_request, &scan_info);
 	if (!could_schedule)
 		return -EBUSY;
-	if (sme->bssid)
+	if (sme->bssid) {
 		ether_addr_copy(priv->connect_requested_bss, sme->bssid);
-	else
+	} else {
+		virt_wifi_inform_bss(wiphy);
 		eth_zero_addr(priv->connect_requested_bss);
+	}
 	wiphy_debug(wiphy, "connect\n");
 	struct virt_wifi_netdev_priv *priv =
 		container_of(work, struct virt_wifi_netdev_priv, connect.work);
 	u8 *requested_bss = priv->connect_requested_bss;
-	bool has_addr = !is_zero_ether_addr(requested_bss);
 	bool right_addr = ether_addr_equal(requested_bss, fake_router_bssid);
 	u16 status = WLAN_STATUS_SUCCESS;
-	if (!priv->is_up || (has_addr && !right_addr))
+	if (is_zero_ether_addr(requested_bss))
+		requested_bss = NULL;
+	if (!priv->is_up || (requested_bss && !right_addr))
 		status = WLAN_STATUS_UNSPECIFIED_FAILURE;
 	else
 		priv->is_connected = true;

drivers/net/wwan/wwan_core.c+2−0

@@ -984,6 +984,8 @@ static void wwan_create_default_link(struct wwan_device *wwandev, · 983 unmodified lines
984	goto unlock;	984	goto unlock;
985	}	985	}
986		986
		987	rtnl_configure_link(dev, NULL); /* Link initialized, notify new link */
		988
987	unlock:	989	unlock:
988	rtnl_unlock();	990	rtnl_unlock();
989		991

drivers/nfc/nfcsim.c+1−2

@@ -192,8 +192,7 @@ static void nfcsim_recv_wq(struct work_struct *work) · 191 unmodified lines
192		192
193	if (!IS_ERR(skb))	193	if (!IS_ERR(skb))
194	dev_kfree_skb(skb);	194	dev_kfree_skb(skb);
195		195	return;
196	skb = ERR_PTR(-ENODEV);
197	}	196	}
198		197
199	dev->cb(dev->nfc_digital_dev, dev->arg, skb);	198	dev->cb(dev->nfc_digital_dev, dev->arg, skb);

drivers/nfc/s3fwrn5/firmware.c+1−1

@@ -423,7 +423,7 @@ int s3fwrn5_fw_download(struct s3fwrn5_fw_info *fw_info) · 422 unmodified lines
423	if (IS_ERR(tfm)) {	423	if (IS_ERR(tfm)) {
424	ret = PTR_ERR(tfm);	424	ret = PTR_ERR(tfm);
425	dev_err(&fw_info->ndev->nfc_dev->dev,	425	dev_err(&fw_info->ndev->nfc_dev->dev,
426	"Cannot allocate shash (code=%d)\n", ret);	426	"Cannot allocate shash (code=%pe)\n", tfm);
427	goto out;	427	goto out;
428	}	428	}
429		429

drivers/nvme/host/core.c+15−4

 		cpu_to_le64(nvme_sect_to_lba(ns, blk_rq_pos(req)));
 	cmnd->write_zeroes.length =
 		cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
-	cmnd->write_zeroes.control = 0;
+	if (nvme_ns_has_pi(ns))
+		cmnd->write_zeroes.control = cpu_to_le16(NVME_RW_PRINFO_PRACT);
+	else
+		cmnd->write_zeroes.control = 0;
 	return BLK_STS_OK;
 }
 static void nvme_ns_remove(struct nvme_ns *ns)
 {
+	bool last_path = false;
 	if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
 		return;
 	mutex_lock(&ns->ctrl->subsys->lock);
 	list_del_rcu(&ns->siblings);
-	if (list_empty(&ns->head->list))
-		list_del_init(&ns->head->entry);
 	mutex_unlock(&ns->ctrl->subsys->lock);
 	synchronize_rcu(); /* guarantee not available in head->list */
 	list_del_init(&ns->list);
 	up_write(&ns->ctrl->namespaces_rwsem);
-	nvme_mpath_check_last_path(ns);
+	/* Synchronize with nvme_init_ns_head() */
+	mutex_lock(&ns->head->subsys->lock);
+	if (list_empty(&ns->head->list)) {
+		list_del_init(&ns->head->entry);
+		last_path = true;
+	}
+	mutex_unlock(&ns->head->subsys->lock);
+	if (last_path)
+		nvme_mpath_shutdown_disk(ns->head);
 	nvme_put_ns(ns);
 }

drivers/nvme/host/multipath.c+8−1

 #endif
 }
-void nvme_mpath_remove_disk(struct nvme_ns_head *head)
+void nvme_mpath_shutdown_disk(struct nvme_ns_head *head)
 {
 	if (!head->disk)
 		return;
+	kblockd_schedule_work(&head->requeue_work);
 	if (head->disk->flags & GENHD_FL_UP) {
 		nvme_cdev_del(&head->cdev, &head->cdev_device);
 		del_gendisk(head->disk);
 	}
+}
+void nvme_mpath_remove_disk(struct nvme_ns_head *head)
+{
+	if (!head->disk)
+		return;
 	blk_set_queue_dying(head->disk->queue);
 	/* make sure all pending bios are cleaned up */
 	kblockd_schedule_work(&head->requeue_work);

drivers/nvme/host/nvme.h+2−9

@@ -716,14 +716,7 @@ void nvme_mpath_uninit(struct nvme_ctrl *ctrl); · 715 unmodified lines
716	void nvme_mpath_stop(struct nvme_ctrl *ctrl);	716	void nvme_mpath_stop(struct nvme_ctrl *ctrl);
717	bool nvme_mpath_clear_current_path(struct nvme_ns *ns);	717	bool nvme_mpath_clear_current_path(struct nvme_ns *ns);
718	void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl);	718	void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl);
719		719	void nvme_mpath_shutdown_disk(struct nvme_ns_head *head);
720	static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
721	{
722	struct nvme_ns_head *head = ns->head;
723
724	if (head->disk && list_empty(&head->list))
725	kblockd_schedule_work(&head->requeue_work);
726	}
727		720
728	static inline void nvme_trace_bio_complete(struct request *req)	721	static inline void nvme_trace_bio_complete(struct request *req)
729	{	722	{
@@ -772,7 +765,7 @@ static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns) · 42 unmodified lines
772	static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl)	765	static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl)
773	{	766	{
774	}	767	}
775	static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)	768	static inline void nvme_mpath_shutdown_disk(struct nvme_ns_head *head)
776	{	769	{
777	}	770	}
778	static inline void nvme_trace_bio_complete(struct request *req)	771	static inline void nvme_trace_bio_complete(struct request *req)

drivers/nvme/host/pci.c+3−1

 	bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
 	int result;
-	if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
+	if (dev->ctrl.state != NVME_CTRL_RESETTING) {
+		dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
+			 dev->ctrl.state);
 		result = -ENODEV;
 		goto out;
 	}

drivers/nvme/host/trace.h+3−3

@@ -56,7 +56,7 @@ TRACE_EVENT(nvme_setup_cmd, · 55 unmodified lines
56	__field(u8, fctype)	56	__field(u8, fctype)
57	__field(u16, cid)	57	__field(u16, cid)
58	__field(u32, nsid)	58	__field(u32, nsid)
59	__field(u64, metadata)	59	__field(bool, metadata)
60	__array(u8, cdw10, 24)	60	__array(u8, cdw10, 24)
61	),	61	),
62	TP_fast_assign(	62	TP_fast_assign(
@@ -66,13 +66,13 @@ TRACE_EVENT(nvme_setup_cmd, · 3 unmodified lines
66	__entry->flags = cmd->common.flags;	66	__entry->flags = cmd->common.flags;
67	__entry->cid = cmd->common.command_id;	67	__entry->cid = cmd->common.command_id;
68	__entry->nsid = le32_to_cpu(cmd->common.nsid);	68	__entry->nsid = le32_to_cpu(cmd->common.nsid);
69	__entry->metadata = le64_to_cpu(cmd->common.metadata);	69	__entry->metadata = !!blk_integrity_rq(req);
70	__entry->fctype = cmd->fabrics.fctype;	70	__entry->fctype = cmd->fabrics.fctype;
71	__assign_disk_name(__entry->disk, req->rq_disk);	71	__assign_disk_name(__entry->disk, req->rq_disk);
72	memcpy(__entry->cdw10, &cmd->common.cdw10,	72	memcpy(__entry->cdw10, &cmd->common.cdw10,
73	sizeof(__entry->cdw10));	73	sizeof(__entry->cdw10));
74	),	74	),
75	TP_printk("nvme%d: %sqid=%d, cmdid=%u, nsid=%u, flags=0x%x, meta=0x%llx, cmd=(%s %s)",	75	TP_printk("nvme%d: %sqid=%d, cmdid=%u, nsid=%u, flags=0x%x, meta=0x%x, cmd=(%s %s)",
76	__entry->ctrl_id, __print_disk_name(__entry->disk),	76	__entry->ctrl_id, __print_disk_name(__entry->disk),
77	__entry->qid, __entry->cid, __entry->nsid,	77	__entry->qid, __entry->cid, __entry->nsid,
78	__entry->flags, __entry->metadata,	78	__entry->flags, __entry->metadata,

drivers/platform/x86/amd-pmc.c+225−24

@@ -46,34 +46,79 @@ · 45 unmodified lines
46	#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE	46	#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
47	#define AMD_PMC_RESULT_FAILED 0xFF	47	#define AMD_PMC_RESULT_FAILED 0xFF
48		48
		49	/* FCH SSC Registers */
		50	#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
		51	#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
		52	#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
		53	#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
		54	#define FCH_SSC_MAPPING_SIZE 0x800
		55	#define FCH_BASE_PHY_ADDR_LOW 0xFED81100
		56	#define FCH_BASE_PHY_ADDR_HIGH 0x00000000
		57
		58	/* SMU Message Definations */
		59	#define SMU_MSG_GETSMUVERSION 0x02
		60	#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
		61	#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
		62	#define SMU_MSG_LOG_START 0x06
		63	#define SMU_MSG_LOG_RESET 0x07
		64	#define SMU_MSG_LOG_DUMP_DATA 0x08
		65	#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
49	/* List of supported CPU ids */	66	/* List of supported CPU ids */
50	#define AMD_CPU_ID_RV 0x15D0	67	#define AMD_CPU_ID_RV 0x15D0
51	#define AMD_CPU_ID_RN 0x1630	68	#define AMD_CPU_ID_RN 0x1630
52	#define AMD_CPU_ID_PCO AMD_CPU_ID_RV	69	#define AMD_CPU_ID_PCO AMD_CPU_ID_RV
53	#define AMD_CPU_ID_CZN AMD_CPU_ID_RN	70	#define AMD_CPU_ID_CZN AMD_CPU_ID_RN
		71	#define AMD_CPU_ID_YC 0x14B5
54		72
55	#define AMD_SMU_FW_VERSION 0x0
56	#define PMC_MSG_DELAY_MIN_US 100	73	#define PMC_MSG_DELAY_MIN_US 100
57	#define RESPONSE_REGISTER_LOOP_MAX 200	74	#define RESPONSE_REGISTER_LOOP_MAX 200
58		75
		76	#define SOC_SUBSYSTEM_IP_MAX 12
		77	#define DELAY_MIN_US 2000
		78	#define DELAY_MAX_US 3000
59	enum amd_pmc_def {	79	enum amd_pmc_def {
60	MSG_TEST = 0x01,	80	MSG_TEST = 0x01,
61	MSG_OS_HINT_PCO,	81	MSG_OS_HINT_PCO,
62	MSG_OS_HINT_RN,	82	MSG_OS_HINT_RN,
63	};	83	};
64		84
		85	struct amd_pmc_bit_map {
		86	const char *name;
		87	u32 bit_mask;
		88	};
		89
		90	static const struct amd_pmc_bit_map soc15_ip_blk[] = {
		91	{"DISPLAY", BIT(0)},
		92	{"CPU", BIT(1)},
		93	{"GFX", BIT(2)},
		94	{"VDD", BIT(3)},
		95	{"ACP", BIT(4)},
		96	{"VCN", BIT(5)},
		97	{"ISP", BIT(6)},
		98	{"NBIO", BIT(7)},
		99	{"DF", BIT(8)},
		100	{"USB0", BIT(9)},
		101	{"USB1", BIT(10)},
		102	{"LAPIC", BIT(11)},
		103	{}
		104	};
		105
65	struct amd_pmc_dev {	106	struct amd_pmc_dev {
66	void __iomem *regbase;	107	void __iomem *regbase;
67	void __iomem *smu_base;	108	void __iomem *smu_virt_addr;
		109	void __iomem *fch_virt_addr;
68	u32 base_addr;	110	u32 base_addr;
69	u32 cpu_id;	111	u32 cpu_id;
		112	u32 active_ips;
70	struct device *dev;	113	struct device *dev;
		114	struct mutex lock; /* generic mutex lock */
71	#if IS_ENABLED(CONFIG_DEBUG_FS)	115	#if IS_ENABLED(CONFIG_DEBUG_FS)
72	struct dentry *dbgfs_dir;	116	struct dentry *dbgfs_dir;
73	#endif /* CONFIG_DEBUG_FS */	117	#endif /* CONFIG_DEBUG_FS */
74	};	118	};
75		119
76	static struct amd_pmc_dev pmc;	120	static struct amd_pmc_dev pmc;
		121	static int amd_pmc_send_cmd(struct amd_pmc_dev dev, bool set, u32 data, u8 msg, bool ret);
77		122
78	static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)	123	static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
79	{	124	{
@@ -85,18 +130,77 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3 · 5 unmodified lines
85	iowrite32(val, dev->regbase + reg_offset);	130	iowrite32(val, dev->regbase + reg_offset);
86	}	131	}
87		132
		133	struct smu_metrics {
		134	u32 table_version;
		135	u32 hint_count;
		136	u32 s0i3_cyclecount;
		137	u32 timein_s0i2;
		138	u64 timeentering_s0i3_lastcapture;
		139	u64 timeentering_s0i3_totaltime;
		140	u64 timeto_resume_to_os_lastcapture;
		141	u64 timeto_resume_to_os_totaltime;
		142	u64 timein_s0i3_lastcapture;
		143	u64 timein_s0i3_totaltime;
		144	u64 timein_swdrips_lastcapture;
		145	u64 timein_swdrips_totaltime;
		146	u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
		147	u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
		148	} __packed;
		149
88	#ifdef CONFIG_DEBUG_FS	150	#ifdef CONFIG_DEBUG_FS
89	static int smu_fw_info_show(struct seq_file s, void unused)	151	static int smu_fw_info_show(struct seq_file s, void unused)
90	{	152	{
91	struct amd_pmc_dev *dev = s->private;	153	struct amd_pmc_dev *dev = s->private;
92	u32 value;	154	struct smu_metrics table;
		155	int idx;
		156
		157	if (dev->cpu_id == AMD_CPU_ID_PCO)
		158	return -EINVAL;
		159
		160	memcpy_fromio(&table, dev->smu_virt_addr, sizeof(struct smu_metrics));
		161
		162	seq_puts(s, "\n=== SMU Statistics ===\n");
		163	seq_printf(s, "Table Version: %d\n", table.table_version);
		164	seq_printf(s, "Hint Count: %d\n", table.hint_count);
		165	seq_printf(s, "S0i3 Cycle Count: %d\n", table.s0i3_cyclecount);
		166	seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
		167	seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
		168
		169	seq_puts(s, "\n=== Active time (in us) ===\n");
		170	for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
		171	if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
		172	seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
		173	table.timecondition_notmet_lastcapture[idx]);
		174	}
93		175
94	value = ioread32(dev->smu_base + AMD_SMU_FW_VERSION);
95	seq_printf(s, "SMU FW Info: %x\n", value);
96	return 0;	176	return 0;
97	}	177	}
98	DEFINE_SHOW_ATTRIBUTE(smu_fw_info);	178	DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
99		179
		180	static int s0ix_stats_show(struct seq_file s, void unused)
		181	{
		182	struct amd_pmc_dev *dev = s->private;
		183	u64 entry_time, exit_time, residency;
		184
		185	entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
		186	entry_time = entry_time << 32 \| ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
		187
		188	exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
		189	exit_time = exit_time << 32 \| ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
		190
		191	/* It's in 48MHz. We need to convert it */
		192	residency = exit_time - entry_time;
		193	do_div(residency, 48);
		194
		195	seq_puts(s, "=== S0ix statistics ===\n");
		196	seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
		197	seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
		198	seq_printf(s, "Residency Time: %lld\n", residency);
		199
		200	return 0;
		201	}
		202	DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
		203
100	static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)	204	static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
101	{	205	{
102	debugfs_remove_recursive(dev->dbgfs_dir);	206	debugfs_remove_recursive(dev->dbgfs_dir);
@@ -107,6 +211,8 @@ static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) · 4 unmodified lines
107	dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);	211	dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
108	debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,	212	debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
109	&smu_fw_info_fops);	213	&smu_fw_info_fops);
		214	debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
		215	&s0ix_stats_fops);
110	}	216	}
111	#else	217	#else
112	static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)	218	static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
@@ -118,6 +224,32 @@ static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) · 5 unmodified lines
118	}	224	}
119	#endif /* CONFIG_DEBUG_FS */	225	#endif /* CONFIG_DEBUG_FS */
120		226
		227	static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
		228	{
		229	u32 phys_addr_low, phys_addr_hi;
		230	u64 smu_phys_addr;
		231
		232	if (dev->cpu_id == AMD_CPU_ID_PCO)
		233	return -EINVAL;
		234
		235	/* Get Active devices list from SMU */
		236	amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
		237
		238	/* Get dram address */
		239	amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
		240	amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
		241	smu_phys_addr = ((u64)phys_addr_hi << 32 \| phys_addr_low);
		242
		243	dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, sizeof(struct smu_metrics));
		244	if (!dev->smu_virt_addr)
		245	return -ENOMEM;
		246
		247	/* Start the logging */
		248	amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
		249
		250	return 0;
		251	}
		252
121	static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)	253	static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
122	{	254	{
123	u32 value;	255	u32 value;
@@ -132,19 +264,19 @@ static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) · 8 unmodified lines
132	dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);	264	dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
133	}	265	}
134		266
135	static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)	267	static int amd_pmc_send_cmd(struct amd_pmc_dev dev, bool set, u32 data, u8 msg, bool ret)
136	{	268	{
137	int rc;	269	int rc;
138	u8 msg;
139	u32 val;	270	u32 val;
140		271
		272	mutex_lock(&dev->lock);
141	/* Wait until we get a valid response */	273	/* Wait until we get a valid response */
142	rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,	274	rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
143	val, val > 0, PMC_MSG_DELAY_MIN_US,	275	val, val != 0, PMC_MSG_DELAY_MIN_US,
144	PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);	276	PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
145	if (rc) {	277	if (rc) {
146	dev_err(dev->dev, "failed to talk to SMU\n");	278	dev_err(dev->dev, "failed to talk to SMU\n");
147	return rc;	279	goto out_unlock;
148	}	280	}
149		281
150	/* Write zero to response register */	282	/* Write zero to response register */
@@ -154,34 +286,91 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set) · 3 unmodified lines
154	amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, set);	286	amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, set);
155		287
156	/* Write message ID to message ID register */	288	/* Write message ID to message ID register */
157	msg = (dev->cpu_id == AMD_CPU_ID_RN) ? MSG_OS_HINT_RN : MSG_OS_HINT_PCO;
158	amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);	289	amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);
159	return 0;	290
		291	/* Wait until we get a valid response */
		292	rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
		293	val, val != 0, PMC_MSG_DELAY_MIN_US,
		294	PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
		295	if (rc) {
		296	dev_err(dev->dev, "SMU response timed out\n");
		297	goto out_unlock;
		298	}
		299
		300	switch (val) {
		301	case AMD_PMC_RESULT_OK:
		302	if (ret) {
		303	/* PMFW may take longer time to return back the data */
		304	usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
		305	*data = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
		306	}
		307	break;
		308	case AMD_PMC_RESULT_CMD_REJECT_BUSY:
		309	dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
		310	rc = -EBUSY;
		311	goto out_unlock;
		312	case AMD_PMC_RESULT_CMD_UNKNOWN:
		313	dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
		314	rc = -EINVAL;
		315	goto out_unlock;
		316	case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
		317	case AMD_PMC_RESULT_FAILED:
		318	default:
		319	dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
		320	rc = -EIO;
		321	goto out_unlock;
		322	}
		323
		324	out_unlock:
		325	mutex_unlock(&dev->lock);
		326	amd_pmc_dump_registers(dev);
		327	return rc;
		328	}
		329
		330	static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
		331	{
		332	switch (dev->cpu_id) {
		333	case AMD_CPU_ID_PCO:
		334	return MSG_OS_HINT_PCO;
		335	case AMD_CPU_ID_RN:
		336	case AMD_CPU_ID_YC:
		337	return MSG_OS_HINT_RN;
		338	}
		339	return -EINVAL;
160	}	340	}
161		341
162	static int __maybe_unused amd_pmc_suspend(struct device *dev)	342	static int __maybe_unused amd_pmc_suspend(struct device *dev)
163	{	343	{
164	struct amd_pmc_dev *pdev = dev_get_drvdata(dev);	344	struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
165	int rc;	345	int rc;
		346	u8 msg;
		347
		348	/* Reset and Start SMU logging - to monitor the s0i3 stats */
		349	amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0);
		350	amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0);
166		351
167	rc = amd_pmc_send_cmd(pdev, 1);	352	msg = amd_pmc_get_os_hint(pdev);
		353	rc = amd_pmc_send_cmd(pdev, 1, NULL, msg, 0);
168	if (rc)	354	if (rc)
169	dev_err(pdev->dev, "suspend failed\n");	355	dev_err(pdev->dev, "suspend failed\n");
170		356
171	amd_pmc_dump_registers(pdev);	357	return rc;
172	return 0;
173	}	358	}
174		359
175	static int __maybe_unused amd_pmc_resume(struct device *dev)	360	static int __maybe_unused amd_pmc_resume(struct device *dev)
176	{	361	{
177	struct amd_pmc_dev *pdev = dev_get_drvdata(dev);	362	struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
178	int rc;	363	int rc;
		364	u8 msg;
		365
		366	/* Let SMU know that we are looking for stats */
		367	amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
179		368
180	rc = amd_pmc_send_cmd(pdev, 0);	369	msg = amd_pmc_get_os_hint(pdev);
		370	rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
181	if (rc)	371	if (rc)
182	dev_err(pdev->dev, "resume failed\n");	372	dev_err(pdev->dev, "resume failed\n");
183		373
184	amd_pmc_dump_registers(pdev);
185	return 0;	374	return 0;
186	}	375	}
187		376
@@ -190,6 +379,7 @@ static const struct dev_pm_ops amd_pmc_pm_ops = { · 2 unmodified lines
190	};	379	};
191		380
192	static const struct pci_device_id pmc_pci_ids[] = {	381	static const struct pci_device_id pmc_pci_ids[] = {
		382	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
193	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },	383	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
194	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },	384	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
195	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },	385	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
@@ -201,9 +391,8 @@ static int amd_pmc_probe(struct platform_device *pdev) · 5 unmodified lines
201	{	391	{
202	struct amd_pmc_dev *dev = &pmc;	392	struct amd_pmc_dev *dev = &pmc;
203	struct pci_dev *rdev;	393	struct pci_dev *rdev;
204	u32 base_addr_lo;	394	u32 base_addr_lo, base_addr_hi;
205	u32 base_addr_hi;	395	u64 base_addr, fch_phys_addr;
206	u64 base_addr;
207	int err;	396	int err;
208	u32 val;	397	u32 val;
209		398
@@ -248,16 +437,25 @@ static int amd_pmc_probe(struct platform_device *pdev) · 38 unmodified lines
248	pci_dev_put(rdev);	437	pci_dev_put(rdev);
249	base_addr = ((u64)base_addr_hi << 32 \| base_addr_lo);	438	base_addr = ((u64)base_addr_hi << 32 \| base_addr_lo);
250		439
251	dev->smu_base = devm_ioremap(dev->dev, base_addr, AMD_PMC_MAPPING_SIZE);
252	if (!dev->smu_base)
253	return -ENOMEM;
254
255	dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,	440	dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
256	AMD_PMC_MAPPING_SIZE);	441	AMD_PMC_MAPPING_SIZE);
257	if (!dev->regbase)	442	if (!dev->regbase)
258	return -ENOMEM;	443	return -ENOMEM;
259		444
260	amd_pmc_dump_registers(dev);	445	mutex_init(&dev->lock);
		446
		447	/* Use FCH registers to get the S0ix stats */
		448	base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
		449	base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
		450	fch_phys_addr = ((u64)base_addr_hi << 32 \| base_addr_lo);
		451	dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
		452	if (!dev->fch_virt_addr)
		453	return -ENOMEM;
		454
		455	/* Use SMU to get the s0i3 debug stats */
		456	err = amd_pmc_setup_smu_logging(dev);
		457	if (err)
		458	dev_err(dev->dev, "SMU debugging info not supported on this platform\n");
261		459
262	platform_set_drvdata(pdev, dev);	460	platform_set_drvdata(pdev, dev);
263	amd_pmc_dbgfs_register(dev);	461	amd_pmc_dbgfs_register(dev);
@@ -269,11 +467,14 @@ static int amd_pmc_remove(struct platform_device *pdev) · 5 unmodified lines
269	struct amd_pmc_dev *dev = platform_get_drvdata(pdev);	467	struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
270		468
271	amd_pmc_dbgfs_unregister(dev);	469	amd_pmc_dbgfs_unregister(dev);
		470	mutex_destroy(&dev->lock);
272	return 0;	471	return 0;
273	}	472	}
274		473
275	static const struct acpi_device_id amd_pmc_acpi_ids[] = {	474	static const struct acpi_device_id amd_pmc_acpi_ids[] = {
276	{"AMDI0005", 0},	475	{"AMDI0005", 0},
		476	{"AMDI0006", 0},
		477	{"AMDI0007", 0},
277	{"AMD0004", 0},	478	{"AMD0004", 0},
278	{ }	479	{ }
279	};	480	};

drivers/platform/x86/gigabyte-wmi.c+1−0

@@ -141,6 +141,7 @@ static u8 gigabyte_wmi_detect_sensor_usability(struct wmi_device *wdev) · 140 unmodified lines
141		141
142	static const struct dmi_system_id gigabyte_wmi_known_working_platforms[] = {	142	static const struct dmi_system_id gigabyte_wmi_known_working_platforms[] = {
143	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550 AORUS ELITE"),	143	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550 AORUS ELITE"),
		144	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550 AORUS ELITE V2"),
144	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550 GAMING X V2"),	145	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550 GAMING X V2"),
145	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550M AORUS PRO-P"),	146	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550M AORUS PRO-P"),
146	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550M DS3H"),	147	DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550M DS3H"),

drivers/platform/x86/intel-hid.c+1−0

@@ -25,6 +25,7 @@ static const struct acpi_device_id intel_hid_ids[] = { · 24 unmodified lines
25	{"INT33D5", 0},	25	{"INT33D5", 0},
26	{"INTC1051", 0},	26	{"INTC1051", 0},
27	{"INTC1054", 0},	27	{"INTC1054", 0},
		28	{"INTC1070", 0},
28	{"", 0},	29	{"", 0},
29	};	30	};
30	MODULE_DEVICE_TABLE(acpi, intel_hid_ids);	31	MODULE_DEVICE_TABLE(acpi, intel_hid_ids);

drivers/platform/x86/think-lmi.c+36−9

 	else
 		ret = tlmi_save_bios_settings("");
+	if (!ret && !tlmi_priv.pending_changes) {
+		tlmi_priv.pending_changes = true;
+		/* let userland know it may need to check reboot pending again */
+		kobject_uevent(&tlmi_priv.class_dev->kobj, KOBJ_CHANGE);
+	}
 out:
 	kfree(auth_str);
 	kfree(set_str);
 	.sysfs_ops	= &tlmi_kobj_sysfs_ops,
 };
+static ssize_t pending_reboot_show(struct kobject *kobj, struct kobj_attribute *attr,
+				   char *buf)
+{
+	return sprintf(buf, "%d\n", tlmi_priv.pending_changes);
+}
+static struct kobj_attribute pending_reboot = __ATTR_RO(pending_reboot);
 /* ---- Initialisation --------------------------------------------------------- */
 static void tlmi_release_attr(void)
 {
 			kobject_put(&tlmi_priv.setting[i]->kobj);
 		}
 	}
+	sysfs_remove_file(&tlmi_priv.attribute_kset->kobj, &pending_reboot.attr);
 	kset_unregister(tlmi_priv.attribute_kset);
 	/* Authentication structures */
 		/* Build attribute */
 		tlmi_priv.setting[i]->kobj.kset = tlmi_priv.attribute_kset;
-		ret = kobject_init_and_add(&tlmi_priv.setting[i]->kobj, &tlmi_attr_setting_ktype,
+		ret = kobject_add(&tlmi_priv.setting[i]->kobj, NULL,
-				NULL, "%s", tlmi_priv.setting[i]->display_name);
+				  "%s", tlmi_priv.setting[i]->display_name);
 		if (ret)
 			goto fail_create_attr;
 			goto fail_create_attr;
 	}
+	ret = sysfs_create_file(&tlmi_priv.attribute_kset->kobj, &pending_reboot.attr);
+	if (ret)
+		goto fail_create_attr;
 	/* Create authentication entries */
 	tlmi_priv.authentication_kset = kset_create_and_add("authentication", NULL,
 								&tlmi_priv.class_dev->kobj);
 		goto fail_create_attr;
 	}
 	tlmi_priv.pwd_admin->kobj.kset = tlmi_priv.authentication_kset;
-	ret = kobject_init_and_add(&tlmi_priv.pwd_admin->kobj, &tlmi_pwd_setting_ktype,
+	ret = kobject_add(&tlmi_priv.pwd_admin->kobj, NULL, "%s", "Admin");
-			NULL, "%s", "Admin");
 	if (ret)
 		goto fail_create_attr;
 		goto fail_create_attr;
 	tlmi_priv.pwd_power->kobj.kset = tlmi_priv.authentication_kset;
-	ret = kobject_init_and_add(&tlmi_priv.pwd_power->kobj, &tlmi_pwd_setting_ktype,
+	ret = kobject_add(&tlmi_priv.pwd_power->kobj, NULL, "%s", "System");
-			NULL, "%s", "System");
 	if (ret)
 		goto fail_create_attr;
 				pr_info("Error retrieving possible values for %d : %s\n",
 						i, setting->display_name);
 		}
+		kobject_init(&setting->kobj, &tlmi_attr_setting_ktype);
 		tlmi_priv.setting[i] = setting;
 		tlmi_priv.settings_count++;
 		kfree(item);
 	if (pwdcfg.password_state & TLMI_PAP_PWD)
 		tlmi_priv.pwd_admin->valid = true;
+	kobject_init(&tlmi_priv.pwd_admin->kobj, &tlmi_pwd_setting_ktype);
 	tlmi_priv.pwd_power = kzalloc(sizeof(struct tlmi_pwd_setting), GFP_KERNEL);
 	if (!tlmi_priv.pwd_power) {
 		ret = -ENOMEM;
-		goto fail_clear_attr;
+		goto fail_free_pwd_admin;
 	}
 	strscpy(tlmi_priv.pwd_power->kbdlang, "us", TLMI_LANG_MAXLEN);
 	tlmi_priv.pwd_power->encoding = TLMI_ENCODING_ASCII;
 	if (pwdcfg.password_state & TLMI_POP_PWD)
 		tlmi_priv.pwd_power->valid = true;
+	kobject_init(&tlmi_priv.pwd_power->kobj, &tlmi_pwd_setting_ktype);
 	return 0;
+fail_free_pwd_admin:
+	kfree(tlmi_priv.pwd_admin);
 fail_clear_attr:
-	for (i = 0; i < TLMI_SETTINGS_COUNT; ++i)
+	for (i = 0; i < TLMI_SETTINGS_COUNT; ++i) {
-		kfree(tlmi_priv.setting[i]);
+		if (tlmi_priv.setting[i]) {
+			kfree(tlmi_priv.setting[i]->possible_values);
+			kfree(tlmi_priv.setting[i]);
+		}
+	}
 	return ret;
 }

drivers/platform/x86/think-lmi.h+1−0

@@ -60,6 +60,7 @@ struct think_lmi { · 59 unmodified lines
60	bool can_get_bios_selections;	60	bool can_get_bios_selections;
61	bool can_set_bios_password;	61	bool can_set_bios_password;
62	bool can_get_password_settings;	62	bool can_get_password_settings;
		63	bool pending_changes;
63		64
64	struct tlmi_attr_setting *setting[TLMI_SETTINGS_COUNT];	65	struct tlmi_attr_setting *setting[TLMI_SETTINGS_COUNT];
65	struct device *class_dev;	66	struct device *class_dev;

drivers/platform/x86/wireless-hotkey.c+1−1

@@ -78,7 +78,7 @@ static int wl_add(struct acpi_device *device) · 77 unmodified lines
78		78
79	err = wireless_input_setup();	79	err = wireless_input_setup();
80	if (err)	80	if (err)
81	pr_err("Failed to setup hp wireless hotkeys\n");	81	pr_err("Failed to setup wireless hotkeys\n");
82		82
83	return err;	83	return err;
84	}	84	}

drivers/regulator/bd9576-regulator.c+2−2

@@ -294,9 +294,9 @@ static bool check_temp_flag_mismatch(struct regulator_dev *rdev, int severity, · 293 unmodified lines
294	struct bd957x_regulator_data *r)	294	struct bd957x_regulator_data *r)
295	{	295	{
296	if ((severity == REGULATOR_SEVERITY_ERR &&	296	if ((severity == REGULATOR_SEVERITY_ERR &&
297	r->ovd_notif != REGULATOR_EVENT_OVER_TEMP) \|\|	297	r->temp_notif != REGULATOR_EVENT_OVER_TEMP) \|\|
298	(severity == REGULATOR_SEVERITY_WARN &&	298	(severity == REGULATOR_SEVERITY_WARN &&
299	r->ovd_notif != REGULATOR_EVENT_OVER_TEMP_WARN)) {	299	r->temp_notif != REGULATOR_EVENT_OVER_TEMP_WARN)) {
300	dev_warn(rdev_get_dev(rdev),	300	dev_warn(rdev_get_dev(rdev),
301	"Can't support both thermal WARN and ERR\n");	301	"Can't support both thermal WARN and ERR\n");
302	if (severity == REGULATOR_SEVERITY_WARN)	302	if (severity == REGULATOR_SEVERITY_WARN)

drivers/regulator/hi6421-regulator.c+13−9

 static int hi6421_regulator_enable(struct regulator_dev *rdev)
 {
-	struct hi6421_regulator_pdata *pdata;
+	struct hi6421_regulator_pdata *pdata = rdev_get_drvdata(rdev);
-	pdata = dev_get_drvdata(rdev->dev.parent);
 	/* hi6421 spec requires regulator enablement must be serialized:
 	 *  - Because when BUCK, LDO switching from off to on, it will have
 	 *    a huge instantaneous current; so you can not turn on two or
 static unsigned int hi6421_regulator_ldo_get_mode(struct regulator_dev *rdev)
 {
-	struct hi6421_regulator_info *info = rdev_get_drvdata(rdev);
+	struct hi6421_regulator_info *info;
 	unsigned int reg_val;
+	info = container_of(rdev->desc, struct hi6421_regulator_info, desc);
 	regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val);
 	if (reg_val & info->mode_mask)
 		return REGULATOR_MODE_IDLE;
 static unsigned int hi6421_regulator_buck_get_mode(struct regulator_dev *rdev)
 {
-	struct hi6421_regulator_info *info = rdev_get_drvdata(rdev);
+	struct hi6421_regulator_info *info;
 	unsigned int reg_val;
+	info = container_of(rdev->desc, struct hi6421_regulator_info, desc);
 	regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val);
 	if (reg_val & info->mode_mask)
 		return REGULATOR_MODE_STANDBY;
 static int hi6421_regulator_ldo_set_mode(struct regulator_dev *rdev,
 						unsigned int mode)
 {
-	struct hi6421_regulator_info *info = rdev_get_drvdata(rdev);
+	struct hi6421_regulator_info *info;
 	unsigned int new_mode;
+	info = container_of(rdev->desc, struct hi6421_regulator_info, desc);
 	switch (mode) {
 	case REGULATOR_MODE_NORMAL:
 		new_mode = 0;
 static int hi6421_regulator_buck_set_mode(struct regulator_dev *rdev,
 						unsigned int mode)
 {
-	struct hi6421_regulator_info *info = rdev_get_drvdata(rdev);
+	struct hi6421_regulator_info *info;
 	unsigned int new_mode;
+	info = container_of(rdev->desc, struct hi6421_regulator_info, desc);
 	switch (mode) {
 	case REGULATOR_MODE_NORMAL:
 		new_mode = 0;
 hi6421_regulator_ldo_get_optimum_mode(struct regulator_dev *rdev,
 			int input_uV, int output_uV, int load_uA)
 {
-	struct hi6421_regulator_info *info = rdev_get_drvdata(rdev);
+	struct hi6421_regulator_info *info;
+	info = container_of(rdev->desc, struct hi6421_regulator_info, desc);
 	if (load_uA > info->eco_microamp)
 		return REGULATOR_MODE_NORMAL;
 	if (!pdata)
 		return -ENOMEM;
 	mutex_init(&pdata->lock);
-	platform_set_drvdata(pdev, pdata);
 	for (i = 0; i < ARRAY_SIZE(hi6421_regulator_info); i++) {
 		/* assign per-regulator data */
 		info = &hi6421_regulator_info[i];
 		config.dev = pdev->dev.parent;
-		config.driver_data = info;
+		config.driver_data = pdata;
 		config.regmap = pmic->regmap;
 		rdev = devm_regulator_register(&pdev->dev, &info->desc,

drivers/regulator/hi6421v600-regulator.c+9−7

 static int hi6421_spmi_regulator_enable(struct regulator_dev *rdev)
 {
-	struct hi6421_spmi_reg_priv *priv;
+	struct hi6421_spmi_reg_priv *priv = rdev_get_drvdata(rdev);
 	int ret;
-	priv = dev_get_drvdata(rdev->dev.parent);
 	/* cannot enable more than one regulator at one time */
 	mutex_lock(&priv->enable_mutex);
 static unsigned int hi6421_spmi_regulator_get_mode(struct regulator_dev *rdev)
 {
-	struct hi6421_spmi_reg_info *sreg = rdev_get_drvdata(rdev);
+	struct hi6421_spmi_reg_info *sreg;
 	unsigned int reg_val;
+	sreg = container_of(rdev->desc, struct hi6421_spmi_reg_info, desc);
 	regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val);
 	if (reg_val & sreg->eco_mode_mask)
 static int hi6421_spmi_regulator_set_mode(struct regulator_dev *rdev,
 					  unsigned int mode)
 {
-	struct hi6421_spmi_reg_info *sreg = rdev_get_drvdata(rdev);
+	struct hi6421_spmi_reg_info *sreg;
 	unsigned int val;
+	sreg = container_of(rdev->desc, struct hi6421_spmi_reg_info, desc);
 	switch (mode) {
 	case REGULATOR_MODE_NORMAL:
 		val = 0;
 				       int input_uV, int output_uV,
 				       int load_uA)
 {
-	struct hi6421_spmi_reg_info *sreg = rdev_get_drvdata(rdev);
+	struct hi6421_spmi_reg_info *sreg;
+	sreg = container_of(rdev->desc, struct hi6421_spmi_reg_info, desc);
 	if (!sreg->eco_uA || ((unsigned int)load_uA > sreg->eco_uA))
 		return REGULATOR_MODE_NORMAL;
 		return -ENOMEM;
 	mutex_init(&priv->enable_mutex);
-	platform_set_drvdata(pdev, priv);
 	for (i = 0; i < ARRAY_SIZE(regulator_info); i++) {
 		info = &regulator_info[i];
 		config.dev = pdev->dev.parent;
-		config.driver_data = info;
+		config.driver_data = priv;
 		config.regmap = pmic->regmap;
 		rdev = devm_regulator_register(dev, &info->desc, &config);

drivers/regulator/mtk-dvfsrc-regulator.c+1−2

 	for (i = 0; i < regulator_init_data->size; i++) {
 		config.dev = dev->parent;
 		config.driver_data = (mt_regulators + i);
-		rdev = devm_regulator_register(dev->parent,
+		rdev = devm_regulator_register(dev, &(mt_regulators + i)->desc,
-					       &(mt_regulators + i)->desc,
 					       &config);
 		if (IS_ERR(rdev)) {
 			dev_err(dev, "failed to register %s\n",

drivers/regulator/rtmv20-regulator.c+1−1

@@ -37,7 +37,7 @@ · 36 unmodified lines
37	#define RTMV20_WIDTH2_MASK GENMASK(7, 0)	37	#define RTMV20_WIDTH2_MASK GENMASK(7, 0)
38	#define RTMV20_LBPLVL_MASK GENMASK(3, 0)	38	#define RTMV20_LBPLVL_MASK GENMASK(3, 0)
39	#define RTMV20_LBPEN_MASK BIT(7)	39	#define RTMV20_LBPEN_MASK BIT(7)
40	#define RTMV20_STROBEPOL_MASK BIT(1)	40	#define RTMV20_STROBEPOL_MASK BIT(0)
41	#define RTMV20_VSYNPOL_MASK BIT(1)	41	#define RTMV20_VSYNPOL_MASK BIT(1)
42	#define RTMV20_FSINEN_MASK BIT(7)	42	#define RTMV20_FSINEN_MASK BIT(7)
43	#define RTMV20_ESEN_MASK BIT(6)	43	#define RTMV20_ESEN_MASK BIT(6)

drivers/scsi/arm/acornscsi.c+1−0

@@ -2642,6 +2642,7 @@ int acornscsi_abort(struct scsi_cmnd *SCpnt) · 2641 unmodified lines
2642	//#endif	2642	//#endif
2643	clear_bit(SCpnt->device->id * 8 +	2643	clear_bit(SCpnt->device->id * 8 +
2644	(u8)(SCpnt->device->lun & 0x7), host->busyluns);	2644	(u8)(SCpnt->device->lun & 0x7), host->busyluns);
		2645	fallthrough;
2645		2646
2646	/*	2647	/*
2647	* We found the command, and cleared it out. Either	2648	* We found the command, and cleared it out. Either

drivers/scsi/arm/fas216.c+1−0

@@ -1375,6 +1375,7 @@ static void fas216_busservice_intr(FAS216_Info *info, unsigned int stat, unsigne · 1374 unmodified lines
1375	case IS_COMPLETE:	1375	case IS_COMPLETE:
1376	break;	1376	break;
1377	}	1377	}
		1378	break;
1378		1379
1379	default:	1380	default:
1380	break;	1381	break;

drivers/scsi/mpt3sas/mpt3sas_base.c+16−16

@@ -2983,13 +2983,13 @@ _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc) · 2982 unmodified lines
2983	}	2983	}
2984		2984
2985	/**	2985	/**
2986	* _base_free_irq - free irq	2986	* mpt3sas_base_free_irq - free irq
2987	* @ioc: per adapter object	2987	* @ioc: per adapter object
2988	*	2988	*
2989	* Freeing respective reply_queue from the list.	2989	* Freeing respective reply_queue from the list.
2990	*/	2990	*/
2991	static void	2991	void
2992	_base_free_irq(struct MPT3SAS_ADAPTER *ioc)	2992	mpt3sas_base_free_irq(struct MPT3SAS_ADAPTER *ioc)
2993	{	2993	{
2994	struct adapter_reply_queue reply_q, next;	2994	struct adapter_reply_queue reply_q, next;
2995		2995
@@ -3191,12 +3191,12 @@ _base_check_and_enable_high_iops_queues(struct MPT3SAS_ADAPTER *ioc, · 195 unmodified lines
3191	}	3191	}
3192		3192
3193	/**	3193	/**
3194	* _base_disable_msix - disables msix	3194	* mpt3sas_base_disable_msix - disables msix
3195	* @ioc: per adapter object	3195	* @ioc: per adapter object
3196	*	3196	*
3197	*/	3197	*/
3198	static void	3198	void
3199	_base_disable_msix(struct MPT3SAS_ADAPTER *ioc)	3199	mpt3sas_base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
3200	{	3200	{
3201	if (!ioc->msix_enable)	3201	if (!ioc->msix_enable)
3202	return;	3202	return;
@@ -3304,8 +3304,8 @@ _base_enable_msix(struct MPT3SAS_ADAPTER *ioc) · 101 unmodified lines
3304	for (i = 0; i < ioc->reply_queue_count; i++) {	3304	for (i = 0; i < ioc->reply_queue_count; i++) {
3305	r = _base_request_irq(ioc, i);	3305	r = _base_request_irq(ioc, i);
3306	if (r) {	3306	if (r) {
3307	_base_free_irq(ioc);	3307	mpt3sas_base_free_irq(ioc);
3308	_base_disable_msix(ioc);	3308	mpt3sas_base_disable_msix(ioc);
3309	goto try_ioapic;	3309	goto try_ioapic;
3310	}	3310	}
3311	}	3311	}
@@ -3342,8 +3342,8 @@ mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc) · 30 unmodified lines
3342		3342
3343	dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));	3343	dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3344		3344
3345	_base_free_irq(ioc);	3345	mpt3sas_base_free_irq(ioc);
3346	_base_disable_msix(ioc);	3346	mpt3sas_base_disable_msix(ioc);
3347		3347
3348	kfree(ioc->replyPostRegisterIndex);	3348	kfree(ioc->replyPostRegisterIndex);
3349	ioc->replyPostRegisterIndex = NULL;	3349	ioc->replyPostRegisterIndex = NULL;
@@ -7613,14 +7613,14 @@ _base_diag_reset(struct MPT3SAS_ADAPTER *ioc) · 4263 unmodified lines
7613	}	7613	}
7614		7614
7615	/**	7615	/**
7616	* _base_make_ioc_ready - put controller in READY state	7616	* mpt3sas_base_make_ioc_ready - put controller in READY state
7617	* @ioc: per adapter object	7617	* @ioc: per adapter object
7618	* @type: FORCE_BIG_HAMMER or SOFT_RESET	7618	* @type: FORCE_BIG_HAMMER or SOFT_RESET
7619	*	7619	*
7620	* Return: 0 for success, non-zero for failure.	7620	* Return: 0 for success, non-zero for failure.
7621	*/	7621	*/
7622	static int	7622	int
7623	_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)	7623	mpt3sas_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)
7624	{	7624	{
7625	u32 ioc_state;	7625	u32 ioc_state;
7626	int rc;	7626	int rc;
@@ -7897,7 +7897,7 @@ mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc) · 270 unmodified lines
7897	if (ioc->chip_phys && ioc->chip) {	7897	if (ioc->chip_phys && ioc->chip) {
7898	mpt3sas_base_mask_interrupts(ioc);	7898	mpt3sas_base_mask_interrupts(ioc);
7899	ioc->shost_recovery = 1;	7899	ioc->shost_recovery = 1;
7900	_base_make_ioc_ready(ioc, SOFT_RESET);	7900	mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET);
7901	ioc->shost_recovery = 0;	7901	ioc->shost_recovery = 0;
7902	}	7902	}
7903		7903
@@ -8017,7 +8017,7 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) · 113 unmodified lines
8017	ioc->build_sg_mpi = &_base_build_sg;	8017	ioc->build_sg_mpi = &_base_build_sg;
8018	ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;	8018	ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
8019		8019
8020	r = _base_make_ioc_ready(ioc, SOFT_RESET);	8020	r = mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET);
8021	if (r)	8021	if (r)
8022	goto out_free_resources;	8022	goto out_free_resources;
8023		8023
@@ -8471,7 +8471,7 @@ mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, · 447 unmodified lines
8471	_base_pre_reset_handler(ioc);	8471	_base_pre_reset_handler(ioc);
8472	mpt3sas_wait_for_commands_to_complete(ioc);	8472	mpt3sas_wait_for_commands_to_complete(ioc);
8473	mpt3sas_base_mask_interrupts(ioc);	8473	mpt3sas_base_mask_interrupts(ioc);
8474	r = _base_make_ioc_ready(ioc, type);	8474	r = mpt3sas_base_make_ioc_ready(ioc, type);
8475	if (r)	8475	if (r)
8476	goto out;	8476	goto out;
8477	_base_clear_outstanding_commands(ioc);	8477	_base_clear_outstanding_commands(ioc);

drivers/scsi/mpt3sas/mpt3sas_base.h+4−0

 	status, mpi_request, sz); } while (0)
 int mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int wait_count);
+int
+mpt3sas_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type);
+void mpt3sas_base_free_irq(struct MPT3SAS_ADAPTER *ioc);
+void mpt3sas_base_disable_msix(struct MPT3SAS_ADAPTER *ioc);
 /* scsih shared API */
 struct scsi_cmnd *mpt3sas_scsih_scsi_lookup_get(struct MPT3SAS_ADAPTER *ioc,

drivers/scsi/mpt3sas/mpt3sas_scsih.c+6−1

 	_scsih_ir_shutdown(ioc);
 	_scsih_nvme_shutdown(ioc);
-	mpt3sas_base_detach(ioc);
+	mpt3sas_base_mask_interrupts(ioc);
+	ioc->shost_recovery = 1;
+	mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET);
+	ioc->shost_recovery = 0;
+	mpt3sas_base_free_irq(ioc);
+	mpt3sas_base_disable_msix(ioc);
 }

drivers/scsi/scsi_transport_iscsi.c+34−56

 	struct device *dev = container_of(kobj, struct device, kobj);
 	struct iscsi_iface *iface = iscsi_dev_to_iface(dev);
 	struct iscsi_transport *t = iface->transport;
-	int param;
+	int param = -1;
-	int param_type;
 	if (attr == &dev_attr_iface_enabled.attr)
 		param = ISCSI_NET_PARAM_IFACE_ENABLE;
-	else if (attr == &dev_attr_iface_vlan_id.attr)
-		param = ISCSI_NET_PARAM_VLAN_ID;
-	else if (attr == &dev_attr_iface_vlan_priority.attr)
-		param = ISCSI_NET_PARAM_VLAN_PRIORITY;
-	else if (attr == &dev_attr_iface_vlan_enabled.attr)
-		param = ISCSI_NET_PARAM_VLAN_ENABLED;
-	else if (attr == &dev_attr_iface_mtu.attr)
-		param = ISCSI_NET_PARAM_MTU;
-	else if (attr == &dev_attr_iface_port.attr)
-		param = ISCSI_NET_PARAM_PORT;
-	else if (attr == &dev_attr_iface_ipaddress_state.attr)
-		param = ISCSI_NET_PARAM_IPADDR_STATE;
-	else if (attr == &dev_attr_iface_delayed_ack_en.attr)
-		param = ISCSI_NET_PARAM_DELAYED_ACK_EN;
-	else if (attr == &dev_attr_iface_tcp_nagle_disable.attr)
-		param = ISCSI_NET_PARAM_TCP_NAGLE_DISABLE;
-	else if (attr == &dev_attr_iface_tcp_wsf_disable.attr)
-		param = ISCSI_NET_PARAM_TCP_WSF_DISABLE;
-	else if (attr == &dev_attr_iface_tcp_wsf.attr)
-		param = ISCSI_NET_PARAM_TCP_WSF;
-	else if (attr == &dev_attr_iface_tcp_timer_scale.attr)
-		param = ISCSI_NET_PARAM_TCP_TIMER_SCALE;
-	else if (attr == &dev_attr_iface_tcp_timestamp_en.attr)
-		param = ISCSI_NET_PARAM_TCP_TIMESTAMP_EN;
-	else if (attr == &dev_attr_iface_cache_id.attr)
-		param = ISCSI_NET_PARAM_CACHE_ID;
-	else if (attr == &dev_attr_iface_redirect_en.attr)
-		param = ISCSI_NET_PARAM_REDIRECT_EN;
 	else if (attr == &dev_attr_iface_def_taskmgmt_tmo.attr)
 		param = ISCSI_IFACE_PARAM_DEF_TASKMGMT_TMO;
 	else if (attr == &dev_attr_iface_header_digest.attr)
 		param = ISCSI_IFACE_PARAM_STRICT_LOGIN_COMP_EN;
 	else if (attr == &dev_attr_iface_initiator_name.attr)
 		param = ISCSI_IFACE_PARAM_INITIATOR_NAME;
+	if (param != -1)
+		return t->attr_is_visible(ISCSI_IFACE_PARAM, param);
+	if (attr == &dev_attr_iface_vlan_id.attr)
+		param = ISCSI_NET_PARAM_VLAN_ID;
+	else if (attr == &dev_attr_iface_vlan_priority.attr)
+		param = ISCSI_NET_PARAM_VLAN_PRIORITY;
+	else if (attr == &dev_attr_iface_vlan_enabled.attr)
+		param = ISCSI_NET_PARAM_VLAN_ENABLED;
+	else if (attr == &dev_attr_iface_mtu.attr)
+		param = ISCSI_NET_PARAM_MTU;
+	else if (attr == &dev_attr_iface_port.attr)
+		param = ISCSI_NET_PARAM_PORT;
+	else if (attr == &dev_attr_iface_ipaddress_state.attr)
+		param = ISCSI_NET_PARAM_IPADDR_STATE;
+	else if (attr == &dev_attr_iface_delayed_ack_en.attr)
+		param = ISCSI_NET_PARAM_DELAYED_ACK_EN;
+	else if (attr == &dev_attr_iface_tcp_nagle_disable.attr)
+		param = ISCSI_NET_PARAM_TCP_NAGLE_DISABLE;
+	else if (attr == &dev_attr_iface_tcp_wsf_disable.attr)
+		param = ISCSI_NET_PARAM_TCP_WSF_DISABLE;
+	else if (attr == &dev_attr_iface_tcp_wsf.attr)
+		param = ISCSI_NET_PARAM_TCP_WSF;
+	else if (attr == &dev_attr_iface_tcp_timer_scale.attr)
+		param = ISCSI_NET_PARAM_TCP_TIMER_SCALE;
+	else if (attr == &dev_attr_iface_tcp_timestamp_en.attr)
+		param = ISCSI_NET_PARAM_TCP_TIMESTAMP_EN;
+	else if (attr == &dev_attr_iface_cache_id.attr)
+		param = ISCSI_NET_PARAM_CACHE_ID;
+	else if (attr == &dev_attr_iface_redirect_en.attr)
+		param = ISCSI_NET_PARAM_REDIRECT_EN;
 	else if (iface->iface_type == ISCSI_IFACE_TYPE_IPV4) {
 		if (attr == &dev_attr_ipv4_iface_ipaddress.attr)
 			param = ISCSI_NET_PARAM_IPV4_ADDR;
 		return 0;
 	}
-	switch (param) {
+	return t->attr_is_visible(ISCSI_NET_PARAM, param);
-	case ISCSI_IFACE_PARAM_DEF_TASKMGMT_TMO:
-	case ISCSI_IFACE_PARAM_HDRDGST_EN:
-	case ISCSI_IFACE_PARAM_DATADGST_EN:
-	case ISCSI_IFACE_PARAM_IMM_DATA_EN:
-	case ISCSI_IFACE_PARAM_INITIAL_R2T_EN:
-	case ISCSI_IFACE_PARAM_DATASEQ_INORDER_EN:
-	case ISCSI_IFACE_PARAM_PDU_INORDER_EN:
-	case ISCSI_IFACE_PARAM_ERL:
-	case ISCSI_IFACE_PARAM_MAX_RECV_DLENGTH:
-	case ISCSI_IFACE_PARAM_FIRST_BURST:
-	case ISCSI_IFACE_PARAM_MAX_R2T:
-	case ISCSI_IFACE_PARAM_MAX_BURST:
-	case ISCSI_IFACE_PARAM_CHAP_AUTH_EN:
-	case ISCSI_IFACE_PARAM_BIDI_CHAP_EN:
-	case ISCSI_IFACE_PARAM_DISCOVERY_AUTH_OPTIONAL:
-	case ISCSI_IFACE_PARAM_DISCOVERY_LOGOUT_EN:
-	case ISCSI_IFACE_PARAM_STRICT_LOGIN_COMP_EN:
-	case ISCSI_IFACE_PARAM_INITIATOR_NAME:
-		param_type = ISCSI_IFACE_PARAM;
-		break;
-	default:
-		param_type = ISCSI_NET_PARAM;
-	}
-	return t->attr_is_visible(param_type, param);
 }
 static struct attribute *iscsi_iface_attrs[] = {

drivers/spi/spi-atmel.c+2−7

 		}
 		mr = spi_readl(as, MR);
-		if (spi->cs_gpiod)
-			gpiod_set_value(spi->cs_gpiod, 1);
 	} else {
 		u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
 		int i;
 		mr = spi_readl(as, MR);
 		mr = SPI_BFINS(PCS, ~(1 << chip_select), mr);
-		if (spi->cs_gpiod)
-			gpiod_set_value(spi->cs_gpiod, 1);
 		spi_writel(as, MR, mr);
 	}
 	if (!spi->cs_gpiod)
 		spi_writel(as, CR, SPI_BIT(LASTXFER));
-	else
-		gpiod_set_value(spi->cs_gpiod, 0);
 }
 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
 	master->bus_num = pdev->id;
 	master->num_chipselect = 4;
 	master->setup = atmel_spi_setup;
-	master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
+	master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX |
+			SPI_MASTER_GPIO_SS);
 	master->transfer_one = atmel_spi_one_transfer;
 	master->set_cs = atmel_spi_set_cs;
 	master->cleanup = atmel_spi_cleanup;

drivers/spi/spi-bcm2835.c+7−5

  * struct bcm2835_spi - BCM2835 SPI controller
  * @regs: base address of register map
  * @clk: core clock, divided to calculate serial clock
+ * @clk_hz: core clock cached speed
  * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full
  * @tfr: SPI transfer currently processed
  * @ctlr: SPI controller reverse lookup
 struct bcm2835_spi {
 	void __iomem *regs;
 	struct clk *clk;
+	unsigned long clk_hz;
 	int irq;
 	struct spi_transfer *tfr;
 	struct spi_controller *ctlr;
 {
 	struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
 	struct bcm2835_spidev *slv = spi_get_ctldata(spi);
-	unsigned long spi_hz, clk_hz, cdiv;
+	unsigned long spi_hz, cdiv;
 	unsigned long hz_per_byte, byte_limit;
 	u32 cs = slv->prepare_cs;
 	/* set clock */
 	spi_hz = tfr->speed_hz;
-	clk_hz = clk_get_rate(bs->clk);
-	if (spi_hz >= clk_hz / 2) {
+	if (spi_hz >= bs->clk_hz / 2) {
 		cdiv = 2; /* clk_hz/2 is the fastest we can go */
 	} else if (spi_hz) {
 		/* CDIV must be a multiple of two */
-		cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
+		cdiv = DIV_ROUND_UP(bs->clk_hz, spi_hz);
 		cdiv += (cdiv % 2);
 		if (cdiv >= 65536)
 	} else {
 		cdiv = 0; /* 0 is the slowest we can go */
 	}
-	tfr->effective_speed_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
+	tfr->effective_speed_hz = cdiv ? (bs->clk_hz / cdiv) : (bs->clk_hz / 65536);
 	bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
 	/* handle all the 3-wire mode */
 		return bs->irq ? bs->irq : -ENODEV;
 	clk_prepare_enable(bs->clk);
+	bs->clk_hz = clk_get_rate(bs->clk);
 	err = bcm2835_dma_init(ctlr, &pdev->dev, bs);
 	if (err)

drivers/spi/spi-cadence-quadspi.c+17−13

@@ -309,6 +309,9 @@ static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr) · 308 unmodified lines
309	{	309	{
310	unsigned int dummy_clk;	310	unsigned int dummy_clk;
311		311
		312	if (!op->dummy.nbytes)
		313	return 0;
		314
312	dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);	315	dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
313	if (dtr)	316	if (dtr)
314	dummy_clk /= 2;	317	dummy_clk /= 2;
@@ -797,19 +800,20 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, · 482 unmodified lines
797	reg = cqspi_calc_rdreg(f_pdata);	800	reg = cqspi_calc_rdreg(f_pdata);
798	writel(reg, reg_base + CQSPI_REG_RD_INSTR);	801	writel(reg, reg_base + CQSPI_REG_RD_INSTR);
799		802
800	if (f_pdata->dtr) {	803	/*
801	/*	804	* SPI NAND flashes require the address of the status register to be
802	* Some flashes like the cypress Semper flash expect a 4-byte	805	* passed in the Read SR command. Also, some SPI NOR flashes like the
803	* dummy address with the Read SR command in DTR mode, but this	806	* cypress Semper flash expect a 4-byte dummy address in the Read SR
804	* controller does not support sending address with the Read SR	807	* command in DTR mode.
805	* command. So, disable write completion polling on the	808	*
806	* controller's side. spi-nor will take care of polling the	809	* But this controller does not support address phase in the Read SR
807	* status register.	810	* command when doing auto-HW polling. So, disable write completion
808	*/	811	* polling on the controller's side. spinand and spi-nor will take
809	reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);	812	* care of polling the status register.
810	reg \|= CQSPI_REG_WR_DISABLE_AUTO_POLL;	813	*/
811	writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);	814	reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
812	}	815	reg \|= CQSPI_REG_WR_DISABLE_AUTO_POLL;
		816	writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
813		817
814	reg = readl(reg_base + CQSPI_REG_SIZE);	818	reg = readl(reg_base + CQSPI_REG_SIZE);
815	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;	819	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;

drivers/spi/spi-cadence.c+9−5

 		goto clk_dis_apb;
 	}
+	pm_runtime_use_autosuspend(&pdev->dev);
+	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
+	pm_runtime_get_noresume(&pdev->dev);
+	pm_runtime_set_active(&pdev->dev);
+	pm_runtime_enable(&pdev->dev);
 	ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
 	if (ret < 0)
 		master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
 	/* SPI controller initializations */
 	cdns_spi_init_hw(xspi);
-	pm_runtime_set_active(&pdev->dev);
-	pm_runtime_enable(&pdev->dev);
-	pm_runtime_use_autosuspend(&pdev->dev);
-	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
 	irq = platform_get_irq(pdev, 0);
 	if (irq <= 0) {
 		ret = -ENXIO;
 	master->bits_per_word_mask = SPI_BPW_MASK(8);
+	pm_runtime_mark_last_busy(&pdev->dev);
+	pm_runtime_put_autosuspend(&pdev->dev);
 	ret = spi_register_master(master);
 	if (ret) {
 		dev_err(&pdev->dev, "spi_register_master failed\n");

drivers/spi/spi-imx.c+19−19

 {
 	struct spi_device *spi = msg->spi;
 	u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
-	u32 testreg;
+	u32 testreg, delay;
 	u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
 	/* set Master or Slave mode */
 	writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
+	/*
+	 * Wait until the changes in the configuration register CONFIGREG
+	 * propagate into the hardware. It takes exactly one tick of the
+	 * SCLK clock, but we will wait two SCLK clock just to be sure. The
+	 * effect of the delay it takes for the hardware to apply changes
+	 * is noticable if the SCLK clock run very slow. In such a case, if
+	 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
+	 * be asserted before the SCLK polarity changes, which would disrupt
+	 * the SPI communication as the device on the other end would consider
+	 * the change of SCLK polarity as a clock tick already.
+	 */
+	delay = (2 * 1000000) / spi_imx->spi_bus_clk;
+	if (likely(delay < 10))	/* SCLK is faster than 100 kHz */
+		udelay(delay);
+	else			/* SCLK is _very_ slow */
+		usleep_range(delay, delay + 10);
 	return 0;
 }
 				       struct spi_device *spi)
 {
 	u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
-	u32 clk, delay;
+	u32 clk;
 	/* Clear BL field and set the right value */
 	ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
 	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
-	/*
-	 * Wait until the changes in the configuration register CONFIGREG
-	 * propagate into the hardware. It takes exactly one tick of the
-	 * SCLK clock, but we will wait two SCLK clock just to be sure. The
-	 * effect of the delay it takes for the hardware to apply changes
-	 * is noticable if the SCLK clock run very slow. In such a case, if
-	 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
-	 * be asserted before the SCLK polarity changes, which would disrupt
-	 * the SPI communication as the device on the other end would consider
-	 * the change of SCLK polarity as a clock tick already.
-	 */
-	delay = (2 * 1000000) / clk;
-	if (likely(delay < 10))	/* SCLK is faster than 100 kHz */
-		udelay(delay);
-	else			/* SCLK is _very_ slow */
-		usleep_range(delay, delay + 10);
 	return 0;
 }

drivers/spi/spi-mt65xx.c+19−9

 	mtk_spi_setup_packet(master);
 	cnt = xfer->len / 4;
-	iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
+	if (xfer->tx_buf)
+		iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
+	if (xfer->rx_buf)
+		ioread32_rep(mdata->base + SPI_RX_DATA_REG, xfer->rx_buf, cnt);
 	remainder = xfer->len % 4;
 	if (remainder > 0) {
 		reg_val = 0;
-		memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);
+		if (xfer->tx_buf) {
-		writel(reg_val, mdata->base + SPI_TX_DATA_REG);
+			memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);
+			writel(reg_val, mdata->base + SPI_TX_DATA_REG);
+		}
+		if (xfer->rx_buf) {
+			reg_val = readl(mdata->base + SPI_RX_DATA_REG);
+			memcpy(xfer->rx_buf + (cnt * 4), &reg_val, remainder);
+		}
 	}
 	mtk_spi_enable_transfer(master);
 	pm_runtime_enable(&pdev->dev);
-	ret = devm_spi_register_master(&pdev->dev, master);
-	if (ret) {
-		dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
-		goto err_disable_runtime_pm;
-	}
 	if (mdata->dev_comp->need_pad_sel) {
 		if (mdata->pad_num != master->num_chipselect) {
 			dev_err(&pdev->dev,
 		dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
 			   addr_bits, ret);
+	ret = devm_spi_register_master(&pdev->dev, master);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
+		goto err_disable_runtime_pm;
+	}
 	return 0;
 err_disable_runtime_pm:

drivers/spi/spi-stm32.c+17−7

 	ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
 	mask = ier;
-	/* EOTIE is triggered on EOT, SUSP and TXC events. */
+	/*
+	 * EOTIE enables irq from EOT, SUSP and TXC events. We need to set
+	 * SUSP to acknowledge it later. TXC is automatically cleared
+	 */
 	mask |= STM32H7_SPI_SR_SUSP;
 	/*
-	 * When TXTF is set, DXPIE and TXPIE are cleared. So in case of
+	 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
-	 * Full-Duplex, need to poll RXP event to know if there are remaining
+	 * are set. So in case of Full-Duplex, need to poll TXP and RXP event.
-	 * data, before disabling SPI.
 	 */
-	if (spi->rx_buf && !spi->cur_usedma)
+	if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
-		mask |= STM32H7_SPI_SR_RXP;
+		mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
 	if (!(sr & mask)) {
 		dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
 		master->can_dma = stm32_spi_can_dma;
 	pm_runtime_set_active(&pdev->dev);
+	pm_runtime_get_noresume(&pdev->dev);
 	pm_runtime_enable(&pdev->dev);
 	ret = spi_register_master(master);
 err_pm_disable:
 	pm_runtime_disable(&pdev->dev);
+	pm_runtime_put_noidle(&pdev->dev);
+	pm_runtime_set_suspended(&pdev->dev);
 err_dma_release:
 	if (spi->dma_tx)
 		dma_release_channel(spi->dma_tx);
 	struct spi_master *master = platform_get_drvdata(pdev);
 	struct stm32_spi *spi = spi_master_get_devdata(master);
+	pm_runtime_get_sync(&pdev->dev);
 	spi_unregister_master(master);
 	spi->cfg->disable(spi);
+	pm_runtime_disable(&pdev->dev);
+	pm_runtime_put_noidle(&pdev->dev);
+	pm_runtime_set_suspended(&pdev->dev);
 	if (master->dma_tx)
 		dma_release_channel(master->dma_tx);
 	if (master->dma_rx)
 	clk_disable_unprepare(spi->clk);
-	pm_runtime_disable(&pdev->dev);
 	pinctrl_pm_select_sleep_state(&pdev->dev);

drivers/target/target_core_sbc.c+17−18

 #include "target_core_alua.h"
 static sense_reason_t
-sbc_check_prot(struct se_device *, struct se_cmd *, unsigned char *, u32, bool);
+sbc_check_prot(struct se_device *, struct se_cmd *, unsigned char, u32, bool);
 static sense_reason_t sbc_execute_unmap(struct se_cmd *cmd);
 static sense_reason_t
 }
 static sense_reason_t
-sbc_setup_write_same(struct se_cmd *cmd, unsigned char *flags, struct sbc_ops *ops)
+sbc_setup_write_same(struct se_cmd *cmd, unsigned char flags, struct sbc_ops *ops)
 {
 	struct se_device *dev = cmd->se_dev;
 	sector_t end_lba = dev->transport->get_blocks(dev) + 1;
 	unsigned int sectors = sbc_get_write_same_sectors(cmd);
 	sense_reason_t ret;
-	if ((flags[0] & 0x04) || (flags[0] & 0x02)) {
+	if ((flags & 0x04) || (flags & 0x02)) {
 		pr_err("WRITE_SAME PBDATA and LBDATA"
 			" bits not supported for Block Discard"
 			" Emulation\n");
 	}
 	/* We always have ANC_SUP == 0 so setting ANCHOR is always an error */
-	if (flags[0] & 0x10) {
+	if (flags & 0x10) {
 		pr_warn("WRITE SAME with ANCHOR not supported\n");
 		return TCM_INVALID_CDB_FIELD;
 	}
 	 * Special case for WRITE_SAME w/ UNMAP=1 that ends up getting
 	 * translated into block discard requests within backend code.
 	 */
-	if (flags[0] & 0x08) {
+	if (flags & 0x08) {
 		if (!ops->execute_unmap)
 			return TCM_UNSUPPORTED_SCSI_OPCODE;
 	if (!ops->execute_write_same)
 		return TCM_UNSUPPORTED_SCSI_OPCODE;
-	ret = sbc_check_prot(dev, cmd, &cmd->t_task_cdb[0], sectors, true);
+	ret = sbc_check_prot(dev, cmd, flags >> 5, sectors, true);
 	if (ret)
 		return ret;
 }
 static sense_reason_t
-sbc_check_prot(struct se_device *dev, struct se_cmd *cmd, unsigned char *cdb,
+sbc_check_prot(struct se_device *dev, struct se_cmd *cmd, unsigned char protect,
 	       u32 sectors, bool is_write)
 {
-	u8 protect = cdb[1] >> 5;
 	int sp_ops = cmd->se_sess->sup_prot_ops;
 	int pi_prot_type = dev->dev_attrib.pi_prot_type;
 	bool fabric_prot = false;
 		fallthrough;
 	default:
 		pr_err("Unable to determine pi_prot_type for CDB: 0x%02x "
-		       "PROTECT: 0x%02x\n", cdb[0], protect);
+		       "PROTECT: 0x%02x\n", cmd->t_task_cdb[0], protect);
 		return TCM_INVALID_CDB_FIELD;
 	}
 		if (sbc_check_dpofua(dev, cmd, cdb))
 			return TCM_INVALID_CDB_FIELD;
-		ret = sbc_check_prot(dev, cmd, cdb, sectors, false);
+		ret = sbc_check_prot(dev, cmd, cdb[1] >> 5, sectors, false);
 		if (ret)
 			return ret;
 		if (sbc_check_dpofua(dev, cmd, cdb))
 			return TCM_INVALID_CDB_FIELD;
-		ret = sbc_check_prot(dev, cmd, cdb, sectors, false);
+		ret = sbc_check_prot(dev, cmd, cdb[1] >> 5, sectors, false);
 		if (ret)
 			return ret;
 		if (sbc_check_dpofua(dev, cmd, cdb))
 			return TCM_INVALID_CDB_FIELD;
-		ret = sbc_check_prot(dev, cmd, cdb, sectors, false);
+		ret = sbc_check_prot(dev, cmd, cdb[1] >> 5, sectors, false);
 		if (ret)
 			return ret;
 		if (sbc_check_dpofua(dev, cmd, cdb))
 			return TCM_INVALID_CDB_FIELD;
-		ret = sbc_check_prot(dev, cmd, cdb, sectors, true);
+		ret = sbc_check_prot(dev, cmd, cdb[1] >> 5, sectors, true);
 		if (ret)
 			return ret;
 		if (sbc_check_dpofua(dev, cmd, cdb))
 			return TCM_INVALID_CDB_FIELD;
-		ret = sbc_check_prot(dev, cmd, cdb, sectors, true);
+		ret = sbc_check_prot(dev, cmd, cdb[1] >> 5, sectors, true);
 		if (ret)
 			return ret;
 		if (sbc_check_dpofua(dev, cmd, cdb))
 			return TCM_INVALID_CDB_FIELD;
-		ret = sbc_check_prot(dev, cmd, cdb, sectors, true);
+		ret = sbc_check_prot(dev, cmd, cdb[1] >> 5, sectors, true);
 		if (ret)
 			return ret;
 			size = sbc_get_size(cmd, 1);
 			cmd->t_task_lba = get_unaligned_be64(&cdb[12]);
-			ret = sbc_setup_write_same(cmd, &cdb[10], ops);
+			ret = sbc_setup_write_same(cmd, cdb[10], ops);
 			if (ret)
 				return ret;
 			break;
 		size = sbc_get_size(cmd, 1);
 		cmd->t_task_lba = get_unaligned_be64(&cdb[2]);
-		ret = sbc_setup_write_same(cmd, &cdb[1], ops);
+		ret = sbc_setup_write_same(cmd, cdb[1], ops);
 		if (ret)
 			return ret;
 		break;
 		 * Follow sbcr26 with WRITE_SAME (10) and check for the existence
 		 * of byte 1 bit 3 UNMAP instead of original reserved field
 		 */
-		ret = sbc_setup_write_same(cmd, &cdb[1], ops);
+		ret = sbc_setup_write_same(cmd, cdb[1], ops);
 		if (ret)
 			return ret;
 		break;

drivers/target/target_core_transport.c+1−1

@@ -886,7 +886,7 @@ void target_complete_cmd(struct se_cmd *cmd, u8 scsi_status) · 885 unmodified lines
886	INIT_WORK(&cmd->work, success ? target_complete_ok_work :	886	INIT_WORK(&cmd->work, success ? target_complete_ok_work :
887	target_complete_failure_work);	887	target_complete_failure_work);
888		888
889	if (wwn->cmd_compl_affinity == SE_COMPL_AFFINITY_CPUID)	889	if (!wwn \|\| wwn->cmd_compl_affinity == SE_COMPL_AFFINITY_CPUID)
890	cpu = cmd->cpuid;	890	cpu = cmd->cpuid;
891	else	891	else
892	cpu = wwn->cmd_compl_affinity;	892	cpu = wwn->cmd_compl_affinity;

drivers/usb/class/cdc-wdm.c+3−3

drivers/usb/core/devio.c+1−1

@@ -1133,7 +1133,7 @@ static int do_proc_control(struct usb_dev_state *ps, · 1132 unmodified lines
1133	"wIndex=%04x wLength=%04x\n",	1133	"wIndex=%04x wLength=%04x\n",
1134	ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,	1134	ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1135	ctrl->wIndex, ctrl->wLength);	1135	ctrl->wIndex, ctrl->wLength);
1136	if (ctrl->bRequestType & 0x80) {	1136	if ((ctrl->bRequestType & USB_DIR_IN) && ctrl->wLength) {
1137	pipe = usb_rcvctrlpipe(dev, 0);	1137	pipe = usb_rcvctrlpipe(dev, 0);
1138	snoop_urb(dev, NULL, pipe, ctrl->wLength, tmo, SUBMIT, NULL, 0);	1138	snoop_urb(dev, NULL, pipe, ctrl->wLength, tmo, SUBMIT, NULL, 0);
1139		1139

drivers/usb/core/hub.c+84−36

@@ -48,6 +48,7 @@ · 47 unmodified lines
48		48
49	#define USB_TP_TRANSMISSION_DELAY 40 /* ns */	49	#define USB_TP_TRANSMISSION_DELAY 40 /* ns */
50	#define USB_TP_TRANSMISSION_DELAY_MAX 65535 /* ns */	50	#define USB_TP_TRANSMISSION_DELAY_MAX 65535 /* ns */
		51	#define USB_PING_RESPONSE_TIME 400 /* ns */
51		52
52	/* Protect struct usb_device->state and ->children members	53	/* Protect struct usb_device->state and ->children members
53	* Note: Both are also protected by ->dev.sem, except that ->state can	54	* Note: Both are also protected by ->dev.sem, except that ->state can
@@ -182,8 +183,9 @@ int usb_device_supports_lpm(struct usb_device *udev) · 128 unmodified lines
182	}	183	}
183		184
184	/*	185	/*
185	* Set the Maximum Exit Latency (MEL) for the host to initiate a transition from	186	* Set the Maximum Exit Latency (MEL) for the host to wakup up the path from
186	* either U1 or U2.	187	* U1/U2, send a PING to the device and receive a PING_RESPONSE.
		188	* See USB 3.1 section C.1.5.2
187	*/	189	*/
188	static void usb_set_lpm_mel(struct usb_device *udev,	190	static void usb_set_lpm_mel(struct usb_device *udev,
189	struct usb3_lpm_parameters *udev_lpm_params,	191	struct usb3_lpm_parameters *udev_lpm_params,
@@ -193,35 +195,37 @@ static void usb_set_lpm_mel(struct usb_device *udev, · 3 unmodified lines
193	unsigned int hub_exit_latency)	195	unsigned int hub_exit_latency)
194	{	196	{
195	unsigned int total_mel;	197	unsigned int total_mel;
196	unsigned int device_mel;
197	unsigned int hub_mel;
198		198
199	/*	199	/*
200	* Calculate the time it takes to transition all links from the roothub	200	* tMEL1. time to transition path from host to device into U0.
201	* to the parent hub into U0. The parent hub must then decode the	201	* MEL for parent already contains the delay up to parent, so only add
202	* packet (hub header decode latency) to figure out which port it was	202	* the exit latency for the last link (pick the slower exit latency),
203	* bound for.	203	* and the hub header decode latency. See USB 3.1 section C 2.2.1
204	*	204	* Store MEL in nanoseconds
205	* The Hub Header decode latency is expressed in 0.1us intervals (0x1
206	* means 0.1us). Multiply that by 100 to get nanoseconds.
207	*/	205	*/
208	total_mel = hub_lpm_params->mel +	206	total_mel = hub_lpm_params->mel +
209	(hub->descriptor->u.ss.bHubHdrDecLat * 100);	207	max(udev_exit_latency, hub_exit_latency) * 1000 +
		208	hub->descriptor->u.ss.bHubHdrDecLat * 100;
210		209
211	/*	210	/*
212	* How long will it take to transition the downstream hub's port into	211	* tMEL2. Time to submit PING packet. Sum of tTPTransmissionDelay for
213	* U0? The greater of either the hub exit latency or the device exit	212	* each link + wHubDelay for each hub. Add only for last link.
214	* latency.	213	* tMEL4, the time for PING_RESPONSE to traverse upstream is similar.
215	*	214	* Multiply by 2 to include it as well.
216	* The BOS U1/U2 exit latencies are expressed in 1us intervals.
217	* Multiply that by 1000 to get nanoseconds.
218	*/	215	*/
219	device_mel = udev_exit_latency * 1000;	216	total_mel += (__le16_to_cpu(hub->descriptor->u.ss.wHubDelay) +
220	hub_mel = hub_exit_latency * 1000;	217	USB_TP_TRANSMISSION_DELAY) * 2;
221	if (device_mel > hub_mel)	218
222	total_mel += device_mel;	219	/*
223	else	220	* tMEL3, tPingResponse. Time taken by device to generate PING_RESPONSE
224	total_mel += hub_mel;	221	* after receiving PING. Also add 2100ns as stated in USB 3.1 C 1.5.2.4
		222	* to cover the delay if the PING_RESPONSE is queued behind a Max Packet
		223	* Size DP.
		224	* Note these delays should be added only once for the entire path, so
		225	* add them to the MEL of the device connected to the roothub.
		226	*/
		227	if (!hub->hdev->parent)
		228	total_mel += USB_PING_RESPONSE_TIME + 2100;
225		229
226	udev_lpm_params->mel = total_mel;	230	udev_lpm_params->mel = total_mel;
227	}	231	}
@@ -4112,6 +4116,47 @@ static int usb_set_lpm_timeout(struct usb_device *udev, · 3884 unmodified lines
4112	return 0;	4116	return 0;
4113	}	4117	}
4114		4118
		4119	/*
		4120	* Don't allow device intiated U1/U2 if the system exit latency + one bus
		4121	* interval is greater than the minimum service interval of any active
		4122	* periodic endpoint. See USB 3.2 section 9.4.9
		4123	*/
		4124	static bool usb_device_may_initiate_lpm(struct usb_device *udev,
		4125	enum usb3_link_state state)
		4126	{
		4127	unsigned int sel; /* us */
		4128	int i, j;
		4129
		4130	if (state == USB3_LPM_U1)
		4131	sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
		4132	else if (state == USB3_LPM_U2)
		4133	sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
		4134	else
		4135	return false;
		4136
		4137	for (i = 0; i < udev->actconfig->desc.bNumInterfaces; i++) {
		4138	struct usb_interface *intf;
		4139	struct usb_endpoint_descriptor *desc;
		4140	unsigned int interval;
		4141
		4142	intf = udev->actconfig->interface[i];
		4143	if (!intf)
		4144	continue;
		4145
		4146	for (j = 0; j < intf->cur_altsetting->desc.bNumEndpoints; j++) {
		4147	desc = &intf->cur_altsetting->endpoint[j].desc;
		4148
		4149	if (usb_endpoint_xfer_int(desc) \|\|
		4150	usb_endpoint_xfer_isoc(desc)) {
		4151	interval = (1 << (desc->bInterval - 1)) * 125;
		4152	if (sel + 125 > interval)
		4153	return false;
		4154	}
		4155	}
		4156	}
		4157	return true;
		4158	}
		4159
4115	/*	4160	/*
4116	* Enable the hub-initiated U1/U2 idle timeouts, and enable device-initiated	4161	* Enable the hub-initiated U1/U2 idle timeouts, and enable device-initiated
4117	* U1/U2 entry.	4162	* U1/U2 entry.
@@ -4184,20 +4229,23 @@ static void usb_enable_link_state(struct usb_hcd hcd, struct usb_device udev, · 66 unmodified lines
4184	* U1/U2_ENABLE	4229	* U1/U2_ENABLE
4185	*/	4230	*/
4186	if (udev->actconfig &&	4231	if (udev->actconfig &&
4187	usb_set_device_initiated_lpm(udev, state, true) == 0) {	4232	usb_device_may_initiate_lpm(udev, state)) {
4188	if (state == USB3_LPM_U1)	4233	if (usb_set_device_initiated_lpm(udev, state, true)) {
4189	udev->usb3_lpm_u1_enabled = 1;	4234	/*
4190	else if (state == USB3_LPM_U2)	4235	* Request to enable device initiated U1/U2 failed,
4191	udev->usb3_lpm_u2_enabled = 1;	4236	* better to turn off lpm in this case.
4192	} else {	4237	*/
4193	/* Don't request U1/U2 entry if the device	4238	usb_set_lpm_timeout(udev, state, 0);
4194	* cannot transition to U1/U2.	4239	hcd->driver->disable_usb3_lpm_timeout(hcd, udev, state);
4195	*/	4240	return;
4196	usb_set_lpm_timeout(udev, state, 0);	4241	}
4197	hcd->driver->disable_usb3_lpm_timeout(hcd, udev, state);
4198	}	4242	}
4199	}
4200		4243
		4244	if (state == USB3_LPM_U1)
		4245	udev->usb3_lpm_u1_enabled = 1;
		4246	else if (state == USB3_LPM_U2)
		4247	udev->usb3_lpm_u2_enabled = 1;
		4248	}
4201	/*	4249	/*
4202	* Disable the hub-initiated U1/U2 idle timeouts, and disable device-initiated	4250	* Disable the hub-initiated U1/U2 idle timeouts, and disable device-initiated
4203	* U1/U2 entry.	4251	* U1/U2 entry.

drivers/usb/core/quirks.c+0−4

@@ -501,10 +501,6 @@ static const struct usb_device_id usb_quirk_list[] = { · 500 unmodified lines
501	/* DJI CineSSD */	501	/* DJI CineSSD */
502	{ USB_DEVICE(0x2ca3, 0x0031), .driver_info = USB_QUIRK_NO_LPM },	502	{ USB_DEVICE(0x2ca3, 0x0031), .driver_info = USB_QUIRK_NO_LPM },
503		503
504	/* Fibocom L850-GL LTE Modem */
505	{ USB_DEVICE(0x2cb7, 0x0007), .driver_info =
506	USB_QUIRK_IGNORE_REMOTE_WAKEUP },
507
508	/* INTEL VALUE SSD */	504	/* INTEL VALUE SSD */
509	{ USB_DEVICE(0x8086, 0xf1a5), .driver_info = USB_QUIRK_RESET_RESUME },	505	{ USB_DEVICE(0x8086, 0xf1a5), .driver_info = USB_QUIRK_RESET_RESUME },
510		506

drivers/usb/dwc2/core.h+4−0

  *			0 - No (default)
  *			1 - Partial power down
  *			2 - Hibernation
+ * @no_clock_gating:	Specifies whether to avoid clock gating feature.
+ *			0 - No (use clock gating)
+ *			1 - Yes (avoid it)
  * @lpm:		Enable LPM support.
  *			0 - No
  *			1 - Yes
 #define DWC2_POWER_DOWN_PARAM_NONE		0
 #define DWC2_POWER_DOWN_PARAM_PARTIAL		1
 #define DWC2_POWER_DOWN_PARAM_HIBERNATION	2
+	bool no_clock_gating;
 	bool lpm;
 	bool lpm_clock_gating;

drivers/usb/dwc2/core_intr.c+2−1

@@ -556,7 +556,8 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) · 555 unmodified lines
556	* If neither hibernation nor partial power down are supported,	556	* If neither hibernation nor partial power down are supported,
557	* clock gating is used to save power.	557	* clock gating is used to save power.
558	*/	558	*/
559	dwc2_gadget_enter_clock_gating(hsotg);	559	if (!hsotg->params.no_clock_gating)
		560	dwc2_gadget_enter_clock_gating(hsotg);
560	}	561	}
561		562
562	/*	563	/*

drivers/usb/dwc2/gadget.c+27−4

 		return;
 	}
-	/* Zlp for all endpoints, for ep0 only in DATA IN stage */
+	/* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
 	if (hs_ep->send_zlp) {
-		dwc2_hsotg_program_zlp(hsotg, hs_ep);
 		hs_ep->send_zlp = 0;
-		/* transfer will be completed on next complete interrupt */
+		if (!using_desc_dma(hsotg)) {
-		return;
+			dwc2_hsotg_program_zlp(hsotg, hs_ep);
+			/* transfer will be completed on next complete interrupt */
+			return;
+		}
 	}
 	if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
 					 __func__);
 		}
 	} else {
+		/* Mask GINTSTS_GOUTNAKEFF interrupt */
+		dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
 		if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
 			dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
+		if (!using_dma(hsotg)) {
+			/* Wait for GINTSTS_RXFLVL interrupt */
+			if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
+						    GINTSTS_RXFLVL, 100)) {
+				dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
+					 __func__);
+			} else {
+				/*
+				 * Pop GLOBAL OUT NAK status packet from RxFIFO
+				 * to assert GOUTNAKEFF interrupt
+				 */
+				dwc2_readl(hsotg, GRXSTSP);
+			}
+		}
 		/* Wait for global nak to take effect */
 		if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
 					    GINTSTS_GOUTNAKEFF, 100))
 		epctl = dwc2_readl(hs, epreg);
 		if (value) {
+			/* Unmask GOUTNAKEFF interrupt */
+			dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
 			if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
 				dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
 			// STALL bit will be set in GOUTNAKEFF interrupt handler

drivers/usb/dwc2/hcd.c+4−2

 		 * If not hibernation nor partial power down are supported,
 		 * clock gating is used to save power.
 		 */
-		dwc2_host_enter_clock_gating(hsotg);
+		if (!hsotg->params.no_clock_gating)
+			dwc2_host_enter_clock_gating(hsotg);
 		break;
 	}
 		 * If not hibernation nor partial power down are supported,
 		 * clock gating is used to save power.
 		 */
-		dwc2_host_enter_clock_gating(hsotg);
+		if (!hsotg->params.no_clock_gating)
+			dwc2_host_enter_clock_gating(hsotg);
 		/* After entering suspend, hardware is not accessible */
 		clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);

drivers/usb/dwc2/params.c+1−0

@@ -76,6 +76,7 @@ static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) · 75 unmodified lines
76	struct dwc2_core_params *p = &hsotg->params;	76	struct dwc2_core_params *p = &hsotg->params;
77		77
78	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;	78	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
		79	p->no_clock_gating = true;
79	p->phy_utmi_width = 8;	80	p->phy_utmi_width = 8;
80	}	81	}
81		82

drivers/usb/dwc3/core.h+1−0

@@ -1279,6 +1279,7 @@ struct dwc3 { · 1278 unmodified lines
1279	unsigned dis_metastability_quirk:1;	1279	unsigned dis_metastability_quirk:1;
1280		1280
1281	unsigned dis_split_quirk:1;	1281	unsigned dis_split_quirk:1;
		1282	unsigned async_callbacks:1;
1282		1283
1283	u16 imod_interval;	1284	u16 imod_interval;
1284	};	1285	};

drivers/usb/dwc3/ep0.c+6−4

 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 {
-	int ret;
+	int ret = -EINVAL;
-	spin_unlock(&dwc->lock);
+	if (dwc->async_callbacks) {
-	ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
+		spin_unlock(&dwc->lock);
-	spin_lock(&dwc->lock);
+		ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
+		spin_lock(&dwc->lock);
+	}
 	return ret;
 }

drivers/usb/dwc3/gadget.c+16−5

 	return ret;
 }
+static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
+{
+	struct dwc3		*dwc = gadget_to_dwc(g);
+	unsigned long		flags;
+	spin_lock_irqsave(&dwc->lock, flags);
+	dwc->async_callbacks = enable;
+	spin_unlock_irqrestore(&dwc->lock, flags);
+}
 static const struct usb_gadget_ops dwc3_gadget_ops = {
 	.get_frame		= dwc3_gadget_get_frame,
 	.wakeup			= dwc3_gadget_wakeup,
 	.udc_set_ssp_rate	= dwc3_gadget_set_ssp_rate,
 	.get_config_params	= dwc3_gadget_config_params,
 	.vbus_draw		= dwc3_gadget_vbus_draw,
+	.udc_async_callbacks	= dwc3_gadget_async_callbacks,
 };
 /* -------------------------------------------------------------------------- */
 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
 {
-	if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
+	if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
 		spin_unlock(&dwc->lock);
 		dwc->gadget_driver->disconnect(dwc->gadget);
 		spin_lock(&dwc->lock);
 static void dwc3_suspend_gadget(struct dwc3 *dwc)
 {
-	if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
+	if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
 		spin_unlock(&dwc->lock);
 		dwc->gadget_driver->suspend(dwc->gadget);
 		spin_lock(&dwc->lock);
 static void dwc3_resume_gadget(struct dwc3 *dwc)
 {
-	if (dwc->gadget_driver && dwc->gadget_driver->resume) {
+	if (dwc->async_callbacks && dwc->gadget_driver->resume) {
 		spin_unlock(&dwc->lock);
 		dwc->gadget_driver->resume(dwc->gadget);
 		spin_lock(&dwc->lock);
 	if (!dwc->gadget_driver)
 		return;
-	if (dwc->gadget->speed != USB_SPEED_UNKNOWN) {
+	if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
 		spin_unlock(&dwc->lock);
 		usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
 		spin_lock(&dwc->lock);
 	 * implemented.
 	 */
-	if (dwc->gadget_driver && dwc->gadget_driver->resume) {
+	if (dwc->async_callbacks && dwc->gadget_driver->resume) {
 		spin_unlock(&dwc->lock);
 		dwc->gadget_driver->resume(dwc->gadget);
 		spin_lock(&dwc->lock);

drivers/usb/gadget/function/u_serial.c+1−1

@@ -1198,7 +1198,7 @@ void gserial_free_line(unsigned char port_num) · 1197 unmodified lines
1198	struct gs_port *port;	1198	struct gs_port *port;
1199		1199
1200	mutex_lock(&ports[port_num].lock);	1200	mutex_lock(&ports[port_num].lock);
1201	if (WARN_ON(!ports[port_num].port)) {	1201	if (!ports[port_num].port) {
1202	mutex_unlock(&ports[port_num].lock);	1202	mutex_unlock(&ports[port_num].lock);
1203	return;	1203	return;
1204	}	1204	}

drivers/usb/gadget/udc/tegra-xudc.c+1−0

@@ -3853,6 +3853,7 @@ static int tegra_xudc_probe(struct platform_device *pdev) · 3852 unmodified lines
3853	return 0;	3853	return 0;
3854		3854
3855	free_eps:	3855	free_eps:
		3856	pm_runtime_disable(&pdev->dev);
3856	tegra_xudc_free_eps(xudc);	3857	tegra_xudc_free_eps(xudc);
3857	free_event_ring:	3858	free_event_ring:
3858	tegra_xudc_free_event_ring(xudc);	3859	tegra_xudc_free_event_ring(xudc);

drivers/usb/host/ehci-hcd.c+14−4

 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
 {
 	struct ehci_hcd		*ehci = hcd_to_ehci (hcd);
-	u32			status, masked_status, pcd_status = 0, cmd;
+	u32			status, current_status, masked_status, pcd_status = 0;
+	u32			cmd;
 	int			bh;
 	spin_lock(&ehci->lock);
-	status = ehci_readl(ehci, &ehci->regs->status);
+	status = 0;
+	current_status = ehci_readl(ehci, &ehci->regs->status);
+restart:
 	/* e.g. cardbus physical eject */
-	if (status == ~(u32) 0) {
+	if (current_status == ~(u32) 0) {
 		ehci_dbg (ehci, "device removed\n");
 		goto dead;
 	}
+	status |= current_status;
 	/*
 	 * We don't use STS_FLR, but some controllers don't like it to
 	 * remain on, so mask it out along with the other status bits.
 	 */
-	masked_status = status & (INTR_MASK | STS_FLR);
+	masked_status = current_status & (INTR_MASK | STS_FLR);
 	/* Shared IRQ? */
 	if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
 	/* clear (just) interrupts */
 	ehci_writel(ehci, masked_status, &ehci->regs->status);
+	/* For edge interrupts, don't race with an interrupt bit being raised */
+	current_status = ehci_readl(ehci, &ehci->regs->status);
+	if (current_status & INTR_MASK)
+		goto restart;
 	cmd = ehci_readl(ehci, &ehci->regs->command);
 	bh = 0;

drivers/usb/host/max3421-hcd.c+14−30

 	 */
 	struct urb *curr_urb;
 	enum scheduling_pass sched_pass;
-	struct usb_device *loaded_dev;	/* dev that's loaded into the chip */
-	int loaded_epnum;		/* epnum whose toggles are loaded */
 	int urb_done;			/* > 0 -> no errors, < 0: errno */
 	size_t curr_len;
 	u8 hien;
  * Caller must NOT hold HCD spinlock.
  */
 static void
-max3421_set_address(struct usb_hcd *hcd, struct usb_device *dev, int epnum,
+max3421_set_address(struct usb_hcd *hcd, struct usb_device *dev, int epnum)
-		    int force_toggles)
 {
-	struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
+	int rcvtog, sndtog;
-	int old_epnum, same_ep, rcvtog, sndtog;
-	struct usb_device *old_dev;
 	u8 hctl;
-	old_dev = max3421_hcd->loaded_dev;
-	old_epnum = max3421_hcd->loaded_epnum;
-	same_ep = (dev == old_dev && epnum == old_epnum);
-	if (same_ep && !force_toggles)
-		return;
-	if (old_dev && !same_ep) {
-		/* save the old end-points toggles: */
-		u8 hrsl = spi_rd8(hcd, MAX3421_REG_HRSL);
-		rcvtog = (hrsl >> MAX3421_HRSL_RCVTOGRD_BIT) & 1;
-		sndtog = (hrsl >> MAX3421_HRSL_SNDTOGRD_BIT) & 1;
-		/* no locking: HCD (i.e., we) own toggles, don't we? */
-		usb_settoggle(old_dev, old_epnum, 0, rcvtog);
-		usb_settoggle(old_dev, old_epnum, 1, sndtog);
-	}
 	/* setup new endpoint's toggle bits: */
 	rcvtog = usb_gettoggle(dev, epnum, 0);
 	sndtog = usb_gettoggle(dev, epnum, 1);
 	hctl = (BIT(rcvtog + MAX3421_HCTL_RCVTOG0_BIT) |
 		BIT(sndtog + MAX3421_HCTL_SNDTOG0_BIT));
-	max3421_hcd->loaded_epnum = epnum;
 	spi_wr8(hcd, MAX3421_REG_HCTL, hctl);
 	/*
 	 * address-assignment so it's best to just always load the
 	 * address whenever the end-point changed/was forced.
 	 */
-	max3421_hcd->loaded_dev = dev;
 	spi_wr8(hcd, MAX3421_REG_PERADDR, dev->devnum);
 }
 	struct max3421_hcd *max3421_hcd = hcd_to_max3421(hcd);
 	struct urb *urb, *curr_urb = NULL;
 	struct max3421_ep *max3421_ep;
-	int epnum, force_toggles = 0;
+	int epnum;
 	struct usb_host_endpoint *ep;
 	struct list_head *pos;
 	unsigned long flags;
 			usb_settoggle(urb->dev, epnum, 0, 1);
 			usb_settoggle(urb->dev, epnum, 1, 1);
 			max3421_ep->pkt_state = PKT_STATE_SETUP;
-			force_toggles = 1;
 		} else
 			max3421_ep->pkt_state = PKT_STATE_TRANSFER;
 	}
 	spin_unlock_irqrestore(&max3421_hcd->lock, flags);
 	max3421_ep->last_active = max3421_hcd->frame_number;
-	max3421_set_address(hcd, urb->dev, epnum, force_toggles);
+	max3421_set_address(hcd, urb->dev, epnum);
 	max3421_set_speed(hcd, urb->dev);
 	max3421_next_transfer(hcd, 0);
 	return 1;
 		status = 0;
 	urb = max3421_hcd->curr_urb;
 	if (urb) {
+		/* save the old end-points toggles: */
+		u8 hrsl = spi_rd8(hcd, MAX3421_REG_HRSL);
+		int rcvtog = (hrsl >> MAX3421_HRSL_RCVTOGRD_BIT) & 1;
+		int sndtog = (hrsl >> MAX3421_HRSL_SNDTOGRD_BIT) & 1;
+		int epnum = usb_endpoint_num(&urb->ep->desc);
+		/* no locking: HCD (i.e., we) own toggles, don't we? */
+		usb_settoggle(urb->dev, epnum, 0, rcvtog);
+		usb_settoggle(urb->dev, epnum, 1, sndtog);
 		max3421_hcd->curr_urb = NULL;
 		spin_lock_irqsave(&max3421_hcd->lock, flags);
 		usb_hcd_unlink_urb_from_ep(hcd, urb);

drivers/usb/host/xhci-hub.c+2−1

 	 * Inform the usbcore about resume-in-progress by returning
 	 * a non-zero value even if there are no status changes.
 	 */
+	spin_lock_irqsave(&xhci->lock, flags);
 	status = bus_state->resuming_ports;
 	mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
-	spin_lock_irqsave(&xhci->lock, flags);
 	/* For each port, did anything change?  If so, set that bit in buf. */
 	for (i = 0; i < max_ports; i++) {
 		temp = readl(ports[i]->addr);

drivers/usb/host/xhci-pci-renesas.c+8−8

@@ -207,8 +207,7 @@ static int renesas_check_rom_state(struct pci_dev *pdev) · 206 unmodified lines
207	return 0;	207	return 0;
208		208
209	case RENESAS_ROM_STATUS_NO_RESULT: /* No result yet */	209	case RENESAS_ROM_STATUS_NO_RESULT: /* No result yet */
210	dev_dbg(&pdev->dev, "Unknown ROM status ...\n");	210	return 0;
211	break;
212		211
213	case RENESAS_ROM_STATUS_ERROR: /* Error State */	212	case RENESAS_ROM_STATUS_ERROR: /* Error State */
214	default: /* All other states are marked as "Reserved states" */	213	default: /* All other states are marked as "Reserved states" */
@@ -225,12 +224,13 @@ static int renesas_fw_check_running(struct pci_dev *pdev) · 10 unmodified lines
225	u8 fw_state;	224	u8 fw_state;
226	int err;	225	int err;
227		226
228	/*	227	/* Check if device has ROM and loaded, if so skip everything */
229	* Only if device has ROM and loaded FW we can skip loading and	228	err = renesas_check_rom(pdev);
230	* return success. Otherwise (even unknown state), attempt to load FW.	229	if (err) { /* we have rom */
231	*/	230	err = renesas_check_rom_state(pdev);
232	if (renesas_check_rom(pdev) && !renesas_check_rom_state(pdev))	231	if (!err)
233	return 0;	232	return err;
		233	}
234		234
235	/*	235	/*
236	* Test if the device is actually needing the firmware. As most	236	* Test if the device is actually needing the firmware. As most

drivers/usb/host/xhci-pci.c+7−0

 	{ /* end: all zeroes */ }
 };
 MODULE_DEVICE_TABLE(pci, pci_ids);
+/*
+ * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
+ * load firmware, so don't encumber the xhci-pci driver with it.
+ */
+#if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
 MODULE_FIRMWARE("renesas_usb_fw.mem");
+#endif
 /* pci driver glue; this is a "new style" PCI driver module */
 static struct pci_driver xhci_pci_driver = {

drivers/usb/phy/phy.c+8−2

 	list_for_each_entry(usb_phy, &phy_list, head) {
 		if (usb_phy->dev == dev)
-			break;
+			return usb_phy;
 	}
-	return usb_phy;
+	return NULL;
 }
 static void usb_phy_set_default_current(struct usb_phy *usb_phy)
 	struct usb_phy *usb_phy;
 	char uchger_state[50] = { 0 };
 	char uchger_type[50] = { 0 };
+	unsigned long flags;
+	spin_lock_irqsave(&phy_lock, flags);
 	usb_phy = __device_to_usb_phy(dev);
+	spin_unlock_irqrestore(&phy_lock, flags);
+	if (!usb_phy)
+		return -ENODEV;
 	snprintf(uchger_state, ARRAY_SIZE(uchger_state),
 		 "USB_CHARGER_STATE=%s", usb_chger_state[usb_phy->chg_state]);

drivers/usb/renesas_usbhs/fifo.c+7−0

 #define usbhsf_dma_map(p)	__usbhsf_dma_map_ctrl(p, 1)
 #define usbhsf_dma_unmap(p)	__usbhsf_dma_map_ctrl(p, 0)
 static int __usbhsf_dma_map_ctrl(struct usbhs_pkt *pkt, int map);
+static void usbhsf_tx_irq_ctrl(struct usbhs_pipe *pipe, int enable);
+static void usbhsf_rx_irq_ctrl(struct usbhs_pipe *pipe, int enable);
 struct usbhs_pkt *usbhs_pkt_pop(struct usbhs_pipe *pipe, struct usbhs_pkt *pkt)
 {
 	struct usbhs_priv *priv = usbhs_pipe_to_priv(pipe);
 		if (chan) {
 			dmaengine_terminate_all(chan);
 			usbhsf_dma_unmap(pkt);
+		} else {
+			if (usbhs_pipe_is_dir_in(pipe))
+				usbhsf_rx_irq_ctrl(pipe, 0);
+			else
+				usbhsf_tx_irq_ctrl(pipe, 0);
 		}
 		usbhs_pipe_clear_without_sequence(pipe, 0, 0);

drivers/usb/serial/cp210x.c+3−2

 	{ USB_DEVICE(0x10C4, 0x89A4) }, /* CESINEL FTBC Flexible Thyristor Bridge Controller */
 	{ USB_DEVICE(0x10C4, 0x89FB) }, /* Qivicon ZigBee USB Radio Stick */
 	{ USB_DEVICE(0x10C4, 0x8A2A) }, /* HubZ dual ZigBee and Z-Wave dongle */
+	{ USB_DEVICE(0x10C4, 0x8A5B) }, /* CEL EM3588 ZigBee USB Stick */
 	{ USB_DEVICE(0x10C4, 0x8A5E) }, /* CEL EM3588 ZigBee USB Stick Long Range */
 	{ USB_DEVICE(0x10C4, 0x8B34) }, /* Qivicon ZigBee USB Radio Stick */
 	{ USB_DEVICE(0x10C4, 0xEA60) }, /* Silicon Labs factory default */
 	{ USB_DEVICE(0x1901, 0x0194) },	/* GE Healthcare Remote Alarm Box */
 	{ USB_DEVICE(0x1901, 0x0195) },	/* GE B850/B650/B450 CP2104 DP UART interface */
 	{ USB_DEVICE(0x1901, 0x0196) },	/* GE B850 CP2105 DP UART interface */
-	{ USB_DEVICE(0x1901, 0x0197) }, /* GE CS1000 Display serial interface */
+	{ USB_DEVICE(0x1901, 0x0197) }, /* GE CS1000 M.2 Key E serial interface */
-	{ USB_DEVICE(0x1901, 0x0198) }, /* GE CS1000 M.2 Key E serial interface */
+	{ USB_DEVICE(0x1901, 0x0198) }, /* GE CS1000 Display serial interface */
 	{ USB_DEVICE(0x199B, 0xBA30) }, /* LORD WSDA-200-USB */
 	{ USB_DEVICE(0x19CF, 0x3000) }, /* Parrot NMEA GPS Flight Recorder */
 	{ USB_DEVICE(0x1ADB, 0x0001) }, /* Schweitzer Engineering C662 Cable */

drivers/usb/serial/option.c+3−0

 #define QUECTEL_PRODUCT_UC15			0x9090
 /* These u-blox products use Qualcomm's vendor ID */
 #define UBLOX_PRODUCT_R410M			0x90b2
+#define UBLOX_PRODUCT_R6XX			0x90fa
 /* These Yuga products use Qualcomm's vendor ID */
 #define YUGA_PRODUCT_CLM920_NC5			0x9625
 	/* u-blox products using Qualcomm vendor ID */
 	{ USB_DEVICE(QUALCOMM_VENDOR_ID, UBLOX_PRODUCT_R410M),
 	  .driver_info = RSVD(1) | RSVD(3) },
+	{ USB_DEVICE(QUALCOMM_VENDOR_ID, UBLOX_PRODUCT_R6XX),
+	  .driver_info = RSVD(3) },
 	/* Quectel products using Quectel vendor ID */
 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC21, 0xff, 0xff, 0xff),
 	  .driver_info = NUMEP2 },

drivers/usb/storage/unusual_uas.h+7−0

@@ -45,6 +45,13 @@ UNUSUAL_DEV(0x059f, 0x105f, 0x0000, 0x9999, · 44 unmodified lines
45	USB_SC_DEVICE, USB_PR_DEVICE, NULL,	45	USB_SC_DEVICE, USB_PR_DEVICE, NULL,
46	US_FL_NO_REPORT_OPCODES \| US_FL_NO_SAME),	46	US_FL_NO_REPORT_OPCODES \| US_FL_NO_SAME),
47		47
		48	/* Reported-by: Julian Sikorski <belegdol@gmail.com> */
		49	UNUSUAL_DEV(0x059f, 0x1061, 0x0000, 0x9999,
		50	"LaCie",
		51	"Rugged USB3-FW",
		52	USB_SC_DEVICE, USB_PR_DEVICE, NULL,
		53	US_FL_IGNORE_UAS),
		54
48	/*	55	/*
49	* Apricorn USB3 dongle sometimes returns "USBSUSBSUSBS" in response to SCSI	56	* Apricorn USB3 dongle sometimes returns "USBSUSBSUSBS" in response to SCSI
50	* commands in UAS mode. Observed with the 1.28 firmware; are there others?	57	* commands in UAS mode. Observed with the 1.28 firmware; are there others?

drivers/usb/typec/stusb160x.c+16−4

 	if (!fwnode)
 		return -ENODEV;
+	/*
+	 * This fwnode has a "compatible" property, but is never populated as a
+	 * struct device. Instead we simply parse it to read the properties.
+	 * This it breaks fw_devlink=on. To maintain backward compatibility
+	 * with existing DT files, we work around this by deleting any
+	 * fwnode_links to/from this fwnode.
+	 */
+	fw_devlink_purge_absent_suppliers(fwnode);
 	/*
 	 * When both VDD and VSYS power supplies are present, the low power
 	 * supply VSYS is selected when VSYS voltage is above 3.1 V.
 	typec_set_pwr_opmode(chip->port, chip->pwr_opmode);
 	if (client->irq) {
-		ret = stusb160x_irq_init(chip, client->irq);
-		if (ret)
-			goto port_unregister;
 		chip->role_sw = fwnode_usb_role_switch_get(fwnode);
 		if (IS_ERR(chip->role_sw)) {
 			ret = PTR_ERR(chip->role_sw);
 					ret);
 			goto port_unregister;
 		}
+		ret = stusb160x_irq_init(chip, client->irq);
+		if (ret)
+			goto role_sw_put;
 	} else {
 		/*
 		 * If Source or Dual power role, need to enable VDD supply
 	return 0;
+role_sw_put:
+	if (chip->role_sw)
+		usb_role_switch_put(chip->role_sw);
 port_unregister:
 	typec_unregister_port(chip->port);
 all_reg_disable:

drivers/usb/typec/tipd/core.c+9−0

@@ -629,6 +629,15 @@ static int tps6598x_probe(struct i2c_client *client) · 628 unmodified lines
629	if (!fwnode)	629	if (!fwnode)
630	return -ENODEV;	630	return -ENODEV;
631		631
		632	/*
		633	* This fwnode has a "compatible" property, but is never populated as a
		634	* struct device. Instead we simply parse it to read the properties.
		635	* This breaks fw_devlink=on. To maintain backward compatibility
		636	* with existing DT files, we work around this by deleting any
		637	* fwnode_links to/from this fwnode.
		638	*/
		639	fw_devlink_purge_absent_suppliers(fwnode);
		640
632	tps->role_sw = fwnode_usb_role_switch_get(fwnode);	641	tps->role_sw = fwnode_usb_role_switch_get(fwnode);
633	if (IS_ERR(tps->role_sw)) {	642	if (IS_ERR(tps->role_sw)) {
634	ret = PTR_ERR(tps->role_sw);	643	ret = PTR_ERR(tps->role_sw);

fs/Kconfig.binfmt+0−15

@@ -168,21 +168,6 @@ config OSF4_COMPAT · 167 unmodified lines
168	with v4 shared libraries freely available from Compaq. If you're	168	with v4 shared libraries freely available from Compaq. If you're
169	going to use shared libraries from Tru64 version 5.0 or later, say N.	169	going to use shared libraries from Tru64 version 5.0 or later, say N.
170		170
171	config BINFMT_EM86
172	tristate "Kernel support for Linux/Intel ELF binaries"
173	depends on ALPHA
174	help
175	Say Y here if you want to be able to execute Linux/Intel ELF
176	binaries just like native Alpha binaries on your Alpha machine. For
177	this to work, you need to have the emulator /usr/bin/em86 in place.
178
179	You can get the same functionality by saying N here and saying Y to
180	"Kernel support for MISC binaries".
181
182	You may answer M to compile the emulation support as a module and
183	later load the module when you want to use a Linux/Intel binary. The
184	module will be called binfmt_em86. If unsure, say Y.
185
186	config BINFMT_MISC	171	config BINFMT_MISC
187	tristate "Kernel support for MISC binaries"	172	tristate "Kernel support for MISC binaries"
188	help	173	help

fs/Makefile+0−1

@@ -39,7 +39,6 @@ obj-$(CONFIG_FS_ENCRYPTION) += crypto/ · 38 unmodified lines
39	obj-$(CONFIG_FS_VERITY) += verity/	39	obj-$(CONFIG_FS_VERITY) += verity/
40	obj-$(CONFIG_FILE_LOCKING) += locks.o	40	obj-$(CONFIG_FILE_LOCKING) += locks.o
41	obj-$(CONFIG_BINFMT_AOUT) += binfmt_aout.o	41	obj-$(CONFIG_BINFMT_AOUT) += binfmt_aout.o
42	obj-$(CONFIG_BINFMT_EM86) += binfmt_em86.o
43	obj-$(CONFIG_BINFMT_MISC) += binfmt_misc.o	42	obj-$(CONFIG_BINFMT_MISC) += binfmt_misc.o
44	obj-$(CONFIG_BINFMT_SCRIPT) += binfmt_script.o	43	obj-$(CONFIG_BINFMT_SCRIPT) += binfmt_script.o
45	obj-$(CONFIG_BINFMT_ELF) += binfmt_elf.o	44	obj-$(CONFIG_BINFMT_ELF) += binfmt_elf.o

fs/afs/cmservice.c+7−18

 static int afs_deliver_yfs_cb_callback(struct afs_call *);
-#define CM_NAME(name) \
-	char afs_SRXCB##name##_name[] __tracepoint_string =	\
-		"CB." #name
 /*
  * CB.CallBack operation type
  */
-static CM_NAME(CallBack);
 static const struct afs_call_type afs_SRXCBCallBack = {
-	.name		= afs_SRXCBCallBack_name,
+	.name		= "CB.CallBack",
 	.deliver	= afs_deliver_cb_callback,
 	.destructor	= afs_cm_destructor,
 	.work		= SRXAFSCB_CallBack,
 /*
  * CB.InitCallBackState operation type
  */
-static CM_NAME(InitCallBackState);
 static const struct afs_call_type afs_SRXCBInitCallBackState = {
-	.name		= afs_SRXCBInitCallBackState_name,
+	.name		= "CB.InitCallBackState",
 	.deliver	= afs_deliver_cb_init_call_back_state,
 	.destructor	= afs_cm_destructor,
 	.work		= SRXAFSCB_InitCallBackState,
 /*
  * CB.InitCallBackState3 operation type
  */
-static CM_NAME(InitCallBackState3);
 static const struct afs_call_type afs_SRXCBInitCallBackState3 = {
-	.name		= afs_SRXCBInitCallBackState3_name,
+	.name		= "CB.InitCallBackState3",
 	.deliver	= afs_deliver_cb_init_call_back_state3,
 	.destructor	= afs_cm_destructor,
 	.work		= SRXAFSCB_InitCallBackState,
 /*
  * CB.Probe operation type
  */
-static CM_NAME(Probe);
 static const struct afs_call_type afs_SRXCBProbe = {
-	.name		= afs_SRXCBProbe_name,
+	.name		= "CB.Probe",
 	.deliver	= afs_deliver_cb_probe,
 	.destructor	= afs_cm_destructor,
 	.work		= SRXAFSCB_Probe,
 /*
  * CB.ProbeUuid operation type
  */
-static CM_NAME(ProbeUuid);
 static const struct afs_call_type afs_SRXCBProbeUuid = {
-	.name		= afs_SRXCBProbeUuid_name,
+	.name		= "CB.ProbeUuid",
 	.deliver	= afs_deliver_cb_probe_uuid,
 	.destructor	= afs_cm_destructor,
 	.work		= SRXAFSCB_ProbeUuid,
 /*
  * CB.TellMeAboutYourself operation type
  */
-static CM_NAME(TellMeAboutYourself);
 static const struct afs_call_type afs_SRXCBTellMeAboutYourself = {
-	.name		= afs_SRXCBTellMeAboutYourself_name,
+	.name		= "CB.TellMeAboutYourself",
 	.deliver	= afs_deliver_cb_tell_me_about_yourself,
 	.destructor	= afs_cm_destructor,
 	.work		= SRXAFSCB_TellMeAboutYourself,
 /*
  * YFS CB.CallBack operation type
  */
-static CM_NAME(YFS_CallBack);
 static const struct afs_call_type afs_SRXYFSCB_CallBack = {
-	.name		= afs_SRXCBYFS_CallBack_name,
+	.name		= "YFSCB.CallBack",
 	.deliver	= afs_deliver_yfs_cb_callback,
 	.destructor	= afs_cm_destructor,
 	.work		= SRXAFSCB_CallBack,

fs/afs/dir.c+6−4

 		return ret;
 	}
-	ret = -ENOENT;
 	if (!cookie.found) {
 		_leave(" = -ENOENT [not found]");
 		return -ENOENT;
 		if (d_count(new_dentry) > 2) {
 			/* copy the target dentry's name */
-			ret = -ENOMEM;
 			op->rename.tmp = d_alloc(new_dentry->d_parent,
 						 &new_dentry->d_name);
-			if (!op->rename.tmp)
+			if (!op->rename.tmp) {
+				op->error = -ENOMEM;
 				goto error;
+			}
 			ret = afs_sillyrename(new_dvnode,
 					      AFS_FS_I(d_inode(new_dentry)),
 					      new_dentry, op->key);
-			if (ret)
+			if (ret) {
+				op->error = ret;
 				goto error;
+			}
 			op->dentry_2 = op->rename.tmp;
 			op->rename.rehash = NULL;

fs/afs/write.c+12−6

 	if (wbc->range_cyclic) {
 		start = mapping->writeback_index * PAGE_SIZE;
 		ret = afs_writepages_region(mapping, wbc, start, LLONG_MAX, &next);
-		if (start > 0 && wbc->nr_to_write > 0 && ret == 0)
+		if (ret == 0) {
-			ret = afs_writepages_region(mapping, wbc, 0, start,
+			mapping->writeback_index = next / PAGE_SIZE;
-						    &next);
+			if (start > 0 && wbc->nr_to_write > 0) {
-		mapping->writeback_index = next / PAGE_SIZE;
+				ret = afs_writepages_region(mapping, wbc, 0,
+							    start, &next);
+				if (ret == 0)
+					mapping->writeback_index =
+						next / PAGE_SIZE;
+			}
+		}
 	} else if (wbc->range_start == 0 && wbc->range_end == LLONG_MAX) {
 		ret = afs_writepages_region(mapping, wbc, 0, LLONG_MAX, &next);
-		if (wbc->nr_to_write > 0)
+		if (wbc->nr_to_write > 0 && ret == 0)
-			mapping->writeback_index = next;
+			mapping->writeback_index = next / PAGE_SIZE;
 	} else {
 		ret = afs_writepages_region(mapping, wbc,
 					    wbc->range_start, wbc->range_end, &next);

fs/binfmt_em86.c+0−110

@@ -1,110 +0,0 @@
1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* linux/fs/binfmt_em86.c
4	*
5	* Based on linux/fs/binfmt_script.c
6	* Copyright (C) 1996 Martin von Löwis
7	* original #!-checking implemented by tytso.
8	*
9	* em86 changes Copyright (C) 1997 Jim Paradis
10	*/
11
12	#include <linux/module.h>
13	#include <linux/string.h>
14	#include <linux/stat.h>
15	#include <linux/binfmts.h>
16	#include <linux/elf.h>
17	#include <linux/init.h>
18	#include <linux/fs.h>
19	#include <linux/file.h>
20	#include <linux/errno.h>
21
22
23	#define EM86_INTERP "/usr/bin/em86"
24	#define EM86_I_NAME "em86"
25
26	static int load_em86(struct linux_binprm *bprm)
27	{
28	const char i_name, i_arg;
29	char *interp;
30	struct file * file;
31	int retval;
32	struct elfhdr elf_ex;
33
34	/* Make sure this is a Linux/Intel ELF executable... */
35	elf_ex = ((struct elfhdr )bprm->buf);
36
37	if (memcmp(elf_ex.e_ident, ELFMAG, SELFMAG) != 0)
38	return -ENOEXEC;
39
40	/* First of all, some simple consistency checks */
41	if ((elf_ex.e_type != ET_EXEC && elf_ex.e_type != ET_DYN) \|\|
42	(!((elf_ex.e_machine == EM_386) \|\| (elf_ex.e_machine == EM_486))) \|\|
43	!bprm->file->f_op->mmap) {
44	return -ENOEXEC;
45	}
46
47	/* Need to be able to load the file after exec */
48	if (bprm->interp_flags & BINPRM_FLAGS_PATH_INACCESSIBLE)
49	return -ENOENT;
50
51	/* Unlike in the script case, we don't have to do any hairy
52	* parsing to find our interpreter... it's hardcoded!
53	*/
54	interp = EM86_INTERP;
55	i_name = EM86_I_NAME;
56	i_arg = NULL; /* We reserve the right to add an arg later */
57
58	/*
59	* Splice in (1) the interpreter's name for argv[0]
60	* (2) (optional) argument to interpreter
61	* (3) filename of emulated file (replace argv[0])
62	*
63	* This is done in reverse order, because of how the
64	* user environment and arguments are stored.
65	*/
66	remove_arg_zero(bprm);
67	retval = copy_string_kernel(bprm->filename, bprm);
68	if (retval < 0) return retval;
69	bprm->argc++;
70	if (i_arg) {
71	retval = copy_string_kernel(i_arg, bprm);
72	if (retval < 0) return retval;
73	bprm->argc++;
74	}
75	retval = copy_string_kernel(i_name, bprm);
76	if (retval < 0) return retval;
77	bprm->argc++;
78
79	/*
80	* OK, now restart the process with the interpreter's inode.
81	* Note that we use open_exec() as the name is now in kernel
82	* space, and we don't need to copy it.
83	*/
84	file = open_exec(interp);
85	if (IS_ERR(file))
86	return PTR_ERR(file);
87
88	bprm->interpreter = file;
89	return 0;
90	}
91
92	static struct linux_binfmt em86_format = {
93	.module = THIS_MODULE,
94	.load_binary = load_em86,
95	};
96
97	static int __init init_em86_binfmt(void)
98	{
99	register_binfmt(&em86_format);
100	return 0;
101	}
102
103	static void __exit exit_em86_binfmt(void)
104	{
105	unregister_binfmt(&em86_format);
106	}
107
108	core_initcall(init_em86_binfmt);
109	module_exit(exit_em86_binfmt);
110	MODULE_LICENSE("GPL");

fs/block_dev.c+2−0

@@ -812,6 +812,8 @@ static void bdev_free_inode(struct inode *inode) · 811 unmodified lines
812	free_percpu(bdev->bd_stats);	812	free_percpu(bdev->bd_stats);
813	kfree(bdev->bd_meta_info);	813	kfree(bdev->bd_meta_info);
814		814
		815	if (!bdev_is_partition(bdev))
		816	kfree(bdev->bd_disk);
815	kmem_cache_free(bdev_cachep, BDEV_I(inode));	817	kmem_cache_free(bdev_cachep, BDEV_I(inode));
816	}	818	}
817		819

fs/btrfs/backref.c+3−3

@@ -1488,15 +1488,15 @@ static int btrfs_find_all_roots_safe(struct btrfs_trans_handle *trans, · 1487 unmodified lines
1488	int btrfs_find_all_roots(struct btrfs_trans_handle *trans,	1488	int btrfs_find_all_roots(struct btrfs_trans_handle *trans,
1489	struct btrfs_fs_info *fs_info, u64 bytenr,	1489	struct btrfs_fs_info *fs_info, u64 bytenr,
1490	u64 time_seq, struct ulist **roots,	1490	u64 time_seq, struct ulist **roots,
1491	bool ignore_offset)	1491	bool ignore_offset, bool skip_commit_root_sem)
1492	{	1492	{
1493	int ret;	1493	int ret;
1494		1494
1495	if (!trans)	1495	if (!trans && !skip_commit_root_sem)
1496	down_read(&fs_info->commit_root_sem);	1496	down_read(&fs_info->commit_root_sem);
1497	ret = btrfs_find_all_roots_safe(trans, fs_info, bytenr,	1497	ret = btrfs_find_all_roots_safe(trans, fs_info, bytenr,
1498	time_seq, roots, ignore_offset);	1498	time_seq, roots, ignore_offset);
1499	if (!trans)	1499	if (!trans && !skip_commit_root_sem)
1500	up_read(&fs_info->commit_root_sem);	1500	up_read(&fs_info->commit_root_sem);
1501	return ret;	1501	return ret;
1502	}	1502	}

fs/btrfs/backref.h+2−1

 			 const u64 *extent_item_pos, bool ignore_offset);
 int btrfs_find_all_roots(struct btrfs_trans_handle *trans,
 			 struct btrfs_fs_info *fs_info, u64 bytenr,
-			 u64 time_seq, struct ulist **roots, bool ignore_offset);
+			 u64 time_seq, struct ulist **roots, bool ignore_offset,
+			 bool skip_commit_root_sem);
 char *btrfs_ref_to_path(struct btrfs_root *fs_root, struct btrfs_path *path,
 			u32 name_len, unsigned long name_off,
 			struct extent_buffer *eb_in, u64 parent,

fs/btrfs/compression.c+1−1

@@ -352,7 +352,7 @@ static void end_compressed_bio_write(struct bio *bio) · 351 unmodified lines
352	btrfs_record_physical_zoned(inode, cb->start, bio);	352	btrfs_record_physical_zoned(inode, cb->start, bio);
353	btrfs_writepage_endio_finish_ordered(BTRFS_I(inode), NULL,	353	btrfs_writepage_endio_finish_ordered(BTRFS_I(inode), NULL,
354	cb->start, cb->start + cb->len - 1,	354	cb->start, cb->start + cb->len - 1,
355	bio->bi_status == BLK_STS_OK);	355	!cb->errors);
356		356
357	end_compressed_writeback(inode, cb);	357	end_compressed_writeback(inode, cb);
358	/* note, our inode could be gone now */	358	/* note, our inode could be gone now */

fs/btrfs/delayed-ref.c+2−2

@@ -974,7 +974,7 @@ int btrfs_add_delayed_tree_ref(struct btrfs_trans_handle *trans, · 973 unmodified lines
974	kmem_cache_free(btrfs_delayed_tree_ref_cachep, ref);	974	kmem_cache_free(btrfs_delayed_tree_ref_cachep, ref);
975		975
976	if (qrecord_inserted)	976	if (qrecord_inserted)
977	btrfs_qgroup_trace_extent_post(fs_info, record);	977	btrfs_qgroup_trace_extent_post(trans, record);
978		978
979	return 0;	979	return 0;
980	}	980	}
@@ -1069,7 +1069,7 @@ int btrfs_add_delayed_data_ref(struct btrfs_trans_handle *trans, · 88 unmodified lines
1069		1069
1070		1070
1071	if (qrecord_inserted)	1071	if (qrecord_inserted)
1072	return btrfs_qgroup_trace_extent_post(fs_info, record);	1072	return btrfs_qgroup_trace_extent_post(trans, record);
1073	return 0;	1073	return 0;
1074	}	1074	}
1075		1075

fs/btrfs/disk-io.c+1−1

@@ -209,7 +209,7 @@ void btrfs_set_buffer_lockdep_class(u64 objectid, struct extent_buffer *eb, · 208 unmodified lines
209	static void csum_tree_block(struct extent_buffer buf, u8 result)	209	static void csum_tree_block(struct extent_buffer buf, u8 result)
210	{	210	{
211	struct btrfs_fs_info *fs_info = buf->fs_info;	211	struct btrfs_fs_info *fs_info = buf->fs_info;
212	const int num_pages = fs_info->nodesize >> PAGE_SHIFT;	212	const int num_pages = num_extent_pages(buf);
213	const int first_page_part = min_t(u32, PAGE_SIZE, fs_info->nodesize);	213	const int first_page_part = min_t(u32, PAGE_SIZE, fs_info->nodesize);
214	SHASH_DESC_ON_STACK(shash, fs_info->csum_shash);	214	SHASH_DESC_ON_STACK(shash, fs_info->csum_shash);
215	char *kaddr;	215	char *kaddr;

fs/btrfs/extent-tree.c+3−0

 	mutex_lock(&fs_info->fs_devices->device_list_mutex);
 	devices = &fs_info->fs_devices->devices;
 	list_for_each_entry(device, devices, dev_list) {
+		if (test_bit(BTRFS_DEV_STATE_MISSING, &device->dev_state))
+			continue;
 		ret = btrfs_trim_free_extents(device, &group_trimmed);
 		if (ret) {
 			dev_failed++;

fs/btrfs/inode.c+1−1

@@ -2992,7 +2992,7 @@ static int btrfs_finish_ordered_io(struct btrfs_ordered_extent *ordered_extent) · 2991 unmodified lines
2992	goto out;	2992	goto out;
2993	}	2993	}
2994		2994
2995	if (ordered_extent->disk)	2995	if (ordered_extent->bdev)
2996	btrfs_rewrite_logical_zoned(ordered_extent);	2996	btrfs_rewrite_logical_zoned(ordered_extent);
2997		2997
2998	btrfs_free_io_failure_record(inode, start, end);	2998	btrfs_free_io_failure_record(inode, start, end);

fs/btrfs/ordered-data.c+0−2

@@ -190,8 +190,6 @@ static int __btrfs_add_ordered_extent(struct btrfs_inode *inode, u64 file_offset · 189 unmodified lines
190	entry->truncated_len = (u64)-1;	190	entry->truncated_len = (u64)-1;
191	entry->qgroup_rsv = ret;	191	entry->qgroup_rsv = ret;
192	entry->physical = (u64)-1;	192	entry->physical = (u64)-1;
193	entry->disk = NULL;
194	entry->partno = (u8)-1;
195		193
196	ASSERT(type == BTRFS_ORDERED_REGULAR \|\|	194	ASSERT(type == BTRFS_ORDERED_REGULAR \|\|
197	type == BTRFS_ORDERED_NOCOW \|\|	195	type == BTRFS_ORDERED_NOCOW \|\|

fs/btrfs/ordered-data.h+1−2

@@ -145,8 +145,7 @@ struct btrfs_ordered_extent { · 144 unmodified lines
145	* command in a workqueue context	145	* command in a workqueue context
146	*/	146	*/
147	u64 physical;	147	u64 physical;
148	struct gendisk *disk;	148	struct block_device *bdev;
149	u8 partno;
150	};	149	};
151		150
152	/*	151	/*

fs/btrfs/qgroup.c+30−8

 	return 0;
 }
-int btrfs_qgroup_trace_extent_post(struct btrfs_fs_info *fs_info,
+int btrfs_qgroup_trace_extent_post(struct btrfs_trans_handle *trans,
 				   struct btrfs_qgroup_extent_record *qrecord)
 {
 	struct ulist *old_root;
 	u64 bytenr = qrecord->bytenr;
 	int ret;
-	ret = btrfs_find_all_roots(NULL, fs_info, bytenr, 0, &old_root, false);
+	/*
+	 * We are always called in a context where we are already holding a
+	 * transaction handle. Often we are called when adding a data delayed
+	 * reference from btrfs_truncate_inode_items() (truncating or unlinking),
+	 * in which case we will be holding a write lock on extent buffer from a
+	 * subvolume tree. In this case we can't allow btrfs_find_all_roots() to
+	 * acquire fs_info->commit_root_sem, because that is a higher level lock
+	 * that must be acquired before locking any extent buffers.
+	 *
+	 * So we want btrfs_find_all_roots() to not acquire the commit_root_sem
+	 * but we can't pass it a non-NULL transaction handle, because otherwise
+	 * it would not use commit roots and would lock extent buffers, causing
+	 * a deadlock if it ends up trying to read lock the same extent buffer
+	 * that was previously write locked at btrfs_truncate_inode_items().
+	 *
+	 * So pass a NULL transaction handle to btrfs_find_all_roots() and
+	 * explicitly tell it to not acquire the commit_root_sem - if we are
+	 * holding a transaction handle we don't need its protection.
+	 */
+	ASSERT(trans != NULL);
+	ret = btrfs_find_all_roots(NULL, trans->fs_info, bytenr, 0, &old_root,
+				   false, true);
 	if (ret < 0) {
-		fs_info->qgroup_flags |= BTRFS_QGROUP_STATUS_FLAG_INCONSISTENT;
+		trans->fs_info->qgroup_flags |= BTRFS_QGROUP_STATUS_FLAG_INCONSISTENT;
-		btrfs_warn(fs_info,
+		btrfs_warn(trans->fs_info,
 "error accounting new delayed refs extent (err code: %d), quota inconsistent",
 			ret);
 		return 0;
 		kfree(record);
 		return 0;
 	}
-	return btrfs_qgroup_trace_extent_post(fs_info, record);
+	return btrfs_qgroup_trace_extent_post(trans, record);
 }
 int btrfs_qgroup_trace_leaf_items(struct btrfs_trans_handle *trans,
 				/* Search commit root to find old_roots */
 				ret = btrfs_find_all_roots(NULL, fs_info,
 						record->bytenr, 0,
-						&record->old_roots, false);
+						&record->old_roots, false, false);
 				if (ret < 0)
 					goto cleanup;
 			}
 			 * current root. It's safe inside commit_transaction().
 			 */
 			ret = btrfs_find_all_roots(trans, fs_info,
-				record->bytenr, BTRFS_SEQ_LAST, &new_roots, false);
+			   record->bytenr, BTRFS_SEQ_LAST, &new_roots, false, false);
 			if (ret < 0)
 				goto cleanup;
 			if (qgroup_to_skip) {
 			num_bytes = found.offset;
 		ret = btrfs_find_all_roots(NULL, fs_info, found.objectid, 0,
-					   &roots, false);
+					   &roots, false, false);
 		if (ret < 0)
 			goto out;
 		/* For rescan, just pass old_roots as NULL */

fs/btrfs/qgroup.h+1−1

@@ -298,7 +298,7 @@ int btrfs_qgroup_trace_extent_nolock( · 297 unmodified lines
298	* using current root, then we can move all expensive backref walk out of	298	* using current root, then we can move all expensive backref walk out of
299	* transaction committing, but not now as qgroup accounting will be wrong again.	299	* transaction committing, but not now as qgroup accounting will be wrong again.
300	*/	300	*/
301	int btrfs_qgroup_trace_extent_post(struct btrfs_fs_info *fs_info,	301	int btrfs_qgroup_trace_extent_post(struct btrfs_trans_handle *trans,
302	struct btrfs_qgroup_extent_record *qrecord);	302	struct btrfs_qgroup_extent_record *qrecord);
303		303
304	/*	304	/*

fs/btrfs/tests/qgroup-tests.c+10−10

@@ -224,7 +224,7 @@ static int test_no_shared_qgroup(struct btrfs_root *root, · 223 unmodified lines
224	* quota.	224	* quota.
225	*/	225	*/
226	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &old_roots,	226	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &old_roots,
227	false);	227	false, false);
228	if (ret) {	228	if (ret) {
229	ulist_free(old_roots);	229	ulist_free(old_roots);
230	test_err("couldn't find old roots: %d", ret);	230	test_err("couldn't find old roots: %d", ret);
@@ -237,7 +237,7 @@ static int test_no_shared_qgroup(struct btrfs_root *root, · 6 unmodified lines
237	return ret;	237	return ret;
238		238
239	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &new_roots,	239	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &new_roots,
240	false);	240	false, false);
241	if (ret) {	241	if (ret) {
242	ulist_free(old_roots);	242	ulist_free(old_roots);
243	ulist_free(new_roots);	243	ulist_free(new_roots);
@@ -261,7 +261,7 @@ static int test_no_shared_qgroup(struct btrfs_root *root, · 17 unmodified lines
261	new_roots = NULL;	261	new_roots = NULL;
262		262
263	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &old_roots,	263	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &old_roots,
264	false);	264	false, false);
265	if (ret) {	265	if (ret) {
266	ulist_free(old_roots);	266	ulist_free(old_roots);
267	test_err("couldn't find old roots: %d", ret);	267	test_err("couldn't find old roots: %d", ret);
@@ -273,7 +273,7 @@ static int test_no_shared_qgroup(struct btrfs_root *root, · 5 unmodified lines
273	return -EINVAL;	273	return -EINVAL;
274		274
275	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &new_roots,	275	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &new_roots,
276	false);	276	false, false);
277	if (ret) {	277	if (ret) {
278	ulist_free(old_roots);	278	ulist_free(old_roots);
279	ulist_free(new_roots);	279	ulist_free(new_roots);
@@ -325,7 +325,7 @@ static int test_multiple_refs(struct btrfs_root *root, · 45 unmodified lines
325	}	325	}
326		326
327	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &old_roots,	327	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &old_roots,
328	false);	328	false, false);
329	if (ret) {	329	if (ret) {
330	ulist_free(old_roots);	330	ulist_free(old_roots);
331	test_err("couldn't find old roots: %d", ret);	331	test_err("couldn't find old roots: %d", ret);
@@ -338,7 +338,7 @@ static int test_multiple_refs(struct btrfs_root *root, · 6 unmodified lines
338	return ret;	338	return ret;
339		339
340	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &new_roots,	340	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &new_roots,
341	false);	341	false, false);
342	if (ret) {	342	if (ret) {
343	ulist_free(old_roots);	343	ulist_free(old_roots);
344	ulist_free(new_roots);	344	ulist_free(new_roots);
@@ -360,7 +360,7 @@ static int test_multiple_refs(struct btrfs_root *root, · 15 unmodified lines
360	}	360	}
361		361
362	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &old_roots,	362	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &old_roots,
363	false);	363	false, false);
364	if (ret) {	364	if (ret) {
365	ulist_free(old_roots);	365	ulist_free(old_roots);
366	test_err("couldn't find old roots: %d", ret);	366	test_err("couldn't find old roots: %d", ret);
@@ -373,7 +373,7 @@ static int test_multiple_refs(struct btrfs_root *root, · 6 unmodified lines
373	return ret;	373	return ret;
374		374
375	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &new_roots,	375	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &new_roots,
376	false);	376	false, false);
377	if (ret) {	377	if (ret) {
378	ulist_free(old_roots);	378	ulist_free(old_roots);
379	ulist_free(new_roots);	379	ulist_free(new_roots);
@@ -401,7 +401,7 @@ static int test_multiple_refs(struct btrfs_root *root, · 21 unmodified lines
401	}	401	}
402		402
403	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &old_roots,	403	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &old_roots,
404	false);	404	false, false);
405	if (ret) {	405	if (ret) {
406	ulist_free(old_roots);	406	ulist_free(old_roots);
407	test_err("couldn't find old roots: %d", ret);	407	test_err("couldn't find old roots: %d", ret);
@@ -414,7 +414,7 @@ static int test_multiple_refs(struct btrfs_root *root, · 6 unmodified lines
414	return ret;	414	return ret;
415		415
416	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &new_roots,	416	ret = btrfs_find_all_roots(&trans, fs_info, nodesize, 0, &new_roots,
417	false);	417	false, false);
418	if (ret) {	418	if (ret) {
419	ulist_free(old_roots);	419	ulist_free(old_roots);
420	ulist_free(new_roots);	420	ulist_free(new_roots);

fs/btrfs/tree-log.c+24−11

 		spin_lock(&inode->lock);
 		inode->logged_trans = trans->transid;
 		/*
-		 * Don't update last_log_commit if we logged that an inode exists
+		 * Don't update last_log_commit if we logged that an inode exists.
-		 * after it was loaded to memory (full_sync bit set).
+		 * We do this for two reasons:
-		 * This is to prevent data loss when we do a write to the inode,
+		 *
-		 * then the inode gets evicted after all delalloc was flushed,
+		 * 1) We might have had buffered writes to this inode that were
-		 * then we log it exists (due to a rename for example) and then
+		 *    flushed and had their ordered extents completed in this
-		 * fsync it. This last fsync would do nothing (not logging the
+		 *    transaction, but we did not previously log the inode with
-		 * extents previously written).
+		 *    LOG_INODE_ALL. Later the inode was evicted and after that
+		 *    it was loaded again and this LOG_INODE_EXISTS log operation
+		 *    happened. We must make sure that if an explicit fsync against
+		 *    the inode is performed later, it logs the new extents, an
+		 *    updated inode item, etc, and syncs the log. The same logic
+		 *    applies to direct IO writes instead of buffered writes.
+		 *
+		 * 2) When we log the inode with LOG_INODE_EXISTS, its inode item
+		 *    is logged with an i_size of 0 or whatever value was logged
+		 *    before. If later the i_size of the inode is increased by a
+		 *    truncate operation, the log is synced through an fsync of
+		 *    some other inode and then finally an explicit fsync against
+		 *    this inode is made, we must make sure this fsync logs the
+		 *    inode with the new i_size, the hole between old i_size and
+		 *    the new i_size, and syncs the log.
 		 */
-		if (inode_only != LOG_INODE_EXISTS ||
+		if (inode_only != LOG_INODE_EXISTS)
-		    !test_bit(BTRFS_INODE_NEEDS_FULL_SYNC, &inode->runtime_flags))
 			inode->last_log_commit = inode->last_sub_trans;
 		spin_unlock(&inode->lock);
 	}
 	 * if this inode hasn't been logged and directory we're renaming it
 	 * from hasn't been logged, we don't need to log it
 	 */
-	if (inode->logged_trans < trans->transid &&
+	if (!inode_logged(trans, inode) &&
-	    (!old_dir || old_dir->logged_trans < trans->transid))
+	    (!old_dir || !inode_logged(trans, old_dir)))
 		return;
 	/*

fs/btrfs/volumes.c+1−0

@@ -1078,6 +1078,7 @@ static void __btrfs_free_extra_devids(struct btrfs_fs_devices *fs_devices, · 1077 unmodified lines
1078	if (test_bit(BTRFS_DEV_STATE_WRITEABLE, &device->dev_state)) {	1078	if (test_bit(BTRFS_DEV_STATE_WRITEABLE, &device->dev_state)) {
1079	list_del_init(&device->dev_alloc_list);	1079	list_del_init(&device->dev_alloc_list);
1080	clear_bit(BTRFS_DEV_STATE_WRITEABLE, &device->dev_state);	1080	clear_bit(BTRFS_DEV_STATE_WRITEABLE, &device->dev_state);
		1081	fs_devices->rw_devices--;
1081	}	1082	}
1082	list_del_init(&device->dev_list);	1083	list_del_init(&device->dev_list);
1083	fs_devices->num_devices--;	1084	fs_devices->num_devices--;

fs/btrfs/zoned.c+4−8

 		return;
 	ordered->physical = physical;
-	ordered->disk = bio->bi_bdev->bd_disk;
+	ordered->bdev = bio->bi_bdev;
-	ordered->partno = bio->bi_bdev->bd_partno;
 	btrfs_put_ordered_extent(ordered);
 }
 	struct extent_map_tree *em_tree;
 	struct extent_map *em;
 	struct btrfs_ordered_sum *sum;
-	struct block_device *bdev;
 	u64 orig_logical = ordered->disk_bytenr;
 	u64 *logical = NULL;
 	int nr, stripe_len;
 	/* Zoned devices should not have partitions. So, we can assume it is 0 */
-	ASSERT(ordered->partno == 0);
+	ASSERT(!bdev_is_partition(ordered->bdev));
-	bdev = bdgrab(ordered->disk->part0);
+	if (WARN_ON(!ordered->bdev))
-	if (WARN_ON(!bdev))
 		return;
-	if (WARN_ON(btrfs_rmap_block(fs_info, orig_logical, bdev,
+	if (WARN_ON(btrfs_rmap_block(fs_info, orig_logical, ordered->bdev,
 				     ordered->physical, &logical, &nr,
 				     &stripe_len)))
 		goto out;
 out:
 	kfree(logical);
-	bdput(bdev);
 }
 bool btrfs_check_meta_write_pointer(struct btrfs_fs_info *fs_info,

fs/ceph/mds_client.c+1−1

@@ -4456,7 +4456,7 @@ bool check_session_state(struct ceph_mds_session *s) · 4455 unmodified lines
4456	break;	4456	break;
4457	case CEPH_MDS_SESSION_CLOSING:	4457	case CEPH_MDS_SESSION_CLOSING:
4458	/* Should never reach this when we're unmounting */	4458	/* Should never reach this when we're unmounting */
4459	WARN_ON_ONCE(true);	4459	WARN_ON_ONCE(s->s_ttl);
4460	fallthrough;	4460	fallthrough;
4461	case CEPH_MDS_SESSION_NEW:	4461	case CEPH_MDS_SESSION_NEW:
4462	case CEPH_MDS_SESSION_RESTARTING:	4462	case CEPH_MDS_SESSION_RESTARTING:

fs/cifs/cifssmb.c+7−3

 				InformationLevel) - 4;
 	offset = param_offset + params;
-	/* Setup pointer to Request Data (inode type) */
+	/* Setup pointer to Request Data (inode type).
-	pRqD = (struct unlink_psx_rq *)(((char *)&pSMB->hdr.Protocol) + offset);
+	 * Note that SMB offsets are from the beginning of SMB which is 4 bytes
+	 * in, after RFC1001 field
+	 */
+	pRqD = (struct unlink_psx_rq *)((char *)(pSMB) + offset + 4);
 	pRqD->type = cpu_to_le16(type);
 	pSMB->ParameterOffset = cpu_to_le16(param_offset);
 	pSMB->DataOffset = cpu_to_le16(offset);
 	param_offset = offsetof(struct smb_com_transaction2_spi_req,
 				InformationLevel) - 4;
 	offset = param_offset + params;
-	pdata = (OPEN_PSX_REQ *)(((char *)&pSMB->hdr.Protocol) + offset);
+	/* SMB offsets are from the beginning of SMB which is 4 bytes in, after RFC1001 field */
+	pdata = (OPEN_PSX_REQ *)((char *)(pSMB) + offset + 4);
 	pdata->Level = cpu_to_le16(SMB_QUERY_FILE_UNIX_BASIC);
 	pdata->Permissions = cpu_to_le64(mode);
 	pdata->PosixOpenFlags = cpu_to_le32(posix_flags);

fs/cifs/connect.c+2−2

@@ -220,7 +220,7 @@ cifs_reconnect(struct TCP_Server_Info *server) · 219 unmodified lines
220	#ifdef CONFIG_CIFS_DFS_UPCALL	220	#ifdef CONFIG_CIFS_DFS_UPCALL
221	struct super_block *sb = NULL;	221	struct super_block *sb = NULL;
222	struct cifs_sb_info *cifs_sb = NULL;	222	struct cifs_sb_info *cifs_sb = NULL;
223	struct dfs_cache_tgt_list tgt_list = {0};	223	struct dfs_cache_tgt_list tgt_list = DFS_CACHE_TGT_LIST_INIT(tgt_list);
224	struct dfs_cache_tgt_iterator *tgt_it = NULL;	224	struct dfs_cache_tgt_iterator *tgt_it = NULL;
225	#endif	225	#endif
226		226
@@ -3130,7 +3130,7 @@ static int do_dfs_failover(const char path, const char full_path, struct cifs_ · 2903 unmodified lines
3130	{	3130	{
3131	int rc;	3131	int rc;
3132	char *npath = NULL;	3132	char *npath = NULL;
3133	struct dfs_cache_tgt_list tgt_list = {0};	3133	struct dfs_cache_tgt_list tgt_list = DFS_CACHE_TGT_LIST_INIT(tgt_list);
3134	struct dfs_cache_tgt_iterator *tgt_it = NULL;	3134	struct dfs_cache_tgt_iterator *tgt_it = NULL;
3135	struct smb3_fs_context tmp_ctx = {NULL};	3135	struct smb3_fs_context tmp_ctx = {NULL};
3136		3136

fs/cifs/dfs_cache.c+191−38

@@ -19,6 +19,7 @@ · 18 unmodified lines
19	#include "cifs_debug.h"	19	#include "cifs_debug.h"
20	#include "cifs_unicode.h"	20	#include "cifs_unicode.h"
21	#include "smb2glob.h"	21	#include "smb2glob.h"
		22	#include "dns_resolve.h"
22		23
23	#include "dfs_cache.h"	24	#include "dfs_cache.h"
24		25
@@ -911,6 +912,7 @@ static int get_targets(struct cache_entry ce, struct dfs_cache_tgt_list tl) · 886 unmodified lines
911		912
912	err_free_it:	913	err_free_it:
913	list_for_each_entry_safe(it, nit, head, it_list) {	914	list_for_each_entry_safe(it, nit, head, it_list) {
		915	list_del(&it->it_list);
914	kfree(it->it_name);	916	kfree(it->it_name);
915	kfree(it);	917	kfree(it);
916	}	918	}
@@ -1293,6 +1295,194 @@ int dfs_cache_get_tgt_share(char path, const struct dfs_cache_tgt_iterator it, · 376 unmodified lines
1293	return 0;	1295	return 0;
1294	}	1296	}
1295		1297
		1298	static bool target_share_equal(struct TCP_Server_Info server, const char s1, const char *s2)
		1299	{
		1300	char unc[sizeof("\\\\") + SERVER_NAME_LENGTH] = {0};
		1301	const char *host;
		1302	size_t hostlen;
		1303	char *ip = NULL;
		1304	struct sockaddr sa;
		1305	bool match;
		1306	int rc;
		1307
		1308	if (strcasecmp(s1, s2))
		1309	return false;
		1310
		1311	/*
		1312	* Resolve share's hostname and check if server address matches. Otherwise just ignore it
		1313	* as we could not have upcall to resolve hostname or failed to convert ip address.
		1314	*/
		1315	match = true;
		1316	extract_unc_hostname(s1, &host, &hostlen);
		1317	scnprintf(unc, sizeof(unc), "\\\\%.*s", (int)hostlen, host);
		1318
		1319	rc = dns_resolve_server_name_to_ip(unc, &ip, NULL);
		1320	if (rc < 0) {
		1321	cifs_dbg(FYI, "%s: could not resolve %.*s. assuming server address matches.\n",
		1322	__func__, (int)hostlen, host);
		1323	return true;
		1324	}
		1325
		1326	if (!cifs_convert_address(&sa, ip, strlen(ip))) {
		1327	cifs_dbg(VFS, "%s: failed to convert address \'%s\'. skip address matching.\n",
		1328	__func__, ip);
		1329	} else {
		1330	mutex_lock(&server->srv_mutex);
		1331	match = cifs_match_ipaddr((struct sockaddr *)&server->dstaddr, &sa);
		1332	mutex_unlock(&server->srv_mutex);
		1333	}
		1334
		1335	kfree(ip);
		1336	return match;
		1337	}
		1338
		1339	/*
		1340	* Mark dfs tcon for reconnecting when the currently connected tcon does not match any of the new
		1341	* target shares in @refs.
		1342	*/
		1343	static void mark_for_reconnect_if_needed(struct cifs_tcon tcon, struct dfs_cache_tgt_list tl,
		1344	const struct dfs_info3_param *refs, int numrefs)
		1345	{
		1346	struct dfs_cache_tgt_iterator *it;
		1347	int i;
		1348
		1349	for (it = dfs_cache_get_tgt_iterator(tl); it; it = dfs_cache_get_next_tgt(tl, it)) {
		1350	for (i = 0; i < numrefs; i++) {
		1351	if (target_share_equal(tcon->ses->server, dfs_cache_get_tgt_name(it),
		1352	refs[i].node_name))
		1353	return;
		1354	}
		1355	}
		1356
		1357	cifs_dbg(FYI, "%s: no cached or matched targets. mark dfs share for reconnect.\n", __func__);
		1358	for (i = 0; i < tcon->ses->chan_count; i++) {
		1359	spin_lock(&GlobalMid_Lock);
		1360	if (tcon->ses->chans[i].server->tcpStatus != CifsExiting)
		1361	tcon->ses->chans[i].server->tcpStatus = CifsNeedReconnect;
		1362	spin_unlock(&GlobalMid_Lock);
		1363	}
		1364	}
		1365
		1366	/* Refresh dfs referral of tcon and mark it for reconnect if needed */
		1367	static int refresh_tcon(struct cifs_ses *sessions, struct cifs_tcon tcon, bool force_refresh)
		1368	{
		1369	const char *path = tcon->dfs_path + 1;
		1370	struct cifs_ses *ses;
		1371	struct cache_entry *ce;
		1372	struct dfs_info3_param *refs = NULL;
		1373	int numrefs = 0;
		1374	bool needs_refresh = false;
		1375	struct dfs_cache_tgt_list tl = DFS_CACHE_TGT_LIST_INIT(tl);
		1376	int rc = 0;
		1377	unsigned int xid;
		1378
		1379	ses = find_ipc_from_server_path(sessions, path);
		1380	if (IS_ERR(ses)) {
		1381	cifs_dbg(FYI, "%s: could not find ipc session\n", __func__);
		1382	return PTR_ERR(ses);
		1383	}
		1384
		1385	down_read(&htable_rw_lock);
		1386	ce = lookup_cache_entry(path);
		1387	needs_refresh = force_refresh \|\| IS_ERR(ce) \|\| cache_entry_expired(ce);
		1388	if (!IS_ERR(ce)) {
		1389	rc = get_targets(ce, &tl);
		1390	if (rc)
		1391	cifs_dbg(FYI, "%s: could not get dfs targets: %d\n", __func__, rc);
		1392	}
		1393	up_read(&htable_rw_lock);
		1394
		1395	if (!needs_refresh) {
		1396	rc = 0;
		1397	goto out;
		1398	}
		1399
		1400	xid = get_xid();
		1401	rc = get_dfs_referral(xid, ses, path, &refs, &numrefs);
		1402	free_xid(xid);
		1403
		1404	/* Create or update a cache entry with the new referral */
		1405	if (!rc) {
		1406	dump_refs(refs, numrefs);
		1407
		1408	down_write(&htable_rw_lock);
		1409	ce = lookup_cache_entry(path);
		1410	if (IS_ERR(ce))
		1411	add_cache_entry_locked(refs, numrefs);
		1412	else if (force_refresh \|\| cache_entry_expired(ce))
		1413	update_cache_entry_locked(ce, refs, numrefs);
		1414	up_write(&htable_rw_lock);
		1415
		1416	mark_for_reconnect_if_needed(tcon, &tl, refs, numrefs);
		1417	}
		1418
		1419	out:
		1420	dfs_cache_free_tgts(&tl);
		1421	free_dfs_info_array(refs, numrefs);
		1422	return rc;
		1423	}
		1424
		1425	/**
		1426	* dfs_cache_remount_fs - remount a DFS share
		1427	*
		1428	* Reconfigure dfs mount by forcing a new DFS referral and if the currently cached targets do not
		1429	* match any of the new targets, mark it for reconnect.
		1430	*
		1431	* @cifs_sb: cifs superblock.
		1432	*
		1433	* Return zero if remounted, otherwise non-zero.
		1434	*/
		1435	int dfs_cache_remount_fs(struct cifs_sb_info *cifs_sb)
		1436	{
		1437	struct cifs_tcon *tcon;
		1438	struct mount_group *mg;
		1439	struct cifs_ses *sessions[CACHE_MAX_ENTRIES + 1] = {NULL};
		1440	int rc;
		1441
		1442	if (!cifs_sb \|\| !cifs_sb->master_tlink)
		1443	return -EINVAL;
		1444
		1445	tcon = cifs_sb_master_tcon(cifs_sb);
		1446	if (!tcon->dfs_path) {
		1447	cifs_dbg(FYI, "%s: not a dfs tcon\n", __func__);
		1448	return 0;
		1449	}
		1450
		1451	if (uuid_is_null(&cifs_sb->dfs_mount_id)) {
		1452	cifs_dbg(FYI, "%s: tcon has no dfs mount group id\n", __func__);
		1453	return -EINVAL;
		1454	}
		1455
		1456	mutex_lock(&mount_group_list_lock);
		1457	mg = find_mount_group_locked(&cifs_sb->dfs_mount_id);
		1458	if (IS_ERR(mg)) {
		1459	mutex_unlock(&mount_group_list_lock);
		1460	cifs_dbg(FYI, "%s: tcon has ipc session to refresh referral\n", __func__);
		1461	return PTR_ERR(mg);
		1462	}
		1463	kref_get(&mg->refcount);
		1464	mutex_unlock(&mount_group_list_lock);
		1465
		1466	spin_lock(&mg->lock);
		1467	memcpy(&sessions, mg->sessions, mg->num_sessions * sizeof(mg->sessions[0]));
		1468	spin_unlock(&mg->lock);
		1469
		1470	/*
		1471	* After reconnecting to a different server, unique ids won't match anymore, so we disable
		1472	* serverino. This prevents dentry revalidation to think the dentry are stale (ESTALE).
		1473	*/
		1474	cifs_autodisable_serverino(cifs_sb);
		1475	/*
		1476	* Force the use of prefix path to support failover on DFS paths that resolve to targets
		1477	* that have different prefix paths.
		1478	*/
		1479	cifs_sb->mnt_cifs_flags \|= CIFS_MOUNT_USE_PREFIX_PATH;
		1480	rc = refresh_tcon(sessions, tcon, true);
		1481
		1482	kref_put(&mg->refcount, mount_group_release);
		1483	return rc;
		1484	}
		1485
1296	/*	1486	/*
1297	* Refresh all active dfs mounts regardless of whether they are in cache or not.	1487	* Refresh all active dfs mounts regardless of whether they are in cache or not.
1298	* (cache can be cleared)	1488	* (cache can be cleared)
@@ -1303,7 +1493,6 @@ static void refresh_mounts(struct cifs_ses **sessions) · 4 unmodified lines
1303	struct cifs_ses *ses;	1493	struct cifs_ses *ses;
1304	struct cifs_tcon tcon, ntcon;	1494	struct cifs_tcon tcon, ntcon;
1305	struct list_head tcons;	1495	struct list_head tcons;
1306	unsigned int xid;
1307		1496
1308	INIT_LIST_HEAD(&tcons);	1497	INIT_LIST_HEAD(&tcons);
1309		1498
@@ -1321,44 +1510,8 @@ static void refresh_mounts(struct cifs_ses **sessions) · 11 unmodified lines
1321	spin_unlock(&cifs_tcp_ses_lock);	1510	spin_unlock(&cifs_tcp_ses_lock);
1322		1511
1323	list_for_each_entry_safe(tcon, ntcon, &tcons, ulist) {	1512	list_for_each_entry_safe(tcon, ntcon, &tcons, ulist) {
1324	const char *path = tcon->dfs_path + 1;
1325	struct cache_entry *ce;
1326	struct dfs_info3_param *refs = NULL;
1327	int numrefs = 0;
1328	bool needs_refresh = false;
1329	int rc = 0;
1330
1331	list_del_init(&tcon->ulist);	1513	list_del_init(&tcon->ulist);
1332		1514	refresh_tcon(sessions, tcon, false);
1333	ses = find_ipc_from_server_path(sessions, path);
1334	if (IS_ERR(ses))
1335	goto next_tcon;
1336
1337	down_read(&htable_rw_lock);
1338	ce = lookup_cache_entry(path);
1339	needs_refresh = IS_ERR(ce) \|\| cache_entry_expired(ce);
1340	up_read(&htable_rw_lock);
1341
1342	if (!needs_refresh)
1343	goto next_tcon;
1344
1345	xid = get_xid();
1346	rc = get_dfs_referral(xid, ses, path, &refs, &numrefs);
1347	free_xid(xid);
1348
1349	/* Create or update a cache entry with the new referral */
1350	if (!rc) {
1351	down_write(&htable_rw_lock);
1352	ce = lookup_cache_entry(path);
1353	if (IS_ERR(ce))
1354	add_cache_entry_locked(refs, numrefs);
1355	else if (cache_entry_expired(ce))
1356	update_cache_entry_locked(ce, refs, numrefs);
1357	up_write(&htable_rw_lock);
1358	}
1359
1360	next_tcon:
1361	free_dfs_info_array(refs, numrefs);
1362	cifs_put_tcon(tcon);	1515	cifs_put_tcon(tcon);
1363	}	1516	}
1364	}	1517	}

fs/cifs/dfs_cache.h+3−0

 #include <linux/uuid.h>
 #include "cifsglob.h"
+#define DFS_CACHE_TGT_LIST_INIT(var) { .tl_numtgts = 0, .tl_list = LIST_HEAD_INIT((var).tl_list), }
 struct dfs_cache_tgt_list {
 	int tl_numtgts;
 	struct list_head tl_list;
 void dfs_cache_put_refsrv_sessions(const uuid_t *mount_id);
 void dfs_cache_add_refsrv_session(const uuid_t *mount_id, struct cifs_ses *ses);
 char *dfs_cache_canonical_path(const char *path, const struct nls_table *cp, int remap);
+int dfs_cache_remount_fs(struct cifs_sb_info *cifs_sb);
 static inline struct dfs_cache_tgt_iterator *
 dfs_cache_get_next_tgt(struct dfs_cache_tgt_list *tl,

fs/cifs/file.c+1−1

@@ -4619,7 +4619,7 @@ read_complete: · 4618 unmodified lines
4619		4619
4620	static int cifs_readpage(struct file file, struct page page)	4620	static int cifs_readpage(struct file file, struct page page)
4621	{	4621	{
4622	loff_t offset = (loff_t)page->index << PAGE_SHIFT;	4622	loff_t offset = page_file_offset(page);
4623	int rc = -EACCES;	4623	int rc = -EACCES;
4624	unsigned int xid;	4624	unsigned int xid;
4625		4625

fs/cifs/fs_context.c+14−0

 #include <linux/magic.h>
 #include <linux/security.h>
 #include <net/net_namespace.h>
+#ifdef CONFIG_CIFS_DFS_UPCALL
+#include "dfs_cache.h"
+#endif
 */
 #include <linux/ctype.h>
 	smb3_cleanup_fs_context_contents(cifs_sb->ctx);
 	rc = smb3_fs_context_dup(cifs_sb->ctx, ctx);
 	smb3_update_mnt_flags(cifs_sb);
+#ifdef CONFIG_CIFS_DFS_UPCALL
+	if (!rc)
+		rc = dfs_cache_remount_fs(cifs_sb);
+#endif
 	return rc;
 }
 		ctx->cred_uid = uid;
 		ctx->cruid_specified = true;
 		break;
+	case Opt_backupuid:
+		uid = make_kuid(current_user_ns(), result.uint_32);
+		if (!uid_valid(uid))
+			goto cifs_parse_mount_err;
+		ctx->backupuid = uid;
+		ctx->backupuid_specified = true;
+		break;
 	case Opt_backupgid:
 		gid = make_kgid(current_user_ns(), result.uint_32);
 		if (!gid_valid(gid))

fs/cifs/smb2ops.c+37−11

 {
 	struct cifs_io_parms io_parms = {0};
 	int nbytes;
+	int rc = 0;
 	struct kvec iov[2];
 	io_parms.netfid = cfile->fid.netfid;
 	io_parms.tcon = tcon;
 	io_parms.persistent_fid = cfile->fid.persistent_fid;
 	io_parms.volatile_fid = cfile->fid.volatile_fid;
-	io_parms.offset = off;
-	io_parms.length = len;
-	/* iov[0] is reserved for smb header */
+	while (len) {
-	iov[1].iov_base = buf;
+		io_parms.offset = off;
-	iov[1].iov_len = io_parms.length;
+		io_parms.length = len;
-	return SMB2_write(xid, &io_parms, &nbytes, iov, 1);
+		if (io_parms.length > SMB2_MAX_BUFFER_SIZE)
+			io_parms.length = SMB2_MAX_BUFFER_SIZE;
+		/* iov[0] is reserved for smb header */
+		iov[1].iov_base = buf;
+		iov[1].iov_len = io_parms.length;
+		rc = SMB2_write(xid, &io_parms, &nbytes, iov, 1);
+		if (rc)
+			break;
+		if (nbytes > len)
+			return -EINVAL;
+		buf += nbytes;
+		off += nbytes;
+		len -= nbytes;
+	}
+	return rc;
 }
 static int smb3_simple_fallocate_range(unsigned int xid,
 			(char **)&out_data, &out_data_len);
 	if (rc)
 		goto out;
-	/*
-	 * It is already all allocated
-	 */
-	if (out_data_len == 0)
-		goto out;
 	buf = kzalloc(1024 * 1024, GFP_KERNEL);
 	if (buf == NULL) {
 		goto out;
 	}
+	if (keep_size == true) {
+		/*
+		 * We can not preallocate pages beyond the end of the file
+		 * in SMB2
+		 */
+		if (off >= i_size_read(inode)) {
+			rc = 0;
+			goto out;
+		}
+		/*
+		 * For fallocates that are partially beyond the end of file,
+		 * clamp len so we only fallocate up to the end of file.
+		 */
+		if (off + len > i_size_read(inode)) {
+			len = i_size_read(inode) - off;
+		}
+	}
 	if ((keep_size == true) || (i_size_read(inode) >= off + len)) {
 		/*
 		 * At this point, we are trying to fallocate an internal

fs/ext2/dir.c+6−6

 	return err;
 }
-static bool ext2_check_page(struct page *page, int quiet)
+static bool ext2_check_page(struct page *page, int quiet, char *kaddr)
 {
 	struct inode *dir = page->mapping->host;
 	struct super_block *sb = dir->i_sb;
 	unsigned chunk_size = ext2_chunk_size(dir);
-	char *kaddr = page_address(page);
 	u32 max_inumber = le32_to_cpu(EXT2_SB(sb)->s_es->s_inodes_count);
 	unsigned offs, rec_len;
 	unsigned limit = PAGE_SIZE;
 	if (!IS_ERR(page)) {
 		*page_addr = kmap_local_page(page);
 		if (unlikely(!PageChecked(page))) {
-			if (PageError(page) || !ext2_check_page(page, quiet))
+			if (PageError(page) || !ext2_check_page(page, quiet,
+								*page_addr))
 				goto fail;
 		}
 	}
  * ext2_delete_entry deletes a directory entry by merging it with the
  * previous entry. Page is up-to-date.
  */
-int ext2_delete_entry (struct ext2_dir_entry_2 * dir, struct page * page )
+int ext2_delete_entry (struct ext2_dir_entry_2 *dir, struct page *page,
+			char *kaddr)
 {
 	struct inode *inode = page->mapping->host;
-	char *kaddr = page_address(page);
 	unsigned from = ((char*)dir - kaddr) & ~(ext2_chunk_size(inode)-1);
 	unsigned to = ((char *)dir - kaddr) +
 				ext2_rec_len_from_disk(dir->rec_len);
 		de = ext2_next_entry(de);
 	}
 	if (pde)
-		from = (char*)pde - (char*)page_address(page);
+		from = (char *)pde - kaddr;
 	pos = page_offset(page) + from;
 	lock_page(page);
 	err = ext2_prepare_chunk(page, pos, to - from);

fs/ext2/ext2.h+2−1

 extern int ext2_make_empty(struct inode *, struct inode *);
 extern struct ext2_dir_entry_2 *ext2_find_entry(struct inode *, const struct qstr *,
 						struct page **, void **res_page_addr);
-extern int ext2_delete_entry (struct ext2_dir_entry_2 *, struct page *);
+extern int ext2_delete_entry(struct ext2_dir_entry_2 *dir, struct page *page,
+			     char *kaddr);
 extern int ext2_empty_dir (struct inode *);
 extern struct ext2_dir_entry_2 *ext2_dotdot(struct inode *dir, struct page **p, void **pa);
 extern void ext2_set_link(struct inode *, struct ext2_dir_entry_2 *, struct page *, void *,

fs/ext2/namei.c+2−2

@@ -293,7 +293,7 @@ static int ext2_unlink(struct inode * dir, struct dentry *dentry) · 292 unmodified lines
293	goto out;	293	goto out;
294	}	294	}
295		295
296	err = ext2_delete_entry (de, page);	296	err = ext2_delete_entry (de, page, page_addr);
297	ext2_put_page(page, page_addr);	297	ext2_put_page(page, page_addr);
298	if (err)	298	if (err)
299	goto out;	299	goto out;
@@ -397,7 +397,7 @@ static int ext2_rename (struct user_namespace * mnt_userns, · 97 unmodified lines
397	old_inode->i_ctime = current_time(old_inode);	397	old_inode->i_ctime = current_time(old_inode);
398	mark_inode_dirty(old_inode);	398	mark_inode_dirty(old_inode);
399		399
400	ext2_delete_entry(old_de, old_page);	400	ext2_delete_entry(old_de, old_page, old_page_addr);
401		401
402	if (dir_de) {	402	if (dir_de) {
403	if (old_dir != new_dir)	403	if (old_dir != new_dir)

fs/fs-writeback.c+3−0

@@ -521,6 +521,9 @@ static bool inode_prepare_wbs_switch(struct inode *inode, · 520 unmodified lines
521	*/	521	*/
522	smp_mb();	522	smp_mb();
523		523
		524	if (IS_DAX(inode))
		525	return false;
		526
524	/* while holding I_WB_SWITCH, no one else can update the association */	527	/* while holding I_WB_SWITCH, no one else can update the association */
525	spin_lock(&inode->i_lock);	528	spin_lock(&inode->i_lock);
526	if (!(inode->i_sb->s_flags & SB_ACTIVE) \|\|	529	if (!(inode->i_sb->s_flags & SB_ACTIVE) \|\|

fs/hugetlbfs/inode.c+1−1

@@ -77,7 +77,7 @@ enum hugetlb_param { · 76 unmodified lines
77	static const struct fs_parameter_spec hugetlb_fs_parameters[] = {	77	static const struct fs_parameter_spec hugetlb_fs_parameters[] = {
78	fsparam_u32 ("gid", Opt_gid),	78	fsparam_u32 ("gid", Opt_gid),
79	fsparam_string("min_size", Opt_min_size),	79	fsparam_string("min_size", Opt_min_size),
80	fsparam_u32 ("mode", Opt_mode),	80	fsparam_u32oct("mode", Opt_mode),
81	fsparam_string("nr_inodes", Opt_nr_inodes),	81	fsparam_string("nr_inodes", Opt_nr_inodes),
82	fsparam_string("pagesize", Opt_pagesize),	82	fsparam_string("pagesize", Opt_pagesize),
83	fsparam_string("size", Opt_size),	83	fsparam_string("size", Opt_size),

fs/internal.h+0−1

@@ -61,7 +61,6 @@ extern void __init chrdev_init(void); · 60 unmodified lines
61	*/	61	*/
62	extern const struct fs_context_operations legacy_fs_context_ops;	62	extern const struct fs_context_operations legacy_fs_context_ops;
63	extern int parse_monolithic_mount_data(struct fs_context , void );	63	extern int parse_monolithic_mount_data(struct fs_context , void );
64	extern void fc_drop_locked(struct fs_context *);
65	extern void vfs_clean_context(struct fs_context *fc);	64	extern void vfs_clean_context(struct fs_context *fc);
66	extern int finish_clean_context(struct fs_context *fc);	65	extern int finish_clean_context(struct fs_context *fc);
67		66

fs/io-wq.c+6−1

 	int work_flags;
 	unsigned long flags;
-	if (test_bit(IO_WQ_BIT_EXIT, &wqe->wq->state)) {
+	/*
+	 * If io-wq is exiting for this task, or if the request has explicitly
+	 * been marked as one that should not get executed, cancel it here.
+	 */
+	if (test_bit(IO_WQ_BIT_EXIT, &wqe->wq->state) ||
+	    (work->flags & IO_WQ_WORK_CANCEL)) {
 		io_run_cancel(work, wqe);
 		return;
 	}

fs/io_uring.c+70−23

 {
 	struct io_kiocb *cur;
-	io_for_each_link(cur, req)
+	if (req->flags & REQ_F_LINK_TIMEOUT) {
-		io_prep_async_work(cur);
+		struct io_ring_ctx *ctx = req->ctx;
+		spin_lock_irq(&ctx->completion_lock);
+		io_for_each_link(cur, req)
+			io_prep_async_work(cur);
+		spin_unlock_irq(&ctx->completion_lock);
+	} else {
+		io_for_each_link(cur, req)
+			io_prep_async_work(cur);
+	}
 }
 static void io_queue_async_work(struct io_kiocb *req)
 	/* init ->work of the whole link before punting */
 	io_prep_async_link(req);
+	/*
+	 * Not expected to happen, but if we do have a bug where this _can_
+	 * happen, catch it here and ensure the request is marked as
+	 * canceled. That will make io-wq go through the usual work cancel
+	 * procedure rather than attempt to run this request (or create a new
+	 * worker for it).
+	 */
+	if (WARN_ON_ONCE(!same_thread_group(req->task, current)))
+		req->work.flags |= IO_WQ_WORK_CANCEL;
 	trace_io_uring_queue_async_work(ctx, io_wq_is_hashed(&req->work), req,
 					&req->work, req->flags);
 	io_wq_enqueue(tctx->io_wq, &req->work);
 			node = next;
 		}
 		if (wq_list_empty(&tctx->task_list)) {
+			spin_lock_irq(&tctx->task_lock);
 			clear_bit(0, &tctx->task_state);
-			if (wq_list_empty(&tctx->task_list))
+			if (wq_list_empty(&tctx->task_list)) {
+				spin_unlock_irq(&tctx->task_lock);
 				break;
+			}
+			spin_unlock_irq(&tctx->task_lock);
 			/* another tctx_task_work() is enqueued, yield */
 			if (test_and_set_bit(0, &tctx->task_state))
 				break;
 	io_req_task_work_add(req);
 }
+static void io_req_task_queue_reissue(struct io_kiocb *req)
+{
+	req->io_task_work.func = io_queue_async_work;
+	io_req_task_work_add(req);
+}
 static inline void io_queue_next(struct io_kiocb *req)
 {
 	struct io_kiocb *nxt = io_req_find_next(req);
  * Find and free completed poll iocbs
  */
 static void io_iopoll_complete(struct io_ring_ctx *ctx, unsigned int *nr_events,
-			       struct list_head *done)
+			       struct list_head *done, bool resubmit)
 {
 	struct req_batch rb;
 	struct io_kiocb *req;
 		req = list_first_entry(done, struct io_kiocb, inflight_entry);
 		list_del(&req->inflight_entry);
-		if (READ_ONCE(req->result) == -EAGAIN &&
+		if (READ_ONCE(req->result) == -EAGAIN && resubmit &&
 		    !(req->flags & REQ_F_DONT_REISSUE)) {
 			req->iopoll_completed = 0;
 			req_ref_get(req);
-			io_queue_async_work(req);
+			io_req_task_queue_reissue(req);
 			continue;
 		}
 }
 static int io_do_iopoll(struct io_ring_ctx *ctx, unsigned int *nr_events,
-			long min)
+			long min, bool resubmit)
 {
 	struct io_kiocb *req, *tmp;
 	LIST_HEAD(done);
 	}
 	if (!list_empty(&done))
-		io_iopoll_complete(ctx, nr_events, &done);
+		io_iopoll_complete(ctx, nr_events, &done, resubmit);
 	return ret;
 }
 	while (!list_empty(&ctx->iopoll_list)) {
 		unsigned int nr_events = 0;
-		io_do_iopoll(ctx, &nr_events, 0);
+		io_do_iopoll(ctx, &nr_events, 0, false);
 		/* let it sleep and repeat later if can't complete a request */
 		if (nr_events == 0)
 			    list_empty(&ctx->iopoll_list))
 				break;
 		}
-		ret = io_do_iopoll(ctx, &nr_events, min);
+		ret = io_do_iopoll(ctx, &nr_events, min, true);
 	} while (!ret && nr_events < min && !need_resched());
 out:
 	mutex_unlock(&ctx->uring_lock);
 	 */
 	if (percpu_ref_is_dying(&ctx->refs))
 		return false;
+	/*
+	 * Play it safe and assume not safe to re-import and reissue if we're
+	 * not in the original thread group (or in task context).
+	 */
+	if (!same_thread_group(req->task, current) || !in_task())
+		return false;
 	return true;
 }
 #else
 		req->flags &= ~REQ_F_REISSUE;
 		if (io_resubmit_prep(req)) {
 			req_ref_get(req);
-			io_queue_async_work(req);
+			io_req_task_queue_reissue(req);
 		} else {
 			int cflags = 0;
 struct io_poll_table {
 	struct poll_table_struct pt;
 	struct io_kiocb *req;
+	int nr_entries;
 	int error;
 };
 	if (req->poll.events & EPOLLONESHOT)
 		flags = 0;
 	if (!io_cqring_fill_event(ctx, req->user_data, error, flags)) {
-		io_poll_remove_waitqs(req);
 		req->poll.done = true;
 		flags = 0;
 	}
 		done = io_poll_complete(req, req->result);
 		if (done) {
+			io_poll_remove_double(req);
 			hash_del(&req->hash_node);
 		} else {
 			req->result = 0;
 	struct io_kiocb *req = pt->req;
 	/*
-	 * If poll->head is already set, it's because the file being polled
+	 * The file being polled uses multiple waitqueues for poll handling
-	 * uses multiple waitqueues for poll handling (eg one for read, one
+	 * (e.g. one for read, one for write). Setup a separate io_poll_iocb
-	 * for write). Setup a separate io_poll_iocb if this happens.
+	 * if this happens.
 	 */
-	if (unlikely(poll->head)) {
+	if (unlikely(pt->nr_entries)) {
 		struct io_poll_iocb *poll_one = poll;
 		/* already have a 2nd entry, fail a third attempt */
 		*poll_ptr = poll;
 	}
-	pt->error = 0;
+	pt->nr_entries++;
 	poll->head = head;
 	if (poll->events & EPOLLEXCLUSIVE)
 	ipt->pt._key = mask;
 	ipt->req = req;
-	ipt->error = -EINVAL;
+	ipt->error = 0;
+	ipt->nr_entries = 0;
 	mask = vfs_poll(req->file, &ipt->pt) & poll->events;
+	if (unlikely(!ipt->nr_entries) && !ipt->error)
+		ipt->error = -EINVAL;
 	spin_lock_irq(&ctx->completion_lock);
+	if (ipt->error || (mask && (poll->events & EPOLLONESHOT)))
+		io_poll_remove_double(req);
 	if (likely(poll->head)) {
 		spin_lock(&poll->head->lock);
 		if (unlikely(list_empty(&poll->wait.entry))) {
 	ret = __io_arm_poll_handler(req, &apoll->poll, &ipt, mask,
 					io_async_wake);
 	if (ret || ipt.error) {
-		io_poll_remove_double(req);
 		spin_unlock_irq(&ctx->completion_lock);
 		if (ret)
 			return IO_APOLL_READY;
 		mutex_lock(&ctx->uring_lock);
 		if (!list_empty(&ctx->iopoll_list))
-			io_do_iopoll(ctx, &nr_events, 0);
+			io_do_iopoll(ctx, &nr_events, 0, true);
 		/*
 		 * Don't submit if refs are dying, good for io_uring_register(),
 	struct io_wq_data data;
 	unsigned int concurrency;
+	mutex_lock(&ctx->uring_lock);
 	hash = ctx->hash_map;
 	if (!hash) {
 		hash = kzalloc(sizeof(*hash), GFP_KERNEL);
-		if (!hash)
+		if (!hash) {
+			mutex_unlock(&ctx->uring_lock);
 			return ERR_PTR(-ENOMEM);
+		}
 		refcount_set(&hash->refs, 1);
 		init_waitqueue_head(&hash->wait);
 		ctx->hash_map = hash;
 	}
+	mutex_unlock(&ctx->uring_lock);
 	data.hash = hash;
 	data.task = task;
 		f = fdget(p->wq_fd);
 		if (!f.file)
 			return -ENXIO;
-		fdput(f);
+		if (f.file->f_op != &io_uring_fops) {
-		if (f.file->f_op != &io_uring_fops)
+			fdput(f);
 			return -EINVAL;
+		}
+		fdput(f);
 	}
 	if (ctx->flags & IORING_SETUP_SQPOLL) {
 		struct task_struct *tsk;

fs/ocfs2/file.c+62−41

 	}
 }
+/*
+ * zero out partial blocks of one cluster.
+ *
+ * start: file offset where zero starts, will be made upper block aligned.
+ * len: it will be trimmed to the end of current cluster if "start + len"
+ *      is bigger than it.
+ */
+static int ocfs2_zeroout_partial_cluster(struct inode *inode,
+					u64 start, u64 len)
+{
+	int ret;
+	u64 start_block, end_block, nr_blocks;
+	u64 p_block, offset;
+	u32 cluster, p_cluster, nr_clusters;
+	struct super_block *sb = inode->i_sb;
+	u64 end = ocfs2_align_bytes_to_clusters(sb, start);
+	if (start + len < end)
+		end = start + len;
+	start_block = ocfs2_blocks_for_bytes(sb, start);
+	end_block = ocfs2_blocks_for_bytes(sb, end);
+	nr_blocks = end_block - start_block;
+	if (!nr_blocks)
+		return 0;
+	cluster = ocfs2_bytes_to_clusters(sb, start);
+	ret = ocfs2_get_clusters(inode, cluster, &p_cluster,
+				&nr_clusters, NULL);
+	if (ret)
+		return ret;
+	if (!p_cluster)
+		return 0;
+	offset = start_block - ocfs2_clusters_to_blocks(sb, cluster);
+	p_block = ocfs2_clusters_to_blocks(sb, p_cluster) + offset;
+	return sb_issue_zeroout(sb, p_block, nr_blocks, GFP_NOFS);
+}
 static int ocfs2_zero_partial_clusters(struct inode *inode,
 				       u64 start, u64 len)
 {
 	struct ocfs2_super *osb = OCFS2_SB(inode->i_sb);
 	unsigned int csize = osb->s_clustersize;
 	handle_t *handle;
+	loff_t isize = i_size_read(inode);
 	/*
 	 * The "start" and "end" values are NOT necessarily part of
 	if ((start & (csize - 1)) == 0 && (end & (csize - 1)) == 0)
 		goto out;
+	/* No page cache for EOF blocks, issue zero out to disk. */
+	if (end > isize) {
+		/*
+		 * zeroout eof blocks in last cluster starting from
+		 * "isize" even "start" > "isize" because it is
+		 * complicated to zeroout just at "start" as "start"
+		 * may be not aligned with block size, buffer write
+		 * would be required to do that, but out of eof buffer
+		 * write is not supported.
+		 */
+		ret = ocfs2_zeroout_partial_cluster(inode, isize,
+					end - isize);
+		if (ret) {
+			mlog_errno(ret);
+			goto out;
+		}
+		if (start >= isize)
+			goto out;
+		end = isize;
+	}
 	handle = ocfs2_start_trans(osb, OCFS2_INODE_UPDATE_CREDITS);
 	if (IS_ERR(handle)) {
 		ret = PTR_ERR(handle);
 	return ret;
 }
-/*
- * zero out partial blocks of one cluster.
- *
- * start: file offset where zero starts, will be made upper block aligned.
- * len: it will be trimmed to the end of current cluster if "start + len"
- *      is bigger than it.
- */
-static int ocfs2_zeroout_partial_cluster(struct inode *inode,
-					u64 start, u64 len)
-{
-	int ret;
-	u64 start_block, end_block, nr_blocks;
-	u64 p_block, offset;
-	u32 cluster, p_cluster, nr_clusters;
-	struct super_block *sb = inode->i_sb;
-	u64 end = ocfs2_align_bytes_to_clusters(sb, start);
-	if (start + len < end)
-		end = start + len;
-	start_block = ocfs2_blocks_for_bytes(sb, start);
-	end_block = ocfs2_blocks_for_bytes(sb, end);
-	nr_blocks = end_block - start_block;
-	if (!nr_blocks)
-		return 0;
-	cluster = ocfs2_bytes_to_clusters(sb, start);
-	ret = ocfs2_get_clusters(inode, cluster, &p_cluster,
-				&nr_clusters, NULL);
-	if (ret)
-		return ret;
-	if (!p_cluster)
-		return 0;
-	offset = start_block - ocfs2_clusters_to_blocks(sb, cluster);
-	p_block = ocfs2_clusters_to_blocks(sb, p_cluster) + offset;
-	return sb_issue_zeroout(sb, p_block, nr_blocks, GFP_NOFS);
-}
 /*
  * Parts of this function taken from xfs_change_file_space()
  */
 		goto out_inode_unlock;
 	}
-	orig_isize = i_size_read(inode);
 	switch (sr->l_whence) {
 	case 0: /*SEEK_SET*/
 		break;
 		sr->l_start += f_pos;
 		break;
 	case 2: /*SEEK_END*/
-		sr->l_start += orig_isize;
+		sr->l_start += i_size_read(inode);
 		break;
 	default:
 		ret = -EINVAL;
 		ret = -EINVAL;
 	}
+	orig_isize = i_size_read(inode);
 	/* zeroout eof blocks in the cluster. */
 	if (!ret && change_size && orig_isize < size) {
 		ret = ocfs2_zeroout_partial_cluster(inode, orig_isize,

fs/pipe.c+5−5

@@ -429,20 +429,20 @@ pipe_write(struct kiocb iocb, struct iov_iter from) · 428 unmodified lines
429	#endif	429	#endif
430		430
431	/*	431	/*
432	* Only wake up if the pipe started out empty, since	432	* Epoll nonsensically wants a wakeup whether the pipe
433	* otherwise there should be no readers waiting.	433	* was already empty or not.
434	*	434	*
435	* If it wasn't empty we try to merge new data into	435	* If it wasn't empty we try to merge new data into
436	* the last buffer.	436	* the last buffer.
437	*	437	*
438	* That naturally merges small writes, but it also	438	* That naturally merges small writes, but it also
439	* page-aligs the rest of the writes for large writes	439	* page-aligns the rest of the writes for large writes
440	* spanning multiple pages.	440	* spanning multiple pages.
441	*/	441	*/
442	head = pipe->head;	442	head = pipe->head;
443	was_empty = pipe_empty(head, pipe->tail);	443	was_empty = true;
444	chars = total_len & (PAGE_SIZE-1);	444	chars = total_len & (PAGE_SIZE-1);
445	if (chars && !was_empty) {	445	if (chars && !pipe_empty(head, pipe->tail)) {
446	unsigned int mask = pipe->ring_size - 1;	446	unsigned int mask = pipe->ring_size - 1;
447	struct pipe_buffer *buf = &pipe->bufs[(head - 1) & mask];	447	struct pipe_buffer *buf = &pipe->bufs[(head - 1) & mask];
448	int offset = buf->offset + buf->len;	448	int offset = buf->offset + buf->len;

fs/reiserfs/stree.c+26−5

@@ -387,6 +387,24 @@ void pathrelse(struct treepath *search_path) · 386 unmodified lines
387	search_path->path_length = ILLEGAL_PATH_ELEMENT_OFFSET;	387	search_path->path_length = ILLEGAL_PATH_ELEMENT_OFFSET;
388	}	388	}
389		389
		390	static int has_valid_deh_location(struct buffer_head bh, struct item_head ih)
		391	{
		392	struct reiserfs_de_head *deh;
		393	int i;
		394
		395	deh = B_I_DEH(bh, ih);
		396	for (i = 0; i < ih_entry_count(ih); i++) {
		397	if (deh_location(&deh[i]) > ih_item_len(ih)) {
		398	reiserfs_warning(NULL, "reiserfs-5094",
		399	"directory entry location seems wrong %h",
		400	&deh[i]);
		401	return 0;
		402	}
		403	}
		404
		405	return 1;
		406	}
		407
390	static int is_leaf(char buf, int blocksize, struct buffer_head bh)	408	static int is_leaf(char buf, int blocksize, struct buffer_head bh)
391	{	409	{
392	struct block_head *blkh;	410	struct block_head *blkh;
@@ -454,11 +472,14 @@ static int is_leaf(char buf, int blocksize, struct buffer_head bh) · 61 unmodified lines
454	"(second one): %h", ih);	472	"(second one): %h", ih);
455	return 0;	473	return 0;
456	}	474	}
457	if (is_direntry_le_ih(ih) && (ih_item_len(ih) < (ih_entry_count(ih) * IH_SIZE))) {	475	if (is_direntry_le_ih(ih)) {
458	reiserfs_warning(NULL, "reiserfs-5093",	476	if (ih_item_len(ih) < (ih_entry_count(ih) * IH_SIZE)) {
459	"item entry count seems wrong %h",	477	reiserfs_warning(NULL, "reiserfs-5093",
460	ih);	478	"item entry count seems wrong %h",
461	return 0;	479	ih);
		480	return 0;
		481	}
		482	return has_valid_deh_location(bh, ih);
462	}	483	}
463	prev_location = ih_location(ih);	484	prev_location = ih_location(ih);
464	}	485	}

fs/reiserfs/super.c+8−0

@@ -2082,6 +2082,14 @@ static int reiserfs_fill_super(struct super_block s, void data, int silent) · 2081 unmodified lines
2082	unlock_new_inode(root_inode);	2082	unlock_new_inode(root_inode);
2083	}	2083	}
2084		2084
		2085	if (!S_ISDIR(root_inode->i_mode) \|\| !inode_get_bytes(root_inode) \|\|
		2086	!root_inode->i_size) {
		2087	SWARN(silent, s, "", "corrupt root inode, run fsck");
		2088	iput(root_inode);
		2089	errval = -EUCLEAN;
		2090	goto error;
		2091	}
		2092
2085	s->s_root = d_make_root(root_inode);	2093	s->s_root = d_make_root(root_inode);
2086	if (!s->s_root)	2094	if (!s->s_root)
2087	goto error;	2095	goto error;

fs/seq_file.c+3−0

@@ -32,6 +32,9 @@ static void seq_set_overflow(struct seq_file *m) · 31 unmodified lines
32		32
33	static void *seq_buf_alloc(unsigned long size)	33	static void *seq_buf_alloc(unsigned long size)
34	{	34	{
		35	if (unlikely(size > MAX_RW_COUNT))
		36	return NULL;
		37
35	return kvmalloc(size, GFP_KERNEL_ACCOUNT);	38	return kvmalloc(size, GFP_KERNEL_ACCOUNT);
36	}	39	}
37		40

fs/userfaultfd.c+12−14

 }
 static __always_inline int validate_range(struct mm_struct *mm,
-					  __u64 *start, __u64 len)
+					  __u64 start, __u64 len)
 {
 	__u64 task_size = mm->task_size;
-	*start = untagged_addr(*start);
+	if (start & ~PAGE_MASK)
-	if (*start & ~PAGE_MASK)
 		return -EINVAL;
 	if (len & ~PAGE_MASK)
 		return -EINVAL;
 	if (!len)
 		return -EINVAL;
-	if (*start < mmap_min_addr)
+	if (start < mmap_min_addr)
 		return -EINVAL;
-	if (*start >= task_size)
+	if (start >= task_size)
 		return -EINVAL;
-	if (len > task_size - *start)
+	if (len > task_size - start)
 		return -EINVAL;
 	return 0;
 }
 		vm_flags |= VM_UFFD_MINOR;
 	}
-	ret = validate_range(mm, &uffdio_register.range.start,
+	ret = validate_range(mm, uffdio_register.range.start,
 			     uffdio_register.range.len);
 	if (ret)
 		goto out;
 	if (copy_from_user(&uffdio_unregister, buf, sizeof(uffdio_unregister)))
 		goto out;
-	ret = validate_range(mm, &uffdio_unregister.start,
+	ret = validate_range(mm, uffdio_unregister.start,
 			     uffdio_unregister.len);
 	if (ret)
 		goto out;
 	if (copy_from_user(&uffdio_wake, buf, sizeof(uffdio_wake)))
 		goto out;
-	ret = validate_range(ctx->mm, &uffdio_wake.start, uffdio_wake.len);
+	ret = validate_range(ctx->mm, uffdio_wake.start, uffdio_wake.len);
 	if (ret)
 		goto out;
 			   sizeof(uffdio_copy)-sizeof(__s64)))
 		goto out;
-	ret = validate_range(ctx->mm, &uffdio_copy.dst, uffdio_copy.len);
+	ret = validate_range(ctx->mm, uffdio_copy.dst, uffdio_copy.len);
 	if (ret)
 		goto out;
 	/*
 			   sizeof(uffdio_zeropage)-sizeof(__s64)))
 		goto out;
-	ret = validate_range(ctx->mm, &uffdio_zeropage.range.start,
+	ret = validate_range(ctx->mm, uffdio_zeropage.range.start,
 			     uffdio_zeropage.range.len);
 	if (ret)
 		goto out;
 			   sizeof(struct uffdio_writeprotect)))
 		return -EFAULT;
-	ret = validate_range(ctx->mm, &uffdio_wp.range.start,
+	ret = validate_range(ctx->mm, uffdio_wp.range.start,
 			     uffdio_wp.range.len);
 	if (ret)
 		return ret;
 			   sizeof(uffdio_continue) - (sizeof(__s64))))
 		goto out;
-	ret = validate_range(ctx->mm, &uffdio_continue.range.start,
+	ret = validate_range(ctx->mm, uffdio_continue.range.start,
 			     uffdio_continue.range.len);
 	if (ret)
 		goto out;

fs/xfs/libxfs/xfs_log_format.h+10−1

@@ -411,7 +411,16 @@ struct xfs_log_dinode { · 410 unmodified lines
411	/* start of the extended dinode, writable fields */	411	/* start of the extended dinode, writable fields */
412	uint32_t di_crc; /* CRC of the inode */	412	uint32_t di_crc; /* CRC of the inode */
413	uint64_t di_changecount; /* number of attribute changes */	413	uint64_t di_changecount; /* number of attribute changes */
414	xfs_lsn_t di_lsn; /* flush sequence */	414
		415	/*
		416	* The LSN we write to this field during formatting is not a reflection
		417	* of the current on-disk LSN. It should never be used for recovery
		418	* sequencing, nor should it be recovered into the on-disk inode at all.
		419	* See xlog_recover_inode_commit_pass2() and xfs_log_dinode_to_disk()
		420	* for details.
		421	*/
		422	xfs_lsn_t di_lsn;
		423
415	uint64_t di_flags2; /* more random flags */	424	uint64_t di_flags2; /* more random flags */
416	uint32_t di_cowextsize; /* basic cow extent size for file */	425	uint32_t di_cowextsize; /* basic cow extent size for file */
417	uint8_t di_pad2[12]; /* more padding for future expansion */	426	uint8_t di_pad2[12]; /* more padding for future expansion */

fs/xfs/xfs_buf_item_recover.c+13−2

 static xfs_lsn_t
 xlog_recover_get_buf_lsn(
 	struct xfs_mount	*mp,
-	struct xfs_buf		*bp)
+	struct xfs_buf		*bp,
+	struct xfs_buf_log_format *buf_f)
 {
 	uint32_t		magic32;
 	uint16_t		magic16;
 	void			*blk = bp->b_addr;
 	uuid_t			*uuid;
 	xfs_lsn_t		lsn = -1;
+	uint16_t		blft;
 	/* v4 filesystems always recover immediately */
 	if (!xfs_sb_version_hascrc(&mp->m_sb))
 		goto recover_immediately;
+	/*
+	 * realtime bitmap and summary file blocks do not have magic numbers or
+	 * UUIDs, so we must recover them immediately.
+	 */
+	blft = xfs_blft_from_flags(buf_f);
+	if (blft == XFS_BLFT_RTBITMAP_BUF || blft == XFS_BLFT_RTSUMMARY_BUF)
+		goto recover_immediately;
 	magic32 = be32_to_cpu(*(__be32 *)blk);
 	switch (magic32) {
 	case XFS_ABTB_CRC_MAGIC:
 	switch (magicda) {
 	case XFS_DIR3_LEAF1_MAGIC:
 	case XFS_DIR3_LEAFN_MAGIC:
+	case XFS_ATTR3_LEAF_MAGIC:
 	case XFS_DA3_NODE_MAGIC:
 		lsn = be64_to_cpu(((struct xfs_da3_blkinfo *)blk)->lsn);
 		uuid = &((struct xfs_da3_blkinfo *)blk)->uuid;
 	 * the verifier will be reset to match whatever recover turns that
 	 * buffer into.
 	 */
-	lsn = xlog_recover_get_buf_lsn(mp, bp);
+	lsn = xlog_recover_get_buf_lsn(mp, bp, buf_f);
 	if (lsn && lsn != -1 && XFS_LSN_CMP(lsn, current_lsn) >= 0) {
 		trace_xfs_log_recover_buf_skip(log, buf_f);
 		xlog_recover_validate_buf_type(mp, bp, buf_f, NULLCOMMITLSN);

fs/xfs/xfs_inode_item_recover.c+29−10

 STATIC void
 xfs_log_dinode_to_disk(
 	struct xfs_log_dinode	*from,
-	struct xfs_dinode	*to)
+	struct xfs_dinode	*to,
+	xfs_lsn_t		lsn)
 {
 	to->di_magic = cpu_to_be16(from->di_magic);
 	to->di_mode = cpu_to_be16(from->di_mode);
 		to->di_flags2 = cpu_to_be64(from->di_flags2);
 		to->di_cowextsize = cpu_to_be32(from->di_cowextsize);
 		to->di_ino = cpu_to_be64(from->di_ino);
-		to->di_lsn = cpu_to_be64(from->di_lsn);
+		to->di_lsn = cpu_to_be64(lsn);
 		memcpy(to->di_pad2, from->di_pad2, sizeof(to->di_pad2));
 		uuid_copy(&to->di_uuid, &from->di_uuid);
 		to->di_flushiter = 0;
 	}
 	/*
-	 * If the inode has an LSN in it, recover the inode only if it's less
+	 * If the inode has an LSN in it, recover the inode only if the on-disk
-	 * than the lsn of the transaction we are replaying. Note: we still
+	 * inode's LSN is older than the lsn of the transaction we are
-	 * need to replay an owner change even though the inode is more recent
+	 * replaying. We can have multiple checkpoints with the same start LSN,
-	 * than the transaction as there is no guarantee that all the btree
+	 * so the current LSN being equal to the on-disk LSN doesn't necessarily
-	 * blocks are more recent than this transaction, too.
+	 * mean that the on-disk inode is more recent than the change being
+	 * replayed.
+	 *
+	 * We must check the current_lsn against the on-disk inode
+	 * here because the we can't trust the log dinode to contain a valid LSN
+	 * (see comment below before replaying the log dinode for details).
+	 *
+	 * Note: we still need to replay an owner change even though the inode
+	 * is more recent than the transaction as there is no guarantee that all
+	 * the btree blocks are more recent than this transaction, too.
 	 */
 	if (dip->di_version >= 3) {
 		xfs_lsn_t	lsn = be64_to_cpu(dip->di_lsn);
-		if (lsn && lsn != -1 && XFS_LSN_CMP(lsn, current_lsn) >= 0) {
+		if (lsn && lsn != -1 && XFS_LSN_CMP(lsn, current_lsn) > 0) {
 			trace_xfs_log_recover_inode_skip(log, in_f);
 			error = 0;
 			goto out_owner_change;
 		goto out_release;
 	}
-	/* recover the log dinode inode into the on disk inode */
+	/*
-	xfs_log_dinode_to_disk(ldip, dip);
+	 * Recover the log dinode inode into the on disk inode.
+	 *
+	 * The LSN in the log dinode is garbage - it can be zero or reflect
+	 * stale in-memory runtime state that isn't coherent with the changes
+	 * logged in this transaction or the changes written to the on-disk
+	 * inode.  Hence we write the current lSN into the inode because that
+	 * matches what xfs_iflush() would write inode the inode when flushing
+	 * the changes in this transaction.
+	 */
+	xfs_log_dinode_to_disk(ldip, dip, current_lsn);
 	fields = in_f->ilf_fields;
 	if (fields & XFS_ILOG_DEV)

fs/xfs/xfs_log.c+165−86

@@ -78,13 +78,12 @@ xlog_verify_iclog( · 77 unmodified lines
78	STATIC void	78	STATIC void
79	xlog_verify_tail_lsn(	79	xlog_verify_tail_lsn(
80	struct xlog *log,	80	struct xlog *log,
81	struct xlog_in_core *iclog,	81	struct xlog_in_core *iclog);
82	xfs_lsn_t tail_lsn);
83	#else	82	#else
84	#define xlog_verify_dest_ptr(a,b)	83	#define xlog_verify_dest_ptr(a,b)
85	#define xlog_verify_grant_tail(a)	84	#define xlog_verify_grant_tail(a)
86	#define xlog_verify_iclog(a,b,c)	85	#define xlog_verify_iclog(a,b,c)
87	#define xlog_verify_tail_lsn(a,b,c)	86	#define xlog_verify_tail_lsn(a,b)
88	#endif	87	#endif
89		88
90	STATIC int	89	STATIC int
@@ -487,51 +486,80 @@ out_error: · 396 unmodified lines
487	return error;	486	return error;
488	}	487	}
489		488
490	static bool
491	__xlog_state_release_iclog(
492	struct xlog *log,
493	struct xlog_in_core *iclog)
494	{
495	lockdep_assert_held(&log->l_icloglock);
496
497	if (iclog->ic_state == XLOG_STATE_WANT_SYNC) {
498	/* update tail before writing to iclog */
499	xfs_lsn_t tail_lsn = xlog_assign_tail_lsn(log->l_mp);
500
501	iclog->ic_state = XLOG_STATE_SYNCING;
502	iclog->ic_header.h_tail_lsn = cpu_to_be64(tail_lsn);
503	xlog_verify_tail_lsn(log, iclog, tail_lsn);
504	/* cycle incremented when incrementing curr_block */
505	trace_xlog_iclog_syncing(iclog, _RET_IP_);
506	return true;
507	}
508
509	ASSERT(iclog->ic_state == XLOG_STATE_ACTIVE);
510	return false;
511	}
512
513	/*	489	/*
514	* Flush iclog to disk if this is the last reference to the given iclog and the	490	* Flush iclog to disk if this is the last reference to the given iclog and the
515	* it is in the WANT_SYNC state.	491	* it is in the WANT_SYNC state.
		492	*
		493	* If the caller passes in a non-zero @old_tail_lsn and the current log tail
		494	* does not match, there may be metadata on disk that must be persisted before
		495	* this iclog is written. To satisfy that requirement, set the
		496	* XLOG_ICL_NEED_FLUSH flag as a condition for writing this iclog with the new
		497	* log tail value.
		498	*
		499	* If XLOG_ICL_NEED_FUA is already set on the iclog, we need to ensure that the
		500	* log tail is updated correctly. NEED_FUA indicates that the iclog will be
		501	* written to stable storage, and implies that a commit record is contained
		502	* within the iclog. We need to ensure that the log tail does not move beyond
		503	* the tail that the first commit record in the iclog ordered against, otherwise
		504	* correct recovery of that checkpoint becomes dependent on future operations
		505	* performed on this iclog.
		506	*
		507	* Hence if NEED_FUA is set and the current iclog tail lsn is empty, write the
		508	* current tail into iclog. Once the iclog tail is set, future operations must
		509	* not modify it, otherwise they potentially violate ordering constraints for
		510	* the checkpoint commit that wrote the initial tail lsn value. The tail lsn in
		511	* the iclog will get zeroed on activation of the iclog after sync, so we
		512	* always capture the tail lsn on the iclog on the first NEED_FUA release
		513	* regardless of the number of active reference counts on this iclog.
516	*/	514	*/
		515
517	int	516	int
518	xlog_state_release_iclog(	517	xlog_state_release_iclog(
519	struct xlog *log,	518	struct xlog *log,
520	struct xlog_in_core *iclog)	519	struct xlog_in_core *iclog,
		520	xfs_lsn_t old_tail_lsn)
521	{	521	{
		522	xfs_lsn_t tail_lsn;
522	lockdep_assert_held(&log->l_icloglock);	523	lockdep_assert_held(&log->l_icloglock);
523		524
524	trace_xlog_iclog_release(iclog, _RET_IP_);	525	trace_xlog_iclog_release(iclog, _RET_IP_);
525	if (iclog->ic_state == XLOG_STATE_IOERROR)	526	if (iclog->ic_state == XLOG_STATE_IOERROR)
526	return -EIO;	527	return -EIO;
527		528
528	if (atomic_dec_and_test(&iclog->ic_refcnt) &&	529	/*
529	__xlog_state_release_iclog(log, iclog)) {	530	* Grabbing the current log tail needs to be atomic w.r.t. the writing
530	spin_unlock(&log->l_icloglock);	531	* of the tail LSN into the iclog so we guarantee that the log tail does
531	xlog_sync(log, iclog);	532	* not move between deciding if a cache flush is required and writing
532	spin_lock(&log->l_icloglock);	533	* the LSN into the iclog below.
		534	*/
		535	if (old_tail_lsn \|\| iclog->ic_state == XLOG_STATE_WANT_SYNC) {
		536	tail_lsn = xlog_assign_tail_lsn(log->l_mp);
		537
		538	if (old_tail_lsn && tail_lsn != old_tail_lsn)
		539	iclog->ic_flags \|= XLOG_ICL_NEED_FLUSH;
		540
		541	if ((iclog->ic_flags & XLOG_ICL_NEED_FUA) &&
		542	!iclog->ic_header.h_tail_lsn)
		543	iclog->ic_header.h_tail_lsn = cpu_to_be64(tail_lsn);
533	}	544	}
534		545
		546	if (!atomic_dec_and_test(&iclog->ic_refcnt))
		547	return 0;
		548
		549	if (iclog->ic_state != XLOG_STATE_WANT_SYNC) {
		550	ASSERT(iclog->ic_state == XLOG_STATE_ACTIVE);
		551	return 0;
		552	}
		553
		554	iclog->ic_state = XLOG_STATE_SYNCING;
		555	if (!iclog->ic_header.h_tail_lsn)
		556	iclog->ic_header.h_tail_lsn = cpu_to_be64(tail_lsn);
		557	xlog_verify_tail_lsn(log, iclog);
		558	trace_xlog_iclog_syncing(iclog, _RET_IP_);
		559
		560	spin_unlock(&log->l_icloglock);
		561	xlog_sync(log, iclog);
		562	spin_lock(&log->l_icloglock);
535	return 0;	563	return 0;
536	}	564	}
537		565
@@ -773,6 +801,21 @@ xfs_log_mount_cancel( · 235 unmodified lines
773	xfs_log_unmount(mp);	801	xfs_log_unmount(mp);
774	}	802	}
775		803
		804	/*
		805	* Flush out the iclog to disk ensuring that device caches are flushed and
		806	* the iclog hits stable storage before any completion waiters are woken.
		807	*/
		808	static inline int
		809	xlog_force_iclog(
		810	struct xlog_in_core *iclog)
		811	{
		812	atomic_inc(&iclog->ic_refcnt);
		813	iclog->ic_flags \|= XLOG_ICL_NEED_FLUSH \| XLOG_ICL_NEED_FUA;
		814	if (iclog->ic_state == XLOG_STATE_ACTIVE)
		815	xlog_state_switch_iclogs(iclog->ic_log, iclog, 0);
		816	return xlog_state_release_iclog(iclog->ic_log, iclog, 0);
		817	}
		818
776	/*	819	/*
777	* Wait for the iclog and all prior iclogs to be written disk as required by the	820	* Wait for the iclog and all prior iclogs to be written disk as required by the
778	* log force state machine. Waiting on ic_force_wait ensures iclog completions	821	* log force state machine. Waiting on ic_force_wait ensures iclog completions
@@ -827,13 +870,6 @@ xlog_write_unmount_record( · 48 unmodified lines
827	/* account for space used by record data */	870	/* account for space used by record data */
828	ticket->t_curr_res -= sizeof(ulf);	871	ticket->t_curr_res -= sizeof(ulf);
829		872
830	/*
831	* For external log devices, we need to flush the data device cache
832	* first to ensure all metadata writeback is on stable storage before we
833	* stamp the tail LSN into the unmount record.
834	*/
835	if (log->l_targ != log->l_mp->m_ddev_targp)
836	blkdev_issue_flush(log->l_targ->bt_bdev);
837	return xlog_write(log, &vec, ticket, NULL, NULL, XLOG_UNMOUNT_TRANS);	873	return xlog_write(log, &vec, ticket, NULL, NULL, XLOG_UNMOUNT_TRANS);
838	}	874	}
839		875
@@ -865,18 +901,7 @@ out_err: · 25 unmodified lines
865		901
866	spin_lock(&log->l_icloglock);	902	spin_lock(&log->l_icloglock);
867	iclog = log->l_iclog;	903	iclog = log->l_iclog;
868	atomic_inc(&iclog->ic_refcnt);	904	error = xlog_force_iclog(iclog);
869	if (iclog->ic_state == XLOG_STATE_ACTIVE)
870	xlog_state_switch_iclogs(log, iclog, 0);
871	else
872	ASSERT(iclog->ic_state == XLOG_STATE_WANT_SYNC \|\|
873	iclog->ic_state == XLOG_STATE_IOERROR);
874	/*
875	* Ensure the journal is fully flushed and on stable storage once the
876	* iclog containing the unmount record is written.
877	*/
878	iclog->ic_flags \|= (XLOG_ICL_NEED_FLUSH \| XLOG_ICL_NEED_FUA);
879	error = xlog_state_release_iclog(log, iclog);
880	xlog_wait_on_iclog(iclog);	905	xlog_wait_on_iclog(iclog);
881		906
882	if (tic) {	907	if (tic) {
@@ -1796,10 +1821,20 @@ xlog_write_iclog( · 913 unmodified lines
1796	* metadata writeback and causing priority inversions.	1821	* metadata writeback and causing priority inversions.
1797	*/	1822	*/
1798	iclog->ic_bio.bi_opf = REQ_OP_WRITE \| REQ_META \| REQ_SYNC \| REQ_IDLE;	1823	iclog->ic_bio.bi_opf = REQ_OP_WRITE \| REQ_META \| REQ_SYNC \| REQ_IDLE;
1799	if (iclog->ic_flags & XLOG_ICL_NEED_FLUSH)	1824	if (iclog->ic_flags & XLOG_ICL_NEED_FLUSH) {
1800	iclog->ic_bio.bi_opf \|= REQ_PREFLUSH;	1825	iclog->ic_bio.bi_opf \|= REQ_PREFLUSH;
		1826	/*
		1827	* For external log devices, we also need to flush the data
		1828	* device cache first to ensure all metadata writeback covered
		1829	* by the LSN in this iclog is on stable storage. This is slow,
		1830	* but it must complete before we issue the external log IO.
		1831	*/
		1832	if (log->l_targ != log->l_mp->m_ddev_targp)
		1833	blkdev_issue_flush(log->l_mp->m_ddev_targp->bt_bdev);
		1834	}
1801	if (iclog->ic_flags & XLOG_ICL_NEED_FUA)	1835	if (iclog->ic_flags & XLOG_ICL_NEED_FUA)
1802	iclog->ic_bio.bi_opf \|= REQ_FUA;	1836	iclog->ic_bio.bi_opf \|= REQ_FUA;
		1837
1803	iclog->ic_flags &= ~(XLOG_ICL_NEED_FLUSH \| XLOG_ICL_NEED_FUA);	1838	iclog->ic_flags &= ~(XLOG_ICL_NEED_FLUSH \| XLOG_ICL_NEED_FUA);
1804		1839
1805	if (xlog_map_iclog_data(&iclog->ic_bio, iclog->ic_data, count)) {	1840	if (xlog_map_iclog_data(&iclog->ic_bio, iclog->ic_data, count)) {
@@ -2310,7 +2345,7 @@ xlog_write_copy_finish( · 504 unmodified lines
2310	return 0;	2345	return 0;
2311		2346
2312	release_iclog:	2347	release_iclog:
2313	error = xlog_state_release_iclog(log, iclog);	2348	error = xlog_state_release_iclog(log, iclog, 0);
2314	spin_unlock(&log->l_icloglock);	2349	spin_unlock(&log->l_icloglock);
2315	return error;	2350	return error;
2316	}	2351	}
@@ -2529,7 +2564,7 @@ next_lv: · 212 unmodified lines
2529	ASSERT(optype & XLOG_COMMIT_TRANS);	2564	ASSERT(optype & XLOG_COMMIT_TRANS);
2530	*commit_iclog = iclog;	2565	*commit_iclog = iclog;
2531	} else {	2566	} else {
2532	error = xlog_state_release_iclog(log, iclog);	2567	error = xlog_state_release_iclog(log, iclog, 0);
2533	}	2568	}
2534	spin_unlock(&log->l_icloglock);	2569	spin_unlock(&log->l_icloglock);
2535		2570
@@ -2567,6 +2602,7 @@ xlog_state_activate_iclog( · 31 unmodified lines
2567	memset(iclog->ic_header.h_cycle_data, 0,	2602	memset(iclog->ic_header.h_cycle_data, 0,
2568	sizeof(iclog->ic_header.h_cycle_data));	2603	sizeof(iclog->ic_header.h_cycle_data));
2569	iclog->ic_header.h_lsn = 0;	2604	iclog->ic_header.h_lsn = 0;
		2605	iclog->ic_header.h_tail_lsn = 0;
2570	}	2606	}
2571		2607
2572	/*	2608	/*
@@ -2967,7 +3003,7 @@ restart: · 394 unmodified lines
2967	* reference to the iclog.	3003	* reference to the iclog.
2968	*/	3004	*/
2969	if (!atomic_add_unless(&iclog->ic_refcnt, -1, 1))	3005	if (!atomic_add_unless(&iclog->ic_refcnt, -1, 1))
2970	error = xlog_state_release_iclog(log, iclog);	3006	error = xlog_state_release_iclog(log, iclog, 0);
2971	spin_unlock(&log->l_icloglock);	3007	spin_unlock(&log->l_icloglock);
2972	if (error)	3008	if (error)
2973	return error;	3009	return error;
@@ -3131,6 +3167,35 @@ xlog_state_switch_iclogs( · 157 unmodified lines
3131	log->l_iclog = iclog->ic_next;	3167	log->l_iclog = iclog->ic_next;
3132	}	3168	}
3133		3169
		3170	/*
		3171	* Force the iclog to disk and check if the iclog has been completed before
		3172	* xlog_force_iclog() returns. This can happen on synchronous (e.g.
		3173	* pmem) or fast async storage because we drop the icloglock to issue the IO.
		3174	* If completion has already occurred, tell the caller so that it can avoid an
		3175	* unnecessary wait on the iclog.
		3176	*/
		3177	static int
		3178	xlog_force_and_check_iclog(
		3179	struct xlog_in_core *iclog,
		3180	bool *completed)
		3181	{
		3182	xfs_lsn_t lsn = be64_to_cpu(iclog->ic_header.h_lsn);
		3183	int error;
		3184
		3185	*completed = false;
		3186	error = xlog_force_iclog(iclog);
		3187	if (error)
		3188	return error;
		3189
		3190	/*
		3191	* If the iclog has already been completed and reused the header LSN
		3192	* will have been rewritten by completion
		3193	*/
		3194	if (be64_to_cpu(iclog->ic_header.h_lsn) != lsn)
		3195	*completed = true;
		3196	return 0;
		3197	}
		3198
3134	/*	3199	/*
3135	* Write out all data in the in-core log as of this exact moment in time.	3200	* Write out all data in the in-core log as of this exact moment in time.
3136	*	3201	*
@@ -3165,7 +3230,6 @@ xfs_log_force( · 28 unmodified lines
3165	{	3230	{
3166	struct xlog *log = mp->m_log;	3231	struct xlog *log = mp->m_log;
3167	struct xlog_in_core *iclog;	3232	struct xlog_in_core *iclog;
3168	xfs_lsn_t lsn;
3169		3233
3170	XFS_STATS_INC(mp, xs_log_force);	3234	XFS_STATS_INC(mp, xs_log_force);
3171	trace_xfs_log_force(mp, 0, _RET_IP_);	3235	trace_xfs_log_force(mp, 0, _RET_IP_);
@@ -3193,39 +3257,33 @@ xfs_log_force( · 21 unmodified lines
3193	iclog = iclog->ic_prev;	3257	iclog = iclog->ic_prev;
3194	} else if (iclog->ic_state == XLOG_STATE_ACTIVE) {	3258	} else if (iclog->ic_state == XLOG_STATE_ACTIVE) {
3195	if (atomic_read(&iclog->ic_refcnt) == 0) {	3259	if (atomic_read(&iclog->ic_refcnt) == 0) {
3196	/*	3260	/* We have exclusive access to this iclog. */
3197	* We are the only one with access to this iclog.	3261	bool completed;
3198	*	3262
3199	* Flush it out now. There should be a roundoff of zero	3263	if (xlog_force_and_check_iclog(iclog, &completed))
3200	* to show that someone has already taken care of the
3201	* roundoff from the previous sync.
3202	*/
3203	atomic_inc(&iclog->ic_refcnt);
3204	lsn = be64_to_cpu(iclog->ic_header.h_lsn);
3205	xlog_state_switch_iclogs(log, iclog, 0);
3206	if (xlog_state_release_iclog(log, iclog))
3207	goto out_error;	3264	goto out_error;
3208		3265
3209	if (be64_to_cpu(iclog->ic_header.h_lsn) != lsn)	3266	if (completed)
3210	goto out_unlock;	3267	goto out_unlock;
3211	} else {	3268	} else {
3212	/*	3269	/*
3213	* Someone else is writing to this iclog.	3270	* Someone else is still writing to this iclog, so we
3214	*	3271	* need to ensure that when they release the iclog it
3215	* Use its call to flush out the data. However, the	3272	* gets synced immediately as we may be waiting on it.
3216	* other thread may not force out this LR, so we mark
3217	* it WANT_SYNC.
3218	*/	3273	*/
3219	xlog_state_switch_iclogs(log, iclog, 0);	3274	xlog_state_switch_iclogs(log, iclog, 0);
3220	}	3275	}
3221	} else {
3222	/*
3223	* If the head iclog is not active nor dirty, we just attach
3224	* ourselves to the head and go to sleep if necessary.
3225	*/
3226	;
3227	}	3276	}
3228		3277
		3278	/*
		3279	* The iclog we are about to wait on may contain the checkpoint pushed
		3280	* by the above xlog_cil_force() call, but it may not have been pushed
		3281	* to disk yet. Like the ACTIVE case above, we need to make sure caches
		3282	* are flushed when this iclog is written.
		3283	*/
		3284	if (iclog->ic_state == XLOG_STATE_WANT_SYNC)
		3285	iclog->ic_flags \|= XLOG_ICL_NEED_FLUSH \| XLOG_ICL_NEED_FUA;
		3286
3229	if (flags & XFS_LOG_SYNC)	3287	if (flags & XFS_LOG_SYNC)
3230	return xlog_wait_on_iclog(iclog);	3288	return xlog_wait_on_iclog(iclog);
3231	out_unlock:	3289	out_unlock:
@@ -3245,6 +3303,7 @@ xlog_force_lsn( · 13 unmodified lines
3245	bool already_slept)	3303	bool already_slept)
3246	{	3304	{
3247	struct xlog_in_core *iclog;	3305	struct xlog_in_core *iclog;
		3306	bool completed;
3248		3307
3249	spin_lock(&log->l_icloglock);	3308	spin_lock(&log->l_icloglock);
3250	iclog = log->l_iclog;	3309	iclog = log->l_iclog;
@@ -3258,7 +3317,8 @@ xlog_force_lsn( · 7 unmodified lines
3258	goto out_unlock;	3317	goto out_unlock;
3259	}	3318	}
3260		3319
3261	if (iclog->ic_state == XLOG_STATE_ACTIVE) {	3320	switch (iclog->ic_state) {
		3321	case XLOG_STATE_ACTIVE:
3262	/*	3322	/*
3263	* We sleep here if we haven't already slept (e.g. this is the	3323	* We sleep here if we haven't already slept (e.g. this is the
3264	* first time we've looked at the correct iclog buf) and the	3324	* first time we've looked at the correct iclog buf) and the
@@ -3281,12 +3341,31 @@ xlog_force_lsn( · 16 unmodified lines
3281	&log->l_icloglock);	3341	&log->l_icloglock);
3282	return -EAGAIN;	3342	return -EAGAIN;
3283	}	3343	}
3284	atomic_inc(&iclog->ic_refcnt);	3344	if (xlog_force_and_check_iclog(iclog, &completed))
3285	xlog_state_switch_iclogs(log, iclog, 0);
3286	if (xlog_state_release_iclog(log, iclog))
3287	goto out_error;	3345	goto out_error;
3288	if (log_flushed)	3346	if (log_flushed)
3289	*log_flushed = 1;	3347	*log_flushed = 1;
		3348	if (completed)
		3349	goto out_unlock;
		3350	break;
		3351	case XLOG_STATE_WANT_SYNC:
		3352	/*
		3353	* This iclog may contain the checkpoint pushed by the
		3354	* xlog_cil_force_seq() call, but there are other writers still
		3355	* accessing it so it hasn't been pushed to disk yet. Like the
		3356	* ACTIVE case above, we need to make sure caches are flushed
		3357	* when this iclog is written.
		3358	*/
		3359	iclog->ic_flags \|= XLOG_ICL_NEED_FLUSH \| XLOG_ICL_NEED_FUA;
		3360	break;
		3361	default:
		3362	/*
		3363	* The entire checkpoint was written by the CIL force and is on
		3364	* its way to disk already. It will be stable when it
		3365	* completes, so we don't need to manipulate caches here at all.
		3366	* We just need to wait for completion if necessary.
		3367	*/
		3368	break;
3290	}	3369	}
3291		3370
3292	if (flags & XFS_LOG_SYNC)	3371	if (flags & XFS_LOG_SYNC)
@@ -3559,10 +3638,10 @@ xlog_verify_grant_tail( · 266 unmodified lines
3559	STATIC void	3638	STATIC void
3560	xlog_verify_tail_lsn(	3639	xlog_verify_tail_lsn(
3561	struct xlog *log,	3640	struct xlog *log,
3562	struct xlog_in_core *iclog,	3641	struct xlog_in_core *iclog)
3563	xfs_lsn_t tail_lsn)
3564	{	3642	{
3565	int blocks;	3643	xfs_lsn_t tail_lsn = be64_to_cpu(iclog->ic_header.h_tail_lsn);
		3644	int blocks;
3566		3645
3567	if (CYCLE_LSN(tail_lsn) == log->l_prev_cycle) {	3646	if (CYCLE_LSN(tail_lsn) == log->l_prev_cycle) {
3568	blocks =	3647	blocks =

fs/xfs/xfs_log_cil.c+11−2

 	struct xfs_trans_header thdr;
 	struct xfs_log_iovec	lhdr;
 	struct xfs_log_vec	lvhdr = { NULL };
+	xfs_lsn_t		preflush_tail_lsn;
 	xfs_lsn_t		commit_lsn;
-	xfs_lsn_t		push_seq;
+	xfs_csn_t		push_seq;
 	struct bio		bio;
 	DECLARE_COMPLETION_ONSTACK(bdev_flush);
 	 * because we hold the flush lock exclusively. Hence we can now issue
 	 * a cache flush to ensure all the completed metadata in the journal we
 	 * are about to overwrite is on stable storage.
+	 *
+	 * Because we are issuing this cache flush before we've written the
+	 * tail lsn to the iclog, we can have metadata IO completions move the
+	 * tail forwards between the completion of this flush and the iclog
+	 * being written. In this case, we need to re-issue the cache flush
+	 * before the iclog write. To detect whether the log tail moves, sample
+	 * the tail LSN *before* we issue the flush.
 	 */
+	preflush_tail_lsn = atomic64_read(&log->l_tail_lsn);
 	xfs_flush_bdev_async(&bio, log->l_mp->m_ddev_targp->bt_bdev,
 				&bdev_flush);
 	 * storage.
 	 */
 	commit_iclog->ic_flags |= XLOG_ICL_NEED_FUA;
-	xlog_state_release_iclog(log, commit_iclog);
+	xlog_state_release_iclog(log, commit_iclog, preflush_tail_lsn);
 	spin_unlock(&log->l_icloglock);
 	return;

fs/xfs/xfs_log_priv.h+12−4

 	{ XLOG_STATE_DIRTY,	"XLOG_STATE_DIRTY" }, \
 	{ XLOG_STATE_IOERROR,	"XLOG_STATE_IOERROR" }
+/*
+ * In core log flags
+ */
+#define XLOG_ICL_NEED_FLUSH	(1 << 0)	/* iclog needs REQ_PREFLUSH */
+#define XLOG_ICL_NEED_FUA	(1 << 1)	/* iclog needs REQ_FUA */
+#define XLOG_ICL_STRINGS \
+	{ XLOG_ICL_NEED_FLUSH,	"XLOG_ICL_NEED_FLUSH" }, \
+	{ XLOG_ICL_NEED_FUA,	"XLOG_ICL_NEED_FUA" }
 /*
  * Log ticket flags
 #define XLOG_COVER_OPS		5
-#define XLOG_ICL_NEED_FLUSH	(1 << 0)	/* iclog needs REQ_PREFLUSH */
-#define XLOG_ICL_NEED_FUA	(1 << 1)	/* iclog needs REQ_FUA */
 /* Ticket reservation region accounting */
 #define XLOG_TIC_LEN_MAX	15
 void	xfs_log_ticket_ungrant(struct xlog *log, struct xlog_ticket *ticket);
 void	xfs_log_ticket_regrant(struct xlog *log, struct xlog_ticket *ticket);
-int xlog_state_release_iclog(struct xlog *log, struct xlog_in_core *iclog);
+int xlog_state_release_iclog(struct xlog *log, struct xlog_in_core *iclog,
+		xfs_lsn_t log_tail_lsn);
 /*
  * When we crack an atomic LSN, we sample it first so that the value will not

fs/xfs/xfs_trace.h+4−1

 		__field(uint32_t, state)
 		__field(int32_t, refcount)
 		__field(uint32_t, offset)
+		__field(uint32_t, flags)
 		__field(unsigned long long, lsn)
 		__field(unsigned long, caller_ip)
 	),
 		__entry->state = iclog->ic_state;
 		__entry->refcount = atomic_read(&iclog->ic_refcnt);
 		__entry->offset = iclog->ic_offset;
+		__entry->flags = iclog->ic_flags;
 		__entry->lsn = be64_to_cpu(iclog->ic_header.h_lsn);
 		__entry->caller_ip = caller_ip;
 	),
-	TP_printk("dev %d:%d state %s refcnt %d offset %u lsn 0x%llx caller %pS",
+	TP_printk("dev %d:%d state %s refcnt %d offset %u lsn 0x%llx flags %s caller %pS",
 		  MAJOR(__entry->dev), MINOR(__entry->dev),
 		  __print_symbolic(__entry->state, XLOG_STATE_STRINGS),
 		  __entry->refcount,
 		  __entry->offset,
 		  __entry->lsn,
+		  __print_flags(__entry->flags, "|", XLOG_ICL_STRINGS),
 		  (char *)__entry->caller_ip)
 );

include/acpi/acpi_bus.h+2−6

  * @hrv: Hardware Revision of the device, pass -1 to not check _HRV
  *
  * The caller is responsible for invoking acpi_dev_put() on the returned device.
- *
- * FIXME: Due to above requirement there is a window that may invalidate @adev
- * and next iteration will use a dangling pointer, e.g. in the case of a
- * hotplug event. That said, the caller should ensure that this will never
- * happen.
  */
 #define for_each_acpi_dev_match(adev, hid, uid, hrv)			\
 	for (adev = acpi_dev_get_first_match_dev(hid, uid, hrv);	\
 static inline void acpi_dev_put(struct acpi_device *adev)
 {
-	put_device(&adev->dev);
+	if (adev)
+		put_device(&adev->dev);
 }
 struct acpi_device *acpi_bus_get_acpi_device(acpi_handle handle);

include/drm/drm_ioctl.h+1−0

@@ -68,6 +68,7 @@ typedef int drm_ioctl_compat_t(struct file *filp, unsigned int cmd, · 67 unmodified lines
68	unsigned long arg);	68	unsigned long arg);
69		69
70	#define DRM_IOCTL_NR(n) _IOC_NR(n)	70	#define DRM_IOCTL_NR(n) _IOC_NR(n)
		71	#define DRM_IOCTL_TYPE(n) _IOC_TYPE(n)
71	#define DRM_MAJOR 226	72	#define DRM_MAJOR 226
72		73
73	/**	74	/**

include/linux/blkdev.h+1−1

@@ -57,7 +57,7 @@ struct blk_keyslot_manager; · 56 unmodified lines
57	* Maximum number of blkcg policies allowed to be registered concurrently.	57	* Maximum number of blkcg policies allowed to be registered concurrently.
58	* Defined here to simplify include dependency.	58	* Defined here to simplify include dependency.
59	*/	59	*/
60	#define BLKCG_MAX_POLS 5	60	#define BLKCG_MAX_POLS 6
61		61
62	typedef void (rq_end_io_fn)(struct request *, blk_status_t);	62	typedef void (rq_end_io_fn)(struct request *, blk_status_t);
63		63

include/linux/bpf_types.h+1−0

@@ -134,4 +134,5 @@ BPF_LINK_TYPE(BPF_LINK_TYPE_CGROUP, cgroup) · 133 unmodified lines
134	BPF_LINK_TYPE(BPF_LINK_TYPE_ITER, iter)	134	BPF_LINK_TYPE(BPF_LINK_TYPE_ITER, iter)
135	#ifdef CONFIG_NET	135	#ifdef CONFIG_NET
136	BPF_LINK_TYPE(BPF_LINK_TYPE_NETNS, netns)	136	BPF_LINK_TYPE(BPF_LINK_TYPE_NETNS, netns)
		137	BPF_LINK_TYPE(BPF_LINK_TYPE_XDP, xdp)
137	#endif	138	#endif

include/linux/bpf_verifier.h+2−1

 	};
 	u64 map_key_state; /* constant (32 bit) key tracking for maps */
 	int ctx_field_size; /* the ctx field size for load insn, maybe 0 */
-	int sanitize_stack_off; /* stack slot to be cleared */
 	u32 seen; /* this insn was processed by the verifier at env->pass_cnt */
+	bool sanitize_stack_spill; /* subject to Spectre v4 sanitation */
 	bool zext_dst; /* this insn zero extends dst reg */
 	u8 alu_state; /* used in combination with alu_limit */
 	u32 used_map_cnt;		/* number of used maps */
 	u32 used_btf_cnt;		/* number of used BTF objects */
 	u32 id_gen;			/* used to generate unique reg IDs */
+	bool explore_alu_limits;
 	bool allow_ptr_leaks;
 	bool allow_uninit_stack;
 	bool allow_ptr_to_map_access;

include/linux/entry-kvm.h+5−1

 #ifndef __LINUX_ENTRYKVM_H
 #define __LINUX_ENTRYKVM_H
-#include <linux/entry-common.h>
+#include <linux/static_call_types.h>
+#include <linux/tracehook.h>
+#include <linux/syscalls.h>
+#include <linux/seccomp.h>
+#include <linux/sched.h>
 #include <linux/tick.h>
 /* Transfer to guest mode work */

include/linux/filter.h+15−0

@@ -73,6 +73,11 @@ struct ctl_table_header; · 72 unmodified lines
73	/* unused opcode to mark call to interpreter with arguments */	73	/* unused opcode to mark call to interpreter with arguments */
74	#define BPF_CALL_ARGS 0xe0	74	#define BPF_CALL_ARGS 0xe0
75		75
		76	/* unused opcode to mark speculation barrier for mitigating
		77	* Speculative Store Bypass
		78	*/
		79	#define BPF_NOSPEC 0xc0
		80
76	/* As per nm, we expose JITed images as text (code) section for	81	/* As per nm, we expose JITed images as text (code) section for
77	* kallsyms. That way, tools like perf can find it to match	82	* kallsyms. That way, tools like perf can find it to match
78	* addresses.	83	* addresses.
@@ -390,6 +395,16 @@ static inline bool insn_is_zext(const struct bpf_insn *insn) · 311 unmodified lines
390	.off = 0, \	395	.off = 0, \
391	.imm = 0 })	396	.imm = 0 })
392		397
		398	/* Speculation barrier */
		399
		400	#define BPF_ST_NOSPEC() \
		401	((struct bpf_insn) { \
		402	.code = BPF_ST \| BPF_NOSPEC, \
		403	.dst_reg = 0, \
		404	.src_reg = 0, \
		405	.off = 0, \
		406	.imm = 0 })
		407
393	/* Internal classic blocks for direct assignment */	408	/* Internal classic blocks for direct assignment */
394		409
395	#define __BPF_STMT(CODE, K) \	410	#define __BPF_STMT(CODE, K) \

include/linux/fs_context.h+1−0

@@ -141,6 +141,7 @@ extern int vfs_get_tree(struct fs_context *fc); · 140 unmodified lines
141	extern void put_fs_context(struct fs_context *fc);	141	extern void put_fs_context(struct fs_context *fc);
142	extern int vfs_parse_fs_param_source(struct fs_context *fc,	142	extern int vfs_parse_fs_param_source(struct fs_context *fc,
143	struct fs_parameter *param);	143	struct fs_parameter *param);
		144	extern void fc_drop_locked(struct fs_context *fc);
144		145
145	/*	146	/*
146	* sget() wrappers to be called from the ->get_tree() op.	147	* sget() wrappers to be called from the ->get_tree() op.

include/linux/highmem.h+4−2

 	VM_BUG_ON(offset + len > PAGE_SIZE);
 	memcpy(to + offset, from, len);
+	flush_dcache_page(page);
 	kunmap_local(to);
 }
 static inline void memzero_page(struct page *page, size_t offset, size_t len)
 {
-	char *addr = kmap_atomic(page);
+	char *addr = kmap_local_page(page);
 	memset(addr + offset, 0, len);
-	kunmap_atomic(addr);
+	flush_dcache_page(page);
+	kunmap_local(addr);
 }
 #endif /* _LINUX_HIGHMEM_H */

include/linux/intel-ish-client-if.h+2−0

@@ -81,6 +81,8 @@ int ishtp_register_event_cb(struct ishtp_cl_device *device, · 80 unmodified lines
81		81
82	/* Get the device * from ishtp device instance */	82	/* Get the device * from ishtp device instance */
83	struct device ishtp_device(struct ishtp_cl_device cl_device);	83	struct device ishtp_device(struct ishtp_cl_device cl_device);
		84	/* wait for IPC resume */
		85	bool ishtp_wait_resume(struct ishtp_device *dev);
84	/* Trace interface for clients */	86	/* Trace interface for clients */
85	ishtp_print_log ishtp_trace_callback(struct ishtp_cl_device *cl_device);	87	ishtp_print_log ishtp_trace_callback(struct ishtp_cl_device *cl_device);
86	/* Get device pointer of PCI device for DMA acces */	88	/* Get device pointer of PCI device for DMA acces */

include/linux/kvm_host.h+0−1

@@ -872,7 +872,6 @@ void kvm_release_pfn_clean(kvm_pfn_t pfn); · 871 unmodified lines
872	void kvm_release_pfn_dirty(kvm_pfn_t pfn);	872	void kvm_release_pfn_dirty(kvm_pfn_t pfn);
873	void kvm_set_pfn_dirty(kvm_pfn_t pfn);	873	void kvm_set_pfn_dirty(kvm_pfn_t pfn);
874	void kvm_set_pfn_accessed(kvm_pfn_t pfn);	874	void kvm_set_pfn_accessed(kvm_pfn_t pfn);
875	void kvm_get_pfn(kvm_pfn_t pfn);
876		875
877	void kvm_release_pfn(kvm_pfn_t pfn, bool dirty, struct gfn_to_pfn_cache *cache);	876	void kvm_release_pfn(kvm_pfn_t pfn, bool dirty, struct gfn_to_pfn_cache *cache);
878	int kvm_read_guest_page(struct kvm kvm, gfn_t gfn, void data, int offset,	877	int kvm_read_guest_page(struct kvm kvm, gfn_t gfn, void data, int offset,

include/linux/memblock.h+2−2

@@ -209,7 +209,7 @@ static inline void __next_physmem_range(u64 idx, struct memblock_type type, · 208 unmodified lines
209	*/	209	*/
210	#define for_each_mem_range(i, p_start, p_end) \	210	#define for_each_mem_range(i, p_start, p_end) \
211	__for_each_mem_range(i, &memblock.memory, NULL, NUMA_NO_NODE, \	211	__for_each_mem_range(i, &memblock.memory, NULL, NUMA_NO_NODE, \
212	MEMBLOCK_NONE, p_start, p_end, NULL)	212	MEMBLOCK_HOTPLUG, p_start, p_end, NULL)
213		213
214	/**	214	/**
215	* for_each_mem_range_rev - reverse iterate through memblock areas from	215	* for_each_mem_range_rev - reverse iterate through memblock areas from
@@ -220,7 +220,7 @@ static inline void __next_physmem_range(u64 idx, struct memblock_type type, · 4 unmodified lines
220	*/	220	*/
221	#define for_each_mem_range_rev(i, p_start, p_end) \	221	#define for_each_mem_range_rev(i, p_start, p_end) \
222	__for_each_mem_range_rev(i, &memblock.memory, NULL, NUMA_NO_NODE, \	222	__for_each_mem_range_rev(i, &memblock.memory, NULL, NUMA_NO_NODE, \
223	MEMBLOCK_NONE, p_start, p_end, NULL)	223	MEMBLOCK_HOTPLUG, p_start, p_end, NULL)
224		224
225	/**	225	/**
226	* for_each_reserved_mem_range - iterate over all reserved memblock areas	226	* for_each_reserved_mem_range - iterate over all reserved memblock areas

include/linux/mfd/rt5033-private.h+2−2

@@ -200,13 +200,13 @@ enum rt5033_reg { · 199 unmodified lines
200	#define RT5033_REGULATOR_BUCK_VOLTAGE_MIN 1000000U	200	#define RT5033_REGULATOR_BUCK_VOLTAGE_MIN 1000000U
201	#define RT5033_REGULATOR_BUCK_VOLTAGE_MAX 3000000U	201	#define RT5033_REGULATOR_BUCK_VOLTAGE_MAX 3000000U
202	#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP 100000U	202	#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP 100000U
203	#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP_NUM 32	203	#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP_NUM 21
204		204
205	/* RT5033 regulator LDO output voltage uV */	205	/* RT5033 regulator LDO output voltage uV */
206	#define RT5033_REGULATOR_LDO_VOLTAGE_MIN 1200000U	206	#define RT5033_REGULATOR_LDO_VOLTAGE_MIN 1200000U
207	#define RT5033_REGULATOR_LDO_VOLTAGE_MAX 3000000U	207	#define RT5033_REGULATOR_LDO_VOLTAGE_MAX 3000000U
208	#define RT5033_REGULATOR_LDO_VOLTAGE_STEP 100000U	208	#define RT5033_REGULATOR_LDO_VOLTAGE_STEP 100000U
209	#define RT5033_REGULATOR_LDO_VOLTAGE_STEP_NUM 32	209	#define RT5033_REGULATOR_LDO_VOLTAGE_STEP_NUM 19
210		210
211	/* RT5033 regulator SAFE LDO output voltage uV */	211	/* RT5033 regulator SAFE LDO output voltage uV */
212	#define RT5033_REGULATOR_SAFE_LDO_VOLTAGE 4900000U	212	#define RT5033_REGULATOR_SAFE_LDO_VOLTAGE 4900000U

include/linux/page-flags.h+0−37

@@ -632,43 +632,6 @@ static inline int PageTransCompound(struct page *page) · 631 unmodified lines
632	return PageCompound(page);	632	return PageCompound(page);
633	}	633	}
634		634
635	/*
636	* PageTransCompoundMap is the same as PageTransCompound, but it also
637	* guarantees the primary MMU has the entire compound page mapped
638	* through pmd_trans_huge, which in turn guarantees the secondary MMUs
639	* can also map the entire compound page. This allows the secondary
640	* MMUs to call get_user_pages() only once for each compound page and
641	* to immediately map the entire compound page with a single secondary
642	* MMU fault. If there will be a pmd split later, the secondary MMUs
643	* will get an update through the MMU notifier invalidation through
644	* split_huge_pmd().
645	*
646	* Unlike PageTransCompound, this is safe to be called only while
647	* split_huge_pmd() cannot run from under us, like if protected by the
648	* MMU notifier, otherwise it may result in page->_mapcount check false
649	* positives.
650	*
651	* We have to treat page cache THP differently since every subpage of it
652	* would get _mapcount inc'ed once it is PMD mapped. But, it may be PTE
653	* mapped in the current process so comparing subpage's _mapcount to
654	* compound_mapcount to filter out PTE mapped case.
655	*/
656	static inline int PageTransCompoundMap(struct page *page)
657	{
658	struct page *head;
659
660	if (!PageTransCompound(page))
661	return 0;
662
663	if (PageAnon(page))
664	return atomic_read(&page->_mapcount) < 0;
665
666	head = compound_head(page);
667	/* File THP is PMD mapped and not PTE mapped */
668	return atomic_read(&page->_mapcount) ==
669	atomic_read(compound_mapcount_ptr(head));
670	}
671
672	/*	635	/*
673	* PageTransTail returns true for both transparent huge pages	636	* PageTransTail returns true for both transparent huge pages
674	* and hugetlbfs pages, so it should only be called when it's known	637	* and hugetlbfs pages, so it should only be called when it's known

include/linux/pgtable.h+1−25

@@ -1397,34 +1397,10 @@ static inline int p4d_clear_huge(p4d_t *p4d) · 1396 unmodified lines
1397	}	1397	}
1398	#endif /* !__PAGETABLE_P4D_FOLDED */	1398	#endif /* !__PAGETABLE_P4D_FOLDED */
1399		1399
1400	#ifndef __PAGETABLE_PUD_FOLDED
1401	int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot);	1400	int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot);
1402	int pud_clear_huge(pud_t *pud);
1403	#else
1404	static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
1405	{
1406	return 0;
1407	}
1408	static inline int pud_clear_huge(pud_t *pud)
1409	{
1410	return 0;
1411	}
1412	#endif /* !__PAGETABLE_PUD_FOLDED */
1413
1414	#ifndef __PAGETABLE_PMD_FOLDED
1415	int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot);	1401	int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot);
		1402	int pud_clear_huge(pud_t *pud);
1416	int pmd_clear_huge(pmd_t *pmd);	1403	int pmd_clear_huge(pmd_t *pmd);
1417	#else
1418	static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
1419	{
1420	return 0;
1421	}
1422	static inline int pmd_clear_huge(pmd_t *pmd)
1423	{
1424	return 0;
1425	}
1426	#endif /* !__PAGETABLE_PMD_FOLDED */
1427
1428	int p4d_free_pud_page(p4d_t *p4d, unsigned long addr);	1404	int p4d_free_pud_page(p4d_t *p4d, unsigned long addr);
1429	int pud_free_pmd_page(pud_t *pud, unsigned long addr);	1405	int pud_free_pmd_page(pud_t *pud, unsigned long addr);
1430	int pmd_free_pte_page(pmd_t *pmd, unsigned long addr);	1406	int pmd_free_pte_page(pmd_t *pmd, unsigned long addr);

include/linux/skmsg.h+35−19

 	return rcu_dereference_sk_user_data(sk);
 }
+static inline void sk_psock_set_state(struct sk_psock *psock,
+				      enum sk_psock_state_bits bit)
+{
+	set_bit(bit, &psock->state);
+}
+static inline void sk_psock_clear_state(struct sk_psock *psock,
+					enum sk_psock_state_bits bit)
+{
+	clear_bit(bit, &psock->state);
+}
+static inline bool sk_psock_test_state(const struct sk_psock *psock,
+				       enum sk_psock_state_bits bit)
+{
+	return test_bit(bit, &psock->state);
+}
+static inline void sock_drop(struct sock *sk, struct sk_buff *skb)
+{
+	sk_drops_add(sk, skb);
+	kfree_skb(skb);
+}
+static inline void drop_sk_msg(struct sk_psock *psock, struct sk_msg *msg)
+{
+	if (msg->skb)
+		sock_drop(psock->sk, msg->skb);
+	kfree(msg);
+}
 static inline void sk_psock_queue_msg(struct sk_psock *psock,
 				      struct sk_msg *msg)
 {
 	spin_lock_bh(&psock->ingress_lock);
-	list_add_tail(&msg->list, &psock->ingress_msg);
+	if (sk_psock_test_state(psock, SK_PSOCK_TX_ENABLED))
+		list_add_tail(&msg->list, &psock->ingress_msg);
+	else
+		drop_sk_msg(psock, msg);
 	spin_unlock_bh(&psock->ingress_lock);
 }
 		psock->psock_update_sk_prot(sk, psock, true);
 }
-static inline void sk_psock_set_state(struct sk_psock *psock,
-				      enum sk_psock_state_bits bit)
-{
-	set_bit(bit, &psock->state);
-}
-static inline void sk_psock_clear_state(struct sk_psock *psock,
-					enum sk_psock_state_bits bit)
-{
-	clear_bit(bit, &psock->state);
-}
-static inline bool sk_psock_test_state(const struct sk_psock *psock,
-				       enum sk_psock_state_bits bit)
-{
-	return test_bit(bit, &psock->state);
-}
 static inline struct sk_psock *sk_psock_get(struct sock *sk)
 {
 	struct sk_psock *psock;

include/net/llc_pdu.h+23−8

@@ -15,9 +15,11 @@ · 14 unmodified lines
15	#include <linux/if_ether.h>	15	#include <linux/if_ether.h>
16		16
17	/* Lengths of frame formats */	17	/* Lengths of frame formats */
18	#define LLC_PDU_LEN_I 4 /* header and 2 control bytes */	18	#define LLC_PDU_LEN_I 4 /* header and 2 control bytes */
19	#define LLC_PDU_LEN_S 4	19	#define LLC_PDU_LEN_S 4
20	#define LLC_PDU_LEN_U 3 /* header and 1 control byte */	20	#define LLC_PDU_LEN_U 3 /* header and 1 control byte */
		21	/* header and 1 control byte and XID info */
		22	#define LLC_PDU_LEN_U_XID (LLC_PDU_LEN_U + sizeof(struct llc_xid_info))
21	/* Known SAP addresses */	23	/* Known SAP addresses */
22	#define LLC_GLOBAL_SAP 0xFF	24	#define LLC_GLOBAL_SAP 0xFF
23	#define LLC_NULL_SAP 0x00 /* not network-layer visible */	25	#define LLC_NULL_SAP 0x00 /* not network-layer visible */
@@ -50,9 +52,10 @@ · 26 unmodified lines
50	#define LLC_PDU_TYPE_U_MASK 0x03 /* 8-bit control field */	52	#define LLC_PDU_TYPE_U_MASK 0x03 /* 8-bit control field */
51	#define LLC_PDU_TYPE_MASK 0x03	53	#define LLC_PDU_TYPE_MASK 0x03
52		54
53	#define LLC_PDU_TYPE_I 0 /* first bit */	55	#define LLC_PDU_TYPE_I 0 /* first bit */
54	#define LLC_PDU_TYPE_S 1 /* first two bits */	56	#define LLC_PDU_TYPE_S 1 /* first two bits */
55	#define LLC_PDU_TYPE_U 3 /* first two bits */	57	#define LLC_PDU_TYPE_U 3 /* first two bits */
		58	#define LLC_PDU_TYPE_U_XID 4 /* private type for detecting XID commands */
56		59
57	#define LLC_PDU_TYPE_IS_I(pdu) \	60	#define LLC_PDU_TYPE_IS_I(pdu) \
58	((!(pdu->ctrl_1 & LLC_PDU_TYPE_I_MASK)) ? 1 : 0)	61	((!(pdu->ctrl_1 & LLC_PDU_TYPE_I_MASK)) ? 1 : 0)
@@ -230,9 +233,18 @@ static inline struct llc_pdu_un llc_pdu_un_hdr(struct sk_buff skb) · 171 unmodified lines
230	static inline void llc_pdu_header_init(struct sk_buff *skb, u8 type,	233	static inline void llc_pdu_header_init(struct sk_buff *skb, u8 type,
231	u8 ssap, u8 dsap, u8 cr)	234	u8 ssap, u8 dsap, u8 cr)
232	{	235	{
233	const int hlen = type == LLC_PDU_TYPE_U ? 3 : 4;	236	int hlen = 4; /* default value for I and S types */
234	struct llc_pdu_un *pdu;	237	struct llc_pdu_un *pdu;
235		238
		239	switch (type) {
		240	case LLC_PDU_TYPE_U:
		241	hlen = 3;
		242	break;
		243	case LLC_PDU_TYPE_U_XID:
		244	hlen = 6;
		245	break;
		246	}
		247
236	skb_push(skb, hlen);	248	skb_push(skb, hlen);
237	skb_reset_network_header(skb);	249	skb_reset_network_header(skb);
238	pdu = llc_pdu_un_hdr(skb);	250	pdu = llc_pdu_un_hdr(skb);
@@ -374,7 +386,10 @@ static inline void llc_pdu_init_as_xid_cmd(struct sk_buff *skb, · 135 unmodified lines
374	xid_info->fmt_id = LLC_XID_FMT_ID; /* 0x81 */	386	xid_info->fmt_id = LLC_XID_FMT_ID; /* 0x81 */
375	xid_info->type = svcs_supported;	387	xid_info->type = svcs_supported;
376	xid_info->rw = rx_window << 1; /* size of receive window */	388	xid_info->rw = rx_window << 1; /* size of receive window */
377	skb_put(skb, sizeof(struct llc_xid_info));	389
		390	/* no need to push/put since llc_pdu_header_init() has already
		391	* pushed 3 + 3 bytes
		392	*/
378	}	393	}
379		394
380	/**	395	/**

include/net/sctp/structs.h+3−2

 	} cacc;
 	struct {
+		__u32 last_rtx_chunks;
 		__u16 pmtu;
 		__u16 probe_size;
 		__u16 probe_high;
 void sctp_transport_immediate_rtx(struct sctp_transport *);
 void sctp_transport_dst_release(struct sctp_transport *t);
 void sctp_transport_dst_confirm(struct sctp_transport *t);
-void sctp_transport_pl_send(struct sctp_transport *t);
+bool sctp_transport_pl_send(struct sctp_transport *t);
-void sctp_transport_pl_recv(struct sctp_transport *t);
+bool sctp_transport_pl_recv(struct sctp_transport *t);
 /* This is the structure we use to queue packets as they come into

include/net/tcp.h+0−1

@@ -1709,7 +1709,6 @@ struct tcp_fastopen_context { · 1708 unmodified lines
1709	struct rcu_head rcu;	1709	struct rcu_head rcu;
1710	};	1710	};
1711		1711
1712	extern unsigned int sysctl_tcp_fastopen_blackhole_timeout;
1713	void tcp_fastopen_active_disable(struct sock *sk);	1712	void tcp_fastopen_active_disable(struct sock *sk);
1714	bool tcp_fastopen_active_should_disable(struct sock *sk);	1713	bool tcp_fastopen_active_should_disable(struct sock *sk);
1715	void tcp_fastopen_active_disable_ofo_check(struct sock *sk);	1714	void tcp_fastopen_active_disable_ofo_check(struct sock *sk);

include/sound/soc.h+6−0

 	/* Do not create a PCM for this DAI link (Backend link) */
 	unsigned int ignore:1;
+	/* This flag will reorder stop sequence. By enabling this flag
+	 * DMA controller stop sequence will be invoked first followed by
+	 * CPU DAI driver stop sequence
+	 */
+	unsigned int stop_dma_first:1;
 #ifdef CONFIG_SND_SOC_TOPOLOGY
 	struct snd_soc_dobj dobj; /* For topology */
 #endif

include/trace/events/afs.h+62−5

@@ -174,6 +174,34 @@ enum afs_vl_operation { · 173 unmodified lines
174	afs_VL_GetCapabilities = 65537, /* AFS Get VL server capabilities */	174	afs_VL_GetCapabilities = 65537, /* AFS Get VL server capabilities */
175	};	175	};
176		176
		177	enum afs_cm_operation {
		178	afs_CB_CallBack = 204, /* AFS break callback promises */
		179	afs_CB_InitCallBackState = 205, /* AFS initialise callback state */
		180	afs_CB_Probe = 206, /* AFS probe client */
		181	afs_CB_GetLock = 207, /* AFS get contents of CM lock table */
		182	afs_CB_GetCE = 208, /* AFS get cache file description */
		183	afs_CB_GetXStatsVersion = 209, /* AFS get version of extended statistics */
		184	afs_CB_GetXStats = 210, /* AFS get contents of extended statistics data */
		185	afs_CB_InitCallBackState3 = 213, /* AFS initialise callback state, version 3 */
		186	afs_CB_ProbeUuid = 214, /* AFS check the client hasn't rebooted */
		187	};
		188
		189	enum yfs_cm_operation {
		190	yfs_CB_Probe = 206, /* YFS probe client */
		191	yfs_CB_GetLock = 207, /* YFS get contents of CM lock table */
		192	yfs_CB_XStatsVersion = 209, /* YFS get version of extended statistics */
		193	yfs_CB_GetXStats = 210, /* YFS get contents of extended statistics data */
		194	yfs_CB_InitCallBackState3 = 213, /* YFS initialise callback state, version 3 */
		195	yfs_CB_ProbeUuid = 214, /* YFS check the client hasn't rebooted */
		196	yfs_CB_GetServerPrefs = 215,
		197	yfs_CB_GetCellServDV = 216,
		198	yfs_CB_GetLocalCell = 217,
		199	yfs_CB_GetCacheConfig = 218,
		200	yfs_CB_GetCellByNum = 65537,
		201	yfs_CB_TellMeAboutYourself = 65538, /* get client capabilities */
		202	yfs_CB_CallBack = 64204,
		203	};
		204
177	enum afs_edit_dir_op {	205	enum afs_edit_dir_op {
178	afs_edit_dir_create,	206	afs_edit_dir_create,
179	afs_edit_dir_create_error,	207	afs_edit_dir_create_error,
@@ -436,6 +464,32 @@ enum afs_cb_break_reason { · 256 unmodified lines
436	EM(afs_YFSVL_GetCellName, "YFSVL.GetCellName") \	464	EM(afs_YFSVL_GetCellName, "YFSVL.GetCellName") \
437	E_(afs_VL_GetCapabilities, "VL.GetCapabilities")	465	E_(afs_VL_GetCapabilities, "VL.GetCapabilities")
438		466
		467	#define afs_cm_operations \
		468	EM(afs_CB_CallBack, "CB.CallBack") \
		469	EM(afs_CB_InitCallBackState, "CB.InitCallBackState") \
		470	EM(afs_CB_Probe, "CB.Probe") \
		471	EM(afs_CB_GetLock, "CB.GetLock") \
		472	EM(afs_CB_GetCE, "CB.GetCE") \
		473	EM(afs_CB_GetXStatsVersion, "CB.GetXStatsVersion") \
		474	EM(afs_CB_GetXStats, "CB.GetXStats") \
		475	EM(afs_CB_InitCallBackState3, "CB.InitCallBackState3") \
		476	E_(afs_CB_ProbeUuid, "CB.ProbeUuid")
		477
		478	#define yfs_cm_operations \
		479	EM(yfs_CB_Probe, "YFSCB.Probe") \
		480	EM(yfs_CB_GetLock, "YFSCB.GetLock") \
		481	EM(yfs_CB_XStatsVersion, "YFSCB.XStatsVersion") \
		482	EM(yfs_CB_GetXStats, "YFSCB.GetXStats") \
		483	EM(yfs_CB_InitCallBackState3, "YFSCB.InitCallBackState3") \
		484	EM(yfs_CB_ProbeUuid, "YFSCB.ProbeUuid") \
		485	EM(yfs_CB_GetServerPrefs, "YFSCB.GetServerPrefs") \
		486	EM(yfs_CB_GetCellServDV, "YFSCB.GetCellServDV") \
		487	EM(yfs_CB_GetLocalCell, "YFSCB.GetLocalCell") \
		488	EM(yfs_CB_GetCacheConfig, "YFSCB.GetCacheConfig") \
		489	EM(yfs_CB_GetCellByNum, "YFSCB.GetCellByNum") \
		490	EM(yfs_CB_TellMeAboutYourself, "YFSCB.TellMeAboutYourself") \
		491	E_(yfs_CB_CallBack, "YFSCB.CallBack")
		492
439	#define afs_edit_dir_ops \	493	#define afs_edit_dir_ops \
440	EM(afs_edit_dir_create, "create") \	494	EM(afs_edit_dir_create, "create") \
441	EM(afs_edit_dir_create_error, "c_fail") \	495	EM(afs_edit_dir_create_error, "c_fail") \
@@ -569,6 +623,8 @@ afs_server_traces; · 127 unmodified lines
569	afs_cell_traces;	623	afs_cell_traces;
570	afs_fs_operations;	624	afs_fs_operations;
571	afs_vl_operations;	625	afs_vl_operations;
		626	afs_cm_operations;
		627	yfs_cm_operations;
572	afs_edit_dir_ops;	628	afs_edit_dir_ops;
573	afs_edit_dir_reasons;	629	afs_edit_dir_reasons;
574	afs_eproto_causes;	630	afs_eproto_causes;
@@ -649,20 +705,21 @@ TRACE_EVENT(afs_cb_call, · 74 unmodified lines
649		705
650	TP_STRUCT__entry(	706	TP_STRUCT__entry(
651	__field(unsigned int, call )	707	__field(unsigned int, call )
652	__field(const char *, name )
653	__field(u32, op )	708	__field(u32, op )
		709	__field(u16, service_id )
654	),	710	),
655		711
656	TP_fast_assign(	712	TP_fast_assign(
657	__entry->call = call->debug_id;	713	__entry->call = call->debug_id;
658	__entry->name = call->type->name;
659	__entry->op = call->operation_ID;	714	__entry->op = call->operation_ID;
		715	__entry->service_id = call->service_id;
660	),	716	),
661		717
662	TP_printk("c=%08x %s o=%u",	718	TP_printk("c=%08x %s",
663	__entry->call,	719	__entry->call,
664	__entry->name,	720	__entry->service_id == 2501 ?
665	__entry->op)	721	__print_symbolic(__entry->op, yfs_cm_operations) :
		722	__print_symbolic(__entry->op, afs_cm_operations))
666	);	723	);
667		724
668	TRACE_EVENT(afs_call,	725	TRACE_EVENT(afs_call,

include/trace/events/net.h+1−1

@@ -136,7 +136,7 @@ DECLARE_EVENT_CLASS(net_dev_template, · 135 unmodified lines
136	__assign_str(name, skb->dev->name);	136	__assign_str(name, skb->dev->name);
137	),	137	),
138		138
139	TP_printk("dev=%s skbaddr=%p len=%u",	139	TP_printk("dev=%s skbaddr=%px len=%u",
140	__get_str(name), __entry->skbaddr, __entry->len)	140	__get_str(name), __entry->skbaddr, __entry->len)
141	)	141	)
142		142

include/trace/events/qdisc.h+27−1

@@ -41,11 +41,37 @@ TRACE_EVENT(qdisc_dequeue, · 40 unmodified lines
41	__entry->txq_state = txq->state;	41	__entry->txq_state = txq->state;
42	),	42	),
43		43
44	TP_printk("dequeue ifindex=%d qdisc handle=0x%X parent=0x%X txq_state=0x%lX packets=%d skbaddr=%p",	44	TP_printk("dequeue ifindex=%d qdisc handle=0x%X parent=0x%X txq_state=0x%lX packets=%d skbaddr=%px",
45	__entry->ifindex, __entry->handle, __entry->parent,	45	__entry->ifindex, __entry->handle, __entry->parent,
46	__entry->txq_state, __entry->packets, __entry->skbaddr )	46	__entry->txq_state, __entry->packets, __entry->skbaddr )
47	);	47	);
48		48
		49	TRACE_EVENT(qdisc_enqueue,
		50
		51	TP_PROTO(struct Qdisc qdisc, const struct netdev_queue txq, struct sk_buff *skb),
		52
		53	TP_ARGS(qdisc, txq, skb),
		54
		55	TP_STRUCT__entry(
		56	__field(struct Qdisc *, qdisc)
		57	__field(void *, skbaddr)
		58	__field(int, ifindex)
		59	__field(u32, handle)
		60	__field(u32, parent)
		61	),
		62
		63	TP_fast_assign(
		64	__entry->qdisc = qdisc;
		65	__entry->skbaddr = skb;
		66	__entry->ifindex = txq->dev ? txq->dev->ifindex : 0;
		67	__entry->handle = qdisc->handle;
		68	__entry->parent = qdisc->parent;
		69	),
		70
		71	TP_printk("enqueue ifindex=%d qdisc handle=0x%X parent=0x%X skbaddr=%px",
		72	__entry->ifindex, __entry->handle, __entry->parent, __entry->skbaddr)
		73	);
		74
49	TRACE_EVENT(qdisc_reset,	75	TRACE_EVENT(qdisc_reset,
50		76
51	TP_PROTO(struct Qdisc *q),	77	TP_PROTO(struct Qdisc *q),

include/uapi/linux/idxd.h+1−1

@@ -1,4 +1,4 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */	1	/* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */
2	/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */	2	/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3	#ifndef _USR_IDXD_H_	3	#ifndef _USR_IDXD_H_
4	#define _USR_IDXD_H_	4	#define _USR_IDXD_H_

include/uapi/rdma/irdma-abi.h+1−1

@@ -1,4 +1,4 @@
1	/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */	1	/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB */
2	/*	2	/*
3	* Copyright (c) 2006 - 2021 Intel Corporation. All rights reserved.	3	* Copyright (c) 2006 - 2021 Intel Corporation. All rights reserved.
4	* Copyright (c) 2005 Topspin Communications. All rights reserved.	4	* Copyright (c) 2005 Topspin Communications. All rights reserved.

kernel/bpf/core.c+18−1

 #include <linux/perf_event.h>
 #include <linux/extable.h>
 #include <linux/log2.h>
+#include <asm/barrier.h>
 #include <asm/unaligned.h>
 /* Registers */
 		/* Non-UAPI available opcodes. */
 		[BPF_JMP | BPF_CALL_ARGS] = &&JMP_CALL_ARGS,
 		[BPF_JMP | BPF_TAIL_CALL] = &&JMP_TAIL_CALL,
+		[BPF_ST  | BPF_NOSPEC] = &&ST_NOSPEC,
 		[BPF_LDX | BPF_PROBE_MEM | BPF_B] = &&LDX_PROBE_MEM_B,
 		[BPF_LDX | BPF_PROBE_MEM | BPF_H] = &&LDX_PROBE_MEM_H,
 		[BPF_LDX | BPF_PROBE_MEM | BPF_W] = &&LDX_PROBE_MEM_W,
 	COND_JMP(s, JSGE, >=)
 	COND_JMP(s, JSLE, <=)
 #undef COND_JMP
-	/* STX and ST and LDX*/
+	/* ST, STX and LDX*/
+	ST_NOSPEC:
+		/* Speculation barrier for mitigating Speculative Store Bypass.
+		 * In case of arm64, we rely on the firmware mitigation as
+		 * controlled via the ssbd kernel parameter. Whenever the
+		 * mitigation is enabled, it works for all of the kernel code
+		 * with no need to provide any additional instructions here.
+		 * In case of x86, we use 'lfence' insn for mitigation. We
+		 * reuse preexisting logic from Spectre v1 mitigation that
+		 * happens to produce the required code on x86 for v4 as well.
+		 */
+#ifdef CONFIG_X86
+		barrier_nospec();
+#endif
+		CONT;
 #define LDST(SIZEOP, SIZE)						\
 	STX_MEM_##SIZEOP:						\
 		*(SIZE *)(unsigned long) (DST + insn->off) = SRC;	\

kernel/bpf/disasm.c+9−7

 			verbose(cbs->private_data, "BUG_%02x\n", insn->code);
 		}
 	} else if (class == BPF_ST) {
-		if (BPF_MODE(insn->code) != BPF_MEM) {
+		if (BPF_MODE(insn->code) == BPF_MEM) {
+			verbose(cbs->private_data, "(%02x) *(%s *)(r%d %+d) = %d\n",
+				insn->code,
+				bpf_ldst_string[BPF_SIZE(insn->code) >> 3],
+				insn->dst_reg,
+				insn->off, insn->imm);
+		} else if (BPF_MODE(insn->code) == 0xc0 /* BPF_NOSPEC, no UAPI */) {
+			verbose(cbs->private_data, "(%02x) nospec\n", insn->code);
+		} else {
 			verbose(cbs->private_data, "BUG_st_%02x\n", insn->code);
-			return;
 		}
-		verbose(cbs->private_data, "(%02x) *(%s *)(r%d %+d) = %d\n",
-			insn->code,
-			bpf_ldst_string[BPF_SIZE(insn->code) >> 3],
-			insn->dst_reg,
-			insn->off, insn->imm);
 	} else if (class == BPF_LDX) {
 		if (BPF_MODE(insn->code) != BPF_MEM) {
 			verbose(cbs->private_data, "BUG_ldx_%02x\n", insn->code);

kernel/bpf/verifier.c+51−99

 	cur = env->cur_state->frame[env->cur_state->curframe];
 	if (value_regno >= 0)
 		reg = &cur->regs[value_regno];
+	if (!env->bypass_spec_v4) {
+		bool sanitize = reg && is_spillable_regtype(reg->type);
+		for (i = 0; i < size; i++) {
+			if (state->stack[spi].slot_type[i] == STACK_INVALID) {
+				sanitize = true;
+				break;
+			}
+		}
+		if (sanitize)
+			env->insn_aux_data[insn_idx].sanitize_stack_spill = true;
+	}
 	if (reg && size == BPF_REG_SIZE && register_is_bounded(reg) &&
 	    !register_is_null(reg) && env->bpf_capable) {
 			verbose(env, "invalid size of register spill\n");
 			return -EACCES;
 		}
 		if (state != cur && reg->type == PTR_TO_STACK) {
 			verbose(env, "cannot spill pointers to stack into stack frame of the caller\n");
 			return -EINVAL;
 		}
-		if (!env->bypass_spec_v4) {
-			bool sanitize = false;
-			if (state->stack[spi].slot_type[0] == STACK_SPILL &&
-			    register_is_const(&state->stack[spi].spilled_ptr))
-				sanitize = true;
-			for (i = 0; i < BPF_REG_SIZE; i++)
-				if (state->stack[spi].slot_type[i] == STACK_MISC) {
-					sanitize = true;
-					break;
-				}
-			if (sanitize) {
-				int *poff = &env->insn_aux_data[insn_idx].sanitize_stack_off;
-				int soff = (-spi - 1) * BPF_REG_SIZE;
-				/* detected reuse of integer stack slot with a pointer
-				 * which means either llvm is reusing stack slot or
-				 * an attacker is trying to exploit CVE-2018-3639
-				 * (speculative store bypass)
-				 * Have to sanitize that slot with preemptive
-				 * store of zero.
-				 */
-				if (*poff && *poff != soff) {
-					/* disallow programs where single insn stores
-					 * into two different stack slots, since verifier
-					 * cannot sanitize them
-					 */
-					verbose(env,
-						"insn %d cannot access two stack slots fp%d and fp%d",
-						insn_idx, *poff, soff);
-					return -EINVAL;
-				}
-				*poff = soff;
-			}
-		}
 		save_register_state(state, spi, reg);
 	} else {
 		u8 type = STACK_MISC;
 	if (tail_call_reachable)
 		for (j = 0; j < frame; j++)
 			subprog[ret_prog[j]].tail_call_reachable = true;
+	if (subprog[0].tail_call_reachable)
+		env->prog->aux->tail_call_reachable = true;
 	/* end of for() loop means the last insn of the 'subprog'
 	 * was reached. Doesn't matter whether it was JA or EXIT
 		alu_state |= off_is_imm ? BPF_ALU_IMMEDIATE : 0;
 		alu_state |= ptr_is_dst_reg ?
 			     BPF_ALU_SANITIZE_SRC : BPF_ALU_SANITIZE_DST;
+		/* Limit pruning on unknown scalars to enable deep search for
+		 * potential masking differences from other program paths.
+		 */
+		if (!off_is_imm)
+			env->explore_alu_limits = true;
 	}
 	err = update_alu_sanitation_state(aux, alu_state, alu_limit);
 }
 /* Returns true if (rold safe implies rcur safe) */
-static bool regsafe(struct bpf_reg_state *rold, struct bpf_reg_state *rcur,
+static bool regsafe(struct bpf_verifier_env *env, struct bpf_reg_state *rold,
-		    struct bpf_id_pair *idmap)
+		    struct bpf_reg_state *rcur, struct bpf_id_pair *idmap)
 {
 	bool equal;
 		return false;
 	switch (rold->type) {
 	case SCALAR_VALUE:
+		if (env->explore_alu_limits)
+			return false;
 		if (rcur->type == SCALAR_VALUE) {
 			if (!rold->precise && !rcur->precise)
 				return true;
 	return false;
 }
-static bool stacksafe(struct bpf_func_state *old,
+static bool stacksafe(struct bpf_verifier_env *env, struct bpf_func_state *old,
-		      struct bpf_func_state *cur,
+		      struct bpf_func_state *cur, struct bpf_id_pair *idmap)
-		      struct bpf_id_pair *idmap)
 {
 	int i, spi;
 			continue;
 		if (old->stack[spi].slot_type[0] != STACK_SPILL)
 			continue;
-		if (!regsafe(&old->stack[spi].spilled_ptr,
+		if (!regsafe(env, &old->stack[spi].spilled_ptr,
-			     &cur->stack[spi].spilled_ptr,
+			     &cur->stack[spi].spilled_ptr, idmap))
-			     idmap))
 			/* when explored and current stack slot are both storing
 			 * spilled registers, check that stored pointers types
 			 * are the same as well.
 	memset(env->idmap_scratch, 0, sizeof(env->idmap_scratch));
 	for (i = 0; i < MAX_BPF_REG; i++)
-		if (!regsafe(&old->regs[i], &cur->regs[i], env->idmap_scratch))
+		if (!regsafe(env, &old->regs[i], &cur->regs[i],
+			     env->idmap_scratch))
 			return false;
-	if (!stacksafe(old, cur, env->idmap_scratch))
+	if (!stacksafe(env, old, cur, env->idmap_scratch))
 		return false;
 	if (!refsafe(old, cur))
 	for (i = 0; i < insn_cnt; i++, insn++) {
 		bpf_convert_ctx_access_t convert_ctx_access;
+		bool ctx_access;
 		if (insn->code == (BPF_LDX | BPF_MEM | BPF_B) ||
 		    insn->code == (BPF_LDX | BPF_MEM | BPF_H) ||
 		    insn->code == (BPF_LDX | BPF_MEM | BPF_W) ||
-		    insn->code == (BPF_LDX | BPF_MEM | BPF_DW))
+		    insn->code == (BPF_LDX | BPF_MEM | BPF_DW)) {
 			type = BPF_READ;
-		else if (insn->code == (BPF_STX | BPF_MEM | BPF_B) ||
+			ctx_access = true;
-			 insn->code == (BPF_STX | BPF_MEM | BPF_H) ||
+		} else if (insn->code == (BPF_STX | BPF_MEM | BPF_B) ||
-			 insn->code == (BPF_STX | BPF_MEM | BPF_W) ||
+			   insn->code == (BPF_STX | BPF_MEM | BPF_H) ||
-			 insn->code == (BPF_STX | BPF_MEM | BPF_DW))
+			   insn->code == (BPF_STX | BPF_MEM | BPF_W) ||
+			   insn->code == (BPF_STX | BPF_MEM | BPF_DW) ||
+			   insn->code == (BPF_ST | BPF_MEM | BPF_B) ||
+			   insn->code == (BPF_ST | BPF_MEM | BPF_H) ||
+			   insn->code == (BPF_ST | BPF_MEM | BPF_W) ||
+			   insn->code == (BPF_ST | BPF_MEM | BPF_DW)) {
 			type = BPF_WRITE;
-		else
+			ctx_access = BPF_CLASS(insn->code) == BPF_STX;
+		} else {
 			continue;
+		}
 		if (type == BPF_WRITE &&
-		    env->insn_aux_data[i + delta].sanitize_stack_off) {
+		    env->insn_aux_data[i + delta].sanitize_stack_spill) {
 			struct bpf_insn patch[] = {
-				/* Sanitize suspicious stack slot with zero.
-				 * There are no memory dependencies for this store,
-				 * since it's only using frame pointer and immediate
-				 * constant of zero
-				 */
-				BPF_ST_MEM(BPF_DW, BPF_REG_FP,
-					   env->insn_aux_data[i + delta].sanitize_stack_off,
-					   0),
-				/* the original STX instruction will immediately
-				 * overwrite the same stack slot with appropriate value
-				 */
 				*insn,
+				BPF_ST_NOSPEC(),
 			};
 			cnt = ARRAY_SIZE(patch);
 			continue;
 		}
+		if (!ctx_access)
+			continue;
 		switch (env->insn_aux_data[i + delta].ptr_type) {
 		case PTR_TO_CTX:
 			if (!ops->convert_ctx_access)
 	}
 }
-/* The verifier is using insn_aux_data[] to store temporary data during
- * verification and to store information for passes that run after the
- * verification like dead code sanitization. do_check_common() for subprogram N
- * may analyze many other subprograms. sanitize_insn_aux_data() clears all
- * temporary data after do_check_common() finds that subprogram N cannot be
- * verified independently. pass_cnt counts the number of times
- * do_check_common() was run and insn->aux->seen tells the pass number
- * insn_aux_data was touched. These variables are compared to clear temporary
- * data from failed pass. For testing and experiments do_check_common() can be
- * run multiple times even when prior attempt to verify is unsuccessful.
- *
- * Note that special handling is needed on !env->bypass_spec_v1 if this is
- * ever called outside of error path with subsequent program rejection.
- */
-static void sanitize_insn_aux_data(struct bpf_verifier_env *env)
-{
-	struct bpf_insn *insn = env->prog->insnsi;
-	struct bpf_insn_aux_data *aux;
-	int i, class;
-	for (i = 0; i < env->prog->len; i++) {
-		class = BPF_CLASS(insn[i].code);
-		if (class != BPF_LDX && class != BPF_STX)
-			continue;
-		aux = &env->insn_aux_data[i];
-		if (aux->seen != env->pass_cnt)
-			continue;
-		memset(aux, 0, offsetof(typeof(*aux), orig_idx));
-	}
-}
 static int do_check_common(struct bpf_verifier_env *env, int subprog)
 {
 	bool pop_log = !(env->log.level & BPF_LOG_LEVEL2);
 	if (!ret && pop_log)
 		bpf_vlog_reset(&env->log, 0);
 	free_states(env);
-	if (ret)
-		/* clean aux data in case subprog was rejected */
-		sanitize_insn_aux_data(env);
 	return ret;
 }

kernel/cgroup/cgroup-v1.c+1−3

@@ -1221,9 +1221,7 @@ int cgroup1_get_tree(struct fs_context *fc) · 1220 unmodified lines
1221	ret = cgroup_do_get_tree(fc);	1221	ret = cgroup_do_get_tree(fc);
1222		1222
1223	if (!ret && percpu_ref_is_dying(&ctx->root->cgrp.self.refcnt)) {	1223	if (!ret && percpu_ref_is_dying(&ctx->root->cgrp.self.refcnt)) {
1224	struct super_block *sb = fc->root->d_sb;	1224	fc_drop_locked(fc);
1225	dput(fc->root);
1226	deactivate_locked_super(sb);
1227	ret = 1;	1225	ret = 1;
1228	}	1226	}
1229		1227

kernel/dma/ops_helpers.c+10−2

  */
 #include <linux/dma-map-ops.h>
+static struct page *dma_common_vaddr_to_page(void *cpu_addr)
+{
+	if (is_vmalloc_addr(cpu_addr))
+		return vmalloc_to_page(cpu_addr);
+	return virt_to_page(cpu_addr);
+}
 /*
  * Create scatter-list for the already allocated DMA buffer.
  */
 		 void *cpu_addr, dma_addr_t dma_addr, size_t size,
 		 unsigned long attrs)
 {
-	struct page *page = virt_to_page(cpu_addr);
+	struct page *page = dma_common_vaddr_to_page(cpu_addr);
 	int ret;
 	ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
 	unsigned long user_count = vma_pages(vma);
 	unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
 	unsigned long off = vma->vm_pgoff;
+	struct page *page = dma_common_vaddr_to_page(cpu_addr);
 	int ret = -ENXIO;
 	vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
 		return -ENXIO;
 	return remap_pfn_range(vma, vma->vm_start,
-			page_to_pfn(virt_to_page(cpu_addr)) + vma->vm_pgoff,
+			page_to_pfn(page) + vma->vm_pgoff,
 			user_count << PAGE_SHIFT, vma->vm_page_prot);
 #else
 	return -ENXIO;

kernel/smpboot.c+1−1

@@ -47,7 +47,7 @@ void __init idle_thread_set_boot_cpu(void) · 46 unmodified lines
47	*	47	*
48	* Creates the thread if it does not exist.	48	* Creates the thread if it does not exist.
49	*/	49	*/
50	static inline void idle_init(unsigned int cpu)	50	static __always_inline void idle_init(unsigned int cpu)
51	{	51	{
52	struct task_struct *tsk = per_cpu(idle_threads, cpu);	52	struct task_struct *tsk = per_cpu(idle_threads, cpu);
53		53

kernel/time/posix-cpu-timers.c+5−5

 	if (!p)
 		goto out;
+	/* Protect timer list r/w in arm_timer() */
+	sighand = lock_task_sighand(p, &flags);
+	if (unlikely(sighand == NULL))
+		goto out;
 	/*
 	 * Fetch the current sample and update the timer's expiry time.
 	 */
 	bump_cpu_timer(timer, now);
-	/* Protect timer list r/w in arm_timer() */
-	sighand = lock_task_sighand(p, &flags);
-	if (unlikely(sighand == NULL))
-		goto out;
 	/*
 	 * Now re-arm for the new expiry time.
 	 */

kernel/time/timer.c+5−3

 	unsigned int		cpu;
 	bool			next_expiry_recalc;
 	bool			is_idle;
+	bool			timers_pending;
 	DECLARE_BITMAP(pending_map, WHEEL_SIZE);
 	struct hlist_head	vectors[WHEEL_SIZE];
 } ____cacheline_aligned;
 		 * can reevaluate the wheel:
 		 */
 		base->next_expiry = bucket_expiry;
+		base->timers_pending = true;
 		base->next_expiry_recalc = false;
 		trigger_dyntick_cpu(base, timer);
 	}
 	}
 	base->next_expiry_recalc = false;
+	base->timers_pending = !(next == base->clk + NEXT_TIMER_MAX_DELTA);
 	return next;
 }
 	struct timer_base *base = this_cpu_ptr(&timer_bases[BASE_STD]);
 	u64 expires = KTIME_MAX;
 	unsigned long nextevt;
-	bool is_max_delta;
 	/*
 	 * Pretend that there is no timer pending if the cpu is offline.
 	if (base->next_expiry_recalc)
 		base->next_expiry = __next_timer_interrupt(base);
 	nextevt = base->next_expiry;
-	is_max_delta = (nextevt == base->clk + NEXT_TIMER_MAX_DELTA);
 	/*
 	 * We have a fresh next event. Check whether we can forward the
 		expires = basem;
 		base->is_idle = false;
 	} else {
-		if (!is_max_delta)
+		if (base->timers_pending)
 			expires = basem + (u64)(nextevt - basej) * TICK_NSEC;
 		/*
 		 * If we expect to sleep more than a tick, mark the base idle.
 		base = per_cpu_ptr(&timer_bases[b], cpu);
 		base->clk = jiffies;
 		base->next_expiry = base->clk + NEXT_TIMER_MAX_DELTA;
+		base->timers_pending = false;
 		base->is_idle = false;
 	}
 	return 0;

kernel/trace/ftrace.c+3−2

 		 * infrastructure to do the synchronization, thus we must do it
 		 * ourselves.
 		 */
-		synchronize_rcu_tasks_rude();
+		if (old_hash != EMPTY_HASH)
+			synchronize_rcu_tasks_rude();
 		free_ftrace_hash(old_hash);
 	}
  */
 int register_ftrace_function(struct ftrace_ops *ops)
 {
-	int ret = -1;
+	int ret;
 	ftrace_ops_init(ops);

kernel/trace/ring_buffer.c+24−4

@@ -3880,10 +3880,30 @@ static bool rb_per_cpu_empty(struct ring_buffer_per_cpu *cpu_buffer) · 3879 unmodified lines
3880	if (unlikely(!head))	3880	if (unlikely(!head))
3881	return true;	3881	return true;
3882		3882
3883	return reader->read == rb_page_commit(reader) &&	3883	/* Reader should exhaust content in reader page */
3884	(commit == reader \|\|	3884	if (reader->read != rb_page_commit(reader))
3885	(commit == head &&	3885	return false;
3886	head->read == rb_page_commit(commit)));	3886
		3887	/*
		3888	* If writers are committing on the reader page, knowing all
		3889	* committed content has been read, the ring buffer is empty.
		3890	*/
		3891	if (commit == reader)
		3892	return true;
		3893
		3894	/*
		3895	* If writers are committing on a page other than reader page
		3896	* and head page, there should always be content to read.
		3897	*/
		3898	if (commit != head)
		3899	return false;
		3900
		3901	/*
		3902	* Writers are committing on the head page, we just need
		3903	* to care about there're committed data, and the reader will
		3904	* swap reader page with head page when it is to read data.
		3905	*/
		3906	return rb_page_commit(commit) == 0;
3887	}	3907	}
3888		3908
3889	/**	3909	/**

kernel/trace/trace.c+4−0

 	"\t            [:name=histname1]\n"
 	"\t            [:<handler>.<action>]\n"
 	"\t            [if <filter>]\n\n"
+	"\t    Note, special fields can be used as well:\n"
+	"\t            common_timestamp - to record current timestamp\n"
+	"\t            common_cpu - to record the CPU the event happened on\n"
+	"\n"
 	"\t    When a matching event is hit, an entry is added to a hash\n"
 	"\t    table using the key(s) and value(s) named, and the value of a\n"
 	"\t    sum called 'hitcount' is incremented.  Keys and values\n"

kernel/trace/trace_events_hist.c+16−6

 		 field->flags & HIST_FIELD_FL_ALIAS)
 		field_name = hist_field_name(field->operands[0], ++level);
 	else if (field->flags & HIST_FIELD_FL_CPU)
-		field_name = "cpu";
+		field_name = "common_cpu";
 	else if (field->flags & HIST_FIELD_FL_EXPR ||
 		 field->flags & HIST_FIELD_FL_VAR_REF) {
 		if (field->system) {
 		hist_data->enable_timestamps = true;
 		if (*flags & HIST_FIELD_FL_TIMESTAMP_USECS)
 			hist_data->attrs->ts_in_usecs = true;
-	} else if (strcmp(field_name, "cpu") == 0)
+	} else if (strcmp(field_name, "common_cpu") == 0)
 		*flags |= HIST_FIELD_FL_CPU;
 	else {
 		field = trace_find_event_field(file->event_call, field_name);
 		if (!field || !field->size) {
-			hist_err(tr, HIST_ERR_FIELD_NOT_FOUND, errpos(field_name));
+			/*
-			field = ERR_PTR(-EINVAL);
+			 * For backward compatibility, if field_name
-			goto out;
+			 * was "cpu", then we treat this the same as
+			 * common_cpu.
+			 */
+			if (strcmp(field_name, "cpu") == 0) {
+				*flags |= HIST_FIELD_FL_CPU;
+			} else {
+				hist_err(tr, HIST_ERR_FIELD_NOT_FOUND,
+					 errpos(field_name));
+				field = ERR_PTR(-EINVAL);
+				goto out;
+			}
 		}
 	}
  out:
 		seq_printf(m, "%s=", hist_field->var.name);
 	if (hist_field->flags & HIST_FIELD_FL_CPU)
-		seq_puts(m, "cpu");
+		seq_puts(m, "common_cpu");
 	else if (field_name) {
 		if (hist_field->flags & HIST_FIELD_FL_VAR_REF ||
 		    hist_field->flags & HIST_FIELD_FL_ALIAS)

kernel/trace/trace_events_synth.c+3−5

 	dyn_event_init(&event->devent, &synth_event_ops);
 	for (i = 0, j = 0; i < n_fields; i++) {
+		fields[i]->field_pos = i;
 		event->fields[i] = fields[i];
-		if (fields[i]->is_dynamic) {
+		if (fields[i]->is_dynamic)
-			event->dynamic_fields[j] = fields[i];
-			event->dynamic_fields[j]->field_pos = i;
 			event->dynamic_fields[j++] = fields[i];
-			event->n_dynamic_fields++;
-		}
 	}
+	event->n_dynamic_fields = j;
 	event->n_fields = n_fields;
  out:
 	return event;

kernel/trace/trace_synth.h+1−1

 	char *name;
 	size_t size;
 	unsigned int offset;
+	unsigned int field_pos;
 	bool is_signed;
 	bool is_string;
 	bool is_dynamic;
-	bool field_pos;
 };
 struct synth_event {

kernel/tracepoint.c+1−1

 	 * a pointer to it.  This array is referenced by __DO_TRACE from
 	 * include/linux/tracepoint.h using rcu_dereference_sched().
 	 */
-	rcu_assign_pointer(tp->funcs, tp_funcs);
 	tracepoint_update_call(tp, tp_funcs, false);
+	rcu_assign_pointer(tp->funcs, tp_funcs);
 	static_key_enable(&tp->key);
 	release_probes(old);

kernel/workqueue.c+13−7

 						  unbound_release_work);
 	struct workqueue_struct *wq = pwq->wq;
 	struct worker_pool *pool = pwq->pool;
-	bool is_last;
+	bool is_last = false;
-	if (WARN_ON_ONCE(!(wq->flags & WQ_UNBOUND)))
+	/*
-		return;
+	 * when @pwq is not linked, it doesn't hold any reference to the
+	 * @wq, and @wq is invalid to access.
+	 */
+	if (!list_empty(&pwq->pwqs_node)) {
+		if (WARN_ON_ONCE(!(wq->flags & WQ_UNBOUND)))
+			return;
-	mutex_lock(&wq->mutex);
+		mutex_lock(&wq->mutex);
-	list_del_rcu(&pwq->pwqs_node);
+		list_del_rcu(&pwq->pwqs_node);
-	is_last = list_empty(&wq->pwqs);
+		is_last = list_empty(&wq->pwqs);
-	mutex_unlock(&wq->mutex);
+		mutex_unlock(&wq->mutex);
+	}
 	mutex_lock(&wq_pool_mutex);
 	put_unbound_pool(pool);

lib/Kconfig+0−3

@@ -683,9 +683,6 @@ config PARMAN · 682 unmodified lines
683	config OBJAGG	683	config OBJAGG
684	tristate "objagg" if COMPILE_TEST	684	tristate "objagg" if COMPILE_TEST
685		685
686	config STRING_SELFTEST
687	tristate "Test string functions"
688
689	endmenu	686	endmenu
690		687
691	config GENERIC_IOREMAP	688	config GENERIC_IOREMAP

lib/Kconfig.debug+3−0

@@ -2180,6 +2180,9 @@ config ASYNC_RAID6_TEST · 2179 unmodified lines
2180	config TEST_HEXDUMP	2180	config TEST_HEXDUMP
2181	tristate "Test functions located in the hexdump module at runtime"	2181	tristate "Test functions located in the hexdump module at runtime"
2182		2182
		2183	config STRING_SELFTEST
		2184	tristate "Test string functions at runtime"
		2185
2183	config TEST_STRING_HELPERS	2186	config TEST_STRING_HELPERS
2184	tristate "Test functions located in the string_helpers module at runtime"	2187	tristate "Test functions located in the string_helpers module at runtime"
2185		2188

mm/backing-dev.c+1−1

 	blkcg_unpin_online(blkcg);
 	fprop_local_destroy_percpu(&wb->memcg_completions);
-	percpu_ref_exit(&wb->refcnt);
 	spin_lock_irq(&cgwb_lock);
 	list_del(&wb->offline_node);
 	spin_unlock_irq(&cgwb_lock);
+	percpu_ref_exit(&wb->refcnt);
 	wb_exit(wb);
 	WARN_ON_ONCE(!list_empty(&wb->b_attached));
 	kfree_rcu(wb, rcu);

mm/kfence/core.c+16−3

@@ -733,6 +733,22 @@ void kfence_shutdown_cache(struct kmem_cache *s) · 732 unmodified lines
733		733
734	void __kfence_alloc(struct kmem_cache s, size_t size, gfp_t flags)	734	void __kfence_alloc(struct kmem_cache s, size_t size, gfp_t flags)
735	{	735	{
		736	/*
		737	* Perform size check before switching kfence_allocation_gate, so that
		738	* we don't disable KFENCE without making an allocation.
		739	*/
		740	if (size > PAGE_SIZE)
		741	return NULL;
		742
		743	/*
		744	* Skip allocations from non-default zones, including DMA. We cannot
		745	* guarantee that pages in the KFENCE pool will have the requested
		746	* properties (e.g. reside in DMAable memory).
		747	*/
		748	if ((flags & GFP_ZONEMASK) \|\|
		749	(s->flags & (SLAB_CACHE_DMA \| SLAB_CACHE_DMA32)))
		750	return NULL;
		751
736	/*	752	/*
737	* allocation_gate only needs to become non-zero, so it doesn't make	753	* allocation_gate only needs to become non-zero, so it doesn't make
738	* sense to continue writing to it and pay the associated contention	754	* sense to continue writing to it and pay the associated contention
@@ -757,9 +773,6 @@ void __kfence_alloc(struct kmem_cache s, size_t size, gfp_t flags) · 18 unmodified lines
757	if (!READ_ONCE(kfence_enabled))	773	if (!READ_ONCE(kfence_enabled))
758	return NULL;	774	return NULL;
759		775
760	if (size > PAGE_SIZE)
761	return NULL;
762
763	return kfence_guarded_alloc(s, size, flags);	776	return kfence_guarded_alloc(s, size, flags);
764	}	777	}
765		778

mm/kfence/kfence_test.c+1−1

@@ -852,7 +852,7 @@ static void kfence_test_exit(void) · 851 unmodified lines
852	tracepoint_synchronize_unregister();	852	tracepoint_synchronize_unregister();
853	}	853	}
854		854
855	late_initcall(kfence_test_init);	855	late_initcall_sync(kfence_test_init);
856	module_exit(kfence_test_exit);	856	module_exit(kfence_test_exit);
857		857
858	MODULE_LICENSE("GPL v2");	858	MODULE_LICENSE("GPL v2");

mm/memblock.c+2−1

@@ -947,7 +947,8 @@ static bool should_skip_region(struct memblock_type *type, · 946 unmodified lines
947	return true;	947	return true;
948		948
949	/* skip hotpluggable memory regions if needed */	949	/* skip hotpluggable memory regions if needed */
950	if (movable_node_is_enabled() && memblock_is_hotpluggable(m))	950	if (movable_node_is_enabled() && memblock_is_hotpluggable(m) &&
		951	!(flags & MEMBLOCK_HOTPLUG))
951	return true;	952	return true;
952		953
953	/* if we want mirror memory skip non-mirror memory regions */	954	/* if we want mirror memory skip non-mirror memory regions */

mm/memcontrol.c+2−1

@@ -3574,7 +3574,8 @@ static unsigned long mem_cgroup_usage(struct mem_cgroup *memcg, bool swap) · 3573 unmodified lines
3574	unsigned long val;	3574	unsigned long val;
3575		3575
3576	if (mem_cgroup_is_root(memcg)) {	3576	if (mem_cgroup_is_root(memcg)) {
3577	cgroup_rstat_flush(memcg->css.cgroup);	3577	/* mem_cgroup_threshold() calls here from irqsafe context */
		3578	cgroup_rstat_flush_irqsafe(memcg->css.cgroup);
3578	val = memcg_page_state(memcg, NR_FILE_PAGES) +	3579	val = memcg_page_state(memcg, NR_FILE_PAGES) +
3579	memcg_page_state(memcg, NR_ANON_MAPPED);	3580	memcg_page_state(memcg, NR_ANON_MAPPED);
3580	if (swap)	3581	if (swap)

mm/memory.c+10−1

@@ -4026,8 +4026,17 @@ vm_fault_t finish_fault(struct vm_fault *vmf) · 4025 unmodified lines
4026	return ret;	4026	return ret;
4027	}	4027	}
4028		4028
4029	if (unlikely(pte_alloc(vma->vm_mm, vmf->pmd)))	4029	if (vmf->prealloc_pte) {
		4030	vmf->ptl = pmd_lock(vma->vm_mm, vmf->pmd);
		4031	if (likely(pmd_none(*vmf->pmd))) {
		4032	mm_inc_nr_ptes(vma->vm_mm);
		4033	pmd_populate(vma->vm_mm, vmf->pmd, vmf->prealloc_pte);
		4034	vmf->prealloc_pte = NULL;
		4035	}
		4036	spin_unlock(vmf->ptl);
		4037	} else if (unlikely(pte_alloc(vma->vm_mm, vmf->pmd))) {
4030	return VM_FAULT_OOM;	4038	return VM_FAULT_OOM;
		4039	}
4031	}	4040	}
4032		4041
4033	/* See comment in handle_pte_fault() */	4042	/* See comment in handle_pte_fault() */

mm/migrate.c+1−1

@@ -2068,7 +2068,7 @@ int migrate_misplaced_page(struct page page, struct vm_area_struct vma, · 2067 unmodified lines
2068	LIST_HEAD(migratepages);	2068	LIST_HEAD(migratepages);
2069	new_page_t *new;	2069	new_page_t *new;
2070	bool compound;	2070	bool compound;
2071	unsigned int nr_pages = thp_nr_pages(page);	2071	int nr_pages = thp_nr_pages(page);
2072		2072
2073	/*	2073	/*
2074	* PTE mapped THP or HugeTLB page can't reach here so the page could	2074	* PTE mapped THP or HugeTLB page can't reach here so the page could

mm/mmap_lock.c+2−2

@@ -156,14 +156,14 @@ static inline void put_memcg_path_buf(void) · 155 unmodified lines
156	#define TRACE_MMAP_LOCK_EVENT(type, mm, ...) \	156	#define TRACE_MMAP_LOCK_EVENT(type, mm, ...) \
157	do { \	157	do { \
158	const char *memcg_path; \	158	const char *memcg_path; \
159	preempt_disable(); \	159	local_lock(&memcg_paths.lock); \
160	memcg_path = get_mm_memcg_path(mm); \	160	memcg_path = get_mm_memcg_path(mm); \
161	trace_mmap_lock_##type(mm, \	161	trace_mmap_lock_##type(mm, \
162	memcg_path != NULL ? memcg_path : "", \	162	memcg_path != NULL ? memcg_path : "", \
163	##__VA_ARGS__); \	163	##__VA_ARGS__); \
164	if (likely(memcg_path != NULL)) \	164	if (likely(memcg_path != NULL)) \
165	put_memcg_path_buf(); \	165	put_memcg_path_buf(); \
166	preempt_enable(); \	166	local_unlock(&memcg_paths.lock); \
167	} while (0)	167	} while (0)
168		168
169	#else /* !CONFIG_MEMCG */	169	#else /* !CONFIG_MEMCG */

mm/page_alloc.c+16−13

 	}
 #endif
-	if (_init_on_alloc_enabled_early) {
+	if ((_init_on_alloc_enabled_early || _init_on_free_enabled_early) &&
-		if (page_poisoning_requested)
+	    page_poisoning_requested) {
-			pr_info("mem auto-init: CONFIG_PAGE_POISONING is on, "
+		pr_info("mem auto-init: CONFIG_PAGE_POISONING is on, "
-				"will take precedence over init_on_alloc\n");
+			"will take precedence over init_on_alloc and init_on_free\n");
-		else
+		_init_on_alloc_enabled_early = false;
-			static_branch_enable(&init_on_alloc);
+		_init_on_free_enabled_early = false;
-	}
-	if (_init_on_free_enabled_early) {
-		if (page_poisoning_requested)
-			pr_info("mem auto-init: CONFIG_PAGE_POISONING is on, "
-				"will take precedence over init_on_free\n");
-		else
-			static_branch_enable(&init_on_free);
 	}
+	if (_init_on_alloc_enabled_early)
+		static_branch_enable(&init_on_alloc);
+	else
+		static_branch_disable(&init_on_alloc);
+	if (_init_on_free_enabled_early)
+		static_branch_enable(&init_on_free);
+	else
+		static_branch_disable(&init_on_free);
 #ifdef CONFIG_DEBUG_PAGEALLOC
 	if (!debug_pagealloc_enabled())
 		return;

mm/secretmem.c+1−0

@@ -152,6 +152,7 @@ static void secretmem_freepage(struct page *page) · 151 unmodified lines
152	}	152	}
153		153
154	const struct address_space_operations secretmem_aops = {	154	const struct address_space_operations secretmem_aops = {
		155	.set_page_dirty = __set_page_dirty_no_writeback,
155	.freepage = secretmem_freepage,	156	.freepage = secretmem_freepage,
156	.migratepage = secretmem_migratepage,	157	.migratepage = secretmem_migratepage,
157	.isolate_page = secretmem_isolate_page,	158	.isolate_page = secretmem_isolate_page,

mm/slab.h+1−1

@@ -346,7 +346,7 @@ static inline void memcg_slab_free_hook(struct kmem_cache *s_orig, · 345 unmodified lines
346	continue;	346	continue;
347		347
348	page = virt_to_head_page(p[i]);	348	page = virt_to_head_page(p[i]);
349	objcgs = page_objcgs(page);	349	objcgs = page_objcgs_check(page);
350	if (!objcgs)	350	if (!objcgs)
351	continue;	351	continue;
352		352

mm/slub.c+12−10

 	struct kmem_cache *s;
 };
+static inline void free_nonslab_page(struct page *page)
+{
+	unsigned int order = compound_order(page);
+	VM_BUG_ON_PAGE(!PageCompound(page), page);
+	kfree_hook(page_address(page));
+	mod_lruvec_page_state(page, NR_SLAB_UNRECLAIMABLE_B, -(PAGE_SIZE << order));
+	__free_pages(page, order);
+}
 /*
  * This function progressively scans the array with free objects (with
  * a limited look ahead) and extract objects belonging to the same
 	if (!s) {
 		/* Handle kalloc'ed objects */
 		if (unlikely(!PageSlab(page))) {
-			BUG_ON(!PageCompound(page));
+			free_nonslab_page(page);
-			kfree_hook(object);
-			__free_pages(page, compound_order(page));
 			p[size] = NULL; /* mark object processed */
 			return size;
 		}
 	page = virt_to_head_page(x);
 	if (unlikely(!PageSlab(page))) {
-		unsigned int order = compound_order(page);
+		free_nonslab_page(page);
-		BUG_ON(!PageCompound(page));
-		kfree_hook(object);
-		mod_lruvec_page_state(page, NR_SLAB_UNRECLAIMABLE_B,
-				      -(PAGE_SIZE << order));
-		__free_pages(page, order);
 		return;
 	}
 	slab_free(page->slab_cache, page, object, NULL, 1, _RET_IP_);

net/bpf/test_run.c+3−0

@@ -701,6 +701,9 @@ int bpf_prog_test_run_xdp(struct bpf_prog prog, const union bpf_attr kattr, · 700 unmodified lines
701	void *data;	701	void *data;
702	int ret;	702	int ret;
703		703
		704	if (prog->expected_attach_type == BPF_XDP_DEVMAP \|\|
		705	prog->expected_attach_type == BPF_XDP_CPUMAP)
		706	return -EINVAL;
704	if (kattr->test.ctx_in \|\| kattr->test.ctx_out)	707	if (kattr->test.ctx_in \|\| kattr->test.ctx_out)
705	return -EINVAL;	708	return -EINVAL;
706		709

net/bridge/br_fdb.c+1−1

@@ -780,7 +780,7 @@ int br_fdb_replay(const struct net_device br_dev, const struct net_device dev, · 779 unmodified lines
780	struct net_device *dst_dev;	780	struct net_device *dst_dev;
781		781
782	dst_dev = dst ? dst->dev : br->dev;	782	dst_dev = dst ? dst->dev : br->dev;
783	if (dst_dev != br_dev && dst_dev != dev)	783	if (dst_dev && dst_dev != dev)
784	continue;	784	continue;
785		785
786	err = br_fdb_replay_one(nb, fdb, dst_dev, action, ctx);	786	err = br_fdb_replay_one(nb, fdb, dst_dev, action, ctx);

net/caif/caif_socket.c+2−1

@@ -539,7 +539,8 @@ static int caif_seqpkt_sendmsg(struct socket sock, struct msghdr msg, · 538 unmodified lines
539	goto err;	539	goto err;
540		540
541	ret = -EINVAL;	541	ret = -EINVAL;
542	if (unlikely(msg->msg_iter.iov->iov_base == NULL))	542	if (unlikely(msg->msg_iter.nr_segs == 0) \|\|
		543	unlikely(msg->msg_iter.iov->iov_base == NULL))
543	goto err;	544	goto err;
544	noblock = msg->msg_flags & MSG_DONTWAIT;	545	noblock = msg->msg_flags & MSG_DONTWAIT;
545		546

net/can/j1939/transport.c+8−3

 static bool j1939_session_deactivate(struct j1939_session *session)
 {
+	struct j1939_priv *priv = session->priv;
 	bool active;
-	j1939_session_list_lock(session->priv);
+	j1939_session_list_lock(priv);
+	/* This function should be called with a session ref-count of at
+	 * least 2.
+	 */
+	WARN_ON_ONCE(kref_read(&session->kref) < 2);
 	active = j1939_session_deactivate_locked(session);
-	j1939_session_list_unlock(session->priv);
+	j1939_session_list_unlock(priv);
 	return active;
 }
 		if (!session->transmission)
 			j1939_tp_schedule_txtimer(session, 0);
 	} else {
-		j1939_tp_set_rxtimeout(session, 250);
+		j1939_tp_set_rxtimeout(session, 750);
 	}
 	session->last_cmd = 0xff;
 	consume_skb(se_skb);

net/can/raw.c+18−2

 				return -EFAULT;
 		}
+		rtnl_lock();
 		lock_sock(sk);
-		if (ro->bound && ro->ifindex)
+		if (ro->bound && ro->ifindex) {
 			dev = dev_get_by_index(sock_net(sk), ro->ifindex);
+			if (!dev) {
+				if (count > 1)
+					kfree(filter);
+				err = -ENODEV;
+				goto out_fil;
+			}
+		}
 		if (ro->bound) {
 			/* (try to) register the new filters */
 			dev_put(dev);
 		release_sock(sk);
+		rtnl_unlock();
 		break;
 		err_mask &= CAN_ERR_MASK;
+		rtnl_lock();
 		lock_sock(sk);
-		if (ro->bound && ro->ifindex)
+		if (ro->bound && ro->ifindex) {
 			dev = dev_get_by_index(sock_net(sk), ro->ifindex);
+			if (!dev) {
+				err = -ENODEV;
+				goto out_err;
+			}
+		}
 		/* remove current error mask */
 		if (ro->bound) {
 			dev_put(dev);
 		release_sock(sk);
+		rtnl_unlock();
 		break;

net/core/dev.c+26−8

 #include <trace/events/napi.h>
 #include <trace/events/net.h>
 #include <trace/events/skb.h>
+#include <trace/events/qdisc.h>
 #include <linux/inetdevice.h>
 #include <linux/cpu_rmap.h>
 #include <linux/static_key.h>
 	}
 }
+static int dev_qdisc_enqueue(struct sk_buff *skb, struct Qdisc *q,
+			     struct sk_buff **to_free,
+			     struct netdev_queue *txq)
+{
+	int rc;
+	rc = q->enqueue(skb, q, to_free) & NET_XMIT_MASK;
+	if (rc == NET_XMIT_SUCCESS)
+		trace_qdisc_enqueue(q, txq, skb);
+	return rc;
+}
 static inline int __dev_xmit_skb(struct sk_buff *skb, struct Qdisc *q,
 				 struct net_device *dev,
 				 struct netdev_queue *txq)
 			 * of q->seqlock to protect from racing with requeuing.
 			 */
 			if (unlikely(!nolock_qdisc_is_empty(q))) {
-				rc = q->enqueue(skb, q, &to_free) &
+				rc = dev_qdisc_enqueue(skb, q, &to_free, txq);
-					NET_XMIT_MASK;
 				__qdisc_run(q);
 				qdisc_run_end(q);
 			return NET_XMIT_SUCCESS;
 		}
-		rc = q->enqueue(skb, q, &to_free) & NET_XMIT_MASK;
+		rc = dev_qdisc_enqueue(skb, q, &to_free, txq);
 		qdisc_run(q);
 no_lock_out:
 		qdisc_run_end(q);
 		rc = NET_XMIT_SUCCESS;
 	} else {
-		rc = q->enqueue(skb, q, &to_free) & NET_XMIT_MASK;
+		rc = dev_qdisc_enqueue(skb, q, &to_free, txq);
 		if (qdisc_run_begin(q)) {
 			if (unlikely(contended)) {
 				spin_unlock(&q->busylock);
 	struct net_device *dev;
 	int err, fd;
+	rtnl_lock();
 	dev = dev_get_by_index(net, attr->link_create.target_ifindex);
-	if (!dev)
+	if (!dev) {
+		rtnl_unlock();
 		return -EINVAL;
+	}
 	link = kzalloc(sizeof(*link), GFP_USER);
 	if (!link) {
 		err = -ENOMEM;
-		goto out_put_dev;
+		goto unlock;
 	}
 	bpf_link_init(&link->link, BPF_LINK_TYPE_XDP, &bpf_xdp_link_lops, prog);
 	err = bpf_link_prime(&link->link, &link_primer);
 	if (err) {
 		kfree(link);
-		goto out_put_dev;
+		goto unlock;
 	}
-	rtnl_lock();
 	err = dev_xdp_attach_link(dev, NULL, link);
 	rtnl_unlock();
 	if (err) {
+		link->dev = NULL;
 		bpf_link_cleanup(&link_primer);
 		goto out_put_dev;
 	}
 	dev_put(dev);
 	return fd;
+unlock:
+	rtnl_unlock();
 out_put_dev:
 	dev_put(dev);
 	return err;

net/core/devlink.c+2−8

 	switch (attrs->flavour) {
 	case DEVLINK_PORT_FLAVOUR_PHYSICAL:
-	case DEVLINK_PORT_FLAVOUR_VIRTUAL:
 		n = snprintf(name, len, "p%u", attrs->phys.port_number);
 		if (n < len && attrs->split)
 			n += snprintf(name + n, len - n, "s%u",
 				      attrs->phys.split_subport_number);
-		if (!attrs->split)
-			n = snprintf(name, len, "p%u", attrs->phys.port_number);
-		else
-			n = snprintf(name, len, "p%us%u",
-				     attrs->phys.port_number,
-				     attrs->phys.split_subport_number);
 		break;
 	case DEVLINK_PORT_FLAVOUR_CPU:
 	case DEVLINK_PORT_FLAVOUR_DSA:
 		n = snprintf(name, len, "pf%usf%u", attrs->pci_sf.pf,
 			     attrs->pci_sf.sf);
 		break;
+	case DEVLINK_PORT_FLAVOUR_VIRTUAL:
+		return -EOPNOTSUPP;
 	}
 	if (n >= len)

net/core/flow_dissector.c+9−9

 }
 EXPORT_SYMBOL(flow_get_u32_dst);
-/* Sort the source and destination IP (and the ports if the IP are the same),
+/* Sort the source and destination IP and the ports,
  * to have consistent hash within the two directions
  */
 static inline void __flow_hash_consistentify(struct flow_keys *keys)
 	case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
 		addr_diff = (__force u32)keys->addrs.v4addrs.dst -
 			    (__force u32)keys->addrs.v4addrs.src;
-		if ((addr_diff < 0) ||
+		if (addr_diff < 0)
-		    (addr_diff == 0 &&
-		     ((__force u16)keys->ports.dst <
-		      (__force u16)keys->ports.src))) {
 			swap(keys->addrs.v4addrs.src, keys->addrs.v4addrs.dst);
+		if ((__force u16)keys->ports.dst <
+		    (__force u16)keys->ports.src) {
 			swap(keys->ports.src, keys->ports.dst);
 		}
 		break;
 		addr_diff = memcmp(&keys->addrs.v6addrs.dst,
 				   &keys->addrs.v6addrs.src,
 				   sizeof(keys->addrs.v6addrs.dst));
-		if ((addr_diff < 0) ||
+		if (addr_diff < 0) {
-		    (addr_diff == 0 &&
-		     ((__force u16)keys->ports.dst <
-		      (__force u16)keys->ports.src))) {
 			for (i = 0; i < 4; i++)
 				swap(keys->addrs.v6addrs.src.s6_addr32[i],
 				     keys->addrs.v6addrs.dst.s6_addr32[i]);
+		}
+		if ((__force u16)keys->ports.dst <
+		    (__force u16)keys->ports.src) {
 			swap(keys->ports.src, keys->ports.dst);
 		}
 		break;

net/core/skbuff.c+16−2

 	if (skb->cloned &&
 	    atomic_sub_return(skb->nohdr ? (1 << SKB_DATAREF_SHIFT) + 1 : 1,
 			      &shinfo->dataref))
-		return;
+		goto exit;
 	skb_zcopy_clear(skb, true);
 		kfree_skb_list(shinfo->frag_list);
 	skb_free_head(skb);
+exit:
+	/* When we clone an SKB we copy the reycling bit. The pp_recycle
+	 * bit is only set on the head though, so in order to avoid races
+	 * while trying to recycle fragments on __skb_frag_unref() we need
+	 * to make one SKB responsible for triggering the recycle path.
+	 * So disable the recycling bit if an SKB is cloned and we have
+	 * additional references to to the fragmented part of the SKB.
+	 * Eventually the last SKB will have the recycling bit set and it's
+	 * dataref set to 0, which will trigger the recycling
+	 */
+	skb->pp_recycle = 0;
 }
 /*
 	if (!from->head_frag ||
 	    skb_headlen(from) < L1_CACHE_BYTES ||
-	    skb_shinfo(from)->nr_frags >= MAX_SKB_FRAGS)
+	    skb_shinfo(from)->nr_frags >= MAX_SKB_FRAGS) {
 		hlen = skb_headlen(from);
+		if (!hlen)
+			hlen = from->len;
+	}
 	if (skb_has_frag_list(from))
 		hlen = from->len;

net/core/skmsg.c+39−16

 	if (skb_linearize(skb))
 		return -EAGAIN;
 	num_sge = skb_to_sgvec(skb, msg->sg.data, 0, skb->len);
-	if (unlikely(num_sge < 0)) {
+	if (unlikely(num_sge < 0))
-		kfree(msg);
 		return num_sge;
-	}
 	copied = skb->len;
 	msg->sg.start = 0;
 {
 	struct sock *sk = psock->sk;
 	struct sk_msg *msg;
+	int err;
 	/* If we are receiving on the same sock skb->sk is already assigned,
 	 * skip memory accounting and owner transition seeing it already set
 	 * into user buffers.
 	 */
 	skb_set_owner_r(skb, sk);
-	return sk_psock_skb_ingress_enqueue(skb, psock, sk, msg);
+	err = sk_psock_skb_ingress_enqueue(skb, psock, sk, msg);
+	if (err < 0)
+		kfree(msg);
+	return err;
 }
 /* Puts an skb on the ingress queue of the socket already assigned to the
 {
 	struct sk_msg *msg = kzalloc(sizeof(*msg), __GFP_NOWARN | GFP_ATOMIC);
 	struct sock *sk = psock->sk;
+	int err;
 	if (unlikely(!msg))
 		return -EAGAIN;
 	sk_msg_init(msg);
 	skb_set_owner_r(skb, sk);
-	return sk_psock_skb_ingress_enqueue(skb, psock, sk, msg);
+	err = sk_psock_skb_ingress_enqueue(skb, psock, sk, msg);
+	if (err < 0)
+		kfree(msg);
+	return err;
 }
 static int sk_psock_handle_skb(struct sk_psock *psock, struct sk_buff *skb,
 	return sk_psock_skb_ingress(psock, skb);
 }
-static void sock_drop(struct sock *sk, struct sk_buff *skb)
+static void sk_psock_skb_state(struct sk_psock *psock,
+			       struct sk_psock_work_state *state,
+			       struct sk_buff *skb,
+			       int len, int off)
 {
-	sk_drops_add(sk, skb);
+	spin_lock_bh(&psock->ingress_lock);
-	kfree_skb(skb);
+	if (sk_psock_test_state(psock, SK_PSOCK_TX_ENABLED)) {
+		state->skb = skb;
+		state->len = len;
+		state->off = off;
+	} else {
+		sock_drop(psock->sk, skb);
+	}
+	spin_unlock_bh(&psock->ingress_lock);
 }
 static void sk_psock_backlog(struct work_struct *work)
 {
 	struct sk_psock *psock = container_of(work, struct sk_psock, work);
 	struct sk_psock_work_state *state = &psock->work_state;
-	struct sk_buff *skb;
+	struct sk_buff *skb = NULL;
 	bool ingress;
 	u32 len, off;
 	int ret;
 	mutex_lock(&psock->work_mutex);
-	if (state->skb) {
+	if (unlikely(state->skb)) {
+		spin_lock_bh(&psock->ingress_lock);
 		skb = state->skb;
 		len = state->len;
 		off = state->off;
 		state->skb = NULL;
-		goto start;
+		spin_unlock_bh(&psock->ingress_lock);
 	}
+	if (skb)
+		goto start;
 	while ((skb = skb_dequeue(&psock->ingress_skb))) {
 		len = skb->len;
 							  len, ingress);
 			if (ret <= 0) {
 				if (ret == -EAGAIN) {
-					state->skb = skb;
+					sk_psock_skb_state(psock, state, skb,
-					state->len = len;
+							   len, off);
-					state->off = off;
 					goto end;
 				}
 				/* Hard errors break pipe and stop xmit. */
 		skb_bpf_redirect_clear(skb);
 		sock_drop(psock->sk, skb);
 	}
+	kfree_skb(psock->work_state.skb);
+	/* We null the skb here to ensure that calls to sk_psock_backlog
+	 * do not pick up the free'd skb.
+	 */
+	psock->work_state.skb = NULL;
 	__sk_psock_purge_ingress_msg(psock);
 }
 void sk_psock_drop(struct sock *sk, struct sk_psock *psock)
 {
-	sk_psock_stop(psock, false);
 	write_lock_bh(&sk->sk_callback_lock);
 	sk_psock_restore_proto(sk, psock);
 	rcu_assign_sk_user_data(sk, NULL);
 		sk_psock_stop_verdict(sk, psock);
 	write_unlock_bh(&sk->sk_callback_lock);
+	sk_psock_stop(psock, false);
 	INIT_RCU_WORK(&psock->rwork, sk_psock_destroy);
 	queue_rcu_work(system_wq, &psock->rwork);
 }

net/decnet/af_decnet.c+12−15

 static int dn_confirm_accept(struct sock *sk, long *timeo, gfp_t allocation)
 {
 	struct dn_scp *scp = DN_SK(sk);
-	DEFINE_WAIT(wait);
+	DEFINE_WAIT_FUNC(wait, woken_wake_function);
 	int err;
 	if (scp->state != DN_CR)
 	scp->segsize_loc = dst_metric_advmss(__sk_dst_get(sk));
 	dn_send_conn_conf(sk, allocation);
-	prepare_to_wait(sk_sleep(sk), &wait, TASK_INTERRUPTIBLE);
+	add_wait_queue(sk_sleep(sk), &wait);
 	for(;;) {
 		release_sock(sk);
 		if (scp->state == DN_CC)
-			*timeo = schedule_timeout(*timeo);
+			*timeo = wait_woken(&wait, TASK_INTERRUPTIBLE, *timeo);
 		lock_sock(sk);
 		err = 0;
 		if (scp->state == DN_RUN)
 		err = -EAGAIN;
 		if (!*timeo)
 			break;
-		prepare_to_wait(sk_sleep(sk), &wait, TASK_INTERRUPTIBLE);
 	}
-	finish_wait(sk_sleep(sk), &wait);
+	remove_wait_queue(sk_sleep(sk), &wait);
 	if (err == 0) {
 		sk->sk_socket->state = SS_CONNECTED;
 	} else if (scp->state != DN_CC) {
 static int dn_wait_run(struct sock *sk, long *timeo)
 {
 	struct dn_scp *scp = DN_SK(sk);
-	DEFINE_WAIT(wait);
+	DEFINE_WAIT_FUNC(wait, woken_wake_function);
 	int err = 0;
 	if (scp->state == DN_RUN)
 	if (!*timeo)
 		return -EALREADY;
-	prepare_to_wait(sk_sleep(sk), &wait, TASK_INTERRUPTIBLE);
+	add_wait_queue(sk_sleep(sk), &wait);
 	for(;;) {
 		release_sock(sk);
 		if (scp->state == DN_CI || scp->state == DN_CC)
-			*timeo = schedule_timeout(*timeo);
+			*timeo = wait_woken(&wait, TASK_INTERRUPTIBLE, *timeo);
 		lock_sock(sk);
 		err = 0;
 		if (scp->state == DN_RUN)
 		err = -ETIMEDOUT;
 		if (!*timeo)
 			break;
-		prepare_to_wait(sk_sleep(sk), &wait, TASK_INTERRUPTIBLE);
 	}
-	finish_wait(sk_sleep(sk), &wait);
+	remove_wait_queue(sk_sleep(sk), &wait);
 out:
 	if (err == 0) {
 		sk->sk_socket->state = SS_CONNECTED;
 static struct sk_buff *dn_wait_for_connect(struct sock *sk, long *timeo)
 {
-	DEFINE_WAIT(wait);
+	DEFINE_WAIT_FUNC(wait, woken_wake_function);
 	struct sk_buff *skb = NULL;
 	int err = 0;
-	prepare_to_wait(sk_sleep(sk), &wait, TASK_INTERRUPTIBLE);
+	add_wait_queue(sk_sleep(sk), &wait);
 	for(;;) {
 		release_sock(sk);
 		skb = skb_dequeue(&sk->sk_receive_queue);
 		if (skb == NULL) {
-			*timeo = schedule_timeout(*timeo);
+			*timeo = wait_woken(&wait, TASK_INTERRUPTIBLE, *timeo);
 			skb = skb_dequeue(&sk->sk_receive_queue);
 		}
 		lock_sock(sk);
 		err = -EAGAIN;
 		if (!*timeo)
 			break;
-		prepare_to_wait(sk_sleep(sk), &wait, TASK_INTERRUPTIBLE);
 	}
-	finish_wait(sk_sleep(sk), &wait);
+	remove_wait_queue(sk_sleep(sk), &wait);
 	return skb == NULL ? ERR_PTR(err) : skb;
 }

net/dsa/slave.c+9−5

 	struct dsa_slave_priv *p = netdev_priv(slave);
 	const struct dsa_port *cpu_dp = dp->cpu_dp;
 	struct net_device *master = cpu_dp->master;
+	const struct dsa_switch *ds = dp->ds;
 	slave->needed_headroom = cpu_dp->tag_ops->needed_headroom;
 	slave->needed_tailroom = cpu_dp->tag_ops->needed_tailroom;
 	slave->needed_tailroom += master->needed_tailroom;
 	p->xmit = cpu_dp->tag_ops->xmit;
+	slave->features = master->vlan_features | NETIF_F_HW_TC;
+	if (ds->ops->port_vlan_add && ds->ops->port_vlan_del)
+		slave->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
+	slave->hw_features |= NETIF_F_HW_TC;
+	slave->features |= NETIF_F_LLTX;
+	if (slave->needed_tailroom)
+		slave->features &= ~(NETIF_F_SG | NETIF_F_FRAGLIST);
 }
 static struct lock_class_key dsa_slave_netdev_xmit_lock_key;
 	if (slave_dev == NULL)
 		return -ENOMEM;
-	slave_dev->features = master->vlan_features | NETIF_F_HW_TC;
-	if (ds->ops->port_vlan_add && ds->ops->port_vlan_del)
-		slave_dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
-	slave_dev->hw_features |= NETIF_F_HW_TC;
-	slave_dev->features |= NETIF_F_LLTX;
 	slave_dev->ethtool_ops = &dsa_slave_ethtool_ops;
 	if (!is_zero_ether_addr(port->mac))
 		ether_addr_copy(slave_dev->dev_addr, port->mac);

net/dsa/tag_ksz.c+9−0

 	u8 *tag;
 	u8 *addr;
+	if (skb->ip_summed == CHECKSUM_PARTIAL && skb_checksum_help(skb))
+		return NULL;
 	/* Tag encoding */
 	tag = skb_put(skb, KSZ_INGRESS_TAG_LEN);
 	addr = skb_mac_header(skb);
 	u8 *addr;
 	u16 val;
+	if (skb->ip_summed == CHECKSUM_PARTIAL && skb_checksum_help(skb))
+		return NULL;
 	/* Tag encoding */
 	tag = skb_put(skb, KSZ9477_INGRESS_TAG_LEN);
 	addr = skb_mac_header(skb);
 	u8 *addr;
 	u8 *tag;
+	if (skb->ip_summed == CHECKSUM_PARTIAL && skb_checksum_help(skb))
+		return NULL;
 	/* Tag encoding */
 	tag = skb_put(skb, KSZ_INGRESS_TAG_LEN);
 	addr = skb_mac_header(skb);

net/ipv4/ip_tunnel.c+1−1

@@ -390,7 +390,7 @@ int ip_tunnel_rcv(struct ip_tunnel tunnel, struct sk_buff skb, · 389 unmodified lines
390	tunnel->i_seqno = ntohl(tpi->seq) + 1;	390	tunnel->i_seqno = ntohl(tpi->seq) + 1;
391	}	391	}
392		392
393	skb_reset_network_header(skb);	393	skb_set_network_header(skb, (tunnel->dev->type == ARPHRD_ETHER) ? ETH_HLEN : 0);
394		394
395	err = IP_ECN_decapsulate(iph, skb);	395	err = IP_ECN_decapsulate(iph, skb);
396	if (unlikely(err)) {	396	if (unlikely(err)) {

net/ipv4/tcp_bpf.c+1−1

@@ -503,7 +503,7 @@ static int __init tcp_bpf_v4_build_proto(void) · 502 unmodified lines
503	tcp_bpf_rebuild_protos(tcp_bpf_prots[TCP_BPF_IPV4], &tcp_prot);	503	tcp_bpf_rebuild_protos(tcp_bpf_prots[TCP_BPF_IPV4], &tcp_prot);
504	return 0;	504	return 0;
505	}	505	}
506	core_initcall(tcp_bpf_v4_build_proto);	506	late_initcall(tcp_bpf_v4_build_proto);
507		507
508	static int tcp_bpf_assert_proto_ops(struct proto *ops)	508	static int tcp_bpf_assert_proto_ops(struct proto *ops)
509	{	509	{

net/ipv4/tcp_fastopen.c+24−4

@@ -507,8 +507,18 @@ void tcp_fastopen_active_disable(struct sock *sk) · 506 unmodified lines
507	{	507	{
508	struct net *net = sock_net(sk);	508	struct net *net = sock_net(sk);
509		509
		510	if (!sock_net(sk)->ipv4.sysctl_tcp_fastopen_blackhole_timeout)
		511	return;
		512
		513	/* Paired with READ_ONCE() in tcp_fastopen_active_should_disable() */
		514	WRITE_ONCE(net->ipv4.tfo_active_disable_stamp, jiffies);
		515
		516	/* Paired with smp_rmb() in tcp_fastopen_active_should_disable().
		517	* We want net->ipv4.tfo_active_disable_stamp to be updated first.
		518	*/
		519	smp_mb__before_atomic();
510	atomic_inc(&net->ipv4.tfo_active_disable_times);	520	atomic_inc(&net->ipv4.tfo_active_disable_times);
511	net->ipv4.tfo_active_disable_stamp = jiffies;	521
512	NET_INC_STATS(net, LINUX_MIB_TCPFASTOPENBLACKHOLE);	522	NET_INC_STATS(net, LINUX_MIB_TCPFASTOPENBLACKHOLE);
513	}	523	}
514		524
@@ -519,17 +529,27 @@ void tcp_fastopen_active_disable(struct sock *sk) · 4 unmodified lines
519	bool tcp_fastopen_active_should_disable(struct sock *sk)	529	bool tcp_fastopen_active_should_disable(struct sock *sk)
520	{	530	{
521	unsigned int tfo_bh_timeout = sock_net(sk)->ipv4.sysctl_tcp_fastopen_blackhole_timeout;	531	unsigned int tfo_bh_timeout = sock_net(sk)->ipv4.sysctl_tcp_fastopen_blackhole_timeout;
522	int tfo_da_times = atomic_read(&sock_net(sk)->ipv4.tfo_active_disable_times);
523	unsigned long timeout;	532	unsigned long timeout;
		533	int tfo_da_times;
524	int multiplier;	534	int multiplier;
525		535
		536	if (!tfo_bh_timeout)
		537	return false;
		538
		539	tfo_da_times = atomic_read(&sock_net(sk)->ipv4.tfo_active_disable_times);
526	if (!tfo_da_times)	540	if (!tfo_da_times)
527	return false;	541	return false;
528		542
		543	/* Paired with smp_mb__before_atomic() in tcp_fastopen_active_disable() */
		544	smp_rmb();
		545
529	/* Limit timeout to max: 2^6 * initial timeout */	546	/* Limit timeout to max: 2^6 * initial timeout */
530	multiplier = 1 << min(tfo_da_times - 1, 6);	547	multiplier = 1 << min(tfo_da_times - 1, 6);
531	timeout = multiplier * tfo_bh_timeout * HZ;	548
532	if (time_before(jiffies, sock_net(sk)->ipv4.tfo_active_disable_stamp + timeout))	549	/* Paired with the WRITE_ONCE() in tcp_fastopen_active_disable(). */
		550	timeout = READ_ONCE(sock_net(sk)->ipv4.tfo_active_disable_stamp) +
		551	multiplier * tfo_bh_timeout * HZ;
		552	if (time_before(jiffies, timeout))
533	return true;	553	return true;
534		554
535	/* Mark check bit so we can check for successful active TFO	555	/* Mark check bit so we can check for successful active TFO

net/ipv4/tcp_ipv4.c+1−1

@@ -2965,7 +2965,7 @@ static int __net_init tcp_sk_init(struct net *net) · 2964 unmodified lines
2965	net->ipv4.sysctl_tcp_comp_sack_nr = 44;	2965	net->ipv4.sysctl_tcp_comp_sack_nr = 44;
2966	net->ipv4.sysctl_tcp_fastopen = TFO_CLIENT_ENABLE;	2966	net->ipv4.sysctl_tcp_fastopen = TFO_CLIENT_ENABLE;
2967	spin_lock_init(&net->ipv4.tcp_fastopen_ctx_lock);	2967	spin_lock_init(&net->ipv4.tcp_fastopen_ctx_lock);
2968	net->ipv4.sysctl_tcp_fastopen_blackhole_timeout = 60 * 60;	2968	net->ipv4.sysctl_tcp_fastopen_blackhole_timeout = 0;
2969	atomic_set(&net->ipv4.tfo_active_disable_times, 0);	2969	atomic_set(&net->ipv4.tfo_active_disable_times, 0);
2970		2970
2971	/* Reno is always built in */	2971	/* Reno is always built in */

net/ipv4/udp.c+19−6

 					 const struct iphdr *iph,
 					 struct udphdr *uh,
 					 struct udp_table *udptable,
+					 struct sock *sk,
 					 struct sk_buff *skb, u32 info)
 {
+	int (*lookup)(struct sock *sk, struct sk_buff *skb);
 	int network_offset, transport_offset;
-	struct sock *sk;
+	struct udp_sock *up;
 	network_offset = skb_network_offset(skb);
 	transport_offset = skb_transport_offset(skb);
 	/* Transport header needs to point to the UDP header */
 	skb_set_transport_header(skb, iph->ihl << 2);
+	if (sk) {
+		up = udp_sk(sk);
+		lookup = READ_ONCE(up->encap_err_lookup);
+		if (lookup && lookup(sk, skb))
+			sk = NULL;
+		goto out;
+	}
 	sk = __udp4_lib_lookup(net, iph->daddr, uh->source,
 			       iph->saddr, uh->dest, skb->dev->ifindex, 0,
 			       udptable, NULL);
 	if (sk) {
-		int (*lookup)(struct sock *sk, struct sk_buff *skb);
+		up = udp_sk(sk);
-		struct udp_sock *up = udp_sk(sk);
 		lookup = READ_ONCE(up->encap_err_lookup);
 		if (!lookup || lookup(sk, skb))
 			sk = NULL;
 	}
+out:
 	if (!sk)
 		sk = ERR_PTR(__udp4_lib_err_encap_no_sk(skb, info));
 	sk = __udp4_lib_lookup(net, iph->daddr, uh->dest,
 			       iph->saddr, uh->source, skb->dev->ifindex,
 			       inet_sdif(skb), udptable, NULL);
 	if (!sk || udp_sk(sk)->encap_type) {
 		/* No socket for error: try tunnels before discarding */
-		sk = ERR_PTR(-ENOENT);
 		if (static_branch_unlikely(&udp_encap_needed_key)) {
-			sk = __udp4_lib_err_encap(net, iph, uh, udptable, skb,
+			sk = __udp4_lib_err_encap(net, iph, uh, udptable, sk, skb,
 						  info);
 			if (!sk)
 				return 0;
-		}
+		} else
+			sk = ERR_PTR(-ENOENT);
 		if (IS_ERR(sk)) {
 			__ICMP_INC_STATS(net, ICMP_MIB_INERRORS);

net/ipv4/udp_bpf.c+1−1

@@ -134,7 +134,7 @@ static int __init udp_bpf_v4_build_proto(void) · 133 unmodified lines
134	udp_bpf_rebuild_protos(&udp_bpf_prots[UDP_BPF_IPV4], &udp_prot);	134	udp_bpf_rebuild_protos(&udp_bpf_prots[UDP_BPF_IPV4], &udp_prot);
135	return 0;	135	return 0;
136	}	136	}
137	core_initcall(udp_bpf_v4_build_proto);	137	late_initcall(udp_bpf_v4_build_proto);
138		138
139	int udp_bpf_update_proto(struct sock sk, struct sk_psock psock, bool restore)	139	int udp_bpf_update_proto(struct sock sk, struct sk_psock psock, bool restore)
140	{	140	{

net/ipv6/ip6_output.c+4−3

 			if (likely(nskb)) {
 				if (skb->sk)
-					skb_set_owner_w(skb, skb->sk);
+					skb_set_owner_w(nskb, skb->sk);
 				consume_skb(skb);
 			} else {
 				kfree_skb(skb);
 	if (net->ipv6.devconf_all->proxy_ndp &&
 	    pneigh_lookup(&nd_tbl, net, &hdr->daddr, skb->dev, 0)) {
 		int proxied = ip6_forward_proxy_check(skb);
-		if (proxied > 0)
+		if (proxied > 0) {
+			hdr->hop_limit--;
 			return ip6_input(skb);
-		else if (proxied < 0) {
+		} else if (proxied < 0) {
 			__IP6_INC_STATS(net, idev, IPSTATS_MIB_INDISCARDS);
 			goto drop;
 		}

net/ipv6/route.c+1−1

@@ -3769,7 +3769,7 @@ static struct fib6_info ip6_route_info_create(struct fib6_config cfg, · 3768 unmodified lines
3769	err = PTR_ERR(rt->fib6_metrics);	3769	err = PTR_ERR(rt->fib6_metrics);
3770	/* Do not leave garbage there. */	3770	/* Do not leave garbage there. */
3771	rt->fib6_metrics = (struct dst_metrics *)&dst_default_metrics;	3771	rt->fib6_metrics = (struct dst_metrics *)&dst_default_metrics;
3772	goto out;	3772	goto out_free;
3773	}	3773	}
3774		3774
3775	if (cfg->fc_flags & RTF_ADDRCONF)	3775	if (cfg->fc_flags & RTF_ADDRCONF)

net/ipv6/udp.c+19−6

 					 const struct ipv6hdr *hdr, int offset,
 					 struct udphdr *uh,
 					 struct udp_table *udptable,
+					 struct sock *sk,
 					 struct sk_buff *skb,
 					 struct inet6_skb_parm *opt,
 					 u8 type, u8 code, __be32 info)
 {
+	int (*lookup)(struct sock *sk, struct sk_buff *skb);
 	int network_offset, transport_offset;
-	struct sock *sk;
+	struct udp_sock *up;
 	network_offset = skb_network_offset(skb);
 	transport_offset = skb_transport_offset(skb);
 	/* Transport header needs to point to the UDP header */
 	skb_set_transport_header(skb, offset);
+	if (sk) {
+		up = udp_sk(sk);
+		lookup = READ_ONCE(up->encap_err_lookup);
+		if (lookup && lookup(sk, skb))
+			sk = NULL;
+		goto out;
+	}
 	sk = __udp6_lib_lookup(net, &hdr->daddr, uh->source,
 			       &hdr->saddr, uh->dest,
 			       inet6_iif(skb), 0, udptable, skb);
 	if (sk) {
-		int (*lookup)(struct sock *sk, struct sk_buff *skb);
+		up = udp_sk(sk);
-		struct udp_sock *up = udp_sk(sk);
 		lookup = READ_ONCE(up->encap_err_lookup);
 		if (!lookup || lookup(sk, skb))
 			sk = NULL;
 	}
+out:
 	if (!sk) {
 		sk = ERR_PTR(__udp6_lib_err_encap_no_sk(skb, opt, type, code,
 							offset, info));
 	sk = __udp6_lib_lookup(net, daddr, uh->dest, saddr, uh->source,
 			       inet6_iif(skb), inet6_sdif(skb), udptable, NULL);
 	if (!sk || udp_sk(sk)->encap_type) {
 		/* No socket for error: try tunnels before discarding */
-		sk = ERR_PTR(-ENOENT);
 		if (static_branch_unlikely(&udpv6_encap_needed_key)) {
 			sk = __udp6_lib_err_encap(net, hdr, offset, uh,
-						  udptable, skb,
+						  udptable, sk, skb,
 						  opt, type, code, info);
 			if (!sk)
 				return 0;
-		}
+		} else
+			sk = ERR_PTR(-ENOENT);
 		if (IS_ERR(sk)) {
 			__ICMP6_INC_STATS(net, __in6_dev_get(skb->dev),

net/llc/af_llc.c+9−1

@@ -98,8 +98,16 @@ static inline u8 llc_ui_header_len(struct sock sk, struct sockaddr_llc addr) · 97 unmodified lines
98	{	98	{
99	u8 rc = LLC_PDU_LEN_U;	99	u8 rc = LLC_PDU_LEN_U;
100		100
101	if (addr->sllc_test \|\| addr->sllc_xid)	101	if (addr->sllc_test)
102	rc = LLC_PDU_LEN_U;	102	rc = LLC_PDU_LEN_U;
		103	else if (addr->sllc_xid)
		104	/* We need to expand header to sizeof(struct llc_xid_info)
		105	* since llc_pdu_init_as_xid_cmd() sets 4,5,6 bytes of LLC header
		106	* as XID PDU. In llc_ui_sendmsg() we reserved header size and then
		107	* filled all other space with user data. If we won't reserve this
		108	* bytes, llc_pdu_init_as_xid_cmd() will overwrite user data
		109	*/
		110	rc = LLC_PDU_LEN_U_XID;
103	else if (sk->sk_type == SOCK_STREAM)	111	else if (sk->sk_type == SOCK_STREAM)

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Merge tag 'kvmarm-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD

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@@ -131,7 +131,7 @@ · 130 unmodified lines
131	/* buf unit size is cache_line_size, which is 64, so the shift is 6 */	131	/* buf unit size is cache_line_size, which is 64, so the shift is 6 */
132	#define PPE_BUF_SIZE_SHIFT 6	132	#define PPE_BUF_SIZE_SHIFT 6
133	#define PPE_TX_BUF_HOLD BIT(31)	133	#define PPE_TX_BUF_HOLD BIT(31)
134	#define CACHE_LINE_MASK 0x3F	134	#define SOC_CACHE_LINE_MASK 0x3F
135	#else	135	#else
136	#define PPE_CFG_QOS_VMID_GRP_SHIFT 8	136	#define PPE_CFG_QOS_VMID_GRP_SHIFT 8
137	#define PPE_CFG_RX_CTRL_ALIGN_SHIFT 11	137	#define PPE_CFG_RX_CTRL_ALIGN_SHIFT 11
@@ -531,8 +531,8 @@ hip04_mac_start_xmit(struct sk_buff skb, struct net_device ndev) · 393 unmodified lines
531	#if defined(CONFIG_HI13X1_GMAC)	531	#if defined(CONFIG_HI13X1_GMAC)
532	desc->cfg = (__force u32)cpu_to_be32(TX_CLEAR_WB \| TX_FINISH_CACHE_INV	532	desc->cfg = (__force u32)cpu_to_be32(TX_CLEAR_WB \| TX_FINISH_CACHE_INV
533	\| TX_RELEASE_TO_PPE \| priv->port << TX_POOL_SHIFT);	533	\| TX_RELEASE_TO_PPE \| priv->port << TX_POOL_SHIFT);
534	desc->data_offset = (__force u32)cpu_to_be32(phys & CACHE_LINE_MASK);	534	desc->data_offset = (__force u32)cpu_to_be32(phys & SOC_CACHE_LINE_MASK);
535	desc->send_addr = (__force u32)cpu_to_be32(phys & ~CACHE_LINE_MASK);	535	desc->send_addr = (__force u32)cpu_to_be32(phys & ~SOC_CACHE_LINE_MASK);
536	#else	536	#else
537	desc->cfg = (__force u32)cpu_to_be32(TX_CLEAR_WB \| TX_FINISH_CACHE_INV);	537	desc->cfg = (__force u32)cpu_to_be32(TX_CLEAR_WB \| TX_FINISH_CACHE_INV);
538	desc->send_addr = (__force u32)cpu_to_be32(phys);	538	desc->send_addr = (__force u32)cpu_to_be32(phys);

@@ -824,7 +824,7 @@ static struct usb_class_driver wdm_class = { · 823 unmodified lines
824	};	824	};
825		825
826	/* --- WWAN framework integration --- */	826	/* --- WWAN framework integration --- */
827	#ifdef CONFIG_WWAN	827	#ifdef CONFIG_WWAN_CORE
828	static int wdm_wwan_port_start(struct wwan_port *port)	828	static int wdm_wwan_port_start(struct wwan_port *port)
829	{	829	{
830	struct wdm_device *desc = wwan_port_get_drvdata(port);	830	struct wdm_device *desc = wwan_port_get_drvdata(port);
@@ -963,11 +963,11 @@ static void wdm_wwan_rx(struct wdm_device *desc, int length) · 132 unmodified lines
963	/* inbuf has been copied, it is safe to check for outstanding data */	963	/* inbuf has been copied, it is safe to check for outstanding data */
964	schedule_work(&desc->service_outs_intr);	964	schedule_work(&desc->service_outs_intr);
965	}	965	}
966	#else /* CONFIG_WWAN */	966	#else /* CONFIG_WWAN_CORE */
967	static void wdm_wwan_init(struct wdm_device *desc) {}	967	static void wdm_wwan_init(struct wdm_device *desc) {}
968	static void wdm_wwan_deinit(struct wdm_device *desc) {}	968	static void wdm_wwan_deinit(struct wdm_device *desc) {}
969	static void wdm_wwan_rx(struct wdm_device *desc, int length) {}	969	static void wdm_wwan_rx(struct wdm_device *desc, int length) {}
970	#endif /* CONFIG_WWAN */	970	#endif /* CONFIG_WWAN_CORE */
971		971
972	/* --- error handling --- */	972	/* --- error handling --- */
973	static void wdm_rxwork(struct work_struct *work)	973	static void wdm_rxwork(struct work_struct *work)