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Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux

Pull drm updates from Dave Airlie: "Highlights: - drm: Generic display port aux features, primary plane support, drm master management fixes, logging cleanups, enforced locking checks (instead of docs), documentation improvements, minor number handling cleanup, pseudofs for shared inodes. - ttm: add ability to allocate from both ends - i915: broadwell features, power domain and runtime pm, per-process address space infrastructure (not enabled) - msm: power management, hdmi audio support - nouveau: ongoing GPU fault recovery, initial maxwell support, random fixes - exynos: refactored driver to clean up a lot of abstraction, DP support moved into drm, LVDS bridge support added, parallel panel support - gma500: SGX MMU support, SGX irq handling, asle irq work fixes - radeon: video engine bringup, ring handling fixes, use dp aux helpers - vmwgfx: add rendernode support" * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (849 commits) DRM: armada: fix corruption while loading cursors drm/dp_helper: don't return EPROTO for defers (v2) drm/bridge: export ptn3460_init function drm/exynos: remove MODULE_DEVICE_TABLE definitions ARM: dts: exynos4412-trats2: enable exynos/fimd node ARM: dts: exynos4210-trats: enable exynos/fimd node ARM: dts: exynos4412-trats2: add panel node ARM: dts: exynos4210-trats: add panel node ARM: dts: exynos4: add MIPI DSI Master node drm/panel: add S6E8AA0 driver ARM: dts: exynos4210-universal_c210: add proper panel node drm/panel: add ld9040 driver panel/ld9040: add DT bindings panel/s6e8aa0: add DT bindings drm/exynos: add DSIM driver exynos/dsim: add DT bindings drm/exynos: disallow fbdev initialization if no device is connected drm/mipi_dsi: create dsi devices only for nodes with reg property drm/mipi_dsi: add flags to DSI messages Skip intel_crt_init for Dell XPS 8700 ...

Linus Torvalds committed 12 years ago

Commit e9f37d32 parents 5fb6b95 c39b069483 files · +37464 −15916Browse files

Showing the changes to include/uapi (5 of 483 files). Show all

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5 files
  1. include/uapi/drm/drm.h +17 −0
  2. include/uapi/drm/msm_drm.h +12 −0
  3. include/uapi/drm/radeon_drm.h +20 −0
  4. include/uapi/drm/tegra_drm.h +15 −9
  5. include/uapi/drm/vmwgfx_drm.h +11 −1
include/uapi/drm/drm.h+17−0
@@ -619,6 +619,15 @@ struct drm_gem_open { · 618 unmodified lines
619#define DRM_PRIME_CAP_EXPORT 0x2619#define DRM_PRIME_CAP_EXPORT 0x2
620#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6620#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
621#define DRM_CAP_ASYNC_PAGE_FLIP 0x7621#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
622/*
623 * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight
624 * combination for the hardware cursor. The intention is that a hardware
625 * agnostic userspace can query a cursor plane size to use.
626 *
627 * Note that the cross-driver contract is to merely return a valid size;
628 * drivers are free to attach another meaning on top, eg. i915 returns the
629 * maximum plane size.
630 */
622#define DRM_CAP_CURSOR_WIDTH 0x8631#define DRM_CAP_CURSOR_WIDTH 0x8
623#define DRM_CAP_CURSOR_HEIGHT 0x9632#define DRM_CAP_CURSOR_HEIGHT 0x9
624 633
@@ -637,6 +646,14 @@ struct drm_get_cap { · 12 unmodified lines
637 */646 */
638#define DRM_CLIENT_CAP_STEREO_3D 1647#define DRM_CLIENT_CAP_STEREO_3D 1
639 648
649/**
650 * DRM_CLIENT_CAP_UNIVERSAL_PLANES
651 *
652 * If set to 1, the DRM core will expose all planes (overlay, primary, and
653 * cursor) to userspace.
654 */
655#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
656
640/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */657/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
641struct drm_set_client_cap {658struct drm_set_client_cap {
642 __u64 capability;659 __u64 capability;
include/uapi/drm/msm_drm.h+12−0
@@ -50,6 +50,7 @@ struct drm_msm_timespec { · 49 unmodified lines
50 50
51#define MSM_PARAM_GPU_ID 0x0151#define MSM_PARAM_GPU_ID 0x01
52#define MSM_PARAM_GMEM_SIZE 0x0252#define MSM_PARAM_GMEM_SIZE 0x02
53#define MSM_PARAM_CHIP_ID 0x03
53 54
54struct drm_msm_param {55struct drm_msm_param {
55 uint32_t pipe; /* in, MSM_PIPE_x */56 uint32_t pipe; /* in, MSM_PIPE_x */
@@ -69,6 +70,12 @@ struct drm_msm_param { · 13 unmodified lines
69#define MSM_BO_WC 0x0002000070#define MSM_BO_WC 0x00020000
70#define MSM_BO_UNCACHED 0x0004000071#define MSM_BO_UNCACHED 0x00040000
71 72
73#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
74 MSM_BO_GPU_READONLY | \
75 MSM_BO_CACHED | \
76 MSM_BO_WC | \
77 MSM_BO_UNCACHED)
78
72struct drm_msm_gem_new {79struct drm_msm_gem_new {
73 uint64_t size; /* in */80 uint64_t size; /* in */
74 uint32_t flags; /* in, mask of MSM_BO_x */81 uint32_t flags; /* in, mask of MSM_BO_x */
@@ -85,6 +92,8 @@ struct drm_msm_gem_info { · 10 unmodified lines
85#define MSM_PREP_WRITE 0x0292#define MSM_PREP_WRITE 0x02
86#define MSM_PREP_NOSYNC 0x0493#define MSM_PREP_NOSYNC 0x04
87 94
95#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
96
88struct drm_msm_gem_cpu_prep {97struct drm_msm_gem_cpu_prep {
89 uint32_t handle; /* in */98 uint32_t handle; /* in */
90 uint32_t op; /* in, mask of MSM_PREP_x */99 uint32_t op; /* in, mask of MSM_PREP_x */
@@ -152,6 +161,9 @@ struct drm_msm_gem_submit_cmd { · 61 unmodified lines
152 */161 */
153#define MSM_SUBMIT_BO_READ 0x0001162#define MSM_SUBMIT_BO_READ 0x0001
154#define MSM_SUBMIT_BO_WRITE 0x0002163#define MSM_SUBMIT_BO_WRITE 0x0002
164
165#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
166
155struct drm_msm_gem_submit_bo {167struct drm_msm_gem_submit_bo {
156 uint32_t flags; /* in, mask of MSM_SUBMIT_BO_x */168 uint32_t flags; /* in, mask of MSM_SUBMIT_BO_x */
157 uint32_t handle; /* in, GEM handle */169 uint32_t handle; /* in, GEM handle */
include/uapi/drm/radeon_drm.h+20−0
@@ -510,6 +510,7 @@ typedef struct { · 509 unmodified lines
510#define DRM_RADEON_GEM_GET_TILING 0x29510#define DRM_RADEON_GEM_GET_TILING 0x29
511#define DRM_RADEON_GEM_BUSY 0x2a511#define DRM_RADEON_GEM_BUSY 0x2a
512#define DRM_RADEON_GEM_VA 0x2b512#define DRM_RADEON_GEM_VA 0x2b
513#define DRM_RADEON_GEM_OP 0x2c
513 514
514#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)515#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
515#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)516#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
@@ -552,6 +553,7 @@ typedef struct { · 36 unmodified lines
552#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)553#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
553#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)554#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
554#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)555#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
556#define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)
555 557
556typedef struct drm_radeon_init {558typedef struct drm_radeon_init {
557 enum {559 enum {
@@ -884,6 +886,16 @@ struct drm_radeon_gem_pwrite { · 326 unmodified lines
884 uint64_t data_ptr;886 uint64_t data_ptr;
885};887};
886 888
889/* Sets or returns a value associated with a buffer. */
890struct drm_radeon_gem_op {
891 uint32_t handle; /* buffer */
892 uint32_t op; /* RADEON_GEM_OP_* */
893 uint64_t value; /* input or return value */
894};
895
896#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
897#define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1
898
887#define RADEON_VA_MAP 1899#define RADEON_VA_MAP 1
888#define RADEON_VA_UNMAP 2900#define RADEON_VA_UNMAP 2
889 901
@@ -919,6 +931,7 @@ struct drm_radeon_gem_va { · 29 unmodified lines
919#define RADEON_CS_RING_COMPUTE 1931#define RADEON_CS_RING_COMPUTE 1
920#define RADEON_CS_RING_DMA 2932#define RADEON_CS_RING_DMA 2
921#define RADEON_CS_RING_UVD 3933#define RADEON_CS_RING_UVD 3
934#define RADEON_CS_RING_VCE 4
922/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */935/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
923/* 0 = normal, + = higher priority, - = lower priority */936/* 0 = normal, + = higher priority, - = lower priority */
924 937
@@ -987,6 +1000,13 @@ struct drm_radeon_cs { · 62 unmodified lines
987#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x191000#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
988/* max engine clock - needed for OpenCL */1001/* max engine clock - needed for OpenCL */
989#define RADEON_INFO_MAX_SCLK 0x1a1002#define RADEON_INFO_MAX_SCLK 0x1a
1003/* version of VCE firmware */
1004#define RADEON_INFO_VCE_FW_VERSION 0x1b
1005/* version of VCE feedback */
1006#define RADEON_INFO_VCE_FB_VERSION 0x1c
1007#define RADEON_INFO_NUM_BYTES_MOVED 0x1d
1008#define RADEON_INFO_VRAM_USAGE 0x1e
1009#define RADEON_INFO_GTT_USAGE 0x1f
990 1010
991 1011
992struct drm_radeon_info {1012struct drm_radeon_info {
include/uapi/drm/tegra_drm.h+15−9
@@ -1,17 +1,23 @@
1/*1/*
2 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.2 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
3 *3 *
4 * This program is free software; you can redistribute it and/or modify it4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * under the terms and conditions of the GNU General Public License,5 * copy of this software and associated documentation files (the "Software"),
6 * version 2, as published by the Free Software Foundation.6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
7 *10 *
8 * This program is distributed in the hope it will be useful, but WITHOUT11 * The above copyright notice and this permission notice shall be included in
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or12 * all copies or substantial portions of the Software.
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *13 *
13 * You should have received a copy of the GNU General Public License14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
15 */21 */
16 22
17#ifndef _UAPI_TEGRA_DRM_H_23#ifndef _UAPI_TEGRA_DRM_H_
include/uapi/drm/vmwgfx_drm.h+11−1
@@ -89,6 +89,15 @@ · 88 unmodified lines
89#define DRM_VMW_PARAM_MAX_MOB_MEMORY 989#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
90#define DRM_VMW_PARAM_MAX_MOB_SIZE 1090#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
91 91
92/**
93 * enum drm_vmw_handle_type - handle type for ref ioctls
94 *
95 */
96enum drm_vmw_handle_type {
97 DRM_VMW_HANDLE_LEGACY = 0,
98 DRM_VMW_HANDLE_PRIME = 1
99};
100
92/**101/**
93 * struct drm_vmw_getparam_arg102 * struct drm_vmw_getparam_arg
94 *103 *
@@ -177,6 +186,7 @@ struct drm_vmw_surface_create_req { · 82 unmodified lines
177 * struct drm_wmv_surface_arg186 * struct drm_wmv_surface_arg
178 *187 *
179 * @sid: Surface id of created surface or surface to destroy or reference.188 * @sid: Surface id of created surface or surface to destroy or reference.
189 * @handle_type: Handle type for DRM_VMW_REF_SURFACE Ioctl.
180 *190 *
181 * Output data from the DRM_VMW_CREATE_SURFACE Ioctl.191 * Output data from the DRM_VMW_CREATE_SURFACE Ioctl.
182 * Input argument to the DRM_VMW_UNREF_SURFACE Ioctl.192 * Input argument to the DRM_VMW_UNREF_SURFACE Ioctl.
@@ -185,7 +195,7 @@ struct drm_vmw_surface_create_req { · 2 unmodified lines
185 195
186struct drm_vmw_surface_arg {196struct drm_vmw_surface_arg {
187 int32_t sid;197 int32_t sid;
188 uint32_t pad64;198 enum drm_vmw_handle_type handle_type;
189};199};
190 200
191/**201/**