PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 defines the size of the PCIe capability structure for v1 devices with link, but we also have a need in the vfio code for sizing the capability for devices without link, such as Root Complex Integrated Endpoints. Create a separate define for this ending the structure before the link fields. Additionally, this reveals that PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 is currently incorrect, ending the capability length before the v2 link fields. Rename this to specify an RC Integrated Endpoint (no link) capability length and move PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 to include the link fields as we have for the v1 version.
Unified · Split
| @@ -513,6 +513,7 @@ · 512 unmodified lines | |||
| 513 | #define PCI_EXP_DEVSTA_URD 0x0008 /* Unsupported Request Detected */ | 513 | #define PCI_EXP_DEVSTA_URD 0x0008 /* Unsupported Request Detected */ |
| 514 | #define PCI_EXP_DEVSTA_AUXPD 0x0010 /* AUX Power Detected */ | 514 | #define PCI_EXP_DEVSTA_AUXPD 0x0010 /* AUX Power Detected */ |
| 515 | #define PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */ | 515 | #define PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */ |
| 516 | #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 12 /* v1 endpoints without link end here */ | ||
| 516 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ | 517 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ |
| 517 | #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ | 518 | #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ |
| 518 | #define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */ | 519 | #define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */ |
| @@ -556,7 +557,7 @@ · 37 unmodified lines | |||
| 556 | #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ | 557 | #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ |
| 557 | #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ | 558 | #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ |
| 558 | #define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ | 559 | #define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ |
| 559 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints end here */ | 560 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints with link end here */ |
| 560 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ | 561 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
| 561 | #define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ | 562 | #define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ |
| 562 | #define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ | 563 | #define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ |
| @@ -639,7 +640,7 @@ · 76 unmodified lines | |||
| 639 | #define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */ | 640 | #define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */ |
| 640 | #define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ | 641 | #define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ |
| 641 | #define PCI_EXP_DEVSTA2 42 /* Device Status 2 */ | 642 | #define PCI_EXP_DEVSTA2 42 /* Device Status 2 */ |
| 642 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ | 643 | #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints without link end here */ |
| 643 | #define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */ | 644 | #define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */ |
| 644 | #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */ | 645 | #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */ |
| 645 | #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */ | 646 | #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */ |
| @@ -647,6 +648,7 @@ · 1 unmodified line | |||
| 647 | #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ | 648 | #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ |
| 648 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ | 649 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ |
| 649 | #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ | 650 | #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ |
| 651 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ | ||
| 650 | #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ | 652 | #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ |
| 651 | #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ | 653 | #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ |
| 652 | #define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */ | 654 | #define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */ |