Merge tag 'mmc-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Pull MMC updates from Ulf Hansson: "MMC core: - Fixup processing of SDIO IRQs during system suspend/resume - Add helper function to indicate if SDIO IRQs is enabled MMC host: - bcm2835: Take SWIOTLB memory size limitation into account - dw_mmc: Improve SDIO IRQs support - mtk-sd: Various improvements - mtk-sd: Improve SDIO IRQs support - sdhci-iproc: Add support for emmc2 of the BCM2711 - sdhci-of-arasan: Add Support for Intel LGM eMMC - sdhci-of-aspeed: Add support for the ASPEED SD controller - sdhci-of-esdhc: Deal with erratum A011334 support in ls1028a 1.0 SoC - sdhci-pci: Prepare to add support of Genesys Logic GL975x - sdhci-pci: Add another Id for Intel CML - sdhci-pci-o2micro: Fix O2 Host data read/write DLL Lock phase shift issue - sunxi: Add support for H5 compatibles" * tag 'mmc-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (59 commits) ms_block: fix spelling mistake "randomally" -> "randomly" mmc: dw_mmc: hi3798cv200: make array degrees static const, makes object smaller mmc: sdhci: Convert to use sdio_irq_claimed() mmc: sdhci: Drop redundant code for SDIO IRQs mmc: sdhci: Drop redundant check in sdhci_ack_sdio_irq() mmc: core: Fixup processing of SDIO IRQs during system suspend/resume mmc: core: WARN if SDIO IRQs are enabled for non-powered card in suspend mmc: core: Clarify that the ->ack_sdio_irq() callback is mandatory mmc: core: Clarify sdio_irq_pending flag for MMC_CAP2_SDIO_IRQ_NOTHREAD mmc: core: Move code to get pending SDIO IRQs to a function mmc: mtk-sd: Re-store SDIO IRQs mask at system resume mmc: dw_mmc: Re-store SDIO IRQs mask at system resume mmc: core: Add helper function to indicate if SDIO IRQs is enabled mmc: sdhci-pci-o2micro: Fix O2 Host data read/write DLL Lock phase shift issue mmc: sdhci-pci-o2micro: Move functions in preparation to fix DLL lock phase shift issue mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name mmc: sdhci: Fix incorrect switch to HS mode mmc: sdhci-of-aspeed: Depend on CONFIG_OF_ADDRESS mmc: sdhci-of-aspeed: Allow max-frequency limitation of SDCLK mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock() ...

Linus Torvalds committed 7 years ago

Commit ea982ba2 parents 7ad67ca b46119743 files · +958 −310Browse files

Unified · Split

43 files

Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml +10 −4
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +17 −0
Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml +106 −0
Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt +3 −1
MAINTAINERS +1 −0
drivers/memstick/core/ms_block.c +1 −1
drivers/memstick/host/r592.c +2 −4
drivers/mmc/core/sdio.c +3 −1
drivers/mmc/core/sdio_irq.c +37 −20
drivers/mmc/host/Kconfig +12 −0
drivers/mmc/host/Makefile +1 −0
drivers/mmc/host/atmel-mci.c +4 −0
drivers/mmc/host/bcm2835.c +1 −2
drivers/mmc/host/dw_mmc-hi3798cv200.c +1 −1
drivers/mmc/host/dw_mmc.c +4 −0
drivers/mmc/host/jz4740_mmc.c +7 −12
drivers/mmc/host/meson-gx-mmc.c +0 −1
drivers/mmc/host/mmc_spi.c +1 −1
drivers/mmc/host/mmci.c +37 −32
drivers/mmc/host/mtk-sd.c +23 −6
drivers/mmc/host/mxcmmc.c +1 −3
drivers/mmc/host/mxs-mmc.c +1 −3
drivers/mmc/host/renesas_sdhi_core.c +8 −5
drivers/mmc/host/renesas_sdhi_sys_dmac.c +0 −36
drivers/mmc/host/s3cmci.c +0 −1
drivers/mmc/host/sdhci-cadence.c +4 −3
drivers/mmc/host/sdhci-esdhc-imx.c +15 −19
drivers/mmc/host/sdhci-iproc.c +9 −0
drivers/mmc/host/sdhci-msm.c +0 −2
drivers/mmc/host/sdhci-of-arasan.c +15 −0
drivers/mmc/host/sdhci-of-aspeed.c +342 −0
drivers/mmc/host/sdhci-of-esdhc.c +1 −0
drivers/mmc/host/sdhci-pci-core.c +5 −8
drivers/mmc/host/sdhci-pci-o2micro.c +216 −95
drivers/mmc/host/sdhci-pci.h +1 −0
drivers/mmc/host/sdhci-pltfm.c +1 −4
drivers/mmc/host/sdhci-s3c.c +2 −3
drivers/mmc/host/sdhci.c +48 −28
drivers/mmc/host/sdhci.h +4 −8
drivers/mmc/host/sdhci_f_sdh30.c +1 −3
drivers/mmc/host/uniphier-sd.c +1 −3
include/linux/mmc/host.h +10 −0
include/linux/pci_ids.h +2 −0

Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml+10−4

           - const: allwinner,sun8i-a83t-mmc
           - const: allwinner,sun7i-a20-mmc
       - items:
-          - const: allwinner,sun50i-h6-emmc
+          - const: allwinner,sun8i-r40-emmc
           - const: allwinner,sun50i-a64-emmc
       - items:
-          - const: allwinner,sun50i-h6-mmc
+          - const: allwinner,sun8i-r40-mmc
           - const: allwinner,sun50i-a64-mmc
       - items:
-          - const: allwinner,sun8i-r40-emmc
+          - const: allwinner,sun50i-h5-emmc
           - const: allwinner,sun50i-a64-emmc
       - items:
-          - const: allwinner,sun8i-r40-mmc
+          - const: allwinner,sun50i-h5-mmc
+          - const: allwinner,sun50i-a64-mmc
+      - items:
+          - const: allwinner,sun50i-h6-emmc
+          - const: allwinner,sun50i-a64-emmc
+      - items:
+          - const: allwinner,sun50i-h6-mmc
           - const: allwinner,sun50i-a64-mmc
   reg:

Documentation/devicetree/bindings/mmc/arasan,sdhci.txt+17−0

@@ -17,6 +17,8 @@ Required Properties: · 16 unmodified lines
17	For this device it is strongly suggested to include arasan,soc-ctl-syscon.	17	For this device it is strongly suggested to include arasan,soc-ctl-syscon.
18	- "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY	18	- "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
19	Note: This binding has been deprecated and moved to [5].	19	Note: This binding has been deprecated and moved to [5].
		20	- "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
		21	For this device it is strongly suggested to include arasan,soc-ctl-syscon.
20		22
21	[5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt	23	[5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
22		24
@@ -80,3 +82,18 @@ Example: · 57 unmodified lines
80	phy-names = "phy_arasan";	82	phy-names = "phy_arasan";
81	#clock-cells = <0>;	83	#clock-cells = <0>;
82	};	84	};
		85
		86	emmc: sdhci@ec700000 {
		87	compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
		88	reg = <0xec700000 0x300>;
		89	interrupt-parent = <&ioapic1>;
		90	interrupts = <44 1>;
		91	clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
		92	<&cgu0 LGM_GCLK_EMMC>;
		93	clock-names = "clk_xin", "clk_ahb", "gate";
		94	clock-output-names = "emmc_cardclock";
		95	#clock-cells = <0>;
		96	phys = <&emmc_phy>;
		97	phy-names = "phy_arasan";
		98	arasan,soc-ctl-syscon = <&sysconf>;
		99	};

Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml+106−0

@@ -0,0 +1,106 @@
	1	# SPDX-License-Identifier: GPL-2.0-or-later
	2	# Copyright 2019 IBM Corp.
	3	%YAML 1.2
	4	---
	5	$id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
	6	$schema: http://devicetree.org/meta-schemas/core.yaml#
	7
	8	title: ASPEED SD/SDIO/MMC Controller
	9
	10	maintainers:
	11	- Andrew Jeffery <andrew@aj.id.au>
	12	- Ryan Chen <ryanchen.aspeed@gmail.com>
	13
	14	description: \|+
	15	The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO
	16	Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if
	17	only a single slot is enabled.
	18
	19	The two slots are supported by a common configuration area. As the SDHCIs for
	20	the slots are dependent on the common configuration area, they are described
	21	as child nodes.
	22
	23	properties:
	24	compatible:
	25	enum:
	26	- aspeed,ast2400-sd-controller
	27	- aspeed,ast2500-sd-controller
	28	- aspeed,ast2600-sd-controller
	29	reg:
	30	maxItems: 1
	31	description: Common configuration registers
	32	"#address-cells":
	33	const: 1
	34	"#size-cells":
	35	const: 1
	36	ranges: true
	37	clocks:
	38	maxItems: 1
	39	description: The SD/SDIO controller clock gate
	40
	41	patternProperties:
	42	"^sdhci@[0-9a-f]+$":
	43	type: object
	44	allOf:
	45	- $ref: mmc-controller.yaml
	46	properties:
	47	compatible:
	48	enum:
	49	- aspeed,ast2400-sdhci
	50	- aspeed,ast2500-sdhci
	51	- aspeed,ast2600-sdhci
	52	reg:
	53	maxItems: 1
	54	description: The SDHCI registers
	55	clocks:
	56	maxItems: 1
	57	description: The SD bus clock
	58	interrupts:
	59	maxItems: 1
	60	description: The SD interrupt shared between both slots
	61	sdhci,auto-cmd12:
	62	type: boolean
	63	description: Specifies that controller should use auto CMD12
	64	required:
	65	- compatible
	66	- reg
	67	- clocks
	68	- interrupts
	69
	70	additionalProperties: false
	71
	72	required:
	73	- compatible
	74	- reg
	75	- "#address-cells"
	76	- "#size-cells"
	77	- ranges
	78	- clocks
	79
	80	examples:
	81	- \|
	82	#include <dt-bindings/clock/aspeed-clock.h>
	83	sdc@1e740000 {
	84	compatible = "aspeed,ast2500-sd-controller";
	85	reg = <0x1e740000 0x100>;
	86	#address-cells = <1>;
	87	#size-cells = <1>;
	88	ranges = <0 0x1e740000 0x20000>;
	89	clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
	90
	91	sdhci0: sdhci@100 {
	92	compatible = "aspeed,ast2500-sdhci";
	93	reg = <0x100 0x100>;
	94	interrupts = <26>;
	95	sdhci,auto-cmd12;
	96	clocks = <&syscon ASPEED_CLK_SDIO>;
	97	};
	98
	99	sdhci1: sdhci@200 {
	100	compatible = "aspeed,ast2500-sdhci";
	101	reg = <0x200 0x100>;
	102	interrupts = <26>;
	103	sdhci,auto-cmd12;
	104	clocks = <&syscon ASPEED_CLK_SDIO>;
	105	};
	106	};

Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt+3−1

 Required properties:
 - compatible : Should be one of the following
 	       "brcm,bcm2835-sdhci"
+	       "brcm,bcm2711-emmc2"
 	       "brcm,sdhci-iproc-cygnus"
 	       "brcm,sdhci-iproc"
-Use brcm2835-sdhci for Rasperry PI.
+Use brcm2835-sdhci for the eMMC controller on the BCM2835 (Raspberry Pi) and
+bcm2711-emmc2 for the additional eMMC2 controller on BCM2711.
 Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers
 restricted to 32bit host accesses to SDHCI registers.

MAINTAINERS+1−0

@@ -1462,6 +1462,7 @@ F: arch/arm/mach-artpec · 1461 unmodified lines
1462	F: arch/arm/boot/dts/artpec6*	1462	F: arch/arm/boot/dts/artpec6*
1463	F: drivers/clk/axis	1463	F: drivers/clk/axis
1464	F: drivers/crypto/axis	1464	F: drivers/crypto/axis
		1465	F: drivers/mmc/host/usdhi6rol0.c
1465	F: drivers/pinctrl/pinctrl-artpec*	1466	F: drivers/pinctrl/pinctrl-artpec*
1466	F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt	1467	F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
1467		1468

drivers/memstick/core/ms_block.c+1−1

@@ -1087,7 +1087,7 @@ static u16 msb_get_free_block(struct msb_data *msb, int zone) · 1086 unmodified lines
1087		1087
1088	pos %= msb->free_block_count[zone];	1088	pos %= msb->free_block_count[zone];
1089		1089
1090	dbg_verbose("have %d choices for a free block, selected randomally: %d",	1090	dbg_verbose("have %d choices for a free block, selected randomly: %d",
1091	msb->free_block_count[zone], pos);	1091	msb->free_block_count[zone], pos);
1092		1092
1093	pba = find_next_zero_bit(msb->used_blocks_bitmap,	1093	pba = find_next_zero_bit(msb->used_blocks_bitmap,

drivers/memstick/host/r592.c+2−4

 #ifdef CONFIG_PM_SLEEP
 static int r592_suspend(struct device *core_dev)
 {
-	struct pci_dev *pdev = to_pci_dev(core_dev);
+	struct r592_device *dev = dev_get_drvdata(core_dev);
-	struct r592_device *dev = pci_get_drvdata(pdev);
 	r592_clear_interrupts(dev);
 	memstick_suspend_host(dev->host);
 static int r592_resume(struct device *core_dev)
 {
-	struct pci_dev *pdev = to_pci_dev(core_dev);
+	struct r592_device *dev = dev_get_drvdata(core_dev);
-	struct r592_device *dev = pci_get_drvdata(pdev);
 	r592_clear_interrupts(dev);
 	r592_enable_device(dev, false);

drivers/mmc/core/sdio.c+3−1

  */
 static int mmc_sdio_suspend(struct mmc_host *host)
 {
+	WARN_ON(host->sdio_irqs && !mmc_card_keep_power(host));
 	/* Prevent processing of SDIO IRQs in suspended state. */
 	mmc_card_set_suspended(host->card);
 	cancel_delayed_work_sync(&host->sdio_irq_work);
 		if (!(host->caps2 & MMC_CAP2_SDIO_IRQ_NOTHREAD))
 			wake_up_process(host->sdio_irq_thread);
 		else if (host->caps & MMC_CAP_SDIO_IRQ)
-			host->ops->enable_sdio_irq(host, 1);
+			queue_delayed_work(system_wq, &host->sdio_irq_work, 0);
 	}
 out:

drivers/mmc/core/sdio_irq.c+37−20

 #include "core.h"
 #include "card.h"
+static int sdio_get_pending_irqs(struct mmc_host *host, u8 *pending)
+{
+	struct mmc_card *card = host->card;
+	int ret;
+	WARN_ON(!host->claimed);
+	ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_INTx, 0, pending);
+	if (ret) {
+		pr_debug("%s: error %d reading SDIO_CCCR_INTx\n",
+		       mmc_card_id(card), ret);
+		return ret;
+	}
+	if (*pending && mmc_card_broken_irq_polling(card) &&
+	    !(host->caps & MMC_CAP_SDIO_IRQ)) {
+		unsigned char dummy;
+		/* A fake interrupt could be created when we poll SDIO_CCCR_INTx
+		 * register with a Marvell SD8797 card. A dummy CMD52 read to
+		 * function 0 register 0xff can avoid this.
+		 */
+		mmc_io_rw_direct(card, 0, 0, 0xff, 0, &dummy);
+	}
+	return 0;
+}
 static int process_sdio_pending_irqs(struct mmc_host *host)
 {
 	struct mmc_card *card = host->card;
 	int i, ret, count;
+	bool sdio_irq_pending = host->sdio_irq_pending;
 	unsigned char pending;
 	struct sdio_func *func;
 	if (mmc_card_suspended(card))
 		return 0;
+	/* Clear the flag to indicate that we have processed the IRQ. */
+	host->sdio_irq_pending = false;
 	/*
 	 * Optimization, if there is only 1 function interrupt registered
 	 * and we know an IRQ was signaled then call irq handler directly.
 	 * Otherwise do the full probe.
 	 */
 	func = card->sdio_single_irq;
-	if (func && host->sdio_irq_pending) {
+	if (func && sdio_irq_pending) {
 		func->irq_handler(func);
 		return 1;
 	}
-	ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_INTx, 0, &pending);
+	ret = sdio_get_pending_irqs(host, &pending);
-	if (ret) {
+	if (ret)
-		pr_debug("%s: error %d reading SDIO_CCCR_INTx\n",
-		       mmc_card_id(card), ret);
 		return ret;
-	}
-	if (pending && mmc_card_broken_irq_polling(card) &&
-	    !(host->caps & MMC_CAP_SDIO_IRQ)) {
-		unsigned char dummy;
-		/* A fake interrupt could be created when we poll SDIO_CCCR_INTx
-		 * register with a Marvell SD8797 card. A dummy CMD52 read to
-		 * function 0 register 0xff can avoid this.
-		 */
-		mmc_io_rw_direct(card, 0, 0, 0xff, 0, &dummy);
-	}
 	count = 0;
 	for (i = 1; i <= 7; i++) {
 {
 	mmc_claim_host(host);
 	if (host->sdio_irqs) {
-		host->sdio_irq_pending = true;
 		process_sdio_pending_irqs(host);
-		if (host->ops->ack_sdio_irq)
+		if (!host->sdio_irq_pending)
 			host->ops->ack_sdio_irq(host);
 	}
 	mmc_release_host(host);
 void sdio_signal_irq(struct mmc_host *host)
 {
+	host->sdio_irq_pending = true;
 	queue_delayed_work(system_wq, &host->sdio_irq_work, 0);
 }
 EXPORT_SYMBOL_GPL(sdio_signal_irq);
 		if (ret)
 			break;
 		ret = process_sdio_pending_irqs(host);
-		host->sdio_irq_pending = false;
 		mmc_release_host(host);
 		/*

drivers/mmc/host/Kconfig+12−0

@@ -154,6 +154,18 @@ config MMC_SDHCI_OF_ARASAN · 153 unmodified lines
154		154
155	If unsure, say N.	155	If unsure, say N.
156		156
		157	config MMC_SDHCI_OF_ASPEED
		158	tristate "SDHCI OF support for the ASPEED SDHCI controller"
		159	depends on MMC_SDHCI_PLTFM
		160	depends on OF && OF_ADDRESS
		161	help
		162	This selects the ASPEED Secure Digital Host Controller Interface.
		163
		164	If you have a controller with this interface, say Y or M here. You
		165	also need to enable an appropriate bus interface.
		166
		167	If unsure, say N.
		168
157	config MMC_SDHCI_OF_AT91	169	config MMC_SDHCI_OF_AT91
158	tristate "SDHCI OF support for the Atmel SDMMC controller"	170	tristate "SDHCI OF support for the Atmel SDMMC controller"
159	depends on MMC_SDHCI_PLTFM	171	depends on MMC_SDHCI_PLTFM

drivers/mmc/host/Makefile+1−0

@@ -84,6 +84,7 @@ obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o · 83 unmodified lines
84	obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o	84	obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o
85	obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o	85	obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o
86	obj-$(CONFIG_MMC_SDHCI_OF_ARASAN) += sdhci-of-arasan.o	86	obj-$(CONFIG_MMC_SDHCI_OF_ARASAN) += sdhci-of-arasan.o
		87	obj-$(CONFIG_MMC_SDHCI_OF_ASPEED) += sdhci-of-aspeed.o
87	obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o	88	obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o
88	obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o	89	obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
89	obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o	90	obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o

drivers/mmc/host/atmel-mci.c+4−0

 	case 0x600:
 	case 0x500:
 		host->caps.has_odd_clk_div = 1;
+		/* Fall through */
 	case 0x400:
 	case 0x300:
 		host->caps.has_dma_conf_reg = 1;
 		host->caps.has_cfg_reg = 1;
 		host->caps.has_cstor_reg = 1;
 		host->caps.has_highspeed = 1;
+		/* Fall through */
 	case 0x200:
 		host->caps.has_rwproof = 1;
 		host->caps.need_blksz_mul_4 = 0;
 		host->caps.need_notbusy_for_read_ops = 1;
+		/* Fall through */
 	case 0x100:
 		host->caps.has_bad_data_ordering = 0;
 		host->caps.need_reset_after_xfer = 0;
+		/* Fall through */
 	case 0x0:
 		break;
 	default:

drivers/mmc/host/bcm2835.c+1−2

 	}
 	mmc->max_segs = 128;
-	mmc->max_req_size = 524288;
+	mmc->max_req_size = min_t(size_t, 524288, dma_max_mapping_size(dev));
 	mmc->max_seg_size = mmc->max_req_size;
 	mmc->max_blk_size = 1024;
 	mmc->max_blk_count =  65535;
 	host->irq = platform_get_irq(pdev, 0);
 	if (host->irq <= 0) {
-		dev_err(dev, "get IRQ failed\n");
 		ret = -EINVAL;
 		goto err;
 	}

drivers/mmc/host/dw_mmc-hi3798cv200.c+1−1

@@ -66,7 +66,7 @@ static void dw_mci_hi3798cv200_set_ios(struct dw_mci host, struct mmc_ios ios) · 65 unmodified lines
66	static int dw_mci_hi3798cv200_execute_tuning(struct dw_mci_slot *slot,	66	static int dw_mci_hi3798cv200_execute_tuning(struct dw_mci_slot *slot,
67	u32 opcode)	67	u32 opcode)
68	{	68	{
69	int degrees[] = { 0, 45, 90, 135, 180, 225, 270, 315 };	69	static const int degrees[] = { 0, 45, 90, 135, 180, 225, 270, 315 };
70	struct dw_mci *host = slot->host;	70	struct dw_mci *host = slot->host;
71	struct hi3798cv200_priv *priv = host->priv;	71	struct hi3798cv200_priv *priv = host->priv;
72	int raise_point = -1, fall_point = -1;	72	int raise_point = -1, fall_point = -1;

drivers/mmc/host/dw_mmc.c+4−0

@@ -3460,6 +3460,10 @@ int dw_mci_runtime_resume(struct device *dev) · 3459 unmodified lines
3460	/* Force setup bus to guarantee available clock output */	3460	/* Force setup bus to guarantee available clock output */
3461	dw_mci_setup_bus(host->slot, true);	3461	dw_mci_setup_bus(host->slot, true);
3462		3462
		3463	/* Re-enable SDIO interrupts. */
		3464	if (sdio_irq_claimed(host->slot->mmc))
		3465	__dw_mci_enable_sdio_irq(host->slot, 1);
		3466
3463	/* Now that slots are all setup, we can enable card detect */	3467	/* Now that slots are all setup, we can enable card detect */
3464	dw_mci_enable_cd(host);	3468	dw_mci_enable_cd(host);
3465		3469

drivers/mmc/host/jz4740_mmc.c+7−12

 #include <asm/cacheflush.h>
-#include <asm/mach-jz4740/dma.h>
 #define JZ_REG_MMC_STRPCL	0x00
 #define JZ_REG_MMC_STATUS	0x04
 #define JZ_REG_MMC_CLKRT	0x08
 				     uint32_t val)
 {
 	if (host->version >= JZ_MMC_JZ4780)
-		return writel(val, host->base + JZ_REG_MMC_IREG);
+		writel(val, host->base + JZ_REG_MMC_IREG);
 	else
-		return writew(val, host->base + JZ_REG_MMC_IREG);
+		writew(val, host->base + JZ_REG_MMC_IREG);
 }
 static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host)
 	if (data->flags & MMC_DATA_WRITE) {
 		conf.direction = DMA_MEM_TO_DEV;
 		conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO;
-		conf.slave_id = JZ4740_DMA_TYPE_MMC_TRANSMIT;
 	} else {
 		conf.direction = DMA_DEV_TO_MEM;
 		conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO;
-		conf.slave_id = JZ4740_DMA_TYPE_MMC_RECEIVE;
 	}
 	sg_count = jz4740_mmc_prepare_dma_data(host, data, COOKIE_MAPPED);
 			del_timer(&host->timeout_timer);
 			if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
-					cmd->error = -ETIMEDOUT;
+				cmd->error = -ETIMEDOUT;
 			} else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
-					cmd->error = -EIO;
+				cmd->error = -EIO;
 			} else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
 				    JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
-					if (cmd->data)
+				if (cmd->data)
-							cmd->data->error = -EIO;
+					cmd->data->error = -EIO;
-					cmd->error = -EIO;
+				cmd->error = -EIO;
 			}
 			jz4740_mmc_set_irq_enabled(host, irq_reg, false);
 	host->irq = platform_get_irq(pdev, 0);
 	if (host->irq < 0) {
 		ret = host->irq;
-		dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
 		goto err_free_host;
 	}

drivers/mmc/host/meson-gx-mmc.c+0−1

@@ -1091,7 +1091,6 @@ static int meson_mmc_probe(struct platform_device *pdev) · 1090 unmodified lines
1091		1091
1092	host->irq = platform_get_irq(pdev, 0);	1092	host->irq = platform_get_irq(pdev, 0);
1093	if (host->irq <= 0) {	1093	if (host->irq <= 0) {
1094	dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1095	ret = -EINVAL;	1094	ret = -EINVAL;
1096	goto free_host;	1095	goto free_host;
1097	}	1096	}

drivers/mmc/host/mmc_spi.c+1−1

@@ -891,7 +891,7 @@ mmc_spi_data_do(struct mmc_spi_host host, struct mmc_command cmd, · 890 unmodified lines
891	/* Handle scatterlist segments one at a time, with synch for	891	/* Handle scatterlist segments one at a time, with synch for
892	* each 512-byte block	892	* each 512-byte block
893	*/	893	*/
894	for (sg = data->sg, n_sg = data->sg_len; n_sg; n_sg--, sg++) {	894	for_each_sg(data->sg, sg, data->sg_len, n_sg) {
895	int status = 0;	895	int status = 0;
896	dma_addr_t dma_addr = 0;	896	dma_addr_t dma_addr = 0;
897	void *kmap_addr;	897	void *kmap_addr;

drivers/mmc/host/mmci.c+37−32

@@ -1219,47 +1219,58 @@ mmci_cmd_irq(struct mmci_host host, struct mmc_command cmd, · 1218 unmodified lines
1219	(MCI_CMDCRCFAIL\|MCI_CMDTIMEOUT\|MCI_CMDSENT\|MCI_CMDRESPEND)))	1219	(MCI_CMDCRCFAIL\|MCI_CMDTIMEOUT\|MCI_CMDSENT\|MCI_CMDRESPEND)))
1220	return;	1220	return;
1221		1221
1222	/*	1222	/* Handle busy detection on DAT0 if the variant supports it. */
1223	* ST Micro variant: handle busy detection.
1224	*/
1225	if (busy_resp && host->variant->busy_detect) {	1223	if (busy_resp && host->variant->busy_detect) {
1226		1224
1227	/* We are busy with a command, return */
1228	if (host->busy_status &&
1229	(status & host->variant->busy_detect_flag))
1230	return;
1231
1232	/*	1225	/*
1233	* We were not busy, but we now got a busy response on	1226	* Before unmasking for the busy end IRQ, confirm that the
1234	* something that was not an error, and we double-check	1227	* command was sent successfully. To keep track of having a
1235	* that the special busy status bit is still set before	1228	* command in-progress, waiting for busy signaling to end,
1236	* proceeding.	1229	* store the status in host->busy_status.
		1230	*
		1231	* Note that, the card may need a couple of clock cycles before
		1232	* it starts signaling busy on DAT0, hence re-read the
		1233	* MMCISTATUS register here, to allow the busy bit to be set.
		1234	* Potentially we may even need to poll the register for a
		1235	* while, to allow it to be set, but tests indicates that it
		1236	* isn't needed.
1237	*/	1237	*/
1238	if (!host->busy_status &&	1238	if (!host->busy_status &&
1239	!(status & (MCI_CMDCRCFAIL\|MCI_CMDTIMEOUT)) &&	1239	!(status & (MCI_CMDCRCFAIL\|MCI_CMDTIMEOUT)) &&
1240	(readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {	1240	(readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
1241		1241
1242	/* Clear the busy start IRQ */
1243	writel(host->variant->busy_detect_mask,
1244	host->base + MMCICLEAR);
1245
1246	/* Unmask the busy end IRQ */
1247	writel(readl(base + MMCIMASK0) \|	1242	writel(readl(base + MMCIMASK0) \|
1248	host->variant->busy_detect_mask,	1243	host->variant->busy_detect_mask,
1249	base + MMCIMASK0);	1244	base + MMCIMASK0);
1250	/*	1245
1251	* Now cache the last response status code (until
1252	* the busy bit goes low), and return.
1253	*/
1254	host->busy_status =	1246	host->busy_status =
1255	status & (MCI_CMDSENT\|MCI_CMDRESPEND);	1247	status & (MCI_CMDSENT\|MCI_CMDRESPEND);
1256	return;	1248	return;
1257	}	1249	}
1258		1250
1259	/*	1251	/*
1260	* At this point we are not busy with a command, we have	1252	* If there is a command in-progress that has been successfully
1261	* not received a new busy request, clear and mask the busy	1253	* sent, then bail out if busy status is set and wait for the
1262	* end IRQ and fall through to process the IRQ.	1254	* busy end IRQ.
		1255	*
		1256	* Note that, the HW triggers an IRQ on both edges while
		1257	* monitoring DAT0 for busy completion, but there is only one
		1258	* status bit in MMCISTATUS for the busy state. Therefore
		1259	* both the start and the end interrupts needs to be cleared,
		1260	* one after the other. So, clear the busy start IRQ here.
		1261	*/
		1262	if (host->busy_status &&
		1263	(status & host->variant->busy_detect_flag)) {
		1264	writel(host->variant->busy_detect_mask,
		1265	host->base + MMCICLEAR);
		1266	return;
		1267	}
		1268
		1269	/*
		1270	* If there is a command in-progress that has been successfully
		1271	* sent and the busy bit isn't set, it means we have received
		1272	* the busy end IRQ. Clear and mask the IRQ, then continue to
		1273	* process the command.
1263	*/	1274	*/
1264	if (host->busy_status) {	1275	if (host->busy_status) {
1265		1276
@@ -1505,14 +1516,8 @@ static irqreturn_t mmci_irq(int irq, void *dev_id) · 239 unmodified lines
1505	}	1516	}
1506		1517
1507	/*	1518	/*
1508	* We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's	1519	* Busy detection is managed by mmci_cmd_irq(), including to
1509	* enabled) in mmci_cmd_irq() function where ST Micro busy	1520	* clear the corresponding IRQ.
1510	* detection variant is handled. Considering the HW seems to be
1511	* triggering the IRQ on both edges while monitoring DAT0 for
1512	* busy completion and that same status bit is used to monitor
1513	* start and end of busy detection, special care must be taken
1514	* to make sure that both start and end interrupts are always
1515	* cleared one after the other.
1516	*/	1521	*/
1517	status &= readl(host->base + MMCIMASK0);	1522	status &= readl(host->base + MMCIMASK0);
1518	if (host->variant->busy_detect)	1523	if (host->variant->busy_detect)

drivers/mmc/host/mtk-sd.c+23−6

@@ -192,6 +192,7 @@ · 191 unmodified lines
192	#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */	192	#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
193	#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */	193	#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
194		194
		195	#define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */
195	/* SDC_ADV_CFG0 mask */	196	/* SDC_ADV_CFG0 mask */
196	#define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */	197	#define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
197		198
@@ -328,6 +329,7 @@ struct mt_bdma_desc { · 130 unmodified lines
328	u32 ptr;	329	u32 ptr;
329	u32 bd_data_len;	330	u32 bd_data_len;
330	#define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */	331	#define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
		332	#define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */
331	};	333	};
332		334
333	struct msdc_dma {	335	struct msdc_dma {
@@ -641,8 +643,14 @@ static inline void msdc_dma_setup(struct msdc_host host, struct msdc_dma dma, · 307 unmodified lines
641	bd[j].bd_info \|= (upper_32_bits(dma_address) & 0xf)	643	bd[j].bd_info \|= (upper_32_bits(dma_address) & 0xf)
642	<< 28;	644	<< 28;
643	}	645	}
644	bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;	646
645	bd[j].bd_data_len \|= (dma_len & BDMA_DESC_BUFLEN);	647	if (host->dev_comp->support_64g) {
		648	bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
		649	bd[j].bd_data_len \|= (dma_len & BDMA_DESC_BUFLEN_EXT);
		650	} else {
		651	bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
		652	bd[j].bd_data_len \|= (dma_len & BDMA_DESC_BUFLEN);
		653	}
646		654
647	if (j == data->sg_count - 1) /* the last bd */	655	if (j == data->sg_count - 1) /* the last bd */
648	bd[j].bd_info \|= BDMA_DESC_EOL;	656	bd[j].bd_info \|= BDMA_DESC_EOL;
@@ -1071,11 +1079,13 @@ static bool msdc_cmd_done(struct msdc_host *host, int events, · 422 unmodified lines
1071	}	1079	}
1072		1080
1073	if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {	1081	if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1074	if (cmd->opcode != MMC_SEND_TUNING_BLOCK &&	1082	if (events & MSDC_INT_CMDTMO \|\|
1075	cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)	1083	(cmd->opcode != MMC_SEND_TUNING_BLOCK &&
		1084	cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1076	/*	1085	/*
1077	* should not clear fifo/interrupt as the tune data	1086	* should not clear fifo/interrupt as the tune data
1078	* may have alreay come.	1087	* may have alreay come when cmd19/cmd21 gets response
		1088	* CRC error.
1079	*/	1089	*/
1080	msdc_reset_hw(host);	1090	msdc_reset_hw(host);
1081	if (events & MSDC_INT_RSPCRCERR) {	1091	if (events & MSDC_INT_RSPCRCERR) {
@@ -1568,6 +1578,7 @@ static void msdc_init_hw(struct msdc_host *host) · 486 unmodified lines
1568		1578
1569	/* Config SDIO device detect interrupt function */	1579	/* Config SDIO device detect interrupt function */
1570	sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);	1580	sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
		1581	sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1571		1582
1572	/* Configure to default data timeout */	1583	/* Configure to default data timeout */
1573	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);	1584	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
@@ -2275,7 +2286,10 @@ static int msdc_drv_probe(struct platform_device *pdev) · 701 unmodified lines
2275	mmc->caps \|= MMC_CAP_ERASE \| MMC_CAP_CMD23;	2286	mmc->caps \|= MMC_CAP_ERASE \| MMC_CAP_CMD23;
2276	/* MMC core transfer sizes tunable parameters */	2287	/* MMC core transfer sizes tunable parameters */
2277	mmc->max_segs = MAX_BD_NUM;	2288	mmc->max_segs = MAX_BD_NUM;
2278	mmc->max_seg_size = BDMA_DESC_BUFLEN;	2289	if (host->dev_comp->support_64g)
		2290	mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
		2291	else
		2292	mmc->max_seg_size = BDMA_DESC_BUFLEN;
2279	mmc->max_blk_size = 2048;	2293	mmc->max_blk_size = 2048;
2280	mmc->max_req_size = 512 * 1024;	2294	mmc->max_req_size = 512 * 1024;
2281	mmc->max_blk_count = mmc->max_req_size / 512;	2295	mmc->max_blk_count = mmc->max_req_size / 512;
@@ -2421,6 +2435,9 @@ static void msdc_restore_reg(struct msdc_host *host) · 139 unmodified lines
2421	} else {	2435	} else {
2422	writel(host->save_para.pad_tune, host->base + tune_reg);	2436	writel(host->save_para.pad_tune, host->base + tune_reg);
2423	}	2437	}
		2438
		2439	if (sdio_irq_claimed(host->mmc))
		2440	__msdc_enable_sdio_irq(host, 1);
2424	}	2441	}
2425		2442
2426	static int msdc_runtime_suspend(struct device *dev)	2443	static int msdc_runtime_suspend(struct device *dev)

drivers/mmc/host/mxcmmc.c+1−3

 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	irq = platform_get_irq(pdev, 0);
-	if (irq < 0) {
+	if (irq < 0)
-		dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq);
 		return irq;
-	}
 	mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
 	if (!mmc)

drivers/mmc/host/mxs-mmc.c+1−3

 	struct device_node *np = pdev->dev.of_node;
 	struct mxs_mmc_host *host;
 	struct mmc_host *mmc;
-	struct resource *iores;
 	int ret = 0, irq_err;
 	struct regulator *reg_vmmc;
 	struct mxs_ssp *ssp;
 	host = mmc_priv(mmc);
 	ssp = &host->ssp;
 	ssp->dev = &pdev->dev;
-	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	ssp->base = devm_platform_ioremap_resource(pdev, 0);
-	ssp->base = devm_ioremap_resource(&pdev->dev, iores);
 	if (IS_ERR(ssp->base)) {
 		ret = PTR_ERR(ssp->base);
 		goto out_mmc_free;

drivers/mmc/host/renesas_sdhi_core.c+8−5

 {
 	struct renesas_sdhi *priv = host_to_priv(host);
 	unsigned int freq, diff, best_freq = 0, diff_min = ~0;
-	int i, ret;
+	int i;
 	/* tested only on R-Car Gen2+ currently; may work for others */
 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 		}
 	}
-	ret = clk_set_rate(priv->clk, best_freq);
+	clk_set_rate(priv->clk, best_freq);
-	return ret == 0 ? best_freq : clk_get_rate(priv->clk);
+	return clk_get_rate(priv->clk);
 }
 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
-	if (new_clock == 0)
+	if (new_clock == 0) {
+		host->mmc->actual_clock = 0;
 		goto out;
+	}
-	clock = renesas_sdhi_clk_update(host, new_clock) / 512;
+	host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
+	clock = host->mmc->actual_clock / 512;
 	for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
 		clock <<= 1;

drivers/mmc/host/renesas_sdhi_sys_dmac.c+0−36

@@ -68,26 +68,6 @@ static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = { · 67 unmodified lines
68	.max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,	68	.max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
69	};	69	};
70		70
71	/* Definitions for sampling clocks */
72	static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
73	{
74	.clk_rate = 0,
75	.tap = 0x00000300,
76	},
77	};
78
79	static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
80	.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT \| TMIO_MMC_CLK_ACTUAL \|
81	TMIO_MMC_HAVE_CBSY \| TMIO_MMC_MIN_RCAR2,
82	.capabilities = MMC_CAP_SD_HIGHSPEED \| MMC_CAP_SDIO_IRQ \|
83	MMC_CAP_CMD23,
84	.capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
85	.bus_shift = 2,
86	.scc_offset = 0x1000,
87	.taps = rcar_gen3_scc_taps,
88	.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
89	};
90
91	static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {	71	static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
92	{ .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },	72	{ .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
93	{ .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },	73	{ .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
@@ -102,11 +82,8 @@ static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = { · 8 unmodified lines
102	{ .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },	82	{ .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
103	{ .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },	83	{ .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
104	{ .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },	84	{ .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
105	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
106	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
107	{ .compatible = "renesas,rcar-gen1-sdhi", .data = &of_rcar_gen1_compatible, },	85	{ .compatible = "renesas,rcar-gen1-sdhi", .data = &of_rcar_gen1_compatible, },
108	{ .compatible = "renesas,rcar-gen2-sdhi", .data = &of_rcar_gen2_compatible, },	86	{ .compatible = "renesas,rcar-gen2-sdhi", .data = &of_rcar_gen2_compatible, },
109	{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
110	{ .compatible = "renesas,sdhi-shmobile" },	87	{ .compatible = "renesas,sdhi-shmobile" },
111	{},	88	{},
112	};	89	};
@@ -470,21 +447,8 @@ static const struct tmio_mmc_dma_ops renesas_sdhi_sys_dmac_dma_ops = { · 357 unmodified lines
470	.dataend = renesas_sdhi_sys_dmac_dataend_dma,	447	.dataend = renesas_sdhi_sys_dmac_dataend_dma,
471	};	448	};
472		449
473	/*
474	* Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
475	* implementation. Currently empty as all supported ES versions use
476	* the internal DMAC.
477	*/
478	static const struct soc_device_attribute gen3_soc_whitelist[] = {
479	{ /* sentinel */ }
480	};
481
482	static int renesas_sdhi_sys_dmac_probe(struct platform_device *pdev)	450	static int renesas_sdhi_sys_dmac_probe(struct platform_device *pdev)
483	{	451	{
484	if (of_device_get_match_data(&pdev->dev) == &of_rcar_gen3_compatible &&
485	!soc_device_match(gen3_soc_whitelist))
486	return -ENODEV;
487
488	return renesas_sdhi_probe(pdev, &renesas_sdhi_sys_dmac_dma_ops);	452	return renesas_sdhi_probe(pdev, &renesas_sdhi_sys_dmac_dma_ops);
489	}	453	}
490		454

drivers/mmc/host/s3cmci.c+0−1

@@ -1614,7 +1614,6 @@ static int s3cmci_probe(struct platform_device *pdev) · 1613 unmodified lines
1614		1614
1615	host->irq = platform_get_irq(pdev, 0);	1615	host->irq = platform_get_irq(pdev, 0);
1616	if (host->irq <= 0) {	1616	if (host->irq <= 0) {
1617	dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1618	ret = -EINVAL;	1617	ret = -EINVAL;
1619	goto probe_iounmap;	1618	goto probe_iounmap;
1620	}	1619	}

drivers/mmc/host/sdhci-cadence.c+4−3

 	struct sdhci_pltfm_host *pltfm_host;
 	struct sdhci_cdns_priv *priv;
 	struct clk *clk;
-	size_t priv_size;
 	unsigned int nr_phy_params;
 	int ret;
 	struct device *dev = &pdev->dev;
+	static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;
 	clk = devm_clk_get(dev, NULL);
 	if (IS_ERR(clk))
 		return ret;
 	nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
-	priv_size = sizeof(*priv) + sizeof(priv->phy_params[0]) * nr_phy_params;
+	host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data,
-	host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data, priv_size);
+				struct_size(priv, phy_params, nr_phy_params));
 	if (IS_ERR(host)) {
 		ret = PTR_ERR(host);
 		goto disable_clk;
 	host->mmc_host_ops.hs400_enhanced_strobe =
 				sdhci_cdns_hs400_enhanced_strobe;
 	sdhci_enable_v4_mode(host);
+	__sdhci_read_caps(host, &version, NULL, NULL);
 	sdhci_get_of_property(pdev);

drivers/mmc/host/sdhci-esdhc-imx.c+15−19

@@ -1666,12 +1666,10 @@ static int sdhci_esdhc_runtime_suspend(struct device *dev) · 1665 unmodified lines
1666	if (host->tuning_mode != SDHCI_TUNING_MODE_3)	1666	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1667	mmc_retune_needed(host->mmc);	1667	mmc_retune_needed(host->mmc);
1668		1668
1669	if (!sdhci_sdio_irq_enabled(host)) {	1669	imx_data->actual_clock = host->mmc->actual_clock;
1670	imx_data->actual_clock = host->mmc->actual_clock;	1670	esdhc_pltfm_set_clock(host, 0);
1671	esdhc_pltfm_set_clock(host, 0);	1671	clk_disable_unprepare(imx_data->clk_per);
1672	clk_disable_unprepare(imx_data->clk_per);	1672	clk_disable_unprepare(imx_data->clk_ipg);
1673	clk_disable_unprepare(imx_data->clk_ipg);
1674	}
1675	clk_disable_unprepare(imx_data->clk_ahb);	1673	clk_disable_unprepare(imx_data->clk_ahb);
1676		1674
1677	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)	1675	if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
@@ -1695,15 +1693,15 @@ static int sdhci_esdhc_runtime_resume(struct device *dev) · 17 unmodified lines
1695	if (err)	1693	if (err)
1696	goto remove_pm_qos_request;	1694	goto remove_pm_qos_request;
1697		1695
1698	if (!sdhci_sdio_irq_enabled(host)) {	1696	err = clk_prepare_enable(imx_data->clk_per);
1699	err = clk_prepare_enable(imx_data->clk_per);	1697	if (err)
1700	if (err)	1698	goto disable_ahb_clk;
1701	goto disable_ahb_clk;	1699
1702	err = clk_prepare_enable(imx_data->clk_ipg);	1700	err = clk_prepare_enable(imx_data->clk_ipg);
1703	if (err)	1701	if (err)
1704	goto disable_per_clk;	1702	goto disable_per_clk;
1705	esdhc_pltfm_set_clock(host, imx_data->actual_clock);	1703
1706	}	1704	esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1707		1705
1708	err = sdhci_runtime_resume_host(host, 0);	1706	err = sdhci_runtime_resume_host(host, 0);
1709	if (err)	1707	if (err)
@@ -1715,11 +1713,9 @@ static int sdhci_esdhc_runtime_resume(struct device *dev) · 5 unmodified lines
1715	return err;	1713	return err;
1716		1714
1717	disable_ipg_clk:	1715	disable_ipg_clk:
1718	if (!sdhci_sdio_irq_enabled(host))	1716	clk_disable_unprepare(imx_data->clk_ipg);
1719	clk_disable_unprepare(imx_data->clk_ipg);
1720	disable_per_clk:	1717	disable_per_clk:
1721	if (!sdhci_sdio_irq_enabled(host))	1718	clk_disable_unprepare(imx_data->clk_per);
1722	clk_disable_unprepare(imx_data->clk_per);
1723	disable_ahb_clk:	1719	disable_ahb_clk:
1724	clk_disable_unprepare(imx_data->clk_ahb);	1720	clk_disable_unprepare(imx_data->clk_ahb);
1725	remove_pm_qos_request:	1721	remove_pm_qos_request:

drivers/mmc/host/sdhci-iproc.c+9−0

@@ -261,8 +261,17 @@ static const struct sdhci_iproc_data bcm2835_data = { · 260 unmodified lines
261	.mmc_caps = 0x00000000,	261	.mmc_caps = 0x00000000,
262	};	262	};
263		263
		264	static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
		265	.ops = &sdhci_iproc_32only_ops,
		266	};
		267
		268	static const struct sdhci_iproc_data bcm2711_data = {
		269	.pdata = &sdhci_bcm2711_pltfm_data,
		270	};
		271
264	static const struct of_device_id sdhci_iproc_of_match[] = {	272	static const struct of_device_id sdhci_iproc_of_match[] = {
265	{ .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },	273	{ .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
		274	{ .compatible = "brcm,bcm2711-emmc2", .data = &bcm2711_data },
266	{ .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},	275	{ .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
267	{ .compatible = "brcm,sdhci-iproc", .data = &iproc_data },	276	{ .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
268	{ }	277	{ }

drivers/mmc/host/sdhci-msm.c+0−2

 	/* Setup IRQ for handling power/voltage tasks with PMIC */
 	msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
 	if (msm_host->pwr_irq < 0) {
-		dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
-			msm_host->pwr_irq);
 		ret = msm_host->pwr_irq;
 		goto clk_disable;
 	}

drivers/mmc/host/sdhci-of-arasan.c+15−0

 	.hiword_update = true,
 };
+static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
+	.baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
+	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
+	.hiword_update = false,
+};
 /**
  * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
  *
 	.pdata = &sdhci_arasan_cqe_pdata,
 };
+static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
+	.soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
+	.pdata = &sdhci_arasan_cqe_pdata,
+};
 #ifdef CONFIG_PM_SLEEP
 /**
  * sdhci_arasan_suspend - Suspend method for the driver
 		.compatible = "rockchip,rk3399-sdhci-5.1",
 		.data = &sdhci_arasan_rk3399_data,
 	},
+	{
+		.compatible = "intel,lgm-sdhci-5.1-emmc",
+		.data = &intel_lgm_emmc_data,
+	},
 	/* Generic compatible below here */
 	{
 		.compatible = "arasan,sdhci-8.9a",

drivers/mmc/host/sdhci-of-aspeed.c+342−0

@@ -0,0 +1,342 @@
	1	// SPDX-License-Identifier: GPL-2.0-or-later
	2	/* Copyright (C) 2019 ASPEED Technology Inc. */
	3	/* Copyright (C) 2019 IBM Corp. */
	4
	5	#include <linux/clk.h>
	6	#include <linux/delay.h>
	7	#include <linux/device.h>
	8	#include <linux/io.h>
	9	#include <linux/mmc/host.h>
	10	#include <linux/module.h>
	11	#include <linux/of_address.h>
	12	#include <linux/of.h>
	13	#include <linux/of_platform.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/spinlock.h>
	16
	17	#include "sdhci-pltfm.h"
	18
	19	#define ASPEED_SDC_INFO 0x00
	20	#define ASPEED_SDC_S1MMC8 BIT(25)
	21	#define ASPEED_SDC_S0MMC8 BIT(24)
	22
	23	struct aspeed_sdc {
	24	struct clk *clk;
	25	struct resource *res;
	26
	27	spinlock_t lock;
	28	void __iomem *regs;
	29	};
	30
	31	struct aspeed_sdhci {
	32	struct aspeed_sdc *parent;
	33	u32 width_mask;
	34	};
	35
	36	static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc,
	37	struct aspeed_sdhci *sdhci,
	38	bool bus8)
	39	{
	40	u32 info;
	41
	42	/* Set/clear 8 bit mode */
	43	spin_lock(&sdc->lock);
	44	info = readl(sdc->regs + ASPEED_SDC_INFO);
	45	if (bus8)
	46	info \|= sdhci->width_mask;
	47	else
	48	info &= ~sdhci->width_mask;
	49	writel(info, sdc->regs + ASPEED_SDC_INFO);
	50	spin_unlock(&sdc->lock);
	51	}
	52
	53	static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
	54	{
	55	struct sdhci_pltfm_host *pltfm_host;
	56	unsigned long parent;
	57	int div;
	58	u16 clk;
	59
	60	pltfm_host = sdhci_priv(host);
	61	parent = clk_get_rate(pltfm_host->clk);
	62
	63	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
	64
	65	if (clock == 0)
	66	return;
	67
	68	if (WARN_ON(clock > host->max_clk))
	69	clock = host->max_clk;
	70
	71	for (div = 1; div < 256; div *= 2) {
	72	if ((parent / div) <= clock)
	73	break;
	74	}
	75	div >>= 1;
	76
	77	clk = div << SDHCI_DIVIDER_SHIFT;
	78
	79	sdhci_enable_clk(host, clk);
	80	}
	81
	82	static unsigned int aspeed_sdhci_get_max_clock(struct sdhci_host *host)
	83	{
	84	if (host->mmc->f_max)
	85	return host->mmc->f_max;
	86
	87	return sdhci_pltfm_clk_get_max_clock(host);
	88	}
	89
	90	static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width)
	91	{
	92	struct sdhci_pltfm_host *pltfm_priv;
	93	struct aspeed_sdhci *aspeed_sdhci;
	94	struct aspeed_sdc *aspeed_sdc;
	95	u8 ctrl;
	96
	97	pltfm_priv = sdhci_priv(host);
	98	aspeed_sdhci = sdhci_pltfm_priv(pltfm_priv);
	99	aspeed_sdc = aspeed_sdhci->parent;
	100
	101	/* Set/clear 8-bit mode */
	102	aspeed_sdc_configure_8bit_mode(aspeed_sdc, aspeed_sdhci,
	103	width == MMC_BUS_WIDTH_8);
	104
	105	/* Set/clear 1 or 4 bit mode */
	106	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	107	if (width == MMC_BUS_WIDTH_4)
	108	ctrl \|= SDHCI_CTRL_4BITBUS;
	109	else
	110	ctrl &= ~SDHCI_CTRL_4BITBUS;
	111	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
	112	}
	113
	114	static const struct sdhci_ops aspeed_sdhci_ops = {
	115	.set_clock = aspeed_sdhci_set_clock,
	116	.get_max_clock = aspeed_sdhci_get_max_clock,
	117	.set_bus_width = aspeed_sdhci_set_bus_width,
	118	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
	119	.reset = sdhci_reset,
	120	.set_uhs_signaling = sdhci_set_uhs_signaling,
	121	};
	122
	123	static const struct sdhci_pltfm_data aspeed_sdhci_pdata = {
	124	.ops = &aspeed_sdhci_ops,
	125	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	126	};
	127
	128	static inline int aspeed_sdhci_calculate_slot(struct aspeed_sdhci *dev,
	129	struct resource *res)
	130	{
	131	resource_size_t delta;
	132
	133	if (!res \|\| resource_type(res) != IORESOURCE_MEM)
	134	return -EINVAL;
	135
	136	if (res->start < dev->parent->res->start)
	137	return -EINVAL;
	138
	139	delta = res->start - dev->parent->res->start;
	140	if (delta & (0x100 - 1))
	141	return -EINVAL;
	142
	143	return (delta / 0x100) - 1;
	144	}
	145
	146	static int aspeed_sdhci_probe(struct platform_device *pdev)
	147	{
	148	struct sdhci_pltfm_host *pltfm_host;
	149	struct aspeed_sdhci *dev;
	150	struct sdhci_host *host;
	151	struct resource *res;
	152	int slot;
	153	int ret;
	154
	155	host = sdhci_pltfm_init(pdev, &aspeed_sdhci_pdata, sizeof(*dev));
	156	if (IS_ERR(host))
	157	return PTR_ERR(host);
	158
	159	pltfm_host = sdhci_priv(host);
	160	dev = sdhci_pltfm_priv(pltfm_host);
	161	dev->parent = dev_get_drvdata(pdev->dev.parent);
	162
	163	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	164	slot = aspeed_sdhci_calculate_slot(dev, res);
	165
	166	if (slot < 0)
	167	return slot;
	168	else if (slot >= 2)
	169	return -EINVAL;
	170
	171	dev_info(&pdev->dev, "Configuring for slot %d\n", slot);
	172	dev->width_mask = !slot ? ASPEED_SDC_S0MMC8 : ASPEED_SDC_S1MMC8;
	173
	174	sdhci_get_of_property(pdev);
	175
	176	pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);
	177	if (IS_ERR(pltfm_host->clk))
	178	return PTR_ERR(pltfm_host->clk);
	179
	180	ret = clk_prepare_enable(pltfm_host->clk);
	181	if (ret) {
	182	dev_err(&pdev->dev, "Unable to enable SDIO clock\n");
	183	goto err_pltfm_free;
	184	}
	185
	186	ret = mmc_of_parse(host->mmc);
	187	if (ret)
	188	goto err_sdhci_add;
	189
	190	ret = sdhci_add_host(host);
	191	if (ret)
	192	goto err_sdhci_add;
	193
	194	return 0;
	195
	196	err_sdhci_add:
	197	clk_disable_unprepare(pltfm_host->clk);
	198	err_pltfm_free:
	199	sdhci_pltfm_free(pdev);
	200	return ret;
	201	}
	202
	203	static int aspeed_sdhci_remove(struct platform_device *pdev)
	204	{
	205	struct sdhci_pltfm_host *pltfm_host;
	206	struct sdhci_host *host;
	207	int dead = 0;
	208
	209	host = platform_get_drvdata(pdev);
	210	pltfm_host = sdhci_priv(host);
	211
	212	sdhci_remove_host(host, dead);
	213
	214	clk_disable_unprepare(pltfm_host->clk);
	215
	216	sdhci_pltfm_free(pdev);
	217
	218	return 0;
	219	}
	220
	221	static const struct of_device_id aspeed_sdhci_of_match[] = {
	222	{ .compatible = "aspeed,ast2400-sdhci", },
	223	{ .compatible = "aspeed,ast2500-sdhci", },
	224	{ .compatible = "aspeed,ast2600-sdhci", },
	225	{ }
	226	};
	227
	228	static struct platform_driver aspeed_sdhci_driver = {
	229	.driver = {
	230	.name = "sdhci-aspeed",
	231	.of_match_table = aspeed_sdhci_of_match,
	232	},
	233	.probe = aspeed_sdhci_probe,
	234	.remove = aspeed_sdhci_remove,
	235	};
	236
	237	static int aspeed_sdc_probe(struct platform_device *pdev)
	238
	239	{
	240	struct device_node parent, child;
	241	struct aspeed_sdc *sdc;
	242	int ret;
	243
	244	sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);
	245	if (!sdc)
	246	return -ENOMEM;
	247
	248	spin_lock_init(&sdc->lock);
	249
	250	sdc->clk = devm_clk_get(&pdev->dev, NULL);
	251	if (IS_ERR(sdc->clk))
	252	return PTR_ERR(sdc->clk);
	253
	254	ret = clk_prepare_enable(sdc->clk);
	255	if (ret) {
	256	dev_err(&pdev->dev, "Unable to enable SDCLK\n");
	257	return ret;
	258	}
	259
	260	sdc->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	261	sdc->regs = devm_ioremap_resource(&pdev->dev, sdc->res);
	262	if (IS_ERR(sdc->regs)) {
	263	ret = PTR_ERR(sdc->regs);
	264	goto err_clk;
	265	}
	266
	267	dev_set_drvdata(&pdev->dev, sdc);
	268
	269	parent = pdev->dev.of_node;
	270	for_each_available_child_of_node(parent, child) {
	271	struct platform_device *cpdev;
	272
	273	cpdev = of_platform_device_create(child, NULL, &pdev->dev);
	274	if (!cpdev) {
	275	of_node_put(child);
	276	ret = -ENODEV;
	277	goto err_clk;
	278	}
	279	}
	280
	281	return 0;
	282
	283	err_clk:
	284	clk_disable_unprepare(sdc->clk);
	285	return ret;
	286	}
	287
	288	static int aspeed_sdc_remove(struct platform_device *pdev)
	289	{
	290	struct aspeed_sdc *sdc = dev_get_drvdata(&pdev->dev);
	291
	292	clk_disable_unprepare(sdc->clk);
	293
	294	return 0;
	295	}
	296
	297	static const struct of_device_id aspeed_sdc_of_match[] = {
	298	{ .compatible = "aspeed,ast2400-sd-controller", },
	299	{ .compatible = "aspeed,ast2500-sd-controller", },
	300	{ .compatible = "aspeed,ast2600-sd-controller", },
	301	{ }
	302	};
	303
	304	MODULE_DEVICE_TABLE(of, aspeed_sdc_of_match);
	305
	306	static struct platform_driver aspeed_sdc_driver = {
	307	.driver = {
	308	.name = "sd-controller-aspeed",
	309	.pm = &sdhci_pltfm_pmops,
	310	.of_match_table = aspeed_sdc_of_match,
	311	},
	312	.probe = aspeed_sdc_probe,
	313	.remove = aspeed_sdc_remove,
	314	};
	315
	316	static int __init aspeed_sdc_init(void)
	317	{
	318	int rc;
	319
	320	rc = platform_driver_register(&aspeed_sdhci_driver);
	321	if (rc < 0)
	322	return rc;
	323
	324	rc = platform_driver_register(&aspeed_sdc_driver);
	325	if (rc < 0)
	326	platform_driver_unregister(&aspeed_sdhci_driver);
	327
	328	return rc;
	329	}
	330	module_init(aspeed_sdc_init);
	331
	332	static void __exit aspeed_sdc_exit(void)
	333	{
	334	platform_driver_unregister(&aspeed_sdc_driver);
	335	platform_driver_unregister(&aspeed_sdhci_driver);
	336	}
	337	module_exit(aspeed_sdc_exit);
	338
	339	MODULE_DESCRIPTION("Driver for the ASPEED SD/SDIO/SDHCI Controllers");
	340	MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>");
	341	MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>");
	342	MODULE_LICENSE("GPL");

drivers/mmc/host/sdhci-of-esdhc.c+1−0

@@ -999,6 +999,7 @@ static struct soc_device_attribute soc_incorrect_hostver[] = { · 998 unmodified lines
999	static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = {	999	static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = {
1000	{ .family = "QorIQ LX2160A", .revision = "1.0", },	1000	{ .family = "QorIQ LX2160A", .revision = "1.0", },
1001	{ .family = "QorIQ LX2160A", .revision = "2.0", },	1001	{ .family = "QorIQ LX2160A", .revision = "2.0", },
		1002	{ .family = "QorIQ LS1028A", .revision = "1.0", },
1002	{ },	1003	{ },
1003	};	1004	};
1004		1005

drivers/mmc/host/sdhci-pci-core.c+5−8

 	SDHCI_PCI_DEVICE(INTEL, EHL_SD,    intel_byt_sd),
 	SDHCI_PCI_DEVICE(INTEL, CML_EMMC,  intel_glk_emmc),
 	SDHCI_PCI_DEVICE(INTEL, CML_SD,    intel_byt_sd),
+	SDHCI_PCI_DEVICE(INTEL, CMLH_SD,   intel_byt_sd),
 	SDHCI_PCI_DEVICE(O2, 8120,     o2),
 	SDHCI_PCI_DEVICE(O2, 8220,     o2),
 	SDHCI_PCI_DEVICE(O2, 8221,     o2),
 #ifdef CONFIG_PM_SLEEP
 static int sdhci_pci_suspend(struct device *dev)
 {
-	struct pci_dev *pdev = to_pci_dev(dev);
+	struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
-	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
 	if (!chip)
 		return 0;
 static int sdhci_pci_resume(struct device *dev)
 {
-	struct pci_dev *pdev = to_pci_dev(dev);
+	struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
-	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
 	if (!chip)
 		return 0;
 #ifdef CONFIG_PM
 static int sdhci_pci_runtime_suspend(struct device *dev)
 {
-	struct pci_dev *pdev = to_pci_dev(dev);
+	struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
-	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
 	if (!chip)
 		return 0;
 static int sdhci_pci_runtime_resume(struct device *dev)
 {
-	struct pci_dev *pdev = to_pci_dev(dev);
+	struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
-	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
 	if (!chip)
 		return 0;

drivers/mmc/host/sdhci-pci-o2micro.c+216−95

@@ -11,6 +11,7 @@ · 10 unmodified lines
11	#include <linux/mmc/host.h>	11	#include <linux/mmc/host.h>
12	#include <linux/mmc/mmc.h>	12	#include <linux/mmc/mmc.h>
13	#include <linux/delay.h>	13	#include <linux/delay.h>
		14	#include <linux/iopoll.h>
14		15
15	#include "sdhci.h"	16	#include "sdhci.h"
16	#include "sdhci-pci.h"	17	#include "sdhci-pci.h"
@@ -51,13 +52,136 @@ · 34 unmodified lines
51	#define O2_SD_VENDOR_SETTING2 0x1C8	52	#define O2_SD_VENDOR_SETTING2 0x1C8
52	#define O2_SD_HW_TUNING_DISABLE BIT(4)	53	#define O2_SD_HW_TUNING_DISABLE BIT(4)
53		54
54	#define O2_PLL_WDT_CONTROL1 0x1CC	55	#define O2_PLL_DLL_WDT_CONTROL1 0x1CC
55	#define O2_PLL_FORCE_ACTIVE BIT(18)	56	#define O2_PLL_FORCE_ACTIVE BIT(18)
56	#define O2_PLL_LOCK_STATUS BIT(14)	57	#define O2_PLL_LOCK_STATUS BIT(14)
57	#define O2_PLL_SOFT_RESET BIT(12)	58	#define O2_PLL_SOFT_RESET BIT(12)
		59	#define O2_DLL_LOCK_STATUS BIT(11)
58		60
59	#define O2_SD_DETECT_SETTING 0x324	61	#define O2_SD_DETECT_SETTING 0x324
60		62
		63	static const u32 dmdn_table[] = {0x2B1C0000,
		64	0x2C1A0000, 0x371B0000, 0x35100000};
		65	#define DMDN_SZ ARRAY_SIZE(dmdn_table)
		66
		67	struct o2_host {
		68	u8 dll_adjust_count;
		69	};
		70
		71	static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
		72	{
		73	ktime_t timeout;
		74	u32 scratch32;
		75
		76	/* Wait max 50 ms */
		77	timeout = ktime_add_ms(ktime_get(), 50);
		78	while (1) {
		79	bool timedout = ktime_after(ktime_get(), timeout);
		80
		81	scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
		82	if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
		83	== (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
		84	break;
		85
		86	if (timedout) {
		87	pr_err("%s: Card Detect debounce never finished.\n",
		88	mmc_hostname(host->mmc));
		89	sdhci_dumpregs(host);
		90	return;
		91	}
		92	udelay(10);
		93	}
		94	}
		95
		96	static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
		97	{
		98	ktime_t timeout;
		99	u16 scratch;
		100	u32 scratch32;
		101
		102	/* PLL software reset */
		103	scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
		104	scratch32 \|= O2_PLL_SOFT_RESET;
		105	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
		106	udelay(1);
		107	scratch32 &= ~(O2_PLL_SOFT_RESET);
		108	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
		109
		110	/* PLL force active */
		111	scratch32 \|= O2_PLL_FORCE_ACTIVE;
		112	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
		113
		114	/* Wait max 20 ms */
		115	timeout = ktime_add_ms(ktime_get(), 20);
		116	while (1) {
		117	bool timedout = ktime_after(ktime_get(), timeout);
		118
		119	scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
		120	if (scratch & O2_PLL_LOCK_STATUS)
		121	break;
		122	if (timedout) {
		123	pr_err("%s: Internal clock never stabilised.\n",
		124	mmc_hostname(host->mmc));
		125	sdhci_dumpregs(host);
		126	goto out;
		127	}
		128	udelay(10);
		129	}
		130
		131	/* Wait for card detect finish */
		132	udelay(1);
		133	sdhci_o2_wait_card_detect_stable(host);
		134
		135	out:
		136	/* Cancel PLL force active */
		137	scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
		138	scratch32 &= ~O2_PLL_FORCE_ACTIVE;
		139	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
		140	}
		141
		142	static int sdhci_o2_get_cd(struct mmc_host *mmc)
		143	{
		144	struct sdhci_host *host = mmc_priv(mmc);
		145
		146	if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
		147	sdhci_o2_enable_internal_clock(host);
		148
		149	return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
		150	}
		151
		152	static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
		153	{
		154	u32 scratch_32;
		155
		156	pci_read_config_dword(chip->pdev,
		157	O2_SD_PLL_SETTING, &scratch_32);
		158
		159	scratch_32 &= 0x0000FFFF;
		160	scratch_32 \|= value;
		161
		162	pci_write_config_dword(chip->pdev,
		163	O2_SD_PLL_SETTING, scratch_32);
		164	}
		165
		166	static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
		167	{
		168	return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
		169	}
		170
		171	/*
		172	* This function is used to detect dll lock status.
		173	* Since the dll lock status bit will toggle randomly
		174	* with very short interval which needs to be polled
		175	* as fast as possible. Set sleep_us as 1 microsecond.
		176	*/
		177	static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
		178	{
		179	u32 scratch32 = 0;
		180
		181	return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
		182	scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
		183	}
		184
61	static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)	185	static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
62	{	186	{
63	u16 reg;	187	u16 reg;
@@ -95,6 +219,83 @@ static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode) · 31 unmodified lines
95	sdhci_reset_tuning(host);	219	sdhci_reset_tuning(host);
96	}	220	}
97		221
		222	/*
		223	* This function is used to fix o2 dll shift issue.
		224	* It isn't necessary to detect card present before recovery.
		225	* Firstly, it is used by bht emmc card, which is embedded.
		226	* Second, before call recovery card present will be detected
		227	* outside of the execute tuning function.
		228	*/
		229	static int sdhci_o2_dll_recovery(struct sdhci_host *host)
		230	{
		231	int ret = 0;
		232	u8 scratch_8 = 0;
		233	u32 scratch_32 = 0;
		234	struct sdhci_pci_slot *slot = sdhci_priv(host);
		235	struct sdhci_pci_chip *chip = slot->chip;
		236	struct o2_host *o2_host = sdhci_pci_priv(slot);
		237
		238	/* UnLock WP */
		239	pci_read_config_byte(chip->pdev,
		240	O2_SD_LOCK_WP, &scratch_8);
		241	scratch_8 &= 0x7f;
		242	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
		243	while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
		244	/* Disable clock */
		245	sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
		246
		247	/* PLL software reset */
		248	scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
		249	scratch_32 \|= O2_PLL_SOFT_RESET;
		250	sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
		251
		252	pci_read_config_dword(chip->pdev,
		253	O2_SD_FUNC_REG4,
		254	&scratch_32);
		255	/* Enable Base Clk setting change */
		256	scratch_32 \|= O2_SD_FREG4_ENABLE_CLK_SET;
		257	pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
		258	o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
		259
		260	/* Enable internal clock */
		261	scratch_8 = SDHCI_CLOCK_INT_EN;
		262	sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
		263
		264	if (sdhci_o2_get_cd(host->mmc)) {
		265	/*
		266	* need wait at least 5ms for dll status stable,
		267	* after enable internal clock
		268	*/
		269	usleep_range(5000, 6000);
		270	if (sdhci_o2_wait_dll_detect_lock(host)) {
		271	scratch_8 \|= SDHCI_CLOCK_CARD_EN;
		272	sdhci_writeb(host, scratch_8,
		273	SDHCI_CLOCK_CONTROL);
		274	ret = 1;
		275	} else {
		276	pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
		277	mmc_hostname(host->mmc),
		278	o2_host->dll_adjust_count);
		279	}
		280	} else {
		281	pr_err("%s: card present detect failed.\n",
		282	mmc_hostname(host->mmc));
		283	break;
		284	}
		285
		286	o2_host->dll_adjust_count++;
		287	}
		288	if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
		289	pr_err("%s: DLL adjust over max times\n",
		290	mmc_hostname(host->mmc));
		291	/* Lock WP */
		292	pci_read_config_byte(chip->pdev,
		293	O2_SD_LOCK_WP, &scratch_8);
		294	scratch_8 \|= 0x80;
		295	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
		296	return ret;
		297	}
		298
98	static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)	299	static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
99	{	300	{
100	struct sdhci_host *host = mmc_priv(mmc);	301	struct sdhci_host *host = mmc_priv(mmc);
@@ -109,7 +310,16 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) · 8 unmodified lines
109		310
110	if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))	311	if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
111	return -EINVAL;	312	return -EINVAL;
112		313	/*
		314	* Judge the tuning reason, whether caused by dll shift
		315	* If cause by dll shift, should call sdhci_o2_dll_recovery
		316	*/
		317	if (!sdhci_o2_wait_dll_detect_lock(host))
		318	if (!sdhci_o2_dll_recovery(host)) {
		319	pr_err("%s: o2 dll recovery failed\n",
		320	mmc_hostname(host->mmc));
		321	return -EINVAL;
		322	}
113	/*	323	/*
114	* o2 sdhci host didn't support 8bit emmc tuning	324	* o2 sdhci host didn't support 8bit emmc tuning
115	*/	325	*/
@@ -136,19 +346,6 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) · 20 unmodified lines
136	return 0;	346	return 0;
137	}	347	}
138		348
139	static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
140	{
141	u32 scratch_32;
142	pci_read_config_dword(chip->pdev,
143	O2_SD_PLL_SETTING, &scratch_32);
144
145	scratch_32 &= 0x0000FFFF;
146	scratch_32 \|= value;
147
148	pci_write_config_dword(chip->pdev,
149	O2_SD_PLL_SETTING, scratch_32);
150	}
151
152	static void o2_pci_led_enable(struct sdhci_pci_chip *chip)	349	static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
153	{	350	{
154	int ret;	351	int ret;
@@ -284,92 +481,13 @@ static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip, · 129 unmodified lines
284	host->irq = pci_irq_vector(chip->pdev, 0);	481	host->irq = pci_irq_vector(chip->pdev, 0);
285	}	482	}
286		483
287	static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
288	{
289	ktime_t timeout;
290	u32 scratch32;
291
292	/* Wait max 50 ms */
293	timeout = ktime_add_ms(ktime_get(), 50);
294	while (1) {
295	bool timedout = ktime_after(ktime_get(), timeout);
296
297	scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
298	if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
299	== (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
300	break;
301
302	if (timedout) {
303	pr_err("%s: Card Detect debounce never finished.\n",
304	mmc_hostname(host->mmc));
305	sdhci_dumpregs(host);
306	return;
307	}
308	udelay(10);
309	}
310	}
311
312	static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
313	{
314	ktime_t timeout;
315	u16 scratch;
316	u32 scratch32;
317
318	/* PLL software reset */
319	scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
320	scratch32 \|= O2_PLL_SOFT_RESET;
321	sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
322	udelay(1);
323	scratch32 &= ~(O2_PLL_SOFT_RESET);
324	sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
325
326	/* PLL force active */
327	scratch32 \|= O2_PLL_FORCE_ACTIVE;
328	sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
329
330	/* Wait max 20 ms */
331	timeout = ktime_add_ms(ktime_get(), 20);
332	while (1) {
333	bool timedout = ktime_after(ktime_get(), timeout);
334
335	scratch = sdhci_readw(host, O2_PLL_WDT_CONTROL1);
336	if (scratch & O2_PLL_LOCK_STATUS)
337	break;
338	if (timedout) {
339	pr_err("%s: Internal clock never stabilised.\n",
340	mmc_hostname(host->mmc));
341	sdhci_dumpregs(host);
342	goto out;
343	}
344	udelay(10);
345	}
346
347	/* Wait for card detect finish */
348	udelay(1);
349	sdhci_o2_wait_card_detect_stable(host);
350
351	out:
352	/* Cancel PLL force active */
353	scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
354	scratch32 &= ~O2_PLL_FORCE_ACTIVE;
355	sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
356	}
357
358	static int sdhci_o2_get_cd(struct mmc_host *mmc)
359	{
360	struct sdhci_host *host = mmc_priv(mmc);
361
362	sdhci_o2_enable_internal_clock(host);
363
364	return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
365	}
366
367	static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)	484	static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
368	{	485	{
369	/* Enable internal clock */	486	/* Enable internal clock */
370	clk \|= SDHCI_CLOCK_INT_EN;	487	clk \|= SDHCI_CLOCK_INT_EN;
371	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);	488	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
372		489
		490	sdhci_o2_enable_internal_clock(host);
373	if (sdhci_o2_get_cd(host->mmc)) {	491	if (sdhci_o2_get_cd(host->mmc)) {
374	clk \|= SDHCI_CLOCK_CARD_EN;	492	clk \|= SDHCI_CLOCK_CARD_EN;
375	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);	493	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
@@ -395,12 +513,14 @@ int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) · 19 unmodified lines
395	{	513	{
396	struct sdhci_pci_chip *chip;	514	struct sdhci_pci_chip *chip;
397	struct sdhci_host *host;	515	struct sdhci_host *host;
		516	struct o2_host *o2_host = sdhci_pci_priv(slot);
398	u32 reg, caps;	517	u32 reg, caps;
399	int ret;	518	int ret;
400		519
401	chip = slot->chip;	520	chip = slot->chip;
402	host = slot->host;	521	host = slot->host;
403		522
		523	o2_host->dll_adjust_count = 0;
404	caps = sdhci_readl(host, SDHCI_CAPABILITIES);	524	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
405		525
406	/*	526	/*
@@ -687,4 +807,5 @@ const struct sdhci_pci_fixes sdhci_o2 = { · 280 unmodified lines
687	.resume = sdhci_pci_o2_resume,	807	.resume = sdhci_pci_o2_resume,
688	#endif	808	#endif
689	.ops = &sdhci_pci_o2_ops,	809	.ops = &sdhci_pci_o2_ops,
		810	.priv_size = sizeof(struct o2_host),
690	};	811	};

drivers/mmc/host/sdhci-pci.h+1−0

@@ -54,6 +54,7 @@ · 53 unmodified lines
54	#define PCI_DEVICE_ID_INTEL_EHL_SD 0x4b48	54	#define PCI_DEVICE_ID_INTEL_EHL_SD 0x4b48
55	#define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c4	55	#define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c4
56	#define PCI_DEVICE_ID_INTEL_CML_SD 0x02f5	56	#define PCI_DEVICE_ID_INTEL_CML_SD 0x02f5
		57	#define PCI_DEVICE_ID_INTEL_CMLH_SD 0x06f5
57		58
58	#define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000	59	#define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000
59	#define PCI_DEVICE_ID_VIA_95D0 0x95d0	60	#define PCI_DEVICE_ID_VIA_95D0 0x95d0

drivers/mmc/host/sdhci-pltfm.c+1−4

 				    size_t priv_size)
 {
 	struct sdhci_host *host;
-	struct resource *iomem;
 	void __iomem *ioaddr;
 	int irq, ret;
-	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	ioaddr = devm_platform_ioremap_resource(pdev, 0);
-	ioaddr = devm_ioremap_resource(&pdev->dev, iomem);
 	if (IS_ERR(ioaddr)) {
 		ret = PTR_ERR(ioaddr);
 		goto err;
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0) {
-		dev_err(&pdev->dev, "failed to get IRQ number\n");
 		ret = irq;
 		goto err;
 	}

drivers/mmc/host/sdhci-s3c.c+2−3

 	}
 	irq = platform_get_irq(pdev, 0);
-	if (irq < 0) {
+	if (irq < 0)
-		dev_err(dev, "no irq specified\n");
 		return irq;
-	}
 	host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
 	if (IS_ERR(host)) {
 	switch (pdata->max_width) {
 	case 8:
 		host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+		/* Fall through */
 	case 4:
 		host->mmc->caps |= MMC_CAP_4_BIT_DATA;
 		break;

drivers/mmc/host/sdhci.c+48−28

@@ -668,10 +668,10 @@ void sdhci_adma_write_desc(struct sdhci_host host, void *desc, · 667 unmodified lines
668	/* 32-bit and 64-bit descriptors have these members in same position */	668	/* 32-bit and 64-bit descriptors have these members in same position */
669	dma_desc->cmd = cpu_to_le16(cmd);	669	dma_desc->cmd = cpu_to_le16(cmd);
670	dma_desc->len = cpu_to_le16(len);	670	dma_desc->len = cpu_to_le16(len);
671	dma_desc->addr_lo = cpu_to_le32((u32)addr);	671	dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
672		672
673	if (host->flags & SDHCI_USE_64_BIT_DMA)	673	if (host->flags & SDHCI_USE_64_BIT_DMA)
674	dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);	674	dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
675		675
676	*desc += host->desc_sz;	676	*desc += host->desc_sz;
677	}	677	}
@@ -816,6 +816,13 @@ static void sdhci_adma_table_post(struct sdhci_host *host, · 138 unmodified lines
816	}	816	}
817	}	817	}
818		818
		819	static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
		820	{
		821	sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
		822	if (host->flags & SDHCI_USE_64_BIT_DMA)
		823	sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
		824	}
		825
819	static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)	826	static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
820	{	827	{
821	if (host->bounce_buffer)	828	if (host->bounce_buffer)
@@ -826,13 +833,10 @@ static dma_addr_t sdhci_sdma_address(struct sdhci_host *host) · 4 unmodified lines
826		833
827	static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)	834	static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
828	{	835	{
829	if (host->v4_mode) {	836	if (host->v4_mode)
830	sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS);	837	sdhci_set_adma_addr(host, addr);
831	if (host->flags & SDHCI_USE_64_BIT_DMA)	838	else
832	sdhci_writel(host, (u64)addr >> 32, SDHCI_ADMA_ADDRESS_HI);
833	} else {
834	sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);	839	sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
835	}
836	}	840	}
837		841
838	static unsigned int sdhci_target_timeout(struct sdhci_host *host,	842	static unsigned int sdhci_target_timeout(struct sdhci_host *host,
@@ -1095,12 +1099,7 @@ static void sdhci_prepare_data(struct sdhci_host host, struct mmc_command cmd) · 256 unmodified lines
1095	host->flags &= ~SDHCI_REQ_USE_DMA;	1099	host->flags &= ~SDHCI_REQ_USE_DMA;
1096	} else if (host->flags & SDHCI_USE_ADMA) {	1100	} else if (host->flags & SDHCI_USE_ADMA) {
1097	sdhci_adma_table_pre(host, data, sg_cnt);	1101	sdhci_adma_table_pre(host, data, sg_cnt);
1098		1102	sdhci_set_adma_addr(host, host->adma_addr);
1099	sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
1100	if (host->flags & SDHCI_USE_64_BIT_DMA)
1101	sdhci_writel(host,
1102	(u64)host->adma_addr >> 32,
1103	SDHCI_ADMA_ADDRESS_HI);
1104	} else {	1103	} else {
1105	WARN_ON(sg_cnt != 1);	1104	WARN_ON(sg_cnt != 1);
1106	sdhci_set_sdma_addr(host, sdhci_sdma_address(host));	1105	sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
@@ -1636,8 +1635,8 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) · 529 unmodified lines
1636	clk \|= SDHCI_CLOCK_INT_EN;	1635	clk \|= SDHCI_CLOCK_INT_EN;
1637	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);	1636	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1638		1637
1639	/* Wait max 20 ms */	1638	/* Wait max 150 ms */
1640	timeout = ktime_add_ms(ktime_get(), 20);	1639	timeout = ktime_add_ms(ktime_get(), 150);
1641	while (1) {	1640	while (1) {
1642	bool timedout = ktime_after(ktime_get(), timeout);	1641	bool timedout = ktime_after(ktime_get(), timeout);
1643		1642
@@ -1653,6 +1652,29 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) · 9 unmodified lines
1653	udelay(10);	1652	udelay(10);
1654	}	1653	}
1655		1654
		1655	if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
		1656	clk \|= SDHCI_CLOCK_PLL_EN;
		1657	clk &= ~SDHCI_CLOCK_INT_STABLE;
		1658	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
		1659
		1660	/* Wait max 150 ms */
		1661	timeout = ktime_add_ms(ktime_get(), 150);
		1662	while (1) {
		1663	bool timedout = ktime_after(ktime_get(), timeout);
		1664
		1665	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
		1666	if (clk & SDHCI_CLOCK_INT_STABLE)
		1667	break;
		1668	if (timedout) {
		1669	pr_err("%s: PLL clock never stabilised.\n",
		1670	mmc_hostname(host->mmc));
		1671	sdhci_dumpregs(host);
		1672	return;
		1673	}
		1674	udelay(10);
		1675	}
		1676	}
		1677
1656	clk \|= SDHCI_CLOCK_CARD_EN;	1678	clk \|= SDHCI_CLOCK_CARD_EN;
1657	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);	1679	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1658	}	1680	}
@@ -1849,7 +1871,9 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) · 190 unmodified lines
1849	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104;	1871	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104;
1850	else if (timing == MMC_TIMING_UHS_SDR12)	1872	else if (timing == MMC_TIMING_UHS_SDR12)
1851	ctrl_2 \|= SDHCI_CTRL_UHS_SDR12;	1873	ctrl_2 \|= SDHCI_CTRL_UHS_SDR12;
1852	else if (timing == MMC_TIMING_UHS_SDR25)	1874	else if (timing == MMC_TIMING_SD_HS \|\|
		1875	timing == MMC_TIMING_MMC_HS \|\|
		1876	timing == MMC_TIMING_UHS_SDR25)
1853	ctrl_2 \|= SDHCI_CTRL_UHS_SDR25;	1877	ctrl_2 \|= SDHCI_CTRL_UHS_SDR25;
1854	else if (timing == MMC_TIMING_UHS_SDR50)	1878	else if (timing == MMC_TIMING_UHS_SDR50)
1855	ctrl_2 \|= SDHCI_CTRL_UHS_SDR50;	1879	ctrl_2 \|= SDHCI_CTRL_UHS_SDR50;
@@ -2120,11 +2144,6 @@ void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) · 264 unmodified lines
2120	pm_runtime_get_noresume(host->mmc->parent);	2144	pm_runtime_get_noresume(host->mmc->parent);
2121		2145
2122	spin_lock_irqsave(&host->lock, flags);	2146	spin_lock_irqsave(&host->lock, flags);
2123	if (enable)
2124	host->flags \|= SDHCI_SDIO_IRQ_ENABLED;
2125	else
2126	host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
2127
2128	sdhci_enable_sdio_irq_nolock(host, enable);	2147	sdhci_enable_sdio_irq_nolock(host, enable);
2129	spin_unlock_irqrestore(&host->lock, flags);	2148	spin_unlock_irqrestore(&host->lock, flags);
2130		2149
@@ -2139,8 +2158,7 @@ static void sdhci_ack_sdio_irq(struct mmc_host *mmc) · 8 unmodified lines
2139	unsigned long flags;	2158	unsigned long flags;
2140		2159
2141	spin_lock_irqsave(&host->lock, flags);	2160	spin_lock_irqsave(&host->lock, flags);
2142	if (host->flags & SDHCI_SDIO_IRQ_ENABLED)	2161	sdhci_enable_sdio_irq_nolock(host, true);
2143	sdhci_enable_sdio_irq_nolock(host, true);
2144	spin_unlock_irqrestore(&host->lock, flags);	2162	spin_unlock_irqrestore(&host->lock, flags);
2145	}	2163	}
2146		2164
@@ -2305,7 +2323,7 @@ void sdhci_reset_tuning(struct sdhci_host *host) · 158 unmodified lines
2305	}	2323	}
2306	EXPORT_SYMBOL_GPL(sdhci_reset_tuning);	2324	EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2307		2325
2308	static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)	2326	void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2309	{	2327	{
2310	sdhci_reset_tuning(host);	2328	sdhci_reset_tuning(host);
2311		2329
@@ -2316,6 +2334,7 @@ static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) · 4 unmodified lines
2316		2334
2317	mmc_abort_tuning(host->mmc, opcode);	2335	mmc_abort_tuning(host->mmc, opcode);
2318	}	2336	}
		2337	EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2319		2338
2320	/*	2339	/*
2321	* We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI	2340	* We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
@@ -3024,7 +3043,7 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id) · 702 unmodified lines
3024		3043
3025	spin_lock(&host->lock);	3044	spin_lock(&host->lock);
3026		3045
3027	if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {	3046	if (host->runtime_suspended) {
3028	spin_unlock(&host->lock);	3047	spin_unlock(&host->lock);
3029	return IRQ_NONE;	3048	return IRQ_NONE;
3030	}	3049	}
@@ -3358,7 +3377,7 @@ int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset) · 327 unmodified lines
3358	host->runtime_suspended = false;	3377	host->runtime_suspended = false;
3359		3378
3360	/* Enable SDIO IRQ */	3379	/* Enable SDIO IRQ */
3361	if (host->flags & SDHCI_SDIO_IRQ_ENABLED)	3380	if (sdio_irq_claimed(mmc))
3362	sdhci_enable_sdio_irq_nolock(host, true);	3381	sdhci_enable_sdio_irq_nolock(host, true);
3363		3382
3364	/* Enable Card Detection */	3383	/* Enable Card Detection */
@@ -3565,7 +3584,8 @@ static int sdhci_set_dma_mask(struct sdhci_host *host) · 200 unmodified lines
3565	return ret;	3584	return ret;
3566	}	3585	}
3567		3586
3568	void __sdhci_read_caps(struct sdhci_host host, u16 ver, u32 caps, u32 caps1)	3587	void __sdhci_read_caps(struct sdhci_host host, const u16 ver,
		3588	const u32 caps, const u32 caps1)
3569	{	3589	{
3570	u16 v;	3590	u16 v;
3571	u64 dt_caps_mask = 0;	3591	u64 dt_caps_mask = 0;

drivers/mmc/host/sdhci.h+4−8

 #define  SDHCI_DIV_HI_MASK	0x300
 #define  SDHCI_PROG_CLOCK_MODE	0x0020
 #define  SDHCI_CLOCK_CARD_EN	0x0004
+#define  SDHCI_CLOCK_PLL_EN	0x0008
 #define  SDHCI_CLOCK_INT_STABLE	0x0002
 #define  SDHCI_CLOCK_INT_EN	0x0001
 #define SDHCI_AUTO_CMD12	(1<<6)	/* Auto CMD12 support */
 #define SDHCI_AUTO_CMD23	(1<<7)	/* Auto CMD23 support */
 #define SDHCI_PV_ENABLED	(1<<8)	/* Preset value enabled */
-#define SDHCI_SDIO_IRQ_ENABLED	(1<<9)	/* SDIO irq enabled */
 #define SDHCI_USE_64_BIT_DMA	(1<<12)	/* Use 64-bit DMA */
 #define SDHCI_HS400_TUNING	(1<<13)	/* Tuning for HS400 */
 #define SDHCI_SIGNALING_330	(1<<14)	/* Host is capable of 3.3V signaling */
 }
 void sdhci_card_detect(struct sdhci_host *host);
-void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps,
+void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
-		       u32 *caps1);
+		       const u32 *caps, const u32 *caps1);
 int sdhci_setup_host(struct sdhci_host *host);
 void sdhci_cleanup_host(struct sdhci_host *host);
 int __sdhci_add_host(struct sdhci_host *host);
 	__sdhci_read_caps(host, NULL, NULL, NULL);
 }
-static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
-{
-	return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
-}
 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
 		   unsigned int *actual_clock);
 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
 void sdhci_end_tuning(struct sdhci_host *host);
 void sdhci_reset_tuning(struct sdhci_host *host);
 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);
+void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode);
 #endif /* __SDHCI_HW_H */

drivers/mmc/host/sdhci_f_sdh30.c+1−3

 	u32 reg = 0;
 	irq = platform_get_irq(pdev, 0);
-	if (irq < 0) {
+	if (irq < 0)
-		dev_err(dev, "%s: no irq specified\n", __func__);
 		return irq;
-	}
 	host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv));
 	if (IS_ERR(host))

drivers/mmc/host/uniphier-sd.c+1−3

 	int irq, ret;
 	irq = platform_get_irq(pdev, 0);
-	if (irq < 0) {
+	if (irq < 0)
-		dev_err(dev, "failed to get IRQ number");
 		return irq;
-	}
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)

include/linux/mmc/host.h+10−0

 	int	(*get_cd)(struct mmc_host *host);
 	void	(*enable_sdio_irq)(struct mmc_host *host, int enable);
+	/* Mandatory callback when using MMC_CAP2_SDIO_IRQ_NOTHREAD. */
 	void	(*ack_sdio_irq)(struct mmc_host *host);
 	/* optional callback for HC quirks */
 void mmc_cqe_request_done(struct mmc_host *host, struct mmc_request *mrq);
+/*
+ * May be called from host driver's system/runtime suspend/resume callbacks,
+ * to know if SDIO IRQs has been claimed.
+ */
+static inline bool sdio_irq_claimed(struct mmc_host *host)
+{
+	return host->sdio_irqs > 0;
+}
 static inline void mmc_signal_sdio_irq(struct mmc_host *host)
 {
 	host->ops->enable_sdio_irq(host, 0);

include/linux/pci_ids.h+2−0

@@ -2405,6 +2405,8 @@ · 2404 unmodified lines
2405	#define PCI_DEVICE_ID_RDC_R6061 0x6061	2405	#define PCI_DEVICE_ID_RDC_R6061 0x6061
2406	#define PCI_DEVICE_ID_RDC_D1010 0x1010	2406	#define PCI_DEVICE_ID_RDC_D1010 0x1010
2407		2407
		2408	#define PCI_VENDOR_ID_GLI 0x17a0
		2409
2408	#define PCI_VENDOR_ID_LENOVO 0x17aa	2410	#define PCI_VENDOR_ID_LENOVO 0x17aa
2409		2411
2410	#define PCI_VENDOR_ID_QCOM 0x17cb	2412	#define PCI_VENDOR_ID_QCOM 0x17cb

Merge tag 'mmc-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

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