History

Merge branch kvm-arm64/vgic-invlpir into kvmarm-master/next

* kvm-arm64/vgic-invlpir: : . : Implement MMIO-based LPI invalidation for vGICv3. : . KVM: arm64: vgic-v3: Advertise GICR_CTLR.{IR, CES} as a new GICD_IIDR revision KVM: arm64: vgic-v3: Implement MMIO-based LPI invalidation KVM: arm64: vgic-v3: Expose GICR_CTLR.RWP when disabling LPIs irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES}

Marc Zyngier committed 4 years ago

Commit ec2cff62 parents 3b8e21e 49a1a2c7 files · +195 −39Browse files

Showing the changes to include (2 of 7 files). Show all

Unified · Split

2 files
  1. include/kvm/arm_vgic.h +6 −2
  2. include/linux/irqchip/arm-gic-v3.h +2 −0
include/kvm/arm_vgic.h+6−2
@@ -231,6 +231,9 @@ struct vgic_dist { · 230 unmodified lines
231 231
232 /* Implementation revision as reported in the GICD_IIDR */232 /* Implementation revision as reported in the GICD_IIDR */
233 u32 implementation_rev;233 u32 implementation_rev;
234#define KVM_VGIC_IMP_REV_2 2 /* GICv2 restorable groups */
235#define KVM_VGIC_IMP_REV_3 3 /* GICv3 GICR_CTLR.{IW,CES,RWP} */
236#define KVM_VGIC_IMP_REV_LATEST KVM_VGIC_IMP_REV_3
234 237
235 /* Userspace can write to GICv2 IGROUPR */238 /* Userspace can write to GICv2 IGROUPR */
236 bool v2_groups_user_writable;239 bool v2_groups_user_writable;
@@ -344,11 +347,12 @@ struct vgic_cpu { · 107 unmodified lines
344 struct vgic_io_device rd_iodev;347 struct vgic_io_device rd_iodev;
345 struct vgic_redist_region *rdreg;348 struct vgic_redist_region *rdreg;
346 u32 rdreg_index;349 u32 rdreg_index;
350 atomic_t syncr_busy;
347 351
348 /* Contains the attributes and gpa of the LPI pending tables. */352 /* Contains the attributes and gpa of the LPI pending tables. */
349 u64 pendbaser;353 u64 pendbaser;
350 354 /* GICR_CTLR.{ENABLE_LPIS,RWP} */
351 bool lpis_enabled;355 atomic_t ctlr;
352 356
353 /* Cache guest priority bits */357 /* Cache guest priority bits */
354 u32 num_pri_bits;358 u32 num_pri_bits;
include/linux/irqchip/arm-gic-v3.h+2−0
@@ -127,6 +127,8 @@ · 126 unmodified lines
127#define GICR_PIDR2 GICD_PIDR2127#define GICR_PIDR2 GICD_PIDR2
128 128
129#define GICR_CTLR_ENABLE_LPIS (1UL << 0)129#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
130#define GICR_CTLR_CES (1UL << 1)
131#define GICR_CTLR_IR (1UL << 2)
130#define GICR_CTLR_RWP (1UL << 3)132#define GICR_CTLR_RWP (1UL << 3)
131 133
132#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)134#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)