* kvm-arm64/vgic-invlpir: : . : Implement MMIO-based LPI invalidation for vGICv3. : . KVM: arm64: vgic-v3: Advertise GICR_CTLR.{IR, CES} as a new GICD_IIDR revision KVM: arm64: vgic-v3: Implement MMIO-based LPI invalidation KVM: arm64: vgic-v3: Expose GICR_CTLR.RWP when disabling LPIs irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES}
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| @@ -231,6 +231,9 @@ struct vgic_dist { · 230 unmodified lines | ||
| 231 | 231 | |
| 232 | 232 | /* Implementation revision as reported in the GICD_IIDR */ |
| 233 | 233 | u32 implementation_rev; |
| 234 | +#define KVM_VGIC_IMP_REV_2 2 /* GICv2 restorable groups */ | |
| 235 | +#define KVM_VGIC_IMP_REV_3 3 /* GICv3 GICR_CTLR.{IW,CES,RWP} */ | |
| 236 | +#define KVM_VGIC_IMP_REV_LATEST KVM_VGIC_IMP_REV_3 | |
| 234 | 237 | |
| 235 | 238 | /* Userspace can write to GICv2 IGROUPR */ |
| 236 | 239 | bool v2_groups_user_writable; |
| @@ -344,11 +347,12 @@ struct vgic_cpu { · 107 unmodified lines | ||
| 344 | 347 | struct vgic_io_device rd_iodev; |
| 345 | 348 | struct vgic_redist_region *rdreg; |
| 346 | 349 | u32 rdreg_index; |
| 350 | + atomic_t syncr_busy; | |
| 347 | 351 | |
| 348 | 352 | /* Contains the attributes and gpa of the LPI pending tables. */ |
| 349 | 353 | u64 pendbaser; |
| 350 | − | |
| 351 | − bool lpis_enabled; | |
| 354 | + /* GICR_CTLR.{ENABLE_LPIS,RWP} */ | |
| 355 | + atomic_t ctlr; | |
| 352 | 356 | |
| 353 | 357 | /* Cache guest priority bits */ |
| 354 | 358 | u32 num_pri_bits; |
| @@ -127,6 +127,8 @@ · 126 unmodified lines | ||
| 127 | 127 | #define GICR_PIDR2 GICD_PIDR2 |
| 128 | 128 | |
| 129 | 129 | #define GICR_CTLR_ENABLE_LPIS (1UL << 0) |
| 130 | +#define GICR_CTLR_CES (1UL << 1) | |
| 131 | +#define GICR_CTLR_IR (1UL << 2) | |
| 130 | 132 | #define GICR_CTLR_RWP (1UL << 3) |
| 131 | 133 | |
| 132 | 134 | #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) |