Pull ARM SoC driver updates from Olof Johansson: "Various driver updates for platforms: - A larger set of work on Tegra 2/3 around memory controller and regulator features, some fuse cleanups, etc.. - MMP platform drivers, in particular for USB PHY, and other smaller additions. - Samsung Exynos 5422 driver for DMC (dynamic memory configuration), and ASV (adaptive voltage), allowing the platform to run at more optimal operating points. - Misc refactorings and support for RZ/G2N and R8A774B1 from Renesas - Clock/reset control driver for TI/OMAP - Meson-A1 reset controller support - Qualcomm sdm845 and sda845 SoC IDs for socinfo" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (150 commits) firmware: arm_scmi: Fix doorbell ring logic for !CONFIG_64BIT soc: fsl: add RCPM driver dt-bindings: fsl: rcpm: Add 'little-endian' and update Chassis definition memory: tegra: Consolidate registers definition into common header memory: tegra: Ensure timing control debug features are disabled memory: tegra: Introduce Tegra30 EMC driver memory: tegra: Do not handle error from wait_for_completion_timeout() memory: tegra: Increase handshake timeout on Tegra20 memory: tegra: Print a brief info message about EMC timings memory: tegra: Pre-configure debug register on Tegra20 memory: tegra: Include io.h instead of iopoll.h memory: tegra: Adapt for Tegra20 clock driver changes memory: tegra: Don't set EMC rate to maximum on probe for Tegra20 memory: tegra: Add gr2d and gr3d to DRM IOMMU group memory: tegra: Set DMA mask based on supported address bits soc: at91: Add Atmel SFR SN (Serial Number) support memory: atmel-ebi: switch to SPDX license identifiers memory: atmel-ebi: move NUM_CS definition inside EBI driver soc: mediatek: Refactor bus protection control soc: mediatek: Refactor sram control ...
Showing the changes to include/linux (10 of 133 files). Show all
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| @@ -16,11 +16,14 @@ enum { · 15 unmodified lines | ||
| 16 | 16 | |
| 17 | 17 | struct meson_sm_firmware; |
| 18 | 18 | |
| 19 | −int meson_sm_call(unsigned int cmd_index, u32 *ret, u32 arg0, u32 arg1, | |
| 20 | − u32 arg2, u32 arg3, u32 arg4); | |
| 21 | −int meson_sm_call_write(void *buffer, unsigned int b_size, unsigned int cmd_index, | |
| 22 | − u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4); | |
| 23 | −int meson_sm_call_read(void *buffer, unsigned int bsize, unsigned int cmd_index, | |
| 24 | − u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4); | |
| 19 | +int meson_sm_call(struct meson_sm_firmware *fw, unsigned int cmd_index, | |
| 20 | + u32 *ret, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4); | |
| 21 | +int meson_sm_call_write(struct meson_sm_firmware *fw, void *buffer, | |
| 22 | + unsigned int b_size, unsigned int cmd_index, u32 arg0, | |
| 23 | + u32 arg1, u32 arg2, u32 arg3, u32 arg4); | |
| 24 | +int meson_sm_call_read(struct meson_sm_firmware *fw, void *buffer, | |
| 25 | + unsigned int bsize, unsigned int cmd_index, u32 arg0, | |
| 26 | + u32 arg1, u32 arg2, u32 arg3, u32 arg4); | |
| 27 | +struct meson_sm_firmware *meson_sm_get(struct device_node *firmware_node); | |
| 25 | 28 | |
| 26 | 29 | #endif /* _MESON_SM_FW_H_ */ |
| @@ -2,7 +2,7 @@ · 1 unmodified line | ||
| 2 | 2 | /* |
| 3 | 3 | * Xilinx Zynq MPSoC Firmware layer |
| 4 | 4 | * |
| 5 | − * Copyright (C) 2014-2018 Xilinx | |
| 5 | + * Copyright (C) 2014-2019 Xilinx | |
| 6 | 6 | * |
| 7 | 7 | * Michal Simek <michal.simek@xilinx.com> |
| 8 | 8 | * Davorin Mista <davorin.mista@aggios.com> |
| @@ -46,6 +46,7 @@ · 37 unmodified lines | ||
| 46 | 46 | #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U |
| 47 | 47 | #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U |
| 48 | 48 | #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U |
| 49 | +#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U | |
| 49 | 50 | |
| 50 | 51 | /* |
| 51 | 52 | * Firmware FPGA Manager flags |
| @@ -108,10 +108,10 @@ void logic_outsl(unsigned long addr, const void *buffer, unsigned int count); · 107 unmodified lines | ||
| 108 | 108 | * area by redefining the macro below. |
| 109 | 109 | */ |
| 110 | 110 | #define PIO_INDIRECT_SIZE 0x4000 |
| 111 | −#define MMIO_UPPER_LIMIT (IO_SPACE_LIMIT - PIO_INDIRECT_SIZE) | |
| 112 | 111 | #else |
| 113 | −#define MMIO_UPPER_LIMIT IO_SPACE_LIMIT | |
| 112 | +#define PIO_INDIRECT_SIZE 0 | |
| 114 | 113 | #endif /* CONFIG_INDIRECT_PIO */ |
| 114 | +#define MMIO_UPPER_LIMIT (IO_SPACE_LIMIT - PIO_INDIRECT_SIZE) | |
| 115 | 115 | |
| 116 | 116 | struct logic_pio_hwaddr *find_io_range_by_fwnode(struct fwnode_handle *fwnode); |
| 117 | 117 | unsigned long logic_pio_trans_hwaddr(struct fwnode_handle *fwnode, |
| @@ -106,7 +106,6 @@ · 105 unmodified lines | ||
| 106 | 106 | #define AT91_MATRIX_DDR_IOSR BIT(18) |
| 107 | 107 | #define AT91_MATRIX_NFD0_SELECT BIT(24) |
| 108 | 108 | #define AT91_MATRIX_DDR_MP_EN BIT(25) |
| 109 | −#define AT91_MATRIX_EBI_NUM_CS 8 | |
| 110 | 109 | |
| 111 | 110 | #define AT91_MATRIX_USBPUCR_PUON BIT(30) |
| 112 | 111 | |
| @@ -0,0 +1,21 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | +/* | |
| 3 | + * TI PRM (Power & Reset Manager) platform data | |
| 4 | + * | |
| 5 | + * Copyright (C) 2019 Texas Instruments, Inc. | |
| 6 | + * | |
| 7 | + * Tero Kristo <t-kristo@ti.com> | |
| 8 | + */ | |
| 9 | + | |
| 10 | +#ifndef _LINUX_PLATFORM_DATA_TI_PRM_H | |
| 11 | +#define _LINUX_PLATFORM_DATA_TI_PRM_H | |
| 12 | + | |
| 13 | +struct clockdomain; | |
| 14 | + | |
| 15 | +struct ti_prm_platform_data { | |
| 16 | + void (*clkdm_deny_idle)(struct clockdomain *clkdm); | |
| 17 | + void (*clkdm_allow_idle)(struct clockdomain *clkdm); | |
| 18 | + struct clockdomain * (*clkdm_lookup)(const char *name); | |
| 19 | +}; | |
| 20 | + | |
| 21 | +#endif /* _LINUX_PLATFORM_DATA_TI_PRM_H */ | |
| @@ -63,6 +63,11 @@ struct wakeup_source { · 62 unmodified lines | ||
| 63 | 63 | bool autosleep_enabled:1; |
| 64 | 64 | }; |
| 65 | 65 | |
| 66 | +#define for_each_wakeup_source(ws) \ | |
| 67 | + for ((ws) = wakeup_sources_walk_start(); \ | |
| 68 | + (ws); \ | |
| 69 | + (ws) = wakeup_sources_walk_next((ws))) | |
| 70 | + | |
| 66 | 71 | #ifdef CONFIG_PM_SLEEP |
| 67 | 72 | |
| 68 | 73 | /* |
| @@ -92,6 +97,10 @@ extern void wakeup_source_remove(struct wakeup_source *ws); · 23 unmodified lines | ||
| 92 | 97 | extern struct wakeup_source *wakeup_source_register(struct device *dev, |
| 93 | 98 | const char *name); |
| 94 | 99 | extern void wakeup_source_unregister(struct wakeup_source *ws); |
| 100 | +extern int wakeup_sources_read_lock(void); | |
| 101 | +extern void wakeup_sources_read_unlock(int idx); | |
| 102 | +extern struct wakeup_source *wakeup_sources_walk_start(void); | |
| 103 | +extern struct wakeup_source *wakeup_sources_walk_next(struct wakeup_source *ws); | |
| 95 | 104 | extern int device_wakeup_enable(struct device *dev); |
| 96 | 105 | extern int device_wakeup_disable(struct device *dev); |
| 97 | 106 | extern void device_set_wakeup_capable(struct device *dev, bool capable); |
| @@ -62,7 +62,8 @@ struct reset_control_lookup { · 61 unmodified lines | ||
| 62 | 62 | * @of_node: corresponding device tree node as phandle target |
| 63 | 63 | * @of_reset_n_cells: number of cells in reset line specifiers |
| 64 | 64 | * @of_xlate: translation function to translate from specifier as found in the |
| 65 | − * device tree to id as given to the reset control ops | |
| 65 | + * device tree to id as given to the reset control ops, defaults | |
| 66 | + * to :c:func:`of_reset_simple_xlate`. | |
| 66 | 67 | * @nr_resets: number of reset controls in this reset controller device |
| 67 | 68 | */ |
| 68 | 69 | struct reset_controller_dev { |
| @@ -203,12 +203,34 @@ static inline struct reset_control *reset_control_get_shared( · 202 unmodified lines | ||
| 203 | 203 | return __reset_control_get(dev, id, 0, true, false, false); |
| 204 | 204 | } |
| 205 | 205 | |
| 206 | +/** | |
| 207 | + * reset_control_get_optional_exclusive - optional reset_control_get_exclusive() | |
| 208 | + * @dev: device to be reset by the controller | |
| 209 | + * @id: reset line name | |
| 210 | + * | |
| 211 | + * Optional variant of reset_control_get_exclusive(). If the requested reset | |
| 212 | + * is not specified in the device tree, this function returns NULL instead of | |
| 213 | + * an error. | |
| 214 | + * | |
| 215 | + * See reset_control_get_exclusive() for more information. | |
| 216 | + */ | |
| 206 | 217 | static inline struct reset_control *reset_control_get_optional_exclusive( |
| 207 | 218 | struct device *dev, const char *id) |
| 208 | 219 | { |
| 209 | 220 | return __reset_control_get(dev, id, 0, false, true, true); |
| 210 | 221 | } |
| 211 | 222 | |
| 223 | +/** | |
| 224 | + * reset_control_get_optional_shared - optional reset_control_get_shared() | |
| 225 | + * @dev: device to be reset by the controller | |
| 226 | + * @id: reset line name | |
| 227 | + * | |
| 228 | + * Optional variant of reset_control_get_shared(). If the requested reset | |
| 229 | + * is not specified in the device tree, this function returns NULL instead of | |
| 230 | + * an error. | |
| 231 | + * | |
| 232 | + * See reset_control_get_shared() for more information. | |
| 233 | + */ | |
| 212 | 234 | static inline struct reset_control *reset_control_get_optional_shared( |
| 213 | 235 | struct device *dev, const char *id) |
| 214 | 236 | { |
| @@ -354,12 +376,36 @@ static inline struct reset_control *devm_reset_control_get_shared( · 139 unmodified lines | ||
| 354 | 376 | return __devm_reset_control_get(dev, id, 0, true, false, false); |
| 355 | 377 | } |
| 356 | 378 | |
| 379 | +/** | |
| 380 | + * devm_reset_control_get_optional_exclusive - resource managed | |
| 381 | + * reset_control_get_optional_exclusive() | |
| 382 | + * @dev: device to be reset by the controller | |
| 383 | + * @id: reset line name | |
| 384 | + * | |
| 385 | + * Managed reset_control_get_optional_exclusive(). For reset controllers | |
| 386 | + * returned from this function, reset_control_put() is called automatically on | |
| 387 | + * driver detach. | |
| 388 | + * | |
| 389 | + * See reset_control_get_optional_exclusive() for more information. | |
| 390 | + */ | |
| 357 | 391 | static inline struct reset_control *devm_reset_control_get_optional_exclusive( |
| 358 | 392 | struct device *dev, const char *id) |
| 359 | 393 | { |
| 360 | 394 | return __devm_reset_control_get(dev, id, 0, false, true, true); |
| 361 | 395 | } |
| 362 | 396 | |
| 397 | +/** | |
| 398 | + * devm_reset_control_get_optional_shared - resource managed | |
| 399 | + * reset_control_get_optional_shared() | |
| 400 | + * @dev: device to be reset by the controller | |
| 401 | + * @id: reset line name | |
| 402 | + * | |
| 403 | + * Managed reset_control_get_optional_shared(). For reset controllers returned | |
| 404 | + * from this function, reset_control_put() is called automatically on driver | |
| 405 | + * detach. | |
| 406 | + * | |
| 407 | + * See reset_control_get_optional_shared() for more information. | |
| 408 | + */ | |
| 363 | 409 | static inline struct reset_control *devm_reset_control_get_optional_shared( |
| 364 | 410 | struct device *dev, const char *id) |
| 365 | 411 | { |
| @@ -2,7 +2,9 @@ · 1 unmodified line | ||
| 2 | 2 | #ifndef __ASM_MACH_CPUTYPE_H |
| 3 | 3 | #define __ASM_MACH_CPUTYPE_H |
| 4 | 4 | |
| 5 | +#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) | |
| 5 | 6 | #include <asm/cputype.h> |
| 7 | +#endif | |
| 6 | 8 | |
| 7 | 9 | /* |
| 8 | 10 | * CPU Stepping CPU_ID CHIP_ID |
| @@ -38,33 +38,27 @@ struct llcc_slice_desc { · 37 unmodified lines | ||
| 38 | 38 | }; |
| 39 | 39 | |
| 40 | 40 | /** |
| 41 | − * llcc_slice_config - Data associated with the llcc slice | |
| 42 | − * @usecase_id: usecase id for which the llcc slice is used | |
| 43 | − * @slice_id: llcc slice id assigned to each slice | |
| 44 | − * @max_cap: maximum capacity of the llcc slice | |
| 45 | − * @priority: priority of the llcc slice | |
| 46 | − * @fixed_size: whether the llcc slice can grow beyond its size | |
| 47 | − * @bonus_ways: bonus ways associated with llcc slice | |
| 48 | − * @res_ways: reserved ways associated with llcc slice | |
| 49 | − * @cache_mode: mode of the llcc slice | |
| 50 | − * @probe_target_ways: Probe only reserved and bonus ways on a cache miss | |
| 51 | − * @dis_cap_alloc: Disable capacity based allocation | |
| 52 | − * @retain_on_pc: Retain through power collapse | |
| 53 | − * @activate_on_init: activate the slice on init | |
| 41 | + * llcc_edac_reg_data - llcc edac registers data for each error type | |
| 42 | + * @name: Name of the error | |
| 43 | + * @synd_reg: Syndrome register address | |
| 44 | + * @count_status_reg: Status register address to read the error count | |
| 45 | + * @ways_status_reg: Status register address to read the error ways | |
| 46 | + * @reg_cnt: Number of registers | |
| 47 | + * @count_mask: Mask value to get the error count | |
| 48 | + * @ways_mask: Mask value to get the error ways | |
| 49 | + * @count_shift: Shift value to get the error count | |
| 50 | + * @ways_shift: Shift value to get the error ways | |
| 54 | 51 | */ |
| 55 | −struct llcc_slice_config { | |
| 56 | − u32 usecase_id; | |
| 57 | − u32 slice_id; | |
| 58 | − u32 max_cap; | |
| 59 | − u32 priority; | |
| 60 | − bool fixed_size; | |
| 61 | − u32 bonus_ways; | |
| 62 | − u32 res_ways; | |
| 63 | − u32 cache_mode; | |
| 64 | − u32 probe_target_ways; | |
| 65 | − bool dis_cap_alloc; | |
| 66 | − bool retain_on_pc; | |
| 67 | − bool activate_on_init; | |
| 52 | +struct llcc_edac_reg_data { | |
| 53 | + char *name; | |
| 54 | + u64 synd_reg; | |
| 55 | + u64 count_status_reg; | |
| 56 | + u64 ways_status_reg; | |
| 57 | + u32 reg_cnt; | |
| 58 | + u32 count_mask; | |
| 59 | + u32 ways_mask; | |
| 60 | + u8 count_shift; | |
| 61 | + u8 ways_shift; | |
| 68 | 62 | }; |
| 69 | 63 | |
| 70 | 64 | /** |
| @@ -93,30 +87,6 @@ struct llcc_drv_data { · 22 unmodified lines | ||
| 93 | 87 | int ecc_irq; |
| 94 | 88 | }; |
| 95 | 89 | |
| 96 | −/** | |
| 97 | − * llcc_edac_reg_data - llcc edac registers data for each error type | |
| 98 | − * @name: Name of the error | |
| 99 | − * @synd_reg: Syndrome register address | |
| 100 | − * @count_status_reg: Status register address to read the error count | |
| 101 | − * @ways_status_reg: Status register address to read the error ways | |
| 102 | − * @reg_cnt: Number of registers | |
| 103 | − * @count_mask: Mask value to get the error count | |
| 104 | − * @ways_mask: Mask value to get the error ways | |
| 105 | − * @count_shift: Shift value to get the error count | |
| 106 | − * @ways_shift: Shift value to get the error ways | |
| 107 | − */ | |
| 108 | −struct llcc_edac_reg_data { | |
| 109 | − char *name; | |
| 110 | − u64 synd_reg; | |
| 111 | − u64 count_status_reg; | |
| 112 | − u64 ways_status_reg; | |
| 113 | − u32 reg_cnt; | |
| 114 | − u32 count_mask; | |
| 115 | − u32 ways_mask; | |
| 116 | − u8 count_shift; | |
| 117 | − u8 ways_shift; | |
| 118 | −}; | |
| 119 | − | |
| 120 | 90 | #if IS_ENABLED(CONFIG_QCOM_LLCC) |
| 121 | 91 | /** |
| 122 | 92 | * llcc_slice_getd - get llcc slice descriptor |
| @@ -154,20 +124,6 @@ int llcc_slice_activate(struct llcc_slice_desc *desc); · 31 unmodified lines | ||
| 154 | 124 | */ |
| 155 | 125 | int llcc_slice_deactivate(struct llcc_slice_desc *desc); |
| 156 | 126 | |
| 157 | −/** | |
| 158 | − * qcom_llcc_probe - program the sct table | |
| 159 | − * @pdev: platform device pointer | |
| 160 | − * @table: soc sct table | |
| 161 | − * @sz: Size of the config table | |
| 162 | − */ | |
| 163 | −int qcom_llcc_probe(struct platform_device *pdev, | |
| 164 | − const struct llcc_slice_config *table, u32 sz); | |
| 165 | − | |
| 166 | −/** | |
| 167 | − * qcom_llcc_remove - remove the sct table | |
| 168 | − * @pdev: Platform device pointer | |
| 169 | − */ | |
| 170 | −int qcom_llcc_remove(struct platform_device *pdev); | |
| 171 | 127 | #else |
| 172 | 128 | static inline struct llcc_slice_desc *llcc_slice_getd(u32 uid) |
| 173 | 129 | { |
| @@ -197,16 +153,6 @@ static inline int llcc_slice_deactivate(struct llcc_slice_desc *desc) · 23 unmodified lines | ||
| 197 | 153 | { |
| 198 | 154 | return -EINVAL; |
| 199 | 155 | } |
| 200 | −static inline int qcom_llcc_probe(struct platform_device *pdev, | |
| 201 | − const struct llcc_slice_config *table, u32 sz) | |
| 202 | −{ | |
| 203 | − return -ENODEV; | |
| 204 | −} | |
| 205 | − | |
| 206 | −static inline int qcom_llcc_remove(struct platform_device *pdev) | |
| 207 | −{ | |
| 208 | − return -ENODEV; | |
| 209 | −} | |
| 210 | 156 | #endif |
| 211 | 157 | |
| 212 | 158 | #endif |