Support for the Marvell MV64x60 line of bridge chips that contained MPSC controllers has been removed and there are no other components that have that controller so remove its driver.
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| @@ -918,52 +918,6 @@ · 917 unmodified lines | ||
| 918 | 918 | |
| 919 | 919 | extern void mv64340_irq_init(unsigned int base); |
| 920 | 920 | |
| 921 | −/* MPSC Platform Device, Driver Data (Shared register regions) */ | |
| 922 | −#define MPSC_SHARED_NAME "mpsc_shared" | |
| 923 | − | |
| 924 | −#define MPSC_ROUTING_BASE_ORDER 0 | |
| 925 | −#define MPSC_SDMA_INTR_BASE_ORDER 1 | |
| 926 | − | |
| 927 | −#define MPSC_ROUTING_REG_BLOCK_SIZE 0x000c | |
| 928 | −#define MPSC_SDMA_INTR_REG_BLOCK_SIZE 0x0084 | |
| 929 | − | |
| 930 | −struct mpsc_shared_pdata { | |
| 931 | − u32 mrr_val; | |
| 932 | − u32 rcrr_val; | |
| 933 | − u32 tcrr_val; | |
| 934 | − u32 intr_cause_val; | |
| 935 | − u32 intr_mask_val; | |
| 936 | −}; | |
| 937 | − | |
| 938 | −/* MPSC Platform Device, Driver Data */ | |
| 939 | −#define MPSC_CTLR_NAME "mpsc" | |
| 940 | − | |
| 941 | −#define MPSC_BASE_ORDER 0 | |
| 942 | −#define MPSC_SDMA_BASE_ORDER 1 | |
| 943 | −#define MPSC_BRG_BASE_ORDER 2 | |
| 944 | − | |
| 945 | −#define MPSC_REG_BLOCK_SIZE 0x0038 | |
| 946 | −#define MPSC_SDMA_REG_BLOCK_SIZE 0x0c18 | |
| 947 | −#define MPSC_BRG_REG_BLOCK_SIZE 0x0008 | |
| 948 | − | |
| 949 | −struct mpsc_pdata { | |
| 950 | − u8 mirror_regs; | |
| 951 | − u8 cache_mgmt; | |
| 952 | − u8 max_idle; | |
| 953 | − int default_baud; | |
| 954 | − int default_bits; | |
| 955 | − int default_parity; | |
| 956 | − int default_flow; | |
| 957 | − u32 chr_1_val; | |
| 958 | − u32 chr_2_val; | |
| 959 | − u32 chr_10_val; | |
| 960 | − u32 mpcr_val; | |
| 961 | − u32 bcr_val; | |
| 962 | − u8 brg_can_tune; | |
| 963 | − u8 brg_clk_src; | |
| 964 | − u32 brg_clk_freq; | |
| 965 | −}; | |
| 966 | − | |
| 967 | 921 | /* Watchdog Platform Device, Driver Data */ |
| 968 | 922 | #define MV64x60_WDT_NAME "mv64x60_wdt" |
| 969 | 923 | |