Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull KVM fixes from Paolo Bonzini: "A somewhat bigger ARM update, and the usual smattering of x86 bug fixes" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: kvm: vmx: Fix entry number check for add_atomic_switch_msr() KVM: x86: Recompute PID.ON when clearing PID.SN KVM: nVMX: Restore a preemption timer consistency check x86/kvm/nVMX: read from MSR_IA32_VMX_PROCBASED_CTLS2 only when it is available KVM: arm64: Forbid kprobing of the VHE world-switch code KVM: arm64: Relax the restriction on using stage2 PUD huge mapping arm: KVM: Add missing kvm_stage2_has_pmd() helper KVM: arm/arm64: vgic: Always initialize the group of private IRQs arm/arm64: KVM: Don't panic on failure to properly reset system registers arm/arm64: KVM: Allow a VCPU to fully reset itself KVM: arm/arm64: Reset the VCPU without preemption and vcpu state loaded arm64: KVM: Don't generate UNDEF when LORegion feature is present KVM: arm/arm64: vgic: Make vgic_cpu->ap_list_lock a raw_spinlock KVM: arm/arm64: vgic: Make vgic_dist->lpi_list_lock a raw_spinlock KVM: arm/arm64: vgic: Make vgic_irq->irq_lock a raw_spinlock

Linus Torvalds committed 7 years ago

Commit ed0a0ec2 parents 64c0133 98ae70c26 files · +331 −193Browse files

Unified · Split

26 files

arch/arm/include/asm/kvm_host.h +10 −0
arch/arm/include/asm/stage2_pgtable.h +5 −0
arch/arm/kvm/coproc.c +2 −2
arch/arm/kvm/reset.c +24 −0
arch/arm64/include/asm/kvm_host.h +11 −0
arch/arm64/kvm/hyp/switch.c +5 −0
arch/arm64/kvm/hyp/sysreg-sr.c +5 −0
arch/arm64/kvm/reset.c +48 −2
arch/arm64/kvm/sys_regs.c +32 −18
arch/x86/kvm/vmx/nested.c +9 −3
arch/x86/kvm/vmx/vmx.c +13 −16
arch/x86/kvm/vmx/vmx.h +5 −5
arch/x86/kvm/x86.c +1 −1
include/kvm/arm_vgic.h +3 −3
virt/kvm/arm/arm.c +10 −0
virt/kvm/arm/mmu.c +6 −3
virt/kvm/arm/psci.c +16 −20
virt/kvm/arm/vgic/vgic-debug.c +2 −2
virt/kvm/arm/vgic/vgic-init.c +18 −12
virt/kvm/arm/vgic/vgic-its.c +11 −11
virt/kvm/arm/vgic/vgic-mmio-v2.c +7 −7
virt/kvm/arm/vgic/vgic-mmio-v3.c +6 −6
virt/kvm/arm/vgic/vgic-mmio.c +17 −17
virt/kvm/arm/vgic/vgic-v2.c +2 −2
virt/kvm/arm/vgic/vgic-v3.c +4 −4
virt/kvm/arm/vgic/vgic.c +59 −59

arch/arm/include/asm/kvm_host.h+10−0

@@ -48,6 +48,7 @@ · 47 unmodified lines
48	48	#define KVM_REQ_SLEEP \
49	49	KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT \| KVM_REQUEST_NO_WAKEUP)
50	50	#define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
	51	+#define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
51	52
52	53	DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
53	54
@@ -147,6 +148,13 @@ struct kvm_cpu_context { · 93 unmodified lines
147	148
148	149	typedef struct kvm_cpu_context kvm_cpu_context_t;
149	150
	151	+struct vcpu_reset_state {
	152	+ unsigned long pc;
	153	+ unsigned long r0;
	154	+ bool be;
	155	+ bool reset;
	156	+};
	157	+
150	158	struct kvm_vcpu_arch {
151	159	struct kvm_cpu_context ctxt;
152	160
@@ -186,6 +194,8 @@ struct kvm_vcpu_arch { · 33 unmodified lines
186	194	/* Cache some mmu pages needed inside spinlock regions */
187	195	struct kvm_mmu_memory_cache mmu_page_cache;
188	196
	197	+ struct vcpu_reset_state reset_state;
	198	+
189	199	/* Detect first run of a vcpu */
190	200	bool has_run_once;
191	201	};

arch/arm/include/asm/stage2_pgtable.h+5−0

@@ -76,4 +76,9 @@ static inline bool kvm_stage2_has_pud(struct kvm *kvm) · 75 unmodified lines
76	76	#define S2_PMD_MASK PMD_MASK
77	77	#define S2_PMD_SIZE PMD_SIZE
78	78
	79	+static inline bool kvm_stage2_has_pmd(struct kvm *kvm)
	80	+{
	81	+ return true;
	82	+}
	83	+
79	84	#endif /* __ARM_S2_PGTABLE_H_ */

arch/arm/kvm/coproc.c+2−2

@@ -1450,6 +1450,6 @@ void kvm_reset_coprocs(struct kvm_vcpu *vcpu) · 1449 unmodified lines
1450	1450	reset_coproc_regs(vcpu, table, num);
1451	1451
1452	1452	for (num = 1; num < NR_CP15_REGS; num++)
1453		− if (vcpu_cp15(vcpu, num) == 0x42424242)
1454		− panic("Didn't reset vcpu_cp15(vcpu, %zi)", num);
	1453	+ WARN(vcpu_cp15(vcpu, num) == 0x42424242,
	1454	+ "Didn't reset vcpu_cp15(vcpu, %zi)", num);
1455	1455	}

arch/arm/kvm/reset.c+24−0

@@ -26,6 +26,7 @@ · 25 unmodified lines
26	26	#include <asm/cputype.h>
27	27	#include <asm/kvm_arm.h>
28	28	#include <asm/kvm_coproc.h>
	29	+#include <asm/kvm_emulate.h>
29	30
30	31	#include <kvm/arm_arch_timer.h>
31	32
@@ -69,6 +70,29 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) · 37 unmodified lines
69	70	/* Reset CP15 registers */
70	71	kvm_reset_coprocs(vcpu);
71	72
	73	+ /*
	74	+ * Additional reset state handling that PSCI may have imposed on us.
	75	+ * Must be done after all the sys_reg reset.
	76	+ */
	77	+ if (READ_ONCE(vcpu->arch.reset_state.reset)) {
	78	+ unsigned long target_pc = vcpu->arch.reset_state.pc;
	79	+
	80	+ /* Gracefully handle Thumb2 entry point */
	81	+ if (target_pc & 1) {
	82	+ target_pc &= ~1UL;
	83	+ vcpu_set_thumb(vcpu);
	84	+ }
	85	+
	86	+ /* Propagate caller endianness */
	87	+ if (vcpu->arch.reset_state.be)
	88	+ kvm_vcpu_set_be(vcpu);
	89	+
	90	+ *vcpu_pc(vcpu) = target_pc;
	91	+ vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0);
	92	+
	93	+ vcpu->arch.reset_state.reset = false;
	94	+ }
	95	+
72	96	/* Reset arch_timer context */
73	97	return kvm_timer_vcpu_reset(vcpu);
74	98	}

arch/arm64/include/asm/kvm_host.h+11−0

@@ -48,6 +48,7 @@ · 47 unmodified lines
48	48	#define KVM_REQ_SLEEP \
49	49	KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT \| KVM_REQUEST_NO_WAKEUP)
50	50	#define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
	51	+#define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
51	52
52	53	DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
53	54
@@ -208,6 +209,13 @@ struct kvm_cpu_context { · 154 unmodified lines
208	209
209	210	typedef struct kvm_cpu_context kvm_cpu_context_t;
210	211
	212	+struct vcpu_reset_state {
	213	+ unsigned long pc;
	214	+ unsigned long r0;
	215	+ bool be;
	216	+ bool reset;
	217	+};
	218	+
211	219	struct kvm_vcpu_arch {
212	220	struct kvm_cpu_context ctxt;
213	221
@@ -297,6 +305,9 @@ struct kvm_vcpu_arch { · 83 unmodified lines
297	305	/* Virtual SError ESR to restore when HCR_EL2.VSE is set */
298	306	u64 vsesr_el2;
299	307
	308	+ /* Additional reset state */
	309	+ struct vcpu_reset_state reset_state;
	310	+
300	311	/* True when deferrable sysregs are loaded on the physical CPU,
301	312	* see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */
302	313	bool sysregs_loaded_on_cpu;

arch/arm64/kvm/hyp/switch.c+5−0

@@ -23,6 +23,7 @@ · 22 unmodified lines
23	23	#include <kvm/arm_psci.h>
24	24
25	25	#include <asm/cpufeature.h>
	26	+#include <asm/kprobes.h>
26	27	#include <asm/kvm_asm.h>
27	28	#include <asm/kvm_emulate.h>
28	29	#include <asm/kvm_host.h>
@@ -107,6 +108,7 @@ static void activate_traps_vhe(struct kvm_vcpu *vcpu) · 78 unmodified lines
107	108
108	109	write_sysreg(kvm_get_hyp_vector(), vbar_el1);
109	110	}
	111	+NOKPROBE_SYMBOL(activate_traps_vhe);
110	112
111	113	static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
112	114	{
@@ -154,6 +156,7 @@ static void deactivate_traps_vhe(void) · 41 unmodified lines
154	156	write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
155	157	write_sysreg(vectors, vbar_el1);
156	158	}
	159	+NOKPROBE_SYMBOL(deactivate_traps_vhe);
157	160
158	161	static void __hyp_text __deactivate_traps_nvhe(void)
159	162	{
@@ -513,6 +516,7 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) · 353 unmodified lines
513	516
514	517	return exit_code;
515	518	}
	519	+NOKPROBE_SYMBOL(kvm_vcpu_run_vhe);
516	520
517	521	/* Switch to the guest for legacy non-VHE systems */
518	522	int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
@@ -620,6 +624,7 @@ static void __hyp_call_panic_vhe(u64 spsr, u64 elr, u64 par, · 101 unmodified lines
620	624	read_sysreg_el2(esr), read_sysreg_el2(far),
621	625	read_sysreg(hpfar_el2), par, vcpu);
622	626	}
	627	+NOKPROBE_SYMBOL(__hyp_call_panic_vhe);
623	628
624	629	void __hyp_text __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
625	630	{

arch/arm64/kvm/hyp/sysreg-sr.c+5−0

@@ -18,6 +18,7 @@ · 17 unmodified lines
18	18	#include <linux/compiler.h>
19	19	#include <linux/kvm_host.h>
20	20
	21	+#include <asm/kprobes.h>
21	22	#include <asm/kvm_asm.h>
22	23	#include <asm/kvm_emulate.h>
23	24	#include <asm/kvm_hyp.h>
@@ -98,12 +99,14 @@ void sysreg_save_host_state_vhe(struct kvm_cpu_context *ctxt) · 74 unmodified lines
98	99	{
99	100	__sysreg_save_common_state(ctxt);
100	101	}
	102	+NOKPROBE_SYMBOL(sysreg_save_host_state_vhe);
101	103
102	104	void sysreg_save_guest_state_vhe(struct kvm_cpu_context *ctxt)
103	105	{
104	106	__sysreg_save_common_state(ctxt);
105	107	__sysreg_save_el2_return_state(ctxt);
106	108	}
	109	+NOKPROBE_SYMBOL(sysreg_save_guest_state_vhe);
107	110
108	111	static void __hyp_text __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
109	112	{
@@ -188,12 +191,14 @@ void sysreg_restore_host_state_vhe(struct kvm_cpu_context *ctxt) · 78 unmodified lines
188	191	{
189	192	__sysreg_restore_common_state(ctxt);
190	193	}
	194	+NOKPROBE_SYMBOL(sysreg_restore_host_state_vhe);
191	195
192	196	void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt)
193	197	{
194	198	__sysreg_restore_common_state(ctxt);
195	199	__sysreg_restore_el2_return_state(ctxt);
196	200	}
	201	+NOKPROBE_SYMBOL(sysreg_restore_guest_state_vhe);
197	202
198	203	void __hyp_text __sysreg32_save_state(struct kvm_vcpu *vcpu)
199	204	{

arch/arm64/kvm/reset.c+48−2

@@ -32,6 +32,7 @@ · 31 unmodified lines
32	32	#include <asm/kvm_arm.h>
33	33	#include <asm/kvm_asm.h>
34	34	#include <asm/kvm_coproc.h>
	35	+#include <asm/kvm_emulate.h>
35	36	#include <asm/kvm_mmu.h>
36	37
37	38	/* Maximum phys_shift supported for any VM on this host */
@@ -105,16 +106,33 @@ int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext) · 67 unmodified lines
105	106	* This function finds the right table above and sets the registers on
106	107	* the virtual CPU struct to their architecturally defined reset
107	108	* values.
	109	+ *
	110	+ * Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT
	111	+ * ioctl or as part of handling a request issued by another VCPU in the PSCI
	112	+ * handling code. In the first case, the VCPU will not be loaded, and in the
	113	+ * second case the VCPU will be loaded. Because this function operates purely
	114	+ * on the memory-backed valus of system registers, we want to do a full put if
	115	+ * we were loaded (handling a request) and load the values back at the end of
	116	+ * the function. Otherwise we leave the state alone. In both cases, we
	117	+ * disable preemption around the vcpu reset as we would otherwise race with
	118	+ * preempt notifiers which also call put/load.
108	119	*/
109	120	int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
110	121	{
111	122	const struct kvm_regs *cpu_reset;
	123	+ int ret = -EINVAL;
	124	+ bool loaded;
	125	+
	126	+ preempt_disable();
	127	+ loaded = (vcpu->cpu != -1);
	128	+ if (loaded)
	129	+ kvm_arch_vcpu_put(vcpu);
112	130
113	131	switch (vcpu->arch.target) {
114	132	default:
115	133	if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
116	134	if (!cpu_has_32bit_el1())
117		− return -EINVAL;
	135	+ goto out;
118	136	cpu_reset = &default_regs_reset32;
119	137	} else {
120	138	cpu_reset = &default_regs_reset;
@@ -129,6 +147,29 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) · 8 unmodified lines
129	147	/* Reset system registers */
130	148	kvm_reset_sys_regs(vcpu);
131	149
	150	+ /*
	151	+ * Additional reset state handling that PSCI may have imposed on us.
	152	+ * Must be done after all the sys_reg reset.
	153	+ */
	154	+ if (vcpu->arch.reset_state.reset) {
	155	+ unsigned long target_pc = vcpu->arch.reset_state.pc;
	156	+
	157	+ /* Gracefully handle Thumb2 entry point */
	158	+ if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
	159	+ target_pc &= ~1UL;
	160	+ vcpu_set_thumb(vcpu);
	161	+ }
	162	+
	163	+ /* Propagate caller endianness */
	164	+ if (vcpu->arch.reset_state.be)
	165	+ kvm_vcpu_set_be(vcpu);
	166	+
	167	+ *vcpu_pc(vcpu) = target_pc;
	168	+ vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0);
	169	+
	170	+ vcpu->arch.reset_state.reset = false;
	171	+ }
	172	+
132	173	/* Reset PMU */
133	174	kvm_pmu_vcpu_reset(vcpu);
134	175
@@ -137,7 +178,12 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) · 2 unmodified lines
137	178	vcpu->arch.workaround_flags \|= VCPU_WORKAROUND_2_FLAG;
138	179
139	180	/* Reset timer */
140		− return kvm_timer_vcpu_reset(vcpu);
	181	+ ret = kvm_timer_vcpu_reset(vcpu);
	182	+out:
	183	+ if (loaded)
	184	+ kvm_arch_vcpu_load(vcpu, smp_processor_id());
	185	+ preempt_enable();
	186	+ return ret;
141	187	}
142	188
143	189	void kvm_set_ipa_limit(void)

arch/arm64/kvm/sys_regs.c+32−18

@@ -314,12 +314,29 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu, · 313 unmodified lines
314	314	return read_zero(vcpu, p);
315	315	}
316	316
317		−static bool trap_undef(struct kvm_vcpu *vcpu,
318		− struct sys_reg_params *p,
319		− const struct sys_reg_desc *r)
	317	+/*
	318	+ * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
	319	+ * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
	320	+ * system, these registers should UNDEF. LORID_EL1 being a RO register, we
	321	+ * treat it separately.
	322	+ */
	323	+static bool trap_loregion(struct kvm_vcpu *vcpu,
	324	+ struct sys_reg_params *p,
	325	+ const struct sys_reg_desc *r)
320	326	{
321		− kvm_inject_undefined(vcpu);
322		− return false;
	327	+ u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
	328	+ u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
	329	+ (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
	330	+
	331	+ if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
	332	+ kvm_inject_undefined(vcpu);
	333	+ return false;
	334	+ }
	335	+
	336	+ if (p->is_write && sr == SYS_LORID_EL1)
	337	+ return write_to_read_only(vcpu, p, r);
	338	+
	339	+ return trap_raz_wi(vcpu, p, r);
323	340	}
324	341
325	342	static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
@@ -1048,11 +1065,6 @@ static u64 read_id_reg(struct sys_reg_desc const *r, bool raz) · 722 unmodified lines
1048	1065	if (val & ptrauth_mask)
1049	1066	kvm_debug("ptrauth unsupported for guests, suppressing\n");
1050	1067	val &= ~ptrauth_mask;
1051		− } else if (id == SYS_ID_AA64MMFR1_EL1) {
1052		− if (val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))
1053		− kvm_debug("LORegions unsupported for guests, suppressing\n");
1054		−
1055		− val &= ~(0xfUL << ID_AA64MMFR1_LOR_SHIFT);
1056	1068	}
1057	1069
1058	1070	return val;
@@ -1338,11 +1350,11 @@ static const struct sys_reg_desc sys_reg_descs[] = { · 279 unmodified lines
1338	1350	{ SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1339	1351	{ SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1340	1352
1341		− { SYS_DESC(SYS_LORSA_EL1), trap_undef },
1342		− { SYS_DESC(SYS_LOREA_EL1), trap_undef },
1343		− { SYS_DESC(SYS_LORN_EL1), trap_undef },
1344		− { SYS_DESC(SYS_LORC_EL1), trap_undef },
1345		− { SYS_DESC(SYS_LORID_EL1), trap_undef },
	1353	+ { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
	1354	+ { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
	1355	+ { SYS_DESC(SYS_LORN_EL1), trap_loregion },
	1356	+ { SYS_DESC(SYS_LORC_EL1), trap_loregion },
	1357	+ { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1346	1358
1347	1359	{ SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1348	1360	{ SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
@@ -2596,7 +2608,9 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) · 1247 unmodified lines
2596	2608	table = get_target_table(vcpu->arch.target, true, &num);
2597	2609	reset_sys_reg_descs(vcpu, table, num);
2598	2610
2599		− for (num = 1; num < NR_SYS_REGS; num++)
2600		− if (__vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
2601		− panic("Didn't reset __vcpu_sys_reg(%zi)", num);
	2611	+ for (num = 1; num < NR_SYS_REGS; num++) {
	2612	+ if (WARN(__vcpu_sys_reg(vcpu, num) == 0x4242424242424242,
	2613	+ "Didn't reset __vcpu_sys_reg(%zi)\n", num))
	2614	+ break;
	2615	+ }
2602	2616	}

arch/x86/kvm/vmx/nested.c+9−3

@@ -2473,6 +2473,10 @@ static int nested_check_vm_execution_controls(struct kvm_vcpu *vcpu, · 2472 unmodified lines
2473	2473	(nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id))
2474	2474	return -EINVAL;
2475	2475
	2476	+ if (!nested_cpu_has_preemption_timer(vmcs12) &&
	2477	+ nested_cpu_has_save_preemption_timer(vmcs12))
	2478	+ return -EINVAL;
	2479	+
2476	2480	if (nested_cpu_has_ept(vmcs12) &&
2477	2481	!valid_ept_address(vcpu, vmcs12->ept_pointer))
2478	2482	return -EINVAL;
@@ -5557,9 +5561,11 @@ void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps, · 3078 unmodified lines
5557	5561	* secondary cpu-based controls. Do not include those that
5558	5562	* depend on CPUID bits, they are added later by vmx_cpuid_update.
5559	5563	*/
5560		− rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
5561		− msrs->secondary_ctls_low,
5562		− msrs->secondary_ctls_high);
	5564	+ if (msrs->procbased_ctls_high & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
	5565	+ rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
	5566	+ msrs->secondary_ctls_low,
	5567	+ msrs->secondary_ctls_high);
	5568	+
5563	5569	msrs->secondary_ctls_low = 0;
5564	5570	msrs->secondary_ctls_high &=
5565	5571	SECONDARY_EXEC_DESC \|

arch/x86/kvm/vmx/vmx.c+13−16

@@ -863,7 +863,8 @@ static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, · 862 unmodified lines
863	863	if (!entry_only)
864	864	j = find_msr(&m->host, msr);
865	865
866		− if (i == NR_AUTOLOAD_MSRS \|\| j == NR_AUTOLOAD_MSRS) {
	866	+ if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) \|\|
	867	+ (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) {
867	868	printk_once(KERN_WARNING "Not enough msr switch entries. "
868	869	"Can't add msr %x\n", msr);
869	870	return;
@@ -1193,21 +1194,6 @@ static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) · 323 unmodified lines
1193	1194	if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1194	1195	return;
1195	1196
1196		− /*
1197		− * First handle the simple case where no cmpxchg is necessary; just
1198		− * allow posting non-urgent interrupts.
1199		− *
1200		− * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1201		− * PI.NDST: pi_post_block will do it for us and the wakeup_handler
1202		− * expects the VCPU to be on the blocked_vcpu_list that matches
1203		− * PI.NDST.
1204		− */
1205		− if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR \|\|
1206		− vcpu->cpu == cpu) {
1207		− pi_clear_sn(pi_desc);
1208		− return;
1209		− }
1210		−
1211	1197	/* The full case. */
1212	1198	do {
1213	1199	old.control = new.control = pi_desc->control;
@@ -1222,6 +1208,17 @@ static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) · 8 unmodified lines
1222	1208	new.sn = 0;
1223	1209	} while (cmpxchg64(&pi_desc->control, old.control,
1224	1210	new.control) != old.control);
	1211	+
	1212	+ /*
	1213	+ * Clear SN before reading the bitmap. The VT-d firmware
	1214	+ * writes the bitmap and reads SN atomically (5.2.3 in the
	1215	+ * spec), so it doesn't really have a memory barrier that
	1216	+ * pairs with this, but we cannot do that and we need one.
	1217	+ */
	1218	+ smp_mb__after_atomic();
	1219	+
	1220	+ if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
	1221	+ pi_set_on(pi_desc);
1225	1222	}
1226	1223
1227	1224	/*

arch/x86/kvm/vmx/vmx.h+5−5

@@ -337,16 +337,16 @@ static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) · 336 unmodified lines
337	337	return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
338	338	}
339	339
340		−static inline void pi_clear_sn(struct pi_desc *pi_desc)
	340	+static inline void pi_set_sn(struct pi_desc *pi_desc)
341	341	{
342		− return clear_bit(POSTED_INTR_SN,
	342	+ return set_bit(POSTED_INTR_SN,
343	343	(unsigned long *)&pi_desc->control);
344	344	}
345	345
346		−static inline void pi_set_sn(struct pi_desc *pi_desc)
	346	+static inline void pi_set_on(struct pi_desc *pi_desc)
347	347	{
348		− return set_bit(POSTED_INTR_SN,
349		− (unsigned long *)&pi_desc->control);
	348	+ set_bit(POSTED_INTR_ON,
	349	+ (unsigned long *)&pi_desc->control);
350	350	}
351	351
352	352	static inline void pi_clear_on(struct pi_desc *pi_desc)

arch/x86/kvm/x86.c+1−1

@@ -7801,7 +7801,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) · 7800 unmodified lines
7801	7801	* 1) We should set ->mode before checking ->requests. Please see
7802	7802	* the comment in kvm_vcpu_exiting_guest_mode().
7803	7803	*
7804		− * 2) For APICv, we should set ->mode before checking PIR.ON. This
	7804	+ * 2) For APICv, we should set ->mode before checking PID.ON. This
7805	7805	* pairs with the memory barrier implicit in pi_test_and_set_on
7806	7806	* (see vmx_deliver_posted_interrupt).
7807	7807	*

include/kvm/arm_vgic.h+3−3

@@ -100,7 +100,7 @@ enum vgic_irq_config { · 99 unmodified lines
100	100	};
101	101
102	102	struct vgic_irq {
103		− spinlock_t irq_lock; /* Protects the content of the struct */
	103	+ raw_spinlock_t irq_lock; /* Protects the content of the struct */
104	104	struct list_head lpi_list; /* Used to link all LPIs together */
105	105	struct list_head ap_list;
106	106
@@ -256,7 +256,7 @@ struct vgic_dist { · 149 unmodified lines
256	256	u64 propbaser;
257	257
258	258	/* Protects the lpi_list and the count value below. */
259		− spinlock_t lpi_list_lock;
	259	+ raw_spinlock_t lpi_list_lock;
260	260	struct list_head lpi_list_head;
261	261	int lpi_list_count;
262	262
@@ -307,7 +307,7 @@ struct vgic_cpu { · 44 unmodified lines
307	307	unsigned int used_lrs;
308	308	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
309	309
310		− spinlock_t ap_list_lock; /* Protects the ap_list */
	310	+ raw_spinlock_t ap_list_lock; /* Protects the ap_list */
311	311
312	312	/*
313	313	* List of IRQs that this VCPU should consider because they are either

virt/kvm/arm/arm.c+10−0

@@ -626,6 +626,13 @@ static void vcpu_req_sleep(struct kvm_vcpu *vcpu) · 625 unmodified lines
626	626	/* Awaken to handle a signal, request we sleep again later. */
627	627	kvm_make_request(KVM_REQ_SLEEP, vcpu);
628	628	}
	629	+
	630	+ /*
	631	+ * Make sure we will observe a potential reset request if we've
	632	+ * observed a change to the power state. Pairs with the smp_wmb() in
	633	+ * kvm_psci_vcpu_on().
	634	+ */
	635	+ smp_rmb();
629	636	}
630	637
631	638	static int kvm_vcpu_initialized(struct kvm_vcpu *vcpu)
@@ -639,6 +646,9 @@ static void check_vcpu_requests(struct kvm_vcpu *vcpu) · 7 unmodified lines
639	646	if (kvm_check_request(KVM_REQ_SLEEP, vcpu))
640	647	vcpu_req_sleep(vcpu);
641	648
	649	+ if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu))
	650	+ kvm_reset_vcpu(vcpu);
	651	+
642	652	/*
643	653	* Clear IRQ_PENDING requests that were made to guarantee
644	654	* that a VCPU sees new virtual interrupts.

virt/kvm/arm/mmu.c+6−3

@@ -1695,11 +1695,14 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, · 1694 unmodified lines
1695	1695
1696	1696	vma_pagesize = vma_kernel_pagesize(vma);
1697	1697	/*
1698		− * PUD level may not exist for a VM but PMD is guaranteed to
1699		− * exist.
	1698	+ * The stage2 has a minimum of 2 level table (For arm64 see
	1699	+ * kvm_arm_setup_stage2()). Hence, we are guaranteed that we can
	1700	+ * use PMD_SIZE huge mappings (even when the PMD is folded into PGD).
	1701	+ * As for PUD huge maps, we must make sure that we have at least
	1702	+ * 3 levels, i.e, PMD is not folded.
1700	1703	*/
1701	1704	if ((vma_pagesize == PMD_SIZE \|\|
1702		− (vma_pagesize == PUD_SIZE && kvm_stage2_has_pud(kvm))) &&
	1705	+ (vma_pagesize == PUD_SIZE && kvm_stage2_has_pmd(kvm))) &&
1703	1706	!force_pte) {
1704	1707	gfn = (fault_ipa & huge_page_mask(hstate_vma(vma))) >> PAGE_SHIFT;
1705	1708	}

virt/kvm/arm/psci.c+16−20

@@ -104,12 +104,10 @@ static void kvm_psci_vcpu_off(struct kvm_vcpu *vcpu) · 103 unmodified lines
104	104
105	105	static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
106	106	{
	107	+ struct vcpu_reset_state *reset_state;
107	108	struct kvm *kvm = source_vcpu->kvm;
108	109	struct kvm_vcpu *vcpu = NULL;
109		− struct swait_queue_head *wq;
110	110	unsigned long cpu_id;
111		− unsigned long context_id;
112		− phys_addr_t target_pc;
113	111
114	112	cpu_id = smccc_get_arg1(source_vcpu) & MPIDR_HWID_BITMASK;
115	113	if (vcpu_mode_is_32bit(source_vcpu))
@@ -130,32 +128,30 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) · 14 unmodified lines
130	128	return PSCI_RET_INVALID_PARAMS;
131	129	}
132	130
133		− target_pc = smccc_get_arg2(source_vcpu);
134		− context_id = smccc_get_arg3(source_vcpu);
	131	+ reset_state = &vcpu->arch.reset_state;
135	132
136		− kvm_reset_vcpu(vcpu);
137		−
138		− /* Gracefully handle Thumb2 entry point */
139		− if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
140		− target_pc &= ~((phys_addr_t) 1);
141		− vcpu_set_thumb(vcpu);
142		− }
	133	+ reset_state->pc = smccc_get_arg2(source_vcpu);
143	134
144	135	/* Propagate caller endianness */
145		− if (kvm_vcpu_is_be(source_vcpu))
146		− kvm_vcpu_set_be(vcpu);
	136	+ reset_state->be = kvm_vcpu_is_be(source_vcpu);
147	137
148		− *vcpu_pc(vcpu) = target_pc;
149	138	/*
150	139	* NOTE: We always update r0 (or x0) because for PSCI v0.1
151	140	* the general puspose registers are undefined upon CPU_ON.
152	141	*/
153		− smccc_set_retval(vcpu, context_id, 0, 0, 0);
154		− vcpu->arch.power_off = false;
155		− smp_mb(); /* Make sure the above is visible */
	142	+ reset_state->r0 = smccc_get_arg3(source_vcpu);
	143	+
	144	+ WRITE_ONCE(reset_state->reset, true);
	145	+ kvm_make_request(KVM_REQ_VCPU_RESET, vcpu);
156	146
157		− wq = kvm_arch_vcpu_wq(vcpu);
158		− swake_up_one(wq);
	147	+ /*
	148	+ * Make sure the reset request is observed if the change to
	149	+ * power_state is observed.
	150	+ */
	151	+ smp_wmb();
	152	+
	153	+ vcpu->arch.power_off = false;
	154	+ kvm_vcpu_wake_up(vcpu);
159	155
160	156	return PSCI_RET_SUCCESS;
161	157	}

virt/kvm/arm/vgic/vgic-debug.c+2−2

@@ -251,9 +251,9 @@ static int vgic_debug_show(struct seq_file s, void v) · 250 unmodified lines
251	251	return 0;
252	252	}
253	253
254		− spin_lock_irqsave(&irq->irq_lock, flags);
	254	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
255	255	print_irq_state(s, irq, vcpu);
256		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	256	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
257	257
258	258	vgic_put_irq(kvm, irq);
259	259	return 0;

virt/kvm/arm/vgic/vgic-init.c+18−12

@@ -64,7 +64,7 @@ void kvm_vgic_early_init(struct kvm *kvm) · 63 unmodified lines
64	64	struct vgic_dist *dist = &kvm->arch.vgic;
65	65
66	66	INIT_LIST_HEAD(&dist->lpi_list_head);
67		− spin_lock_init(&dist->lpi_list_lock);
	67	+ raw_spin_lock_init(&dist->lpi_list_lock);
68	68	}
69	69
70	70	/* CREATION */
@@ -171,7 +171,7 @@ static int kvm_vgic_dist_init(struct kvm *kvm, unsigned int nr_spis) · 100 unmodified lines
171	171
172	172	irq->intid = i + VGIC_NR_PRIVATE_IRQS;
173	173	INIT_LIST_HEAD(&irq->ap_list);
174		− spin_lock_init(&irq->irq_lock);
	174	+ raw_spin_lock_init(&irq->irq_lock);
175	175	irq->vcpu = NULL;
176	176	irq->target_vcpu = vcpu0;
177	177	kref_init(&irq->refcount);
@@ -206,7 +206,7 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) · 28 unmodified lines
206	206	vgic_cpu->sgi_iodev.base_addr = VGIC_ADDR_UNDEF;
207	207
208	208	INIT_LIST_HEAD(&vgic_cpu->ap_list_head);
209		− spin_lock_init(&vgic_cpu->ap_list_lock);
	209	+ raw_spin_lock_init(&vgic_cpu->ap_list_lock);
210	210
211	211	/*
212	212	* Enable and configure all SGIs to be edge-triggered and
@@ -216,7 +216,7 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) · 3 unmodified lines
216	216	struct vgic_irq *irq = &vgic_cpu->private_irqs[i];
217	217
218	218	INIT_LIST_HEAD(&irq->ap_list);
219		− spin_lock_init(&irq->irq_lock);
	219	+ raw_spin_lock_init(&irq->irq_lock);
220	220	irq->intid = i;
221	221	irq->vcpu = NULL;
222	222	irq->target_vcpu = vcpu;
@@ -231,13 +231,6 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) · 8 unmodified lines
231	231	irq->config = VGIC_CONFIG_LEVEL;
232	232	}
233	233
234		− /*
235		− * GICv3 can only be created via the KVM_DEVICE_CREATE API and
236		− * so we always know the emulation type at this point as it's
237		− * either explicitly configured as GICv3, or explicitly
238		− * configured as GICv2, or not configured yet which also
239		− * implies GICv2.
240		− */
241	234	if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
242	235	irq->group = 1;
243	236	else
@@ -281,7 +274,7 @@ int vgic_init(struct kvm *kvm) · 37 unmodified lines
281	274	{
282	275	struct vgic_dist *dist = &kvm->arch.vgic;
283	276	struct kvm_vcpu *vcpu;
284		− int ret = 0, i;
	277	+ int ret = 0, i, idx;
285	278
286	279	if (vgic_initialized(kvm))
287	280	return 0;
@@ -298,6 +291,19 @@ int vgic_init(struct kvm *kvm) · 10 unmodified lines
298	291	if (ret)
299	292	goto out;
300	293
	294	+ /* Initialize groups on CPUs created before the VGIC type was known */
	295	+ kvm_for_each_vcpu(idx, vcpu, kvm) {
	296	+ struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
	297	+
	298	+ for (i = 0; i < VGIC_NR_PRIVATE_IRQS; i++) {
	299	+ struct vgic_irq *irq = &vgic_cpu->private_irqs[i];
	300	+ if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
	301	+ irq->group = 1;
	302	+ else
	303	+ irq->group = 0;
	304	+ }
	305	+ }
	306	+
301	307	if (vgic_has_its(kvm)) {
302	308	ret = vgic_v4_init(kvm);
303	309	if (ret)

virt/kvm/arm/vgic/vgic-its.c+11−11

@@ -65,7 +65,7 @@ static struct vgic_irq vgic_add_lpi(struct kvm kvm, u32 intid, · 64 unmodified lines
65	65
66	66	INIT_LIST_HEAD(&irq->lpi_list);
67	67	INIT_LIST_HEAD(&irq->ap_list);
68		− spin_lock_init(&irq->irq_lock);
	68	+ raw_spin_lock_init(&irq->irq_lock);
69	69
70	70	irq->config = VGIC_CONFIG_EDGE;
71	71	kref_init(&irq->refcount);
@@ -73,7 +73,7 @@ static struct vgic_irq vgic_add_lpi(struct kvm kvm, u32 intid, · 1 unmodified line
73	73	irq->target_vcpu = vcpu;
74	74	irq->group = 1;
75	75
76		− spin_lock_irqsave(&dist->lpi_list_lock, flags);
	76	+ raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
77	77
78	78	/*
79	79	* There could be a race with another vgic_add_lpi(), so we need to
@@ -101,7 +101,7 @@ static struct vgic_irq vgic_add_lpi(struct kvm kvm, u32 intid, · 21 unmodified lines
101	101	dist->lpi_list_count++;
102	102
103	103	out_unlock:
104		− spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
	104	+ raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
105	105
106	106	/*
107	107	* We "cache" the configuration table entries in our struct vgic_irq's.
@@ -287,7 +287,7 @@ static int update_lpi_config(struct kvm kvm, struct vgic_irq irq, · 179 unmodified lines
287	287	if (ret)
288	288	return ret;
289	289
290		− spin_lock_irqsave(&irq->irq_lock, flags);
	290	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
291	291
292	292	if (!filter_vcpu \|\| filter_vcpu == irq->target_vcpu) {
293	293	irq->priority = LPI_PROP_PRIORITY(prop);
@@ -299,7 +299,7 @@ static int update_lpi_config(struct kvm kvm, struct vgic_irq irq, · 5 unmodified lines
299	299	}
300	300	}
301	301
302		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	302	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
303	303
304	304	if (irq->hw)
305	305	return its_prop_update_vlpi(irq->host_irq, prop, needs_inv);
@@ -332,7 +332,7 @@ int vgic_copy_lpi_list(struct kvm kvm, struct kvm_vcpu vcpu, u32 **intid_ptr) · 26 unmodified lines
332	332	if (!intids)
333	333	return -ENOMEM;
334	334
335		− spin_lock_irqsave(&dist->lpi_list_lock, flags);
	335	+ raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
336	336	list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
337	337	if (i == irq_count)
338	338	break;
@@ -341,7 +341,7 @@ int vgic_copy_lpi_list(struct kvm kvm, struct kvm_vcpu vcpu, u32 **intid_ptr) · 2 unmodified lines
341	341	continue;
342	342	intids[i++] = irq->intid;
343	343	}
344		− spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
	344	+ raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
345	345
346	346	*intid_ptr = intids;
347	347	return i;
@@ -352,9 +352,9 @@ static int update_affinity(struct vgic_irq irq, struct kvm_vcpu vcpu) · 4 unmodified lines
352	352	int ret = 0;
353	353	unsigned long flags;
354	354
355		− spin_lock_irqsave(&irq->irq_lock, flags);
	355	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
356	356	irq->target_vcpu = vcpu;
357		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	357	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
358	358
359	359	if (irq->hw) {
360	360	struct its_vlpi_map map;
@@ -455,7 +455,7 @@ static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu) · 94 unmodified lines
455	455	}
456	456
457	457	irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]);
458		− spin_lock_irqsave(&irq->irq_lock, flags);
	458	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
459	459	irq->pending_latch = pendmask & (1U << bit_nr);
460	460	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
461	461	vgic_put_irq(vcpu->kvm, irq);
@@ -612,7 +612,7 @@ static int vgic_its_trigger_msi(struct kvm kvm, struct vgic_its its, · 150 unmodified lines
612	612	return irq_set_irqchip_state(irq->host_irq,
613	613	IRQCHIP_STATE_PENDING, true);
614	614
615		− spin_lock_irqsave(&irq->irq_lock, flags);
	615	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
616	616	irq->pending_latch = true;
617	617	vgic_queue_irq_unlock(kvm, irq, flags);
618	618

virt/kvm/arm/vgic/vgic-mmio-v2.c+7−7

@@ -147,7 +147,7 @@ static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu, · 146 unmodified lines
147	147
148	148	irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);
149	149
150		− spin_lock_irqsave(&irq->irq_lock, flags);
	150	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
151	151	irq->pending_latch = true;
152	152	irq->source \|= 1U << source_vcpu->vcpu_id;
153	153
@@ -191,13 +191,13 @@ static void vgic_mmio_write_target(struct kvm_vcpu *vcpu, · 37 unmodified lines
191	191	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);
192	192	int target;
193	193
194		− spin_lock_irqsave(&irq->irq_lock, flags);
	194	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
195	195
196	196	irq->targets = (val >> (i * 8)) & cpu_mask;
197	197	target = irq->targets ? __ffs(irq->targets) : 0;
198	198	irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
199	199
200		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	200	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
201	201	vgic_put_irq(vcpu->kvm, irq);
202	202	}
203	203	}
@@ -230,13 +230,13 @@ static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu, · 26 unmodified lines
230	230	for (i = 0; i < len; i++) {
231	231	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
232	232
233		− spin_lock_irqsave(&irq->irq_lock, flags);
	233	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
234	234
235	235	irq->source &= ~((val >> (i * 8)) & 0xff);
236	236	if (!irq->source)
237	237	irq->pending_latch = false;
238	238
239		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	239	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
240	240	vgic_put_irq(vcpu->kvm, irq);
241	241	}
242	242	}
@@ -252,7 +252,7 @@ static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu, · 9 unmodified lines
252	252	for (i = 0; i < len; i++) {
253	253	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
254	254
255		− spin_lock_irqsave(&irq->irq_lock, flags);
	255	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
256	256
257	257	irq->source \|= (val >> (i * 8)) & 0xff;
258	258
@@ -260,7 +260,7 @@ static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu, · 1 unmodified line
260	260	irq->pending_latch = true;
261	261	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
262	262	} else {
263		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	263	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
264	264	}
265	265	vgic_put_irq(vcpu->kvm, irq);
266	266	}

virt/kvm/arm/vgic/vgic-mmio-v3.c+6−6

@@ -169,13 +169,13 @@ static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu, · 168 unmodified lines
169	169	if (!irq)
170	170	return;
171	171
172		− spin_lock_irqsave(&irq->irq_lock, flags);
	172	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
173	173
174	174	/* We only care about and preserve Aff0, Aff1 and Aff2. */
175	175	irq->mpidr = val & GENMASK(23, 0);
176	176	irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
177	177
178		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	178	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
179	179	vgic_put_irq(vcpu->kvm, irq);
180	180	}
181	181
@@ -281,7 +281,7 @@ static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu, · 99 unmodified lines
281	281	for (i = 0; i < len * 8; i++) {
282	282	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
283	283
284		− spin_lock_irqsave(&irq->irq_lock, flags);
	284	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
285	285	if (test_bit(i, &val)) {
286	286	/*
287	287	* pending_latch is set irrespective of irq type
@@ -292,7 +292,7 @@ static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu, · 4 unmodified lines
292	292	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
293	293	} else {
294	294	irq->pending_latch = false;
295		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	295	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
296	296	}
297	297
298	298	vgic_put_irq(vcpu->kvm, irq);
@@ -957,7 +957,7 @@ void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1) · 658 unmodified lines
957	957
958	958	irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
959	959
960		− spin_lock_irqsave(&irq->irq_lock, flags);
	960	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
961	961
962	962	/*
963	963	* An access targetting Group0 SGIs can only generate
@@ -968,7 +968,7 @@ void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1) · 4 unmodified lines
968	968	irq->pending_latch = true;
969	969	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
970	970	} else {
971		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	971	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
972	972	}
973	973
974	974	vgic_put_irq(vcpu->kvm, irq);

virt/kvm/arm/vgic/vgic-mmio.c+17−17

@@ -77,7 +77,7 @@ void vgic_mmio_write_group(struct kvm_vcpu *vcpu, gpa_t addr, · 76 unmodified lines
77	77	for (i = 0; i < len * 8; i++) {
78	78	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
79	79
80		− spin_lock_irqsave(&irq->irq_lock, flags);
	80	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
81	81	irq->group = !!(val & BIT(i));
82	82	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
83	83
@@ -120,7 +120,7 @@ void vgic_mmio_write_senable(struct kvm_vcpu *vcpu, · 36 unmodified lines
120	120	for_each_set_bit(i, &val, len * 8) {
121	121	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
122	122
123		− spin_lock_irqsave(&irq->irq_lock, flags);
	123	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
124	124	irq->enabled = true;
125	125	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
126	126
@@ -139,11 +139,11 @@ void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu, · 12 unmodified lines
139	139	for_each_set_bit(i, &val, len * 8) {
140	140	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
141	141
142		− spin_lock_irqsave(&irq->irq_lock, flags);
	142	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
143	143
144	144	irq->enabled = false;
145	145
146		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	146	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
147	147	vgic_put_irq(vcpu->kvm, irq);
148	148	}
149	149	}
@@ -160,10 +160,10 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu, · 10 unmodified lines
160	160	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
161	161	unsigned long flags;
162	162
163		− spin_lock_irqsave(&irq->irq_lock, flags);
	163	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
164	164	if (irq_is_pending(irq))
165	165	value \|= (1U << i);
166		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	166	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
167	167
168	168	vgic_put_irq(vcpu->kvm, irq);
169	169	}
@@ -215,7 +215,7 @@ void vgic_mmio_write_spending(struct kvm_vcpu *vcpu, · 45 unmodified lines
215	215	for_each_set_bit(i, &val, len * 8) {
216	216	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
217	217
218		− spin_lock_irqsave(&irq->irq_lock, flags);
	218	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
219	219	if (irq->hw)
220	220	vgic_hw_irq_spending(vcpu, irq, is_uaccess);
221	221	else
@@ -262,14 +262,14 @@ void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu, · 40 unmodified lines
262	262	for_each_set_bit(i, &val, len * 8) {
263	263	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
264	264
265		− spin_lock_irqsave(&irq->irq_lock, flags);
	265	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
266	266
267	267	if (irq->hw)
268	268	vgic_hw_irq_cpending(vcpu, irq, is_uaccess);
269	269	else
270	270	irq->pending_latch = false;
271	271
272		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	272	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
273	273	vgic_put_irq(vcpu->kvm, irq);
274	274	}
275	275	}
@@ -311,7 +311,7 @@ static void vgic_mmio_change_active(struct kvm_vcpu vcpu, struct vgic_irq irq, · 35 unmodified lines
311	311	unsigned long flags;
312	312	struct kvm_vcpu *requester_vcpu = vgic_get_mmio_requester_vcpu();
313	313
314		− spin_lock_irqsave(&irq->irq_lock, flags);
	314	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
315	315
316	316	if (irq->hw) {
317	317	vgic_hw_irq_change_active(vcpu, irq, active, !requester_vcpu);
@@ -342,7 +342,7 @@ static void vgic_mmio_change_active(struct kvm_vcpu vcpu, struct vgic_irq irq, · 24 unmodified lines
342	342	if (irq->active)
343	343	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
344	344	else
345		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	345	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
346	346	}
347	347
348	348	/*
@@ -485,10 +485,10 @@ void vgic_mmio_write_priority(struct kvm_vcpu *vcpu, · 136 unmodified lines
485	485	for (i = 0; i < len; i++) {
486	486	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
487	487
488		− spin_lock_irqsave(&irq->irq_lock, flags);
	488	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
489	489	/* Narrow the priority range to what we actually support */
490	490	irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
491		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	491	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
492	492
493	493	vgic_put_irq(vcpu->kvm, irq);
494	494	}
@@ -534,14 +534,14 @@ void vgic_mmio_write_config(struct kvm_vcpu *vcpu, · 39 unmodified lines
534	534	continue;
535	535
536	536	irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
537		− spin_lock_irqsave(&irq->irq_lock, flags);
	537	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
538	538
539	539	if (test_bit(i * 2 + 1, &val))
540	540	irq->config = VGIC_CONFIG_EDGE;
541	541	else
542	542	irq->config = VGIC_CONFIG_LEVEL;
543	543
544		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	544	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
545	545	vgic_put_irq(vcpu->kvm, irq);
546	546	}
547	547	}
@@ -590,12 +590,12 @@ void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid, · 42 unmodified lines
590	590	* restore irq config before line level.
591	591	*/
592	592	new_level = !!(val & (1U << i));
593		− spin_lock_irqsave(&irq->irq_lock, flags);
	593	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
594	594	irq->line_level = new_level;
595	595	if (new_level)
596	596	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
597	597	else
598		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	598	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
599	599
600	600	vgic_put_irq(vcpu->kvm, irq);
601	601	}

virt/kvm/arm/vgic/vgic-v2.c+2−2

@@ -84,7 +84,7 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu) · 83 unmodified lines
84	84
85	85	irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
86	86
87		− spin_lock(&irq->irq_lock);
	87	+ raw_spin_lock(&irq->irq_lock);
88	88
89	89	/* Always preserve the active bit */
90	90	irq->active = !!(val & GICH_LR_ACTIVE_BIT);
@@ -127,7 +127,7 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu) · 36 unmodified lines
127	127	vgic_irq_set_phys_active(irq, false);
128	128	}
129	129
130		− spin_unlock(&irq->irq_lock);
	130	+ raw_spin_unlock(&irq->irq_lock);
131	131	vgic_put_irq(vcpu->kvm, irq);
132	132	}
133	133

virt/kvm/arm/vgic/vgic-v3.c+4−4

@@ -76,7 +76,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) · 75 unmodified lines
76	76	if (!irq) /* An LPI could have been unmapped. */
77	77	continue;
78	78
79		− spin_lock(&irq->irq_lock);
	79	+ raw_spin_lock(&irq->irq_lock);
80	80
81	81	/* Always preserve the active bit */
82	82	irq->active = !!(val & ICH_LR_ACTIVE_BIT);
@@ -119,7 +119,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) · 36 unmodified lines
119	119	vgic_irq_set_phys_active(irq, false);
120	120	}
121	121
122		− spin_unlock(&irq->irq_lock);
	122	+ raw_spin_unlock(&irq->irq_lock);
123	123	vgic_put_irq(vcpu->kvm, irq);
124	124	}
125	125
@@ -347,9 +347,9 @@ retry: · 221 unmodified lines
347	347
348	348	status = val & (1 << bit_nr);
349	349
350		− spin_lock_irqsave(&irq->irq_lock, flags);
	350	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
351	351	if (irq->target_vcpu != vcpu) {
352		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	352	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
353	353	goto retry;
354	354	}
355	355	irq->pending_latch = status;

virt/kvm/arm/vgic/vgic.c+59−59

@@ -54,11 +54,11 @@ struct vgic_global kvm_vgic_global_state __ro_after_init = { · 53 unmodified lines
54	54	* When taking more than one ap_list_lock at the same time, always take the
55	55	* lowest numbered VCPU's ap_list_lock first, so:
56	56	* vcpuX->vcpu_id < vcpuY->vcpu_id:
57		− * spin_lock(vcpuX->arch.vgic_cpu.ap_list_lock);
58		− * spin_lock(vcpuY->arch.vgic_cpu.ap_list_lock);
	57	+ * raw_spin_lock(vcpuX->arch.vgic_cpu.ap_list_lock);
	58	+ * raw_spin_lock(vcpuY->arch.vgic_cpu.ap_list_lock);
59	59	*
60	60	* Since the VGIC must support injecting virtual interrupts from ISRs, we have
61		− * to use the spin_lock_irqsave/spin_unlock_irqrestore versions of outer
	61	+ * to use the raw_spin_lock_irqsave/raw_spin_unlock_irqrestore versions of outer
62	62	* spinlocks for any lock that may be taken while injecting an interrupt.
63	63	*/
64	64
@@ -72,7 +72,7 @@ static struct vgic_irq vgic_get_lpi(struct kvm kvm, u32 intid) · 7 unmodified lines
72	72	struct vgic_irq *irq = NULL;
73	73	unsigned long flags;
74	74
75		− spin_lock_irqsave(&dist->lpi_list_lock, flags);
	75	+ raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
76	76
77	77	list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
78	78	if (irq->intid != intid)
@@ -88,7 +88,7 @@ static struct vgic_irq vgic_get_lpi(struct kvm kvm, u32 intid) · 9 unmodified lines
88	88	irq = NULL;
89	89
90	90	out_unlock:
91		− spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
	91	+ raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
92	92
93	93	return irq;
94	94	}
@@ -138,15 +138,15 @@ void vgic_put_irq(struct kvm kvm, struct vgic_irq irq) · 43 unmodified lines
138	138	if (irq->intid < VGIC_MIN_LPI)
139	139	return;
140	140
141		− spin_lock_irqsave(&dist->lpi_list_lock, flags);
	141	+ raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
142	142	if (!kref_put(&irq->refcount, vgic_irq_release)) {
143		− spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
	143	+ raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
144	144	return;
145	145	};
146	146
147	147	list_del(&irq->lpi_list);
148	148	dist->lpi_list_count--;
149		− spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
	149	+ raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
150	150
151	151	kfree(irq);
152	152	}
@@ -244,8 +244,8 @@ static int vgic_irq_cmp(void priv, struct list_head a, struct list_head *b) · 91 unmodified lines
244	244	bool penda, pendb;
245	245	int ret;
246	246
247		− spin_lock(&irqa->irq_lock);
248		− spin_lock_nested(&irqb->irq_lock, SINGLE_DEPTH_NESTING);
	247	+ raw_spin_lock(&irqa->irq_lock);
	248	+ raw_spin_lock_nested(&irqb->irq_lock, SINGLE_DEPTH_NESTING);
249	249
250	250	if (irqa->active \|\| irqb->active) {
251	251	ret = (int)irqb->active - (int)irqa->active;
@@ -263,8 +263,8 @@ static int vgic_irq_cmp(void priv, struct list_head a, struct list_head *b) · 11 unmodified lines
263	263	/* Both pending and enabled, sort by priority */
264	264	ret = irqa->priority - irqb->priority;
265	265	out:
266		− spin_unlock(&irqb->irq_lock);
267		− spin_unlock(&irqa->irq_lock);
	266	+ raw_spin_unlock(&irqb->irq_lock);
	267	+ raw_spin_unlock(&irqa->irq_lock);
268	268	return ret;
269	269	}
270	270
@@ -325,7 +325,7 @@ retry: · 54 unmodified lines
325	325	* not need to be inserted into an ap_list and there is also
326	326	* no more work for us to do.
327	327	*/
328		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	328	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
329	329
330	330	/*
331	331	* We have to kick the VCPU here, because we could be
@@ -347,12 +347,12 @@ retry: · 15 unmodified lines
347	347	* We must unlock the irq lock to take the ap_list_lock where
348	348	* we are going to insert this new pending interrupt.
349	349	*/
350		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	350	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
351	351
352	352	/* someone can do stuff here, which we re-check below */
353	353
354		− spin_lock_irqsave(&vcpu->arch.vgic_cpu.ap_list_lock, flags);
355		− spin_lock(&irq->irq_lock);
	354	+ raw_spin_lock_irqsave(&vcpu->arch.vgic_cpu.ap_list_lock, flags);
	355	+ raw_spin_lock(&irq->irq_lock);
356	356
357	357	/*
358	358	* Did something change behind our backs?
@@ -367,10 +367,11 @@ retry: · 8 unmodified lines
367	367	*/
368	368
369	369	if (unlikely(irq->vcpu \|\| vcpu != vgic_target_oracle(irq))) {
370		− spin_unlock(&irq->irq_lock);
371		− spin_unlock_irqrestore(&vcpu->arch.vgic_cpu.ap_list_lock, flags);
	370	+ raw_spin_unlock(&irq->irq_lock);
	371	+ raw_spin_unlock_irqrestore(&vcpu->arch.vgic_cpu.ap_list_lock,
	372	+ flags);
372	373
373		− spin_lock_irqsave(&irq->irq_lock, flags);
	374	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
374	375	goto retry;
375	376	}
376	377
@@ -382,8 +383,8 @@ retry: · 5 unmodified lines
382	383	list_add_tail(&irq->ap_list, &vcpu->arch.vgic_cpu.ap_list_head);
383	384	irq->vcpu = vcpu;
384	385
385		− spin_unlock(&irq->irq_lock);
386		− spin_unlock_irqrestore(&vcpu->arch.vgic_cpu.ap_list_lock, flags);
	386	+ raw_spin_unlock(&irq->irq_lock);
	387	+ raw_spin_unlock_irqrestore(&vcpu->arch.vgic_cpu.ap_list_lock, flags);
387	388
388	389	kvm_make_request(KVM_REQ_IRQ_PENDING, vcpu);
389	390	kvm_vcpu_kick(vcpu);
@@ -430,11 +431,11 @@ int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid, · 40 unmodified lines
430	431	if (!irq)
431	432	return -EINVAL;
432	433
433		− spin_lock_irqsave(&irq->irq_lock, flags);
	434	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
434	435
435	436	if (!vgic_validate_injection(irq, level, owner)) {
436	437	/* Nothing to see here, move along... */
437		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	438	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
438	439	vgic_put_irq(kvm, irq);
439	440	return 0;
440	441	}
@@ -494,9 +495,9 @@ int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq, · 53 unmodified lines
494	495
495	496	BUG_ON(!irq);
496	497
497		− spin_lock_irqsave(&irq->irq_lock, flags);
	498	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
498	499	ret = kvm_vgic_map_irq(vcpu, irq, host_irq, get_input_level);
499		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	500	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
500	501	vgic_put_irq(vcpu->kvm, irq);
501	502
502	503	return ret;
@@ -519,11 +520,11 @@ void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid) · 16 unmodified lines
519	520	if (!irq->hw)
520	521	goto out;
521	522
522		− spin_lock_irqsave(&irq->irq_lock, flags);
	523	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
523	524	irq->active = false;
524	525	irq->pending_latch = false;
525	526	irq->line_level = false;
526		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	527	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
527	528	out:
528	529	vgic_put_irq(vcpu->kvm, irq);
529	530	}
@@ -539,9 +540,9 @@ int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid) · 9 unmodified lines
539	540	irq = vgic_get_irq(vcpu->kvm, vcpu, vintid);
540	541	BUG_ON(!irq);
541	542
542		− spin_lock_irqsave(&irq->irq_lock, flags);
	543	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
543	544	kvm_vgic_unmap_irq(irq);
544		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	545	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
545	546	vgic_put_irq(vcpu->kvm, irq);
546	547
547	548	return 0;
@@ -571,12 +572,12 @@ int kvm_vgic_set_owner(struct kvm_vcpu vcpu, unsigned int intid, void owner) · 23 unmodified lines
571	572	return -EINVAL;
572	573
573	574	irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
574		− spin_lock_irqsave(&irq->irq_lock, flags);
	575	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
575	576	if (irq->owner && irq->owner != owner)
576	577	ret = -EEXIST;
577	578	else
578	579	irq->owner = owner;
579		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	580	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
580	581
581	582	return ret;
582	583	}
@@ -597,13 +598,13 @@ static void vgic_prune_ap_list(struct kvm_vcpu *vcpu) · 14 unmodified lines
597	598	DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
598	599
599	600	retry:
600		− spin_lock(&vgic_cpu->ap_list_lock);
	601	+ raw_spin_lock(&vgic_cpu->ap_list_lock);
601	602
602	603	list_for_each_entry_safe(irq, tmp, &vgic_cpu->ap_list_head, ap_list) {
603	604	struct kvm_vcpu target_vcpu, vcpuA, *vcpuB;
604	605	bool target_vcpu_needs_kick = false;
605	606
606		− spin_lock(&irq->irq_lock);
	607	+ raw_spin_lock(&irq->irq_lock);
607	608
608	609	BUG_ON(vcpu != irq->vcpu);
609	610
@@ -616,7 +617,7 @@ retry: · 6 unmodified lines
616	617	*/
617	618	list_del(&irq->ap_list);
618	619	irq->vcpu = NULL;
619		− spin_unlock(&irq->irq_lock);
	620	+ raw_spin_unlock(&irq->irq_lock);
620	621
621	622	/*
622	623	* This vgic_put_irq call matches the
@@ -631,14 +632,14 @@ retry: · 8 unmodified lines
631	632
632	633	if (target_vcpu == vcpu) {
633	634	/* We're on the right CPU */
634		− spin_unlock(&irq->irq_lock);
	635	+ raw_spin_unlock(&irq->irq_lock);
635	636	continue;
636	637	}
637	638
638	639	/* This interrupt looks like it has to be migrated. */
639	640
640		− spin_unlock(&irq->irq_lock);
641		− spin_unlock(&vgic_cpu->ap_list_lock);
	641	+ raw_spin_unlock(&irq->irq_lock);
	642	+ raw_spin_unlock(&vgic_cpu->ap_list_lock);
642	643
643	644	/*
644	645	* Ensure locking order by always locking the smallest
@@ -652,10 +653,10 @@ retry: · 7 unmodified lines
652	653	vcpuB = vcpu;
653	654	}
654	655
655		− spin_lock(&vcpuA->arch.vgic_cpu.ap_list_lock);
656		− spin_lock_nested(&vcpuB->arch.vgic_cpu.ap_list_lock,
657		− SINGLE_DEPTH_NESTING);
658		− spin_lock(&irq->irq_lock);
	656	+ raw_spin_lock(&vcpuA->arch.vgic_cpu.ap_list_lock);
	657	+ raw_spin_lock_nested(&vcpuB->arch.vgic_cpu.ap_list_lock,
	658	+ SINGLE_DEPTH_NESTING);
	659	+ raw_spin_lock(&irq->irq_lock);
659	660
660	661	/*
661	662	* If the affinity has been preserved, move the
@@ -675,9 +676,9 @@ retry: · 13 unmodified lines
675	676	target_vcpu_needs_kick = true;
676	677	}
677	678
678		− spin_unlock(&irq->irq_lock);
679		− spin_unlock(&vcpuB->arch.vgic_cpu.ap_list_lock);
680		− spin_unlock(&vcpuA->arch.vgic_cpu.ap_list_lock);
	679	+ raw_spin_unlock(&irq->irq_lock);
	680	+ raw_spin_unlock(&vcpuB->arch.vgic_cpu.ap_list_lock);
	681	+ raw_spin_unlock(&vcpuA->arch.vgic_cpu.ap_list_lock);
681	682
682	683	if (target_vcpu_needs_kick) {
683	684	kvm_make_request(KVM_REQ_IRQ_PENDING, target_vcpu);
@@ -687,7 +688,7 @@ retry: · 3 unmodified lines
687	688	goto retry;
688	689	}
689	690
690		− spin_unlock(&vgic_cpu->ap_list_lock);
	691	+ raw_spin_unlock(&vgic_cpu->ap_list_lock);
691	692	}
692	693
693	694	static inline void vgic_fold_lr_state(struct kvm_vcpu *vcpu)
@@ -741,10 +742,10 @@ static int compute_ap_list_depth(struct kvm_vcpu *vcpu, · 47 unmodified lines
741	742	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
742	743	int w;
743	744
744		− spin_lock(&irq->irq_lock);
	745	+ raw_spin_lock(&irq->irq_lock);
745	746	/* GICv2 SGIs can count for more than one... */
746	747	w = vgic_irq_get_lr_count(irq);
747		− spin_unlock(&irq->irq_lock);
	748	+ raw_spin_unlock(&irq->irq_lock);
748	749
749	750	count += w;
750	751	*multi_sgi \|= (w > 1);
@@ -770,7 +771,7 @@ static void vgic_flush_lr_state(struct kvm_vcpu *vcpu) · 19 unmodified lines
770	771	count = 0;
771	772
772	773	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
773		− spin_lock(&irq->irq_lock);
	774	+ raw_spin_lock(&irq->irq_lock);
774	775
775	776	/*
776	777	* If we have multi-SGIs in the pipeline, we need to
@@ -780,7 +781,7 @@ static void vgic_flush_lr_state(struct kvm_vcpu *vcpu) · 3 unmodified lines
780	781	* the AP list has been sorted already.
781	782	*/
782	783	if (multi_sgi && irq->priority > prio) {
783		− spin_unlock(&irq->irq_lock);
	784	+ _raw_spin_unlock(&irq->irq_lock);
784	785	break;
785	786	}
786	787
@@ -791,7 +792,7 @@ static void vgic_flush_lr_state(struct kvm_vcpu *vcpu) · 4 unmodified lines
791	792	prio = irq->priority;
792	793	}
793	794
794		− spin_unlock(&irq->irq_lock);
	795	+ raw_spin_unlock(&irq->irq_lock);
795	796
796	797	if (count == kvm_vgic_global_state.nr_lr) {
797	798	if (!list_is_last(&irq->ap_list,
@@ -872,9 +873,9 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) · 74 unmodified lines
872	873
873	874	DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
874	875
875		− spin_lock(&vcpu->arch.vgic_cpu.ap_list_lock);
	876	+ raw_spin_lock(&vcpu->arch.vgic_cpu.ap_list_lock);
876	877	vgic_flush_lr_state(vcpu);
877		− spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
	878	+ raw_spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
878	879
879	880	if (can_access_vgic_from_kernel())
880	881	vgic_restore_state(vcpu);
@@ -918,20 +919,20 @@ int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) · 37 unmodified lines
918	919
919	920	vgic_get_vmcr(vcpu, &vmcr);
920	921
921		− spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags);
	922	+ raw_spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags);
922	923
923	924	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
924		− spin_lock(&irq->irq_lock);
	925	+ raw_spin_lock(&irq->irq_lock);
925	926	pending = irq_is_pending(irq) && irq->enabled &&
926	927	!irq->active &&
927	928	irq->priority < vmcr.pmr;
928		− spin_unlock(&irq->irq_lock);
	929	+ raw_spin_unlock(&irq->irq_lock);
929	930
930	931	if (pending)
931	932	break;
932	933	}
933	934
934		− spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags);
	935	+ raw_spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags);
935	936
936	937	return pending;
937	938	}
@@ -963,11 +964,10 @@ bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid) · 25 unmodified lines
963	964	return false;
964	965
965	966	irq = vgic_get_irq(vcpu->kvm, vcpu, vintid);
966		− spin_lock_irqsave(&irq->irq_lock, flags);
	967	+ raw_spin_lock_irqsave(&irq->irq_lock, flags);
967	968	map_is_active = irq->hw && irq->active;
968		− spin_unlock_irqrestore(&irq->irq_lock, flags);
	969	+ raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
969	970	vgic_put_irq(vcpu->kvm, irq);
970	971
971	972	return map_is_active;
972	973	}
973		−