History

Merge tag 'arc-4.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC udpates from Vineet Gupta: - updates for various platforms - boot log updates for upcoming HS48 family of cores (dual issue) * tag 'arc-4.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: [plat-hsdk]: Add reset controller node to manage ethernet reset ARC: [plat-hsdk]: Temporary fix to set CPU frequency to 1GHz ARC: fix allnoconfig build warning ARCv2: boot log: identify HS48 cores (dual issue) ARC: boot log: decontaminate ARCv2 ISA_CONFIG register arc: remove redundant UTS_MACHINE define in arch/arc/Makefile ARC: [plat-eznps] Update platform maintainer as Noam left ARC: [plat-hsdk] use actual clk driver to manage cpu clk ARC: [*defconfig] Reenable soft lock-up detector ARC: [plat-axs10x] sdio: Temporary fix of sdio ciu frequency ARC: [plat-hsdk] sdio: Temporary fix of sdio ciu frequency ARC: [plat-axs103] Add temporary quirk to reset ethernet IP

Linus Torvalds committed 9 years ago

Commit ed0f72f2 parents eab26ad ab8eb7d17 files · +130 −28Browse files

Unified · Split

17 files
  1. MAINTAINERS +2 −1
  2. arch/arc/Kconfig +1 −1
  3. arch/arc/Makefile +0 −2
  4. arch/arc/boot/dts/axs10x_mb.dtsi +8 −1
  5. arch/arc/boot/dts/hsdk.dts +29 −3
  6. arch/arc/configs/axs101_defconfig +1 −1
  7. arch/arc/configs/axs103_defconfig +1 −1
  8. arch/arc/configs/axs103_smp_defconfig +1 −1
  9. arch/arc/configs/haps_hs_smp_defconfig +1 −1
  10. arch/arc/configs/hsdk_defconfig +2 −1
  11. arch/arc/configs/vdk_hs38_defconfig +1 −1
  12. arch/arc/configs/vdk_hs38_smp_defconfig +1 −1
  13. arch/arc/include/asm/arcregs.h +6 −5
  14. arch/arc/kernel/setup.c +25 −7
  15. arch/arc/plat-axs10x/axs10x.c +7 −0
  16. arch/arc/plat-hsdk/Kconfig +2 −1
  17. arch/arc/plat-hsdk/platform.c +42 −0
MAINTAINERS+2−1
@@ -5259,7 +5259,8 @@ S: Maintained · 5258 unmodified lines
5259F: drivers/iommu/exynos-iommu.c5259F: drivers/iommu/exynos-iommu.c
5260 5260
5261EZchip NPS platform support5261EZchip NPS platform support
5262M: Noam Camus <noamc@ezchip.com>5262M: Elad Kanfi <eladkan@mellanox.com>
5263M: Vineet Gupta <vgupta@synopsys.com>
5263S: Supported5264S: Supported
5264F: arch/arc/plat-eznps5265F: arch/arc/plat-eznps
5265F: arch/arc/boot/dts/eznps.dts5266F: arch/arc/boot/dts/eznps.dts
arch/arc/Kconfig+1−1
@@ -24,7 +24,7 @@ config ARC · 23 unmodified lines
24 select GENERIC_SMP_IDLE_THREAD24 select GENERIC_SMP_IDLE_THREAD
25 select HAVE_ARCH_KGDB25 select HAVE_ARCH_KGDB
26 select HAVE_ARCH_TRACEHOOK26 select HAVE_ARCH_TRACEHOOK
27 select HAVE_FUTEX_CMPXCHG27 select HAVE_FUTEX_CMPXCHG if FUTEX
28 select HAVE_IOREMAP_PROT28 select HAVE_IOREMAP_PROT
29 select HAVE_KPROBES29 select HAVE_KPROBES
30 select HAVE_KRETPROBES30 select HAVE_KRETPROBES
arch/arc/Makefile+0−2
@@ -6,8 +6,6 @@ · 5 unmodified lines
6# published by the Free Software Foundation.6# published by the Free Software Foundation.
7#7#
8 8
9UTS_MACHINE := arc
10
11ifeq ($(CROSS_COMPILE),)9ifeq ($(CROSS_COMPILE),)
12ifndef CONFIG_CPU_BIG_ENDIAN10ifndef CONFIG_CPU_BIG_ENDIAN
13CROSS_COMPILE := arc-linux-11CROSS_COMPILE := arc-linux-
arch/arc/boot/dts/axs10x_mb.dtsi+8−1
@@ -44,7 +44,14 @@ · 43 unmodified lines
44 44
45 mmcclk: mmcclk {45 mmcclk: mmcclk {
46 compatible = "fixed-clock";46 compatible = "fixed-clock";
47 clock-frequency = <50000000>;47 /*
48 * DW sdio controller has external ciu clock divider
49 * controlled via register in SDIO IP. It divides
50 * sdio_ref_clk (which comes from CGU) by 16 for
51 * default. So default mmcclk clock (which comes
52 * to sdk_in) is 25000000 Hz.
53 */
54 clock-frequency = <25000000>;
48 #clock-cells = <0>;55 #clock-cells = <0>;
49 };56 };
50 57
arch/arc/boot/dts/hsdk.dts+29−3
@@ -12,6 +12,7 @@ · 11 unmodified lines
12/dts-v1/;12/dts-v1/;
13 13
14#include <dt-bindings/net/ti-dp83867.h>14#include <dt-bindings/net/ti-dp83867.h>
15#include <dt-bindings/reset/snps,hsdk-reset.h>
15 16
16/ {17/ {
17 model = "snps,hsdk";18 model = "snps,hsdk";
@@ -57,10 +58,10 @@ · 39 unmodified lines
57 };58 };
58 };59 };
59 60
60 core_clk: core-clk {61 input_clk: input-clk {
61 #clock-cells = <0>;62 #clock-cells = <0>;
62 compatible = "fixed-clock";63 compatible = "fixed-clock";
63 clock-frequency = <500000000>;64 clock-frequency = <33333333>;
64 };65 };
65 66
66 cpu_intc: cpu-interrupt-controller {67 cpu_intc: cpu-interrupt-controller {
@@ -102,6 +103,19 @@ · 35 unmodified lines
102 103
103 ranges = <0x00000000 0xf0000000 0x10000000>;104 ranges = <0x00000000 0xf0000000 0x10000000>;
104 105
106 cgu_rst: reset-controller@8a0 {
107 compatible = "snps,hsdk-reset";
108 #reset-cells = <1>;
109 reg = <0x8A0 0x4>, <0xFF0 0x4>;
110 };
111
112 core_clk: core-clk@0 {
113 compatible = "snps,hsdk-core-pll-clock";
114 reg = <0x00 0x10>, <0x14B8 0x4>;
115 #clock-cells = <0>;
116 clocks = <&input_clk>;
117 };
118
105 serial: serial@5000 {119 serial: serial@5000 {
106 compatible = "snps,dw-apb-uart";120 compatible = "snps,dw-apb-uart";
107 reg = <0x5000 0x100>;121 reg = <0x5000 0x100>;
@@ -120,7 +134,17 @@ · 12 unmodified lines
120 134
121 mmcclk_ciu: mmcclk-ciu {135 mmcclk_ciu: mmcclk-ciu {
122 compatible = "fixed-clock";136 compatible = "fixed-clock";
123 clock-frequency = <100000000>;137 /*
138 * DW sdio controller has external ciu clock divider
139 * controlled via register in SDIO IP. Due to its
140 * unexpected default value (it should devide by 1
141 * but it devides by 8) SDIO IP uses wrong clock and
142 * works unstable (see STAR 9001204800)
143 * So add temporary fix and change clock frequency
144 * from 100000000 to 12500000 Hz until we fix dw sdio
145 * driver itself.
146 */
147 clock-frequency = <12500000>;
124 #clock-cells = <0>;148 #clock-cells = <0>;
125 };149 };
126 150
@@ -141,6 +165,8 @@ · 14 unmodified lines
141 clocks = <&gmacclk>;165 clocks = <&gmacclk>;
142 clock-names = "stmmaceth";166 clock-names = "stmmaceth";
143 phy-handle = <&phy0>;167 phy-handle = <&phy0>;
168 resets = <&cgu_rst HSDK_ETH_RESET>;
169 reset-names = "stmmaceth";
144 170
145 mdio {171 mdio {
146 #address-cells = <1>;172 #address-cells = <1>;
arch/arc/configs/axs101_defconfig+1−1
@@ -105,7 +105,7 @@ CONFIG_NLS_ISO8859_1=y · 104 unmodified lines
105# CONFIG_ENABLE_WARN_DEPRECATED is not set105# CONFIG_ENABLE_WARN_DEPRECATED is not set
106# CONFIG_ENABLE_MUST_CHECK is not set106# CONFIG_ENABLE_MUST_CHECK is not set
107CONFIG_STRIP_ASM_SYMS=y107CONFIG_STRIP_ASM_SYMS=y
108CONFIG_LOCKUP_DETECTOR=y108CONFIG_SOFTLOCKUP_DETECTOR=y
109CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10109CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
110# CONFIG_SCHED_DEBUG is not set110# CONFIG_SCHED_DEBUG is not set
111# CONFIG_DEBUG_PREEMPT is not set111# CONFIG_DEBUG_PREEMPT is not set
arch/arc/configs/axs103_defconfig+1−1
@@ -104,7 +104,7 @@ CONFIG_NLS_ISO8859_1=y · 103 unmodified lines
104# CONFIG_ENABLE_WARN_DEPRECATED is not set104# CONFIG_ENABLE_WARN_DEPRECATED is not set
105# CONFIG_ENABLE_MUST_CHECK is not set105# CONFIG_ENABLE_MUST_CHECK is not set
106CONFIG_STRIP_ASM_SYMS=y106CONFIG_STRIP_ASM_SYMS=y
107CONFIG_LOCKUP_DETECTOR=y107CONFIG_SOFTLOCKUP_DETECTOR=y
108CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10108CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
109# CONFIG_SCHED_DEBUG is not set109# CONFIG_SCHED_DEBUG is not set
110# CONFIG_DEBUG_PREEMPT is not set110# CONFIG_DEBUG_PREEMPT is not set
arch/arc/configs/axs103_smp_defconfig+1−1
@@ -107,7 +107,7 @@ CONFIG_NLS_ISO8859_1=y · 106 unmodified lines
107# CONFIG_ENABLE_WARN_DEPRECATED is not set107# CONFIG_ENABLE_WARN_DEPRECATED is not set
108# CONFIG_ENABLE_MUST_CHECK is not set108# CONFIG_ENABLE_MUST_CHECK is not set
109CONFIG_STRIP_ASM_SYMS=y109CONFIG_STRIP_ASM_SYMS=y
110CONFIG_LOCKUP_DETECTOR=y110CONFIG_SOFTLOCKUP_DETECTOR=y
111CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10111CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
112# CONFIG_SCHED_DEBUG is not set112# CONFIG_SCHED_DEBUG is not set
113# CONFIG_DEBUG_PREEMPT is not set113# CONFIG_DEBUG_PREEMPT is not set
arch/arc/configs/haps_hs_smp_defconfig+1−1
@@ -84,5 +84,5 @@ CONFIG_TMPFS=y · 83 unmodified lines
84CONFIG_NFS_FS=y84CONFIG_NFS_FS=y
85# CONFIG_ENABLE_WARN_DEPRECATED is not set85# CONFIG_ENABLE_WARN_DEPRECATED is not set
86# CONFIG_ENABLE_MUST_CHECK is not set86# CONFIG_ENABLE_MUST_CHECK is not set
87CONFIG_LOCKUP_DETECTOR=y87CONFIG_SOFTLOCKUP_DETECTOR=y
88# CONFIG_DEBUG_PREEMPT is not set88# CONFIG_DEBUG_PREEMPT is not set
arch/arc/configs/hsdk_defconfig+2−1
@@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI=y · 62 unmodified lines
63CONFIG_MMC_SDHCI_PLTFM=y63CONFIG_MMC_SDHCI_PLTFM=y
64CONFIG_MMC_DW=y64CONFIG_MMC_DW=y
65# CONFIG_IOMMU_SUPPORT is not set65# CONFIG_IOMMU_SUPPORT is not set
66CONFIG_RESET_HSDK=y
66CONFIG_EXT3_FS=y67CONFIG_EXT3_FS=y
67CONFIG_VFAT_FS=y68CONFIG_VFAT_FS=y
68CONFIG_TMPFS=y69CONFIG_TMPFS=y
@@ -72,7 +73,7 @@ CONFIG_NLS_ISO8859_1=y · 3 unmodified lines
72# CONFIG_ENABLE_WARN_DEPRECATED is not set73# CONFIG_ENABLE_WARN_DEPRECATED is not set
73# CONFIG_ENABLE_MUST_CHECK is not set74# CONFIG_ENABLE_MUST_CHECK is not set
74CONFIG_STRIP_ASM_SYMS=y75CONFIG_STRIP_ASM_SYMS=y
75CONFIG_LOCKUP_DETECTOR=y76CONFIG_SOFTLOCKUP_DETECTOR=y
76CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=1077CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
77# CONFIG_SCHED_DEBUG is not set78# CONFIG_SCHED_DEBUG is not set
78# CONFIG_DEBUG_PREEMPT is not set79# CONFIG_DEBUG_PREEMPT is not set
arch/arc/configs/vdk_hs38_defconfig+1−1
@@ -94,7 +94,7 @@ CONFIG_NLS_ISO8859_1=y · 93 unmodified lines
94# CONFIG_ENABLE_MUST_CHECK is not set94# CONFIG_ENABLE_MUST_CHECK is not set
95CONFIG_STRIP_ASM_SYMS=y95CONFIG_STRIP_ASM_SYMS=y
96CONFIG_DEBUG_SHIRQ=y96CONFIG_DEBUG_SHIRQ=y
97CONFIG_LOCKUP_DETECTOR=y97CONFIG_SOFTLOCKUP_DETECTOR=y
98CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=1098CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
99# CONFIG_SCHED_DEBUG is not set99# CONFIG_SCHED_DEBUG is not set
100# CONFIG_DEBUG_PREEMPT is not set100# CONFIG_DEBUG_PREEMPT is not set
arch/arc/configs/vdk_hs38_smp_defconfig+1−1
@@ -98,7 +98,7 @@ CONFIG_NLS_ISO8859_1=y · 97 unmodified lines
98# CONFIG_ENABLE_MUST_CHECK is not set98# CONFIG_ENABLE_MUST_CHECK is not set
99CONFIG_STRIP_ASM_SYMS=y99CONFIG_STRIP_ASM_SYMS=y
100CONFIG_DEBUG_SHIRQ=y100CONFIG_DEBUG_SHIRQ=y
101CONFIG_LOCKUP_DETECTOR=y101CONFIG_SOFTLOCKUP_DETECTOR=y
102CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10102CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
103# CONFIG_SCHED_DEBUG is not set103# CONFIG_SCHED_DEBUG is not set
104# CONFIG_DEBUG_PREEMPT is not set104# CONFIG_DEBUG_PREEMPT is not set
arch/arc/include/asm/arcregs.h+6−5
@@ -98,6 +98,7 @@ · 97 unmodified lines
98 98
99/* Auxiliary registers */99/* Auxiliary registers */
100#define AUX_IDENTITY 4100#define AUX_IDENTITY 4
101#define AUX_EXEC_CTRL 8
101#define AUX_INTR_VEC_BASE 0x25102#define AUX_INTR_VEC_BASE 0x25
102#define AUX_VOL 0x5e103#define AUX_VOL 0x5e
103 104
@@ -135,12 +136,12 @@ struct bcr_identity { · 31 unmodified lines
135#endif136#endif
136};137};
137 138
138struct bcr_isa {139struct bcr_isa_arcv2 {
139#ifdef CONFIG_CPU_BIG_ENDIAN140#ifdef CONFIG_CPU_BIG_ENDIAN
140 unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,141 unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
141 pad1:11, atomic1:1, ver:8;142 pad1:12, ver:8;
142#else143#else
143 unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,144 unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
144 ldd:1, pad2:4, div_rem:4;145 ldd:1, pad2:4, div_rem:4;
145#endif146#endif
146};147};
@@ -263,13 +264,13 @@ struct cpuinfo_arc { · 116 unmodified lines
263 struct cpuinfo_arc_mmu mmu;264 struct cpuinfo_arc_mmu mmu;
264 struct cpuinfo_arc_bpu bpu;265 struct cpuinfo_arc_bpu bpu;
265 struct bcr_identity core;266 struct bcr_identity core;
266 struct bcr_isa isa;267 struct bcr_isa_arcv2 isa;
267 const char *details, *name;268 const char *details, *name;
268 unsigned int vec_base;269 unsigned int vec_base;
269 struct cpuinfo_arc_ccm iccm, dccm;270 struct cpuinfo_arc_ccm iccm, dccm;
270 struct {271 struct {
271 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,272 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
272 fpu_sp:1, fpu_dp:1, pad2:6,273 fpu_sp:1, fpu_dp:1, dual_iss_enb:1, dual_iss_exist:1, pad2:4,
273 debug:1, ap:1, smart:1, rtt:1, pad3:4,274 debug:1, ap:1, smart:1, rtt:1, pad3:4,
274 timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;275 timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
275 } extn;276 } extn;
arch/arc/kernel/setup.c+25−7
@@ -51,6 +51,7 @@ static const struct id_to_str arc_cpu_rel[] = { · 50 unmodified lines
51 { 0x51, "R2.0" },51 { 0x51, "R2.0" },
52 { 0x52, "R2.1" },52 { 0x52, "R2.1" },
53 { 0x53, "R3.0" },53 { 0x53, "R3.0" },
54 { 0x54, "R4.0" },
54#endif55#endif
55 { 0x00, NULL }56 { 0x00, NULL }
56};57};
@@ -62,6 +63,7 @@ static const struct id_to_str arc_cpu_nm[] = { · 5 unmodified lines
62#else63#else
63 { 0x40, "ARC EM" },64 { 0x40, "ARC EM" },
64 { 0x50, "ARC HS38" },65 { 0x50, "ARC HS38" },
66 { 0x54, "ARC HS48" },
65#endif67#endif
66 { 0x00, "Unknown" }68 { 0x00, "Unknown" }
67};69};
@@ -119,11 +121,11 @@ static void read_arc_build_cfg_regs(void) · 51 unmodified lines
119 struct bcr_generic bcr;121 struct bcr_generic bcr;
120 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];122 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
121 const struct id_to_str *tbl;123 const struct id_to_str *tbl;
124 struct bcr_isa_arcv2 isa;
122 125
123 FIX_PTR(cpu);126 FIX_PTR(cpu);
124 127
125 READ_BCR(AUX_IDENTITY, cpu->core);128 READ_BCR(AUX_IDENTITY, cpu->core);
126 READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
127 129
128 for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) {130 for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) {
129 if (cpu->core.family == tbl->id) {131 if (cpu->core.family == tbl->id) {
@@ -133,7 +135,7 @@ static void read_arc_build_cfg_regs(void) · 3 unmodified lines
133 }135 }
134 136
135 for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) {137 for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) {
136 if ((cpu->core.family & 0xF0) == tbl->id)138 if ((cpu->core.family & 0xF4) == tbl->id)
137 break;139 break;
138 }140 }
139 cpu->name = tbl->str;141 cpu->name = tbl->str;
@@ -192,6 +194,14 @@ static void read_arc_build_cfg_regs(void) · 52 unmodified lines
192 cpu->bpu.full = bpu.ft;194 cpu->bpu.full = bpu.ft;
193 cpu->bpu.num_cache = 256 << bpu.bce;195 cpu->bpu.num_cache = 256 << bpu.bce;
194 cpu->bpu.num_pred = 2048 << bpu.pte;196 cpu->bpu.num_pred = 2048 << bpu.pte;
197
198 if (cpu->core.family >= 0x54) {
199 unsigned int exec_ctrl;
200
201 READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
202 cpu->extn.dual_iss_exist = 1;
203 cpu->extn.dual_iss_enb = exec_ctrl & 1;
204 }
195 }205 }
196 206
197 READ_BCR(ARC_REG_AP_BCR, bcr);207 READ_BCR(ARC_REG_AP_BCR, bcr);
@@ -205,18 +215,25 @@ static void read_arc_build_cfg_regs(void) · 7 unmodified lines
205 215
206 cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;216 cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;
207 217
218 READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
219
208 /* some hacks for lack of feature BCR info in old ARC700 cores */220 /* some hacks for lack of feature BCR info in old ARC700 cores */
209 if (is_isa_arcompact()) {221 if (is_isa_arcompact()) {
210 if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */222 if (!isa.ver) /* ISA BCR absent, use Kconfig info */
211 cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);223 cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
212 else224 else {
213 cpu->isa.atomic = cpu->isa.atomic1;225 /* ARC700_BUILD only has 2 bits of isa info */
226 struct bcr_generic bcr = *(struct bcr_generic *)&isa;
227 cpu->isa.atomic = bcr.info & 1;
228 }
214 229
215 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);230 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
216 231
217 /* there's no direct way to distinguish 750 vs. 770 */232 /* there's no direct way to distinguish 750 vs. 770 */
218 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))233 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
219 cpu->name = "ARC750";234 cpu->name = "ARC750";
235 } else {
236 cpu->isa = isa;
220 }237 }
221}238}
222 239
@@ -232,10 +249,11 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) · 9 unmodified lines
232 "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",249 "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
233 core->family, core->cpu_id, core->chip_id);250 core->family, core->cpu_id, core->chip_id);
234 251
235 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s\n",252 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
236 cpu_id, cpu->name, cpu->details,253 cpu_id, cpu->name, cpu->details,
237 is_isa_arcompact() ? "ARCompact" : "ARCv2",254 is_isa_arcompact() ? "ARCompact" : "ARCv2",
238 IS_AVAIL1(cpu->isa.be, "[Big-Endian]"));255 IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
256 IS_AVAIL3(cpu->extn.dual_iss_exist, cpu->extn.dual_iss_enb, " Dual-Issue"));
239 257
240 n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",258 n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
241 IS_AVAIL1(cpu->extn.timer0, "Timer0 "),259 IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
arch/arc/plat-axs10x/axs10x.c+7−0
@@ -111,6 +111,13 @@ static void __init axs10x_early_init(void) · 110 unmodified lines
111 111
112 axs10x_enable_gpio_intc_wire();112 axs10x_enable_gpio_intc_wire();
113 113
114 /*
115 * Reset ethernet IP core.
116 * TODO: get rid of this quirk after axs10x reset driver (or simple
117 * reset driver) will be available in upstream.
118 */
119 iowrite32((1 << 5), (void __iomem *) CREG_MB_SW_RESET);
120
114 scnprintf(mb, 32, "MainBoard v%d", mb_rev);121 scnprintf(mb, 32, "MainBoard v%d", mb_rev);
115 axs10x_print_board_ver(CREG_MB_VER, mb);122 axs10x_print_board_ver(CREG_MB_VER, mb);
116}123}
arch/arc/plat-hsdk/Kconfig+2−1
@@ -6,4 +6,5 @@ · 5 unmodified lines
6#6#
7 7
8menuconfig ARC_SOC_HSDK8menuconfig ARC_SOC_HSDK
9 bool "ARC HS Development Kit SOC"9 bool "ARC HS Development Kit SOC"
10 select CLK_HSDK
arch/arc/plat-hsdk/platform.c+42−0
@@ -38,6 +38,42 @@ static void __init hsdk_init_per_cpu(unsigned int cpu) · 37 unmodified lines
38#define CREG_PAE (CREG_BASE + 0x180)38#define CREG_PAE (CREG_BASE + 0x180)
39#define CREG_PAE_UPDATE (CREG_BASE + 0x194)39#define CREG_PAE_UPDATE (CREG_BASE + 0x194)
40 40
41#define CREG_CORE_IF_CLK_DIV (CREG_BASE + 0x4B8)
42#define CREG_CORE_IF_CLK_DIV_2 0x1
43#define CGU_BASE ARC_PERIPHERAL_BASE
44#define CGU_PLL_STATUS (ARC_PERIPHERAL_BASE + 0x4)
45#define CGU_PLL_CTRL (ARC_PERIPHERAL_BASE + 0x0)
46#define CGU_PLL_STATUS_LOCK BIT(0)
47#define CGU_PLL_STATUS_ERR BIT(1)
48#define CGU_PLL_CTRL_1GHZ 0x3A10
49#define HSDK_PLL_LOCK_TIMEOUT 500
50
51#define HSDK_PLL_LOCKED() \
52 !!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK)
53
54#define HSDK_PLL_ERR() \
55 !!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR)
56
57static void __init hsdk_set_cpu_freq_1ghz(void)
58{
59 u32 timeout = HSDK_PLL_LOCK_TIMEOUT;
60
61 /*
62 * As we set cpu clock which exceeds 500MHz, the divider for the interface
63 * clock must be programmed to div-by-2.
64 */
65 iowrite32(CREG_CORE_IF_CLK_DIV_2, (void __iomem *) CREG_CORE_IF_CLK_DIV);
66
67 /* Set cpu clock to 1GHz */
68 iowrite32(CGU_PLL_CTRL_1GHZ, (void __iomem *) CGU_PLL_CTRL);
69
70 while (!HSDK_PLL_LOCKED() && timeout--)
71 cpu_relax();
72
73 if (!HSDK_PLL_LOCKED() || HSDK_PLL_ERR())
74 pr_err("Failed to setup CPU frequency to 1GHz!");
75}
76
41static void __init hsdk_init_early(void)77static void __init hsdk_init_early(void)
42{78{
43 /*79 /*
@@ -52,6 +88,12 @@ static void __init hsdk_init_early(void) · 8 unmodified lines
52 88
53 /* Really apply settings made above */89 /* Really apply settings made above */
54 writel(1, (void __iomem *) CREG_PAE_UPDATE);90 writel(1, (void __iomem *) CREG_PAE_UPDATE);
91
92 /*
93 * Setup CPU frequency to 1GHz.
94 * TODO: remove it after smart hsdk pll driver will be introduced.
95 */
96 hsdk_set_cpu_freq_1ghz();
55}97}
56 98
57static const char *hsdk_compat[] __initconst = {99static const char *hsdk_compat[] __initconst = {

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