Convert the mscc-miim device tree binding to the new YAML format. The original binding don't mention if the interrupt property is optional or not. But on the SparX-5 SoC, for example, the interrupt property isn't used, thus in the new binding that property is optional. FWIW the driver doesn't use interrupts at all.
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| 1 | +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | |
| 2 | +%YAML 1.2 | |
| 3 | +--- | |
| 4 | +$id: http://devicetree.org/schemas/net/mscc,miim.yaml# | |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | + | |
| 7 | +title: Microsemi MII Management Controller (MIIM) | |
| 8 | + | |
| 9 | +maintainers: | |
| 10 | + - Alexandre Belloni <alexandre.belloni@bootlin.com> | |
| 11 | + | |
| 12 | +allOf: | |
| 13 | + - $ref: "mdio.yaml#" | |
| 14 | + | |
| 15 | +properties: | |
| 16 | + compatible: | |
| 17 | + enum: | |
| 18 | + - mscc,ocelot-miim | |
| 19 | + - microchip,lan966x-miim | |
| 20 | + | |
| 21 | + "#address-cells": | |
| 22 | + const: 1 | |
| 23 | + | |
| 24 | + "#size-cells": | |
| 25 | + const: 0 | |
| 26 | + | |
| 27 | + reg: | |
| 28 | + items: | |
| 29 | + - description: base address | |
| 30 | + - description: associated reset register for internal PHYs | |
| 31 | + minItems: 1 | |
| 32 | + | |
| 33 | + interrupts: | |
| 34 | + maxItems: 1 | |
| 35 | + | |
| 36 | +required: | |
| 37 | + - compatible | |
| 38 | + - reg | |
| 39 | + - "#address-cells" | |
| 40 | + - "#size-cells" | |
| 41 | + | |
| 42 | +unevaluatedProperties: false | |
| 43 | + | |
| 44 | +examples: | |
| 45 | + - | | |
| 46 | + mdio@107009c { | |
| 47 | + compatible = "mscc,ocelot-miim"; | |
| 48 | + reg = <0x107009c 0x36>, <0x10700f0 0x8>; | |
| 49 | + interrupts = <14>; | |
| 50 | + #address-cells = <1>; | |
| 51 | + #size-cells = <0>; | |
| 52 | + | |
| 53 | + phy0: ethernet-phy@0 { | |
| 54 | + reg = <0>; | |
| 55 | + }; | |
| 56 | + }; | |
| @@ -1,26 +0,0 @@ | ||
| 1 | −Microsemi MII Management Controller (MIIM) / MDIO | |
| 2 | −================================================= | |
| 3 | − | |
| 4 | −Properties: | |
| 5 | −- compatible: must be "mscc,ocelot-miim" or "microchip,lan966x-miim" | |
| 6 | −- reg: The base address of the MDIO bus controller register bank. Optionally, a | |
| 7 | − second register bank can be defined if there is an associated reset register | |
| 8 | − for internal PHYs | |
| 9 | −- #address-cells: Must be <1>. | |
| 10 | −- #size-cells: Must be <0>. MDIO addresses have no size component. | |
| 11 | −- interrupts: interrupt specifier (refer to the interrupt binding) | |
| 12 | − | |
| 13 | −Typically an MDIO bus might have several children. | |
| 14 | − | |
| 15 | −Example: | |
| 16 | − mdio@107009c { | |
| 17 | − #address-cells = <1>; | |
| 18 | − #size-cells = <0>; | |
| 19 | − compatible = "mscc,ocelot-miim"; | |
| 20 | − reg = <0x107009c 0x36>, <0x10700f0 0x8>; | |
| 21 | − interrupts = <14>; | |
| 22 | − | |
| 23 | − phy0: ethernet-phy@0 { | |
| 24 | − reg = <0>; | |
| 25 | − }; | |
| 26 | − }; | |