History

Merge branch 'mellanox/mlx5-next' into rdma.git for-next

From git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux.git This is required to resolve dependencies of the next series of RDMA patches. * branch 'mellanox/mlx5-next': net/mlx5: Add support for flow table destination number net/mlx5: Add forward compatible support for the FTE match data net/mlx5: Fix tristate and description for MLX5 module net/mlx5: Better return types for CQE API net/mlx5: Use ERR_CAST() instead of coding it net/mlx5: Add missing SET_DRIVER_VERSION command translation net/mlx5: Add XRQ commands definitions net/mlx5: Add core support for double vlan push/pop steering action net/mlx5: Expose MPEGC (Management PCIe General Configuration) structures net/mlx5: FW tracer, add hardware structures net/mlx5: fix uaccess beyond "count" in debugfs read/write handlers

Jason Gunthorpe committed 8 years ago

Commit eda98772 parents 4fca037 664000b14 files · +166 −149Browse files

Unified · Split

14 files
  1. drivers/infiniband/hw/mlx5/Kconfig +1 −1
  2. drivers/net/ethernet/mellanox/mlx5/core/Kconfig +3 −3
  3. drivers/net/ethernet/mellanox/mlx5/core/cmd.c +16 −21
  4. drivers/net/ethernet/mellanox/mlx5/core/debugfs.c +2 −20
  5. drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c +3 −0
  6. drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h +2 −0
  7. drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +3 −3
  8. drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c +24 −12
  9. drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +8 −79
  10. drivers/net/ethernet/mellanox/mlx5/core/main.c +1 −1
  11. include/linux/mlx5/device.h +4 −4
  12. include/linux/mlx5/driver.h +5 −0
  13. include/linux/mlx5/fs.h +4 −1
  14. include/linux/mlx5/mlx5_ifc.h +90 −4
drivers/infiniband/hw/mlx5/Kconfig+1−1
@@ -1,5 +1,5 @@
1config MLX5_INFINIBAND1config MLX5_INFINIBAND
2 tristate "Mellanox Connect-IB HCA support"2 tristate "Mellanox 5th generation network adapters (ConnectX series) support"
3 depends on NETDEVICES && ETHERNET && PCI && MLX5_CORE3 depends on NETDEVICES && ETHERNET && PCI && MLX5_CORE
4 depends on INFINIBAND_USER_ACCESS || INFINIBAND_USER_ACCESS=n4 depends on INFINIBAND_USER_ACCESS || INFINIBAND_USER_ACCESS=n
5 ---help---5 ---help---
drivers/net/ethernet/mellanox/mlx5/core/Kconfig+3−3
@@ -3,7 +3,7 @@ · 2 unmodified lines
3#3#
4 4
5config MLX5_CORE5config MLX5_CORE
6 tristate "Mellanox Technologies ConnectX-4 and Connect-IB core driver"6 tristate "Mellanox 5th generation network adapters (ConnectX series) core driver"
7 depends on MAY_USE_DEVLINK7 depends on MAY_USE_DEVLINK
8 depends on PCI8 depends on PCI
9 imply PTP_1588_CLOCK9 imply PTP_1588_CLOCK
@@ -27,7 +27,7 @@ config MLX5_FPGA · 17 unmodified lines
27 sandbox-specific client drivers.27 sandbox-specific client drivers.
28 28
29config MLX5_CORE_EN29config MLX5_CORE_EN
30 bool "Mellanox Technologies ConnectX-4 Ethernet support"30 bool "Mellanox 5th generation network adapters (ConnectX series) Ethernet support"
31 depends on NETDEVICES && ETHERNET && INET && PCI && MLX5_CORE31 depends on NETDEVICES && ETHERNET && INET && PCI && MLX5_CORE
32 depends on IPV6=y || IPV6=n || MLX5_CORE=m32 depends on IPV6=y || IPV6=n || MLX5_CORE=m
33 select PAGE_POOL33 select PAGE_POOL
@@ -69,7 +69,7 @@ config MLX5_CORE_EN_DCB · 35 unmodified lines
69 If unsure, set to Y69 If unsure, set to Y
70 70
71config MLX5_CORE_IPOIB71config MLX5_CORE_IPOIB
72 bool "Mellanox Technologies ConnectX-4 IPoIB offloads support"72 bool "Mellanox 5th generation network adapters (connectX series) IPoIB offloads support"
73 depends on MLX5_CORE_EN73 depends on MLX5_CORE_EN
74 default n74 default n
75 ---help---75 ---help---
drivers/net/ethernet/mellanox/mlx5/core/cmd.c+16−21
@@ -278,6 +278,7 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op, · 277 unmodified lines
278 case MLX5_CMD_OP_DESTROY_PSV:278 case MLX5_CMD_OP_DESTROY_PSV:
279 case MLX5_CMD_OP_DESTROY_SRQ:279 case MLX5_CMD_OP_DESTROY_SRQ:
280 case MLX5_CMD_OP_DESTROY_XRC_SRQ:280 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
281 case MLX5_CMD_OP_DESTROY_XRQ:
281 case MLX5_CMD_OP_DESTROY_DCT:282 case MLX5_CMD_OP_DESTROY_DCT:
282 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:283 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
283 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:284 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
@@ -347,6 +348,9 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op, · 63 unmodified lines
347 case MLX5_CMD_OP_CREATE_XRC_SRQ:348 case MLX5_CMD_OP_CREATE_XRC_SRQ:
348 case MLX5_CMD_OP_QUERY_XRC_SRQ:349 case MLX5_CMD_OP_QUERY_XRC_SRQ:
349 case MLX5_CMD_OP_ARM_XRC_SRQ:350 case MLX5_CMD_OP_ARM_XRC_SRQ:
351 case MLX5_CMD_OP_CREATE_XRQ:
352 case MLX5_CMD_OP_QUERY_XRQ:
353 case MLX5_CMD_OP_ARM_XRQ:
350 case MLX5_CMD_OP_CREATE_DCT:354 case MLX5_CMD_OP_CREATE_DCT:
351 case MLX5_CMD_OP_DRAIN_DCT:355 case MLX5_CMD_OP_DRAIN_DCT:
352 case MLX5_CMD_OP_QUERY_DCT:356 case MLX5_CMD_OP_QUERY_DCT:
@@ -456,6 +460,7 @@ const char *mlx5_command_str(int command) · 103 unmodified lines
456 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);460 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
457 MLX5_COMMAND_STR_CASE(QUERY_ISSI);461 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
458 MLX5_COMMAND_STR_CASE(SET_ISSI);462 MLX5_COMMAND_STR_CASE(SET_ISSI);
463 MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
459 MLX5_COMMAND_STR_CASE(CREATE_MKEY);464 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
460 MLX5_COMMAND_STR_CASE(QUERY_MKEY);465 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
461 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);466 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
@@ -603,6 +608,10 @@ const char *mlx5_command_str(int command) · 141 unmodified lines
603 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);608 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
604 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);609 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
605 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);610 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
611 MLX5_COMMAND_STR_CASE(CREATE_XRQ);
612 MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
613 MLX5_COMMAND_STR_CASE(QUERY_XRQ);
614 MLX5_COMMAND_STR_CASE(ARM_XRQ);
606 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);615 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
607 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);616 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
608 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);617 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
@@ -1037,7 +1046,10 @@ static ssize_t dbg_write(struct file *filp, const char __user *buf, · 428 unmodified lines
1037 if (!dbg->in_msg || !dbg->out_msg)1046 if (!dbg->in_msg || !dbg->out_msg)
1038 return -ENOMEM;1047 return -ENOMEM;
1039 1048
1040 if (copy_from_user(lbuf, buf, sizeof(lbuf)))1049 if (count < sizeof(lbuf) - 1)
1050 return -EINVAL;
1051
1052 if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1041 return -EFAULT;1053 return -EFAULT;
1042 1054
1043 lbuf[sizeof(lbuf) - 1] = 0;1055 lbuf[sizeof(lbuf) - 1] = 0;
@@ -1241,21 +1253,12 @@ static ssize_t data_read(struct file *filp, char __user *buf, size_t count, · 197 unmodified lines
1241{1253{
1242 struct mlx5_core_dev *dev = filp->private_data;1254 struct mlx5_core_dev *dev = filp->private_data;
1243 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;1255 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1244 int copy;
1245
1246 if (*pos)
1247 return 0;
1248 1256
1249 if (!dbg->out_msg)1257 if (!dbg->out_msg)
1250 return -ENOMEM;1258 return -ENOMEM;
1251 1259
1252 copy = min_t(int, count, dbg->outlen);1260 return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1253 if (copy_to_user(buf, dbg->out_msg, copy))1261 dbg->outlen);
1254 return -EFAULT;
1255
1256 *pos += copy;
1257
1258 return copy;
1259}1262}
1260 1263
1261static const struct file_operations dfops = {1264static const struct file_operations dfops = {
@@ -1273,19 +1276,11 @@ static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count, · 11 unmodified lines
1273 char outlen[8];1276 char outlen[8];
1274 int err;1277 int err;
1275 1278
1276 if (*pos)
1277 return 0;
1278
1279 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);1279 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1280 if (err < 0)1280 if (err < 0)
1281 return err;1281 return err;
1282 1282
1283 if (copy_to_user(buf, &outlen, err))1283 return simple_read_from_buffer(buf, count, pos, outlen, err);
1284 return -EFAULT;
1285
1286 *pos += err;
1287
1288 return err;
1289}1284}
1290 1285
1291static ssize_t outlen_write(struct file *filp, const char __user *buf,1286static ssize_t outlen_write(struct file *filp, const char __user *buf,
drivers/net/ethernet/mellanox/mlx5/core/debugfs.c+2−20
@@ -150,22 +150,13 @@ static ssize_t average_read(struct file *filp, char __user *buf, size_t count, · 149 unmodified lines
150 int ret;150 int ret;
151 char tbuf[22];151 char tbuf[22];
152 152
153 if (*pos)
154 return 0;
155
156 stats = filp->private_data;153 stats = filp->private_data;
157 spin_lock_irq(&stats->lock);154 spin_lock_irq(&stats->lock);
158 if (stats->n)155 if (stats->n)
159 field = div64_u64(stats->sum, stats->n);156 field = div64_u64(stats->sum, stats->n);
160 spin_unlock_irq(&stats->lock);157 spin_unlock_irq(&stats->lock);
161 ret = snprintf(tbuf, sizeof(tbuf), "%llu\n", field);158 ret = snprintf(tbuf, sizeof(tbuf), "%llu\n", field);
162 if (ret > 0) {159 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
163 if (copy_to_user(buf, tbuf, ret))
164 return -EFAULT;
165 }
166
167 *pos += ret;
168 return ret;
169}160}
170 161
171static ssize_t average_write(struct file *filp, const char __user *buf,162static ssize_t average_write(struct file *filp, const char __user *buf,
@@ -442,9 +433,6 @@ static ssize_t dbg_read(struct file *filp, char __user *buf, size_t count, · 270 unmodified lines
442 u64 field;433 u64 field;
443 int ret;434 int ret;
444 435
445 if (*pos)
446 return 0;
447
448 desc = filp->private_data;436 desc = filp->private_data;
449 d = (void *)(desc - desc->i) - sizeof(*d);437 d = (void *)(desc - desc->i) - sizeof(*d);
450 switch (d->type) {438 switch (d->type) {
@@ -470,13 +458,7 @@ static ssize_t dbg_read(struct file *filp, char __user *buf, size_t count, · 19 unmodified lines
470 else458 else
471 ret = snprintf(tbuf, sizeof(tbuf), "0x%llx\n", field);459 ret = snprintf(tbuf, sizeof(tbuf), "0x%llx\n", field);
472 460
473 if (ret > 0) {461 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
474 if (copy_to_user(buf, tbuf, ret))
475 return -EFAULT;
476 }
477
478 *pos += ret;
479 return ret;
480}462}
481 463
482static const struct file_operations fops = {464static const struct file_operations fops = {
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c+3−0
@@ -240,6 +240,9 @@ const char *parse_fs_dst(struct trace_seq *p, · 239 unmodified lines
240 case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE:240 case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE:
241 trace_seq_printf(p, "ft=%p\n", dst->ft);241 trace_seq_printf(p, "ft=%p\n", dst->ft);
242 break;242 break;
243 case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM:
244 trace_seq_printf(p, "ft_num=%u\n", dst->ft_num);
245 break;
243 case MLX5_FLOW_DESTINATION_TYPE_TIR:246 case MLX5_FLOW_DESTINATION_TYPE_TIR:
244 trace_seq_printf(p, "tir=%u\n", dst->tir_num);247 trace_seq_printf(p, "tir=%u\n", dst->tir_num);
245 break;248 break;
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h+2−0
@@ -138,6 +138,8 @@ TRACE_EVENT(mlx5_fs_del_fg, · 137 unmodified lines
138 {MLX5_FLOW_CONTEXT_ACTION_MOD_HDR, "MOD_HDR"},\138 {MLX5_FLOW_CONTEXT_ACTION_MOD_HDR, "MOD_HDR"},\
139 {MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH, "VLAN_PUSH"},\139 {MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH, "VLAN_PUSH"},\
140 {MLX5_FLOW_CONTEXT_ACTION_VLAN_POP, "VLAN_POP"},\140 {MLX5_FLOW_CONTEXT_ACTION_VLAN_POP, "VLAN_POP"},\
141 {MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2, "VLAN_PUSH_2"},\
142 {MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2, "VLAN_POP_2"},\
141 {MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO, "NEXT_PRIO"}143 {MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO, "NEXT_PRIO"}
142 144
143TRACE_EVENT(mlx5_fs_set_fte,145TRACE_EVENT(mlx5_fs_set_fte,
drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c+3−3
@@ -70,9 +70,9 @@ mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, · 69 unmodified lines
70 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |70 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
71 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);71 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
72 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {72 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
73 flow_act.vlan.ethtype = ntohs(attr->vlan_proto);73 flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto);
74 flow_act.vlan.vid = attr->vlan_vid;74 flow_act.vlan[0].vid = attr->vlan_vid;
75 flow_act.vlan.prio = attr->vlan_prio;75 flow_act.vlan[0].prio = attr->vlan_prio;
76 }76 }
77 77
78 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {78 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c+24−12
@@ -349,9 +349,15 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, · 348 unmodified lines
349 349
350 vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan);350 vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan);
351 351
352 MLX5_SET(vlan, vlan, ethtype, fte->action.vlan.ethtype);352 MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[0].ethtype);
353 MLX5_SET(vlan, vlan, vid, fte->action.vlan.vid);353 MLX5_SET(vlan, vlan, vid, fte->action.vlan[0].vid);
354 MLX5_SET(vlan, vlan, prio, fte->action.vlan.prio);354 MLX5_SET(vlan, vlan, prio, fte->action.vlan[0].prio);
355
356 vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan_2);
357
358 MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[1].ethtype);
359 MLX5_SET(vlan, vlan, vid, fte->action.vlan[1].vid);
360 MLX5_SET(vlan, vlan, prio, fte->action.vlan[1].prio);
355 361
356 in_match_value = MLX5_ADDR_OF(flow_context, in_flow_context,362 in_match_value = MLX5_ADDR_OF(flow_context, in_flow_context,
357 match_value);363 match_value);
@@ -362,18 +368,20 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, · 4 unmodified lines
362 int list_size = 0;368 int list_size = 0;
363 369
364 list_for_each_entry(dst, &fte->node.children, node.list) {370 list_for_each_entry(dst, &fte->node.children, node.list) {
365 unsigned int id;371 unsigned int id, type = dst->dest_attr.type;
366 372
367 if (dst->dest_attr.type == MLX5_FLOW_DESTINATION_TYPE_COUNTER)373 if (type == MLX5_FLOW_DESTINATION_TYPE_COUNTER)
368 continue;374 continue;
369 375
370 MLX5_SET(dest_format_struct, in_dests, destination_type,376 switch (type) {
371 dst->dest_attr.type);377 case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM:
372 if (dst->dest_attr.type ==378 id = dst->dest_attr.ft_num;
373 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {379 type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
380 break;
381 case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE:
374 id = dst->dest_attr.ft->id;382 id = dst->dest_attr.ft->id;
375 } else if (dst->dest_attr.type ==383 break;
376 MLX5_FLOW_DESTINATION_TYPE_VPORT) {384 case MLX5_FLOW_DESTINATION_TYPE_VPORT:
377 id = dst->dest_attr.vport.num;385 id = dst->dest_attr.vport.num;
378 MLX5_SET(dest_format_struct, in_dests,386 MLX5_SET(dest_format_struct, in_dests,
379 destination_eswitch_owner_vhca_id_valid,387 destination_eswitch_owner_vhca_id_valid,
@@ -381,9 +389,13 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, · 1 unmodified line
381 MLX5_SET(dest_format_struct, in_dests,389 MLX5_SET(dest_format_struct, in_dests,
382 destination_eswitch_owner_vhca_id,390 destination_eswitch_owner_vhca_id,
383 dst->dest_attr.vport.vhca_id);391 dst->dest_attr.vport.vhca_id);
384 } else {392 break;
393 default:
385 id = dst->dest_attr.tir_num;394 id = dst->dest_attr.tir_num;
386 }395 }
396
397 MLX5_SET(dest_format_struct, in_dests, destination_type,
398 type);
387 MLX5_SET(dest_format_struct, in_dests, destination_id, id);399 MLX5_SET(dest_format_struct, in_dests, destination_id, id);
388 in_dests += MLX5_ST_SZ_BYTES(dest_format_struct);400 in_dests += MLX5_ST_SZ_BYTES(dest_format_struct);
389 list_size++;401 list_size++;
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c+8−79
@@ -309,89 +309,17 @@ static struct fs_prio *find_prio(struct mlx5_flow_namespace *ns, · 308 unmodified lines
309 return NULL;309 return NULL;
310}310}
311 311
312static bool check_last_reserved(const u32 *match_criteria)
313{
314 char *match_criteria_reserved =
315 MLX5_ADDR_OF(fte_match_param, match_criteria, MLX5_FTE_MATCH_PARAM_RESERVED);
316
317 return !match_criteria_reserved[0] &&
318 !memcmp(match_criteria_reserved, match_criteria_reserved + 1,
319 MLX5_FLD_SZ_BYTES(fte_match_param,
320 MLX5_FTE_MATCH_PARAM_RESERVED) - 1);
321}
322
323static bool check_valid_mask(u8 match_criteria_enable, const u32 *match_criteria)
324{
325 if (match_criteria_enable & ~(
326 (1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS) |
327 (1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS) |
328 (1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS) |
329 (1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2)))
330 return false;
331
332 if (!(match_criteria_enable &
333 1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS)) {
334 char *fg_type_mask = MLX5_ADDR_OF(fte_match_param,
335 match_criteria, outer_headers);
336
337 if (fg_type_mask[0] ||
338 memcmp(fg_type_mask, fg_type_mask + 1,
339 MLX5_ST_SZ_BYTES(fte_match_set_lyr_2_4) - 1))
340 return false;
341 }
342
343 if (!(match_criteria_enable &
344 1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS)) {
345 char *fg_type_mask = MLX5_ADDR_OF(fte_match_param,
346 match_criteria, misc_parameters);
347
348 if (fg_type_mask[0] ||
349 memcmp(fg_type_mask, fg_type_mask + 1,
350 MLX5_ST_SZ_BYTES(fte_match_set_misc) - 1))
351 return false;
352 }
353
354 if (!(match_criteria_enable &
355 1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS)) {
356 char *fg_type_mask = MLX5_ADDR_OF(fte_match_param,
357 match_criteria, inner_headers);
358
359 if (fg_type_mask[0] ||
360 memcmp(fg_type_mask, fg_type_mask + 1,
361 MLX5_ST_SZ_BYTES(fte_match_set_lyr_2_4) - 1))
362 return false;
363 }
364
365 if (!(match_criteria_enable &
366 1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2)) {
367 char *fg_type_mask = MLX5_ADDR_OF(fte_match_param,
368 match_criteria, misc_parameters_2);
369
370 if (fg_type_mask[0] ||
371 memcmp(fg_type_mask, fg_type_mask + 1,
372 MLX5_ST_SZ_BYTES(fte_match_set_misc2) - 1))
373 return false;
374 }
375
376 return check_last_reserved(match_criteria);
377}
378
379static bool check_valid_spec(const struct mlx5_flow_spec *spec)312static bool check_valid_spec(const struct mlx5_flow_spec *spec)
380{313{
381 int i;314 int i;
382 315
383 if (!check_valid_mask(spec->match_criteria_enable, spec->match_criteria)) {
384 pr_warn("mlx5_core: Match criteria given mismatches match_criteria_enable\n");
385 return false;
386 }
387
388 for (i = 0; i < MLX5_ST_SZ_DW_MATCH_PARAM; i++)316 for (i = 0; i < MLX5_ST_SZ_DW_MATCH_PARAM; i++)
389 if (spec->match_value[i] & ~spec->match_criteria[i]) {317 if (spec->match_value[i] & ~spec->match_criteria[i]) {
390 pr_warn("mlx5_core: match_value differs from match_criteria\n");318 pr_warn("mlx5_core: match_value differs from match_criteria\n");
391 return false;319 return false;
392 }320 }
393 321
394 return check_last_reserved(spec->match_value);322 return true;
395}323}
396 324
397static struct mlx5_flow_root_namespace *find_root(struct fs_node *node)325static struct mlx5_flow_root_namespace *find_root(struct fs_node *node)
@@ -1158,9 +1086,6 @@ struct mlx5_flow_group *mlx5_create_flow_group(struct mlx5_flow_table *ft, · 760 unmodified lines
1158 struct mlx5_flow_group *fg;1086 struct mlx5_flow_group *fg;
1159 int err;1087 int err;
1160 1088
1161 if (!check_valid_mask(match_criteria_enable, match_criteria))
1162 return ERR_PTR(-EINVAL);
1163
1164 if (ft->autogroup.active)1089 if (ft->autogroup.active)
1165 return ERR_PTR(-EPERM);1090 return ERR_PTR(-EPERM);
1166 1091
@@ -1431,7 +1356,9 @@ static bool mlx5_flow_dests_cmp(struct mlx5_flow_destination *d1, · 264 unmodified lines
1431 (d1->type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&1356 (d1->type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
1432 d1->ft == d2->ft) ||1357 d1->ft == d2->ft) ||
1433 (d1->type == MLX5_FLOW_DESTINATION_TYPE_TIR &&1358 (d1->type == MLX5_FLOW_DESTINATION_TYPE_TIR &&
1434 d1->tir_num == d2->tir_num))1359 d1->tir_num == d2->tir_num) ||
1360 (d1->type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM &&
1361 d1->ft_num == d2->ft_num))
1435 return true;1362 return true;
1436 }1363 }
1437 1364
@@ -1464,7 +1391,9 @@ static bool check_conflicting_actions(u32 action1, u32 action2) · 26 unmodified lines
1464 MLX5_FLOW_CONTEXT_ACTION_DECAP |1391 MLX5_FLOW_CONTEXT_ACTION_DECAP |
1465 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |1392 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
1466 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP |1393 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP |
1467 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH))1394 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
1395 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 |
1396 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2))
1468 return true;1397 return true;
1469 1398
1470 return false;1399 return false;
@@ -1823,7 +1752,7 @@ search_again_locked: · 352 unmodified lines
1823 1752
1824 g = alloc_auto_flow_group(ft, spec);1753 g = alloc_auto_flow_group(ft, spec);
1825 if (IS_ERR(g)) {1754 if (IS_ERR(g)) {
1826 rule = (void *)g;1755 rule = ERR_CAST(g);
1827 up_write_ref_node(&ft->node);1756 up_write_ref_node(&ft->node);
1828 return rule;1757 return rule;
1829 }1758 }
drivers/net/ethernet/mellanox/mlx5/core/main.c+1−1
@@ -64,7 +64,7 @@ · 63 unmodified lines
64#include "lib/clock.h"64#include "lib/clock.h"
65 65
66MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");66MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
67MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");67MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
68MODULE_LICENSE("Dual BSD/GPL");68MODULE_LICENSE("Dual BSD/GPL");
69MODULE_VERSION(DRIVER_VERSION);69MODULE_VERSION(DRIVER_VERSION);
70 70
include/linux/mlx5/device.h+4−4
@@ -750,7 +750,7 @@ enum { · 749 unmodified lines
750 750
751#define MLX5_MINI_CQE_ARRAY_SIZE 8751#define MLX5_MINI_CQE_ARRAY_SIZE 8
752 752
753static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)753static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
754{754{
755 return (cqe->op_own >> 2) & 0x3;755 return (cqe->op_own >> 2) & 0x3;
756}756}
@@ -770,14 +770,14 @@ static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe) · 13 unmodified lines
770 return (cqe->l4_l3_hdr_type >> 2) & 0x3;770 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
771}771}
772 772
773static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)773static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
774{774{
775 return cqe->outer_l3_tunneled & 0x1;775 return cqe->outer_l3_tunneled & 0x1;
776}776}
777 777
778static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)778static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
779{779{
780 return !!(cqe->l4_l3_hdr_type & 0x1);780 return cqe->l4_l3_hdr_type & 0x1;
781}781}
782 782
783static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)783static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
include/linux/mlx5/driver.h+5−0
@@ -138,9 +138,14 @@ enum { · 137 unmodified lines
138 MLX5_REG_HOST_ENDIANNESS = 0x7004,138 MLX5_REG_HOST_ENDIANNESS = 0x7004,
139 MLX5_REG_MCIA = 0x9014,139 MLX5_REG_MCIA = 0x9014,
140 MLX5_REG_MLCR = 0x902b,140 MLX5_REG_MLCR = 0x902b,
141 MLX5_REG_MTRC_CAP = 0x9040,
142 MLX5_REG_MTRC_CONF = 0x9041,
143 MLX5_REG_MTRC_STDB = 0x9042,
144 MLX5_REG_MTRC_CTRL = 0x9043,
141 MLX5_REG_MPCNT = 0x9051,145 MLX5_REG_MPCNT = 0x9051,
142 MLX5_REG_MTPPS = 0x9053,146 MLX5_REG_MTPPS = 0x9053,
143 MLX5_REG_MTPPSE = 0x9054,147 MLX5_REG_MTPPSE = 0x9054,
148 MLX5_REG_MPEGC = 0x9056,
144 MLX5_REG_MCQI = 0x9061,149 MLX5_REG_MCQI = 0x9061,
145 MLX5_REG_MCC = 0x9062,150 MLX5_REG_MCC = 0x9062,
146 MLX5_REG_MCDA = 0x9063,151 MLX5_REG_MCDA = 0x9063,
include/linux/mlx5/fs.h+4−1
@@ -89,6 +89,7 @@ struct mlx5_flow_destination { · 88 unmodified lines
89 enum mlx5_flow_destination_type type;89 enum mlx5_flow_destination_type type;
90 union {90 union {
91 u32 tir_num;91 u32 tir_num;
92 u32 ft_num;
92 struct mlx5_flow_table *ft;93 struct mlx5_flow_table *ft;
93 struct mlx5_fc *counter;94 struct mlx5_fc *counter;
94 struct {95 struct {
@@ -152,6 +153,8 @@ struct mlx5_fs_vlan { · 57 unmodified lines
152 u8 prio;153 u8 prio;
153};154};
154 155
156#define MLX5_FS_VLAN_DEPTH 2
157
155struct mlx5_flow_act {158struct mlx5_flow_act {
156 u32 action;159 u32 action;
157 bool has_flow_tag;160 bool has_flow_tag;
@@ -159,7 +162,7 @@ struct mlx5_flow_act { · 1 unmodified line
159 u32 encap_id;162 u32 encap_id;
160 u32 modify_id;163 u32 modify_id;
161 uintptr_t esp_id;164 uintptr_t esp_id;
162 struct mlx5_fs_vlan vlan;165 struct mlx5_fs_vlan vlan[MLX5_FS_VLAN_DEPTH];
163 struct ib_counters *counters;166 struct ib_counters *counters;
164};167};
165 168
include/linux/mlx5/mlx5_ifc.h+90−4
@@ -341,7 +341,10 @@ struct mlx5_ifc_flow_table_prop_layout_bits { · 340 unmodified lines
341 u8 reserved_at_9[0x1];341 u8 reserved_at_9[0x1];
342 u8 pop_vlan[0x1];342 u8 pop_vlan[0x1];
343 u8 push_vlan[0x1];343 u8 push_vlan[0x1];
344 u8 reserved_at_c[0x14];344 u8 reserved_at_c[0x1];
345 u8 pop_vlan_2[0x1];
346 u8 push_vlan_2[0x1];
347 u8 reserved_at_f[0x11];
345 348
346 u8 reserved_at_20[0x2];349 u8 reserved_at_20[0x2];
347 u8 log_max_ft_size[0x6];350 u8 log_max_ft_size[0x6];
@@ -1181,6 +1184,7 @@ enum mlx5_flow_destination_type { · 833 unmodified lines
1181 1184
1182 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,1185 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1183 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,1186 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1187 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1184};1188};
1185 1189
1186struct mlx5_ifc_dest_format_struct_bits {1190struct mlx5_ifc_dest_format_struct_bits {
@@ -2390,6 +2394,8 @@ enum { · 1203 unmodified lines
2390 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,2394 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2391 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,2395 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2392 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,2396 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2397 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2398 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2393};2399};
2394 2400
2395struct mlx5_ifc_vlan_bits {2401struct mlx5_ifc_vlan_bits {
@@ -2420,7 +2426,9 @@ struct mlx5_ifc_flow_context_bits { · 24 unmodified lines
2420 2426
2421 u8 modify_header_id[0x20];2427 u8 modify_header_id[0x20];
2422 2428
2423 u8 reserved_at_100[0x100];2429 struct mlx5_ifc_vlan_bits push_vlan_2;
2430
2431 u8 reserved_at_120[0xe0];
2424 2432
2425 struct mlx5_ifc_fte_match_param_bits match_value;2433 struct mlx5_ifc_fte_match_param_bits match_value;
2426 2434
@@ -8053,6 +8061,19 @@ struct mlx5_ifc_peir_reg_bits { · 5626 unmodified lines
8053 u8 error_type[0x8];8061 u8 error_type[0x8];
8054};8062};
8055 8063
8064struct mlx5_ifc_mpegc_reg_bits {
8065 u8 reserved_at_0[0x30];
8066 u8 field_select[0x10];
8067
8068 u8 tx_overflow_sense[0x1];
8069 u8 mark_cqe[0x1];
8070 u8 mark_cnp[0x1];
8071 u8 reserved_at_43[0x1b];
8072 u8 tx_lossy_overflow_oper[0x2];
8073
8074 u8 reserved_at_60[0x100];
8075};
8076
8056struct mlx5_ifc_pcam_enhanced_features_bits {8077struct mlx5_ifc_pcam_enhanced_features_bits {
8057 u8 reserved_at_0[0x6d];8078 u8 reserved_at_0[0x6d];
8058 u8 rx_icrc_encapsulated_counter[0x1];8079 u8 rx_icrc_encapsulated_counter[0x1];
@@ -8101,7 +8122,11 @@ struct mlx5_ifc_pcam_reg_bits { · 42 unmodified lines
8101};8122};
8102 8123
8103struct mlx5_ifc_mcam_enhanced_features_bits {8124struct mlx5_ifc_mcam_enhanced_features_bits {
8104 u8 reserved_at_0[0x7b];8125 u8 reserved_at_0[0x74];
8126 u8 mark_tx_action_cnp[0x1];
8127 u8 mark_tx_action_cqe[0x1];
8128 u8 dynamic_tx_overflow[0x1];
8129 u8 reserved_at_77[0x4];
8105 u8 pcie_outbound_stalled[0x1];8130 u8 pcie_outbound_stalled[0x1];
8106 u8 tx_overflow_buffer_pkt[0x1];8131 u8 tx_overflow_buffer_pkt[0x1];
8107 u8 mtpps_enh_out_per_adj[0x1];8132 u8 mtpps_enh_out_per_adj[0x1];
@@ -8116,7 +8141,11 @@ struct mlx5_ifc_mcam_access_reg_bits { · 8 unmodified lines
8116 u8 mcqi[0x1];8141 u8 mcqi[0x1];
8117 u8 reserved_at_1f[0x1];8142 u8 reserved_at_1f[0x1];
8118 8143
8119 u8 regs_95_to_64[0x20];8144 u8 regs_95_to_87[0x9];
8145 u8 mpegc[0x1];
8146 u8 regs_85_to_68[0x12];
8147 u8 tracer_registers[0x4];
8148
8120 u8 regs_63_to_32[0x20];8149 u8 regs_63_to_32[0x20];
8121 u8 regs_31_to_0[0x20];8150 u8 regs_31_to_0[0x20];
8122};8151};
@@ -9191,4 +9220,61 @@ struct mlx5_ifc_create_uctx_in_bits { · 1068 unmodified lines
9191 struct mlx5_ifc_uctx_bits uctx;9220 struct mlx5_ifc_uctx_bits uctx;
9192};9221};
9193 9222
9223struct mlx5_ifc_mtrc_string_db_param_bits {
9224 u8 string_db_base_address[0x20];
9225
9226 u8 reserved_at_20[0x8];
9227 u8 string_db_size[0x18];
9228};
9229
9230struct mlx5_ifc_mtrc_cap_bits {
9231 u8 trace_owner[0x1];
9232 u8 trace_to_memory[0x1];
9233 u8 reserved_at_2[0x4];
9234 u8 trc_ver[0x2];
9235 u8 reserved_at_8[0x14];
9236 u8 num_string_db[0x4];
9237
9238 u8 first_string_trace[0x8];
9239 u8 num_string_trace[0x8];
9240 u8 reserved_at_30[0x28];
9241
9242 u8 log_max_trace_buffer_size[0x8];
9243
9244 u8 reserved_at_60[0x20];
9245
9246 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9247
9248 u8 reserved_at_280[0x180];
9249};
9250
9251struct mlx5_ifc_mtrc_conf_bits {
9252 u8 reserved_at_0[0x1c];
9253 u8 trace_mode[0x4];
9254 u8 reserved_at_20[0x18];
9255 u8 log_trace_buffer_size[0x8];
9256 u8 trace_mkey[0x20];
9257 u8 reserved_at_60[0x3a0];
9258};
9259
9260struct mlx5_ifc_mtrc_stdb_bits {
9261 u8 string_db_index[0x4];
9262 u8 reserved_at_4[0x4];
9263 u8 read_size[0x18];
9264 u8 start_offset[0x20];
9265 u8 string_db_data[0];
9266};
9267
9268struct mlx5_ifc_mtrc_ctrl_bits {
9269 u8 trace_status[0x2];
9270 u8 reserved_at_2[0x2];
9271 u8 arm_event[0x1];
9272 u8 reserved_at_5[0xb];
9273 u8 modify_field_select[0x10];
9274 u8 reserved_at_20[0x2b];
9275 u8 current_timestamp52_32[0x15];
9276 u8 current_timestamp31_0[0x20];
9277 u8 reserved_at_80[0x180];
9278};
9279
9194#endif /* MLX5_IFC_H */9280#endif /* MLX5_IFC_H */

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