Add TLS RX offload related IFC hardware fields and enumerations.
Unified · Split
| @@ -450,10 +450,12 @@ enum { · 449 unmodified lines | |||
| 450 | 450 | ||
| 451 | enum { | 451 | enum { |
| 452 | MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1, | 452 | MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1, |
| 453 | MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2, | ||
| 453 | }; | 454 | }; |
| 454 | 455 | ||
| 455 | enum { | 456 | enum { |
| 456 | MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1, | 457 | MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1, |
| 458 | MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2, | ||
| 457 | }; | 459 | }; |
| 458 | 460 | ||
| 459 | enum { | 461 | enum { |
| @@ -764,7 +766,7 @@ struct mlx5_err_cqe { · 304 unmodified lines | |||
| 764 | }; | 766 | }; |
| 765 | 767 | ||
| 766 | struct mlx5_cqe64 { | 768 | struct mlx5_cqe64 { |
| 767 | u8 outer_l3_tunneled; | 769 | u8 tls_outer_l3_tunneled; |
| 768 | u8 rsvd0; | 770 | u8 rsvd0; |
| 769 | __be16 wqe_id; | 771 | __be16 wqe_id; |
| 770 | u8 lro_tcppsh_abort_dupack; | 772 | u8 lro_tcppsh_abort_dupack; |
| @@ -854,7 +856,12 @@ static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe) · 83 unmodified lines | |||
| 854 | 856 | ||
| 855 | static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) | 857 | static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) |
| 856 | { | 858 | { |
| 857 | return cqe->outer_l3_tunneled & 0x1; | 859 | return cqe->tls_outer_l3_tunneled & 0x1; |
| 860 | } | ||
| 861 | |||
| 862 | static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe) | ||
| 863 | { | ||
| 864 | return (cqe->tls_outer_l3_tunneled >> 3) & 0x3; | ||
| 858 | } | 865 | } |
| 859 | 866 | ||
| 860 | static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) | 867 | static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) |
| @@ -942,6 +949,13 @@ enum { · 81 unmodified lines | |||
| 942 | CQE_L4_OK = 1 << 2, | 949 | CQE_L4_OK = 1 << 2, |
| 943 | }; | 950 | }; |
| 944 | 951 | ||
| 952 | enum { | ||
| 953 | CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0, | ||
| 954 | CQE_TLS_OFFLOAD_DECRYPTED = 0x1, | ||
| 955 | CQE_TLS_OFFLOAD_RESYNC = 0x2, | ||
| 956 | CQE_TLS_OFFLOAD_ERROR = 0x3, | ||
| 957 | }; | ||
| 958 | |||
| 945 | struct mlx5_sig_err_cqe { | 959 | struct mlx5_sig_err_cqe { |
| 946 | u8 rsvd0[16]; | 960 | u8 rsvd0[16]; |
| 947 | __be32 expected_trans_sig; | 961 | __be32 expected_trans_sig; |
| @@ -1491,7 +1491,7 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 1490 unmodified lines | |||
| 1491 | 1491 | ||
| 1492 | u8 reserved_at_480[0x1]; | 1492 | u8 reserved_at_480[0x1]; |
| 1493 | u8 tls_tx[0x1]; | 1493 | u8 tls_tx[0x1]; |
| 1494 | u8 reserved_at_482[0x1]; | 1494 | u8 tls_rx[0x1]; |
| 1495 | u8 log_max_l2_table[0x5]; | 1495 | u8 log_max_l2_table[0x5]; |
| 1496 | u8 reserved_at_488[0x8]; | 1496 | u8 reserved_at_488[0x8]; |
| 1497 | u8 log_uar_page_sz[0x10]; | 1497 | u8 log_uar_page_sz[0x10]; |
| @@ -3136,7 +3136,8 @@ struct mlx5_ifc_tirc_bits { · 1638 unmodified lines | |||
| 3136 | u8 reserved_at_0[0x20]; | 3136 | u8 reserved_at_0[0x20]; |
| 3137 | 3137 | ||
| 3138 | u8 disp_type[0x4]; | 3138 | u8 disp_type[0x4]; |
| 3139 | u8 reserved_at_24[0x1c]; | 3139 | u8 tls_en[0x1]; |
| 3140 | u8 reserved_at_25[0x1b]; | ||
| 3140 | 3141 | ||
| 3141 | u8 reserved_at_40[0x40]; | 3142 | u8 reserved_at_40[0x40]; |
| 3142 | 3143 | ||