ee5db7e9 parents 467669c 5235166 368d4e5 604b607 5b65c2a 981c5b4 8493ecc 5df4eb0 5ae6e894357 files · +172503 −102549Browse filesUnified · Split
| @@ -34,6 +34,7 @@ · 33 unmodified lines | ||
| 34 | 34 | *.gcno |
| 35 | 35 | modules.builtin |
| 36 | 36 | Module.symvers |
| 37 | +*.dwo | |
| 37 | 38 | |
| 38 | 39 | # |
| 39 | 40 | # Top-level generic files |
| @@ -1381,6 +1381,9 @@ S: 17 rue Danton · 1380 unmodified lines | ||
| 1381 | 1381 | S: F - 94270 Le Kremlin-Bicêtre |
| 1382 | 1382 | S: France |
| 1383 | 1383 | |
| 1384 | +N: Jack Hammer | |
| 1385 | +D: IBM ServeRAID RAID (ips) driver maintenance | |
| 1386 | + | |
| 1384 | 1387 | N: Greg Hankins |
| 1385 | 1388 | E: gregh@cc.gatech.edu |
| 1386 | 1389 | D: fixed keyboard driver to separate LED and locking status |
| @@ -1691,6 +1694,10 @@ S: Reading · 304 unmodified lines | ||
| 1691 | 1694 | S: RG6 2NU |
| 1692 | 1695 | S: United Kingdom |
| 1693 | 1696 | |
| 1697 | +N: Dave Jeffery | |
| 1698 | +E: dhjeffery@gmail.com | |
| 1699 | +D: SCSI hacks and IBM ServeRAID RAID driver maintenance | |
| 1700 | + | |
| 1694 | 1701 | N: Jakub Jelinek |
| 1695 | 1702 | E: jakub@redhat.com |
| 1696 | 1703 | W: http://sunsite.mff.cuni.cz/~jj |
| @@ -94,5 +94,5 @@ current_snap · 93 unmodified lines | ||
| 94 | 94 | |
| 95 | 95 | parent |
| 96 | 96 | |
| 97 | − Information identifying the pool, image, and snapshot id for | |
| 98 | − the parent image in a layered rbd image (format 2 only). | |
| 97 | + Information identifying the chain of parent images in a layered rbd | |
| 98 | + image. Entries are separated by empty lines. | |
| @@ -0,0 +1,16 @@ | ||
| 1 | +What: /sys/class/leds/<led>/gt683r/mode | |
| 2 | +Date: Jun 2014 | |
| 3 | +KernelVersion: 3.17 | |
| 4 | +Contact: Janne Kanniainen <janne.kanniainen@gmail.com> | |
| 5 | +Description: | |
| 6 | + Set the mode of LEDs. You should notice that changing the mode | |
| 7 | + of one LED will update the mode of its two sibling devices as | |
| 8 | + well. | |
| 9 | + | |
| 10 | + 0 - normal | |
| 11 | + 1 - audio | |
| 12 | + 2 - breathing | |
| 13 | + | |
| 14 | + Normal: LEDs are fully on when enabled | |
| 15 | + Audio: LEDs brightness depends on sound level | |
| 16 | + Breathing: LEDs brightness varies at human breathing rate | |
| @@ -184,3 +184,41 @@ Description: · 183 unmodified lines | ||
| 184 | 184 | |
| 185 | 185 | It will always be a non-negative integer. In the case of |
| 186 | 186 | devices lacking any ECC capability, it is 0. |
| 187 | + | |
| 188 | +What: /sys/class/mtd/mtdX/ecc_failures | |
| 189 | +Date: June 2014 | |
| 190 | +KernelVersion: 3.17 | |
| 191 | +Contact: linux-mtd@lists.infradead.org | |
| 192 | +Description: | |
| 193 | + The number of failures reported by this device's ECC. Typically, | |
| 194 | + these failures are associated with failed read operations. | |
| 195 | + | |
| 196 | + It will always be a non-negative integer. In the case of | |
| 197 | + devices lacking any ECC capability, it is 0. | |
| 198 | + | |
| 199 | +What: /sys/class/mtd/mtdX/corrected_bits | |
| 200 | +Date: June 2014 | |
| 201 | +KernelVersion: 3.17 | |
| 202 | +Contact: linux-mtd@lists.infradead.org | |
| 203 | +Description: | |
| 204 | + The number of bits that have been corrected by means of the | |
| 205 | + device's ECC. | |
| 206 | + | |
| 207 | + It will always be a non-negative integer. In the case of | |
| 208 | + devices lacking any ECC capability, it is 0. | |
| 209 | + | |
| 210 | +What: /sys/class/mtd/mtdX/bad_blocks | |
| 211 | +Date: June 2014 | |
| 212 | +KernelVersion: 3.17 | |
| 213 | +Contact: linux-mtd@lists.infradead.org | |
| 214 | +Description: | |
| 215 | + The number of blocks marked as bad, if any, in this partition. | |
| 216 | + | |
| 217 | +What: /sys/class/mtd/mtdX/bbt_blocks | |
| 218 | +Date: June 2014 | |
| 219 | +KernelVersion: 3.17 | |
| 220 | +Contact: linux-mtd@lists.infradead.org | |
| 221 | +Description: | |
| 222 | + The number of blocks that are marked as reserved, if any, in | |
| 223 | + this partition. These are typically used to store the in-flash | |
| 224 | + bad block table (BBT). | |
| @@ -0,0 +1,13 @@ | ||
| 1 | +What: /sys/bus/pci/drivers/pciback/quirks | |
| 2 | +Date: Oct 2011 | |
| 3 | +KernelVersion: 3.1 | |
| 4 | +Contact: xen-devel@lists.xenproject.org | |
| 5 | +Description: | |
| 6 | + If the permissive attribute is set, then writing a string in | |
| 7 | + the format of DDDD:BB:DD.F-REG:SIZE:MASK will allow the guest | |
| 8 | + to write and read from the PCI device. That is Domain:Bus: | |
| 9 | + Device.Function-Register:Size:Mask (Domain is optional). | |
| 10 | + For example: | |
| 11 | + #echo 00:19.0-E0:2:FF > /sys/bus/pci/drivers/pciback/quirks | |
| 12 | + will allow the guest to read and write to the configuration | |
| 13 | + register 0x0E. | |
| @@ -0,0 +1,11 @@ | ||
| 1 | +What: /sys/devices/*/<our-device>/fuse | |
| 2 | +Date: February 2014 | |
| 3 | +Contact: Peter De Schrijver <pdeschrijver@nvidia.com> | |
| 4 | +Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114 | |
| 5 | + and Tegra124 SoC's from NVIDIA. The efuses contain write once | |
| 6 | + data programmed at the factory. The data is layed out in 32bit | |
| 7 | + words in LSB first format. Each bit represents a single value | |
| 8 | + as decoded from the fuse registers. Bits order/assignment | |
| 9 | + exactly matches the HW registers, including any unused bits. | |
| 10 | +Users: any user space application which wants to read the efuses on | |
| 11 | + Tegra SoC's | |
| @@ -1,48 +1,27 @@ | ||
| 1 | −WWhat: /sys/class/hidraw/hidraw*/device/oled*_img | |
| 2 | −Date: June 2012 | |
| 3 | −Contact: linux-bluetooth@vger.kernel.org | |
| 4 | −Description: | |
| 5 | − The /sys/class/hidraw/hidraw*/device/oled*_img files control | |
| 6 | − OLED mocro displays on Intuos4 Wireless tablet. Accepted image | |
| 7 | − has to contain 256 bytes (64x32 px 1 bit colour). The format | |
| 8 | − is the same as PBM image 62x32px without header (64 bits per | |
| 9 | − horizontal line, 32 lines). An example of setting OLED No. 0: | |
| 10 | − dd bs=256 count=1 if=img_file of=[path to oled0_img]/oled0_img | |
| 11 | − The attribute is read only and no local copy of the image is | |
| 12 | − stored. | |
| 13 | − | |
| 14 | −What: /sys/class/hidraw/hidraw*/device/speed | |
| 1 | +What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/speed | |
| 15 | 2 | Date: April 2010 |
| 16 | 3 | Kernel Version: 2.6.35 |
| 17 | 4 | Contact: linux-bluetooth@vger.kernel.org |
| 18 | 5 | Description: |
| 19 | − The /sys/class/hidraw/hidraw*/device/speed file controls | |
| 20 | − reporting speed of Wacom bluetooth tablet. Reading from | |
| 21 | − this file returns 1 if tablet reports in high speed mode | |
| 6 | + The /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/speed file | |
| 7 | + controls reporting speed of Wacom bluetooth tablet. Reading | |
| 8 | + from this file returns 1 if tablet reports in high speed mode | |
| 22 | 9 | or 0 otherwise. Writing to this file one of these values |
| 23 | 10 | switches reporting speed. |
| 24 | 11 | |
| 25 | −What: /sys/class/leds/0005\:056A\:00BD.0001\:selector\:*/ | |
| 26 | −Date: May 2012 | |
| 27 | −Kernel Version: 3.5 | |
| 28 | −Contact: linux-bluetooth@vger.kernel.org | |
| 29 | −Description: | |
| 30 | − LED selector for Intuos4 WL. There are 4 leds, but only one LED | |
| 31 | − can be lit at a time. Max brightness is 127. | |
| 32 | − | |
| 33 | −What: /sys/bus/usb/devices/<busnum>-<devnum>:<cfg>.<intf>/wacom_led/led | |
| 34 | −Date: August 2011 | |
| 12 | +What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/led | |
| 13 | +Date: August 2014 | |
| 35 | 14 | Contact: linux-input@vger.kernel.org |
| 36 | 15 | Description: |
| 37 | 16 | Attribute group for control of the status LEDs and the OLEDs. |
| 38 | 17 | This attribute group is only available for Intuos 4 M, L, |
| 39 | − and XL (with LEDs and OLEDs), Intuos 5 (LEDs only), and Cintiq | |
| 40 | − 21UX2 and Cintiq 24HD (LEDs only). Therefore its presence | |
| 41 | − implicitly signifies the presence of said LEDs and OLEDs on the | |
| 42 | − tablet device. | |
| 18 | + and XL (with LEDs and OLEDs), Intuos 4 WL, Intuos 5 (LEDs only), | |
| 19 | + Intuos Pro (LEDs only) and Cintiq 21UX2 and Cintiq 24HD | |
| 20 | + (LEDs only). Therefore its presence implicitly signifies the | |
| 21 | + presence of said LEDs and OLEDs on the tablet device. | |
| 43 | 22 | |
| 44 | −What: /sys/bus/usb/devices/<busnum>-<devnum>:<cfg>.<intf>/wacom_led/status0_luminance | |
| 45 | −Date: August 2011 | |
| 23 | +What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/status0_luminance | |
| 24 | +Date: August 2014 | |
| 46 | 25 | Contact: linux-input@vger.kernel.org |
| 47 | 26 | Description: |
| 48 | 27 | Writing to this file sets the status LED luminance (1..127) |
| @@ -50,16 +29,16 @@ Description: · 1 unmodified line | ||
| 50 | 29 | button is pressed on the stylus. This luminance level is |
| 51 | 30 | normally lower than the level when a button is pressed. |
| 52 | 31 | |
| 53 | −What: /sys/bus/usb/devices/<busnum>-<devnum>:<cfg>.<intf>/wacom_led/status1_luminance | |
| 54 | −Date: August 2011 | |
| 32 | +What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/status1_luminance | |
| 33 | +Date: August 2014 | |
| 55 | 34 | Contact: linux-input@vger.kernel.org |
| 56 | 35 | Description: |
| 57 | 36 | Writing to this file sets the status LED luminance (1..127) |
| 58 | 37 | when the stylus touches the tablet surface, or any button is |
| 59 | 38 | pressed on the stylus. |
| 60 | 39 | |
| 61 | −What: /sys/bus/usb/devices/<busnum>-<devnum>:<cfg>.<intf>/wacom_led/status_led0_select | |
| 62 | −Date: August 2011 | |
| 40 | +What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/status_led0_select | |
| 41 | +Date: August 2014 | |
| 63 | 42 | Contact: linux-input@vger.kernel.org |
| 64 | 43 | Description: |
| 65 | 44 | Writing to this file sets which one of the four (for Intuos 4 |
| @@ -67,23 +46,23 @@ Description: · 1 unmodified line | ||
| 67 | 46 | 24HD) status LEDs is active (0..3). The other three LEDs on the |
| 68 | 47 | same side are always inactive. |
| 69 | 48 | |
| 70 | −What: /sys/bus/usb/devices/<busnum>-<devnum>:<cfg>.<intf>/wacom_led/status_led1_select | |
| 71 | −Date: September 2011 | |
| 49 | +What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/status_led1_select | |
| 50 | +Date: August 2014 | |
| 72 | 51 | Contact: linux-input@vger.kernel.org |
| 73 | 52 | Description: |
| 74 | 53 | Writing to this file sets which one of the left four (for Cintiq 21UX2 |
| 75 | 54 | and Cintiq 24HD) status LEDs is active (0..3). The other three LEDs on |
| 76 | 55 | the left are always inactive. |
| 77 | 56 | |
| 78 | −What: /sys/bus/usb/devices/<busnum>-<devnum>:<cfg>.<intf>/wacom_led/buttons_luminance | |
| 79 | −Date: August 2011 | |
| 57 | +What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/buttons_luminance | |
| 58 | +Date: August 2014 | |
| 80 | 59 | Contact: linux-input@vger.kernel.org |
| 81 | 60 | Description: |
| 82 | 61 | Writing to this file sets the overall luminance level (0..15) |
| 83 | 62 | of all eight button OLED displays. |
| 84 | 63 | |
| 85 | −What: /sys/bus/usb/devices/<busnum>-<devnum>:<cfg>.<intf>/wacom_led/button<n>_rawimg | |
| 86 | −Date: August 2011 | |
| 64 | +What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/button<n>_rawimg | |
| 65 | +Date: August 2014 | |
| 87 | 66 | Contact: linux-input@vger.kernel.org |
| 88 | 67 | Description: |
| 89 | 68 | When writing a 1024 byte raw image in Wacom Intuos 4 |
| @@ -93,3 +72,8 @@ Description: · 3 unmodified lines | ||
| 93 | 72 | byte chunk encodes the image data for two consecutive lines on |
| 94 | 73 | the display. The low nibble of each byte contains the first |
| 95 | 74 | line, and the high nibble contains the second line. |
| 75 | + When the Wacom Intuos 4 is connected over Bluetooth, the | |
| 76 | + image has to contain 256 bytes (64x32 px 1 bit colour). | |
| 77 | + The format is also scrambled, like in the USB mode, and it can | |
| 78 | + be summarized by converting 76543210 into GECA6420. | |
| 79 | + HGFEDCBA HFDB7531 | |
| @@ -0,0 +1,269 @@ | ||
| 1 | + | |
| 2 | +What: /sys/fs/nilfs2/features/revision | |
| 3 | +Date: April 2014 | |
| 4 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 5 | +Description: | |
| 6 | + Show current revision of NILFS file system driver. | |
| 7 | + This value informs about file system revision that | |
| 8 | + driver is ready to support. | |
| 9 | + | |
| 10 | +What: /sys/fs/nilfs2/features/README | |
| 11 | +Date: April 2014 | |
| 12 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 13 | +Description: | |
| 14 | + Describe attributes of /sys/fs/nilfs2/features group. | |
| 15 | + | |
| 16 | +What: /sys/fs/nilfs2/<device>/revision | |
| 17 | +Date: April 2014 | |
| 18 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 19 | +Description: | |
| 20 | + Show NILFS file system revision on volume. | |
| 21 | + This value informs about metadata structures' | |
| 22 | + revision on mounted volume. | |
| 23 | + | |
| 24 | +What: /sys/fs/nilfs2/<device>/blocksize | |
| 25 | +Date: April 2014 | |
| 26 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 27 | +Description: | |
| 28 | + Show volume's block size in bytes. | |
| 29 | + | |
| 30 | +What: /sys/fs/nilfs2/<device>/device_size | |
| 31 | +Date: April 2014 | |
| 32 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 33 | +Description: | |
| 34 | + Show volume size in bytes. | |
| 35 | + | |
| 36 | +What: /sys/fs/nilfs2/<device>/free_blocks | |
| 37 | +Date: April 2014 | |
| 38 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 39 | +Description: | |
| 40 | + Show count of free blocks on volume. | |
| 41 | + | |
| 42 | +What: /sys/fs/nilfs2/<device>/uuid | |
| 43 | +Date: April 2014 | |
| 44 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 45 | +Description: | |
| 46 | + Show volume's UUID (Universally Unique Identifier). | |
| 47 | + | |
| 48 | +What: /sys/fs/nilfs2/<device>/volume_name | |
| 49 | +Date: April 2014 | |
| 50 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 51 | +Description: | |
| 52 | + Show volume's label. | |
| 53 | + | |
| 54 | +What: /sys/fs/nilfs2/<device>/README | |
| 55 | +Date: April 2014 | |
| 56 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 57 | +Description: | |
| 58 | + Describe attributes of /sys/fs/nilfs2/<device> group. | |
| 59 | + | |
| 60 | +What: /sys/fs/nilfs2/<device>/superblock/sb_write_time | |
| 61 | +Date: April 2014 | |
| 62 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 63 | +Description: | |
| 64 | + Show last write time of super block in human-readable | |
| 65 | + format. | |
| 66 | + | |
| 67 | +What: /sys/fs/nilfs2/<device>/superblock/sb_write_time_secs | |
| 68 | +Date: April 2014 | |
| 69 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 70 | +Description: | |
| 71 | + Show last write time of super block in seconds. | |
| 72 | + | |
| 73 | +What: /sys/fs/nilfs2/<device>/superblock/sb_write_count | |
| 74 | +Date: April 2014 | |
| 75 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 76 | +Description: | |
| 77 | + Show current write count of super block. | |
| 78 | + | |
| 79 | +What: /sys/fs/nilfs2/<device>/superblock/sb_update_frequency | |
| 80 | +Date: April 2014 | |
| 81 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 82 | +Description: | |
| 83 | + Show/Set interval of periodical update of superblock | |
| 84 | + (in seconds). | |
| 85 | + | |
| 86 | +What: /sys/fs/nilfs2/<device>/superblock/README | |
| 87 | +Date: April 2014 | |
| 88 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 89 | +Description: | |
| 90 | + Describe attributes of /sys/fs/nilfs2/<device>/superblock | |
| 91 | + group. | |
| 92 | + | |
| 93 | +What: /sys/fs/nilfs2/<device>/segctor/last_pseg_block | |
| 94 | +Date: April 2014 | |
| 95 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 96 | +Description: | |
| 97 | + Show start block number of the latest segment. | |
| 98 | + | |
| 99 | +What: /sys/fs/nilfs2/<device>/segctor/last_seg_sequence | |
| 100 | +Date: April 2014 | |
| 101 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 102 | +Description: | |
| 103 | + Show sequence value of the latest segment. | |
| 104 | + | |
| 105 | +What: /sys/fs/nilfs2/<device>/segctor/last_seg_checkpoint | |
| 106 | +Date: April 2014 | |
| 107 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 108 | +Description: | |
| 109 | + Show checkpoint number of the latest segment. | |
| 110 | + | |
| 111 | +What: /sys/fs/nilfs2/<device>/segctor/current_seg_sequence | |
| 112 | +Date: April 2014 | |
| 113 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 114 | +Description: | |
| 115 | + Show segment sequence counter. | |
| 116 | + | |
| 117 | +What: /sys/fs/nilfs2/<device>/segctor/current_last_full_seg | |
| 118 | +Date: April 2014 | |
| 119 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 120 | +Description: | |
| 121 | + Show index number of the latest full segment. | |
| 122 | + | |
| 123 | +What: /sys/fs/nilfs2/<device>/segctor/next_full_seg | |
| 124 | +Date: April 2014 | |
| 125 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 126 | +Description: | |
| 127 | + Show index number of the full segment index | |
| 128 | + to be used next. | |
| 129 | + | |
| 130 | +What: /sys/fs/nilfs2/<device>/segctor/next_pseg_offset | |
| 131 | +Date: April 2014 | |
| 132 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 133 | +Description: | |
| 134 | + Show offset of next partial segment in the current | |
| 135 | + full segment. | |
| 136 | + | |
| 137 | +What: /sys/fs/nilfs2/<device>/segctor/next_checkpoint | |
| 138 | +Date: April 2014 | |
| 139 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 140 | +Description: | |
| 141 | + Show next checkpoint number. | |
| 142 | + | |
| 143 | +What: /sys/fs/nilfs2/<device>/segctor/last_seg_write_time | |
| 144 | +Date: April 2014 | |
| 145 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 146 | +Description: | |
| 147 | + Show write time of the last segment in | |
| 148 | + human-readable format. | |
| 149 | + | |
| 150 | +What: /sys/fs/nilfs2/<device>/segctor/last_seg_write_time_secs | |
| 151 | +Date: April 2014 | |
| 152 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 153 | +Description: | |
| 154 | + Show write time of the last segment in seconds. | |
| 155 | + | |
| 156 | +What: /sys/fs/nilfs2/<device>/segctor/last_nongc_write_time | |
| 157 | +Date: April 2014 | |
| 158 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 159 | +Description: | |
| 160 | + Show write time of the last segment not for cleaner | |
| 161 | + operation in human-readable format. | |
| 162 | + | |
| 163 | +What: /sys/fs/nilfs2/<device>/segctor/last_nongc_write_time_secs | |
| 164 | +Date: April 2014 | |
| 165 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 166 | +Description: | |
| 167 | + Show write time of the last segment not for cleaner | |
| 168 | + operation in seconds. | |
| 169 | + | |
| 170 | +What: /sys/fs/nilfs2/<device>/segctor/dirty_data_blocks_count | |
| 171 | +Date: April 2014 | |
| 172 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 173 | +Description: | |
| 174 | + Show number of dirty data blocks. | |
| 175 | + | |
| 176 | +What: /sys/fs/nilfs2/<device>/segctor/README | |
| 177 | +Date: April 2014 | |
| 178 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 179 | +Description: | |
| 180 | + Describe attributes of /sys/fs/nilfs2/<device>/segctor | |
| 181 | + group. | |
| 182 | + | |
| 183 | +What: /sys/fs/nilfs2/<device>/segments/segments_number | |
| 184 | +Date: April 2014 | |
| 185 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 186 | +Description: | |
| 187 | + Show number of segments on a volume. | |
| 188 | + | |
| 189 | +What: /sys/fs/nilfs2/<device>/segments/blocks_per_segment | |
| 190 | +Date: April 2014 | |
| 191 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 192 | +Description: | |
| 193 | + Show number of blocks in segment. | |
| 194 | + | |
| 195 | +What: /sys/fs/nilfs2/<device>/segments/clean_segments | |
| 196 | +Date: April 2014 | |
| 197 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 198 | +Description: | |
| 199 | + Show count of clean segments. | |
| 200 | + | |
| 201 | +What: /sys/fs/nilfs2/<device>/segments/dirty_segments | |
| 202 | +Date: April 2014 | |
| 203 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 204 | +Description: | |
| 205 | + Show count of dirty segments. | |
| 206 | + | |
| 207 | +What: /sys/fs/nilfs2/<device>/segments/README | |
| 208 | +Date: April 2014 | |
| 209 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 210 | +Description: | |
| 211 | + Describe attributes of /sys/fs/nilfs2/<device>/segments | |
| 212 | + group. | |
| 213 | + | |
| 214 | +What: /sys/fs/nilfs2/<device>/checkpoints/checkpoints_number | |
| 215 | +Date: April 2014 | |
| 216 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 217 | +Description: | |
| 218 | + Show number of checkpoints on volume. | |
| 219 | + | |
| 220 | +What: /sys/fs/nilfs2/<device>/checkpoints/snapshots_number | |
| 221 | +Date: April 2014 | |
| 222 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 223 | +Description: | |
| 224 | + Show number of snapshots on volume. | |
| 225 | + | |
| 226 | +What: /sys/fs/nilfs2/<device>/checkpoints/last_seg_checkpoint | |
| 227 | +Date: April 2014 | |
| 228 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 229 | +Description: | |
| 230 | + Show checkpoint number of the latest segment. | |
| 231 | + | |
| 232 | +What: /sys/fs/nilfs2/<device>/checkpoints/next_checkpoint | |
| 233 | +Date: April 2014 | |
| 234 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 235 | +Description: | |
| 236 | + Show next checkpoint number. | |
| 237 | + | |
| 238 | +What: /sys/fs/nilfs2/<device>/checkpoints/README | |
| 239 | +Date: April 2014 | |
| 240 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 241 | +Description: | |
| 242 | + Describe attributes of /sys/fs/nilfs2/<device>/checkpoints | |
| 243 | + group. | |
| 244 | + | |
| 245 | +What: /sys/fs/nilfs2/<device>/mounted_snapshots/README | |
| 246 | +Date: April 2014 | |
| 247 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 248 | +Description: | |
| 249 | + Describe content of /sys/fs/nilfs2/<device>/mounted_snapshots | |
| 250 | + group. | |
| 251 | + | |
| 252 | +What: /sys/fs/nilfs2/<device>/mounted_snapshots/<id>/inodes_count | |
| 253 | +Date: April 2014 | |
| 254 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 255 | +Description: | |
| 256 | + Show number of inodes for snapshot. | |
| 257 | + | |
| 258 | +What: /sys/fs/nilfs2/<device>/mounted_snapshots/<id>/blocks_count | |
| 259 | +Date: April 2014 | |
| 260 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 261 | +Description: | |
| 262 | + Show number of blocks for snapshot. | |
| 263 | + | |
| 264 | +What: /sys/fs/nilfs2/<device>/mounted_snapshots/<id>/README | |
| 265 | +Date: April 2014 | |
| 266 | +Contact: "Vyacheslav Dubeyko" <slava@dubeyko.com> | |
| 267 | +Description: | |
| 268 | + Describe attributes of /sys/fs/nilfs2/<device>/mounted_snapshots/<id> | |
| 269 | + group. | |
| @@ -0,0 +1,39 @@ | ||
| 1 | +What: /sys/fs/xfs/<disk>/log/log_head_lsn | |
| 2 | +Date: July 2014 | |
| 3 | +KernelVersion: 3.17 | |
| 4 | +Contact: xfs@oss.sgi.com | |
| 5 | +Description: | |
| 6 | + The log sequence number (LSN) of the current head of the | |
| 7 | + log. The LSN is exported in "cycle:basic block" format. | |
| 8 | +Users: xfstests | |
| 9 | + | |
| 10 | +What: /sys/fs/xfs/<disk>/log/log_tail_lsn | |
| 11 | +Date: July 2014 | |
| 12 | +KernelVersion: 3.17 | |
| 13 | +Contact: xfs@oss.sgi.com | |
| 14 | +Description: | |
| 15 | + The log sequence number (LSN) of the current tail of the | |
| 16 | + log. The LSN is exported in "cycle:basic block" format. | |
| 17 | + | |
| 18 | +What: /sys/fs/xfs/<disk>/log/reserve_grant_head | |
| 19 | +Date: July 2014 | |
| 20 | +KernelVersion: 3.17 | |
| 21 | +Contact: xfs@oss.sgi.com | |
| 22 | +Description: | |
| 23 | + The current state of the log reserve grant head. It | |
| 24 | + represents the total log reservation of all currently | |
| 25 | + outstanding transactions. The grant head is exported in | |
| 26 | + "cycle:bytes" format. | |
| 27 | +Users: xfstests | |
| 28 | + | |
| 29 | +What: /sys/fs/xfs/<disk>/log/write_grant_head | |
| 30 | +Date: July 2014 | |
| 31 | +KernelVersion: 3.17 | |
| 32 | +Contact: xfs@oss.sgi.com | |
| 33 | +Description: | |
| 34 | + The current state of the log write grant head. It | |
| 35 | + represents the total log reservation of all currently | |
| 36 | + oustanding transactions, including regrants due to | |
| 37 | + rolling transactions. The grant head is exported in | |
| 38 | + "cycle:bytes" format. | |
| 39 | +Users: xfstests | |
| @@ -315,7 +315,7 @@ char *date;</synopsis> · 314 unmodified lines | ||
| 315 | 315 | <function>drm_dev_unregister()</function> followed by a call to |
| 316 | 316 | <function>drm_dev_unref()</function>. |
| 317 | 317 | </para> |
| 318 | −!Edrivers/gpu/drm/drm_stub.c | |
| 318 | +!Edrivers/gpu/drm/drm_drv.c | |
| 319 | 319 | </sect2> |
| 320 | 320 | <sect2> |
| 321 | 321 | <title>Driver Load</title> |
| @@ -1610,7 +1610,7 @@ int max_width, max_height;</synopsis> · 1288 unmodified lines | ||
| 1610 | 1610 | The connector is then registered with a call to |
| 1611 | 1611 | <function>drm_connector_init</function> with a pointer to the connector |
| 1612 | 1612 | functions and a connector type, and exposed through sysfs with a call to |
| 1613 | − <function>drm_sysfs_connector_add</function>. | |
| 1613 | + <function>drm_connector_register</function>. | |
| 1614 | 1614 | </para> |
| 1615 | 1615 | <para> |
| 1616 | 1616 | Supported connector types are |
| @@ -1768,7 +1768,7 @@ int max_width, max_height;</synopsis> · 151 unmodified lines | ||
| 1768 | 1768 | (<function>drm_encoder_cleanup</function>) and connectors |
| 1769 | 1769 | (<function>drm_connector_cleanup</function>). Furthermore, connectors |
| 1770 | 1770 | that have been added to sysfs must be removed by a call to |
| 1771 | − <function>drm_sysfs_connector_remove</function> before calling | |
| 1771 | + <function>drm_connector_unregister</function> before calling | |
| 1772 | 1772 | <function>drm_connector_cleanup</function>. |
| 1773 | 1773 | </para> |
| 1774 | 1774 | <para> |
| @@ -1813,7 +1813,7 @@ void intel_crt_init(struct drm_device *dev) · 38 unmodified lines | ||
| 1813 | 1813 | drm_encoder_helper_add(&intel_output->enc, &intel_crt_helper_funcs); |
| 1814 | 1814 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
| 1815 | 1815 | |
| 1816 | − drm_sysfs_connector_add(connector); | |
| 1816 | + drm_connector_register(connector); | |
| 1817 | 1817 | }]]></programlisting> |
| 1818 | 1818 | <para> |
| 1819 | 1819 | In the example above (taken from the i915 driver), a CRTC, connector and |
| @@ -2336,6 +2336,12 @@ void intel_crt_init(struct drm_device *dev) · 516 unmodified lines | ||
| 2336 | 2336 | !Pdrivers/gpu/drm/drm_dp_helper.c dp helpers |
| 2337 | 2337 | !Iinclude/drm/drm_dp_helper.h |
| 2338 | 2338 | !Edrivers/gpu/drm/drm_dp_helper.c |
| 2339 | + </sect2> | |
| 2340 | + <sect2> | |
| 2341 | + <title>Display Port MST Helper Functions Reference</title> | |
| 2342 | +!Pdrivers/gpu/drm/drm_dp_mst_topology.c dp mst helper | |
| 2343 | +!Iinclude/drm/drm_dp_mst_helper.h | |
| 2344 | +!Edrivers/gpu/drm/drm_dp_mst_topology.c | |
| 2339 | 2345 | </sect2> |
| 2340 | 2346 | <sect2> |
| 2341 | 2347 | <title>EDID Helper Functions Reference</title> |
| @@ -2502,7 +2508,7 @@ void intel_crt_init(struct drm_device *dev) · 160 unmodified lines | ||
| 2502 | 2508 | <td valign="top" >Description/Restrictions</td> |
| 2503 | 2509 | </tr> |
| 2504 | 2510 | <tr> |
| 2505 | − <td rowspan="20" valign="top" >DRM</td> | |
| 2511 | + <td rowspan="21" valign="top" >DRM</td> | |
| 2506 | 2512 | <td rowspan="2" valign="top" >Generic</td> |
| 2507 | 2513 | <td valign="top" >“EDID”</td> |
| 2508 | 2514 | <td valign="top" >BLOB | IMMUTABLE</td> |
| @@ -2633,7 +2639,7 @@ void intel_crt_init(struct drm_device *dev) · 124 unmodified lines | ||
| 2633 | 2639 | <td valign="top" >TBD</td> |
| 2634 | 2640 | </tr> |
| 2635 | 2641 | <tr> |
| 2636 | − <td rowspan="2" valign="top" >Optional</td> | |
| 2642 | + <td rowspan="3" valign="top" >Optional</td> | |
| 2637 | 2643 | <td valign="top" >“scaling mode”</td> |
| 2638 | 2644 | <td valign="top" >ENUM</td> |
| 2639 | 2645 | <td valign="top" >{ "None", "Full", "Center", "Full aspect" }</td> |
| @@ -2641,6 +2647,15 @@ void intel_crt_init(struct drm_device *dev) · 1 unmodified line | ||
| 2641 | 2647 | <td valign="top" >TBD</td> |
| 2642 | 2648 | </tr> |
| 2643 | 2649 | <tr> |
| 2650 | + <td valign="top" >"aspect ratio"</td> | |
| 2651 | + <td valign="top" >ENUM</td> | |
| 2652 | + <td valign="top" >{ "None", "4:3", "16:9" }</td> | |
| 2653 | + <td valign="top" >Connector</td> | |
| 2654 | + <td valign="top" >DRM property to set aspect ratio from user space app. | |
| 2655 | + This enum is made generic to allow addition of custom aspect | |
| 2656 | + ratios.</td> | |
| 2657 | + </tr> | |
| 2658 | + <tr> | |
| 2644 | 2659 | <td valign="top" >“dirty”</td> |
| 2645 | 2660 | <td valign="top" >ENUM | IMMUTABLE</td> |
| 2646 | 2661 | <td valign="top" >{ "Off", "On", "Annotate" }</td> |
| @@ -2649,7 +2664,7 @@ void intel_crt_init(struct drm_device *dev) · 2 unmodified lines | ||
| 2649 | 2664 | </tr> |
| 2650 | 2665 | <tr> |
| 2651 | 2666 | <td rowspan="21" valign="top" >i915</td> |
| 2652 | − <td rowspan="3" valign="top" >Generic</td> | |
| 2667 | + <td rowspan="2" valign="top" >Generic</td> | |
| 2653 | 2668 | <td valign="top" >"Broadcast RGB"</td> |
| 2654 | 2669 | <td valign="top" >ENUM</td> |
| 2655 | 2670 | <td valign="top" >{ "Automatic", "Full", "Limited 16:235" }</td> |
| @@ -2664,10 +2679,11 @@ void intel_crt_init(struct drm_device *dev) · 8 unmodified lines | ||
| 2664 | 2679 | <td valign="top" >TBD</td> |
| 2665 | 2680 | </tr> |
| 2666 | 2681 | <tr> |
| 2667 | − <td valign="top" >Standard name as in DRM</td> | |
| 2668 | − <td valign="top" >Standard type as in DRM</td> | |
| 2669 | − <td valign="top" >Standard value as in DRM</td> | |
| 2670 | − <td valign="top" >Standard Object as in DRM</td> | |
| 2682 | + <td rowspan="1" valign="top" >Plane</td> | |
| 2683 | + <td valign="top" >“rotation”</td> | |
| 2684 | + <td valign="top" >BITMASK</td> | |
| 2685 | + <td valign="top" >{ 0, "rotate-0" }, { 2, "rotate-180" }</td> | |
| 2686 | + <td valign="top" >Plane</td> | |
| 2671 | 2687 | <td valign="top" >TBD</td> |
| 2672 | 2688 | </tr> |
| 2673 | 2689 | <tr> |
| @@ -2799,8 +2815,8 @@ void intel_crt_init(struct drm_device *dev) · 125 unmodified lines | ||
| 2799 | 2815 | <td valign="top" >TBD</td> |
| 2800 | 2816 | </tr> |
| 2801 | 2817 | <tr> |
| 2802 | − <td rowspan="3" valign="top" >CDV gma-500</td> | |
| 2803 | − <td rowspan="3" valign="top" >Generic</td> | |
| 2818 | + <td rowspan="2" valign="top" >CDV gma-500</td> | |
| 2819 | + <td rowspan="2" valign="top" >Generic</td> | |
| 2804 | 2820 | <td valign="top" >"Broadcast RGB"</td> |
| 2805 | 2821 | <td valign="top" >ENUM</td> |
| 2806 | 2822 | <td valign="top" >{ “Full”, “Limited 16:235” }</td> |
| @@ -2815,15 +2831,8 @@ void intel_crt_init(struct drm_device *dev) · 8 unmodified lines | ||
| 2815 | 2831 | <td valign="top" >TBD</td> |
| 2816 | 2832 | </tr> |
| 2817 | 2833 | <tr> |
| 2818 | − <td valign="top" >Standard name as in DRM</td> | |
| 2819 | − <td valign="top" >Standard type as in DRM</td> | |
| 2820 | − <td valign="top" >Standard value as in DRM</td> | |
| 2821 | − <td valign="top" >Standard Object as in DRM</td> | |
| 2822 | − <td valign="top" >TBD</td> | |
| 2823 | − </tr> | |
| 2824 | − <tr> | |
| 2825 | − <td rowspan="20" valign="top" >Poulsbo</td> | |
| 2826 | − <td rowspan="2" valign="top" >Generic</td> | |
| 2834 | + <td rowspan="19" valign="top" >Poulsbo</td> | |
| 2835 | + <td rowspan="1" valign="top" >Generic</td> | |
| 2827 | 2836 | <td valign="top" >“backlight”</td> |
| 2828 | 2837 | <td valign="top" >RANGE</td> |
| 2829 | 2838 | <td valign="top" >Min=0, Max=100</td> |
| @@ -2831,13 +2840,6 @@ void intel_crt_init(struct drm_device *dev) · 1 unmodified line | ||
| 2831 | 2840 | <td valign="top" >TBD</td> |
| 2832 | 2841 | </tr> |
| 2833 | 2842 | <tr> |
| 2834 | − <td valign="top" >Standard name as in DRM</td> | |
| 2835 | − <td valign="top" >Standard type as in DRM</td> | |
| 2836 | − <td valign="top" >Standard value as in DRM</td> | |
| 2837 | − <td valign="top" >Standard Object as in DRM</td> | |
| 2838 | − <td valign="top" >TBD</td> | |
| 2839 | − </tr> | |
| 2840 | − <tr> | |
| 2841 | 2843 | <td rowspan="17" valign="top" >SDVO-TV</td> |
| 2842 | 2844 | <td valign="top" >“mode”</td> |
| 2843 | 2845 | <td valign="top" >ENUM</td> |
| @@ -3064,7 +3066,7 @@ void intel_crt_init(struct drm_device *dev) · 220 unmodified lines | ||
| 3064 | 3066 | <td valign="top" >TBD</td> |
| 3065 | 3067 | </tr> |
| 3066 | 3068 | <tr> |
| 3067 | − <td rowspan="3" valign="top" >i2c/ch7006_drv</td> | |
| 3069 | + <td rowspan="2" valign="top" >i2c/ch7006_drv</td> | |
| 3068 | 3070 | <td valign="top" >Generic</td> |
| 3069 | 3071 | <td valign="top" >“scale”</td> |
| 3070 | 3072 | <td valign="top" >RANGE</td> |
| @@ -3073,14 +3075,7 @@ void intel_crt_init(struct drm_device *dev) · 2 unmodified lines | ||
| 3073 | 3075 | <td valign="top" >TBD</td> |
| 3074 | 3076 | </tr> |
| 3075 | 3077 | <tr> |
| 3076 | − <td rowspan="2" valign="top" >TV</td> | |
| 3077 | − <td valign="top" >Standard names as in DRM</td> | |
| 3078 | − <td valign="top" >Standard types as in DRM</td> | |
| 3079 | − <td valign="top" >Standard Values as in DRM</td> | |
| 3080 | − <td valign="top" >Standard object as in DRM</td> | |
| 3081 | − <td valign="top" >TBD</td> | |
| 3082 | − </tr> | |
| 3083 | − <tr> | |
| 3078 | + <td rowspan="1" valign="top" >TV</td> | |
| 3084 | 3079 | <td valign="top" >“mode”</td> |
| 3085 | 3080 | <td valign="top" >ENUM</td> |
| 3086 | 3081 | <td valign="top" >{ "PAL", "PAL-M","PAL-N"}, ”PAL-Nc" |
| @@ -3089,7 +3084,7 @@ void intel_crt_init(struct drm_device *dev) · 2 unmodified lines | ||
| 3089 | 3084 | <td valign="top" >TBD</td> |
| 3090 | 3085 | </tr> |
| 3091 | 3086 | <tr> |
| 3092 | − <td rowspan="16" valign="top" >nouveau</td> | |
| 3087 | + <td rowspan="15" valign="top" >nouveau</td> | |
| 3093 | 3088 | <td rowspan="6" valign="top" >NV10 Overlay</td> |
| 3094 | 3089 | <td valign="top" >"colorkey"</td> |
| 3095 | 3090 | <td valign="top" >RANGE</td> |
| @@ -3198,14 +3193,6 @@ void intel_crt_init(struct drm_device *dev) · 102 unmodified lines | ||
| 3198 | 3193 | <td valign="top" >TBD</td> |
| 3199 | 3194 | </tr> |
| 3200 | 3195 | <tr> |
| 3201 | − <td valign="top" >Generic</td> | |
| 3202 | − <td valign="top" >Standard name as in DRM</td> | |
| 3203 | − <td valign="top" >Standard type as in DRM</td> | |
| 3204 | − <td valign="top" >Standard value as in DRM</td> | |
| 3205 | − <td valign="top" >Standard Object as in DRM</td> | |
| 3206 | − <td valign="top" >TBD</td> | |
| 3207 | − </tr> | |
| 3208 | − <tr> | |
| 3209 | 3196 | <td rowspan="2" valign="top" >omap</td> |
| 3210 | 3197 | <td rowspan="2" valign="top" >Generic</td> |
| 3211 | 3198 | <td valign="top" >“rotation”</td> |
| @@ -3236,7 +3223,7 @@ void intel_crt_init(struct drm_device *dev) · 24 unmodified lines | ||
| 3236 | 3223 | <td valign="top" >TBD</td> |
| 3237 | 3224 | </tr> |
| 3238 | 3225 | <tr> |
| 3239 | − <td rowspan="10" valign="top" >radeon</td> | |
| 3226 | + <td rowspan="9" valign="top" >radeon</td> | |
| 3240 | 3227 | <td valign="top" >DVI-I</td> |
| 3241 | 3228 | <td valign="top" >“coherent”</td> |
| 3242 | 3229 | <td valign="top" >RANGE</td> |
| @@ -3308,14 +3295,6 @@ void intel_crt_init(struct drm_device *dev) · 65 unmodified lines | ||
| 3308 | 3295 | <td valign="top" >TBD</td> |
| 3309 | 3296 | </tr> |
| 3310 | 3297 | <tr> |
| 3311 | − <td valign="top" >Generic</td> | |
| 3312 | − <td valign="top" >Standard name as in DRM</td> | |
| 3313 | − <td valign="top" >Standard type as in DRM</td> | |
| 3314 | − <td valign="top" >Standard value as in DRM</td> | |
| 3315 | − <td valign="top" >Standard Object as in DRM</td> | |
| 3316 | − <td valign="top" >TBD</td> | |
| 3317 | − </tr> | |
| 3318 | − <tr> | |
| 3319 | 3298 | <td rowspan="3" valign="top" >rcar-du</td> |
| 3320 | 3299 | <td rowspan="3" valign="top" >Generic</td> |
| 3321 | 3300 | <td valign="top" >"alpha"</td> |
| @@ -576,7 +576,7 @@ Some devices are known to have faulty MSI implementations. Usually this · 575 unmodified lines | ||
| 576 | 576 | is handled in the individual device driver, but occasionally it's necessary |
| 577 | 577 | to handle this with a quirk. Some drivers have an option to disable use |
| 578 | 578 | of MSI. While this is a convenient workaround for the driver author, |
| 579 | −it is not good practise, and should not be emulated. | |
| 579 | +it is not good practice, and should not be emulated. | |
| 580 | 580 | |
| 581 | 581 | 5.4. Finding why MSIs are disabled on a device |
| 582 | 582 | |
| @@ -818,7 +818,7 @@ RCU pointer/list update: · 817 unmodified lines | ||
| 818 | 818 | list_add_tail_rcu |
| 819 | 819 | list_del_rcu |
| 820 | 820 | list_replace_rcu |
| 821 | − hlist_add_after_rcu | |
| 821 | + hlist_add_behind_rcu | |
| 822 | 822 | hlist_add_before_rcu |
| 823 | 823 | hlist_add_head_rcu |
| 824 | 824 | hlist_del_rcu |
| @@ -146,10 +146,6 @@ LWN.net: · 145 unmodified lines | ||
| 146 | 146 | Porting drivers from prior kernels to 2.6: |
| 147 | 147 | http://lwn.net/Articles/driver-porting/ |
| 148 | 148 | |
| 149 | −KernelTrap: | |
| 150 | − Occasional Linux kernel articles and developer interviews | |
| 151 | − http://kerneltrap.org/ | |
| 152 | − | |
| 153 | 149 | KernelNewbies: |
| 154 | 150 | Documentation and assistance for new kernel programmers |
| 155 | 151 | http://kernelnewbies.org/ |
| @@ -84,18 +84,42 @@ is another popular alternative. · 83 unmodified lines | ||
| 84 | 84 | |
| 85 | 85 | 2) Describe your changes. |
| 86 | 86 | |
| 87 | −Describe the technical detail of the change(s) your patch includes. | |
| 88 | − | |
| 89 | −Be as specific as possible. The WORST descriptions possible include | |
| 90 | −things like "update driver X", "bug fix for driver X", or "this patch | |
| 91 | −includes updates for subsystem X. Please apply." | |
| 87 | +Describe your problem. Whether your patch is a one-line bug fix or | |
| 88 | +5000 lines of a new feature, there must be an underlying problem that | |
| 89 | +motivated you to do this work. Convince the reviewer that there is a | |
| 90 | +problem worth fixing and that it makes sense for them to read past the | |
| 91 | +first paragraph. | |
| 92 | + | |
| 93 | +Describe user-visible impact. Straight up crashes and lockups are | |
| 94 | +pretty convincing, but not all bugs are that blatant. Even if the | |
| 95 | +problem was spotted during code review, describe the impact you think | |
| 96 | +it can have on users. Keep in mind that the majority of Linux | |
| 97 | +installations run kernels from secondary stable trees or | |
| 98 | +vendor/product-specific trees that cherry-pick only specific patches | |
| 99 | +from upstream, so include anything that could help route your change | |
| 100 | +downstream: provoking circumstances, excerpts from dmesg, crash | |
| 101 | +descriptions, performance regressions, latency spikes, lockups, etc. | |
| 102 | + | |
| 103 | +Quantify optimizations and trade-offs. If you claim improvements in | |
| 104 | +performance, memory consumption, stack footprint, or binary size, | |
| 105 | +include numbers that back them up. But also describe non-obvious | |
| 106 | +costs. Optimizations usually aren't free but trade-offs between CPU, | |
| 107 | +memory, and readability; or, when it comes to heuristics, between | |
| 108 | +different workloads. Describe the expected downsides of your | |
| 109 | +optimization so that the reviewer can weigh costs against benefits. | |
| 110 | + | |
| 111 | +Once the problem is established, describe what you are actually doing | |
| 112 | +about it in technical detail. It's important to describe the change | |
| 113 | +in plain English for the reviewer to verify that the code is behaving | |
| 114 | +as you intend it to. | |
| 92 | 115 | |
| 93 | 116 | The maintainer will thank you if you write your patch description in a |
| 94 | 117 | form which can be easily pulled into Linux's source code management |
| 95 | 118 | system, git, as a "commit log". See #15, below. |
| 96 | 119 | |
| 97 | −If your description starts to get long, that's a sign that you probably | |
| 98 | −need to split up your patch. See #3, next. | |
| 120 | +Solve only one problem per patch. If your description starts to get | |
| 121 | +long, that's a sign that you probably need to split up your patch. | |
| 122 | +See #3, next. | |
| 99 | 123 | |
| 100 | 124 | When you submit or resubmit a patch or patch series, include the |
| 101 | 125 | complete patch description and justification for it. Don't just |
| @@ -396,13 +420,13 @@ you are responsible for last-minute changes. Example : · 294 unmodified lines | ||
| 396 | 420 | [lucky@maintainer.example.org: struct foo moved from foo.c to foo.h] |
| 397 | 421 | Signed-off-by: Lucky K Maintainer <lucky@maintainer.example.org> |
| 398 | 422 | |
| 399 | −This practise is particularly helpful if you maintain a stable branch and | |
| 423 | +This practice is particularly helpful if you maintain a stable branch and | |
| 400 | 424 | want at the same time to credit the author, track changes, merge the fix, |
| 401 | 425 | and protect the submitter from complaints. Note that under no circumstances |
| 402 | 426 | can you change the author's identity (the From header), as it is the one |
| 403 | 427 | which appears in the changelog. |
| 404 | 428 | |
| 405 | −Special note to back-porters: It seems to be a common and useful practise | |
| 429 | +Special note to back-porters: It seems to be a common and useful practice | |
| 406 | 430 | to insert an indication of the origin of a patch at the top of the commit |
| 407 | 431 | message (just after the subject line) to facilitate tracking. For instance, |
| 408 | 432 | here's what we see in 2.6-stable : |
| @@ -0,0 +1,52 @@ | ||
| 1 | +ARM Cache Coherent Network | |
| 2 | +========================== | |
| 3 | + | |
| 4 | +CCN-504 is a ring-bus interconnect consisting of 11 crosspoints | |
| 5 | +(XPs), with each crosspoint supporting up to two device ports, | |
| 6 | +so nodes (devices) 0 and 1 are connected to crosspoint 0, | |
| 7 | +nodes 2 and 3 to crosspoint 1 etc. | |
| 8 | + | |
| 9 | +PMU (perf) driver | |
| 10 | +----------------- | |
| 11 | + | |
| 12 | +The CCN driver registers a perf PMU driver, which provides | |
| 13 | +description of available events and configuration options | |
| 14 | +in sysfs, see /sys/bus/event_source/devices/ccn*. | |
| 15 | + | |
| 16 | +The "format" directory describes format of the config, config1 | |
| 17 | +and config2 fields of the perf_event_attr structure. The "events" | |
| 18 | +directory provides configuration templates for all documented | |
| 19 | +events, that can be used with perf tool. For example "xp_valid_flit" | |
| 20 | +is an equivalent of "type=0x8,event=0x4". Other parameters must be | |
| 21 | +explicitly specified. For events originating from device, "node" | |
| 22 | +defines its index. All crosspoint events require "xp" (index), | |
| 23 | +"port" (device port number) and "vc" (virtual channel ID) and | |
| 24 | +"dir" (direction). Watchpoints (special "event" value 0xfe) also | |
| 25 | +require comparator values ("cmp_l" and "cmp_h") and "mask", being | |
| 26 | +index of the comparator mask. | |
| 27 | + | |
| 28 | +Masks are defined separately from the event description | |
| 29 | +(due to limited number of the config values) in the "cmp_mask" | |
| 30 | +directory, with first 8 configurable by user and additional | |
| 31 | +4 hardcoded for the most frequent use cases. | |
| 32 | + | |
| 33 | +Cycle counter is described by a "type" value 0xff and does | |
| 34 | +not require any other settings. | |
| 35 | + | |
| 36 | +Example of perf tool use: | |
| 37 | + | |
| 38 | +/ # perf list | grep ccn | |
| 39 | + ccn/cycles/ [Kernel PMU event] | |
| 40 | +<...> | |
| 41 | + ccn/xp_valid_flit/ [Kernel PMU event] | |
| 42 | +<...> | |
| 43 | + | |
| 44 | +/ # perf stat -C 0 -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \ | |
| 45 | + sleep 1 | |
| 46 | + | |
| 47 | +The driver does not support sampling, therefore "perf record" will | |
| 48 | +not work. Also notice that only single cpu is being selected | |
| 49 | +("-C 0") - this is because perf framework does not support | |
| 50 | +"non-CPU related" counters (yet?) so system-wide session ("-a") | |
| 51 | +would try (and in most cases fail) to set up the same event | |
| 52 | +per each CPU. | |
| @@ -53,8 +53,8 @@ Kirkwood family · 52 unmodified lines | ||
| 53 | 53 | Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf |
| 54 | 54 | Homepage: http://www.marvell.com/embedded-processors/kirkwood/ |
| 55 | 55 | Core: Feroceon ARMv5 compatible |
| 56 | − Linux kernel mach directory: arch/arm/mach-kirkwood | |
| 57 | − Linux kernel plat directory: arch/arm/plat-orion | |
| 56 | + Linux kernel mach directory: arch/arm/mach-mvebu | |
| 57 | + Linux kernel plat directory: none | |
| 58 | 58 | |
| 59 | 59 | Discovery family |
| 60 | 60 | ---------------- |
| @@ -83,7 +83,9 @@ EBU Armada family · 22 unmodified lines | ||
| 83 | 83 | 88F6710 |
| 84 | 84 | 88F6707 |
| 85 | 85 | 88F6W11 |
| 86 | − Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/Marvell_ARMADA_370_SoC.pdf | |
| 86 | + Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/Marvell_ARMADA_370_SoC.pdf | |
| 87 | + Hardware Spec: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA370-datasheet.pdf | |
| 88 | + Functional Spec: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA370-FunctionalSpec-datasheet.pdf | |
| 87 | 89 | |
| 88 | 90 | Armada 375 Flavors: |
| 89 | 91 | 88F6720 |
| @@ -100,8 +102,7 @@ EBU Armada family · 10 unmodified lines | ||
| 100 | 102 | MV78460 |
| 101 | 103 | NOTE: not to be confused with the non-SMP 78xx0 SoCs |
| 102 | 104 | Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf |
| 103 | − | |
| 104 | − No public datasheet available. | |
| 105 | + Functional Spec: http://www.marvell.com/embedded-processors/armada-xp/assets/ARMADA-XP-Functional-SpecDatasheet.pdf | |
| 105 | 106 | |
| 106 | 107 | Core: Sheeva ARMv7 compatible |
| 107 | 108 | |
| @@ -135,7 +136,9 @@ Dove family (application processor) · 27 unmodified lines | ||
| 135 | 136 | Functional Spec : http://www.marvell.com/application-processors/armada-500/assets/Armada-510-Functional-Spec.pdf |
| 136 | 137 | Homepage: http://www.marvell.com/application-processors/armada-500/ |
| 137 | 138 | Core: ARMv7 compatible |
| 138 | − Directory: arch/arm/mach-dove | |
| 139 | + | |
| 140 | + Directory: arch/arm/mach-mvebu (DT enabled platforms) | |
| 141 | + arch/arm/mach-dove (non-DT enabled platforms) | |
| 139 | 142 | |
| 140 | 143 | PXA 2xx/3xx/93x/95x family |
| 141 | 144 | -------------------------- |
| @@ -253,10 +256,10 @@ Berlin family (Digital Entertainment) · 111 unmodified lines | ||
| 253 | 256 | Long-term plans |
| 254 | 257 | --------------- |
| 255 | 258 | |
| 256 | − * Unify the mach-dove/, mach-mv78xx0/, mach-orion5x/ and | |
| 257 | − mach-kirkwood/ into the mach-mvebu/ to support all SoCs from the | |
| 258 | − Marvell EBU (Engineering Business Unit) in a single mach-<foo> | |
| 259 | − directory. The plat-orion/ would therefore disappear. | |
| 259 | + * Unify the mach-dove/, mach-mv78xx0/, mach-orion5x/ into the | |
| 260 | + mach-mvebu/ to support all SoCs from the Marvell EBU (Engineering | |
| 261 | + Business Unit) in a single mach-<foo> directory. The plat-orion/ | |
| 262 | + would therefore disappear. | |
| 260 | 263 | |
| 261 | 264 | * Unify the mach-mmp/ and mach-pxa/ into the same mach-pxa |
| 262 | 265 | directory. The plat-pxa/ would therefore disappear. |
| @@ -13,8 +13,6 @@ Introduction · 12 unmodified lines | ||
| 13 | 13 | |
| 14 | 14 | - S3C24XX: See Documentation/arm/Samsung-S3C24XX/Overview.txt for full list |
| 15 | 15 | - S3C64XX: S3C6400 and S3C6410 |
| 16 | − - S5P6440 | |
| 17 | − - S5PC100 | |
| 18 | 16 | - S5PC110 / S5PV210 |
| 19 | 17 | |
| 20 | 18 | |
| @@ -34,8 +32,6 @@ Configuration · 13 unmodified lines | ||
| 34 | 32 | A number of configurations are supplied, as there is no current way of |
| 35 | 33 | unifying all the SoCs into one kernel. |
| 36 | 34 | |
| 37 | − s5p6440_defconfig - S5P6440 specific default configuration | |
| 38 | − s5pc100_defconfig - S5PC100 specific default configuration | |
| 39 | 35 | s5pc110_defconfig - S5PC110 specific default configuration |
| 40 | 36 | s5pv210_defconfig - S5PV210 specific default configuration |
| 41 | 37 | |
| @@ -67,13 +63,6 @@ Layout changes · 25 unmodified lines | ||
| 67 | 63 | where to simplify the include and dependency issues involved with having |
| 68 | 64 | so many different platform directories. |
| 69 | 65 | |
| 70 | − It was decided to remove plat-s5pc1xx as some of the support was already | |
| 71 | − in plat-s5p or plat-samsung, with the S5PC110 support added with S5PV210 | |
| 72 | − the only user was the S5PC100. The S5PC100 specific items where moved to | |
| 73 | − arch/arm/mach-s5pc100. | |
| 74 | − | |
| 75 | − | |
| 76 | − | |
| 77 | 66 | |
| 78 | 67 | Port Contributors |
| 79 | 68 | ----------------- |
| @@ -68,7 +68,6 @@ BEGIN { · 67 unmodified lines | ||
| 68 | 68 | |
| 69 | 69 | while (getline line < ARGV[1] > 0) { |
| 70 | 70 | if (line ~ /\#define.*_MASK/ && |
| 71 | − !(line ~ /S5PC100_EPLL_MASK/) && | |
| 72 | 71 | !(line ~ /USB_SIG_MASK/)) { |
| 73 | 72 | splitdefine(line, fields) |
| 74 | 73 | name = fields[0] |
| @@ -168,6 +168,14 @@ Before jumping into the kernel, the following conditions must be met: · 167 unmodified lines | ||
| 168 | 168 | the kernel image will be entered must be initialised by software at a |
| 169 | 169 | higher exception level to prevent execution in an UNKNOWN state. |
| 170 | 170 | |
| 171 | + For systems with a GICv3 interrupt controller: | |
| 172 | + - If EL3 is present: | |
| 173 | + ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1. | |
| 174 | + ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1. | |
| 175 | + - If the kernel is entered at EL1: | |
| 176 | + ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1 | |
| 177 | + ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1. | |
| 178 | + | |
| 171 | 179 | The requirements described above for CPU mode, caches, MMUs, architected |
| 172 | 180 | timers, coherency and system registers apply to all CPUs. All CPUs must |
| 173 | 181 | enter the kernel in the same exception level. |
| @@ -24,64 +24,27 @@ Please note that implementation details can be changed. · 23 unmodified lines | ||
| 24 | 24 | |
| 25 | 25 | a page/swp_entry may be charged (usage += PAGE_SIZE) at |
| 26 | 26 | |
| 27 | − mem_cgroup_charge_anon() | |
| 28 | − Called at new page fault and Copy-On-Write. | |
| 29 | − | |
| 30 | − mem_cgroup_try_charge_swapin() | |
| 31 | − Called at do_swap_page() (page fault on swap entry) and swapoff. | |
| 32 | − Followed by charge-commit-cancel protocol. (With swap accounting) | |
| 33 | − At commit, a charge recorded in swap_cgroup is removed. | |
| 34 | − | |
| 35 | − mem_cgroup_charge_file() | |
| 36 | − Called at add_to_page_cache() | |
| 37 | − | |
| 38 | − mem_cgroup_cache_charge_swapin() | |
| 39 | − Called at shmem's swapin. | |
| 40 | − | |
| 41 | − mem_cgroup_prepare_migration() | |
| 42 | − Called before migration. "extra" charge is done and followed by | |
| 43 | − charge-commit-cancel protocol. | |
| 44 | − At commit, charge against oldpage or newpage will be committed. | |
| 27 | + mem_cgroup_try_charge() | |
| 45 | 28 | |
| 46 | 29 | 2. Uncharge |
| 47 | 30 | a page/swp_entry may be uncharged (usage -= PAGE_SIZE) by |
| 48 | 31 | |
| 49 | − mem_cgroup_uncharge_page() | |
| 50 | − Called when an anonymous page is fully unmapped. I.e., mapcount goes | |
| 51 | − to 0. If the page is SwapCache, uncharge is delayed until | |
| 52 | − mem_cgroup_uncharge_swapcache(). | |
| 53 | − | |
| 54 | − mem_cgroup_uncharge_cache_page() | |
| 55 | − Called when a page-cache is deleted from radix-tree. If the page is | |
| 56 | − SwapCache, uncharge is delayed until mem_cgroup_uncharge_swapcache(). | |
| 57 | − | |
| 58 | − mem_cgroup_uncharge_swapcache() | |
| 59 | − Called when SwapCache is removed from radix-tree. The charge itself | |
| 60 | − is moved to swap_cgroup. (If mem+swap controller is disabled, no | |
| 61 | − charge to swap occurs.) | |
| 32 | + mem_cgroup_uncharge() | |
| 33 | + Called when a page's refcount goes down to 0. | |
| 62 | 34 | |
| 63 | 35 | mem_cgroup_uncharge_swap() |
| 64 | 36 | Called when swp_entry's refcnt goes down to 0. A charge against swap |
| 65 | 37 | disappears. |
| 66 | 38 | |
| 67 | − mem_cgroup_end_migration(old, new) | |
| 68 | − At success of migration old is uncharged (if necessary), a charge | |
| 69 | − to new page is committed. At failure, charge to old page is committed. | |
| 70 | − | |
| 71 | 39 | 3. charge-commit-cancel |
| 72 | − In some case, we can't know this "charge" is valid or not at charging | |
| 73 | − (because of races). | |
| 74 | − To handle such case, there are charge-commit-cancel functions. | |
| 75 | − mem_cgroup_try_charge_XXX | |
| 76 | − mem_cgroup_commit_charge_XXX | |
| 77 | − mem_cgroup_cancel_charge_XXX | |
| 78 | − these are used in swap-in and migration. | |
| 40 | + Memcg pages are charged in two steps: | |
| 41 | + mem_cgroup_try_charge() | |
| 42 | + mem_cgroup_commit_charge() or mem_cgroup_cancel_charge() | |
| 79 | 43 | |
| 80 | 44 | At try_charge(), there are no flags to say "this page is charged". |
| 81 | 45 | at this point, usage += PAGE_SIZE. |
| 82 | 46 | |
| 83 | − At commit(), the function checks the page should be charged or not | |
| 84 | − and set flags or avoid charging.(usage -= PAGE_SIZE) | |
| 47 | + At commit(), the page is associated with the memcg. | |
| 85 | 48 | |
| 86 | 49 | At cancel(), simply usage -= PAGE_SIZE. |
| 87 | 50 | |
| @@ -91,18 +54,6 @@ Under below explanation, we assume CONFIG_MEM_RES_CTRL_SWAP=y. · 3 unmodified lines | ||
| 91 | 54 | Anonymous page is newly allocated at |
| 92 | 55 | - page fault into MAP_ANONYMOUS mapping. |
| 93 | 56 | - Copy-On-Write. |
| 94 | − It is charged right after it's allocated before doing any page table | |
| 95 | − related operations. Of course, it's uncharged when another page is used | |
| 96 | − for the fault address. | |
| 97 | − | |
| 98 | − At freeing anonymous page (by exit() or munmap()), zap_pte() is called | |
| 99 | − and pages for ptes are freed one by one.(see mm/memory.c). Uncharges | |
| 100 | − are done at page_remove_rmap() when page_mapcount() goes down to 0. | |
| 101 | − | |
| 102 | − Another page freeing is by page-reclaim (vmscan.c) and anonymous | |
| 103 | − pages are swapped out. In this case, the page is marked as | |
| 104 | − PageSwapCache(). uncharge() routine doesn't uncharge the page marked | |
| 105 | − as SwapCache(). It's delayed until __delete_from_swap_cache(). | |
| 106 | 57 | |
| 107 | 58 | 4.1 Swap-in. |
| 108 | 59 | At swap-in, the page is taken from swap-cache. There are 2 cases. |
| @@ -111,41 +62,6 @@ Under below explanation, we assume CONFIG_MEM_RES_CTRL_SWAP=y. · 2 unmodified lines | ||
| 111 | 62 | (b) If the SwapCache has been mapped by processes, it has been |
| 112 | 63 | charged already. |
| 113 | 64 | |
| 114 | − This swap-in is one of the most complicated work. In do_swap_page(), | |
| 115 | − following events occur when pte is unchanged. | |
| 116 | − | |
| 117 | − (1) the page (SwapCache) is looked up. | |
| 118 | − (2) lock_page() | |
| 119 | − (3) try_charge_swapin() | |
| 120 | − (4) reuse_swap_page() (may call delete_swap_cache()) | |
| 121 | − (5) commit_charge_swapin() | |
| 122 | − (6) swap_free(). | |
| 123 | − | |
| 124 | − Considering following situation for example. | |
| 125 | − | |
| 126 | − (A) The page has not been charged before (2) and reuse_swap_page() | |
| 127 | − doesn't call delete_from_swap_cache(). | |
| 128 | − (B) The page has not been charged before (2) and reuse_swap_page() | |
| 129 | − calls delete_from_swap_cache(). | |
| 130 | − (C) The page has been charged before (2) and reuse_swap_page() doesn't | |
| 131 | − call delete_from_swap_cache(). | |
| 132 | − (D) The page has been charged before (2) and reuse_swap_page() calls | |
| 133 | − delete_from_swap_cache(). | |
| 134 | − | |
| 135 | − memory.usage/memsw.usage changes to this page/swp_entry will be | |
| 136 | − Case (A) (B) (C) (D) | |
| 137 | − Event | |
| 138 | − Before (2) 0/ 1 0/ 1 1/ 1 1/ 1 | |
| 139 | − =========================================== | |
| 140 | − (3) +1/+1 +1/+1 +1/+1 +1/+1 | |
| 141 | − (4) - 0/ 0 - -1/ 0 | |
| 142 | − (5) 0/-1 0/ 0 -1/-1 0/ 0 | |
| 143 | − (6) - 0/-1 - 0/-1 | |
| 144 | − =========================================== | |
| 145 | − Result 1/ 1 1/ 1 1/ 1 1/ 1 | |
| 146 | − | |
| 147 | − In any cases, charges to this page should be 1/ 1. | |
| 148 | − | |
| 149 | 65 | 4.2 Swap-out. |
| 150 | 66 | At swap-out, typical state transition is below. |
| 151 | 67 | |
| @@ -158,28 +74,20 @@ Under below explanation, we assume CONFIG_MEM_RES_CTRL_SWAP=y. · 6 unmodified lines | ||
| 158 | 74 | swp_entry's refcnt -= 1. |
| 159 | 75 | |
| 160 | 76 | |
| 161 | − At (b), the page is marked as SwapCache and not uncharged. | |
| 162 | − At (d), the page is removed from SwapCache and a charge in page_cgroup | |
| 163 | − is moved to swap_cgroup. | |
| 164 | − | |
| 165 | 77 | Finally, at task exit, |
| 166 | 78 | (e) zap_pte() is called and swp_entry's refcnt -=1 -> 0. |
| 167 | − Here, a charge in swap_cgroup disappears. | |
| 168 | 79 | |
| 169 | 80 | 5. Page Cache |
| 170 | 81 | Page Cache is charged at |
| 171 | 82 | - add_to_page_cache_locked(). |
| 172 | 83 | |
| 173 | − uncharged at | |
| 174 | − - __remove_from_page_cache(). | |
| 175 | − | |
| 176 | 84 | The logic is very clear. (About migration, see below) |
| 177 | 85 | Note: __remove_from_page_cache() is called by remove_from_page_cache() |
| 178 | 86 | and __remove_mapping(). |
| 179 | 87 | |
| 180 | 88 | 6. Shmem(tmpfs) Page Cache |
| 181 | − Memcg's charge/uncharge have special handlers of shmem. The best way | |
| 182 | − to understand shmem's page state transition is to read mm/shmem.c. | |
| 89 | + The best way to understand shmem's page state transition is to read | |
| 90 | + mm/shmem.c. | |
| 183 | 91 | But brief explanation of the behavior of memcg around shmem will be |
| 184 | 92 | helpful to understand the logic. |
| 185 | 93 | |
| @@ -192,56 +100,10 @@ Under below explanation, we assume CONFIG_MEM_RES_CTRL_SWAP=y. · 6 unmodified lines | ||
| 192 | 100 | It's charged when... |
| 193 | 101 | - A new page is added to shmem's radix-tree. |
| 194 | 102 | - A swp page is read. (move a charge from swap_cgroup to page_cgroup) |
| 195 | − It's uncharged when | |
| 196 | − - A page is removed from radix-tree and not SwapCache. | |
| 197 | − - When SwapCache is removed, a charge is moved to swap_cgroup. | |
| 198 | − - When swp_entry's refcnt goes down to 0, a charge in swap_cgroup | |
| 199 | − disappears. | |
| 200 | 103 | |
| 201 | 104 | 7. Page Migration |
| 202 | − One of the most complicated functions is page-migration-handler. | |
| 203 | − Memcg has 2 routines. Assume that we are migrating a page's contents | |
| 204 | − from OLDPAGE to NEWPAGE. | |
| 205 | − | |
| 206 | − Usual migration logic is.. | |
| 207 | − (a) remove the page from LRU. | |
| 208 | − (b) allocate NEWPAGE (migration target) | |
| 209 | − (c) lock by lock_page(). | |
| 210 | − (d) unmap all mappings. | |
| 211 | − (e-1) If necessary, replace entry in radix-tree. | |
| 212 | − (e-2) move contents of a page. | |
| 213 | − (f) map all mappings again. | |
| 214 | − (g) pushback the page to LRU. | |
| 215 | − (-) OLDPAGE will be freed. | |
| 216 | − | |
| 217 | − Before (g), memcg should complete all necessary charge/uncharge to | |
| 218 | − NEWPAGE/OLDPAGE. | |
| 219 | − | |
| 220 | − The point is.... | |
| 221 | − - If OLDPAGE is anonymous, all charges will be dropped at (d) because | |
| 222 | − try_to_unmap() drops all mapcount and the page will not be | |
| 223 | − SwapCache. | |
| 224 | − | |
| 225 | − - If OLDPAGE is SwapCache, charges will be kept at (g) because | |
| 226 | − __delete_from_swap_cache() isn't called at (e-1) | |
| 227 | − | |
| 228 | − - If OLDPAGE is page-cache, charges will be kept at (g) because | |
| 229 | − remove_from_swap_cache() isn't called at (e-1) | |
| 230 | − | |
| 231 | − memcg provides following hooks. | |
| 232 | − | |
| 233 | − - mem_cgroup_prepare_migration(OLDPAGE) | |
| 234 | − Called after (b) to account a charge (usage += PAGE_SIZE) against | |
| 235 | − memcg which OLDPAGE belongs to. | |
| 236 | − | |
| 237 | − - mem_cgroup_end_migration(OLDPAGE, NEWPAGE) | |
| 238 | − Called after (f) before (g). | |
| 239 | − If OLDPAGE is used, commit OLDPAGE again. If OLDPAGE is already | |
| 240 | − charged, a charge by prepare_migration() is automatically canceled. | |
| 241 | − If NEWPAGE is used, commit NEWPAGE and uncharge OLDPAGE. | |
| 242 | − | |
| 243 | − But zap_pte() (by exit or munmap) can be called while migration, | |
| 244 | − we have to check if OLDPAGE/NEWPAGE is a valid page after commit(). | |
| 105 | + | |
| 106 | + mem_cgroup_migrate() | |
| 245 | 107 | |
| 246 | 108 | 8. LRU |
| 247 | 109 | Each memcg has its own private LRU. Now, its handling is under global |
| @@ -106,6 +106,11 @@ which paths. · 105 unmodified lines | ||
| 106 | 106 | The path number in the range 0 ... (<num_paths> - 1). |
| 107 | 107 | Expressed in hexadecimal (WITHOUT any prefix like 0x). |
| 108 | 108 | |
| 109 | +R<n>,<m> | |
| 110 | + This parameter allows repetitive patterns to be loaded quickly. <n> and <m> | |
| 111 | + are hexadecimal numbers. The last <n> mappings are repeated in the next <m> | |
| 112 | + slots. | |
| 113 | + | |
| 109 | 114 | Status |
| 110 | 115 | ====== |
| 111 | 116 | |
| @@ -124,3 +129,10 @@ Create a switch device with 64kB region size: · 12 unmodified lines | ||
| 124 | 129 | Set mappings for the first 7 entries to point to devices switch0, switch1, |
| 125 | 130 | switch2, switch0, switch1, switch2, switch1: |
| 126 | 131 | dmsetup message switch 0 set_region_mappings 0:0 :1 :2 :0 :1 :2 :1 |
| 132 | + | |
| 133 | +Set repetitive mapping. This command: | |
| 134 | + dmsetup message switch 0 set_region_mappings 1000:1 :2 R2,10 | |
| 135 | +is equivalent to: | |
| 136 | + dmsetup message switch 0 set_region_mappings 1000:1 :2 :1 :2 :1 :2 :1 :2 \ | |
| 137 | + :1 :2 :1 :2 :1 :2 :1 :2 :1 :2 | |
| 138 | + | |
| @@ -0,0 +1,7 @@ | ||
| 1 | +Adapteva Platforms Device Tree Bindings | |
| 2 | +--------------------------------------- | |
| 3 | + | |
| 4 | +Parallella board | |
| 5 | + | |
| 6 | +Required root node properties: | |
| 7 | + - compatible = "adapteva,parallella"; | |
| @@ -86,3 +86,9 @@ Interrupt controllers: · 85 unmodified lines | ||
| 86 | 86 | compatible = "arm,versatile-sic"; |
| 87 | 87 | interrupt-controller; |
| 88 | 88 | #interrupt-cells = <1>; |
| 89 | + | |
| 90 | +Required nodes: | |
| 91 | + | |
| 92 | +- core-module: the root node to the Versatile platforms must have | |
| 93 | + a core-module with regs and the compatible strings | |
| 94 | + "arm,core-module-versatile", "syscon" | |
| @@ -0,0 +1,14 @@ | ||
| 1 | +Marvell Armada 38x CA9 MPcore SoC Controller | |
| 2 | +============================================ | |
| 3 | + | |
| 4 | +Required properties: | |
| 5 | + | |
| 6 | +- compatible: Should be "marvell,armada-380-mpcore-soc-ctrl". | |
| 7 | + | |
| 8 | +- reg: should be the register base and length as documented in the | |
| 9 | + datasheet for the CA9 MPcore SoC Control registers | |
| 10 | + | |
| 11 | +mpcore-soc-ctrl@20d20 { | |
| 12 | + compatible = "marvell,armada-380-mpcore-soc-ctrl"; | |
| 13 | + reg = <0x20d20 0x6c>; | |
| 14 | +}; | |
| @@ -1,7 +1,10 @@ | ||
| 1 | 1 | * Power Management Controller (PMC) |
| 2 | 2 | |
| 3 | 3 | Required properties: |
| 4 | −- compatible: Should be "atmel,at91rm9200-pmc" | |
| 4 | +- compatible: Should be "atmel,<chip>-pmc". | |
| 5 | + <chip> can be: at91rm9200, at91sam9260, at91sam9g45, at91sam9n12, | |
| 6 | + at91sam9x5, sama5d3 | |
| 7 | + | |
| 5 | 8 | - reg: Should contain PMC registers location and length |
| 6 | 9 | |
| 7 | 10 | Examples: |
| @@ -0,0 +1,36 @@ | ||
| 1 | +Broadcom Kona Family CPU Enable Method | |
| 2 | +-------------------------------------- | |
| 3 | +This binding defines the enable method used for starting secondary | |
| 4 | +CPUs in the following Broadcom SoCs: | |
| 5 | + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664 | |
| 6 | + | |
| 7 | +The enable method is specified by defining the following required | |
| 8 | +properties in the "cpus" device tree node: | |
| 9 | + - enable-method = "brcm,bcm11351-cpu-method"; | |
| 10 | + - secondary-boot-reg = <...>; | |
| 11 | + | |
| 12 | +The secondary-boot-reg property is a u32 value that specifies the | |
| 13 | +physical address of the register used to request the ROM holding pen | |
| 14 | +code release a secondary CPU. The value written to the register is | |
| 15 | +formed by encoding the target CPU id into the low bits of the | |
| 16 | +physical start address it should jump to. | |
| 17 | + | |
| 18 | +Example: | |
| 19 | + cpus { | |
| 20 | + #address-cells = <1>; | |
| 21 | + #size-cells = <0>; | |
| 22 | + enable-method = "brcm,bcm11351-cpu-method"; | |
| 23 | + secondary-boot-reg = <0x3500417c>; | |
| 24 | + | |
| 25 | + cpu0: cpu@0 { | |
| 26 | + device_type = "cpu"; | |
| 27 | + compatible = "arm,cortex-a9"; | |
| 28 | + reg = <0>; | |
| 29 | + }; | |
| 30 | + | |
| 31 | + cpu1: cpu@1 { | |
| 32 | + device_type = "cpu"; | |
| 33 | + compatible = "arm,cortex-a9"; | |
| 34 | + reg = <1>; | |
| 35 | + }; | |
| 36 | + }; | |
| @@ -0,0 +1,95 @@ | ||
| 1 | +ARM Broadcom STB platforms Device Tree Bindings | |
| 2 | +----------------------------------------------- | |
| 3 | +Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants) | |
| 4 | +SoC shall have the following DT organization: | |
| 5 | + | |
| 6 | +Required root node properties: | |
| 7 | + - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb" | |
| 8 | + | |
| 9 | +example: | |
| 10 | +/ { | |
| 11 | + #address-cells = <2>; | |
| 12 | + #size-cells = <2>; | |
| 13 | + model = "Broadcom STB (bcm7445)"; | |
| 14 | + compatible = "brcm,bcm7445", "brcm,brcmstb"; | |
| 15 | + | |
| 16 | +Further, syscon nodes that map platform-specific registers used for general | |
| 17 | +system control is required: | |
| 18 | + | |
| 19 | + - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon" | |
| 20 | + - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon" | |
| 21 | + - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon" | |
| 22 | + | |
| 23 | +example: | |
| 24 | + rdb { | |
| 25 | + #address-cells = <1>; | |
| 26 | + #size-cells = <1>; | |
| 27 | + compatible = "simple-bus"; | |
| 28 | + ranges = <0 0x00 0xf0000000 0x1000000>; | |
| 29 | + | |
| 30 | + sun_top_ctrl: syscon@404000 { | |
| 31 | + compatible = "brcm,bcm7445-sun-top-ctrl", "syscon"; | |
| 32 | + reg = <0x404000 0x51c>; | |
| 33 | + }; | |
| 34 | + | |
| 35 | + hif_cpubiuctrl: syscon@3e2400 { | |
| 36 | + compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon"; | |
| 37 | + reg = <0x3e2400 0x5b4>; | |
| 38 | + }; | |
| 39 | + | |
| 40 | + hif_continuation: syscon@452000 { | |
| 41 | + compatible = "brcm,bcm7445-hif-continuation", "syscon"; | |
| 42 | + reg = <0x452000 0x100>; | |
| 43 | + }; | |
| 44 | + }; | |
| 45 | + | |
| 46 | +Lastly, nodes that allow for support of SMP initialization and reboot are | |
| 47 | +required: | |
| 48 | + | |
| 49 | +smpboot | |
| 50 | +------- | |
| 51 | +Required properties: | |
| 52 | + | |
| 53 | + - compatible | |
| 54 | + The string "brcm,brcmstb-smpboot". | |
| 55 | + | |
| 56 | + - syscon-cpu | |
| 57 | + A phandle / integer array property which lets the BSP know the location | |
| 58 | + of certain CPU power-on registers. | |
| 59 | + | |
| 60 | + The layout of the property is as follows: | |
| 61 | + o a phandle to the "hif_cpubiuctrl" syscon node | |
| 62 | + o offset to the base CPU power zone register | |
| 63 | + o offset to the base CPU reset register | |
| 64 | + | |
| 65 | + - syscon-cont | |
| 66 | + A phandle pointing to the syscon node which describes the CPU boot | |
| 67 | + continuation registers. | |
| 68 | + o a phandle to the "hif_continuation" syscon node | |
| 69 | + | |
| 70 | +example: | |
| 71 | + smpboot { | |
| 72 | + compatible = "brcm,brcmstb-smpboot"; | |
| 73 | + syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; | |
| 74 | + syscon-cont = <&hif_continuation>; | |
| 75 | + }; | |
| 76 | + | |
| 77 | +reboot | |
| 78 | +------- | |
| 79 | +Required properties | |
| 80 | + | |
| 81 | + - compatible | |
| 82 | + The string property "brcm,brcmstb-reboot". | |
| 83 | + | |
| 84 | + - syscon | |
| 85 | + A phandle / integer array that points to the syscon node which describes | |
| 86 | + the general system reset registers. | |
| 87 | + o a phandle to "sun_top_ctrl" | |
| 88 | + o offset to the "reset source enable" register | |
| 89 | + o offset to the "software master reset" register | |
| 90 | + | |
| 91 | +example: | |
| 92 | + reboot { | |
| 93 | + compatible = "brcm,brcmstb-reboot"; | |
| 94 | + syscon = <&sun_top_ctrl 0x304 0x308>; | |
| 95 | + }; | |
| @@ -0,0 +1,21 @@ | ||
| 1 | +* ARM CCN (Cache Coherent Network) | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | + | |
| 5 | +- compatible: (standard compatible string) should be one of: | |
| 6 | + "arm,ccn-504" | |
| 7 | + "arm,ccn-508" | |
| 8 | + | |
| 9 | +- reg: (standard registers property) physical address and size | |
| 10 | + (16MB) of the configuration registers block | |
| 11 | + | |
| 12 | +- interrupts: (standard interrupt property) single interrupt | |
| 13 | + generated by the control block | |
| 14 | + | |
| 15 | +Example: | |
| 16 | + | |
| 17 | + ccn@0x2000000000 { | |
| 18 | + compatible = "arm,ccn-504"; | |
| 19 | + reg = <0x20 0x00000000 0 0x1000000>; | |
| 20 | + interrupts = <0 181 4>; | |
| 21 | + }; | |
| @@ -0,0 +1,41 @@ | ||
| 1 | +======================================================== | |
| 2 | +Secondary CPU enable-method "marvell,berlin-smp" binding | |
| 3 | +======================================================== | |
| 4 | + | |
| 5 | +This document describes the "marvell,berlin-smp" method for enabling secondary | |
| 6 | +CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should | |
| 7 | +be defined in the "cpus" node. | |
| 8 | + | |
| 9 | +Enable method name: "marvell,berlin-smp" | |
| 10 | +Compatible machines: "marvell,berlin2" and "marvell,berlin2q" | |
| 11 | +Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9" | |
| 12 | +Related properties: (none) | |
| 13 | + | |
| 14 | +Note: | |
| 15 | +This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and | |
| 16 | +"marvell,berlin-cpu-ctrl"[1]. | |
| 17 | + | |
| 18 | +Example: | |
| 19 | + | |
| 20 | + cpus { | |
| 21 | + #address-cells = <1>; | |
| 22 | + #size-cells = <0>; | |
| 23 | + enable-method = "marvell,berlin-smp"; | |
| 24 | + | |
| 25 | + cpu@0 { | |
| 26 | + compatible = "marvell,pj4b"; | |
| 27 | + device_type = "cpu"; | |
| 28 | + next-level-cache = <&l2>; | |
| 29 | + reg = <0>; | |
| 30 | + }; | |
| 31 | + | |
| 32 | + cpu@1 { | |
| 33 | + compatible = "marvell,pj4b"; | |
| 34 | + device_type = "cpu"; | |
| 35 | + next-level-cache = <&l2>; | |
| 36 | + reg = <1>; | |
| 37 | + }; | |
| 38 | + }; | |
| 39 | + | |
| 40 | +-- | |
| 41 | +[1] arm/marvell,berlin.txt | |
| @@ -152,7 +152,9 @@ nodes to be present and contain the properties described below. · 151 unmodified lines | ||
| 152 | 152 | "arm,cortex-a7" |
| 153 | 153 | "arm,cortex-a8" |
| 154 | 154 | "arm,cortex-a9" |
| 155 | + "arm,cortex-a12" | |
| 155 | 156 | "arm,cortex-a15" |
| 157 | + "arm,cortex-a17" | |
| 156 | 158 | "arm,cortex-a53" |
| 157 | 159 | "arm,cortex-a57" |
| 158 | 160 | "arm,cortex-m0" |
| @@ -163,6 +165,7 @@ nodes to be present and contain the properties described below. · 4 unmodified lines | ||
| 163 | 165 | "arm,cortex-r4" |
| 164 | 166 | "arm,cortex-r5" |
| 165 | 167 | "arm,cortex-r7" |
| 168 | + "brcm,brahma-b15" | |
| 166 | 169 | "faraday,fa526" |
| 167 | 170 | "intel,sa110" |
| 168 | 171 | "intel,sa1100" |
| @@ -184,6 +187,7 @@ nodes to be present and contain the properties described below. · 15 unmodified lines | ||
| 184 | 187 | can be one of: |
| 185 | 188 | "allwinner,sun6i-a31" |
| 186 | 189 | "arm,psci" |
| 190 | + "brcm,brahma-b15" | |
| 187 | 191 | "marvell,armada-375-smp" |
| 188 | 192 | "marvell,armada-380-smp" |
| 189 | 193 | "marvell,armada-xp-smp" |
| @@ -0,0 +1,79 @@ | ||
| 1 | +* ARM Generic Interrupt Controller, version 3 | |
| 2 | + | |
| 3 | +AArch64 SMP cores are often associated with a GICv3, providing Private | |
| 4 | +Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI), | |
| 5 | +Software Generated Interrupts (SGI), and Locality-specific Peripheral | |
| 6 | +Interrupts (LPI). | |
| 7 | + | |
| 8 | +Main node required properties: | |
| 9 | + | |
| 10 | +- compatible : should at least contain "arm,gic-v3". | |
| 11 | +- interrupt-controller : Identifies the node as an interrupt controller | |
| 12 | +- #interrupt-cells : Specifies the number of cells needed to encode an | |
| 13 | + interrupt source. Must be a single cell with a value of at least 3. | |
| 14 | + | |
| 15 | + The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI | |
| 16 | + interrupts. Other values are reserved for future use. | |
| 17 | + | |
| 18 | + The 2nd cell contains the interrupt number for the interrupt type. | |
| 19 | + SPI interrupts are in the range [0-987]. PPI interrupts are in the | |
| 20 | + range [0-15]. | |
| 21 | + | |
| 22 | + The 3rd cell is the flags, encoded as follows: | |
| 23 | + bits[3:0] trigger type and level flags. | |
| 24 | + 1 = edge triggered | |
| 25 | + 4 = level triggered | |
| 26 | + | |
| 27 | + Cells 4 and beyond are reserved for future use. When the 1st cell | |
| 28 | + has a value of 0 or 1, cells 4 and beyond act as padding, and may be | |
| 29 | + ignored. It is recommended that padding cells have a value of 0. | |
| 30 | + | |
| 31 | +- reg : Specifies base physical address(s) and size of the GIC | |
| 32 | + registers, in the following order: | |
| 33 | + - GIC Distributor interface (GICD) | |
| 34 | + - GIC Redistributors (GICR), one range per redistributor region | |
| 35 | + - GIC CPU interface (GICC) | |
| 36 | + - GIC Hypervisor interface (GICH) | |
| 37 | + - GIC Virtual CPU interface (GICV) | |
| 38 | + | |
| 39 | + GICC, GICH and GICV are optional. | |
| 40 | + | |
| 41 | +- interrupts : Interrupt source of the VGIC maintenance interrupt. | |
| 42 | + | |
| 43 | +Optional | |
| 44 | + | |
| 45 | +- redistributor-stride : If using padding pages, specifies the stride | |
| 46 | + of consecutive redistributors. Must be a multiple of 64kB. | |
| 47 | + | |
| 48 | +- #redistributor-regions: The number of independent contiguous regions | |
| 49 | + occupied by the redistributors. Required if more than one such | |
| 50 | + region is present. | |
| 51 | + | |
| 52 | +Examples: | |
| 53 | + | |
| 54 | + gic: interrupt-controller@2cf00000 { | |
| 55 | + compatible = "arm,gic-v3"; | |
| 56 | + #interrupt-cells = <3>; | |
| 57 | + interrupt-controller; | |
| 58 | + reg = <0x0 0x2f000000 0 0x10000>, // GICD | |
| 59 | + <0x0 0x2f100000 0 0x200000>, // GICR | |
| 60 | + <0x0 0x2c000000 0 0x2000>, // GICC | |
| 61 | + <0x0 0x2c010000 0 0x2000>, // GICH | |
| 62 | + <0x0 0x2c020000 0 0x2000>; // GICV | |
| 63 | + interrupts = <1 9 4>; | |
| 64 | + }; | |
| 65 | + | |
| 66 | + gic: interrupt-controller@2c010000 { | |
| 67 | + compatible = "arm,gic-v3"; | |
| 68 | + #interrupt-cells = <3>; | |
| 69 | + interrupt-controller; | |
| 70 | + redistributor-stride = <0x0 0x40000>; // 256kB stride | |
| 71 | + #redistributor-regions = <2>; | |
| 72 | + reg = <0x0 0x2c010000 0 0x10000>, // GICD | |
| 73 | + <0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31 | |
| 74 | + <0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63 | |
| 75 | + <0x0 0x2c040000 0 0x2000>, // GICC | |
| 76 | + <0x0 0x2c060000 0 0x2000>, // GICH | |
| 77 | + <0x0 0x2c080000 0 0x2000>; // GICV | |
| 78 | + interrupts = <1 9 4>; | |
| 79 | + }; | |
| @@ -16,6 +16,7 @@ Main node required properties: · 15 unmodified lines | ||
| 16 | 16 | "arm,cortex-a9-gic" |
| 17 | 17 | "arm,cortex-a7-gic" |
| 18 | 18 | "arm,arm11mp-gic" |
| 19 | + "brcm,brahma-b15-gic" | |
| 19 | 20 | - interrupt-controller : Identifies the node as an interrupt controller |
| 20 | 21 | - #interrupt-cells : Specifies the number of cells needed to encode an |
| 21 | 22 | interrupt source. The type shall be a <u32> and the value shall be 3. |
| @@ -31,6 +31,17 @@ Example: · 30 unmodified lines | ||
| 31 | 31 | reboot-offset = <0x4>; |
| 32 | 32 | }; |
| 33 | 33 | |
| 34 | +----------------------------------------------------------------------- | |
| 35 | +Hisilicon CPU controller | |
| 36 | + | |
| 37 | +Required properties: | |
| 38 | +- compatible : "hisilicon,cpuctrl" | |
| 39 | +- reg : Register address and size | |
| 40 | + | |
| 41 | +The clock registers and power registers of secondary cores are defined | |
| 42 | +in CPU controller, especially in HIX5HD2 SoC. | |
| 43 | + | |
| 44 | +----------------------------------------------------------------------- | |
| 34 | 45 | PCTRL: Peripheral misc control register |
| 35 | 46 | |
| 36 | 47 | Required Properties: |
| @@ -24,6 +24,22 @@ SoC and board used. Currently known SoC compatibles are: · 23 unmodified lines | ||
| 24 | 24 | ... |
| 25 | 25 | } |
| 26 | 26 | |
| 27 | +* Marvell Berlin CPU control bindings | |
| 28 | + | |
| 29 | +CPU control register allows various operations on CPUs, like resetting them | |
| 30 | +independently. | |
| 31 | + | |
| 32 | +Required properties: | |
| 33 | +- compatible: should be "marvell,berlin-cpu-ctrl" | |
| 34 | +- reg: address and length of the register set | |
| 35 | + | |
| 36 | +Example: | |
| 37 | + | |
| 38 | +cpu-ctrl@f7dd0000 { | |
| 39 | + compatible = "marvell,berlin-cpu-ctrl"; | |
| 40 | + reg = <0xf7dd0000 0x10000>; | |
| 41 | +}; | |
| 42 | + | |
| 27 | 43 | * Marvell Berlin2 chip control binding |
| 28 | 44 | |
| 29 | 45 | Marvell Berlin SoCs have a chip control register set providing several |
| @@ -0,0 +1,8 @@ | ||
| 1 | +Mediatek MT6589 Platforms Device Tree Bindings | |
| 2 | + | |
| 3 | +Boards with a SoC of the Mediatek MT6589 shall have the following property: | |
| 4 | + | |
| 5 | +Required root node property: | |
| 6 | + | |
| 7 | +compatible: must contain "mediatek,mt6589" | |
| 8 | + | |
| @@ -129,6 +129,9 @@ Boards: · 128 unmodified lines | ||
| 129 | 129 | - AM437x GP EVM |
| 130 | 130 | compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43" |
| 131 | 131 | |
| 132 | +- AM437x SK EVM: AM437x StarterKit Evaluation Module | |
| 133 | + compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43" | |
| 134 | + | |
| 132 | 135 | - DRA742 EVM: Software Development Board for DRA742 |
| 133 | 136 | compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7" |
| 134 | 137 | |
| @@ -0,0 +1,65 @@ | ||
| 1 | +OMAP PRCM bindings | |
| 2 | + | |
| 3 | +Power Reset and Clock Manager lists the device clocks and clockdomains under | |
| 4 | +a DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it, | |
| 5 | +each describing one module and the clock hierarchy under it. see [1] for | |
| 6 | +documentation about the individual clock/clockdomain nodes. | |
| 7 | + | |
| 8 | +[1] Documentation/devicetree/bindings/clock/ti/* | |
| 9 | + | |
| 10 | +Required properties: | |
| 11 | +- compatible: Must be one of: | |
| 12 | + "ti,am3-prcm" | |
| 13 | + "ti,am3-scrm" | |
| 14 | + "ti,am4-prcm" | |
| 15 | + "ti,am4-scrm" | |
| 16 | + "ti,omap2-prcm" | |
| 17 | + "ti,omap2-scrm" | |
| 18 | + "ti,omap3-prm" | |
| 19 | + "ti,omap3-cm" | |
| 20 | + "ti,omap3-scrm" | |
| 21 | + "ti,omap4-cm1" | |
| 22 | + "ti,omap4-prm" | |
| 23 | + "ti,omap4-cm2" | |
| 24 | + "ti,omap4-scrm" | |
| 25 | + "ti,omap5-prm" | |
| 26 | + "ti,omap5-cm-core-aon" | |
| 27 | + "ti,omap5-scrm" | |
| 28 | + "ti,omap5-cm-core" | |
| 29 | + "ti,dra7-prm" | |
| 30 | + "ti,dra7-cm-core-aon" | |
| 31 | + "ti,dra7-cm-core" | |
| 32 | +- reg: Contains PRCM module register address range | |
| 33 | + (base address and length) | |
| 34 | +- clocks: clocks for this module | |
| 35 | +- clockdomains: clockdomains for this module | |
| 36 | + | |
| 37 | +Example: | |
| 38 | + | |
| 39 | +cm: cm@48004000 { | |
| 40 | + compatible = "ti,omap3-cm"; | |
| 41 | + reg = <0x48004000 0x4000>; | |
| 42 | + | |
| 43 | + cm_clocks: clocks { | |
| 44 | + #address-cells = <1>; | |
| 45 | + #size-cells = <0>; | |
| 46 | + }; | |
| 47 | + | |
| 48 | + cm_clockdomains: clockdomains { | |
| 49 | + }; | |
| 50 | +} | |
| 51 | + | |
| 52 | +&cm_clocks { | |
| 53 | + omap2_32k_fck: omap_32k_fck { | |
| 54 | + #clock-cells = <0>; | |
| 55 | + compatible = "fixed-clock"; | |
| 56 | + clock-frequency = <32768>; | |
| 57 | + }; | |
| 58 | +}; | |
| 59 | + | |
| 60 | +&cm_clockdomains { | |
| 61 | + core_l3_clkdm: core_l3_clkdm { | |
| 62 | + compatible = "ti,clockdomain"; | |
| 63 | + clocks = <&sdrc_ick>; | |
| 64 | + }; | |
| 65 | +}; | |
| @@ -7,6 +7,8 @@ Properties: · 6 unmodified lines | ||
| 7 | 7 | - "samsung,exynos4212-pmu" - for Exynos4212 SoC, |
| 8 | 8 | - "samsung,exynos4412-pmu" - for Exynos4412 SoC, |
| 9 | 9 | - "samsung,exynos5250-pmu" - for Exynos5250 SoC, |
| 10 | + - "samsung,exynos5260-pmu" - for Exynos5260 SoC. | |
| 11 | + - "samsung,exynos5410-pmu" - for Exynos5410 SoC, | |
| 10 | 12 | - "samsung,exynos5420-pmu" - for Exynos5420 SoC. |
| 11 | 13 | second value must be always "syscon". |
| 12 | 14 | |
| @@ -0,0 +1,9 @@ | ||
| 1 | +SPEAr Misc configuration | |
| 2 | +=========================== | |
| 3 | +SPEAr SOCs have some miscellaneous registers which are used to configure | |
| 4 | +few properties of different peripheral controllers. | |
| 5 | + | |
| 6 | +misc node required properties: | |
| 7 | + | |
| 8 | +- compatible Should be "st,spear1340-misc", "syscon". | |
| 9 | +- reg: Address range of misc space upto 8K | |
| @@ -30,6 +30,8 @@ board-specific compatible values: · 29 unmodified lines | ||
| 30 | 30 | nvidia,seaboard |
| 31 | 31 | nvidia,ventana |
| 32 | 32 | nvidia,whistler |
| 33 | + toradex,apalis_t30 | |
| 34 | + toradex,apalis_t30-eval | |
| 33 | 35 | toradex,colibri_t20-512 |
| 34 | 36 | toradex,iris |
| 35 | 37 | |
| @@ -1,7 +1,7 @@ | ||
| 1 | −Xilinx Zynq EP107 Emulation Platform board | |
| 1 | +Xilinx Zynq Platforms Device Tree Bindings | |
| 2 | 2 | |
| 3 | −This board is an emulation platform for the Zynq product which is | |
| 4 | −based on an ARM Cortex A9 processor. | |
| 3 | +Boards with Zynq-7000 SOC based on an ARM Cortex A9 processor | |
| 4 | +shall have the following properties. | |
| 5 | 5 | |
| 6 | 6 | Required root node properties: |
| 7 | − - compatible = "xlnx,zynq-ep107"; | |
| 7 | + - compatible = "xlnx,zynq-7000"; | |
| @@ -1,4 +1,4 @@ | ||
| 1 | −Clock bindings for ARM Integrator Core Module clocks | |
| 1 | +Clock bindings for ARM Integrator and Versatile Core Module clocks | |
| 2 | 2 | |
| 3 | 3 | Auxilary Oscillator Clock |
| 4 | 4 | |
| @@ -12,7 +12,7 @@ parent node. · 7 unmodified lines | ||
| 12 | 12 | |
| 13 | 13 | |
| 14 | 14 | Required properties: |
| 15 | −- compatible: must be "arm,integrator-cm-auxosc" | |
| 15 | +- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc" | |
| 16 | 16 | - #clock-cells: must be <0> |
| 17 | 17 | |
| 18 | 18 | Optional properties: |
| @@ -0,0 +1,53 @@ | ||
| 1 | +* Samsung Audio Subsystem Clock Controller | |
| 2 | + | |
| 3 | +The Samsung Audio Subsystem clock controller generates and supplies clocks | |
| 4 | +to Audio Subsystem block available in the S5PV210 and compatible SoCs. | |
| 5 | + | |
| 6 | +Required Properties: | |
| 7 | + | |
| 8 | +- compatible: should be "samsung,s5pv210-audss-clock". | |
| 9 | +- reg: physical base address and length of the controller's register set. | |
| 10 | + | |
| 11 | +- #clock-cells: should be 1. | |
| 12 | + | |
| 13 | +- clocks: | |
| 14 | + - hclk: AHB bus clock of the Audio Subsystem. | |
| 15 | + - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If | |
| 16 | + not specified (i.e. xusbxti is used for PLL reference), it is fixed to | |
| 17 | + a clock named "xxti". | |
| 18 | + - fout_epll: Input PLL to the AudioSS block, parent of mout_audss. | |
| 19 | + - iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not | |
| 20 | + specified, it is fixed to a clock named "iiscdclk0". | |
| 21 | + - sclk_audio0: Audio bus clock, parent of mout_i2s. | |
| 22 | + | |
| 23 | +- clock-names: Aliases for the above clocks. They should be "hclk", | |
| 24 | + "xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively. | |
| 25 | + | |
| 26 | +All available clocks are defined as preprocessor macros in | |
| 27 | +dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device | |
| 28 | +tree sources. | |
| 29 | + | |
| 30 | +Example: Clock controller node. | |
| 31 | + | |
| 32 | + clk_audss: clock-controller@c0900000 { | |
| 33 | + compatible = "samsung,s5pv210-audss-clock"; | |
| 34 | + reg = <0xc0900000 0x1000>; | |
| 35 | + #clock-cells = <1>; | |
| 36 | + clock-names = "hclk", "xxti", | |
| 37 | + "fout_epll", "sclk_audio0"; | |
| 38 | + clocks = <&clocks DOUT_HCLKP>, <&xxti>, | |
| 39 | + <&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>; | |
| 40 | + }; | |
| 41 | + | |
| 42 | +Example: I2S controller node that consumes the clock generated by the clock | |
| 43 | + controller. Refer to the standard clock bindings for information | |
| 44 | + about 'clocks' and 'clock-names' property. | |
| 45 | + | |
| 46 | + i2s0: i2s@03830000 { | |
| 47 | + /* ... */ | |
| 48 | + clock-names = "iis", "i2s_opclk0", | |
| 49 | + "i2s_opclk1"; | |
| 50 | + clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>, | |
| 51 | + <&clk_audss CLK_DOUT_AUD_BUS>; | |
| 52 | + /* ... */ | |
| 53 | + }; | |
| @@ -0,0 +1,26 @@ | ||
| 1 | +* Clock bindings for Freescale i.MX1 CPUs | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: Should be "fsl,imx1-ccm". | |
| 5 | +- reg: Address and length of the register set. | |
| 6 | +- #clock-cells: Should be <1>. | |
| 7 | + | |
| 8 | +The clock consumer should specify the desired clock by having the clock | |
| 9 | +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h | |
| 10 | +for the full list of i.MX1 clock IDs. | |
| 11 | + | |
| 12 | +Examples: | |
| 13 | + clks: ccm@0021b000 { | |
| 14 | + #clock-cells = <1>; | |
| 15 | + compatible = "fsl,imx1-ccm"; | |
| 16 | + reg = <0x0021b000 0x1000>; | |
| 17 | + }; | |
| 18 | + | |
| 19 | + pwm: pwm@00208000 { | |
| 20 | + #pwm-cells = <2>; | |
| 21 | + compatible = "fsl,imx1-pwm"; | |
| 22 | + reg = <0x00208000 0x1000>; | |
| 23 | + interrupts = <34>; | |
| 24 | + clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>; | |
| 25 | + clock-names = "ipg", "per"; | |
| 26 | + }; | |
| @@ -0,0 +1,28 @@ | ||
| 1 | +* Clock bindings for Freescale i.MX21 | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible : Should be "fsl,imx21-ccm". | |
| 5 | +- reg : Address and length of the register set. | |
| 6 | +- interrupts : Should contain CCM interrupt. | |
| 7 | +- #clock-cells: Should be <1>. | |
| 8 | + | |
| 9 | +The clock consumer should specify the desired clock by having the clock | |
| 10 | +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h | |
| 11 | +for the full list of i.MX21 clock IDs. | |
| 12 | + | |
| 13 | +Examples: | |
| 14 | + clks: ccm@10027000{ | |
| 15 | + compatible = "fsl,imx21-ccm"; | |
| 16 | + reg = <0x10027000 0x800>; | |
| 17 | + #clock-cells = <1>; | |
| 18 | + }; | |
| 19 | + | |
| 20 | + uart1: serial@1000a000 { | |
| 21 | + compatible = "fsl,imx21-uart"; | |
| 22 | + reg = <0x1000a000 0x1000>; | |
| 23 | + interrupts = <20>; | |
| 24 | + clocks = <&clks IMX21_CLK_UART1_IPG_GATE>, | |
| 25 | + <&clks IMX21_CLK_PER1>; | |
| 26 | + clock-names = "ipg", "per"; | |
| 27 | + status = "disabled"; | |
| 28 | + }; | |
| @@ -7,117 +7,22 @@ Required properties: · 6 unmodified lines | ||
| 7 | 7 | - #clock-cells: Should be <1> |
| 8 | 8 | |
| 9 | 9 | The clock consumer should specify the desired clock by having the clock |
| 10 | −ID in its "clocks" phandle cell. The following is a full list of i.MX27 | |
| 11 | −clocks and IDs. | |
| 12 | − | |
| 13 | − Clock ID | |
| 14 | − ----------------------- | |
| 15 | − dummy 0 | |
| 16 | − ckih 1 | |
| 17 | − ckil 2 | |
| 18 | − mpll 3 | |
| 19 | − spll 4 | |
| 20 | − mpll_main2 5 | |
| 21 | − ahb 6 | |
| 22 | − ipg 7 | |
| 23 | − nfc_div 8 | |
| 24 | − per1_div 9 | |
| 25 | − per2_div 10 | |
| 26 | − per3_div 11 | |
| 27 | − per4_div 12 | |
| 28 | − vpu_sel 13 | |
| 29 | − vpu_div 14 | |
| 30 | − usb_div 15 | |
| 31 | − cpu_sel 16 | |
| 32 | − clko_sel 17 | |
| 33 | − cpu_div 18 | |
| 34 | − clko_div 19 | |
| 35 | − ssi1_sel 20 | |
| 36 | − ssi2_sel 21 | |
| 37 | − ssi1_div 22 | |
| 38 | − ssi2_div 23 | |
| 39 | − clko_en 24 | |
| 40 | − ssi2_ipg_gate 25 | |
| 41 | − ssi1_ipg_gate 26 | |
| 42 | − slcdc_ipg_gate 27 | |
| 43 | − sdhc3_ipg_gate 28 | |
| 44 | − sdhc2_ipg_gate 29 | |
| 45 | − sdhc1_ipg_gate 30 | |
| 46 | − scc_ipg_gate 31 | |
| 47 | − sahara_ipg_gate 32 | |
| 48 | − rtc_ipg_gate 33 | |
| 49 | − pwm_ipg_gate 34 | |
| 50 | − owire_ipg_gate 35 | |
| 51 | − lcdc_ipg_gate 36 | |
| 52 | − kpp_ipg_gate 37 | |
| 53 | − iim_ipg_gate 38 | |
| 54 | − i2c2_ipg_gate 39 | |
| 55 | − i2c1_ipg_gate 40 | |
| 56 | − gpt6_ipg_gate 41 | |
| 57 | − gpt5_ipg_gate 42 | |
| 58 | − gpt4_ipg_gate 43 | |
| 59 | − gpt3_ipg_gate 44 | |
| 60 | − gpt2_ipg_gate 45 | |
| 61 | − gpt1_ipg_gate 46 | |
| 62 | − gpio_ipg_gate 47 | |
| 63 | − fec_ipg_gate 48 | |
| 64 | − emma_ipg_gate 49 | |
| 65 | − dma_ipg_gate 50 | |
| 66 | − cspi3_ipg_gate 51 | |
| 67 | − cspi2_ipg_gate 52 | |
| 68 | − cspi1_ipg_gate 53 | |
| 69 | − nfc_baud_gate 54 | |
| 70 | − ssi2_baud_gate 55 | |
| 71 | − ssi1_baud_gate 56 | |
| 72 | − vpu_baud_gate 57 | |
| 73 | − per4_gate 58 | |
| 74 | − per3_gate 59 | |
| 75 | − per2_gate 60 | |
| 76 | − per1_gate 61 | |
| 77 | − usb_ahb_gate 62 | |
| 78 | − slcdc_ahb_gate 63 | |
| 79 | − sahara_ahb_gate 64 | |
| 80 | − lcdc_ahb_gate 65 | |
| 81 | − vpu_ahb_gate 66 | |
| 82 | − fec_ahb_gate 67 | |
| 83 | − emma_ahb_gate 68 | |
| 84 | − emi_ahb_gate 69 | |
| 85 | − dma_ahb_gate 70 | |
| 86 | − csi_ahb_gate 71 | |
| 87 | − brom_ahb_gate 72 | |
| 88 | − ata_ahb_gate 73 | |
| 89 | − wdog_ipg_gate 74 | |
| 90 | − usb_ipg_gate 75 | |
| 91 | − uart6_ipg_gate 76 | |
| 92 | − uart5_ipg_gate 77 | |
| 93 | − uart4_ipg_gate 78 | |
| 94 | − uart3_ipg_gate 79 | |
| 95 | − uart2_ipg_gate 80 | |
| 96 | − uart1_ipg_gate 81 | |
| 97 | − ckih_div1p5 82 | |
| 98 | − fpm 83 | |
| 99 | − mpll_osc_sel 84 | |
| 100 | − mpll_sel 85 | |
| 101 | − spll_gate 86 | |
| 102 | − mshc_div 87 | |
| 103 | − rtic_ipg_gate 88 | |
| 104 | − mshc_ipg_gate 89 | |
| 105 | − rtic_ahb_gate 90 | |
| 106 | − mshc_baud_gate 91 | |
| 10 | +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h | |
| 11 | +for the full list of i.MX27 clock IDs. | |
| 107 | 12 | |
| 108 | 13 | Examples: |
| 14 | + clks: ccm@10027000{ | |
| 15 | + compatible = "fsl,imx27-ccm"; | |
| 16 | + reg = <0x10027000 0x1000>; | |
| 17 | + #clock-cells = <1>; | |
| 18 | + }; | |
| 109 | 19 | |
| 110 | −clks: ccm@10027000{ | |
| 111 | − compatible = "fsl,imx27-ccm"; | |
| 112 | − reg = <0x10027000 0x1000>; | |
| 113 | − #clock-cells = <1>; | |
| 114 | −}; | |
| 115 | − | |
| 116 | −uart1: serial@1000a000 { | |
| 117 | − compatible = "fsl,imx27-uart", "fsl,imx21-uart"; | |
| 118 | − reg = <0x1000a000 0x1000>; | |
| 119 | − interrupts = <20>; | |
| 120 | − clocks = <&clks 81>, <&clks 61>; | |
| 121 | − clock-names = "ipg", "per"; | |
| 122 | − status = "disabled"; | |
| 123 | −}; | |
| 20 | + uart1: serial@1000a000 { | |
| 21 | + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; | |
| 22 | + reg = <0x1000a000 0x1000>; | |
| 23 | + interrupts = <20>; | |
| 24 | + clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, | |
| 25 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 26 | + clock-names = "ipg", "per"; | |
| 27 | + status = "disabled"; | |
| 28 | + }; | |
| @@ -7,223 +7,13 @@ Required properties: · 6 unmodified lines | ||
| 7 | 7 | - #clock-cells: Should be <1> |
| 8 | 8 | |
| 9 | 9 | The clock consumer should specify the desired clock by having the clock |
| 10 | −ID in its "clocks" phandle cell. The following is a full list of i.MX6Q | |
| 11 | −clocks and IDs. | |
| 12 | − | |
| 13 | − Clock ID | |
| 14 | − --------------------------- | |
| 15 | − dummy 0 | |
| 16 | − ckil 1 | |
| 17 | − ckih 2 | |
| 18 | − osc 3 | |
| 19 | − pll2_pfd0_352m 4 | |
| 20 | − pll2_pfd1_594m 5 | |
| 21 | − pll2_pfd2_396m 6 | |
| 22 | − pll3_pfd0_720m 7 | |
| 23 | − pll3_pfd1_540m 8 | |
| 24 | − pll3_pfd2_508m 9 | |
| 25 | − pll3_pfd3_454m 10 | |
| 26 | − pll2_198m 11 | |
| 27 | − pll3_120m 12 | |
| 28 | − pll3_80m 13 | |
| 29 | − pll3_60m 14 | |
| 30 | − twd 15 | |
| 31 | − step 16 | |
| 32 | − pll1_sw 17 | |
| 33 | − periph_pre 18 | |
| 34 | − periph2_pre 19 | |
| 35 | − periph_clk2_sel 20 | |
| 36 | − periph2_clk2_sel 21 | |
| 37 | − axi_sel 22 | |
| 38 | − esai_sel 23 | |
| 39 | − asrc_sel 24 | |
| 40 | − spdif_sel 25 | |
| 41 | − gpu2d_axi 26 | |
| 42 | − gpu3d_axi 27 | |
| 43 | − gpu2d_core_sel 28 | |
| 44 | − gpu3d_core_sel 29 | |
| 45 | − gpu3d_shader_sel 30 | |
| 46 | − ipu1_sel 31 | |
| 47 | − ipu2_sel 32 | |
| 48 | − ldb_di0_sel 33 | |
| 49 | − ldb_di1_sel 34 | |
| 50 | − ipu1_di0_pre_sel 35 | |
| 51 | − ipu1_di1_pre_sel 36 | |
| 52 | − ipu2_di0_pre_sel 37 | |
| 53 | − ipu2_di1_pre_sel 38 | |
| 54 | − ipu1_di0_sel 39 | |
| 55 | − ipu1_di1_sel 40 | |
| 56 | − ipu2_di0_sel 41 | |
| 57 | − ipu2_di1_sel 42 | |
| 58 | − hsi_tx_sel 43 | |
| 59 | − pcie_axi_sel 44 | |
| 60 | − ssi1_sel 45 | |
| 61 | − ssi2_sel 46 | |
| 62 | − ssi3_sel 47 | |
| 63 | − usdhc1_sel 48 | |
| 64 | − usdhc2_sel 49 | |
| 65 | − usdhc3_sel 50 | |
| 66 | − usdhc4_sel 51 | |
| 67 | − enfc_sel 52 | |
| 68 | − emi_sel 53 | |
| 69 | − emi_slow_sel 54 | |
| 70 | − vdo_axi_sel 55 | |
| 71 | − vpu_axi_sel 56 | |
| 72 | − cko1_sel 57 | |
| 73 | − periph 58 | |
| 74 | − periph2 59 | |
| 75 | − periph_clk2 60 | |
| 76 | − periph2_clk2 61 | |
| 77 | − ipg 62 | |
| 78 | − ipg_per 63 | |
| 79 | − esai_pred 64 | |
| 80 | − esai_podf 65 | |
| 81 | − asrc_pred 66 | |
| 82 | − asrc_podf 67 | |
| 83 | − spdif_pred 68 | |
| 84 | − spdif_podf 69 | |
| 85 | − can_root 70 | |
| 86 | − ecspi_root 71 | |
| 87 | − gpu2d_core_podf 72 | |
| 88 | − gpu3d_core_podf 73 | |
| 89 | − gpu3d_shader 74 | |
| 90 | − ipu1_podf 75 | |
| 91 | − ipu2_podf 76 | |
| 92 | − ldb_di0_podf 77 | |
| 93 | − ldb_di1_podf 78 | |
| 94 | − ipu1_di0_pre 79 | |
| 95 | − ipu1_di1_pre 80 | |
| 96 | − ipu2_di0_pre 81 | |
| 97 | − ipu2_di1_pre 82 | |
| 98 | − hsi_tx_podf 83 | |
| 99 | − ssi1_pred 84 | |
| 100 | − ssi1_podf 85 | |
| 101 | − ssi2_pred 86 | |
| 102 | − ssi2_podf 87 | |
| 103 | − ssi3_pred 88 | |
| 104 | − ssi3_podf 89 | |
| 105 | − uart_serial_podf 90 | |
| 106 | − usdhc1_podf 91 | |
| 107 | − usdhc2_podf 92 | |
| 108 | − usdhc3_podf 93 | |
| 109 | − usdhc4_podf 94 | |
| 110 | − enfc_pred 95 | |
| 111 | − enfc_podf 96 | |
| 112 | − emi_podf 97 | |
| 113 | − emi_slow_podf 98 | |
| 114 | − vpu_axi_podf 99 | |
| 115 | − cko1_podf 100 | |
| 116 | − axi 101 | |
| 117 | − mmdc_ch0_axi_podf 102 | |
| 118 | − mmdc_ch1_axi_podf 103 | |
| 119 | − arm 104 | |
| 120 | − ahb 105 | |
| 121 | − apbh_dma 106 | |
| 122 | − asrc 107 | |
| 123 | − can1_ipg 108 | |
| 124 | − can1_serial 109 | |
| 125 | − can2_ipg 110 | |
| 126 | − can2_serial 111 | |
| 127 | − ecspi1 112 | |
| 128 | − ecspi2 113 | |
| 129 | − ecspi3 114 | |
| 130 | − ecspi4 115 | |
| 131 | − ecspi5 116 | |
| 132 | − enet 117 | |
| 133 | − esai 118 | |
| 134 | − gpt_ipg 119 | |
| 135 | − gpt_ipg_per 120 | |
| 136 | − gpu2d_core 121 | |
| 137 | − gpu3d_core 122 | |
| 138 | − hdmi_iahb 123 | |
| 139 | − hdmi_isfr 124 | |
| 140 | − i2c1 125 | |
| 141 | − i2c2 126 | |
| 142 | − i2c3 127 | |
| 143 | − iim 128 | |
| 144 | − enfc 129 | |
| 145 | − ipu1 130 | |
| 146 | − ipu1_di0 131 | |
| 147 | − ipu1_di1 132 | |
| 148 | − ipu2 133 | |
| 149 | − ipu2_di0 134 | |
| 150 | − ldb_di0 135 | |
| 151 | − ldb_di1 136 | |
| 152 | − ipu2_di1 137 | |
| 153 | − hsi_tx 138 | |
| 154 | − mlb 139 | |
| 155 | − mmdc_ch0_axi 140 | |
| 156 | − mmdc_ch1_axi 141 | |
| 157 | − ocram 142 | |
| 158 | − openvg_axi 143 | |
| 159 | − pcie_axi 144 | |
| 160 | − pwm1 145 | |
| 161 | − pwm2 146 | |
| 162 | − pwm3 147 | |
| 163 | − pwm4 148 | |
| 164 | − per1_bch 149 | |
| 165 | − gpmi_bch_apb 150 | |
| 166 | − gpmi_bch 151 | |
| 167 | − gpmi_io 152 | |
| 168 | − gpmi_apb 153 | |
| 169 | − sata 154 | |
| 170 | − sdma 155 | |
| 171 | − spba 156 | |
| 172 | − ssi1 157 | |
| 173 | − ssi2 158 | |
| 174 | − ssi3 159 | |
| 175 | − uart_ipg 160 | |
| 176 | − uart_serial 161 | |
| 177 | − usboh3 162 | |
| 178 | − usdhc1 163 | |
| 179 | − usdhc2 164 | |
| 180 | − usdhc3 165 | |
| 181 | − usdhc4 166 | |
| 182 | − vdo_axi 167 | |
| 183 | − vpu_axi 168 | |
| 184 | − cko1 169 | |
| 185 | − pll1_sys 170 | |
| 186 | − pll2_bus 171 | |
| 187 | − pll3_usb_otg 172 | |
| 188 | − pll4_audio 173 | |
| 189 | − pll5_video 174 | |
| 190 | − pll8_mlb 175 | |
| 191 | − pll7_usb_host 176 | |
| 192 | − pll6_enet 177 | |
| 193 | − ssi1_ipg 178 | |
| 194 | − ssi2_ipg 179 | |
| 195 | − ssi3_ipg 180 | |
| 196 | − rom 181 | |
| 197 | − usbphy1 182 | |
| 198 | − usbphy2 183 | |
| 199 | − ldb_di0_div_3_5 184 | |
| 200 | − ldb_di1_div_3_5 185 | |
| 201 | − sata_ref 186 | |
| 202 | − sata_ref_100m 187 | |
| 203 | − pcie_ref 188 | |
| 204 | − pcie_ref_125m 189 | |
| 205 | − enet_ref 190 | |
| 206 | − usbphy1_gate 191 | |
| 207 | − usbphy2_gate 192 | |
| 208 | − pll4_post_div 193 | |
| 209 | − pll5_post_div 194 | |
| 210 | − pll5_video_div 195 | |
| 211 | − eim_slow 196 | |
| 212 | − spdif 197 | |
| 213 | − cko2_sel 198 | |
| 214 | − cko2_podf 199 | |
| 215 | − cko2 200 | |
| 216 | − cko 201 | |
| 217 | − vdoa 202 | |
| 218 | − pll4_audio_div 203 | |
| 219 | − lvds1_sel 204 | |
| 220 | − lvds2_sel 205 | |
| 221 | − lvds1_gate 206 | |
| 222 | − lvds2_gate 207 | |
| 223 | − esai_ahb 208 | |
| 10 | +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h | |
| 11 | +for the full list of i.MX6 Quad and DualLite clock IDs. | |
| 224 | 12 | |
| 225 | 13 | Examples: |
| 226 | 14 | |
| 15 | +#include <dt-bindings/clock/imx6qdl-clock.h> | |
| 16 | + | |
| 227 | 17 | clks: ccm@020c4000 { |
| 228 | 18 | compatible = "fsl,imx6q-ccm"; |
| 229 | 19 | reg = <0x020c4000 0x4000>; |
| @@ -235,7 +25,7 @@ uart1: serial@02020000 { · 5 unmodified lines | ||
| 235 | 25 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 236 | 26 | reg = <0x02020000 0x4000>; |
| 237 | 27 | interrupts = <0 26 0x04>; |
| 238 | − clocks = <&clks 160>, <&clks 161>; | |
| 28 | + clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>; | |
| 239 | 29 | clock-names = "ipg", "per"; |
| 240 | 30 | status = "disabled"; |
| 241 | 31 | }; |
| @@ -3,14 +3,15 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms · 2 unmodified lines | ||
| 3 | 3 | Required properties: |
| 4 | 4 | - compatible : shall be one of the following: |
| 5 | 5 | "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP |
| 6 | −- reg : Address and length of the clock complex register set | |
| 6 | +- reg : Address and length of the clock complex register set, followed | |
| 7 | + by address and length of the PMU DFS registers | |
| 7 | 8 | - #clock-cells : should be set to 1. |
| 8 | 9 | - clocks : shall be the input parent clock phandle for the clock. |
| 9 | 10 | |
| 10 | 11 | cpuclk: clock-complex@d0018700 { |
| 11 | 12 | #clock-cells = <1>; |
| 12 | 13 | compatible = "marvell,armada-xp-cpu-clock"; |
| 13 | − reg = <0xd0018700 0xA0>; | |
| 14 | + reg = <0xd0018700 0xA0>, <0x1c054 0x10>; | |
| 14 | 15 | clocks = <&coreclk 1>; |
| 15 | 16 | } |
| 16 | 17 | |
| @@ -0,0 +1,78 @@ | ||
| 1 | +* Samsung S5P6442/S5PC110/S5PV210 Clock Controller | |
| 2 | + | |
| 3 | +Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock | |
| 4 | +controller, which generates and supplies clock to various controllers | |
| 5 | +within the SoC. | |
| 6 | + | |
| 7 | +Required Properties: | |
| 8 | + | |
| 9 | +- compatible: should be one of following: | |
| 10 | + - "samsung,s5pv210-clock" : for clock controller of Samsung | |
| 11 | + S5PC110/S5PV210 SoCs, | |
| 12 | + - "samsung,s5p6442-clock" : for clock controller of Samsung | |
| 13 | + S5P6442 SoC. | |
| 14 | + | |
| 15 | +- reg: physical base address of the controller and length of memory mapped | |
| 16 | + region. | |
| 17 | + | |
| 18 | +- #clock-cells: should be 1. | |
| 19 | + | |
| 20 | +All available clocks are defined as preprocessor macros in | |
| 21 | +dt-bindings/clock/s5pv210.h header and can be used in device tree sources. | |
| 22 | + | |
| 23 | +External clocks: | |
| 24 | + | |
| 25 | +There are several clocks that are generated outside the SoC. It is expected | |
| 26 | +that they are defined using standard clock bindings with following | |
| 27 | +clock-output-names: | |
| 28 | + - "xxti": external crystal oscillator connected to XXTI and XXTO pins of | |
| 29 | +the SoC, | |
| 30 | + - "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO | |
| 31 | +pins of the SoC, | |
| 32 | + | |
| 33 | +A subset of above clocks available on given board shall be specified in | |
| 34 | +board device tree, including the system base clock, as selected by XOM[0] | |
| 35 | +pin of the SoC. Refer to generic fixed rate clock bindings | |
| 36 | +documentation[1] for more information how to specify these clocks. | |
| 37 | + | |
| 38 | +[1] Documentation/devicetree/bindings/clock/fixed-clock.txt | |
| 39 | + | |
| 40 | +Example: Clock controller node: | |
| 41 | + | |
| 42 | + clock: clock-controller@7e00f000 { | |
| 43 | + compatible = "samsung,s5pv210-clock"; | |
| 44 | + reg = <0x7e00f000 0x1000>; | |
| 45 | + #clock-cells = <1>; | |
| 46 | + }; | |
| 47 | + | |
| 48 | +Example: Required external clocks: | |
| 49 | + | |
| 50 | + xxti: clock-xxti { | |
| 51 | + compatible = "fixed-clock"; | |
| 52 | + clock-output-names = "xxti"; | |
| 53 | + clock-frequency = <24000000>; | |
| 54 | + #clock-cells = <0>; | |
| 55 | + }; | |
| 56 | + | |
| 57 | + xusbxti: clock-xusbxti { | |
| 58 | + compatible = "fixed-clock"; | |
| 59 | + clock-output-names = "xusbxti"; | |
| 60 | + clock-frequency = <24000000>; | |
| 61 | + #clock-cells = <0>; | |
| 62 | + }; | |
| 63 | + | |
| 64 | +Example: UART controller node that consumes the clock generated by the clock | |
| 65 | + controller (refer to the standard clock bindings for information about | |
| 66 | + "clocks" and "clock-names" properties): | |
| 67 | + | |
| 68 | + uart0: serial@e2900000 { | |
| 69 | + compatible = "samsung,s5pv210-uart"; | |
| 70 | + reg = <0xe2900000 0x400>; | |
| 71 | + interrupt-parent = <&vic1>; | |
| 72 | + interrupts = <10>; | |
| 73 | + clock-names = "uart", "clk_uart_baud0", | |
| 74 | + "clk_uart_baud1"; | |
| 75 | + clocks = <&clocks UART0>, <&clocks UART0>, | |
| 76 | + <&clocks SCLK_UART0>; | |
| 77 | + status = "disabled"; | |
| 78 | + }; | |
| @@ -47,6 +47,7 @@ The full ID of peripheral types can be found below. · 46 unmodified lines | ||
| 47 | 47 | 20 ASRC |
| 48 | 48 | 21 ESAI |
| 49 | 49 | 22 SSI Dual FIFO (needs firmware ver >= 2) |
| 50 | + 23 Shared ASRC | |
| 50 | 51 | |
| 51 | 52 | The third cell specifies the transfer priority as below. |
| 52 | 53 | |
| @@ -0,0 +1,29 @@ | ||
| 1 | +* Freescale MPC512x and MPC8308 DMA Controller | |
| 2 | + | |
| 3 | +The DMA controller in Freescale MPC512x and MPC8308 SoCs can move | |
| 4 | +blocks of memory contents between memory and peripherals or | |
| 5 | +from memory to memory. | |
| 6 | + | |
| 7 | +Refer to "Generic DMA Controller and DMA request bindings" in | |
| 8 | +the dma/dma.txt file for a more detailed description of binding. | |
| 9 | + | |
| 10 | +Required properties: | |
| 11 | +- compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma"; | |
| 12 | +- reg: should contain the DMA controller registers location and length; | |
| 13 | +- interrupt for the DMA controller: syntax of interrupt client node | |
| 14 | + is described in interrupt-controller/interrupts.txt file. | |
| 15 | +- #dma-cells: the length of the DMA specifier, must be <1>. | |
| 16 | + Each channel of this DMA controller has a peripheral request line, | |
| 17 | + the assignment is fixed in hardware. This one cell | |
| 18 | + in dmas property of a client device represents the channel number. | |
| 19 | + | |
| 20 | +Example: | |
| 21 | + | |
| 22 | + dma0: dma@14000 { | |
| 23 | + compatible = "fsl,mpc5121-dma"; | |
| 24 | + reg = <0x14000 0x1800>; | |
| 25 | + interrupts = <65 0x8>; | |
| 26 | + #dma-cells = <1>; | |
| 27 | + }; | |
| 28 | + | |
| 29 | +DMA clients must use the format described in dma/dma.txt file. | |
| @@ -0,0 +1,61 @@ | ||
| 1 | +* Renesas "Type-AXI" NBPFAXI* DMA controllers | |
| 2 | + | |
| 3 | +* DMA controller | |
| 4 | + | |
| 5 | +Required properties | |
| 6 | + | |
| 7 | +- compatible: must be one of | |
| 8 | + "renesas,nbpfaxi64dmac1b4" | |
| 9 | + "renesas,nbpfaxi64dmac1b8" | |
| 10 | + "renesas,nbpfaxi64dmac1b16" | |
| 11 | + "renesas,nbpfaxi64dmac4b4" | |
| 12 | + "renesas,nbpfaxi64dmac4b8" | |
| 13 | + "renesas,nbpfaxi64dmac4b16" | |
| 14 | + "renesas,nbpfaxi64dmac8b4" | |
| 15 | + "renesas,nbpfaxi64dmac8b8" | |
| 16 | + "renesas,nbpfaxi64dmac8b16" | |
| 17 | +- #dma-cells: must be 2: the first integer is a terminal number, to which this | |
| 18 | + slave is connected, the second one is flags. Flags is a bitmask | |
| 19 | + with the following bits defined: | |
| 20 | + | |
| 21 | +#define NBPF_SLAVE_RQ_HIGH 1 | |
| 22 | +#define NBPF_SLAVE_RQ_LOW 2 | |
| 23 | +#define NBPF_SLAVE_RQ_LEVEL 4 | |
| 24 | + | |
| 25 | +Optional properties: | |
| 26 | + | |
| 27 | +You can use dma-channels and dma-requests as described in dma.txt, although they | |
| 28 | +won't be used, this information is derived from the compatibility string. | |
| 29 | + | |
| 30 | +Example: | |
| 31 | + | |
| 32 | + dma: dma-controller@48000000 { | |
| 33 | + compatible = "renesas,nbpfaxi64dmac8b4"; | |
| 34 | + reg = <0x48000000 0x400>; | |
| 35 | + interrupts = <0 12 0x4 | |
| 36 | + 0 13 0x4 | |
| 37 | + 0 14 0x4 | |
| 38 | + 0 15 0x4 | |
| 39 | + 0 16 0x4 | |
| 40 | + 0 17 0x4 | |
| 41 | + 0 18 0x4 | |
| 42 | + 0 19 0x4>; | |
| 43 | + #dma-cells = <2>; | |
| 44 | + dma-channels = <8>; | |
| 45 | + dma-requests = <8>; | |
| 46 | + }; | |
| 47 | + | |
| 48 | +* DMA client | |
| 49 | + | |
| 50 | +Required properties: | |
| 51 | + | |
| 52 | +dmas and dma-names are required, as described in dma.txt. | |
| 53 | + | |
| 54 | +Example: | |
| 55 | + | |
| 56 | +#include <dt-bindings/dma/nbpfaxi.h> | |
| 57 | + | |
| 58 | +... | |
| 59 | + dmas = <&dma 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL) | |
| 60 | + &dma 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; | |
| 61 | + dma-names = "rx", "tx"; | |
| @@ -0,0 +1,29 @@ | ||
| 1 | +* R-Car Audio DMAC peri peri Device Tree bindings | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: should be "renesas,rcar-audmapp" | |
| 5 | +- #dma-cells: should be <1>, see "dmas" property below | |
| 6 | + | |
| 7 | +Example: | |
| 8 | + audmapp: audio-dma-pp@0xec740000 { | |
| 9 | + compatible = "renesas,rcar-audmapp"; | |
| 10 | + #dma-cells = <1>; | |
| 11 | + | |
| 12 | + reg = <0 0xec740000 0 0x200>; | |
| 13 | + }; | |
| 14 | + | |
| 15 | + | |
| 16 | +* DMA client | |
| 17 | + | |
| 18 | +Required properties: | |
| 19 | +- dmas: a list of <[DMA multiplexer phandle] [SRS/DRS value]> pairs, | |
| 20 | + where SRS/DRS values are fixed handles, specified in the SoC | |
| 21 | + manual as the value that would be written into the PDMACHCR. | |
| 22 | +- dma-names: a list of DMA channel names, one per "dmas" entry | |
| 23 | + | |
| 24 | +Example: | |
| 25 | + | |
| 26 | + dmas = <&audmapp 0x2d00 | |
| 27 | + &audmapp 0x3700>; | |
| 28 | + dma-names = "src0_ssiu0", | |
| 29 | + "dvc0_ssiu0"; | |
| @@ -0,0 +1,98 @@ | ||
| 1 | +* Renesas R-Car DMA Controller Device Tree bindings | |
| 2 | + | |
| 3 | +Renesas R-Car Generation 2 SoCs have have multiple multi-channel DMA | |
| 4 | +controller instances named DMAC capable of serving multiple clients. Channels | |
| 5 | +can be dedicated to specific clients or shared between a large number of | |
| 6 | +clients. | |
| 7 | + | |
| 8 | +DMA clients are connected to the DMAC ports referenced by an 8-bit identifier | |
| 9 | +called MID/RID. | |
| 10 | + | |
| 11 | +Each DMA client is connected to one dedicated port of the DMAC, identified by | |
| 12 | +an 8-bit port number called the MID/RID. A DMA controller can thus serve up to | |
| 13 | +256 clients in total. When the number of hardware channels is lower than the | |
| 14 | +number of clients to be served, channels must be shared between multiple DMA | |
| 15 | +clients. The association of DMA clients to DMAC channels is fully dynamic and | |
| 16 | +not described in these device tree bindings. | |
| 17 | + | |
| 18 | +Required Properties: | |
| 19 | + | |
| 20 | +- compatible: must contain "renesas,rcar-dmac" | |
| 21 | + | |
| 22 | +- reg: base address and length of the registers block for the DMAC | |
| 23 | + | |
| 24 | +- interrupts: interrupt specifiers for the DMAC, one for each entry in | |
| 25 | + interrupt-names. | |
| 26 | +- interrupt-names: one entry per channel, named "ch%u", where %u is the | |
| 27 | + channel number ranging from zero to the number of channels minus one. | |
| 28 | + | |
| 29 | +- clock-names: "fck" for the functional clock | |
| 30 | +- clocks: a list of phandle + clock-specifier pairs, one for each entry | |
| 31 | + in clock-names. | |
| 32 | +- clock-names: must contain "fck" for the functional clock. | |
| 33 | + | |
| 34 | +- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port | |
| 35 | + connected to the DMA client | |
| 36 | +- dma-channels: number of DMA channels | |
| 37 | + | |
| 38 | +Example: R8A7790 (R-Car H2) SYS-DMACs | |
| 39 | + | |
| 40 | + dmac0: dma-controller@e6700000 { | |
| 41 | + compatible = "renesas,rcar-dmac"; | |
| 42 | + reg = <0 0xe6700000 0 0x20000>; | |
| 43 | + interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH | |
| 44 | + 0 200 IRQ_TYPE_LEVEL_HIGH | |
| 45 | + 0 201 IRQ_TYPE_LEVEL_HIGH | |
| 46 | + 0 202 IRQ_TYPE_LEVEL_HIGH | |
| 47 | + 0 203 IRQ_TYPE_LEVEL_HIGH | |
| 48 | + 0 204 IRQ_TYPE_LEVEL_HIGH | |
| 49 | + 0 205 IRQ_TYPE_LEVEL_HIGH | |
| 50 | + 0 206 IRQ_TYPE_LEVEL_HIGH | |
| 51 | + 0 207 IRQ_TYPE_LEVEL_HIGH | |
| 52 | + 0 208 IRQ_TYPE_LEVEL_HIGH | |
| 53 | + 0 209 IRQ_TYPE_LEVEL_HIGH | |
| 54 | + 0 210 IRQ_TYPE_LEVEL_HIGH | |
| 55 | + 0 211 IRQ_TYPE_LEVEL_HIGH | |
| 56 | + 0 212 IRQ_TYPE_LEVEL_HIGH | |
| 57 | + 0 213 IRQ_TYPE_LEVEL_HIGH | |
| 58 | + 0 214 IRQ_TYPE_LEVEL_HIGH>; | |
| 59 | + interrupt-names = "error", | |
| 60 | + "ch0", "ch1", "ch2", "ch3", | |
| 61 | + "ch4", "ch5", "ch6", "ch7", | |
| 62 | + "ch8", "ch9", "ch10", "ch11", | |
| 63 | + "ch12", "ch13", "ch14"; | |
| 64 | + clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; | |
| 65 | + clock-names = "fck"; | |
| 66 | + #dma-cells = <1>; | |
| 67 | + dma-channels = <15>; | |
| 68 | + }; | |
| 69 | + | |
| 70 | + dmac1: dma-controller@e6720000 { | |
| 71 | + compatible = "renesas,rcar-dmac"; | |
| 72 | + reg = <0 0xe6720000 0 0x20000>; | |
| 73 | + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH | |
| 74 | + 0 216 IRQ_TYPE_LEVEL_HIGH | |
| 75 | + 0 217 IRQ_TYPE_LEVEL_HIGH | |
| 76 | + 0 218 IRQ_TYPE_LEVEL_HIGH | |
| 77 | + 0 219 IRQ_TYPE_LEVEL_HIGH | |
| 78 | + 0 308 IRQ_TYPE_LEVEL_HIGH | |
| 79 | + 0 309 IRQ_TYPE_LEVEL_HIGH | |
| 80 | + 0 310 IRQ_TYPE_LEVEL_HIGH | |
| 81 | + 0 311 IRQ_TYPE_LEVEL_HIGH | |
| 82 | + 0 312 IRQ_TYPE_LEVEL_HIGH | |
| 83 | + 0 313 IRQ_TYPE_LEVEL_HIGH | |
| 84 | + 0 314 IRQ_TYPE_LEVEL_HIGH | |
| 85 | + 0 315 IRQ_TYPE_LEVEL_HIGH | |
| 86 | + 0 316 IRQ_TYPE_LEVEL_HIGH | |
| 87 | + 0 317 IRQ_TYPE_LEVEL_HIGH | |
| 88 | + 0 318 IRQ_TYPE_LEVEL_HIGH>; | |
| 89 | + interrupt-names = "error", | |
| 90 | + "ch0", "ch1", "ch2", "ch3", | |
| 91 | + "ch4", "ch5", "ch6", "ch7", | |
| 92 | + "ch8", "ch9", "ch10", "ch11", | |
| 93 | + "ch12", "ch13", "ch14"; | |
| 94 | + clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; | |
| 95 | + clock-names = "fck"; | |
| 96 | + #dma-cells = <1>; | |
| 97 | + dma-channels = <15>; | |
| 98 | + }; | |
| @@ -35,9 +35,11 @@ Required properties: · 34 unmodified lines | ||
| 35 | 35 | |
| 36 | 36 | Each dmas request consists of 4 cells: |
| 37 | 37 | 1. A phandle pointing to the DMA controller |
| 38 | − 2. Device Type | |
| 38 | + 2. Device signal number, the signal line for single and burst requests | |
| 39 | + connected from the device to the DMA40 engine | |
| 39 | 40 | 3. The DMA request line number (only when 'use fixed channel' is set) |
| 40 | − 4. A 32bit mask specifying; mode, direction and endianness [NB: This list will grow] | |
| 41 | + 4. A 32bit mask specifying; mode, direction and endianness | |
| 42 | + [NB: This list will grow] | |
| 41 | 43 | 0x00000001: Mode: |
| 42 | 44 | Logical channel when unset |
| 43 | 45 | Physical channel when set |
| @@ -54,6 +56,74 @@ Each dmas request consists of 4 cells: · 10 unmodified lines | ||
| 54 | 56 | Normal priority when unset |
| 55 | 57 | High priority when set |
| 56 | 58 | |
| 59 | +Existing signal numbers for the DB8500 ASIC. Unless specified, the signals are | |
| 60 | +bidirectional, i.e. the same for RX and TX operations: | |
| 61 | + | |
| 62 | +0: SPI controller 0 | |
| 63 | +1: SD/MMC controller 0 (unused) | |
| 64 | +2: SD/MMC controller 1 (unused) | |
| 65 | +3: SD/MMC controller 2 (unused) | |
| 66 | +4: I2C port 1 | |
| 67 | +5: I2C port 3 | |
| 68 | +6: I2C port 2 | |
| 69 | +7: I2C port 4 | |
| 70 | +8: Synchronous Serial Port SSP0 | |
| 71 | +9: Synchronous Serial Port SSP1 | |
| 72 | +10: Multi-Channel Display Engine MCDE RX | |
| 73 | +11: UART port 2 | |
| 74 | +12: UART port 1 | |
| 75 | +13: UART port 0 | |
| 76 | +14: Multirate Serial Port MSP2 | |
| 77 | +15: I2C port 0 | |
| 78 | +16: USB OTG in/out endpoints 7 & 15 | |
| 79 | +17: USB OTG in/out endpoints 6 & 14 | |
| 80 | +18: USB OTG in/out endpoints 5 & 13 | |
| 81 | +19: USB OTG in/out endpoints 4 & 12 | |
| 82 | +20: SLIMbus or HSI channel 0 | |
| 83 | +21: SLIMbus or HSI channel 1 | |
| 84 | +22: SLIMbus or HSI channel 2 | |
| 85 | +23: SLIMbus or HSI channel 3 | |
| 86 | +24: Multimedia DSP SXA0 | |
| 87 | +25: Multimedia DSP SXA1 | |
| 88 | +26: Multimedia DSP SXA2 | |
| 89 | +27: Multimedia DSP SXA3 | |
| 90 | +28: SD/MM controller 2 | |
| 91 | +29: SD/MM controller 0 | |
| 92 | +30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2 | |
| 93 | +31: MSP port 0 or SLIMbus channel 0 | |
| 94 | +32: SD/MM controller 1 | |
| 95 | +33: SPI controller 2 | |
| 96 | +34: i2c3 RX2 TX2 | |
| 97 | +35: SPI controller 1 | |
| 98 | +36: USB OTG in/out endpoints 3 & 11 | |
| 99 | +37: USB OTG in/out endpoints 2 & 10 | |
| 100 | +38: USB OTG in/out endpoints 1 & 9 | |
| 101 | +39: USB OTG in/out endpoints 8 | |
| 102 | +40: SPI controller 3 | |
| 103 | +41: SD/MM controller 3 | |
| 104 | +42: SD/MM controller 4 | |
| 105 | +43: SD/MM controller 5 | |
| 106 | +44: Multimedia DSP SXA4 | |
| 107 | +45: Multimedia DSP SXA5 | |
| 108 | +46: SLIMbus channel 8 or Multimedia DSP SXA6 | |
| 109 | +47: SLIMbus channel 9 or Multimedia DSP SXA7 | |
| 110 | +48: Crypto Accelerator 1 | |
| 111 | +49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX | |
| 112 | +50: Hash Accelerator 1 TX | |
| 113 | +51: memcpy TX (to be used by the DMA driver for memcpy operations) | |
| 114 | +52: SLIMbus or HSI channel 4 | |
| 115 | +53: SLIMbus or HSI channel 5 | |
| 116 | +54: SLIMbus or HSI channel 6 | |
| 117 | +55: SLIMbus or HSI channel 7 | |
| 118 | +56: memcpy (to be used by the DMA driver for memcpy operations) | |
| 119 | +57: memcpy (to be used by the DMA driver for memcpy operations) | |
| 120 | +58: memcpy (to be used by the DMA driver for memcpy operations) | |
| 121 | +59: memcpy (to be used by the DMA driver for memcpy operations) | |
| 122 | +60: memcpy (to be used by the DMA driver for memcpy operations) | |
| 123 | +61: Crypto Accelerator 0 | |
| 124 | +62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX | |
| 125 | +63: Hash Accelerator 0 TX | |
| 126 | + | |
| 57 | 127 | Example: |
| 58 | 128 | |
| 59 | 129 | uart@80120000 { |
| @@ -0,0 +1,45 @@ | ||
| 1 | +Allwinner A31 DMA Controller | |
| 2 | + | |
| 3 | +This driver follows the generic DMA bindings defined in dma.txt. | |
| 4 | + | |
| 5 | +Required properties: | |
| 6 | + | |
| 7 | +- compatible: Must be "allwinner,sun6i-a31-dma" | |
| 8 | +- reg: Should contain the registers base address and length | |
| 9 | +- interrupts: Should contain a reference to the interrupt used by this device | |
| 10 | +- clocks: Should contain a reference to the parent AHB clock | |
| 11 | +- resets: Should contain a reference to the reset controller asserting | |
| 12 | + this device in reset | |
| 13 | +- #dma-cells : Should be 1, a single cell holding a line request number | |
| 14 | + | |
| 15 | +Example: | |
| 16 | + dma: dma-controller@01c02000 { | |
| 17 | + compatible = "allwinner,sun6i-a31-dma"; | |
| 18 | + reg = <0x01c02000 0x1000>; | |
| 19 | + interrupts = <0 50 4>; | |
| 20 | + clocks = <&ahb1_gates 6>; | |
| 21 | + resets = <&ahb1_rst 6>; | |
| 22 | + #dma-cells = <1>; | |
| 23 | + }; | |
| 24 | + | |
| 25 | +Clients: | |
| 26 | + | |
| 27 | +DMA clients connected to the A31 DMA controller must use the format | |
| 28 | +described in the dma.txt file, using a two-cell specifier for each | |
| 29 | +channel: a phandle plus one integer cells. | |
| 30 | +The two cells in order are: | |
| 31 | + | |
| 32 | +1. A phandle pointing to the DMA controller. | |
| 33 | +2. The port ID as specified in the datasheet | |
| 34 | + | |
| 35 | +Example: | |
| 36 | +spi2: spi@01c6a000 { | |
| 37 | + compatible = "allwinner,sun6i-a31-spi"; | |
| 38 | + reg = <0x01c6a000 0x1000>; | |
| 39 | + interrupts = <0 67 4>; | |
| 40 | + clocks = <&ahb1_gates 22>, <&spi2_clk>; | |
| 41 | + clock-names = "ahb", "mod"; | |
| 42 | + dmas = <&dma 25>, <&dma 25>; | |
| 43 | + dma-names = "rx", "tx"; | |
| 44 | + resets = <&ahb1_rst 22>; | |
| 45 | +}; | |
| @@ -0,0 +1,30 @@ | ||
| 1 | +Device Tree bindings for Armada DRM CRTC driver | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | + - compatible: value should be "marvell,dove-lcd". | |
| 5 | + - reg: base address and size of the LCD controller | |
| 6 | + - interrupts: single interrupt number for the LCD controller | |
| 7 | + - port: video output port with endpoints, as described by graph.txt | |
| 8 | + | |
| 9 | +Optional properties: | |
| 10 | + | |
| 11 | + - clocks: as described by clock-bindings.txt | |
| 12 | + - clock-names: as described by clock-bindings.txt | |
| 13 | + "axiclk" - axi bus clock for pixel clock | |
| 14 | + "plldivider" - pll divider clock for pixel clock | |
| 15 | + "ext_ref_clk0" - external clock 0 for pixel clock | |
| 16 | + "ext_ref_clk1" - external clock 1 for pixel clock | |
| 17 | + | |
| 18 | +Note: all clocks are optional but at least one must be specified. | |
| 19 | +Further clocks may be added in the future according to requirements of | |
| 20 | +different SoCs. | |
| 21 | + | |
| 22 | +Example: | |
| 23 | + | |
| 24 | + lcd0: lcd-controller@820000 { | |
| 25 | + compatible = "marvell,dove-lcd"; | |
| 26 | + reg = <0x820000 0x1000>; | |
| 27 | + interrupts = <47>; | |
| 28 | + clocks = <&si5351 0>; | |
| 29 | + clock-names = "ext_ref_clk_1"; | |
| 30 | + }; | |
| @@ -3,6 +3,8 @@ Device-Tree bindings for the NXP TDA998x HDMI transmitter · 2 unmodified lines | ||
| 3 | 3 | Required properties; |
| 4 | 4 | - compatible: must be "nxp,tda998x" |
| 5 | 5 | |
| 6 | + - reg: I2C address | |
| 7 | + | |
| 6 | 8 | Optional properties: |
| 7 | 9 | - interrupts: interrupt number and trigger type |
| 8 | 10 | default: polling |
| @@ -0,0 +1,52 @@ | ||
| 1 | +Qualcomm adreno/snapdragon GPU | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: "qcom,adreno-3xx" | |
| 5 | +- reg: Physical base address and length of the controller's registers. | |
| 6 | +- interrupts: The interrupt signal from the gpu. | |
| 7 | +- clocks: device clocks | |
| 8 | + See ../clocks/clock-bindings.txt for details. | |
| 9 | +- clock-names: the following clocks are required: | |
| 10 | + * "core_clk" | |
| 11 | + * "iface_clk" | |
| 12 | + * "mem_iface_clk" | |
| 13 | +- qcom,chipid: gpu chip-id. Note this may become optional for future | |
| 14 | + devices if we can reliably read the chipid from hw | |
| 15 | +- qcom,gpu-pwrlevels: list of operating points | |
| 16 | + - compatible: "qcom,gpu-pwrlevels" | |
| 17 | + - for each qcom,gpu-pwrlevel: | |
| 18 | + - qcom,gpu-freq: requested gpu clock speed | |
| 19 | + - NOTE: downstream android driver defines additional parameters to | |
| 20 | + configure memory bandwidth scaling per OPP. | |
| 21 | + | |
| 22 | +Example: | |
| 23 | + | |
| 24 | +/ { | |
| 25 | + ... | |
| 26 | + | |
| 27 | + gpu: qcom,kgsl-3d0@4300000 { | |
| 28 | + compatible = "qcom,adreno-3xx"; | |
| 29 | + reg = <0x04300000 0x20000>; | |
| 30 | + reg-names = "kgsl_3d0_reg_memory"; | |
| 31 | + interrupts = <GIC_SPI 80 0>; | |
| 32 | + interrupt-names = "kgsl_3d0_irq"; | |
| 33 | + clock-names = | |
| 34 | + "core_clk", | |
| 35 | + "iface_clk", | |
| 36 | + "mem_iface_clk"; | |
| 37 | + clocks = | |
| 38 | + <&mmcc GFX3D_CLK>, | |
| 39 | + <&mmcc GFX3D_AHB_CLK>, | |
| 40 | + <&mmcc MMSS_IMEM_AHB_CLK>; | |
| 41 | + qcom,chipid = <0x03020100>; | |
| 42 | + qcom,gpu-pwrlevels { | |
| 43 | + compatible = "qcom,gpu-pwrlevels"; | |
| 44 | + qcom,gpu-pwrlevel@0 { | |
| 45 | + qcom,gpu-freq = <450000000>; | |
| 46 | + }; | |
| 47 | + qcom,gpu-pwrlevel@1 { | |
| 48 | + qcom,gpu-freq = <27000000>; | |
| 49 | + }; | |
| 50 | + }; | |
| 51 | + }; | |
| 52 | +}; | |
| @@ -0,0 +1,46 @@ | ||
| 1 | +Qualcomm adreno/snapdragon hdmi output | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: one of the following | |
| 5 | + * "qcom,hdmi-tx-8660" | |
| 6 | + * "qcom,hdmi-tx-8960" | |
| 7 | +- reg: Physical base address and length of the controller's registers | |
| 8 | +- reg-names: "core_physical" | |
| 9 | +- interrupts: The interrupt signal from the hdmi block. | |
| 10 | +- clocks: device clocks | |
| 11 | + See ../clocks/clock-bindings.txt for details. | |
| 12 | +- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin | |
| 13 | +- qcom,hdmi-tx-ddc-data-gpio: ddc data pin | |
| 14 | +- qcom,hdmi-tx-hpd-gpio: hpd pin | |
| 15 | +- core-vdda-supply: phandle to supply regulator | |
| 16 | +- hdmi-mux-supply: phandle to mux regulator | |
| 17 | + | |
| 18 | +Optional properties: | |
| 19 | +- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin | |
| 20 | +- qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin | |
| 21 | + | |
| 22 | +Example: | |
| 23 | + | |
| 24 | +/ { | |
| 25 | + ... | |
| 26 | + | |
| 27 | + hdmi: qcom,hdmi-tx-8960@4a00000 { | |
| 28 | + compatible = "qcom,hdmi-tx-8960"; | |
| 29 | + reg-names = "core_physical"; | |
| 30 | + reg = <0x04a00000 0x1000>; | |
| 31 | + interrupts = <GIC_SPI 79 0>; | |
| 32 | + clock-names = | |
| 33 | + "core_clk", | |
| 34 | + "master_iface_clk", | |
| 35 | + "slave_iface_clk"; | |
| 36 | + clocks = | |
| 37 | + <&mmcc HDMI_APP_CLK>, | |
| 38 | + <&mmcc HDMI_M_AHB_CLK>, | |
| 39 | + <&mmcc HDMI_S_AHB_CLK>; | |
| 40 | + qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>; | |
| 41 | + qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>; | |
| 42 | + qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>; | |
| 43 | + core-vdda-supply = <&pm8921_hdmi_mvs>; | |
| 44 | + hdmi-mux-supply = <&ext_3p3v>; | |
| 45 | + }; | |
| 46 | +}; | |
| @@ -0,0 +1,48 @@ | ||
| 1 | +Qualcomm adreno/snapdragon display controller | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: | |
| 5 | + * "qcom,mdp" - mdp4 | |
| 6 | +- reg: Physical base address and length of the controller's registers. | |
| 7 | +- interrupts: The interrupt signal from the display controller. | |
| 8 | +- connectors: array of phandles for output device(s) | |
| 9 | +- clocks: device clocks | |
| 10 | + See ../clocks/clock-bindings.txt for details. | |
| 11 | +- clock-names: the following clocks are required: | |
| 12 | + * "core_clk" | |
| 13 | + * "iface_clk" | |
| 14 | + * "lut_clk" | |
| 15 | + * "src_clk" | |
| 16 | + * "hdmi_clk" | |
| 17 | + * "mpd_clk" | |
| 18 | + | |
| 19 | +Optional properties: | |
| 20 | +- gpus: phandle for gpu device | |
| 21 | + | |
| 22 | +Example: | |
| 23 | + | |
| 24 | +/ { | |
| 25 | + ... | |
| 26 | + | |
| 27 | + mdp: qcom,mdp@5100000 { | |
| 28 | + compatible = "qcom,mdp"; | |
| 29 | + reg = <0x05100000 0xf0000>; | |
| 30 | + interrupts = <GIC_SPI 75 0>; | |
| 31 | + connectors = <&hdmi>; | |
| 32 | + gpus = <&gpu>; | |
| 33 | + clock-names = | |
| 34 | + "core_clk", | |
| 35 | + "iface_clk", | |
| 36 | + "lut_clk", | |
| 37 | + "src_clk", | |
| 38 | + "hdmi_clk", | |
| 39 | + "mdp_clk"; | |
| 40 | + clocks = | |
| 41 | + <&mmcc MDP_SRC>, | |
| 42 | + <&mmcc MDP_AHB_CLK>, | |
| 43 | + <&mmcc MDP_LUT_CLK>, | |
| 44 | + <&mmcc TV_SRC>, | |
| 45 | + <&mmcc HDMI_TV_CLK>, | |
| 46 | + <&mmcc MDP_TV_CLK>; | |
| 47 | + }; | |
| 48 | +}; | |
| @@ -0,0 +1,40 @@ | ||
| 1 | +NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block. | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible : should be: | |
| 5 | + "nvidia,tegra20-efuse" | |
| 6 | + "nvidia,tegra30-efuse" | |
| 7 | + "nvidia,tegra114-efuse" | |
| 8 | + "nvidia,tegra124-efuse" | |
| 9 | + Details: | |
| 10 | + nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data | |
| 11 | + due to a hardware bug. Tegra20 also lacks certain information which is | |
| 12 | + available in later generations such as fab code, lot code, wafer id,.. | |
| 13 | + nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse: | |
| 14 | + The differences between these SoCs are the size of the efuse array, | |
| 15 | + the location of the spare (OEM programmable) bits and the location of | |
| 16 | + the speedo data. | |
| 17 | +- reg: Should contain 1 entry: the entry gives the physical address and length | |
| 18 | + of the fuse registers. | |
| 19 | +- clocks: Must contain an entry for each entry in clock-names. | |
| 20 | + See ../clocks/clock-bindings.txt for details. | |
| 21 | +- clock-names: Must include the following entries: | |
| 22 | + - fuse | |
| 23 | +- resets: Must contain an entry for each entry in reset-names. | |
| 24 | + See ../reset/reset.txt for details. | |
| 25 | +- reset-names: Must include the following entries: | |
| 26 | + - fuse | |
| 27 | + | |
| 28 | +Example: | |
| 29 | + | |
| 30 | + fuse@7000f800 { | |
| 31 | + compatible = "nvidia,tegra20-efuse"; | |
| 32 | + reg = <0x7000F800 0x400>, | |
| 33 | + <0x70000000 0x400>; | |
| 34 | + clocks = <&tegra_car TEGRA20_CLK_FUSE>; | |
| 35 | + clock-names = "fuse"; | |
| 36 | + resets = <&tegra_car 39>; | |
| 37 | + reset-names = "fuse"; | |
| 38 | + }; | |
| 39 | + | |
| 40 | + | |
| @@ -0,0 +1,26 @@ | ||
| 1 | +Xilinx Zynq GPIO controller Device Tree Bindings | |
| 2 | +------------------------------------------- | |
| 3 | + | |
| 4 | +Required properties: | |
| 5 | +- #gpio-cells : Should be two | |
| 6 | + - First cell is the GPIO line number | |
| 7 | + - Second cell is used to specify optional | |
| 8 | + parameters (unused) | |
| 9 | +- compatible : Should be "xlnx,zynq-gpio-1.0" | |
| 10 | +- clocks : Clock specifier (see clock bindings for details) | |
| 11 | +- gpio-controller : Marks the device node as a GPIO controller. | |
| 12 | +- interrupts : Interrupt specifier (see interrupt bindings for | |
| 13 | + details) | |
| 14 | +- interrupt-parent : Must be core interrupt controller | |
| 15 | +- reg : Address and length of the register set for the device | |
| 16 | + | |
| 17 | +Example: | |
| 18 | + gpio@e000a000 { | |
| 19 | + #gpio-cells = <2>; | |
| 20 | + compatible = "xlnx,zynq-gpio-1.0"; | |
| 21 | + clocks = <&clkc 42>; | |
| 22 | + gpio-controller; | |
| 23 | + interrupt-parent = <&intc>; | |
| 24 | + interrupts = <0 20 4>; | |
| 25 | + reg = <0xe000a000 0x1000>; | |
| 26 | + }; | |
| @@ -0,0 +1,43 @@ | ||
| 1 | +NVIDIA GK20A Graphics Processing Unit | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: "nvidia,<chip>-<gpu>" | |
| 5 | + Currently recognized values: | |
| 6 | + - nvidia,tegra124-gk20a | |
| 7 | +- reg: Physical base address and length of the controller's registers. | |
| 8 | + Must contain two entries: | |
| 9 | + - first entry for bar0 | |
| 10 | + - second entry for bar1 | |
| 11 | +- interrupts: Must contain an entry for each entry in interrupt-names. | |
| 12 | + See ../interrupt-controller/interrupts.txt for details. | |
| 13 | +- interrupt-names: Must include the following entries: | |
| 14 | + - stall | |
| 15 | + - nonstall | |
| 16 | +- vdd-supply: regulator for supply voltage. | |
| 17 | +- clocks: Must contain an entry for each entry in clock-names. | |
| 18 | + See ../clocks/clock-bindings.txt for details. | |
| 19 | +- clock-names: Must include the following entries: | |
| 20 | + - gpu | |
| 21 | + - pwr | |
| 22 | +- resets: Must contain an entry for each entry in reset-names. | |
| 23 | + See ../reset/reset.txt for details. | |
| 24 | +- reset-names: Must include the following entries: | |
| 25 | + - gpu | |
| 26 | + | |
| 27 | +Example: | |
| 28 | + | |
| 29 | + gpu@0,57000000 { | |
| 30 | + compatible = "nvidia,gk20a"; | |
| 31 | + reg = <0x0 0x57000000 0x0 0x01000000>, | |
| 32 | + <0x0 0x58000000 0x0 0x01000000>; | |
| 33 | + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, | |
| 34 | + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
| 35 | + interrupt-names = "stall", "nonstall"; | |
| 36 | + vdd-supply = <&vdd_gpu>; | |
| 37 | + clocks = <&tegra_car TEGRA124_CLK_GPU>, | |
| 38 | + <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; | |
| 39 | + clock-names = "gpu", "pwr"; | |
| 40 | + resets = <&tegra_car 184>; | |
| 41 | + reset-names = "gpu"; | |
| 42 | + status = "disabled"; | |
| 43 | + }; | |
| @@ -0,0 +1,189 @@ | ||
| 1 | +STMicroelectronics stih4xx platforms | |
| 2 | + | |
| 3 | +- sti-vtg: video timing generator | |
| 4 | + Required properties: | |
| 5 | + - compatible: "st,vtg" | |
| 6 | + - reg: Physical base address of the IP registers and length of memory mapped region. | |
| 7 | + Optional properties: | |
| 8 | + - interrupts : VTG interrupt number to the CPU. | |
| 9 | + - st,slave: phandle on a slave vtg | |
| 10 | + | |
| 11 | +- sti-vtac: video timing advanced inter dye communication Rx and TX | |
| 12 | + Required properties: | |
| 13 | + - compatible: "st,vtac-main" or "st,vtac-aux" | |
| 14 | + - reg: Physical base address of the IP registers and length of memory mapped region. | |
| 15 | + - clocks: from common clock binding: handle hardware IP needed clocks, the | |
| 16 | + number of clocks may depend of the SoC type. | |
| 17 | + See ../clocks/clock-bindings.txt for details. | |
| 18 | + - clock-names: names of the clocks listed in clocks property in the same | |
| 19 | + order. | |
| 20 | + | |
| 21 | +- sti-display-subsystem: Master device for DRM sub-components | |
| 22 | + This device must be the parent of all the sub-components and is responsible | |
| 23 | + of bind them. | |
| 24 | + Required properties: | |
| 25 | + - compatible: "st,sti-display-subsystem" | |
| 26 | + - ranges: to allow probing of subdevices | |
| 27 | + | |
| 28 | +- sti-compositor: frame compositor engine | |
| 29 | + must be a child of sti-display-subsystem | |
| 30 | + Required properties: | |
| 31 | + - compatible: "st,stih<chip>-compositor" | |
| 32 | + - reg: Physical base address of the IP registers and length of memory mapped region. | |
| 33 | + - clocks: from common clock binding: handle hardware IP needed clocks, the | |
| 34 | + number of clocks may depend of the SoC type. | |
| 35 | + See ../clocks/clock-bindings.txt for details. | |
| 36 | + - clock-names: names of the clocks listed in clocks property in the same | |
| 37 | + order. | |
| 38 | + - resets: resets to be used by the device | |
| 39 | + See ../reset/reset.txt for details. | |
| 40 | + - reset-names: names of the resets listed in resets property in the same | |
| 41 | + order. | |
| 42 | + - st,vtg: phandle(s) on vtg device (main and aux) nodes. | |
| 43 | + | |
| 44 | +- sti-tvout: video out hardware block | |
| 45 | + must be a child of sti-display-subsystem | |
| 46 | + Required properties: | |
| 47 | + - compatible: "st,stih<chip>-tvout" | |
| 48 | + - reg: Physical base address of the IP registers and length of memory mapped region. | |
| 49 | + - reg-names: names of the mapped memory regions listed in regs property in | |
| 50 | + the same order. | |
| 51 | + - resets: resets to be used by the device | |
| 52 | + See ../reset/reset.txt for details. | |
| 53 | + - reset-names: names of the resets listed in resets property in the same | |
| 54 | + order. | |
| 55 | + - ranges: to allow probing of subdevices | |
| 56 | + | |
| 57 | +- sti-hdmi: hdmi output block | |
| 58 | + must be a child of sti-tvout | |
| 59 | + Required properties: | |
| 60 | + - compatible: "st,stih<chip>-hdmi"; | |
| 61 | + - reg: Physical base address of the IP registers and length of memory mapped region. | |
| 62 | + - reg-names: names of the mapped memory regions listed in regs property in | |
| 63 | + the same order. | |
| 64 | + - interrupts : HDMI interrupt number to the CPU. | |
| 65 | + - interrupt-names: name of the interrupts listed in interrupts property in | |
| 66 | + the same order | |
| 67 | + - clocks: from common clock binding: handle hardware IP needed clocks, the | |
| 68 | + number of clocks may depend of the SoC type. | |
| 69 | + - clock-names: names of the clocks listed in clocks property in the same | |
| 70 | + order. | |
| 71 | + - hdmi,hpd-gpio: gpio id to detect if an hdmi cable is plugged or not. | |
| 72 | + | |
| 73 | +sti-hda: | |
| 74 | + Required properties: | |
| 75 | + must be a child of sti-tvout | |
| 76 | + - compatible: "st,stih<chip>-hda" | |
| 77 | + - reg: Physical base address of the IP registers and length of memory mapped region. | |
| 78 | + - reg-names: names of the mapped memory regions listed in regs property in | |
| 79 | + the same order. | |
| 80 | + - clocks: from common clock binding: handle hardware IP needed clocks, the | |
| 81 | + number of clocks may depend of the SoC type. | |
| 82 | + See ../clocks/clock-bindings.txt for details. | |
| 83 | + - clock-names: names of the clocks listed in clocks property in the same | |
| 84 | + order. | |
| 85 | + | |
| 86 | +Example: | |
| 87 | + | |
| 88 | +/ { | |
| 89 | + ... | |
| 90 | + | |
| 91 | + vtg_main_slave: sti-vtg-main-slave@fe85A800 { | |
| 92 | + compatible = "st,vtg"; | |
| 93 | + reg = <0xfe85A800 0x300>; | |
| 94 | + interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>; | |
| 95 | + }; | |
| 96 | + | |
| 97 | + vtg_main: sti-vtg-main-master@fd348000 { | |
| 98 | + compatible = "st,vtg"; | |
| 99 | + reg = <0xfd348000 0x400>; | |
| 100 | + st,slave = <&vtg_main_slave>; | |
| 101 | + }; | |
| 102 | + | |
| 103 | + vtg_aux_slave: sti-vtg-aux-slave@fd348400 { | |
| 104 | + compatible = "st,vtg"; | |
| 105 | + reg = <0xfe858200 0x300>; | |
| 106 | + interrupts = <GIC_SPI 176 IRQ_TYPE_NONE>; | |
| 107 | + }; | |
| 108 | + | |
| 109 | + vtg_aux: sti-vtg-aux-master@fd348400 { | |
| 110 | + compatible = "st,vtg"; | |
| 111 | + reg = <0xfd348400 0x400>; | |
| 112 | + st,slave = <&vtg_aux_slave>; | |
| 113 | + }; | |
| 114 | + | |
| 115 | + | |
| 116 | + sti-vtac-rx-main@fee82800 { | |
| 117 | + compatible = "st,vtac-main"; | |
| 118 | + reg = <0xfee82800 0x200>; | |
| 119 | + clock-names = "vtac"; | |
| 120 | + clocks = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>; | |
| 121 | + }; | |
| 122 | + | |
| 123 | + sti-vtac-rx-aux@fee82a00 { | |
| 124 | + compatible = "st,vtac-aux"; | |
| 125 | + reg = <0xfee82a00 0x200>; | |
| 126 | + clock-names = "vtac"; | |
| 127 | + clocks = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>; | |
| 128 | + }; | |
| 129 | + | |
| 130 | + sti-vtac-tx-main@fd349000 { | |
| 131 | + compatible = "st,vtac-main"; | |
| 132 | + reg = <0xfd349000 0x200>, <0xfd320000 0x10000>; | |
| 133 | + clock-names = "vtac"; | |
| 134 | + clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>; | |
| 135 | + }; | |
| 136 | + | |
| 137 | + sti-vtac-tx-aux@fd349200 { | |
| 138 | + compatible = "st,vtac-aux"; | |
| 139 | + reg = <0xfd349200 0x200>, <0xfd320000 0x10000>; | |
| 140 | + clock-names = "vtac"; | |
| 141 | + clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>; | |
| 142 | + }; | |
| 143 | + | |
| 144 | + sti-display-subsystem { | |
| 145 | + compatible = "st,sti-display-subsystem"; | |
| 146 | + ranges; | |
| 147 | + | |
| 148 | + sti-compositor@fd340000 { | |
| 149 | + compatible = "st,stih416-compositor"; | |
| 150 | + reg = <0xfd340000 0x1000>; | |
| 151 | + clock-names = "compo_main", "compo_aux", | |
| 152 | + "pix_main", "pix_aux"; | |
| 153 | + clocks = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>, | |
| 154 | + <&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>; | |
| 155 | + reset-names = "compo-main", "compo-aux"; | |
| 156 | + resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>; | |
| 157 | + st,vtg = <&vtg_main>, <&vtg_aux>; | |
| 158 | + }; | |
| 159 | + | |
| 160 | + sti-tvout@fe000000 { | |
| 161 | + compatible = "st,stih416-tvout"; | |
| 162 | + reg = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>; | |
| 163 | + reg-names = "tvout-reg", "hda-reg", "syscfg"; | |
| 164 | + reset-names = "tvout"; | |
| 165 | + resets = <&softreset STIH416_HDTVOUT_SOFTRESET>; | |
| 166 | + ranges; | |
| 167 | + | |
| 168 | + sti-hdmi@fe85c000 { | |
| 169 | + compatible = "st,stih416-hdmi"; | |
| 170 | + reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>; | |
| 171 | + reg-names = "hdmi-reg", "syscfg"; | |
| 172 | + interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>; | |
| 173 | + interrupt-names = "irq"; | |
| 174 | + clock-names = "pix", "tmds", "phy", "audio"; | |
| 175 | + clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>; | |
| 176 | + hdmi,hpd-gpio = <&PIO2 5>; | |
| 177 | + }; | |
| 178 | + | |
| 179 | + sti-hda@fe85a000 { | |
| 180 | + compatible = "st,stih416-hda"; | |
| 181 | + reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>; | |
| 182 | + reg-names = "hda-reg", "video-dacs-ctrl"; | |
| 183 | + clock-names = "pix", "hddac"; | |
| 184 | + clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>; | |
| 185 | + }; | |
| 186 | + }; | |
| 187 | + }; | |
| 188 | + ... | |
| 189 | +}; | |
| @@ -10,7 +10,7 @@ Required properties : · 9 unmodified lines | ||
| 10 | 10 | Recommended properties : |
| 11 | 11 | |
| 12 | 12 | - clock-frequency : maximal I2C bus clock frequency in Hz. |
| 13 | − - efm32,location : Decides the location of the USART I/O pins. | |
| 13 | + - energymicro,location : Decides the location of the USART I/O pins. | |
| 14 | 14 | Allowed range : [0 .. 6] |
| 15 | 15 | |
| 16 | 16 | Example: |
| @@ -23,7 +23,7 @@ Example: · 6 unmodified lines | ||
| 23 | 23 | clocks = <&cmu clk_HFPERCLKI2C0>; |
| 24 | 24 | clock-frequency = <100000>; |
| 25 | 25 | status = "ok"; |
| 26 | − efm32,location = <3>; | |
| 26 | + energymicro,location = <3>; | |
| 27 | 27 | |
| 28 | 28 | eeprom@50 { |
| 29 | 29 | compatible = "microchip,24c02"; |
| @@ -70,6 +70,7 @@ nuvoton,npct501 i2c trusted platform module (TPM) · 69 unmodified lines | ||
| 70 | 70 | nxp,pca9556 Octal SMBus and I2C registered interface |
| 71 | 71 | nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset |
| 72 | 72 | nxp,pcf8563 Real-time clock/calendar |
| 73 | +nxp,pcf85063 Tiny Real-Time Clock | |
| 73 | 74 | ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus |
| 74 | 75 | pericom,pt7c4338 Real-time Clock Module |
| 75 | 76 | plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch |
| @@ -0,0 +1,25 @@ | ||
| 1 | +Atmel maXTouch touchscreen/touchpad | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: | |
| 5 | + atmel,maxtouch | |
| 6 | + | |
| 7 | +- reg: The I2C address of the device | |
| 8 | + | |
| 9 | +- interrupts: The sink for the touchpad's IRQ output | |
| 10 | + See ../interrupt-controller/interrupts.txt | |
| 11 | + | |
| 12 | +Optional properties for main touchpad device: | |
| 13 | + | |
| 14 | +- linux,gpio-keymap: An array of up to 4 entries indicating the Linux | |
| 15 | + keycode generated by each GPIO. Linux keycodes are defined in | |
| 16 | + <dt-bindings/input/input.h>. | |
| 17 | + | |
| 18 | +Example: | |
| 19 | + | |
| 20 | + touch@4b { | |
| 21 | + compatible = "atmel,maxtouch"; | |
| 22 | + reg = <0x4b>; | |
| 23 | + interrupt-parent = <&gpio>; | |
| 24 | + interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>; | |
| 25 | + }; | |
| @@ -0,0 +1,53 @@ | ||
| 1 | +Device tree bindings for Microchip CAP1106, 6 channel capacitive touch sensor | |
| 2 | + | |
| 3 | +The node for this driver must be a child of a I2C controller node, as the | |
| 4 | +device communication via I2C only. | |
| 5 | + | |
| 6 | +Required properties: | |
| 7 | + | |
| 8 | + compatible: Must be "microchip,cap1106" | |
| 9 | + | |
| 10 | + reg: The I2C slave address of the device. | |
| 11 | + Only 0x28 is valid. | |
| 12 | + | |
| 13 | + interrupts: Property describing the interrupt line the | |
| 14 | + device's ALERT#/CM_IRQ# pin is connected to. | |
| 15 | + The device only has one interrupt source. | |
| 16 | + | |
| 17 | +Optional properties: | |
| 18 | + | |
| 19 | + autorepeat: Enables the Linux input system's autorepeat | |
| 20 | + feature on the input device. | |
| 21 | + | |
| 22 | + microchip,sensor-gain: Defines the gain of the sensor circuitry. This | |
| 23 | + effectively controls the sensitivity, as a | |
| 24 | + smaller delta capacitance is required to | |
| 25 | + generate the same delta count values. | |
| 26 | + Valid values are 1, 2, 4, and 8. | |
| 27 | + By default, a gain of 1 is set. | |
| 28 | + | |
| 29 | + linux,keycodes: Specifies an array of numeric keycode values to | |
| 30 | + be used for the channels. If this property is | |
| 31 | + omitted, KEY_A, KEY_B, etc are used as | |
| 32 | + defaults. The array must have exactly six | |
| 33 | + entries. | |
| 34 | + | |
| 35 | +Example: | |
| 36 | + | |
| 37 | +i2c_controller { | |
| 38 | + cap1106@28 { | |
| 39 | + compatible = "microchip,cap1106"; | |
| 40 | + interrupt-parent = <&gpio1>; | |
| 41 | + interrupts = <0 0>; | |
| 42 | + reg = <0x28>; | |
| 43 | + autorepeat; | |
| 44 | + microchip,sensor-gain = <2>; | |
| 45 | + | |
| 46 | + linux,keycodes = <103 /* KEY_UP */ | |
| 47 | + 106 /* KEY_RIGHT */ | |
| 48 | + 108 /* KEY_DOWN */ | |
| 49 | + 105 /* KEY_LEFT */ | |
| 50 | + 109 /* KEY_PAGEDOWN */ | |
| 51 | + 104>; /* KEY_PAGEUP */ | |
| 52 | + }; | |
| 53 | +} | |
| @@ -0,0 +1,26 @@ | ||
| 1 | +* Pixcir I2C touchscreen controllers | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: must be "pixcir,pixcir_ts" or "pixcir,pixcir_tangoc" | |
| 5 | +- reg: I2C address of the chip | |
| 6 | +- interrupts: interrupt to which the chip is connected | |
| 7 | +- attb-gpio: GPIO connected to the ATTB line of the chip | |
| 8 | +- touchscreen-size-x: horizontal resolution of touchscreen (in pixels) | |
| 9 | +- touchscreen-size-y: vertical resolution of touchscreen (in pixels) | |
| 10 | + | |
| 11 | +Example: | |
| 12 | + | |
| 13 | + i2c@00000000 { | |
| 14 | + /* ... */ | |
| 15 | + | |
| 16 | + pixcir_ts@5c { | |
| 17 | + compatible = "pixcir,pixcir_ts"; | |
| 18 | + reg = <0x5c>; | |
| 19 | + interrupts = <2 0>; | |
| 20 | + attb-gpio = <&gpf 2 0 2>; | |
| 21 | + touchscreen-size-x = <800>; | |
| 22 | + touchscreen-size-y = <600>; | |
| 23 | + }; | |
| 24 | + | |
| 25 | + /* ... */ | |
| 26 | + }; | |
| @@ -9,6 +9,9 @@ Required properties: · 8 unmodified lines | ||
| 9 | 9 | - x-size: horizontal resolution of touchscreen |
| 10 | 10 | - y-size: vertical resolution of touchscreen |
| 11 | 11 | |
| 12 | +Optional properties: | |
| 13 | +- vdd-supply: Regulator controlling the controller supply | |
| 14 | + | |
| 12 | 15 | Example: |
| 13 | 16 | |
| 14 | 17 | i2c@00000000 { |
| @@ -18,6 +21,7 @@ Example: · 3 unmodified lines | ||
| 18 | 21 | compatible = "neonode,zforce"; |
| 19 | 22 | reg = <0x50>; |
| 20 | 23 | interrupts = <2 0>; |
| 24 | + vdd-supply = <®_zforce_vdd>; | |
| 21 | 25 | |
| 22 | 26 | gpios = <&gpio5 6 0>, /* INT */ |
| 23 | 27 | <&gpio5 9 0>; /* RST */ |
| @@ -4,11 +4,13 @@ Specifying interrupt information for devices · 3 unmodified lines | ||
| 4 | 4 | 1) Interrupt client nodes |
| 5 | 5 | ------------------------- |
| 6 | 6 | |
| 7 | −Nodes that describe devices which generate interrupts must contain an either an | |
| 8 | −"interrupts" property or an "interrupts-extended" property. These properties | |
| 9 | −contain a list of interrupt specifiers, one per output interrupt. The format of | |
| 10 | −the interrupt specifier is determined by the interrupt controller to which the | |
| 11 | −interrupts are routed; see section 2 below for details. | |
| 7 | +Nodes that describe devices which generate interrupts must contain an | |
| 8 | +"interrupts" property, an "interrupts-extended" property, or both. If both are | |
| 9 | +present, the latter should take precedence; the former may be provided simply | |
| 10 | +for compatibility with software that does not recognize the latter. These | |
| 11 | +properties contain a list of interrupt specifiers, one per output interrupt. The | |
| 12 | +format of the interrupt specifier is determined by the interrupt controller to | |
| 13 | +which the interrupts are routed; see section 2 below for details. | |
| 12 | 14 | |
| 13 | 15 | Example: |
| 14 | 16 | interrupt-parent = <&intc1>; |
| @@ -1,18 +1,19 @@ | ||
| 1 | 1 | LEDs connected to pca9632, pca9633 or pca9634 |
| 2 | 2 | |
| 3 | 3 | Required properties: |
| 4 | −- compatible : should be : "nxp,pca9632", "nxp,pca9633" or "nxp,pca9634" | |
| 4 | +- compatible : should be : "nxp,pca9632", "nxp,pca9633", "nxp,pca9634" or "nxp,pca9635" | |
| 5 | 5 | |
| 6 | 6 | Optional properties: |
| 7 | −- nxp,totem-pole : use totem pole (push-pull) instead of default open-drain | |
| 7 | +- nxp,totem-pole : use totem pole (push-pull) instead of open-drain (pca9632 defaults | |
| 8 | + to open-drain, newer chips to totem pole) | |
| 8 | 9 | - nxp,hw-blink : use hardware blinking instead of software blinking |
| 9 | 10 | |
| 10 | 11 | Each led is represented as a sub-node of the nxp,pca963x device. |
| 11 | 12 | |
| 12 | 13 | LED sub-node properties: |
| 13 | 14 | - label : (optional) see Documentation/devicetree/bindings/leds/common.txt |
| 14 | −- reg : number of LED line (could be from 0 to 3 in pca9632 or pca9633 | |
| 15 | − or 0 to 7 in pca9634) | |
| 15 | +- reg : number of LED line (could be from 0 to 3 in pca9632 or pca9633, | |
| 16 | + 0 to 7 in pca9634, or 0 to 15 in pca9635) | |
| 16 | 17 | - linux,default-trigger : (optional) |
| 17 | 18 | see Documentation/devicetree/bindings/leds/common.txt |
| 18 | 19 | |
| @@ -8,7 +8,7 @@ Required properties: · 7 unmodified lines | ||
| 8 | 8 | |
| 9 | 9 | Optional properties: |
| 10 | 10 | - gpio-controller: allows lines to be used as output-only GPIOs. |
| 11 | −- #gpio-cells: if present, must be 0. | |
| 11 | +- #gpio-cells: if present, must not be 0. | |
| 12 | 12 | |
| 13 | 13 | Each led is represented as a sub-node of the ti,tca6507 device. |
| 14 | 14 | |
| @@ -42,6 +42,16 @@ Optional properties: · 41 unmodified lines | ||
| 42 | 42 | the chip default will be used. If present exactly five values must |
| 43 | 43 | be specified. |
| 44 | 44 | |
| 45 | + - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if | |
| 46 | + they are being externally supplied. As covered in | |
| 47 | + Documentation/devicetree/bindings/regulator/regulator.txt | |
| 48 | + | |
| 49 | +Optional subnodes: | |
| 50 | + - ldo1 : Initial data for the LDO1 regulator, as covered in | |
| 51 | + Documentation/devicetree/bindings/regulator/regulator.txt | |
| 52 | + - micvdd : Initial data for the MICVDD regulator, as covered in | |
| 53 | + Documentation/devicetree/bindings/regulator/regulator.txt | |
| 54 | + | |
| 45 | 55 | Example: |
| 46 | 56 | |
| 47 | 57 | codec: wm5102@1a { |
| @@ -13,6 +13,14 @@ Required properties: · 12 unmodified lines | ||
| 13 | 13 | The second cell is the flags, encoded as the trigger masks from binding document |
| 14 | 14 | interrupts.txt, using dt-bindings/irq. |
| 15 | 15 | |
| 16 | +Optional properties: | |
| 17 | +-------------------- | |
| 18 | +- ams,enable-internal-int-pullup: Boolean property, to enable internal pullup on | |
| 19 | + interrupt pin. Missing this will disable internal pullup on INT pin. | |
| 20 | +- ams,enable-internal-i2c-pullup: Boolean property, to enable internal pullup on | |
| 21 | + i2c scl/sda pins. Missing this will disable internal pullup on i2c | |
| 22 | + scl/sda lines. | |
| 23 | + | |
| 16 | 24 | Optional submodule and their properties: |
| 17 | 25 | ======================================= |
| 18 | 26 | |
| @@ -1,5 +1,5 @@ | ||
| 1 | 1 | |
| 2 | −* Samsung S2MPS11 and S2MPS14 Voltage and Current Regulator | |
| 2 | +* Samsung S2MPS11, S2MPS14 and S2MPU02 Voltage and Current Regulator | |
| 3 | 3 | |
| 4 | 4 | The Samsung S2MPS11 is a multi-function device which includes voltage and |
| 5 | 5 | current regulators, RTC, charger controller and other sub-blocks. It is |
| @@ -7,7 +7,8 @@ interfaced to the host controller using an I2C interface. Each sub-block is · 1 unmodified line | ||
| 7 | 7 | addressed by the host system using different I2C slave addresses. |
| 8 | 8 | |
| 9 | 9 | Required properties: |
| 10 | −- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps14-pmic". | |
| 10 | +- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps14-pmic" | |
| 11 | + or "samsung,s2mpu02-pmic". | |
| 11 | 12 | - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. |
| 12 | 13 | |
| 13 | 14 | Optional properties: |
| @@ -81,11 +82,13 @@ as per the datasheet of s2mps11. · 67 unmodified lines | ||
| 81 | 82 | - valid values for n are: |
| 82 | 83 | - S2MPS11: 1 to 38 |
| 83 | 84 | - S2MPS14: 1 to 25 |
| 84 | − - Example: LDO1, LD02, LDO28 | |
| 85 | + - S2MPU02: 1 to 28 | |
| 86 | + - Example: LDO1, LDO2, LDO28 | |
| 85 | 87 | - BUCKn |
| 86 | 88 | - valid values for n are: |
| 87 | 89 | - S2MPS11: 1 to 10 |
| 88 | 90 | - S2MPS14: 1 to 5 |
| 91 | + - S2MPU02: 1 to 7 | |
| 89 | 92 | - Example: BUCK1, BUCK2, BUCK9 |
| 90 | 93 | |
| 91 | 94 | Example: |
| @@ -96,7 +99,7 @@ Example: · 4 unmodified lines | ||
| 96 | 99 | |
| 97 | 100 | s2m_osc: clocks { |
| 98 | 101 | compatible = "samsung,s2mps11-clk"; |
| 99 | − #clock-cells = 1; | |
| 102 | + #clock-cells = <1>; | |
| 100 | 103 | clock-output-names = "xx", "yy", "zz"; |
| 101 | 104 | }; |
| 102 | 105 | |
| @@ -4,7 +4,7 @@ PRCM is an MFD device exposing several Power Management related devices · 3 unmodified lines | ||
| 4 | 4 | (like clks and reset controllers). |
| 5 | 5 | |
| 6 | 6 | Required properties: |
| 7 | − - compatible: "allwinner,sun6i-a31-prcm" | |
| 7 | + - compatible: "allwinner,sun6i-a31-prcm" or "allwinner,sun8i-a23-prcm" | |
| 8 | 8 | - reg: The PRCM registers range |
| 9 | 9 | |
| 10 | 10 | The prcm node may contain several subdevices definitions: |
| @@ -0,0 +1,13 @@ | ||
| 1 | +NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible : should be: | |
| 5 | + "nvidia,tegra20-apbmisc" | |
| 6 | + "nvidia,tegra30-apbmisc" | |
| 7 | + "nvidia,tegra114-apbmisc" | |
| 8 | + "nvidia,tegra124-apbmisc" | |
| 9 | +- reg: Should contain 2 entries: the first entry gives the physical address | |
| 10 | + and length of the registers which contain revision and debug features. | |
| 11 | + The second entry gives the physical address and length of the | |
| 12 | + registers indicating the strapping options. | |
| 13 | + | |
| @@ -46,13 +46,14 @@ Required Properties: · 45 unmodified lines | ||
| 46 | 46 | - if CIU clock divider value is 0 (that is divide by 1), both tx and rx |
| 47 | 47 | phase shift clocks should be 0. |
| 48 | 48 | |
| 49 | −Required properties for a slot: | |
| 49 | +Required properties for a slot (Deprecated - Recommend to use one slot per host): | |
| 50 | 50 | |
| 51 | 51 | * gpios: specifies a list of gpios used for command, clock and data bus. The |
| 52 | 52 | first gpio is the command line and the second gpio is the clock line. The |
| 53 | 53 | rest of the gpios (depending on the bus-width property) are the data lines in |
| 54 | 54 | no particular order. The format of the gpio specifier depends on the gpio |
| 55 | 55 | controller. |
| 56 | +(Deprecated - Refer to Documentation/devicetree/binding/pinctrl/samsung-pinctrl.txt) | |
| 56 | 57 | |
| 57 | 58 | Example: |
| 58 | 59 | |
| @@ -69,21 +70,13 @@ Example: · 10 unmodified lines | ||
| 69 | 70 | |
| 70 | 71 | dwmmc0@12200000 { |
| 71 | 72 | num-slots = <1>; |
| 72 | − supports-highspeed; | |
| 73 | + cap-mmc-highspeed; | |
| 74 | + cap-sd-highspeed; | |
| 73 | 75 | broken-cd; |
| 74 | 76 | fifo-depth = <0x80>; |
| 75 | 77 | card-detect-delay = <200>; |
| 76 | 78 | samsung,dw-mshc-ciu-div = <3>; |
| 77 | 79 | samsung,dw-mshc-sdr-timing = <2 3>; |
| 78 | 80 | samsung,dw-mshc-ddr-timing = <1 2>; |
| 79 | − | |
| 80 | − slot@0 { | |
| 81 | − reg = <0>; | |
| 82 | − bus-width = <8>; | |
| 83 | − gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>, | |
| 84 | − <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>, | |
| 85 | − <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>, | |
| 86 | − <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>, | |
| 87 | − <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>; | |
| 88 | − }; | |
| 81 | + bus-width = <8>; | |
| 89 | 82 | }; |
| @@ -34,13 +34,11 @@ Example: · 33 unmodified lines | ||
| 34 | 34 | num-slots = <1>; |
| 35 | 35 | vmmc-supply = <&ldo12>; |
| 36 | 36 | fifo-depth = <0x100>; |
| 37 | − supports-highspeed; | |
| 38 | 37 | pinctrl-names = "default"; |
| 39 | 38 | pinctrl-0 = <&sd_pmx_pins &sd_cfg_func1 &sd_cfg_func2>; |
| 40 | − slot@0 { | |
| 41 | − reg = <0>; | |
| 42 | − bus-width = <4>; | |
| 43 | − disable-wp; | |
| 44 | − cd-gpios = <&gpio10 3 0>; | |
| 45 | − }; | |
| 39 | + bus-width = <4>; | |
| 40 | + disable-wp; | |
| 41 | + cd-gpios = <&gpio10 3 0>; | |
| 42 | + cap-mmc-highspeed; | |
| 43 | + cap-sd-highspeed; | |
| 46 | 44 | }; |
| @@ -34,8 +34,8 @@ Optional properties: · 33 unmodified lines | ||
| 34 | 34 | - cap-power-off-card: powering off the card is safe |
| 35 | 35 | - cap-sdio-irq: enable SDIO IRQ signalling on this interface |
| 36 | 36 | - full-pwr-cycle: full power cycle of the card is supported |
| 37 | −- mmc-highspeed-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported | |
| 38 | −- mmc-highspeed-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported | |
| 37 | +- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported | |
| 38 | +- mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported | |
| 39 | 39 | - mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported |
| 40 | 40 | - mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported |
| 41 | 41 | - mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported |
| @@ -0,0 +1,32 @@ | ||
| 1 | +* Renesas Multi Media Card Interface (MMCIF) Controller | |
| 2 | + | |
| 3 | +This file documents differences between the core properties in mmc.txt | |
| 4 | +and the properties used by the MMCIF device. | |
| 5 | + | |
| 6 | + | |
| 7 | +Required properties: | |
| 8 | + | |
| 9 | +- compatible: must contain one of the following | |
| 10 | + - "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs | |
| 11 | + - "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs | |
| 12 | + - "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs | |
| 13 | + - "renesas,sh-mmcif" for the generic MMCIF | |
| 14 | + | |
| 15 | +- clocks: reference to the functional clock | |
| 16 | + | |
| 17 | +- dmas: reference to the DMA channels, one per channel name listed in the | |
| 18 | + dma-names property. | |
| 19 | +- dma-names: must contain "tx" for the transmit DMA channel and "rx" for the | |
| 20 | + receive DMA channel. | |
| 21 | + | |
| 22 | + | |
| 23 | +Example: R8A7790 (R-Car H2) MMCIF0 | |
| 24 | + | |
| 25 | + mmcif0: mmc@ee200000 { | |
| 26 | + compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; | |
| 27 | + reg = <0 0xee200000 0 0x80>; | |
| 28 | + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; | |
| 29 | + clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; | |
| 30 | + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; | |
| 31 | + dma-names = "tx", "rx"; | |
| 32 | + }; | |
| @@ -27,8 +27,8 @@ Example: · 26 unmodified lines | ||
| 27 | 27 | bus-width = <8>; |
| 28 | 28 | non-removable; |
| 29 | 29 | |
| 30 | − vmmc = <&pm8941_l20>; | |
| 31 | − vqmmc = <&pm8941_s3>; | |
| 30 | + vmmc-supply = <&pm8941_l20>; | |
| 31 | + vqmmc-supply = <&pm8941_s3>; | |
| 32 | 32 | |
| 33 | 33 | pinctrl-names = "default"; |
| 34 | 34 | pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>; |
| @@ -44,8 +44,8 @@ Example: · 9 unmodified lines | ||
| 44 | 44 | bus-width = <4>; |
| 45 | 45 | cd-gpios = <&msmgpio 62 0x1>; |
| 46 | 46 | |
| 47 | − vmmc = <&pm8941_l21>; | |
| 48 | − vqmmc = <&pm8941_l13>; | |
| 47 | + vmmc-supply = <&pm8941_l21>; | |
| 48 | + vqmmc-supply = <&pm8941_l13>; | |
| 49 | 49 | |
| 50 | 50 | pinctrl-names = "default"; |
| 51 | 51 | pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>; |
| @@ -0,0 +1,33 @@ | ||
| 1 | +* STMicroelectronics sdhci-st MMC/SD controller | |
| 2 | + | |
| 3 | +This file documents the differences between the core properties in | |
| 4 | +Documentation/devicetree/bindings/mmc/mmc.txt and the properties | |
| 5 | +used by the sdhci-st driver. | |
| 6 | + | |
| 7 | +Required properties: | |
| 8 | +- compatible : Must be "st,sdhci" | |
| 9 | +- clock-names : Should be "mmc" | |
| 10 | + See: Documentation/devicetree/bindings/resource-names.txt | |
| 11 | +- clocks : Phandle of the clock used by the sdhci controler | |
| 12 | + See: Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| 13 | + | |
| 14 | +Optional properties: | |
| 15 | +- non-removable: non-removable slot | |
| 16 | + See: Documentation/devicetree/bindings/mmc/mmc.txt | |
| 17 | +- bus-width: Number of data lines | |
| 18 | + See: Documentation/devicetree/bindings/mmc/mmc.txt | |
| 19 | + | |
| 20 | +Example: | |
| 21 | + | |
| 22 | +mmc0: sdhci@fe81e000 { | |
| 23 | + compatible = "st,sdhci"; | |
| 24 | + status = "disabled"; | |
| 25 | + reg = <0xfe81e000 0x1000>; | |
| 26 | + interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>; | |
| 27 | + interrupt-names = "mmcirq"; | |
| 28 | + pinctrl-names = "default"; | |
| 29 | + pinctrl-0 = <&pinctrl_mmc0>; | |
| 30 | + clock-names = "mmc"; | |
| 31 | + clocks = <&clk_s_a1_ls 1>; | |
| 32 | + bus-width = <8> | |
| 33 | +}; | |
| @@ -67,7 +67,8 @@ Optional properties: · 66 unmodified lines | ||
| 67 | 67 | * card-detect-delay: Delay in milli-seconds before detecting card after card |
| 68 | 68 | insert event. The default value is 0. |
| 69 | 69 | |
| 70 | −* supports-highspeed: Enables support for high speed cards (up to 50MHz) | |
| 70 | +* supports-highspeed (DEPRECATED): Enables support for high speed cards (up to 50MHz) | |
| 71 | + (use "cap-mmc-highspeed" or "cap-sd-highspeed" instead) | |
| 71 | 72 | |
| 72 | 73 | * broken-cd: as documented in mmc core bindings. |
| 73 | 74 | |
| @@ -98,14 +99,11 @@ board specific portions as listed below. · 24 unmodified lines | ||
| 98 | 99 | clock-frequency = <400000000>; |
| 99 | 100 | clock-freq-min-max = <400000 200000000>; |
| 100 | 101 | num-slots = <1>; |
| 101 | − supports-highspeed; | |
| 102 | 102 | broken-cd; |
| 103 | 103 | fifo-depth = <0x80>; |
| 104 | 104 | card-detect-delay = <200>; |
| 105 | 105 | vmmc-supply = <&buck8>; |
| 106 | − | |
| 107 | − slot@0 { | |
| 108 | − reg = <0>; | |
| 109 | − bus-width = <8>; | |
| 110 | − }; | |
| 106 | + bus-width = <8>; | |
| 107 | + cap-mmc-highspeed; | |
| 108 | + cap-sd-highspeed; | |
| 111 | 109 | }; |
| @@ -12,6 +12,7 @@ Required properties: · 11 unmodified lines | ||
| 12 | 12 | Should be "ti,omap3-hsmmc", for OMAP3 controllers |
| 13 | 13 | Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0 |
| 14 | 14 | Should be "ti,omap4-hsmmc", for OMAP4 controllers |
| 15 | + Should be "ti,am33xx-hsmmc", for AM335x controllers | |
| 15 | 16 | - ti,hwmods: Must be "mmc<n>", n is controller instance starting 1 |
| 16 | 17 | |
| 17 | 18 | Optional properties: |
| @@ -56,3 +57,56 @@ Examples: · 38 unmodified lines | ||
| 56 | 57 | &edma 25>; |
| 57 | 58 | dma-names = "tx", "rx"; |
| 58 | 59 | }; |
| 60 | + | |
| 61 | +[workaround for missing swakeup on am33xx] | |
| 62 | + | |
| 63 | +This SOC is missing the swakeup line, it will not detect SDIO irq | |
| 64 | +while in suspend. | |
| 65 | + | |
| 66 | + ------ | |
| 67 | + | PRCM | | |
| 68 | + ------ | |
| 69 | + ^ | | |
| 70 | + swakeup | | fclk | |
| 71 | + | v | |
| 72 | + ------ ------- ----- | |
| 73 | + | card | -- CIRQ --> | hsmmc | -- IRQ --> | CPU | | |
| 74 | + ------ ------- ----- | |
| 75 | + | |
| 76 | +In suspend the fclk is off and the module is disfunctional. Even register reads | |
| 77 | +will fail. A small logic in the host will request fclk restore, when an | |
| 78 | +external event is detected. Once the clock is restored, the host detects the | |
| 79 | +event normally. Since am33xx doesn't have this line it never wakes from | |
| 80 | +suspend. | |
| 81 | + | |
| 82 | +The workaround is to reconfigure the dat1 line as a GPIO upon suspend. To make | |
| 83 | +this work, we need to set the named pinctrl states "default" and "idle". | |
| 84 | +Prepare idle to remux dat1 as a gpio, and default to remux it back as sdio | |
| 85 | +dat1. The MMC driver will then toggle between idle and default state during | |
| 86 | +runtime. | |
| 87 | + | |
| 88 | +In summary: | |
| 89 | +1. select matching 'compatible' section, see example below. | |
| 90 | +2. specify pinctrl states "default" and "idle", "sleep" is optional. | |
| 91 | +3. specify the gpio irq used for detecting sdio irq in suspend | |
| 92 | + | |
| 93 | +If configuration is incomplete, a warning message is emitted "falling back to | |
| 94 | +polling". Also check the "sdio irq mode" in /sys/kernel/debug/mmc0/regs. Mind | |
| 95 | +not every application needs SDIO irq, e.g. MMC cards. | |
| 96 | + | |
| 97 | + mmc1: mmc@48060100 { | |
| 98 | + compatible = "ti,am33xx-hsmmc"; | |
| 99 | + ... | |
| 100 | + pinctrl-names = "default", "idle", "sleep" | |
| 101 | + pinctrl-0 = <&mmc1_pins>; | |
| 102 | + pinctrl-1 = <&mmc1_idle>; | |
| 103 | + pinctrl-2 = <&mmc1_sleep>; | |
| 104 | + ... | |
| 105 | + interrupts-extended = <&intc 64 &gpio2 28 0>; | |
| 106 | + }; | |
| 107 | + | |
| 108 | + mmc1_idle : pinmux_cirq_pin { | |
| 109 | + pinctrl-single,pins = < | |
| 110 | + 0x0f8 0x3f /* GPIO2_28 */ | |
| 111 | + >; | |
| 112 | + }; | |
| @@ -18,6 +18,7 @@ Required properties: · 17 unmodified lines | ||
| 18 | 18 | "renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC |
| 19 | 19 | "renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC |
| 20 | 20 | "renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC |
| 21 | + "renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC | |
| 21 | 22 | |
| 22 | 23 | Optional properties: |
| 23 | 24 | - toshiba,mmc-wrprotect-disable: write-protect detection is unavailable |
| @@ -25,6 +25,16 @@ Optional properties: · 24 unmodified lines | ||
| 25 | 25 | discoverable or this property is not enabled, |
| 26 | 26 | the software may chooses an implementation-defined |
| 27 | 27 | ECC scheme. |
| 28 | + - fsl,no-blockmark-swap: Don't swap the bad block marker from the OOB | |
| 29 | + area with the byte in the data area but rely on the | |
| 30 | + flash based BBT for identifying bad blocks. | |
| 31 | + NOTE: this is only valid in conjunction with | |
| 32 | + 'nand-on-flash-bbt'. | |
| 33 | + WARNING: on i.MX28 blockmark swapping cannot be | |
| 34 | + disabled for the BootROM in the FCB. Thus, | |
| 35 | + partitions written from Linux with this feature | |
| 36 | + turned on may not be accessible by the BootROM | |
| 37 | + code. | |
| 28 | 38 | |
| 29 | 39 | The device tree may optionally contain sub-nodes describing partitions of the |
| 30 | 40 | address space. See partition.txt for more detail. |
| @@ -0,0 +1,66 @@ | ||
| 1 | +APM X-Gene SoC Ethernet nodes | |
| 2 | + | |
| 3 | +Ethernet nodes are defined to describe on-chip ethernet interfaces in | |
| 4 | +APM X-Gene SoC. | |
| 5 | + | |
| 6 | +Required properties: | |
| 7 | +- compatible: Should be "apm,xgene-enet" | |
| 8 | +- reg: Address and length of the register set for the device. It contains the | |
| 9 | + information of registers in the same order as described by reg-names | |
| 10 | +- reg-names: Should contain the register set names | |
| 11 | + - "enet_csr": Ethernet control and status register address space | |
| 12 | + - "ring_csr": Descriptor ring control and status register address space | |
| 13 | + - "ring_cmd": Descriptor ring command register address space | |
| 14 | +- interrupts: Ethernet main interrupt | |
| 15 | +- clocks: Reference to the clock entry. | |
| 16 | +- local-mac-address: MAC address assigned to this device | |
| 17 | +- phy-connection-type: Interface type between ethernet device and PHY device | |
| 18 | +- phy-handle: Reference to a PHY node connected to this device | |
| 19 | + | |
| 20 | +- mdio: Device tree subnode with the following required properties: | |
| 21 | + - compatible: Must be "apm,xgene-mdio". | |
| 22 | + - #address-cells: Must be <1>. | |
| 23 | + - #size-cells: Must be <0>. | |
| 24 | + | |
| 25 | + For the phy on the mdio bus, there must be a node with the following fields: | |
| 26 | + - compatible: PHY identifier. Please refer ./phy.txt for the format. | |
| 27 | + - reg: The ID number for the phy. | |
| 28 | + | |
| 29 | +Optional properties: | |
| 30 | +- status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok". | |
| 31 | + | |
| 32 | +Example: | |
| 33 | + menetclk: menetclk { | |
| 34 | + compatible = "apm,xgene-device-clock"; | |
| 35 | + clock-output-names = "menetclk"; | |
| 36 | + status = "ok"; | |
| 37 | + }; | |
| 38 | + | |
| 39 | + menet: ethernet@17020000 { | |
| 40 | + compatible = "apm,xgene-enet"; | |
| 41 | + status = "disabled"; | |
| 42 | + reg = <0x0 0x17020000 0x0 0xd100>, | |
| 43 | + <0x0 0X17030000 0x0 0X400>, | |
| 44 | + <0x0 0X10000000 0x0 0X200>; | |
| 45 | + reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
| 46 | + interrupts = <0x0 0x3c 0x4>; | |
| 47 | + clocks = <&menetclk 0>; | |
| 48 | + local-mac-address = [00 01 73 00 00 01]; | |
| 49 | + phy-connection-type = "rgmii"; | |
| 50 | + phy-handle = <&menetphy>; | |
| 51 | + mdio { | |
| 52 | + compatible = "apm,xgene-mdio"; | |
| 53 | + #address-cells = <1>; | |
| 54 | + #size-cells = <0>; | |
| 55 | + menetphy: menetphy@3 { | |
| 56 | + compatible = "ethernet-phy-id001c.c915"; | |
| 57 | + reg = <0x3>; | |
| 58 | + }; | |
| 59 | + | |
| 60 | + }; | |
| 61 | + }; | |
| 62 | + | |
| 63 | +/* Board-specific peripheral configurations */ | |
| 64 | +&menet { | |
| 65 | + status = "ok"; | |
| 66 | +}; | |
| @@ -12,7 +12,14 @@ Optional properties: · 11 unmodified lines | ||
| 12 | 12 | only if property "phy-reset-gpios" is available. Missing the property |
| 13 | 13 | will have the duration be 1 millisecond. Numbers greater than 1000 are |
| 14 | 14 | invalid and 1 millisecond will be used instead. |
| 15 | −- phy-supply: regulator that powers the Ethernet PHY. | |
| 15 | +- phy-supply : regulator that powers the Ethernet PHY. | |
| 16 | +- phy-handle : phandle to the PHY device connected to this device. | |
| 17 | +- fixed-link : Assume a fixed link. See fixed-link.txt in the same directory. | |
| 18 | + Use instead of phy-handle. | |
| 19 | + | |
| 20 | +Optional subnodes: | |
| 21 | +- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes | |
| 22 | + according to phy.txt in the same directory | |
| 16 | 23 | |
| 17 | 24 | Example: |
| 18 | 25 | |
| @@ -25,3 +32,23 @@ ethernet@83fec000 { · 6 unmodified lines | ||
| 25 | 32 | local-mac-address = [00 04 9F 01 1B B9]; |
| 26 | 33 | phy-supply = <®_fec_supply>; |
| 27 | 34 | }; |
| 35 | + | |
| 36 | +Example with phy specified: | |
| 37 | + | |
| 38 | +ethernet@83fec000 { | |
| 39 | + compatible = "fsl,imx51-fec", "fsl,imx27-fec"; | |
| 40 | + reg = <0x83fec000 0x4000>; | |
| 41 | + interrupts = <87>; | |
| 42 | + phy-mode = "mii"; | |
| 43 | + phy-reset-gpios = <&gpio2 14 0>; /* GPIO2_14 */ | |
| 44 | + local-mac-address = [00 04 9F 01 1B B9]; | |
| 45 | + phy-supply = <®_fec_supply>; | |
| 46 | + phy-handle = <ðphy>; | |
| 47 | + mdio { | |
| 48 | + ethphy: ethernet-phy@6 { | |
| 49 | + compatible = "ethernet-phy-ieee802.3-c22"; | |
| 50 | + reg = <6>; | |
| 51 | + max-speed = <100>; | |
| 52 | + }; | |
| 53 | + }; | |
| 54 | +}; | |
| @@ -0,0 +1,7 @@ | ||
| 1 | +AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: should be "auo,b133htn01" | |
| 5 | + | |
| 6 | +This binding is compatible with the simple-panel binding, which is specified | |
| 7 | +in simple-panel.txt in this directory. | |
| @@ -0,0 +1,7 @@ | ||
| 1 | +Foxlink Group 5" WVGA TFT LCD panel | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: should be "foxlink,fl500wvr00-a0t" | |
| 5 | + | |
| 6 | +This binding is compatible with the simple-panel binding, which is specified | |
| 7 | +in simple-panel.txt in this directory. | |
| @@ -0,0 +1,7 @@ | ||
| 1 | +Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: should be "innolux,n116bge" | |
| 5 | + | |
| 6 | +This binding is compatible with the simple-panel binding, which is specified | |
| 7 | +in simple-panel.txt in this directory. | |
| @@ -0,0 +1,7 @@ | ||
| 1 | +InnoLux 15.6" WXGA TFT LCD panel | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: should be "innolux,n156bge-l21" | |
| 5 | + | |
| 6 | +This binding is compatible with the simple-panel binding, which is specified | |
| 7 | +in simple-panel.txt in this directory. | |
| @@ -2,6 +2,10 @@ · 1 unmodified line | ||
| 2 | 2 | |
| 3 | 3 | Required properties: |
| 4 | 4 | - compatible: should contain "snps,dw-pcie" to identify the core. |
| 5 | +- reg: Should contain the configuration address space. | |
| 6 | +- reg-names: Must be "config" for the PCIe configuration space. | |
| 7 | + (The old way of getting the configuration address space from "ranges" | |
| 8 | + is deprecated and should be avoided.) | |
| 5 | 9 | - #address-cells: set to <3> |
| 6 | 10 | - #size-cells: set to <2> |
| 7 | 11 | - device_type: set to "pci" |
| @@ -14,9 +14,6 @@ Required properties: · 13 unmodified lines | ||
| 14 | 14 | - interrupt-names: Must include the following entries: |
| 15 | 15 | "intr": The Tegra interrupt that is asserted for controller interrupts |
| 16 | 16 | "msi": The Tegra interrupt that is asserted when an MSI is received |
| 17 | −- pex-clk-supply: Supply voltage for internal reference clock | |
| 18 | −- vdd-supply: Power supply for controller (1.05V) | |
| 19 | −- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20) | |
| 20 | 17 | - bus-range: Range of bus numbers associated with this controller |
| 21 | 18 | - #address-cells: Address representation for root ports (must be 3) |
| 22 | 19 | - cell 0 specifies the bus and device numbers of the root port: |
| @@ -60,6 +57,33 @@ Required properties: · 37 unmodified lines | ||
| 60 | 57 | - afi |
| 61 | 58 | - pcie_x |
| 62 | 59 | |
| 60 | +Power supplies for Tegra20: | |
| 61 | +- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. | |
| 62 | +- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. | |
| 63 | +- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must | |
| 64 | + supply 1.05 V. | |
| 65 | +- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must | |
| 66 | + supply 1.05 V. | |
| 67 | +- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V. | |
| 68 | + | |
| 69 | +Power supplies for Tegra30: | |
| 70 | +- Required: | |
| 71 | + - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must | |
| 72 | + supply 1.05 V. | |
| 73 | + - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must | |
| 74 | + supply 1.05 V. | |
| 75 | + - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must | |
| 76 | + supply 1.8 V. | |
| 77 | + - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks. | |
| 78 | + Must supply 3.3 V. | |
| 79 | +- Optional: | |
| 80 | + - If lanes 0 to 3 are used: | |
| 81 | + - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V. | |
| 82 | + - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. | |
| 83 | + - If lanes 4 or 5 are used: | |
| 84 | + - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V. | |
| 85 | + - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. | |
| 86 | + | |
| 63 | 87 | Root ports are defined as subnodes of the PCIe controller node. |
| 64 | 88 | |
| 65 | 89 | Required properties: |
| @@ -0,0 +1,14 @@ | ||
| 1 | +SPEAr13XX PCIe DT detail: | |
| 2 | +================================ | |
| 3 | + | |
| 4 | +SPEAr13XX uses synopsis designware PCIe controller and ST MiPHY as phy | |
| 5 | +controller. | |
| 6 | + | |
| 7 | +Required properties: | |
| 8 | +- compatible : should be "st,spear1340-pcie", "snps,dw-pcie". | |
| 9 | +- phys : phandle to phy node associated with pcie controller | |
| 10 | +- phy-names : must be "pcie-phy" | |
| 11 | +- All other definitions as per generic PCI bindings | |
| 12 | + | |
| 13 | + Optional properties: | |
| 14 | +- st,pcie-is-gen1 indicates that forced gen1 initialization is needed. | |
| @@ -0,0 +1,59 @@ | ||
| 1 | +TI PCI Controllers | |
| 2 | + | |
| 3 | +PCIe Designware Controller | |
| 4 | + - compatible: Should be "ti,dra7-pcie"" | |
| 5 | + - reg : Two register ranges as listed in the reg-names property | |
| 6 | + - reg-names : The first entry must be "ti-conf" for the TI specific registers | |
| 7 | + The second entry must be "rc-dbics" for the designware pcie | |
| 8 | + registers | |
| 9 | + The third entry must be "config" for the PCIe configuration space | |
| 10 | + - phys : list of PHY specifiers (used by generic PHY framework) | |
| 11 | + - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the | |
| 12 | + number of PHYs as specified in *phys* property. | |
| 13 | + - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", | |
| 14 | + where <X> is the instance number of the pcie from the HW spec. | |
| 15 | + - interrupts : Two interrupt entries must be specified. The first one is for | |
| 16 | + main interrupt line and the second for MSI interrupt line. | |
| 17 | + - #address-cells, | |
| 18 | + #size-cells, | |
| 19 | + #interrupt-cells, | |
| 20 | + device_type, | |
| 21 | + ranges, | |
| 22 | + num-lanes, | |
| 23 | + interrupt-map-mask, | |
| 24 | + interrupt-map : as specified in ../designware-pcie.txt | |
| 25 | + | |
| 26 | +Example: | |
| 27 | +axi { | |
| 28 | + compatible = "simple-bus"; | |
| 29 | + #size-cells = <1>; | |
| 30 | + #address-cells = <1>; | |
| 31 | + ranges = <0x51000000 0x51000000 0x3000 | |
| 32 | + 0x0 0x20000000 0x10000000>; | |
| 33 | + pcie@51000000 { | |
| 34 | + compatible = "ti,dra7-pcie"; | |
| 35 | + reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; | |
| 36 | + reg-names = "rc_dbics", "ti_conf", "config"; | |
| 37 | + interrupts = <0 232 0x4>, <0 233 0x4>; | |
| 38 | + #address-cells = <3>; | |
| 39 | + #size-cells = <2>; | |
| 40 | + device_type = "pci"; | |
| 41 | + ranges = <0x81000000 0 0 0x03000 0 0x00010000 | |
| 42 | + 0x82000000 0 0x20013000 0x13000 0 0xffed000>; | |
| 43 | + #interrupt-cells = <1>; | |
| 44 | + num-lanes = <1>; | |
| 45 | + ti,hwmods = "pcie1"; | |
| 46 | + phys = <&pcie1_phy>; | |
| 47 | + phy-names = "pcie-phy0"; | |
| 48 | + interrupt-map-mask = <0 0 0 7>; | |
| 49 | + interrupt-map = <0 0 0 1 &pcie_intc 1>, | |
| 50 | + <0 0 0 2 &pcie_intc 2>, | |
| 51 | + <0 0 0 3 &pcie_intc 3>, | |
| 52 | + <0 0 0 4 &pcie_intc 4>; | |
| 53 | + pcie_intc: interrupt-controller { | |
| 54 | + interrupt-controller; | |
| 55 | + #address-cells = <0>; | |
| 56 | + #interrupt-cells = <1>; | |
| 57 | + }; | |
| 58 | + }; | |
| 59 | +}; | |
| @@ -30,6 +30,7 @@ Required properties: · 29 unmodified lines | ||
| 30 | 30 | - "samsung,exynos4210-usb2-phy" |
| 31 | 31 | - "samsung,exynos4x12-usb2-phy" |
| 32 | 32 | - "samsung,exynos5250-usb2-phy" |
| 33 | + - "samsung,s5pv210-usb2-phy" | |
| 33 | 34 | - reg : a list of registers used by phy driver |
| 34 | 35 | - first and obligatory is the location of phy modules registers |
| 35 | 36 | - samsung,sysreg-phandle - handle to syscon used to control the system registers |
| @@ -0,0 +1,15 @@ | ||
| 1 | +ST SPEAr miphy DT details | |
| 2 | +========================= | |
| 3 | + | |
| 4 | +ST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA. | |
| 5 | + | |
| 6 | +Required properties: | |
| 7 | +- compatible : should be "st,spear1310-miphy" or "st,spear1340-miphy" | |
| 8 | +- reg : offset and length of the PHY register set. | |
| 9 | +- misc: phandle for the syscon node to access misc registers | |
| 10 | +- #phy-cells : from the generic PHY bindings, must be 1. | |
| 11 | + - cell[1]: 0 if phy used for SATA, 1 for PCIe. | |
| 12 | + | |
| 13 | +Optional properties: | |
| 14 | +- phy-id: Instance id of the phy. Only required when there are multiple phys | |
| 15 | + present on a implementation. | |
| @@ -13,6 +13,8 @@ Required properties: · 12 unmodified lines | ||
| 13 | 13 | "allwinner,sun6i-a31-pinctrl" |
| 14 | 14 | "allwinner,sun6i-a31-r-pinctrl" |
| 15 | 15 | "allwinner,sun7i-a20-pinctrl" |
| 16 | + "allwinner,sun8i-a23-pinctrl" | |
| 17 | + "allwinner,sun8i-a23-r-pinctrl" | |
| 16 | 18 | - reg: Should contain the register physical address and length for the |
| 17 | 19 | pin controller. |
| 18 | 20 | |
| @@ -0,0 +1,127 @@ | ||
| 1 | +Device tree binding for NVIDIA Tegra XUSB pad controller | |
| 2 | +======================================================== | |
| 3 | + | |
| 4 | +The Tegra XUSB pad controller manages a set of lanes, each of which can be | |
| 5 | +assigned to one out of a set of different pads. Some of these pads have an | |
| 6 | +associated PHY that must be powered up before the pad can be used. | |
| 7 | + | |
| 8 | +This document defines the device-specific binding for the XUSB pad controller. | |
| 9 | + | |
| 10 | +Refer to pinctrl-bindings.txt in this directory for generic information about | |
| 11 | +pin controller device tree bindings and ../phy/phy-bindings.txt for details on | |
| 12 | +how to describe and reference PHYs in device trees. | |
| 13 | + | |
| 14 | +Required properties: | |
| 15 | +-------------------- | |
| 16 | +- compatible: should be "nvidia,tegra124-xusb-padctl" | |
| 17 | +- reg: Physical base address and length of the controller's registers. | |
| 18 | +- resets: Must contain an entry for each entry in reset-names. | |
| 19 | + See ../reset/reset.txt for details. | |
| 20 | +- reset-names: Must include the following entries: | |
| 21 | + - padctl | |
| 22 | +- #phy-cells: Should be 1. The specifier is the index of the PHY to reference. | |
| 23 | + See <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> for the list of valid values. | |
| 24 | + | |
| 25 | +Lane muxing: | |
| 26 | +------------ | |
| 27 | + | |
| 28 | +Child nodes contain the pinmux configurations following the conventions from | |
| 29 | +the pinctrl-bindings.txt document. Typically a single, static configuration is | |
| 30 | +given and applied at boot time. | |
| 31 | + | |
| 32 | +Each subnode describes groups of lanes along with parameters and pads that | |
| 33 | +they should be assigned to. The name of these subnodes is not important. All | |
| 34 | +subnodes should be parsed solely based on their content. | |
| 35 | + | |
| 36 | +Each subnode only applies the parameters that are explicitly listed. In other | |
| 37 | +words, if a subnode that lists a function but no pin configuration parameters | |
| 38 | +implies no information about any pin configuration parameters. Similarly, a | |
| 39 | +subnode that describes only an IDDQ parameter implies no information about | |
| 40 | +what function the pins are assigned to. For this reason even seemingly boolean | |
| 41 | +values are actually tristates in this binding: unspecified, off or on. | |
| 42 | +Unspecified is represented as an absent property, and off/on are represented | |
| 43 | +as integer values 0 and 1. | |
| 44 | + | |
| 45 | +Required properties: | |
| 46 | +- nvidia,lanes: An array of strings. Each string is the name of a lane. | |
| 47 | + | |
| 48 | +Optional properties: | |
| 49 | +- nvidia,function: A string that is the name of the function (pad) that the | |
| 50 | + pin or group should be assigned to. Valid values for function names are | |
| 51 | + listed below. | |
| 52 | +- nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes) | |
| 53 | + | |
| 54 | +Note that not all of these properties are valid for all lanes. Lanes can be | |
| 55 | +divided into three groups: | |
| 56 | + | |
| 57 | + - otg-0, otg-1, otg-2: | |
| 58 | + | |
| 59 | + Valid functions for this group are: "snps", "xusb", "uart", "rsvd". | |
| 60 | + | |
| 61 | + The nvidia,iddq property does not apply to this group. | |
| 62 | + | |
| 63 | + - ulpi-0, hsic-0, hsic-1: | |
| 64 | + | |
| 65 | + Valid functions for this group are: "snps", "xusb". | |
| 66 | + | |
| 67 | + The nvidia,iddq property does not apply to this group. | |
| 68 | + | |
| 69 | + - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0: | |
| 70 | + | |
| 71 | + Valid functions for this group are: "pcie", "usb3", "sata", "rsvd". | |
| 72 | + | |
| 73 | + | |
| 74 | +Example: | |
| 75 | +======== | |
| 76 | + | |
| 77 | +SoC file extract: | |
| 78 | +----------------- | |
| 79 | + | |
| 80 | + padctl@0,7009f000 { | |
| 81 | + compatible = "nvidia,tegra124-xusb-padctl"; | |
| 82 | + reg = <0x0 0x7009f000 0x0 0x1000>; | |
| 83 | + resets = <&tegra_car 142>; | |
| 84 | + reset-names = "padctl"; | |
| 85 | + | |
| 86 | + #phy-cells = <1>; | |
| 87 | + }; | |
| 88 | + | |
| 89 | +Board file extract: | |
| 90 | +------------------- | |
| 91 | + | |
| 92 | + pcie-controller@0,01003000 { | |
| 93 | + ... | |
| 94 | + | |
| 95 | + phys = <&padctl 0>; | |
| 96 | + phy-names = "pcie"; | |
| 97 | + | |
| 98 | + ... | |
| 99 | + }; | |
| 100 | + | |
| 101 | + ... | |
| 102 | + | |
| 103 | + padctl: padctl@0,7009f000 { | |
| 104 | + pinctrl-0 = <&padctl_default>; | |
| 105 | + pinctrl-names = "default"; | |
| 106 | + | |
| 107 | + padctl_default: pinmux { | |
| 108 | + usb3 { | |
| 109 | + nvidia,lanes = "pcie-0", "pcie-1"; | |
| 110 | + nvidia,function = "usb3"; | |
| 111 | + nvidia,iddq = <0>; | |
| 112 | + }; | |
| 113 | + | |
| 114 | + pcie { | |
| 115 | + nvidia,lanes = "pcie-2", "pcie-3", | |
| 116 | + "pcie-4"; | |
| 117 | + nvidia,function = "pcie"; | |
| 118 | + nvidia,iddq = <0>; | |
| 119 | + }; | |
| 120 | + | |
| 121 | + sata { | |
| 122 | + nvidia,lanes = "sata-0"; | |
| 123 | + nvidia,function = "sata"; | |
| 124 | + nvidia,iddq = <0>; | |
| 125 | + }; | |
| 126 | + }; | |
| 127 | + }; | |
| @@ -46,7 +46,7 @@ Valid values for pins are: · 45 unmodified lines | ||
| 46 | 46 | gpio0-gpio89 |
| 47 | 47 | |
| 48 | 48 | Valid values for function are: |
| 49 | − cam_mclk, codec_mic_i2s, codec_spkr_i2s, gsbi1, gsbi2, gsbi3, gsbi4, | |
| 49 | + cam_mclk, codec_mic_i2s, codec_spkr_i2s, gpio, gsbi1, gsbi2, gsbi3, gsbi4, | |
| 50 | 50 | gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, |
| 51 | 51 | gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1, |
| 52 | 52 | gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, |
| @@ -51,7 +51,7 @@ Valid values for qcom,pins are: · 50 unmodified lines | ||
| 51 | 51 | |
| 52 | 52 | |
| 53 | 53 | Valid values for function are: |
| 54 | − mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gsbi1, gsbi2, gsbi4, gsbi5, | |
| 54 | + mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5, | |
| 55 | 55 | gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1, |
| 56 | 56 | spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata, |
| 57 | 57 | pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt, |
| @@ -0,0 +1,181 @@ | ||
| 1 | +Qualcomm MSM8960 TLMM block | |
| 2 | + | |
| 3 | +This binding describes the Top Level Mode Multiplexer block found in the | |
| 4 | +MSM8960 platform. | |
| 5 | + | |
| 6 | +- compatible: | |
| 7 | + Usage: required | |
| 8 | + Value type: <string> | |
| 9 | + Definition: must be "qcom,msm8960-pinctrl" | |
| 10 | + | |
| 11 | +- reg: | |
| 12 | + Usage: required | |
| 13 | + Value type: <prop-encoded-array> | |
| 14 | + Definition: the base address and size of the TLMM register space. | |
| 15 | + | |
| 16 | +- interrupts: | |
| 17 | + Usage: required | |
| 18 | + Value type: <prop-encoded-array> | |
| 19 | + Definition: should specify the TLMM summary IRQ. | |
| 20 | + | |
| 21 | +- interrupt-controller: | |
| 22 | + Usage: required | |
| 23 | + Value type: <none> | |
| 24 | + Definition: identifies this node as an interrupt controller | |
| 25 | + | |
| 26 | +- #interrupt-cells: | |
| 27 | + Usage: required | |
| 28 | + Value type: <u32> | |
| 29 | + Definition: must be 2. Specifying the pin number and flags, as defined | |
| 30 | + in <dt-bindings/interrupt-controller/irq.h> | |
| 31 | + | |
| 32 | +- gpio-controller: | |
| 33 | + Usage: required | |
| 34 | + Value type: <none> | |
| 35 | + Definition: identifies this node as a gpio controller | |
| 36 | + | |
| 37 | +- #gpio-cells: | |
| 38 | + Usage: required | |
| 39 | + Value type: <u32> | |
| 40 | + Definition: must be 2. Specifying the pin number and flags, as defined | |
| 41 | + in <dt-bindings/gpio/gpio.h> | |
| 42 | + | |
| 43 | +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for | |
| 44 | +a general description of GPIO and interrupt bindings. | |
| 45 | + | |
| 46 | +Please refer to pinctrl-bindings.txt in this directory for details of the | |
| 47 | +common pinctrl bindings used by client devices, including the meaning of the | |
| 48 | +phrase "pin configuration node". | |
| 49 | + | |
| 50 | +The pin configuration nodes act as a container for an abitrary number of | |
| 51 | +subnodes. Each of these subnodes represents some desired configuration for a | |
| 52 | +pin, a group, or a list of pins or groups. This configuration can include the | |
| 53 | +mux function to select on those pin(s)/group(s), and various pin configuration | |
| 54 | +parameters, such as pull-up, drive strength, etc. | |
| 55 | + | |
| 56 | + | |
| 57 | +PIN CONFIGURATION NODES: | |
| 58 | + | |
| 59 | +The name of each subnode is not important; all subnodes should be enumerated | |
| 60 | +and processed purely based on their content. | |
| 61 | + | |
| 62 | +Each subnode only affects those parameters that are explicitly listed. In | |
| 63 | +other words, a subnode that lists a mux function but no pin configuration | |
| 64 | +parameters implies no information about any pin configuration parameters. | |
| 65 | +Similarly, a pin subnode that describes a pullup parameter implies no | |
| 66 | +information about e.g. the mux function. | |
| 67 | + | |
| 68 | + | |
| 69 | +The following generic properties as defined in pinctrl-bindings.txt are valid | |
| 70 | +to specify in a pin configuration subnode: | |
| 71 | + | |
| 72 | +- pins: | |
| 73 | + Usage: required | |
| 74 | + Value type: <string-array> | |
| 75 | + Definition: List of gpio pins affected by the properties specified in | |
| 76 | + this subnode. Valid pins are: | |
| 77 | + gpio0-gpio151, | |
| 78 | + sdc1_clk, | |
| 79 | + sdc1_cmd, | |
| 80 | + sdc1_data | |
| 81 | + sdc3_clk, | |
| 82 | + sdc3_cmd, | |
| 83 | + sdc3_data | |
| 84 | + | |
| 85 | +- function: | |
| 86 | + Usage: required | |
| 87 | + Value type: <string> | |
| 88 | + Definition: Specify the alternative function to be configured for the | |
| 89 | + specified pins. Functions are only valid for gpio pins. | |
| 90 | + Valid values are: | |
| 91 | + audio_pcm, bt, cam_mclk0, cam_mclk1, cam_mclk2, | |
| 92 | + codec_mic_i2s, codec_spkr_i2s, ext_gps, fm, gps_blanking, | |
| 93 | + gps_pps_in, gps_pps_out, gp_clk_0a, gp_clk_0b, gp_clk_1a, | |
| 94 | + gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gp_pdm_0a, | |
| 95 | + gp_pdm_0b, gp_pdm_1a, gp_pdm_1b, gp_pdm_2a, gp_pdm_2b, gpio, | |
| 96 | + gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n, | |
| 97 | + gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, | |
| 98 | + gsbi2_spi_cs3_n, gsbi3, gsbi4, gsbi4_3d_cam_i2c_l, | |
| 99 | + gsbi4_3d_cam_i2c_r, gsbi5, gsbi5_3d_cam_i2c_l, | |
| 100 | + gsbi5_3d_cam_i2c_r, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, | |
| 101 | + gsbi11, gsbi11_spi_cs1a_n, gsbi11_spi_cs1b_n, | |
| 102 | + gsbi11_spi_cs2a_n, gsbi11_spi_cs2b_n, gsbi11_spi_cs3_n, | |
| 103 | + gsbi12, hdmi_cec, hdmi_ddc_clock, hdmi_ddc_data, | |
| 104 | + hdmi_hot_plug_detect, hsic, mdp_vsync, mi2s, mic_i2s, | |
| 105 | + pmb_clk, pmb_ext_ctrl, ps_hold, rpm_wdog, sdc2, sdc4, sdc5, | |
| 106 | + slimbus1, slimbus2, spkr_i2s, ssbi1, ssbi2, ssbi_ext_gps, | |
| 107 | + ssbi_pmic2, ssbi_qpa1, ssbi_ts, tsif1, tsif2, ts_eoc, | |
| 108 | + usb_fs1, usb_fs1_oe, usb_fs1_oe_n, usb_fs2, usb_fs2_oe, | |
| 109 | + usb_fs2_oe_n, vfe_camif_timer1_a, vfe_camif_timer1_b, | |
| 110 | + vfe_camif_timer2, vfe_camif_timer3_a, vfe_camif_timer3_b, | |
| 111 | + vfe_camif_timer4_a, vfe_camif_timer4_b, vfe_camif_timer4_c, | |
| 112 | + vfe_camif_timer5_a, vfe_camif_timer5_b, vfe_camif_timer6_a, | |
| 113 | + vfe_camif_timer6_b, vfe_camif_timer6_c, vfe_camif_timer7_a, | |
| 114 | + vfe_camif_timer7_b, vfe_camif_timer7_c, wlan | |
| 115 | + | |
| 116 | +- bias-disable: | |
| 117 | + Usage: optional | |
| 118 | + Value type: <none> | |
| 119 | + Definition: The specified pins should be configued as no pull. | |
| 120 | + | |
| 121 | +- bias-pull-down: | |
| 122 | + Usage: optional | |
| 123 | + Value type: <none> | |
| 124 | + Definition: The specified pins should be configued as pull down. | |
| 125 | + | |
| 126 | +- bias-pull-up: | |
| 127 | + Usage: optional | |
| 128 | + Value type: <none> | |
| 129 | + Definition: The specified pins should be configued as pull up. | |
| 130 | + | |
| 131 | +- output-high: | |
| 132 | + Usage: optional | |
| 133 | + Value type: <none> | |
| 134 | + Definition: The specified pins are configured in output mode, driven | |
| 135 | + high. | |
| 136 | + Not valid for sdc pins. | |
| 137 | + | |
| 138 | +- output-low: | |
| 139 | + Usage: optional | |
| 140 | + Value type: <none> | |
| 141 | + Definition: The specified pins are configured in output mode, driven | |
| 142 | + low. | |
| 143 | + Not valid for sdc pins. | |
| 144 | + | |
| 145 | +- drive-strength: | |
| 146 | + Usage: optional | |
| 147 | + Value type: <u32> | |
| 148 | + Definition: Selects the drive strength for the specified pins, in mA. | |
| 149 | + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 | |
| 150 | + | |
| 151 | +Example: | |
| 152 | + | |
| 153 | + msmgpio: pinctrl@800000 { | |
| 154 | + compatible = "qcom,msm8960-pinctrl"; | |
| 155 | + reg = <0x800000 0x4000>; | |
| 156 | + | |
| 157 | + gpio-controller; | |
| 158 | + #gpio-cells = <2>; | |
| 159 | + interrupt-controller; | |
| 160 | + #interrupt-cells = <2>; | |
| 161 | + interrupts = <0 16 0x4>; | |
| 162 | + | |
| 163 | + gsbi8_uart: gsbi8-uart { | |
| 164 | + mux { | |
| 165 | + pins = "gpio34", "gpio35"; | |
| 166 | + function = "gsbi8"; | |
| 167 | + }; | |
| 168 | + | |
| 169 | + tx { | |
| 170 | + pins = "gpio34"; | |
| 171 | + drive-strength = <4>; | |
| 172 | + bias-disable; | |
| 173 | + }; | |
| 174 | + | |
| 175 | + rx { | |
| 176 | + pins = "gpio35"; | |
| 177 | + drive-strength = <2>; | |
| 178 | + bias-pull-up; | |
| 179 | + }; | |
| 180 | + }; | |
| 181 | + }; | |
| @@ -70,7 +70,7 @@ Valid values for function are: · 69 unmodified lines | ||
| 70 | 70 | cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc, |
| 71 | 71 | hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk, |
| 72 | 72 | gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, spkr_mi2s, |
| 73 | − ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus | |
| 73 | + ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, gpio | |
| 74 | 74 | |
| 75 | 75 | (Note that this is not yet the complete list of functions) |
| 76 | 76 | |
| @@ -15,6 +15,7 @@ Required Properties: · 14 unmodified lines | ||
| 15 | 15 | - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller. |
| 16 | 16 | - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. |
| 17 | 17 | - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. |
| 18 | + - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller. | |
| 18 | 19 | - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller. |
| 19 | 20 | - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. |
| 20 | 21 | |
| @@ -21,6 +21,7 @@ defined as gpio sub-nodes of the pinmux controller. · 20 unmodified lines | ||
| 21 | 21 | Required properties for iomux controller: |
| 22 | 22 | - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" |
| 23 | 23 | "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" |
| 24 | + "rockchip,rk3288-pinctrl" | |
| 24 | 25 | - rockchip,grf: phandle referencing a syscon providing the |
| 25 | 26 | "general register files" |
| 26 | 27 | |
| @@ -36,7 +37,7 @@ Deprecated properties for iomux controller: · 9 unmodified lines | ||
| 36 | 37 | Use rockchip,grf and rockchip,pmu described above instead. |
| 37 | 38 | |
| 38 | 39 | Required properties for gpio sub nodes: |
| 39 | − - compatible: "rockchip,gpio-bank", "rockchip,rk3188-gpio-bank0" | |
| 40 | + - compatible: "rockchip,gpio-bank" | |
| 40 | 41 | - reg: register of the gpio bank (different than the iomux registerset) |
| 41 | 42 | - interrupts: base interrupt of the gpio bank in the interrupt controller |
| 42 | 43 | - clocks: clock that drives this bank |
| @@ -50,6 +51,7 @@ Required properties for gpio sub nodes: · 7 unmodified lines | ||
| 50 | 51 | bindings/interrupt-controller/interrupts.txt |
| 51 | 52 | |
| 52 | 53 | Deprecated properties for gpio sub nodes: |
| 54 | + - compatible: "rockchip,rk3188-gpio-bank0" | |
| 53 | 55 | - reg: second element: separate pull register for rk3188 bank0, use |
| 54 | 56 | rockchip,pmu described above instead |
| 55 | 57 | |
| @@ -44,7 +44,11 @@ Required Properties: · 43 unmodified lines | ||
| 44 | 44 | - Pin mux/config groups as child nodes: The pin mux (selecting pin function |
| 45 | 45 | mode) and pin config (pull up/down, driver strength) settings are represented |
| 46 | 46 | as child nodes of the pin-controller node. There should be atleast one |
| 47 | − child node and there is no limit on the count of these child nodes. | |
| 47 | + child node and there is no limit on the count of these child nodes. It is | |
| 48 | + also possible for a child node to consist of several further child nodes | |
| 49 | + to allow grouping multiple pinctrl groups into one. The format of second | |
| 50 | + level child nodes is exactly the same as for first level ones and is | |
| 51 | + described below. | |
| 48 | 52 | |
| 49 | 53 | The child node should contain a list of pin(s) on which a particular pin |
| 50 | 54 | function selection or pin configuration (or both) have to applied. This |
| @@ -71,6 +75,7 @@ Required Properties: · 20 unmodified lines | ||
| 71 | 75 | "samsung,pins" property of the child node. The following pin configuration |
| 72 | 76 | properties are supported. |
| 73 | 77 | |
| 78 | + - samsung,pin-val: Initial value of pin output buffer. | |
| 74 | 79 | - samsung,pin-pud: Pull up/down configuration. |
| 75 | 80 | - samsung,pin-drv: Drive strength configuration. |
| 76 | 81 | - samsung,pin-pud-pdn: Pull up/down configuration in power down mode. |
| @@ -249,6 +254,23 @@ Example 1: A pin-controller node with pin groups. · 172 unmodified lines | ||
| 249 | 254 | samsung,pin-pud = <3>; |
| 250 | 255 | samsung,pin-drv = <0>; |
| 251 | 256 | }; |
| 257 | + | |
| 258 | + sd4_bus8: sd4-bus-width8 { | |
| 259 | + part-1 { | |
| 260 | + samsung,pins = "gpk0-3", "gpk0-4", | |
| 261 | + "gpk0-5", "gpk0-6"; | |
| 262 | + samsung,pin-function = <3>; | |
| 263 | + samsung,pin-pud = <3>; | |
| 264 | + samsung,pin-drv = <3>; | |
| 265 | + }; | |
| 266 | + part-2 { | |
| 267 | + samsung,pins = "gpk1-3", "gpk1-4", | |
| 268 | + "gpk1-5", "gpk1-6"; | |
| 269 | + samsung,pin-function = <4>; | |
| 270 | + samsung,pin-pud = <4>; | |
| 271 | + samsung,pin-drv = <3>; | |
| 272 | + }; | |
| 273 | + }; | |
| 252 | 274 | }; |
| 253 | 275 | |
| 254 | 276 | Example 2: A pin-controller node with external wakeup interrupt controller node. |
| @@ -84,3 +84,19 @@ Example: · 83 unmodified lines | ||
| 84 | 84 | compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c"; |
| 85 | 85 | reg = <0x66>; |
| 86 | 86 | }; |
| 87 | + | |
| 88 | +* Freescale on-board CPLD | |
| 89 | + | |
| 90 | +Some Freescale boards like T1040RDB have an on board CPLD connected. | |
| 91 | + | |
| 92 | +Required properties: | |
| 93 | +- compatible: Should be a board-specific string like "fsl,<board>-cpld" | |
| 94 | + Example: | |
| 95 | + "fsl,t1040rdb-cpld", "fsl,t1042rdb-cpld", "fsl,t1042rdb_pi-cpld" | |
| 96 | +- reg: should describe CPLD registers | |
| 97 | + | |
| 98 | +Example: | |
| 99 | + cpld@3,0 { | |
| 100 | + compatible = "fsl,t1040rdb-cpld"; | |
| 101 | + reg = <3 0 0x300>; | |
| 102 | + }; | |
| @@ -0,0 +1,20 @@ | ||
| 1 | +Rockchip PWM controller | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | + - compatible: should be "rockchip,<name>-pwm" | |
| 5 | + "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs | |
| 6 | + "rockchip,rk3288-pwm": found on RK3288 SoC | |
| 7 | + "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC | |
| 8 | + - reg: physical base address and length of the controller's registers | |
| 9 | + - clocks: phandle and clock specifier of the PWM reference clock | |
| 10 | + - #pwm-cells: should be 2. See pwm.txt in this directory for a | |
| 11 | + description of the cell format. | |
| 12 | + | |
| 13 | +Example: | |
| 14 | + | |
| 15 | + pwm0: pwm@20030000 { | |
| 16 | + compatible = "rockchip,rk2928-pwm"; | |
| 17 | + reg = <0x20030000 0x10>; | |
| 18 | + clocks = <&cru PCLK_PWM01>; | |
| 19 | + #pwm-cells = <2>; | |
| 20 | + }; | |
| @@ -0,0 +1,41 @@ | ||
| 1 | +STMicroelectronics PWM driver bindings | |
| 2 | +-------------------------------------- | |
| 3 | + | |
| 4 | +Required parameters: | |
| 5 | +- compatible : "st,pwm" | |
| 6 | +- #pwm-cells : Number of cells used to specify a PWM. First cell | |
| 7 | + specifies the per-chip index of the PWM to use and the | |
| 8 | + second cell is the period in nanoseconds - fixed to 2 | |
| 9 | + for STiH41x. | |
| 10 | +- reg : Physical base address and length of the controller's | |
| 11 | + registers. | |
| 12 | +- pinctrl-names: Set to "default". | |
| 13 | +- pinctrl-0: List of phandles pointing to pin configuration nodes | |
| 14 | + for PWM module. | |
| 15 | + For Pinctrl properties, please refer to [1]. | |
| 16 | +- clock-names: Set to "pwm". | |
| 17 | +- clocks: phandle of the clock used by the PWM module. | |
| 18 | + For Clk properties, please refer to [2]. | |
| 19 | + | |
| 20 | +Optional properties: | |
| 21 | +- st,pwm-num-chan: Number of available channels. If not passed, the driver | |
| 22 | + will consider single channel by default. | |
| 23 | + | |
| 24 | +[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | |
| 25 | +[2] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| 26 | + | |
| 27 | +Example: | |
| 28 | + | |
| 29 | +pwm1: pwm@fe510000 { | |
| 30 | + compatible = "st,pwm"; | |
| 31 | + reg = <0xfe510000 0x68>; | |
| 32 | + #pwm-cells = <2>; | |
| 33 | + pinctrl-names = "default"; | |
| 34 | + pinctrl-0 = <&pinctrl_pwm1_chan0_default | |
| 35 | + &pinctrl_pwm1_chan1_default | |
| 36 | + &pinctrl_pwm1_chan2_default | |
| 37 | + &pinctrl_pwm1_chan3_default>; | |
| 38 | + clocks = <&clk_sysin>; | |
| 39 | + clock-names = "pwm"; | |
| 40 | + st,pwm-num-chan = <4>; | |
| 41 | +}; | |
| @@ -86,7 +86,7 @@ as per the datasheet of s5m8767. · 85 unmodified lines | ||
| 86 | 86 | |
| 87 | 87 | - LDOn |
| 88 | 88 | - valid values for n are 1 to 28 |
| 89 | − - Example: LDO1, LD02, LDO28 | |
| 89 | + - Example: LDO1, LDO2, LDO28 | |
| 90 | 90 | - BUCKn |
| 91 | 91 | - valid values for n are 1 to 9. |
| 92 | 92 | - Example: BUCK1, BUCK2, BUCK9 |
| @@ -0,0 +1,20 @@ | ||
| 1 | +Binding for Cadence UART Controller | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible : should be "cdns,uart-r1p8", or "xlnx,xuartps" | |
| 5 | +- reg: Should contain UART controller registers location and length. | |
| 6 | +- interrupts: Should contain UART controller interrupts. | |
| 7 | +- clocks: Must contain phandles to the UART clocks | |
| 8 | + See ../clocks/clock-bindings.txt for details. | |
| 9 | +- clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk" | |
| 10 | + See ../clocks/clock-bindings.txt for details. | |
| 11 | + | |
| 12 | + | |
| 13 | +Example: | |
| 14 | + uart@e0000000 { | |
| 15 | + compatible = "cdns,uart-r1p8"; | |
| 16 | + clocks = <&clkc 23>, <&clkc 40>; | |
| 17 | + clock-names = "uart_clk", "pclk"; | |
| 18 | + reg = <0xE0000000 0x1000>; | |
| 19 | + interrupts = <0 27 4>; | |
| 20 | + }; | |
| @@ -8,7 +8,6 @@ Required SoC Specific Properties: · 7 unmodified lines | ||
| 8 | 8 | - compatible: should be one of the following. |
| 9 | 9 | - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms |
| 10 | 10 | - samsung,s3c6410-spi: for s3c6410 platforms |
| 11 | − - samsung,s5p6440-spi: for s5p6440 and s5p6450 platforms | |
| 12 | 11 | - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms |
| 13 | 12 | - samsung,exynos4210-spi: for exynos4 and exynos5 platforms |
| 14 | 13 | |
| @@ -3,6 +3,7 @@ · 2 unmodified lines | ||
| 3 | 3 | ** Required properties: |
| 4 | 4 | |
| 5 | 5 | - compatible : One of the following: |
| 6 | + "samsung,exynos3250-tmu" | |
| 6 | 7 | "samsung,exynos4412-tmu" |
| 7 | 8 | "samsung,exynos4210-tmu" |
| 8 | 9 | "samsung,exynos5250-tmu" |
| @@ -1,7 +1,13 @@ | ||
| 1 | 1 | * Renesas R-Car Thermal |
| 2 | 2 | |
| 3 | 3 | Required properties: |
| 4 | −- compatible : "renesas,rcar-thermal" | |
| 4 | +- compatible : "renesas,thermal-<soctype>", "renesas,rcar-thermal" | |
| 5 | + as fallback. | |
| 6 | + Examples with soctypes are: | |
| 7 | + - "renesas,thermal-r8a73a4" (R-Mobile AP6) | |
| 8 | + - "renesas,thermal-r8a7779" (R-Car H1) | |
| 9 | + - "renesas,thermal-r8a7790" (R-Car H2) | |
| 10 | + - "renesas,thermal-r8a7791" (R-Car M2) | |
| 5 | 11 | - reg : Address range of the thermal registers. |
| 6 | 12 | The 1st reg will be recognized as common register |
| 7 | 13 | if it has "interrupts". |
| @@ -12,18 +18,18 @@ Option properties: · 4 unmodified lines | ||
| 12 | 18 | |
| 13 | 19 | Example (non interrupt support): |
| 14 | 20 | |
| 15 | −thermal@e61f0100 { | |
| 16 | − compatible = "renesas,rcar-thermal"; | |
| 17 | − reg = <0xe61f0100 0x38>; | |
| 21 | +thermal@ffc48000 { | |
| 22 | + compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; | |
| 23 | + reg = <0xffc48000 0x38>; | |
| 18 | 24 | }; |
| 19 | 25 | |
| 20 | 26 | Example (interrupt support): |
| 21 | 27 | |
| 22 | 28 | thermal@e61f0000 { |
| 23 | − compatible = "renesas,rcar-thermal"; | |
| 29 | + compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; | |
| 24 | 30 | reg = <0xe61f0000 0x14 |
| 25 | 31 | 0xe61f0100 0x38 |
| 26 | 32 | 0xe61f0200 0x38 |
| 27 | 33 | 0xe61f0300 0x38>; |
| 28 | − interrupts = <0 69 4>; | |
| 34 | + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; | |
| 29 | 35 | }; |
| @@ -0,0 +1,42 @@ | ||
| 1 | +Binding for Thermal Sensor driver for STMicroelectronics STi series of SoCs. | |
| 2 | + | |
| 3 | +Required parameters: | |
| 4 | +------------------- | |
| 5 | + | |
| 6 | +compatible : st,<SoC>-<module>-thermal; should be one of: | |
| 7 | + "st,stih415-sas-thermal", | |
| 8 | + "st,stih415-mpe-thermal", | |
| 9 | + "st,stih416-sas-thermal" | |
| 10 | + "st,stih416-mpe-thermal" | |
| 11 | + "st,stid127-thermal" or | |
| 12 | + "st,stih407-thermal" | |
| 13 | + according to the SoC type (stih415, stih416, stid127, stih407) | |
| 14 | + and module type (sas or mpe). On stid127 & stih407 there is only | |
| 15 | + one die/module, so there is no module type in the compatible | |
| 16 | + string. | |
| 17 | +clock-names : Should be "thermal". | |
| 18 | + See: Documentation/devicetree/bindings/resource-names.txt | |
| 19 | +clocks : Phandle of the clock used by the thermal sensor. | |
| 20 | + See: Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| 21 | + | |
| 22 | +Optional parameters: | |
| 23 | +------------------- | |
| 24 | + | |
| 25 | +reg : For non-sysconf based sensors, this should be the physical base | |
| 26 | + address and length of the sensor's registers. | |
| 27 | +interrupts : Standard way to define interrupt number. | |
| 28 | + Interrupt is mandatory to be defined when compatible is | |
| 29 | + "stih416-mpe-thermal". | |
| 30 | + NB: For thermal sensor's for which no interrupt has been | |
| 31 | + defined, a polling delay of 1000ms will be used to read the | |
| 32 | + temperature from device. | |
| 33 | + | |
| 34 | +Example: | |
| 35 | + | |
| 36 | + temp1@fdfe8000 { | |
| 37 | + compatible = "st,stih416-mpe-thermal"; | |
| 38 | + reg = <0xfdfe8000 0x10>; | |
| 39 | + clock-names = "thermal"; | |
| 40 | + clocks = <&clk_m_mpethsens>; | |
| 41 | + interrupts = <GIC_SPI 23 IRQ_TYPE_NONE>; | |
| 42 | + }; | |
| @@ -6,6 +6,7 @@ using them to avoid name-space collisions. · 5 unmodified lines | ||
| 6 | 6 | abilis Abilis Systems |
| 7 | 7 | active-semi Active-Semi International Inc |
| 8 | 8 | ad Avionic Design GmbH |
| 9 | +adapteva Adapteva, Inc. | |
| 9 | 10 | adi Analog Devices, Inc. |
| 10 | 11 | aeroflexgaisler Aeroflex Gaisler AB |
| 11 | 12 | ak Asahi Kasei Corp. |
| @@ -72,6 +73,7 @@ karo Ka-Ro electronics GmbH · 60 unmodified lines | ||
| 72 | 73 | keymile Keymile GmbH |
| 73 | 74 | lacie LaCie |
| 74 | 75 | lantiq Lantiq Semiconductor |
| 76 | +lenovo Lenovo Group Ltd. | |
| 75 | 77 | lg LG Corporation |
| 76 | 78 | linux Linux-specific binding |
| 77 | 79 | lsi LSI Corp. (LSI Logic) |
| @@ -101,6 +103,7 @@ panasonic Panasonic Corporation · 23 unmodified lines | ||
| 101 | 103 | phytec PHYTEC Messtechnik GmbH |
| 102 | 104 | picochip Picochip Ltd |
| 103 | 105 | plathome Plat'Home Co., Ltd. |
| 106 | +pixcir PIXCIR MICROELECTRONICS Co., Ltd | |
| 104 | 107 | powervr PowerVR (deprecated, use img) |
| 105 | 108 | qca Qualcomm Atheros, Inc. |
| 106 | 109 | qcom Qualcomm Technologies, Inc |
| @@ -124,6 +127,7 @@ sii Seiko Instruments, Inc. · 17 unmodified lines | ||
| 124 | 127 | sirf SiRF Technology, Inc. |
| 125 | 128 | smsc Standard Microsystems Corporation |
| 126 | 129 | snps Synopsys, Inc. |
| 130 | +solidrun SolidRun | |
| 127 | 131 | spansion Spansion Inc. |
| 128 | 132 | st STMicroelectronics |
| 129 | 133 | ste ST-Ericsson |
| @@ -0,0 +1,109 @@ | ||
| 1 | +* ARM PrimeCell Color LCD Controller PL110/PL111 | |
| 2 | + | |
| 3 | +See also Documentation/devicetree/bindings/arm/primecell.txt | |
| 4 | + | |
| 5 | +Required properties: | |
| 6 | + | |
| 7 | +- compatible: must be one of: | |
| 8 | + "arm,pl110", "arm,primecell" | |
| 9 | + "arm,pl111", "arm,primecell" | |
| 10 | + | |
| 11 | +- reg: base address and size of the control registers block | |
| 12 | + | |
| 13 | +- interrupt-names: either the single entry "combined" representing a | |
| 14 | + combined interrupt output (CLCDINTR), or the four entries | |
| 15 | + "mbe", "vcomp", "lnbu", "fuf" representing the individual | |
| 16 | + CLCDMBEINTR, CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR interrupts | |
| 17 | + | |
| 18 | +- interrupts: contains an interrupt specifier for each entry in | |
| 19 | + interrupt-names | |
| 20 | + | |
| 21 | +- clock-names: should contain "clcdclk" and "apb_pclk" | |
| 22 | + | |
| 23 | +- clocks: contains phandle and clock specifier pairs for the entries | |
| 24 | + in the clock-names property. See | |
| 25 | + Documentation/devicetree/binding/clock/clock-bindings.txt | |
| 26 | + | |
| 27 | +Optional properties: | |
| 28 | + | |
| 29 | +- memory-region: phandle to a node describing memory (see | |
| 30 | + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) | |
| 31 | + to be used for the framebuffer; if not present, the framebuffer | |
| 32 | + may be located anywhere in the memory | |
| 33 | + | |
| 34 | +- max-memory-bandwidth: maximum bandwidth in bytes per second that the | |
| 35 | + cell's memory interface can handle; if not present, the memory | |
| 36 | + interface is fast enough to handle all possible video modes | |
| 37 | + | |
| 38 | +Required sub-nodes: | |
| 39 | + | |
| 40 | +- port: describes LCD panel signals, following the common binding | |
| 41 | + for video transmitter interfaces; see | |
| 42 | + Documentation/devicetree/bindings/media/video-interfaces.txt; | |
| 43 | + when it is a TFT panel, the port's endpoint must define the | |
| 44 | + following property: | |
| 45 | + | |
| 46 | + - arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values, | |
| 47 | + defining the way CLD pads are wired up; first value | |
| 48 | + contains index of the "CLD" external pin (pad) used | |
| 49 | + as R0 (first bit of the red component), second value | |
| 50 | + index of the pad used as G0, third value index of the | |
| 51 | + pad used as B0, see also "LCD panel signal multiplexing | |
| 52 | + details" paragraphs in the PL110/PL111 Technical | |
| 53 | + Reference Manuals; this implicitly defines available | |
| 54 | + color modes, for example: | |
| 55 | + - PL111 TFT 4:4:4 panel: | |
| 56 | + arm,pl11x,tft-r0g0b0-pads = <4 15 20>; | |
| 57 | + - PL110 TFT (1:)5:5:5 panel: | |
| 58 | + arm,pl11x,tft-r0g0b0-pads = <1 7 13>; | |
| 59 | + - PL111 TFT (1:)5:5:5 panel: | |
| 60 | + arm,pl11x,tft-r0g0b0-pads = <3 11 19>; | |
| 61 | + - PL111 TFT 5:6:5 panel: | |
| 62 | + arm,pl11x,tft-r0g0b0-pads = <3 10 19>; | |
| 63 | + - PL110 and PL111 TFT 8:8:8 panel: | |
| 64 | + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; | |
| 65 | + - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped: | |
| 66 | + arm,pl11x,tft-r0g0b0-pads = <16 8 0>; | |
| 67 | + | |
| 68 | + | |
| 69 | +Example: | |
| 70 | + | |
| 71 | + clcd@10020000 { | |
| 72 | + compatible = "arm,pl111", "arm,primecell"; | |
| 73 | + reg = <0x10020000 0x1000>; | |
| 74 | + interrupt-names = "combined"; | |
| 75 | + interrupts = <0 44 4>; | |
| 76 | + clocks = <&oscclk1>, <&oscclk2>; | |
| 77 | + clock-names = "clcdclk", "apb_pclk"; | |
| 78 | + max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */ | |
| 79 | + | |
| 80 | + port { | |
| 81 | + clcd_pads: endpoint { | |
| 82 | + remote-endpoint = <&clcd_panel>; | |
| 83 | + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; | |
| 84 | + }; | |
| 85 | + }; | |
| 86 | + | |
| 87 | + }; | |
| 88 | + | |
| 89 | + panel { | |
| 90 | + compatible = "panel-dpi"; | |
| 91 | + | |
| 92 | + port { | |
| 93 | + clcd_panel: endpoint { | |
| 94 | + remote-endpoint = <&clcd_pads>; | |
| 95 | + }; | |
| 96 | + }; | |
| 97 | + | |
| 98 | + panel-timing { | |
| 99 | + clock-frequency = <25175000>; | |
| 100 | + hactive = <640>; | |
| 101 | + hback-porch = <40>; | |
| 102 | + hfront-porch = <24>; | |
| 103 | + hsync-len = <96>; | |
| 104 | + vactive = <480>; | |
| 105 | + vback-porch = <32>; | |
| 106 | + vfront-porch = <11>; | |
| 107 | + vsync-len = <2>; | |
| 108 | + }; | |
| 109 | + }; | |
| @@ -46,6 +46,7 @@ Required properties (as per of_videomode_helper): · 45 unmodified lines | ||
| 46 | 46 | |
| 47 | 47 | Optional properties (as per of_videomode_helper): |
| 48 | 48 | - atmel,lcdcon-backlight: enable backlight |
| 49 | + - atmel,lcdcon-backlight-inverted: invert backlight PWM polarity | |
| 49 | 50 | - atmel,lcd-wiring-mode: lcd wiring mode "RGB" or "BRG" |
| 50 | 51 | - atmel,power-control-gpio: gpio to power on or off the LCD (as many as needed) |
| 51 | 52 | |
| @@ -0,0 +1,47 @@ | ||
| 1 | +* Currus Logic CLPS711X Framebuffer | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: Shall contain "cirrus,clps711x-fb". | |
| 5 | +- reg : Physical base address and length of the controller's registers + | |
| 6 | + location and size of the framebuffer memory. | |
| 7 | +- clocks : phandle + clock specifier pair of the FB reference clock. | |
| 8 | +- display : phandle to a display node as described in | |
| 9 | + Documentation/devicetree/bindings/video/display-timing.txt. | |
| 10 | + Additionally, the display node has to define properties: | |
| 11 | + - bits-per-pixel: Bits per pixel. | |
| 12 | + - ac-prescale : LCD AC bias frequency. This frequency is the required | |
| 13 | + AC bias frequency for a given manufacturer's LCD plate. | |
| 14 | + - cmap-invert : Invert the color levels (Optional). | |
| 15 | + | |
| 16 | +Optional properties: | |
| 17 | +- lcd-supply: Regulator for LCD supply voltage. | |
| 18 | + | |
| 19 | +Example: | |
| 20 | + fb: fb@800002c0 { | |
| 21 | + compatible = "cirrus,ep7312-fb", "cirrus,clps711x-fb"; | |
| 22 | + reg = <0x800002c0 0xd44>, <0x60000000 0xc000>; | |
| 23 | + clocks = <&clks 2>; | |
| 24 | + lcd-supply = <®5v0>; | |
| 25 | + display = <&display>; | |
| 26 | + }; | |
| 27 | + | |
| 28 | + display: display { | |
| 29 | + model = "320x240x4"; | |
| 30 | + native-mode = <&timing0>; | |
| 31 | + bits-per-pixel = <4>; | |
| 32 | + ac-prescale = <17>; | |
| 33 | + | |
| 34 | + display-timings { | |
| 35 | + timing0: 320x240 { | |
| 36 | + hactive = <320>; | |
| 37 | + hback-porch = <0>; | |
| 38 | + hfront-porch = <0>; | |
| 39 | + hsync-len = <0>; | |
| 40 | + vactive = <240>; | |
| 41 | + vback-porch = <0>; | |
| 42 | + vfront-porch = <0>; | |
| 43 | + vsync-len = <0>; | |
| 44 | + clock-frequency = <6500000>; | |
| 45 | + }; | |
| 46 | + }; | |
| 47 | + }; | |
| @@ -1,7 +1,9 @@ | ||
| 1 | 1 | Exynos MIPI DSI Master |
| 2 | 2 | |
| 3 | 3 | Required properties: |
| 4 | − - compatible: "samsung,exynos4210-mipi-dsi" | |
| 4 | + - compatible: value should be one of the following | |
| 5 | + "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */ | |
| 6 | + "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */ | |
| 5 | 7 | - reg: physical base address and length of the registers set for the device |
| 6 | 8 | - interrupts: should contain DSI interrupt |
| 7 | 9 | - clocks: list of clock specifiers, must contain an entry for each required |
| @@ -4,8 +4,9 @@ Required properties: · 3 unmodified lines | ||
| 4 | 4 | - compatible: value should be one of the following: |
| 5 | 5 | 1) "samsung,exynos5-mixer" <DEPRECATED> |
| 6 | 6 | 2) "samsung,exynos4210-mixer" |
| 7 | − 3) "samsung,exynos5250-mixer" | |
| 8 | − 4) "samsung,exynos5420-mixer" | |
| 7 | + 3) "samsung,exynos4212-mixer" | |
| 8 | + 4) "samsung,exynos5250-mixer" | |
| 9 | + 5) "samsung,exynos5420-mixer" | |
| 9 | 10 | |
| 10 | 11 | - reg: physical base address of the mixer and length of memory mapped |
| 11 | 12 | region. |
| @@ -8,8 +8,6 @@ Required properties: · 7 unmodified lines | ||
| 8 | 8 | - compatible: value should be one of the following |
| 9 | 9 | "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */ |
| 10 | 10 | "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */ |
| 11 | − "samsung,s5p6440-fimd"; /* for S5P64X0 SoCs */ | |
| 12 | − "samsung,s5pc100-fimd"; /* for S5PC100 SoC */ | |
| 13 | 11 | "samsung,s5pv210-fimd"; /* for S5PV210 SoC */ |
| 14 | 12 | "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */ |
| 15 | 13 | "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */ |
| @@ -44,6 +42,34 @@ Optional Properties: · 28 unmodified lines | ||
| 44 | 42 | - display-timings: timing settings for FIMD, as described in document [1]. |
| 45 | 43 | Can be used in case timings cannot be provided otherwise |
| 46 | 44 | or to override timings provided by the panel. |
| 45 | +- samsung,sysreg: handle to syscon used to control the system registers | |
| 46 | +- i80-if-timings: timing configuration for lcd i80 interface support. | |
| 47 | + - cs-setup: clock cycles for the active period of address signal is enabled | |
| 48 | + until chip select is enabled. | |
| 49 | + If not specified, the default value(0) will be used. | |
| 50 | + - wr-setup: clock cycles for the active period of CS signal is enabled until | |
| 51 | + write signal is enabled. | |
| 52 | + If not specified, the default value(0) will be used. | |
| 53 | + - wr-active: clock cycles for the active period of CS is enabled. | |
| 54 | + If not specified, the default value(1) will be used. | |
| 55 | + - wr-hold: clock cycles for the active period of CS is disabled until write | |
| 56 | + signal is disabled. | |
| 57 | + If not specified, the default value(0) will be used. | |
| 58 | + | |
| 59 | + The parameters are defined as: | |
| 60 | + | |
| 61 | + VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|?? | |
| 62 | + : : : : : | |
| 63 | + Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX | |
| 64 | + | cs-setup+1 | : : : | |
| 65 | + |<---------->| : : : | |
| 66 | + Chip Select ???????????????|____________:____________:____________|?? | |
| 67 | + | wr-setup+1 | | wr-hold+1 | | |
| 68 | + |<---------->| |<---------->| | |
| 69 | + Write Enable ????????????????????????????|____________|??????????????? | |
| 70 | + | wr-active+1| | |
| 71 | + |<---------->| | |
| 72 | + Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>-- | |
| 47 | 73 | |
| 48 | 74 | The device node can contain 'port' child nodes according to the bindings defined |
| 49 | 75 | in [2]. The following are properties specific to those nodes: |
| @@ -0,0 +1,40 @@ | ||
| 1 | +A DT changeset is a method which allows one to apply changes | |
| 2 | +in the live tree in such a way that either the full set of changes | |
| 3 | +will be applied, or none of them will be. If an error occurs partway | |
| 4 | +through applying the changeset, then the tree will be rolled back to the | |
| 5 | +previous state. A changeset can also be removed after it has been | |
| 6 | +applied. | |
| 7 | + | |
| 8 | +When a changeset is applied, all of the changes get applied to the tree | |
| 9 | +at once before emitting OF_RECONFIG notifiers. This is so that the | |
| 10 | +receiver sees a complete and consistent state of the tree when it | |
| 11 | +receives the notifier. | |
| 12 | + | |
| 13 | +The sequence of a changeset is as follows. | |
| 14 | + | |
| 15 | +1. of_changeset_init() - initializes a changeset | |
| 16 | + | |
| 17 | +2. A number of DT tree change calls, of_changeset_attach_node(), | |
| 18 | +of_changeset_detach_node(), of_changeset_add_property(), | |
| 19 | +of_changeset_remove_property, of_changeset_update_property() to prepare | |
| 20 | +a set of changes. No changes to the active tree are made at this point. | |
| 21 | +All the change operations are recorded in the of_changeset 'entries' | |
| 22 | +list. | |
| 23 | + | |
| 24 | +3. mutex_lock(of_mutex) - starts a changeset; The global of_mutex | |
| 25 | +ensures there can only be one editor at a time. | |
| 26 | + | |
| 27 | +4. of_changeset_apply() - Apply the changes to the tree. Either the | |
| 28 | +entire changeset will get applied, or if there is an error the tree will | |
| 29 | +be restored to the previous state | |
| 30 | + | |
| 31 | +5. mutex_unlock(of_mutex) - All operations complete, release the mutex | |
| 32 | + | |
| 33 | +If a successfully applied changeset needs to be removed, it can be done | |
| 34 | +with the following sequence. | |
| 35 | + | |
| 36 | +1. mutex_lock(of_mutex) | |
| 37 | + | |
| 38 | +2. of_changeset_revert() | |
| 39 | + | |
| 40 | +3. mutex_unlock(of_mutex) | |
| @@ -0,0 +1,11 @@ | ||
| 1 | +Todo list for devicetree: | |
| 2 | + | |
| 3 | +=== General structure === | |
| 4 | +- Switch from custom lists to (h)list_head for nodes and properties structure | |
| 5 | +- Remove of_allnodes list and iterate using list of child nodes alone | |
| 6 | + | |
| 7 | +=== CONFIG_OF_DYNAMIC === | |
| 8 | +- Switch to RCU for tree updates and get rid of global spinlock | |
| 9 | +- Document node lifecycle for CONFIG_OF_DYNAMIC | |
| 10 | +- Always set ->full_name at of_attach_node() time | |
| 11 | +- pseries: Get rid of open-coded tree modification from arch/powerpc/platforms/pseries/dlpar.c | |
| @@ -84,31 +84,32 @@ The slave DMA usage consists of following steps: · 83 unmodified lines | ||
| 84 | 84 | the given transaction. |
| 85 | 85 | |
| 86 | 86 | Interface: |
| 87 | − struct dma_async_tx_descriptor *(*chan->device->device_prep_slave_sg)( | |
| 87 | + struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( | |
| 88 | 88 | struct dma_chan *chan, struct scatterlist *sgl, |
| 89 | 89 | unsigned int sg_len, enum dma_data_direction direction, |
| 90 | 90 | unsigned long flags); |
| 91 | 91 | |
| 92 | − struct dma_async_tx_descriptor *(*chan->device->device_prep_dma_cyclic)( | |
| 92 | + struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( | |
| 93 | 93 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, |
| 94 | 94 | size_t period_len, enum dma_data_direction direction); |
| 95 | 95 | |
| 96 | − struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( | |
| 96 | + struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( | |
| 97 | 97 | struct dma_chan *chan, struct dma_interleaved_template *xt, |
| 98 | 98 | unsigned long flags); |
| 99 | 99 | |
| 100 | 100 | The peripheral driver is expected to have mapped the scatterlist for |
| 101 | 101 | the DMA operation prior to calling device_prep_slave_sg, and must |
| 102 | 102 | keep the scatterlist mapped until the DMA operation has completed. |
| 103 | − The scatterlist must be mapped using the DMA struct device. So, | |
| 104 | − normal setup should look like this: | |
| 103 | + The scatterlist must be mapped using the DMA struct device. | |
| 104 | + If a mapping needs to be synchronized later, dma_sync_*_for_*() must be | |
| 105 | + called using the DMA struct device, too. | |
| 106 | + So, normal setup should look like this: | |
| 105 | 107 | |
| 106 | 108 | nr_sg = dma_map_sg(chan->device->dev, sgl, sg_len); |
| 107 | 109 | if (nr_sg == 0) |
| 108 | 110 | /* error */ |
| 109 | 111 | |
| 110 | − desc = chan->device->device_prep_slave_sg(chan, sgl, nr_sg, | |
| 111 | − direction, flags); | |
| 112 | + desc = dmaengine_prep_slave_sg(chan, sgl, nr_sg, direction, flags); | |
| 112 | 113 | |
| 113 | 114 | Once a descriptor has been obtained, the callback information can be |
| 114 | 115 | added and the descriptor must then be submitted. Some DMA engine |
| @@ -188,7 +189,7 @@ Further APIs: · 73 unmodified lines | ||
| 188 | 189 | description of this API. |
| 189 | 190 | |
| 190 | 191 | This can be used in conjunction with dma_async_is_complete() and |
| 191 | − the cookie returned from 'descriptor->submit()' to check for | |
| 192 | + the cookie returned from dmaengine_submit() to check for | |
| 192 | 193 | completion of a specific DMA transaction. |
| 193 | 194 | |
| 194 | 195 | Note: |
| @@ -349,7 +349,11 @@ prototypes: · 348 unmodified lines | ||
| 349 | 349 | locking rules: |
| 350 | 350 | inode->i_lock may block |
| 351 | 351 | fl_copy_lock: yes no |
| 352 | −fl_release_private: maybe no | |
| 352 | +fl_release_private: maybe maybe[1] | |
| 353 | + | |
| 354 | +[1]: ->fl_release_private for flock or POSIX locks is currently allowed | |
| 355 | +to block. Leases however can still be freed while the i_lock is held and | |
| 356 | +so fl_release_private called on a lease should not block. | |
| 353 | 357 | |
| 354 | 358 | ----------------------- lock_manager_operations --------------------------- |
| 355 | 359 | prototypes: |
| @@ -40,6 +40,7 @@ Gunter Kukkukk (testing and suggestions for support of old servers) · 39 unmodified lines | ||
| 40 | 40 | Igor Mammedov (DFS support) |
| 41 | 41 | Jeff Layton (many, many fixes, as well as great work on the cifs Kerberos code) |
| 42 | 42 | Scott Lovenberg |
| 43 | +Pavel Shilovsky (for great work adding SMB2 support, and various SMB3 features) | |
| 43 | 44 | |
| 44 | 45 | Test case and Bug Report contributors |
| 45 | 46 | ------------------------------------- |
| @@ -1,4 +1,4 @@ | ||
| 1 | −Version 1.53 May 20, 2008 | |
| 1 | +Version 2.03 August 1, 2014 | |
| 2 | 2 | |
| 3 | 3 | A Partial List of Missing Features |
| 4 | 4 | ================================== |
| @@ -7,63 +7,49 @@ Contributions are welcome. There are plenty of opportunities · 2 unmodified lines | ||
| 7 | 7 | for visible, important contributions to this module. Here |
| 8 | 8 | is a partial list of the known problems and missing features: |
| 9 | 9 | |
| 10 | −a) Support for SecurityDescriptors(Windows/CIFS ACLs) for chmod/chgrp/chown | |
| 11 | −so that these operations can be supported to Windows servers | |
| 10 | +a) SMB3 (and SMB3.02) missing optional features: | |
| 11 | + - RDMA | |
| 12 | + - multichannel (started) | |
| 13 | + - directory leases (improved metadata caching) | |
| 14 | + - T10 copy offload (copy chunk is only mechanism supported) | |
| 15 | + - encrypted shares | |
| 12 | 16 | |
| 13 | −b) Mapping POSIX ACLs (and eventually NFSv4 ACLs) to CIFS | |
| 14 | −SecurityDescriptors | |
| 17 | +b) improved sparse file support | |
| 15 | 18 | |
| 16 | −c) Better pam/winbind integration (e.g. to handle uid mapping | |
| 17 | −better) | |
| 18 | − | |
| 19 | −d) Cleanup now unneeded SessSetup code in | |
| 20 | −fs/cifs/connect.c and add back in NTLMSSP code if any servers | |
| 21 | −need it | |
| 22 | − | |
| 23 | −e) fix NTLMv2 signing when two mounts with different users to same | |
| 24 | −server. | |
| 25 | − | |
| 26 | −f) Directory entry caching relies on a 1 second timer, rather than | |
| 19 | +c) Directory entry caching relies on a 1 second timer, rather than | |
| 27 | 20 | using FindNotify or equivalent. - (started) |
| 28 | 21 | |
| 29 | −g) quota support (needs minor kernel change since quota calls | |
| 22 | +d) quota support (needs minor kernel change since quota calls | |
| 30 | 23 | to make it to network filesystems or deviceless filesystems) |
| 31 | 24 | |
| 32 | −h) investigate sync behavior (including syncpage) and check | |
| 33 | −for proper behavior of intr/nointr | |
| 34 | − | |
| 35 | −i) improve support for very old servers (OS/2 and Win9x for example) | |
| 25 | +e) improve support for very old servers (OS/2 and Win9x for example) | |
| 36 | 26 | Including support for changing the time remotely (utimes command). |
| 37 | 27 | |
| 38 | −j) hook lower into the sockets api (as NFS/SunRPC does) to avoid the | |
| 28 | +f) hook lower into the sockets api (as NFS/SunRPC does) to avoid the | |
| 39 | 29 | extra copy in/out of the socket buffers in some cases. |
| 40 | 30 | |
| 41 | −k) Better optimize open (and pathbased setfilesize) to reduce the | |
| 31 | +g) Better optimize open (and pathbased setfilesize) to reduce the | |
| 42 | 32 | oplock breaks coming from windows srv. Piggyback identical file |
| 43 | 33 | opens on top of each other by incrementing reference count rather |
| 44 | 34 | than resending (helps reduce server resource utilization and avoid |
| 45 | 35 | spurious oplock breaks). |
| 46 | 36 | |
| 47 | −l) Improve performance of readpages by sending more than one read | |
| 48 | −at a time when 8 pages or more are requested. In conjuntion | |
| 49 | −add support for async_cifs_readpages. | |
| 50 | − | |
| 51 | −m) Add support for storing symlink info to Windows servers | |
| 37 | +h) Add support for storing symlink info to Windows servers | |
| 52 | 38 | in the Extended Attribute format their SFU clients would recognize. |
| 53 | 39 | |
| 54 | −n) Finish fcntl D_NOTIFY support so kde and gnome file list windows | |
| 40 | +i) Finish inotify support so kde and gnome file list windows | |
| 55 | 41 | will autorefresh (partially complete by Asser). Needs minor kernel |
| 56 | 42 | vfs change to support removing D_NOTIFY on a file. |
| 57 | 43 | |
| 58 | −o) Add GUI tool to configure /proc/fs/cifs settings and for display of | |
| 44 | +j) Add GUI tool to configure /proc/fs/cifs settings and for display of | |
| 59 | 45 | the CIFS statistics (started) |
| 60 | 46 | |
| 61 | −p) implement support for security and trusted categories of xattrs | |
| 47 | +k) implement support for security and trusted categories of xattrs | |
| 62 | 48 | (requires minor protocol extension) to enable better support for SELINUX |
| 63 | 49 | |
| 64 | −q) Implement O_DIRECT flag on open (already supported on mount) | |
| 50 | +l) Implement O_DIRECT flag on open (already supported on mount) | |
| 65 | 51 | |
| 66 | −r) Create UID mapping facility so server UIDs can be mapped on a per | |
| 52 | +m) Create UID mapping facility so server UIDs can be mapped on a per | |
| 67 | 53 | mount or a per server basis to client UIDs or nobody if no mapping |
| 68 | 54 | exists. This is helpful when Unix extensions are negotiated to |
| 69 | 55 | allow better permission checking when UIDs differ on the server |
| @@ -71,28 +57,29 @@ and client. Add new protocol request to the CIFS protocol · 1 unmodified line | ||
| 71 | 57 | standard for asking the server for the corresponding name of a |
| 72 | 58 | particular uid. |
| 73 | 59 | |
| 74 | −s) Add support for CIFS Unix and also the newer POSIX extensions to the | |
| 75 | −server side for Samba 4. | |
| 60 | +n) DOS attrs - returned as pseudo-xattr in Samba format (check VFAT and NTFS for this too) | |
| 61 | + | |
| 62 | +o) mount check for unmatched uids | |
| 76 | 63 | |
| 77 | −t) In support for OS/2 (LANMAN 1.2 and LANMAN2.1 based SMB servers) | |
| 78 | −need to add ability to set time to server (utimes command) | |
| 64 | +p) Add support for new vfs entry point for fallocate | |
| 79 | 65 | |
| 80 | −u) DOS attrs - returned as pseudo-xattr in Samba format (check VFAT and NTFS for this too) | |
| 66 | +q) Add tools to take advantage of cifs/smb3 specific ioctls and features | |
| 67 | +such as "CopyChunk" (fast server side file copy) | |
| 81 | 68 | |
| 82 | −v) mount check for unmatched uids | |
| 69 | +r) encrypted file support | |
| 83 | 70 | |
| 84 | −w) Add support for new vfs entry point for fallocate | |
| 71 | +s) improved stats gathering, tools (perhaps integration with nfsometer?) | |
| 85 | 72 | |
| 86 | −x) Fix Samba 3 server to handle Linux kernel aio so dbench with lots of | |
| 87 | −processes can proceed better in parallel (on the server) | |
| 73 | +t) allow setting more NTFS/SMB3 file attributes remotely (currently limited to compressed | |
| 74 | +file attribute via chflags) | |
| 88 | 75 | |
| 89 | −y) Fix Samba 3 to handle reads/writes over 127K (and remove the cifs mount | |
| 90 | −restriction of wsize max being 127K) | |
| 76 | +u) mount helper GUI (to simplify the various configuration options on mount) | |
| 91 | 77 | |
| 92 | −KNOWN BUGS (updated April 24, 2007) | |
| 78 | + | |
| 79 | +KNOWN BUGS | |
| 93 | 80 | ==================================== |
| 94 | 81 | See http://bugzilla.samba.org - search on product "CifsVFS" for |
| 95 | −current bug list. | |
| 82 | +current bug list. Also check http://bugzilla.kernel.org (Product = File System, Component = CIFS) | |
| 96 | 83 | |
| 97 | 84 | 1) existing symbolic links (Windows reparse points) are recognized but |
| 98 | 85 | can not be created remotely. They are implemented for Samba and those that |
| @@ -100,30 +87,18 @@ support the CIFS Unix extensions, although earlier versions of Samba · 1 unmodified line | ||
| 100 | 87 | overly restrict the pathnames. |
| 101 | 88 | 2) follow_link and readdir code does not follow dfs junctions |
| 102 | 89 | but recognizes them |
| 103 | −3) create of new files to FAT partitions on Windows servers can | |
| 104 | −succeed but still return access denied (appears to be Windows | |
| 105 | −server not cifs client problem) and has not been reproduced recently. | |
| 106 | −NTFS partitions do not have this problem. | |
| 107 | −4) Unix/POSIX capabilities are reset after reconnection, and affect | |
| 108 | −a few fields in the tree connection but we do do not know which | |
| 109 | −superblocks to apply these changes to. We should probably walk | |
| 110 | −the list of superblocks to set these. Also need to check the | |
| 111 | −flags on the second mount to the same share, and see if we | |
| 112 | −can do the same trick that NFS does to remount duplicate shares. | |
| 113 | 90 | |
| 114 | 91 | Misc testing to do |
| 115 | 92 | ================== |
| 116 | 93 | 1) check out max path names and max path name components against various server |
| 117 | 94 | types. Try nested symlinks (8 deep). Return max path name in stat -f information |
| 118 | 95 | |
| 119 | −2) Modify file portion of ltp so it can run against a mounted network | |
| 120 | −share and run it against cifs vfs in automated fashion. | |
| 96 | +2) Improve xfstest's cifs enablement and adapt xfstests where needed to test | |
| 97 | +cifs better | |
| 121 | 98 | |
| 122 | 99 | 3) Additional performance testing and optimization using iozone and similar - |
| 123 | 100 | there are some easy changes that can be done to parallelize sequential writes, |
| 124 | 101 | and when signing is disabled to request larger read sizes (larger than |
| 125 | 102 | negotiated size) and send larger write sizes to modern servers. |
| 126 | 103 | |
| 127 | −4) More exhaustively test against less common servers. More testing | |
| 128 | −against Windows 9x, Windows ME servers. | |
| 129 | − | |
| 104 | +4) More exhaustively test against less common servers | |
| @@ -66,23 +66,31 @@ b/ A per-superblock list "s_anon" of dentries which are the roots of · 65 unmodified lines | ||
| 66 | 66 | |
| 67 | 67 | c/ Helper routines to allocate anonymous dentries, and to help attach |
| 68 | 68 | loose directory dentries at lookup time. They are: |
| 69 | − d_alloc_anon(inode) will return a dentry for the given inode. | |
| 69 | + d_obtain_alias(inode) will return a dentry for the given inode. | |
| 70 | 70 | If the inode already has a dentry, one of those is returned. |
| 71 | 71 | If it doesn't, a new anonymous (IS_ROOT and |
| 72 | 72 | DCACHE_DISCONNECTED) dentry is allocated and attached. |
| 73 | 73 | In the case of a directory, care is taken that only one dentry |
| 74 | 74 | can ever be attached. |
| 75 | − d_splice_alias(inode, dentry) will make sure that there is a | |
| 76 | − dentry with the same name and parent as the given dentry, and | |
| 77 | − which refers to the given inode. | |
| 78 | − If the inode is a directory and already has a dentry, then that | |
| 79 | − dentry is d_moved over the given dentry. | |
| 80 | − If the passed dentry gets attached, care is taken that this is | |
| 81 | − mutually exclusive to a d_alloc_anon operation. | |
| 82 | − If the passed dentry is used, NULL is returned, else the used | |
| 83 | − dentry is returned. This corresponds to the calling pattern of | |
| 84 | − ->lookup. | |
| 85 | − | |
| 75 | + d_splice_alias(inode, dentry) or d_materialise_unique(dentry, inode) | |
| 76 | + will introduce a new dentry into the tree; either the passed-in | |
| 77 | + dentry or a preexisting alias for the given inode (such as an | |
| 78 | + anonymous one created by d_obtain_alias), if appropriate. The two | |
| 79 | + functions differ in their handling of directories with preexisting | |
| 80 | + aliases: | |
| 81 | + d_splice_alias will use any existing IS_ROOT dentry, but it will | |
| 82 | + return -EIO rather than try to move a dentry with a different | |
| 83 | + parent. This is appropriate for local filesystems, which | |
| 84 | + should never see such an alias unless the filesystem is | |
| 85 | + corrupted somehow (for example, if two on-disk directory | |
| 86 | + entries refer to the same directory.) | |
| 87 | + d_materialise_unique will attempt to move any dentry. This is | |
| 88 | + appropriate for distributed filesystems, where finding a | |
| 89 | + directory other than where we last cached it may be a normal | |
| 90 | + consequence of concurrent operations on other hosts. | |
| 91 | + Both functions return NULL when the passed-in dentry is used, | |
| 92 | + following the calling convention of ->lookup. | |
| 93 | + | |
| 86 | 94 | |
| 87 | 95 | Filesystem Issues |
| 88 | 96 | ----------------- |
| @@ -120,12 +128,12 @@ struct which has the following members: · 31 unmodified lines | ||
| 120 | 128 | |
| 121 | 129 | fh_to_dentry (mandatory) |
| 122 | 130 | Given a filehandle fragment, this should find the implied object and |
| 123 | − create a dentry for it (possibly with d_alloc_anon). | |
| 131 | + create a dentry for it (possibly with d_obtain_alias). | |
| 124 | 132 | |
| 125 | 133 | fh_to_parent (optional but strongly recommended) |
| 126 | 134 | Given a filehandle fragment, this should find the parent of the |
| 127 | − implied object and create a dentry for it (possibly with d_alloc_anon). | |
| 128 | − May fail if the filehandle fragment is too small. | |
| 135 | + implied object and create a dentry for it (possibly with | |
| 136 | + d_obtain_alias). May fail if the filehandle fragment is too small. | |
| 129 | 137 | |
| 130 | 138 | get_parent (optional but strongly recommended) |
| 131 | 139 | When given a dentry for a directory, this should return a dentry for |
| @@ -1053,7 +1053,8 @@ struct dentry_operations { · 1052 unmodified lines | ||
| 1053 | 1053 | If the 'rcu_walk' parameter is true, then the caller is doing a |
| 1054 | 1054 | pathwalk in RCU-walk mode. Sleeping is not permitted in this mode, |
| 1055 | 1055 | and the caller can be asked to leave it and call again by returning |
| 1056 | − -ECHILD. | |
| 1056 | + -ECHILD. -EISDIR may also be returned to tell pathwalk to | |
| 1057 | + ignore d_automount or any mounts. | |
| 1057 | 1058 | |
| 1058 | 1059 | This function is only used if DCACHE_MANAGE_TRANSIT is set on the |
| 1059 | 1060 | dentry being transited from. |
| @@ -60,7 +60,7 @@ Platform Data · 59 unmodified lines | ||
| 60 | 60 | Finally, GPIOs can be bound to devices and functions using platform data. Board |
| 61 | 61 | files that desire to do so need to include the following header: |
| 62 | 62 | |
| 63 | − #include <linux/gpio/driver.h> | |
| 63 | + #include <linux/gpio/machine.h> | |
| 64 | 64 | |
| 65 | 65 | GPIOs are mapped by the means of tables of lookups, containing instances of the |
| 66 | 66 | gpiod_lookup structure. Two macros are defined to help declaring such mappings: |
| @@ -29,13 +29,24 @@ gpiod_get() functions. Like many other kernel subsystems, gpiod_get() takes the · 28 unmodified lines | ||
| 29 | 29 | device that will use the GPIO and the function the requested GPIO is supposed to |
| 30 | 30 | fulfill: |
| 31 | 31 | |
| 32 | − struct gpio_desc *gpiod_get(struct device *dev, const char *con_id) | |
| 32 | + struct gpio_desc *gpiod_get(struct device *dev, const char *con_id, | |
| 33 | + enum gpiod_flags flags) | |
| 33 | 34 | |
| 34 | 35 | If a function is implemented by using several GPIOs together (e.g. a simple LED |
| 35 | 36 | device that displays digits), an additional index argument can be specified: |
| 36 | 37 | |
| 37 | 38 | struct gpio_desc *gpiod_get_index(struct device *dev, |
| 38 | − const char *con_id, unsigned int idx) | |
| 39 | + const char *con_id, unsigned int idx, | |
| 40 | + enum gpiod_flags flags) | |
| 41 | + | |
| 42 | +The flags parameter is used to optionally specify a direction and initial value | |
| 43 | +for the GPIO. Values can be: | |
| 44 | + | |
| 45 | +* GPIOD_ASIS or 0 to not initialize the GPIO at all. The direction must be set | |
| 46 | + later with one of the dedicated functions. | |
| 47 | +* GPIOD_IN to initialize the GPIO as input. | |
| 48 | +* GPIOD_OUT_LOW to initialize the GPIO as output with a value of 0. | |
| 49 | +* GPIOD_OUT_HIGH to initialize the GPIO as output with a value of 1. | |
| 39 | 50 | |
| 40 | 51 | Both functions return either a valid GPIO descriptor, or an error code checkable |
| 41 | 52 | with IS_ERR() (they will never return a NULL pointer). -ENOENT will be returned |
| @@ -46,11 +57,13 @@ errors and an absence of GPIO for optional GPIO parameters. · 4 unmodified lines | ||
| 46 | 57 | |
| 47 | 58 | Device-managed variants of these functions are also defined: |
| 48 | 59 | |
| 49 | − struct gpio_desc *devm_gpiod_get(struct device *dev, const char *con_id) | |
| 60 | + struct gpio_desc *devm_gpiod_get(struct device *dev, const char *con_id, | |
| 61 | + enum gpiod_flags flags) | |
| 50 | 62 | |
| 51 | 63 | struct gpio_desc *devm_gpiod_get_index(struct device *dev, |
| 52 | 64 | const char *con_id, |
| 53 | − unsigned int idx) | |
| 65 | + unsigned int idx, | |
| 66 | + enum gpiod_flags flags) | |
| 54 | 67 | |
| 55 | 68 | A GPIO descriptor can be disposed of using the gpiod_put() function: |
| 56 | 69 | |
| @@ -67,8 +80,9 @@ Using GPIOs · 10 unmodified lines | ||
| 67 | 80 | |
| 68 | 81 | Setting Direction |
| 69 | 82 | ----------------- |
| 70 | −The first thing a driver must do with a GPIO is setting its direction. This is | |
| 71 | −done by invoking one of the gpiod_direction_*() functions: | |
| 83 | +The first thing a driver must do with a GPIO is setting its direction. If no | |
| 84 | +direction-setting flags have been given to gpiod_get*(), this is done by | |
| 85 | +invoking one of the gpiod_direction_*() functions: | |
| 72 | 86 | |
| 73 | 87 | int gpiod_direction_input(struct gpio_desc *desc) |
| 74 | 88 | int gpiod_direction_output(struct gpio_desc *desc, int value) |
| @@ -157,13 +157,34 @@ Locking IRQ usage · 156 unmodified lines | ||
| 157 | 157 | Input GPIOs can be used as IRQ signals. When this happens, a driver is requested |
| 158 | 158 | to mark the GPIO as being used as an IRQ: |
| 159 | 159 | |
| 160 | − int gpiod_lock_as_irq(struct gpio_desc *desc) | |
| 160 | + int gpio_lock_as_irq(struct gpio_chip *chip, unsigned int offset) | |
| 161 | 161 | |
| 162 | 162 | This will prevent the use of non-irq related GPIO APIs until the GPIO IRQ lock |
| 163 | 163 | is released: |
| 164 | 164 | |
| 165 | − void gpiod_unlock_as_irq(struct gpio_desc *desc) | |
| 165 | + void gpio_unlock_as_irq(struct gpio_chip *chip, unsigned int offset) | |
| 166 | 166 | |
| 167 | 167 | When implementing an irqchip inside a GPIO driver, these two functions should |
| 168 | 168 | typically be called in the .startup() and .shutdown() callbacks from the |
| 169 | 169 | irqchip. |
| 170 | + | |
| 171 | + | |
| 172 | +Requesting self-owned GPIO pins | |
| 173 | +------------------------------- | |
| 174 | + | |
| 175 | +Sometimes it is useful to allow a GPIO chip driver to request its own GPIO | |
| 176 | +descriptors through the gpiolib API. Using gpio_request() for this purpose | |
| 177 | +does not help since it pins the module to the kernel forever (it calls | |
| 178 | +try_module_get()). A GPIO driver can use the following functions instead | |
| 179 | +to request and free descriptors without being pinned to the kernel forever. | |
| 180 | + | |
| 181 | + int gpiochip_request_own_desc(struct gpio_desc *desc, const char *label) | |
| 182 | + | |
| 183 | + void gpiochip_free_own_desc(struct gpio_desc *desc) | |
| 184 | + | |
| 185 | +Descriptors requested with gpiochip_request_own_desc() must be released with | |
| 186 | +gpiochip_free_own_desc(). | |
| 187 | + | |
| 188 | +These functions must be used with care since they do not affect module use | |
| 189 | +count. Do not use the functions to request gpio descriptors not owned by the | |
| 190 | +calling driver. | |
| @@ -1,28 +1,13 @@ | ||
| 1 | 1 | UHID - User-space I/O driver support for HID subsystem |
| 2 | 2 | ======================================================== |
| 3 | 3 | |
| 4 | −The HID subsystem needs two kinds of drivers. In this document we call them: | |
| 4 | +UHID allows user-space to implement HID transport drivers. Please see | |
| 5 | +hid-transport.txt for an introduction into HID transport drivers. This document | |
| 6 | +relies heavily on the definitions declared there. | |
| 5 | 7 | |
| 6 | − 1. The "HID I/O Driver" is the driver that performs raw data I/O to the | |
| 7 | − low-level device. Internally, they register an hid_ll_driver structure with | |
| 8 | − the HID core. They perform device setup, read raw data from the device and | |
| 9 | − push it into the HID subsystem and they provide a callback so the HID | |
| 10 | − subsystem can send data to the device. | |
| 11 | − | |
| 12 | − 2. The "HID Device Driver" is the driver that parses HID reports and reacts on | |
| 13 | − them. There are generic drivers like "generic-usb" and "generic-bluetooth" | |
| 14 | − which adhere to the HID specification and provide the standardizes features. | |
| 15 | − But there may be special drivers and quirks for each non-standard device out | |
| 16 | − there. Internally, they use the hid_driver structure. | |
| 17 | − | |
| 18 | −Historically, the USB stack was the first subsystem to provide an HID I/O | |
| 19 | −Driver. However, other standards like Bluetooth have adopted the HID specs and | |
| 20 | −may provide HID I/O Drivers, too. The UHID driver allows to implement HID I/O | |
| 21 | −Drivers in user-space and feed the data into the kernel HID-subsystem. | |
| 22 | − | |
| 23 | −This allows user-space to operate on the same level as USB-HID, Bluetooth-HID | |
| 24 | −and similar. It does not provide a way to write HID Device Drivers, though. Use | |
| 25 | −hidraw for this purpose. | |
| 8 | +With UHID, a user-space transport driver can create kernel hid-devices for each | |
| 9 | +device connected to the user-space controlled bus. The UHID API defines the I/O | |
| 10 | +events provided from the kernel to user-space and vice versa. | |
| 26 | 11 | |
| 27 | 12 | There is an example user-space application in ./samples/uhid/uhid-example.c |
| 28 | 13 | |
| @@ -42,8 +27,9 @@ by setting O_NONBLOCK. · 13 unmodified lines | ||
| 42 | 27 | struct uhid_event { |
| 43 | 28 | __u32 type; |
| 44 | 29 | union { |
| 45 | − struct uhid_create_req create; | |
| 46 | − struct uhid_data_req data; | |
| 30 | + struct uhid_create2_req create2; | |
| 31 | + struct uhid_output_req output; | |
| 32 | + struct uhid_input2_req input2; | |
| 47 | 33 | ... |
| 48 | 34 | } u; |
| 49 | 35 | }; |
| @@ -54,8 +40,11 @@ multiple write()'s. A single event must always be sent as a whole. Furthermore, · 4 unmodified lines | ||
| 54 | 40 | only a single event can be sent per read() or write(). Pending data is ignored. |
| 55 | 41 | If you want to handle multiple events in a single syscall, then use vectored |
| 56 | 42 | I/O with readv()/writev(). |
| 43 | +The "type" field defines the payload. For each type, there is a | |
| 44 | +payload-structure available in the union "u" (except for empty payloads). This | |
| 45 | +payload contains management and/or device data. | |
| 57 | 46 | |
| 58 | −The first thing you should do is sending an UHID_CREATE event. This will | |
| 47 | +The first thing you should do is sending an UHID_CREATE2 event. This will | |
| 59 | 48 | register the device. UHID will respond with an UHID_START event. You can now |
| 60 | 49 | start sending data to and reading data from UHID. However, unless UHID sends the |
| 61 | 50 | UHID_OPEN event, the internally attached HID Device Driver has no user attached. |
| @@ -69,12 +58,20 @@ ref-counting for you. · 7 unmodified lines | ||
| 69 | 58 | You may decide to ignore UHID_OPEN/UHID_CLOSE, though. I/O is allowed even |
| 70 | 59 | though the device may have no users. |
| 71 | 60 | |
| 72 | −If you want to send data to the HID subsystem, you send an HID_INPUT event with | |
| 73 | −your raw data payload. If the kernel wants to send data to the device, you will | |
| 74 | −read an UHID_OUTPUT or UHID_OUTPUT_EV event. | |
| 61 | +If you want to send data on the interrupt channel to the HID subsystem, you send | |
| 62 | +an HID_INPUT2 event with your raw data payload. If the kernel wants to send data | |
| 63 | +on the interrupt channel to the device, you will read an UHID_OUTPUT event. | |
| 64 | +Data requests on the control channel are currently limited to GET_REPORT and | |
| 65 | +SET_REPORT (no other data reports on the control channel are defined so far). | |
| 66 | +Those requests are always synchronous. That means, the kernel sends | |
| 67 | +UHID_GET_REPORT and UHID_SET_REPORT events and requires you to forward them to | |
| 68 | +the device on the control channel. Once the device responds, you must forward | |
| 69 | +the response via UHID_GET_REPORT_REPLY and UHID_SET_REPORT_REPLY to the kernel. | |
| 70 | +The kernel blocks internal driver-execution during such round-trips (times out | |
| 71 | +after a hard-coded period). | |
| 75 | 72 | |
| 76 | 73 | If your device disconnects, you should send an UHID_DESTROY event. This will |
| 77 | −unregister the device. You can now send UHID_CREATE again to register a new | |
| 74 | +unregister the device. You can now send UHID_CREATE2 again to register a new | |
| 78 | 75 | device. |
| 79 | 76 | If you close() the fd, the device is automatically unregistered and destroyed |
| 80 | 77 | internally. |
| @@ -82,73 +79,79 @@ internally. · 1 unmodified line | ||
| 82 | 79 | write() |
| 83 | 80 | ------- |
| 84 | 81 | write() allows you to modify the state of the device and feed input data into |
| 85 | −the kernel. The following types are supported: UHID_CREATE, UHID_DESTROY and | |
| 86 | −UHID_INPUT. The kernel will parse the event immediately and if the event ID is | |
| 82 | +the kernel. The kernel will parse the event immediately and if the event ID is | |
| 87 | 83 | not supported, it will return -EOPNOTSUPP. If the payload is invalid, then |
| 88 | 84 | -EINVAL is returned, otherwise, the amount of data that was read is returned and |
| 89 | −the request was handled successfully. | |
| 85 | +the request was handled successfully. O_NONBLOCK does not affect write() as | |
| 86 | +writes are always handled immediately in a non-blocking fashion. Future requests | |
| 87 | +might make use of O_NONBLOCK, though. | |
| 90 | 88 | |
| 91 | − UHID_CREATE: | |
| 89 | + UHID_CREATE2: | |
| 92 | 90 | This creates the internal HID device. No I/O is possible until you send this |
| 93 | − event to the kernel. The payload is of type struct uhid_create_req and | |
| 91 | + event to the kernel. The payload is of type struct uhid_create2_req and | |
| 94 | 92 | contains information about your device. You can start I/O now. |
| 95 | 93 | |
| 96 | − UHID_CREATE2: | |
| 97 | − Same as UHID_CREATE, but the HID report descriptor data (rd_data) is an array | |
| 98 | − inside struct uhid_create2_req, instead of a pointer to a separate array. | |
| 99 | − Enables use from languages that don't support pointers, e.g. Python. | |
| 100 | − | |
| 101 | 94 | UHID_DESTROY: |
| 102 | 95 | This destroys the internal HID device. No further I/O will be accepted. There |
| 103 | 96 | may still be pending messages that you can receive with read() but no further |
| 104 | 97 | UHID_INPUT events can be sent to the kernel. |
| 105 | − You can create a new device by sending UHID_CREATE again. There is no need to | |
| 98 | + You can create a new device by sending UHID_CREATE2 again. There is no need to | |
| 106 | 99 | reopen the character device. |
| 107 | 100 | |
| 108 | − UHID_INPUT: | |
| 109 | − You must send UHID_CREATE before sending input to the kernel! This event | |
| 110 | − contains a data-payload. This is the raw data that you read from your device. | |
| 111 | − The kernel will parse the HID reports and react on it. | |
| 112 | − | |
| 113 | 101 | UHID_INPUT2: |
| 114 | − Same as UHID_INPUT, but the data array is the last field of uhid_input2_req. | |
| 115 | − Enables userspace to write only the required bytes to kernel (ev.type + | |
| 116 | − ev.u.input2.size + the part of the data array that matters), instead of | |
| 117 | − the entire struct uhid_input2_req. | |
| 118 | − | |
| 119 | − UHID_FEATURE_ANSWER: | |
| 120 | − If you receive a UHID_FEATURE request you must answer with this request. You | |
| 121 | − must copy the "id" field from the request into the answer. Set the "err" field | |
| 122 | − to 0 if no error occurred or to EIO if an I/O error occurred. | |
| 102 | + You must send UHID_CREATE2 before sending input to the kernel! This event | |
| 103 | + contains a data-payload. This is the raw data that you read from your device | |
| 104 | + on the interrupt channel. The kernel will parse the HID reports. | |
| 105 | + | |
| 106 | + UHID_GET_REPORT_REPLY: | |
| 107 | + If you receive a UHID_GET_REPORT request you must answer with this request. | |
| 108 | + You must copy the "id" field from the request into the answer. Set the "err" | |
| 109 | + field to 0 if no error occurred or to EIO if an I/O error occurred. | |
| 123 | 110 | If "err" is 0 then you should fill the buffer of the answer with the results |
| 124 | − of the feature request and set "size" correspondingly. | |
| 111 | + of the GET_REPORT request and set "size" correspondingly. | |
| 112 | + | |
| 113 | + UHID_SET_REPORT_REPLY: | |
| 114 | + This is the SET_REPORT equivalent of UHID_GET_REPORT_REPLY. Unlike GET_REPORT, | |
| 115 | + SET_REPORT never returns a data buffer, therefore, it's sufficient to set the | |
| 116 | + "id" and "err" fields correctly. | |
| 125 | 117 | |
| 126 | 118 | read() |
| 127 | 119 | ------ |
| 128 | −read() will return a queued output report. These output reports can be of type | |
| 129 | −UHID_START, UHID_STOP, UHID_OPEN, UHID_CLOSE, UHID_OUTPUT or UHID_OUTPUT_EV. No | |
| 130 | −reaction is required to any of them but you should handle them according to your | |
| 131 | −needs. Only UHID_OUTPUT and UHID_OUTPUT_EV have payloads. | |
| 120 | +read() will return a queued output report. No reaction is required to any of | |
| 121 | +them but you should handle them according to your needs. | |
| 132 | 122 | |
| 133 | 123 | UHID_START: |
| 134 | 124 | This is sent when the HID device is started. Consider this as an answer to |
| 135 | − UHID_CREATE. This is always the first event that is sent. | |
| 125 | + UHID_CREATE2. This is always the first event that is sent. Note that this | |
| 126 | + event might not be available immediately after write(UHID_CREATE2) returns. | |
| 127 | + Device drivers might required delayed setups. | |
| 128 | + This event contains a payload of type uhid_start_req. The "dev_flags" field | |
| 129 | + describes special behaviors of a device. The following flags are defined: | |
| 130 | + UHID_DEV_NUMBERED_FEATURE_REPORTS: | |
| 131 | + UHID_DEV_NUMBERED_OUTPUT_REPORTS: | |
| 132 | + UHID_DEV_NUMBERED_INPUT_REPORTS: | |
| 133 | + Each of these flags defines whether a given report-type uses numbered | |
| 134 | + reports. If numbered reports are used for a type, all messages from | |
| 135 | + the kernel already have the report-number as prefix. Otherwise, no | |
| 136 | + prefix is added by the kernel. | |
| 137 | + For messages sent by user-space to the kernel, you must adjust the | |
| 138 | + prefixes according to these flags. | |
| 136 | 139 | |
| 137 | 140 | UHID_STOP: |
| 138 | 141 | This is sent when the HID device is stopped. Consider this as an answer to |
| 139 | 142 | UHID_DESTROY. |
| 140 | − If the kernel HID device driver closes the device manually (that is, you | |
| 141 | − didn't send UHID_DESTROY) then you should consider this device closed and send | |
| 142 | − an UHID_DESTROY event. You may want to reregister your device, though. This is | |
| 143 | − always the last message that is sent to you unless you reopen the device with | |
| 144 | − UHID_CREATE. | |
| 143 | + If you didn't destroy your device via UHID_DESTROY, but the kernel sends an | |
| 144 | + UHID_STOP event, this should usually be ignored. It means that the kernel | |
| 145 | + reloaded/changed the device driver loaded on your HID device (or some other | |
| 146 | + maintenance actions happened). | |
| 147 | + You can usually ignored any UHID_STOP events safely. | |
| 145 | 148 | |
| 146 | 149 | UHID_OPEN: |
| 147 | 150 | This is sent when the HID device is opened. That is, the data that the HID |
| 148 | 151 | device provides is read by some other process. You may ignore this event but |
| 149 | 152 | it is useful for power-management. As long as you haven't received this event |
| 150 | 153 | there is actually no other process that reads your data so there is no need to |
| 151 | − send UHID_INPUT events to the kernel. | |
| 154 | + send UHID_INPUT2 events to the kernel. | |
| 152 | 155 | |
| 153 | 156 | UHID_CLOSE: |
| 154 | 157 | This is sent when there are no more processes which read the HID data. It is |
| @@ -156,27 +159,29 @@ needs. Only UHID_OUTPUT and UHID_OUTPUT_EV have payloads. · 1 unmodified line | ||
| 156 | 159 | |
| 157 | 160 | UHID_OUTPUT: |
| 158 | 161 | This is sent if the HID device driver wants to send raw data to the I/O |
| 159 | − device. You should read the payload and forward it to the device. The payload | |
| 160 | − is of type "struct uhid_data_req". | |
| 162 | + device on the interrupt channel. You should read the payload and forward it to | |
| 163 | + the device. The payload is of type "struct uhid_data_req". | |
| 161 | 164 | This may be received even though you haven't received UHID_OPEN, yet. |
| 162 | 165 | |
| 163 | − UHID_OUTPUT_EV (obsolete): | |
| 164 | − Same as UHID_OUTPUT but this contains a "struct input_event" as payload. This | |
| 165 | − is called for force-feedback, LED or similar events which are received through | |
| 166 | − an input device by the HID subsystem. You should convert this into raw reports | |
| 167 | − and send them to your device similar to events of type UHID_OUTPUT. | |
| 168 | − This is no longer sent by newer kernels. Instead, HID core converts it into a | |
| 169 | − raw output report and sends it via UHID_OUTPUT. | |
| 170 | − | |
| 171 | − UHID_FEATURE: | |
| 172 | − This event is sent if the kernel driver wants to perform a feature request as | |
| 173 | − described in the HID specs. The report-type and report-number are available in | |
| 174 | − the payload. | |
| 175 | − The kernel serializes feature requests so there will never be two in parallel. | |
| 176 | − However, if you fail to respond with a UHID_FEATURE_ANSWER in a time-span of 5 | |
| 177 | − seconds, then the requests will be dropped and a new one might be sent. | |
| 178 | − Therefore, the payload also contains an "id" field that identifies every | |
| 179 | − request. | |
| 180 | − | |
| 181 | −Document by: | |
| 182 | − David Herrmann <dh.herrmann@googlemail.com> | |
| 166 | + UHID_GET_REPORT: | |
| 167 | + This event is sent if the kernel driver wants to perform a GET_REPORT request | |
| 168 | + on the control channeld as described in the HID specs. The report-type and | |
| 169 | + report-number are available in the payload. | |
| 170 | + The kernel serializes GET_REPORT requests so there will never be two in | |
| 171 | + parallel. However, if you fail to respond with a UHID_GET_REPORT_REPLY, the | |
| 172 | + request might silently time out. | |
| 173 | + Once you read a GET_REPORT request, you shall forward it to the hid device and | |
| 174 | + remember the "id" field in the payload. Once your hid device responds to the | |
| 175 | + GET_REPORT (or if it fails), you must send a UHID_GET_REPORT_REPLY to the | |
| 176 | + kernel with the exact same "id" as in the request. If the request already | |
| 177 | + timed out, the kernel will ignore the response silently. The "id" field is | |
| 178 | + never re-used, so conflicts cannot happen. | |
| 179 | + | |
| 180 | + UHID_SET_REPORT: | |
| 181 | + This is the SET_REPORT equivalent of UHID_GET_REPORT. On receipt, you shall | |
| 182 | + send a SET_REPORT request to your hid device. Once it replies, you must tell | |
| 183 | + the kernel about it via UHID_SET_REPORT_REPLY. | |
| 184 | + The same restrictions as for UHID_GET_REPORT apply. | |
| 185 | + | |
| 186 | +---------------------------------------------------- | |
| 187 | +Written 2012, David Herrmann <dh.herrmann@gmail.com> | |
| @@ -25,6 +25,7 @@ Supported adapters: · 24 unmodified lines | ||
| 25 | 25 | * Intel Avoton (SOC) |
| 26 | 26 | * Intel Wellsburg (PCH) |
| 27 | 27 | * Intel Coleto Creek (PCH) |
| 28 | + * Intel Wildcat Point (PCH) | |
| 28 | 29 | * Intel Wildcat Point-LP (PCH) |
| 29 | 30 | * Intel BayTrail (SOC) |
| 30 | 31 | Datasheets: Publicly available at the Intel website |
| @@ -2,9 +2,9 @@ MODULE: i2c-stub · 1 unmodified line | ||
| 2 | 2 | |
| 3 | 3 | DESCRIPTION: |
| 4 | 4 | |
| 5 | −This module is a very simple fake I2C/SMBus driver. It implements five | |
| 5 | +This module is a very simple fake I2C/SMBus driver. It implements six | |
| 6 | 6 | types of SMBus commands: write quick, (r/w) byte, (r/w) byte data, (r/w) |
| 7 | −word data, and (r/w) I2C block data. | |
| 7 | +word data, (r/w) I2C block data, and (r/w) SMBus block data. | |
| 8 | 8 | |
| 9 | 9 | You need to provide chip addresses as a module parameter when loading this |
| 10 | 10 | driver, which will then only react to SMBus commands to these addresses. |
| @@ -19,6 +19,14 @@ A pointer register with auto-increment is implemented for all byte · 8 unmodified lines | ||
| 19 | 19 | operations. This allows for continuous byte reads like those supported by |
| 20 | 20 | EEPROMs, among others. |
| 21 | 21 | |
| 22 | +SMBus block command support is disabled by default, and must be enabled | |
| 23 | +explicitly by setting the respective bits (0x03000000) in the functionality | |
| 24 | +module parameter. | |
| 25 | + | |
| 26 | +SMBus block commands must be written to configure an SMBus command for | |
| 27 | +SMBus block operations. Writes can be partial. Block read commands always | |
| 28 | +return the number of bytes selected with the largest write so far. | |
| 29 | + | |
| 22 | 30 | The typical use-case is like this: |
| 23 | 31 | 1. load this module |
| 24 | 32 | 2. use i2cset (from the i2c-tools project) to pre-load some data |
| @@ -39,15 +47,18 @@ unsigned long functionality: · 14 unmodified lines | ||
| 39 | 47 | value 0x1f0000 would only enable the quick, byte and byte data |
| 40 | 48 | commands. |
| 41 | 49 | |
| 50 | +u8 bank_reg[10] | |
| 51 | +u8 bank_mask[10] | |
| 52 | +u8 bank_start[10] | |
| 53 | +u8 bank_end[10]: | |
| 54 | + Optional bank settings. They tell which bits in which register | |
| 55 | + select the active bank, as well as the range of banked registers. | |
| 56 | + | |
| 42 | 57 | CAVEATS: |
| 43 | 58 | |
| 44 | 59 | If your target driver polls some byte or word waiting for it to change, the |
| 45 | 60 | stub could lock it up. Use i2cset to unlock it. |
| 46 | 61 | |
| 47 | −If the hardware for your driver has banked registers (e.g. Winbond sensors | |
| 48 | −chips) this module will not work well - although it could be extended to | |
| 49 | −support that pretty easily. | |
| 50 | − | |
| 51 | 62 | If you spam it hard enough, printk can be lossy. This module really wants |
| 52 | 63 | something like relayfs. |
| 53 | 64 | |
| @@ -26,6 +26,11 @@ Creating MAD agents · 25 unmodified lines | ||
| 26 | 26 | ioctl. Also, all agents registered through a file descriptor will |
| 27 | 27 | be unregistered when the descriptor is closed. |
| 28 | 28 | |
| 29 | + 2014 -- a new registration ioctl is now provided which allows additional | |
| 30 | + fields to be provided during registration. | |
| 31 | + Users of this registration call are implicitly setting the use of | |
| 32 | + pkey_index (see below). | |
| 33 | + | |
| 29 | 34 | Receiving MADs |
| 30 | 35 | |
| 31 | 36 | MADs are received using read(). The receive side now supports |
| @@ -104,10 +109,10 @@ P_Key Index Handling · 72 unmodified lines | ||
| 104 | 109 | The old ib_umad interface did not allow setting the P_Key index for |
| 105 | 110 | MADs that are sent and did not provide a way for obtaining the P_Key |
| 106 | 111 | index of received MADs. A new layout for struct ib_user_mad_hdr |
| 107 | − with a pkey_index member has been defined; however, to preserve | |
| 108 | − binary compatibility with older applications, this new layout will | |
| 109 | − not be used unless the IB_USER_MAD_ENABLE_PKEY ioctl is called | |
| 110 | − before a file descriptor is used for anything else. | |
| 112 | + with a pkey_index member has been defined; however, to preserve binary | |
| 113 | + compatibility with older applications, this new layout will not be used | |
| 114 | + unless one of IB_USER_MAD_ENABLE_PKEY or IB_USER_MAD_REGISTER_AGENT2 ioctl's | |
| 115 | + are called before a file descriptor is used for anything else. | |
| 111 | 116 | |
| 112 | 117 | In September 2008, the IB_USER_MAD_ABI_VERSION will be incremented |
| 113 | 118 | to 6, the new layout of struct ib_user_mad_hdr will be used by |
| @@ -1,5 +1,7 @@ | ||
| 1 | 1 | 00-INDEX |
| 2 | 2 | - this file |
| 3 | +botching-up-ioctls.txt | |
| 4 | + - how to avoid botching up ioctls | |
| 3 | 5 | cdrom.txt |
| 4 | 6 | - summary of CDROM ioctl calls |
| 5 | 7 | hdio.txt |
| @@ -0,0 +1,219 @@ | ||
| 1 | +(How to avoid) Botching up ioctls | |
| 2 | +================================= | |
| 3 | + | |
| 4 | +From: http://blog.ffwll.ch/2013/11/botching-up-ioctls.html | |
| 5 | + | |
| 6 | +By: Daniel Vetter, Copyright © 2013 Intel Corporation | |
| 7 | + | |
| 8 | +One clear insight kernel graphics hackers gained in the past few years is that | |
| 9 | +trying to come up with a unified interface to manage the execution units and | |
| 10 | +memory on completely different GPUs is a futile effort. So nowadays every | |
| 11 | +driver has its own set of ioctls to allocate memory and submit work to the GPU. | |
| 12 | +Which is nice, since there's no more insanity in the form of fake-generic, but | |
| 13 | +actually only used once interfaces. But the clear downside is that there's much | |
| 14 | +more potential to screw things up. | |
| 15 | + | |
| 16 | +To avoid repeating all the same mistakes again I've written up some of the | |
| 17 | +lessons learned while botching the job for the drm/i915 driver. Most of these | |
| 18 | +only cover technicalities and not the big-picture issues like what the command | |
| 19 | +submission ioctl exactly should look like. Learning these lessons is probably | |
| 20 | +something every GPU driver has to do on its own. | |
| 21 | + | |
| 22 | + | |
| 23 | +Prerequisites | |
| 24 | +------------- | |
| 25 | + | |
| 26 | +First the prerequisites. Without these you have already failed, because you | |
| 27 | +will need to add a a 32-bit compat layer: | |
| 28 | + | |
| 29 | + * Only use fixed sized integers. To avoid conflicts with typedefs in userspace | |
| 30 | + the kernel has special types like __u32, __s64. Use them. | |
| 31 | + | |
| 32 | + * Align everything to the natural size and use explicit padding. 32-bit | |
| 33 | + platforms don't necessarily align 64-bit values to 64-bit boundaries, but | |
| 34 | + 64-bit platforms do. So we always need padding to the natural size to get | |
| 35 | + this right. | |
| 36 | + | |
| 37 | + * Pad the entire struct to a multiple of 64-bits - the structure size will | |
| 38 | + otherwise differ on 32-bit versus 64-bit. Having a different structure size | |
| 39 | + hurts when passing arrays of structures to the kernel, or if the kernel | |
| 40 | + checks the structure size, which e.g. the drm core does. | |
| 41 | + | |
| 42 | + * Pointers are __u64, cast from/to a uintprt_t on the userspace side and | |
| 43 | + from/to a void __user * in the kernel. Try really hard not to delay this | |
| 44 | + conversion or worse, fiddle the raw __u64 through your code since that | |
| 45 | + diminishes the checking tools like sparse can provide. | |
| 46 | + | |
| 47 | + | |
| 48 | +Basics | |
| 49 | +------ | |
| 50 | + | |
| 51 | +With the joys of writing a compat layer avoided we can take a look at the basic | |
| 52 | +fumbles. Neglecting these will make backward and forward compatibility a real | |
| 53 | +pain. And since getting things wrong on the first attempt is guaranteed you | |
| 54 | +will have a second iteration or at least an extension for any given interface. | |
| 55 | + | |
| 56 | + * Have a clear way for userspace to figure out whether your new ioctl or ioctl | |
| 57 | + extension is supported on a given kernel. If you can't rely on old kernels | |
| 58 | + rejecting the new flags/modes or ioctls (since doing that was botched in the | |
| 59 | + past) then you need a driver feature flag or revision number somewhere. | |
| 60 | + | |
| 61 | + * Have a plan for extending ioctls with new flags or new fields at the end of | |
| 62 | + the structure. The drm core checks the passed-in size for each ioctl call | |
| 63 | + and zero-extends any mismatches between kernel and userspace. That helps, | |
| 64 | + but isn't a complete solution since newer userspace on older kernels won't | |
| 65 | + notice that the newly added fields at the end get ignored. So this still | |
| 66 | + needs a new driver feature flags. | |
| 67 | + | |
| 68 | + * Check all unused fields and flags and all the padding for whether it's 0, | |
| 69 | + and reject the ioctl if that's not the case. Otherwise your nice plan for | |
| 70 | + future extensions is going right down the gutters since someone will submit | |
| 71 | + an ioctl struct with random stack garbage in the yet unused parts. Which | |
| 72 | + then bakes in the ABI that those fields can never be used for anything else | |
| 73 | + but garbage. | |
| 74 | + | |
| 75 | + * Have simple testcases for all of the above. | |
| 76 | + | |
| 77 | + | |
| 78 | +Fun with Error Paths | |
| 79 | +-------------------- | |
| 80 | + | |
| 81 | +Nowadays we don't have any excuse left any more for drm drivers being neat | |
| 82 | +little root exploits. This means we both need full input validation and solid | |
| 83 | +error handling paths - GPUs will die eventually in the oddmost corner cases | |
| 84 | +anyway: | |
| 85 | + | |
| 86 | + * The ioctl must check for array overflows. Also it needs to check for | |
| 87 | + over/underflows and clamping issues of integer values in general. The usual | |
| 88 | + example is sprite positioning values fed directly into the hardware with the | |
| 89 | + hardware just having 12 bits or so. Works nicely until some odd display | |
| 90 | + server doesn't bother with clamping itself and the cursor wraps around the | |
| 91 | + screen. | |
| 92 | + | |
| 93 | + * Have simple testcases for every input validation failure case in your ioctl. | |
| 94 | + Check that the error code matches your expectations. And finally make sure | |
| 95 | + that you only test for one single error path in each subtest by submitting | |
| 96 | + otherwise perfectly valid data. Without this an earlier check might reject | |
| 97 | + the ioctl already and shadow the codepath you actually want to test, hiding | |
| 98 | + bugs and regressions. | |
| 99 | + | |
| 100 | + * Make all your ioctls restartable. First X really loves signals and second | |
| 101 | + this will allow you to test 90% of all error handling paths by just | |
| 102 | + interrupting your main test suite constantly with signals. Thanks to X's | |
| 103 | + love for signal you'll get an excellent base coverage of all your error | |
| 104 | + paths pretty much for free for graphics drivers. Also, be consistent with | |
| 105 | + how you handle ioctl restarting - e.g. drm has a tiny drmIoctl helper in its | |
| 106 | + userspace library. The i915 driver botched this with the set_tiling ioctl, | |
| 107 | + now we're stuck forever with some arcane semantics in both the kernel and | |
| 108 | + userspace. | |
| 109 | + | |
| 110 | + * If you can't make a given codepath restartable make a stuck task at least | |
| 111 | + killable. GPUs just die and your users won't like you more if you hang their | |
| 112 | + entire box (by means of an unkillable X process). If the state recovery is | |
| 113 | + still too tricky have a timeout or hangcheck safety net as a last-ditch | |
| 114 | + effort in case the hardware has gone bananas. | |
| 115 | + | |
| 116 | + * Have testcases for the really tricky corner cases in your error recovery code | |
| 117 | + - it's way too easy to create a deadlock between your hangcheck code and | |
| 118 | + waiters. | |
| 119 | + | |
| 120 | + | |
| 121 | +Time, Waiting and Missing it | |
| 122 | +---------------------------- | |
| 123 | + | |
| 124 | +GPUs do most everything asynchronously, so we have a need to time operations and | |
| 125 | +wait for oustanding ones. This is really tricky business; at the moment none of | |
| 126 | +the ioctls supported by the drm/i915 get this fully right, which means there's | |
| 127 | +still tons more lessons to learn here. | |
| 128 | + | |
| 129 | + * Use CLOCK_MONOTONIC as your reference time, always. It's what alsa, drm and | |
| 130 | + v4l use by default nowadays. But let userspace know which timestamps are | |
| 131 | + derived from different clock domains like your main system clock (provided | |
| 132 | + by the kernel) or some independent hardware counter somewhere else. Clocks | |
| 133 | + will mismatch if you look close enough, but if performance measuring tools | |
| 134 | + have this information they can at least compensate. If your userspace can | |
| 135 | + get at the raw values of some clocks (e.g. through in-command-stream | |
| 136 | + performance counter sampling instructions) consider exposing those also. | |
| 137 | + | |
| 138 | + * Use __s64 seconds plus __u64 nanoseconds to specify time. It's not the most | |
| 139 | + convenient time specification, but it's mostly the standard. | |
| 140 | + | |
| 141 | + * Check that input time values are normalized and reject them if not. Note | |
| 142 | + that the kernel native struct ktime has a signed integer for both seconds | |
| 143 | + and nanoseconds, so beware here. | |
| 144 | + | |
| 145 | + * For timeouts, use absolute times. If you're a good fellow and made your | |
| 146 | + ioctl restartable relative timeouts tend to be too coarse and can | |
| 147 | + indefinitely extend your wait time due to rounding on each restart. | |
| 148 | + Especially if your reference clock is something really slow like the display | |
| 149 | + frame counter. With a spec laywer hat on this isn't a bug since timeouts can | |
| 150 | + always be extended - but users will surely hate you if their neat animations | |
| 151 | + starts to stutter due to this. | |
| 152 | + | |
| 153 | + * Consider ditching any synchronous wait ioctls with timeouts and just deliver | |
| 154 | + an asynchronous event on a pollable file descriptor. It fits much better | |
| 155 | + into event driven applications' main loop. | |
| 156 | + | |
| 157 | + * Have testcases for corner-cases, especially whether the return values for | |
| 158 | + already-completed events, successful waits and timed-out waits are all sane | |
| 159 | + and suiting to your needs. | |
| 160 | + | |
| 161 | + | |
| 162 | +Leaking Resources, Not | |
| 163 | +---------------------- | |
| 164 | + | |
| 165 | +A full-blown drm driver essentially implements a little OS, but specialized to | |
| 166 | +the given GPU platforms. This means a driver needs to expose tons of handles | |
| 167 | +for different objects and other resources to userspace. Doing that right | |
| 168 | +entails its own little set of pitfalls: | |
| 169 | + | |
| 170 | + * Always attach the lifetime of your dynamically created resources to the | |
| 171 | + lifetime of a file descriptor. Consider using a 1:1 mapping if your resource | |
| 172 | + needs to be shared across processes - fd-passing over unix domain sockets | |
| 173 | + also simplifies lifetime management for userspace. | |
| 174 | + | |
| 175 | + * Always have O_CLOEXEC support. | |
| 176 | + | |
| 177 | + * Ensure that you have sufficient insulation between different clients. By | |
| 178 | + default pick a private per-fd namespace which forces any sharing to be done | |
| 179 | + explictly. Only go with a more global per-device namespace if the objects | |
| 180 | + are truly device-unique. One counterexample in the drm modeset interfaces is | |
| 181 | + that the per-device modeset objects like connectors share a namespace with | |
| 182 | + framebuffer objects, which mostly are not shared at all. A separate | |
| 183 | + namespace, private by default, for framebuffers would have been more | |
| 184 | + suitable. | |
| 185 | + | |
| 186 | + * Think about uniqueness requirements for userspace handles. E.g. for most drm | |
| 187 | + drivers it's a userspace bug to submit the same object twice in the same | |
| 188 | + command submission ioctl. But then if objects are shareable userspace needs | |
| 189 | + to know whether it has seen an imported object from a different process | |
| 190 | + already or not. I haven't tried this myself yet due to lack of a new class | |
| 191 | + of objects, but consider using inode numbers on your shared file descriptors | |
| 192 | + as unique identifiers - it's how real files are told apart, too. | |
| 193 | + Unfortunately this requires a full-blown virtual filesystem in the kernel. | |
| 194 | + | |
| 195 | + | |
| 196 | +Last, but not Least | |
| 197 | +------------------- | |
| 198 | + | |
| 199 | +Not every problem needs a new ioctl: | |
| 200 | + | |
| 201 | + * Think hard whether you really want a driver-private interface. Of course | |
| 202 | + it's much quicker to push a driver-private interface than engaging in | |
| 203 | + lengthy discussions for a more generic solution. And occasionally doing a | |
| 204 | + private interface to spearhead a new concept is what's required. But in the | |
| 205 | + end, once the generic interface comes around you'll end up maintainer two | |
| 206 | + interfaces. Indefinitely. | |
| 207 | + | |
| 208 | + * Consider other interfaces than ioctls. A sysfs attribute is much better for | |
| 209 | + per-device settings, or for child objects with fairly static lifetimes (like | |
| 210 | + output connectors in drm with all the detection override attributes). Or | |
| 211 | + maybe only your testsuite needs this interface, and then debugfs with its | |
| 212 | + disclaimer of not having a stable ABI would be better. | |
| 213 | + | |
| 214 | +Finally, the name of the game is to get it right on the first attempt, since if | |
| 215 | +your driver proves popular and your hardware platforms long-lived then you'll | |
| 216 | +be stuck with a given ioctl essentially forever. You can try to deprecate | |
| 217 | +horrible ioctls on newer iterations of your hardware, but generally it takes | |
| 218 | +years to accomplish this. And then again years until the last user able to | |
| 219 | +complain about regressions disappears, too. | |
| @@ -1,5 +1,7 @@ | ||
| 1 | 1 | 00-INDEX |
| 2 | 2 | - this file: info on the kernel build process |
| 3 | +headers_install.txt | |
| 4 | + - how to export Linux headers for use by userspace | |
| 3 | 5 | kbuild.txt |
| 4 | 6 | - developer information on kbuild |
| 5 | 7 | kconfig.txt |
File renamed without changes.
| @@ -23,11 +23,10 @@ This document describes the Linux kernel Makefiles. · 22 unmodified lines | ||
| 23 | 23 | === 4 Host Program support |
| 24 | 24 | --- 4.1 Simple Host Program |
| 25 | 25 | --- 4.2 Composite Host Programs |
| 26 | − --- 4.3 Defining shared libraries | |
| 27 | − --- 4.4 Using C++ for host programs | |
| 28 | − --- 4.5 Controlling compiler options for host programs | |
| 29 | − --- 4.6 When host programs are actually built | |
| 30 | − --- 4.7 Using hostprogs-$(CONFIG_FOO) | |
| 26 | + --- 4.3 Using C++ for host programs | |
| 27 | + --- 4.4 Controlling compiler options for host programs | |
| 28 | + --- 4.5 When host programs are actually built | |
| 29 | + --- 4.6 Using hostprogs-$(CONFIG_FOO) | |
| 31 | 30 | |
| 32 | 31 | === 5 Kbuild clean infrastructure |
| 33 | 32 | |
| @@ -643,29 +642,7 @@ Both possibilities are described in the following. · 609 unmodified lines | ||
| 643 | 642 | Finally, the two .o files are linked to the executable, lxdialog. |
| 644 | 643 | Note: The syntax <executable>-y is not permitted for host-programs. |
| 645 | 644 | |
| 646 | −--- 4.3 Defining shared libraries | |
| 647 | − | |
| 648 | − Objects with extension .so are considered shared libraries, and | |
| 649 | − will be compiled as position independent objects. | |
| 650 | − Kbuild provides support for shared libraries, but the usage | |
| 651 | − shall be restricted. | |
| 652 | − In the following example the libkconfig.so shared library is used | |
| 653 | − to link the executable conf. | |
| 654 | − | |
| 655 | − Example: | |
| 656 | − #scripts/kconfig/Makefile | |
| 657 | − hostprogs-y := conf | |
| 658 | − conf-objs := conf.o libkconfig.so | |
| 659 | − libkconfig-objs := expr.o type.o | |
| 660 | − | |
| 661 | − Shared libraries always require a corresponding -objs line, and | |
| 662 | − in the example above the shared library libkconfig is composed by | |
| 663 | − the two objects expr.o and type.o. | |
| 664 | − expr.o and type.o will be built as position independent code and | |
| 665 | − linked as a shared library libkconfig.so. C++ is not supported for | |
| 666 | − shared libraries. | |
| 667 | − | |
| 668 | −--- 4.4 Using C++ for host programs | |
| 645 | +--- 4.3 Using C++ for host programs | |
| 669 | 646 | |
| 670 | 647 | kbuild offers support for host programs written in C++. This was |
| 671 | 648 | introduced solely to support kconfig, and is not recommended |
| @@ -688,7 +665,7 @@ Both possibilities are described in the following. · 16 unmodified lines | ||
| 688 | 665 | qconf-cxxobjs := qconf.o |
| 689 | 666 | qconf-objs := check.o |
| 690 | 667 | |
| 691 | −--- 4.5 Controlling compiler options for host programs | |
| 668 | +--- 4.4 Controlling compiler options for host programs | |
| 692 | 669 | |
| 693 | 670 | When compiling host programs, it is possible to set specific flags. |
| 694 | 671 | The programs will always be compiled utilising $(HOSTCC) passed |
| @@ -716,7 +693,7 @@ Both possibilities are described in the following. · 21 unmodified lines | ||
| 716 | 693 | When linking qconf, it will be passed the extra option |
| 717 | 694 | "-L$(QTDIR)/lib". |
| 718 | 695 | |
| 719 | −--- 4.6 When host programs are actually built | |
| 696 | +--- 4.5 When host programs are actually built | |
| 720 | 697 | |
| 721 | 698 | Kbuild will only build host-programs when they are referenced |
| 722 | 699 | as a prerequisite. |
| @@ -747,7 +724,7 @@ Both possibilities are described in the following. · 24 unmodified lines | ||
| 747 | 724 | This will tell kbuild to build lxdialog even if not referenced in |
| 748 | 725 | any rule. |
| 749 | 726 | |
| 750 | −--- 4.7 Using hostprogs-$(CONFIG_FOO) | |
| 727 | +--- 4.6 Using hostprogs-$(CONFIG_FOO) | |
| 751 | 728 | |
| 752 | 729 | A typical pattern in a Kbuild file looks like this: |
| 753 | 730 | |
| @@ -571,6 +571,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted. · 570 unmodified lines | ||
| 571 | 571 | trust validation. |
| 572 | 572 | format: { id:<keyid> | builtin } |
| 573 | 573 | |
| 574 | + cca= [MIPS] Override the kernel pages' cache coherency | |
| 575 | + algorithm. Accepted values range from 0 to 7 | |
| 576 | + inclusive. See arch/mips/include/asm/pgtable-bits.h | |
| 577 | + for platform specific values (SB1, Loongson3 and | |
| 578 | + others). | |
| 579 | + | |
| 574 | 580 | ccw_timeout_log [S390] |
| 575 | 581 | See Documentation/s390/CommonIO for details. |
| 576 | 582 | |
| @@ -1716,8 +1722,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted. · 1139 unmodified lines | ||
| 1716 | 1722 | 7 (KERN_DEBUG) debug-level messages |
| 1717 | 1723 | |
| 1718 | 1724 | log_buf_len=n[KMG] Sets the size of the printk ring buffer, |
| 1719 | − in bytes. n must be a power of two. The default | |
| 1720 | − size is set in the kernel config file. | |
| 1725 | + in bytes. n must be a power of two and greater | |
| 1726 | + than the minimal size. The minimal size is defined | |
| 1727 | + by LOG_BUF_SHIFT kernel config parameter. There is | |
| 1728 | + also CONFIG_LOG_CPU_MAX_BUF_SHIFT config parameter | |
| 1729 | + that allows to increase the default size depending on | |
| 1730 | + the number of CPUs. See init/Kconfig for more details. | |
| 1721 | 1731 | |
| 1722 | 1732 | logo.nologo [FB] Disables display of the built-in Linux logo. |
| 1723 | 1733 | This may be used to provide more screen space for |
| @@ -2190,6 +2200,21 @@ bytes respectively. Such letter suffixes can also be entirely omitted. · 466 unmodified lines | ||
| 2190 | 2200 | and restore using xsave. The kernel will fallback to |
| 2191 | 2201 | enabling legacy floating-point and sse state. |
| 2192 | 2202 | |
| 2203 | + noxsaveopt [X86] Disables xsaveopt used in saving x86 extended | |
| 2204 | + register states. The kernel will fall back to use | |
| 2205 | + xsave to save the states. By using this parameter, | |
| 2206 | + performance of saving the states is degraded because | |
| 2207 | + xsave doesn't support modified optimization while | |
| 2208 | + xsaveopt supports it on xsaveopt enabled systems. | |
| 2209 | + | |
| 2210 | + noxsaves [X86] Disables xsaves and xrstors used in saving and | |
| 2211 | + restoring x86 extended register state in compacted | |
| 2212 | + form of xsave area. The kernel will fall back to use | |
| 2213 | + xsaveopt and xrstor to save and restore the states | |
| 2214 | + in standard form of xsave area. By using this | |
| 2215 | + parameter, xsave area per process might occupy more | |
| 2216 | + memory on xsaves enabled systems. | |
| 2217 | + | |
| 2193 | 2218 | eagerfpu= [X86] |
| 2194 | 2219 | on enable eager fpu restore |
| 2195 | 2220 | off disable eager fpu restore |
| @@ -3054,6 +3079,13 @@ bytes respectively. Such letter suffixes can also be entirely omitted. · 858 unmodified lines | ||
| 3054 | 3079 | |
| 3055 | 3080 | S [KNL] Run init in single mode |
| 3056 | 3081 | |
| 3082 | + s390_iommu= [HW,S390] | |
| 3083 | + Set s390 IOTLB flushing mode | |
| 3084 | + strict | |
| 3085 | + With strict flushing every unmap operation will result in | |
| 3086 | + an IOTLB flush. Default is lazy flushing before reuse, | |
| 3087 | + which is faster. | |
| 3088 | + | |
| 3057 | 3089 | sa1100ir [NET] |
| 3058 | 3090 | See drivers/net/irda/sa1100_ir.c. |
| 3059 | 3091 | |
| @@ -3728,6 +3760,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted. · 668 unmodified lines | ||
| 3728 | 3760 | Disables the ticketlock slowpath using Xen PV |
| 3729 | 3761 | optimizations. |
| 3730 | 3762 | |
| 3763 | + xen_nopv [X86] | |
| 3764 | + Disables the PV optimizations forcing the HVM guest to | |
| 3765 | + run as generic HVM guest with no PV drivers. | |
| 3766 | + | |
| 3731 | 3767 | xirc2ps_cs= [NET,PCMCIA] |
| 3732 | 3768 | Format: |
| 3733 | 3769 | <irq>,<irq_mask>,<io>,<full_duplex>,<do_sound>,<lockup_hack>[,<irq2>[,<irq3>[,<irq4>]]] |
| @@ -18,3 +18,5 @@ sonypi.txt · 17 unmodified lines | ||
| 18 | 18 | - info on Linux Sony Programmable I/O Device support. |
| 19 | 19 | thinkpad-acpi.txt |
| 20 | 20 | - information on the (IBM and Lenovo) ThinkPad ACPI Extras driver. |
| 21 | +toshiba_haps.txt | |
| 22 | + - information on the Toshiba HDD Active Protection Sensor driver. | |
| @@ -29,15 +29,12 @@ static const char app_name[] = "FREE FALL"; · 28 unmodified lines | ||
| 29 | 29 | |
| 30 | 30 | static int set_unload_heads_path(char *device) |
| 31 | 31 | { |
| 32 | − char devname[64]; | |
| 33 | − | |
| 34 | 32 | if (strlen(device) <= 5 || strncmp(device, "/dev/", 5) != 0) |
| 35 | 33 | return -EINVAL; |
| 36 | − strncpy(devname, device + 5, sizeof(devname) - 1); | |
| 37 | 34 | strncpy(device_path, device, sizeof(device_path) - 1); |
| 38 | 35 | |
| 39 | 36 | snprintf(unload_heads_path, sizeof(unload_heads_path) - 1, |
| 40 | − "/sys/block/%s/device/unload_heads", devname); | |
| 37 | + "/sys/block/%s/device/unload_heads", device+5); | |
| 41 | 38 | return 0; |
| 42 | 39 | } |
| 43 | 40 | |
| @@ -0,0 +1,76 @@ | ||
| 1 | +Kernel driver toshiba_haps | |
| 2 | +Toshiba HDD Active Protection Sensor | |
| 3 | +==================================== | |
| 4 | + | |
| 5 | +Author: Azael Avalos <coproscefalo@gmail.com> | |
| 6 | + | |
| 7 | + | |
| 8 | +0. Contents | |
| 9 | +----------- | |
| 10 | + | |
| 11 | +1. Description | |
| 12 | +2. Interface | |
| 13 | +3. Accelerometer axes | |
| 14 | +4. Supported devices | |
| 15 | +5. Usage | |
| 16 | + | |
| 17 | + | |
| 18 | +1. Description | |
| 19 | +-------------- | |
| 20 | + | |
| 21 | +This driver provides support for the accelerometer found in various Toshiba | |
| 22 | +laptops, being called "Toshiba HDD Protection - Shock Sensor" officialy, | |
| 23 | +and detects laptops automatically with this device. | |
| 24 | +On Windows, Toshiba provided software monitors this device and provides | |
| 25 | +automatic HDD protection (head unload) on sudden moves or harsh vibrations, | |
| 26 | +however, this driver only provides a notification via a sysfs file to let | |
| 27 | +userspace tools or daemons act accordingly, as well as providing a sysfs | |
| 28 | +file to set the desired protection level or sensor sensibility. | |
| 29 | + | |
| 30 | + | |
| 31 | +2. Interface | |
| 32 | +------------ | |
| 33 | + | |
| 34 | +This device comes with 3 methods: | |
| 35 | +_STA - Checks existence of the device, returning Zero if the device does not | |
| 36 | + exists or is not supported. | |
| 37 | +PTLV - Sets the desired protection level. | |
| 38 | +RSSS - Shuts down the HDD protection interface for a few seconds, | |
| 39 | + then restores normal operation. | |
| 40 | + | |
| 41 | +Note: | |
| 42 | +The presence of Solid State Drives (SSD) can make this driver to fail loading, | |
| 43 | +given the fact that such drives have no movable parts, and thus, not requiring | |
| 44 | +any "protection" as well as failing during the evaluation of the _STA method | |
| 45 | +found under this device. | |
| 46 | + | |
| 47 | + | |
| 48 | +3. Accelerometer axes | |
| 49 | +--------------------- | |
| 50 | + | |
| 51 | +This device does not report any axes, however, to query the sensor position | |
| 52 | +a couple HCI (Hardware Configuration Interface) calls (0x6D and 0xA6) are | |
| 53 | +provided to query such information, handled by the kernel module toshiba_acpi | |
| 54 | +since kernel version 3.15. | |
| 55 | + | |
| 56 | + | |
| 57 | +4. Supported devices | |
| 58 | +-------------------- | |
| 59 | + | |
| 60 | +This driver binds itself to the ACPI device TOS620A, and any Toshiba laptop | |
| 61 | +with this device is supported, given the fact that they have the presence of | |
| 62 | +conventional HDD and not only SSD, or a combination of both HDD and SSD. | |
| 63 | + | |
| 64 | + | |
| 65 | +5. Usage | |
| 66 | +-------- | |
| 67 | + | |
| 68 | +The sysfs files under /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS620A:00/ are: | |
| 69 | +protection_level - The protection_level is readable and writeable, and | |
| 70 | + provides a way to let userspace query the current protection | |
| 71 | + level, as well as set the desired protection level, the | |
| 72 | + available protection levels are: | |
| 73 | + 0 - Disabled | 1 - Low | 2 - Medium | 3 - High | |
| 74 | +reset_protection - The reset_protection entry is writeable only, being "1" | |
| 75 | + the only parameter it accepts, it is used to trigger | |
| 76 | + a reset of the protection interface. | |
| @@ -268,6 +268,8 @@ characters, each representing a particular tainted value. · 267 unmodified lines | ||
| 268 | 268 | 14: 'E' if an unsigned module has been loaded in a kernel supporting |
| 269 | 269 | module signature. |
| 270 | 270 | |
| 271 | + 15: 'L' if a soft lockup has previously occurred on the system. | |
| 272 | + | |
| 271 | 273 | The primary reason for the 'Tainted: ' string is to tell kernel |
| 272 | 274 | debuggers if this is a clean kernel or if anything unusual has |
| 273 | 275 | occurred. Tainting is permanent: even if an offending module is |
| @@ -17,8 +17,6 @@ firmware-assisted-dump.txt · 16 unmodified lines | ||
| 17 | 17 | - Documentation on the firmware assisted dump mechanism "fadump". |
| 18 | 18 | hvcs.txt |
| 19 | 19 | - IBM "Hypervisor Virtual Console Server" Installation Guide |
| 20 | −kvm_440.txt | |
| 21 | − - Various notes on the implementation of KVM for PowerPC 440. | |
| 22 | 20 | mpc52xx.txt |
| 23 | 21 | - Linux 2.6.x on MPC52xx family |
| 24 | 22 | pmu-ebb.txt |
| @@ -1,41 +0,0 @@ | ||
| 1 | −Hollis Blanchard <hollisb@us.ibm.com> | |
| 2 | −15 Apr 2008 | |
| 3 | − | |
| 4 | −Various notes on the implementation of KVM for PowerPC 440: | |
| 5 | − | |
| 6 | −To enforce isolation, host userspace, guest kernel, and guest userspace all | |
| 7 | −run at user privilege level. Only the host kernel runs in supervisor mode. | |
| 8 | −Executing privileged instructions in the guest traps into KVM (in the host | |
| 9 | −kernel), where we decode and emulate them. Through this technique, unmodified | |
| 10 | −440 Linux kernels can be run (slowly) as guests. Future performance work will | |
| 11 | −focus on reducing the overhead and frequency of these traps. | |
| 12 | − | |
| 13 | −The usual code flow is started from userspace invoking an "run" ioctl, which | |
| 14 | −causes KVM to switch into guest context. We use IVPR to hijack the host | |
| 15 | −interrupt vectors while running the guest, which allows us to direct all | |
| 16 | −interrupts to kvmppc_handle_interrupt(). At this point, we could either | |
| 17 | −- handle the interrupt completely (e.g. emulate "mtspr SPRG0"), or | |
| 18 | −- let the host interrupt handler run (e.g. when the decrementer fires), or | |
| 19 | −- return to host userspace (e.g. when the guest performs device MMIO) | |
| 20 | − | |
| 21 | −Address spaces: We take advantage of the fact that Linux doesn't use the AS=1 | |
| 22 | −address space (in host or guest), which gives us virtual address space to use | |
| 23 | −for guest mappings. While the guest is running, the host kernel remains mapped | |
| 24 | −in AS=0, but the guest can only use AS=1 mappings. | |
| 25 | − | |
| 26 | −TLB entries: The TLB entries covering the host linear mapping remain | |
| 27 | −present while running the guest. This reduces the overhead of lightweight | |
| 28 | −exits, which are handled by KVM running in the host kernel. We keep three | |
| 29 | −copies of the TLB: | |
| 30 | − - guest TLB: contents of the TLB as the guest sees it | |
| 31 | − - shadow TLB: the TLB that is actually in hardware while guest is running | |
| 32 | − - host TLB: to restore TLB state when context switching guest -> host | |
| 33 | −When a TLB miss occurs because a mapping was not present in the shadow TLB, | |
| 34 | −but was present in the guest TLB, KVM handles the fault without invoking the | |
| 35 | −guest. Large guest pages are backed by multiple 4KB shadow pages through this | |
| 36 | −mechanism. | |
| 37 | − | |
| 38 | −IO: MMIO and DCR accesses are emulated by userspace. We use virtio for network | |
| 39 | −and block IO, so those drivers must be enabled in the guest. It's possible | |
| 40 | −that some qemu device emulation (e.g. e1000 or rtl8139) may also work with | |
| 41 | −little effort. | |
| @@ -20,13 +20,26 @@ II. Known problems · 19 unmodified lines | ||
| 20 | 20 | |
| 21 | 21 | None. |
| 22 | 22 | |
| 23 | −III. To do | |
| 23 | +III. DMA Engine Support | |
| 24 | 24 | |
| 25 | − Add DMA data transfers (non-messaging). | |
| 26 | − Add inbound region (SRIO-to-PCIe) mapping. | |
| 25 | +Tsi721 mport driver supports DMA data transfers between local system memory and | |
| 26 | +remote RapidIO devices. This functionality is implemented according to SLAVE | |
| 27 | +mode API defined by common Linux kernel DMA Engine framework. | |
| 28 | + | |
| 29 | +Depending on system requirements RapidIO DMA operations can be included/excluded | |
| 30 | +by setting CONFIG_RAPIDIO_DMA_ENGINE option. Tsi721 miniport driver uses seven | |
| 31 | +out of eight available BDMA channels to support DMA data transfers. | |
| 32 | +One BDMA channel is reserved for generation of maintenance read/write requests. | |
| 33 | + | |
| 34 | +If Tsi721 mport driver have been built with RAPIDIO_DMA_ENGINE support included, | |
| 35 | +this driver will accept DMA-specific module parameter: | |
| 36 | + "dma_desc_per_channel" - defines number of hardware buffer descriptors used by | |
| 37 | + each BDMA channel of Tsi721 (by default - 128). | |
| 27 | 38 | |
| 28 | 39 | IV. Version History |
| 29 | 40 | |
| 41 | + 1.1.0 - DMA operations re-worked to support data scatter/gather lists larger | |
| 42 | + than hardware buffer descriptors ring. | |
| 30 | 43 | 1.0.0 - Initial driver release. |
| 31 | 44 | |
| 32 | 45 | V. License |
| @@ -1095,7 +1095,7 @@ SCSI_NCR_SETUP_FORCE_SYNC_NEGO (default: not defined) · 1094 unmodified lines | ||
| 1095 | 1095 | SCSI_NCR_SETUP_MASTER_PARITY (default: defined) |
| 1096 | 1096 | If defined, master parity checking is enabled. |
| 1097 | 1097 | |
| 1098 | −SCSI_NCR_SETUP_MASTER_PARITY (default: defined) | |
| 1098 | +SCSI_NCR_SETUP_SCSI_PARITY (default: defined) | |
| 1099 | 1099 | If defined, SCSI parity checking is enabled. |
| 1100 | 1100 | |
| 1101 | 1101 | SCSI_NCR_PROFILE_SUPPORT (default: not defined) |
| @@ -22,7 +22,7 @@ system, building their checks on top of the defined capability hooks. · 21 unmodified lines | ||
| 22 | 22 | For more details on capabilities, see capabilities(7) in the Linux |
| 23 | 23 | man-pages project. |
| 24 | 24 | |
| 25 | −Based on http://kerneltrap.org/Linux/Documenting_Security_Module_Intent, | |
| 25 | +Based on https://lkml.org/lkml/2007/10/26/215, | |
| 26 | 26 | a new LSM is accepted into the kernel when its intent (a description of |
| 27 | 27 | what it tries to protect against and in what cases one would expect to |
| 28 | 28 | use it) has been appropriately documented in Documentation/security/. |
| @@ -826,6 +826,7 @@ can be ORed together: · 825 unmodified lines | ||
| 826 | 826 | 4096 - An out-of-tree module has been loaded. |
| 827 | 827 | 8192 - An unsigned module has been loaded in a kernel supporting module |
| 828 | 828 | signature. |
| 829 | +16384 - A soft lockup has previously occurred on the system. | |
| 829 | 830 | |
| 830 | 831 | ============================================================== |
| 831 | 832 | |
| @@ -2,26 +2,26 @@ this_cpu operations · 1 unmodified line | ||
| 2 | 2 | ------------------- |
| 3 | 3 | |
| 4 | 4 | this_cpu operations are a way of optimizing access to per cpu |
| 5 | −variables associated with the *currently* executing processor through | |
| 6 | −the use of segment registers (or a dedicated register where the cpu | |
| 7 | −permanently stored the beginning of the per cpu area for a specific | |
| 8 | −processor). | |
| 5 | +variables associated with the *currently* executing processor. This is | |
| 6 | +done through the use of segment registers (or a dedicated register where | |
| 7 | +the cpu permanently stored the beginning of the per cpu area for a | |
| 8 | +specific processor). | |
| 9 | 9 | |
| 10 | −The this_cpu operations add a per cpu variable offset to the processor | |
| 11 | −specific percpu base and encode that operation in the instruction | |
| 10 | +this_cpu operations add a per cpu variable offset to the processor | |
| 11 | +specific per cpu base and encode that operation in the instruction | |
| 12 | 12 | operating on the per cpu variable. |
| 13 | 13 | |
| 14 | −This means there are no atomicity issues between the calculation of | |
| 14 | +This means that there are no atomicity issues between the calculation of | |
| 15 | 15 | the offset and the operation on the data. Therefore it is not |
| 16 | −necessary to disable preempt or interrupts to ensure that the | |
| 16 | +necessary to disable preemption or interrupts to ensure that the | |
| 17 | 17 | processor is not changed between the calculation of the address and |
| 18 | 18 | the operation on the data. |
| 19 | 19 | |
| 20 | 20 | Read-modify-write operations are of particular interest. Frequently |
| 21 | 21 | processors have special lower latency instructions that can operate |
| 22 | −without the typical synchronization overhead but still provide some | |
| 23 | −sort of relaxed atomicity guarantee. The x86 for example can execute | |
| 24 | −RMV (Read Modify Write) instructions like inc/dec/cmpxchg without the | |
| 22 | +without the typical synchronization overhead, but still provide some | |
| 23 | +sort of relaxed atomicity guarantees. The x86, for example, can execute | |
| 24 | +RMW (Read Modify Write) instructions like inc/dec/cmpxchg without the | |
| 25 | 25 | lock prefix and the associated latency penalty. |
| 26 | 26 | |
| 27 | 27 | Access to the variable without the lock prefix is not synchronized but |
| @@ -30,6 +30,38 @@ data specific to the currently executing processor. Only the current · 2 unmodified lines | ||
| 30 | 30 | processor should be accessing that variable and therefore there are no |
| 31 | 31 | concurrency issues with other processors in the system. |
| 32 | 32 | |
| 33 | +Please note that accesses by remote processors to a per cpu area are | |
| 34 | +exceptional situations and may impact performance and/or correctness | |
| 35 | +(remote write operations) of local RMW operations via this_cpu_*. | |
| 36 | + | |
| 37 | +The main use of the this_cpu operations has been to optimize counter | |
| 38 | +operations. | |
| 39 | + | |
| 40 | +The following this_cpu() operations with implied preemption protection | |
| 41 | +are defined. These operations can be used without worrying about | |
| 42 | +preemption and interrupts. | |
| 43 | + | |
| 44 | + this_cpu_add() | |
| 45 | + this_cpu_read(pcp) | |
| 46 | + this_cpu_write(pcp, val) | |
| 47 | + this_cpu_add(pcp, val) | |
| 48 | + this_cpu_and(pcp, val) | |
| 49 | + this_cpu_or(pcp, val) | |
| 50 | + this_cpu_add_return(pcp, val) | |
| 51 | + this_cpu_xchg(pcp, nval) | |
| 52 | + this_cpu_cmpxchg(pcp, oval, nval) | |
| 53 | + this_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2) | |
| 54 | + this_cpu_sub(pcp, val) | |
| 55 | + this_cpu_inc(pcp) | |
| 56 | + this_cpu_dec(pcp) | |
| 57 | + this_cpu_sub_return(pcp, val) | |
| 58 | + this_cpu_inc_return(pcp) | |
| 59 | + this_cpu_dec_return(pcp) | |
| 60 | + | |
| 61 | + | |
| 62 | +Inner working of this_cpu operations | |
| 63 | +------------------------------------ | |
| 64 | + | |
| 33 | 65 | On x86 the fs: or the gs: segment registers contain the base of the |
| 34 | 66 | per cpu area. It is then possible to simply use the segment override |
| 35 | 67 | to relocate a per cpu relative address to the proper per cpu area for |
| @@ -48,22 +80,21 @@ results in a single instruction · 12 unmodified lines | ||
| 48 | 80 | mov ax, gs:[x] |
| 49 | 81 | |
| 50 | 82 | instead of a sequence of calculation of the address and then a fetch |
| 51 | −from that address which occurs with the percpu operations. Before | |
| 83 | +from that address which occurs with the per cpu operations. Before | |
| 52 | 84 | this_cpu_ops such sequence also required preempt disable/enable to |
| 53 | 85 | prevent the kernel from moving the thread to a different processor |
| 54 | 86 | while the calculation is performed. |
| 55 | 87 | |
| 56 | −The main use of the this_cpu operations has been to optimize counter | |
| 57 | −operations. | |
| 88 | +Consider the following this_cpu operation: | |
| 58 | 89 | |
| 59 | 90 | this_cpu_inc(x) |
| 60 | 91 | |
| 61 | −results in the following single instruction (no lock prefix!) | |
| 92 | +The above results in the following single instruction (no lock prefix!) | |
| 62 | 93 | |
| 63 | 94 | inc gs:[x] |
| 64 | 95 | |
| 65 | 96 | instead of the following operations required if there is no segment |
| 66 | −register. | |
| 97 | +register: | |
| 67 | 98 | |
| 68 | 99 | int *y; |
| 69 | 100 | int cpu; |
| @@ -73,10 +104,10 @@ register. · 3 unmodified lines | ||
| 73 | 104 | (*y)++; |
| 74 | 105 | put_cpu(); |
| 75 | 106 | |
| 76 | −Note that these operations can only be used on percpu data that is | |
| 107 | +Note that these operations can only be used on per cpu data that is | |
| 77 | 108 | reserved for a specific processor. Without disabling preemption in the |
| 78 | 109 | surrounding code this_cpu_inc() will only guarantee that one of the |
| 79 | −percpu counters is correctly incremented. However, there is no | |
| 110 | +per cpu counters is correctly incremented. However, there is no | |
| 80 | 111 | guarantee that the OS will not move the process directly before or |
| 81 | 112 | after the this_cpu instruction is executed. In general this means that |
| 82 | 113 | the value of the individual counters for each processor are |
| @@ -86,9 +117,9 @@ that is of interest. · 3 unmodified lines | ||
| 86 | 117 | Per cpu variables are used for performance reasons. Bouncing cache |
| 87 | 118 | lines can be avoided if multiple processors concurrently go through |
| 88 | 119 | the same code paths. Since each processor has its own per cpu |
| 89 | −variables no concurrent cacheline updates take place. The price that | |
| 120 | +variables no concurrent cache line updates take place. The price that | |
| 90 | 121 | has to be paid for this optimization is the need to add up the per cpu |
| 91 | −counters when the value of the counter is needed. | |
| 122 | +counters when the value of a counter is needed. | |
| 92 | 123 | |
| 93 | 124 | |
| 94 | 125 | Special operations: |
| @@ -100,33 +131,39 @@ Takes the offset of a per cpu variable (&x !) and returns the address · 5 unmodified lines | ||
| 100 | 131 | of the per cpu variable that belongs to the currently executing |
| 101 | 132 | processor. this_cpu_ptr avoids multiple steps that the common |
| 102 | 133 | get_cpu/put_cpu sequence requires. No processor number is |
| 103 | −available. Instead the offset of the local per cpu area is simply | |
| 104 | −added to the percpu offset. | |
| 134 | +available. Instead, the offset of the local per cpu area is simply | |
| 135 | +added to the per cpu offset. | |
| 105 | 136 | |
| 137 | +Note that this operation is usually used in a code segment when | |
| 138 | +preemption has been disabled. The pointer is then used to | |
| 139 | +access local per cpu data in a critical section. When preemption | |
| 140 | +is re-enabled this pointer is usually no longer useful since it may | |
| 141 | +no longer point to per cpu data of the current processor. | |
| 106 | 142 | |
| 107 | 143 | |
| 108 | 144 | Per cpu variables and offsets |
| 109 | 145 | ----------------------------- |
| 110 | 146 | |
| 111 | −Per cpu variables have *offsets* to the beginning of the percpu | |
| 147 | +Per cpu variables have *offsets* to the beginning of the per cpu | |
| 112 | 148 | area. They do not have addresses although they look like that in the |
| 113 | 149 | code. Offsets cannot be directly dereferenced. The offset must be |
| 114 | −added to a base pointer of a percpu area of a processor in order to | |
| 150 | +added to a base pointer of a per cpu area of a processor in order to | |
| 115 | 151 | form a valid address. |
| 116 | 152 | |
| 117 | 153 | Therefore the use of x or &x outside of the context of per cpu |
| 118 | 154 | operations is invalid and will generally be treated like a NULL |
| 119 | 155 | pointer dereference. |
| 120 | 156 | |
| 121 | −In the context of per cpu operations | |
| 157 | + DEFINE_PER_CPU(int, x); | |
| 122 | 158 | |
| 123 | − x is a per cpu variable. Most this_cpu operations take a cpu | |
| 124 | − variable. | |
| 159 | +In the context of per cpu operations the above implies that x is a per | |
| 160 | +cpu variable. Most this_cpu operations take a cpu variable. | |
| 125 | 161 | |
| 126 | − &x is the *offset* a per cpu variable. this_cpu_ptr() takes | |
| 127 | − the offset of a per cpu variable which makes this look a bit | |
| 128 | − strange. | |
| 162 | + int __percpu *p = &x; | |
| 129 | 163 | |
| 164 | +&x and hence p is the *offset* of a per cpu variable. this_cpu_ptr() | |
| 165 | +takes the offset of a per cpu variable which makes this look a bit | |
| 166 | +strange. | |
| 130 | 167 | |
| 131 | 168 | |
| 132 | 169 | Operations on a field of a per cpu structure |
| @@ -152,7 +189,7 @@ If we have an offset to struct s: · 19 unmodified lines | ||
| 152 | 189 | |
| 153 | 190 | struct s __percpu *ps = &p; |
| 154 | 191 | |
| 155 | − z = this_cpu_dec(ps->m); | |
| 192 | + this_cpu_dec(ps->m); | |
| 156 | 193 | |
| 157 | 194 | z = this_cpu_inc_return(ps->n); |
| 158 | 195 | |
| @@ -172,29 +209,52 @@ if we do not make use of this_cpu ops later to manipulate fields: · 13 unmodified lines | ||
| 172 | 209 | Variants of this_cpu ops |
| 173 | 210 | ------------------------- |
| 174 | 211 | |
| 175 | −this_cpu ops are interrupt safe. Some architecture do not support | |
| 212 | +this_cpu ops are interrupt safe. Some architectures do not support | |
| 176 | 213 | these per cpu local operations. In that case the operation must be |
| 177 | 214 | replaced by code that disables interrupts, then does the operations |
| 178 | −that are guaranteed to be atomic and then reenable interrupts. Doing | |
| 215 | +that are guaranteed to be atomic and then re-enable interrupts. Doing | |
| 179 | 216 | so is expensive. If there are other reasons why the scheduler cannot |
| 180 | 217 | change the processor we are executing on then there is no reason to |
| 181 | −disable interrupts. For that purpose the __this_cpu operations are | |
| 182 | −provided. For example. | |
| 183 | − | |
| 184 | − __this_cpu_inc(x); | |
| 185 | − | |
| 186 | −Will increment x and will not fallback to code that disables | |
| 218 | +disable interrupts. For that purpose the following __this_cpu operations | |
| 219 | +are provided. | |
| 220 | + | |
| 221 | +These operations have no guarantee against concurrent interrupts or | |
| 222 | +preemption. If a per cpu variable is not used in an interrupt context | |
| 223 | +and the scheduler cannot preempt, then they are safe. If any interrupts | |
| 224 | +still occur while an operation is in progress and if the interrupt too | |
| 225 | +modifies the variable, then RMW actions can not be guaranteed to be | |
| 226 | +safe. | |
| 227 | + | |
| 228 | + __this_cpu_add() | |
| 229 | + __this_cpu_read(pcp) | |
| 230 | + __this_cpu_write(pcp, val) | |
| 231 | + __this_cpu_add(pcp, val) | |
| 232 | + __this_cpu_and(pcp, val) | |
| 233 | + __this_cpu_or(pcp, val) | |
| 234 | + __this_cpu_add_return(pcp, val) | |
| 235 | + __this_cpu_xchg(pcp, nval) | |
| 236 | + __this_cpu_cmpxchg(pcp, oval, nval) | |
| 237 | + __this_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2) | |
| 238 | + __this_cpu_sub(pcp, val) | |
| 239 | + __this_cpu_inc(pcp) | |
| 240 | + __this_cpu_dec(pcp) | |
| 241 | + __this_cpu_sub_return(pcp, val) | |
| 242 | + __this_cpu_inc_return(pcp) | |
| 243 | + __this_cpu_dec_return(pcp) | |
| 244 | + | |
| 245 | + | |
| 246 | +Will increment x and will not fall-back to code that disables | |
| 187 | 247 | interrupts on platforms that cannot accomplish atomicity through |
| 188 | 248 | address relocation and a Read-Modify-Write operation in the same |
| 189 | 249 | instruction. |
| 190 | 250 | |
| 191 | 251 | |
| 192 | − | |
| 193 | 252 | &this_cpu_ptr(pp)->n vs this_cpu_ptr(&pp->n) |
| 194 | 253 | -------------------------------------------- |
| 195 | 254 | |
| 196 | 255 | The first operation takes the offset and forms an address and then |
| 197 | −adds the offset of the n field. | |
| 256 | +adds the offset of the n field. This may result in two add | |
| 257 | +instructions emitted by the compiler. | |
| 198 | 258 | |
| 199 | 259 | The second one first adds the two offsets and then does the |
| 200 | 260 | relocation. IMHO the second form looks cleaner and has an easier time |
| @@ -202,4 +262,73 @@ with (). The second form also is consistent with the way · 1 unmodified line | ||
| 202 | 262 | this_cpu_read() and friends are used. |
| 203 | 263 | |
| 204 | 264 | |
| 205 | −Christoph Lameter, April 3rd, 2013 | |
| 265 | +Remote access to per cpu data | |
| 266 | +------------------------------ | |
| 267 | + | |
| 268 | +Per cpu data structures are designed to be used by one cpu exclusively. | |
| 269 | +If you use the variables as intended, this_cpu_ops() are guaranteed to | |
| 270 | +be "atomic" as no other CPU has access to these data structures. | |
| 271 | + | |
| 272 | +There are special cases where you might need to access per cpu data | |
| 273 | +structures remotely. It is usually safe to do a remote read access | |
| 274 | +and that is frequently done to summarize counters. Remote write access | |
| 275 | +something which could be problematic because this_cpu ops do not | |
| 276 | +have lock semantics. A remote write may interfere with a this_cpu | |
| 277 | +RMW operation. | |
| 278 | + | |
| 279 | +Remote write accesses to percpu data structures are highly discouraged | |
| 280 | +unless absolutely necessary. Please consider using an IPI to wake up | |
| 281 | +the remote CPU and perform the update to its per cpu area. | |
| 282 | + | |
| 283 | +To access per-cpu data structure remotely, typically the per_cpu_ptr() | |
| 284 | +function is used: | |
| 285 | + | |
| 286 | + | |
| 287 | + DEFINE_PER_CPU(struct data, datap); | |
| 288 | + | |
| 289 | + struct data *p = per_cpu_ptr(&datap, cpu); | |
| 290 | + | |
| 291 | +This makes it explicit that we are getting ready to access a percpu | |
| 292 | +area remotely. | |
| 293 | + | |
| 294 | +You can also do the following to convert the datap offset to an address | |
| 295 | + | |
| 296 | + struct data *p = this_cpu_ptr(&datap); | |
| 297 | + | |
| 298 | +but, passing of pointers calculated via this_cpu_ptr to other cpus is | |
| 299 | +unusual and should be avoided. | |
| 300 | + | |
| 301 | +Remote access are typically only for reading the status of another cpus | |
| 302 | +per cpu data. Write accesses can cause unique problems due to the | |
| 303 | +relaxed synchronization requirements for this_cpu operations. | |
| 304 | + | |
| 305 | +One example that illustrates some concerns with write operations is | |
| 306 | +the following scenario that occurs because two per cpu variables | |
| 307 | +share a cache-line but the relaxed synchronization is applied to | |
| 308 | +only one process updating the cache-line. | |
| 309 | + | |
| 310 | +Consider the following example | |
| 311 | + | |
| 312 | + | |
| 313 | + struct test { | |
| 314 | + atomic_t a; | |
| 315 | + int b; | |
| 316 | + }; | |
| 317 | + | |
| 318 | + DEFINE_PER_CPU(struct test, onecacheline); | |
| 319 | + | |
| 320 | +There is some concern about what would happen if the field 'a' is updated | |
| 321 | +remotely from one processor and the local processor would use this_cpu ops | |
| 322 | +to update field b. Care should be taken that such simultaneous accesses to | |
| 323 | +data within the same cache line are avoided. Also costly synchronization | |
| 324 | +may be necessary. IPIs are generally recommended in such scenarios instead | |
| 325 | +of a remote write to the per cpu area of another processor. | |
| 326 | + | |
| 327 | +Even in cases where the remote writes are rare, please bear in | |
| 328 | +mind that a remote write will evict the cache line from the processor | |
| 329 | +that most likely will access it. If the processor wakes up and finds a | |
| 330 | +missing local cache line of a per cpu area, its performance and hence | |
| 331 | +the wake up times will be affected. | |
| 332 | + | |
| 333 | +Christoph Lameter, August 4th, 2014 | |
| 334 | +Pranith Kumar, Aug 2nd, 2014 | |
| @@ -47,6 +47,10 @@ use constant HIGH_KSWAPD_REWAKEUP => 21; · 46 unmodified lines | ||
| 47 | 47 | use constant HIGH_NR_SCANNED => 22; |
| 48 | 48 | use constant HIGH_NR_TAKEN => 23; |
| 49 | 49 | use constant HIGH_NR_RECLAIMED => 24; |
| 50 | +use constant HIGH_NR_FILE_SCANNED => 25; | |
| 51 | +use constant HIGH_NR_ANON_SCANNED => 26; | |
| 52 | +use constant HIGH_NR_FILE_RECLAIMED => 27; | |
| 53 | +use constant HIGH_NR_ANON_RECLAIMED => 28; | |
| 50 | 54 | |
| 51 | 55 | my %perprocesspid; |
| 52 | 56 | my %perprocess; |
| @@ -56,14 +60,18 @@ my $opt_read_procstat; · 3 unmodified lines | ||
| 56 | 60 | |
| 57 | 61 | my $total_wakeup_kswapd; |
| 58 | 62 | my ($total_direct_reclaim, $total_direct_nr_scanned); |
| 63 | +my ($total_direct_nr_file_scanned, $total_direct_nr_anon_scanned); | |
| 59 | 64 | my ($total_direct_latency, $total_kswapd_latency); |
| 60 | 65 | my ($total_direct_nr_reclaimed); |
| 66 | +my ($total_direct_nr_file_reclaimed, $total_direct_nr_anon_reclaimed); | |
| 61 | 67 | my ($total_direct_writepage_file_sync, $total_direct_writepage_file_async); |
| 62 | 68 | my ($total_direct_writepage_anon_sync, $total_direct_writepage_anon_async); |
| 63 | 69 | my ($total_kswapd_nr_scanned, $total_kswapd_wake); |
| 70 | +my ($total_kswapd_nr_file_scanned, $total_kswapd_nr_anon_scanned); | |
| 64 | 71 | my ($total_kswapd_writepage_file_sync, $total_kswapd_writepage_file_async); |
| 65 | 72 | my ($total_kswapd_writepage_anon_sync, $total_kswapd_writepage_anon_async); |
| 66 | 73 | my ($total_kswapd_nr_reclaimed); |
| 74 | +my ($total_kswapd_nr_file_reclaimed, $total_kswapd_nr_anon_reclaimed); | |
| 67 | 75 | |
| 68 | 76 | # Catch sigint and exit on request |
| 69 | 77 | my $sigint_report = 0; |
| @@ -374,6 +382,7 @@ EVENT_PROCESS: · 304 unmodified lines | ||
| 374 | 382 | } |
| 375 | 383 | my $isolate_mode = $1; |
| 376 | 384 | my $nr_scanned = $4; |
| 385 | + my $file = $6; | |
| 377 | 386 | |
| 378 | 387 | # To closer match vmstat scanning statistics, only count isolate_both |
| 379 | 388 | # and isolate_inactive as scanning. isolate_active is rotation |
| @@ -382,6 +391,11 @@ EVENT_PROCESS: · 2 unmodified lines | ||
| 382 | 391 | # isolate_both == 3 |
| 383 | 392 | if ($isolate_mode != 2) { |
| 384 | 393 | $perprocesspid{$process_pid}->{HIGH_NR_SCANNED} += $nr_scanned; |
| 394 | + if ($file == 1) { | |
| 395 | + $perprocesspid{$process_pid}->{HIGH_NR_FILE_SCANNED} += $nr_scanned; | |
| 396 | + } else { | |
| 397 | + $perprocesspid{$process_pid}->{HIGH_NR_ANON_SCANNED} += $nr_scanned; | |
| 398 | + } | |
| 385 | 399 | } |
| 386 | 400 | } elsif ($tracepoint eq "mm_vmscan_lru_shrink_inactive") { |
| 387 | 401 | $details = $6; |
| @@ -391,8 +405,19 @@ EVENT_PROCESS: · 3 unmodified lines | ||
| 391 | 405 | print " $regex_lru_shrink_inactive/o\n"; |
| 392 | 406 | next; |
| 393 | 407 | } |
| 408 | + | |
| 394 | 409 | my $nr_reclaimed = $4; |
| 410 | + my $flags = $6; | |
| 411 | + my $file = 0; | |
| 412 | + if ($flags =~ /RECLAIM_WB_FILE/) { | |
| 413 | + $file = 1; | |
| 414 | + } | |
| 395 | 415 | $perprocesspid{$process_pid}->{HIGH_NR_RECLAIMED} += $nr_reclaimed; |
| 416 | + if ($file) { | |
| 417 | + $perprocesspid{$process_pid}->{HIGH_NR_FILE_RECLAIMED} += $nr_reclaimed; | |
| 418 | + } else { | |
| 419 | + $perprocesspid{$process_pid}->{HIGH_NR_ANON_RECLAIMED} += $nr_reclaimed; | |
| 420 | + } | |
| 396 | 421 | } elsif ($tracepoint eq "mm_vmscan_writepage") { |
| 397 | 422 | $details = $6; |
| 398 | 423 | if ($details !~ /$regex_writepage/o) { |
| @@ -493,7 +518,11 @@ sub dump_stats { · 94 unmodified lines | ||
| 493 | 518 | $total_direct_reclaim += $stats{$process_pid}->{MM_VMSCAN_DIRECT_RECLAIM_BEGIN}; |
| 494 | 519 | $total_wakeup_kswapd += $stats{$process_pid}->{MM_VMSCAN_WAKEUP_KSWAPD}; |
| 495 | 520 | $total_direct_nr_scanned += $stats{$process_pid}->{HIGH_NR_SCANNED}; |
| 521 | + $total_direct_nr_file_scanned += $stats{$process_pid}->{HIGH_NR_FILE_SCANNED}; | |
| 522 | + $total_direct_nr_anon_scanned += $stats{$process_pid}->{HIGH_NR_ANON_SCANNED}; | |
| 496 | 523 | $total_direct_nr_reclaimed += $stats{$process_pid}->{HIGH_NR_RECLAIMED}; |
| 524 | + $total_direct_nr_file_reclaimed += $stats{$process_pid}->{HIGH_NR_FILE_RECLAIMED}; | |
| 525 | + $total_direct_nr_anon_reclaimed += $stats{$process_pid}->{HIGH_NR_ANON_RECLAIMED}; | |
| 497 | 526 | $total_direct_writepage_file_sync += $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_FILE_SYNC}; |
| 498 | 527 | $total_direct_writepage_anon_sync += $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_ANON_SYNC}; |
| 499 | 528 | $total_direct_writepage_file_async += $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_FILE_ASYNC}; |
| @@ -513,7 +542,11 @@ sub dump_stats { · 13 unmodified lines | ||
| 513 | 542 | $stats{$process_pid}->{MM_VMSCAN_DIRECT_RECLAIM_BEGIN}, |
| 514 | 543 | $stats{$process_pid}->{MM_VMSCAN_WAKEUP_KSWAPD}, |
| 515 | 544 | $stats{$process_pid}->{HIGH_NR_SCANNED}, |
| 545 | + $stats{$process_pid}->{HIGH_NR_FILE_SCANNED}, | |
| 546 | + $stats{$process_pid}->{HIGH_NR_ANON_SCANNED}, | |
| 516 | 547 | $stats{$process_pid}->{HIGH_NR_RECLAIMED}, |
| 548 | + $stats{$process_pid}->{HIGH_NR_FILE_RECLAIMED}, | |
| 549 | + $stats{$process_pid}->{HIGH_NR_ANON_RECLAIMED}, | |
| 517 | 550 | $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_FILE_SYNC} + $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_ANON_SYNC}, |
| 518 | 551 | $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_FILE_ASYNC} + $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_ANON_ASYNC}, |
| 519 | 552 | $this_reclaim_delay / 1000); |
| @@ -552,7 +585,11 @@ sub dump_stats { · 32 unmodified lines | ||
| 552 | 585 | |
| 553 | 586 | $total_kswapd_wake += $stats{$process_pid}->{MM_VMSCAN_KSWAPD_WAKE}; |
| 554 | 587 | $total_kswapd_nr_scanned += $stats{$process_pid}->{HIGH_NR_SCANNED}; |
| 588 | + $total_kswapd_nr_file_scanned += $stats{$process_pid}->{HIGH_NR_FILE_SCANNED}; | |
| 589 | + $total_kswapd_nr_anon_scanned += $stats{$process_pid}->{HIGH_NR_ANON_SCANNED}; | |
| 555 | 590 | $total_kswapd_nr_reclaimed += $stats{$process_pid}->{HIGH_NR_RECLAIMED}; |
| 591 | + $total_kswapd_nr_file_reclaimed += $stats{$process_pid}->{HIGH_NR_FILE_RECLAIMED}; | |
| 592 | + $total_kswapd_nr_anon_reclaimed += $stats{$process_pid}->{HIGH_NR_ANON_RECLAIMED}; | |
| 556 | 593 | $total_kswapd_writepage_file_sync += $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_FILE_SYNC}; |
| 557 | 594 | $total_kswapd_writepage_anon_sync += $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_ANON_SYNC}; |
| 558 | 595 | $total_kswapd_writepage_file_async += $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_FILE_ASYNC}; |
| @@ -563,7 +600,11 @@ sub dump_stats { · 4 unmodified lines | ||
| 563 | 600 | $stats{$process_pid}->{MM_VMSCAN_KSWAPD_WAKE}, |
| 564 | 601 | $stats{$process_pid}->{HIGH_KSWAPD_REWAKEUP}, |
| 565 | 602 | $stats{$process_pid}->{HIGH_NR_SCANNED}, |
| 603 | + $stats{$process_pid}->{HIGH_NR_FILE_SCANNED}, | |
| 604 | + $stats{$process_pid}->{HIGH_NR_ANON_SCANNED}, | |
| 566 | 605 | $stats{$process_pid}->{HIGH_NR_RECLAIMED}, |
| 606 | + $stats{$process_pid}->{HIGH_NR_FILE_RECLAIMED}, | |
| 607 | + $stats{$process_pid}->{HIGH_NR_ANON_RECLAIMED}, | |
| 567 | 608 | $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_FILE_SYNC} + $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_ANON_SYNC}, |
| 568 | 609 | $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_FILE_ASYNC} + $stats{$process_pid}->{MM_VMSCAN_WRITEPAGE_ANON_ASYNC}); |
| 569 | 610 | |
| @@ -594,7 +635,11 @@ sub dump_stats { · 24 unmodified lines | ||
| 594 | 635 | print "\nSummary\n"; |
| 595 | 636 | print "Direct reclaims: $total_direct_reclaim\n"; |
| 596 | 637 | print "Direct reclaim pages scanned: $total_direct_nr_scanned\n"; |
| 638 | + print "Direct reclaim file pages scanned: $total_direct_nr_file_scanned\n"; | |
| 639 | + print "Direct reclaim anon pages scanned: $total_direct_nr_anon_scanned\n"; | |
| 597 | 640 | print "Direct reclaim pages reclaimed: $total_direct_nr_reclaimed\n"; |
| 641 | + print "Direct reclaim file pages reclaimed: $total_direct_nr_file_reclaimed\n"; | |
| 642 | + print "Direct reclaim anon pages reclaimed: $total_direct_nr_anon_reclaimed\n"; | |
| 598 | 643 | print "Direct reclaim write file sync I/O: $total_direct_writepage_file_sync\n"; |
| 599 | 644 | print "Direct reclaim write anon sync I/O: $total_direct_writepage_anon_sync\n"; |
| 600 | 645 | print "Direct reclaim write file async I/O: $total_direct_writepage_file_async\n"; |
| @@ -604,7 +649,11 @@ sub dump_stats { · 3 unmodified lines | ||
| 604 | 649 | print "\n"; |
| 605 | 650 | print "Kswapd wakeups: $total_kswapd_wake\n"; |
| 606 | 651 | print "Kswapd pages scanned: $total_kswapd_nr_scanned\n"; |
| 652 | + print "Kswapd file pages scanned: $total_kswapd_nr_file_scanned\n"; | |
| 653 | + print "Kswapd anon pages scanned: $total_kswapd_nr_anon_scanned\n"; | |
| 607 | 654 | print "Kswapd pages reclaimed: $total_kswapd_nr_reclaimed\n"; |
| 655 | + print "Kswapd file pages reclaimed: $total_kswapd_nr_file_reclaimed\n"; | |
| 656 | + print "Kswapd anon pages reclaimed: $total_kswapd_nr_anon_reclaimed\n"; | |
| 608 | 657 | print "Kswapd reclaim write file sync I/O: $total_kswapd_writepage_file_sync\n"; |
| 609 | 658 | print "Kswapd reclaim write anon sync I/O: $total_kswapd_writepage_anon_sync\n"; |
| 610 | 659 | print "Kswapd reclaim write file async I/O: $total_kswapd_writepage_file_async\n"; |
| @@ -629,7 +678,11 @@ sub aggregate_perprocesspid() { · 18 unmodified lines | ||
| 629 | 678 | $perprocess{$process}->{MM_VMSCAN_WAKEUP_KSWAPD} += $perprocesspid{$process_pid}->{MM_VMSCAN_WAKEUP_KSWAPD}; |
| 630 | 679 | $perprocess{$process}->{HIGH_KSWAPD_REWAKEUP} += $perprocesspid{$process_pid}->{HIGH_KSWAPD_REWAKEUP}; |
| 631 | 680 | $perprocess{$process}->{HIGH_NR_SCANNED} += $perprocesspid{$process_pid}->{HIGH_NR_SCANNED}; |
| 681 | + $perprocess{$process}->{HIGH_NR_FILE_SCANNED} += $perprocesspid{$process_pid}->{HIGH_NR_FILE_SCANNED}; | |
| 682 | + $perprocess{$process}->{HIGH_NR_ANON_SCANNED} += $perprocesspid{$process_pid}->{HIGH_NR_ANON_SCANNED}; | |
| 632 | 683 | $perprocess{$process}->{HIGH_NR_RECLAIMED} += $perprocesspid{$process_pid}->{HIGH_NR_RECLAIMED}; |
| 684 | + $perprocess{$process}->{HIGH_NR_FILE_RECLAIMED} += $perprocesspid{$process_pid}->{HIGH_NR_FILE_RECLAIMED}; | |
| 685 | + $perprocess{$process}->{HIGH_NR_ANON_RECLAIMED} += $perprocesspid{$process_pid}->{HIGH_NR_ANON_RECLAIMED}; | |
| 633 | 686 | $perprocess{$process}->{MM_VMSCAN_WRITEPAGE_FILE_SYNC} += $perprocesspid{$process_pid}->{MM_VMSCAN_WRITEPAGE_FILE_SYNC}; |
| 634 | 687 | $perprocess{$process}->{MM_VMSCAN_WRITEPAGE_ANON_SYNC} += $perprocesspid{$process_pid}->{MM_VMSCAN_WRITEPAGE_ANON_SYNC}; |
| 635 | 688 | $perprocess{$process}->{MM_VMSCAN_WRITEPAGE_FILE_ASYNC} += $perprocesspid{$process_pid}->{MM_VMSCAN_WRITEPAGE_FILE_ASYNC}; |
| @@ -305,7 +305,15 @@ faster, the map/unmap handling has been implemented in real mode which provides · 304 unmodified lines | ||
| 305 | 305 | an excellent performance which has limitations such as inability to do |
| 306 | 306 | locked pages accounting in real time. |
| 307 | 307 | |
| 308 | −So 3 additional ioctls have been added: | |
| 308 | +4) According to sPAPR specification, A Partitionable Endpoint (PE) is an I/O | |
| 309 | +subtree that can be treated as a unit for the purposes of partitioning and | |
| 310 | +error recovery. A PE may be a single or multi-function IOA (IO Adapter), a | |
| 311 | +function of a multi-function IOA, or multiple IOAs (possibly including switch | |
| 312 | +and bridge structures above the multiple IOAs). PPC64 guests detect PCI errors | |
| 313 | +and recover from them via EEH RTAS services, which works on the basis of | |
| 314 | +additional ioctl commands. | |
| 315 | + | |
| 316 | +So 4 additional ioctls have been added: | |
| 309 | 317 | |
| 310 | 318 | VFIO_IOMMU_SPAPR_TCE_GET_INFO - returns the size and the start |
| 311 | 319 | of the DMA window on the PCI bus. |
| @@ -316,9 +324,12 @@ So 3 additional ioctls have been added: · 4 unmodified lines | ||
| 316 | 324 | |
| 317 | 325 | VFIO_IOMMU_DISABLE - disables the container. |
| 318 | 326 | |
| 327 | + VFIO_EEH_PE_OP - provides an API for EEH setup, error detection and recovery. | |
| 319 | 328 | |
| 320 | 329 | The code flow from the example above should be slightly changed: |
| 321 | 330 | |
| 331 | + struct vfio_eeh_pe_op pe_op = { .argsz = sizeof(pe_op), .flags = 0 }; | |
| 332 | + | |
| 322 | 333 | ..... |
| 323 | 334 | /* Add the group to the container */ |
| 324 | 335 | ioctl(group, VFIO_GROUP_SET_CONTAINER, &container); |
| @@ -342,9 +353,79 @@ The code flow from the example above should be slightly changed: · 17 unmodified lines | ||
| 342 | 353 | dma_map.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE; |
| 343 | 354 | |
| 344 | 355 | /* Check here is .iova/.size are within DMA window from spapr_iommu_info */ |
| 345 | − | |
| 346 | 356 | ioctl(container, VFIO_IOMMU_MAP_DMA, &dma_map); |
| 347 | − ..... | |
| 357 | + | |
| 358 | + /* Get a file descriptor for the device */ | |
| 359 | + device = ioctl(group, VFIO_GROUP_GET_DEVICE_FD, "0000:06:0d.0"); | |
| 360 | + | |
| 361 | + .... | |
| 362 | + | |
| 363 | + /* Gratuitous device reset and go... */ | |
| 364 | + ioctl(device, VFIO_DEVICE_RESET); | |
| 365 | + | |
| 366 | + /* Make sure EEH is supported */ | |
| 367 | + ioctl(container, VFIO_CHECK_EXTENSION, VFIO_EEH); | |
| 368 | + | |
| 369 | + /* Enable the EEH functionality on the device */ | |
| 370 | + pe_op.op = VFIO_EEH_PE_ENABLE; | |
| 371 | + ioctl(container, VFIO_EEH_PE_OP, &pe_op); | |
| 372 | + | |
| 373 | + /* You're suggested to create additional data struct to represent | |
| 374 | + * PE, and put child devices belonging to same IOMMU group to the | |
| 375 | + * PE instance for later reference. | |
| 376 | + */ | |
| 377 | + | |
| 378 | + /* Check the PE's state and make sure it's in functional state */ | |
| 379 | + pe_op.op = VFIO_EEH_PE_GET_STATE; | |
| 380 | + ioctl(container, VFIO_EEH_PE_OP, &pe_op); | |
| 381 | + | |
| 382 | + /* Save device state using pci_save_state(). | |
| 383 | + * EEH should be enabled on the specified device. | |
| 384 | + */ | |
| 385 | + | |
| 386 | + .... | |
| 387 | + | |
| 388 | + /* When 0xFF's returned from reading PCI config space or IO BARs | |
| 389 | + * of the PCI device. Check the PE's state to see if that has been | |
| 390 | + * frozen. | |
| 391 | + */ | |
| 392 | + ioctl(container, VFIO_EEH_PE_OP, &pe_op); | |
| 393 | + | |
| 394 | + /* Waiting for pending PCI transactions to be completed and don't | |
| 395 | + * produce any more PCI traffic from/to the affected PE until | |
| 396 | + * recovery is finished. | |
| 397 | + */ | |
| 398 | + | |
| 399 | + /* Enable IO for the affected PE and collect logs. Usually, the | |
| 400 | + * standard part of PCI config space, AER registers are dumped | |
| 401 | + * as logs for further analysis. | |
| 402 | + */ | |
| 403 | + pe_op.op = VFIO_EEH_PE_UNFREEZE_IO; | |
| 404 | + ioctl(container, VFIO_EEH_PE_OP, &pe_op); | |
| 405 | + | |
| 406 | + /* | |
| 407 | + * Issue PE reset: hot or fundamental reset. Usually, hot reset | |
| 408 | + * is enough. However, the firmware of some PCI adapters would | |
| 409 | + * require fundamental reset. | |
| 410 | + */ | |
| 411 | + pe_op.op = VFIO_EEH_PE_RESET_HOT; | |
| 412 | + ioctl(container, VFIO_EEH_PE_OP, &pe_op); | |
| 413 | + pe_op.op = VFIO_EEH_PE_RESET_DEACTIVATE; | |
| 414 | + ioctl(container, VFIO_EEH_PE_OP, &pe_op); | |
| 415 | + | |
| 416 | + /* Configure the PCI bridges for the affected PE */ | |
| 417 | + pe_op.op = VFIO_EEH_PE_CONFIGURE; | |
| 418 | + ioctl(container, VFIO_EEH_PE_OP, &pe_op); | |
| 419 | + | |
| 420 | + /* Restored state we saved at initialization time. pci_restore_state() | |
| 421 | + * is good enough as an example. | |
| 422 | + */ | |
| 423 | + | |
| 424 | + /* Hopefully, error is recovered successfully. Now, you can resume to | |
| 425 | + * start PCI traffic to/from the affected PE. | |
| 426 | + */ | |
| 427 | + | |
| 428 | + .... | |
| 348 | 429 | |
| 349 | 430 | ------------------------------------------------------------------------------- |
| 350 | 431 | |
| @@ -148,9 +148,9 @@ of banks, as set via the KVM_X86_SETUP_MCE ioctl. · 147 unmodified lines | ||
| 148 | 148 | |
| 149 | 149 | 4.4 KVM_CHECK_EXTENSION |
| 150 | 150 | |
| 151 | −Capability: basic | |
| 151 | +Capability: basic, KVM_CAP_CHECK_EXTENSION_VM for vm ioctl | |
| 152 | 152 | Architectures: all |
| 153 | −Type: system ioctl | |
| 153 | +Type: system ioctl, vm ioctl | |
| 154 | 154 | Parameters: extension identifier (KVM_CAP_*) |
| 155 | 155 | Returns: 0 if unsupported; 1 (or some other positive integer) if supported |
| 156 | 156 | |
| @@ -160,6 +160,9 @@ receives an integer that describes the extension availability. · 3 unmodified lines | ||
| 160 | 160 | Generally 0 means no and 1 means yes, but some extensions may report |
| 161 | 161 | additional information in the integer return value. |
| 162 | 162 | |
| 163 | +Based on their initialization different VMs may have different capabilities. | |
| 164 | +It is thus encouraged to use the vm ioctl to query for capabilities (available | |
| 165 | +with KVM_CAP_CHECK_EXTENSION_VM on the vm fd) | |
| 163 | 166 | |
| 164 | 167 | 4.5 KVM_GET_VCPU_MMAP_SIZE |
| 165 | 168 | |
| @@ -1892,7 +1895,8 @@ registers, find a list below: · 1726 unmodified lines | ||
| 1892 | 1895 | PPC | KVM_REG_PPC_PID | 64 |
| 1893 | 1896 | PPC | KVM_REG_PPC_ACOP | 64 |
| 1894 | 1897 | PPC | KVM_REG_PPC_VRSAVE | 32 |
| 1895 | − PPC | KVM_REG_PPC_LPCR | 64 | |
| 1898 | + PPC | KVM_REG_PPC_LPCR | 32 | |
| 1899 | + PPC | KVM_REG_PPC_LPCR_64 | 64 | |
| 1896 | 1900 | PPC | KVM_REG_PPC_PPR | 64 |
| 1897 | 1901 | PPC | KVM_REG_PPC_ARCH_COMPAT | 32 |
| 1898 | 1902 | PPC | KVM_REG_PPC_DABRX | 32 |
| @@ -2677,8 +2681,8 @@ The 'data' member contains, in its first 'len' bytes, the value as it would · 778 unmodified lines | ||
| 2677 | 2681 | appear if the VCPU performed a load or store of the appropriate width directly |
| 2678 | 2682 | to the byte array. |
| 2679 | 2683 | |
| 2680 | −NOTE: For KVM_EXIT_IO, KVM_EXIT_MMIO, KVM_EXIT_OSI, KVM_EXIT_DCR, | |
| 2681 | − KVM_EXIT_PAPR and KVM_EXIT_EPR the corresponding | |
| 2684 | +NOTE: For KVM_EXIT_IO, KVM_EXIT_MMIO, KVM_EXIT_OSI, KVM_EXIT_PAPR and | |
| 2685 | + KVM_EXIT_EPR the corresponding | |
| 2682 | 2686 | operations are complete (and guest state is consistent) only after userspace |
| 2683 | 2687 | has re-entered the kernel with KVM_RUN. The kernel side will first finish |
| 2684 | 2688 | incomplete operations and then check for pending signals. Userspace |
| @@ -2749,7 +2753,7 @@ Principles of Operation Book in the Chapter for Dynamic Address Translation · 64 unmodified lines | ||
| 2749 | 2753 | __u8 is_write; |
| 2750 | 2754 | } dcr; |
| 2751 | 2755 | |
| 2752 | −powerpc specific. | |
| 2756 | +Deprecated - was used for 440 KVM. | |
| 2753 | 2757 | |
| 2754 | 2758 | /* KVM_EXIT_OSI */ |
| 2755 | 2759 | struct { |
| @@ -2931,8 +2935,8 @@ The fields in each entry are defined as follows: · 175 unmodified lines | ||
| 2931 | 2935 | this function/index combination |
| 2932 | 2936 | |
| 2933 | 2937 | |
| 2934 | −6. Capabilities that can be enabled | |
| 2935 | −----------------------------------- | |
| 2938 | +6. Capabilities that can be enabled on vCPUs | |
| 2939 | +-------------------------------------------- | |
| 2936 | 2940 | |
| 2937 | 2941 | There are certain capabilities that change the behavior of the virtual CPU or |
| 2938 | 2942 | the virtual machine when enabled. To enable them, please see section 4.37. |
| @@ -3091,3 +3095,43 @@ Parameters: none · 152 unmodified lines | ||
| 3091 | 3095 | |
| 3092 | 3096 | This capability enables the in-kernel irqchip for s390. Please refer to |
| 3093 | 3097 | "4.24 KVM_CREATE_IRQCHIP" for details. |
| 3098 | + | |
| 3099 | +7. Capabilities that can be enabled on VMs | |
| 3100 | +------------------------------------------ | |
| 3101 | + | |
| 3102 | +There are certain capabilities that change the behavior of the virtual | |
| 3103 | +machine when enabled. To enable them, please see section 4.37. Below | |
| 3104 | +you can find a list of capabilities and what their effect on the VM | |
| 3105 | +is when enabling them. | |
| 3106 | + | |
| 3107 | +The following information is provided along with the description: | |
| 3108 | + | |
| 3109 | + Architectures: which instruction set architectures provide this ioctl. | |
| 3110 | + x86 includes both i386 and x86_64. | |
| 3111 | + | |
| 3112 | + Parameters: what parameters are accepted by the capability. | |
| 3113 | + | |
| 3114 | + Returns: the return value. General error numbers (EBADF, ENOMEM, EINVAL) | |
| 3115 | + are not detailed, but errors with specific meanings are. | |
| 3116 | + | |
| 3117 | + | |
| 3118 | +7.1 KVM_CAP_PPC_ENABLE_HCALL | |
| 3119 | + | |
| 3120 | +Architectures: ppc | |
| 3121 | +Parameters: args[0] is the sPAPR hcall number | |
| 3122 | + args[1] is 0 to disable, 1 to enable in-kernel handling | |
| 3123 | + | |
| 3124 | +This capability controls whether individual sPAPR hypercalls (hcalls) | |
| 3125 | +get handled by the kernel or not. Enabling or disabling in-kernel | |
| 3126 | +handling of an hcall is effective across the VM. On creation, an | |
| 3127 | +initial set of hcalls are enabled for in-kernel handling, which | |
| 3128 | +consists of those hcalls for which in-kernel handlers were implemented | |
| 3129 | +before this capability was implemented. If disabled, the kernel will | |
| 3130 | +not to attempt to handle the hcall, but will always exit to userspace | |
| 3131 | +to handle it. Note that it may not make sense to enable some and | |
| 3132 | +disable others of a group of related hcalls, but KVM does not prevent | |
| 3133 | +userspace from doing that. | |
| 3134 | + | |
| 3135 | +If the hcall number specified is not one that has an in-kernel | |
| 3136 | +implementation, the KVM_ENABLE_CAP ioctl will fail with an EINVAL | |
| 3137 | +error. | |
| @@ -35,7 +35,7 @@ invlpg instruction (or instructions _near_ it) show up high in · 34 unmodified lines | ||
| 35 | 35 | profiles. If you believe that individual invalidations being |
| 36 | 36 | called too often, you can lower the tunable: |
| 37 | 37 | |
| 38 | − /sys/debug/kernel/x86/tlb_single_page_flush_ceiling | |
| 38 | + /sys/kernel/debug/x86/tlb_single_page_flush_ceiling | |
| 39 | 39 | |
| 40 | 40 | This will cause us to do the global flush for more cases. |
| 41 | 41 | Lowering it to 0 will disable the use of the individual flushes. |
| @@ -150,10 +150,6 @@ LWN.net: · 149 unmodified lines | ||
| 150 | 150 | 将旧版内核的驱动程序移植到 2.6 版： |
| 151 | 151 | http://lwn.net/Articles/driver-porting/ |
| 152 | 152 | |
| 153 | −KernelTrap： | |
| 154 | − Linux 内核的最新动态以及开发者访谈 | |
| 155 | − http://kerneltrap.org/ | |
| 156 | − | |
| 157 | 153 | 内核新手(KernelNewbies): |
| 158 | 154 | 为新的内核开发者提供文档和帮助 |
| 159 | 155 | http://kernelnewbies.org/ |
| @@ -597,7 +597,7 @@ AMD GEODE CS5536 USB DEVICE CONTROLLER DRIVER · 596 unmodified lines | ||
| 597 | 597 | M: Thomas Dahlmann <dahlmann.thomas@arcor.de> |
| 598 | 598 | L: linux-geode@lists.infradead.org (moderated for non-subscribers) |
| 599 | 599 | S: Supported |
| 600 | −F: drivers/usb/gadget/amd5536udc.* | |
| 600 | +F: drivers/usb/gadget/udc/amd5536udc.* | |
| 601 | 601 | |
| 602 | 602 | AMD GEODE PROCESSOR/CHIPSET SUPPORT |
| 603 | 603 | P: Andres Salomon <dilinger@queued.net> |
| @@ -606,7 +606,7 @@ W: http://www.amd.com/us-en/ConnectivitySolutions/TechnicalResources/0,,50_2334_ · 2 unmodified lines | ||
| 606 | 606 | S: Supported |
| 607 | 607 | F: drivers/char/hw_random/geode-rng.c |
| 608 | 608 | F: drivers/crypto/geode* |
| 609 | −F: drivers/video/geode/ | |
| 609 | +F: drivers/video/fbdev/geode/ | |
| 610 | 610 | F: arch/x86/include/asm/geode.h |
| 611 | 611 | |
| 612 | 612 | AMD IOMMU (AMD-VI) |
| @@ -621,7 +621,7 @@ AMD MICROCODE UPDATE SUPPORT · 8 unmodified lines | ||
| 621 | 621 | M: Andreas Herrmann <herrmann.der.user@googlemail.com> |
| 622 | 622 | L: amd64-microcode@amd64.org |
| 623 | 623 | S: Maintained |
| 624 | −F: arch/x86/kernel/microcode_amd.c | |
| 624 | +F: arch/x86/kernel/cpu/microcode/amd* | |
| 625 | 625 | |
| 626 | 626 | AMD XGBE DRIVER |
| 627 | 627 | M: Tom Lendacky <thomas.lendacky@amd.com> |
| @@ -719,6 +719,14 @@ S: Maintained · 91 unmodified lines | ||
| 719 | 719 | F: drivers/net/appletalk/ |
| 720 | 720 | F: net/appletalk/ |
| 721 | 721 | |
| 722 | +APPLIED MICRO (APM) X-GENE SOC ETHERNET DRIVER | |
| 723 | +M: Iyappan Subramanian <isubramanian@apm.com> | |
| 724 | +M: Keyur Chudgar <kchudgar@apm.com> | |
| 725 | +M: Ravi Patel <rapatel@apm.com> | |
| 726 | +S: Supported | |
| 727 | +F: drivers/net/ethernet/apm/xgene/ | |
| 728 | +F: Documentation/devicetree/bindings/net/apm-xgene-enet.txt | |
| 729 | + | |
| 722 | 730 | APTINA CAMERA SENSOR PLL |
| 723 | 731 | M: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> |
| 724 | 732 | L: linux-media@vger.kernel.org |
| @@ -735,8 +743,8 @@ F: drivers/ata/pata_arasan_cf.c · 10 unmodified lines | ||
| 735 | 743 | ARC FRAMEBUFFER DRIVER |
| 736 | 744 | M: Jaya Kumar <jayalk@intworks.biz> |
| 737 | 745 | S: Maintained |
| 738 | −F: drivers/video/arcfb.c | |
| 739 | −F: drivers/video/fb_defio.c | |
| 746 | +F: drivers/video/fbdev/arcfb.c | |
| 747 | +F: drivers/video/fbdev/core/fb_defio.c | |
| 740 | 748 | |
| 741 | 749 | ARM MFM AND FLOPPY DRIVERS |
| 742 | 750 | M: Ian Molton <spyro@f2s.com> |
| @@ -775,7 +783,7 @@ F: sound/arm/aaci.* · 32 unmodified lines | ||
| 775 | 783 | ARM PRIMECELL CLCD PL110 DRIVER |
| 776 | 784 | M: Russell King <linux@arm.linux.org.uk> |
| 777 | 785 | S: Maintained |
| 778 | −F: drivers/video/amba-clcd.* | |
| 786 | +F: drivers/video/fbdev/amba-clcd.* | |
| 779 | 787 | |
| 780 | 788 | ARM PRIMECELL KMI PL050 DRIVER |
| 781 | 789 | M: Russell King <linux@arm.linux.org.uk> |
| @@ -911,7 +919,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) · 129 unmodified lines | ||
| 911 | 919 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux.git |
| 912 | 920 | S: Maintained |
| 913 | 921 | F: arch/arm/mach-prima2/ |
| 914 | −F: drivers/clk/clk-prima2.c | |
| 922 | +F: drivers/clk/sirf/ | |
| 915 | 923 | F: drivers/clocksource/timer-prima2.c |
| 916 | 924 | F: drivers/clocksource/timer-marco.c |
| 917 | 925 | N: [^a-z]sirf |
| @@ -985,6 +993,14 @@ F: arch/arm/mach-pxa/hx4700.c · 67 unmodified lines | ||
| 985 | 993 | F: arch/arm/mach-pxa/include/mach/hx4700.h |
| 986 | 994 | F: sound/soc/pxa/hx4700.c |
| 987 | 995 | |
| 996 | +ARM/HISILICON SOC SUPPORT | |
| 997 | +M: Wei Xu <xuwei5@hisilicon.com> | |
| 998 | +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | |
| 999 | +W: http://www.hisilicon.com | |
| 1000 | +S: Supported | |
| 1001 | +T: git git://github.com/hisilicon/linux-hisi.git | |
| 1002 | +F: arch/arm/mach-hisi/ | |
| 1003 | + | |
| 988 | 1004 | ARM/HP JORNADA 7XX MACHINE SUPPORT |
| 989 | 1005 | M: Kristoffer Ericson <kristoffer.ericson@gmail.com> |
| 990 | 1006 | W: www.jlime.com |
| @@ -1116,14 +1132,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) · 125 unmodified lines | ||
| 1116 | 1132 | S: Maintained |
| 1117 | 1133 | F: arch/arm/mach-berlin/ |
| 1118 | 1134 | |
| 1119 | −ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support | |
| 1135 | +ARM/Marvell Dove/MV78xx0/Orion SOC support | |
| 1120 | 1136 | M: Jason Cooper <jason@lakedaemon.net> |
| 1121 | 1137 | M: Andrew Lunn <andrew@lunn.ch> |
| 1122 | 1138 | M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
| 1123 | 1139 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 1124 | 1140 | S: Maintained |
| 1125 | 1141 | F: arch/arm/mach-dove/ |
| 1126 | −F: arch/arm/mach-kirkwood/ | |
| 1127 | 1142 | F: arch/arm/mach-mv78xx0/ |
| 1128 | 1143 | F: arch/arm/mach-orion5x/ |
| 1129 | 1144 | F: arch/arm/plat-orion/ |
| @@ -1157,6 +1172,7 @@ M: Linus Walleij <linus.walleij@linaro.org> · 27 unmodified lines | ||
| 1157 | 1172 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 1158 | 1173 | S: Maintained |
| 1159 | 1174 | F: arch/arm/mach-nomadik/ |
| 1175 | +F: drivers/pinctrl/nomadik/ | |
| 1160 | 1176 | F: drivers/i2c/busses/i2c-nomadik.c |
| 1161 | 1177 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git |
| 1162 | 1178 | |
| @@ -1172,14 +1188,13 @@ M: Daniel Walker <dwalker@fifo99.com> · 9 unmodified lines | ||
| 1172 | 1188 | M: Bryan Huntsman <bryanh@codeaurora.org> |
| 1173 | 1189 | L: linux-arm-msm@vger.kernel.org |
| 1174 | 1190 | F: arch/arm/mach-msm/ |
| 1175 | −F: drivers/video/msm/ | |
| 1191 | +F: drivers/video/fbdev/msm/ | |
| 1176 | 1192 | F: drivers/mmc/host/msm_sdcc.c |
| 1177 | 1193 | F: drivers/mmc/host/msm_sdcc.h |
| 1178 | 1194 | F: drivers/tty/serial/msm_serial.h |
| 1179 | 1195 | F: drivers/tty/serial/msm_serial.c |
| 1180 | 1196 | F: drivers/*/pm8???-* |
| 1181 | −F: drivers/mfd/ssbi/ | |
| 1182 | −F: include/linux/mfd/pm8xxx/ | |
| 1197 | +F: drivers/mfd/ssbi.c | |
| 1183 | 1198 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm.git |
| 1184 | 1199 | S: Maintained |
| 1185 | 1200 | |
| @@ -1262,6 +1277,7 @@ F: drivers/scsi/arm/ · 76 unmodified lines | ||
| 1262 | 1277 | ARM/Rockchip SoC support |
| 1263 | 1278 | M: Heiko Stuebner <heiko@sntech.de> |
| 1264 | 1279 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 1280 | +L: linux-rockchip@lists.infradead.org | |
| 1265 | 1281 | S: Maintained |
| 1266 | 1282 | F: arch/arm/mach-rockchip/ |
| 1267 | 1283 | F: drivers/*/*rockchip* |
| @@ -1376,6 +1392,7 @@ F: drivers/pinctrl/pinctrl-st.c · 108 unmodified lines | ||
| 1376 | 1392 | F: drivers/media/rc/st_rc.c |
| 1377 | 1393 | F: drivers/i2c/busses/i2c-st.c |
| 1378 | 1394 | F: drivers/tty/serial/st-asc.c |
| 1395 | +F: drivers/mmc/host/sdhci-st.c | |
| 1379 | 1396 | |
| 1380 | 1397 | ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT |
| 1381 | 1398 | M: Lennert Buytenhek <kernel@wantstofly.org> |
| @@ -1406,7 +1423,7 @@ F: drivers/mtd/nand/nuc900_nand.c · 24 unmodified lines | ||
| 1406 | 1423 | F: drivers/rtc/rtc-nuc900.c |
| 1407 | 1424 | F: drivers/spi/spi-nuc900.c |
| 1408 | 1425 | F: drivers/usb/host/ehci-w90x900.c |
| 1409 | −F: drivers/video/nuc900fb.c | |
| 1426 | +F: drivers/video/fbdev/nuc900fb.c | |
| 1410 | 1427 | |
| 1411 | 1428 | ARM/U300 MACHINE SUPPORT |
| 1412 | 1429 | M: Linus Walleij <linus.walleij@linaro.org> |
| @@ -1435,7 +1452,8 @@ F: drivers/mfd/abx500* · 22 unmodified lines | ||
| 1435 | 1452 | F: drivers/mfd/ab8500* |
| 1436 | 1453 | F: drivers/mfd/dbx500* |
| 1437 | 1454 | F: drivers/mfd/db8500* |
| 1438 | −F: drivers/pinctrl/pinctrl-nomadik* | |
| 1455 | +F: drivers/pinctrl/nomadik/pinctrl-ab* | |
| 1456 | +F: drivers/pinctrl/nomadik/pinctrl-nomadik* | |
| 1439 | 1457 | F: drivers/rtc/rtc-ab8500.c |
| 1440 | 1458 | F: drivers/rtc/rtc-pl031.c |
| 1441 | 1459 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git |
| @@ -1475,9 +1493,9 @@ F: drivers/rtc/rtc-vt8500.c · 33 unmodified lines | ||
| 1475 | 1493 | F: drivers/tty/serial/vt8500_serial.c |
| 1476 | 1494 | F: drivers/usb/host/ehci-platform.c |
| 1477 | 1495 | F: drivers/usb/host/uhci-platform.c |
| 1478 | −F: drivers/video/vt8500lcdfb.* | |
| 1479 | −F: drivers/video/wm8505fb* | |
| 1480 | −F: drivers/video/wmt_ge_rops.* | |
| 1496 | +F: drivers/video/fbdev/vt8500lcdfb.* | |
| 1497 | +F: drivers/video/fbdev/wm8505fb* | |
| 1498 | +F: drivers/video/fbdev/wmt_ge_rops.* | |
| 1481 | 1499 | |
| 1482 | 1500 | ARM/ZIPIT Z2 SUPPORT |
| 1483 | 1501 | M: Marek Vasut <marek.vasut@gmail.com> |
| @@ -1667,7 +1685,7 @@ ATMEL LCDFB DRIVER · 183 unmodified lines | ||
| 1667 | 1685 | M: Nicolas Ferre <nicolas.ferre@atmel.com> |
| 1668 | 1686 | L: linux-fbdev@vger.kernel.org |
| 1669 | 1687 | S: Maintained |
| 1670 | −F: drivers/video/atmel_lcdfb.c | |
| 1688 | +F: drivers/video/fbdev/atmel_lcdfb.c | |
| 1671 | 1689 | F: include/video/atmel_lcdc.h |
| 1672 | 1690 | |
| 1673 | 1691 | ATMEL MACB ETHERNET DRIVER |
| @@ -1691,7 +1709,7 @@ ATMEL USBA UDC DRIVER · 17 unmodified lines | ||
| 1691 | 1709 | M: Nicolas Ferre <nicolas.ferre@atmel.com> |
| 1692 | 1710 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 1693 | 1711 | S: Supported |
| 1694 | −F: drivers/usb/gadget/atmel_usba_udc.* | |
| 1712 | +F: drivers/usb/gadget/udc/atmel_usba_udc.* | |
| 1695 | 1713 | |
| 1696 | 1714 | ATMEL WIRELESS DRIVER |
| 1697 | 1715 | M: Simon Kelley <simon@thekelleys.org.uk> |
| @@ -1826,6 +1844,12 @@ S: Orphan · 128 unmodified lines | ||
| 1826 | 1844 | F: Documentation/filesystems/befs.txt |
| 1827 | 1845 | F: fs/befs/ |
| 1828 | 1846 | |
| 1847 | +BECKHOFF CX5020 ETHERCAT MASTER DRIVER | |
| 1848 | +M: Dariusz Marcinkiewicz <reksio@newterm.pl> | |
| 1849 | +L: netdev@vger.kernel.org | |
| 1850 | +S: Maintained | |
| 1851 | +F: drivers/net/ethernet/ec_bhf.c | |
| 1852 | + | |
| 1829 | 1853 | BFS FILE SYSTEM |
| 1830 | 1854 | M: "Tigran A. Aivazian" <tigran@aivazian.fsnet.co.uk> |
| 1831 | 1855 | S: Maintained |
| @@ -1983,7 +2007,7 @@ F: arch/arm/boot/dts/bcm113* · 151 unmodified lines | ||
| 1983 | 2007 | F: arch/arm/boot/dts/bcm216* |
| 1984 | 2008 | F: arch/arm/boot/dts/bcm281* |
| 1985 | 2009 | F: arch/arm/configs/bcm_defconfig |
| 1986 | −F: drivers/mmc/host/sdhci_bcm_kona.c | |
| 2010 | +F: drivers/mmc/host/sdhci-bcm-kona.c | |
| 1987 | 2011 | F: drivers/clocksource/bcm_kona_timer.c |
| 1988 | 2012 | |
| 1989 | 2013 | BROADCOM BCM2835 ARM ARCHICTURE |
| @@ -2004,6 +2028,14 @@ F: arch/arm/mach-bcm/bcm_5301x.c · 14 unmodified lines | ||
| 2004 | 2028 | F: arch/arm/boot/dts/bcm5301x.dtsi |
| 2005 | 2029 | F: arch/arm/boot/dts/bcm470* |
| 2006 | 2030 | |
| 2031 | +BROADCOM BCM7XXX ARM ARCHITECTURE | |
| 2032 | +M: Marc Carino <marc.ceeeee@gmail.com> | |
| 2033 | +M: Brian Norris <computersforpeace@gmail.com> | |
| 2034 | +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | |
| 2035 | +S: Maintained | |
| 2036 | +F: arch/arm/mach-bcm/*brcmstb* | |
| 2037 | +F: arch/arm/boot/dts/bcm7*.dts* | |
| 2038 | + | |
| 2007 | 2039 | BROADCOM TG3 GIGABIT ETHERNET DRIVER |
| 2008 | 2040 | M: Prashant Sreedharan <prashant@broadcom.com> |
| 2009 | 2041 | M: Michael Chan <mchan@broadcom.com> |
| @@ -2034,7 +2066,7 @@ S: Supported · 24 unmodified lines | ||
| 2034 | 2066 | F: drivers/scsi/bnx2i/ |
| 2035 | 2067 | |
| 2036 | 2068 | BROADCOM KONA GPIO DRIVER |
| 2037 | −M: Markus Mayer <markus.mayer@linaro.org> | |
| 2069 | +M: Ray Jui <rjui@broadcom.com> | |
| 2038 | 2070 | L: bcm-kernel-feedback-list@broadcom.com |
| 2039 | 2071 | S: Supported |
| 2040 | 2072 | F: drivers/gpio/gpio-bcm-kona.c |
| @@ -2325,12 +2357,6 @@ L: netdev@vger.kernel.org · 284 unmodified lines | ||
| 2325 | 2357 | S: Maintained |
| 2326 | 2358 | F: drivers/net/ethernet/cirrus/ep93xx_eth.c |
| 2327 | 2359 | |
| 2328 | −CIRRUS LOGIC EP93XX OHCI USB HOST DRIVER | |
| 2329 | −M: Lennert Buytenhek <kernel@wantstofly.org> | |
| 2330 | −L: linux-usb@vger.kernel.org | |
| 2331 | −S: Maintained | |
| 2332 | −F: drivers/usb/host/ohci-ep93xx.c | |
| 2333 | − | |
| 2334 | 2360 | CIRRUS LOGIC AUDIO CODEC DRIVERS |
| 2335 | 2361 | M: Brian Austin <brian.austin@cirrus.com> |
| 2336 | 2362 | M: Paul Handrigan <Paul.Handrigan@cirrus.com> |
| @@ -2415,7 +2441,7 @@ W: http://linux-cifs.samba.org/ · 78 unmodified lines | ||
| 2415 | 2441 | Q: http://patchwork.ozlabs.org/project/linux-cifs-client/list/ |
| 2416 | 2442 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6.git |
| 2417 | 2443 | S: Supported |
| 2418 | −F: Documentation/filesystems/cifs.txt | |
| 2444 | +F: Documentation/filesystems/cifs/ | |
| 2419 | 2445 | F: fs/cifs/ |
| 2420 | 2446 | |
| 2421 | 2447 | COMPACTPCI HOTPLUG CORE |
| @@ -2692,7 +2718,7 @@ M: Russell King <linux@arm.linux.org.uk> · 270 unmodified lines | ||
| 2692 | 2718 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 2693 | 2719 | W: http://www.arm.linux.org.uk/ |
| 2694 | 2720 | S: Maintained |
| 2695 | −F: drivers/video/cyber2000fb.* | |
| 2721 | +F: drivers/video/fbdev/cyber2000fb.* | |
| 2696 | 2722 | |
| 2697 | 2723 | CYCLADES ASYNC MUX DRIVER |
| 2698 | 2724 | W: http://www.cyclades.com/ |
| @@ -2930,7 +2956,7 @@ M: Bernie Thompson <bernie@plugable.com> · 231 unmodified lines | ||
| 2930 | 2956 | L: linux-fbdev@vger.kernel.org |
| 2931 | 2957 | S: Maintained |
| 2932 | 2958 | W: http://plugable.com/category/projects/udlfb/ |
| 2933 | −F: drivers/video/udlfb.c | |
| 2959 | +F: drivers/video/fbdev/udlfb.c | |
| 2934 | 2960 | F: include/video/udlfb.h |
| 2935 | 2961 | F: Documentation/fb/udlfb.txt |
| 2936 | 2962 | |
| @@ -2950,7 +2976,9 @@ L: linux-media@vger.kernel.org · 13 unmodified lines | ||
| 2950 | 2976 | L: dri-devel@lists.freedesktop.org |
| 2951 | 2977 | L: linaro-mm-sig@lists.linaro.org |
| 2952 | 2978 | F: drivers/dma-buf/ |
| 2953 | −F: include/linux/dma-buf* include/linux/reservation.h include/linux/*fence.h | |
| 2979 | +F: include/linux/dma-buf* | |
| 2980 | +F: include/linux/reservation.h | |
| 2981 | +F: include/linux/*fence.h | |
| 2954 | 2982 | F: Documentation/dma-buf-sharing.txt |
| 2955 | 2983 | T: git git://git.linaro.org/people/sumitsemwal/linux-dma-buf.git |
| 2956 | 2984 | |
| @@ -3045,7 +3073,6 @@ L: dri-devel@lists.freedesktop.org · 88 unmodified lines | ||
| 3045 | 3073 | T: git git://people.freedesktop.org/~agd5f/linux |
| 3046 | 3074 | S: Supported |
| 3047 | 3075 | F: drivers/gpu/drm/radeon/ |
| 3048 | −F: include/drm/radeon* | |
| 3049 | 3076 | F: include/uapi/drm/radeon* |
| 3050 | 3077 | |
| 3051 | 3078 | DRM PANEL DRIVERS |
| @@ -3095,6 +3122,17 @@ F: include/linux/host1x.h · 43 unmodified lines | ||
| 3095 | 3122 | F: include/uapi/drm/tegra_drm.h |
| 3096 | 3123 | F: Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt |
| 3097 | 3124 | |
| 3125 | +DRM DRIVERS FOR RENESAS | |
| 3126 | +M: Laurent Pinchart <laurent.pinchart@ideasonboard.com> | |
| 3127 | +L: dri-devel@lists.freedesktop.org | |
| 3128 | +L: linux-sh@vger.kernel.org | |
| 3129 | +T: git git://people.freedesktop.org/~airlied/linux | |
| 3130 | +S: Supported | |
| 3131 | +F: drivers/gpu/drm/rcar-du/ | |
| 3132 | +F: drivers/gpu/drm/shmobile/ | |
| 3133 | +F: include/linux/platform_data/rcar-du.h | |
| 3134 | +F: include/linux/platform_data/shmob_drm.h | |
| 3135 | + | |
| 3098 | 3136 | DSBR100 USB FM RADIO DRIVER |
| 3099 | 3137 | M: Alexey Klimov <klimov.linux@gmail.com> |
| 3100 | 3138 | L: linux-media@vger.kernel.org |
| @@ -3239,26 +3277,12 @@ T: git git://linuxtv.org/anttip/media_tree.git · 138 unmodified lines | ||
| 3239 | 3277 | S: Maintained |
| 3240 | 3278 | F: drivers/media/tuners/e4000* |
| 3241 | 3279 | |
| 3242 | −EATA-DMA SCSI DRIVER | |
| 3243 | −M: Michael Neuffer <mike@i-Connect.Net> | |
| 3244 | −L: linux-eata@i-connect.net | |
| 3245 | −L: linux-scsi@vger.kernel.org | |
| 3246 | −S: Maintained | |
| 3247 | −F: drivers/scsi/eata* | |
| 3248 | − | |
| 3249 | 3280 | EATA ISA/EISA/PCI SCSI DRIVER |
| 3250 | 3281 | M: Dario Ballabio <ballabio_dario@emc.com> |
| 3251 | 3282 | L: linux-scsi@vger.kernel.org |
| 3252 | 3283 | S: Maintained |
| 3253 | 3284 | F: drivers/scsi/eata.c |
| 3254 | 3285 | |
| 3255 | −EATA-PIO SCSI DRIVER | |
| 3256 | −M: Michael Neuffer <mike@i-Connect.Net> | |
| 3257 | −L: linux-eata@i-connect.net | |
| 3258 | −L: linux-scsi@vger.kernel.org | |
| 3259 | −S: Maintained | |
| 3260 | −F: drivers/scsi/eata_pio.* | |
| 3261 | − | |
| 3262 | 3286 | EC100 MEDIA DRIVER |
| 3263 | 3287 | M: Antti Palosaari <crope@iki.fi> |
| 3264 | 3288 | L: linux-media@vger.kernel.org |
| @@ -3433,7 +3457,7 @@ M: Matt Fleming <matt.fleming@intel.com> · 168 unmodified lines | ||
| 3433 | 3457 | L: linux-efi@vger.kernel.org |
| 3434 | 3458 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/mfleming/efi.git |
| 3435 | 3459 | S: Maintained |
| 3436 | −F: Documentation/x86/efi-stub.txt | |
| 3460 | +F: Documentation/efi-stub.txt | |
| 3437 | 3461 | F: arch/ia64/kernel/efi.c |
| 3438 | 3462 | F: arch/x86/boot/compressed/eboot.[ch] |
| 3439 | 3463 | F: arch/x86/include/asm/efi.h |
| @@ -3454,7 +3478,7 @@ EFIFB FRAMEBUFFER DRIVER · 14 unmodified lines | ||
| 3454 | 3478 | L: linux-fbdev@vger.kernel.org |
| 3455 | 3479 | M: Peter Jones <pjones@redhat.com> |
| 3456 | 3480 | S: Maintained |
| 3457 | −F: drivers/video/efifb.c | |
| 3481 | +F: drivers/video/fbdev/efifb.c | |
| 3458 | 3482 | |
| 3459 | 3483 | EFS FILESYSTEM |
| 3460 | 3484 | W: http://aeschi.ch.eu.org/efs/ |
| @@ -3519,7 +3543,7 @@ EPSON S1D13XXX FRAMEBUFFER DRIVER · 58 unmodified lines | ||
| 3519 | 3543 | M: Kristoffer Ericson <kristoffer.ericson@gmail.com> |
| 3520 | 3544 | S: Maintained |
| 3521 | 3545 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/kristoffer/linux-hpc.git |
| 3522 | −F: drivers/video/s1d13xxxfb.c | |
| 3546 | +F: drivers/video/fbdev/s1d13xxxfb.c | |
| 3523 | 3547 | F: include/video/s1d13xxxfb.h |
| 3524 | 3548 | |
| 3525 | 3549 | ETHERNET BRIDGE |
| @@ -3597,7 +3621,7 @@ M: Donghwa Lee <dh09.lee@samsung.com> · 71 unmodified lines | ||
| 3597 | 3621 | M: Kyungmin Park <kyungmin.park@samsung.com> |
| 3598 | 3622 | L: linux-fbdev@vger.kernel.org |
| 3599 | 3623 | S: Maintained |
| 3600 | −F: drivers/video/exynos/exynos_mipi* | |
| 3624 | +F: drivers/video/fbdev/exynos/exynos_mipi* | |
| 3601 | 3625 | F: include/video/exynos_mipi* |
| 3602 | 3626 | |
| 3603 | 3627 | F71805F HARDWARE MONITORING DRIVER |
| @@ -3776,7 +3800,7 @@ FREESCALE DIU FRAMEBUFFER DRIVER · 172 unmodified lines | ||
| 3776 | 3800 | M: Timur Tabi <timur@tabi.org> |
| 3777 | 3801 | L: linux-fbdev@vger.kernel.org |
| 3778 | 3802 | S: Maintained |
| 3779 | −F: drivers/video/fsl-diu-fb.* | |
| 3803 | +F: drivers/video/fbdev/fsl-diu-fb.* | |
| 3780 | 3804 | |
| 3781 | 3805 | FREESCALE DMA DRIVER |
| 3782 | 3806 | M: Li Yang <leoli@freescale.com> |
| @@ -3798,7 +3822,7 @@ L: linux-fbdev@vger.kernel.org · 15 unmodified lines | ||
| 3798 | 3822 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 3799 | 3823 | S: Maintained |
| 3800 | 3824 | F: include/linux/platform_data/video-imxfb.h |
| 3801 | −F: drivers/video/imxfb.c | |
| 3825 | +F: drivers/video/fbdev/imxfb.c | |
| 3802 | 3826 | |
| 3803 | 3827 | FREESCALE SOC FS_ENET DRIVER |
| 3804 | 3828 | M: Pantelis Antoniou <pantelis.antoniou@gmail.com> |
| @@ -3820,7 +3844,7 @@ M: Li Yang <leoli@freescale.com> · 15 unmodified lines | ||
| 3820 | 3844 | L: linux-usb@vger.kernel.org |
| 3821 | 3845 | L: linuxppc-dev@lists.ozlabs.org |
| 3822 | 3846 | S: Maintained |
| 3823 | −F: drivers/usb/gadget/fsl* | |
| 3847 | +F: drivers/usb/gadget/udc/fsl* | |
| 3824 | 3848 | |
| 3825 | 3849 | FREESCALE QUICC ENGINE UCC ETHERNET DRIVER |
| 3826 | 3850 | M: Li Yang <leoli@freescale.com> |
| @@ -3837,10 +3861,13 @@ F: drivers/tty/serial/ucc_uart.c · 10 unmodified lines | ||
| 3837 | 3861 | |
| 3838 | 3862 | FREESCALE SOC SOUND DRIVERS |
| 3839 | 3863 | M: Timur Tabi <timur@tabi.org> |
| 3864 | +M: Nicolin Chen <nicoleotsuka@gmail.com> | |
| 3865 | +M: Xiubo Li <Li.Xiubo@freescale.com> | |
| 3840 | 3866 | L: alsa-devel@alsa-project.org (moderated for non-subscribers) |
| 3841 | 3867 | L: linuxppc-dev@lists.ozlabs.org |
| 3842 | 3868 | S: Maintained |
| 3843 | 3869 | F: sound/soc/fsl/fsl* |
| 3870 | +F: sound/soc/fsl/imx* | |
| 3844 | 3871 | F: sound/soc/fsl/mpc8610_hpcd.c |
| 3845 | 3872 | |
| 3846 | 3873 | FREEVXFS FILESYSTEM |
| @@ -4033,7 +4060,8 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git · 186 unmodified lines | ||
| 4033 | 4060 | S: Maintained |
| 4034 | 4061 | F: Documentation/gpio/ |
| 4035 | 4062 | F: drivers/gpio/ |
| 4036 | −F: include/linux/gpio* | |
| 4063 | +F: include/linux/gpio/ | |
| 4064 | +F: include/linux/gpio.h | |
| 4037 | 4065 | F: include/asm-generic/gpio.h |
| 4038 | 4066 | |
| 4039 | 4067 | GRE DEMULTIPLEXER DRIVER |
| @@ -4223,7 +4251,7 @@ M: Ferenc Bakonyi <fero@drama.obuda.kando.hu> · 183 unmodified lines | ||
| 4223 | 4251 | L: linux-nvidia@lists.surfsouth.com |
| 4224 | 4252 | W: http://drama.obuda.kando.hu/~fero/cgi-bin/hgafb.shtml |
| 4225 | 4253 | S: Maintained |
| 4226 | −F: drivers/video/hgafb.c | |
| 4254 | +F: drivers/video/fbdev/hgafb.c | |
| 4227 | 4255 | |
| 4228 | 4256 | HIBERNATION (aka Software Suspend, aka swsusp) |
| 4229 | 4257 | M: "Rafael J. Wysocki" <rjw@rjwysocki.net> |
| @@ -4365,7 +4393,7 @@ F: drivers/hv/ · 135 unmodified lines | ||
| 4365 | 4393 | F: drivers/input/serio/hyperv-keyboard.c |
| 4366 | 4394 | F: drivers/net/hyperv/ |
| 4367 | 4395 | F: drivers/scsi/storvsc_drv.c |
| 4368 | −F: drivers/video/hyperv_fb.c | |
| 4396 | +F: drivers/video/fbdev/hyperv_fb.c | |
| 4369 | 4397 | F: include/linux/hyperv.h |
| 4370 | 4398 | F: tools/hv/ |
| 4371 | 4399 | |
| @@ -4439,6 +4467,13 @@ F: include/linux/i2c-*.h · 67 unmodified lines | ||
| 4439 | 4467 | F: include/uapi/linux/i2c.h |
| 4440 | 4468 | F: include/uapi/linux/i2c-*.h |
| 4441 | 4469 | |
| 4470 | +I2C ACPI SUPPORT | |
| 4471 | +M: Mika Westerberg <mika.westerberg@linux.intel.com> | |
| 4472 | +L: linux-i2c@vger.kernel.org | |
| 4473 | +L: linux-acpi@vger.kernel.org | |
| 4474 | +S: Maintained | |
| 4475 | +F: drivers/i2c/i2c-acpi.c | |
| 4476 | + | |
| 4442 | 4477 | I2C-TAOS-EVM DRIVER |
| 4443 | 4478 | M: Jean Delvare <jdelvare@suse.de> |
| 4444 | 4479 | L: linux-i2c@vger.kernel.org |
| @@ -4509,10 +4544,7 @@ S: Supported · 64 unmodified lines | ||
| 4509 | 4544 | F: drivers/scsi/ibmvscsi/ibmvfc* |
| 4510 | 4545 | |
| 4511 | 4546 | IBM ServeRAID RAID DRIVER |
| 4512 | −P: Jack Hammer | |
| 4513 | −M: Dave Jeffery <ipslinux@adaptec.com> | |
| 4514 | −W: http://www.developer.ibm.com/welcome/netfinity/serveraid.html | |
| 4515 | −S: Supported | |
| 4547 | +S: Orphan | |
| 4516 | 4548 | F: drivers/scsi/ips.* |
| 4517 | 4549 | |
| 4518 | 4550 | ICH LPC AND GPIO DRIVER |
| @@ -4624,7 +4656,7 @@ F: security/integrity/ima/ · 105 unmodified lines | ||
| 4624 | 4656 | IMS TWINTURBO FRAMEBUFFER DRIVER |
| 4625 | 4657 | L: linux-fbdev@vger.kernel.org |
| 4626 | 4658 | S: Orphan |
| 4627 | −F: drivers/video/imsttfb.c | |
| 4659 | +F: drivers/video/fbdev/imsttfb.c | |
| 4628 | 4660 | |
| 4629 | 4661 | INFINIBAND SUBSYSTEM |
| 4630 | 4662 | M: Roland Dreier <roland@kernel.org> |
| @@ -4691,13 +4723,13 @@ M: Maik Broemme <mbroemme@plusserver.de> · 60 unmodified lines | ||
| 4691 | 4723 | L: linux-fbdev@vger.kernel.org |
| 4692 | 4724 | S: Maintained |
| 4693 | 4725 | F: Documentation/fb/intelfb.txt |
| 4694 | −F: drivers/video/intelfb/ | |
| 4726 | +F: drivers/video/fbdev/intelfb/ | |
| 4695 | 4727 | |
| 4696 | 4728 | INTEL 810/815 FRAMEBUFFER DRIVER |
| 4697 | 4729 | M: Antonino Daplas <adaplas@gmail.com> |
| 4698 | 4730 | L: linux-fbdev@vger.kernel.org |
| 4699 | 4731 | S: Maintained |
| 4700 | −F: drivers/video/i810/ | |
| 4732 | +F: drivers/video/fbdev/i810/ | |
| 4701 | 4733 | |
| 4702 | 4734 | INTEL MENLOW THERMAL DRIVER |
| 4703 | 4735 | M: Sujith Thomas <sujith.thomas@intel.com> |
| @@ -4709,8 +4741,8 @@ F: drivers/platform/x86/intel_menlow.c · 5 unmodified lines | ||
| 4709 | 4741 | INTEL IA32 MICROCODE UPDATE SUPPORT |
| 4710 | 4742 | M: Tigran Aivazian <tigran@aivazian.fsnet.co.uk> |
| 4711 | 4743 | S: Maintained |
| 4712 | −F: arch/x86/kernel/microcode_core.c | |
| 4713 | −F: arch/x86/kernel/microcode_intel.c | |
| 4744 | +F: arch/x86/kernel/cpu/microcode/core* | |
| 4745 | +F: arch/x86/kernel/cpu/microcode/intel* | |
| 4714 | 4746 | |
| 4715 | 4747 | INTEL I/OAT DMA DRIVER |
| 4716 | 4748 | M: Dan Williams <dan.j.williams@intel.com> |
| @@ -5169,7 +5201,6 @@ L: linux-nfs@vger.kernel.org · 452 unmodified lines | ||
| 5169 | 5201 | W: http://nfs.sourceforge.net/ |
| 5170 | 5202 | S: Supported |
| 5171 | 5203 | F: fs/nfsd/ |
| 5172 | −F: include/linux/nfsd/ | |
| 5173 | 5204 | F: include/uapi/linux/nfsd/ |
| 5174 | 5205 | F: fs/lockd/ |
| 5175 | 5206 | F: fs/nfs_common/ |
| @@ -5424,6 +5455,7 @@ F: arch/powerpc/boot/rs6000.h · 248 unmodified lines | ||
| 5424 | 5455 | LINUX FOR POWERPC (32-BIT AND 64-BIT) |
| 5425 | 5456 | M: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
| 5426 | 5457 | M: Paul Mackerras <paulus@samba.org> |
| 5458 | +M: Michael Ellerman <mpe@ellerman.id.au> | |
| 5427 | 5459 | W: http://www.penguinppc.org/ |
| 5428 | 5460 | L: linuxppc-dev@lists.ozlabs.org |
| 5429 | 5461 | Q: http://patchwork.ozlabs.org/project/linuxppc-dev/list/ |
| @@ -5465,16 +5497,17 @@ F: arch/powerpc/*/*/*virtex* · 35 unmodified lines | ||
| 5465 | 5497 | |
| 5466 | 5498 | LINUX FOR POWERPC EMBEDDED PPC8XX |
| 5467 | 5499 | M: Vitaly Bordug <vitb@kernel.crashing.org> |
| 5468 | −M: Marcelo Tosatti <marcelo@kvack.org> | |
| 5469 | 5500 | W: http://www.penguinppc.org/ |
| 5470 | 5501 | L: linuxppc-dev@lists.ozlabs.org |
| 5471 | 5502 | S: Maintained |
| 5472 | 5503 | F: arch/powerpc/platforms/8xx/ |
| 5473 | 5504 | |
| 5474 | 5505 | LINUX FOR POWERPC EMBEDDED PPC83XX AND PPC85XX |
| 5506 | +M: Scott Wood <scottwood@freescale.com> | |
| 5475 | 5507 | M: Kumar Gala <galak@kernel.crashing.org> |
| 5476 | 5508 | W: http://www.penguinppc.org/ |
| 5477 | 5509 | L: linuxppc-dev@lists.ozlabs.org |
| 5510 | +T: git git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git | |
| 5478 | 5511 | S: Maintained |
| 5479 | 5512 | F: arch/powerpc/platforms/83xx/ |
| 5480 | 5513 | F: arch/powerpc/platforms/85xx/ |
| @@ -5761,7 +5794,7 @@ F: drivers/mmc/host/mvsdio.* · 280 unmodified lines | ||
| 5761 | 5794 | MATROX FRAMEBUFFER DRIVER |
| 5762 | 5795 | L: linux-fbdev@vger.kernel.org |
| 5763 | 5796 | S: Orphan |
| 5764 | −F: drivers/video/matrox/matroxfb_* | |
| 5797 | +F: drivers/video/fbdev/matrox/matroxfb_* | |
| 5765 | 5798 | F: include/uapi/linux/matroxfb.h |
| 5766 | 5799 | |
| 5767 | 5800 | MAX16065 HARDWARE MONITOR DRIVER |
| @@ -5888,7 +5921,6 @@ F: drivers/clocksource/metag_generic.c · 120 unmodified lines | ||
| 5888 | 5921 | F: drivers/irqchip/irq-metag.c |
| 5889 | 5922 | F: drivers/irqchip/irq-metag-ext.c |
| 5890 | 5923 | F: drivers/tty/metag_da.c |
| 5891 | −F: fs/imgdafs/ | |
| 5892 | 5924 | |
| 5893 | 5925 | MICROBLAZE ARCHITECTURE |
| 5894 | 5926 | M: Michal Simek <monstr@monstr.eu> |
| @@ -5968,6 +6000,12 @@ T: git git://linuxtv.org/media_tree.git · 73 unmodified lines | ||
| 5968 | 6000 | S: Maintained |
| 5969 | 6001 | F: drivers/media/radio/radio-mr800.c |
| 5970 | 6002 | |
| 6003 | +MRF24J40 IEEE 802.15.4 RADIO DRIVER | |
| 6004 | +M: Alan Ott <alan@signal11.us> | |
| 6005 | +L: linux-wpan@vger.kernel.org | |
| 6006 | +S: Maintained | |
| 6007 | +F: drivers/net/ieee802154/mrf24j40.c | |
| 6008 | + | |
| 5971 | 6009 | MSI LAPTOP SUPPORT |
| 5972 | 6010 | M: "Lee, Chun-Yi" <jlee@suse.com> |
| 5973 | 6011 | L: platform-driver-x86@vger.kernel.org |
| @@ -6035,8 +6073,7 @@ F: include/media/mt9v032.h · 61 unmodified lines | ||
| 6035 | 6073 | MULTIFUNCTION DEVICES (MFD) |
| 6036 | 6074 | M: Samuel Ortiz <sameo@linux.intel.com> |
| 6037 | 6075 | M: Lee Jones <lee.jones@linaro.org> |
| 6038 | −T: git git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-next.git | |
| 6039 | −T: git git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-fixes.git | |
| 6076 | +T: git git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git | |
| 6040 | 6077 | S: Supported |
| 6041 | 6078 | F: drivers/mfd/ |
| 6042 | 6079 | F: include/linux/mfd/ |
| @@ -6403,8 +6440,8 @@ NVIDIA (rivafb and nvidiafb) FRAMEBUFFER DRIVER · 360 unmodified lines | ||
| 6403 | 6440 | M: Antonino Daplas <adaplas@gmail.com> |
| 6404 | 6441 | L: linux-fbdev@vger.kernel.org |
| 6405 | 6442 | S: Maintained |
| 6406 | −F: drivers/video/riva/ | |
| 6407 | −F: drivers/video/nvidia/ | |
| 6443 | +F: drivers/video/fbdev/riva/ | |
| 6444 | +F: drivers/video/fbdev/nvidia/ | |
| 6408 | 6445 | |
| 6409 | 6446 | NVM EXPRESS DRIVER |
| 6410 | 6447 | M: Matthew Wilcox <willy@linux.intel.com> |
| @@ -6474,14 +6511,14 @@ M: Tomi Valkeinen <tomi.valkeinen@ti.com> · 63 unmodified lines | ||
| 6474 | 6511 | L: linux-fbdev@vger.kernel.org |
| 6475 | 6512 | L: linux-omap@vger.kernel.org |
| 6476 | 6513 | S: Maintained |
| 6477 | −F: drivers/video/omap/ | |
| 6514 | +F: drivers/video/fbdev/omap/ | |
| 6478 | 6515 | |
| 6479 | 6516 | OMAP DISPLAY SUBSYSTEM and FRAMEBUFFER SUPPORT (DSS2) |
| 6480 | 6517 | M: Tomi Valkeinen <tomi.valkeinen@ti.com> |
| 6481 | 6518 | L: linux-omap@vger.kernel.org |
| 6482 | 6519 | L: linux-fbdev@vger.kernel.org |
| 6483 | 6520 | S: Maintained |
| 6484 | −F: drivers/video/omap2/ | |
| 6521 | +F: drivers/video/fbdev/omap2/ | |
| 6485 | 6522 | F: Documentation/arm/OMAP/DSS |
| 6486 | 6523 | |
| 6487 | 6524 | OMAP HARDWARE SPINLOCK SUPPORT |
| @@ -6773,7 +6810,7 @@ F: drivers/char/agp/parisc-agp.c · 285 unmodified lines | ||
| 6773 | 6810 | F: drivers/input/serio/gscps2.c |
| 6774 | 6811 | F: drivers/parport/parport_gsc.* |
| 6775 | 6812 | F: drivers/tty/serial/8250/8250_gsc.c |
| 6776 | −F: drivers/video/sti* | |
| 6813 | +F: drivers/video/fbdev/sti* | |
| 6777 | 6814 | F: drivers/video/console/sti* |
| 6778 | 6815 | F: drivers/video/logo/logo_parisc* |
| 6779 | 6816 | |
| @@ -6855,6 +6892,14 @@ S: Supported · 75 unmodified lines | ||
| 6855 | 6892 | F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt |
| 6856 | 6893 | F: drivers/pci/host/pci-tegra.c |
| 6857 | 6894 | |
| 6895 | +PCI DRIVER FOR TI DRA7XX | |
| 6896 | +M: Kishon Vijay Abraham I <kishon@ti.com> | |
| 6897 | +L: linux-omap@vger.kernel.org | |
| 6898 | +L: linux-pci@vger.kernel.org | |
| 6899 | +S: Supported | |
| 6900 | +F: Documentation/devicetree/bindings/pci/ti-pci.txt | |
| 6901 | +F: drivers/pci/host/pci-dra7xx.c | |
| 6902 | + | |
| 6858 | 6903 | PCI DRIVER FOR RENESAS R-CAR |
| 6859 | 6904 | M: Simon Horman <horms@verge.net.au> |
| 6860 | 6905 | L: linux-pci@vger.kernel.org |
| @@ -6885,6 +6930,12 @@ S: Maintained · 24 unmodified lines | ||
| 6885 | 6930 | F: Documentation/devicetree/bindings/pci/host-generic-pci.txt |
| 6886 | 6931 | F: drivers/pci/host/pci-host-generic.c |
| 6887 | 6932 | |
| 6933 | +PCIE DRIVER FOR ST SPEAR13XX | |
| 6934 | +M: Mohit Kumar <mohit.kumar@st.com> | |
| 6935 | +L: linux-pci@vger.kernel.org | |
| 6936 | +S: Maintained | |
| 6937 | +F: drivers/pci/host/*spear* | |
| 6938 | + | |
| 6888 | 6939 | PCMCIA SUBSYSTEM |
| 6889 | 6940 | P: Linux PCMCIA Team |
| 6890 | 6941 | L: linux-pcmcia@lists.infradead.org |
| @@ -6974,9 +7025,9 @@ M: Jamie Iles <jamie@jamieiles.com> · 83 unmodified lines | ||
| 6974 | 7025 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 6975 | 7026 | T: git git://github.com/jamieiles/linux-2.6-ji.git |
| 6976 | 7027 | S: Supported |
| 7028 | +F: arch/arm/boot/dts/picoxcell* | |
| 6977 | 7029 | F: arch/arm/mach-picoxcell/ |
| 6978 | −F: drivers/*/picoxcell* | |
| 6979 | −F: drivers/*/*/picoxcell* | |
| 7030 | +F: drivers/crypto/picoxcell* | |
| 6980 | 7031 | |
| 6981 | 7032 | PIN CONTROL SUBSYSTEM |
| 6982 | 7033 | M: Linus Walleij <linus.walleij@linaro.org> |
| @@ -7002,9 +7053,7 @@ M: Thomas Abraham <thomas.abraham@linaro.org> · 19 unmodified lines | ||
| 7002 | 7053 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 7003 | 7054 | L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) |
| 7004 | 7055 | S: Maintained |
| 7005 | −F: drivers/pinctrl/pinctrl-exynos.* | |
| 7006 | −F: drivers/pinctrl/pinctrl-s3c* | |
| 7007 | −F: drivers/pinctrl/pinctrl-samsung.* | |
| 7056 | +F: drivers/pinctrl/samsung/ | |
| 7008 | 7057 | |
| 7009 | 7058 | PIN CONTROLLER - ST SPEAR |
| 7010 | 7059 | M: Viresh Kumar <viresh.linux@gmail.com> |
| @@ -7028,7 +7077,7 @@ S: Maintained · 17 unmodified lines | ||
| 7028 | 7077 | T: git git://github.com/gxt/linux.git |
| 7029 | 7078 | F: drivers/input/serio/i8042-unicore32io.h |
| 7030 | 7079 | F: drivers/i2c/busses/i2c-puv3.c |
| 7031 | −F: drivers/video/fb-puv3.c | |
| 7080 | +F: drivers/video/fbdev/fb-puv3.c | |
| 7032 | 7081 | F: drivers/rtc/rtc-puv3.c |
| 7033 | 7082 | |
| 7034 | 7083 | PMBUS HARDWARE MONITORING DRIVERS |
| @@ -7052,6 +7101,7 @@ F: drivers/scsi/pmcraid.* · 17 unmodified lines | ||
| 7052 | 7101 | PMC SIERRA PM8001 DRIVER |
| 7053 | 7102 | M: xjtuwjp@gmail.com |
| 7054 | 7103 | M: lindar_liu@usish.com |
| 7104 | +L: pmchba@pmcs.com | |
| 7055 | 7105 | L: linux-scsi@vger.kernel.org |
| 7056 | 7106 | S: Supported |
| 7057 | 7107 | F: drivers/scsi/pm8001/ |
| @@ -7201,7 +7251,7 @@ F: drivers/ptp/* · 143 unmodified lines | ||
| 7201 | 7251 | F: include/linux/ptp_cl* |
| 7202 | 7252 | |
| 7203 | 7253 | PTRACE SUPPORT |
| 7204 | −M: Roland McGrath <roland@redhat.com> | |
| 7254 | +M: Roland McGrath <roland@hack.frob.com> | |
| 7205 | 7255 | M: Oleg Nesterov <oleg@redhat.com> |
| 7206 | 7256 | S: Maintained |
| 7207 | 7257 | F: include/asm-generic/syscall.h |
| @@ -7251,7 +7301,7 @@ S: Maintained · 43 unmodified lines | ||
| 7251 | 7301 | F: arch/arm/mach-pxa/ |
| 7252 | 7302 | F: drivers/pcmcia/pxa2xx* |
| 7253 | 7303 | F: drivers/spi/spi-pxa2xx* |
| 7254 | −F: drivers/usb/gadget/pxa2* | |
| 7304 | +F: drivers/usb/gadget/udc/pxa2* | |
| 7255 | 7305 | F: include/sound/pxa2xx-lib.h |
| 7256 | 7306 | F: sound/arm/pxa* |
| 7257 | 7307 | F: sound/soc/pxa/ |
| @@ -7260,7 +7310,7 @@ PXA3xx NAND FLASH DRIVER · 2 unmodified lines | ||
| 7260 | 7310 | M: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> |
| 7261 | 7311 | L: linux-mtd@lists.infradead.org |
| 7262 | 7312 | S: Maintained |
| 7263 | −F: drivers/mtd/nand/pxa3xx-nand.c | |
| 7313 | +F: drivers/mtd/nand/pxa3xx_nand.c | |
| 7264 | 7314 | |
| 7265 | 7315 | MMP SUPPORT |
| 7266 | 7316 | M: Eric Miao <eric.y.miao@gmail.com> |
| @@ -7408,7 +7458,7 @@ RADEON FRAMEBUFFER DISPLAY DRIVER · 141 unmodified lines | ||
| 7408 | 7458 | M: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
| 7409 | 7459 | L: linux-fbdev@vger.kernel.org |
| 7410 | 7460 | S: Maintained |
| 7411 | −F: drivers/video/aty/radeon* | |
| 7461 | +F: drivers/video/fbdev/aty/radeon* | |
| 7412 | 7462 | F: include/uapi/linux/radeonfb.h |
| 7413 | 7463 | |
| 7414 | 7464 | RADIOSHARK RADIO DRIVER |
| @@ -7430,7 +7480,7 @@ RAGE128 FRAMEBUFFER DISPLAY DRIVER · 15 unmodified lines | ||
| 7430 | 7480 | M: Paul Mackerras <paulus@samba.org> |
| 7431 | 7481 | L: linux-fbdev@vger.kernel.org |
| 7432 | 7482 | S: Maintained |
| 7433 | −F: drivers/video/aty/aty128fb.c | |
| 7483 | +F: drivers/video/fbdev/aty/aty128fb.c | |
| 7434 | 7484 | |
| 7435 | 7485 | RALINK RT2X00 WIRELESS LAN DRIVER |
| 7436 | 7486 | P: rt2x00 project |
| @@ -7678,7 +7728,7 @@ S3 SAVAGE FRAMEBUFFER DRIVER · 241 unmodified lines | ||
| 7678 | 7728 | M: Antonino Daplas <adaplas@gmail.com> |
| 7679 | 7729 | L: linux-fbdev@vger.kernel.org |
| 7680 | 7730 | S: Maintained |
| 7681 | −F: drivers/video/savage/ | |
| 7731 | +F: drivers/video/fbdev/savage/ | |
| 7682 | 7732 | |
| 7683 | 7733 | S390 |
| 7684 | 7734 | M: Martin Schwidefsky <schwidefsky@de.ibm.com> |
| @@ -7801,7 +7851,7 @@ SAMSUNG FRAMEBUFFER DRIVER · 116 unmodified lines | ||
| 7801 | 7851 | M: Jingoo Han <jg1.han@samsung.com> |
| 7802 | 7852 | L: linux-fbdev@vger.kernel.org |
| 7803 | 7853 | S: Maintained |
| 7804 | −F: drivers/video/s3c-fb.c | |
| 7854 | +F: drivers/video/fbdev/s3c-fb.c | |
| 7805 | 7855 | |
| 7806 | 7856 | SAMSUNG MULTIFUNCTION DEVICE DRIVERS |
| 7807 | 7857 | M: Sangbeom Kim <sbkim73@samsung.com> |
| @@ -8298,7 +8348,7 @@ M: Thomas Winischhofer <thomas@winischhofer.net> · 490 unmodified lines | ||
| 8298 | 8348 | W: http://www.winischhofer.net/linuxsisvga.shtml |
| 8299 | 8349 | S: Maintained |
| 8300 | 8350 | F: Documentation/fb/sisfb.txt |
| 8301 | −F: drivers/video/sis/ | |
| 8351 | +F: drivers/video/fbdev/sis/ | |
| 8302 | 8352 | F: include/video/sisfb.h |
| 8303 | 8353 | |
| 8304 | 8354 | SIS USB2VGA DRIVER |
| @@ -8407,7 +8457,7 @@ SMSC UFX6000 and UFX7000 USB to VGA DRIVER · 102 unmodified lines | ||
| 8407 | 8457 | M: Steve Glendinning <steve.glendinning@shawell.net> |
| 8408 | 8458 | L: linux-fbdev@vger.kernel.org |
| 8409 | 8459 | S: Maintained |
| 8410 | −F: drivers/video/smscufx.c | |
| 8460 | +F: drivers/video/fbdev/smscufx.c | |
| 8411 | 8461 | |
| 8412 | 8462 | SOC-CAMERA V4L2 SUBSYSTEM |
| 8413 | 8463 | M: Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
| @@ -9605,8 +9655,8 @@ USB WEBCAM GADGET · 1191 unmodified lines | ||
| 9605 | 9655 | M: Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| 9606 | 9656 | L: linux-usb@vger.kernel.org |
| 9607 | 9657 | S: Maintained |
| 9608 | −F: drivers/usb/gadget/*uvc*.c | |
| 9609 | −F: drivers/usb/gadget/webcam.c | |
| 9658 | +F: drivers/usb/gadget/function/*uvc*.c | |
| 9659 | +F: drivers/usb/gadget/legacy/webcam.c | |
| 9610 | 9660 | |
| 9611 | 9661 | USB WIRELESS RNDIS DRIVER (rndis_wlan) |
| 9612 | 9662 | M: Jussi Kivilinna <jussi.kivilinna@iki.fi> |
| @@ -9671,7 +9721,7 @@ L: linux-fbdev@vger.kernel.org · 58 unmodified lines | ||
| 9671 | 9721 | W: http://dev.gentoo.org/~spock/projects/uvesafb/ |
| 9672 | 9722 | S: Maintained |
| 9673 | 9723 | F: Documentation/fb/uvesafb.txt |
| 9674 | −F: drivers/video/uvesafb.* | |
| 9724 | +F: drivers/video/fbdev/uvesafb.* | |
| 9675 | 9725 | |
| 9676 | 9726 | VFAT/FAT/MSDOS FILESYSTEM |
| 9677 | 9727 | M: OGAWA Hirofumi <hirofumi@mail.parknet.co.jp> |
| @@ -9744,7 +9794,7 @@ S: Maintained · 66 unmodified lines | ||
| 9744 | 9794 | F: include/linux/via-core.h |
| 9745 | 9795 | F: include/linux/via-gpio.h |
| 9746 | 9796 | F: include/linux/via_i2c.h |
| 9747 | −F: drivers/video/via/ | |
| 9797 | +F: drivers/video/fbdev/via/ | |
| 9748 | 9798 | |
| 9749 | 9799 | VIA VELOCITY NETWORK DRIVER |
| 9750 | 9800 | M: Francois Romieu <romieu@fr.zoreil.com> |
| @@ -9877,6 +9927,13 @@ M: Pierre Ossman <pierre@ossman.eu> · 126 unmodified lines | ||
| 9877 | 9927 | S: Maintained |
| 9878 | 9928 | F: drivers/mmc/host/wbsd.* |
| 9879 | 9929 | |
| 9930 | +WACOM PROTOCOL 4 SERIAL TABLETS | |
| 9931 | +M: Julian Squires <julian@cipht.net> | |
| 9932 | +M: Hans de Goede <hdegoede@redhat.com> | |
| 9933 | +L: linux-input@vger.kernel.org | |
| 9934 | +S: Maintained | |
| 9935 | +F: drivers/input/tablet/wacom_serial4.c | |
| 9936 | + | |
| 9880 | 9937 | WATCHDOG DEVICE DRIVERS |
| 9881 | 9938 | M: Wim Van Sebroeck <wim@iguana.be> |
| 9882 | 9939 | L: linux-watchdog@vger.kernel.org |
| @@ -10002,7 +10059,7 @@ F: arch/x86/ · 119 unmodified lines | ||
| 10002 | 10059 | X86 PLATFORM DRIVERS |
| 10003 | 10060 | M: Matthew Garrett <matthew.garrett@nebula.com> |
| 10004 | 10061 | L: platform-driver-x86@vger.kernel.org |
| 10005 | −T: git git://git.kernel.org/pub/scm/linux/kernel/git/mjg59/platform-drivers-x86.git | |
| 10062 | +T: git git://cavan.codon.org.uk/platform-drivers-x86.git | |
| 10006 | 10063 | S: Maintained |
| 10007 | 10064 | F: drivers/platform/x86/ |
| 10008 | 10065 | |
| @@ -10064,6 +10121,13 @@ S: Supported · 55 unmodified lines | ||
| 10064 | 10121 | F: arch/x86/pci/*xen* |
| 10065 | 10122 | F: drivers/pci/*xen* |
| 10066 | 10123 | |
| 10124 | +XEN BLOCK SUBSYSTEM | |
| 10125 | +M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> | |
| 10126 | +L: xen-devel@lists.xenproject.org (moderated for non-subscribers) | |
| 10127 | +S: Supported | |
| 10128 | +F: drivers/block/xen-blkback/* | |
| 10129 | +F: drivers/block/xen* | |
| 10130 | + | |
| 10067 | 10131 | XEN SWIOTLB SUBSYSTEM |
| 10068 | 10132 | M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> |
| 10069 | 10133 | L: xen-devel@lists.xenproject.org (moderated for non-subscribers) |
| @@ -1,7 +1,7 @@ | ||
| 1 | 1 | VERSION = 3 |
| 2 | −PATCHLEVEL = 16 | |
| 2 | +PATCHLEVEL = 17 | |
| 3 | 3 | SUBLEVEL = 0 |
| 4 | −EXTRAVERSION = | |
| 4 | +EXTRAVERSION = -rc2 | |
| 5 | 5 | NAME = Shuffling Zombie Juror |
| 6 | 6 | |
| 7 | 7 | # *DOCUMENTATION* |
| @@ -372,6 +372,7 @@ GENKSYMS = scripts/genksyms/genksyms · 364 unmodified lines | ||
| 372 | 372 | INSTALLKERNEL := installkernel |
| 373 | 373 | DEPMOD = /sbin/depmod |
| 374 | 374 | PERL = perl |
| 375 | +PYTHON = python | |
| 375 | 376 | CHECK = sparse |
| 376 | 377 | |
| 377 | 378 | CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ |
| @@ -422,7 +423,7 @@ KERNELVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(S · 44 unmodified lines | ||
| 422 | 423 | export VERSION PATCHLEVEL SUBLEVEL KERNELRELEASE KERNELVERSION |
| 423 | 424 | export ARCH SRCARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC |
| 424 | 425 | export CPP AR NM STRIP OBJCOPY OBJDUMP |
| 425 | −export MAKE AWK GENKSYMS INSTALLKERNEL PERL UTS_MACHINE | |
| 426 | +export MAKE AWK GENKSYMS INSTALLKERNEL PERL PYTHON UTS_MACHINE | |
| 426 | 427 | export HOSTCXX HOSTCXXFLAGS LDFLAGS_MODULE CHECK CHECKFLAGS |
| 427 | 428 | |
| 428 | 429 | export KBUILD_CPPFLAGS NOSTDINC_FLAGS LINUXINCLUDE OBJCOPYFLAGS LDFLAGS |
| @@ -621,6 +622,9 @@ else · 192 unmodified lines | ||
| 621 | 622 | KBUILD_CFLAGS += -O2 |
| 622 | 623 | endif |
| 623 | 624 | |
| 625 | +# Tell gcc to never replace conditional load with a non-conditional one | |
| 626 | +KBUILD_CFLAGS += $(call cc-option,--param=allow-store-data-races=0) | |
| 627 | + | |
| 624 | 628 | ifdef CONFIG_READABLE_ASM |
| 625 | 629 | # Disable optimizations that make assembler listings hard to read. |
| 626 | 630 | # reorder blocks reorders the control in the function |
| @@ -636,6 +640,22 @@ KBUILD_CFLAGS += $(call cc-option,-Wframe-larger-than=${CONFIG_FRAME_WARN}) · 9 unmodified lines | ||
| 636 | 640 | endif |
| 637 | 641 | |
| 638 | 642 | # Handle stack protector mode. |
| 643 | +# | |
| 644 | +# Since kbuild can potentially perform two passes (first with the old | |
| 645 | +# .config values and then with updated .config values), we cannot error out | |
| 646 | +# if a desired compiler option is unsupported. If we were to error, kbuild | |
| 647 | +# could never get to the second pass and actually notice that we changed | |
| 648 | +# the option to something that was supported. | |
| 649 | +# | |
| 650 | +# Additionally, we don't want to fallback and/or silently change which compiler | |
| 651 | +# flags will be used, since that leads to producing kernels with different | |
| 652 | +# security feature characteristics depending on the compiler used. ("But I | |
| 653 | +# selected CC_STACKPROTECTOR_STRONG! Why did it build with _REGULAR?!") | |
| 654 | +# | |
| 655 | +# The middle ground is to warn here so that the failed option is obvious, but | |
| 656 | +# to let the build fail with bad compiler flags so that we can't produce a | |
| 657 | +# kernel when there is a CONFIG and compiler mismatch. | |
| 658 | +# | |
| 639 | 659 | ifdef CONFIG_CC_STACKPROTECTOR_REGULAR |
| 640 | 660 | stackp-flag := -fstack-protector |
| 641 | 661 | ifeq ($(call cc-option, $(stackp-flag)),) |
| @@ -668,6 +688,7 @@ KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare) · 26 unmodified lines | ||
| 668 | 688 | # source of a reference will be _MergedGlobals and not on of the whitelisted names. |
| 669 | 689 | # See modpost pattern 2 |
| 670 | 690 | KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,) |
| 691 | +KBUILD_CFLAGS += $(call cc-option, -fcatch-undefined-behavior) | |
| 671 | 692 | else |
| 672 | 693 | |
| 673 | 694 | # This warning generated too much noise in a regular build. |
| @@ -691,9 +712,16 @@ endif · 17 unmodified lines | ||
| 691 | 712 | KBUILD_CFLAGS += $(call cc-option, -fno-var-tracking-assignments) |
| 692 | 713 | |
| 693 | 714 | ifdef CONFIG_DEBUG_INFO |
| 715 | +ifdef CONFIG_DEBUG_INFO_SPLIT | |
| 716 | +KBUILD_CFLAGS += $(call cc-option, -gsplit-dwarf, -g) | |
| 717 | +else | |
| 694 | 718 | KBUILD_CFLAGS += -g |
| 719 | +endif | |
| 695 | 720 | KBUILD_AFLAGS += -Wa,-gdwarf-2 |
| 696 | 721 | endif |
| 722 | +ifdef CONFIG_DEBUG_INFO_DWARF4 | |
| 723 | +KBUILD_CFLAGS += $(call cc-option, -gdwarf-4,) | |
| 724 | +endif | |
| 697 | 725 | |
| 698 | 726 | ifdef CONFIG_DEBUG_INFO_REDUCED |
| 699 | 727 | KBUILD_CFLAGS += $(call cc-option, -femit-struct-debug-baseonly) \ |
| @@ -1035,6 +1063,13 @@ headers_check: headers_install · 335 unmodified lines | ||
| 1035 | 1063 | $(Q)$(MAKE) $(hdr-inst)=include/uapi HDRCHECK=1 |
| 1036 | 1064 | $(Q)$(MAKE) $(hdr-inst)=arch/$(hdr-arch)/include/uapi/asm $(hdr-dst) HDRCHECK=1 |
| 1037 | 1065 | |
| 1066 | +# --------------------------------------------------------------------------- | |
| 1067 | +# Kernel selftest | |
| 1068 | + | |
| 1069 | +PHONY += kselftest | |
| 1070 | +kselftest: | |
| 1071 | + $(Q)$(MAKE) -C tools/testing/selftests run_tests | |
| 1072 | + | |
| 1038 | 1073 | # --------------------------------------------------------------------------- |
| 1039 | 1074 | # Modules |
| 1040 | 1075 | |
| @@ -1222,9 +1257,9 @@ help: · 181 unmodified lines | ||
| 1222 | 1257 | @echo ' tags/TAGS - Generate tags file for editors' |
| 1223 | 1258 | @echo ' cscope - Generate cscope index' |
| 1224 | 1259 | @echo ' gtags - Generate GNU GLOBAL index' |
| 1225 | − @echo ' kernelrelease - Output the release version string' | |
| 1226 | − @echo ' kernelversion - Output the version stored in Makefile' | |
| 1227 | − @echo ' image_name - Output the image name' | |
| 1260 | + @echo ' kernelrelease - Output the release version string (use with make -s)' | |
| 1261 | + @echo ' kernelversion - Output the version stored in Makefile (use with make -s)' | |
| 1262 | + @echo ' image_name - Output the image name (use with make -s)' | |
| 1228 | 1263 | @echo ' headers_install - Install sanitised kernel headers to INSTALL_HDR_PATH'; \ |
| 1229 | 1264 | echo ' (default: $(INSTALL_HDR_PATH))'; \ |
| 1230 | 1265 | echo '' |
| @@ -1238,6 +1273,11 @@ help: · 7 unmodified lines | ||
| 1238 | 1273 | @echo ' headerdep - Detect inclusion cycles in headers' |
| 1239 | 1274 | @$(MAKE) -f $(srctree)/scripts/Makefile.help checker-help |
| 1240 | 1275 | @echo '' |
| 1276 | + @echo 'Kernel selftest' | |
| 1277 | + @echo ' kselftest - Build and run kernel selftest (run as root)' | |
| 1278 | + @echo ' Build, install, and boot kernel before' | |
| 1279 | + @echo ' running kselftest on it' | |
| 1280 | + @echo '' | |
| 1241 | 1281 | @echo 'Kernel packaging:' |
| 1242 | 1282 | @$(MAKE) $(build)=$(package-dir) help |
| 1243 | 1283 | @echo '' |
| @@ -1379,6 +1419,7 @@ clean: $(clean-dirs) · 135 unmodified lines | ||
| 1379 | 1419 | @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \ |
| 1380 | 1420 | \( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \ |
| 1381 | 1421 | -o -name '*.ko.*' \ |
| 1422 | + -o -name '*.dwo' \ | |
| 1382 | 1423 | -o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \ |
| 1383 | 1424 | -o -name '*.symtypes' -o -name 'modules.order' \ |
| 1384 | 1425 | -o -name modules.builtin -o -name '.tmp_*.o.*' \ |
| @@ -6,4 +6,5 @@ generic-y += exec.h · 5 unmodified lines | ||
| 6 | 6 | generic-y += hash.h |
| 7 | 7 | generic-y += mcs_spinlock.h |
| 8 | 8 | generic-y += preempt.h |
| 9 | +generic-y += scatterlist.h | |
| 9 | 10 | generic-y += trace_clock.h |
| @@ -1,6 +0,0 @@ | ||
| 1 | −#ifndef _ALPHA_SCATTERLIST_H | |
| 2 | −#define _ALPHA_SCATTERLIST_H | |
| 3 | − | |
| 4 | −#include <asm-generic/scatterlist.h> | |
| 5 | − | |
| 6 | −#endif /* !(_ALPHA_SCATTERLIST_H) */ | |
| @@ -296,7 +296,7 @@ struct cpuinfo_arc_mmu { · 295 unmodified lines | ||
| 296 | 296 | }; |
| 297 | 297 | |
| 298 | 298 | struct cpuinfo_arc_cache { |
| 299 | − unsigned int sz, line_len, assoc, ver; | |
| 299 | + unsigned int sz_k:8, line_len:8, assoc:4, ver:4, alias:1, vipt:1, pad:6; | |
| 300 | 300 | }; |
| 301 | 301 | |
| 302 | 302 | struct cpuinfo_arc_ccm { |
| @@ -16,9 +16,13 @@ · 15 unmodified lines | ||
| 16 | 16 | #define TIMER0_IRQ 3 |
| 17 | 17 | #define TIMER1_IRQ 4 |
| 18 | 18 | |
| 19 | +#include <linux/interrupt.h> | |
| 19 | 20 | #include <asm-generic/irq.h> |
| 20 | 21 | |
| 21 | 22 | extern void arc_init_IRQ(void); |
| 22 | 23 | void arc_local_timer_setup(void); |
| 24 | +void arc_request_percpu_irq(int irq, int cpu, | |
| 25 | + irqreturn_t (*isr)(int irq, void *dev), | |
| 26 | + const char *irq_nm, void *percpu_dev); | |
| 23 | 27 | |
| 24 | 28 | #endif |
| @@ -131,24 +131,6 @@ static inline int arch_irqs_disabled(void) · 130 unmodified lines | ||
| 131 | 131 | return arch_irqs_disabled_flags(arch_local_save_flags()); |
| 132 | 132 | } |
| 133 | 133 | |
| 134 | −static inline void arch_mask_irq(unsigned int irq) | |
| 135 | −{ | |
| 136 | − unsigned int ienb; | |
| 137 | − | |
| 138 | − ienb = read_aux_reg(AUX_IENABLE); | |
| 139 | − ienb &= ~(1 << irq); | |
| 140 | − write_aux_reg(AUX_IENABLE, ienb); | |
| 141 | −} | |
| 142 | − | |
| 143 | −static inline void arch_unmask_irq(unsigned int irq) | |
| 144 | −{ | |
| 145 | − unsigned int ienb; | |
| 146 | − | |
| 147 | − ienb = read_aux_reg(AUX_IENABLE); | |
| 148 | − ienb |= (1 << irq); | |
| 149 | − write_aux_reg(AUX_IENABLE, ienb); | |
| 150 | −} | |
| 151 | − | |
| 152 | 134 | #else |
| 153 | 135 | |
| 154 | 136 | #ifdef CONFIG_TRACE_IRQFLAGS |
| @@ -19,21 +19,16 @@ · 18 unmodified lines | ||
| 19 | 19 | |
| 20 | 20 | /* |
| 21 | 21 | * Early Hardware specific Interrupt setup |
| 22 | + * -Platform independent, needed for each CPU (not foldable into init_IRQ) | |
| 22 | 23 | * -Called very early (start_kernel -> setup_arch -> setup_processor) |
| 23 | − * -Platform Independent (must for any ARC700) | |
| 24 | − * -Needed for each CPU (hence not foldable into init_IRQ) | |
| 25 | 24 | * |
| 26 | 25 | * what it does ? |
| 27 | − * -Disable all IRQs (on CPU side) | |
| 28 | 26 | * -Optionally, setup the High priority Interrupts as Level 2 IRQs |
| 29 | 27 | */ |
| 30 | 28 | void arc_init_IRQ(void) |
| 31 | 29 | { |
| 32 | 30 | int level_mask = 0; |
| 33 | 31 | |
| 34 | − /* Disable all IRQs: enable them as devices request */ | |
| 35 | − write_aux_reg(AUX_IENABLE, 0); | |
| 36 | − | |
| 37 | 32 | /* setup any high priority Interrupts (Level2 in ARCompact jargon) */ |
| 38 | 33 | level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3; |
| 39 | 34 | level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5; |
| @@ -60,20 +55,28 @@ void arc_init_IRQ(void) · 20 unmodified lines | ||
| 60 | 55 | * below, per IRQ. |
| 61 | 56 | */ |
| 62 | 57 | |
| 63 | −static void arc_mask_irq(struct irq_data *data) | |
| 58 | +static void arc_irq_mask(struct irq_data *data) | |
| 64 | 59 | { |
| 65 | − arch_mask_irq(data->irq); | |
| 60 | + unsigned int ienb; | |
| 61 | + | |
| 62 | + ienb = read_aux_reg(AUX_IENABLE); | |
| 63 | + ienb &= ~(1 << data->irq); | |
| 64 | + write_aux_reg(AUX_IENABLE, ienb); | |
| 66 | 65 | } |
| 67 | 66 | |
| 68 | −static void arc_unmask_irq(struct irq_data *data) | |
| 67 | +static void arc_irq_unmask(struct irq_data *data) | |
| 69 | 68 | { |
| 70 | − arch_unmask_irq(data->irq); | |
| 69 | + unsigned int ienb; | |
| 70 | + | |
| 71 | + ienb = read_aux_reg(AUX_IENABLE); | |
| 72 | + ienb |= (1 << data->irq); | |
| 73 | + write_aux_reg(AUX_IENABLE, ienb); | |
| 71 | 74 | } |
| 72 | 75 | |
| 73 | 76 | static struct irq_chip onchip_intc = { |
| 74 | 77 | .name = "ARC In-core Intc", |
| 75 | − .irq_mask = arc_mask_irq, | |
| 76 | − .irq_unmask = arc_unmask_irq, | |
| 78 | + .irq_mask = arc_irq_mask, | |
| 79 | + .irq_unmask = arc_irq_unmask, | |
| 77 | 80 | }; |
| 78 | 81 | |
| 79 | 82 | static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq, |
| @@ -150,6 +153,32 @@ void arch_do_IRQ(unsigned int irq, struct pt_regs *regs) · 70 unmodified lines | ||
| 150 | 153 | set_irq_regs(old_regs); |
| 151 | 154 | } |
| 152 | 155 | |
| 156 | +void arc_request_percpu_irq(int irq, int cpu, | |
| 157 | + irqreturn_t (*isr)(int irq, void *dev), | |
| 158 | + const char *irq_nm, | |
| 159 | + void *percpu_dev) | |
| 160 | +{ | |
| 161 | + /* Boot cpu calls request, all call enable */ | |
| 162 | + if (!cpu) { | |
| 163 | + int rc; | |
| 164 | + | |
| 165 | + /* | |
| 166 | + * These 2 calls are essential to making percpu IRQ APIs work | |
| 167 | + * Ideally these details could be hidden in irq chip map function | |
| 168 | + * but the issue is IPIs IRQs being static (non-DT) and platform | |
| 169 | + * specific, so we can't identify them there. | |
| 170 | + */ | |
| 171 | + irq_set_percpu_devid(irq); | |
| 172 | + irq_modify_status(irq, IRQ_NOAUTOEN, 0); /* @irq, @clr, @set */ | |
| 173 | + | |
| 174 | + rc = request_percpu_irq(irq, isr, irq_nm, percpu_dev); | |
| 175 | + if (rc) | |
| 176 | + panic("Percpu IRQ request failed for %d\n", irq); | |
| 177 | + } | |
| 178 | + | |
| 179 | + enable_percpu_irq(irq, 0); | |
| 180 | +} | |
| 181 | + | |
| 153 | 182 | /* |
| 154 | 183 | * arch_local_irq_enable - Enable interrupts. |
| 155 | 184 | * |
| @@ -141,17 +141,13 @@ badframe: · 140 unmodified lines | ||
| 141 | 141 | /* |
| 142 | 142 | * Determine which stack to use.. |
| 143 | 143 | */ |
| 144 | −static inline void __user *get_sigframe(struct k_sigaction *ka, | |
| 144 | +static inline void __user *get_sigframe(struct ksignal *ksig, | |
| 145 | 145 | struct pt_regs *regs, |
| 146 | 146 | unsigned long framesize) |
| 147 | 147 | { |
| 148 | − unsigned long sp = regs->sp; | |
| 148 | + unsigned long sp = sigsp(regs->sp, ksig); | |
| 149 | 149 | void __user *frame; |
| 150 | 150 | |
| 151 | − /* This is the X/Open sanctioned signal stack switching */ | |
| 152 | − if ((ka->sa.sa_flags & SA_ONSTACK) && !sas_ss_flags(sp)) | |
| 153 | − sp = current->sas_ss_sp + current->sas_ss_size; | |
| 154 | − | |
| 155 | 151 | /* No matter what happens, 'sp' must be word |
| 156 | 152 | * aligned otherwise nasty things could happen |
| 157 | 153 | */ |
| @@ -179,14 +175,13 @@ static inline int map_sig(int sig) · 21 unmodified lines | ||
| 179 | 175 | } |
| 180 | 176 | |
| 181 | 177 | static int |
| 182 | −setup_rt_frame(int signo, struct k_sigaction *ka, siginfo_t *info, | |
| 183 | − sigset_t *set, struct pt_regs *regs) | |
| 178 | +setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs) | |
| 184 | 179 | { |
| 185 | 180 | struct rt_sigframe __user *sf; |
| 186 | 181 | unsigned int magic = 0; |
| 187 | 182 | int err = 0; |
| 188 | 183 | |
| 189 | − sf = get_sigframe(ka, regs, sizeof(struct rt_sigframe)); | |
| 184 | + sf = get_sigframe(ksig, regs, sizeof(struct rt_sigframe)); | |
| 190 | 185 | if (!sf) |
| 191 | 186 | return 1; |
| 192 | 187 | |
| @@ -205,8 +200,8 @@ setup_rt_frame(int signo, struct k_sigaction *ka, siginfo_t *info, · 12 unmodified lines | ||
| 205 | 200 | * #2: struct siginfo |
| 206 | 201 | * #3: struct ucontext (completely populated) |
| 207 | 202 | */ |
| 208 | − if (unlikely(ka->sa.sa_flags & SA_SIGINFO)) { | |
| 209 | − err |= copy_siginfo_to_user(&sf->info, info); | |
| 203 | + if (unlikely(ksig->ka.sa.sa_flags & SA_SIGINFO)) { | |
| 204 | + err |= copy_siginfo_to_user(&sf->info, &ksig->info); | |
| 210 | 205 | err |= __put_user(0, &sf->uc.uc_flags); |
| 211 | 206 | err |= __put_user(NULL, &sf->uc.uc_link); |
| 212 | 207 | err |= __save_altstack(&sf->uc.uc_stack, regs->sp); |
| @@ -227,16 +222,16 @@ setup_rt_frame(int signo, struct k_sigaction *ka, siginfo_t *info, · 14 unmodified lines | ||
| 227 | 222 | return err; |
| 228 | 223 | |
| 229 | 224 | /* #1 arg to the user Signal handler */ |
| 230 | − regs->r0 = map_sig(signo); | |
| 225 | + regs->r0 = map_sig(ksig->sig); | |
| 231 | 226 | |
| 232 | 227 | /* setup PC of user space signal handler */ |
| 233 | − regs->ret = (unsigned long)ka->sa.sa_handler; | |
| 228 | + regs->ret = (unsigned long)ksig->ka.sa.sa_handler; | |
| 234 | 229 | |
| 235 | 230 | /* |
| 236 | 231 | * handler returns using sigreturn stub provided already by userpsace |
| 237 | 232 | */ |
| 238 | − BUG_ON(!(ka->sa.sa_flags & SA_RESTORER)); | |
| 239 | − regs->blink = (unsigned long)ka->sa.sa_restorer; | |
| 233 | + BUG_ON(!(ksig->ka.sa.sa_flags & SA_RESTORER)); | |
| 234 | + regs->blink = (unsigned long)ksig->ka.sa.sa_restorer; | |
| 240 | 235 | |
| 241 | 236 | /* User Stack for signal handler will be above the frame just carved */ |
| 242 | 237 | regs->sp = (unsigned long)sf; |
| @@ -298,38 +293,30 @@ static void arc_restart_syscall(struct k_sigaction *ka, struct pt_regs *regs) · 55 unmodified lines | ||
| 298 | 293 | * OK, we're invoking a handler |
| 299 | 294 | */ |
| 300 | 295 | static void |
| 301 | −handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info, | |
| 302 | − struct pt_regs *regs) | |
| 296 | +handle_signal(struct ksignal *ksig, struct pt_regs *regs) | |
| 303 | 297 | { |
| 304 | 298 | sigset_t *oldset = sigmask_to_save(); |
| 305 | 299 | int ret; |
| 306 | 300 | |
| 307 | 301 | /* Set up the stack frame */ |
| 308 | − ret = setup_rt_frame(sig, ka, info, oldset, regs); | |
| 302 | + ret = setup_rt_frame(ksig, oldset, regs); | |
| 309 | 303 | |
| 310 | − if (ret) | |
| 311 | − force_sigsegv(sig, current); | |
| 312 | − else | |
| 313 | − signal_delivered(sig, info, ka, regs, 0); | |
| 304 | + signal_setup_done(ret, ksig, 0); | |
| 314 | 305 | } |
| 315 | 306 | |
| 316 | 307 | void do_signal(struct pt_regs *regs) |
| 317 | 308 | { |
| 318 | − struct k_sigaction ka; | |
| 319 | − siginfo_t info; | |
| 320 | − int signr; | |
| 309 | + struct ksignal ksig; | |
| 321 | 310 | int restart_scall; |
| 322 | 311 | |
| 323 | − signr = get_signal_to_deliver(&info, &ka, regs, NULL); | |
| 324 | − | |
| 325 | 312 | restart_scall = in_syscall(regs) && syscall_restartable(regs); |
| 326 | 313 | |
| 327 | − if (signr > 0) { | |
| 314 | + if (get_signal(&ksig)) { | |
| 328 | 315 | if (restart_scall) { |
| 329 | − arc_restart_syscall(&ka, regs); | |
| 316 | + arc_restart_syscall(&ksig.ka, regs); | |
| 330 | 317 | syscall_wont_restart(regs); /* No more restarts */ |
| 331 | 318 | } |
| 332 | − handle_signal(signr, &ka, &info, regs); | |
| 319 | + handle_signal(&ksig, regs); | |
| 333 | 320 | return; |
| 334 | 321 | } |
| 335 | 322 | |
| @@ -12,23 +12,15 @@ · 11 unmodified lines | ||
| 12 | 12 | * -- Initial Write (Borrowed heavily from ARM) |
| 13 | 13 | */ |
| 14 | 14 | |
| 15 | −#include <linux/module.h> | |
| 16 | −#include <linux/init.h> | |
| 17 | 15 | #include <linux/spinlock.h> |
| 18 | 16 | #include <linux/sched.h> |
| 19 | 17 | #include <linux/interrupt.h> |
| 20 | 18 | #include <linux/profile.h> |
| 21 | −#include <linux/errno.h> | |
| 22 | −#include <linux/err.h> | |
| 23 | 19 | #include <linux/mm.h> |
| 24 | 20 | #include <linux/cpu.h> |
| 25 | −#include <linux/smp.h> | |
| 26 | 21 | #include <linux/irq.h> |
| 27 | −#include <linux/delay.h> | |
| 28 | 22 | #include <linux/atomic.h> |
| 29 | −#include <linux/percpu.h> | |
| 30 | 23 | #include <linux/cpumask.h> |
| 31 | −#include <linux/spinlock_types.h> | |
| 32 | 24 | #include <linux/reboot.h> |
| 33 | 25 | #include <asm/processor.h> |
| 34 | 26 | #include <asm/setup.h> |
| @@ -136,7 +128,7 @@ void start_kernel_secondary(void) · 101 unmodified lines | ||
| 136 | 128 | pr_info("## CPU%u LIVE ##: Executing Code...\n", cpu); |
| 137 | 129 | |
| 138 | 130 | if (machine_desc->init_smp) |
| 139 | − machine_desc->init_smp(smp_processor_id()); | |
| 131 | + machine_desc->init_smp(cpu); | |
| 140 | 132 | |
| 141 | 133 | arc_local_timer_setup(); |
| 142 | 134 | |
| @@ -338,18 +330,11 @@ irqreturn_t do_IPI(int irq, void *dev_id) · 195 unmodified lines | ||
| 338 | 330 | */ |
| 339 | 331 | static DEFINE_PER_CPU(int, ipi_dev); |
| 340 | 332 | |
| 341 | −static struct irqaction arc_ipi_irq = { | |
| 342 | − .name = "IPI Interrupt", | |
| 343 | − .flags = IRQF_PERCPU, | |
| 344 | − .handler = do_IPI, | |
| 345 | −}; | |
| 346 | − | |
| 347 | 333 | int smp_ipi_irq_setup(int cpu, int irq) |
| 348 | 334 | { |
| 349 | − if (!cpu) | |
| 350 | − return setup_irq(irq, &arc_ipi_irq); | |
| 351 | − else | |
| 352 | − arch_unmask_irq(irq); | |
| 335 | + int *dev = per_cpu_ptr(&ipi_dev, cpu); | |
| 336 | + | |
| 337 | + arc_request_percpu_irq(irq, cpu, do_IPI, "IPI Interrupt", dev); | |
| 353 | 338 | |
| 354 | 339 | return 0; |
| 355 | 340 | } |
| @@ -144,12 +144,12 @@ static struct clocksource arc_counter = { · 143 unmodified lines | ||
| 144 | 144 | /********** Clock Event Device *********/ |
| 145 | 145 | |
| 146 | 146 | /* |
| 147 | − * Arm the timer to interrupt after @limit cycles | |
| 147 | + * Arm the timer to interrupt after @cycles | |
| 148 | 148 | * The distinction for oneshot/periodic is done in arc_event_timer_ack() below |
| 149 | 149 | */ |
| 150 | −static void arc_timer_event_setup(unsigned int limit) | |
| 150 | +static void arc_timer_event_setup(unsigned int cycles) | |
| 151 | 151 | { |
| 152 | − write_aux_reg(ARC_REG_TIMER0_LIMIT, limit); | |
| 152 | + write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); | |
| 153 | 153 | write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ |
| 154 | 154 | |
| 155 | 155 | write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); |
| @@ -168,6 +168,10 @@ static void arc_clkevent_set_mode(enum clock_event_mode mode, · 12 unmodified lines | ||
| 168 | 168 | { |
| 169 | 169 | switch (mode) { |
| 170 | 170 | case CLOCK_EVT_MODE_PERIODIC: |
| 171 | + /* | |
| 172 | + * At X Hz, 1 sec = 1000ms -> X cycles; | |
| 173 | + * 10ms -> X / 100 cycles | |
| 174 | + */ | |
| 171 | 175 | arc_timer_event_setup(arc_get_core_freq() / HZ); |
| 172 | 176 | break; |
| 173 | 177 | case CLOCK_EVT_MODE_ONESHOT: |
| @@ -210,12 +214,6 @@ static irqreturn_t timer_irq_handler(int irq, void *dev_id) · 36 unmodified lines | ||
| 210 | 214 | return IRQ_HANDLED; |
| 211 | 215 | } |
| 212 | 216 | |
| 213 | −static struct irqaction arc_timer_irq = { | |
| 214 | − .name = "Timer0 (clock-evt-dev)", | |
| 215 | − .flags = IRQF_TIMER | IRQF_PERCPU, | |
| 216 | − .handler = timer_irq_handler, | |
| 217 | −}; | |
| 218 | − | |
| 219 | 217 | /* |
| 220 | 218 | * Setup the local event timer for @cpu |
| 221 | 219 | */ |
| @@ -228,15 +226,9 @@ void arc_local_timer_setup() · 6 unmodified lines | ||
| 228 | 226 | clockevents_config_and_register(evt, arc_get_core_freq(), |
| 229 | 227 | 0, ARC_TIMER_MAX); |
| 230 | 228 | |
| 231 | − /* | |
| 232 | − * setup the per-cpu timer IRQ handler - for all cpus | |
| 233 | − * For non boot CPU explicitly unmask at intc | |
| 234 | − * setup_irq() -> .. -> irq_startup() already does this on boot-cpu | |
| 235 | − */ | |
| 236 | − if (!cpu) | |
| 237 | − setup_irq(TIMER0_IRQ, &arc_timer_irq); | |
| 238 | − else | |
| 239 | − arch_unmask_irq(TIMER0_IRQ); | |
| 229 | + /* setup the per-cpu timer IRQ handler - for all cpus */ | |
| 230 | + arc_request_percpu_irq(TIMER0_IRQ, cpu, timer_irq_handler, | |
| 231 | + "Timer0 (per-cpu-tick)", evt); | |
| 240 | 232 | } |
| 241 | 233 | |
| 242 | 234 | /* |
| @@ -77,21 +77,19 @@ char *arc_cache_mumbojumbo(int c, char *buf, int len) · 76 unmodified lines | ||
| 77 | 77 | { |
| 78 | 78 | int n = 0; |
| 79 | 79 | |
| 80 | −#define PR_CACHE(p, enb, str) \ | |
| 81 | −{ \ | |
| 80 | +#define PR_CACHE(p, cfg, str) \ | |
| 82 | 81 | if (!(p)->ver) \ |
| 83 | 82 | n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \ |
| 84 | 83 | else \ |
| 85 | 84 | n += scnprintf(buf + n, len - n, \ |
| 86 | − str"\t\t: (%uK) VIPT, %dway set-asc, %ub Line %s\n", \ | |
| 87 | − TO_KB((p)->sz), (p)->assoc, (p)->line_len, \ | |
| 88 | − enb ? "" : "DISABLED (kernel-build)"); \ | |
| 89 | −} | |
| 85 | + str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \ | |
| 86 | + (p)->sz_k, (p)->assoc, (p)->line_len, \ | |
| 87 | + (p)->vipt ? "VIPT" : "PIPT", \ | |
| 88 | + (p)->alias ? " aliasing" : "", \ | |
| 89 | + IS_ENABLED(cfg) ? "" : " (not used)"); | |
| 90 | 90 | |
| 91 | − PR_CACHE(&cpuinfo_arc700[c].icache, IS_ENABLED(CONFIG_ARC_HAS_ICACHE), | |
| 92 | − "I-Cache"); | |
| 93 | − PR_CACHE(&cpuinfo_arc700[c].dcache, IS_ENABLED(CONFIG_ARC_HAS_DCACHE), | |
| 94 | − "D-Cache"); | |
| 91 | + PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache"); | |
| 92 | + PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache"); | |
| 95 | 93 | |
| 96 | 94 | return buf; |
| 97 | 95 | } |
| @@ -116,20 +114,31 @@ void read_decode_cache_bcr(void) · 18 unmodified lines | ||
| 116 | 114 | p_ic = &cpuinfo_arc700[cpu].icache; |
| 117 | 115 | READ_BCR(ARC_REG_IC_BCR, ibcr); |
| 118 | 116 | |
| 117 | + if (!ibcr.ver) | |
| 118 | + goto dc_chk; | |
| 119 | + | |
| 119 | 120 | BUG_ON(ibcr.config != 3); |
| 120 | 121 | p_ic->assoc = 2; /* Fixed to 2w set assoc */ |
| 121 | 122 | p_ic->line_len = 8 << ibcr.line_len; |
| 122 | − p_ic->sz = 0x200 << ibcr.sz; | |
| 123 | + p_ic->sz_k = 1 << (ibcr.sz - 1); | |
| 123 | 124 | p_ic->ver = ibcr.ver; |
| 125 | + p_ic->vipt = 1; | |
| 126 | + p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1; | |
| 124 | 127 | |
| 128 | +dc_chk: | |
| 125 | 129 | p_dc = &cpuinfo_arc700[cpu].dcache; |
| 126 | 130 | READ_BCR(ARC_REG_DC_BCR, dbcr); |
| 127 | 131 | |
| 132 | + if (!dbcr.ver) | |
| 133 | + return; | |
| 134 | + | |
| 128 | 135 | BUG_ON(dbcr.config != 2); |
| 129 | 136 | p_dc->assoc = 4; /* Fixed to 4w set assoc */ |
| 130 | 137 | p_dc->line_len = 16 << dbcr.line_len; |
| 131 | − p_dc->sz = 0x200 << dbcr.sz; | |
| 138 | + p_dc->sz_k = 1 << (dbcr.sz - 1); | |
| 132 | 139 | p_dc->ver = dbcr.ver; |
| 140 | + p_dc->vipt = 1; | |
| 141 | + p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1; | |
| 133 | 142 | } |
| 134 | 143 | |
| 135 | 144 | /* |
| @@ -142,14 +151,16 @@ void read_decode_cache_bcr(void) · 6 unmodified lines | ||
| 142 | 151 | void arc_cache_init(void) |
| 143 | 152 | { |
| 144 | 153 | unsigned int __maybe_unused cpu = smp_processor_id(); |
| 145 | − struct cpuinfo_arc_cache __maybe_unused *ic, __maybe_unused *dc; | |
| 146 | 154 | char str[256]; |
| 147 | 155 | |
| 148 | 156 | printk(arc_cache_mumbojumbo(0, str, sizeof(str))); |
| 149 | 157 | |
| 150 | −#ifdef CONFIG_ARC_HAS_ICACHE | |
| 151 | − ic = &cpuinfo_arc700[cpu].icache; | |
| 152 | − if (ic->ver) { | |
| 158 | + if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { | |
| 159 | + struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; | |
| 160 | + | |
| 161 | + if (!ic->ver) | |
| 162 | + panic("cache support enabled but non-existent cache\n"); | |
| 163 | + | |
| 153 | 164 | if (ic->line_len != L1_CACHE_BYTES) |
| 154 | 165 | panic("ICache line [%d] != kernel Config [%d]", |
| 155 | 166 | ic->line_len, L1_CACHE_BYTES); |
| @@ -158,26 +169,26 @@ void arc_cache_init(void) · 2 unmodified lines | ||
| 158 | 169 | panic("Cache ver [%d] doesn't match MMU ver [%d]\n", |
| 159 | 170 | ic->ver, CONFIG_ARC_MMU_VER); |
| 160 | 171 | } |
| 161 | −#endif | |
| 162 | 172 | |
| 163 | −#ifdef CONFIG_ARC_HAS_DCACHE | |
| 164 | − dc = &cpuinfo_arc700[cpu].dcache; | |
| 165 | − if (dc->ver) { | |
| 166 | − unsigned int dcache_does_alias; | |
| 173 | + if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { | |
| 174 | + struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; | |
| 175 | + int handled; | |
| 176 | + | |
| 177 | + if (!dc->ver) | |
| 178 | + panic("cache support enabled but non-existent cache\n"); | |
| 167 | 179 | |
| 168 | 180 | if (dc->line_len != L1_CACHE_BYTES) |
| 169 | 181 | panic("DCache line [%d] != kernel Config [%d]", |
| 170 | 182 | dc->line_len, L1_CACHE_BYTES); |
| 171 | 183 | |
| 172 | 184 | /* check for D-Cache aliasing */ |
| 173 | − dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE; | |
| 185 | + handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); | |
| 174 | 186 | |
| 175 | − if (dcache_does_alias && !cache_is_vipt_aliasing()) | |
| 187 | + if (dc->alias && !handled) | |
| 176 | 188 | panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); |
| 177 | − else if (!dcache_does_alias && cache_is_vipt_aliasing()) | |
| 189 | + else if (!dc->alias && handled) | |
| 178 | 190 | panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n"); |
| 179 | 191 | } |
| 180 | −#endif | |
| 181 | 192 | } |
| 182 | 193 | |
| 183 | 194 | #define OP_INV 0x1 |
| @@ -255,10 +266,32 @@ static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr, · 71 unmodified lines | ||
| 255 | 266 | * Machine specific helpers for Entire D-Cache or Per Line ops |
| 256 | 267 | */ |
| 257 | 268 | |
| 258 | −static inline void wait_for_flush(void) | |
| 269 | +static unsigned int __before_dc_op(const int op) | |
| 270 | +{ | |
| 271 | + unsigned int reg = reg; | |
| 272 | + | |
| 273 | + if (op == OP_FLUSH_N_INV) { | |
| 274 | + /* Dcache provides 2 cmd: FLUSH or INV | |
| 275 | + * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE | |
| 276 | + * flush-n-inv is achieved by INV cmd but with IM=1 | |
| 277 | + * So toggle INV sub-mode depending on op request and default | |
| 278 | + */ | |
| 279 | + reg = read_aux_reg(ARC_REG_DC_CTRL); | |
| 280 | + write_aux_reg(ARC_REG_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH) | |
| 281 | + ; | |
| 282 | + } | |
| 283 | + | |
| 284 | + return reg; | |
| 285 | +} | |
| 286 | + | |
| 287 | +static void __after_dc_op(const int op, unsigned int reg) | |
| 259 | 288 | { |
| 260 | − while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS) | |
| 261 | − ; | |
| 289 | + if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ | |
| 290 | + while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS); | |
| 291 | + | |
| 292 | + /* Switch back to default Invalidate mode */ | |
| 293 | + if (op == OP_FLUSH_N_INV) | |
| 294 | + write_aux_reg(ARC_REG_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH); | |
| 262 | 295 | } |
| 263 | 296 | |
| 264 | 297 | /* |
| @@ -269,18 +302,10 @@ static inline void wait_for_flush(void) · 4 unmodified lines | ||
| 269 | 302 | */ |
| 270 | 303 | static inline void __dc_entire_op(const int cacheop) |
| 271 | 304 | { |
| 272 | − unsigned int tmp = tmp; | |
| 305 | + unsigned int ctrl_reg; | |
| 273 | 306 | int aux; |
| 274 | 307 | |
| 275 | − if (cacheop == OP_FLUSH_N_INV) { | |
| 276 | − /* Dcache provides 2 cmd: FLUSH or INV | |
| 277 | − * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE | |
| 278 | − * flush-n-inv is achieved by INV cmd but with IM=1 | |
| 279 | − * Default INV sub-mode is DISCARD, which needs to be toggled | |
| 280 | − */ | |
| 281 | − tmp = read_aux_reg(ARC_REG_DC_CTRL); | |
| 282 | − write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH); | |
| 283 | − } | |
| 308 | + ctrl_reg = __before_dc_op(cacheop); | |
| 284 | 309 | |
| 285 | 310 | if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ |
| 286 | 311 | aux = ARC_REG_DC_IVDC; |
| @@ -289,12 +314,7 @@ static inline void __dc_entire_op(const int cacheop) · 2 unmodified lines | ||
| 289 | 314 | |
| 290 | 315 | write_aux_reg(aux, 0x1); |
| 291 | 316 | |
| 292 | − if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */ | |
| 293 | − wait_for_flush(); | |
| 294 | − | |
| 295 | − /* Switch back the DISCARD ONLY Invalidate mode */ | |
| 296 | − if (cacheop == OP_FLUSH_N_INV) | |
| 297 | − write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH); | |
| 317 | + __after_dc_op(cacheop, ctrl_reg); | |
| 298 | 318 | } |
| 299 | 319 | |
| 300 | 320 | /* For kernel mappings cache operation: index is same as paddr */ |
| @@ -306,29 +326,16 @@ static inline void __dc_entire_op(const int cacheop) · 5 unmodified lines | ||
| 306 | 326 | static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr, |
| 307 | 327 | unsigned long sz, const int cacheop) |
| 308 | 328 | { |
| 309 | − unsigned long flags, tmp = tmp; | |
| 329 | + unsigned long flags; | |
| 330 | + unsigned int ctrl_reg; | |
| 310 | 331 | |
| 311 | 332 | local_irq_save(flags); |
| 312 | 333 | |
| 313 | − if (cacheop == OP_FLUSH_N_INV) { | |
| 314 | − /* | |
| 315 | − * Dcache provides 2 cmd: FLUSH or INV | |
| 316 | − * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE | |
| 317 | − * flush-n-inv is achieved by INV cmd but with IM=1 | |
| 318 | − * Default INV sub-mode is DISCARD, which needs to be toggled | |
| 319 | − */ | |
| 320 | − tmp = read_aux_reg(ARC_REG_DC_CTRL); | |
| 321 | − write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH); | |
| 322 | − } | |
| 334 | + ctrl_reg = __before_dc_op(cacheop); | |
| 323 | 335 | |
| 324 | 336 | __cache_line_loop(paddr, vaddr, sz, cacheop); |
| 325 | 337 | |
| 326 | − if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */ | |
| 327 | − wait_for_flush(); | |
| 328 | − | |
| 329 | − /* Switch back the DISCARD ONLY Invalidate mode */ | |
| 330 | − if (cacheop == OP_FLUSH_N_INV) | |
| 331 | − write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH); | |
| 338 | + __after_dc_op(cacheop, ctrl_reg); | |
| 332 | 339 | |
| 333 | 340 | local_irq_restore(flags); |
| 334 | 341 | } |
| @@ -389,8 +396,16 @@ static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr, · 54 unmodified lines | ||
| 389 | 396 | /*********************************************************** |
| 390 | 397 | * Machine specific helper for per line I-Cache invalidate. |
| 391 | 398 | */ |
| 392 | −static void __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr, | |
| 393 | − unsigned long sz) | |
| 399 | + | |
| 400 | +static inline void __ic_entire_inv(void) | |
| 401 | +{ | |
| 402 | + write_aux_reg(ARC_REG_IC_IVIC, 1); | |
| 403 | + read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ | |
| 404 | +} | |
| 405 | + | |
| 406 | +static inline void | |
| 407 | +__ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr, | |
| 408 | + unsigned long sz) | |
| 394 | 409 | { |
| 395 | 410 | unsigned long flags; |
| 396 | 411 | |
| @@ -399,30 +414,39 @@ static void __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr, · 2 unmodified lines | ||
| 399 | 414 | local_irq_restore(flags); |
| 400 | 415 | } |
| 401 | 416 | |
| 402 | −static inline void __ic_entire_inv(void) | |
| 403 | −{ | |
| 404 | − write_aux_reg(ARC_REG_IC_IVIC, 1); | |
| 405 | − read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ | |
| 406 | −} | |
| 417 | +#ifndef CONFIG_SMP | |
| 418 | + | |
| 419 | +#define __ic_line_inv_vaddr(p, v, s) __ic_line_inv_vaddr_local(p, v, s) | |
| 407 | 420 | |
| 408 | −struct ic_line_inv_vaddr_ipi { | |
| 421 | +#else | |
| 422 | + | |
| 423 | +struct ic_inv_args { | |
| 409 | 424 | unsigned long paddr, vaddr; |
| 410 | 425 | int sz; |
| 411 | 426 | }; |
| 412 | 427 | |
| 413 | 428 | static void __ic_line_inv_vaddr_helper(void *info) |
| 414 | 429 | { |
| 415 | − struct ic_line_inv_vaddr_ipi *ic_inv = (struct ic_line_inv_vaddr_ipi*) info; | |
| 430 | + struct ic_inv *ic_inv_args = (struct ic_inv_args *) info; | |
| 431 | + | |
| 416 | 432 | __ic_line_inv_vaddr_local(ic_inv->paddr, ic_inv->vaddr, ic_inv->sz); |
| 417 | 433 | } |
| 418 | 434 | |
| 419 | 435 | static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr, |
| 420 | 436 | unsigned long sz) |
| 421 | 437 | { |
| 422 | − struct ic_line_inv_vaddr_ipi ic_inv = { paddr, vaddr , sz}; | |
| 438 | + struct ic_inv_args ic_inv = { | |
| 439 | + .paddr = paddr, | |
| 440 | + .vaddr = vaddr, | |
| 441 | + .sz = sz | |
| 442 | + }; | |
| 443 | + | |
| 423 | 444 | on_each_cpu(__ic_line_inv_vaddr_helper, &ic_inv, 1); |
| 424 | 445 | } |
| 425 | −#else | |
| 446 | + | |
| 447 | +#endif /* CONFIG_SMP */ | |
| 448 | + | |
| 449 | +#else /* !CONFIG_ARC_HAS_ICACHE */ | |
| 426 | 450 | |
| 427 | 451 | #define __ic_entire_inv() |
| 428 | 452 | #define __ic_line_inv_vaddr(pstart, vstart, sz) |
| @@ -159,7 +159,6 @@ good_area: · 158 unmodified lines | ||
| 159 | 159 | return; |
| 160 | 160 | } |
| 161 | 161 | |
| 162 | − /* TBD: switch to pagefault_out_of_memory() */ | |
| 163 | 162 | if (fault & VM_FAULT_OOM) |
| 164 | 163 | goto out_of_memory; |
| 165 | 164 | else if (fault & VM_FAULT_SIGBUS) |
| @@ -220,9 +220,9 @@ ex_saved_reg1: · 219 unmodified lines | ||
| 220 | 220 | |
| 221 | 221 | .macro CONV_PTE_TO_TLB |
| 222 | 222 | and r3, r0, PTE_BITS_RWX ; r w x |
| 223 | − lsl r2, r3, 3 ; r w x 0 0 0 | |
| 223 | + lsl r2, r3, 3 ; r w x 0 0 0 (GLOBAL, kernel only) | |
| 224 | 224 | and.f 0, r0, _PAGE_GLOBAL |
| 225 | − or.z r2, r2, r3 ; r w x r w x | |
| 225 | + or.z r2, r2, r3 ; r w x r w x (!GLOBAL, user page) | |
| 226 | 226 | |
| 227 | 227 | and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE |
| 228 | 228 | or r3, r3, r2 |
| @@ -8,5 +8,5 @@ · 7 unmodified lines | ||
| 8 | 8 | |
| 9 | 9 | KBUILD_CFLAGS += -Iarch/arc/plat-arcfpga/include |
| 10 | 10 | |
| 11 | −obj-y := platform.o irq.o | |
| 11 | +obj-y := platform.o | |
| 12 | 12 | obj-$(CONFIG_ISS_SMP_EXTN) += smp.o |
| @@ -24,6 +24,4 @@ · 23 unmodified lines | ||
| 24 | 24 | #define IDU_INTERRUPT_0 16 |
| 25 | 25 | #endif |
| 26 | 26 | |
| 27 | −extern void __init plat_fpga_init_IRQ(void); | |
| 28 | − | |
| 29 | 27 | #endif |
| @@ -1,25 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * ARC FPGA Platform IRQ hookups | |
| 3 | − * | |
| 4 | − * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com) | |
| 5 | − * | |
| 6 | − * This program is free software; you can redistribute it and/or modify | |
| 7 | − * it under the terms of the GNU General Public License version 2 as | |
| 8 | − * published by the Free Software Foundation. | |
| 9 | − */ | |
| 10 | − | |
| 11 | −#include <linux/interrupt.h> | |
| 12 | −#include <plat/irq.h> | |
| 13 | − | |
| 14 | −void __init plat_fpga_init_IRQ(void) | |
| 15 | −{ | |
| 16 | − /* | |
| 17 | − * SMP Hack because UART IRQ hardwired to cpu0 (boot-cpu) but if the | |
| 18 | − * request_irq() comes from any other CPU, the low level IRQ unamsking | |
| 19 | − * essential for getting Interrupts won't be enabled on cpu0, locking | |
| 20 | − * up the UART state machine. | |
| 21 | − */ | |
| 22 | −#ifdef CONFIG_SMP | |
| 23 | − arch_unmask_irq(UART0_IRQ); | |
| 24 | −#endif | |
| 25 | −} | |
| @@ -57,7 +57,6 @@ MACHINE_START(ANGEL4, "angel4") · 56 unmodified lines | ||
| 57 | 57 | .dt_compat = aa4_compat, |
| 58 | 58 | .init_early = plat_fpga_early_init, |
| 59 | 59 | .init_machine = plat_fpga_populate_dev, |
| 60 | − .init_irq = plat_fpga_init_IRQ, | |
| 61 | 60 | #ifdef CONFIG_ISS_SMP_EXTN |
| 62 | 61 | .init_smp = iss_model_init_smp, |
| 63 | 62 | #endif |
| @@ -72,7 +71,6 @@ MACHINE_START(ML509, "ml509") · 8 unmodified lines | ||
| 72 | 71 | .dt_compat = ml509_compat, |
| 73 | 72 | .init_early = plat_fpga_early_init, |
| 74 | 73 | .init_machine = plat_fpga_populate_dev, |
| 75 | − .init_irq = plat_fpga_init_IRQ, | |
| 76 | 74 | #ifdef CONFIG_SMP |
| 77 | 75 | .init_smp = iss_model_init_smp, |
| 78 | 76 | #endif |
| @@ -87,5 +85,4 @@ MACHINE_START(NSIMOSCI, "nsimosci") · 8 unmodified lines | ||
| 87 | 85 | .dt_compat = nsimosci_compat, |
| 88 | 86 | .init_early = NULL, |
| 89 | 87 | .init_machine = plat_fpga_populate_dev, |
| 90 | − .init_irq = NULL, | |
| 91 | 88 | MACHINE_END |
| @@ -83,6 +83,7 @@ config ARM · 82 unmodified lines | ||
| 83 | 83 | <http://www.arm.linux.org.uk/>. |
| 84 | 84 | |
| 85 | 85 | config ARM_HAS_SG_CHAIN |
| 86 | + select ARCH_HAS_SG_CHAIN | |
| 86 | 87 | bool |
| 87 | 88 | |
| 88 | 89 | config NEED_SG_DMA_LENGTH |
| @@ -239,13 +240,6 @@ config ARM_PATCH_PHYS_VIRT · 150 unmodified lines | ||
| 239 | 240 | this feature (eg, building a kernel for a single machine) and |
| 240 | 241 | you need to shrink the kernel to the minimal size. |
| 241 | 242 | |
| 242 | −config NEED_MACH_GPIO_H | |
| 243 | − bool | |
| 244 | − help | |
| 245 | − Select this when mach/gpio.h is required to provide special | |
| 246 | − definitions for this platform. The need for mach/gpio.h should | |
| 247 | − be avoided when possible. | |
| 248 | − | |
| 249 | 243 | config NEED_MACH_IO_H |
| 250 | 244 | bool |
| 251 | 245 | help |
| @@ -334,7 +328,6 @@ config ARCH_INTEGRATOR · 82 unmodified lines | ||
| 334 | 328 | select HAVE_TCM |
| 335 | 329 | select ICST |
| 336 | 330 | select MULTI_IRQ_HANDLER |
| 337 | − select NEED_MACH_MEMORY_H | |
| 338 | 331 | select PLAT_VERSATILE |
| 339 | 332 | select SPARSE_IRQ |
| 340 | 333 | select USE_OF |
| @@ -354,7 +347,6 @@ config ARCH_REALVIEW · 13 unmodified lines | ||
| 354 | 347 | select ICST |
| 355 | 348 | select NEED_MACH_MEMORY_H |
| 356 | 349 | select PLAT_VERSATILE |
| 357 | − select PLAT_VERSATILE_CLCD | |
| 358 | 350 | help |
| 359 | 351 | This enables support for ARM Ltd RealView boards. |
| 360 | 352 | |
| @@ -369,7 +361,6 @@ config ARCH_VERSATILE · 8 unmodified lines | ||
| 369 | 361 | select HAVE_MACH_CLKDEV |
| 370 | 362 | select ICST |
| 371 | 363 | select PLAT_VERSATILE |
| 372 | − select PLAT_VERSATILE_CLCD | |
| 373 | 364 | select PLAT_VERSATILE_CLOCK |
| 374 | 365 | select VERSATILE_FPGA_IRQ |
| 375 | 366 | help |
| @@ -541,21 +532,6 @@ config ARCH_DOVE · 165 unmodified lines | ||
| 541 | 532 | help |
| 542 | 533 | Support for the Marvell Dove SoC 88AP510 |
| 543 | 534 | |
| 544 | −config ARCH_KIRKWOOD | |
| 545 | − bool "Marvell Kirkwood" | |
| 546 | − select ARCH_REQUIRE_GPIOLIB | |
| 547 | − select CPU_FEROCEON | |
| 548 | − select GENERIC_CLOCKEVENTS | |
| 549 | − select MVEBU_MBUS | |
| 550 | − select PCI | |
| 551 | − select PCI_QUIRKS | |
| 552 | − select PINCTRL | |
| 553 | − select PINCTRL_KIRKWOOD | |
| 554 | − select PLAT_ORION_LEGACY | |
| 555 | − help | |
| 556 | − Support for the following Marvell Kirkwood series SoCs: | |
| 557 | − 88F6180, 88F6192 and 88F6281. | |
| 558 | − | |
| 559 | 535 | config ARCH_MV78XX0 |
| 560 | 536 | bool "Marvell MV78xx0" |
| 561 | 537 | select ARCH_REQUIRE_GPIOLIB |
| @@ -772,61 +748,6 @@ config ARCH_S3C64XX · 210 unmodified lines | ||
| 772 | 748 | help |
| 773 | 749 | Samsung S3C64XX series based systems |
| 774 | 750 | |
| 775 | −config ARCH_S5P64X0 | |
| 776 | − bool "Samsung S5P6440 S5P6450" | |
| 777 | − select ATAGS | |
| 778 | − select CLKDEV_LOOKUP | |
| 779 | − select CLKSRC_SAMSUNG_PWM | |
| 780 | − select CPU_V6 | |
| 781 | − select GENERIC_CLOCKEVENTS | |
| 782 | − select GPIO_SAMSUNG | |
| 783 | − select HAVE_S3C2410_I2C if I2C | |
| 784 | − select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
| 785 | − select HAVE_S3C_RTC if RTC_CLASS | |
| 786 | − select NEED_MACH_GPIO_H | |
| 787 | − select SAMSUNG_ATAGS | |
| 788 | − select SAMSUNG_WDT_RESET | |
| 789 | − help | |
| 790 | − Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, | |
| 791 | − SMDK6450. | |
| 792 | − | |
| 793 | −config ARCH_S5PC100 | |
| 794 | − bool "Samsung S5PC100" | |
| 795 | − select ARCH_REQUIRE_GPIOLIB | |
| 796 | − select ATAGS | |
| 797 | − select CLKDEV_LOOKUP | |
| 798 | − select CLKSRC_SAMSUNG_PWM | |
| 799 | − select CPU_V7 | |
| 800 | − select GENERIC_CLOCKEVENTS | |
| 801 | − select GPIO_SAMSUNG | |
| 802 | − select HAVE_S3C2410_I2C if I2C | |
| 803 | − select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
| 804 | − select HAVE_S3C_RTC if RTC_CLASS | |
| 805 | − select NEED_MACH_GPIO_H | |
| 806 | − select SAMSUNG_ATAGS | |
| 807 | − select SAMSUNG_WDT_RESET | |
| 808 | − help | |
| 809 | − Samsung S5PC100 series based systems | |
| 810 | − | |
| 811 | −config ARCH_S5PV210 | |
| 812 | − bool "Samsung S5PV210/S5PC110" | |
| 813 | − select ARCH_HAS_HOLES_MEMORYMODEL | |
| 814 | − select ARCH_SPARSEMEM_ENABLE | |
| 815 | − select ATAGS | |
| 816 | − select CLKDEV_LOOKUP | |
| 817 | − select CLKSRC_SAMSUNG_PWM | |
| 818 | − select CPU_V7 | |
| 819 | − select GENERIC_CLOCKEVENTS | |
| 820 | − select GPIO_SAMSUNG | |
| 821 | − select HAVE_S3C2410_I2C if I2C | |
| 822 | − select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
| 823 | − select HAVE_S3C_RTC if RTC_CLASS | |
| 824 | − select NEED_MACH_GPIO_H | |
| 825 | − select NEED_MACH_MEMORY_H | |
| 826 | − select SAMSUNG_ATAGS | |
| 827 | − help | |
| 828 | − Samsung S5PV210/S5PC110 series based systems | |
| 829 | − | |
| 830 | 751 | config ARCH_DAVINCI |
| 831 | 752 | bool "TI DaVinci" |
| 832 | 753 | select ARCH_HAS_HOLES_MEMORYMODEL |
| @@ -965,8 +886,6 @@ source "arch/arm/mach-ixp4xx/Kconfig" · 132 unmodified lines | ||
| 965 | 886 | |
| 966 | 887 | source "arch/arm/mach-keystone/Kconfig" |
| 967 | 888 | |
| 968 | −source "arch/arm/mach-kirkwood/Kconfig" | |
| 969 | − | |
| 970 | 889 | source "arch/arm/mach-ks8695/Kconfig" |
| 971 | 890 | |
| 972 | 891 | source "arch/arm/mach-msm/Kconfig" |
| @@ -977,6 +896,8 @@ source "arch/arm/mach-mv78xx0/Kconfig" · 4 unmodified lines | ||
| 977 | 896 | |
| 978 | 897 | source "arch/arm/mach-imx/Kconfig" |
| 979 | 898 | |
| 899 | +source "arch/arm/mach-mediatek/Kconfig" | |
| 900 | + | |
| 980 | 901 | source "arch/arm/mach-mxs/Kconfig" |
| 981 | 902 | |
| 982 | 903 | source "arch/arm/mach-netx/Kconfig" |
| @@ -1018,10 +939,6 @@ source "arch/arm/mach-s3c24xx/Kconfig" · 35 unmodified lines | ||
| 1018 | 939 | |
| 1019 | 940 | source "arch/arm/mach-s3c64xx/Kconfig" |
| 1020 | 941 | |
| 1021 | −source "arch/arm/mach-s5p64x0/Kconfig" | |
| 1022 | − | |
| 1023 | −source "arch/arm/mach-s5pc100/Kconfig" | |
| 1024 | − | |
| 1025 | 942 | source "arch/arm/mach-s5pv210/Kconfig" |
| 1026 | 943 | |
| 1027 | 944 | source "arch/arm/mach-exynos/Kconfig" |
| @@ -1568,10 +1485,12 @@ config ARM_PSCI · 540 unmodified lines | ||
| 1568 | 1485 | config ARCH_NR_GPIO |
| 1569 | 1486 | int |
| 1570 | 1487 | default 1024 if ARCH_SHMOBILE || ARCH_TEGRA |
| 1571 | − default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX | |
| 1488 | + default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ | |
| 1489 | + SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 | |
| 1572 | 1490 | default 416 if ARCH_SUNXI |
| 1573 | 1491 | default 392 if ARCH_U8500 |
| 1574 | 1492 | default 352 if ARCH_VT8500 |
| 1493 | + default 288 if ARCH_ROCKCHIP | |
| 1575 | 1494 | default 264 if MACH_H4700 |
| 1576 | 1495 | default 0 |
| 1577 | 1496 | help |
| @@ -1583,7 +1502,7 @@ source kernel/Kconfig.preempt · 5 unmodified lines | ||
| 1583 | 1502 | |
| 1584 | 1503 | config HZ_FIXED |
| 1585 | 1504 | int |
| 1586 | − default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ | |
| 1505 | + default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ | |
| 1587 | 1506 | ARCH_S5PV210 || ARCH_EXYNOS4 |
| 1588 | 1507 | default AT91_TIMER_HZ if ARCH_AT91 |
| 1589 | 1508 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY |
| @@ -2064,6 +1983,8 @@ config XIP_PHYS_ADDR · 474 unmodified lines | ||
| 2064 | 1983 | config KEXEC |
| 2065 | 1984 | bool "Kexec system call (EXPERIMENTAL)" |
| 2066 | 1985 | depends on (!SMP || PM_SLEEP_SMP) |
| 1986 | + select CRYPTO | |
| 1987 | + select CRYPTO_SHA256 | |
| 2067 | 1988 | help |
| 2068 | 1989 | kexec is a system call that implements the ability to shutdown your |
| 2069 | 1990 | current kernel, and to start another kernel. It is like a reboot |
| @@ -2208,7 +2129,6 @@ menu "Power management options" · 138 unmodified lines | ||
| 2208 | 2129 | source "kernel/power/Kconfig" |
| 2209 | 2130 | |
| 2210 | 2131 | config ARCH_SUSPEND_POSSIBLE |
| 2211 | − depends on !ARCH_S5PC100 | |
| 2212 | 2132 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
| 2213 | 2133 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
| 2214 | 2134 | def_bool y |
| @@ -223,6 +223,14 @@ choice · 222 unmodified lines | ||
| 223 | 223 | Say Y here if you want kernel low-level debugging support |
| 224 | 224 | on HI3716 UART. |
| 225 | 225 | |
| 226 | + config DEBUG_HIX5HD2_UART | |
| 227 | + bool "Hisilicon Hix5hd2 Debug UART" | |
| 228 | + depends on ARCH_HIX5HD2 | |
| 229 | + select DEBUG_UART_PL01X | |
| 230 | + help | |
| 231 | + Say Y here if you want kernel low-level debugging support | |
| 232 | + on Hix5hd2 UART. | |
| 233 | + | |
| 226 | 234 | config DEBUG_HIGHBANK_UART |
| 227 | 235 | bool "Kernel low-level debugging messages via Highbank UART" |
| 228 | 236 | depends on ARCH_HIGHBANK |
| @@ -582,7 +590,7 @@ choice · 353 unmodified lines | ||
| 582 | 590 | on Rockchip based platforms. |
| 583 | 591 | |
| 584 | 592 | config DEBUG_RK3X_UART0 |
| 585 | − bool "Kernel low-level debugging messages via Rockchip RK3X UART0" | |
| 593 | + bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART0" | |
| 586 | 594 | depends on ARCH_ROCKCHIP |
| 587 | 595 | select DEBUG_UART_8250 |
| 588 | 596 | help |
| @@ -590,7 +598,7 @@ choice · 1 unmodified line | ||
| 590 | 598 | on Rockchip based platforms. |
| 591 | 599 | |
| 592 | 600 | config DEBUG_RK3X_UART1 |
| 593 | − bool "Kernel low-level debugging messages via Rockchip RK3X UART1" | |
| 601 | + bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART1" | |
| 594 | 602 | depends on ARCH_ROCKCHIP |
| 595 | 603 | select DEBUG_UART_8250 |
| 596 | 604 | help |
| @@ -598,7 +606,7 @@ choice · 1 unmodified line | ||
| 598 | 606 | on Rockchip based platforms. |
| 599 | 607 | |
| 600 | 608 | config DEBUG_RK3X_UART2 |
| 601 | − bool "Kernel low-level debugging messages via Rockchip RK3X UART2" | |
| 609 | + bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART2" | |
| 602 | 610 | depends on ARCH_ROCKCHIP |
| 603 | 611 | select DEBUG_UART_8250 |
| 604 | 612 | help |
| @@ -606,64 +614,64 @@ choice · 1 unmodified line | ||
| 606 | 614 | on Rockchip based platforms. |
| 607 | 615 | |
| 608 | 616 | config DEBUG_RK3X_UART3 |
| 609 | − bool "Kernel low-level debugging messages via Rockchip RK3X UART3" | |
| 617 | + bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART3" | |
| 610 | 618 | depends on ARCH_ROCKCHIP |
| 611 | 619 | select DEBUG_UART_8250 |
| 612 | 620 | help |
| 613 | 621 | Say Y here if you want kernel low-level debugging support |
| 614 | 622 | on Rockchip based platforms. |
| 615 | 623 | |
| 624 | + config DEBUG_RK32_UART2 | |
| 625 | + bool "Kernel low-level debugging messages via Rockchip RK32 UART2" | |
| 626 | + depends on ARCH_ROCKCHIP | |
| 627 | + select DEBUG_UART_8250 | |
| 628 | + help | |
| 629 | + Say Y here if you want kernel low-level debugging support | |
| 630 | + on Rockchip RK32xx based platforms. | |
| 631 | + | |
| 616 | 632 | config DEBUG_S3C_UART0 |
| 617 | 633 | depends on PLAT_SAMSUNG |
| 618 | 634 | select DEBUG_EXYNOS_UART if ARCH_EXYNOS |
| 619 | 635 | select DEBUG_S3C24XX_UART if ARCH_S3C24XX |
| 620 | − bool "Use S3C UART 0 for low-level debug" | |
| 636 | + select DEBUG_S5PV210_UART if ARCH_S5PV210 | |
| 637 | + bool "Use Samsung S3C UART 0 for low-level debug" | |
| 621 | 638 | help |
| 622 | 639 | Say Y here if you want the debug print routines to direct |
| 623 | 640 | their output to UART 0. The port must have been initialised |
| 624 | 641 | by the boot-loader before use. |
| 625 | 642 | |
| 626 | − The uncompressor code port configuration is now handled | |
| 627 | − by CONFIG_S3C_LOWLEVEL_UART_PORT. | |
| 628 | − | |
| 629 | 643 | config DEBUG_S3C_UART1 |
| 630 | 644 | depends on PLAT_SAMSUNG |
| 631 | 645 | select DEBUG_EXYNOS_UART if ARCH_EXYNOS |
| 632 | 646 | select DEBUG_S3C24XX_UART if ARCH_S3C24XX |
| 633 | − bool "Use S3C UART 1 for low-level debug" | |
| 647 | + select DEBUG_S5PV210_UART if ARCH_S5PV210 | |
| 648 | + bool "Use Samsung S3C UART 1 for low-level debug" | |
| 634 | 649 | help |
| 635 | 650 | Say Y here if you want the debug print routines to direct |
| 636 | 651 | their output to UART 1. The port must have been initialised |
| 637 | 652 | by the boot-loader before use. |
| 638 | 653 | |
| 639 | − The uncompressor code port configuration is now handled | |
| 640 | − by CONFIG_S3C_LOWLEVEL_UART_PORT. | |
| 641 | − | |
| 642 | 654 | config DEBUG_S3C_UART2 |
| 643 | 655 | depends on PLAT_SAMSUNG |
| 644 | 656 | select DEBUG_EXYNOS_UART if ARCH_EXYNOS |
| 645 | 657 | select DEBUG_S3C24XX_UART if ARCH_S3C24XX |
| 646 | − bool "Use S3C UART 2 for low-level debug" | |
| 658 | + select DEBUG_S5PV210_UART if ARCH_S5PV210 | |
| 659 | + bool "Use Samsung S3C UART 2 for low-level debug" | |
| 647 | 660 | help |
| 648 | 661 | Say Y here if you want the debug print routines to direct |
| 649 | 662 | their output to UART 2. The port must have been initialised |
| 650 | 663 | by the boot-loader before use. |
| 651 | 664 | |
| 652 | − The uncompressor code port configuration is now handled | |
| 653 | − by CONFIG_S3C_LOWLEVEL_UART_PORT. | |
| 654 | − | |
| 655 | 665 | config DEBUG_S3C_UART3 |
| 656 | − depends on PLAT_SAMSUNG && ARCH_EXYNOS | |
| 657 | − select DEBUG_EXYNOS_UART | |
| 658 | − bool "Use S3C UART 3 for low-level debug" | |
| 666 | + depends on PLAT_SAMSUNG && (ARCH_EXYNOS || ARCH_S5PV210) | |
| 667 | + select DEBUG_EXYNOS_UART if ARCH_EXYNOS | |
| 668 | + select DEBUG_S5PV210_UART if ARCH_S5PV210 | |
| 669 | + bool "Use Samsung S3C UART 3 for low-level debug" | |
| 659 | 670 | help |
| 660 | 671 | Say Y here if you want the debug print routines to direct |
| 661 | 672 | their output to UART 3. The port must have been initialised |
| 662 | 673 | by the boot-loader before use. |
| 663 | 674 | |
| 664 | − The uncompressor code port configuration is now handled | |
| 665 | − by CONFIG_S3C_LOWLEVEL_UART_PORT. | |
| 666 | − | |
| 667 | 675 | config DEBUG_S3C2410_UART0 |
| 668 | 676 | depends on ARCH_S3C24XX |
| 669 | 677 | select DEBUG_S3C2410_UART |
| @@ -715,6 +723,14 @@ choice · 45 unmodified lines | ||
| 715 | 723 | Say Y here if you want kernel low-level debugging support |
| 716 | 724 | on Allwinner A1X based platforms on the UART1. |
| 717 | 725 | |
| 726 | + config DEBUG_SUNXI_R_UART | |
| 727 | + bool "Kernel low-level debugging messages via sunXi R_UART" | |
| 728 | + depends on MACH_SUN6I || MACH_SUN8I | |
| 729 | + select DEBUG_UART_8250 | |
| 730 | + help | |
| 731 | + Say Y here if you want kernel low-level debugging support | |
| 732 | + on Allwinner A31/A23 based platforms on the R_UART. | |
| 733 | + | |
| 718 | 734 | config TEGRA_DEBUG_UART_AUTO_ODMDATA |
| 719 | 735 | bool "Kernel low-level debugging messages via Tegra UART via ODMDATA" |
| 720 | 736 | depends on ARCH_TEGRA |
| @@ -949,6 +965,9 @@ config DEBUG_S3C2410_UART · 228 unmodified lines | ||
| 949 | 965 | config DEBUG_S3C24XX_UART |
| 950 | 966 | bool |
| 951 | 967 | |
| 968 | +config DEBUG_S5PV210_UART | |
| 969 | + bool | |
| 970 | + | |
| 952 | 971 | config DEBUG_OMAP2PLUS_UART |
| 953 | 972 | bool |
| 954 | 973 | depends on ARCH_OMAP2PLUS |
| @@ -991,6 +1010,7 @@ config DEBUG_STI_UART · 36 unmodified lines | ||
| 991 | 1010 | config DEBUG_LL_INCLUDE |
| 992 | 1011 | string |
| 993 | 1012 | default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250 |
| 1013 | + default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2 | |
| 994 | 1014 | default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X |
| 995 | 1015 | default "debug/exynos.S" if DEBUG_EXYNOS_UART |
| 996 | 1016 | default "debug/efm32.S" if DEBUG_LL_UART_EFM32 |
| @@ -1009,6 +1029,7 @@ config DEBUG_LL_INCLUDE · 12 unmodified lines | ||
| 1009 | 1029 | default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM |
| 1010 | 1030 | default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART |
| 1011 | 1031 | default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART |
| 1032 | + default "debug/s5pv210.S" if DEBUG_S5PV210_UART | |
| 1012 | 1033 | default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 |
| 1013 | 1034 | default "debug/sti.S" if DEBUG_STI_UART |
| 1014 | 1035 | default "debug/tegra.S" if DEBUG_TEGRA_UART |
| @@ -1033,7 +1054,7 @@ config DEBUG_UART_8250 · 18 unmodified lines | ||
| 1033 | 1054 | def_bool ARCH_DOVE || ARCH_EBSA110 || \ |
| 1034 | 1055 | (FOOTBRIDGE && !DEBUG_DC21285_PORT) || \ |
| 1035 | 1056 | ARCH_GEMINI || ARCH_IOP13XX || ARCH_IOP32X || \ |
| 1036 | − ARCH_IOP33X || ARCH_IXP4XX || ARCH_KIRKWOOD || \ | |
| 1057 | + ARCH_IOP33X || ARCH_IXP4XX || \ | |
| 1037 | 1058 | ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC |
| 1038 | 1059 | |
| 1039 | 1060 | config DEBUG_UART_PHYS |
| @@ -1043,6 +1064,7 @@ config DEBUG_UART_PHYS · 3 unmodified lines | ||
| 1043 | 1064 | default 0x01c28400 if DEBUG_SUNXI_UART1 |
| 1044 | 1065 | default 0x01d0c000 if DEBUG_DAVINCI_DA8XX_UART1 |
| 1045 | 1066 | default 0x01d0d000 if DEBUG_DAVINCI_DA8XX_UART2 |
| 1067 | + default 0x01f02800 if DEBUG_SUNXI_R_UART | |
| 1046 | 1068 | default 0x02530c00 if DEBUG_KEYSTONE_UART0 |
| 1047 | 1069 | default 0x02531000 if DEBUG_KEYSTONE_UART1 |
| 1048 | 1070 | default 0x03010fe0 if ARCH_RPC |
| @@ -1089,13 +1111,14 @@ config DEBUG_UART_PHYS · 40 unmodified lines | ||
| 1089 | 1111 | default 0xe0000000 if ARCH_SPEAR13XX |
| 1090 | 1112 | default 0xf0000be0 if ARCH_EBSA110 |
| 1091 | 1113 | default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE |
| 1092 | − default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \ | |
| 1114 | + default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \ | |
| 1093 | 1115 | ARCH_ORION5X |
| 1094 | 1116 | default 0xf7fc9000 if DEBUG_BERLIN_UART |
| 1095 | − default 0xf8b00000 if DEBUG_HI3716_UART | |
| 1117 | + default 0xf8b00000 if DEBUG_HIX5HD2_UART | |
| 1096 | 1118 | default 0xf991e000 if DEBUG_QCOM_UARTDM |
| 1097 | 1119 | default 0xfcb00000 if DEBUG_HI3620_UART |
| 1098 | 1120 | default 0xfe800000 if ARCH_IOP32X |
| 1121 | + default 0xff690000 if DEBUG_RK32_UART2 | |
| 1099 | 1122 | default 0xffc02000 if DEBUG_SOCFPGA_UART |
| 1100 | 1123 | default 0xffd82340 if ARCH_IOP13XX |
| 1101 | 1124 | default 0xfff36000 if DEBUG_HIGHBANK_UART |
| @@ -1118,6 +1141,7 @@ config DEBUG_UART_VIRT · 16 unmodified lines | ||
| 1118 | 1141 | default 0xf1600000 if ARCH_INTEGRATOR |
| 1119 | 1142 | default 0xf1c28000 if DEBUG_SUNXI_UART0 |
| 1120 | 1143 | default 0xf1c28400 if DEBUG_SUNXI_UART1 |
| 1144 | + default 0xf1f02800 if DEBUG_SUNXI_R_UART | |
| 1121 | 1145 | default 0xf2100000 if DEBUG_PXA_UART1 |
| 1122 | 1146 | default 0xf4090000 if ARCH_LPC32XX |
| 1123 | 1147 | default 0xf4200000 if ARCH_GEMINI |
| @@ -1144,7 +1168,7 @@ config DEBUG_UART_VIRT · 20 unmodified lines | ||
| 1144 | 1168 | default 0xfe230000 if DEBUG_PICOXCELL_UART |
| 1145 | 1169 | default 0xfe300000 if DEBUG_BCM_KONA_UART |
| 1146 | 1170 | default 0xfe800000 if ARCH_IOP32X |
| 1147 | − default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HI3716_UART | |
| 1171 | + default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART | |
| 1148 | 1172 | default 0xfeb24000 if DEBUG_RK3X_UART0 |
| 1149 | 1173 | default 0xfeb26000 if DEBUG_RK3X_UART1 |
| 1150 | 1174 | default 0xfeb30c00 if DEBUG_KEYSTONE_UART0 |
| @@ -1152,9 +1176,9 @@ config DEBUG_UART_VIRT · 1 unmodified line | ||
| 1152 | 1176 | default 0xfec02000 if DEBUG_SOCFPGA_UART |
| 1153 | 1177 | default 0xfec12000 if DEBUG_MVEBU_UART || DEBUG_MVEBU_UART_ALTERNATE |
| 1154 | 1178 | default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0 |
| 1179 | + default 0xfec90000 if DEBUG_RK32_UART2 | |
| 1155 | 1180 | default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1 |
| 1156 | 1181 | default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 |
| 1157 | − default 0xfed12000 if ARCH_KIRKWOOD | |
| 1158 | 1182 | default 0xfed60000 if DEBUG_RK29_UART0 |
| 1159 | 1183 | default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 |
| 1160 | 1184 | default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 |
| @@ -1186,7 +1210,7 @@ config DEBUG_UART_8250_WORD · 25 unmodified lines | ||
| 1186 | 1210 | ARCH_KEYSTONE || \ |
| 1187 | 1211 | DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ |
| 1188 | 1212 | DEBUG_DAVINCI_DA8XX_UART2 || \ |
| 1189 | − DEBUG_BCM_KONA_UART | |
| 1213 | + DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 | |
| 1190 | 1214 | |
| 1191 | 1215 | config DEBUG_UART_8250_FLOW_CONTROL |
| 1192 | 1216 | bool "Enable flow control for 8250 UART" |
| @@ -159,14 +159,13 @@ machine-$(CONFIG_ARCH_EP93XX) += ep93xx · 158 unmodified lines | ||
| 159 | 159 | machine-$(CONFIG_ARCH_EXYNOS) += exynos |
| 160 | 160 | machine-$(CONFIG_ARCH_GEMINI) += gemini |
| 161 | 161 | machine-$(CONFIG_ARCH_HIGHBANK) += highbank |
| 162 | −machine-$(CONFIG_ARCH_HI3xxx) += hisi | |
| 162 | +machine-$(CONFIG_ARCH_HISI) += hisi | |
| 163 | 163 | machine-$(CONFIG_ARCH_INTEGRATOR) += integrator |
| 164 | 164 | machine-$(CONFIG_ARCH_IOP13XX) += iop13xx |
| 165 | 165 | machine-$(CONFIG_ARCH_IOP32X) += iop32x |
| 166 | 166 | machine-$(CONFIG_ARCH_IOP33X) += iop33x |
| 167 | 167 | machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx |
| 168 | 168 | machine-$(CONFIG_ARCH_KEYSTONE) += keystone |
| 169 | −machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood | |
| 170 | 169 | machine-$(CONFIG_ARCH_KS8695) += ks8695 |
| 171 | 170 | machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx |
| 172 | 171 | machine-$(CONFIG_ARCH_MMP) += mmp |
| @@ -175,6 +174,7 @@ machine-$(CONFIG_ARCH_MSM) += msm · 2 unmodified lines | ||
| 175 | 174 | machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 |
| 176 | 175 | machine-$(CONFIG_ARCH_MVEBU) += mvebu |
| 177 | 176 | machine-$(CONFIG_ARCH_MXC) += imx |
| 177 | +machine-$(CONFIG_ARCH_MEDIATEK) += mediatek | |
| 178 | 178 | machine-$(CONFIG_ARCH_MXS) += mxs |
| 179 | 179 | machine-$(CONFIG_ARCH_NETX) += netx |
| 180 | 180 | machine-$(CONFIG_ARCH_NOMADIK) += nomadik |
| @@ -190,8 +190,6 @@ machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip · 9 unmodified lines | ||
| 190 | 190 | machine-$(CONFIG_ARCH_RPC) += rpc |
| 191 | 191 | machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx |
| 192 | 192 | machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx |
| 193 | −machine-$(CONFIG_ARCH_S5P64X0) += s5p64x0 | |
| 194 | −machine-$(CONFIG_ARCH_S5PC100) += s5pc100 | |
| 195 | 193 | machine-$(CONFIG_ARCH_S5PV210) += s5pv210 |
| 196 | 194 | machine-$(CONFIG_ARCH_SA1100) += sa1100 |
| 197 | 195 | machine-$(CONFIG_ARCH_SHMOBILE) += shmobile |
| @@ -215,11 +213,11 @@ machine-$(CONFIG_PLAT_SPEAR) += spear · 17 unmodified lines | ||
| 215 | 213 | plat-$(CONFIG_ARCH_EXYNOS) += samsung |
| 216 | 214 | plat-$(CONFIG_ARCH_OMAP) += omap |
| 217 | 215 | plat-$(CONFIG_ARCH_S3C64XX) += samsung |
| 216 | +plat-$(CONFIG_ARCH_S5PV210) += samsung | |
| 218 | 217 | plat-$(CONFIG_PLAT_IOP) += iop |
| 219 | 218 | plat-$(CONFIG_PLAT_ORION) += orion |
| 220 | 219 | plat-$(CONFIG_PLAT_PXA) += pxa |
| 221 | 220 | plat-$(CONFIG_PLAT_S3C24XX) += samsung |
| 222 | −plat-$(CONFIG_PLAT_S5P) += samsung | |
| 223 | 221 | plat-$(CONFIG_PLAT_VERSATILE) += versatile |
| 224 | 222 | |
| 225 | 223 | ifeq ($(CONFIG_ARCH_EBSA110),y) |
| @@ -243,7 +241,7 @@ MACHINE := · 17 unmodified lines | ||
| 243 | 241 | endif |
| 244 | 242 | |
| 245 | 243 | machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) |
| 246 | −platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y)) | |
| 244 | +platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y))) | |
| 247 | 245 | |
| 248 | 246 | ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y) |
| 249 | 247 | ifeq ($(KBUILD_SRC),) |
| @@ -59,6 +59,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ · 58 unmodified lines | ||
| 59 | 59 | berlin2-sony-nsz-gs7.dtb \ |
| 60 | 60 | berlin2cd-google-chromecast.dtb \ |
| 61 | 61 | berlin2q-marvell-dmp.dtb |
| 62 | +dtb-$(CONFIG_ARCH_BRCMSTB) += \ | |
| 63 | + bcm7445-bcm97445svmb.dtb | |
| 62 | 64 | dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ |
| 63 | 65 | da850-evm.dtb |
| 64 | 66 | dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb |
| @@ -66,7 +68,9 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ · 1 unmodified line | ||
| 66 | 68 | exynos4210-smdkv310.dtb \ |
| 67 | 69 | exynos4210-trats.dtb \ |
| 68 | 70 | exynos4210-universal_c210.dtb \ |
| 71 | + exynos4412-odroidu3.dtb \ | |
| 69 | 72 | exynos4412-odroidx.dtb \ |
| 73 | + exynos4412-odroidx2.dtb \ | |
| 70 | 74 | exynos4412-origen.dtb \ |
| 71 | 75 | exynos4412-smdk4412.dtb \ |
| 72 | 76 | exynos4412-tiny4412.dtb \ |
| @@ -83,6 +87,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ · 10 unmodified lines | ||
| 83 | 87 | exynos5440-ssdk5440.dtb \ |
| 84 | 88 | exynos5800-peach-pi.dtb |
| 85 | 89 | dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb |
| 90 | +dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb | |
| 86 | 91 | dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ |
| 87 | 92 | ecx-2000.dtb |
| 88 | 93 | dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ |
| @@ -90,9 +95,9 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ · 1 unmodified line | ||
| 90 | 95 | dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \ |
| 91 | 96 | k2l-evm.dtb \ |
| 92 | 97 | k2e-evm.dtb |
| 93 | −kirkwood := \ | |
| 94 | − kirkwood-b3.dtb \ | |
| 98 | +dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ | |
| 95 | 99 | kirkwood-cloudbox.dtb \ |
| 100 | + kirkwood-d2net.dtb \ | |
| 96 | 101 | kirkwood-db-88f6281.dtb \ |
| 97 | 102 | kirkwood-db-88f6282.dtb \ |
| 98 | 103 | kirkwood-dns320.dtb \ |
| @@ -123,6 +128,8 @@ kirkwood := \ · 24 unmodified lines | ||
| 123 | 128 | kirkwood-lsxhl.dtb \ |
| 124 | 129 | kirkwood-mplcec4.dtb \ |
| 125 | 130 | kirkwood-mv88f6281gtw-ge.dtb \ |
| 131 | + kirkwood-net2big.dtb \ | |
| 132 | + kirkwood-net5big.dtb \ | |
| 126 | 133 | kirkwood-netgear_readynas_duo_v2.dtb \ |
| 127 | 134 | kirkwood-netgear_readynas_nv+_v2.dtb \ |
| 128 | 135 | kirkwood-ns2.dtb \ |
| @@ -150,17 +157,19 @@ kirkwood := \ · 21 unmodified lines | ||
| 150 | 157 | kirkwood-ts219-6282.dtb \ |
| 151 | 158 | kirkwood-ts419-6281.dtb \ |
| 152 | 159 | kirkwood-ts419-6282.dtb |
| 153 | −dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood) | |
| 154 | −dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood) | |
| 155 | 160 | dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb |
| 156 | 161 | dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb |
| 157 | 162 | dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb |
| 158 | 163 | dtb-$(CONFIG_ARCH_MXC) += \ |
| 159 | 164 | imx25-eukrea-mbimxsd25-baseboard.dtb \ |
| 165 | + imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ | |
| 166 | + imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ | |
| 167 | + imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \ | |
| 160 | 168 | imx25-karo-tx25.dtb \ |
| 161 | 169 | imx25-pdk.dtb \ |
| 162 | 170 | imx27-apf27.dtb \ |
| 163 | 171 | imx27-apf27dev.dtb \ |
| 172 | + imx27-eukrea-mbimxsd27-baseboard.dtb \ | |
| 164 | 173 | imx27-pdk.dtb \ |
| 165 | 174 | imx27-phytec-phycore-rdk.dtb \ |
| 166 | 175 | imx27-phytec-phycard-s-rdk.dtb \ |
| @@ -182,6 +191,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ · 15 unmodified lines | ||
| 182 | 191 | imx53-tx53-x03x.dtb \ |
| 183 | 192 | imx53-tx53-x13x.dtb \ |
| 184 | 193 | imx53-voipac-bsb.dtb \ |
| 194 | + imx6dl-aristainetos_4.dtb \ | |
| 195 | + imx6dl-aristainetos_7.dtb \ | |
| 185 | 196 | imx6dl-cubox-i.dtb \ |
| 186 | 197 | imx6dl-dfi-fs700-m60.dtb \ |
| 187 | 198 | imx6dl-gw51xx.dtb \ |
| @@ -191,11 +202,16 @@ dtb-$(CONFIG_ARCH_MXC) += \ · 3 unmodified lines | ||
| 191 | 202 | imx6dl-hummingboard.dtb \ |
| 192 | 203 | imx6dl-nitrogen6x.dtb \ |
| 193 | 204 | imx6dl-phytec-pbab01.dtb \ |
| 205 | + imx6dl-rex-basic.dtb \ | |
| 194 | 206 | imx6dl-riotboard.dtb \ |
| 195 | 207 | imx6dl-sabreauto.dtb \ |
| 196 | 208 | imx6dl-sabrelite.dtb \ |
| 197 | 209 | imx6dl-sabresd.dtb \ |
| 210 | + imx6dl-tx6dl-comtft.dtb \ | |
| 211 | + imx6dl-tx6u-801x.dtb \ | |
| 212 | + imx6dl-tx6u-811x.dtb \ | |
| 198 | 213 | imx6dl-wandboard.dtb \ |
| 214 | + imx6dl-wandboard-revb1.dtb \ | |
| 199 | 215 | imx6q-arm2.dtb \ |
| 200 | 216 | imx6q-cm-fx6.dtb \ |
| 201 | 217 | imx6q-cubox-i.dtb \ |
| @@ -209,13 +225,21 @@ dtb-$(CONFIG_ARCH_MXC) += \ · 7 unmodified lines | ||
| 209 | 225 | imx6q-gw54xx.dtb \ |
| 210 | 226 | imx6q-nitrogen6x.dtb \ |
| 211 | 227 | imx6q-phytec-pbab01.dtb \ |
| 228 | + imx6q-rex-pro.dtb \ | |
| 212 | 229 | imx6q-sabreauto.dtb \ |
| 213 | 230 | imx6q-sabrelite.dtb \ |
| 214 | 231 | imx6q-sabresd.dtb \ |
| 215 | 232 | imx6q-sbc6x.dtb \ |
| 216 | 233 | imx6q-udoo.dtb \ |
| 217 | 234 | imx6q-wandboard.dtb \ |
| 235 | + imx6q-wandboard-revb1.dtb \ | |
| 236 | + imx6q-tx6q-1010.dtb \ | |
| 237 | + imx6q-tx6q-1010-comtft.dtb \ | |
| 238 | + imx6q-tx6q-1020.dtb \ | |
| 239 | + imx6q-tx6q-1020-comtft.dtb \ | |
| 240 | + imx6q-tx6q-1110.dtb \ | |
| 218 | 241 | imx6sl-evk.dtb \ |
| 242 | + imx6sx-sdb.dtb \ | |
| 219 | 243 | vf610-colibri.dtb \ |
| 220 | 244 | vf610-cosmic.dtb \ |
| 221 | 245 | vf610-twr.dtb |
| @@ -291,7 +315,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ · 69 unmodified lines | ||
| 291 | 315 | am335x-boneblack.dtb \ |
| 292 | 316 | am335x-evm.dtb \ |
| 293 | 317 | am335x-evmsk.dtb \ |
| 294 | − am335x-nano.dtb | |
| 318 | + am335x-nano.dtb \ | |
| 319 | + am335x-pepper.dtb | |
| 295 | 320 | dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ |
| 296 | 321 | omap4-panda.dtb \ |
| 297 | 322 | omap4-panda-a4.dtb \ |
| @@ -301,6 +326,7 @@ dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ · 3 unmodified lines | ||
| 301 | 326 | omap4-var-dvk-om44.dtb \ |
| 302 | 327 | omap4-var-stk-om44.dtb |
| 303 | 328 | dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \ |
| 329 | + am437x-sk-evm.dtb \ | |
| 304 | 330 | am437x-gp-evm.dtb |
| 305 | 331 | dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ |
| 306 | 332 | omap5-sbc-t54.dtb \ |
| @@ -318,16 +344,25 @@ dtb-$(CONFIG_ARCH_QCOM) += \ · 11 unmodified lines | ||
| 318 | 344 | qcom-apq8084-mtp.dtb \ |
| 319 | 345 | qcom-msm8660-surf.dtb \ |
| 320 | 346 | qcom-msm8960-cdp.dtb |
| 347 | +dtb-$(CONFIG_ARCH_ROCKCHIP) += \ | |
| 348 | + rk3066a-bqcurie2.dtb \ | |
| 349 | + rk3188-radxarock.dtb \ | |
| 350 | + rk3288-evb-act8846.dtb \ | |
| 351 | + rk3288-evb-rk808.dtb | |
| 321 | 352 | dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb |
| 322 | 353 | dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ |
| 323 | 354 | s3c6410-smdk6410.dtb |
| 355 | +dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \ | |
| 356 | + s5pv210-goni.dtb \ | |
| 357 | + s5pv210-smdkc110.dtb \ | |
| 358 | + s5pv210-smdkv210.dtb \ | |
| 359 | + s5pv210-torbreck.dtb | |
| 324 | 360 | dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \ |
| 325 | 361 | r8a7740-armadillo800eva.dtb \ |
| 326 | 362 | r8a7778-bockw.dtb \ |
| 327 | 363 | r8a7778-bockw-reference.dtb \ |
| 328 | 364 | r8a7740-armadillo800eva-reference.dtb \ |
| 329 | 365 | r8a7779-marzen.dtb \ |
| 330 | − r8a7779-marzen-reference.dtb \ | |
| 331 | 366 | r8a7791-koelsch.dtb \ |
| 332 | 367 | r8a7790-lager.dtb \ |
| 333 | 368 | sh73a0-kzm9g.dtb \ |
| @@ -339,7 +374,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ · 5 unmodified lines | ||
| 339 | 374 | r7s72100-genmai.dtb \ |
| 340 | 375 | r8a7791-henninger.dtb \ |
| 341 | 376 | r8a7791-koelsch.dtb \ |
| 342 | − r8a7790-lager.dtb | |
| 377 | + r8a7790-lager.dtb \ | |
| 378 | + r8a7779-marzen.dtb | |
| 343 | 379 | dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ |
| 344 | 380 | socfpga_cyclone5_socdk.dtb \ |
| 345 | 381 | socfpga_cyclone5_sockit.dtb \ |
| @@ -360,6 +396,7 @@ dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ · 14 unmodified lines | ||
| 360 | 396 | stih416-b2020e.dtb |
| 361 | 397 | dtb-$(CONFIG_MACH_SUN4I) += \ |
| 362 | 398 | sun4i-a10-a1000.dtb \ |
| 399 | + sun4i-a10-ba10-tvbox.dtb \ | |
| 363 | 400 | sun4i-a10-cubieboard.dtb \ |
| 364 | 401 | sun4i-a10-mini-xplus.dtb \ |
| 365 | 402 | sun4i-a10-hackberry.dtb \ |
| @@ -374,12 +411,16 @@ dtb-$(CONFIG_MACH_SUN5I) += \ · 8 unmodified lines | ||
| 374 | 411 | dtb-$(CONFIG_MACH_SUN6I) += \ |
| 375 | 412 | sun6i-a31-app4-evb1.dtb \ |
| 376 | 413 | sun6i-a31-colombus.dtb \ |
| 414 | + sun6i-a31-hummingbird.dtb \ | |
| 377 | 415 | sun6i-a31-m9.dtb |
| 378 | 416 | dtb-$(CONFIG_MACH_SUN7I) += \ |
| 379 | 417 | sun7i-a20-cubieboard2.dtb \ |
| 380 | 418 | sun7i-a20-cubietruck.dtb \ |
| 381 | 419 | sun7i-a20-i12-tvbox.dtb \ |
| 382 | − sun7i-a20-olinuxino-micro.dtb | |
| 420 | + sun7i-a20-olinuxino-micro.dtb \ | |
| 421 | + sun7i-a20-pcduino3.dtb | |
| 422 | +dtb-$(CONFIG_MACH_SUN8I) += \ | |
| 423 | + sun8i-a23-ippo-q8h-v5.dtb | |
| 383 | 424 | dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ |
| 384 | 425 | tegra20-iris-512.dtb \ |
| 385 | 426 | tegra20-medcom-wide.dtb \ |
| @@ -390,6 +431,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ · 4 unmodified lines | ||
| 390 | 431 | tegra20-trimslice.dtb \ |
| 391 | 432 | tegra20-ventana.dtb \ |
| 392 | 433 | tegra20-whistler.dtb \ |
| 434 | + tegra30-apalis-eval.dtb \ | |
| 393 | 435 | tegra30-beaver.dtb \ |
| 394 | 436 | tegra30-cardhu-a02.dtb \ |
| 395 | 437 | tegra30-cardhu-a04.dtb \ |
| @@ -419,7 +461,9 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ · 23 unmodified lines | ||
| 419 | 461 | wm8650-mid.dtb \ |
| 420 | 462 | wm8750-apc8750.dtb \ |
| 421 | 463 | wm8850-w70v2.dtb |
| 422 | −dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ | |
| 464 | +dtb-$(CONFIG_ARCH_ZYNQ) += \ | |
| 465 | + zynq-parallella.dtb \ | |
| 466 | + zynq-zc702.dtb \ | |
| 423 | 467 | zynq-zc706.dtb \ |
| 424 | 468 | zynq-zed.dtb |
| 425 | 469 | dtb-$(CONFIG_MACH_ARMADA_370) += \ |
| @@ -437,11 +481,13 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ · 11 unmodified lines | ||
| 437 | 481 | armada-xp-axpwifiap.dtb \ |
| 438 | 482 | armada-xp-db.dtb \ |
| 439 | 483 | armada-xp-gp.dtb \ |
| 440 | − armada-xp-netgear-rn2120.dtb \ | |
| 484 | + armada-xp-lenovo-ix4-300d.dtb \ | |
| 441 | 485 | armada-xp-matrix.dtb \ |
| 486 | + armada-xp-netgear-rn2120.dtb \ | |
| 442 | 487 | armada-xp-openblocks-ax3-4.dtb |
| 443 | 488 | dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ |
| 444 | 489 | dove-cubox.dtb \ |
| 490 | + dove-cubox-es.dtb \ | |
| 445 | 491 | dove-d2plug.dtb \ |
| 446 | 492 | dove-d3plug.dtb \ |
| 447 | 493 | dove-dove-db.dtb |
| @@ -16,6 +16,12 @@ · 15 unmodified lines | ||
| 16 | 16 | bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs"; |
| 17 | 17 | }; |
| 18 | 18 | |
| 19 | + clocks { | |
| 20 | + slow_xtal { | |
| 21 | + clock-frequency = <32768>; | |
| 22 | + }; | |
| 23 | + }; | |
| 24 | + | |
| 19 | 25 | ahb { |
| 20 | 26 | apb { |
| 21 | 27 | usart0: serial@fffb0000 { |
| @@ -149,12 +149,113 @@ · 148 unmodified lines | ||
| 149 | 149 | "Headphone Jack", "HPLOUT", |
| 150 | 150 | "Headphone Jack", "HPROUT"; |
| 151 | 151 | }; |
| 152 | + | |
| 153 | + panel { | |
| 154 | + compatible = "ti,tilcdc,panel"; | |
| 155 | + pinctrl-names = "default", "sleep"; | |
| 156 | + pinctrl-0 = <&lcd_pins_default>; | |
| 157 | + pinctrl-1 = <&lcd_pins_sleep>; | |
| 158 | + status = "okay"; | |
| 159 | + panel-info { | |
| 160 | + ac-bias = <255>; | |
| 161 | + ac-bias-intrpt = <0>; | |
| 162 | + dma-burst-sz = <16>; | |
| 163 | + bpp = <32>; | |
| 164 | + fdd = <0x80>; | |
| 165 | + sync-edge = <0>; | |
| 166 | + sync-ctrl = <1>; | |
| 167 | + raster-order = <0>; | |
| 168 | + fifo-th = <0>; | |
| 169 | + }; | |
| 170 | + display-timings { | |
| 171 | + 480x272 { | |
| 172 | + hactive = <480>; | |
| 173 | + vactive = <272>; | |
| 174 | + hback-porch = <43>; | |
| 175 | + hfront-porch = <8>; | |
| 176 | + hsync-len = <4>; | |
| 177 | + vback-porch = <12>; | |
| 178 | + vfront-porch = <4>; | |
| 179 | + vsync-len = <10>; | |
| 180 | + clock-frequency = <9000000>; | |
| 181 | + hsync-active = <0>; | |
| 182 | + vsync-active = <0>; | |
| 183 | + }; | |
| 184 | + }; | |
| 185 | + }; | |
| 152 | 186 | }; |
| 153 | 187 | |
| 154 | 188 | &am33xx_pinmux { |
| 155 | 189 | pinctrl-names = "default"; |
| 156 | 190 | pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; |
| 157 | 191 | |
| 192 | + lcd_pins_default: lcd_pins_default { | |
| 193 | + pinctrl-single,pins = < | |
| 194 | + 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ | |
| 195 | + 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ | |
| 196 | + 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ | |
| 197 | + 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ | |
| 198 | + 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ | |
| 199 | + 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ | |
| 200 | + 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ | |
| 201 | + 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ | |
| 202 | + 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ | |
| 203 | + 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ | |
| 204 | + 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ | |
| 205 | + 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ | |
| 206 | + 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ | |
| 207 | + 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ | |
| 208 | + 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ | |
| 209 | + 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ | |
| 210 | + 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ | |
| 211 | + 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ | |
| 212 | + 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ | |
| 213 | + 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ | |
| 214 | + 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ | |
| 215 | + 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ | |
| 216 | + 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ | |
| 217 | + 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ | |
| 218 | + 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ | |
| 219 | + 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ | |
| 220 | + 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ | |
| 221 | + 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ | |
| 222 | + >; | |
| 223 | + }; | |
| 224 | + | |
| 225 | + lcd_pins_sleep: lcd_pins_sleep { | |
| 226 | + pinctrl-single,pins = < | |
| 227 | + 0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */ | |
| 228 | + 0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */ | |
| 229 | + 0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */ | |
| 230 | + 0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */ | |
| 231 | + 0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */ | |
| 232 | + 0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */ | |
| 233 | + 0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */ | |
| 234 | + 0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */ | |
| 235 | + 0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */ | |
| 236 | + 0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */ | |
| 237 | + 0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */ | |
| 238 | + 0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */ | |
| 239 | + 0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */ | |
| 240 | + 0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */ | |
| 241 | + 0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */ | |
| 242 | + 0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */ | |
| 243 | + 0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */ | |
| 244 | + 0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */ | |
| 245 | + 0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */ | |
| 246 | + 0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */ | |
| 247 | + 0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */ | |
| 248 | + 0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */ | |
| 249 | + 0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */ | |
| 250 | + 0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */ | |
| 251 | + 0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */ | |
| 252 | + 0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */ | |
| 253 | + 0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */ | |
| 254 | + 0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */ | |
| 255 | + >; | |
| 256 | + }; | |
| 257 | + | |
| 258 | + | |
| 158 | 259 | user_leds_s0: user_leds_s0 { |
| 159 | 260 | pinctrl-single,pins = < |
| 160 | 261 | 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ |
| @@ -573,3 +674,7 @@ · 412 unmodified lines | ||
| 573 | 674 | ti,wire-config = <0x00 0x11 0x22 0x33>; |
| 574 | 675 | }; |
| 575 | 676 | }; |
| 677 | + | |
| 678 | +&lcdc { | |
| 679 | + status = "okay"; | |
| 680 | +}; | |
| @@ -0,0 +1,653 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) 2014 Gumstix, Inc. - https://www.gumstix.com/ | |
| 3 | + * | |
| 4 | + * This program is free software; you can redistribute it and/or modify | |
| 5 | + * it under the terms of the GNU General Public License version 2 as | |
| 6 | + * published by the Free Software Foundation. | |
| 7 | + */ | |
| 8 | +/dts-v1/; | |
| 9 | + | |
| 10 | +#include <dt-bindings/input/input.h> | |
| 11 | +#include "am33xx.dtsi" | |
| 12 | + | |
| 13 | +/ { | |
| 14 | + model = "Gumstix Pepper"; | |
| 15 | + compatible = "gumstix,am335x-pepper", "ti,am33xx"; | |
| 16 | + | |
| 17 | + cpus { | |
| 18 | + cpu@0 { | |
| 19 | + cpu0-supply = <&dcdc3_reg>; | |
| 20 | + }; | |
| 21 | + }; | |
| 22 | + | |
| 23 | + memory { | |
| 24 | + device_type = "memory"; | |
| 25 | + reg = <0x80000000 0x20000000>; /* 512 MB */ | |
| 26 | + }; | |
| 27 | + | |
| 28 | + buttons: user_buttons { | |
| 29 | + compatible = "gpio-keys"; | |
| 30 | + }; | |
| 31 | + | |
| 32 | + leds: user_leds { | |
| 33 | + compatible = "gpio-leds"; | |
| 34 | + }; | |
| 35 | + | |
| 36 | + panel: lcd_panel { | |
| 37 | + compatible = "ti,tilcdc,panel"; | |
| 38 | + }; | |
| 39 | + | |
| 40 | + sound: sound_iface { | |
| 41 | + compatible = "ti,da830-evm-audio"; | |
| 42 | + }; | |
| 43 | + | |
| 44 | + vbat: fixedregulator@0 { | |
| 45 | + compatible = "regulator-fixed"; | |
| 46 | + }; | |
| 47 | + | |
| 48 | + v3v3c_reg: fixedregulator@1 { | |
| 49 | + compatible = "regulator-fixed"; | |
| 50 | + }; | |
| 51 | + | |
| 52 | + vdd5_reg: fixedregulator@2 { | |
| 53 | + compatible = "regulator-fixed"; | |
| 54 | + }; | |
| 55 | +}; | |
| 56 | + | |
| 57 | +/* I2C Busses */ | |
| 58 | +&i2c0 { | |
| 59 | + status = "okay"; | |
| 60 | + pinctrl-names = "default"; | |
| 61 | + pinctrl-0 = <&i2c0_pins>; | |
| 62 | + | |
| 63 | + clock-frequency = <400000>; | |
| 64 | + | |
| 65 | + tps: tps@24 { | |
| 66 | + reg = <0x24>; | |
| 67 | + }; | |
| 68 | + | |
| 69 | + eeprom: eeprom@50 { | |
| 70 | + compatible = "at,24c256"; | |
| 71 | + reg = <0x50>; | |
| 72 | + }; | |
| 73 | + | |
| 74 | + audio_codec: tlv320aic3106@1b { | |
| 75 | + compatible = "ti,tlv320aic3106"; | |
| 76 | + reg = <0x1b>; | |
| 77 | + }; | |
| 78 | + | |
| 79 | + accel: lis331dlh@1d { | |
| 80 | + compatible = "st,lis3lv02d"; | |
| 81 | + reg = <0x1d>; | |
| 82 | + }; | |
| 83 | +}; | |
| 84 | + | |
| 85 | +&i2c1 { | |
| 86 | + status = "okay"; | |
| 87 | + pinctrl-names = "default"; | |
| 88 | + pinctrl-0 = <&i2c1_pins>; | |
| 89 | + clock-frequency = <400000>; | |
| 90 | +}; | |
| 91 | + | |
| 92 | +&am33xx_pinmux { | |
| 93 | + i2c0_pins: pinmux_i2c0 { | |
| 94 | + pinctrl-single,pins = < | |
| 95 | + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | |
| 96 | + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | |
| 97 | + >; | |
| 98 | + }; | |
| 99 | + i2c1_pins: pinmux_i2c1 { | |
| 100 | + pinctrl-single,pins = < | |
| 101 | + 0x10C (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_crs,i2c1_sda */ | |
| 102 | + 0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_rxerr,i2c1_scl */ | |
| 103 | + >; | |
| 104 | + }; | |
| 105 | +}; | |
| 106 | + | |
| 107 | +/* Accelerometer */ | |
| 108 | +&accel { | |
| 109 | + pinctrl-names = "default"; | |
| 110 | + pinctrl-0 = <&accel_pins>; | |
| 111 | + | |
| 112 | + Vdd-supply = <&ldo3_reg>; | |
| 113 | + Vdd_IO-supply = <&ldo3_reg>; | |
| 114 | + st,irq1-click; | |
| 115 | + st,wakeup-x-lo; | |
| 116 | + st,wakeup-x-hi; | |
| 117 | + st,wakeup-y-lo; | |
| 118 | + st,wakeup-y-hi; | |
| 119 | + st,wakeup-z-lo; | |
| 120 | + st,wakeup-z-hi; | |
| 121 | + st,min-limit-x = <92>; | |
| 122 | + st,max-limit-x = <14>; | |
| 123 | + st,min-limit-y = <14>; | |
| 124 | + st,max-limit-y = <92>; | |
| 125 | + st,min-limit-z = <92>; | |
| 126 | + st,max-limit-z = <14>; | |
| 127 | +}; | |
| 128 | + | |
| 129 | +&am33xx_pinmux { | |
| 130 | + accel_pins: pinmux_accel { | |
| 131 | + pinctrl-single,pins = < | |
| 132 | + 0x98 (PIN_INPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */ | |
| 133 | + >; | |
| 134 | + }; | |
| 135 | +}; | |
| 136 | + | |
| 137 | +/* Audio */ | |
| 138 | +&audio_codec { | |
| 139 | + status = "okay"; | |
| 140 | + | |
| 141 | + gpio-reset = <&gpio1 16 GPIO_ACTIVE_LOW>; | |
| 142 | + AVDD-supply = <&ldo3_reg>; | |
| 143 | + IOVDD-supply = <&ldo3_reg>; | |
| 144 | + DRVDD-supply = <&ldo3_reg>; | |
| 145 | + DVDD-supply = <&dcdc1_reg>; | |
| 146 | +}; | |
| 147 | + | |
| 148 | +&sound { | |
| 149 | + ti,model = "AM335x-EVM"; | |
| 150 | + ti,audio-codec = <&audio_codec>; | |
| 151 | + ti,mcasp-controller = <&mcasp0>; | |
| 152 | + ti,codec-clock-rate = <12000000>; | |
| 153 | + ti,audio-routing = | |
| 154 | + "Headphone Jack", "HPLOUT", | |
| 155 | + "Headphone Jack", "HPROUT", | |
| 156 | + "LINE1L", "Line In"; | |
| 157 | +}; | |
| 158 | + | |
| 159 | +&mcasp0 { | |
| 160 | + status = "okay"; | |
| 161 | + pinctrl-names = "default"; | |
| 162 | + pinctrl-0 = <&audio_pins>; | |
| 163 | + | |
| 164 | + op-mode = <0>; /* MCASP_ISS_MODE */ | |
| 165 | + tdm-slots = <2>; | |
| 166 | + serial-dir = < | |
| 167 | + 1 2 0 0 | |
| 168 | + 0 0 0 0 | |
| 169 | + 0 0 0 0 | |
| 170 | + 0 0 0 0 | |
| 171 | + >; | |
| 172 | + tx-num-evt = <1>; | |
| 173 | + rx-num-evt = <1>; | |
| 174 | +}; | |
| 175 | + | |
| 176 | +&am33xx_pinmux { | |
| 177 | + audio_pins: pinmux_audio { | |
| 178 | + pinctrl-single,pins = < | |
| 179 | + 0x1AC (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ | |
| 180 | + 0x194 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ | |
| 181 | + 0x190 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ | |
| 182 | + 0x198 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ | |
| 183 | + 0x1A8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */ | |
| 184 | + 0x40 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a0.gpio1_16 */ | |
| 185 | + >; | |
| 186 | + }; | |
| 187 | +}; | |
| 188 | + | |
| 189 | +/* Display: 24-bit LCD Screen */ | |
| 190 | +&panel { | |
| 191 | + status = "okay"; | |
| 192 | + pinctrl-names = "default"; | |
| 193 | + pinctrl-0 = <&lcd_pins>; | |
| 194 | + panel-info { | |
| 195 | + ac-bias = <255>; | |
| 196 | + ac-bias-intrpt = <0>; | |
| 197 | + dma-burst-sz = <16>; | |
| 198 | + bpp = <32>; | |
| 199 | + fdd = <0x80>; | |
| 200 | + sync-edge = <0>; | |
| 201 | + sync-ctrl = <1>; | |
| 202 | + raster-order = <0>; | |
| 203 | + fifo-th = <0>; | |
| 204 | + }; | |
| 205 | + display-timings { | |
| 206 | + native-mode = <&timing0>; | |
| 207 | + timing0: 480x272 { | |
| 208 | + clock-frequency = <18400000>; | |
| 209 | + hactive = <480>; | |
| 210 | + vactive = <272>; | |
| 211 | + hfront-porch = <8>; | |
| 212 | + hback-porch = <4>; | |
| 213 | + hsync-len = <41>; | |
| 214 | + vfront-porch = <4>; | |
| 215 | + vback-porch = <2>; | |
| 216 | + vsync-len = <10>; | |
| 217 | + hsync-active = <1>; | |
| 218 | + vsync-active = <1>; | |
| 219 | + }; | |
| 220 | + }; | |
| 221 | +}; | |
| 222 | + | |
| 223 | +&lcdc { | |
| 224 | + status = "okay"; | |
| 225 | +}; | |
| 226 | + | |
| 227 | +&am33xx_pinmux { | |
| 228 | + lcd_pins: pinmux_lcd { | |
| 229 | + pinctrl-single,pins = < | |
| 230 | + 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ | |
| 231 | + 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ | |
| 232 | + 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ | |
| 233 | + 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ | |
| 234 | + 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ | |
| 235 | + 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ | |
| 236 | + 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ | |
| 237 | + 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ | |
| 238 | + 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ | |
| 239 | + 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ | |
| 240 | + 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ | |
| 241 | + 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ | |
| 242 | + 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ | |
| 243 | + 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ | |
| 244 | + 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ | |
| 245 | + 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ | |
| 246 | + 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data16 */ | |
| 247 | + 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data17 */ | |
| 248 | + 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data18 */ | |
| 249 | + 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data19 */ | |
| 250 | + 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data20 */ | |
| 251 | + 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data21 */ | |
| 252 | + 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data22 */ | |
| 253 | + 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data23 */ | |
| 254 | + 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ | |
| 255 | + 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ | |
| 256 | + 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ | |
| 257 | + 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ | |
| 258 | + /* Display Enable */ | |
| 259 | + 0x6c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 */ | |
| 260 | + >; | |
| 261 | + }; | |
| 262 | +}; | |
| 263 | + | |
| 264 | +/* Ethernet */ | |
| 265 | +&cpsw_emac0 { | |
| 266 | + status = "okay"; | |
| 267 | + phy_id = <&davinci_mdio>, <0>; | |
| 268 | + phy-mode = "rgmii"; | |
| 269 | +}; | |
| 270 | + | |
| 271 | +&cpsw_emac1 { | |
| 272 | + status = "okay"; | |
| 273 | + phy_id = <&davinci_mdio>, <1>; | |
| 274 | + phy-mode = "rgmii"; | |
| 275 | +}; | |
| 276 | + | |
| 277 | +&davinci_mdio { | |
| 278 | + status = "okay"; | |
| 279 | + pinctrl-names = "default"; | |
| 280 | + pinctrl-0 = <&mdio_pins>; | |
| 281 | +}; | |
| 282 | + | |
| 283 | +&mac { | |
| 284 | + status = "okay"; | |
| 285 | + pinctrl-names = "default"; | |
| 286 | + pinctrl-0 = <ðernet_pins>; | |
| 287 | +}; | |
| 288 | + | |
| 289 | + | |
| 290 | +&am33xx_pinmux { | |
| 291 | + ethernet_pins: pinmux_ethernet { | |
| 292 | + pinctrl-single,pins = < | |
| 293 | + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ | |
| 294 | + 0x118 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ | |
| 295 | + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ | |
| 296 | + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ | |
| 297 | + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ | |
| 298 | + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ | |
| 299 | + 0x12c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ | |
| 300 | + 0x130 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ | |
| 301 | + 0x134 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */ | |
| 302 | + 0x138 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */ | |
| 303 | + 0x13c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ | |
| 304 | + 0x140 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ | |
| 305 | + /* ethernet interrupt */ | |
| 306 | + 0x144 (PIN_INPUT_PULLUP | MUX_MODE7) /* rmii2_refclk.gpio0_29 */ | |
| 307 | + /* ethernet PHY nReset */ | |
| 308 | + 0x108 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mii1_col.gpio3_0 */ | |
| 309 | + >; | |
| 310 | + }; | |
| 311 | + | |
| 312 | + mdio_pins: pinmux_mdio { | |
| 313 | + pinctrl-single,pins = < | |
| 314 | + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ | |
| 315 | + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | |
| 316 | + >; | |
| 317 | + }; | |
| 318 | +}; | |
| 319 | + | |
| 320 | +/* MMC */ | |
| 321 | +&mmc1 { | |
| 322 | + /* Bootable SD card slot */ | |
| 323 | + status = "okay"; | |
| 324 | + vmmc-supply = <&ldo3_reg>; | |
| 325 | + bus-width = <4>; | |
| 326 | + pinctrl-names = "default"; | |
| 327 | + pinctrl-0 = <&sd_pins>; | |
| 328 | + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; | |
| 329 | +}; | |
| 330 | + | |
| 331 | +&mmc2 { | |
| 332 | + /* eMMC (not populated) on MMC #2 */ | |
| 333 | + status = "disabled"; | |
| 334 | + pinctrl-names = "default"; | |
| 335 | + pinctrl-0 = <&emmc_pins>; | |
| 336 | + vmmc-supply = <&ldo3_reg>; | |
| 337 | + bus-width = <8>; | |
| 338 | + ti,non-removable; | |
| 339 | +}; | |
| 340 | + | |
| 341 | +&edma { | |
| 342 | + /* Map eDMA MMC2 Events from Crossbar */ | |
| 343 | + ti,edma-xbar-event-map = /bits/ 16 <1 12 | |
| 344 | + 2 13>; | |
| 345 | +}; | |
| 346 | + | |
| 347 | + | |
| 348 | +&mmc3 { | |
| 349 | + /* Wifi & Bluetooth on MMC #3 */ | |
| 350 | + status = "okay"; | |
| 351 | + pinctrl-names = "default"; | |
| 352 | + pinctrl-0 = <&wireless_pins>; | |
| 353 | + vmmmc-supply = <&v3v3c_reg>; | |
| 354 | + bus-width = <4>; | |
| 355 | + ti,non-removable; | |
| 356 | + dmas = <&edma 12 | |
| 357 | + &edma 13>; | |
| 358 | + dma-names = "tx", "rx"; | |
| 359 | +}; | |
| 360 | + | |
| 361 | + | |
| 362 | +&am33xx_pinmux { | |
| 363 | + sd_pins: pinmux_sd_card { | |
| 364 | + pinctrl-single,pins = < | |
| 365 | + 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ | |
| 366 | + 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ | |
| 367 | + 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ | |
| 368 | + 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ | |
| 369 | + 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ | |
| 370 | + 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ | |
| 371 | + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ | |
| 372 | + >; | |
| 373 | + }; | |
| 374 | + emmc_pins: pinmux_emmc { | |
| 375 | + pinctrl-single,pins = < | |
| 376 | + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ | |
| 377 | + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ | |
| 378 | + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ | |
| 379 | + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ | |
| 380 | + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ | |
| 381 | + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ | |
| 382 | + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ | |
| 383 | + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ | |
| 384 | + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ | |
| 385 | + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ | |
| 386 | + /* EMMC nReset */ | |
| 387 | + 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ | |
| 388 | + >; | |
| 389 | + }; | |
| 390 | + wireless_pins: pinmux_wireless { | |
| 391 | + pinctrl-single,pins = < | |
| 392 | + 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ | |
| 393 | + 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ | |
| 394 | + 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ | |
| 395 | + 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */ | |
| 396 | + 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ | |
| 397 | + 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc1_clk */ | |
| 398 | + /* WLAN nReset */ | |
| 399 | + 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ | |
| 400 | + /* WLAN nPower down */ | |
| 401 | + 0x70 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ | |
| 402 | + /* 32kHz Clock */ | |
| 403 | + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ | |
| 404 | + >; | |
| 405 | + }; | |
| 406 | +}; | |
| 407 | + | |
| 408 | +/* Power */ | |
| 409 | +&vbat { | |
| 410 | + regulator-name = "vbat"; | |
| 411 | + regulator-min-microvolt = <5000000>; | |
| 412 | + regulator-max-microvolt = <5000000>; | |
| 413 | +}; | |
| 414 | + | |
| 415 | +&v3v3c_reg { | |
| 416 | + regulator-name = "v3v3c_reg"; | |
| 417 | + regulator-min-microvolt = <3300000>; | |
| 418 | + regulator-max-microvolt = <3300000>; | |
| 419 | + vin-supply = <&vbat>; | |
| 420 | +}; | |
| 421 | + | |
| 422 | +&vdd5_reg { | |
| 423 | + regulator-name = "vdd5_reg"; | |
| 424 | + regulator-min-microvolt = <5000000>; | |
| 425 | + regulator-max-microvolt = <5000000>; | |
| 426 | + vin-supply = <&vbat>; | |
| 427 | +}; | |
| 428 | + | |
| 429 | +/include/ "tps65217.dtsi" | |
| 430 | + | |
| 431 | +&tps { | |
| 432 | + backlight { | |
| 433 | + isel = <1>; /* ISET1 */ | |
| 434 | + fdim = <200>; /* TPS65217_BL_FDIM_200HZ */ | |
| 435 | + default-brightness = <80>; | |
| 436 | + }; | |
| 437 | + | |
| 438 | + regulators { | |
| 439 | + dcdc1_reg: regulator@0 { | |
| 440 | + /* VDD_1V8 system supply */ | |
| 441 | + }; | |
| 442 | + | |
| 443 | + dcdc2_reg: regulator@1 { | |
| 444 | + /* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */ | |
| 445 | + regulator-name = "vdd_core"; | |
| 446 | + regulator-min-microvolt = <925000>; | |
| 447 | + regulator-max-microvolt = <1325000>; | |
| 448 | + regulator-boot-on; | |
| 449 | + }; | |
| 450 | + | |
| 451 | + dcdc3_reg: regulator@2 { | |
| 452 | + /* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */ | |
| 453 | + regulator-name = "vdd_mpu"; | |
| 454 | + regulator-min-microvolt = <925000>; | |
| 455 | + regulator-max-microvolt = <1150000>; | |
| 456 | + regulator-boot-on; | |
| 457 | + }; | |
| 458 | + | |
| 459 | + ldo1_reg: regulator@3 { | |
| 460 | + /* VRTC 1.8V always-on supply */ | |
| 461 | + regulator-always-on; | |
| 462 | + }; | |
| 463 | + | |
| 464 | + ldo2_reg: regulator@4 { | |
| 465 | + /* 3.3V rail */ | |
| 466 | + }; | |
| 467 | + | |
| 468 | + ldo3_reg: regulator@5 { | |
| 469 | + /* VDD_3V3A 3.3V rail */ | |
| 470 | + regulator-min-microvolt = <3300000>; | |
| 471 | + regulator-max-microvolt = <3300000>; | |
| 472 | + }; | |
| 473 | + | |
| 474 | + ldo4_reg: regulator@6 { | |
| 475 | + /* VDD_3V3B 3.3V rail */ | |
| 476 | + }; | |
| 477 | + }; | |
| 478 | +}; | |
| 479 | + | |
| 480 | +/* SPI Busses */ | |
| 481 | +&spi0 { | |
| 482 | + status = "okay"; | |
| 483 | + pinctrl-names = "default"; | |
| 484 | + pinctrl-0 = <&spi0_pins>; | |
| 485 | +}; | |
| 486 | + | |
| 487 | +&am33xx_pinmux { | |
| 488 | + spi0_pins: pinmux_spi0 { | |
| 489 | + pinctrl-single,pins = < | |
| 490 | + 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ | |
| 491 | + 0x15C (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ | |
| 492 | + 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ | |
| 493 | + 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ | |
| 494 | + >; | |
| 495 | + }; | |
| 496 | +}; | |
| 497 | + | |
| 498 | +/* Touch Screen */ | |
| 499 | +&tscadc { | |
| 500 | + status = "okay"; | |
| 501 | + tsc { | |
| 502 | + ti,wires = <4>; | |
| 503 | + ti,x-plate-resistance = <200>; | |
| 504 | + ti,coordinate-readouts = <5>; | |
| 505 | + ti,wire-config = <0x00 0x11 0x22 0x33>; | |
| 506 | + }; | |
| 507 | + | |
| 508 | + adc { | |
| 509 | + ti,adc-channels = <4 5 6 7>; | |
| 510 | + }; | |
| 511 | +}; | |
| 512 | + | |
| 513 | +/* UARTs */ | |
| 514 | +&uart0 { | |
| 515 | + /* Serial Console */ | |
| 516 | + status = "okay"; | |
| 517 | + pinctrl-names = "default"; | |
| 518 | + pinctrl-0 = <&uart0_pins>; | |
| 519 | +}; | |
| 520 | + | |
| 521 | +&uart1 { | |
| 522 | + /* Broken out to J6 header */ | |
| 523 | + status = "okay"; | |
| 524 | + pinctrl-names = "default"; | |
| 525 | + pinctrl-0 = <&uart1_pins>; | |
| 526 | +}; | |
| 527 | + | |
| 528 | +&am33xx_pinmux { | |
| 529 | + uart0_pins: pinmux_uart0 { | |
| 530 | + pinctrl-single,pins = < | |
| 531 | + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ | |
| 532 | + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ | |
| 533 | + >; | |
| 534 | + }; | |
| 535 | + uart1_pins: pinmux_uart1 { | |
| 536 | + pinctrl-single,pins = < | |
| 537 | + 0x178 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ | |
| 538 | + 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ | |
| 539 | + 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ | |
| 540 | + 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ | |
| 541 | + >; | |
| 542 | + }; | |
| 543 | +}; | |
| 544 | + | |
| 545 | +/* USB */ | |
| 546 | +&usb { | |
| 547 | + status = "okay"; | |
| 548 | + | |
| 549 | + pinctrl-names = "default"; | |
| 550 | + pinctrl-0 = <&usb_pins>; | |
| 551 | +}; | |
| 552 | + | |
| 553 | +&usb_ctrl_mod { | |
| 554 | + status = "okay"; | |
| 555 | +}; | |
| 556 | + | |
| 557 | +&usb0_phy { | |
| 558 | + status = "okay"; | |
| 559 | +}; | |
| 560 | + | |
| 561 | +&usb1_phy { | |
| 562 | + status = "okay"; | |
| 563 | +}; | |
| 564 | + | |
| 565 | +&usb0 { | |
| 566 | + status = "okay"; | |
| 567 | + dr_mode = "host"; | |
| 568 | +}; | |
| 569 | + | |
| 570 | +&usb1 { | |
| 571 | + status = "okay"; | |
| 572 | + dr_mode = "host"; | |
| 573 | +}; | |
| 574 | + | |
| 575 | +&cppi41dma { | |
| 576 | + status = "okay"; | |
| 577 | +}; | |
| 578 | + | |
| 579 | +&am33xx_pinmux { | |
| 580 | + usb_pins: pinmux_usb { | |
| 581 | + pinctrl-single,pins = < | |
| 582 | + /* USB0 Over-Current (active low) */ | |
| 583 | + 0x64 (PIN_INPUT | MUX_MODE7) /* gpmc_a9.gpio1_25 */ | |
| 584 | + /* USB1 Over-Current (active low) */ | |
| 585 | + 0x68 (PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */ | |
| 586 | + >; | |
| 587 | + }; | |
| 588 | +}; | |
| 589 | + | |
| 590 | +/* User IO */ | |
| 591 | +&leds { | |
| 592 | + pinctrl-names = "default"; | |
| 593 | + pinctrl-0 = <&user_leds_pins>; | |
| 594 | + | |
| 595 | + led@0 { | |
| 596 | + label = "pepper:user0:blue"; | |
| 597 | + gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; | |
| 598 | + linux,default-trigger = "none"; | |
| 599 | + default-state = "off"; | |
| 600 | + }; | |
| 601 | + | |
| 602 | + led@1 { | |
| 603 | + label = "pepper:user1:red"; | |
| 604 | + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; | |
| 605 | + linux,default-trigger = "none"; | |
| 606 | + default-state = "off"; | |
| 607 | + }; | |
| 608 | +}; | |
| 609 | + | |
| 610 | +&buttons { | |
| 611 | + pinctrl-names = "default"; | |
| 612 | + pinctrl-0 = <&user_buttons_pins>; | |
| 613 | + #address-cells = <1>; | |
| 614 | + #size-cells = <0>; | |
| 615 | + | |
| 616 | + button@0 { | |
| 617 | + label = "home"; | |
| 618 | + linux,code = <KEY_HOME>; | |
| 619 | + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; | |
| 620 | + gpio-key,wakeup; | |
| 621 | + }; | |
| 622 | + | |
| 623 | + button@1 { | |
| 624 | + label = "menu"; | |
| 625 | + linux,code = <KEY_MENU>; | |
| 626 | + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; | |
| 627 | + gpio-key,wakeup; | |
| 628 | + }; | |
| 629 | + | |
| 630 | + buttons@2 { | |
| 631 | + label = "power"; | |
| 632 | + linux,code = <KEY_POWER>; | |
| 633 | + gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; | |
| 634 | + gpio-key,wakeup; | |
| 635 | + }; | |
| 636 | +}; | |
| 637 | + | |
| 638 | +&am33xx_pinmux { | |
| 639 | + user_leds_pins: pinmux_user_leds { | |
| 640 | + pinctrl-single,pins = < | |
| 641 | + 0x50 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a4.gpio1_20 */ | |
| 642 | + 0x54 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ | |
| 643 | + >; | |
| 644 | + }; | |
| 645 | + | |
| 646 | + user_buttons_pins: pinmux_user_buttons { | |
| 647 | + pinctrl-single,pins = < | |
| 648 | + 0x58 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ | |
| 649 | + 0x5C (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a7.gpio1_21 */ | |
| 650 | + 0x164 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio0_7 */ | |
| 651 | + >; | |
| 652 | + }; | |
| 653 | +}; | |
| @@ -347,6 +347,15 @@ · 346 unmodified lines | ||
| 347 | 347 | status = "disabled"; |
| 348 | 348 | }; |
| 349 | 349 | |
| 350 | + mailbox: mailbox@480C8000 { | |
| 351 | + compatible = "ti,omap4-mailbox"; | |
| 352 | + reg = <0x480C8000 0x200>; | |
| 353 | + interrupts = <77>; | |
| 354 | + ti,hwmods = "mailbox"; | |
| 355 | + ti,mbox-num-users = <4>; | |
| 356 | + ti,mbox-num-fifos = <8>; | |
| 357 | + }; | |
| 358 | + | |
| 350 | 359 | timer1: timer@44e31000 { |
| 351 | 360 | compatible = "ti,am335x-timer-1ms"; |
| 352 | 361 | reg = <0x44e31000 0x400>; |
| @@ -30,7 +30,7 @@ · 29 unmodified lines | ||
| 30 | 30 | cpus { |
| 31 | 31 | #address-cells = <1>; |
| 32 | 32 | #size-cells = <0>; |
| 33 | − cpu@0 { | |
| 33 | + cpu: cpu@0 { | |
| 34 | 34 | compatible = "arm,cortex-a9"; |
| 35 | 35 | device_type = "cpu"; |
| 36 | 36 | reg = <0>; |
| @@ -168,9 +168,6 @@ · 131 unmodified lines | ||
| 168 | 168 | ti,hwmods = "mailbox"; |
| 169 | 169 | ti,mbox-num-users = <4>; |
| 170 | 170 | ti,mbox-num-fifos = <8>; |
| 171 | − ti,mbox-names = "wkup_m3"; | |
| 172 | − ti,mbox-data = <0 0 0 0>; | |
| 173 | − status = "disabled"; | |
| 174 | 171 | }; |
| 175 | 172 | |
| 176 | 173 | timer1: timer@44e31000 { |
| @@ -270,7 +267,7 @@ · 93 unmodified lines | ||
| 270 | 267 | ti,hwmods = "counter_32k"; |
| 271 | 268 | }; |
| 272 | 269 | |
| 273 | − rtc@44e3e000 { | |
| 270 | + rtc: rtc@44e3e000 { | |
| 274 | 271 | compatible = "ti,am4372-rtc","ti,da830-rtc"; |
| 275 | 272 | reg = <0x44e3e000 0x1000>; |
| 276 | 273 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH |
| @@ -279,7 +276,7 @@ · 2 unmodified lines | ||
| 279 | 276 | status = "disabled"; |
| 280 | 277 | }; |
| 281 | 278 | |
| 282 | − wdt@44e35000 { | |
| 279 | + wdt: wdt@44e35000 { | |
| 283 | 280 | compatible = "ti,am4372-wdt","ti,omap3-wdt"; |
| 284 | 281 | reg = <0x44e35000 0x1000>; |
| 285 | 282 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -871,7 +868,7 @@ · 585 unmodified lines | ||
| 871 | 868 | #size-cells = <1>; |
| 872 | 869 | ranges; |
| 873 | 870 | |
| 874 | − dispc@4832a400 { | |
| 871 | + dispc: dispc@4832a400 { | |
| 875 | 872 | compatible = "ti,omap3-dispc"; |
| 876 | 873 | reg = <0x4832a400 0x400>; |
| 877 | 874 | interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -257,16 +257,73 @@ · 256 unmodified lines | ||
| 257 | 257 | }; |
| 258 | 258 | |
| 259 | 259 | &i2c0 { |
| 260 | − status = "okay"; | |
| 261 | − pinctrl-names = "default"; | |
| 262 | − pinctrl-0 = <&i2c0_pins>; | |
| 260 | + status = "okay"; | |
| 261 | + pinctrl-names = "default"; | |
| 262 | + pinctrl-0 = <&i2c0_pins>; | |
| 263 | + clock-frequency = <400000>; | |
| 264 | + | |
| 265 | + tps65218: tps65218@24 { | |
| 266 | + reg = <0x24>; | |
| 267 | + compatible = "ti,tps65218"; | |
| 268 | + interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ | |
| 269 | + interrupt-parent = <&gic>; | |
| 270 | + interrupt-controller; | |
| 271 | + #interrupt-cells = <2>; | |
| 272 | + | |
| 273 | + dcdc1: regulator-dcdc1 { | |
| 274 | + compatible = "ti,tps65218-dcdc1"; | |
| 275 | + regulator-name = "vdd_core"; | |
| 276 | + regulator-min-microvolt = <912000>; | |
| 277 | + regulator-max-microvolt = <1144000>; | |
| 278 | + regulator-boot-on; | |
| 279 | + regulator-always-on; | |
| 280 | + }; | |
| 281 | + | |
| 282 | + dcdc2: regulator-dcdc2 { | |
| 283 | + compatible = "ti,tps65218-dcdc2"; | |
| 284 | + regulator-name = "vdd_mpu"; | |
| 285 | + regulator-min-microvolt = <912000>; | |
| 286 | + regulator-max-microvolt = <1378000>; | |
| 287 | + regulator-boot-on; | |
| 288 | + regulator-always-on; | |
| 289 | + }; | |
| 290 | + | |
| 291 | + dcdc3: regulator-dcdc3 { | |
| 292 | + compatible = "ti,tps65218-dcdc3"; | |
| 293 | + regulator-name = "vdcdc3"; | |
| 294 | + regulator-min-microvolt = <1350000>; | |
| 295 | + regulator-max-microvolt = <1350000>; | |
| 296 | + regulator-boot-on; | |
| 297 | + regulator-always-on; | |
| 298 | + }; | |
| 299 | + dcdc5: regulator-dcdc5 { | |
| 300 | + compatible = "ti,tps65218-dcdc5"; | |
| 301 | + regulator-name = "v1_0bat"; | |
| 302 | + regulator-min-microvolt = <1000000>; | |
| 303 | + regulator-max-microvolt = <1000000>; | |
| 304 | + }; | |
| 305 | + | |
| 306 | + dcdc6: regulator-dcdc6 { | |
| 307 | + compatible = "ti,tps65218-dcdc6"; | |
| 308 | + regulator-name = "v1_8bat"; | |
| 309 | + regulator-min-microvolt = <1800000>; | |
| 310 | + regulator-max-microvolt = <1800000>; | |
| 311 | + }; | |
| 312 | + | |
| 313 | + ldo1: regulator-ldo1 { | |
| 314 | + compatible = "ti,tps65218-ldo1"; | |
| 315 | + regulator-min-microvolt = <1800000>; | |
| 316 | + regulator-max-microvolt = <1800000>; | |
| 317 | + regulator-boot-on; | |
| 318 | + regulator-always-on; | |
| 319 | + }; | |
| 320 | + }; | |
| 263 | 321 | }; |
| 264 | 322 | |
| 265 | 323 | &i2c1 { |
| 266 | − status = "okay"; | |
| 267 | − pinctrl-names = "default"; | |
| 268 | − pinctrl-0 = <&i2c1_pins>; | |
| 269 | − | |
| 324 | + status = "okay"; | |
| 325 | + pinctrl-names = "default"; | |
| 326 | + pinctrl-0 = <&i2c1_pins>; | |
| 270 | 327 | pixcir_ts@5c { |
| 271 | 328 | compatible = "pixcir,pixcir_tangoc"; |
| 272 | 329 | pinctrl-names = "default"; |
| @@ -277,8 +334,8 @@ · 4 unmodified lines | ||
| 277 | 334 | |
| 278 | 335 | attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; |
| 279 | 336 | |
| 280 | − x-size = <1024>; | |
| 281 | − y-size = <600>; | |
| 337 | + touchscreen-size-x = <1024>; | |
| 338 | + touchscreen-size-y = <600>; | |
| 282 | 339 | }; |
| 283 | 340 | }; |
| 284 | 341 | |
| @@ -0,0 +1,613 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | |
| 3 | + * | |
| 4 | + * This program is free software; you can redistribute it and/or modify | |
| 5 | + * it under the terms of the GNU General Public License version 2 as | |
| 6 | + * published by the Free Software Foundation. | |
| 7 | + */ | |
| 8 | + | |
| 9 | +/* AM437x SK EVM */ | |
| 10 | + | |
| 11 | +/dts-v1/; | |
| 12 | + | |
| 13 | +#include "am4372.dtsi" | |
| 14 | +#include <dt-bindings/pinctrl/am43xx.h> | |
| 15 | +#include <dt-bindings/pwm/pwm.h> | |
| 16 | +#include <dt-bindings/gpio/gpio.h> | |
| 17 | +#include <dt-bindings/input/input.h> | |
| 18 | + | |
| 19 | +/ { | |
| 20 | + model = "TI AM437x SK EVM"; | |
| 21 | + compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43"; | |
| 22 | + | |
| 23 | + aliases { | |
| 24 | + display0 = &lcd0; | |
| 25 | + }; | |
| 26 | + | |
| 27 | + backlight { | |
| 28 | + compatible = "pwm-backlight"; | |
| 29 | + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; | |
| 30 | + brightness-levels = <0 51 53 56 62 75 101 152 255>; | |
| 31 | + default-brightness-level = <8>; | |
| 32 | + }; | |
| 33 | + | |
| 34 | + sound { | |
| 35 | + compatible = "ti,da830-evm-audio"; | |
| 36 | + ti,model = "AM437x-SK-EVM"; | |
| 37 | + ti,audio-codec = <&tlv320aic3106>; | |
| 38 | + ti,mcasp-controller = <&mcasp1>; | |
| 39 | + ti,codec-clock-rate = <24000000>; | |
| 40 | + ti,audio-routing = | |
| 41 | + "Headphone Jack", "HPLOUT", | |
| 42 | + "Headphone Jack", "HPROUT"; | |
| 43 | + }; | |
| 44 | + | |
| 45 | + matrix_keypad: matrix_keypad@0 { | |
| 46 | + compatible = "gpio-matrix-keypad"; | |
| 47 | + | |
| 48 | + pinctrl-names = "default"; | |
| 49 | + pinctrl-0 = <&matrix_keypad_pins>; | |
| 50 | + | |
| 51 | + debounce-delay-ms = <5>; | |
| 52 | + col-scan-delay-us = <1500>; | |
| 53 | + | |
| 54 | + row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ | |
| 55 | + &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ | |
| 56 | + | |
| 57 | + col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */ | |
| 58 | + &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */ | |
| 59 | + | |
| 60 | + linux,keymap = < | |
| 61 | + MATRIX_KEY(0, 0, KEY_DOWN) | |
| 62 | + MATRIX_KEY(0, 1, KEY_RIGHT) | |
| 63 | + MATRIX_KEY(1, 0, KEY_LEFT) | |
| 64 | + MATRIX_KEY(1, 1, KEY_UP) | |
| 65 | + >; | |
| 66 | + }; | |
| 67 | + | |
| 68 | + leds { | |
| 69 | + compatible = "gpio-leds"; | |
| 70 | + | |
| 71 | + pinctrl-names = "default"; | |
| 72 | + pinctrl-0 = <&leds_pins>; | |
| 73 | + | |
| 74 | + led@0 { | |
| 75 | + label = "am437x-sk:red:heartbeat"; | |
| 76 | + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ | |
| 77 | + linux,default-trigger = "heartbeat"; | |
| 78 | + default-state = "off"; | |
| 79 | + }; | |
| 80 | + | |
| 81 | + led@1 { | |
| 82 | + label = "am437x-sk:green:mmc1"; | |
| 83 | + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ | |
| 84 | + linux,default-trigger = "mmc0"; | |
| 85 | + default-state = "off"; | |
| 86 | + }; | |
| 87 | + | |
| 88 | + led@2 { | |
| 89 | + label = "am437x-sk:blue:cpu0"; | |
| 90 | + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ | |
| 91 | + linux,default-trigger = "cpu0"; | |
| 92 | + default-state = "off"; | |
| 93 | + }; | |
| 94 | + | |
| 95 | + led@3 { | |
| 96 | + label = "am437x-sk:blue:usr3"; | |
| 97 | + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ | |
| 98 | + default-state = "off"; | |
| 99 | + }; | |
| 100 | + }; | |
| 101 | + | |
| 102 | + lcd0: display { | |
| 103 | + compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; | |
| 104 | + label = "lcd"; | |
| 105 | + | |
| 106 | + pinctrl-names = "default"; | |
| 107 | + pinctrl-0 = <&lcd_pins>; | |
| 108 | + | |
| 109 | + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; | |
| 110 | + | |
| 111 | + panel-timing { | |
| 112 | + clock-frequency = <9000000>; | |
| 113 | + hactive = <480>; | |
| 114 | + vactive = <272>; | |
| 115 | + hfront-porch = <8>; | |
| 116 | + hback-porch = <43>; | |
| 117 | + hsync-len = <4>; | |
| 118 | + vback-porch = <12>; | |
| 119 | + vfront-porch = <4>; | |
| 120 | + vsync-len = <10>; | |
| 121 | + hsync-active = <0>; | |
| 122 | + vsync-active = <0>; | |
| 123 | + de-active = <1>; | |
| 124 | + pixelclk-active = <1>; | |
| 125 | + }; | |
| 126 | + | |
| 127 | + port { | |
| 128 | + lcd_in: endpoint { | |
| 129 | + remote-endpoint = <&dpi_out>; | |
| 130 | + }; | |
| 131 | + }; | |
| 132 | + }; | |
| 133 | +}; | |
| 134 | + | |
| 135 | +&am43xx_pinmux { | |
| 136 | + matrix_keypad_pins: matrix_keypad_pins { | |
| 137 | + pinctrl-single,pins = < | |
| 138 | + 0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ | |
| 139 | + 0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ | |
| 140 | + 0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ | |
| 141 | + 0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ | |
| 142 | + >; | |
| 143 | + }; | |
| 144 | + | |
| 145 | + leds_pins: leds_pins { | |
| 146 | + pinctrl-single,pins = < | |
| 147 | + 0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ | |
| 148 | + 0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ | |
| 149 | + 0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ | |
| 150 | + 0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ | |
| 151 | + >; | |
| 152 | + }; | |
| 153 | + | |
| 154 | + i2c0_pins: i2c0_pins { | |
| 155 | + pinctrl-single,pins = < | |
| 156 | + 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | |
| 157 | + 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | |
| 158 | + >; | |
| 159 | + }; | |
| 160 | + | |
| 161 | + i2c1_pins: i2c1_pins { | |
| 162 | + pinctrl-single,pins = < | |
| 163 | + 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ | |
| 164 | + 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ | |
| 165 | + >; | |
| 166 | + }; | |
| 167 | + | |
| 168 | + mmc1_pins: pinmux_mmc1_pins { | |
| 169 | + pinctrl-single,pins = < | |
| 170 | + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ | |
| 171 | + >; | |
| 172 | + }; | |
| 173 | + | |
| 174 | + ecap0_pins: backlight_pins { | |
| 175 | + pinctrl-single,pins = < | |
| 176 | + 0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ | |
| 177 | + >; | |
| 178 | + }; | |
| 179 | + | |
| 180 | + edt_ft5306_ts_pins: edt_ft5306_ts_pins { | |
| 181 | + pinctrl-single,pins = < | |
| 182 | + 0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ | |
| 183 | + 0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ | |
| 184 | + >; | |
| 185 | + }; | |
| 186 | + | |
| 187 | + cpsw_default: cpsw_default { | |
| 188 | + pinctrl-single,pins = < | |
| 189 | + /* Slave 1 */ | |
| 190 | + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ | |
| 191 | + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ | |
| 192 | + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ | |
| 193 | + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ | |
| 194 | + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ | |
| 195 | + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ | |
| 196 | + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ | |
| 197 | + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ | |
| 198 | + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ | |
| 199 | + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ | |
| 200 | + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ | |
| 201 | + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ | |
| 202 | + | |
| 203 | + /* Slave 2 */ | |
| 204 | + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ | |
| 205 | + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ | |
| 206 | + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ | |
| 207 | + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ | |
| 208 | + 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ | |
| 209 | + 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ | |
| 210 | + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ | |
| 211 | + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ | |
| 212 | + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ | |
| 213 | + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ | |
| 214 | + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ | |
| 215 | + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ | |
| 216 | + >; | |
| 217 | + }; | |
| 218 | + | |
| 219 | + cpsw_sleep: cpsw_sleep { | |
| 220 | + pinctrl-single,pins = < | |
| 221 | + /* Slave 1 reset value */ | |
| 222 | + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 223 | + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 224 | + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 225 | + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 226 | + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 227 | + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 228 | + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 229 | + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 230 | + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 231 | + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 232 | + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 233 | + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 234 | + | |
| 235 | + /* Slave 2 reset value */ | |
| 236 | + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 237 | + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 238 | + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 239 | + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 240 | + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 241 | + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 242 | + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 243 | + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 244 | + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 245 | + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 246 | + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 247 | + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 248 | + >; | |
| 249 | + }; | |
| 250 | + | |
| 251 | + davinci_mdio_default: davinci_mdio_default { | |
| 252 | + pinctrl-single,pins = < | |
| 253 | + /* MDIO */ | |
| 254 | + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ | |
| 255 | + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | |
| 256 | + >; | |
| 257 | + }; | |
| 258 | + | |
| 259 | + davinci_mdio_sleep: davinci_mdio_sleep { | |
| 260 | + pinctrl-single,pins = < | |
| 261 | + /* MDIO reset value */ | |
| 262 | + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 263 | + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 264 | + >; | |
| 265 | + }; | |
| 266 | + | |
| 267 | + dss_pins: dss_pins { | |
| 268 | + pinctrl-single,pins = < | |
| 269 | + 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ | |
| 270 | + 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) | |
| 271 | + 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) | |
| 272 | + 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1) | |
| 273 | + 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) | |
| 274 | + 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) | |
| 275 | + 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) | |
| 276 | + 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ | |
| 277 | + 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ | |
| 278 | + 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 279 | + 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 280 | + 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 281 | + 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 282 | + 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 283 | + 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 284 | + 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 285 | + 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 286 | + 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 287 | + 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 288 | + 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 289 | + 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 290 | + 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 291 | + 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
| 292 | + 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ | |
| 293 | + 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ | |
| 294 | + 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ | |
| 295 | + 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ | |
| 296 | + 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ | |
| 297 | + | |
| 298 | + >; | |
| 299 | + }; | |
| 300 | + | |
| 301 | + qspi_pins: qspi_pins { | |
| 302 | + pinctrl-single,pins = < | |
| 303 | + 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ | |
| 304 | + 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ | |
| 305 | + 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ | |
| 306 | + 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ | |
| 307 | + 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */ | |
| 308 | + 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ | |
| 309 | + >; | |
| 310 | + }; | |
| 311 | + | |
| 312 | + mcasp1_pins: mcasp1_pins { | |
| 313 | + pinctrl-single,pins = < | |
| 314 | + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ | |
| 315 | + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ | |
| 316 | + 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ | |
| 317 | + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ | |
| 318 | + >; | |
| 319 | + }; | |
| 320 | + | |
| 321 | + lcd_pins: lcd_pins { | |
| 322 | + pinctrl-single,pins = < | |
| 323 | + /* GPIO 5_8 to select LCD / HDMI */ | |
| 324 | + 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) | |
| 325 | + >; | |
| 326 | + }; | |
| 327 | +}; | |
| 328 | + | |
| 329 | +&i2c0 { | |
| 330 | + status = "okay"; | |
| 331 | + pinctrl-names = "default"; | |
| 332 | + pinctrl-0 = <&i2c0_pins>; | |
| 333 | + clock-frequency = <400000>; | |
| 334 | + | |
| 335 | + tps@24 { | |
| 336 | + compatible = "ti,tps65218"; | |
| 337 | + reg = <0x24>; | |
| 338 | + interrupt-parent = <&gic>; | |
| 339 | + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 340 | + interrupt-controller; | |
| 341 | + #interrupt-cells = <2>; | |
| 342 | + | |
| 343 | + dcdc1: regulator-dcdc1 { | |
| 344 | + compatible = "ti,tps65218-dcdc1"; | |
| 345 | + /* VDD_CORE limits min of OPP50 and max of OPP100 */ | |
| 346 | + regulator-name = "vdd_core"; | |
| 347 | + regulator-min-microvolt = <912000>; | |
| 348 | + regulator-max-microvolt = <1144000>; | |
| 349 | + regulator-boot-on; | |
| 350 | + regulator-always-on; | |
| 351 | + }; | |
| 352 | + | |
| 353 | + dcdc2: regulator-dcdc2 { | |
| 354 | + compatible = "ti,tps65218-dcdc2"; | |
| 355 | + /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ | |
| 356 | + regulator-name = "vdd_mpu"; | |
| 357 | + regulator-min-microvolt = <912000>; | |
| 358 | + regulator-max-microvolt = <1378000>; | |
| 359 | + regulator-boot-on; | |
| 360 | + regulator-always-on; | |
| 361 | + }; | |
| 362 | + | |
| 363 | + dcdc3: regulator-dcdc3 { | |
| 364 | + compatible = "ti,tps65218-dcdc3"; | |
| 365 | + regulator-name = "vdds_ddr"; | |
| 366 | + regulator-min-microvolt = <1350000>; | |
| 367 | + regulator-max-microvolt = <1350000>; | |
| 368 | + regulator-boot-on; | |
| 369 | + regulator-always-on; | |
| 370 | + }; | |
| 371 | + | |
| 372 | + dcdc4: regulator-dcdc4 { | |
| 373 | + compatible = "ti,tps65218-dcdc4"; | |
| 374 | + regulator-name = "v3_3d"; | |
| 375 | + regulator-min-microvolt = <3300000>; | |
| 376 | + regulator-max-microvolt = <3300000>; | |
| 377 | + regulator-boot-on; | |
| 378 | + regulator-always-on; | |
| 379 | + }; | |
| 380 | + | |
| 381 | + ldo1: regulator-ldo1 { | |
| 382 | + compatible = "ti,tps65218-ldo1"; | |
| 383 | + regulator-name = "v1_8d"; | |
| 384 | + regulator-min-microvolt = <1800000>; | |
| 385 | + regulator-max-microvolt = <1800000>; | |
| 386 | + regulator-boot-on; | |
| 387 | + regulator-always-on; | |
| 388 | + }; | |
| 389 | + | |
| 390 | + }; | |
| 391 | + | |
| 392 | + at24@50 { | |
| 393 | + compatible = "at24,24c256"; | |
| 394 | + pagesize = <64>; | |
| 395 | + reg = <0x50>; | |
| 396 | + }; | |
| 397 | +}; | |
| 398 | + | |
| 399 | +&i2c1 { | |
| 400 | + status = "okay"; | |
| 401 | + pinctrl-names = "default"; | |
| 402 | + pinctrl-0 = <&i2c1_pins>; | |
| 403 | + clock-frequency = <400000>; | |
| 404 | + | |
| 405 | + edt-ft5306@38 { | |
| 406 | + status = "okay"; | |
| 407 | + compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; | |
| 408 | + pinctrl-names = "default"; | |
| 409 | + pinctrl-0 = <&edt_ft5306_ts_pins>; | |
| 410 | + | |
| 411 | + reg = <0x38>; | |
| 412 | + interrupt-parent = <&gpio0>; | |
| 413 | + interrupts = <31 0>; | |
| 414 | + | |
| 415 | + wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; | |
| 416 | + | |
| 417 | + touchscreen-size-x = <480>; | |
| 418 | + touchscreen-size-y = <272>; | |
| 419 | + }; | |
| 420 | + | |
| 421 | + tlv320aic3106: tlv320aic3106@1b { | |
| 422 | + compatible = "ti,tlv320aic3106"; | |
| 423 | + reg = <0x1b>; | |
| 424 | + status = "okay"; | |
| 425 | + | |
| 426 | + /* Regulators */ | |
| 427 | + AVDD-supply = <&dcdc4>; | |
| 428 | + IOVDD-supply = <&dcdc4>; | |
| 429 | + DRVDD-supply = <&dcdc4>; | |
| 430 | + DVDD-supply = <&ldo1>; | |
| 431 | + }; | |
| 432 | + | |
| 433 | + lis331dlh@18 { | |
| 434 | + compatible = "st,lis331dlh"; | |
| 435 | + reg = <0x18>; | |
| 436 | + status = "okay"; | |
| 437 | + | |
| 438 | + Vdd-supply = <&dcdc4>; | |
| 439 | + Vdd_IO-supply = <&dcdc4>; | |
| 440 | + interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>; | |
| 441 | + }; | |
| 442 | +}; | |
| 443 | + | |
| 444 | +&epwmss0 { | |
| 445 | + status = "okay"; | |
| 446 | +}; | |
| 447 | + | |
| 448 | +&ecap0 { | |
| 449 | + status = "okay"; | |
| 450 | + pinctrl-names = "default"; | |
| 451 | + pinctrl-0 = <&ecap0_pins>; | |
| 452 | +}; | |
| 453 | + | |
| 454 | +&gpio0 { | |
| 455 | + status = "okay"; | |
| 456 | +}; | |
| 457 | + | |
| 458 | +&gpio1 { | |
| 459 | + status = "okay"; | |
| 460 | +}; | |
| 461 | + | |
| 462 | +&gpio5 { | |
| 463 | + status = "okay"; | |
| 464 | +}; | |
| 465 | + | |
| 466 | +&mmc1 { | |
| 467 | + status = "okay"; | |
| 468 | + pinctrl-names = "default"; | |
| 469 | + pinctrl-0 = <&mmc1_pins>; | |
| 470 | + | |
| 471 | + vmmc-supply = <&dcdc4>; | |
| 472 | + bus-width = <4>; | |
| 473 | + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; | |
| 474 | +}; | |
| 475 | + | |
| 476 | +&usb2_phy1 { | |
| 477 | + status = "okay"; | |
| 478 | +}; | |
| 479 | + | |
| 480 | +&usb1 { | |
| 481 | + dr_mode = "peripheral"; | |
| 482 | + status = "okay"; | |
| 483 | +}; | |
| 484 | + | |
| 485 | +&usb2_phy2 { | |
| 486 | + status = "okay"; | |
| 487 | +}; | |
| 488 | + | |
| 489 | +&usb2 { | |
| 490 | + dr_mode = "host"; | |
| 491 | + status = "okay"; | |
| 492 | +}; | |
| 493 | + | |
| 494 | +&qspi { | |
| 495 | + status = "okay"; | |
| 496 | + pinctrl-names = "default"; | |
| 497 | + pinctrl-0 = <&qspi_pins>; | |
| 498 | + | |
| 499 | + spi-max-frequency = <48000000>; | |
| 500 | + m25p80@0 { | |
| 501 | + compatible = "mx66l51235l"; | |
| 502 | + spi-max-frequency = <48000000>; | |
| 503 | + reg = <0>; | |
| 504 | + spi-cpol; | |
| 505 | + spi-cpha; | |
| 506 | + spi-tx-bus-width = <1>; | |
| 507 | + spi-rx-bus-width = <4>; | |
| 508 | + #address-cells = <1>; | |
| 509 | + #size-cells = <1>; | |
| 510 | + | |
| 511 | + /* MTD partition table. | |
| 512 | + * The ROM checks the first 512KiB | |
| 513 | + * for a valid file to boot(XIP). | |
| 514 | + */ | |
| 515 | + partition@0 { | |
| 516 | + label = "QSPI.U_BOOT"; | |
| 517 | + reg = <0x00000000 0x000080000>; | |
| 518 | + }; | |
| 519 | + partition@1 { | |
| 520 | + label = "QSPI.U_BOOT.backup"; | |
| 521 | + reg = <0x00080000 0x00080000>; | |
| 522 | + }; | |
| 523 | + partition@2 { | |
| 524 | + label = "QSPI.U-BOOT-SPL_OS"; | |
| 525 | + reg = <0x00100000 0x00010000>; | |
| 526 | + }; | |
| 527 | + partition@3 { | |
| 528 | + label = "QSPI.U_BOOT_ENV"; | |
| 529 | + reg = <0x00110000 0x00010000>; | |
| 530 | + }; | |
| 531 | + partition@4 { | |
| 532 | + label = "QSPI.U-BOOT-ENV.backup"; | |
| 533 | + reg = <0x00120000 0x00010000>; | |
| 534 | + }; | |
| 535 | + partition@5 { | |
| 536 | + label = "QSPI.KERNEL"; | |
| 537 | + reg = <0x00130000 0x0800000>; | |
| 538 | + }; | |
| 539 | + partition@6 { | |
| 540 | + label = "QSPI.FILESYSTEM"; | |
| 541 | + reg = <0x00930000 0x36D0000>; | |
| 542 | + }; | |
| 543 | + }; | |
| 544 | +}; | |
| 545 | + | |
| 546 | +&mac { | |
| 547 | + pinctrl-names = "default", "sleep"; | |
| 548 | + pinctrl-0 = <&cpsw_default>; | |
| 549 | + pinctrl-1 = <&cpsw_sleep>; | |
| 550 | + dual_emac = <1>; | |
| 551 | + status = "okay"; | |
| 552 | +}; | |
| 553 | + | |
| 554 | +&davinci_mdio { | |
| 555 | + pinctrl-names = "default", "sleep"; | |
| 556 | + pinctrl-0 = <&davinci_mdio_default>; | |
| 557 | + pinctrl-1 = <&davinci_mdio_sleep>; | |
| 558 | + status = "okay"; | |
| 559 | +}; | |
| 560 | + | |
| 561 | +&cpsw_emac0 { | |
| 562 | + phy_id = <&davinci_mdio>, <4>; | |
| 563 | + phy-mode = "rgmii"; | |
| 564 | + dual_emac_res_vlan = <1>; | |
| 565 | +}; | |
| 566 | + | |
| 567 | +&cpsw_emac1 { | |
| 568 | + phy_id = <&davinci_mdio>, <5>; | |
| 569 | + phy-mode = "rgmii"; | |
| 570 | + dual_emac_res_vlan = <2>; | |
| 571 | +}; | |
| 572 | + | |
| 573 | +&elm { | |
| 574 | + status = "okay"; | |
| 575 | +}; | |
| 576 | + | |
| 577 | +&mcasp1 { | |
| 578 | + pinctrl-names = "default"; | |
| 579 | + pinctrl-0 = <&mcasp1_pins>; | |
| 580 | + | |
| 581 | + status = "okay"; | |
| 582 | + | |
| 583 | + op-mode = <0>; | |
| 584 | + tdm-slots = <2>; | |
| 585 | + serial-dir = < | |
| 586 | + 0 0 1 2 | |
| 587 | + >; | |
| 588 | + | |
| 589 | + tx-num-evt = <1>; | |
| 590 | + rx-num-evt = <1>; | |
| 591 | +}; | |
| 592 | + | |
| 593 | +&dss { | |
| 594 | + status = "okay"; | |
| 595 | + | |
| 596 | + pinctrl-names = "default"; | |
| 597 | + pinctrl-0 = <&dss_pins>; | |
| 598 | + | |
| 599 | + port { | |
| 600 | + dpi_out: endpoint@0 { | |
| 601 | + remote-endpoint = <&lcd_in>; | |
| 602 | + data-lines = <24>; | |
| 603 | + }; | |
| 604 | + }; | |
| 605 | +}; | |
| 606 | + | |
| 607 | +&rtc { | |
| 608 | + status = "okay"; | |
| 609 | +}; | |
| 610 | + | |
| 611 | +&wdt { | |
| 612 | + status = "okay"; | |
| 613 | +}; | |
| @@ -327,6 +327,65 @@ · 326 unmodified lines | ||
| 327 | 327 | status = "okay"; |
| 328 | 328 | pinctrl-names = "default"; |
| 329 | 329 | pinctrl-0 = <&i2c0_pins>; |
| 330 | + clock-frequency = <400000>; | |
| 331 | + | |
| 332 | + tps65218: tps65218@24 { | |
| 333 | + reg = <0x24>; | |
| 334 | + compatible = "ti,tps65218"; | |
| 335 | + interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ | |
| 336 | + interrupt-parent = <&gic>; | |
| 337 | + interrupt-controller; | |
| 338 | + #interrupt-cells = <2>; | |
| 339 | + | |
| 340 | + dcdc1: regulator-dcdc1 { | |
| 341 | + compatible = "ti,tps65218-dcdc1"; | |
| 342 | + regulator-name = "vdd_core"; | |
| 343 | + regulator-min-microvolt = <912000>; | |
| 344 | + regulator-max-microvolt = <1144000>; | |
| 345 | + regulator-boot-on; | |
| 346 | + regulator-always-on; | |
| 347 | + }; | |
| 348 | + | |
| 349 | + dcdc2: regulator-dcdc2 { | |
| 350 | + compatible = "ti,tps65218-dcdc2"; | |
| 351 | + regulator-name = "vdd_mpu"; | |
| 352 | + regulator-min-microvolt = <912000>; | |
| 353 | + regulator-max-microvolt = <1378000>; | |
| 354 | + regulator-boot-on; | |
| 355 | + regulator-always-on; | |
| 356 | + }; | |
| 357 | + | |
| 358 | + dcdc3: regulator-dcdc3 { | |
| 359 | + compatible = "ti,tps65218-dcdc3"; | |
| 360 | + regulator-name = "vdcdc3"; | |
| 361 | + regulator-min-microvolt = <1350000>; | |
| 362 | + regulator-max-microvolt = <1350000>; | |
| 363 | + regulator-boot-on; | |
| 364 | + regulator-always-on; | |
| 365 | + }; | |
| 366 | + | |
| 367 | + dcdc5: regulator-dcdc5 { | |
| 368 | + compatible = "ti,tps65218-dcdc5"; | |
| 369 | + regulator-name = "v1_0bat"; | |
| 370 | + regulator-min-microvolt = <1000000>; | |
| 371 | + regulator-max-microvolt = <1000000>; | |
| 372 | + }; | |
| 373 | + | |
| 374 | + dcdc6: regulator-dcdc6 { | |
| 375 | + compatible = "ti,tps65218-dcdc6"; | |
| 376 | + regulator-name = "v1_8bat"; | |
| 377 | + regulator-min-microvolt = <1800000>; | |
| 378 | + regulator-max-microvolt = <1800000>; | |
| 379 | + }; | |
| 380 | + | |
| 381 | + ldo1: regulator-ldo1 { | |
| 382 | + compatible = "ti,tps65218-ldo1"; | |
| 383 | + regulator-min-microvolt = <1800000>; | |
| 384 | + regulator-max-microvolt = <1800000>; | |
| 385 | + regulator-boot-on; | |
| 386 | + regulator-always-on; | |
| 387 | + }; | |
| 388 | + }; | |
| 330 | 389 | |
| 331 | 390 | at24@50 { |
| 332 | 391 | compatible = "at24,24c256"; |
| @@ -344,8 +403,8 @@ · 11 unmodified lines | ||
| 344 | 403 | |
| 345 | 404 | attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; |
| 346 | 405 | |
| 347 | − x-size = <1024>; | |
| 348 | − y-size = <600>; | |
| 406 | + touchscreen-size-x = <1024>; | |
| 407 | + touchscreen-size-y = <600>; | |
| 349 | 408 | }; |
| 350 | 409 | }; |
| 351 | 410 | |
| @@ -40,6 +40,14 @@ · 39 unmodified lines | ||
| 40 | 40 | compatible = "atmel,osc", "fixed-clock"; |
| 41 | 41 | clock-frequency = <18432000>; |
| 42 | 42 | }; |
| 43 | + | |
| 44 | + slow_xtal { | |
| 45 | + clock-frequency = <32768>; | |
| 46 | + }; | |
| 47 | + | |
| 48 | + main_xtal { | |
| 49 | + clock-frequency = <18432000>; | |
| 50 | + }; | |
| 43 | 51 | }; |
| 44 | 52 | |
| 45 | 53 | ahb { |
| @@ -123,6 +123,32 @@ · 122 unmodified lines | ||
| 123 | 123 | cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; |
| 124 | 124 | wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; |
| 125 | 125 | }; |
| 126 | + | |
| 127 | + mdio { | |
| 128 | + phy0: ethernet-phy@0 { | |
| 129 | + reg = <0>; | |
| 130 | + }; | |
| 131 | + | |
| 132 | + phy3: ethernet-phy@3 { | |
| 133 | + reg = <3>; | |
| 134 | + }; | |
| 135 | + }; | |
| 136 | + | |
| 137 | + ethernet@f0000 { | |
| 138 | + status = "okay"; | |
| 139 | + | |
| 140 | + eth0@c4000 { | |
| 141 | + status = "okay"; | |
| 142 | + phy = <&phy0>; | |
| 143 | + phy-mode = "rgmii-id"; | |
| 144 | + }; | |
| 145 | + | |
| 146 | + eth1@c5000 { | |
| 147 | + status = "okay"; | |
| 148 | + phy = <&phy3>; | |
| 149 | + phy-mode = "gmii"; | |
| 150 | + }; | |
| 151 | + }; | |
| 126 | 152 | }; |
| 127 | 153 | |
| 128 | 154 | pcie-controller { |
| @@ -25,6 +25,8 @@ · 24 unmodified lines | ||
| 25 | 25 | gpio0 = &gpio0; |
| 26 | 26 | gpio1 = &gpio1; |
| 27 | 27 | gpio2 = &gpio2; |
| 28 | + ethernet0 = ð0; | |
| 29 | + ethernet1 = ð1; | |
| 28 | 30 | }; |
| 29 | 31 | |
| 30 | 32 | clocks { |
| @@ -151,6 +153,38 @@ · 120 unmodified lines | ||
| 151 | 153 | <0xc100 0x100>; |
| 152 | 154 | }; |
| 153 | 155 | |
| 156 | + mdio { | |
| 157 | + #address-cells = <1>; | |
| 158 | + #size-cells = <0>; | |
| 159 | + compatible = "marvell,orion-mdio"; | |
| 160 | + reg = <0xc0054 0x4>; | |
| 161 | + clocks = <&gateclk 19>; | |
| 162 | + }; | |
| 163 | + | |
| 164 | + /* Network controller */ | |
| 165 | + ethernet@f0000 { | |
| 166 | + compatible = "marvell,armada-375-pp2"; | |
| 167 | + reg = <0xf0000 0xa000>, /* Packet Processor regs */ | |
| 168 | + <0xc0000 0x3060>, /* LMS regs */ | |
| 169 | + <0xc4000 0x100>, /* eth0 regs */ | |
| 170 | + <0xc5000 0x100>; /* eth1 regs */ | |
| 171 | + clocks = <&gateclk 3>, <&gateclk 19>; | |
| 172 | + clock-names = "pp_clk", "gop_clk"; | |
| 173 | + status = "disabled"; | |
| 174 | + | |
| 175 | + eth0: eth0@c4000 { | |
| 176 | + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| 177 | + port-id = <0>; | |
| 178 | + status = "disabled"; | |
| 179 | + }; | |
| 180 | + | |
| 181 | + eth1: eth1@c5000 { | |
| 182 | + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
| 183 | + port-id = <1>; | |
| 184 | + status = "disabled"; | |
| 185 | + }; | |
| 186 | + }; | |
| 187 | + | |
| 154 | 188 | spi0: spi@10600 { |
| 155 | 189 | compatible = "marvell,orion-spi"; |
| 156 | 190 | reg = <0x10600 0x50>; |
| @@ -286,6 +286,11 @@ · 285 unmodified lines | ||
| 286 | 286 | reg = <0x20800 0x10>; |
| 287 | 287 | }; |
| 288 | 288 | |
| 289 | + mpcore-soc-ctrl@20d20 { | |
| 290 | + compatible = "marvell,armada-380-mpcore-soc-ctrl"; | |
| 291 | + reg = <0x20d20 0x6c>; | |
| 292 | + }; | |
| 293 | + | |
| 289 | 294 | coherency-fabric@21010 { |
| 290 | 295 | compatible = "marvell,armada-380-coherency-fabric"; |
| 291 | 296 | reg = <0x21010 0x1c>; |
| @@ -0,0 +1,284 @@ | ||
| 1 | +/* | |
| 2 | + * Device Tree file for Lenovo Iomega ix4-300d | |
| 3 | + * | |
| 4 | + * Copyright (C) 2014, Benoit Masson <yahoo@perenite.com> | |
| 5 | + * | |
| 6 | + * This program is free software; you can redistribute it and/or | |
| 7 | + * modify it under the terms of the GNU General Public License | |
| 8 | + * as published by the Free Software Foundation; either version | |
| 9 | + * 2 of the License, or (at your option) any later version. | |
| 10 | + */ | |
| 11 | + | |
| 12 | +/dts-v1/; | |
| 13 | + | |
| 14 | +#include <dt-bindings/input/input.h> | |
| 15 | +#include <dt-bindings/gpio/gpio.h> | |
| 16 | +#include "armada-xp-mv78230.dtsi" | |
| 17 | + | |
| 18 | +/ { | |
| 19 | + model = "Lenovo Iomega ix4-300d"; | |
| 20 | + compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230", | |
| 21 | + "marvell,armadaxp", "marvell,armada-370-xp"; | |
| 22 | + | |
| 23 | + chosen { | |
| 24 | + bootargs = "console=ttyS0,115200 earlyprintk"; | |
| 25 | + stdout-path = "/soc/internal-regs/serial@12000"; | |
| 26 | + }; | |
| 27 | + | |
| 28 | + memory { | |
| 29 | + device_type = "memory"; | |
| 30 | + reg = <0 0x00000000 0 0x20000000>; /* 512MB */ | |
| 31 | + }; | |
| 32 | + | |
| 33 | + soc { | |
| 34 | + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 | |
| 35 | + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>; | |
| 36 | + | |
| 37 | + pcie-controller { | |
| 38 | + status = "okay"; | |
| 39 | + | |
| 40 | + /* Quad port sata: Marvell 88SX7042 */ | |
| 41 | + pcie@1,0 { | |
| 42 | + /* Port 0, Lane 0 */ | |
| 43 | + status = "okay"; | |
| 44 | + }; | |
| 45 | + | |
| 46 | + /* USB 3.0 xHCI controller: NEC D720200F1 */ | |
| 47 | + pcie@5,0 { | |
| 48 | + /* Port 1, Lane 0 */ | |
| 49 | + status = "okay"; | |
| 50 | + }; | |
| 51 | + }; | |
| 52 | + | |
| 53 | + internal-regs { | |
| 54 | + pinctrl { | |
| 55 | + poweroff_pin: poweroff-pin { | |
| 56 | + marvell,pins = "mpp24"; | |
| 57 | + marvell,function = "gpio"; | |
| 58 | + }; | |
| 59 | + | |
| 60 | + power_button_pin: power-button-pin { | |
| 61 | + marvell,pins = "mpp44"; | |
| 62 | + marvell,function = "gpio"; | |
| 63 | + }; | |
| 64 | + | |
| 65 | + reset_button_pin: reset-button-pin { | |
| 66 | + marvell,pins = "mpp45"; | |
| 67 | + marvell,function = "gpio"; | |
| 68 | + }; | |
| 69 | + select_button_pin: select-button-pin { | |
| 70 | + marvell,pins = "mpp41"; | |
| 71 | + marvell,function = "gpio"; | |
| 72 | + }; | |
| 73 | + | |
| 74 | + scroll_button_pin: scroll-button-pin { | |
| 75 | + marvell,pins = "mpp42"; | |
| 76 | + marvell,function = "gpio"; | |
| 77 | + }; | |
| 78 | + | |
| 79 | + hdd_led_pin: hdd-led-pin { | |
| 80 | + marvell,pins = "mpp26"; | |
| 81 | + marvell,function = "gpio"; | |
| 82 | + }; | |
| 83 | + }; | |
| 84 | + | |
| 85 | + serial@12000 { | |
| 86 | + status = "okay"; | |
| 87 | + }; | |
| 88 | + | |
| 89 | + mdio { | |
| 90 | + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ | |
| 91 | + reg = <0>; | |
| 92 | + }; | |
| 93 | + | |
| 94 | + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ | |
| 95 | + reg = <1>; | |
| 96 | + }; | |
| 97 | + }; | |
| 98 | + | |
| 99 | + ethernet@70000 { | |
| 100 | + status = "okay"; | |
| 101 | + phy = <&phy0>; | |
| 102 | + phy-mode = "rgmii-id"; | |
| 103 | + }; | |
| 104 | + | |
| 105 | + ethernet@74000 { | |
| 106 | + status = "okay"; | |
| 107 | + phy = <&phy1>; | |
| 108 | + phy-mode = "rgmii-id"; | |
| 109 | + }; | |
| 110 | + | |
| 111 | + usb@50000 { | |
| 112 | + status = "okay"; | |
| 113 | + }; | |
| 114 | + | |
| 115 | + usb@51000 { | |
| 116 | + status = "okay"; | |
| 117 | + }; | |
| 118 | + | |
| 119 | + i2c@11000 { | |
| 120 | + clock-frequency = <400000>; | |
| 121 | + status = "okay"; | |
| 122 | + | |
| 123 | + adt7473@2e { | |
| 124 | + compatible = "adi,adt7473"; | |
| 125 | + reg = <0x2e>; | |
| 126 | + }; | |
| 127 | + | |
| 128 | + pcf8563@51 { | |
| 129 | + compatible = "nxp,pcf8563"; | |
| 130 | + reg = <0x51>; | |
| 131 | + }; | |
| 132 | + | |
| 133 | + }; | |
| 134 | + | |
| 135 | + nand@d0000 { | |
| 136 | + status = "okay"; | |
| 137 | + num-cs = <1>; | |
| 138 | + marvell,nand-keep-config; | |
| 139 | + marvell,nand-enable-arbiter; | |
| 140 | + nand-on-flash-bbt; | |
| 141 | + | |
| 142 | + partition@0 { | |
| 143 | + label = "u-boot"; | |
| 144 | + reg = <0x0000000 0xe0000>; | |
| 145 | + read-only; | |
| 146 | + }; | |
| 147 | + | |
| 148 | + partition@e0000 { | |
| 149 | + label = "u-boot-env"; | |
| 150 | + reg = <0xe0000 0x20000>; | |
| 151 | + read-only; | |
| 152 | + }; | |
| 153 | + | |
| 154 | + partition@100000 { | |
| 155 | + label = "u-boot-env2"; | |
| 156 | + reg = <0x100000 0x20000>; | |
| 157 | + read-only; | |
| 158 | + }; | |
| 159 | + | |
| 160 | + partition@120000 { | |
| 161 | + label = "zImage"; | |
| 162 | + reg = <0x120000 0x400000>; | |
| 163 | + }; | |
| 164 | + | |
| 165 | + partition@520000 { | |
| 166 | + label = "initrd"; | |
| 167 | + reg = <0x520000 0x400000>; | |
| 168 | + }; | |
| 169 | + | |
| 170 | + partition@xE00000 { | |
| 171 | + label = "boot"; | |
| 172 | + reg = <0xE00000 0x3F200000>; | |
| 173 | + }; | |
| 174 | + | |
| 175 | + partition@flash { | |
| 176 | + label = "flash"; | |
| 177 | + reg = <0x0 0x40000000>; | |
| 178 | + }; | |
| 179 | + }; | |
| 180 | + }; | |
| 181 | + }; | |
| 182 | + | |
| 183 | + gpio-keys { | |
| 184 | + compatible = "gpio-keys"; | |
| 185 | + pinctrl-0 = <&power_button_pin &reset_button_pin | |
| 186 | + &select_button_pin &scroll_button_pin>; | |
| 187 | + pinctrl-names = "default"; | |
| 188 | + | |
| 189 | + power-button { | |
| 190 | + label = "Power Button"; | |
| 191 | + linux,code = <KEY_POWER>; | |
| 192 | + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; | |
| 193 | + }; | |
| 194 | + | |
| 195 | + reset-button { | |
| 196 | + label = "Reset Button"; | |
| 197 | + linux,code = <KEY_RESTART>; | |
| 198 | + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; | |
| 199 | + }; | |
| 200 | + | |
| 201 | + select-button { | |
| 202 | + label = "Select Button"; | |
| 203 | + linux,code = <BTN_SELECT>; | |
| 204 | + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; | |
| 205 | + }; | |
| 206 | + | |
| 207 | + scroll-button { | |
| 208 | + label = "Scroll Button"; | |
| 209 | + linux,code = <KEY_SCROLLDOWN>; | |
| 210 | + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; | |
| 211 | + }; | |
| 212 | + }; | |
| 213 | + | |
| 214 | + spi3 { | |
| 215 | + compatible = "spi-gpio"; | |
| 216 | + status = "okay"; | |
| 217 | + gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>; | |
| 218 | + gpio-mosi = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/ | |
| 219 | + cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; | |
| 220 | + num-chipselects = <1>; | |
| 221 | + #address-cells = <1>; | |
| 222 | + #size-cells = <0>; | |
| 223 | + | |
| 224 | + gpio_spi: gpio_spi@0 { | |
| 225 | + compatible = "fairchild,74hc595"; | |
| 226 | + gpio-controller; | |
| 227 | + #gpio-cells = <2>; | |
| 228 | + reg = <0>; | |
| 229 | + registers-number = <2>; | |
| 230 | + spi-max-frequency = <100000>; | |
| 231 | + }; | |
| 232 | + }; | |
| 233 | + | |
| 234 | + gpio-leds { | |
| 235 | + compatible = "gpio-leds"; | |
| 236 | + pinctrl-0 = <&hdd_led_pin>; | |
| 237 | + pinctrl-names = "default"; | |
| 238 | + | |
| 239 | + hdd-led { | |
| 240 | + label = "ix4-300d:hdd:blue"; | |
| 241 | + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; | |
| 242 | + default-state = "off"; | |
| 243 | + }; | |
| 244 | + | |
| 245 | + power-led { | |
| 246 | + label = "ix4-300d:power:white"; | |
| 247 | + gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>; | |
| 248 | + /* init blinking while booting */ | |
| 249 | + linux,default-trigger = "timer"; | |
| 250 | + default-state = "on"; | |
| 251 | + }; | |
| 252 | + | |
| 253 | + sysfail-led { | |
| 254 | + label = "ix4-300d:sysfail:red"; | |
| 255 | + gpios = <&gpio_spi 2 GPIO_ACTIVE_HIGH>; | |
| 256 | + default-state = "off"; | |
| 257 | + }; | |
| 258 | + | |
| 259 | + sys-led { | |
| 260 | + label = "ix4-300d:sys:blue"; | |
| 261 | + gpios = <&gpio_spi 3 GPIO_ACTIVE_HIGH>; | |
| 262 | + default-state = "off"; | |
| 263 | + }; | |
| 264 | + | |
| 265 | + hddfail-led { | |
| 266 | + label = "ix4-300d:hddfail:red"; | |
| 267 | + gpios = <&gpio_spi 4 GPIO_ACTIVE_HIGH>; | |
| 268 | + default-state = "off"; | |
| 269 | + }; | |
| 270 | + | |
| 271 | + }; | |
| 272 | + | |
| 273 | + /* | |
| 274 | + * Warning: you need both eth1 & 0 PHY initialized (i.e having | |
| 275 | + * them up does the tweak) for poweroff to shutdown otherwise it | |
| 276 | + * reboots | |
| 277 | + */ | |
| 278 | + gpio-poweroff { | |
| 279 | + compatible = "gpio-poweroff"; | |
| 280 | + pinctrl-0 = <&poweroff_pin>; | |
| 281 | + pinctrl-names = "default"; | |
| 282 | + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; | |
| 283 | + }; | |
| 284 | +}; | |
| @@ -34,6 +34,7 @@ · 33 unmodified lines | ||
| 34 | 34 | compatible = "marvell,sheeva-v7"; |
| 35 | 35 | reg = <0>; |
| 36 | 36 | clocks = <&cpuclk 0>; |
| 37 | + clock-latency = <1000000>; | |
| 37 | 38 | }; |
| 38 | 39 | |
| 39 | 40 | cpu@1 { |
| @@ -41,6 +42,7 @@ · 1 unmodified line | ||
| 41 | 42 | compatible = "marvell,sheeva-v7"; |
| 42 | 43 | reg = <1>; |
| 43 | 44 | clocks = <&cpuclk 1>; |
| 45 | + clock-latency = <1000000>; | |
| 44 | 46 | }; |
| 45 | 47 | }; |
| 46 | 48 | |
| @@ -36,6 +36,7 @@ · 35 unmodified lines | ||
| 36 | 36 | compatible = "marvell,sheeva-v7"; |
| 37 | 37 | reg = <0>; |
| 38 | 38 | clocks = <&cpuclk 0>; |
| 39 | + clock-latency = <1000000>; | |
| 39 | 40 | }; |
| 40 | 41 | |
| 41 | 42 | cpu@1 { |
| @@ -43,6 +44,7 @@ · 1 unmodified line | ||
| 43 | 44 | compatible = "marvell,sheeva-v7"; |
| 44 | 45 | reg = <1>; |
| 45 | 46 | clocks = <&cpuclk 1>; |
| 47 | + clock-latency = <1000000>; | |
| 46 | 48 | }; |
| 47 | 49 | }; |
| 48 | 50 | |
| @@ -37,6 +37,7 @@ · 36 unmodified lines | ||
| 37 | 37 | compatible = "marvell,sheeva-v7"; |
| 38 | 38 | reg = <0>; |
| 39 | 39 | clocks = <&cpuclk 0>; |
| 40 | + clock-latency = <1000000>; | |
| 40 | 41 | }; |
| 41 | 42 | |
| 42 | 43 | cpu@1 { |
| @@ -44,6 +45,7 @@ · 1 unmodified line | ||
| 44 | 45 | compatible = "marvell,sheeva-v7"; |
| 45 | 46 | reg = <1>; |
| 46 | 47 | clocks = <&cpuclk 1>; |
| 48 | + clock-latency = <1000000>; | |
| 47 | 49 | }; |
| 48 | 50 | |
| 49 | 51 | cpu@2 { |
| @@ -51,6 +53,7 @@ · 1 unmodified line | ||
| 51 | 53 | compatible = "marvell,sheeva-v7"; |
| 52 | 54 | reg = <2>; |
| 53 | 55 | clocks = <&cpuclk 2>; |
| 56 | + clock-latency = <1000000>; | |
| 54 | 57 | }; |
| 55 | 58 | |
| 56 | 59 | cpu@3 { |
| @@ -58,6 +61,7 @@ · 1 unmodified line | ||
| 58 | 61 | compatible = "marvell,sheeva-v7"; |
| 59 | 62 | reg = <3>; |
| 60 | 63 | clocks = <&cpuclk 3>; |
| 64 | + clock-latency = <1000000>; | |
| 61 | 65 | }; |
| 62 | 66 | }; |
| 63 | 67 | |
| @@ -99,7 +99,7 @@ · 98 unmodified lines | ||
| 99 | 99 | cpuclk: clock-complex@18700 { |
| 100 | 100 | #clock-cells = <1>; |
| 101 | 101 | compatible = "marvell,armada-xp-cpu-clock"; |
| 102 | − reg = <0x18700 0xA0>; | |
| 102 | + reg = <0x18700 0xA0>, <0x1c054 0x10>; | |
| 103 | 103 | clocks = <&coreclk 1>; |
| 104 | 104 | }; |
| 105 | 105 | |
| @@ -42,6 +42,14 @@ · 41 unmodified lines | ||
| 42 | 42 | compatible = "atmel,osc", "fixed-clock"; |
| 43 | 43 | clock-frequency = <12000000>; |
| 44 | 44 | }; |
| 45 | + | |
| 46 | + slow_xtal { | |
| 47 | + clock-frequency = <32768>; | |
| 48 | + }; | |
| 49 | + | |
| 50 | + main_xtal { | |
| 51 | + clock-frequency = <12000000>; | |
| 52 | + }; | |
| 45 | 53 | }; |
| 46 | 54 | |
| 47 | 55 | ahb { |
| @@ -34,6 +34,14 @@ · 33 unmodified lines | ||
| 34 | 34 | compatible = "atmel,osc", "fixed-clock"; |
| 35 | 35 | clock-frequency = <12000000>; |
| 36 | 36 | }; |
| 37 | + | |
| 38 | + slow_xtal { | |
| 39 | + clock-frequency = <32768>; | |
| 40 | + }; | |
| 41 | + | |
| 42 | + main_xtal { | |
| 43 | + clock-frequency = <12000000>; | |
| 44 | + }; | |
| 37 | 45 | }; |
| 38 | 46 | |
| 39 | 47 | ahb { |
| @@ -31,6 +31,14 @@ · 30 unmodified lines | ||
| 31 | 31 | compatible = "atmel,osc", "fixed-clock"; |
| 32 | 32 | clock-frequency = <18432000>; |
| 33 | 33 | }; |
| 34 | + | |
| 35 | + slow_xtal { | |
| 36 | + clock-frequency = <32768>; | |
| 37 | + }; | |
| 38 | + | |
| 39 | + main_xtal { | |
| 40 | + clock-frequency = <18432000>; | |
| 41 | + }; | |
| 34 | 42 | }; |
| 35 | 43 | |
| 36 | 44 | ahb { |
| @@ -28,6 +28,14 @@ · 27 unmodified lines | ||
| 28 | 28 | compatible = "atmel,osc", "fixed-clock"; |
| 29 | 29 | clock-frequency = <12000000>; |
| 30 | 30 | }; |
| 31 | + | |
| 32 | + slow_xtal { | |
| 33 | + clock-frequency = <32768>; | |
| 34 | + }; | |
| 35 | + | |
| 36 | + main_xtal { | |
| 37 | + clock-frequency = <12000000>; | |
| 38 | + }; | |
| 31 | 39 | }; |
| 32 | 40 | |
| 33 | 41 | ahb { |
| @@ -21,12 +21,14 @@ · 20 unmodified lines | ||
| 21 | 21 | reg = <0x20000000 0x10000000>; |
| 22 | 22 | }; |
| 23 | 23 | |
| 24 | − slow_xtal { | |
| 25 | − clock-frequency = <32768>; | |
| 26 | − }; | |
| 24 | + clocks { | |
| 25 | + slow_xtal { | |
| 26 | + clock-frequency = <32768>; | |
| 27 | + }; | |
| 27 | 28 | |
| 28 | − main_xtal { | |
| 29 | − clock-frequency = <12000000>; | |
| 29 | + main_xtal { | |
| 30 | + clock-frequency = <12000000>; | |
| 31 | + }; | |
| 30 | 32 | }; |
| 31 | 33 | |
| 32 | 34 | ahb { |
| @@ -14,6 +14,7 @@ · 13 unmodified lines | ||
| 14 | 14 | #include <dt-bindings/pinctrl/at91.h> |
| 15 | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | 16 | #include <dt-bindings/gpio/gpio.h> |
| 17 | +#include <dt-bindings/clock/at91.h> | |
| 17 | 18 | |
| 18 | 19 | / { |
| 19 | 20 | model = "Atmel AT91RM9200 family SoC"; |
| @@ -51,6 +52,20 @@ · 31 unmodified lines | ||
| 51 | 52 | reg = <0x20000000 0x04000000>; |
| 52 | 53 | }; |
| 53 | 54 | |
| 55 | + clocks { | |
| 56 | + slow_xtal: slow_xtal { | |
| 57 | + compatible = "fixed-clock"; | |
| 58 | + #clock-cells = <0>; | |
| 59 | + clock-frequency = <0>; | |
| 60 | + }; | |
| 61 | + | |
| 62 | + main_xtal: main_xtal { | |
| 63 | + compatible = "fixed-clock"; | |
| 64 | + #clock-cells = <0>; | |
| 65 | + clock-frequency = <0>; | |
| 66 | + }; | |
| 67 | + }; | |
| 68 | + | |
| 54 | 69 | ahb { |
| 55 | 70 | compatible = "simple-bus"; |
| 56 | 71 | #address-cells = <1>; |
| @@ -79,6 +94,260 @@ · 22 unmodified lines | ||
| 79 | 94 | pmc: pmc@fffffc00 { |
| 80 | 95 | compatible = "atmel,at91rm9200-pmc"; |
| 81 | 96 | reg = <0xfffffc00 0x100>; |
| 97 | + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
| 98 | + interrupt-controller; | |
| 99 | + #address-cells = <1>; | |
| 100 | + #size-cells = <0>; | |
| 101 | + #interrupt-cells = <1>; | |
| 102 | + | |
| 103 | + main_osc: main_osc { | |
| 104 | + compatible = "atmel,at91rm9200-clk-main-osc"; | |
| 105 | + #clock-cells = <0>; | |
| 106 | + interrupts-extended = <&pmc AT91_PMC_MOSCS>; | |
| 107 | + clocks = <&main_xtal>; | |
| 108 | + }; | |
| 109 | + | |
| 110 | + main: mainck { | |
| 111 | + compatible = "atmel,at91rm9200-clk-main"; | |
| 112 | + #clock-cells = <0>; | |
| 113 | + clocks = <&main_osc>; | |
| 114 | + }; | |
| 115 | + | |
| 116 | + plla: pllack { | |
| 117 | + compatible = "atmel,at91rm9200-clk-pll"; | |
| 118 | + #clock-cells = <0>; | |
| 119 | + interrupts-extended = <&pmc AT91_PMC_LOCKA>; | |
| 120 | + clocks = <&main>; | |
| 121 | + reg = <0>; | |
| 122 | + atmel,clk-input-range = <1000000 32000000>; | |
| 123 | + #atmel,pll-clk-output-range-cells = <3>; | |
| 124 | + atmel,pll-clk-output-ranges = <80000000 160000000 0>, | |
| 125 | + <150000000 180000000 2>; | |
| 126 | + }; | |
| 127 | + | |
| 128 | + pllb: pllbck { | |
| 129 | + compatible = "atmel,at91rm9200-clk-pll"; | |
| 130 | + #clock-cells = <0>; | |
| 131 | + interrupts-extended = <&pmc AT91_PMC_LOCKB>; | |
| 132 | + clocks = <&main>; | |
| 133 | + reg = <1>; | |
| 134 | + atmel,clk-input-range = <1000000 32000000>; | |
| 135 | + #atmel,pll-clk-output-range-cells = <3>; | |
| 136 | + atmel,pll-clk-output-ranges = <80000000 160000000 0>, | |
| 137 | + <150000000 180000000 2>; | |
| 138 | + }; | |
| 139 | + | |
| 140 | + mck: masterck { | |
| 141 | + compatible = "atmel,at91rm9200-clk-master"; | |
| 142 | + #clock-cells = <0>; | |
| 143 | + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; | |
| 144 | + clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; | |
| 145 | + atmel,clk-output-range = <0 80000000>; | |
| 146 | + atmel,clk-divisors = <1 2 3 4>; | |
| 147 | + }; | |
| 148 | + | |
| 149 | + usb: usbck { | |
| 150 | + compatible = "atmel,at91rm9200-clk-usb"; | |
| 151 | + #clock-cells = <0>; | |
| 152 | + atmel,clk-divisors = <1 2>; | |
| 153 | + clocks = <&pllb>; | |
| 154 | + }; | |
| 155 | + | |
| 156 | + prog: progck { | |
| 157 | + compatible = "atmel,at91rm9200-clk-programmable"; | |
| 158 | + #address-cells = <1>; | |
| 159 | + #size-cells = <0>; | |
| 160 | + interrupt-parent = <&pmc>; | |
| 161 | + clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; | |
| 162 | + | |
| 163 | + prog0: prog0 { | |
| 164 | + #clock-cells = <0>; | |
| 165 | + reg = <0>; | |
| 166 | + interrupts = <AT91_PMC_PCKRDY(0)>; | |
| 167 | + }; | |
| 168 | + | |
| 169 | + prog1: prog1 { | |
| 170 | + #clock-cells = <0>; | |
| 171 | + reg = <1>; | |
| 172 | + interrupts = <AT91_PMC_PCKRDY(1)>; | |
| 173 | + }; | |
| 174 | + | |
| 175 | + prog2: prog2 { | |
| 176 | + #clock-cells = <0>; | |
| 177 | + reg = <2>; | |
| 178 | + interrupts = <AT91_PMC_PCKRDY(2)>; | |
| 179 | + }; | |
| 180 | + | |
| 181 | + prog3: prog3 { | |
| 182 | + #clock-cells = <0>; | |
| 183 | + reg = <3>; | |
| 184 | + interrupts = <AT91_PMC_PCKRDY(3)>; | |
| 185 | + }; | |
| 186 | + }; | |
| 187 | + | |
| 188 | + systemck { | |
| 189 | + compatible = "atmel,at91rm9200-clk-system"; | |
| 190 | + #address-cells = <1>; | |
| 191 | + #size-cells = <0>; | |
| 192 | + | |
| 193 | + udpck: udpck { | |
| 194 | + #clock-cells = <0>; | |
| 195 | + reg = <2>; | |
| 196 | + clocks = <&usb>; | |
| 197 | + }; | |
| 198 | + | |
| 199 | + uhpck: uhpck { | |
| 200 | + #clock-cells = <0>; | |
| 201 | + reg = <4>; | |
| 202 | + clocks = <&usb>; | |
| 203 | + }; | |
| 204 | + | |
| 205 | + pck0: pck0 { | |
| 206 | + #clock-cells = <0>; | |
| 207 | + reg = <8>; | |
| 208 | + clocks = <&prog0>; | |
| 209 | + }; | |
| 210 | + | |
| 211 | + pck1: pck1 { | |
| 212 | + #clock-cells = <0>; | |
| 213 | + reg = <9>; | |
| 214 | + clocks = <&prog1>; | |
| 215 | + }; | |
| 216 | + | |
| 217 | + pck2: pck2 { | |
| 218 | + #clock-cells = <0>; | |
| 219 | + reg = <10>; | |
| 220 | + clocks = <&prog2>; | |
| 221 | + }; | |
| 222 | + | |
| 223 | + pck3: pck3 { | |
| 224 | + #clock-cells = <0>; | |
| 225 | + reg = <11>; | |
| 226 | + clocks = <&prog3>; | |
| 227 | + }; | |
| 228 | + }; | |
| 229 | + | |
| 230 | + periphck { | |
| 231 | + compatible = "atmel,at91rm9200-clk-peripheral"; | |
| 232 | + #address-cells = <1>; | |
| 233 | + #size-cells = <0>; | |
| 234 | + clocks = <&mck>; | |
| 235 | + | |
| 236 | + pioA_clk: pioA_clk { | |
| 237 | + #clock-cells = <0>; | |
| 238 | + reg = <2>; | |
| 239 | + }; | |
| 240 | + | |
| 241 | + pioB_clk: pioB_clk { | |
| 242 | + #clock-cells = <0>; | |
| 243 | + reg = <3>; | |
| 244 | + }; | |
| 245 | + | |
| 246 | + pioC_clk: pioC_clk { | |
| 247 | + #clock-cells = <0>; | |
| 248 | + reg = <4>; | |
| 249 | + }; | |
| 250 | + | |
| 251 | + pioD_clk: pioD_clk { | |
| 252 | + #clock-cells = <0>; | |
| 253 | + reg = <5>; | |
| 254 | + }; | |
| 255 | + | |
| 256 | + usart0_clk: usart0_clk { | |
| 257 | + #clock-cells = <0>; | |
| 258 | + reg = <6>; | |
| 259 | + }; | |
| 260 | + | |
| 261 | + usart1_clk: usart1_clk { | |
| 262 | + #clock-cells = <0>; | |
| 263 | + reg = <7>; | |
| 264 | + }; | |
| 265 | + | |
| 266 | + usart2_clk: usart2_clk { | |
| 267 | + #clock-cells = <0>; | |
| 268 | + reg = <8>; | |
| 269 | + }; | |
| 270 | + | |
| 271 | + usart3_clk: usart3_clk { | |
| 272 | + #clock-cells = <0>; | |
| 273 | + reg = <9>; | |
| 274 | + }; | |
| 275 | + | |
| 276 | + mci0_clk: mci0_clk { | |
| 277 | + #clock-cells = <0>; | |
| 278 | + reg = <10>; | |
| 279 | + }; | |
| 280 | + | |
| 281 | + udc_clk: udc_clk { | |
| 282 | + #clock-cells = <0>; | |
| 283 | + reg = <11>; | |
| 284 | + }; | |
| 285 | + | |
| 286 | + twi0_clk: twi0_clk { | |
| 287 | + reg = <12>; | |
| 288 | + #clock-cells = <0>; | |
| 289 | + }; | |
| 290 | + | |
| 291 | + spi0_clk: spi0_clk { | |
| 292 | + #clock-cells = <0>; | |
| 293 | + reg = <13>; | |
| 294 | + }; | |
| 295 | + | |
| 296 | + ssc0_clk: ssc0_clk { | |
| 297 | + #clock-cells = <0>; | |
| 298 | + reg = <14>; | |
| 299 | + }; | |
| 300 | + | |
| 301 | + ssc1_clk: ssc1_clk { | |
| 302 | + #clock-cells = <0>; | |
| 303 | + reg = <15>; | |
| 304 | + }; | |
| 305 | + | |
| 306 | + ssc2_clk: ssc2_clk { | |
| 307 | + #clock-cells = <0>; | |
| 308 | + reg = <16>; | |
| 309 | + }; | |
| 310 | + | |
| 311 | + tc0_clk: tc0_clk { | |
| 312 | + #clock-cells = <0>; | |
| 313 | + reg = <17>; | |
| 314 | + }; | |
| 315 | + | |
| 316 | + tc1_clk: tc1_clk { | |
| 317 | + #clock-cells = <0>; | |
| 318 | + reg = <18>; | |
| 319 | + }; | |
| 320 | + | |
| 321 | + tc2_clk: tc2_clk { | |
| 322 | + #clock-cells = <0>; | |
| 323 | + reg = <19>; | |
| 324 | + }; | |
| 325 | + | |
| 326 | + tc3_clk: tc3_clk { | |
| 327 | + #clock-cells = <0>; | |
| 328 | + reg = <20>; | |
| 329 | + }; | |
| 330 | + | |
| 331 | + tc4_clk: tc4_clk { | |
| 332 | + #clock-cells = <0>; | |
| 333 | + reg = <21>; | |
| 334 | + }; | |
| 335 | + | |
| 336 | + tc5_clk: tc5_clk { | |
| 337 | + #clock-cells = <0>; | |
| 338 | + reg = <22>; | |
| 339 | + }; | |
| 340 | + | |
| 341 | + ohci_clk: ohci_clk { | |
| 342 | + #clock-cells = <0>; | |
| 343 | + reg = <23>; | |
| 344 | + }; | |
| 345 | + | |
| 346 | + macb0_clk: macb0_clk { | |
| 347 | + #clock-cells = <0>; | |
| 348 | + reg = <24>; | |
| 349 | + }; | |
| 350 | + }; | |
| 82 | 351 | }; |
| 83 | 352 | |
| 84 | 353 | st: timer@fffffd00 { |
| @@ -93,6 +362,8 @@ · 8 unmodified lines | ||
| 93 | 362 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 |
| 94 | 363 | 18 IRQ_TYPE_LEVEL_HIGH 0 |
| 95 | 364 | 19 IRQ_TYPE_LEVEL_HIGH 0>; |
| 365 | + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; | |
| 366 | + clock-names = "t0_clk", "t1_clk", "t2_clk"; | |
| 96 | 367 | }; |
| 97 | 368 | |
| 98 | 369 | tcb1: timer@fffa4000 { |
| @@ -101,6 +372,8 @@ · 2 unmodified lines | ||
| 101 | 372 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 |
| 102 | 373 | 21 IRQ_TYPE_LEVEL_HIGH 0 |
| 103 | 374 | 22 IRQ_TYPE_LEVEL_HIGH 0>; |
| 375 | + clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>; | |
| 376 | + clock-names = "t0_clk", "t1_clk", "t2_clk"; | |
| 104 | 377 | }; |
| 105 | 378 | |
| 106 | 379 | i2c0: i2c@fffb8000 { |
| @@ -109,6 +382,7 @@ · 2 unmodified lines | ||
| 109 | 382 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; |
| 110 | 383 | pinctrl-names = "default"; |
| 111 | 384 | pinctrl-0 = <&pinctrl_twi>; |
| 385 | + clocks = <&twi0_clk>; | |
| 112 | 386 | #address-cells = <1>; |
| 113 | 387 | #size-cells = <0>; |
| 114 | 388 | status = "disabled"; |
| @@ -118,6 +392,8 @@ · 3 unmodified lines | ||
| 118 | 392 | compatible = "atmel,hsmci"; |
| 119 | 393 | reg = <0xfffb4000 0x4000>; |
| 120 | 394 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; |
| 395 | + clocks = <&mci0_clk>; | |
| 396 | + clock-names = "mci_clk"; | |
| 121 | 397 | #address-cells = <1>; |
| 122 | 398 | #size-cells = <0>; |
| 123 | 399 | pinctrl-names = "default"; |
| @@ -130,6 +406,8 @@ · 6 unmodified lines | ||
| 130 | 406 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; |
| 131 | 407 | pinctrl-names = "default"; |
| 132 | 408 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 409 | + clocks = <&ssc0_clk>; | |
| 410 | + clock-names = "pclk"; | |
| 133 | 411 | status = "disable"; |
| 134 | 412 | }; |
| 135 | 413 | |
| @@ -139,6 +417,8 @@ · 3 unmodified lines | ||
| 139 | 417 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; |
| 140 | 418 | pinctrl-names = "default"; |
| 141 | 419 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
| 420 | + clocks = <&ssc1_clk>; | |
| 421 | + clock-names = "pclk"; | |
| 142 | 422 | status = "disable"; |
| 143 | 423 | }; |
| 144 | 424 | |
| @@ -148,6 +428,8 @@ · 3 unmodified lines | ||
| 148 | 428 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
| 149 | 429 | pinctrl-names = "default"; |
| 150 | 430 | pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; |
| 431 | + clocks = <&ssc2_clk>; | |
| 432 | + clock-names = "pclk"; | |
| 151 | 433 | status = "disable"; |
| 152 | 434 | }; |
| 153 | 435 | |
| @@ -158,6 +440,8 @@ · 4 unmodified lines | ||
| 158 | 440 | phy-mode = "rmii"; |
| 159 | 441 | pinctrl-names = "default"; |
| 160 | 442 | pinctrl-0 = <&pinctrl_macb_rmii>; |
| 443 | + clocks = <&macb0_clk>; | |
| 444 | + clock-names = "ether_clk"; | |
| 161 | 445 | status = "disabled"; |
| 162 | 446 | }; |
| 163 | 447 | |
| @@ -496,6 +780,7 @@ · 332 unmodified lines | ||
| 496 | 780 | gpio-controller; |
| 497 | 781 | interrupt-controller; |
| 498 | 782 | #interrupt-cells = <2>; |
| 783 | + clocks = <&pioA_clk>; | |
| 499 | 784 | }; |
| 500 | 785 | |
| 501 | 786 | pioB: gpio@fffff600 { |
| @@ -506,6 +791,7 @@ · 4 unmodified lines | ||
| 506 | 791 | gpio-controller; |
| 507 | 792 | interrupt-controller; |
| 508 | 793 | #interrupt-cells = <2>; |
| 794 | + clocks = <&pioB_clk>; | |
| 509 | 795 | }; |
| 510 | 796 | |
| 511 | 797 | pioC: gpio@fffff800 { |
| @@ -516,6 +802,7 @@ · 4 unmodified lines | ||
| 516 | 802 | gpio-controller; |
| 517 | 803 | interrupt-controller; |
| 518 | 804 | #interrupt-cells = <2>; |
| 805 | + clocks = <&pioC_clk>; | |
| 519 | 806 | }; |
| 520 | 807 | |
| 521 | 808 | pioD: gpio@fffffa00 { |
| @@ -526,6 +813,7 @@ · 4 unmodified lines | ||
| 526 | 813 | gpio-controller; |
| 527 | 814 | interrupt-controller; |
| 528 | 815 | #interrupt-cells = <2>; |
| 816 | + clocks = <&pioD_clk>; | |
| 529 | 817 | }; |
| 530 | 818 | }; |
| 531 | 819 | |
| @@ -535,6 +823,8 @@ · 3 unmodified lines | ||
| 535 | 823 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 536 | 824 | pinctrl-names = "default"; |
| 537 | 825 | pinctrl-0 = <&pinctrl_dbgu>; |
| 826 | + clocks = <&mck>; | |
| 827 | + clock-names = "usart"; | |
| 538 | 828 | status = "disabled"; |
| 539 | 829 | }; |
| 540 | 830 | |
| @@ -546,6 +836,8 @@ · 5 unmodified lines | ||
| 546 | 836 | atmel,use-dma-tx; |
| 547 | 837 | pinctrl-names = "default"; |
| 548 | 838 | pinctrl-0 = <&pinctrl_uart0>; |
| 839 | + clocks = <&usart0_clk>; | |
| 840 | + clock-names = "usart"; | |
| 549 | 841 | status = "disabled"; |
| 550 | 842 | }; |
| 551 | 843 | |
| @@ -557,6 +849,8 @@ · 5 unmodified lines | ||
| 557 | 849 | atmel,use-dma-tx; |
| 558 | 850 | pinctrl-names = "default"; |
| 559 | 851 | pinctrl-0 = <&pinctrl_uart1>; |
| 852 | + clocks = <&usart1_clk>; | |
| 853 | + clock-names = "usart"; | |
| 560 | 854 | status = "disabled"; |
| 561 | 855 | }; |
| 562 | 856 | |
| @@ -568,6 +862,8 @@ · 5 unmodified lines | ||
| 568 | 862 | atmel,use-dma-tx; |
| 569 | 863 | pinctrl-names = "default"; |
| 570 | 864 | pinctrl-0 = <&pinctrl_uart2>; |
| 865 | + clocks = <&usart2_clk>; | |
| 866 | + clock-names = "usart"; | |
| 571 | 867 | status = "disabled"; |
| 572 | 868 | }; |
| 573 | 869 | |
| @@ -579,6 +875,8 @@ · 5 unmodified lines | ||
| 579 | 875 | atmel,use-dma-tx; |
| 580 | 876 | pinctrl-names = "default"; |
| 581 | 877 | pinctrl-0 = <&pinctrl_uart3>; |
| 878 | + clocks = <&usart3_clk>; | |
| 879 | + clock-names = "usart"; | |
| 582 | 880 | status = "disabled"; |
| 583 | 881 | }; |
| 584 | 882 | |
| @@ -586,6 +884,8 @@ · 1 unmodified line | ||
| 586 | 884 | compatible = "atmel,at91rm9200-udc"; |
| 587 | 885 | reg = <0xfffb0000 0x4000>; |
| 588 | 886 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; |
| 887 | + clocks = <&udc_clk>, <&udpck>; | |
| 888 | + clock-names = "pclk", "hclk"; | |
| 589 | 889 | status = "disabled"; |
| 590 | 890 | }; |
| 591 | 891 | |
| @@ -597,6 +897,8 @@ · 5 unmodified lines | ||
| 597 | 897 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; |
| 598 | 898 | pinctrl-names = "default"; |
| 599 | 899 | pinctrl-0 = <&pinctrl_spi0>; |
| 900 | + clocks = <&spi0_clk>; | |
| 901 | + clock-names = "spi_clk"; | |
| 600 | 902 | status = "disabled"; |
| 601 | 903 | }; |
| 602 | 904 | }; |
| @@ -622,6 +924,8 @@ · 19 unmodified lines | ||
| 622 | 924 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 623 | 925 | reg = <0x00300000 0x100000>; |
| 624 | 926 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; |
| 927 | + clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>; | |
| 928 | + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | |
| 625 | 929 | status = "disabled"; |
| 626 | 930 | }; |
| 627 | 931 | }; |
| @@ -25,6 +25,14 @@ · 24 unmodified lines | ||
| 25 | 25 | compatible = "atmel,osc", "fixed-clock"; |
| 26 | 26 | clock-frequency = <18432000>; |
| 27 | 27 | }; |
| 28 | + | |
| 29 | + slow_xtal { | |
| 30 | + clock-frequency = <32768>; | |
| 31 | + }; | |
| 32 | + | |
| 33 | + main_xtal { | |
| 34 | + clock-frequency = <18432000>; | |
| 35 | + }; | |
| 28 | 36 | }; |
| 29 | 37 | |
| 30 | 38 | ahb { |
| @@ -12,6 +12,7 @@ · 11 unmodified lines | ||
| 12 | 12 | #include <dt-bindings/pinctrl/at91.h> |
| 13 | 13 | #include <dt-bindings/interrupt-controller/irq.h> |
| 14 | 14 | #include <dt-bindings/gpio/gpio.h> |
| 15 | +#include <dt-bindings/clock/at91.h> | |
| 15 | 16 | |
| 16 | 17 | / { |
| 17 | 18 | model = "Atmel AT91SAM9260 family SoC"; |
| @@ -48,6 +49,26 @@ · 30 unmodified lines | ||
| 48 | 49 | reg = <0x20000000 0x04000000>; |
| 49 | 50 | }; |
| 50 | 51 | |
| 52 | + clocks { | |
| 53 | + slow_xtal: slow_xtal { | |
| 54 | + compatible = "fixed-clock"; | |
| 55 | + #clock-cells = <0>; | |
| 56 | + clock-frequency = <0>; | |
| 57 | + }; | |
| 58 | + | |
| 59 | + main_xtal: main_xtal { | |
| 60 | + compatible = "fixed-clock"; | |
| 61 | + #clock-cells = <0>; | |
| 62 | + clock-frequency = <0>; | |
| 63 | + }; | |
| 64 | + | |
| 65 | + adc_op_clk: adc_op_clk{ | |
| 66 | + compatible = "fixed-clock"; | |
| 67 | + #clock-cells = <0>; | |
| 68 | + clock-frequency = <5000000>; | |
| 69 | + }; | |
| 70 | + }; | |
| 71 | + | |
| 51 | 72 | ahb { |
| 52 | 73 | compatible = "simple-bus"; |
| 53 | 74 | #address-cells = <1>; |
| @@ -74,8 +95,260 @@ · 20 unmodified lines | ||
| 74 | 95 | }; |
| 75 | 96 | |
| 76 | 97 | pmc: pmc@fffffc00 { |
| 77 | − compatible = "atmel,at91rm9200-pmc"; | |
| 98 | + compatible = "atmel,at91sam9260-pmc"; | |
| 78 | 99 | reg = <0xfffffc00 0x100>; |
| 100 | + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
| 101 | + interrupt-controller; | |
| 102 | + #address-cells = <1>; | |
| 103 | + #size-cells = <0>; | |
| 104 | + #interrupt-cells = <1>; | |
| 105 | + | |
| 106 | + main_osc: main_osc { | |
| 107 | + compatible = "atmel,at91rm9200-clk-main-osc"; | |
| 108 | + #clock-cells = <0>; | |
| 109 | + interrupts-extended = <&pmc AT91_PMC_MOSCS>; | |
| 110 | + clocks = <&main_xtal>; | |
| 111 | + }; | |
| 112 | + | |
| 113 | + main: mainck { | |
| 114 | + compatible = "atmel,at91rm9200-clk-main"; | |
| 115 | + #clock-cells = <0>; | |
| 116 | + clocks = <&main_osc>; | |
| 117 | + }; | |
| 118 | + | |
| 119 | + slow_rc_osc: slow_rc_osc { | |
| 120 | + compatible = "fixed-clock"; | |
| 121 | + #clock-cells = <0>; | |
| 122 | + clock-frequency = <32768>; | |
| 123 | + clock-accuracy = <50000000>; | |
| 124 | + }; | |
| 125 | + | |
| 126 | + clk32k: slck { | |
| 127 | + compatible = "atmel,at91sam9260-clk-slow"; | |
| 128 | + #clock-cells = <0>; | |
| 129 | + clocks = <&slow_rc_osc>, <&slow_xtal>; | |
| 130 | + }; | |
| 131 | + | |
| 132 | + plla: pllack { | |
| 133 | + compatible = "atmel,at91rm9200-clk-pll"; | |
| 134 | + #clock-cells = <0>; | |
| 135 | + interrupts-extended = <&pmc AT91_PMC_LOCKA>; | |
| 136 | + clocks = <&main>; | |
| 137 | + reg = <0>; | |
| 138 | + atmel,clk-input-range = <1000000 32000000>; | |
| 139 | + #atmel,pll-clk-output-range-cells = <4>; | |
| 140 | + atmel,pll-clk-output-ranges = <80000000 160000000 0 1>, | |
| 141 | + <150000000 240000000 2 1>; | |
| 142 | + }; | |
| 143 | + | |
| 144 | + pllb: pllbck { | |
| 145 | + compatible = "atmel,at91rm9200-clk-pll"; | |
| 146 | + #clock-cells = <0>; | |
| 147 | + interrupts-extended = <&pmc AT91_PMC_LOCKB>; | |
| 148 | + clocks = <&main>; | |
| 149 | + reg = <1>; | |
| 150 | + atmel,clk-input-range = <1000000 5000000>; | |
| 151 | + #atmel,pll-clk-output-range-cells = <4>; | |
| 152 | + atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; | |
| 153 | + }; | |
| 154 | + | |
| 155 | + mck: masterck { | |
| 156 | + compatible = "atmel,at91rm9200-clk-master"; | |
| 157 | + #clock-cells = <0>; | |
| 158 | + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; | |
| 159 | + clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; | |
| 160 | + atmel,clk-output-range = <0 105000000>; | |
| 161 | + atmel,clk-divisors = <1 2 4 0>; | |
| 162 | + }; | |
| 163 | + | |
| 164 | + usb: usbck { | |
| 165 | + compatible = "atmel,at91rm9200-clk-usb"; | |
| 166 | + #clock-cells = <0>; | |
| 167 | + atmel,clk-divisors = <1 2 4 0>; | |
| 168 | + clocks = <&pllb>; | |
| 169 | + }; | |
| 170 | + | |
| 171 | + prog: progck { | |
| 172 | + compatible = "atmel,at91rm9200-clk-programmable"; | |
| 173 | + #address-cells = <1>; | |
| 174 | + #size-cells = <0>; | |
| 175 | + interrupt-parent = <&pmc>; | |
| 176 | + clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; | |
| 177 | + | |
| 178 | + prog0: prog0 { | |
| 179 | + #clock-cells = <0>; | |
| 180 | + reg = <0>; | |
| 181 | + interrupts = <AT91_PMC_PCKRDY(0)>; | |
| 182 | + }; | |
| 183 | + | |
| 184 | + prog1: prog1 { | |
| 185 | + #clock-cells = <0>; | |
| 186 | + reg = <1>; | |
| 187 | + interrupts = <AT91_PMC_PCKRDY(1)>; | |
| 188 | + }; | |
| 189 | + }; | |
| 190 | + | |
| 191 | + systemck { | |
| 192 | + compatible = "atmel,at91rm9200-clk-system"; | |
| 193 | + #address-cells = <1>; | |
| 194 | + #size-cells = <0>; | |
| 195 | + | |
| 196 | + uhpck: uhpck { | |
| 197 | + #clock-cells = <0>; | |
| 198 | + reg = <6>; | |
| 199 | + clocks = <&usb>; | |
| 200 | + }; | |
| 201 | + | |
| 202 | + udpck: udpck { | |
| 203 | + #clock-cells = <0>; | |
| 204 | + reg = <7>; | |
| 205 | + clocks = <&usb>; | |
| 206 | + }; | |
| 207 | + | |
| 208 | + pck0: pck0 { | |
| 209 | + #clock-cells = <0>; | |
| 210 | + reg = <8>; | |
| 211 | + clocks = <&prog0>; | |
| 212 | + }; | |
| 213 | + | |
| 214 | + pck1: pck1 { | |
| 215 | + #clock-cells = <0>; | |
| 216 | + reg = <9>; | |
| 217 | + clocks = <&prog1>; | |
| 218 | + }; | |
| 219 | + }; | |
| 220 | + | |
| 221 | + periphck { | |
| 222 | + compatible = "atmel,at91rm9200-clk-peripheral"; | |
| 223 | + #address-cells = <1>; | |
| 224 | + #size-cells = <0>; | |
| 225 | + clocks = <&mck>; | |
| 226 | + | |
| 227 | + pioA_clk: pioA_clk { | |
| 228 | + #clock-cells = <0>; | |
| 229 | + reg = <2>; | |
| 230 | + }; | |
| 231 | + | |
| 232 | + pioB_clk: pioB_clk { | |
| 233 | + #clock-cells = <0>; | |
| 234 | + reg = <3>; | |
| 235 | + }; | |
| 236 | + | |
| 237 | + pioC_clk: pioC_clk { | |
| 238 | + #clock-cells = <0>; | |
| 239 | + reg = <4>; | |
| 240 | + }; | |
| 241 | + | |
| 242 | + adc_clk: adc_clk { | |
| 243 | + #clock-cells = <0>; | |
| 244 | + reg = <5>; | |
| 245 | + }; | |
| 246 | + | |
| 247 | + usart0_clk: usart0_clk { | |
| 248 | + #clock-cells = <0>; | |
| 249 | + reg = <6>; | |
| 250 | + }; | |
| 251 | + | |
| 252 | + usart1_clk: usart1_clk { | |
| 253 | + #clock-cells = <0>; | |
| 254 | + reg = <7>; | |
| 255 | + }; | |
| 256 | + | |
| 257 | + usart2_clk: usart2_clk { | |
| 258 | + #clock-cells = <0>; | |
| 259 | + reg = <8>; | |
| 260 | + }; | |
| 261 | + | |
| 262 | + mci0_clk: mci0_clk { | |
| 263 | + #clock-cells = <0>; | |
| 264 | + reg = <9>; | |
| 265 | + }; | |
| 266 | + | |
| 267 | + udc_clk: udc_clk { | |
| 268 | + #clock-cells = <0>; | |
| 269 | + reg = <10>; | |
| 270 | + }; | |
| 271 | + | |
| 272 | + twi0_clk: twi0_clk { | |
| 273 | + reg = <11>; | |
| 274 | + #clock-cells = <0>; | |
| 275 | + }; | |
| 276 | + | |
| 277 | + spi0_clk: spi0_clk { | |
| 278 | + #clock-cells = <0>; | |
| 279 | + reg = <12>; | |
| 280 | + }; | |
| 281 | + | |
| 282 | + spi1_clk: spi1_clk { | |
| 283 | + #clock-cells = <0>; | |
| 284 | + reg = <13>; | |
| 285 | + }; | |
| 286 | + | |
| 287 | + ssc0_clk: ssc0_clk { | |
| 288 | + #clock-cells = <0>; | |
| 289 | + reg = <14>; | |
| 290 | + }; | |
| 291 | + | |
| 292 | + tc0_clk: tc0_clk { | |
| 293 | + #clock-cells = <0>; | |
| 294 | + reg = <17>; | |
| 295 | + }; | |
| 296 | + | |
| 297 | + tc1_clk: tc1_clk { | |
| 298 | + #clock-cells = <0>; | |
| 299 | + reg = <18>; | |
| 300 | + }; | |
| 301 | + | |
| 302 | + tc2_clk: tc2_clk { | |
| 303 | + #clock-cells = <0>; | |
| 304 | + reg = <19>; | |
| 305 | + }; | |
| 306 | + | |
| 307 | + ohci_clk: ohci_clk { | |
| 308 | + #clock-cells = <0>; | |
| 309 | + reg = <20>; | |
| 310 | + }; | |
| 311 | + | |
| 312 | + macb0_clk: macb0_clk { | |
| 313 | + #clock-cells = <0>; | |
| 314 | + reg = <21>; | |
| 315 | + }; | |
| 316 | + | |
| 317 | + isi_clk: isi_clk { | |
| 318 | + #clock-cells = <0>; | |
| 319 | + reg = <22>; | |
| 320 | + }; | |
| 321 | + | |
| 322 | + usart3_clk: usart3_clk { | |
| 323 | + #clock-cells = <0>; | |
| 324 | + reg = <23>; | |
| 325 | + }; | |
| 326 | + | |
| 327 | + uart0_clk: uart0_clk { | |
| 328 | + #clock-cells = <0>; | |
| 329 | + reg = <24>; | |
| 330 | + }; | |
| 331 | + | |
| 332 | + uart1_clk: uart1_clk { | |
| 333 | + #clock-cells = <0>; | |
| 334 | + reg = <25>; | |
| 335 | + }; | |
| 336 | + | |
| 337 | + tc3_clk: tc3_clk { | |
| 338 | + #clock-cells = <0>; | |
| 339 | + reg = <26>; | |
| 340 | + }; | |
| 341 | + | |
| 342 | + tc4_clk: tc4_clk { | |
| 343 | + #clock-cells = <0>; | |
| 344 | + reg = <27>; | |
| 345 | + }; | |
| 346 | + | |
| 347 | + tc5_clk: tc5_clk { | |
| 348 | + #clock-cells = <0>; | |
| 349 | + reg = <28>; | |
| 350 | + }; | |
| 351 | + }; | |
| 79 | 352 | }; |
| 80 | 353 | |
| 81 | 354 | rstc@fffffd00 { |
| @@ -92,6 +365,7 @@ · 10 unmodified lines | ||
| 92 | 365 | compatible = "atmel,at91sam9260-pit"; |
| 93 | 366 | reg = <0xfffffd30 0xf>; |
| 94 | 367 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 368 | + clocks = <&mck>; | |
| 95 | 369 | }; |
| 96 | 370 | |
| 97 | 371 | tcb0: timer@fffa0000 { |
| @@ -100,6 +374,8 @@ · 2 unmodified lines | ||
| 100 | 374 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 |
| 101 | 375 | 18 IRQ_TYPE_LEVEL_HIGH 0 |
| 102 | 376 | 19 IRQ_TYPE_LEVEL_HIGH 0>; |
| 377 | + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; | |
| 378 | + clock-names = "t0_clk", "t1_clk", "t2_clk"; | |
| 103 | 379 | }; |
| 104 | 380 | |
| 105 | 381 | tcb1: timer@fffdc000 { |
| @@ -108,6 +384,8 @@ · 2 unmodified lines | ||
| 108 | 384 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 |
| 109 | 385 | 27 IRQ_TYPE_LEVEL_HIGH 0 |
| 110 | 386 | 28 IRQ_TYPE_LEVEL_HIGH 0>; |
| 387 | + clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>; | |
| 388 | + clock-names = "t0_clk", "t1_clk", "t2_clk"; | |
| 111 | 389 | }; |
| 112 | 390 | |
| 113 | 391 | pinctrl@fffff400 { |
| @@ -443,6 +721,7 @@ · 329 unmodified lines | ||
| 443 | 721 | gpio-controller; |
| 444 | 722 | interrupt-controller; |
| 445 | 723 | #interrupt-cells = <2>; |
| 724 | + clocks = <&pioA_clk>; | |
| 446 | 725 | }; |
| 447 | 726 | |
| 448 | 727 | pioB: gpio@fffff600 { |
| @@ -453,6 +732,7 @@ · 4 unmodified lines | ||
| 453 | 732 | gpio-controller; |
| 454 | 733 | interrupt-controller; |
| 455 | 734 | #interrupt-cells = <2>; |
| 735 | + clocks = <&pioB_clk>; | |
| 456 | 736 | }; |
| 457 | 737 | |
| 458 | 738 | pioC: gpio@fffff800 { |
| @@ -463,6 +743,7 @@ · 4 unmodified lines | ||
| 463 | 743 | gpio-controller; |
| 464 | 744 | interrupt-controller; |
| 465 | 745 | #interrupt-cells = <2>; |
| 746 | + clocks = <&pioC_clk>; | |
| 466 | 747 | }; |
| 467 | 748 | }; |
| 468 | 749 | |
| @@ -472,6 +753,8 @@ · 3 unmodified lines | ||
| 472 | 753 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 473 | 754 | pinctrl-names = "default"; |
| 474 | 755 | pinctrl-0 = <&pinctrl_dbgu>; |
| 756 | + clocks = <&mck>; | |
| 757 | + clock-names = "usart"; | |
| 475 | 758 | status = "disabled"; |
| 476 | 759 | }; |
| 477 | 760 | |
| @@ -483,6 +766,8 @@ · 5 unmodified lines | ||
| 483 | 766 | atmel,use-dma-tx; |
| 484 | 767 | pinctrl-names = "default"; |
| 485 | 768 | pinctrl-0 = <&pinctrl_usart0>; |
| 769 | + clocks = <&usart0_clk>; | |
| 770 | + clock-names = "usart"; | |
| 486 | 771 | status = "disabled"; |
| 487 | 772 | }; |
| 488 | 773 | |
| @@ -494,6 +779,8 @@ · 5 unmodified lines | ||
| 494 | 779 | atmel,use-dma-tx; |
| 495 | 780 | pinctrl-names = "default"; |
| 496 | 781 | pinctrl-0 = <&pinctrl_usart1>; |
| 782 | + clocks = <&usart1_clk>; | |
| 783 | + clock-names = "usart"; | |
| 497 | 784 | status = "disabled"; |
| 498 | 785 | }; |
| 499 | 786 | |
| @@ -505,6 +792,8 @@ · 5 unmodified lines | ||
| 505 | 792 | atmel,use-dma-tx; |
| 506 | 793 | pinctrl-names = "default"; |
| 507 | 794 | pinctrl-0 = <&pinctrl_usart2>; |
| 795 | + clocks = <&usart2_clk>; | |
| 796 | + clock-names = "usart"; | |
| 508 | 797 | status = "disabled"; |
| 509 | 798 | }; |
| 510 | 799 | |
| @@ -516,6 +805,8 @@ · 5 unmodified lines | ||
| 516 | 805 | atmel,use-dma-tx; |
| 517 | 806 | pinctrl-names = "default"; |
| 518 | 807 | pinctrl-0 = <&pinctrl_usart3>; |
| 808 | + clocks = <&usart3_clk>; | |
| 809 | + clock-names = "usart"; | |
| 519 | 810 | status = "disabled"; |
| 520 | 811 | }; |
| 521 | 812 | |
| @@ -527,6 +818,8 @@ · 5 unmodified lines | ||
| 527 | 818 | atmel,use-dma-tx; |
| 528 | 819 | pinctrl-names = "default"; |
| 529 | 820 | pinctrl-0 = <&pinctrl_uart0>; |
| 821 | + clocks = <&uart0_clk>; | |
| 822 | + clock-names = "usart"; | |
| 530 | 823 | status = "disabled"; |
| 531 | 824 | }; |
| 532 | 825 | |
| @@ -538,6 +831,8 @@ · 5 unmodified lines | ||
| 538 | 831 | atmel,use-dma-tx; |
| 539 | 832 | pinctrl-names = "default"; |
| 540 | 833 | pinctrl-0 = <&pinctrl_uart1>; |
| 834 | + clocks = <&uart1_clk>; | |
| 835 | + clock-names = "usart"; | |
| 541 | 836 | status = "disabled"; |
| 542 | 837 | }; |
| 543 | 838 | |
| @@ -547,6 +842,8 @@ · 3 unmodified lines | ||
| 547 | 842 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; |
| 548 | 843 | pinctrl-names = "default"; |
| 549 | 844 | pinctrl-0 = <&pinctrl_macb_rmii>; |
| 845 | + clocks = <&macb0_clk>, <&macb0_clk>; | |
| 846 | + clock-names = "hclk", "pclk"; | |
| 550 | 847 | status = "disabled"; |
| 551 | 848 | }; |
| 552 | 849 | |
| @@ -554,6 +851,8 @@ · 1 unmodified line | ||
| 554 | 851 | compatible = "atmel,at91rm9200-udc"; |
| 555 | 852 | reg = <0xfffa4000 0x4000>; |
| 556 | 853 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; |
| 854 | + clocks = <&udc_clk>, <&udpck>; | |
| 855 | + clock-names = "pclk", "hclk"; | |
| 557 | 856 | status = "disabled"; |
| 558 | 857 | }; |
| 559 | 858 | |
| @@ -563,6 +862,7 @@ · 3 unmodified lines | ||
| 563 | 862 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; |
| 564 | 863 | #address-cells = <1>; |
| 565 | 864 | #size-cells = <0>; |
| 865 | + clocks = <&twi0_clk>; | |
| 566 | 866 | status = "disabled"; |
| 567 | 867 | }; |
| 568 | 868 | |
| @@ -573,6 +873,8 @@ · 4 unmodified lines | ||
| 573 | 873 | #address-cells = <1>; |
| 574 | 874 | #size-cells = <0>; |
| 575 | 875 | pinctrl-names = "default"; |
| 876 | + clocks = <&mci0_clk>; | |
| 877 | + clock-names = "mci_clk"; | |
| 576 | 878 | status = "disabled"; |
| 577 | 879 | }; |
| 578 | 880 | |
| @@ -582,6 +884,8 @@ · 3 unmodified lines | ||
| 582 | 884 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; |
| 583 | 885 | pinctrl-names = "default"; |
| 584 | 886 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 887 | + clocks = <&ssc0_clk>; | |
| 888 | + clock-names = "pclk"; | |
| 585 | 889 | status = "disabled"; |
| 586 | 890 | }; |
| 587 | 891 | |
| @@ -593,6 +897,8 @@ · 5 unmodified lines | ||
| 593 | 897 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; |
| 594 | 898 | pinctrl-names = "default"; |
| 595 | 899 | pinctrl-0 = <&pinctrl_spi0>; |
| 900 | + clocks = <&spi0_clk>; | |
| 901 | + clock-names = "spi_clk"; | |
| 596 | 902 | status = "disabled"; |
| 597 | 903 | }; |
| 598 | 904 | |
| @@ -604,6 +910,8 @@ · 5 unmodified lines | ||
| 604 | 910 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; |
| 605 | 911 | pinctrl-names = "default"; |
| 606 | 912 | pinctrl-0 = <&pinctrl_spi1>; |
| 913 | + clocks = <&spi1_clk>; | |
| 914 | + clock-names = "spi_clk"; | |
| 607 | 915 | status = "disabled"; |
| 608 | 916 | }; |
| 609 | 917 | |
| @@ -613,6 +921,8 @@ · 3 unmodified lines | ||
| 613 | 921 | compatible = "atmel,at91sam9260-adc"; |
| 614 | 922 | reg = <0xfffe0000 0x100>; |
| 615 | 923 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; |
| 924 | + clocks = <&adc_clk>, <&adc_op_clk>; | |
| 925 | + clock-names = "adc_clk", "adc_op_clk"; | |
| 616 | 926 | atmel,adc-use-external-triggers; |
| 617 | 927 | atmel,adc-channels-used = <0xf>; |
| 618 | 928 | atmel,adc-vref = <3300>; |
| @@ -680,6 +990,8 @@ · 61 unmodified lines | ||
| 680 | 990 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 681 | 991 | reg = <0x00500000 0x100000>; |
| 682 | 992 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; |
| 993 | + clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>; | |
| 994 | + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | |
| 683 | 995 | status = "disabled"; |
| 684 | 996 | }; |
| 685 | 997 | }; |
| @@ -46,16 +46,18 @@ · 45 unmodified lines | ||
| 46 | 46 | reg = <0x20000000 0x08000000>; |
| 47 | 47 | }; |
| 48 | 48 | |
| 49 | − main_xtal: main_xtal { | |
| 50 | − compatible = "fixed-clock"; | |
| 51 | − #clock-cells = <0>; | |
| 52 | − clock-frequency = <0>; | |
| 53 | − }; | |
| 49 | + clocks { | |
| 50 | + main_xtal: main_xtal { | |
| 51 | + compatible = "fixed-clock"; | |
| 52 | + #clock-cells = <0>; | |
| 53 | + clock-frequency = <0>; | |
| 54 | + }; | |
| 54 | 55 | |
| 55 | − slow_xtal: slow_xtal { | |
| 56 | − compatible = "fixed-clock"; | |
| 57 | − #clock-cells = <0>; | |
| 58 | − clock-frequency = <0>; | |
| 56 | + slow_xtal: slow_xtal { | |
| 57 | + compatible = "fixed-clock"; | |
| 58 | + #clock-cells = <0>; | |
| 59 | + clock-frequency = <0>; | |
| 60 | + }; | |
| 59 | 61 | }; |
| 60 | 62 | |
| 61 | 63 | ahb { |
| @@ -20,14 +20,6 @@ · 19 unmodified lines | ||
| 20 | 20 | reg = <0x20000000 0x4000000>; |
| 21 | 21 | }; |
| 22 | 22 | |
| 23 | − slow_xtal { | |
| 24 | − clock-frequency = <32768>; | |
| 25 | − }; | |
| 26 | − | |
| 27 | − main_xtal { | |
| 28 | − clock-frequency = <18432000>; | |
| 29 | − }; | |
| 30 | − | |
| 31 | 23 | clocks { |
| 32 | 24 | #address-cells = <1>; |
| 33 | 25 | #size-cells = <1>; |
| @@ -37,6 +29,14 @@ · 3 unmodified lines | ||
| 37 | 29 | compatible = "atmel,osc", "fixed-clock"; |
| 38 | 30 | clock-frequency = <18432000>; |
| 39 | 31 | }; |
| 32 | + | |
| 33 | + slow_xtal { | |
| 34 | + clock-frequency = <32768>; | |
| 35 | + }; | |
| 36 | + | |
| 37 | + main_xtal { | |
| 38 | + clock-frequency = <18432000>; | |
| 39 | + }; | |
| 40 | 40 | }; |
| 41 | 41 | |
| 42 | 42 | ahb { |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | ||
| 10 | 10 | #include <dt-bindings/pinctrl/at91.h> |
| 11 | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
| 12 | 12 | #include <dt-bindings/gpio/gpio.h> |
| 13 | +#include <dt-bindings/clock/at91.h> | |
| 13 | 14 | |
| 14 | 15 | / { |
| 15 | 16 | model = "Atmel AT91SAM9263 family SoC"; |
| @@ -32,6 +33,7 @@ · 16 unmodified lines | ||
| 32 | 33 | ssc1 = &ssc1; |
| 33 | 34 | pwm0 = &pwm0; |
| 34 | 35 | }; |
| 36 | + | |
| 35 | 37 | cpus { |
| 36 | 38 | #address-cells = <0>; |
| 37 | 39 | #size-cells = <0>; |
| @@ -46,6 +48,20 @@ · 8 unmodified lines | ||
| 46 | 48 | reg = <0x20000000 0x08000000>; |
| 47 | 49 | }; |
| 48 | 50 | |
| 51 | + clocks { | |
| 52 | + main_xtal: main_xtal { | |
| 53 | + compatible = "fixed-clock"; | |
| 54 | + #clock-cells = <0>; | |
| 55 | + clock-frequency = <0>; | |
| 56 | + }; | |
| 57 | + | |
| 58 | + slow_xtal: slow_xtal { | |
| 59 | + compatible = "fixed-clock"; | |
| 60 | + #clock-cells = <0>; | |
| 61 | + clock-frequency = <0>; | |
| 62 | + }; | |
| 63 | + }; | |
| 64 | + | |
| 49 | 65 | ahb { |
| 50 | 66 | compatible = "simple-bus"; |
| 51 | 67 | #address-cells = <1>; |
| @@ -69,6 +85,264 @@ · 17 unmodified lines | ||
| 69 | 85 | pmc: pmc@fffffc00 { |
| 70 | 86 | compatible = "atmel,at91rm9200-pmc"; |
| 71 | 87 | reg = <0xfffffc00 0x100>; |
| 88 | + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
| 89 | + interrupt-controller; | |
| 90 | + #address-cells = <1>; | |
| 91 | + #size-cells = <0>; | |
| 92 | + #interrupt-cells = <1>; | |
| 93 | + | |
| 94 | + main_osc: main_osc { | |
| 95 | + compatible = "atmel,at91rm9200-clk-main-osc"; | |
| 96 | + #clock-cells = <0>; | |
| 97 | + interrupts-extended = <&pmc AT91_PMC_MOSCS>; | |
| 98 | + clocks = <&main_xtal>; | |
| 99 | + }; | |
| 100 | + | |
| 101 | + main: mainck { | |
| 102 | + compatible = "atmel,at91rm9200-clk-main"; | |
| 103 | + #clock-cells = <0>; | |
| 104 | + clocks = <&main_osc>; | |
| 105 | + }; | |
| 106 | + | |
| 107 | + plla: pllack { | |
| 108 | + compatible = "atmel,at91rm9200-clk-pll"; | |
| 109 | + #clock-cells = <0>; | |
| 110 | + interrupts-extended = <&pmc AT91_PMC_LOCKA>; | |
| 111 | + clocks = <&main>; | |
| 112 | + reg = <0>; | |
| 113 | + atmel,clk-input-range = <1000000 32000000>; | |
| 114 | + #atmel,pll-clk-output-range-cells = <4>; | |
| 115 | + atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, | |
| 116 | + <190000000 240000000 2 1>; | |
| 117 | + }; | |
| 118 | + | |
| 119 | + pllb: pllbck { | |
| 120 | + compatible = "atmel,at91rm9200-clk-pll"; | |
| 121 | + #clock-cells = <0>; | |
| 122 | + interrupts-extended = <&pmc AT91_PMC_LOCKB>; | |
| 123 | + clocks = <&main>; | |
| 124 | + reg = <1>; | |
| 125 | + atmel,clk-input-range = <1000000 5000000>; | |
| 126 | + #atmel,pll-clk-output-range-cells = <4>; | |
| 127 | + atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; | |
| 128 | + }; | |
| 129 | + | |
| 130 | + mck: masterck { | |
| 131 | + compatible = "atmel,at91rm9200-clk-master"; | |
| 132 | + #clock-cells = <0>; | |
| 133 | + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; | |
| 134 | + clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; | |
| 135 | + atmel,clk-output-range = <0 120000000>; | |
| 136 | + atmel,clk-divisors = <1 2 4 0>; | |
| 137 | + }; | |
| 138 | + | |
| 139 | + usb: usbck { | |
| 140 | + compatible = "atmel,at91rm9200-clk-usb"; | |
| 141 | + #clock-cells = <0>; | |
| 142 | + atmel,clk-divisors = <1 2 4 0>; | |
| 143 | + clocks = <&pllb>; | |
| 144 | + }; | |
| 145 | + | |
| 146 | + prog: progck { | |
| 147 | + compatible = "atmel,at91rm9200-clk-programmable"; | |
| 148 | + #address-cells = <1>; | |
| 149 | + #size-cells = <0>; | |
| 150 | + interrupt-parent = <&pmc>; | |
| 151 | + clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; | |
| 152 | + | |
| 153 | + prog0: prog0 { | |
| 154 | + #clock-cells = <0>; | |
| 155 | + reg = <0>; | |
| 156 | + interrupts = <AT91_PMC_PCKRDY(0)>; | |
| 157 | + }; | |
| 158 | + | |
| 159 | + prog1: prog1 { | |
| 160 | + #clock-cells = <0>; | |
| 161 | + reg = <1>; | |
| 162 | + interrupts = <AT91_PMC_PCKRDY(1)>; | |
| 163 | + }; | |
| 164 | + | |
| 165 | + prog2: prog2 { | |
| 166 | + #clock-cells = <0>; | |
| 167 | + reg = <2>; | |
| 168 | + interrupts = <AT91_PMC_PCKRDY(2)>; | |
| 169 | + }; | |
| 170 | + | |
| 171 | + prog3: prog3 { | |
| 172 | + #clock-cells = <0>; | |
| 173 | + reg = <3>; | |
| 174 | + interrupts = <AT91_PMC_PCKRDY(3)>; | |
| 175 | + }; | |
| 176 | + }; | |
| 177 | + | |
| 178 | + systemck { | |
| 179 | + compatible = "atmel,at91rm9200-clk-system"; | |
| 180 | + #address-cells = <1>; | |
| 181 | + #size-cells = <0>; | |
| 182 | + | |
| 183 | + uhpck: uhpck { | |
| 184 | + #clock-cells = <0>; | |
| 185 | + reg = <6>; | |
| 186 | + clocks = <&usb>; | |
| 187 | + }; | |
| 188 | + | |
| 189 | + udpck: udpck { | |
| 190 | + #clock-cells = <0>; | |
| 191 | + reg = <7>; | |
| 192 | + clocks = <&usb>; | |
| 193 | + }; | |
| 194 | + | |
| 195 | + pck0: pck0 { | |
| 196 | + #clock-cells = <0>; | |
| 197 | + reg = <8>; | |
| 198 | + clocks = <&prog0>; | |
| 199 | + }; | |
| 200 | + | |
| 201 | + pck1: pck1 { | |
| 202 | + #clock-cells = <0>; | |
| 203 | + reg = <9>; | |
| 204 | + clocks = <&prog1>; | |
| 205 | + }; | |
| 206 | + | |
| 207 | + pck2: pck2 { | |
| 208 | + #clock-cells = <0>; | |
| 209 | + reg = <10>; | |
| 210 | + clocks = <&prog2>; | |
| 211 | + }; | |
| 212 | + | |
| 213 | + pck3: pck3 { | |
| 214 | + #clock-cells = <0>; | |
| 215 | + reg = <11>; | |
| 216 | + clocks = <&prog3>; | |
| 217 | + }; | |
| 218 | + }; | |
| 219 | + | |
| 220 | + periphck { | |
| 221 | + compatible = "atmel,at91rm9200-clk-peripheral"; | |
| 222 | + #address-cells = <1>; | |
| 223 | + #size-cells = <0>; | |
| 224 | + clocks = <&mck>; | |
| 225 | + | |
| 226 | + pioA_clk: pioA_clk { | |
| 227 | + #clock-cells = <0>; | |
| 228 | + reg = <2>; | |
| 229 | + }; | |
| 230 | + | |
| 231 | + pioB_clk: pioB_clk { | |
| 232 | + #clock-cells = <0>; | |
| 233 | + reg = <3>; | |
| 234 | + }; | |
| 235 | + | |
| 236 | + pioCDE_clk: pioCDE_clk { | |
| 237 | + #clock-cells = <0>; | |
| 238 | + reg = <4>; | |
| 239 | + }; | |
| 240 | + | |
| 241 | + usart0_clk: usart0_clk { | |
| 242 | + #clock-cells = <0>; | |
| 243 | + reg = <7>; | |
| 244 | + }; | |
| 245 | + | |
| 246 | + usart1_clk: usart1_clk { | |
| 247 | + #clock-cells = <0>; | |
| 248 | + reg = <8>; | |
| 249 | + }; | |
| 250 | + | |
| 251 | + usart2_clk: usart2_clk { | |
| 252 | + #clock-cells = <0>; | |
| 253 | + reg = <9>; | |
| 254 | + }; | |
| 255 | + | |
| 256 | + mci0_clk: mci0_clk { | |
| 257 | + #clock-cells = <0>; | |
| 258 | + reg = <10>; | |
| 259 | + }; | |
| 260 | + | |
| 261 | + mci1_clk: mci1_clk { | |
| 262 | + #clock-cells = <0>; | |
| 263 | + reg = <11>; | |
| 264 | + }; | |
| 265 | + | |
| 266 | + can_clk: can_clk { | |
| 267 | + #clock-cells = <0>; | |
| 268 | + reg = <12>; | |
| 269 | + }; | |
| 270 | + | |
| 271 | + twi0_clk: twi0_clk { | |
| 272 | + #clock-cells = <0>; | |
| 273 | + reg = <13>; | |
| 274 | + }; | |
| 275 | + | |
| 276 | + spi0_clk: spi0_clk { | |
| 277 | + #clock-cells = <0>; | |
| 278 | + reg = <14>; | |
| 279 | + }; | |
| 280 | + | |
| 281 | + spi1_clk: spi1_clk { | |
| 282 | + #clock-cells = <0>; | |
| 283 | + reg = <15>; | |
| 284 | + }; | |
| 285 | + | |
| 286 | + ssc0_clk: ssc0_clk { | |
| 287 | + #clock-cells = <0>; | |
| 288 | + reg = <16>; | |
| 289 | + }; | |
| 290 | + | |
| 291 | + ssc1_clk: ssc1_clk { | |
| 292 | + #clock-cells = <0>; | |
| 293 | + reg = <17>; | |
| 294 | + }; | |
| 295 | + | |
| 296 | + ac91_clk: ac97_clk { | |
| 297 | + #clock-cells = <0>; | |
| 298 | + reg = <18>; | |
| 299 | + }; | |
| 300 | + | |
| 301 | + tcb_clk: tcb_clk { | |
| 302 | + #clock-cells = <0>; | |
| 303 | + reg = <19>; | |
| 304 | + }; | |
| 305 | + | |
| 306 | + pwm_clk: pwm_clk { | |
| 307 | + #clock-cells = <0>; | |
| 308 | + reg = <20>; | |
| 309 | + }; | |
| 310 | + | |
| 311 | + macb0_clk: macb0_clk { | |
| 312 | + #clock-cells = <0>; | |
| 313 | + reg = <21>; | |
| 314 | + }; | |
| 315 | + | |
| 316 | + g2de_clk: g2de_clk { | |
| 317 | + #clock-cells = <0>; | |
| 318 | + reg = <23>; | |
| 319 | + }; | |
| 320 | + | |
| 321 | + udc_clk: udc_clk { | |
| 322 | + #clock-cells = <0>; | |
| 323 | + reg = <24>; | |
| 324 | + }; | |
| 325 | + | |
| 326 | + isi_clk: isi_clk { | |
| 327 | + #clock-cells = <0>; | |
| 328 | + reg = <25>; | |
| 329 | + }; | |
| 330 | + | |
| 331 | + lcd_clk: lcd_clk { | |
| 332 | + #clock-cells = <0>; | |
| 333 | + reg = <26>; | |
| 334 | + }; | |
| 335 | + | |
| 336 | + dma_clk: dma_clk { | |
| 337 | + #clock-cells = <0>; | |
| 338 | + reg = <27>; | |
| 339 | + }; | |
| 340 | + | |
| 341 | + ohci_clk: ohci_clk { | |
| 342 | + #clock-cells = <0>; | |
| 343 | + reg = <29>; | |
| 344 | + }; | |
| 345 | + }; | |
| 72 | 346 | }; |
| 73 | 347 | |
| 74 | 348 | ramc: ramc@ffffe200 { |
| @@ -81,12 +355,15 @@ · 6 unmodified lines | ||
| 81 | 355 | compatible = "atmel,at91sam9260-pit"; |
| 82 | 356 | reg = <0xfffffd30 0xf>; |
| 83 | 357 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 358 | + clocks = <&mck>; | |
| 84 | 359 | }; |
| 85 | 360 | |
| 86 | 361 | tcb0: timer@fff7c000 { |
| 87 | 362 | compatible = "atmel,at91rm9200-tcb"; |
| 88 | 363 | reg = <0xfff7c000 0x100>; |
| 89 | 364 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; |
| 365 | + clocks = <&tcb_clk>; | |
| 366 | + clock-names = "t0_clk"; | |
| 90 | 367 | }; |
| 91 | 368 | |
| 92 | 369 | rstc@fffffd00 { |
| @@ -403,6 +680,7 @@ · 310 unmodified lines | ||
| 403 | 680 | gpio-controller; |
| 404 | 681 | interrupt-controller; |
| 405 | 682 | #interrupt-cells = <2>; |
| 683 | + clocks = <&pioA_clk>; | |
| 406 | 684 | }; |
| 407 | 685 | |
| 408 | 686 | pioB: gpio@fffff400 { |
| @@ -413,6 +691,7 @@ · 4 unmodified lines | ||
| 413 | 691 | gpio-controller; |
| 414 | 692 | interrupt-controller; |
| 415 | 693 | #interrupt-cells = <2>; |
| 694 | + clocks = <&pioB_clk>; | |
| 416 | 695 | }; |
| 417 | 696 | |
| 418 | 697 | pioC: gpio@fffff600 { |
| @@ -423,6 +702,7 @@ · 4 unmodified lines | ||
| 423 | 702 | gpio-controller; |
| 424 | 703 | interrupt-controller; |
| 425 | 704 | #interrupt-cells = <2>; |
| 705 | + clocks = <&pioCDE_clk>; | |
| 426 | 706 | }; |
| 427 | 707 | |
| 428 | 708 | pioD: gpio@fffff800 { |
| @@ -433,6 +713,7 @@ · 4 unmodified lines | ||
| 433 | 713 | gpio-controller; |
| 434 | 714 | interrupt-controller; |
| 435 | 715 | #interrupt-cells = <2>; |
| 716 | + clocks = <&pioCDE_clk>; | |
| 436 | 717 | }; |
| 437 | 718 | |
| 438 | 719 | pioE: gpio@fffffa00 { |
| @@ -443,6 +724,7 @@ · 4 unmodified lines | ||
| 443 | 724 | gpio-controller; |
| 444 | 725 | interrupt-controller; |
| 445 | 726 | #interrupt-cells = <2>; |
| 727 | + clocks = <&pioCDE_clk>; | |
| 446 | 728 | }; |
| 447 | 729 | }; |
| 448 | 730 | |
| @@ -452,6 +734,8 @@ · 3 unmodified lines | ||
| 452 | 734 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 453 | 735 | pinctrl-names = "default"; |
| 454 | 736 | pinctrl-0 = <&pinctrl_dbgu>; |
| 737 | + clocks = <&mck>; | |
| 738 | + clock-names = "usart"; | |
| 455 | 739 | status = "disabled"; |
| 456 | 740 | }; |
| 457 | 741 | |
| @@ -463,6 +747,8 @@ · 5 unmodified lines | ||
| 463 | 747 | atmel,use-dma-tx; |
| 464 | 748 | pinctrl-names = "default"; |
| 465 | 749 | pinctrl-0 = <&pinctrl_usart0>; |
| 750 | + clocks = <&usart0_clk>; | |
| 751 | + clock-names = "usart"; | |
| 466 | 752 | status = "disabled"; |
| 467 | 753 | }; |
| 468 | 754 | |
| @@ -474,6 +760,8 @@ · 5 unmodified lines | ||
| 474 | 760 | atmel,use-dma-tx; |
| 475 | 761 | pinctrl-names = "default"; |
| 476 | 762 | pinctrl-0 = <&pinctrl_usart1>; |
| 763 | + clocks = <&usart1_clk>; | |
| 764 | + clock-names = "usart"; | |
| 477 | 765 | status = "disabled"; |
| 478 | 766 | }; |
| 479 | 767 | |
| @@ -485,6 +773,8 @@ · 5 unmodified lines | ||
| 485 | 773 | atmel,use-dma-tx; |
| 486 | 774 | pinctrl-names = "default"; |
| 487 | 775 | pinctrl-0 = <&pinctrl_usart2>; |
| 776 | + clocks = <&usart2_clk>; | |
| 777 | + clock-names = "usart"; | |
| 488 | 778 | status = "disabled"; |
| 489 | 779 | }; |
| 490 | 780 | |
| @@ -494,6 +784,8 @@ · 3 unmodified lines | ||
| 494 | 784 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
| 495 | 785 | pinctrl-names = "default"; |
| 496 | 786 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 787 | + clocks = <&ssc0_clk>; | |
| 788 | + clock-names = "pclk"; | |
| 497 | 789 | status = "disabled"; |
| 498 | 790 | }; |
| 499 | 791 | |
| @@ -503,6 +795,8 @@ · 3 unmodified lines | ||
| 503 | 795 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; |
| 504 | 796 | pinctrl-names = "default"; |
| 505 | 797 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
| 798 | + clocks = <&ssc1_clk>; | |
| 799 | + clock-names = "pclk"; | |
| 506 | 800 | status = "disabled"; |
| 507 | 801 | }; |
| 508 | 802 | |
| @@ -512,6 +806,8 @@ · 3 unmodified lines | ||
| 512 | 806 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; |
| 513 | 807 | pinctrl-names = "default"; |
| 514 | 808 | pinctrl-0 = <&pinctrl_macb_rmii>; |
| 809 | + clocks = <&macb0_clk>, <&macb0_clk>; | |
| 810 | + clock-names = "hclk", "pclk"; | |
| 515 | 811 | status = "disabled"; |
| 516 | 812 | }; |
| 517 | 813 | |
| @@ -519,6 +815,8 @@ · 1 unmodified line | ||
| 519 | 815 | compatible = "atmel,at91rm9200-udc"; |
| 520 | 816 | reg = <0xfff78000 0x4000>; |
| 521 | 817 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; |
| 818 | + clocks = <&udc_clk>, <&udpck>; | |
| 819 | + clock-names = "pclk", "hclk"; | |
| 522 | 820 | status = "disabled"; |
| 523 | 821 | }; |
| 524 | 822 | |
| @@ -528,6 +826,7 @@ · 3 unmodified lines | ||
| 528 | 826 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; |
| 529 | 827 | #address-cells = <1>; |
| 530 | 828 | #size-cells = <0>; |
| 829 | + clocks = <&twi0_clk>; | |
| 531 | 830 | status = "disabled"; |
| 532 | 831 | }; |
| 533 | 832 | |
| @@ -537,6 +836,8 @@ · 3 unmodified lines | ||
| 537 | 836 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; |
| 538 | 837 | #address-cells = <1>; |
| 539 | 838 | #size-cells = <0>; |
| 839 | + clocks = <&mci0_clk>; | |
| 840 | + clock-names = "mci_clk"; | |
| 540 | 841 | status = "disabled"; |
| 541 | 842 | }; |
| 542 | 843 | |
| @@ -546,6 +847,8 @@ · 3 unmodified lines | ||
| 546 | 847 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; |
| 547 | 848 | #address-cells = <1>; |
| 548 | 849 | #size-cells = <0>; |
| 850 | + clocks = <&mci1_clk>; | |
| 851 | + clock-names = "mci_clk"; | |
| 549 | 852 | status = "disabled"; |
| 550 | 853 | }; |
| 551 | 854 | |
| @@ -568,6 +871,8 @@ · 16 unmodified lines | ||
| 568 | 871 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; |
| 569 | 872 | pinctrl-names = "default"; |
| 570 | 873 | pinctrl-0 = <&pinctrl_spi0>; |
| 874 | + clocks = <&spi0_clk>; | |
| 875 | + clock-names = "spi_clk"; | |
| 571 | 876 | status = "disabled"; |
| 572 | 877 | }; |
| 573 | 878 | |
| @@ -579,6 +884,8 @@ · 5 unmodified lines | ||
| 579 | 884 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; |
| 580 | 885 | pinctrl-names = "default"; |
| 581 | 886 | pinctrl-0 = <&pinctrl_spi1>; |
| 887 | + clocks = <&spi1_clk>; | |
| 888 | + clock-names = "spi_clk"; | |
| 582 | 889 | status = "disabled"; |
| 583 | 890 | }; |
| 584 | 891 | |
| @@ -587,6 +894,8 @@ · 2 unmodified lines | ||
| 587 | 894 | reg = <0xfffb8000 0x300>; |
| 588 | 895 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; |
| 589 | 896 | #pwm-cells = <3>; |
| 897 | + clocks = <&pwm_clk>; | |
| 898 | + clock-names = "pwm_clk"; | |
| 590 | 899 | status = "disabled"; |
| 591 | 900 | }; |
| 592 | 901 | }; |
| @@ -622,6 +931,8 @@ · 29 unmodified lines | ||
| 622 | 931 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 623 | 932 | reg = <0x00a00000 0x100000>; |
| 624 | 933 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; |
| 934 | + clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>; | |
| 935 | + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | |
| 625 | 936 | status = "disabled"; |
| 626 | 937 | }; |
| 627 | 938 | }; |
| @@ -29,6 +29,14 @@ · 28 unmodified lines | ||
| 29 | 29 | compatible = "atmel,osc", "fixed-clock"; |
| 30 | 30 | clock-frequency = <16367660>; |
| 31 | 31 | }; |
| 32 | + | |
| 33 | + slow_xtal { | |
| 34 | + clock-frequency = <32768>; | |
| 35 | + }; | |
| 36 | + | |
| 37 | + main_xtal { | |
| 38 | + clock-frequency = <16367660>; | |
| 39 | + }; | |
| 32 | 40 | }; |
| 33 | 41 | |
| 34 | 42 | ahb { |
| @@ -25,6 +25,30 @@ · 24 unmodified lines | ||
| 25 | 25 | adc0: adc@fffe0000 { |
| 26 | 26 | atmel,adc-startup-time = <40>; |
| 27 | 27 | }; |
| 28 | + | |
| 29 | + pmc: pmc@fffffc00 { | |
| 30 | + plla: pllack { | |
| 31 | + atmel,clk-input-range = <2000000 32000000>; | |
| 32 | + atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, | |
| 33 | + <695000000 750000000 1 0>, | |
| 34 | + <645000000 700000000 2 0>, | |
| 35 | + <595000000 650000000 3 0>, | |
| 36 | + <545000000 600000000 0 1>, | |
| 37 | + <495000000 550000000 1 1>, | |
| 38 | + <445000000 500000000 2 1>, | |
| 39 | + <400000000 450000000 3 1>; | |
| 40 | + }; | |
| 41 | + | |
| 42 | + pllb: pllbck { | |
| 43 | + atmel,clk-input-range = <2000000 32000000>; | |
| 44 | + atmel,pll-clk-output-ranges = <30000000 100000000 0 0>; | |
| 45 | + }; | |
| 46 | + | |
| 47 | + mck: masterck { | |
| 48 | + atmel,clk-output-range = <0 133000000>; | |
| 49 | + atmel,clk-divisors = <1 2 4 6>; | |
| 50 | + }; | |
| 51 | + }; | |
| 28 | 52 | }; |
| 29 | 53 | }; |
| 30 | 54 | }; |
| @@ -26,6 +26,14 @@ · 25 unmodified lines | ||
| 26 | 26 | compatible = "atmel,osc", "fixed-clock"; |
| 27 | 27 | clock-frequency = <18432000>; |
| 28 | 28 | }; |
| 29 | + | |
| 30 | + slow_xtal { | |
| 31 | + clock-frequency = <32768>; | |
| 32 | + }; | |
| 33 | + | |
| 34 | + main_xtal { | |
| 35 | + clock-frequency = <18432000>; | |
| 36 | + }; | |
| 29 | 37 | }; |
| 30 | 38 | |
| 31 | 39 | ahb { |
| @@ -14,6 +14,7 @@ · 13 unmodified lines | ||
| 14 | 14 | #include <dt-bindings/pinctrl/at91.h> |
| 15 | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | 16 | #include <dt-bindings/gpio/gpio.h> |
| 17 | +#include <dt-bindings/clock/at91.h> | |
| 17 | 18 | |
| 18 | 19 | / { |
| 19 | 20 | model = "Atmel AT91SAM9G45 family SoC"; |
| @@ -53,6 +54,26 @@ · 33 unmodified lines | ||
| 53 | 54 | reg = <0x70000000 0x10000000>; |
| 54 | 55 | }; |
| 55 | 56 | |
| 57 | + clocks { | |
| 58 | + slow_xtal: slow_xtal { | |
| 59 | + compatible = "fixed-clock"; | |
| 60 | + #clock-cells = <0>; | |
| 61 | + clock-frequency = <0>; | |
| 62 | + }; | |
| 63 | + | |
| 64 | + main_xtal: main_xtal { | |
| 65 | + compatible = "fixed-clock"; | |
| 66 | + #clock-cells = <0>; | |
| 67 | + clock-frequency = <0>; | |
| 68 | + }; | |
| 69 | + | |
| 70 | + adc_op_clk: adc_op_clk{ | |
| 71 | + compatible = "fixed-clock"; | |
| 72 | + #clock-cells = <0>; | |
| 73 | + clock-frequency = <300000>; | |
| 74 | + }; | |
| 75 | + }; | |
| 76 | + | |
| 56 | 77 | ahb { |
| 57 | 78 | compatible = "simple-bus"; |
| 58 | 79 | #address-cells = <1>; |
| @@ -77,11 +98,279 @@ · 18 unmodified lines | ||
| 77 | 98 | compatible = "atmel,at91sam9g45-ddramc"; |
| 78 | 99 | reg = <0xffffe400 0x200 |
| 79 | 100 | 0xffffe600 0x200>; |
| 101 | + clocks = <&ddrck>; | |
| 102 | + clock-names = "ddrck"; | |
| 80 | 103 | }; |
| 81 | 104 | |
| 82 | 105 | pmc: pmc@fffffc00 { |
| 83 | − compatible = "atmel,at91rm9200-pmc"; | |
| 106 | + compatible = "atmel,at91sam9g45-pmc"; | |
| 84 | 107 | reg = <0xfffffc00 0x100>; |
| 108 | + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
| 109 | + interrupt-controller; | |
| 110 | + #address-cells = <1>; | |
| 111 | + #size-cells = <0>; | |
| 112 | + #interrupt-cells = <1>; | |
| 113 | + | |
| 114 | + main_osc: main_osc { | |
| 115 | + compatible = "atmel,at91rm9200-clk-main-osc"; | |
| 116 | + #clock-cells = <0>; | |
| 117 | + interrupts-extended = <&pmc AT91_PMC_MOSCS>; | |
| 118 | + clocks = <&main_xtal>; | |
| 119 | + }; | |
| 120 | + | |
| 121 | + main: mainck { | |
| 122 | + compatible = "atmel,at91rm9200-clk-main"; | |
| 123 | + #clock-cells = <0>; | |
| 124 | + clocks = <&main_osc>; | |
| 125 | + }; | |
| 126 | + | |
| 127 | + plla: pllack { | |
| 128 | + compatible = "atmel,at91rm9200-clk-pll"; | |
| 129 | + #clock-cells = <0>; | |
| 130 | + interrupts-extended = <&pmc AT91_PMC_LOCKA>; | |
| 131 | + clocks = <&main>; | |
| 132 | + reg = <0>; | |
| 133 | + atmel,clk-input-range = <2000000 32000000>; | |
| 134 | + #atmel,pll-clk-output-range-cells = <4>; | |
| 135 | + atmel,pll-clk-output-ranges = <745000000 800000000 0 0 | |
| 136 | + 695000000 750000000 1 0 | |
| 137 | + 645000000 700000000 2 0 | |
| 138 | + 595000000 650000000 3 0 | |
| 139 | + 545000000 600000000 0 1 | |
| 140 | + 495000000 555000000 1 1 | |
| 141 | + 445000000 500000000 2 1 | |
| 142 | + 400000000 450000000 3 1>; | |
| 143 | + }; | |
| 144 | + | |
| 145 | + plladiv: plladivck { | |
| 146 | + compatible = "atmel,at91sam9x5-clk-plldiv"; | |
| 147 | + #clock-cells = <0>; | |
| 148 | + clocks = <&plla>; | |
| 149 | + }; | |
| 150 | + | |
| 151 | + utmi: utmick { | |
| 152 | + compatible = "atmel,at91sam9x5-clk-utmi"; | |
| 153 | + #clock-cells = <0>; | |
| 154 | + interrupts-extended = <&pmc AT91_PMC_LOCKU>; | |
| 155 | + clocks = <&main>; | |
| 156 | + }; | |
| 157 | + | |
| 158 | + mck: masterck { | |
| 159 | + compatible = "atmel,at91rm9200-clk-master"; | |
| 160 | + #clock-cells = <0>; | |
| 161 | + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; | |
| 162 | + clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>; | |
| 163 | + atmel,clk-output-range = <0 133333333>; | |
| 164 | + atmel,clk-divisors = <1 2 4 3>; | |
| 165 | + }; | |
| 166 | + | |
| 167 | + usb: usbck { | |
| 168 | + compatible = "atmel,at91sam9x5-clk-usb"; | |
| 169 | + #clock-cells = <0>; | |
| 170 | + clocks = <&plladiv>, <&utmi>; | |
| 171 | + }; | |
| 172 | + | |
| 173 | + prog: progck { | |
| 174 | + compatible = "atmel,at91sam9g45-clk-programmable"; | |
| 175 | + #address-cells = <1>; | |
| 176 | + #size-cells = <0>; | |
| 177 | + interrupt-parent = <&pmc>; | |
| 178 | + clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>; | |
| 179 | + | |
| 180 | + prog0: prog0 { | |
| 181 | + #clock-cells = <0>; | |
| 182 | + reg = <0>; | |
| 183 | + interrupts = <AT91_PMC_PCKRDY(0)>; | |
| 184 | + }; | |
| 185 | + | |
| 186 | + prog1: prog1 { | |
| 187 | + #clock-cells = <0>; | |
| 188 | + reg = <1>; | |
| 189 | + interrupts = <AT91_PMC_PCKRDY(1)>; | |
| 190 | + }; | |
| 191 | + }; | |
| 192 | + | |
| 193 | + systemck { | |
| 194 | + compatible = "atmel,at91rm9200-clk-system"; | |
| 195 | + #address-cells = <1>; | |
| 196 | + #size-cells = <0>; | |
| 197 | + | |
| 198 | + ddrck: ddrck { | |
| 199 | + #clock-cells = <0>; | |
| 200 | + reg = <2>; | |
| 201 | + clocks = <&mck>; | |
| 202 | + }; | |
| 203 | + | |
| 204 | + uhpck: uhpck { | |
| 205 | + #clock-cells = <0>; | |
| 206 | + reg = <6>; | |
| 207 | + clocks = <&usb>; | |
| 208 | + }; | |
| 209 | + | |
| 210 | + pck0: pck0 { | |
| 211 | + #clock-cells = <0>; | |
| 212 | + reg = <8>; | |
| 213 | + clocks = <&prog0>; | |
| 214 | + }; | |
| 215 | + | |
| 216 | + pck1: pck1 { | |
| 217 | + #clock-cells = <0>; | |
| 218 | + reg = <9>; | |
| 219 | + clocks = <&prog1>; | |
| 220 | + }; | |
| 221 | + }; | |
| 222 | + | |
| 223 | + periphck { | |
| 224 | + compatible = "atmel,at91rm9200-clk-peripheral"; | |
| 225 | + #address-cells = <1>; | |
| 226 | + #size-cells = <0>; | |
| 227 | + clocks = <&mck>; | |
| 228 | + | |
| 229 | + pioA_clk: pioA_clk { | |
| 230 | + #clock-cells = <0>; | |
| 231 | + reg = <2>; | |
| 232 | + }; | |
| 233 | + | |
| 234 | + pioB_clk: pioB_clk { | |
| 235 | + #clock-cells = <0>; | |
| 236 | + reg = <3>; | |
| 237 | + }; | |
| 238 | + | |
| 239 | + pioC_clk: pioC_clk { | |
| 240 | + #clock-cells = <0>; | |
| 241 | + reg = <4>; | |
| 242 | + }; | |
| 243 | + | |
| 244 | + pioDE_clk: pioDE_clk { | |
| 245 | + #clock-cells = <0>; | |
| 246 | + reg = <5>; | |
| 247 | + }; | |
| 248 | + | |
| 249 | + trng_clk: trng_clk { | |
| 250 | + #clock-cells = <0>; | |
| 251 | + reg = <6>; | |
| 252 | + }; | |
| 253 | + | |
| 254 | + usart0_clk: usart0_clk { | |
| 255 | + #clock-cells = <0>; | |
| 256 | + reg = <7>; | |
| 257 | + }; | |
| 258 | + | |
| 259 | + usart1_clk: usart1_clk { | |
| 260 | + #clock-cells = <0>; | |
| 261 | + reg = <8>; | |
| 262 | + }; | |
| 263 | + | |
| 264 | + usart2_clk: usart2_clk { | |
| 265 | + #clock-cells = <0>; | |
| 266 | + reg = <9>; | |
| 267 | + }; | |
| 268 | + | |
| 269 | + usart3_clk: usart3_clk { | |
| 270 | + #clock-cells = <0>; | |
| 271 | + reg = <10>; | |
| 272 | + }; | |
| 273 | + | |
| 274 | + mci0_clk: mci0_clk { | |
| 275 | + #clock-cells = <0>; | |
| 276 | + reg = <11>; | |
| 277 | + }; | |
| 278 | + | |
| 279 | + twi0_clk: twi0_clk { | |
| 280 | + #clock-cells = <0>; | |
| 281 | + reg = <12>; | |
| 282 | + }; | |
| 283 | + | |
| 284 | + twi1_clk: twi1_clk { | |
| 285 | + #clock-cells = <0>; | |
| 286 | + reg = <13>; | |
| 287 | + }; | |
| 288 | + | |
| 289 | + spi0_clk: spi0_clk { | |
| 290 | + #clock-cells = <0>; | |
| 291 | + reg = <14>; | |
| 292 | + }; | |
| 293 | + | |
| 294 | + spi1_clk: spi1_clk { | |
| 295 | + #clock-cells = <0>; | |
| 296 | + reg = <15>; | |
| 297 | + }; | |
| 298 | + | |
| 299 | + ssc0_clk: ssc0_clk { | |
| 300 | + #clock-cells = <0>; | |
| 301 | + reg = <16>; | |
| 302 | + }; | |
| 303 | + | |
| 304 | + ssc1_clk: ssc1_clk { | |
| 305 | + #clock-cells = <0>; | |
| 306 | + reg = <17>; | |
| 307 | + }; | |
| 308 | + | |
| 309 | + tcb0_clk: tcb0_clk { | |
| 310 | + #clock-cells = <0>; | |
| 311 | + reg = <18>; | |
| 312 | + }; | |
| 313 | + | |
| 314 | + pwm_clk: pwm_clk { | |
| 315 | + #clock-cells = <0>; | |
| 316 | + reg = <19>; | |
| 317 | + }; | |
| 318 | + | |
| 319 | + adc_clk: adc_clk { | |
| 320 | + #clock-cells = <0>; | |
| 321 | + reg = <20>; | |
| 322 | + }; | |
| 323 | + | |
| 324 | + dma0_clk: dma0_clk { | |
| 325 | + #clock-cells = <0>; | |
| 326 | + reg = <21>; | |
| 327 | + }; | |
| 328 | + | |
| 329 | + uhphs_clk: uhphs_clk { | |
| 330 | + #clock-cells = <0>; | |
| 331 | + reg = <22>; | |
| 332 | + }; | |
| 333 | + | |
| 334 | + lcd_clk: lcd_clk { | |
| 335 | + #clock-cells = <0>; | |
| 336 | + reg = <23>; | |
| 337 | + }; | |
| 338 | + | |
| 339 | + ac97_clk: ac97_clk { | |
| 340 | + #clock-cells = <0>; | |
| 341 | + reg = <24>; | |
| 342 | + }; | |
| 343 | + | |
| 344 | + macb0_clk: macb0_clk { | |
| 345 | + #clock-cells = <0>; | |
| 346 | + reg = <25>; | |
| 347 | + }; | |
| 348 | + | |
| 349 | + isi_clk: isi_clk { | |
| 350 | + #clock-cells = <0>; | |
| 351 | + reg = <26>; | |
| 352 | + }; | |
| 353 | + | |
| 354 | + udphs_clk: udphs_clk { | |
| 355 | + #clock-cells = <0>; | |
| 356 | + reg = <27>; | |
| 357 | + }; | |
| 358 | + | |
| 359 | + aestdessha_clk: aestdessha_clk { | |
| 360 | + #clock-cells = <0>; | |
| 361 | + reg = <28>; | |
| 362 | + }; | |
| 363 | + | |
| 364 | + mci1_clk: mci1_clk { | |
| 365 | + #clock-cells = <0>; | |
| 366 | + reg = <29>; | |
| 367 | + }; | |
| 368 | + | |
| 369 | + vdec_clk: vdec_clk { | |
| 370 | + #clock-cells = <0>; | |
| 371 | + reg = <30>; | |
| 372 | + }; | |
| 373 | + }; | |
| 85 | 374 | }; |
| 86 | 375 | |
| 87 | 376 | rstc@fffffd00 { |
| @@ -93,6 +382,7 @@ · 5 unmodified lines | ||
| 93 | 382 | compatible = "atmel,at91sam9260-pit"; |
| 94 | 383 | reg = <0xfffffd30 0xf>; |
| 95 | 384 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 385 | + clocks = <&mck>; | |
| 96 | 386 | }; |
| 97 | 387 | |
| 98 | 388 | |
| @@ -105,12 +395,16 @@ · 6 unmodified lines | ||
| 105 | 395 | compatible = "atmel,at91rm9200-tcb"; |
| 106 | 396 | reg = <0xfff7c000 0x100>; |
| 107 | 397 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; |
| 398 | + clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>; | |
| 399 | + clock-names = "t0_clk", "t1_clk", "t2_clk"; | |
| 108 | 400 | }; |
| 109 | 401 | |
| 110 | 402 | tcb1: timer@fffd4000 { |
| 111 | 403 | compatible = "atmel,at91rm9200-tcb"; |
| 112 | 404 | reg = <0xfffd4000 0x100>; |
| 113 | 405 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; |
| 406 | + clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>; | |
| 407 | + clock-names = "t0_clk", "t1_clk", "t2_clk"; | |
| 114 | 408 | }; |
| 115 | 409 | |
| 116 | 410 | dma: dma-controller@ffffec00 { |
| @@ -118,6 +412,8 @@ · 1 unmodified line | ||
| 118 | 412 | reg = <0xffffec00 0x200>; |
| 119 | 413 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; |
| 120 | 414 | #dma-cells = <2>; |
| 415 | + clocks = <&dma0_clk>; | |
| 416 | + clock-names = "dma_clk"; | |
| 121 | 417 | }; |
| 122 | 418 | |
| 123 | 419 | pinctrl@fffff200 { |
| @@ -516,6 +812,7 @@ · 392 unmodified lines | ||
| 516 | 812 | gpio-controller; |
| 517 | 813 | interrupt-controller; |
| 518 | 814 | #interrupt-cells = <2>; |
| 815 | + clocks = <&pioA_clk>; | |
| 519 | 816 | }; |
| 520 | 817 | |
| 521 | 818 | pioB: gpio@fffff400 { |
| @@ -526,6 +823,7 @@ · 4 unmodified lines | ||
| 526 | 823 | gpio-controller; |
| 527 | 824 | interrupt-controller; |
| 528 | 825 | #interrupt-cells = <2>; |
| 826 | + clocks = <&pioB_clk>; | |
| 529 | 827 | }; |
| 530 | 828 | |
| 531 | 829 | pioC: gpio@fffff600 { |
| @@ -536,6 +834,7 @@ · 4 unmodified lines | ||
| 536 | 834 | gpio-controller; |
| 537 | 835 | interrupt-controller; |
| 538 | 836 | #interrupt-cells = <2>; |
| 837 | + clocks = <&pioC_clk>; | |
| 539 | 838 | }; |
| 540 | 839 | |
| 541 | 840 | pioD: gpio@fffff800 { |
| @@ -546,6 +845,7 @@ · 4 unmodified lines | ||
| 546 | 845 | gpio-controller; |
| 547 | 846 | interrupt-controller; |
| 548 | 847 | #interrupt-cells = <2>; |
| 848 | + clocks = <&pioDE_clk>; | |
| 549 | 849 | }; |
| 550 | 850 | |
| 551 | 851 | pioE: gpio@fffffa00 { |
| @@ -556,6 +856,7 @@ · 4 unmodified lines | ||
| 556 | 856 | gpio-controller; |
| 557 | 857 | interrupt-controller; |
| 558 | 858 | #interrupt-cells = <2>; |
| 859 | + clocks = <&pioDE_clk>; | |
| 559 | 860 | }; |
| 560 | 861 | }; |
| 561 | 862 | |
| @@ -565,6 +866,8 @@ · 3 unmodified lines | ||
| 565 | 866 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 566 | 867 | pinctrl-names = "default"; |
| 567 | 868 | pinctrl-0 = <&pinctrl_dbgu>; |
| 869 | + clocks = <&mck>; | |
| 870 | + clock-names = "usart"; | |
| 568 | 871 | status = "disabled"; |
| 569 | 872 | }; |
| 570 | 873 | |
| @@ -576,6 +879,8 @@ · 5 unmodified lines | ||
| 576 | 879 | atmel,use-dma-tx; |
| 577 | 880 | pinctrl-names = "default"; |
| 578 | 881 | pinctrl-0 = <&pinctrl_usart0>; |
| 882 | + clocks = <&usart0_clk>; | |
| 883 | + clock-names = "usart"; | |
| 579 | 884 | status = "disabled"; |
| 580 | 885 | }; |
| 581 | 886 | |
| @@ -587,6 +892,8 @@ · 5 unmodified lines | ||
| 587 | 892 | atmel,use-dma-tx; |
| 588 | 893 | pinctrl-names = "default"; |
| 589 | 894 | pinctrl-0 = <&pinctrl_usart1>; |
| 895 | + clocks = <&usart1_clk>; | |
| 896 | + clock-names = "usart"; | |
| 590 | 897 | status = "disabled"; |
| 591 | 898 | }; |
| 592 | 899 | |
| @@ -598,6 +905,8 @@ · 5 unmodified lines | ||
| 598 | 905 | atmel,use-dma-tx; |
| 599 | 906 | pinctrl-names = "default"; |
| 600 | 907 | pinctrl-0 = <&pinctrl_usart2>; |
| 908 | + clocks = <&usart2_clk>; | |
| 909 | + clock-names = "usart"; | |
| 601 | 910 | status = "disabled"; |
| 602 | 911 | }; |
| 603 | 912 | |
| @@ -609,6 +918,8 @@ · 5 unmodified lines | ||
| 609 | 918 | atmel,use-dma-tx; |
| 610 | 919 | pinctrl-names = "default"; |
| 611 | 920 | pinctrl-0 = <&pinctrl_usart3>; |
| 921 | + clocks = <&usart3_clk>; | |
| 922 | + clock-names = "usart"; | |
| 612 | 923 | status = "disabled"; |
| 613 | 924 | }; |
| 614 | 925 | |
| @@ -618,6 +929,8 @@ · 3 unmodified lines | ||
| 618 | 929 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; |
| 619 | 930 | pinctrl-names = "default"; |
| 620 | 931 | pinctrl-0 = <&pinctrl_macb_rmii>; |
| 932 | + clocks = <&macb0_clk>, <&macb0_clk>; | |
| 933 | + clock-names = "hclk", "pclk"; | |
| 621 | 934 | status = "disabled"; |
| 622 | 935 | }; |
| 623 | 936 | |
| @@ -629,6 +942,7 @@ · 5 unmodified lines | ||
| 629 | 942 | pinctrl-0 = <&pinctrl_i2c0>; |
| 630 | 943 | #address-cells = <1>; |
| 631 | 944 | #size-cells = <0>; |
| 945 | + clocks = <&twi0_clk>; | |
| 632 | 946 | status = "disabled"; |
| 633 | 947 | }; |
| 634 | 948 | |
| @@ -640,6 +954,7 @@ · 5 unmodified lines | ||
| 640 | 954 | pinctrl-0 = <&pinctrl_i2c1>; |
| 641 | 955 | #address-cells = <1>; |
| 642 | 956 | #size-cells = <0>; |
| 957 | + clocks = <&twi1_clk>; | |
| 643 | 958 | status = "disabled"; |
| 644 | 959 | }; |
| 645 | 960 | |
| @@ -649,6 +964,8 @@ · 3 unmodified lines | ||
| 649 | 964 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
| 650 | 965 | pinctrl-names = "default"; |
| 651 | 966 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 967 | + clocks = <&ssc0_clk>; | |
| 968 | + clock-names = "pclk"; | |
| 652 | 969 | status = "disabled"; |
| 653 | 970 | }; |
| 654 | 971 | |
| @@ -658,6 +975,8 @@ · 3 unmodified lines | ||
| 658 | 975 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; |
| 659 | 976 | pinctrl-names = "default"; |
| 660 | 977 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
| 978 | + clocks = <&ssc1_clk>; | |
| 979 | + clock-names = "pclk"; | |
| 661 | 980 | status = "disabled"; |
| 662 | 981 | }; |
| 663 | 982 | |
| @@ -667,6 +986,8 @@ · 3 unmodified lines | ||
| 667 | 986 | compatible = "atmel,at91sam9g45-adc"; |
| 668 | 987 | reg = <0xfffb0000 0x100>; |
| 669 | 988 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
| 989 | + clocks = <&adc_clk>, <&adc_op_clk>; | |
| 990 | + clock-names = "adc_clk", "adc_op_clk"; | |
| 670 | 991 | atmel,adc-channels-used = <0xff>; |
| 671 | 992 | atmel,adc-vref = <3300>; |
| 672 | 993 | atmel,adc-startup-time = <40>; |
| @@ -706,6 +1027,7 @@ · 33 unmodified lines | ||
| 706 | 1027 | reg = <0xfffb8000 0x300>; |
| 707 | 1028 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; |
| 708 | 1029 | #pwm-cells = <3>; |
| 1030 | + clocks = <&pwm_clk>; | |
| 709 | 1031 | status = "disabled"; |
| 710 | 1032 | }; |
| 711 | 1033 | |
| @@ -718,6 +1040,8 @@ · 6 unmodified lines | ||
| 718 | 1040 | dma-names = "rxtx"; |
| 719 | 1041 | #address-cells = <1>; |
| 720 | 1042 | #size-cells = <0>; |
| 1043 | + clocks = <&mci0_clk>; | |
| 1044 | + clock-names = "mci_clk"; | |
| 721 | 1045 | status = "disabled"; |
| 722 | 1046 | }; |
| 723 | 1047 | |
| @@ -730,6 +1054,8 @@ · 6 unmodified lines | ||
| 730 | 1054 | dma-names = "rxtx"; |
| 731 | 1055 | #address-cells = <1>; |
| 732 | 1056 | #size-cells = <0>; |
| 1057 | + clocks = <&mci1_clk>; | |
| 1058 | + clock-names = "mci_clk"; | |
| 733 | 1059 | status = "disabled"; |
| 734 | 1060 | }; |
| 735 | 1061 | |
| @@ -752,6 +1078,8 @@ · 16 unmodified lines | ||
| 752 | 1078 | interrupts = <14 4 3>; |
| 753 | 1079 | pinctrl-names = "default"; |
| 754 | 1080 | pinctrl-0 = <&pinctrl_spi0>; |
| 1081 | + clocks = <&spi0_clk>; | |
| 1082 | + clock-names = "spi_clk"; | |
| 755 | 1083 | status = "disabled"; |
| 756 | 1084 | }; |
| 757 | 1085 | |
| @@ -763,6 +1091,8 @@ · 5 unmodified lines | ||
| 763 | 1091 | interrupts = <15 4 3>; |
| 764 | 1092 | pinctrl-names = "default"; |
| 765 | 1093 | pinctrl-0 = <&pinctrl_spi1>; |
| 1094 | + clocks = <&spi1_clk>; | |
| 1095 | + clock-names = "spi_clk"; | |
| 766 | 1096 | status = "disabled"; |
| 767 | 1097 | }; |
| 768 | 1098 | |
| @@ -773,6 +1103,8 @@ · 4 unmodified lines | ||
| 773 | 1103 | reg = <0x00600000 0x80000 |
| 774 | 1104 | 0xfff78000 0x400>; |
| 775 | 1105 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; |
| 1106 | + clocks = <&udphs_clk>, <&utmi>; | |
| 1107 | + clock-names = "pclk", "hclk"; | |
| 776 | 1108 | status = "disabled"; |
| 777 | 1109 | |
| 778 | 1110 | ep0 { |
| @@ -835,6 +1167,8 @@ · 56 unmodified lines | ||
| 835 | 1167 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; |
| 836 | 1168 | pinctrl-names = "default"; |
| 837 | 1169 | pinctrl-0 = <&pinctrl_fb>; |
| 1170 | + clocks = <&lcd_clk>, <&lcd_clk>; | |
| 1171 | + clock-names = "hclk", "lcdc_clk"; | |
| 838 | 1172 | status = "disabled"; |
| 839 | 1173 | }; |
| 840 | 1174 | |
| @@ -861,6 +1195,9 @@ · 20 unmodified lines | ||
| 861 | 1195 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 862 | 1196 | reg = <0x00700000 0x100000>; |
| 863 | 1197 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
| 1198 | + //TODO | |
| 1199 | + clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; | |
| 1200 | + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | |
| 864 | 1201 | status = "disabled"; |
| 865 | 1202 | }; |
| 866 | 1203 | |
| @@ -868,6 +1205,9 @@ · 1 unmodified line | ||
| 868 | 1205 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 869 | 1206 | reg = <0x00800000 0x100000>; |
| 870 | 1207 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
| 1208 | + //TODO | |
| 1209 | + clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; | |
| 1210 | + clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck"; | |
| 871 | 1211 | status = "disabled"; |
| 872 | 1212 | }; |
| 873 | 1213 | }; |
| @@ -31,6 +31,14 @@ · 30 unmodified lines | ||
| 31 | 31 | compatible = "atmel,osc", "fixed-clock"; |
| 32 | 32 | clock-frequency = <12000000>; |
| 33 | 33 | }; |
| 34 | + | |
| 35 | + slow_xtal { | |
| 36 | + clock-frequency = <32768>; | |
| 37 | + }; | |
| 38 | + | |
| 39 | + main_xtal { | |
| 40 | + clock-frequency = <12000000>; | |
| 41 | + }; | |
| 34 | 42 | }; |
| 35 | 43 | |
| 36 | 44 | ahb { |
| @@ -50,16 +50,18 @@ · 49 unmodified lines | ||
| 50 | 50 | reg = <0x20000000 0x10000000>; |
| 51 | 51 | }; |
| 52 | 52 | |
| 53 | − slow_xtal: slow_xtal { | |
| 54 | − compatible = "fixed-clock"; | |
| 55 | − #clock-cells = <0>; | |
| 56 | − clock-frequency = <0>; | |
| 57 | − }; | |
| 53 | + clocks { | |
| 54 | + slow_xtal: slow_xtal { | |
| 55 | + compatible = "fixed-clock"; | |
| 56 | + #clock-cells = <0>; | |
| 57 | + clock-frequency = <0>; | |
| 58 | + }; | |
| 58 | 59 | |
| 59 | − main_xtal: main_xtal { | |
| 60 | − compatible = "fixed-clock"; | |
| 61 | − #clock-cells = <0>; | |
| 62 | − clock-frequency = <0>; | |
| 60 | + main_xtal: main_xtal { | |
| 61 | + compatible = "fixed-clock"; | |
| 62 | + #clock-cells = <0>; | |
| 63 | + clock-frequency = <0>; | |
| 64 | + }; | |
| 63 | 65 | }; |
| 64 | 66 | |
| 65 | 67 | ahb { |
| @@ -21,14 +21,6 @@ · 20 unmodified lines | ||
| 21 | 21 | reg = <0x20000000 0x8000000>; |
| 22 | 22 | }; |
| 23 | 23 | |
| 24 | − slow_xtal { | |
| 25 | − clock-frequency = <32768>; | |
| 26 | − }; | |
| 27 | − | |
| 28 | − main_xtal { | |
| 29 | − clock-frequency = <16000000>; | |
| 30 | − }; | |
| 31 | − | |
| 32 | 24 | clocks { |
| 33 | 25 | #address-cells = <1>; |
| 34 | 26 | #size-cells = <1>; |
| @@ -38,6 +30,14 @@ · 3 unmodified lines | ||
| 38 | 30 | compatible = "atmel,osc", "fixed-clock"; |
| 39 | 31 | clock-frequency = <16000000>; |
| 40 | 32 | }; |
| 33 | + | |
| 34 | + slow_xtal { | |
| 35 | + clock-frequency = <32768>; | |
| 36 | + }; | |
| 37 | + | |
| 38 | + main_xtal { | |
| 39 | + clock-frequency = <16000000>; | |
| 40 | + }; | |
| 41 | 41 | }; |
| 42 | 42 | |
| 43 | 43 | ahb { |
| @@ -56,6 +56,8 @@ · 12 unmodified lines | ||
| 56 | 56 | wm8904: codec@1a { |
| 57 | 57 | compatible = "wm8904"; |
| 58 | 58 | reg = <0x1a>; |
| 59 | + clocks = <&pck0>; | |
| 60 | + clock-names = "mclk"; | |
| 59 | 61 | }; |
| 60 | 62 | |
| 61 | 63 | qt1070: keyboard@1b { |
| @@ -50,19 +50,19 @@ · 49 unmodified lines | ||
| 50 | 50 | reg = <0x20000000 0x04000000>; |
| 51 | 51 | }; |
| 52 | 52 | |
| 53 | − slow_xtal: slow_xtal { | |
| 54 | − compatible = "fixed-clock"; | |
| 55 | − #clock-cells = <0>; | |
| 56 | − clock-frequency = <0>; | |
| 57 | − }; | |
| 53 | + clocks { | |
| 54 | + slow_xtal: slow_xtal { | |
| 55 | + compatible = "fixed-clock"; | |
| 56 | + #clock-cells = <0>; | |
| 57 | + clock-frequency = <0>; | |
| 58 | + }; | |
| 58 | 59 | |
| 59 | − main_xtal: main_xtal { | |
| 60 | − compatible = "fixed-clock"; | |
| 61 | − #clock-cells = <0>; | |
| 62 | − clock-frequency = <0>; | |
| 63 | − }; | |
| 60 | + main_xtal: main_xtal { | |
| 61 | + compatible = "fixed-clock"; | |
| 62 | + #clock-cells = <0>; | |
| 63 | + clock-frequency = <0>; | |
| 64 | + }; | |
| 64 | 65 | |
| 65 | − clocks { | |
| 66 | 66 | adc_op_clk: adc_op_clk{ |
| 67 | 67 | compatible = "fixed-clock"; |
| 68 | 68 | #clock-cells = <0>; |
| @@ -95,6 +95,7 @@ · 26 unmodified lines | ||
| 95 | 95 | <0xffffe800 0x200>; |
| 96 | 96 | atmel,nand-addr-offset = <21>; |
| 97 | 97 | atmel,nand-cmd-offset = <22>; |
| 98 | + atmel,nand-has-dma; | |
| 98 | 99 | pinctrl-names = "default"; |
| 99 | 100 | pinctrl-0 = <&pinctrl_nand>; |
| 100 | 101 | gpios = <&pioD 17 GPIO_ACTIVE_HIGH>, |
| @@ -348,6 +349,15 @@ · 247 unmodified lines | ||
| 348 | 349 | }; |
| 349 | 350 | }; |
| 350 | 351 | |
| 352 | + dma0: dma-controller@ffffe600 { | |
| 353 | + compatible = "atmel,at91sam9rl-dma"; | |
| 354 | + reg = <0xffffe600 0x200>; | |
| 355 | + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 356 | + #dma-cells = <2>; | |
| 357 | + clocks = <&dma0_clk>; | |
| 358 | + clock-names = "dma_clk"; | |
| 359 | + }; | |
| 360 | + | |
| 351 | 361 | ramc0: ramc@ffffea00 { |
| 352 | 362 | compatible = "atmel,at91sam9260-sdramc"; |
| 353 | 363 | reg = <0xffffea00 0x200>; |
| @@ -20,15 +20,6 @@ · 19 unmodified lines | ||
| 20 | 20 | reg = <0x20000000 0x4000000>; |
| 21 | 21 | }; |
| 22 | 22 | |
| 23 | − | |
| 24 | − slow_xtal { | |
| 25 | − clock-frequency = <32768>; | |
| 26 | − }; | |
| 27 | − | |
| 28 | − main_xtal { | |
| 29 | − clock-frequency = <12000000>; | |
| 30 | − }; | |
| 31 | − | |
| 32 | 23 | clocks { |
| 33 | 24 | #address-cells = <1>; |
| 34 | 25 | #size-cells = <1>; |
| @@ -38,6 +29,14 @@ · 3 unmodified lines | ||
| 38 | 29 | compatible = "atmel,osc", "fixed-clock"; |
| 39 | 30 | clock-frequency = <12000000>; |
| 40 | 31 | }; |
| 32 | + | |
| 33 | + slow_xtal { | |
| 34 | + clock-frequency = <32768>; | |
| 35 | + }; | |
| 36 | + | |
| 37 | + main_xtal { | |
| 38 | + clock-frequency = <12000000>; | |
| 39 | + }; | |
| 41 | 40 | }; |
| 42 | 41 | |
| 43 | 42 | ahb { |
| @@ -52,22 +52,24 @@ · 51 unmodified lines | ||
| 52 | 52 | reg = <0x20000000 0x10000000>; |
| 53 | 53 | }; |
| 54 | 54 | |
| 55 | − slow_xtal: slow_xtal { | |
| 56 | − compatible = "fixed-clock"; | |
| 57 | − #clock-cells = <0>; | |
| 58 | − clock-frequency = <0>; | |
| 59 | − }; | |
| 55 | + clocks { | |
| 56 | + slow_xtal: slow_xtal { | |
| 57 | + compatible = "fixed-clock"; | |
| 58 | + #clock-cells = <0>; | |
| 59 | + clock-frequency = <0>; | |
| 60 | + }; | |
| 60 | 61 | |
| 61 | − main_xtal: main_xtal { | |
| 62 | − compatible = "fixed-clock"; | |
| 63 | − #clock-cells = <0>; | |
| 64 | − clock-frequency = <0>; | |
| 65 | − }; | |
| 62 | + main_xtal: main_xtal { | |
| 63 | + compatible = "fixed-clock"; | |
| 64 | + #clock-cells = <0>; | |
| 65 | + clock-frequency = <0>; | |
| 66 | + }; | |
| 66 | 67 | |
| 67 | − adc_op_clk: adc_op_clk{ | |
| 68 | − compatible = "fixed-clock"; | |
| 69 | − #clock-cells = <0>; | |
| 70 | − clock-frequency = <5000000>; | |
| 68 | + adc_op_clk: adc_op_clk{ | |
| 69 | + compatible = "fixed-clock"; | |
| 70 | + #clock-cells = <0>; | |
| 71 | + clock-frequency = <5000000>; | |
| 72 | + }; | |
| 71 | 73 | }; |
| 72 | 74 | |
| 73 | 75 | ahb { |
| @@ -23,12 +23,14 @@ · 22 unmodified lines | ||
| 23 | 23 | }; |
| 24 | 24 | }; |
| 25 | 25 | |
| 26 | − slow_xtal { | |
| 27 | − clock-frequency = <32768>; | |
| 28 | − }; | |
| 26 | + clocks { | |
| 27 | + slow_xtal { | |
| 28 | + clock-frequency = <32768>; | |
| 29 | + }; | |
| 29 | 30 | |
| 30 | − main_xtal { | |
| 31 | − clock-frequency = <12000000>; | |
| 31 | + main_xtal { | |
| 32 | + clock-frequency = <12000000>; | |
| 33 | + }; | |
| 32 | 34 | }; |
| 33 | 35 | |
| 34 | 36 | ahb { |
| @@ -27,6 +27,25 @@ · 26 unmodified lines | ||
| 27 | 27 | bootargs = "console=ttyS0,115200n8"; |
| 28 | 28 | }; |
| 29 | 29 | |
| 30 | + cpus { | |
| 31 | + #address-cells = <1>; | |
| 32 | + #size-cells = <0>; | |
| 33 | + enable-method = "brcm,bcm11351-cpu-method"; | |
| 34 | + secondary-boot-reg = <0x3500417c>; | |
| 35 | + | |
| 36 | + cpu0: cpu@0 { | |
| 37 | + device_type = "cpu"; | |
| 38 | + compatible = "arm,cortex-a9"; | |
| 39 | + reg = <0>; | |
| 40 | + }; | |
| 41 | + | |
| 42 | + cpu1: cpu@1 { | |
| 43 | + device_type = "cpu"; | |
| 44 | + compatible = "arm,cortex-a9"; | |
| 45 | + reg = <1>; | |
| 46 | + }; | |
| 47 | + }; | |
| 48 | + | |
| 30 | 49 | gic: interrupt-controller@3ff00100 { |
| 31 | 50 | compatible = "arm,cortex-a9-gic"; |
| 32 | 51 | #interrupt-cells = <3>; |
| @@ -27,6 +27,25 @@ · 26 unmodified lines | ||
| 27 | 27 | bootargs = "console=ttyS0,115200n8"; |
| 28 | 28 | }; |
| 29 | 29 | |
| 30 | + cpus { | |
| 31 | + #address-cells = <1>; | |
| 32 | + #size-cells = <0>; | |
| 33 | + enable-method = "brcm,bcm11351-cpu-method"; | |
| 34 | + secondary-boot-reg = <0x35004178>; | |
| 35 | + | |
| 36 | + cpu0: cpu@0 { | |
| 37 | + device_type = "cpu"; | |
| 38 | + compatible = "arm,cortex-a9"; | |
| 39 | + reg = <0>; | |
| 40 | + }; | |
| 41 | + | |
| 42 | + cpu1: cpu@1 { | |
| 43 | + device_type = "cpu"; | |
| 44 | + compatible = "arm,cortex-a9"; | |
| 45 | + reg = <1>; | |
| 46 | + }; | |
| 47 | + }; | |
| 48 | + | |
| 30 | 49 | gic: interrupt-controller@3ff00100 { |
| 31 | 50 | compatible = "arm,cortex-a9-gic"; |
| 32 | 51 | #interrupt-cells = <3>; |
| @@ -0,0 +1,14 @@ | ||
| 1 | +/dts-v1/; | |
| 2 | +#include "bcm7445.dtsi" | |
| 3 | + | |
| 4 | +/ { | |
| 5 | + model = "Broadcom STB (bcm7445), SVMB reference board"; | |
| 6 | + compatible = "brcm,bcm7445", "brcm,brcmstb"; | |
| 7 | + | |
| 8 | + memory { | |
| 9 | + device_type = "memory"; | |
| 10 | + reg = <0x00 0x00000000 0x00 0x40000000>, | |
| 11 | + <0x00 0x40000000 0x00 0x40000000>, | |
| 12 | + <0x00 0x80000000 0x00 0x40000000>; | |
| 13 | + }; | |
| 14 | +}; | |
| @@ -0,0 +1,111 @@ | ||
| 1 | +#include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 2 | + | |
| 3 | +#include "skeleton.dtsi" | |
| 4 | + | |
| 5 | +/ { | |
| 6 | + #address-cells = <2>; | |
| 7 | + #size-cells = <2>; | |
| 8 | + model = "Broadcom STB (bcm7445)"; | |
| 9 | + compatible = "brcm,bcm7445", "brcm,brcmstb"; | |
| 10 | + interrupt-parent = <&gic>; | |
| 11 | + | |
| 12 | + chosen { | |
| 13 | + bootargs = "console=ttyS0,115200 earlyprintk"; | |
| 14 | + }; | |
| 15 | + | |
| 16 | + cpus { | |
| 17 | + #address-cells = <1>; | |
| 18 | + #size-cells = <0>; | |
| 19 | + | |
| 20 | + cpu@0 { | |
| 21 | + compatible = "brcm,brahma-b15"; | |
| 22 | + device_type = "cpu"; | |
| 23 | + enable-method = "brcm,brahma-b15"; | |
| 24 | + reg = <0>; | |
| 25 | + }; | |
| 26 | + | |
| 27 | + cpu@1 { | |
| 28 | + compatible = "brcm,brahma-b15"; | |
| 29 | + device_type = "cpu"; | |
| 30 | + enable-method = "brcm,brahma-b15"; | |
| 31 | + reg = <1>; | |
| 32 | + }; | |
| 33 | + | |
| 34 | + cpu@2 { | |
| 35 | + compatible = "brcm,brahma-b15"; | |
| 36 | + device_type = "cpu"; | |
| 37 | + enable-method = "brcm,brahma-b15"; | |
| 38 | + reg = <2>; | |
| 39 | + }; | |
| 40 | + | |
| 41 | + cpu@3 { | |
| 42 | + compatible = "brcm,brahma-b15"; | |
| 43 | + device_type = "cpu"; | |
| 44 | + enable-method = "brcm,brahma-b15"; | |
| 45 | + reg = <3>; | |
| 46 | + }; | |
| 47 | + }; | |
| 48 | + | |
| 49 | + gic: interrupt-controller@ffd00000 { | |
| 50 | + compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic"; | |
| 51 | + reg = <0x00 0xffd01000 0x00 0x1000>, | |
| 52 | + <0x00 0xffd02000 0x00 0x2000>, | |
| 53 | + <0x00 0xffd04000 0x00 0x2000>, | |
| 54 | + <0x00 0xffd06000 0x00 0x2000>; | |
| 55 | + interrupt-controller; | |
| 56 | + #interrupt-cells = <3>; | |
| 57 | + }; | |
| 58 | + | |
| 59 | + timer { | |
| 60 | + compatible = "arm,armv7-timer"; | |
| 61 | + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, | |
| 62 | + <GIC_PPI 14 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, | |
| 63 | + <GIC_PPI 11 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, | |
| 64 | + <GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; | |
| 65 | + }; | |
| 66 | + | |
| 67 | + rdb { | |
| 68 | + #address-cells = <1>; | |
| 69 | + #size-cells = <1>; | |
| 70 | + compatible = "simple-bus"; | |
| 71 | + ranges = <0 0x00 0xf0000000 0x1000000>; | |
| 72 | + | |
| 73 | + serial@40ab00 { | |
| 74 | + compatible = "ns16550a"; | |
| 75 | + reg = <0x40ab00 0x20>; | |
| 76 | + reg-shift = <2>; | |
| 77 | + reg-io-width = <4>; | |
| 78 | + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 79 | + clock-frequency = <0x4d3f640>; | |
| 80 | + }; | |
| 81 | + | |
| 82 | + sun_top_ctrl: syscon@404000 { | |
| 83 | + compatible = "brcm,bcm7445-sun-top-ctrl", | |
| 84 | + "syscon"; | |
| 85 | + reg = <0x404000 0x51c>; | |
| 86 | + }; | |
| 87 | + | |
| 88 | + hif_cpubiuctrl: syscon@3e2400 { | |
| 89 | + compatible = "brcm,bcm7445-hif-cpubiuctrl", | |
| 90 | + "syscon"; | |
| 91 | + reg = <0x3e2400 0x5b4>; | |
| 92 | + }; | |
| 93 | + | |
| 94 | + hif_continuation: syscon@452000 { | |
| 95 | + compatible = "brcm,bcm7445-hif-continuation", | |
| 96 | + "syscon"; | |
| 97 | + reg = <0x452000 0x100>; | |
| 98 | + }; | |
| 99 | + }; | |
| 100 | + | |
| 101 | + smpboot { | |
| 102 | + compatible = "brcm,brcmstb-smpboot"; | |
| 103 | + syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; | |
| 104 | + syscon-cont = <&hif_continuation>; | |
| 105 | + }; | |
| 106 | + | |
| 107 | + reboot { | |
| 108 | + compatible = "brcm,brcmstb-reboot"; | |
| 109 | + syscon = <&sun_top_ctrl 0x304 0x308>; | |
| 110 | + }; | |
| 111 | +}; | |
| @@ -22,6 +22,7 @@ · 21 unmodified lines | ||
| 22 | 22 | cpus { |
| 23 | 23 | #address-cells = <1>; |
| 24 | 24 | #size-cells = <0>; |
| 25 | + enable-method = "marvell,berlin-smp"; | |
| 25 | 26 | |
| 26 | 27 | cpu@0 { |
| 27 | 28 | compatible = "marvell,pj4b"; |
| @@ -78,6 +79,11 @@ · 50 unmodified lines | ||
| 78 | 79 | clocks = <&chip CLKID_TWD>; |
| 79 | 80 | }; |
| 80 | 81 | |
| 82 | + cpu-ctrl@dd0000 { | |
| 83 | + compatible = "marvell,berlin-cpu-ctrl"; | |
| 84 | + reg = <0xdd0000 0x10000>; | |
| 85 | + }; | |
| 86 | + | |
| 81 | 87 | apb@e80000 { |
| 82 | 88 | compatible = "simple-bus"; |
| 83 | 89 | #address-cells = <1>; |
| @@ -34,6 +34,14 @@ · 33 unmodified lines | ||
| 34 | 34 | status = "okay"; |
| 35 | 35 | }; |
| 36 | 36 | |
| 37 | +&i2c0 { | |
| 38 | + status = "okay"; | |
| 39 | +}; | |
| 40 | + | |
| 41 | +&i2c2 { | |
| 42 | + status = "okay"; | |
| 43 | +}; | |
| 44 | + | |
| 37 | 45 | &uart0 { |
| 38 | 46 | status = "okay"; |
| 39 | 47 | }; |
| @@ -18,6 +18,7 @@ · 17 unmodified lines | ||
| 18 | 18 | cpus { |
| 19 | 19 | #address-cells = <1>; |
| 20 | 20 | #size-cells = <0>; |
| 21 | + enable-method = "marvell,berlin-smp"; | |
| 21 | 22 | |
| 22 | 23 | cpu@0 { |
| 23 | 24 | compatible = "arm,cortex-a9"; |
| @@ -90,6 +91,8 @@ · 66 unmodified lines | ||
| 90 | 91 | compatible = "arm,pl310-cache"; |
| 91 | 92 | reg = <0xac0000 0x1000>; |
| 92 | 93 | cache-level = <2>; |
| 94 | + arm,data-latency = <2 2 2>; | |
| 95 | + arm,tag-latency = <2 2 2>; | |
| 93 | 96 | }; |
| 94 | 97 | |
| 95 | 98 | scu: snoop-control-unit@ad0000 { |
| @@ -111,6 +114,11 @@ · 15 unmodified lines | ||
| 111 | 114 | #interrupt-cells = <3>; |
| 112 | 115 | }; |
| 113 | 116 | |
| 117 | + cpu-ctrl@dd0000 { | |
| 118 | + compatible = "marvell,berlin-cpu-ctrl"; | |
| 119 | + reg = <0xdd0000 0x10000>; | |
| 120 | + }; | |
| 121 | + | |
| 114 | 122 | apb@e80000 { |
| 115 | 123 | compatible = "simple-bus"; |
| 116 | 124 | #address-cells = <1>; |
| @@ -191,6 +199,32 @@ · 74 unmodified lines | ||
| 191 | 199 | }; |
| 192 | 200 | }; |
| 193 | 201 | |
| 202 | + i2c0: i2c@1400 { | |
| 203 | + compatible = "snps,designware-i2c"; | |
| 204 | + #address-cells = <1>; | |
| 205 | + #size-cells = <0>; | |
| 206 | + reg = <0x1400 0x100>; | |
| 207 | + interrupt-parent = <&aic>; | |
| 208 | + interrupts = <4>; | |
| 209 | + clocks = <&chip CLKID_CFG>; | |
| 210 | + pinctrl-0 = <&twsi0_pmux>; | |
| 211 | + pinctrl-names = "default"; | |
| 212 | + status = "disabled"; | |
| 213 | + }; | |
| 214 | + | |
| 215 | + i2c1: i2c@1800 { | |
| 216 | + compatible = "snps,designware-i2c"; | |
| 217 | + #address-cells = <1>; | |
| 218 | + #size-cells = <0>; | |
| 219 | + reg = <0x1800 0x100>; | |
| 220 | + interrupt-parent = <&aic>; | |
| 221 | + interrupts = <5>; | |
| 222 | + clocks = <&chip CLKID_CFG>; | |
| 223 | + pinctrl-0 = <&twsi1_pmux>; | |
| 224 | + pinctrl-names = "default"; | |
| 225 | + status = "disabled"; | |
| 226 | + }; | |
| 227 | + | |
| 194 | 228 | timer0: timer@2c00 { |
| 195 | 229 | compatible = "snps,dw-apb-timer"; |
| 196 | 230 | reg = <0x2c00 0x14>; |
| @@ -301,6 +335,16 @@ · 104 unmodified lines | ||
| 301 | 335 | reg = <0xea0000 0x400>, <0xdd0170 0x10>; |
| 302 | 336 | clocks = <&refclk>; |
| 303 | 337 | clock-names = "refclk"; |
| 338 | + | |
| 339 | + twsi0_pmux: twsi0-pmux { | |
| 340 | + groups = "G6"; | |
| 341 | + function = "twsi0"; | |
| 342 | + }; | |
| 343 | + | |
| 344 | + twsi1_pmux: twsi1-pmux { | |
| 345 | + groups = "G7"; | |
| 346 | + function = "twsi1"; | |
| 347 | + }; | |
| 304 | 348 | }; |
| 305 | 349 | |
| 306 | 350 | apb@fc0000 { |
| @@ -311,6 +355,32 @@ · 4 unmodified lines | ||
| 311 | 355 | ranges = <0 0xfc0000 0x10000>; |
| 312 | 356 | interrupt-parent = <&sic>; |
| 313 | 357 | |
| 358 | + i2c2: i2c@7000 { | |
| 359 | + compatible = "snps,designware-i2c"; | |
| 360 | + #address-cells = <1>; | |
| 361 | + #size-cells = <0>; | |
| 362 | + reg = <0x7000 0x100>; | |
| 363 | + interrupt-parent = <&sic>; | |
| 364 | + interrupts = <6>; | |
| 365 | + clocks = <&refclk>; | |
| 366 | + pinctrl-0 = <&twsi2_pmux>; | |
| 367 | + pinctrl-names = "default"; | |
| 368 | + status = "disabled"; | |
| 369 | + }; | |
| 370 | + | |
| 371 | + i2c3: i2c@8000 { | |
| 372 | + compatible = "snps,designware-i2c"; | |
| 373 | + #address-cells = <1>; | |
| 374 | + #size-cells = <0>; | |
| 375 | + reg = <0x8000 0x100>; | |
| 376 | + interrupt-parent = <&sic>; | |
| 377 | + interrupts = <7>; | |
| 378 | + clocks = <&refclk>; | |
| 379 | + pinctrl-0 = <&twsi3_pmux>; | |
| 380 | + pinctrl-names = "default"; | |
| 381 | + status = "disabled"; | |
| 382 | + }; | |
| 383 | + | |
| 314 | 384 | uart0: uart@9000 { |
| 315 | 385 | compatible = "snps,dw-apb-uart"; |
| 316 | 386 | reg = <0x9000 0x100>; |
| @@ -348,6 +418,16 @@ · 31 unmodified lines | ||
| 348 | 418 | groups = "GSM14"; |
| 349 | 419 | function = "uart1"; |
| 350 | 420 | }; |
| 421 | + | |
| 422 | + twsi2_pmux: twsi2-pmux { | |
| 423 | + groups = "GSM13"; | |
| 424 | + function = "twsi2"; | |
| 425 | + }; | |
| 426 | + | |
| 427 | + twsi3_pmux: twsi3-pmux { | |
| 428 | + groups = "GSM14"; | |
| 429 | + function = "twsi3"; | |
| 430 | + }; | |
| 351 | 431 | }; |
| 352 | 432 | |
| 353 | 433 | sic: interrupt-controller@e000 { |
| @@ -0,0 +1,105 @@ | ||
| 1 | +/* | |
| 2 | + * Keyboard dts fragment for devices that use cros-ec-keyboard | |
| 3 | + * | |
| 4 | + * Copyright (c) 2014 Google, Inc | |
| 5 | + * | |
| 6 | + * This program is free software; you can redistribute it and/or modify | |
| 7 | + * it under the terms of the GNU General Public License version 2 as | |
| 8 | + * published by the Free Software Foundation. | |
| 9 | +*/ | |
| 10 | + | |
| 11 | +#include <dt-bindings/input/input.h> | |
| 12 | + | |
| 13 | +&cros_ec { | |
| 14 | + keyboard-controller { | |
| 15 | + compatible = "google,cros-ec-keyb"; | |
| 16 | + keypad,num-rows = <8>; | |
| 17 | + keypad,num-columns = <13>; | |
| 18 | + google,needs-ghost-filter; | |
| 19 | + | |
| 20 | + linux,keymap = < | |
| 21 | + MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) | |
| 22 | + MATRIX_KEY(0x00, 0x02, KEY_F1) | |
| 23 | + MATRIX_KEY(0x00, 0x03, KEY_B) | |
| 24 | + MATRIX_KEY(0x00, 0x04, KEY_F10) | |
| 25 | + MATRIX_KEY(0x00, 0x06, KEY_N) | |
| 26 | + MATRIX_KEY(0x00, 0x08, KEY_EQUAL) | |
| 27 | + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) | |
| 28 | + | |
| 29 | + MATRIX_KEY(0x01, 0x01, KEY_ESC) | |
| 30 | + MATRIX_KEY(0x01, 0x02, KEY_F4) | |
| 31 | + MATRIX_KEY(0x01, 0x03, KEY_G) | |
| 32 | + MATRIX_KEY(0x01, 0x04, KEY_F7) | |
| 33 | + MATRIX_KEY(0x01, 0x06, KEY_H) | |
| 34 | + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) | |
| 35 | + MATRIX_KEY(0x01, 0x09, KEY_F9) | |
| 36 | + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) | |
| 37 | + | |
| 38 | + MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) | |
| 39 | + MATRIX_KEY(0x02, 0x01, KEY_TAB) | |
| 40 | + MATRIX_KEY(0x02, 0x02, KEY_F3) | |
| 41 | + MATRIX_KEY(0x02, 0x03, KEY_T) | |
| 42 | + MATRIX_KEY(0x02, 0x04, KEY_F6) | |
| 43 | + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) | |
| 44 | + MATRIX_KEY(0x02, 0x06, KEY_Y) | |
| 45 | + MATRIX_KEY(0x02, 0x07, KEY_102ND) | |
| 46 | + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) | |
| 47 | + MATRIX_KEY(0x02, 0x09, KEY_F8) | |
| 48 | + | |
| 49 | + MATRIX_KEY(0x03, 0x01, KEY_GRAVE) | |
| 50 | + MATRIX_KEY(0x03, 0x02, KEY_F2) | |
| 51 | + MATRIX_KEY(0x03, 0x03, KEY_5) | |
| 52 | + MATRIX_KEY(0x03, 0x04, KEY_F5) | |
| 53 | + MATRIX_KEY(0x03, 0x06, KEY_6) | |
| 54 | + MATRIX_KEY(0x03, 0x08, KEY_MINUS) | |
| 55 | + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) | |
| 56 | + | |
| 57 | + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) | |
| 58 | + MATRIX_KEY(0x04, 0x01, KEY_A) | |
| 59 | + MATRIX_KEY(0x04, 0x02, KEY_D) | |
| 60 | + MATRIX_KEY(0x04, 0x03, KEY_F) | |
| 61 | + MATRIX_KEY(0x04, 0x04, KEY_S) | |
| 62 | + MATRIX_KEY(0x04, 0x05, KEY_K) | |
| 63 | + MATRIX_KEY(0x04, 0x06, KEY_J) | |
| 64 | + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) | |
| 65 | + MATRIX_KEY(0x04, 0x09, KEY_L) | |
| 66 | + MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) | |
| 67 | + MATRIX_KEY(0x04, 0x0b, KEY_ENTER) | |
| 68 | + | |
| 69 | + MATRIX_KEY(0x05, 0x01, KEY_Z) | |
| 70 | + MATRIX_KEY(0x05, 0x02, KEY_C) | |
| 71 | + MATRIX_KEY(0x05, 0x03, KEY_V) | |
| 72 | + MATRIX_KEY(0x05, 0x04, KEY_X) | |
| 73 | + MATRIX_KEY(0x05, 0x05, KEY_COMMA) | |
| 74 | + MATRIX_KEY(0x05, 0x06, KEY_M) | |
| 75 | + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) | |
| 76 | + MATRIX_KEY(0x05, 0x08, KEY_SLASH) | |
| 77 | + MATRIX_KEY(0x05, 0x09, KEY_DOT) | |
| 78 | + MATRIX_KEY(0x05, 0x0b, KEY_SPACE) | |
| 79 | + | |
| 80 | + MATRIX_KEY(0x06, 0x01, KEY_1) | |
| 81 | + MATRIX_KEY(0x06, 0x02, KEY_3) | |
| 82 | + MATRIX_KEY(0x06, 0x03, KEY_4) | |
| 83 | + MATRIX_KEY(0x06, 0x04, KEY_2) | |
| 84 | + MATRIX_KEY(0x06, 0x05, KEY_8) | |
| 85 | + MATRIX_KEY(0x06, 0x06, KEY_7) | |
| 86 | + MATRIX_KEY(0x06, 0x08, KEY_0) | |
| 87 | + MATRIX_KEY(0x06, 0x09, KEY_9) | |
| 88 | + MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) | |
| 89 | + MATRIX_KEY(0x06, 0x0b, KEY_DOWN) | |
| 90 | + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) | |
| 91 | + | |
| 92 | + MATRIX_KEY(0x07, 0x01, KEY_Q) | |
| 93 | + MATRIX_KEY(0x07, 0x02, KEY_E) | |
| 94 | + MATRIX_KEY(0x07, 0x03, KEY_R) | |
| 95 | + MATRIX_KEY(0x07, 0x04, KEY_W) | |
| 96 | + MATRIX_KEY(0x07, 0x05, KEY_I) | |
| 97 | + MATRIX_KEY(0x07, 0x06, KEY_U) | |
| 98 | + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) | |
| 99 | + MATRIX_KEY(0x07, 0x08, KEY_P) | |
| 100 | + MATRIX_KEY(0x07, 0x09, KEY_O) | |
| 101 | + MATRIX_KEY(0x07, 0x0b, KEY_UP) | |
| 102 | + MATRIX_KEY(0x07, 0x0c, KEY_LEFT) | |
| 103 | + >; | |
| 104 | + }; | |
| 105 | +}; | |
| @@ -0,0 +1,12 @@ | ||
| 1 | +#include "dove-cubox.dts" | |
| 2 | + | |
| 3 | +/ { | |
| 4 | + model = "SolidRun CuBox (Engineering Sample)"; | |
| 5 | + compatible = "solidrun,cubox-es", "solidrun,cubox", "marvell,dove"; | |
| 6 | +}; | |
| 7 | + | |
| 8 | +&sdio0 { | |
| 9 | + /* sdio0 card detect is connected to wrong pin on CuBox ES */ | |
| 10 | + cd-gpios = <&gpio0 12 1>; | |
| 11 | + pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>; | |
| 12 | +}; | |
| @@ -111,9 +111,6 @@ · 110 unmodified lines | ||
| 111 | 111 | |
| 112 | 112 | &sdio0 { |
| 113 | 113 | status = "okay"; |
| 114 | − /* sdio0 card detect is connected to wrong pin on CuBox */ | |
| 115 | − cd-gpios = <&gpio0 12 1>; | |
| 116 | − pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>; | |
| 117 | 114 | }; |
| 118 | 115 | |
| 119 | 116 | &spi0 { |
| @@ -630,6 +630,20 @@ · 629 unmodified lines | ||
| 630 | 630 | reg = <0xe8400 0x0c>; |
| 631 | 631 | ngpios = <8>; |
| 632 | 632 | }; |
| 633 | + | |
| 634 | + lcd1: lcd-controller@810000 { | |
| 635 | + compatible = "marvell,dove-lcd"; | |
| 636 | + reg = <0x810000 0x1000>; | |
| 637 | + interrupts = <46>; | |
| 638 | + status = "disabled"; | |
| 639 | + }; | |
| 640 | + | |
| 641 | + lcd0: lcd-controller@820000 { | |
| 642 | + compatible = "marvell,dove-lcd"; | |
| 643 | + reg = <0x820000 0x1000>; | |
| 644 | + interrupts = <47>; | |
| 645 | + status = "disabled"; | |
| 646 | + }; | |
| 633 | 647 | }; |
| 634 | 648 | }; |
| 635 | 649 | }; |
| @@ -496,3 +496,11 @@ · 495 unmodified lines | ||
| 496 | 496 | }; |
| 497 | 497 | }; |
| 498 | 498 | }; |
| 499 | + | |
| 500 | +&usb2_phy1 { | |
| 501 | + phy-supply = <&ldousb_reg>; | |
| 502 | +}; | |
| 503 | + | |
| 504 | +&usb2_phy2 { | |
| 505 | + phy-supply = <&ldousb_reg>; | |
| 506 | +}; | |
| @@ -12,6 +12,9 @@ · 11 unmodified lines | ||
| 12 | 12 | |
| 13 | 13 | #include "skeleton.dtsi" |
| 14 | 14 | |
| 15 | +#define MAX_SOURCES 400 | |
| 16 | +#define DIRECT_IRQ(irq) (MAX_SOURCES + irq) | |
| 17 | + | |
| 15 | 18 | / { |
| 16 | 19 | #address-cells = <1>; |
| 17 | 20 | #size-cells = <1>; |
| @@ -45,6 +48,7 @@ · 27 unmodified lines | ||
| 45 | 48 | compatible = "arm,cortex-a15-gic"; |
| 46 | 49 | interrupt-controller; |
| 47 | 50 | #interrupt-cells = <3>; |
| 51 | + arm,routable-irqs = <192>; | |
| 48 | 52 | reg = <0x48211000 0x1000>, |
| 49 | 53 | <0x48212000 0x1000>, |
| 50 | 54 | <0x48214000 0x2000>, |
| @@ -79,8 +83,8 @@ · 28 unmodified lines | ||
| 79 | 83 | ti,hwmods = "l3_main_1", "l3_main_2"; |
| 80 | 84 | reg = <0x44000000 0x1000000>, |
| 81 | 85 | <0x45000000 0x1000>; |
| 82 | − interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
| 83 | − <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 86 | + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, | |
| 87 | + <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; | |
| 84 | 88 | |
| 85 | 89 | prm: prm@4ae06000 { |
| 86 | 90 | compatible = "ti,dra7-prm"; |
| @@ -95,6 +99,75 @@ · 8 unmodified lines | ||
| 95 | 99 | }; |
| 96 | 100 | }; |
| 97 | 101 | |
| 102 | + axi@0 { | |
| 103 | + compatible = "simple-bus"; | |
| 104 | + #size-cells = <1>; | |
| 105 | + #address-cells = <1>; | |
| 106 | + ranges = <0x51000000 0x51000000 0x3000 | |
| 107 | + 0x0 0x20000000 0x10000000>; | |
| 108 | + pcie@51000000 { | |
| 109 | + compatible = "ti,dra7-pcie"; | |
| 110 | + reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; | |
| 111 | + reg-names = "rc_dbics", "ti_conf", "config"; | |
| 112 | + interrupts = <0 232 0x4>, <0 233 0x4>; | |
| 113 | + #address-cells = <3>; | |
| 114 | + #size-cells = <2>; | |
| 115 | + device_type = "pci"; | |
| 116 | + ranges = <0x81000000 0 0 0x03000 0 0x00010000 | |
| 117 | + 0x82000000 0 0x20013000 0x13000 0 0xffed000>; | |
| 118 | + #interrupt-cells = <1>; | |
| 119 | + num-lanes = <1>; | |
| 120 | + ti,hwmods = "pcie1"; | |
| 121 | + phys = <&pcie1_phy>; | |
| 122 | + phy-names = "pcie-phy0"; | |
| 123 | + interrupt-map-mask = <0 0 0 7>; | |
| 124 | + interrupt-map = <0 0 0 1 &pcie1_intc 1>, | |
| 125 | + <0 0 0 2 &pcie1_intc 2>, | |
| 126 | + <0 0 0 3 &pcie1_intc 3>, | |
| 127 | + <0 0 0 4 &pcie1_intc 4>; | |
| 128 | + pcie1_intc: interrupt-controller { | |
| 129 | + interrupt-controller; | |
| 130 | + #address-cells = <0>; | |
| 131 | + #interrupt-cells = <1>; | |
| 132 | + }; | |
| 133 | + }; | |
| 134 | + }; | |
| 135 | + | |
| 136 | + axi@1 { | |
| 137 | + compatible = "simple-bus"; | |
| 138 | + #size-cells = <1>; | |
| 139 | + #address-cells = <1>; | |
| 140 | + ranges = <0x51800000 0x51800000 0x3000 | |
| 141 | + 0x0 0x30000000 0x10000000>; | |
| 142 | + status = "disabled"; | |
| 143 | + pcie@51000000 { | |
| 144 | + compatible = "ti,dra7-pcie"; | |
| 145 | + reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; | |
| 146 | + reg-names = "rc_dbics", "ti_conf", "config"; | |
| 147 | + interrupts = <0 355 0x4>, <0 356 0x4>; | |
| 148 | + #address-cells = <3>; | |
| 149 | + #size-cells = <2>; | |
| 150 | + device_type = "pci"; | |
| 151 | + ranges = <0x81000000 0 0 0x03000 0 0x00010000 | |
| 152 | + 0x82000000 0 0x30013000 0x13000 0 0xffed000>; | |
| 153 | + #interrupt-cells = <1>; | |
| 154 | + num-lanes = <1>; | |
| 155 | + ti,hwmods = "pcie2"; | |
| 156 | + phys = <&pcie2_phy>; | |
| 157 | + phy-names = "pcie-phy0"; | |
| 158 | + interrupt-map-mask = <0 0 0 7>; | |
| 159 | + interrupt-map = <0 0 0 1 &pcie2_intc 1>, | |
| 160 | + <0 0 0 2 &pcie2_intc 2>, | |
| 161 | + <0 0 0 3 &pcie2_intc 3>, | |
| 162 | + <0 0 0 4 &pcie2_intc 4>; | |
| 163 | + pcie2_intc: interrupt-controller { | |
| 164 | + interrupt-controller; | |
| 165 | + #address-cells = <0>; | |
| 166 | + #interrupt-cells = <1>; | |
| 167 | + }; | |
| 168 | + }; | |
| 169 | + }; | |
| 170 | + | |
| 98 | 171 | cm_core_aon: cm_core_aon@4a005000 { |
| 99 | 172 | compatible = "ti,dra7-cm-core-aon"; |
| 100 | 173 | reg = <0x4a005000 0x2000>; |
| @@ -155,10 +228,10 @@ · 54 unmodified lines | ||
| 155 | 228 | sdma: dma-controller@4a056000 { |
| 156 | 229 | compatible = "ti,omap4430-sdma"; |
| 157 | 230 | reg = <0x4a056000 0x1000>; |
| 158 | − interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | |
| 159 | − <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
| 160 | − <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
| 161 | − <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
| 231 | + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
| 232 | + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
| 233 | + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
| 234 | + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 162 | 235 | #dma-cells = <1>; |
| 163 | 236 | #dma-channels = <32>; |
| 164 | 237 | #dma-requests = <127>; |
| @@ -167,7 +240,7 @@ · 2 unmodified lines | ||
| 167 | 240 | gpio1: gpio@4ae10000 { |
| 168 | 241 | compatible = "ti,omap4-gpio"; |
| 169 | 242 | reg = <0x4ae10000 0x200>; |
| 170 | − interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
| 243 | + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
| 171 | 244 | ti,hwmods = "gpio1"; |
| 172 | 245 | gpio-controller; |
| 173 | 246 | #gpio-cells = <2>; |
| @@ -178,7 +251,7 @@ · 4 unmodified lines | ||
| 178 | 251 | gpio2: gpio@48055000 { |
| 179 | 252 | compatible = "ti,omap4-gpio"; |
| 180 | 253 | reg = <0x48055000 0x200>; |
| 181 | − interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
| 254 | + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
| 182 | 255 | ti,hwmods = "gpio2"; |
| 183 | 256 | gpio-controller; |
| 184 | 257 | #gpio-cells = <2>; |
| @@ -189,7 +262,7 @@ · 4 unmodified lines | ||
| 189 | 262 | gpio3: gpio@48057000 { |
| 190 | 263 | compatible = "ti,omap4-gpio"; |
| 191 | 264 | reg = <0x48057000 0x200>; |
| 192 | − interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
| 265 | + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
| 193 | 266 | ti,hwmods = "gpio3"; |
| 194 | 267 | gpio-controller; |
| 195 | 268 | #gpio-cells = <2>; |
| @@ -200,7 +273,7 @@ · 4 unmodified lines | ||
| 200 | 273 | gpio4: gpio@48059000 { |
| 201 | 274 | compatible = "ti,omap4-gpio"; |
| 202 | 275 | reg = <0x48059000 0x200>; |
| 203 | − interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
| 276 | + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
| 204 | 277 | ti,hwmods = "gpio4"; |
| 205 | 278 | gpio-controller; |
| 206 | 279 | #gpio-cells = <2>; |
| @@ -211,7 +284,7 @@ · 4 unmodified lines | ||
| 211 | 284 | gpio5: gpio@4805b000 { |
| 212 | 285 | compatible = "ti,omap4-gpio"; |
| 213 | 286 | reg = <0x4805b000 0x200>; |
| 214 | − interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
| 287 | + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
| 215 | 288 | ti,hwmods = "gpio5"; |
| 216 | 289 | gpio-controller; |
| 217 | 290 | #gpio-cells = <2>; |
| @@ -222,7 +295,7 @@ · 4 unmodified lines | ||
| 222 | 295 | gpio6: gpio@4805d000 { |
| 223 | 296 | compatible = "ti,omap4-gpio"; |
| 224 | 297 | reg = <0x4805d000 0x200>; |
| 225 | − interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
| 298 | + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
| 226 | 299 | ti,hwmods = "gpio6"; |
| 227 | 300 | gpio-controller; |
| 228 | 301 | #gpio-cells = <2>; |
| @@ -233,7 +306,7 @@ · 4 unmodified lines | ||
| 233 | 306 | gpio7: gpio@48051000 { |
| 234 | 307 | compatible = "ti,omap4-gpio"; |
| 235 | 308 | reg = <0x48051000 0x200>; |
| 236 | − interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
| 309 | + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
| 237 | 310 | ti,hwmods = "gpio7"; |
| 238 | 311 | gpio-controller; |
| 239 | 312 | #gpio-cells = <2>; |
| @@ -244,7 +317,7 @@ · 4 unmodified lines | ||
| 244 | 317 | gpio8: gpio@48053000 { |
| 245 | 318 | compatible = "ti,omap4-gpio"; |
| 246 | 319 | reg = <0x48053000 0x200>; |
| 247 | − interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; | |
| 320 | + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
| 248 | 321 | ti,hwmods = "gpio8"; |
| 249 | 322 | gpio-controller; |
| 250 | 323 | #gpio-cells = <2>; |
| @@ -255,7 +328,7 @@ · 4 unmodified lines | ||
| 255 | 328 | uart1: serial@4806a000 { |
| 256 | 329 | compatible = "ti,omap4-uart"; |
| 257 | 330 | reg = <0x4806a000 0x100>; |
| 258 | − interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
| 331 | + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
| 259 | 332 | ti,hwmods = "uart1"; |
| 260 | 333 | clock-frequency = <48000000>; |
| 261 | 334 | status = "disabled"; |
| @@ -264,7 +337,7 @@ · 2 unmodified lines | ||
| 264 | 337 | uart2: serial@4806c000 { |
| 265 | 338 | compatible = "ti,omap4-uart"; |
| 266 | 339 | reg = <0x4806c000 0x100>; |
| 267 | − interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
| 340 | + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
| 268 | 341 | ti,hwmods = "uart2"; |
| 269 | 342 | clock-frequency = <48000000>; |
| 270 | 343 | status = "disabled"; |
| @@ -273,7 +346,7 @@ · 2 unmodified lines | ||
| 273 | 346 | uart3: serial@48020000 { |
| 274 | 347 | compatible = "ti,omap4-uart"; |
| 275 | 348 | reg = <0x48020000 0x100>; |
| 276 | − interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
| 349 | + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
| 277 | 350 | ti,hwmods = "uart3"; |
| 278 | 351 | clock-frequency = <48000000>; |
| 279 | 352 | status = "disabled"; |
| @@ -282,7 +355,7 @@ · 2 unmodified lines | ||
| 282 | 355 | uart4: serial@4806e000 { |
| 283 | 356 | compatible = "ti,omap4-uart"; |
| 284 | 357 | reg = <0x4806e000 0x100>; |
| 285 | − interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | |
| 358 | + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
| 286 | 359 | ti,hwmods = "uart4"; |
| 287 | 360 | clock-frequency = <48000000>; |
| 288 | 361 | status = "disabled"; |
| @@ -291,7 +364,7 @@ · 2 unmodified lines | ||
| 291 | 364 | uart5: serial@48066000 { |
| 292 | 365 | compatible = "ti,omap4-uart"; |
| 293 | 366 | reg = <0x48066000 0x100>; |
| 294 | − interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
| 367 | + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
| 295 | 368 | ti,hwmods = "uart5"; |
| 296 | 369 | clock-frequency = <48000000>; |
| 297 | 370 | status = "disabled"; |
| @@ -300,7 +373,7 @@ · 2 unmodified lines | ||
| 300 | 373 | uart6: serial@48068000 { |
| 301 | 374 | compatible = "ti,omap4-uart"; |
| 302 | 375 | reg = <0x48068000 0x100>; |
| 303 | − interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; | |
| 376 | + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
| 304 | 377 | ti,hwmods = "uart6"; |
| 305 | 378 | clock-frequency = <48000000>; |
| 306 | 379 | status = "disabled"; |
| @@ -309,6 +382,7 @@ · 2 unmodified lines | ||
| 309 | 382 | uart7: serial@48420000 { |
| 310 | 383 | compatible = "ti,omap4-uart"; |
| 311 | 384 | reg = <0x48420000 0x100>; |
| 385 | + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; | |
| 312 | 386 | ti,hwmods = "uart7"; |
| 313 | 387 | clock-frequency = <48000000>; |
| 314 | 388 | status = "disabled"; |
| @@ -317,6 +391,7 @@ · 2 unmodified lines | ||
| 317 | 391 | uart8: serial@48422000 { |
| 318 | 392 | compatible = "ti,omap4-uart"; |
| 319 | 393 | reg = <0x48422000 0x100>; |
| 394 | + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; | |
| 320 | 395 | ti,hwmods = "uart8"; |
| 321 | 396 | clock-frequency = <48000000>; |
| 322 | 397 | status = "disabled"; |
| @@ -325,6 +400,7 @@ · 2 unmodified lines | ||
| 325 | 400 | uart9: serial@48424000 { |
| 326 | 401 | compatible = "ti,omap4-uart"; |
| 327 | 402 | reg = <0x48424000 0x100>; |
| 403 | + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; | |
| 328 | 404 | ti,hwmods = "uart9"; |
| 329 | 405 | clock-frequency = <48000000>; |
| 330 | 406 | status = "disabled"; |
| @@ -333,15 +409,133 @@ · 2 unmodified lines | ||
| 333 | 409 | uart10: serial@4ae2b000 { |
| 334 | 410 | compatible = "ti,omap4-uart"; |
| 335 | 411 | reg = <0x4ae2b000 0x100>; |
| 412 | + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; | |
| 336 | 413 | ti,hwmods = "uart10"; |
| 337 | 414 | clock-frequency = <48000000>; |
| 338 | 415 | status = "disabled"; |
| 339 | 416 | }; |
| 340 | 417 | |
| 418 | + mailbox1: mailbox@4a0f4000 { | |
| 419 | + compatible = "ti,omap4-mailbox"; | |
| 420 | + reg = <0x4a0f4000 0x200>; | |
| 421 | + ti,hwmods = "mailbox1"; | |
| 422 | + ti,mbox-num-users = <3>; | |
| 423 | + ti,mbox-num-fifos = <8>; | |
| 424 | + status = "disabled"; | |
| 425 | + }; | |
| 426 | + | |
| 427 | + mailbox2: mailbox@4883a000 { | |
| 428 | + compatible = "ti,omap4-mailbox"; | |
| 429 | + reg = <0x4883a000 0x200>; | |
| 430 | + ti,hwmods = "mailbox2"; | |
| 431 | + ti,mbox-num-users = <4>; | |
| 432 | + ti,mbox-num-fifos = <12>; | |
| 433 | + status = "disabled"; | |
| 434 | + }; | |
| 435 | + | |
| 436 | + mailbox3: mailbox@4883c000 { | |
| 437 | + compatible = "ti,omap4-mailbox"; | |
| 438 | + reg = <0x4883c000 0x200>; | |
| 439 | + ti,hwmods = "mailbox3"; | |
| 440 | + ti,mbox-num-users = <4>; | |
| 441 | + ti,mbox-num-fifos = <12>; | |
| 442 | + status = "disabled"; | |
| 443 | + }; | |
| 444 | + | |
| 445 | + mailbox4: mailbox@4883e000 { | |
| 446 | + compatible = "ti,omap4-mailbox"; | |
| 447 | + reg = <0x4883e000 0x200>; | |
| 448 | + ti,hwmods = "mailbox4"; | |
| 449 | + ti,mbox-num-users = <4>; | |
| 450 | + ti,mbox-num-fifos = <12>; | |
| 451 | + status = "disabled"; | |
| 452 | + }; | |
| 453 | + | |
| 454 | + mailbox5: mailbox@48840000 { | |
| 455 | + compatible = "ti,omap4-mailbox"; | |
| 456 | + reg = <0x48840000 0x200>; | |
| 457 | + ti,hwmods = "mailbox5"; | |
| 458 | + ti,mbox-num-users = <4>; | |
| 459 | + ti,mbox-num-fifos = <12>; | |
| 460 | + status = "disabled"; | |
| 461 | + }; | |
| 462 | + | |
| 463 | + mailbox6: mailbox@48842000 { | |
| 464 | + compatible = "ti,omap4-mailbox"; | |
| 465 | + reg = <0x48842000 0x200>; | |
| 466 | + ti,hwmods = "mailbox6"; | |
| 467 | + ti,mbox-num-users = <4>; | |
| 468 | + ti,mbox-num-fifos = <12>; | |
| 469 | + status = "disabled"; | |
| 470 | + }; | |
| 471 | + | |
| 472 | + mailbox7: mailbox@48844000 { | |
| 473 | + compatible = "ti,omap4-mailbox"; | |
| 474 | + reg = <0x48844000 0x200>; | |
| 475 | + ti,hwmods = "mailbox7"; | |
| 476 | + ti,mbox-num-users = <4>; | |
| 477 | + ti,mbox-num-fifos = <12>; | |
| 478 | + status = "disabled"; | |
| 479 | + }; | |
| 480 | + | |
| 481 | + mailbox8: mailbox@48846000 { | |
| 482 | + compatible = "ti,omap4-mailbox"; | |
| 483 | + reg = <0x48846000 0x200>; | |
| 484 | + ti,hwmods = "mailbox8"; | |
| 485 | + ti,mbox-num-users = <4>; | |
| 486 | + ti,mbox-num-fifos = <12>; | |
| 487 | + status = "disabled"; | |
| 488 | + }; | |
| 489 | + | |
| 490 | + mailbox9: mailbox@4885e000 { | |
| 491 | + compatible = "ti,omap4-mailbox"; | |
| 492 | + reg = <0x4885e000 0x200>; | |
| 493 | + ti,hwmods = "mailbox9"; | |
| 494 | + ti,mbox-num-users = <4>; | |
| 495 | + ti,mbox-num-fifos = <12>; | |
| 496 | + status = "disabled"; | |
| 497 | + }; | |
| 498 | + | |
| 499 | + mailbox10: mailbox@48860000 { | |
| 500 | + compatible = "ti,omap4-mailbox"; | |
| 501 | + reg = <0x48860000 0x200>; | |
| 502 | + ti,hwmods = "mailbox10"; | |
| 503 | + ti,mbox-num-users = <4>; | |
| 504 | + ti,mbox-num-fifos = <12>; | |
| 505 | + status = "disabled"; | |
| 506 | + }; | |
| 507 | + | |
| 508 | + mailbox11: mailbox@48862000 { | |
| 509 | + compatible = "ti,omap4-mailbox"; | |
| 510 | + reg = <0x48862000 0x200>; | |
| 511 | + ti,hwmods = "mailbox11"; | |
| 512 | + ti,mbox-num-users = <4>; | |
| 513 | + ti,mbox-num-fifos = <12>; | |
| 514 | + status = "disabled"; | |
| 515 | + }; | |
| 516 | + | |
| 517 | + mailbox12: mailbox@48864000 { | |
| 518 | + compatible = "ti,omap4-mailbox"; | |
| 519 | + reg = <0x48864000 0x200>; | |
| 520 | + ti,hwmods = "mailbox12"; | |
| 521 | + ti,mbox-num-users = <4>; | |
| 522 | + ti,mbox-num-fifos = <12>; | |
| 523 | + status = "disabled"; | |
| 524 | + }; | |
| 525 | + | |
| 526 | + mailbox13: mailbox@48802000 { | |
| 527 | + compatible = "ti,omap4-mailbox"; | |
| 528 | + reg = <0x48802000 0x200>; | |
| 529 | + ti,hwmods = "mailbox13"; | |
| 530 | + ti,mbox-num-users = <4>; | |
| 531 | + ti,mbox-num-fifos = <12>; | |
| 532 | + status = "disabled"; | |
| 533 | + }; | |
| 534 | + | |
| 341 | 535 | timer1: timer@4ae18000 { |
| 342 | 536 | compatible = "ti,omap5430-timer"; |
| 343 | 537 | reg = <0x4ae18000 0x80>; |
| 344 | − interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| 538 | + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
| 345 | 539 | ti,hwmods = "timer1"; |
| 346 | 540 | ti,timer-alwon; |
| 347 | 541 | }; |
| @@ -349,28 +543,28 @@ · 1 unmodified line | ||
| 349 | 543 | timer2: timer@48032000 { |
| 350 | 544 | compatible = "ti,omap5430-timer"; |
| 351 | 545 | reg = <0x48032000 0x80>; |
| 352 | − interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
| 546 | + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
| 353 | 547 | ti,hwmods = "timer2"; |
| 354 | 548 | }; |
| 355 | 549 | |
| 356 | 550 | timer3: timer@48034000 { |
| 357 | 551 | compatible = "ti,omap5430-timer"; |
| 358 | 552 | reg = <0x48034000 0x80>; |
| 359 | − interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
| 553 | + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
| 360 | 554 | ti,hwmods = "timer3"; |
| 361 | 555 | }; |
| 362 | 556 | |
| 363 | 557 | timer4: timer@48036000 { |
| 364 | 558 | compatible = "ti,omap5430-timer"; |
| 365 | 559 | reg = <0x48036000 0x80>; |
| 366 | − interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
| 560 | + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
| 367 | 561 | ti,hwmods = "timer4"; |
| 368 | 562 | }; |
| 369 | 563 | |
| 370 | 564 | timer5: timer@48820000 { |
| 371 | 565 | compatible = "ti,omap5430-timer"; |
| 372 | 566 | reg = <0x48820000 0x80>; |
| 373 | − interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
| 567 | + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 374 | 568 | ti,hwmods = "timer5"; |
| 375 | 569 | ti,timer-dsp; |
| 376 | 570 | }; |
| @@ -378,7 +572,7 @@ · 1 unmodified line | ||
| 378 | 572 | timer6: timer@48822000 { |
| 379 | 573 | compatible = "ti,omap5430-timer"; |
| 380 | 574 | reg = <0x48822000 0x80>; |
| 381 | − interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
| 575 | + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| 382 | 576 | ti,hwmods = "timer6"; |
| 383 | 577 | ti,timer-dsp; |
| 384 | 578 | ti,timer-pwm; |
| @@ -387,7 +581,7 @@ · 2 unmodified lines | ||
| 387 | 581 | timer7: timer@48824000 { |
| 388 | 582 | compatible = "ti,omap5430-timer"; |
| 389 | 583 | reg = <0x48824000 0x80>; |
| 390 | − interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
| 584 | + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
| 391 | 585 | ti,hwmods = "timer7"; |
| 392 | 586 | ti,timer-dsp; |
| 393 | 587 | }; |
| @@ -395,7 +589,7 @@ · 1 unmodified line | ||
| 395 | 589 | timer8: timer@48826000 { |
| 396 | 590 | compatible = "ti,omap5430-timer"; |
| 397 | 591 | reg = <0x48826000 0x80>; |
| 398 | − interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; | |
| 592 | + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
| 399 | 593 | ti,hwmods = "timer8"; |
| 400 | 594 | ti,timer-dsp; |
| 401 | 595 | ti,timer-pwm; |
| @@ -404,21 +598,21 @@ · 2 unmodified lines | ||
| 404 | 598 | timer9: timer@4803e000 { |
| 405 | 599 | compatible = "ti,omap5430-timer"; |
| 406 | 600 | reg = <0x4803e000 0x80>; |
| 407 | − interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
| 601 | + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
| 408 | 602 | ti,hwmods = "timer9"; |
| 409 | 603 | }; |
| 410 | 604 | |
| 411 | 605 | timer10: timer@48086000 { |
| 412 | 606 | compatible = "ti,omap5430-timer"; |
| 413 | 607 | reg = <0x48086000 0x80>; |
| 414 | − interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
| 608 | + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
| 415 | 609 | ti,hwmods = "timer10"; |
| 416 | 610 | }; |
| 417 | 611 | |
| 418 | 612 | timer11: timer@48088000 { |
| 419 | 613 | compatible = "ti,omap5430-timer"; |
| 420 | 614 | reg = <0x48088000 0x80>; |
| 421 | − interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; | |
| 615 | + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
| 422 | 616 | ti,hwmods = "timer11"; |
| 423 | 617 | ti,timer-pwm; |
| 424 | 618 | }; |
| @@ -426,6 +620,7 @@ · 1 unmodified line | ||
| 426 | 620 | timer13: timer@48828000 { |
| 427 | 621 | compatible = "ti,omap5430-timer"; |
| 428 | 622 | reg = <0x48828000 0x80>; |
| 623 | + interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; | |
| 429 | 624 | ti,hwmods = "timer13"; |
| 430 | 625 | status = "disabled"; |
| 431 | 626 | }; |
| @@ -433,6 +628,7 @@ · 1 unmodified line | ||
| 433 | 628 | timer14: timer@4882a000 { |
| 434 | 629 | compatible = "ti,omap5430-timer"; |
| 435 | 630 | reg = <0x4882a000 0x80>; |
| 631 | + interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; | |
| 436 | 632 | ti,hwmods = "timer14"; |
| 437 | 633 | status = "disabled"; |
| 438 | 634 | }; |
| @@ -440,6 +636,7 @@ · 1 unmodified line | ||
| 440 | 636 | timer15: timer@4882c000 { |
| 441 | 637 | compatible = "ti,omap5430-timer"; |
| 442 | 638 | reg = <0x4882c000 0x80>; |
| 639 | + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; | |
| 443 | 640 | ti,hwmods = "timer15"; |
| 444 | 641 | status = "disabled"; |
| 445 | 642 | }; |
| @@ -447,6 +644,7 @@ · 1 unmodified line | ||
| 447 | 644 | timer16: timer@4882e000 { |
| 448 | 645 | compatible = "ti,omap5430-timer"; |
| 449 | 646 | reg = <0x4882e000 0x80>; |
| 647 | + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; | |
| 450 | 648 | ti,hwmods = "timer16"; |
| 451 | 649 | status = "disabled"; |
| 452 | 650 | }; |
| @@ -454,7 +652,7 @@ · 1 unmodified line | ||
| 454 | 652 | wdt2: wdt@4ae14000 { |
| 455 | 653 | compatible = "ti,omap4-wdt"; |
| 456 | 654 | reg = <0x4ae14000 0x80>; |
| 457 | − interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
| 655 | + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 458 | 656 | ti,hwmods = "wd_timer2"; |
| 459 | 657 | }; |
| 460 | 658 | |
| @@ -468,14 +666,14 @@ · 7 unmodified lines | ||
| 468 | 666 | dmm@4e000000 { |
| 469 | 667 | compatible = "ti,omap5-dmm"; |
| 470 | 668 | reg = <0x4e000000 0x800>; |
| 471 | − interrupts = <0 113 0x4>; | |
| 669 | + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 472 | 670 | ti,hwmods = "dmm"; |
| 473 | 671 | }; |
| 474 | 672 | |
| 475 | 673 | i2c1: i2c@48070000 { |
| 476 | 674 | compatible = "ti,omap4-i2c"; |
| 477 | 675 | reg = <0x48070000 0x100>; |
| 478 | − interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
| 676 | + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
| 479 | 677 | #address-cells = <1>; |
| 480 | 678 | #size-cells = <0>; |
| 481 | 679 | ti,hwmods = "i2c1"; |
| @@ -485,7 +683,7 @@ · 3 unmodified lines | ||
| 485 | 683 | i2c2: i2c@48072000 { |
| 486 | 684 | compatible = "ti,omap4-i2c"; |
| 487 | 685 | reg = <0x48072000 0x100>; |
| 488 | − interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
| 686 | + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
| 489 | 687 | #address-cells = <1>; |
| 490 | 688 | #size-cells = <0>; |
| 491 | 689 | ti,hwmods = "i2c2"; |
| @@ -495,7 +693,7 @@ · 3 unmodified lines | ||
| 495 | 693 | i2c3: i2c@48060000 { |
| 496 | 694 | compatible = "ti,omap4-i2c"; |
| 497 | 695 | reg = <0x48060000 0x100>; |
| 498 | − interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
| 696 | + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
| 499 | 697 | #address-cells = <1>; |
| 500 | 698 | #size-cells = <0>; |
| 501 | 699 | ti,hwmods = "i2c3"; |
| @@ -505,7 +703,7 @@ · 3 unmodified lines | ||
| 505 | 703 | i2c4: i2c@4807a000 { |
| 506 | 704 | compatible = "ti,omap4-i2c"; |
| 507 | 705 | reg = <0x4807a000 0x100>; |
| 508 | − interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
| 706 | + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
| 509 | 707 | #address-cells = <1>; |
| 510 | 708 | #size-cells = <0>; |
| 511 | 709 | ti,hwmods = "i2c4"; |
| @@ -515,7 +713,7 @@ · 3 unmodified lines | ||
| 515 | 713 | i2c5: i2c@4807c000 { |
| 516 | 714 | compatible = "ti,omap4-i2c"; |
| 517 | 715 | reg = <0x4807c000 0x100>; |
| 518 | − interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
| 716 | + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
| 519 | 717 | #address-cells = <1>; |
| 520 | 718 | #size-cells = <0>; |
| 521 | 719 | ti,hwmods = "i2c5"; |
| @@ -525,7 +723,7 @@ · 3 unmodified lines | ||
| 525 | 723 | mmc1: mmc@4809c000 { |
| 526 | 724 | compatible = "ti,omap4-hsmmc"; |
| 527 | 725 | reg = <0x4809c000 0x400>; |
| 528 | − interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
| 726 | + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
| 529 | 727 | ti,hwmods = "mmc1"; |
| 530 | 728 | ti,dual-volt; |
| 531 | 729 | ti,needs-special-reset; |
| @@ -538,7 +736,7 @@ · 6 unmodified lines | ||
| 538 | 736 | mmc2: mmc@480b4000 { |
| 539 | 737 | compatible = "ti,omap4-hsmmc"; |
| 540 | 738 | reg = <0x480b4000 0x400>; |
| 541 | − interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
| 739 | + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
| 542 | 740 | ti,hwmods = "mmc2"; |
| 543 | 741 | ti,needs-special-reset; |
| 544 | 742 | dmas = <&sdma 47>, <&sdma 48>; |
| @@ -549,7 +747,7 @@ · 4 unmodified lines | ||
| 549 | 747 | mmc3: mmc@480ad000 { |
| 550 | 748 | compatible = "ti,omap4-hsmmc"; |
| 551 | 749 | reg = <0x480ad000 0x400>; |
| 552 | − interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
| 750 | + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
| 553 | 751 | ti,hwmods = "mmc3"; |
| 554 | 752 | ti,needs-special-reset; |
| 555 | 753 | dmas = <&sdma 77>, <&sdma 78>; |
| @@ -560,7 +758,7 @@ · 4 unmodified lines | ||
| 560 | 758 | mmc4: mmc@480d1000 { |
| 561 | 759 | compatible = "ti,omap4-hsmmc"; |
| 562 | 760 | reg = <0x480d1000 0x400>; |
| 563 | − interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
| 761 | + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
| 564 | 762 | ti,hwmods = "mmc4"; |
| 565 | 763 | ti,needs-special-reset; |
| 566 | 764 | dmas = <&sdma 57>, <&sdma 58>; |
| @@ -703,7 +901,7 @@ · 136 unmodified lines | ||
| 703 | 901 | mcspi1: spi@48098000 { |
| 704 | 902 | compatible = "ti,omap4-mcspi"; |
| 705 | 903 | reg = <0x48098000 0x200>; |
| 706 | − interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
| 904 | + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
| 707 | 905 | #address-cells = <1>; |
| 708 | 906 | #size-cells = <0>; |
| 709 | 907 | ti,hwmods = "mcspi1"; |
| @@ -724,7 +922,7 @@ · 14 unmodified lines | ||
| 724 | 922 | mcspi2: spi@4809a000 { |
| 725 | 923 | compatible = "ti,omap4-mcspi"; |
| 726 | 924 | reg = <0x4809a000 0x200>; |
| 727 | − interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | |
| 925 | + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
| 728 | 926 | #address-cells = <1>; |
| 729 | 927 | #size-cells = <0>; |
| 730 | 928 | ti,hwmods = "mcspi2"; |
| @@ -740,7 +938,7 @@ · 9 unmodified lines | ||
| 740 | 938 | mcspi3: spi@480b8000 { |
| 741 | 939 | compatible = "ti,omap4-mcspi"; |
| 742 | 940 | reg = <0x480b8000 0x200>; |
| 743 | − interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
| 941 | + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
| 744 | 942 | #address-cells = <1>; |
| 745 | 943 | #size-cells = <0>; |
| 746 | 944 | ti,hwmods = "mcspi3"; |
| @@ -753,7 +951,7 @@ · 6 unmodified lines | ||
| 753 | 951 | mcspi4: spi@480ba000 { |
| 754 | 952 | compatible = "ti,omap4-mcspi"; |
| 755 | 953 | reg = <0x480ba000 0x200>; |
| 756 | − interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | |
| 954 | + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
| 757 | 955 | #address-cells = <1>; |
| 758 | 956 | #size-cells = <0>; |
| 759 | 957 | ti,hwmods = "mcspi4"; |
| @@ -773,6 +971,7 @@ · 13 unmodified lines | ||
| 773 | 971 | clocks = <&qspi_gfclk_div>; |
| 774 | 972 | clock-names = "fck"; |
| 775 | 973 | num-cs = <4>; |
| 974 | + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; | |
| 776 | 975 | status = "disabled"; |
| 777 | 976 | }; |
| 778 | 977 | |
| @@ -803,18 +1002,76 @@ · 24 unmodified lines | ||
| 803 | 1002 | clock-names = "sysclk"; |
| 804 | 1003 | #phy-cells = <0>; |
| 805 | 1004 | }; |
| 1005 | + | |
| 1006 | + pcie1_phy: pciephy@4a094000 { | |
| 1007 | + compatible = "ti,phy-pipe3-pcie"; | |
| 1008 | + reg = <0x4a094000 0x80>, /* phy_rx */ | |
| 1009 | + <0x4a094400 0x64>; /* phy_tx */ | |
| 1010 | + reg-names = "phy_rx", "phy_tx"; | |
| 1011 | + ctrl-module = <&omap_control_pcie1phy>; | |
| 1012 | + clocks = <&dpll_pcie_ref_ck>, | |
| 1013 | + <&dpll_pcie_ref_m2ldo_ck>, | |
| 1014 | + <&optfclk_pciephy1_32khz>, | |
| 1015 | + <&optfclk_pciephy1_clk>, | |
| 1016 | + <&optfclk_pciephy1_div_clk>, | |
| 1017 | + <&optfclk_pciephy_div>; | |
| 1018 | + clock-names = "dpll_ref", "dpll_ref_m2", | |
| 1019 | + "wkupclk", "refclk", | |
| 1020 | + "div-clk", "phy-div"; | |
| 1021 | + #phy-cells = <0>; | |
| 1022 | + id = <1>; | |
| 1023 | + ti,hwmods = "pcie1-phy"; | |
| 1024 | + }; | |
| 1025 | + | |
| 1026 | + pcie2_phy: pciephy@4a095000 { | |
| 1027 | + compatible = "ti,phy-pipe3-pcie"; | |
| 1028 | + reg = <0x4a095000 0x80>, /* phy_rx */ | |
| 1029 | + <0x4a095400 0x64>; /* phy_tx */ | |
| 1030 | + reg-names = "phy_rx", "phy_tx"; | |
| 1031 | + ctrl-module = <&omap_control_pcie2phy>; | |
| 1032 | + clocks = <&dpll_pcie_ref_ck>, | |
| 1033 | + <&dpll_pcie_ref_m2ldo_ck>, | |
| 1034 | + <&optfclk_pciephy2_32khz>, | |
| 1035 | + <&optfclk_pciephy2_clk>, | |
| 1036 | + <&optfclk_pciephy2_div_clk>, | |
| 1037 | + <&optfclk_pciephy_div>; | |
| 1038 | + clock-names = "dpll_ref", "dpll_ref_m2", | |
| 1039 | + "wkupclk", "refclk", | |
| 1040 | + "div-clk", "phy-div"; | |
| 1041 | + #phy-cells = <0>; | |
| 1042 | + ti,hwmods = "pcie2-phy"; | |
| 1043 | + id = <2>; | |
| 1044 | + status = "disabled"; | |
| 1045 | + }; | |
| 806 | 1046 | }; |
| 807 | 1047 | |
| 808 | 1048 | sata: sata@4a141100 { |
| 809 | 1049 | compatible = "snps,dwc-ahci"; |
| 810 | 1050 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
| 811 | − interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
| 1051 | + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | |
| 812 | 1052 | phys = <&sata_phy>; |
| 813 | 1053 | phy-names = "sata-phy"; |
| 814 | 1054 | clocks = <&sata_ref_clk>; |
| 815 | 1055 | ti,hwmods = "sata"; |
| 816 | 1056 | }; |
| 817 | 1057 | |
| 1058 | + omap_control_pcie1phy: control-phy@0x4a003c40 { | |
| 1059 | + compatible = "ti,control-phy-pcie"; | |
| 1060 | + reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; | |
| 1061 | + reg-names = "power", "control_sma", "pcie_pcs"; | |
| 1062 | + clocks = <&sys_clkin1>; | |
| 1063 | + clock-names = "sysclk"; | |
| 1064 | + }; | |
| 1065 | + | |
| 1066 | + omap_control_pcie2phy: control-pcie@0x4a003c44 { | |
| 1067 | + compatible = "ti,control-phy-pcie"; | |
| 1068 | + reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; | |
| 1069 | + reg-names = "power", "control_sma", "pcie_pcs"; | |
| 1070 | + clocks = <&sys_clkin1>; | |
| 1071 | + clock-names = "sysclk"; | |
| 1072 | + status = "disabled"; | |
| 1073 | + }; | |
| 1074 | + | |
| 818 | 1075 | omap_control_usb2phy1: control-phy@4a002300 { |
| 819 | 1076 | compatible = "ti,control-phy-usb2"; |
| 820 | 1077 | reg = <0x4a002300 0x4>; |
| @@ -885,7 +1142,7 @@ · 64 unmodified lines | ||
| 885 | 1142 | compatible = "ti,dwc3"; |
| 886 | 1143 | ti,hwmods = "usb_otg_ss1"; |
| 887 | 1144 | reg = <0x48880000 0x10000>; |
| 888 | − interrupts = <0 77 4>; | |
| 1145 | + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
| 889 | 1146 | #address-cells = <1>; |
| 890 | 1147 | #size-cells = <1>; |
| 891 | 1148 | utmi-mode = <2>; |
| @@ -893,7 +1150,7 @@ · 1 unmodified line | ||
| 893 | 1150 | usb1: usb@48890000 { |
| 894 | 1151 | compatible = "snps,dwc3"; |
| 895 | 1152 | reg = <0x48890000 0x17000>; |
| 896 | − interrupts = <0 76 4>; | |
| 1153 | + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
| 897 | 1154 | phys = <&usb2_phy1>, <&usb3_phy1>; |
| 898 | 1155 | phy-names = "usb2-phy", "usb3-phy"; |
| 899 | 1156 | tx-fifo-resize; |
| @@ -906,7 +1163,7 @@ · 6 unmodified lines | ||
| 906 | 1163 | compatible = "ti,dwc3"; |
| 907 | 1164 | ti,hwmods = "usb_otg_ss2"; |
| 908 | 1165 | reg = <0x488c0000 0x10000>; |
| 909 | − interrupts = <0 92 4>; | |
| 1166 | + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
| 910 | 1167 | #address-cells = <1>; |
| 911 | 1168 | #size-cells = <1>; |
| 912 | 1169 | utmi-mode = <2>; |
| @@ -914,7 +1171,7 @@ · 1 unmodified line | ||
| 914 | 1171 | usb2: usb@488d0000 { |
| 915 | 1172 | compatible = "snps,dwc3"; |
| 916 | 1173 | reg = <0x488d0000 0x17000>; |
| 917 | − interrupts = <0 78 4>; | |
| 1174 | + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
| 918 | 1175 | phys = <&usb2_phy2>; |
| 919 | 1176 | phy-names = "usb2-phy"; |
| 920 | 1177 | tx-fifo-resize; |
| @@ -928,7 +1185,7 @@ · 7 unmodified lines | ||
| 928 | 1185 | compatible = "ti,dwc3"; |
| 929 | 1186 | ti,hwmods = "usb_otg_ss3"; |
| 930 | 1187 | reg = <0x48900000 0x10000>; |
| 931 | − /* interrupts = <0 TBD 4>; */ | |
| 1188 | + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; | |
| 932 | 1189 | #address-cells = <1>; |
| 933 | 1190 | #size-cells = <1>; |
| 934 | 1191 | utmi-mode = <2>; |
| @@ -937,7 +1194,7 @@ · 2 unmodified lines | ||
| 937 | 1194 | usb3: usb@48910000 { |
| 938 | 1195 | compatible = "snps,dwc3"; |
| 939 | 1196 | reg = <0x48910000 0x17000>; |
| 940 | − /* interrupts = <0 93 4>; */ | |
| 1197 | + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
| 941 | 1198 | tx-fifo-resize; |
| 942 | 1199 | maximum-speed = "high-speed"; |
| 943 | 1200 | dr_mode = "otg"; |
| @@ -948,7 +1205,7 @@ · 4 unmodified lines | ||
| 948 | 1205 | compatible = "ti,dwc3"; |
| 949 | 1206 | ti,hwmods = "usb_otg_ss4"; |
| 950 | 1207 | reg = <0x48940000 0x10000>; |
| 951 | − /* interrupts = <0 TBD 4>; */ | |
| 1208 | + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; | |
| 952 | 1209 | #address-cells = <1>; |
| 953 | 1210 | #size-cells = <1>; |
| 954 | 1211 | utmi-mode = <2>; |
| @@ -957,7 +1214,7 @@ · 2 unmodified lines | ||
| 957 | 1214 | usb4: usb@48950000 { |
| 958 | 1215 | compatible = "snps,dwc3"; |
| 959 | 1216 | reg = <0x48950000 0x17000>; |
| 960 | − /* interrupts = <0 TBD 4>; */ | |
| 1217 | + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; | |
| 961 | 1218 | tx-fifo-resize; |
| 962 | 1219 | maximum-speed = "high-speed"; |
| 963 | 1220 | dr_mode = "otg"; |
| @@ -967,7 +1224,7 @@ · 3 unmodified lines | ||
| 967 | 1224 | elm: elm@48078000 { |
| 968 | 1225 | compatible = "ti,am3352-elm"; |
| 969 | 1226 | reg = <0x48078000 0xfc0>; /* device IO registers */ |
| 970 | − interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
| 1227 | + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
| 971 | 1228 | ti,hwmods = "elm"; |
| 972 | 1229 | status = "disabled"; |
| 973 | 1230 | }; |
| @@ -976,7 +1233,7 @@ · 2 unmodified lines | ||
| 976 | 1233 | compatible = "ti,am3352-gpmc"; |
| 977 | 1234 | ti,hwmods = "gpmc"; |
| 978 | 1235 | reg = <0x50000000 0x37c>; /* device IO registers */ |
| 979 | − interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
| 1236 | + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
| 980 | 1237 | gpmc,num-cs = <8>; |
| 981 | 1238 | gpmc,num-waitpins = <2>; |
| 982 | 1239 | #address-cells = <2>; |
| @@ -994,6 +1251,17 @@ · 11 unmodified lines | ||
| 994 | 1251 | clock-names = "fck"; |
| 995 | 1252 | status = "disabled"; |
| 996 | 1253 | }; |
| 1254 | + | |
| 1255 | + crossbar_mpu: crossbar@4a020000 { | |
| 1256 | + compatible = "ti,irq-crossbar"; | |
| 1257 | + reg = <0x4a002a48 0x130>; | |
| 1258 | + ti,max-irqs = <160>; | |
| 1259 | + ti,max-crossbar-sources = <MAX_SOURCES>; | |
| 1260 | + ti,reg-size = <2>; | |
| 1261 | + ti,irqs-reserved = <0 1 2 3 5 6 131 132>; | |
| 1262 | + ti,irqs-skip = <10 133 139 140>; | |
| 1263 | + ti,irqs-safe-map = <0>; | |
| 1264 | + }; | |
| 997 | 1265 | }; |
| 998 | 1266 | }; |
| 999 | 1267 | |
| @@ -1154,7 +1154,7 @@ · 1153 unmodified lines | ||
| 1154 | 1154 | |
| 1155 | 1155 | apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { |
| 1156 | 1156 | compatible = "ti,mux-clock"; |
| 1157 | − clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; | |
| 1157 | + clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; | |
| 1158 | 1158 | #clock-cells = <0>; |
| 1159 | 1159 | reg = <0x021c 0x4>; |
| 1160 | 1160 | ti,bit-shift = <7>; |
| @@ -1167,16 +1167,33 @@ · 6 unmodified lines | ||
| 1167 | 1167 | reg = <0x021c>, <0x0220>; |
| 1168 | 1168 | }; |
| 1169 | 1169 | |
| 1170 | + optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 { | |
| 1171 | + compatible = "ti,gate-clock"; | |
| 1172 | + clocks = <&sys_32k_ck>; | |
| 1173 | + #clock-cells = <0>; | |
| 1174 | + reg = <0x13b0>; | |
| 1175 | + ti,bit-shift = <8>; | |
| 1176 | + }; | |
| 1177 | + | |
| 1178 | + optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 { | |
| 1179 | + compatible = "ti,gate-clock"; | |
| 1180 | + clocks = <&sys_32k_ck>; | |
| 1181 | + #clock-cells = <0>; | |
| 1182 | + reg = <0x13b8>; | |
| 1183 | + ti,bit-shift = <8>; | |
| 1184 | + }; | |
| 1185 | + | |
| 1170 | 1186 | optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { |
| 1171 | 1187 | compatible = "ti,divider-clock"; |
| 1172 | 1188 | clocks = <&apll_pcie_ck>; |
| 1173 | 1189 | #clock-cells = <0>; |
| 1174 | 1190 | reg = <0x021c>; |
| 1191 | + ti,dividers = <2>, <1>; | |
| 1175 | 1192 | ti,bit-shift = <8>; |
| 1176 | 1193 | ti,max-div = <2>; |
| 1177 | 1194 | }; |
| 1178 | 1195 | |
| 1179 | − optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { | |
| 1196 | + optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 { | |
| 1180 | 1197 | compatible = "ti,gate-clock"; |
| 1181 | 1198 | clocks = <&apll_pcie_ck>; |
| 1182 | 1199 | #clock-cells = <0>; |
| @@ -1184,7 +1201,15 @@ · 1 unmodified line | ||
| 1184 | 1201 | ti,bit-shift = <9>; |
| 1185 | 1202 | }; |
| 1186 | 1203 | |
| 1187 | − optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { | |
| 1204 | + optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 { | |
| 1205 | + compatible = "ti,gate-clock"; | |
| 1206 | + clocks = <&apll_pcie_ck>; | |
| 1207 | + #clock-cells = <0>; | |
| 1208 | + reg = <0x13b8>; | |
| 1209 | + ti,bit-shift = <9>; | |
| 1210 | + }; | |
| 1211 | + | |
| 1212 | + optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 { | |
| 1188 | 1213 | compatible = "ti,gate-clock"; |
| 1189 | 1214 | clocks = <&optfclk_pciephy_div>; |
| 1190 | 1215 | #clock-cells = <0>; |
| @@ -1192,6 +1217,14 @@ · 1 unmodified line | ||
| 1192 | 1217 | ti,bit-shift = <10>; |
| 1193 | 1218 | }; |
| 1194 | 1219 | |
| 1220 | + optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 { | |
| 1221 | + compatible = "ti,gate-clock"; | |
| 1222 | + clocks = <&optfclk_pciephy_div>; | |
| 1223 | + #clock-cells = <0>; | |
| 1224 | + reg = <0x13b8>; | |
| 1225 | + ti,bit-shift = <10>; | |
| 1226 | + }; | |
| 1227 | + | |
| 1195 | 1228 | apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { |
| 1196 | 1229 | #clock-cells = <0>; |
| 1197 | 1230 | compatible = "fixed-factor-clock"; |
| @@ -31,11 +31,13 @@ · 30 unmodified lines | ||
| 31 | 31 | device_type = "cpu"; |
| 32 | 32 | compatible = "arm,cortex-a9"; |
| 33 | 33 | reg = <0>; |
| 34 | + clock-frequency = <533000000>; | |
| 34 | 35 | }; |
| 35 | 36 | cpu@1 { |
| 36 | 37 | device_type = "cpu"; |
| 37 | 38 | compatible = "arm,cortex-a9"; |
| 38 | 39 | reg = <1>; |
| 40 | + clock-frequency = <533000000>; | |
| 39 | 41 | }; |
| 40 | 42 | }; |
| 41 | 43 | |
| @@ -20,6 +20,16 @@ · 19 unmodified lines | ||
| 20 | 20 | reg = <0x20000000 0x08000000>; |
| 21 | 21 | }; |
| 22 | 22 | |
| 23 | + clocks { | |
| 24 | + slow_xtal { | |
| 25 | + clock-frequency = <32768>; | |
| 26 | + }; | |
| 27 | + | |
| 28 | + main_xtal { | |
| 29 | + clock-frequency = <18432000>; | |
| 30 | + }; | |
| 31 | + }; | |
| 32 | + | |
| 23 | 33 | ahb { |
| 24 | 34 | apb { |
| 25 | 35 | dbgu: serial@fffff200 { |
| @@ -15,6 +15,12 @@ · 14 unmodified lines | ||
| 15 | 15 | model = "Telit EVK-PRO3 for Telit GE863-PRO3"; |
| 16 | 16 | compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9"; |
| 17 | 17 | |
| 18 | + clocks { | |
| 19 | + slow_xtal { | |
| 20 | + clock-frequency = <32768>; | |
| 21 | + }; | |
| 22 | + }; | |
| 23 | + | |
| 18 | 24 | ahb { |
| 19 | 25 | apb { |
| 20 | 26 | macb0: ethernet@fffc4000 { |
| @@ -170,6 +170,15 @@ · 169 unmodified lines | ||
| 170 | 170 | status = "disabled"; |
| 171 | 171 | }; |
| 172 | 172 | |
| 173 | + tmu: tmu@100C0000 { | |
| 174 | + compatible = "samsung,exynos3250-tmu"; | |
| 175 | + reg = <0x100C0000 0x100>; | |
| 176 | + interrupts = <0 216 0>; | |
| 177 | + clocks = <&cmu CLK_TMU_APBIF>; | |
| 178 | + clock-names = "tmu_apbif"; | |
| 179 | + status = "disabled"; | |
| 180 | + }; | |
| 181 | + | |
| 173 | 182 | gic: interrupt-controller@10481000 { |
| 174 | 183 | compatible = "arm,cortex-a15-gic"; |
| 175 | 184 | #interrupt-cells = <3>; |
| @@ -197,7 +206,6 @@ · 21 unmodified lines | ||
| 197 | 206 | |
| 198 | 207 | wakeup-interrupt-controller { |
| 199 | 208 | compatible = "samsung,exynos4210-wakeup-eint"; |
| 200 | − interrupt-parent = <&gic>; | |
| 201 | 209 | interrupts = <0 48 0>; |
| 202 | 210 | }; |
| 203 | 211 | }; |
| @@ -236,7 +244,6 @@ · 32 unmodified lines | ||
| 236 | 244 | compatible = "arm,amba-bus"; |
| 237 | 245 | #address-cells = <1>; |
| 238 | 246 | #size-cells = <1>; |
| 239 | − interrupt-parent = <&gic>; | |
| 240 | 247 | ranges; |
| 241 | 248 | |
| 242 | 249 | pdma0: pdma@12680000 { |
| @@ -280,6 +287,8 @@ · 37 unmodified lines | ||
| 280 | 287 | interrupts = <0 109 0>; |
| 281 | 288 | clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; |
| 282 | 289 | clock-names = "uart", "clk_uart_baud0"; |
| 290 | + pinctrl-names = "default"; | |
| 291 | + pinctrl-0 = <&uart0_data &uart0_fctl>; | |
| 283 | 292 | status = "disabled"; |
| 284 | 293 | }; |
| 285 | 294 | |
| @@ -289,6 +298,8 @@ · 3 unmodified lines | ||
| 289 | 298 | interrupts = <0 110 0>; |
| 290 | 299 | clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; |
| 291 | 300 | clock-names = "uart", "clk_uart_baud0"; |
| 301 | + pinctrl-names = "default"; | |
| 302 | + pinctrl-0 = <&uart1_data>; | |
| 292 | 303 | status = "disabled"; |
| 293 | 304 | }; |
| 294 | 305 | |
| @@ -428,6 +439,19 @@ · 133 unmodified lines | ||
| 428 | 439 | status = "disabled"; |
| 429 | 440 | }; |
| 430 | 441 | |
| 442 | + i2s2: i2s@13970000 { | |
| 443 | + compatible = "samsung,s3c6410-i2s"; | |
| 444 | + reg = <0x13970000 0x100>; | |
| 445 | + interrupts = <0 126 0>; | |
| 446 | + clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; | |
| 447 | + clock-names = "iis", "i2s_opclk0"; | |
| 448 | + dmas = <&pdma0 14>, <&pdma0 13>; | |
| 449 | + dma-names = "tx", "rx"; | |
| 450 | + pinctrl-0 = <&i2s2_bus>; | |
| 451 | + pinctrl-names = "default"; | |
| 452 | + status = "disabled"; | |
| 453 | + }; | |
| 454 | + | |
| 431 | 455 | pwm: pwm@139D0000 { |
| 432 | 456 | compatible = "samsung,exynos4210-pwm"; |
| 433 | 457 | reg = <0x139D0000 0x1000>; |
| @@ -127,6 +127,12 @@ · 126 unmodified lines | ||
| 127 | 127 | reg = <0x10440000 0x1000>; |
| 128 | 128 | }; |
| 129 | 129 | |
| 130 | + pmu { | |
| 131 | + compatible = "arm,cortex-a9-pmu"; | |
| 132 | + interrupt-parent = <&combiner>; | |
| 133 | + interrupts = <2 2>, <3 2>; | |
| 134 | + }; | |
| 135 | + | |
| 130 | 136 | sys_reg: syscon@10010000 { |
| 131 | 137 | compatible = "samsung,exynos4-sysreg", "syscon"; |
| 132 | 138 | reg = <0x10010000 0x400>; |
| @@ -326,6 +332,23 @@ · 193 unmodified lines | ||
| 326 | 332 | clocks = <&clock CLK_USB_HOST>; |
| 327 | 333 | clock-names = "usbhost"; |
| 328 | 334 | status = "disabled"; |
| 335 | + #address-cells = <1>; | |
| 336 | + #size-cells = <0>; | |
| 337 | + port@0 { | |
| 338 | + reg = <0>; | |
| 339 | + phys = <&exynos_usbphy 1>; | |
| 340 | + status = "disabled"; | |
| 341 | + }; | |
| 342 | + port@1 { | |
| 343 | + reg = <1>; | |
| 344 | + phys = <&exynos_usbphy 2>; | |
| 345 | + status = "disabled"; | |
| 346 | + }; | |
| 347 | + port@2 { | |
| 348 | + reg = <2>; | |
| 349 | + phys = <&exynos_usbphy 3>; | |
| 350 | + status = "disabled"; | |
| 351 | + }; | |
| 329 | 352 | }; |
| 330 | 353 | |
| 331 | 354 | ohci@12590000 { |
| @@ -335,6 +358,13 @@ · 3 unmodified lines | ||
| 335 | 358 | clocks = <&clock CLK_USB_HOST>; |
| 336 | 359 | clock-names = "usbhost"; |
| 337 | 360 | status = "disabled"; |
| 361 | + #address-cells = <1>; | |
| 362 | + #size-cells = <0>; | |
| 363 | + port@0 { | |
| 364 | + reg = <0>; | |
| 365 | + phys = <&exynos_usbphy 1>; | |
| 366 | + status = "disabled"; | |
| 367 | + }; | |
| 338 | 368 | }; |
| 339 | 369 | |
| 340 | 370 | i2s1: i2s@13960000 { |
| @@ -612,6 +642,7 @@ · 271 unmodified lines | ||
| 612 | 642 | clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; |
| 613 | 643 | clock-names = "sclk_fimd", "fimd"; |
| 614 | 644 | samsung,power-domain = <&pd_lcd0>; |
| 645 | + samsung,sysreg = <&sys_reg>; | |
| 615 | 646 | status = "disabled"; |
| 616 | 647 | }; |
| 617 | 648 | }; |
| @@ -103,12 +103,6 @@ · 102 unmodified lines | ||
| 103 | 103 | #clock-cells = <1>; |
| 104 | 104 | }; |
| 105 | 105 | |
| 106 | − pmu { | |
| 107 | − compatible = "arm,cortex-a9-pmu"; | |
| 108 | − interrupt-parent = <&combiner>; | |
| 109 | − interrupts = <2 2>, <3 2>; | |
| 110 | − }; | |
| 111 | − | |
| 112 | 106 | pinctrl_0: pinctrl@11400000 { |
| 113 | 107 | compatible = "samsung,exynos4210-pinctrl"; |
| 114 | 108 | reg = <0x11400000 0x1000>; |
| @@ -0,0 +1,384 @@ | ||
| 1 | +/* | |
| 2 | + * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards | |
| 3 | + * device tree source | |
| 4 | + * | |
| 5 | + * This program is free software; you can redistribute it and/or modify | |
| 6 | + * it under the terms of the GNU General Public License version 2 as | |
| 7 | + * published by the Free Software Foundation. | |
| 8 | +*/ | |
| 9 | + | |
| 10 | +#include <dt-bindings/input/input.h> | |
| 11 | +#include "exynos4412.dtsi" | |
| 12 | + | |
| 13 | +/ { | |
| 14 | + firmware@0204F000 { | |
| 15 | + compatible = "samsung,secure-firmware"; | |
| 16 | + reg = <0x0204F000 0x1000>; | |
| 17 | + }; | |
| 18 | + | |
| 19 | + gpio_keys { | |
| 20 | + compatible = "gpio-keys"; | |
| 21 | + pinctrl-names = "default"; | |
| 22 | + pinctrl-0 = <&gpio_power_key>; | |
| 23 | + | |
| 24 | + power_key { | |
| 25 | + interrupt-parent = <&gpx1>; | |
| 26 | + interrupts = <3 0>; | |
| 27 | + gpios = <&gpx1 3 1>; | |
| 28 | + linux,code = <KEY_POWER>; | |
| 29 | + label = "power key"; | |
| 30 | + debounce-interval = <10>; | |
| 31 | + gpio-key,wakeup; | |
| 32 | + }; | |
| 33 | + }; | |
| 34 | + | |
| 35 | + i2s0: i2s@03830000 { | |
| 36 | + pinctrl-0 = <&i2s0_bus>; | |
| 37 | + pinctrl-names = "default"; | |
| 38 | + status = "okay"; | |
| 39 | + clocks = <&clock_audss EXYNOS_I2S_BUS>, | |
| 40 | + <&clock_audss EXYNOS_DOUT_AUD_BUS>; | |
| 41 | + clock-names = "iis", "i2s_opclk0"; | |
| 42 | + }; | |
| 43 | + | |
| 44 | + sound: sound { | |
| 45 | + compatible = "samsung,odroidx2-audio"; | |
| 46 | + samsung,i2s-controller = <&i2s0>; | |
| 47 | + samsung,audio-codec = <&max98090>; | |
| 48 | + }; | |
| 49 | + | |
| 50 | + mmc@12550000 { | |
| 51 | + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; | |
| 52 | + pinctrl-names = "default"; | |
| 53 | + vmmc-supply = <&ldo20_reg &buck8_reg>; | |
| 54 | + status = "okay"; | |
| 55 | + | |
| 56 | + num-slots = <1>; | |
| 57 | + supports-highspeed; | |
| 58 | + broken-cd; | |
| 59 | + card-detect-delay = <200>; | |
| 60 | + samsung,dw-mshc-ciu-div = <3>; | |
| 61 | + samsung,dw-mshc-sdr-timing = <2 3>; | |
| 62 | + samsung,dw-mshc-ddr-timing = <1 2>; | |
| 63 | + | |
| 64 | + slot@0 { | |
| 65 | + reg = <0>; | |
| 66 | + bus-width = <8>; | |
| 67 | + }; | |
| 68 | + }; | |
| 69 | + | |
| 70 | + watchdog@10060000 { | |
| 71 | + status = "okay"; | |
| 72 | + }; | |
| 73 | + | |
| 74 | + rtc@10070000 { | |
| 75 | + status = "okay"; | |
| 76 | + }; | |
| 77 | + | |
| 78 | + g2d@10800000 { | |
| 79 | + status = "okay"; | |
| 80 | + }; | |
| 81 | + | |
| 82 | + camera { | |
| 83 | + status = "okay"; | |
| 84 | + pinctrl-names = "default"; | |
| 85 | + pinctrl-0 = <>; | |
| 86 | + | |
| 87 | + fimc_0: fimc@11800000 { | |
| 88 | + status = "okay"; | |
| 89 | + }; | |
| 90 | + | |
| 91 | + fimc_1: fimc@11810000 { | |
| 92 | + status = "okay"; | |
| 93 | + }; | |
| 94 | + | |
| 95 | + fimc_2: fimc@11820000 { | |
| 96 | + status = "okay"; | |
| 97 | + }; | |
| 98 | + | |
| 99 | + fimc_3: fimc@11830000 { | |
| 100 | + status = "okay"; | |
| 101 | + }; | |
| 102 | + }; | |
| 103 | + | |
| 104 | + sdhci@12530000 { | |
| 105 | + bus-width = <4>; | |
| 106 | + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; | |
| 107 | + pinctrl-names = "default"; | |
| 108 | + vmmc-supply = <&ldo4_reg &ldo21_reg>; | |
| 109 | + cd-gpios = <&gpk2 2 0>; | |
| 110 | + cd-inverted; | |
| 111 | + status = "okay"; | |
| 112 | + }; | |
| 113 | + | |
| 114 | + serial@13800000 { | |
| 115 | + status = "okay"; | |
| 116 | + }; | |
| 117 | + | |
| 118 | + serial@13810000 { | |
| 119 | + status = "okay"; | |
| 120 | + }; | |
| 121 | + | |
| 122 | + fixed-rate-clocks { | |
| 123 | + xxti { | |
| 124 | + compatible = "samsung,clock-xxti"; | |
| 125 | + clock-frequency = <0>; | |
| 126 | + }; | |
| 127 | + | |
| 128 | + xusbxti { | |
| 129 | + compatible = "samsung,clock-xusbxti"; | |
| 130 | + clock-frequency = <24000000>; | |
| 131 | + }; | |
| 132 | + }; | |
| 133 | + | |
| 134 | + i2c@13860000 { | |
| 135 | + pinctrl-0 = <&i2c0_bus>; | |
| 136 | + pinctrl-names = "default"; | |
| 137 | + samsung,i2c-sda-delay = <100>; | |
| 138 | + samsung,i2c-max-bus-freq = <400000>; | |
| 139 | + status = "okay"; | |
| 140 | + | |
| 141 | + usb3503: usb3503@08 { | |
| 142 | + compatible = "smsc,usb3503"; | |
| 143 | + reg = <0x08>; | |
| 144 | + | |
| 145 | + intn-gpios = <&gpx3 0 0>; | |
| 146 | + connect-gpios = <&gpx3 4 0>; | |
| 147 | + reset-gpios = <&gpx3 5 0>; | |
| 148 | + initial-mode = <1>; | |
| 149 | + }; | |
| 150 | + | |
| 151 | + max77686: pmic@09 { | |
| 152 | + compatible = "maxim,max77686"; | |
| 153 | + interrupt-parent = <&gpx3>; | |
| 154 | + interrupts = <2 0>; | |
| 155 | + pinctrl-names = "default"; | |
| 156 | + pinctrl-0 = <&max77686_irq>; | |
| 157 | + reg = <0x09>; | |
| 158 | + #clock-cells = <1>; | |
| 159 | + | |
| 160 | + voltage-regulators { | |
| 161 | + ldo1_reg: LDO1 { | |
| 162 | + regulator-name = "VDD_ALIVE_1.0V"; | |
| 163 | + regulator-min-microvolt = <1000000>; | |
| 164 | + regulator-max-microvolt = <1000000>; | |
| 165 | + regulator-always-on; | |
| 166 | + }; | |
| 167 | + | |
| 168 | + ldo2_reg: LDO2 { | |
| 169 | + regulator-name = "VDDQ_M1_2_1.8V"; | |
| 170 | + regulator-min-microvolt = <1800000>; | |
| 171 | + regulator-max-microvolt = <1800000>; | |
| 172 | + regulator-always-on; | |
| 173 | + }; | |
| 174 | + | |
| 175 | + ldo3_reg: LDO3 { | |
| 176 | + regulator-name = "VDDQ_EXT_1.8V"; | |
| 177 | + regulator-min-microvolt = <1800000>; | |
| 178 | + regulator-max-microvolt = <1800000>; | |
| 179 | + regulator-always-on; | |
| 180 | + }; | |
| 181 | + | |
| 182 | + ldo4_reg: LDO4 { | |
| 183 | + regulator-name = "VDDQ_MMC2_2.8V"; | |
| 184 | + regulator-min-microvolt = <2800000>; | |
| 185 | + regulator-max-microvolt = <2800000>; | |
| 186 | + regulator-always-on; | |
| 187 | + regulator-boot-on; | |
| 188 | + }; | |
| 189 | + | |
| 190 | + ldo5_reg: LDO5 { | |
| 191 | + regulator-name = "VDDQ_MMC1_3_1.8V"; | |
| 192 | + regulator-min-microvolt = <1800000>; | |
| 193 | + regulator-max-microvolt = <1800000>; | |
| 194 | + regulator-always-on; | |
| 195 | + regulator-boot-on; | |
| 196 | + }; | |
| 197 | + | |
| 198 | + ldo6_reg: LDO6 { | |
| 199 | + regulator-name = "VDD10_MPLL_1.0V"; | |
| 200 | + regulator-min-microvolt = <1000000>; | |
| 201 | + regulator-max-microvolt = <1000000>; | |
| 202 | + regulator-always-on; | |
| 203 | + }; | |
| 204 | + | |
| 205 | + ldo7_reg: LDO7 { | |
| 206 | + regulator-name = "VDD10_XPLL_1.0V"; | |
| 207 | + regulator-min-microvolt = <1000000>; | |
| 208 | + regulator-max-microvolt = <1000000>; | |
| 209 | + regulator-always-on; | |
| 210 | + }; | |
| 211 | + | |
| 212 | + ldo11_reg: LDO11 { | |
| 213 | + regulator-name = "VDD18_ABB1_1.8V"; | |
| 214 | + regulator-min-microvolt = <1800000>; | |
| 215 | + regulator-max-microvolt = <1800000>; | |
| 216 | + regulator-always-on; | |
| 217 | + }; | |
| 218 | + | |
| 219 | + ldo12_reg: LDO12 { | |
| 220 | + regulator-name = "VDD33_USB_3.3V"; | |
| 221 | + regulator-min-microvolt = <3300000>; | |
| 222 | + regulator-max-microvolt = <3300000>; | |
| 223 | + regulator-always-on; | |
| 224 | + regulator-boot-on; | |
| 225 | + }; | |
| 226 | + | |
| 227 | + ldo13_reg: LDO13 { | |
| 228 | + regulator-name = "VDDQ_C2C_W_1.8V"; | |
| 229 | + regulator-min-microvolt = <1800000>; | |
| 230 | + regulator-max-microvolt = <1800000>; | |
| 231 | + regulator-always-on; | |
| 232 | + regulator-boot-on; | |
| 233 | + }; | |
| 234 | + | |
| 235 | + ldo14_reg: LDO14 { | |
| 236 | + regulator-name = "VDD18_ABB0_2_1.8V"; | |
| 237 | + regulator-min-microvolt = <1800000>; | |
| 238 | + regulator-max-microvolt = <1800000>; | |
| 239 | + regulator-always-on; | |
| 240 | + regulator-boot-on; | |
| 241 | + }; | |
| 242 | + | |
| 243 | + ldo15_reg: LDO15 { | |
| 244 | + regulator-name = "VDD10_HSIC_1.0V"; | |
| 245 | + regulator-min-microvolt = <1000000>; | |
| 246 | + regulator-max-microvolt = <1000000>; | |
| 247 | + regulator-always-on; | |
| 248 | + regulator-boot-on; | |
| 249 | + }; | |
| 250 | + | |
| 251 | + ldo16_reg: LDO16 { | |
| 252 | + regulator-name = "VDD18_HSIC_1.8V"; | |
| 253 | + regulator-min-microvolt = <1800000>; | |
| 254 | + regulator-max-microvolt = <1800000>; | |
| 255 | + regulator-always-on; | |
| 256 | + regulator-boot-on; | |
| 257 | + }; | |
| 258 | + | |
| 259 | + ldo20_reg: LDO20 { | |
| 260 | + regulator-name = "LDO20_1.8V"; | |
| 261 | + regulator-min-microvolt = <1800000>; | |
| 262 | + regulator-max-microvolt = <1800000>; | |
| 263 | + regulator-boot-on; | |
| 264 | + }; | |
| 265 | + | |
| 266 | + ldo21_reg: LDO21 { | |
| 267 | + regulator-name = "LDO21_3.3V"; | |
| 268 | + regulator-min-microvolt = <3300000>; | |
| 269 | + regulator-max-microvolt = <3300000>; | |
| 270 | + regulator-always-on; | |
| 271 | + regulator-boot-on; | |
| 272 | + }; | |
| 273 | + | |
| 274 | + ldo25_reg: LDO25 { | |
| 275 | + regulator-name = "VDDQ_LCD_1.8V"; | |
| 276 | + regulator-min-microvolt = <1800000>; | |
| 277 | + regulator-max-microvolt = <1800000>; | |
| 278 | + regulator-always-on; | |
| 279 | + regulator-boot-on; | |
| 280 | + }; | |
| 281 | + | |
| 282 | + buck1_reg: BUCK1 { | |
| 283 | + regulator-name = "vdd_mif"; | |
| 284 | + regulator-min-microvolt = <1000000>; | |
| 285 | + regulator-max-microvolt = <1000000>; | |
| 286 | + regulator-always-on; | |
| 287 | + regulator-boot-on; | |
| 288 | + }; | |
| 289 | + | |
| 290 | + buck2_reg: BUCK2 { | |
| 291 | + regulator-name = "vdd_arm"; | |
| 292 | + regulator-min-microvolt = <900000>; | |
| 293 | + regulator-max-microvolt = <1350000>; | |
| 294 | + regulator-always-on; | |
| 295 | + regulator-boot-on; | |
| 296 | + }; | |
| 297 | + | |
| 298 | + buck3_reg: BUCK3 { | |
| 299 | + regulator-name = "vdd_int"; | |
| 300 | + regulator-min-microvolt = <1000000>; | |
| 301 | + regulator-max-microvolt = <1000000>; | |
| 302 | + regulator-always-on; | |
| 303 | + regulator-boot-on; | |
| 304 | + }; | |
| 305 | + | |
| 306 | + buck4_reg: BUCK4 { | |
| 307 | + regulator-name = "vdd_g3d"; | |
| 308 | + regulator-min-microvolt = <900000>; | |
| 309 | + regulator-max-microvolt = <1100000>; | |
| 310 | + regulator-microvolt-offset = <50000>; | |
| 311 | + }; | |
| 312 | + | |
| 313 | + buck5_reg: BUCK5 { | |
| 314 | + regulator-name = "VDDQ_CKEM1_2_1.2V"; | |
| 315 | + regulator-min-microvolt = <1200000>; | |
| 316 | + regulator-max-microvolt = <1200000>; | |
| 317 | + regulator-always-on; | |
| 318 | + regulator-boot-on; | |
| 319 | + }; | |
| 320 | + | |
| 321 | + buck6_reg: BUCK6 { | |
| 322 | + regulator-name = "BUCK6_1.35V"; | |
| 323 | + regulator-min-microvolt = <1350000>; | |
| 324 | + regulator-max-microvolt = <1350000>; | |
| 325 | + regulator-always-on; | |
| 326 | + regulator-boot-on; | |
| 327 | + }; | |
| 328 | + | |
| 329 | + buck7_reg: BUCK7 { | |
| 330 | + regulator-name = "BUCK7_2.0V"; | |
| 331 | + regulator-min-microvolt = <2000000>; | |
| 332 | + regulator-max-microvolt = <2000000>; | |
| 333 | + regulator-always-on; | |
| 334 | + }; | |
| 335 | + | |
| 336 | + buck8_reg: BUCK8 { | |
| 337 | + regulator-name = "BUCK8_2.8V"; | |
| 338 | + regulator-min-microvolt = <2800000>; | |
| 339 | + regulator-max-microvolt = <2800000>; | |
| 340 | + }; | |
| 341 | + }; | |
| 342 | + }; | |
| 343 | + }; | |
| 344 | + | |
| 345 | + i2c@13870000 { | |
| 346 | + pinctrl-names = "default"; | |
| 347 | + pinctrl-0 = <&i2c1_bus>; | |
| 348 | + status = "okay"; | |
| 349 | + max98090: max98090@10 { | |
| 350 | + compatible = "maxim,max98090"; | |
| 351 | + reg = <0x10>; | |
| 352 | + interrupt-parent = <&gpx0>; | |
| 353 | + interrupts = <0 0>; | |
| 354 | + }; | |
| 355 | + }; | |
| 356 | + | |
| 357 | + exynos-usbphy@125B0000 { | |
| 358 | + status = "okay"; | |
| 359 | + }; | |
| 360 | + | |
| 361 | + hsotg@12480000 { | |
| 362 | + status = "okay"; | |
| 363 | + vusb_d-supply = <&ldo15_reg>; | |
| 364 | + vusb_a-supply = <&ldo12_reg>; | |
| 365 | + }; | |
| 366 | + | |
| 367 | + ehci: ehci@12580000 { | |
| 368 | + status = "okay"; | |
| 369 | + }; | |
| 370 | +}; | |
| 371 | + | |
| 372 | +&pinctrl_1 { | |
| 373 | + gpio_power_key: power_key { | |
| 374 | + samsung,pins = "gpx1-3"; | |
| 375 | + samsung,pin-pud = <0>; | |
| 376 | + }; | |
| 377 | + | |
| 378 | + max77686_irq: max77686-irq { | |
| 379 | + samsung,pins = "gpx3-2"; | |
| 380 | + samsung,pin-function = <0>; | |
| 381 | + samsung,pin-pud = <0>; | |
| 382 | + samsung,pin-drv = <0>; | |
| 383 | + }; | |
| 384 | +}; | |
| @@ -0,0 +1,61 @@ | ||
| 1 | +/* | |
| 2 | + * Hardkernel's Exynos4412 based ODROID-U3 board device tree source | |
| 3 | + * | |
| 4 | + * Copyright (c) 2014 Marek Szyprowski <m.szyprowski@samsung.com> | |
| 5 | + * | |
| 6 | + * Device tree source file for Hardkernel's ODROID-U3 board which is based | |
| 7 | + * on Samsung's Exynos4412 SoC. | |
| 8 | + * | |
| 9 | + * This program is free software; you can redistribute it and/or modify | |
| 10 | + * it under the terms of the GNU General Public License version 2 as | |
| 11 | + * published by the Free Software Foundation. | |
| 12 | +*/ | |
| 13 | + | |
| 14 | +/dts-v1/; | |
| 15 | +#include "exynos4412-odroid-common.dtsi" | |
| 16 | + | |
| 17 | +/ { | |
| 18 | + model = "Hardkernel ODROID-U3 board based on Exynos4412"; | |
| 19 | + compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4"; | |
| 20 | + | |
| 21 | + memory { | |
| 22 | + reg = <0x40000000 0x7FF00000>; | |
| 23 | + }; | |
| 24 | + | |
| 25 | + leds { | |
| 26 | + compatible = "gpio-leds"; | |
| 27 | + led1 { | |
| 28 | + label = "led1:heart"; | |
| 29 | + gpios = <&gpc1 0 1>; | |
| 30 | + default-state = "on"; | |
| 31 | + linux,default-trigger = "heartbeat"; | |
| 32 | + }; | |
| 33 | + }; | |
| 34 | +}; | |
| 35 | + | |
| 36 | +&usb3503 { | |
| 37 | + clock-names = "refclk"; | |
| 38 | + clocks = <&pmu_system_controller 0>; | |
| 39 | + refclk-frequency = <24000000>; | |
| 40 | +}; | |
| 41 | + | |
| 42 | +&ehci { | |
| 43 | + port@1 { | |
| 44 | + status = "okay"; | |
| 45 | + }; | |
| 46 | + port@2 { | |
| 47 | + status = "okay"; | |
| 48 | + }; | |
| 49 | +}; | |
| 50 | + | |
| 51 | +&sound { | |
| 52 | + compatible = "samsung,odroidu3-audio"; | |
| 53 | + samsung,model = "Odroid-U3"; | |
| 54 | + samsung,audio-routing = | |
| 55 | + "Headphone Jack", "HPL", | |
| 56 | + "Headphone Jack", "HPR", | |
| 57 | + "Headphone Jack", "MICBIAS", | |
| 58 | + "IN1", "Headphone Jack", | |
| 59 | + "Speakers", "SPKL", | |
| 60 | + "Speakers", "SPKR"; | |
| 61 | +}; | |
| @@ -3,8 +3,8 @@ · 2 unmodified lines | ||
| 3 | 3 | * |
| 4 | 4 | * Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com> |
| 5 | 5 | * |
| 6 | − * Device tree source file for Hardkernel's ODROID-X board which is based on | |
| 7 | − * Samsung's Exynos4412 SoC. | |
| 6 | + * Device tree source file for Hardkernel's ODROID-X board which is based | |
| 7 | + * on Samsung's Exynos4412 SoC. | |
| 8 | 8 | * |
| 9 | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | 10 | * it under the terms of the GNU General Public License version 2 as |
| @@ -12,14 +12,14 @@ · 1 unmodified line | ||
| 12 | 12 | */ |
| 13 | 13 | |
| 14 | 14 | /dts-v1/; |
| 15 | −#include "exynos4412.dtsi" | |
| 15 | +#include "exynos4412-odroid-common.dtsi" | |
| 16 | 16 | |
| 17 | 17 | / { |
| 18 | 18 | model = "Hardkernel ODROID-X board based on Exynos4412"; |
| 19 | 19 | compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; |
| 20 | 20 | |
| 21 | 21 | memory { |
| 22 | − reg = <0x40000000 0x40000000>; | |
| 22 | + reg = <0x40000000 0x3FF00000>; | |
| 23 | 23 | }; |
| 24 | 24 | |
| 25 | 25 | leds { |
| @@ -38,23 +38,25 @@ · 12 unmodified lines | ||
| 38 | 38 | }; |
| 39 | 39 | }; |
| 40 | 40 | |
| 41 | − mmc@12550000 { | |
| 42 | − pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; | |
| 43 | − pinctrl-names = "default"; | |
| 44 | − vmmc-supply = <&ldo20_reg &buck8_reg>; | |
| 41 | + serial@13820000 { | |
| 45 | 42 | status = "okay"; |
| 43 | + }; | |
| 46 | 44 | |
| 47 | − num-slots = <1>; | |
| 48 | − supports-highspeed; | |
| 49 | − broken-cd; | |
| 50 | − card-detect-delay = <200>; | |
| 51 | − samsung,dw-mshc-ciu-div = <3>; | |
| 52 | − samsung,dw-mshc-sdr-timing = <2 3>; | |
| 53 | − samsung,dw-mshc-ddr-timing = <1 2>; | |
| 45 | + serial@13830000 { | |
| 46 | + status = "okay"; | |
| 47 | + }; | |
| 54 | 48 | |
| 55 | − slot@0 { | |
| 56 | − reg = <0>; | |
| 57 | − bus-width = <8>; | |
| 49 | + gpio_keys { | |
| 50 | + pinctrl-0 = <&gpio_power_key &gpio_home_key>; | |
| 51 | + | |
| 52 | + home_key { | |
| 53 | + interrupt-parent = <&gpx2>; | |
| 54 | + interrupts = <2 0>; | |
| 55 | + gpios = <&gpx2 2 0>; | |
| 56 | + linux,code = <KEY_HOME>; | |
| 57 | + label = "home key"; | |
| 58 | + debounce-interval = <10>; | |
| 59 | + gpio-key,wakeup; | |
| 58 | 60 | }; |
| 59 | 61 | }; |
| 60 | 62 | |
| @@ -65,242 +67,19 @@ · 4 unmodified lines | ||
| 65 | 67 | regulator-max-microvolt = <3300000>; |
| 66 | 68 | gpio = <&gpa1 1 1>; |
| 67 | 69 | enable-active-high; |
| 68 | − regulator-boot-on; | |
| 69 | − }; | |
| 70 | − | |
| 71 | − rtc@10070000 { | |
| 72 | − status = "okay"; | |
| 73 | − }; | |
| 74 | − | |
| 75 | − sdhci@12530000 { | |
| 76 | − bus-width = <4>; | |
| 77 | − pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; | |
| 78 | − pinctrl-names = "default"; | |
| 79 | − vmmc-supply = <&ldo4_reg &ldo21_reg>; | |
| 80 | − status = "okay"; | |
| 81 | − }; | |
| 82 | − | |
| 83 | − serial@13800000 { | |
| 84 | − status = "okay"; | |
| 85 | − }; | |
| 86 | − | |
| 87 | − serial@13810000 { | |
| 88 | − status = "okay"; | |
| 89 | − }; | |
| 90 | − | |
| 91 | − serial@13820000 { | |
| 92 | − status = "okay"; | |
| 70 | + regulator-always-on; | |
| 93 | 71 | }; |
| 72 | +}; | |
| 94 | 73 | |
| 95 | − serial@13830000 { | |
| 74 | +&ehci { | |
| 75 | + port@1 { | |
| 96 | 76 | status = "okay"; |
| 97 | 77 | }; |
| 78 | +}; | |
| 98 | 79 | |
| 99 | − fixed-rate-clocks { | |
| 100 | − xxti { | |
| 101 | − compatible = "samsung,clock-xxti"; | |
| 102 | − clock-frequency = <0>; | |
| 103 | − }; | |
| 104 | − | |
| 105 | − xusbxti { | |
| 106 | − compatible = "samsung,clock-xusbxti"; | |
| 107 | − clock-frequency = <24000000>; | |
| 108 | − }; | |
| 109 | − }; | |
| 110 | − | |
| 111 | − i2c@13860000 { | |
| 112 | − pinctrl-0 = <&i2c0_bus>; | |
| 113 | − pinctrl-names = "default"; | |
| 114 | − status = "okay"; | |
| 115 | − | |
| 116 | − max77686: pmic@09 { | |
| 117 | − compatible = "maxim,max77686"; | |
| 118 | − reg = <0x09>; | |
| 119 | − #clock-cells = <1>; | |
| 120 | − | |
| 121 | − voltage-regulators { | |
| 122 | − ldo1_reg: LDO1 { | |
| 123 | − regulator-name = "VDD_ALIVE_1.0V"; | |
| 124 | − regulator-min-microvolt = <1000000>; | |
| 125 | − regulator-max-microvolt = <1000000>; | |
| 126 | − regulator-always-on; | |
| 127 | − }; | |
| 128 | − | |
| 129 | − ldo2_reg: LDO2 { | |
| 130 | − regulator-name = "VDDQ_M1_2_1.8V"; | |
| 131 | − regulator-min-microvolt = <1800000>; | |
| 132 | − regulator-max-microvolt = <1800000>; | |
| 133 | − regulator-always-on; | |
| 134 | − }; | |
| 135 | − | |
| 136 | − ldo3_reg: LDO3 { | |
| 137 | − regulator-name = "VDDQ_EXT_1.8V"; | |
| 138 | − regulator-min-microvolt = <1800000>; | |
| 139 | − regulator-max-microvolt = <1800000>; | |
| 140 | − regulator-always-on; | |
| 141 | − }; | |
| 142 | − | |
| 143 | − ldo4_reg: LDO4 { | |
| 144 | − regulator-name = "VDDQ_MMC2_2.8V"; | |
| 145 | − regulator-min-microvolt = <2800000>; | |
| 146 | − regulator-max-microvolt = <2800000>; | |
| 147 | − regulator-always-on; | |
| 148 | − regulator-boot-on; | |
| 149 | − }; | |
| 150 | − | |
| 151 | − ldo5_reg: LDO5 { | |
| 152 | − regulator-name = "VDDQ_MMC1_3_1.8V"; | |
| 153 | − regulator-min-microvolt = <1800000>; | |
| 154 | − regulator-max-microvolt = <1800000>; | |
| 155 | − regulator-always-on; | |
| 156 | − regulator-boot-on; | |
| 157 | − }; | |
| 158 | − | |
| 159 | − ldo6_reg: LDO6 { | |
| 160 | − regulator-name = "VDD10_MPLL_1.0V"; | |
| 161 | − regulator-min-microvolt = <1000000>; | |
| 162 | − regulator-max-microvolt = <1000000>; | |
| 163 | − regulator-always-on; | |
| 164 | − }; | |
| 165 | − | |
| 166 | − ldo7_reg: LDO7 { | |
| 167 | − regulator-name = "VDD10_XPLL_1.0V"; | |
| 168 | − regulator-min-microvolt = <1000000>; | |
| 169 | − regulator-max-microvolt = <1000000>; | |
| 170 | − regulator-always-on; | |
| 171 | − }; | |
| 172 | − | |
| 173 | − ldo11_reg: LDO11 { | |
| 174 | − regulator-name = "VDD18_ABB1_1.8V"; | |
| 175 | − regulator-min-microvolt = <1800000>; | |
| 176 | − regulator-max-microvolt = <1800000>; | |
| 177 | − regulator-always-on; | |
| 178 | − }; | |
| 179 | − | |
| 180 | − ldo12_reg: LDO12 { | |
| 181 | − regulator-name = "VDD33_USB_3.3V"; | |
| 182 | − regulator-min-microvolt = <3300000>; | |
| 183 | − regulator-max-microvolt = <3300000>; | |
| 184 | − regulator-always-on; | |
| 185 | − regulator-boot-on; | |
| 186 | − }; | |
| 187 | − | |
| 188 | − ldo13_reg: LDO13 { | |
| 189 | − regulator-name = "VDDQ_C2C_W_1.8V"; | |
| 190 | − regulator-min-microvolt = <1800000>; | |
| 191 | − regulator-max-microvolt = <1800000>; | |
| 192 | − regulator-always-on; | |
| 193 | − regulator-boot-on; | |
| 194 | − }; | |
| 195 | − | |
| 196 | − ldo14_reg: LDO14 { | |
| 197 | − regulator-name = "VDD18_ABB0_2_1.8V"; | |
| 198 | − regulator-min-microvolt = <1800000>; | |
| 199 | − regulator-max-microvolt = <1800000>; | |
| 200 | − regulator-always-on; | |
| 201 | − regulator-boot-on; | |
| 202 | − }; | |
| 203 | − | |
| 204 | − ldo15_reg: LDO15 { | |
| 205 | − regulator-name = "VDD10_HSIC_1.0V"; | |
| 206 | − regulator-min-microvolt = <1000000>; | |
| 207 | − regulator-max-microvolt = <1000000>; | |
| 208 | − regulator-always-on; | |
| 209 | − regulator-boot-on; | |
| 210 | − }; | |
| 211 | − | |
| 212 | − ldo16_reg: LDO16 { | |
| 213 | − regulator-name = "VDD18_HSIC_1.8V"; | |
| 214 | − regulator-min-microvolt = <1800000>; | |
| 215 | − regulator-max-microvolt = <1800000>; | |
| 216 | − regulator-always-on; | |
| 217 | − regulator-boot-on; | |
| 218 | − }; | |
| 219 | − | |
| 220 | − ldo20_reg: LDO20 { | |
| 221 | − regulator-name = "LDO20_1.8V"; | |
| 222 | − regulator-min-microvolt = <1800000>; | |
| 223 | − regulator-max-microvolt = <1800000>; | |
| 224 | − regulator-boot-on; | |
| 225 | − }; | |
| 226 | − | |
| 227 | − ldo21_reg: LDO21 { | |
| 228 | − regulator-name = "LDO21_3.3V"; | |
| 229 | − regulator-min-microvolt = <3300000>; | |
| 230 | − regulator-max-microvolt = <3300000>; | |
| 231 | − regulator-always-on; | |
| 232 | − regulator-boot-on; | |
| 233 | − }; | |
| 234 | − | |
| 235 | − ldo25_reg: LDO25 { | |
| 236 | − regulator-name = "VDDQ_LCD_1.8V"; | |
| 237 | − regulator-min-microvolt = <1800000>; | |
| 238 | − regulator-max-microvolt = <1800000>; | |
| 239 | − regulator-always-on; | |
| 240 | − regulator-boot-on; | |
| 241 | − }; | |
| 242 | − | |
| 243 | − buck1_reg: BUCK1 { | |
| 244 | − regulator-name = "vdd_mif"; | |
| 245 | − regulator-min-microvolt = <1000000>; | |
| 246 | − regulator-max-microvolt = <1000000>; | |
| 247 | − regulator-always-on; | |
| 248 | − regulator-boot-on; | |
| 249 | − }; | |
| 250 | − | |
| 251 | − buck2_reg: BUCK2 { | |
| 252 | − regulator-name = "vdd_arm"; | |
| 253 | − regulator-min-microvolt = <900000>; | |
| 254 | − regulator-max-microvolt = <1350000>; | |
| 255 | − regulator-always-on; | |
| 256 | − regulator-boot-on; | |
| 257 | − }; | |
| 258 | − | |
| 259 | − buck3_reg: BUCK3 { | |
| 260 | − regulator-name = "vdd_int"; | |
| 261 | − regulator-min-microvolt = <1000000>; | |
| 262 | − regulator-max-microvolt = <1000000>; | |
| 263 | − regulator-always-on; | |
| 264 | − regulator-boot-on; | |
| 265 | − }; | |
| 266 | − | |
| 267 | − buck4_reg: BUCK4 { | |
| 268 | − regulator-name = "vdd_g3d"; | |
| 269 | − regulator-min-microvolt = <900000>; | |
| 270 | − regulator-max-microvolt = <1100000>; | |
| 271 | − regulator-microvolt-offset = <50000>; | |
| 272 | − }; | |
| 273 | − | |
| 274 | − buck5_reg: BUCK5 { | |
| 275 | − regulator-name = "VDDQ_CKEM1_2_1.2V"; | |
| 276 | − regulator-min-microvolt = <1200000>; | |
| 277 | − regulator-max-microvolt = <1200000>; | |
| 278 | − regulator-always-on; | |
| 279 | − regulator-boot-on; | |
| 280 | − }; | |
| 281 | − | |
| 282 | − buck6_reg: BUCK6 { | |
| 283 | − regulator-name = "BUCK6_1.35V"; | |
| 284 | − regulator-min-microvolt = <1350000>; | |
| 285 | − regulator-max-microvolt = <1350000>; | |
| 286 | − regulator-always-on; | |
| 287 | − regulator-boot-on; | |
| 288 | − }; | |
| 289 | − | |
| 290 | − buck7_reg: BUCK7 { | |
| 291 | − regulator-name = "BUCK7_2.0V"; | |
| 292 | − regulator-min-microvolt = <2000000>; | |
| 293 | − regulator-max-microvolt = <2000000>; | |
| 294 | − regulator-always-on; | |
| 295 | − }; | |
| 296 | − | |
| 297 | − buck8_reg: BUCK8 { | |
| 298 | − regulator-name = "BUCK8_2.8V"; | |
| 299 | − regulator-min-microvolt = <2800000>; | |
| 300 | − regulator-max-microvolt = <2800000>; | |
| 301 | − regulator-always-on; | |
| 302 | − }; | |
| 303 | − }; | |
| 304 | − }; | |
| 80 | +&pinctrl_1 { | |
| 81 | + gpio_home_key: home_key { | |
| 82 | + samsung,pins = "gpx2-2"; | |
| 83 | + samsung,pin-pud = <0>; | |
| 305 | 84 | }; |
| 306 | 85 | }; |
| @@ -0,0 +1,32 @@ | ||
| 1 | +/* | |
| 2 | + * Hardkernel's Exynos4412 based ODROID-X2 board device tree source | |
| 3 | + * | |
| 4 | + * Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com> | |
| 5 | + * | |
| 6 | + * Device tree source file for Hardkernel's ODROID-X2 board which is based | |
| 7 | + * on Samsung's Exynos4412 SoC. | |
| 8 | + * | |
| 9 | + * This program is free software; you can redistribute it and/or modify | |
| 10 | + * it under the terms of the GNU General Public License version 2 as | |
| 11 | + * published by the Free Software Foundation. | |
| 12 | +*/ | |
| 13 | + | |
| 14 | +#include "exynos4412-odroidx.dts" | |
| 15 | + | |
| 16 | +/ { | |
| 17 | + model = "Hardkernel ODROID-X2 board based on Exynos4412"; | |
| 18 | + compatible = "hardkernel,odroid-x2", "samsung,exynos4412", "samsung,exynos4"; | |
| 19 | + | |
| 20 | + memory { | |
| 21 | + reg = <0x40000000 0x7FF00000>; | |
| 22 | + }; | |
| 23 | +}; | |
| 24 | + | |
| 25 | +&sound { | |
| 26 | + samsung,model = "Odroid-X2"; | |
| 27 | + samsung,audio-routing = | |
| 28 | + "Headphone Jack", "HPL", | |
| 29 | + "Headphone Jack", "HPR", | |
| 30 | + "IN1", "Mic Jack", | |
| 31 | + "Mic Jack", "MICBIAS"; | |
| 32 | +}; | |
| @@ -26,6 +26,10 @@ · 25 unmodified lines | ||
| 26 | 26 | samsung,combiner-nr = <20>; |
| 27 | 27 | }; |
| 28 | 28 | |
| 29 | + pmu { | |
| 30 | + interrupts = <2 2>, <3 2>, <18 2>, <19 2>; | |
| 31 | + }; | |
| 32 | + | |
| 29 | 33 | gic: interrupt-controller@10490000 { |
| 30 | 34 | cpu-offset = <0x4000>; |
| 31 | 35 | }; |
| @@ -31,12 +31,6 @@ · 30 unmodified lines | ||
| 31 | 31 | mshc0 = &mshc_0; |
| 32 | 32 | }; |
| 33 | 33 | |
| 34 | − pmu { | |
| 35 | − compatible = "arm,cortex-a9-pmu"; | |
| 36 | − interrupt-parent = <&combiner>; | |
| 37 | − interrupts = <2 2>, <3 2>, <18 2>, <19 2>; | |
| 38 | − }; | |
| 39 | − | |
| 40 | 34 | sysram@02020000 { |
| 41 | 35 | compatible = "mmio-sram"; |
| 42 | 36 | reg = <0x02020000 0x40000>; |
| @@ -94,6 +94,7 @@ · 93 unmodified lines | ||
| 94 | 94 | reg = <0x14400000 0x40000>; |
| 95 | 95 | interrupt-names = "fifo", "vsync", "lcd_sys"; |
| 96 | 96 | interrupts = <18 4>, <18 5>, <18 6>; |
| 97 | + samsung,sysreg = <&sysreg_system_controller>; | |
| 97 | 98 | status = "disabled"; |
| 98 | 99 | }; |
| 99 | 100 | |
| @@ -27,177 +27,18 @@ · 26 unmodified lines | ||
| 27 | 27 | i2c2_bus: i2c2-bus { |
| 28 | 28 | samsung,pin-pud = <0>; |
| 29 | 29 | }; |
| 30 | − | |
| 31 | − max77686_irq: max77686-irq { | |
| 32 | − samsung,pins = "gpx3-2"; | |
| 33 | − samsung,pin-function = <0>; | |
| 34 | − samsung,pin-pud = <0>; | |
| 35 | − samsung,pin-drv = <0>; | |
| 36 | − }; | |
| 37 | 30 | }; |
| 38 | 31 | |
| 39 | 32 | i2c@12C60000 { |
| 40 | 33 | status = "okay"; |
| 41 | 34 | samsung,i2c-sda-delay = <100>; |
| 42 | 35 | samsung,i2c-max-bus-freq = <378000>; |
| 43 | − | |
| 44 | − max77686@09 { | |
| 45 | − compatible = "maxim,max77686"; | |
| 46 | − interrupt-parent = <&gpx3>; | |
| 47 | − interrupts = <2 0>; | |
| 48 | − pinctrl-names = "default"; | |
| 49 | − pinctrl-0 = <&max77686_irq>; | |
| 50 | − wakeup-source; | |
| 51 | − reg = <0x09>; | |
| 52 | − #clock-cells = <1>; | |
| 53 | − | |
| 54 | − voltage-regulators { | |
| 55 | − ldo1_reg: LDO1 { | |
| 56 | − regulator-name = "P1.0V_LDO_OUT1"; | |
| 57 | − regulator-min-microvolt = <1000000>; | |
| 58 | − regulator-max-microvolt = <1000000>; | |
| 59 | − regulator-always-on; | |
| 60 | − }; | |
| 61 | − | |
| 62 | − ldo2_reg: LDO2 { | |
| 63 | − regulator-name = "P1.8V_LDO_OUT2"; | |
| 64 | − regulator-min-microvolt = <1800000>; | |
| 65 | − regulator-max-microvolt = <1800000>; | |
| 66 | − regulator-always-on; | |
| 67 | − }; | |
| 68 | − | |
| 69 | − ldo3_reg: LDO3 { | |
| 70 | − regulator-name = "P1.8V_LDO_OUT3"; | |
| 71 | − regulator-min-microvolt = <1800000>; | |
| 72 | − regulator-max-microvolt = <1800000>; | |
| 73 | − regulator-always-on; | |
| 74 | − }; | |
| 75 | − | |
| 76 | − ldo7_reg: LDO7 { | |
| 77 | − regulator-name = "P1.1V_LDO_OUT7"; | |
| 78 | − regulator-min-microvolt = <1100000>; | |
| 79 | − regulator-max-microvolt = <1100000>; | |
| 80 | − regulator-always-on; | |
| 81 | − }; | |
| 82 | − | |
| 83 | − ldo8_reg: LDO8 { | |
| 84 | − regulator-name = "P1.0V_LDO_OUT8"; | |
| 85 | − regulator-min-microvolt = <1000000>; | |
| 86 | − regulator-max-microvolt = <1000000>; | |
| 87 | − regulator-always-on; | |
| 88 | − }; | |
| 89 | − | |
| 90 | − ldo10_reg: LDO10 { | |
| 91 | − regulator-name = "P1.8V_LDO_OUT10"; | |
| 92 | − regulator-min-microvolt = <1800000>; | |
| 93 | − regulator-max-microvolt = <1800000>; | |
| 94 | − regulator-always-on; | |
| 95 | − }; | |
| 96 | − | |
| 97 | − ldo12_reg: LDO12 { | |
| 98 | − regulator-name = "P3.0V_LDO_OUT12"; | |
| 99 | − regulator-min-microvolt = <3000000>; | |
| 100 | − regulator-max-microvolt = <3000000>; | |
| 101 | − regulator-always-on; | |
| 102 | − }; | |
| 103 | − | |
| 104 | − ldo14_reg: LDO14 { | |
| 105 | − regulator-name = "P1.8V_LDO_OUT14"; | |
| 106 | − regulator-min-microvolt = <1800000>; | |
| 107 | − regulator-max-microvolt = <1800000>; | |
| 108 | − regulator-always-on; | |
| 109 | − }; | |
| 110 | − | |
| 111 | − ldo15_reg: LDO15 { | |
| 112 | − regulator-name = "P1.0V_LDO_OUT15"; | |
| 113 | − regulator-min-microvolt = <1000000>; | |
| 114 | − regulator-max-microvolt = <1000000>; | |
| 115 | − regulator-always-on; | |
| 116 | − }; | |
| 117 | − | |
| 118 | − ldo16_reg: LDO16 { | |
| 119 | − regulator-name = "P1.8V_LDO_OUT16"; | |
| 120 | − regulator-min-microvolt = <1800000>; | |
| 121 | − regulator-max-microvolt = <1800000>; | |
| 122 | − regulator-always-on; | |
| 123 | − }; | |
| 124 | − | |
| 125 | − buck1_reg: BUCK1 { | |
| 126 | − regulator-name = "vdd_mif"; | |
| 127 | − regulator-min-microvolt = <950000>; | |
| 128 | − regulator-max-microvolt = <1300000>; | |
| 129 | − regulator-always-on; | |
| 130 | − regulator-boot-on; | |
| 131 | − }; | |
| 132 | − | |
| 133 | − buck2_reg: BUCK2 { | |
| 134 | − regulator-name = "vdd_arm"; | |
| 135 | − regulator-min-microvolt = <850000>; | |
| 136 | − regulator-max-microvolt = <1350000>; | |
| 137 | − regulator-always-on; | |
| 138 | − regulator-boot-on; | |
| 139 | − }; | |
| 140 | − | |
| 141 | − buck3_reg: BUCK3 { | |
| 142 | − regulator-name = "vdd_int"; | |
| 143 | − regulator-min-microvolt = <900000>; | |
| 144 | − regulator-max-microvolt = <1200000>; | |
| 145 | − regulator-always-on; | |
| 146 | − regulator-boot-on; | |
| 147 | − }; | |
| 148 | − | |
| 149 | − buck4_reg: BUCK4 { | |
| 150 | − regulator-name = "vdd_g3d"; | |
| 151 | − regulator-min-microvolt = <850000>; | |
| 152 | − regulator-max-microvolt = <1300000>; | |
| 153 | − regulator-always-on; | |
| 154 | − regulator-boot-on; | |
| 155 | − }; | |
| 156 | − | |
| 157 | − buck5_reg: BUCK5 { | |
| 158 | − regulator-name = "P1.8V_BUCK_OUT5"; | |
| 159 | − regulator-min-microvolt = <1800000>; | |
| 160 | − regulator-max-microvolt = <1800000>; | |
| 161 | − regulator-always-on; | |
| 162 | − regulator-boot-on; | |
| 163 | − }; | |
| 164 | − | |
| 165 | − buck6_reg: BUCK6 { | |
| 166 | − regulator-name = "P1.35V_BUCK_OUT6"; | |
| 167 | − regulator-min-microvolt = <1350000>; | |
| 168 | − regulator-max-microvolt = <1350000>; | |
| 169 | − regulator-always-on; | |
| 170 | − }; | |
| 171 | − | |
| 172 | − buck7_reg: BUCK7 { | |
| 173 | − regulator-name = "P2.0V_BUCK_OUT7"; | |
| 174 | − regulator-min-microvolt = <2000000>; | |
| 175 | − regulator-max-microvolt = <2000000>; | |
| 176 | − regulator-always-on; | |
| 177 | − }; | |
| 178 | − | |
| 179 | − buck8_reg: BUCK8 { | |
| 180 | − regulator-name = "P2.85V_BUCK_OUT8"; | |
| 181 | − regulator-min-microvolt = <2850000>; | |
| 182 | − regulator-max-microvolt = <2850000>; | |
| 183 | − regulator-always-on; | |
| 184 | − }; | |
| 185 | − }; | |
| 186 | − }; | |
| 187 | 36 | }; |
| 188 | 37 | |
| 189 | 38 | i2c@12C70000 { |
| 190 | 39 | status = "okay"; |
| 191 | 40 | samsung,i2c-sda-delay = <100>; |
| 192 | 41 | samsung,i2c-max-bus-freq = <378000>; |
| 193 | − | |
| 194 | − trackpad { | |
| 195 | − reg = <0x67>; | |
| 196 | − compatible = "cypress,cyapa"; | |
| 197 | − interrupts = <2 0>; | |
| 198 | − interrupt-parent = <&gpx1>; | |
| 199 | − wakeup-source; | |
| 200 | − }; | |
| 201 | 42 | }; |
| 202 | 43 | |
| 203 | 44 | i2c@12C80000 { |
| @@ -44,6 +44,8 @@ · 43 unmodified lines | ||
| 44 | 44 | max77686@09 { |
| 45 | 45 | compatible = "maxim,max77686"; |
| 46 | 46 | reg = <0x09>; |
| 47 | + interrupt-parent = <&gpx3>; | |
| 48 | + interrupts = <2 0>; | |
| 47 | 49 | |
| 48 | 50 | voltage-regulators { |
| 49 | 51 | ldo1_reg: LDO1 { |
| @@ -137,7 +137,7 @@ · 136 unmodified lines | ||
| 137 | 137 | sbs,poll-retry-count = <1>; |
| 138 | 138 | }; |
| 139 | 139 | |
| 140 | − ec: embedded-controller { | |
| 140 | + cros_ec: embedded-controller { | |
| 141 | 141 | compatible = "google,cros-ec-i2c"; |
| 142 | 142 | reg = <0x1e>; |
| 143 | 143 | interrupts = <6 0>; |
| @@ -145,95 +145,6 @@ · 1 unmodified line | ||
| 145 | 145 | pinctrl-names = "default"; |
| 146 | 146 | pinctrl-0 = <&ec_irq>; |
| 147 | 147 | wakeup-source; |
| 148 | − | |
| 149 | − keyboard-controller { | |
| 150 | − compatible = "google,cros-ec-keyb"; | |
| 151 | − keypad,num-rows = <8>; | |
| 152 | − keypad,num-columns = <13>; | |
| 153 | − google,needs-ghost-filter; | |
| 154 | − linux,keymap = <0x0001007d /* L_META */ | |
| 155 | − 0x0002003b /* F1 */ | |
| 156 | − 0x00030030 /* B */ | |
| 157 | − 0x00040044 /* F10 */ | |
| 158 | − 0x00060031 /* N */ | |
| 159 | − 0x0008000d /* = */ | |
| 160 | − 0x000a0064 /* R_ALT */ | |
| 161 | − | |
| 162 | − 0x01010001 /* ESC */ | |
| 163 | − 0x0102003e /* F4 */ | |
| 164 | − 0x01030022 /* G */ | |
| 165 | − 0x01040041 /* F7 */ | |
| 166 | − 0x01060023 /* H */ | |
| 167 | − 0x01080028 /* ' */ | |
| 168 | − 0x01090043 /* F9 */ | |
| 169 | − 0x010b000e /* BKSPACE */ | |
| 170 | − | |
| 171 | − 0x0200001d /* L_CTRL */ | |
| 172 | − 0x0201000f /* TAB */ | |
| 173 | − 0x0202003d /* F3 */ | |
| 174 | − 0x02030014 /* T */ | |
| 175 | − 0x02040040 /* F6 */ | |
| 176 | − 0x0205001b /* ] */ | |
| 177 | − 0x02060015 /* Y */ | |
| 178 | − 0x02070056 /* 102ND */ | |
| 179 | − 0x0208001a /* [ */ | |
| 180 | − 0x02090042 /* F8 */ | |
| 181 | − | |
| 182 | − 0x03010029 /* GRAVE */ | |
| 183 | − 0x0302003c /* F2 */ | |
| 184 | − 0x03030006 /* 5 */ | |
| 185 | − 0x0304003f /* F5 */ | |
| 186 | − 0x03060007 /* 6 */ | |
| 187 | − 0x0308000c /* - */ | |
| 188 | − 0x030b002b /* \ */ | |
| 189 | − | |
| 190 | − 0x04000061 /* R_CTRL */ | |
| 191 | − 0x0401001e /* A */ | |
| 192 | − 0x04020020 /* D */ | |
| 193 | − 0x04030021 /* F */ | |
| 194 | − 0x0404001f /* S */ | |
| 195 | − 0x04050025 /* K */ | |
| 196 | − 0x04060024 /* J */ | |
| 197 | − 0x04080027 /* ; */ | |
| 198 | − 0x04090026 /* L */ | |
| 199 | − 0x040a002b /* \ */ | |
| 200 | − 0x040b001c /* ENTER */ | |
| 201 | − | |
| 202 | − 0x0501002c /* Z */ | |
| 203 | − 0x0502002e /* C */ | |
| 204 | − 0x0503002f /* V */ | |
| 205 | − 0x0504002d /* X */ | |
| 206 | − 0x05050033 /* , */ | |
| 207 | − 0x05060032 /* M */ | |
| 208 | − 0x0507002a /* L_SHIFT */ | |
| 209 | − 0x05080035 /* / */ | |
| 210 | − 0x05090034 /* . */ | |
| 211 | − 0x050B0039 /* SPACE */ | |
| 212 | − | |
| 213 | − 0x06010002 /* 1 */ | |
| 214 | − 0x06020004 /* 3 */ | |
| 215 | − 0x06030005 /* 4 */ | |
| 216 | − 0x06040003 /* 2 */ | |
| 217 | − 0x06050009 /* 8 */ | |
| 218 | − 0x06060008 /* 7 */ | |
| 219 | − 0x0608000b /* 0 */ | |
| 220 | − 0x0609000a /* 9 */ | |
| 221 | − 0x060a0038 /* L_ALT */ | |
| 222 | − 0x060b006c /* DOWN */ | |
| 223 | − 0x060c006a /* RIGHT */ | |
| 224 | − | |
| 225 | − 0x07010010 /* Q */ | |
| 226 | − 0x07020012 /* E */ | |
| 227 | − 0x07030013 /* R */ | |
| 228 | − 0x07040011 /* W */ | |
| 229 | − 0x07050017 /* I */ | |
| 230 | − 0x07060016 /* U */ | |
| 231 | − 0x07070036 /* R_SHIFT */ | |
| 232 | − 0x07080019 /* P */ | |
| 233 | − 0x07090018 /* O */ | |
| 234 | − 0x070b0067 /* UP */ | |
| 235 | − 0x070c0069>; /* LEFT */ | |
| 236 | − }; | |
| 237 | 148 | }; |
| 238 | 149 | |
| 239 | 150 | power-regulator { |
| @@ -351,6 +262,7 @@ · 111 unmodified lines | ||
| 351 | 262 | sound { |
| 352 | 263 | compatible = "google,snow-audio-max98095"; |
| 353 | 264 | |
| 265 | + samsung,model = "Snow-I2S-MAX98095"; | |
| 354 | 266 | samsung,i2s-controller = <&i2s0>; |
| 355 | 267 | samsung,audio-codec = <&max98095>; |
| 356 | 268 | }; |
| @@ -431,3 +343,170 @@ · 74 unmodified lines | ||
| 431 | 343 | }; |
| 432 | 344 | }; |
| 433 | 345 | }; |
| 346 | + | |
| 347 | +&i2c_0 { | |
| 348 | + max77686@09 { | |
| 349 | + compatible = "maxim,max77686"; | |
| 350 | + interrupt-parent = <&gpx3>; | |
| 351 | + interrupts = <2 0>; | |
| 352 | + pinctrl-names = "default"; | |
| 353 | + pinctrl-0 = <&max77686_irq>; | |
| 354 | + wakeup-source; | |
| 355 | + reg = <0x09>; | |
| 356 | + #clock-cells = <1>; | |
| 357 | + | |
| 358 | + voltage-regulators { | |
| 359 | + ldo1_reg: LDO1 { | |
| 360 | + regulator-name = "P1.0V_LDO_OUT1"; | |
| 361 | + regulator-min-microvolt = <1000000>; | |
| 362 | + regulator-max-microvolt = <1000000>; | |
| 363 | + regulator-always-on; | |
| 364 | + }; | |
| 365 | + | |
| 366 | + ldo2_reg: LDO2 { | |
| 367 | + regulator-name = "P1.8V_LDO_OUT2"; | |
| 368 | + regulator-min-microvolt = <1800000>; | |
| 369 | + regulator-max-microvolt = <1800000>; | |
| 370 | + regulator-always-on; | |
| 371 | + }; | |
| 372 | + | |
| 373 | + ldo3_reg: LDO3 { | |
| 374 | + regulator-name = "P1.8V_LDO_OUT3"; | |
| 375 | + regulator-min-microvolt = <1800000>; | |
| 376 | + regulator-max-microvolt = <1800000>; | |
| 377 | + regulator-always-on; | |
| 378 | + }; | |
| 379 | + | |
| 380 | + ldo7_reg: LDO7 { | |
| 381 | + regulator-name = "P1.1V_LDO_OUT7"; | |
| 382 | + regulator-min-microvolt = <1100000>; | |
| 383 | + regulator-max-microvolt = <1100000>; | |
| 384 | + regulator-always-on; | |
| 385 | + }; | |
| 386 | + | |
| 387 | + ldo8_reg: LDO8 { | |
| 388 | + regulator-name = "P1.0V_LDO_OUT8"; | |
| 389 | + regulator-min-microvolt = <1000000>; | |
| 390 | + regulator-max-microvolt = <1000000>; | |
| 391 | + regulator-always-on; | |
| 392 | + }; | |
| 393 | + | |
| 394 | + ldo10_reg: LDO10 { | |
| 395 | + regulator-name = "P1.8V_LDO_OUT10"; | |
| 396 | + regulator-min-microvolt = <1800000>; | |
| 397 | + regulator-max-microvolt = <1800000>; | |
| 398 | + regulator-always-on; | |
| 399 | + }; | |
| 400 | + | |
| 401 | + ldo12_reg: LDO12 { | |
| 402 | + regulator-name = "P3.0V_LDO_OUT12"; | |
| 403 | + regulator-min-microvolt = <3000000>; | |
| 404 | + regulator-max-microvolt = <3000000>; | |
| 405 | + regulator-always-on; | |
| 406 | + }; | |
| 407 | + | |
| 408 | + ldo14_reg: LDO14 { | |
| 409 | + regulator-name = "P1.8V_LDO_OUT14"; | |
| 410 | + regulator-min-microvolt = <1800000>; | |
| 411 | + regulator-max-microvolt = <1800000>; | |
| 412 | + regulator-always-on; | |
| 413 | + }; | |
| 414 | + | |
| 415 | + ldo15_reg: LDO15 { | |
| 416 | + regulator-name = "P1.0V_LDO_OUT15"; | |
| 417 | + regulator-min-microvolt = <1000000>; | |
| 418 | + regulator-max-microvolt = <1000000>; | |
| 419 | + regulator-always-on; | |
| 420 | + }; | |
| 421 | + | |
| 422 | + ldo16_reg: LDO16 { | |
| 423 | + regulator-name = "P1.8V_LDO_OUT16"; | |
| 424 | + regulator-min-microvolt = <1800000>; | |
| 425 | + regulator-max-microvolt = <1800000>; | |
| 426 | + regulator-always-on; | |
| 427 | + }; | |
| 428 | + | |
| 429 | + buck1_reg: BUCK1 { | |
| 430 | + regulator-name = "vdd_mif"; | |
| 431 | + regulator-min-microvolt = <950000>; | |
| 432 | + regulator-max-microvolt = <1300000>; | |
| 433 | + regulator-always-on; | |
| 434 | + regulator-boot-on; | |
| 435 | + }; | |
| 436 | + | |
| 437 | + buck2_reg: BUCK2 { | |
| 438 | + regulator-name = "vdd_arm"; | |
| 439 | + regulator-min-microvolt = <850000>; | |
| 440 | + regulator-max-microvolt = <1350000>; | |
| 441 | + regulator-always-on; | |
| 442 | + regulator-boot-on; | |
| 443 | + }; | |
| 444 | + | |
| 445 | + buck3_reg: BUCK3 { | |
| 446 | + regulator-name = "vdd_int"; | |
| 447 | + regulator-min-microvolt = <900000>; | |
| 448 | + regulator-max-microvolt = <1200000>; | |
| 449 | + regulator-always-on; | |
| 450 | + regulator-boot-on; | |
| 451 | + }; | |
| 452 | + | |
| 453 | + buck4_reg: BUCK4 { | |
| 454 | + regulator-name = "vdd_g3d"; | |
| 455 | + regulator-min-microvolt = <850000>; | |
| 456 | + regulator-max-microvolt = <1300000>; | |
| 457 | + regulator-always-on; | |
| 458 | + regulator-boot-on; | |
| 459 | + }; | |
| 460 | + | |
| 461 | + buck5_reg: BUCK5 { | |
| 462 | + regulator-name = "P1.8V_BUCK_OUT5"; | |
| 463 | + regulator-min-microvolt = <1800000>; | |
| 464 | + regulator-max-microvolt = <1800000>; | |
| 465 | + regulator-always-on; | |
| 466 | + regulator-boot-on; | |
| 467 | + }; | |
| 468 | + | |
| 469 | + buck6_reg: BUCK6 { | |
| 470 | + regulator-name = "P1.35V_BUCK_OUT6"; | |
| 471 | + regulator-min-microvolt = <1350000>; | |
| 472 | + regulator-max-microvolt = <1350000>; | |
| 473 | + regulator-always-on; | |
| 474 | + }; | |
| 475 | + | |
| 476 | + buck7_reg: BUCK7 { | |
| 477 | + regulator-name = "P2.0V_BUCK_OUT7"; | |
| 478 | + regulator-min-microvolt = <2000000>; | |
| 479 | + regulator-max-microvolt = <2000000>; | |
| 480 | + regulator-always-on; | |
| 481 | + }; | |
| 482 | + | |
| 483 | + buck8_reg: BUCK8 { | |
| 484 | + regulator-name = "P2.85V_BUCK_OUT8"; | |
| 485 | + regulator-min-microvolt = <2850000>; | |
| 486 | + regulator-max-microvolt = <2850000>; | |
| 487 | + regulator-always-on; | |
| 488 | + }; | |
| 489 | + }; | |
| 490 | + }; | |
| 491 | +}; | |
| 492 | + | |
| 493 | +&i2c_1 { | |
| 494 | + trackpad { | |
| 495 | + reg = <0x67>; | |
| 496 | + compatible = "cypress,cyapa"; | |
| 497 | + interrupts = <2 0>; | |
| 498 | + interrupt-parent = <&gpx1>; | |
| 499 | + wakeup-source; | |
| 500 | + }; | |
| 501 | +}; | |
| 502 | + | |
| 503 | +&pinctrl_0 { | |
| 504 | + max77686_irq: max77686-irq { | |
| 505 | + samsung,pins = "gpx3-2"; | |
| 506 | + samsung,pin-function = <0>; | |
| 507 | + samsung,pin-pud = <0>; | |
| 508 | + samsung,pin-drv = <0>; | |
| 509 | + }; | |
| 510 | +}; | |
| 511 | + | |
| 512 | +#include "cros-ec-keyboard.dtsi" | |
| @@ -231,6 +231,11 @@ · 230 unmodified lines | ||
| 231 | 231 | interrupts = <0 243 0>; |
| 232 | 232 | }; |
| 233 | 233 | |
| 234 | + pmu_system_controller: system-controller@10D50000 { | |
| 235 | + compatible = "samsung,exynos5260-pmu", "syscon"; | |
| 236 | + reg = <0x10D50000 0x10000>; | |
| 237 | + }; | |
| 238 | + | |
| 234 | 239 | uart0: serial@12C00000 { |
| 235 | 240 | compatible = "samsung,exynos4210-uart"; |
| 236 | 241 | reg = <0x12C00000 0x100>; |
| @@ -34,24 +34,28 @@ · 33 unmodified lines | ||
| 34 | 34 | device_type = "cpu"; |
| 35 | 35 | compatible = "arm,cortex-a15"; |
| 36 | 36 | reg = <0x0>; |
| 37 | + clock-frequency = <1600000000>; | |
| 37 | 38 | }; |
| 38 | 39 | |
| 39 | 40 | CPU1: cpu@1 { |
| 40 | 41 | device_type = "cpu"; |
| 41 | 42 | compatible = "arm,cortex-a15"; |
| 42 | 43 | reg = <0x1>; |
| 44 | + clock-frequency = <1600000000>; | |
| 43 | 45 | }; |
| 44 | 46 | |
| 45 | 47 | CPU2: cpu@2 { |
| 46 | 48 | device_type = "cpu"; |
| 47 | 49 | compatible = "arm,cortex-a15"; |
| 48 | 50 | reg = <0x2>; |
| 51 | + clock-frequency = <1600000000>; | |
| 49 | 52 | }; |
| 50 | 53 | |
| 51 | 54 | CPU3: cpu@3 { |
| 52 | 55 | device_type = "cpu"; |
| 53 | 56 | compatible = "arm,cortex-a15"; |
| 54 | 57 | reg = <0x3>; |
| 58 | + clock-frequency = <1600000000>; | |
| 55 | 59 | }; |
| 56 | 60 | }; |
| 57 | 61 | |
| @@ -93,6 +97,11 @@ · 35 unmodified lines | ||
| 93 | 97 | reg = <0x10000000 0x100>; |
| 94 | 98 | }; |
| 95 | 99 | |
| 100 | + pmu_system_controller: system-controller@10040000 { | |
| 101 | + compatible = "samsung,exynos5410-pmu", "syscon"; | |
| 102 | + reg = <0x10040000 0x5000>; | |
| 103 | + }; | |
| 104 | + | |
| 96 | 105 | mct: mct@101C0000 { |
| 97 | 106 | compatible = "samsung,exynos4210-mct"; |
| 98 | 107 | reg = <0x101C0000 0xB00>; |
| @@ -25,8 +25,18 @@ · 24 unmodified lines | ||
| 25 | 25 | "google,pit", "google,peach","samsung,exynos5420", |
| 26 | 26 | "samsung,exynos5"; |
| 27 | 27 | |
| 28 | − memory { | |
| 29 | − reg = <0x20000000 0x80000000>; | |
| 28 | + aliases { | |
| 29 | + /* Assign 20 so we don't get confused w/ builtin ones */ | |
| 30 | + i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; | |
| 31 | + }; | |
| 32 | + | |
| 33 | + backlight { | |
| 34 | + compatible = "pwm-backlight"; | |
| 35 | + pwms = <&pwm 0 1000000 0>; | |
| 36 | + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; | |
| 37 | + default-brightness-level = <7>; | |
| 38 | + pinctrl-0 = <&pwm0_out>; | |
| 39 | + pinctrl-names = "default"; | |
| 30 | 40 | }; |
| 31 | 41 | |
| 32 | 42 | fixed-rate-clocks { |
| @@ -50,18 +60,14 @@ · 17 unmodified lines | ||
| 50 | 60 | }; |
| 51 | 61 | }; |
| 52 | 62 | |
| 53 | − backlight { | |
| 54 | − compatible = "pwm-backlight"; | |
| 55 | − pwms = <&pwm 0 1000000 0>; | |
| 56 | − brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; | |
| 57 | − default-brightness-level = <7>; | |
| 58 | − pinctrl-0 = <&pwm0_out>; | |
| 59 | − pinctrl-names = "default"; | |
| 63 | + memory { | |
| 64 | + reg = <0x20000000 0x80000000>; | |
| 60 | 65 | }; |
| 61 | 66 | |
| 62 | 67 | sound { |
| 63 | 68 | compatible = "google,snow-audio-max98090"; |
| 64 | 69 | |
| 70 | + samsung,model = "Peach-Pit-I2S-MAX98090"; | |
| 65 | 71 | samsung,i2s-controller = <&i2s0>; |
| 66 | 72 | samsung,audio-codec = <&max98090>; |
| 67 | 73 | }; |
| @@ -87,66 +93,92 @@ · 19 unmodified lines | ||
| 87 | 93 | pinctrl-0 = <&usb301_vbus_en>; |
| 88 | 94 | enable-active-high; |
| 89 | 95 | }; |
| 90 | −}; | |
| 91 | 96 | |
| 92 | −&pinctrl_0 { | |
| 93 | − max98090_irq: max98090-irq { | |
| 94 | − samsung,pins = "gpx0-2"; | |
| 95 | − samsung,pin-function = <0>; | |
| 96 | − samsung,pin-pud = <0>; | |
| 97 | − samsung,pin-drv = <0>; | |
| 97 | + vbat: fixed-regulator { | |
| 98 | + compatible = "regulator-fixed"; | |
| 99 | + regulator-name = "vbat-supply"; | |
| 100 | + regulator-boot-on; | |
| 101 | + regulator-always-on; | |
| 98 | 102 | }; |
| 103 | +}; | |
| 99 | 104 | |
| 100 | − tpm_irq: tpm-irq { | |
| 101 | − samsung,pins = "gpx1-0"; | |
| 102 | − samsung,pin-function = <0>; | |
| 103 | − samsung,pin-pud = <0>; | |
| 104 | − samsung,pin-drv = <0>; | |
| 105 | − }; | |
| 105 | +&dp { | |
| 106 | + status = "okay"; | |
| 107 | + pinctrl-names = "default"; | |
| 108 | + pinctrl-0 = <&dp_hpd_gpio>; | |
| 109 | + samsung,color-space = <0>; | |
| 110 | + samsung,dynamic-range = <0>; | |
| 111 | + samsung,ycbcr-coeff = <0>; | |
| 112 | + samsung,color-depth = <1>; | |
| 113 | + samsung,link-rate = <0x06>; | |
| 114 | + samsung,lane-count = <2>; | |
| 115 | + samsung,hpd-gpio = <&gpx2 6 0>; | |
| 106 | 116 | |
| 107 | − power_key_irq: power-key-irq { | |
| 108 | − samsung,pins = "gpx1-2"; | |
| 109 | − samsung,pin-function = <0>; | |
| 110 | − samsung,pin-pud = <0>; | |
| 111 | − samsung,pin-drv = <0>; | |
| 112 | − }; | |
| 117 | + display-timings { | |
| 118 | + native-mode = <&timing1>; | |
| 113 | 119 | |
| 114 | − hdmi_hpd_irq: hdmi-hpd-irq { | |
| 115 | − samsung,pins = "gpx3-7"; | |
| 116 | − samsung,pin-function = <0>; | |
| 117 | − samsung,pin-pud = <1>; | |
| 118 | − samsung,pin-drv = <0>; | |
| 120 | + timing1: timing@1 { | |
| 121 | + clock-frequency = <70589280>; | |
| 122 | + hactive = <1366>; | |
| 123 | + vactive = <768>; | |
| 124 | + hfront-porch = <40>; | |
| 125 | + hback-porch = <40>; | |
| 126 | + hsync-len = <32>; | |
| 127 | + vback-porch = <10>; | |
| 128 | + vfront-porch = <12>; | |
| 129 | + vsync-len = <6>; | |
| 130 | + }; | |
| 119 | 131 | }; |
| 132 | +}; | |
| 120 | 133 | |
| 121 | − dp_hpd_gpio: dp_hpd_gpio { | |
| 122 | − samsung,pins = "gpx2-6"; | |
| 123 | − samsung,pin-function = <0>; | |
| 124 | − samsung,pin-pud = <3>; | |
| 125 | − samsung,pin-drv = <0>; | |
| 126 | − }; | |
| 134 | +&fimd { | |
| 135 | + status = "okay"; | |
| 136 | + samsung,invert-vclk; | |
| 127 | 137 | }; |
| 128 | 138 | |
| 129 | −&pinctrl_3 { | |
| 130 | − usb300_vbus_en: usb300-vbus-en { | |
| 131 | − samsung,pins = "gph0-0"; | |
| 132 | − samsung,pin-function = <1>; | |
| 133 | − samsung,pin-pud = <0>; | |
| 134 | − samsung,pin-drv = <0>; | |
| 139 | +&hdmi { | |
| 140 | + status = "okay"; | |
| 141 | + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; | |
| 142 | + pinctrl-names = "default"; | |
| 143 | + pinctrl-0 = <&hdmi_hpd_irq>; | |
| 144 | + ddc = <&i2c_2>; | |
| 145 | +}; | |
| 146 | + | |
| 147 | +&hsi2c_7 { | |
| 148 | + status = "okay"; | |
| 149 | + | |
| 150 | + max98090: codec@10 { | |
| 151 | + compatible = "maxim,max98090"; | |
| 152 | + reg = <0x10>; | |
| 153 | + interrupts = <2 0>; | |
| 154 | + interrupt-parent = <&gpx0>; | |
| 155 | + pinctrl-names = "default"; | |
| 156 | + pinctrl-0 = <&max98090_irq>; | |
| 135 | 157 | }; |
| 158 | +}; | |
| 136 | 159 | |
| 137 | − usb301_vbus_en: usb301-vbus-en { | |
| 138 | − samsung,pins = "gph0-1"; | |
| 139 | − samsung,pin-function = <1>; | |
| 140 | − samsung,pin-pud = <0>; | |
| 141 | − samsung,pin-drv = <0>; | |
| 160 | +&hsi2c_9 { | |
| 161 | + status = "okay"; | |
| 162 | + clock-frequency = <400000>; | |
| 163 | + | |
| 164 | + tpm@20 { | |
| 165 | + compatible = "infineon,slb9645tt"; | |
| 166 | + reg = <0x20>; | |
| 167 | + | |
| 168 | + /* Unused irq; but still need to configure the pins */ | |
| 169 | + pinctrl-names = "default"; | |
| 170 | + pinctrl-0 = <&tpm_irq>; | |
| 142 | 171 | }; |
| 143 | 172 | }; |
| 144 | 173 | |
| 145 | −&rtc { | |
| 174 | +&i2c_2 { | |
| 146 | 175 | status = "okay"; |
| 176 | + samsung,i2c-sda-delay = <100>; | |
| 177 | + samsung,i2c-max-bus-freq = <66000>; | |
| 178 | + samsung,i2c-slave-addr = <0x50>; | |
| 147 | 179 | }; |
| 148 | 180 | |
| 149 | −&uart_3 { | |
| 181 | +&i2s0 { | |
| 150 | 182 | status = "okay"; |
| 151 | 183 | }; |
| 152 | 184 | |
| @@ -189,46 +221,210 @@ · 36 unmodified lines | ||
| 189 | 221 | }; |
| 190 | 222 | }; |
| 191 | 223 | |
| 192 | −&hsi2c_7 { | |
| 193 | − status = "okay"; | |
| 194 | 224 | |
| 195 | − max98090: codec@10 { | |
| 196 | − compatible = "maxim,max98090"; | |
| 197 | − reg = <0x10>; | |
| 198 | − interrupts = <2 0>; | |
| 199 | − interrupt-parent = <&gpx0>; | |
| 200 | − pinctrl-names = "default"; | |
| 201 | − pinctrl-0 = <&max98090_irq>; | |
| 225 | +&pinctrl_0 { | |
| 226 | + pinctrl-names = "default"; | |
| 227 | + pinctrl-0 = <&mask_tpm_reset>; | |
| 228 | + | |
| 229 | + max98090_irq: max98090-irq { | |
| 230 | + samsung,pins = "gpx0-2"; | |
| 231 | + samsung,pin-function = <0>; | |
| 232 | + samsung,pin-pud = <0>; | |
| 233 | + samsung,pin-drv = <0>; | |
| 234 | + }; | |
| 235 | + | |
| 236 | + /* We need GPX0_6 to be low at sleep time; just keep it low always */ | |
| 237 | + mask_tpm_reset: mask-tpm-reset { | |
| 238 | + samsung,pins = "gpx0-6"; | |
| 239 | + samsung,pin-function = <1>; | |
| 240 | + samsung,pin-pud = <0>; | |
| 241 | + samsung,pin-drv = <0>; | |
| 242 | + samsung,pin-val = <0>; | |
| 243 | + }; | |
| 244 | + | |
| 245 | + tpm_irq: tpm-irq { | |
| 246 | + samsung,pins = "gpx1-0"; | |
| 247 | + samsung,pin-function = <0>; | |
| 248 | + samsung,pin-pud = <0>; | |
| 249 | + samsung,pin-drv = <0>; | |
| 250 | + }; | |
| 251 | + | |
| 252 | + power_key_irq: power-key-irq { | |
| 253 | + samsung,pins = "gpx1-2"; | |
| 254 | + samsung,pin-function = <0>; | |
| 255 | + samsung,pin-pud = <0>; | |
| 256 | + samsung,pin-drv = <0>; | |
| 257 | + }; | |
| 258 | + | |
| 259 | + ec_irq: ec-irq { | |
| 260 | + samsung,pins = "gpx1-5"; | |
| 261 | + samsung,pin-function = <0>; | |
| 262 | + samsung,pin-pud = <0>; | |
| 263 | + samsung,pin-drv = <0>; | |
| 264 | + }; | |
| 265 | + | |
| 266 | + tps65090_irq: tps65090-irq { | |
| 267 | + samsung,pins = "gpx2-5"; | |
| 268 | + samsung,pin-function = <0>; | |
| 269 | + samsung,pin-pud = <0>; | |
| 270 | + samsung,pin-drv = <0>; | |
| 271 | + }; | |
| 272 | + | |
| 273 | + dp_hpd_gpio: dp_hpd_gpio { | |
| 274 | + samsung,pins = "gpx2-6"; | |
| 275 | + samsung,pin-function = <0>; | |
| 276 | + samsung,pin-pud = <3>; | |
| 277 | + samsung,pin-drv = <0>; | |
| 278 | + }; | |
| 279 | + | |
| 280 | + hdmi_hpd_irq: hdmi-hpd-irq { | |
| 281 | + samsung,pins = "gpx3-7"; | |
| 282 | + samsung,pin-function = <0>; | |
| 283 | + samsung,pin-pud = <1>; | |
| 284 | + samsung,pin-drv = <0>; | |
| 202 | 285 | }; |
| 203 | 286 | }; |
| 204 | 287 | |
| 205 | −&hsi2c_9 { | |
| 206 | − status = "okay"; | |
| 207 | − clock-frequency = <400000>; | |
| 288 | +&pinctrl_3 { | |
| 289 | + /* Drive SPI lines at x2 for better integrity */ | |
| 290 | + spi2-bus { | |
| 291 | + samsung,pin-drv = <2>; | |
| 292 | + }; | |
| 208 | 293 | |
| 209 | − tpm@20 { | |
| 210 | − compatible = "infineon,slb9645tt"; | |
| 211 | − reg = <0x20>; | |
| 294 | + /* Drive SPI chip select at x2 for better integrity */ | |
| 295 | + ec_spi_cs: ec-spi-cs { | |
| 296 | + samsung,pins = "gpb1-2"; | |
| 297 | + samsung,pin-function = <1>; | |
| 298 | + samsung,pin-pud = <0>; | |
| 299 | + samsung,pin-drv = <2>; | |
| 300 | + }; | |
| 212 | 301 | |
| 213 | − /* Unused irq; but still need to configure the pins */ | |
| 214 | − pinctrl-names = "default"; | |
| 215 | − pinctrl-0 = <&tpm_irq>; | |
| 302 | + usb300_vbus_en: usb300-vbus-en { | |
| 303 | + samsung,pins = "gph0-0"; | |
| 304 | + samsung,pin-function = <1>; | |
| 305 | + samsung,pin-pud = <0>; | |
| 306 | + samsung,pin-drv = <0>; | |
| 307 | + }; | |
| 308 | + | |
| 309 | + usb301_vbus_en: usb301-vbus-en { | |
| 310 | + samsung,pins = "gph0-1"; | |
| 311 | + samsung,pin-function = <1>; | |
| 312 | + samsung,pin-pud = <0>; | |
| 313 | + samsung,pin-drv = <0>; | |
| 216 | 314 | }; |
| 217 | 315 | }; |
| 218 | 316 | |
| 219 | −&i2c_2 { | |
| 317 | +&rtc { | |
| 220 | 318 | status = "okay"; |
| 221 | − samsung,i2c-sda-delay = <100>; | |
| 222 | − samsung,i2c-max-bus-freq = <66000>; | |
| 223 | − samsung,i2c-slave-addr = <0x50>; | |
| 224 | 319 | }; |
| 225 | 320 | |
| 226 | −&hdmi { | |
| 321 | +&spi_2 { | |
| 322 | + status = "okay"; | |
| 323 | + num-cs = <1>; | |
| 324 | + samsung,spi-src-clk = <0>; | |
| 325 | + cs-gpios = <&gpb1 2 0>; | |
| 326 | + | |
| 327 | + cros_ec: cros-ec@0 { | |
| 328 | + compatible = "google,cros-ec-spi"; | |
| 329 | + interrupt-parent = <&gpx1>; | |
| 330 | + interrupts = <5 0>; | |
| 331 | + pinctrl-names = "default"; | |
| 332 | + pinctrl-0 = <&ec_spi_cs &ec_irq>; | |
| 333 | + reg = <0>; | |
| 334 | + spi-max-frequency = <3125000>; | |
| 335 | + | |
| 336 | + controller-data { | |
| 337 | + samsung,spi-feedback-delay = <1>; | |
| 338 | + }; | |
| 339 | + | |
| 340 | + i2c-tunnel { | |
| 341 | + compatible = "google,cros-ec-i2c-tunnel"; | |
| 342 | + #address-cells = <1>; | |
| 343 | + #size-cells = <0>; | |
| 344 | + google,remote-bus = <0>; | |
| 345 | + | |
| 346 | + battery: sbs-battery@b { | |
| 347 | + compatible = "sbs,sbs-battery"; | |
| 348 | + reg = <0xb>; | |
| 349 | + sbs,poll-retry-count = <1>; | |
| 350 | + sbs,i2c-retry-count = <2>; | |
| 351 | + }; | |
| 352 | + | |
| 353 | + power-regulator@48 { | |
| 354 | + compatible = "ti,tps65090"; | |
| 355 | + reg = <0x48>; | |
| 356 | + | |
| 357 | + /* | |
| 358 | + * Config irq to disable internal pulls | |
| 359 | + * even though we run in polling mode. | |
| 360 | + */ | |
| 361 | + pinctrl-names = "default"; | |
| 362 | + pinctrl-0 = <&tps65090_irq>; | |
| 363 | + | |
| 364 | + vsys1-supply = <&vbat>; | |
| 365 | + vsys2-supply = <&vbat>; | |
| 366 | + vsys3-supply = <&vbat>; | |
| 367 | + infet1-supply = <&vbat>; | |
| 368 | + infet2-supply = <&vbat>; | |
| 369 | + infet3-supply = <&vbat>; | |
| 370 | + infet4-supply = <&vbat>; | |
| 371 | + infet5-supply = <&vbat>; | |
| 372 | + infet6-supply = <&vbat>; | |
| 373 | + infet7-supply = <&vbat>; | |
| 374 | + vsys-l1-supply = <&vbat>; | |
| 375 | + vsys-l2-supply = <&vbat>; | |
| 376 | + | |
| 377 | + regulators { | |
| 378 | + tps65090_dcdc1: dcdc1 { | |
| 379 | + ti,enable-ext-control; | |
| 380 | + }; | |
| 381 | + tps65090_dcdc2: dcdc2 { | |
| 382 | + ti,enable-ext-control; | |
| 383 | + }; | |
| 384 | + tps65090_dcdc3: dcdc3 { | |
| 385 | + ti,enable-ext-control; | |
| 386 | + }; | |
| 387 | + tps65090_fet1: fet1 { | |
| 388 | + regulator-name = "vcd_led"; | |
| 389 | + }; | |
| 390 | + tps65090_fet2: fet2 { | |
| 391 | + regulator-name = "video_mid"; | |
| 392 | + regulator-always-on; | |
| 393 | + }; | |
| 394 | + tps65090_fet3: fet3 { | |
| 395 | + regulator-name = "wwan_r"; | |
| 396 | + regulator-always-on; | |
| 397 | + }; | |
| 398 | + tps65090_fet4: fet4 { | |
| 399 | + regulator-name = "sdcard"; | |
| 400 | + regulator-always-on; | |
| 401 | + }; | |
| 402 | + tps65090_fet5: fet5 { | |
| 403 | + regulator-name = "camout"; | |
| 404 | + }; | |
| 405 | + tps65090_fet6: fet6 { | |
| 406 | + regulator-name = "lcd_vdd"; | |
| 407 | + }; | |
| 408 | + tps65090_fet7: fet7 { | |
| 409 | + regulator-name = "video_mid_1a"; | |
| 410 | + regulator-always-on; | |
| 411 | + }; | |
| 412 | + tps65090_ldo1: ldo1 { | |
| 413 | + }; | |
| 414 | + tps65090_ldo2: ldo2 { | |
| 415 | + }; | |
| 416 | + }; | |
| 417 | + | |
| 418 | + charger { | |
| 419 | + compatible = "ti,tps65090-charger"; | |
| 420 | + }; | |
| 421 | + }; | |
| 422 | + }; | |
| 423 | + }; | |
| 424 | +}; | |
| 425 | + | |
| 426 | +&uart_3 { | |
| 227 | 427 | status = "okay"; |
| 228 | − hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; | |
| 229 | − pinctrl-names = "default"; | |
| 230 | − pinctrl-0 = <&hdmi_hpd_irq>; | |
| 231 | − ddc = <&i2c_2>; | |
| 232 | 428 | }; |
| 233 | 429 | |
| 234 | 430 | &usbdrd_phy0 { |
| @@ -248,40 +444,4 @@ · 13 unmodified lines | ||
| 248 | 444 | timeout-sec = <32>; |
| 249 | 445 | }; |
| 250 | 446 | |
| 251 | −&i2s0 { | |
| 252 | − status = "okay"; | |
| 253 | −}; | |
| 254 | − | |
| 255 | −&fimd { | |
| 256 | − status = "okay"; | |
| 257 | − samsung,invert-vclk; | |
| 258 | −}; | |
| 259 | − | |
| 260 | −&dp { | |
| 261 | − status = "okay"; | |
| 262 | − pinctrl-names = "default"; | |
| 263 | − pinctrl-0 = <&dp_hpd_gpio>; | |
| 264 | − samsung,color-space = <0>; | |
| 265 | − samsung,dynamic-range = <0>; | |
| 266 | − samsung,ycbcr-coeff = <0>; | |
| 267 | − samsung,color-depth = <1>; | |
| 268 | − samsung,link-rate = <0x06>; | |
| 269 | − samsung,lane-count = <2>; | |
| 270 | − samsung,hpd-gpio = <&gpx2 6 0>; | |
| 271 | − | |
| 272 | − display-timings { | |
| 273 | − native-mode = <&timing1>; | |
| 274 | − | |
| 275 | − timing1: timing@1 { | |
| 276 | − clock-frequency = <70589280>; | |
| 277 | − hactive = <1366>; | |
| 278 | − vactive = <768>; | |
| 279 | − hfront-porch = <40>; | |
| 280 | − hback-porch = <40>; | |
| 281 | − hsync-len = <32>; | |
| 282 | − vback-porch = <10>; | |
| 283 | − vfront-porch = <12>; | |
| 284 | − vsync-len = <6>; | |
| 285 | − }; | |
| 286 | − }; | |
| 287 | −}; | |
| 447 | +#include "cros-ec-keyboard.dtsi" | |
| @@ -265,11 +265,6 @@ · 264 unmodified lines | ||
| 265 | 265 | clock-names = "oscclk", "pclk0", "clk0"; |
| 266 | 266 | }; |
| 267 | 267 | |
| 268 | − disp_pd: power-domain@100440C0 { | |
| 269 | − compatible = "samsung,exynos4210-pd"; | |
| 270 | − reg = <0x100440C0 0x20>; | |
| 271 | − }; | |
| 272 | − | |
| 273 | 268 | msc_pd: power-domain@10044120 { |
| 274 | 269 | compatible = "samsung,exynos4210-pd"; |
| 275 | 270 | reg = <0x10044120 0x20>; |
| @@ -520,8 +515,26 @@ · 244 unmodified lines | ||
| 520 | 515 | phy-names = "dp"; |
| 521 | 516 | }; |
| 522 | 517 | |
| 518 | + mipi_phy: video-phy@10040714 { | |
| 519 | + compatible = "samsung,s5pv210-mipi-video-phy"; | |
| 520 | + reg = <0x10040714 12>; | |
| 521 | + #phy-cells = <1>; | |
| 522 | + }; | |
| 523 | + | |
| 524 | + dsi@14500000 { | |
| 525 | + compatible = "samsung,exynos5410-mipi-dsi"; | |
| 526 | + reg = <0x14500000 0x10000>; | |
| 527 | + interrupts = <0 82 0>; | |
| 528 | + phys = <&mipi_phy 1>; | |
| 529 | + phy-names = "dsim"; | |
| 530 | + clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; | |
| 531 | + clock-names = "bus_clk", "pll_clk"; | |
| 532 | + #address-cells = <1>; | |
| 533 | + #size-cells = <0>; | |
| 534 | + status = "disabled"; | |
| 535 | + }; | |
| 536 | + | |
| 523 | 537 | fimd: fimd@14400000 { |
| 524 | − samsung,power-domain = <&disp_pd>; | |
| 525 | 538 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
| 526 | 539 | clock-names = "sclk_fimd", "fimd"; |
| 527 | 540 | }; |
| @@ -23,8 +23,18 @@ · 22 unmodified lines | ||
| 23 | 23 | "google,pi", "google,peach", "samsung,exynos5800", |
| 24 | 24 | "samsung,exynos5"; |
| 25 | 25 | |
| 26 | − memory { | |
| 27 | − reg = <0x20000000 0x80000000>; | |
| 26 | + aliases { | |
| 27 | + /* Assign 20 so we don't get confused w/ builtin ones */ | |
| 28 | + i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; | |
| 29 | + }; | |
| 30 | + | |
| 31 | + backlight { | |
| 32 | + compatible = "pwm-backlight"; | |
| 33 | + pwms = <&pwm 0 1000000 0>; | |
| 34 | + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; | |
| 35 | + default-brightness-level = <7>; | |
| 36 | + pinctrl-0 = <&pwm0_out>; | |
| 37 | + pinctrl-names = "default"; | |
| 28 | 38 | }; |
| 29 | 39 | |
| 30 | 40 | fixed-rate-clocks { |
| @@ -48,13 +58,16 @@ · 17 unmodified lines | ||
| 48 | 58 | }; |
| 49 | 59 | }; |
| 50 | 60 | |
| 51 | − backlight { | |
| 52 | − compatible = "pwm-backlight"; | |
| 53 | − pwms = <&pwm 0 1000000 0>; | |
| 54 | − brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; | |
| 55 | − default-brightness-level = <7>; | |
| 56 | − pinctrl-0 = <&pwm0_out>; | |
| 57 | − pinctrl-names = "default"; | |
| 61 | + memory { | |
| 62 | + reg = <0x20000000 0x80000000>; | |
| 63 | + }; | |
| 64 | + | |
| 65 | + sound { | |
| 66 | + compatible = "google,snow-audio-max98091"; | |
| 67 | + | |
| 68 | + samsung,model = "Peach-Pi-I2S-MAX98091"; | |
| 69 | + samsung,i2s-controller = <&i2s0>; | |
| 70 | + samsung,audio-codec = <&max98091>; | |
| 58 | 71 | }; |
| 59 | 72 | |
| 60 | 73 | usb300_vbus_reg: regulator-usb300 { |
| @@ -78,59 +91,92 @@ · 17 unmodified lines | ||
| 78 | 91 | pinctrl-0 = <&usb301_vbus_en>; |
| 79 | 92 | enable-active-high; |
| 80 | 93 | }; |
| 81 | −}; | |
| 82 | 94 | |
| 83 | −&pinctrl_0 { | |
| 84 | − tpm_irq: tpm-irq { | |
| 85 | − samsung,pins = "gpx1-0"; | |
| 86 | − samsung,pin-function = <0>; | |
| 87 | − samsung,pin-pud = <0>; | |
| 88 | − samsung,pin-drv = <0>; | |
| 95 | + vbat: fixed-regulator { | |
| 96 | + compatible = "regulator-fixed"; | |
| 97 | + regulator-name = "vbat-supply"; | |
| 98 | + regulator-boot-on; | |
| 99 | + regulator-always-on; | |
| 89 | 100 | }; |
| 101 | +}; | |
| 90 | 102 | |
| 91 | − power_key_irq: power-key-irq { | |
| 92 | − samsung,pins = "gpx1-2"; | |
| 93 | − samsung,pin-function = <0>; | |
| 94 | − samsung,pin-pud = <0>; | |
| 95 | − samsung,pin-drv = <0>; | |
| 96 | − }; | |
| 103 | +&dp { | |
| 104 | + status = "okay"; | |
| 105 | + pinctrl-names = "default"; | |
| 106 | + pinctrl-0 = <&dp_hpd_gpio>; | |
| 107 | + samsung,color-space = <0>; | |
| 108 | + samsung,dynamic-range = <0>; | |
| 109 | + samsung,ycbcr-coeff = <0>; | |
| 110 | + samsung,color-depth = <1>; | |
| 111 | + samsung,link-rate = <0x0a>; | |
| 112 | + samsung,lane-count = <2>; | |
| 113 | + samsung,hpd-gpio = <&gpx2 6 0>; | |
| 97 | 114 | |
| 98 | − dp_hpd_gpio: dp_hpd_gpio { | |
| 99 | − samsung,pins = "gpx2-6"; | |
| 100 | − samsung,pin-function = <0>; | |
| 101 | − samsung,pin-pud = <3>; | |
| 102 | − samsung,pin-drv = <0>; | |
| 103 | − }; | |
| 115 | + display-timings { | |
| 116 | + native-mode = <&timing1>; | |
| 104 | 117 | |
| 105 | − hdmi_hpd_irq: hdmi-hpd-irq { | |
| 106 | − samsung,pins = "gpx3-7"; | |
| 107 | − samsung,pin-function = <0>; | |
| 108 | − samsung,pin-pud = <1>; | |
| 109 | − samsung,pin-drv = <0>; | |
| 118 | + timing1: timing@1 { | |
| 119 | + clock-frequency = <150660000>; | |
| 120 | + hactive = <1920>; | |
| 121 | + vactive = <1080>; | |
| 122 | + hfront-porch = <60>; | |
| 123 | + hback-porch = <172>; | |
| 124 | + hsync-len = <80>; | |
| 125 | + vback-porch = <25>; | |
| 126 | + vfront-porch = <10>; | |
| 127 | + vsync-len = <10>; | |
| 128 | + }; | |
| 110 | 129 | }; |
| 111 | 130 | }; |
| 112 | 131 | |
| 113 | −&pinctrl_3 { | |
| 114 | − usb300_vbus_en: usb300-vbus-en { | |
| 115 | − samsung,pins = "gph0-0"; | |
| 116 | − samsung,pin-function = <1>; | |
| 117 | − samsung,pin-pud = <0>; | |
| 118 | − samsung,pin-drv = <0>; | |
| 132 | +&fimd { | |
| 133 | + status = "okay"; | |
| 134 | + samsung,invert-vclk; | |
| 135 | +}; | |
| 136 | + | |
| 137 | +&hdmi { | |
| 138 | + status = "okay"; | |
| 139 | + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; | |
| 140 | + pinctrl-names = "default"; | |
| 141 | + pinctrl-0 = <&hdmi_hpd_irq>; | |
| 142 | + ddc = <&i2c_2>; | |
| 143 | +}; | |
| 144 | + | |
| 145 | +&hsi2c_7 { | |
| 146 | + status = "okay"; | |
| 147 | + | |
| 148 | + max98091: codec@10 { | |
| 149 | + compatible = "maxim,max98091"; | |
| 150 | + reg = <0x10>; | |
| 151 | + interrupts = <2 0>; | |
| 152 | + interrupt-parent = <&gpx0>; | |
| 153 | + pinctrl-names = "default"; | |
| 154 | + pinctrl-0 = <&max98091_irq>; | |
| 119 | 155 | }; |
| 156 | +}; | |
| 120 | 157 | |
| 121 | − usb301_vbus_en: usb301-vbus-en { | |
| 122 | − samsung,pins = "gph0-1"; | |
| 123 | − samsung,pin-function = <1>; | |
| 124 | − samsung,pin-pud = <0>; | |
| 125 | − samsung,pin-drv = <0>; | |
| 158 | +&hsi2c_9 { | |
| 159 | + status = "okay"; | |
| 160 | + clock-frequency = <400000>; | |
| 161 | + | |
| 162 | + tpm@20 { | |
| 163 | + compatible = "infineon,slb9645tt"; | |
| 164 | + reg = <0x20>; | |
| 165 | + | |
| 166 | + /* Unused irq; but still need to configure the pins */ | |
| 167 | + pinctrl-names = "default"; | |
| 168 | + pinctrl-0 = <&tpm_irq>; | |
| 126 | 169 | }; |
| 127 | 170 | }; |
| 128 | 171 | |
| 129 | −&rtc { | |
| 172 | +&i2c_2 { | |
| 130 | 173 | status = "okay"; |
| 174 | + samsung,i2c-sda-delay = <100>; | |
| 175 | + samsung,i2c-max-bus-freq = <66000>; | |
| 176 | + samsung,i2c-slave-addr = <0x50>; | |
| 131 | 177 | }; |
| 132 | 178 | |
| 133 | −&uart_3 { | |
| 179 | +&i2s0 { | |
| 134 | 180 | status = "okay"; |
| 135 | 181 | }; |
| 136 | 182 | |
| @@ -173,66 +219,210 @@ · 36 unmodified lines | ||
| 173 | 219 | }; |
| 174 | 220 | }; |
| 175 | 221 | |
| 176 | −&dp { | |
| 177 | − status = "okay"; | |
| 222 | + | |
| 223 | +&pinctrl_0 { | |
| 178 | 224 | pinctrl-names = "default"; |
| 179 | − pinctrl-0 = <&dp_hpd_gpio>; | |
| 180 | − samsung,color-space = <0>; | |
| 181 | − samsung,dynamic-range = <0>; | |
| 182 | − samsung,ycbcr-coeff = <0>; | |
| 183 | − samsung,color-depth = <1>; | |
| 184 | − samsung,link-rate = <0x0a>; | |
| 185 | − samsung,lane-count = <2>; | |
| 186 | − samsung,hpd-gpio = <&gpx2 6 0>; | |
| 225 | + pinctrl-0 = <&mask_tpm_reset>; | |
| 187 | 226 | |
| 188 | − display-timings { | |
| 189 | − native-mode = <&timing1>; | |
| 227 | + max98091_irq: max98091-irq { | |
| 228 | + samsung,pins = "gpx0-2"; | |
| 229 | + samsung,pin-function = <0>; | |
| 230 | + samsung,pin-pud = <0>; | |
| 231 | + samsung,pin-drv = <0>; | |
| 232 | + }; | |
| 190 | 233 | |
| 191 | − timing1: timing@1 { | |
| 192 | − clock-frequency = <150660000>; | |
| 193 | − hactive = <1920>; | |
| 194 | − vactive = <1080>; | |
| 195 | − hfront-porch = <60>; | |
| 196 | − hback-porch = <172>; | |
| 197 | − hsync-len = <80>; | |
| 198 | − vback-porch = <25>; | |
| 199 | − vfront-porch = <10>; | |
| 200 | − vsync-len = <10>; | |
| 201 | − }; | |
| 234 | + /* We need GPX0_6 to be low at sleep time; just keep it low always */ | |
| 235 | + mask_tpm_reset: mask-tpm-reset { | |
| 236 | + samsung,pins = "gpx0-6"; | |
| 237 | + samsung,pin-function = <1>; | |
| 238 | + samsung,pin-pud = <0>; | |
| 239 | + samsung,pin-drv = <0>; | |
| 240 | + samsung,pin-val = <0>; | |
| 202 | 241 | }; |
| 203 | −}; | |
| 204 | 242 | |
| 205 | −&fimd { | |
| 206 | − status = "okay"; | |
| 207 | − samsung,invert-vclk; | |
| 243 | + tpm_irq: tpm-irq { | |
| 244 | + samsung,pins = "gpx1-0"; | |
| 245 | + samsung,pin-function = <0>; | |
| 246 | + samsung,pin-pud = <0>; | |
| 247 | + samsung,pin-drv = <0>; | |
| 248 | + }; | |
| 249 | + | |
| 250 | + power_key_irq: power-key-irq { | |
| 251 | + samsung,pins = "gpx1-2"; | |
| 252 | + samsung,pin-function = <0>; | |
| 253 | + samsung,pin-pud = <0>; | |
| 254 | + samsung,pin-drv = <0>; | |
| 255 | + }; | |
| 256 | + | |
| 257 | + ec_irq: ec-irq { | |
| 258 | + samsung,pins = "gpx1-5"; | |
| 259 | + samsung,pin-function = <0>; | |
| 260 | + samsung,pin-pud = <0>; | |
| 261 | + samsung,pin-drv = <0>; | |
| 262 | + }; | |
| 263 | + | |
| 264 | + tps65090_irq: tps65090-irq { | |
| 265 | + samsung,pins = "gpx2-5"; | |
| 266 | + samsung,pin-function = <0>; | |
| 267 | + samsung,pin-pud = <0>; | |
| 268 | + samsung,pin-drv = <0>; | |
| 269 | + }; | |
| 270 | + | |
| 271 | + dp_hpd_gpio: dp_hpd_gpio { | |
| 272 | + samsung,pins = "gpx2-6"; | |
| 273 | + samsung,pin-function = <0>; | |
| 274 | + samsung,pin-pud = <3>; | |
| 275 | + samsung,pin-drv = <0>; | |
| 276 | + }; | |
| 277 | + | |
| 278 | + hdmi_hpd_irq: hdmi-hpd-irq { | |
| 279 | + samsung,pins = "gpx3-7"; | |
| 280 | + samsung,pin-function = <0>; | |
| 281 | + samsung,pin-pud = <1>; | |
| 282 | + samsung,pin-drv = <0>; | |
| 283 | + }; | |
| 208 | 284 | }; |
| 209 | 285 | |
| 210 | −&hsi2c_9 { | |
| 211 | − status = "okay"; | |
| 212 | − clock-frequency = <400000>; | |
| 286 | +&pinctrl_3 { | |
| 287 | + /* Drive SPI lines at x2 for better integrity */ | |
| 288 | + spi2-bus { | |
| 289 | + samsung,pin-drv = <2>; | |
| 290 | + }; | |
| 213 | 291 | |
| 214 | − tpm@20 { | |
| 215 | − compatible = "infineon,slb9645tt"; | |
| 216 | − reg = <0x20>; | |
| 217 | − /* Unused irq; but still need to configure the pins */ | |
| 218 | − pinctrl-names = "default"; | |
| 219 | − pinctrl-0 = <&tpm_irq>; | |
| 292 | + /* Drive SPI chip select at x2 for better integrity */ | |
| 293 | + ec_spi_cs: ec-spi-cs { | |
| 294 | + samsung,pins = "gpb1-2"; | |
| 295 | + samsung,pin-function = <1>; | |
| 296 | + samsung,pin-pud = <0>; | |
| 297 | + samsung,pin-drv = <2>; | |
| 298 | + }; | |
| 299 | + | |
| 300 | + usb300_vbus_en: usb300-vbus-en { | |
| 301 | + samsung,pins = "gph0-0"; | |
| 302 | + samsung,pin-function = <1>; | |
| 303 | + samsung,pin-pud = <0>; | |
| 304 | + samsung,pin-drv = <0>; | |
| 305 | + }; | |
| 306 | + | |
| 307 | + usb301_vbus_en: usb301-vbus-en { | |
| 308 | + samsung,pins = "gph0-1"; | |
| 309 | + samsung,pin-function = <1>; | |
| 310 | + samsung,pin-pud = <0>; | |
| 311 | + samsung,pin-drv = <0>; | |
| 220 | 312 | }; |
| 221 | 313 | }; |
| 222 | 314 | |
| 223 | −&i2c_2 { | |
| 315 | +&rtc { | |
| 224 | 316 | status = "okay"; |
| 225 | − samsung,i2c-sda-delay = <100>; | |
| 226 | − samsung,i2c-max-bus-freq = <66000>; | |
| 227 | − samsung,i2c-slave-addr = <0x50>; | |
| 228 | 317 | }; |
| 229 | 318 | |
| 230 | −&hdmi { | |
| 319 | +&spi_2 { | |
| 320 | + status = "okay"; | |
| 321 | + num-cs = <1>; | |
| 322 | + samsung,spi-src-clk = <0>; | |
| 323 | + cs-gpios = <&gpb1 2 0>; | |
| 324 | + | |
| 325 | + cros_ec: cros-ec@0 { | |
| 326 | + compatible = "google,cros-ec-spi"; | |
| 327 | + interrupt-parent = <&gpx1>; | |
| 328 | + interrupts = <5 0>; | |
| 329 | + pinctrl-names = "default"; | |
| 330 | + pinctrl-0 = <&ec_spi_cs &ec_irq>; | |
| 331 | + reg = <0>; | |
| 332 | + spi-max-frequency = <3125000>; | |
| 333 | + | |
| 334 | + controller-data { | |
| 335 | + samsung,spi-feedback-delay = <1>; | |
| 336 | + }; | |
| 337 | + | |
| 338 | + i2c-tunnel { | |
| 339 | + compatible = "google,cros-ec-i2c-tunnel"; | |
| 340 | + #address-cells = <1>; | |
| 341 | + #size-cells = <0>; | |
| 342 | + google,remote-bus = <0>; | |
| 343 | + | |
| 344 | + battery: sbs-battery@b { | |
| 345 | + compatible = "sbs,sbs-battery"; | |
| 346 | + reg = <0xb>; | |
| 347 | + sbs,poll-retry-count = <1>; | |
| 348 | + sbs,i2c-retry-count = <2>; | |
| 349 | + }; | |
| 350 | + | |
| 351 | + power-regulator@48 { | |
| 352 | + compatible = "ti,tps65090"; | |
| 353 | + reg = <0x48>; | |
| 354 | + | |
| 355 | + /* | |
| 356 | + * Config irq to disable internal pulls | |
| 357 | + * even though we run in polling mode. | |
| 358 | + */ | |
| 359 | + pinctrl-names = "default"; | |
| 360 | + pinctrl-0 = <&tps65090_irq>; | |
| 361 | + | |
| 362 | + vsys1-supply = <&vbat>; | |
| 363 | + vsys2-supply = <&vbat>; | |
| 364 | + vsys3-supply = <&vbat>; | |
| 365 | + infet1-supply = <&vbat>; | |
| 366 | + infet2-supply = <&vbat>; | |
| 367 | + infet3-supply = <&vbat>; | |
| 368 | + infet4-supply = <&vbat>; | |
| 369 | + infet5-supply = <&vbat>; | |
| 370 | + infet6-supply = <&vbat>; | |
| 371 | + infet7-supply = <&vbat>; | |
| 372 | + vsys-l1-supply = <&vbat>; | |
| 373 | + vsys-l2-supply = <&vbat>; | |
| 374 | + | |
| 375 | + regulators { | |
| 376 | + tps65090_dcdc1: dcdc1 { | |
| 377 | + ti,enable-ext-control; | |
| 378 | + }; | |
| 379 | + tps65090_dcdc2: dcdc2 { | |
| 380 | + ti,enable-ext-control; | |
| 381 | + }; | |
| 382 | + tps65090_dcdc3: dcdc3 { | |
| 383 | + ti,enable-ext-control; | |
| 384 | + }; | |
| 385 | + tps65090_fet1: fet1 { | |
| 386 | + regulator-name = "vcd_led"; | |
| 387 | + }; | |
| 388 | + tps65090_fet2: fet2 { | |
| 389 | + regulator-name = "video_mid"; | |
| 390 | + regulator-always-on; | |
| 391 | + }; | |
| 392 | + tps65090_fet3: fet3 { | |
| 393 | + regulator-name = "wwan_r"; | |
| 394 | + regulator-always-on; | |
| 395 | + }; | |
| 396 | + tps65090_fet4: fet4 { | |
| 397 | + regulator-name = "sdcard"; | |
| 398 | + regulator-always-on; | |
| 399 | + }; | |
| 400 | + tps65090_fet5: fet5 { | |
| 401 | + regulator-name = "camout"; | |
| 402 | + }; | |
| 403 | + tps65090_fet6: fet6 { | |
| 404 | + regulator-name = "lcd_vdd"; | |
| 405 | + }; | |
| 406 | + tps65090_fet7: fet7 { | |
| 407 | + regulator-name = "video_mid_1a"; | |
| 408 | + regulator-always-on; | |
| 409 | + }; | |
| 410 | + tps65090_ldo1: ldo1 { | |
| 411 | + }; | |
| 412 | + tps65090_ldo2: ldo2 { | |
| 413 | + }; | |
| 414 | + }; | |
| 415 | + | |
| 416 | + charger { | |
| 417 | + compatible = "ti,tps65090-charger"; | |
| 418 | + }; | |
| 419 | + }; | |
| 420 | + }; | |
| 421 | + }; | |
| 422 | +}; | |
| 423 | + | |
| 424 | +&uart_3 { | |
| 231 | 425 | status = "okay"; |
| 232 | − hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; | |
| 233 | − pinctrl-names = "default"; | |
| 234 | − pinctrl-0 = <&hdmi_hpd_irq>; | |
| 235 | − ddc = <&i2c_2>; | |
| 236 | 426 | }; |
| 237 | 427 | |
| 238 | 428 | &usbdrd_phy0 { |
| @@ -251,3 +441,5 @@ · 12 unmodified lines | ||
| 251 | 441 | &watchdog { |
| 252 | 442 | timeout-sec = <32>; |
| 253 | 443 | }; |
| 444 | + | |
| 445 | +#include "cros-ec-keyboard.dtsi" | |
| @@ -19,6 +19,10 @@ · 18 unmodified lines | ||
| 19 | 19 | compatible = "atmel,osc", "fixed-clock"; |
| 20 | 20 | clock-frequency = <6000000>; |
| 21 | 21 | }; |
| 22 | + | |
| 23 | + main_xtal { | |
| 24 | + clock-frequency = <6000000>; | |
| 25 | + }; | |
| 22 | 26 | }; |
| 23 | 27 | |
| 24 | 28 | ahb { |
| @@ -33,6 +33,7 @@ · 32 unmodified lines | ||
| 33 | 33 | cpus { |
| 34 | 34 | #address-cells = <1>; |
| 35 | 35 | #size-cells = <0>; |
| 36 | + enable-method = "hisilicon,hi3620-smp"; | |
| 36 | 37 | |
| 37 | 38 | cpu@0 { |
| 38 | 39 | device_type = "cpu"; |
| @@ -0,0 +1,53 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (c) 2013-2014 Linaro Ltd. | |
| 3 | + * Copyright (c) 2013-2014 Hisilicon Limited. | |
| 4 | + * | |
| 5 | + * This program is free software; you can redistribute it and/or modify | |
| 6 | + * it under the terms of the GNU General Public License version 2 as | |
| 7 | + * publishhed by the Free Software Foundation. | |
| 8 | + */ | |
| 9 | + | |
| 10 | +/dts-v1/; | |
| 11 | +#include "hisi-x5hd2.dtsi" | |
| 12 | + | |
| 13 | +/ { | |
| 14 | + model = "Hisilicon HIX5HD2 Development Board"; | |
| 15 | + compatible = "hisilicon,hix5hd2"; | |
| 16 | + | |
| 17 | + chosen { | |
| 18 | + bootargs = "console=ttyAMA0,115200 earlyprintk"; | |
| 19 | + }; | |
| 20 | + | |
| 21 | + cpus { | |
| 22 | + #address-cells = <1>; | |
| 23 | + #size-cells = <0>; | |
| 24 | + enable-method = "hisilicon,hix5hd2-smp"; | |
| 25 | + | |
| 26 | + cpu@0 { | |
| 27 | + compatible = "arm,cortex-a9"; | |
| 28 | + device_type = "cpu"; | |
| 29 | + reg = <0>; | |
| 30 | + next-level-cache = <&l2>; | |
| 31 | + }; | |
| 32 | + | |
| 33 | + cpu@1 { | |
| 34 | + compatible = "arm,cortex-a9"; | |
| 35 | + device_type = "cpu"; | |
| 36 | + reg = <1>; | |
| 37 | + next-level-cache = <&l2>; | |
| 38 | + }; | |
| 39 | + }; | |
| 40 | + | |
| 41 | + memory { | |
| 42 | + device_type = "memory"; | |
| 43 | + reg = <0x00000000 0x80000000>; | |
| 44 | + }; | |
| 45 | +}; | |
| 46 | + | |
| 47 | +&timer0 { | |
| 48 | + status = "okay"; | |
| 49 | +}; | |
| 50 | + | |
| 51 | +&uart0 { | |
| 52 | + status = "okay"; | |
| 53 | +}; | |
| @@ -0,0 +1,170 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (c) 2013-2014 Linaro Ltd. | |
| 3 | + * Copyright (c) 2013-2014 Hisilicon Limited. | |
| 4 | + * | |
| 5 | + * This program is free software; you can redistribute it and/or modify | |
| 6 | + * it under the terms of the GNU General Public License version 2 as | |
| 7 | + * publishhed by the Free Software Foundation. | |
| 8 | + */ | |
| 9 | + | |
| 10 | +#include "skeleton.dtsi" | |
| 11 | +#include <dt-bindings/clock/hix5hd2-clock.h> | |
| 12 | + | |
| 13 | +/ { | |
| 14 | + aliases { | |
| 15 | + serial0 = &uart0; | |
| 16 | + }; | |
| 17 | + | |
| 18 | + gic: interrupt-controller@f8a01000 { | |
| 19 | + compatible = "arm,cortex-a9-gic"; | |
| 20 | + #interrupt-cells = <3>; | |
| 21 | + #address-cells = <0>; | |
| 22 | + interrupt-controller; | |
| 23 | + /* gic dist base, gic cpu base */ | |
| 24 | + reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; | |
| 25 | + }; | |
| 26 | + | |
| 27 | + soc { | |
| 28 | + #address-cells = <1>; | |
| 29 | + #size-cells = <1>; | |
| 30 | + compatible = "simple-bus"; | |
| 31 | + interrupt-parent = <&gic>; | |
| 32 | + ranges = <0 0xf8000000 0x8000000>; | |
| 33 | + | |
| 34 | + amba { | |
| 35 | + #address-cells = <1>; | |
| 36 | + #size-cells = <1>; | |
| 37 | + compatible = "arm,amba-bus"; | |
| 38 | + ranges; | |
| 39 | + | |
| 40 | + timer0: timer@00002000 { | |
| 41 | + compatible = "arm,sp804", "arm,primecell"; | |
| 42 | + reg = <0x00002000 0x1000>; | |
| 43 | + /* timer00 & timer01 */ | |
| 44 | + interrupts = <0 24 4>; | |
| 45 | + clocks = <&clock HIX5HD2_FIXED_24M>; | |
| 46 | + status = "disabled"; | |
| 47 | + }; | |
| 48 | + | |
| 49 | + timer1: timer@00a29000 { | |
| 50 | + /* | |
| 51 | + * Only used in NORMAL state, not available ins | |
| 52 | + * SLOW or DOZE state. | |
| 53 | + * The rate is fixed in 24MHz. | |
| 54 | + */ | |
| 55 | + compatible = "arm,sp804", "arm,primecell"; | |
| 56 | + reg = <0x00a29000 0x1000>; | |
| 57 | + /* timer10 & timer11 */ | |
| 58 | + interrupts = <0 25 4>; | |
| 59 | + clocks = <&clock HIX5HD2_FIXED_24M>; | |
| 60 | + status = "disabled"; | |
| 61 | + }; | |
| 62 | + | |
| 63 | + timer2: timer@00a2a000 { | |
| 64 | + compatible = "arm,sp804", "arm,primecell"; | |
| 65 | + reg = <0x00a2a000 0x1000>; | |
| 66 | + /* timer20 & timer21 */ | |
| 67 | + interrupts = <0 26 4>; | |
| 68 | + clocks = <&clock HIX5HD2_FIXED_24M>; | |
| 69 | + status = "disabled"; | |
| 70 | + }; | |
| 71 | + | |
| 72 | + timer3: timer@00a2b000 { | |
| 73 | + compatible = "arm,sp804", "arm,primecell"; | |
| 74 | + reg = <0x00a2b000 0x1000>; | |
| 75 | + /* timer30 & timer31 */ | |
| 76 | + interrupts = <0 27 4>; | |
| 77 | + clocks = <&clock HIX5HD2_FIXED_24M>; | |
| 78 | + status = "disabled"; | |
| 79 | + }; | |
| 80 | + | |
| 81 | + timer4: timer@00a81000 { | |
| 82 | + compatible = "arm,sp804", "arm,primecell"; | |
| 83 | + reg = <0x00a81000 0x1000>; | |
| 84 | + /* timer30 & timer31 */ | |
| 85 | + interrupts = <0 28 4>; | |
| 86 | + clocks = <&clock HIX5HD2_FIXED_24M>; | |
| 87 | + status = "disabled"; | |
| 88 | + }; | |
| 89 | + | |
| 90 | + uart0: uart@00b00000 { | |
| 91 | + compatible = "arm,pl011", "arm,primecell"; | |
| 92 | + reg = <0x00b00000 0x1000>; | |
| 93 | + interrupts = <0 49 4>; | |
| 94 | + clocks = <&clock HIX5HD2_FIXED_83M>; | |
| 95 | + clock-names = "apb_pclk"; | |
| 96 | + status = "disabled"; | |
| 97 | + }; | |
| 98 | + | |
| 99 | + uart1: uart@00006000 { | |
| 100 | + compatible = "arm,pl011", "arm,primecell"; | |
| 101 | + reg = <0x00006000 0x1000>; | |
| 102 | + interrupts = <0 50 4>; | |
| 103 | + clocks = <&clock HIX5HD2_FIXED_83M>; | |
| 104 | + clock-names = "apb_pclk"; | |
| 105 | + status = "disabled"; | |
| 106 | + }; | |
| 107 | + | |
| 108 | + uart2: uart@00b02000 { | |
| 109 | + compatible = "arm,pl011", "arm,primecell"; | |
| 110 | + reg = <0x00b02000 0x1000>; | |
| 111 | + interrupts = <0 51 4>; | |
| 112 | + clocks = <&clock HIX5HD2_FIXED_83M>; | |
| 113 | + clock-names = "apb_pclk"; | |
| 114 | + status = "disabled"; | |
| 115 | + }; | |
| 116 | + | |
| 117 | + uart3: uart@00b03000 { | |
| 118 | + compatible = "arm,pl011", "arm,primecell"; | |
| 119 | + reg = <0x00b03000 0x1000>; | |
| 120 | + interrupts = <0 52 4>; | |
| 121 | + clocks = <&clock HIX5HD2_FIXED_83M>; | |
| 122 | + clock-names = "apb_pclk"; | |
| 123 | + status = "disabled"; | |
| 124 | + }; | |
| 125 | + | |
| 126 | + uart4: uart@00b04000 { | |
| 127 | + compatible = "arm,pl011", "arm,primecell"; | |
| 128 | + reg = <0xb04000 0x1000>; | |
| 129 | + interrupts = <0 53 4>; | |
| 130 | + clocks = <&clock HIX5HD2_FIXED_83M>; | |
| 131 | + clock-names = "apb_pclk"; | |
| 132 | + status = "disabled"; | |
| 133 | + }; | |
| 134 | + }; | |
| 135 | + | |
| 136 | + local_timer@00a00600 { | |
| 137 | + compatible = "arm,cortex-a9-twd-timer"; | |
| 138 | + reg = <0x00a00600 0x20>; | |
| 139 | + interrupts = <1 13 0xf01>; | |
| 140 | + }; | |
| 141 | + | |
| 142 | + l2: l2-cache { | |
| 143 | + compatible = "arm,pl310-cache"; | |
| 144 | + reg = <0x00a10000 0x100000>; | |
| 145 | + interrupts = <0 15 4>; | |
| 146 | + cache-unified; | |
| 147 | + cache-level = <2>; | |
| 148 | + }; | |
| 149 | + | |
| 150 | + sysctrl: system-controller@00000000 { | |
| 151 | + compatible = "hisilicon,sysctrl"; | |
| 152 | + reg = <0x00000000 0x1000>; | |
| 153 | + reboot-offset = <0x4>; | |
| 154 | + }; | |
| 155 | + | |
| 156 | + cpuctrl@00a22000 { | |
| 157 | + compatible = "hisilicon,cpuctrl"; | |
| 158 | + #address-cells = <1>; | |
| 159 | + #size-cells = <1>; | |
| 160 | + reg = <0x00a22000 0x2000>; | |
| 161 | + ranges = <0 0x00a22000 0x2000>; | |
| 162 | + | |
| 163 | + clock: clock@0 { | |
| 164 | + compatible = "hisilicon,hix5hd2-clock"; | |
| 165 | + reg = <0 0x2000>; | |
| 166 | + #clock-cells = <1>; | |
| 167 | + }; | |
| 168 | + }; | |
| 169 | + }; | |
| 170 | +}; | |
| @@ -0,0 +1,73 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | |
| 3 | + * | |
| 4 | + * This program is free software; you can redistribute it and/or | |
| 5 | + * modify it under the terms of the GNU General Public License | |
| 6 | + * as published by the Free Software Foundation; either version 2 | |
| 7 | + * of the License, or (at your option) any later version. | |
| 8 | + * This program is distributed in the hope that it will be useful, | |
| 9 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 10 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 11 | + * GNU General Public License for more details. | |
| 12 | + */ | |
| 13 | + | |
| 14 | +#include "imx25-eukrea-mbimxsd25-baseboard.dts" | |
| 15 | + | |
| 16 | +/ { | |
| 17 | + model = "Eukrea MBIMXSD25 with the CMO-QVGA Display"; | |
| 18 | + compatible = "eukrea,mbimxsd25-baseboard-cmo-qvga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; | |
| 19 | + | |
| 20 | + cmo_qvga: display { | |
| 21 | + model = "CMO-QVGA"; | |
| 22 | + bits-per-pixel = <16>; | |
| 23 | + fsl,pcr = <0xcad08b80>; | |
| 24 | + bus-width = <18>; | |
| 25 | + native-mode = <&qvga_timings>; | |
| 26 | + display-timings { | |
| 27 | + qvga_timings: 320x240 { | |
| 28 | + clock-frequency = <6500000>; | |
| 29 | + hactive = <320>; | |
| 30 | + vactive = <240>; | |
| 31 | + hback-porch = <30>; | |
| 32 | + hfront-porch = <38>; | |
| 33 | + vback-porch = <20>; | |
| 34 | + vfront-porch = <3>; | |
| 35 | + hsync-len = <15>; | |
| 36 | + vsync-len = <4>; | |
| 37 | + }; | |
| 38 | + }; | |
| 39 | + }; | |
| 40 | + | |
| 41 | + regulators { | |
| 42 | + compatible = "simple-bus"; | |
| 43 | + #address-cells = <1>; | |
| 44 | + #size-cells = <0>; | |
| 45 | + | |
| 46 | + reg_lcd_3v3: regulator@0 { | |
| 47 | + compatible = "regulator-fixed"; | |
| 48 | + reg = <0>; | |
| 49 | + pinctrl-names = "default"; | |
| 50 | + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; | |
| 51 | + regulator-name = "lcd-3v3"; | |
| 52 | + regulator-min-microvolt = <3300000>; | |
| 53 | + regulator-max-microvolt = <3300000>; | |
| 54 | + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; | |
| 55 | + enable-active-high; | |
| 56 | + }; | |
| 57 | + }; | |
| 58 | +}; | |
| 59 | + | |
| 60 | +&iomuxc { | |
| 61 | + imx25-eukrea-mbimxsd25-baseboard-cmo-qvga { | |
| 62 | + pinctrl_reg_lcd_3v3: reg_lcd_3v3 { | |
| 63 | + fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>; | |
| 64 | + }; | |
| 65 | + }; | |
| 66 | +}; | |
| 67 | + | |
| 68 | +&lcdc { | |
| 69 | + display = <&cmo_qvga>; | |
| 70 | + fsl,lpccr = <0x00a903ff>; | |
| 71 | + lcd-supply = <®_lcd_3v3>; | |
| 72 | + status = "okay"; | |
| 73 | +}; | |
| @@ -0,0 +1,45 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | |
| 3 | + * | |
| 4 | + * This program is free software; you can redistribute it and/or | |
| 5 | + * modify it under the terms of the GNU General Public License | |
| 6 | + * as published by the Free Software Foundation; either version 2 | |
| 7 | + * of the License, or (at your option) any later version. | |
| 8 | + * This program is distributed in the hope that it will be useful, | |
| 9 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 10 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 11 | + * GNU General Public License for more details. | |
| 12 | + */ | |
| 13 | + | |
| 14 | +#include "imx25-eukrea-mbimxsd25-baseboard.dts" | |
| 15 | + | |
| 16 | +/ { | |
| 17 | + model = "Eukrea MBIMXSD25 with the DVI-SVGA Display"; | |
| 18 | + compatible = "eukrea,mbimxsd25-baseboard-dvi-svga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; | |
| 19 | + | |
| 20 | + dvi_svga: display { | |
| 21 | + model = "DVI-SVGA"; | |
| 22 | + bits-per-pixel = <16>; | |
| 23 | + fsl,pcr = <0xfa208b80>; | |
| 24 | + bus-width = <18>; | |
| 25 | + native-mode = <&dvi_svga_timings>; | |
| 26 | + display-timings { | |
| 27 | + dvi_svga_timings: 800x600 { | |
| 28 | + clock-frequency = <40000000>; | |
| 29 | + hactive = <800>; | |
| 30 | + vactive = <600>; | |
| 31 | + hback-porch = <75>; | |
| 32 | + hfront-porch = <75>; | |
| 33 | + vback-porch = <7>; | |
| 34 | + vfront-porch = <75>; | |
| 35 | + hsync-len = <7>; | |
| 36 | + vsync-len = <7>; | |
| 37 | + }; | |
| 38 | + }; | |
| 39 | + }; | |
| 40 | +}; | |
| 41 | + | |
| 42 | +&lcdc { | |
| 43 | + display = <&dvi_svga>; | |
| 44 | + status = "okay"; | |
| 45 | +}; | |
| @@ -0,0 +1,45 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> | |
| 3 | + * | |
| 4 | + * This program is free software; you can redistribute it and/or | |
| 5 | + * modify it under the terms of the GNU General Public License | |
| 6 | + * as published by the Free Software Foundation; either version 2 | |
| 7 | + * of the License, or (at your option) any later version. | |
| 8 | + * This program is distributed in the hope that it will be useful, | |
| 9 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 10 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 11 | + * GNU General Public License for more details. | |
| 12 | + */ | |
| 13 | + | |
| 14 | +#include "imx25-eukrea-mbimxsd25-baseboard.dts" | |
| 15 | + | |
| 16 | +/ { | |
| 17 | + model = "Eukrea MBIMXSD25 with the DVI-VGA Display"; | |
| 18 | + compatible = "eukrea,mbimxsd25-baseboard-dvi-vga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; | |
| 19 | + | |
| 20 | + dvi_vga: display { | |
| 21 | + model = "DVI-VGA"; | |
| 22 | + bits-per-pixel = <16>; | |
| 23 | + fsl,pcr = <0xfa208b80>; | |
| 24 | + bus-width = <18>; | |
| 25 | + native-mode = <&dvi_vga_timings>; | |
| 26 | + display-timings { | |
| 27 | + dvi_vga_timings: 640x480 { | |
| 28 | + clock-frequency = <31250000>; | |
| 29 | + hactive = <640>; | |
| 30 | + vactive = <480>; | |
| 31 | + hback-porch = <100>; | |
| 32 | + hfront-porch = <100>; | |
| 33 | + vback-porch = <7>; | |
| 34 | + vfront-porch = <100>; | |
| 35 | + hsync-len = <7>; | |
| 36 | + vsync-len = <7>; | |
| 37 | + }; | |
| 38 | + }; | |
| 39 | + }; | |
| 40 | +}; | |
| 41 | + | |
| 42 | +&lcdc { | |
| 43 | + display = <&dvi_vga>; | |
| 44 | + status = "okay"; | |
| 45 | +}; | |
| @@ -155,7 +155,6 @@ · 154 unmodified lines | ||
| 155 | 155 | |
| 156 | 156 | &ssi1 { |
| 157 | 157 | codec-handle = <&tlv320aic23>; |
| 158 | − fsl,mode = "i2s-slave"; | |
| 159 | 158 | status = "okay"; |
| 160 | 159 | }; |
| 161 | 160 | |
| @@ -233,7 +233,6 @@ · 232 unmodified lines | ||
| 233 | 233 | |
| 234 | 234 | &ssi1 { |
| 235 | 235 | codec-handle = <&codec>; |
| 236 | − fsl,mode = "i2s-slave"; | |
| 237 | 236 | status = "okay"; |
| 238 | 237 | }; |
| 239 | 238 | |
| @@ -249,3 +248,10 @@ · 9 unmodified lines | ||
| 249 | 248 | dr_mode = "host"; |
| 250 | 249 | status = "okay"; |
| 251 | 250 | }; |
| 251 | + | |
| 252 | +&usbotg { | |
| 253 | + phy_type = "utmi"; | |
| 254 | + dr_mode = "otg"; | |
| 255 | + external-vbus-divider; | |
| 256 | + status = "okay"; | |
| 257 | +}; | |
| @@ -312,7 +312,7 @@ · 311 unmodified lines | ||
| 312 | 312 | gpt4: timer@53f84000 { |
| 313 | 313 | compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; |
| 314 | 314 | reg = <0x53f84000 0x4000>; |
| 315 | − clocks = <&clks 9>, <&clks 45>; | |
| 315 | + clocks = <&clks 95>, <&clks 47>; | |
| 316 | 316 | clock-names = "ipg", "per"; |
| 317 | 317 | interrupts = <1>; |
| 318 | 318 | }; |
| @@ -320,7 +320,7 @@ · 1 unmodified line | ||
| 320 | 320 | gpt3: timer@53f88000 { |
| 321 | 321 | compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; |
| 322 | 322 | reg = <0x53f88000 0x4000>; |
| 323 | − clocks = <&clks 9>, <&clks 47>; | |
| 323 | + clocks = <&clks 94>, <&clks 47>; | |
| 324 | 324 | clock-names = "ipg", "per"; |
| 325 | 325 | interrupts = <29>; |
| 326 | 326 | }; |
| @@ -328,7 +328,7 @@ · 1 unmodified line | ||
| 328 | 328 | gpt2: timer@53f8c000 { |
| 329 | 329 | compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; |
| 330 | 330 | reg = <0x53f8c000 0x4000>; |
| 331 | − clocks = <&clks 9>, <&clks 47>; | |
| 331 | + clocks = <&clks 93>, <&clks 47>; | |
| 332 | 332 | clock-names = "ipg", "per"; |
| 333 | 333 | interrupts = <53>; |
| 334 | 334 | }; |
| @@ -336,7 +336,7 @@ · 1 unmodified line | ||
| 336 | 336 | gpt1: timer@53f90000 { |
| 337 | 337 | compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; |
| 338 | 338 | reg = <0x53f90000 0x4000>; |
| 339 | − clocks = <&clks 9>, <&clks 47>; | |
| 339 | + clocks = <&clks 92>, <&clks 47>; | |
| 340 | 340 | clock-names = "ipg", "per"; |
| 341 | 341 | interrupts = <54>; |
| 342 | 342 | }; |
| @@ -0,0 +1,296 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> | |
| 3 | + * | |
| 4 | + * The code contained herein is licensed under the GNU General Public | |
| 5 | + * License. You may obtain a copy of the GNU General Public License | |
| 6 | + * Version 2 or later at the following locations: | |
| 7 | + * | |
| 8 | + * http://www.opensource.org/licenses/gpl-license.html | |
| 9 | + * http://www.gnu.org/copyleft/gpl.html | |
| 10 | + */ | |
| 11 | + | |
| 12 | +/dts-v1/; | |
| 13 | +#include "imx27.dtsi" | |
| 14 | + | |
| 15 | +/ { | |
| 16 | + model = "Eukrea CPUIMX27"; | |
| 17 | + compatible = "eukrea,cpuimx27", "fsl,imx27"; | |
| 18 | + | |
| 19 | + memory { | |
| 20 | + reg = <0xa0000000 0x04000000>; | |
| 21 | + }; | |
| 22 | + | |
| 23 | + clocks { | |
| 24 | + #address-cells = <1>; | |
| 25 | + #size-cells = <0>; | |
| 26 | + compatible = "simple-bus"; | |
| 27 | + | |
| 28 | + clk14745600: clock@0 { | |
| 29 | + #clock-cells = <0>; | |
| 30 | + compatible = "fixed-clock"; | |
| 31 | + clock-frequency = <14745600>; | |
| 32 | + reg = <0>; | |
| 33 | + }; | |
| 34 | + }; | |
| 35 | +}; | |
| 36 | + | |
| 37 | +&fec { | |
| 38 | + pinctrl-names = "default"; | |
| 39 | + pinctrl-0 = <&pinctrl_fec>; | |
| 40 | + status = "okay"; | |
| 41 | +}; | |
| 42 | + | |
| 43 | +&i2c1 { | |
| 44 | + pinctrl-names = "default"; | |
| 45 | + pinctrl-0 = <&pinctrl_i2c1>; | |
| 46 | + status = "okay"; | |
| 47 | + | |
| 48 | + pcf8563@51 { | |
| 49 | + compatible = "nxp,pcf8563"; | |
| 50 | + reg = <0x51>; | |
| 51 | + }; | |
| 52 | +}; | |
| 53 | + | |
| 54 | +&nfc { | |
| 55 | + pinctrl-names = "default"; | |
| 56 | + pinctrl-0 = <&pinctrl_nfc>; | |
| 57 | + nand-bus-width = <8>; | |
| 58 | + nand-ecc-mode = "hw"; | |
| 59 | + nand-on-flash-bbt; | |
| 60 | + status = "okay"; | |
| 61 | +}; | |
| 62 | + | |
| 63 | +&owire { | |
| 64 | + pinctrl-names = "default"; | |
| 65 | + pinctrl-0 = <&pinctrl_owire>; | |
| 66 | + status = "okay"; | |
| 67 | +}; | |
| 68 | + | |
| 69 | +&sdhci2 { | |
| 70 | + pinctrl-names = "default"; | |
| 71 | + pinctrl-0 = <&pinctrl_sdhc2>; | |
| 72 | + bus-width = <4>; | |
| 73 | + non-removable; | |
| 74 | + status = "okay"; | |
| 75 | +}; | |
| 76 | + | |
| 77 | +&uart4 { | |
| 78 | + pinctrl-names = "default"; | |
| 79 | + pinctrl-0 = <&pinctrl_uart4>; | |
| 80 | + fsl,uart-has-rtscts; | |
| 81 | + status = "okay"; | |
| 82 | +}; | |
| 83 | + | |
| 84 | +&usbh2 { | |
| 85 | + pinctrl-names = "default"; | |
| 86 | + pinctrl-0 = <&pinctrl_usbh2>; | |
| 87 | + dr_mode = "host"; | |
| 88 | + phy_type = "ulpi"; | |
| 89 | + disable-over-current; | |
| 90 | + status = "okay"; | |
| 91 | +}; | |
| 92 | + | |
| 93 | +&usbotg { | |
| 94 | + pinctrl-names = "default"; | |
| 95 | + pinctrl-0 = <&pinctrl_usbotg>; | |
| 96 | + dr_mode = "otg"; | |
| 97 | + phy_type = "ulpi"; | |
| 98 | + disable-over-current; | |
| 99 | + status = "okay"; | |
| 100 | +}; | |
| 101 | + | |
| 102 | +&weim { | |
| 103 | + status = "okay"; | |
| 104 | + | |
| 105 | + nor: nor@0,0 { | |
| 106 | + #address-cells = <1>; | |
| 107 | + #size-cells = <1>; | |
| 108 | + compatible = "cfi-flash"; | |
| 109 | + reg = <0 0x00000000 0x04000000>; | |
| 110 | + bank-width = <2>; | |
| 111 | + linux,mtd-name = "physmap-flash.0"; | |
| 112 | + fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>; | |
| 113 | + }; | |
| 114 | + | |
| 115 | + uart8250@3,200000 { | |
| 116 | + pinctrl-names = "default"; | |
| 117 | + pinctrl-0 = <&pinctrl_uart8250_1>; | |
| 118 | + compatible = "ns8250"; | |
| 119 | + clocks = <&clk14745600>; | |
| 120 | + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; | |
| 121 | + interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>; | |
| 122 | + reg = <3 0x200000 0x1000>; | |
| 123 | + reg-shift = <1>; | |
| 124 | + reg-io-width = <1>; | |
| 125 | + no-loopback-test; | |
| 126 | + }; | |
| 127 | + | |
| 128 | + uart8250@3,400000 { | |
| 129 | + pinctrl-names = "default"; | |
| 130 | + pinctrl-0 = <&pinctrl_uart8250_2>; | |
| 131 | + compatible = "ns8250"; | |
| 132 | + clocks = <&clk14745600>; | |
| 133 | + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; | |
| 134 | + interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>; | |
| 135 | + reg = <3 0x400000 0x1000>; | |
| 136 | + reg-shift = <1>; | |
| 137 | + reg-io-width = <1>; | |
| 138 | + no-loopback-test; | |
| 139 | + }; | |
| 140 | + | |
| 141 | + uart8250@3,800000 { | |
| 142 | + pinctrl-names = "default"; | |
| 143 | + pinctrl-0 = <&pinctrl_uart8250_3>; | |
| 144 | + compatible = "ns8250"; | |
| 145 | + clocks = <&clk14745600>; | |
| 146 | + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; | |
| 147 | + interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>; | |
| 148 | + reg = <3 0x800000 0x1000>; | |
| 149 | + reg-shift = <1>; | |
| 150 | + reg-io-width = <1>; | |
| 151 | + no-loopback-test; | |
| 152 | + }; | |
| 153 | + | |
| 154 | + uart8250@3,1000000 { | |
| 155 | + pinctrl-names = "default"; | |
| 156 | + pinctrl-0 = <&pinctrl_uart8250_4>; | |
| 157 | + compatible = "ns8250"; | |
| 158 | + clocks = <&clk14745600>; | |
| 159 | + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; | |
| 160 | + interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>; | |
| 161 | + reg = <3 0x1000000 0x1000>; | |
| 162 | + reg-shift = <1>; | |
| 163 | + reg-io-width = <1>; | |
| 164 | + no-loopback-test; | |
| 165 | + }; | |
| 166 | +}; | |
| 167 | + | |
| 168 | +&iomuxc { | |
| 169 | + imx27-eukrea-cpuimx27 { | |
| 170 | + pinctrl_fec: fecgrp { | |
| 171 | + fsl,pins = < | |
| 172 | + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 | |
| 173 | + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 | |
| 174 | + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 | |
| 175 | + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 | |
| 176 | + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 | |
| 177 | + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 | |
| 178 | + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 | |
| 179 | + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 | |
| 180 | + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 | |
| 181 | + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 | |
| 182 | + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 | |
| 183 | + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 | |
| 184 | + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 | |
| 185 | + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 | |
| 186 | + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 | |
| 187 | + MX27_PAD_ATA_DATA13__FEC_COL 0x0 | |
| 188 | + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 | |
| 189 | + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 | |
| 190 | + >; | |
| 191 | + }; | |
| 192 | + | |
| 193 | + pinctrl_i2c1: i2c1grp { | |
| 194 | + fsl,pins = < | |
| 195 | + MX27_PAD_I2C_DATA__I2C_DATA 0x0 | |
| 196 | + MX27_PAD_I2C_CLK__I2C_CLK 0x0 | |
| 197 | + >; | |
| 198 | + }; | |
| 199 | + | |
| 200 | + pinctrl_nfc: nfcgrp { | |
| 201 | + fsl,pins = < | |
| 202 | + MX27_PAD_NFRB__NFRB 0x0 | |
| 203 | + MX27_PAD_NFCLE__NFCLE 0x0 | |
| 204 | + MX27_PAD_NFWP_B__NFWP_B 0x0 | |
| 205 | + MX27_PAD_NFCE_B__NFCE_B 0x0 | |
| 206 | + MX27_PAD_NFALE__NFALE 0x0 | |
| 207 | + MX27_PAD_NFRE_B__NFRE_B 0x0 | |
| 208 | + MX27_PAD_NFWE_B__NFWE_B 0x0 | |
| 209 | + >; | |
| 210 | + }; | |
| 211 | + | |
| 212 | + pinctrl_owire: owiregrp { | |
| 213 | + fsl,pins = < | |
| 214 | + MX27_PAD_RTCK__OWIRE 0x0 | |
| 215 | + >; | |
| 216 | + }; | |
| 217 | + | |
| 218 | + pinctrl_sdhc2: sdhc2grp { | |
| 219 | + fsl,pins = < | |
| 220 | + MX27_PAD_SD2_CLK__SD2_CLK 0x0 | |
| 221 | + MX27_PAD_SD2_CMD__SD2_CMD 0x0 | |
| 222 | + MX27_PAD_SD2_D0__SD2_D0 0x0 | |
| 223 | + MX27_PAD_SD2_D1__SD2_D1 0x0 | |
| 224 | + MX27_PAD_SD2_D2__SD2_D2 0x0 | |
| 225 | + MX27_PAD_SD2_D3__SD2_D3 0x0 | |
| 226 | + >; | |
| 227 | + }; | |
| 228 | + | |
| 229 | + pinctrl_uart4: uart4grp { | |
| 230 | + fsl,pins = < | |
| 231 | + MX27_PAD_USBH1_TXDM__UART4_TXD 0x0 | |
| 232 | + MX27_PAD_USBH1_RXDP__UART4_RXD 0x0 | |
| 233 | + MX27_PAD_USBH1_TXDP__UART4_CTS 0x0 | |
| 234 | + MX27_PAD_USBH1_FS__UART4_RTS 0x0 | |
| 235 | + >; | |
| 236 | + }; | |
| 237 | + | |
| 238 | + pinctrl_uart8250_1: uart82501grp { | |
| 239 | + fsl,pins = < | |
| 240 | + MX27_PAD_USB_PWR__GPIO2_23 0x0 | |
| 241 | + >; | |
| 242 | + }; | |
| 243 | + | |
| 244 | + pinctrl_uart8250_2: uart82502grp { | |
| 245 | + fsl,pins = < | |
| 246 | + MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 | |
| 247 | + >; | |
| 248 | + }; | |
| 249 | + | |
| 250 | + pinctrl_uart8250_3: uart82503grp { | |
| 251 | + fsl,pins = < | |
| 252 | + MX27_PAD_USBH1_OE_B__GPIO2_27 0x0 | |
| 253 | + >; | |
| 254 | + }; | |
| 255 | + | |
| 256 | + pinctrl_uart8250_4: uart82504grp { | |
| 257 | + fsl,pins = < | |
| 258 | + MX27_PAD_USBH1_RXDM__GPIO2_30 0x0 | |
| 259 | + >; | |
| 260 | + }; | |
| 261 | + | |
| 262 | + pinctrl_usbh2: usbh2grp { | |
| 263 | + fsl,pins = < | |
| 264 | + MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 | |
| 265 | + MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 | |
| 266 | + MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 | |
| 267 | + MX27_PAD_USBH2_STP__USBH2_STP 0x0 | |
| 268 | + MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 | |
| 269 | + MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 | |
| 270 | + MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 | |
| 271 | + MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 | |
| 272 | + MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 | |
| 273 | + MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 | |
| 274 | + MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 | |
| 275 | + MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 | |
| 276 | + >; | |
| 277 | + }; | |
| 278 | + | |
| 279 | + pinctrl_usbotg: usbotggrp { | |
| 280 | + fsl,pins = < | |
| 281 | + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 | |
| 282 | + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 | |
| 283 | + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 | |
| 284 | + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 | |
| 285 | + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 | |
| 286 | + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 | |
| 287 | + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 | |
| 288 | + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 | |
| 289 | + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 | |
| 290 | + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 | |
| 291 | + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 | |
| 292 | + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 | |
| 293 | + >; | |
| 294 | + }; | |
| 295 | + }; | |
| 296 | +}; | |
| @@ -0,0 +1,273 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> | |
| 3 | + * | |
| 4 | + * The code contained herein is licensed under the GNU General Public | |
| 5 | + * License. You may obtain a copy of the GNU General Public License | |
| 6 | + * Version 2 or later at the following locations: | |
| 7 | + * | |
| 8 | + * http://www.opensource.org/licenses/gpl-license.html | |
| 9 | + * http://www.gnu.org/copyleft/gpl.html | |
| 10 | + */ | |
| 11 | + | |
| 12 | +#include "imx27-eukrea-cpuimx27.dtsi" | |
| 13 | + | |
| 14 | +/ { | |
| 15 | + model = "Eukrea MBIMXSD27"; | |
| 16 | + compatible = "eukrea,mbimxsd27-baseboard", "eukrea,cpuimx27", "fsl,imx27"; | |
| 17 | + | |
| 18 | + display0: CMO-QVGA { | |
| 19 | + model = "CMO-QVGA"; | |
| 20 | + native-mode = <&timing0>; | |
| 21 | + bits-per-pixel = <16>; | |
| 22 | + fsl,pcr = <0xfad08b80>; | |
| 23 | + | |
| 24 | + display-timings { | |
| 25 | + timing0: 320x240 { | |
| 26 | + clock-frequency = <6500000>; | |
| 27 | + hactive = <320>; | |
| 28 | + vactive = <240>; | |
| 29 | + hback-porch = <20>; | |
| 30 | + hsync-len = <30>; | |
| 31 | + hfront-porch = <38>; | |
| 32 | + vback-porch = <4>; | |
| 33 | + vsync-len = <3>; | |
| 34 | + vfront-porch = <15>; | |
| 35 | + }; | |
| 36 | + }; | |
| 37 | + }; | |
| 38 | + | |
| 39 | + backlight { | |
| 40 | + compatible = "gpio-backlight"; | |
| 41 | + pinctrl-names = "default"; | |
| 42 | + pinctrl-0 = <&pinctrl_backlight>; | |
| 43 | + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; | |
| 44 | + }; | |
| 45 | + | |
| 46 | + leds { | |
| 47 | + compatible = "gpio-leds"; | |
| 48 | + pinctrl-names = "default"; | |
| 49 | + pinctrl-0 = <&pinctrl_gpioleds>; | |
| 50 | + | |
| 51 | + led1 { | |
| 52 | + label = "system::live"; | |
| 53 | + gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; | |
| 54 | + linux,default-trigger = "heartbeat"; | |
| 55 | + }; | |
| 56 | + | |
| 57 | + led2 { | |
| 58 | + label = "system::user"; | |
| 59 | + gpios = <&gpio6 19 GPIO_ACTIVE_LOW>; | |
| 60 | + }; | |
| 61 | + }; | |
| 62 | + | |
| 63 | + regulators { | |
| 64 | + #address-cells = <1>; | |
| 65 | + #size-cells = <0>; | |
| 66 | + compatible = "simple-bus"; | |
| 67 | + | |
| 68 | + reg_lcd: regulator@0 { | |
| 69 | + pinctrl-names = "default"; | |
| 70 | + pinctrl-0 = <&pinctrl_lcdreg>; | |
| 71 | + compatible = "regulator-fixed"; | |
| 72 | + reg = <0>; | |
| 73 | + regulator-name = "LCD"; | |
| 74 | + regulator-min-microvolt = <5000000>; | |
| 75 | + regulator-max-microvolt = <5000000>; | |
| 76 | + gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>; | |
| 77 | + enable-active-high; | |
| 78 | + }; | |
| 79 | + }; | |
| 80 | +}; | |
| 81 | + | |
| 82 | +&cspi1 { | |
| 83 | + pinctrl-0 = <&pinctrl_cspi1>; | |
| 84 | + fsl,spi-num-chipselects = <1>; | |
| 85 | + cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; | |
| 86 | + status = "okay"; | |
| 87 | + | |
| 88 | + ads7846 { | |
| 89 | + compatible = "ti,ads7846"; | |
| 90 | + pinctrl-names = "default"; | |
| 91 | + pinctrl-0 = <&pinctrl_touch>; | |
| 92 | + reg = <0>; | |
| 93 | + interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; | |
| 94 | + spi-cpol; | |
| 95 | + spi-max-frequency = <1500000>; | |
| 96 | + ti,keep-vref-on; | |
| 97 | + }; | |
| 98 | +}; | |
| 99 | + | |
| 100 | +&fb { | |
| 101 | + pinctrl-names = "default"; | |
| 102 | + pinctrl-0 = <&pinctrl_imxfb>; | |
| 103 | + display = <&display0>; | |
| 104 | + lcd-supply = <®_lcd>; | |
| 105 | + fsl,dmacr = <0x00040060>; | |
| 106 | + fsl,lscr1 = <0x00120300>; | |
| 107 | + fsl,lpccr = <0x00a903ff>; | |
| 108 | + status = "okay"; | |
| 109 | +}; | |
| 110 | + | |
| 111 | +&i2c1 { | |
| 112 | + codec: codec@1a { | |
| 113 | + compatible = "ti,tlv320aic23"; | |
| 114 | + reg = <0x1a>; | |
| 115 | + }; | |
| 116 | +}; | |
| 117 | + | |
| 118 | +&kpp { | |
| 119 | + linux,keymap = < | |
| 120 | + MATRIX_KEY(0, 0, KEY_UP) | |
| 121 | + MATRIX_KEY(0, 1, KEY_DOWN) | |
| 122 | + MATRIX_KEY(1, 0, KEY_RIGHT) | |
| 123 | + MATRIX_KEY(1, 1, KEY_LEFT) | |
| 124 | + >; | |
| 125 | + status = "okay"; | |
| 126 | +}; | |
| 127 | + | |
| 128 | +&sdhci1 { | |
| 129 | + pinctrl-names = "default"; | |
| 130 | + pinctrl-0 = <&pinctrl_sdhc1>; | |
| 131 | + bus-width = <4>; | |
| 132 | + status = "okay"; | |
| 133 | +}; | |
| 134 | + | |
| 135 | +&ssi1 { | |
| 136 | + pinctrl-names = "default"; | |
| 137 | + pinctrl-0 = <&pinctrl_ssi1>; | |
| 138 | + codec-handle = <&codec>; | |
| 139 | + status = "okay"; | |
| 140 | +}; | |
| 141 | + | |
| 142 | +&uart1 { | |
| 143 | + fsl,uart-has-rtscts; | |
| 144 | + pinctrl-names = "default"; | |
| 145 | + pinctrl-0 = <&pinctrl_uart1>; | |
| 146 | + status = "okay"; | |
| 147 | +}; | |
| 148 | + | |
| 149 | +&uart2 { | |
| 150 | + fsl,uart-has-rtscts; | |
| 151 | + pinctrl-names = "default"; | |
| 152 | + pinctrl-0 = <&pinctrl_uart2>; | |
| 153 | + status = "okay"; | |
| 154 | +}; | |
| 155 | + | |
| 156 | +&uart3 { | |
| 157 | + fsl,uart-has-rtscts; | |
| 158 | + pinctrl-names = "default"; | |
| 159 | + pinctrl-0 = <&pinctrl_uart3>; | |
| 160 | + status = "okay"; | |
| 161 | +}; | |
| 162 | + | |
| 163 | +&iomuxc { | |
| 164 | + imx27-eukrea-cpuimx27-baseboard { | |
| 165 | + pinctrl_cspi1: cspi1grp { | |
| 166 | + fsl,pins = < | |
| 167 | + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 | |
| 168 | + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 | |
| 169 | + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 | |
| 170 | + MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */ | |
| 171 | + >; | |
| 172 | + }; | |
| 173 | + | |
| 174 | + pinctrl_backlight: backlightgrp { | |
| 175 | + fsl,pins = < | |
| 176 | + MX27_PAD_PWMO__GPIO5_5 0x0 | |
| 177 | + >; | |
| 178 | + }; | |
| 179 | + | |
| 180 | + pinctrl_gpioleds: gpioledsgrp { | |
| 181 | + fsl,pins = < | |
| 182 | + MX27_PAD_PC_PWRON__GPIO6_16 0x0 | |
| 183 | + MX27_PAD_PC_CD2_B__GPIO6_19 0x0 | |
| 184 | + >; | |
| 185 | + }; | |
| 186 | + | |
| 187 | + pinctrl_imxfb: imxfbgrp { | |
| 188 | + fsl,pins = < | |
| 189 | + MX27_PAD_LD0__LD0 0x0 | |
| 190 | + MX27_PAD_LD1__LD1 0x0 | |
| 191 | + MX27_PAD_LD2__LD2 0x0 | |
| 192 | + MX27_PAD_LD3__LD3 0x0 | |
| 193 | + MX27_PAD_LD4__LD4 0x0 | |
| 194 | + MX27_PAD_LD5__LD5 0x0 | |
| 195 | + MX27_PAD_LD6__LD6 0x0 | |
| 196 | + MX27_PAD_LD7__LD7 0x0 | |
| 197 | + MX27_PAD_LD8__LD8 0x0 | |
| 198 | + MX27_PAD_LD9__LD9 0x0 | |
| 199 | + MX27_PAD_LD10__LD10 0x0 | |
| 200 | + MX27_PAD_LD11__LD11 0x0 | |
| 201 | + MX27_PAD_LD12__LD12 0x0 | |
| 202 | + MX27_PAD_LD13__LD13 0x0 | |
| 203 | + MX27_PAD_LD14__LD14 0x0 | |
| 204 | + MX27_PAD_LD15__LD15 0x0 | |
| 205 | + MX27_PAD_LD16__LD16 0x0 | |
| 206 | + MX27_PAD_LD17__LD17 0x0 | |
| 207 | + MX27_PAD_CONTRAST__CONTRAST 0x0 | |
| 208 | + MX27_PAD_OE_ACD__OE_ACD 0x0 | |
| 209 | + MX27_PAD_HSYNC__HSYNC 0x0 | |
| 210 | + MX27_PAD_VSYNC__VSYNC 0x0 | |
| 211 | + >; | |
| 212 | + }; | |
| 213 | + | |
| 214 | + pinctrl_lcdreg: lcdreggrp { | |
| 215 | + fsl,pins = < | |
| 216 | + MX27_PAD_CLS__GPIO1_25 0x0 | |
| 217 | + >; | |
| 218 | + }; | |
| 219 | + | |
| 220 | + pinctrl_sdhc1: sdhc1grp { | |
| 221 | + fsl,pins = < | |
| 222 | + MX27_PAD_SD1_CLK__SD1_CLK 0x0 | |
| 223 | + MX27_PAD_SD1_CMD__SD1_CMD 0x0 | |
| 224 | + MX27_PAD_SD1_D0__SD1_D0 0x0 | |
| 225 | + MX27_PAD_SD1_D1__SD1_D1 0x0 | |
| 226 | + MX27_PAD_SD1_D2__SD1_D2 0x0 | |
| 227 | + MX27_PAD_SD1_D3__SD1_D3 0x0 | |
| 228 | + >; | |
| 229 | + }; | |
| 230 | + | |
| 231 | + pinctrl_ssi1: ssi1grp { | |
| 232 | + fsl,pins = < | |
| 233 | + MX27_PAD_SSI4_CLK__SSI4_CLK 0x0 | |
| 234 | + MX27_PAD_SSI4_FS__SSI4_FS 0x0 | |
| 235 | + MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1 | |
| 236 | + MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1 | |
| 237 | + >; | |
| 238 | + }; | |
| 239 | + | |
| 240 | + pinctrl_touch: touchgrp { | |
| 241 | + fsl,pins = < | |
| 242 | + MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */ | |
| 243 | + >; | |
| 244 | + }; | |
| 245 | + | |
| 246 | + pinctrl_uart1: uart1grp { | |
| 247 | + fsl,pins = < | |
| 248 | + MX27_PAD_UART1_TXD__UART1_TXD 0x0 | |
| 249 | + MX27_PAD_UART1_RXD__UART1_RXD 0x0 | |
| 250 | + MX27_PAD_UART1_CTS__UART1_CTS 0x0 | |
| 251 | + MX27_PAD_UART1_RTS__UART1_RTS 0x0 | |
| 252 | + >; | |
| 253 | + }; | |
| 254 | + | |
| 255 | + pinctrl_uart2: uart2grp { | |
| 256 | + fsl,pins = < | |
| 257 | + MX27_PAD_UART2_TXD__UART2_TXD 0x0 | |
| 258 | + MX27_PAD_UART2_RXD__UART2_RXD 0x0 | |
| 259 | + MX27_PAD_UART2_CTS__UART2_CTS 0x0 | |
| 260 | + MX27_PAD_UART2_RTS__UART2_RTS 0x0 | |
| 261 | + >; | |
| 262 | + }; | |
| 263 | + | |
| 264 | + pinctrl_uart3: uart3grp { | |
| 265 | + fsl,pins = < | |
| 266 | + MX27_PAD_UART3_TXD__UART3_TXD 0x0 | |
| 267 | + MX27_PAD_UART3_RXD__UART3_RXD 0x0 | |
| 268 | + MX27_PAD_UART3_CTS__UART3_CTS 0x0 | |
| 269 | + MX27_PAD_UART3_RTS__UART3_RTS 0x0 | |
| 270 | + >; | |
| 271 | + }; | |
| 272 | + }; | |
| 273 | +}; | |
| @@ -28,7 +28,7 @@ · 27 unmodified lines | ||
| 28 | 28 | usbphy0: usbphy@0 { |
| 29 | 29 | compatible = "usb-nop-xceiv"; |
| 30 | 30 | reg = <0>; |
| 31 | − clocks = <&clks 0>; | |
| 31 | + clocks = <&clks IMX27_CLK_DUMMY>; | |
| 32 | 32 | clock-names = "main_clk"; |
| 33 | 33 | }; |
| 34 | 34 | }; |
| @@ -61,7 +61,7 @@ · 60 unmodified lines | ||
| 61 | 61 | compatible = "usb-nop-xceiv"; |
| 62 | 62 | reg = <2>; |
| 63 | 63 | vcc-supply = <®_5v0>; |
| 64 | − clocks = <&clks 0>; | |
| 64 | + clocks = <&clks IMX27_CLK_DUMMY>; | |
| 65 | 65 | clock-names = "main_clk"; |
| 66 | 66 | }; |
| 67 | 67 | }; |
| @@ -51,7 +51,7 @@ · 50 unmodified lines | ||
| 51 | 51 | compatible = "usb-nop-xceiv"; |
| 52 | 52 | reg = <0>; |
| 53 | 53 | vcc-supply = <&sw3_reg>; |
| 54 | − clocks = <&clks 0>; | |
| 54 | + clocks = <&clks IMX27_CLK_DUMMY>; | |
| 55 | 55 | clock-names = "main_clk"; |
| 56 | 56 | }; |
| 57 | 57 | }; |
| @@ -310,7 +310,6 @@ · 252 unmodified lines | ||
| 310 | 310 | &ssi1 { |
| 311 | 311 | pinctrl-names = "default"; |
| 312 | 312 | pinctrl-0 = <&pinctrl_ssi1>; |
| 313 | − fsl,mode = "i2s-slave"; | |
| 314 | 313 | status = "okay"; |
| 315 | 314 | }; |
| 316 | 315 | |
| @@ -101,14 +101,6 @@ · 100 unmodified lines | ||
| 101 | 101 | #define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x032 |
| 102 | 102 | #define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004 |
| 103 | 103 | #define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x032 |
| 104 | −#define MX27_PAD_UNUSED0__UNUSED0 0x20 0x004 | |
| 105 | −#define MX27_PAD_UNUSED0__GPIO2_0 0x20 0x032 | |
| 106 | −#define MX27_PAD_UNUSED1__UNUSED1 0x21 0x004 | |
| 107 | −#define MX27_PAD_UNUSED1__GPIO2_1 0x21 0x032 | |
| 108 | −#define MX27_PAD_UNUSED2__UNUSED2 0x22 0x004 | |
| 109 | −#define MX27_PAD_UNUSED2__GPIO2_2 0x22 0x032 | |
| 110 | −#define MX27_PAD_UNUSED3__UNUSED3 0x23 0x004 | |
| 111 | −#define MX27_PAD_UNUSED3__GPIO2_3 0x23 0x032 | |
| 112 | 104 | #define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004 |
| 113 | 105 | #define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005 |
| 114 | 106 | #define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x032 |
| @@ -183,16 +175,6 @@ · 68 unmodified lines | ||
| 183 | 175 | #define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004 |
| 184 | 176 | #define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001 |
| 185 | 177 | #define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x032 |
| 186 | −#define MX27_PAD_UNUSED4__UNUSED4 0x40 0x004 | |
| 187 | −#define MX27_PAD_UNUSED4__GPIO3_0 0x40 0x032 | |
| 188 | −#define MX27_PAD_UNUSED5__UNUSED5 0x41 0x004 | |
| 189 | −#define MX27_PAD_UNUSED5__GPIO3_1 0x41 0x032 | |
| 190 | −#define MX27_PAD_UNUSED6__UNUSED6 0x42 0x004 | |
| 191 | −#define MX27_PAD_UNUSED6__GPIO3_2 0x42 0x032 | |
| 192 | −#define MX27_PAD_UNUSED7__UNUSED7 0x43 0x004 | |
| 193 | −#define MX27_PAD_UNUSED7__GPIO3_3 0x43 0x032 | |
| 194 | −#define MX27_PAD_UNUSED8__UNUSED8 0x44 0x004 | |
| 195 | −#define MX27_PAD_UNUSED8__GPIO3_4 0x44 0x032 | |
| 196 | 178 | #define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004 |
| 197 | 179 | #define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x032 |
| 198 | 180 | #define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004 |
| @@ -422,18 +404,6 @@ · 223 unmodified lines | ||
| 422 | 404 | #define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x032 |
| 423 | 405 | #define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004 |
| 424 | 406 | #define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x032 |
| 425 | −#define MX27_PAD_UNUSED9__UNUSED9 0x9a 0x004 | |
| 426 | −#define MX27_PAD_UNUSED9__GPIO5_26 0x9a 0x032 | |
| 427 | −#define MX27_PAD_UNUSED10__UNUSED10 0x9b 0x004 | |
| 428 | −#define MX27_PAD_UNUSED10__GPIO5_27 0x9b 0x032 | |
| 429 | −#define MX27_PAD_UNUSED11__UNUSED11 0x9c 0x004 | |
| 430 | −#define MX27_PAD_UNUSED11__GPIO5_28 0x9c 0x032 | |
| 431 | −#define MX27_PAD_UNUSED12__UNUSED12 0x9d 0x004 | |
| 432 | −#define MX27_PAD_UNUSED12__GPIO5_29 0x9d 0x032 | |
| 433 | −#define MX27_PAD_UNUSED13__UNUSED13 0x9e 0x004 | |
| 434 | −#define MX27_PAD_UNUSED13__GPIO5_30 0x9e 0x032 | |
| 435 | −#define MX27_PAD_UNUSED14__UNUSED14 0x9f 0x004 | |
| 436 | −#define MX27_PAD_UNUSED14__GPIO5_31 0x9f 0x032 | |
| 437 | 407 | #define MX27_PAD_NFRB__NFRB 0xa0 0x000 |
| 438 | 408 | #define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005 |
| 439 | 409 | #define MX27_PAD_NFRB__GPIO6_0 0xa0 0x032 |
| @@ -506,21 +476,5 @@ · 66 unmodified lines | ||
| 506 | 476 | #define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005 |
| 507 | 477 | #define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006 |
| 508 | 478 | #define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x032 |
| 509 | −#define MX27_PAD_UNUSED15__UNUSED15 0xb8 0x004 | |
| 510 | −#define MX27_PAD_UNUSED15__GPIO6_24 0xb8 0x032 | |
| 511 | −#define MX27_PAD_UNUSED16__UNUSED16 0xb9 0x004 | |
| 512 | −#define MX27_PAD_UNUSED16__GPIO6_25 0xb9 0x032 | |
| 513 | −#define MX27_PAD_UNUSED17__UNUSED17 0xba 0x004 | |
| 514 | −#define MX27_PAD_UNUSED17__GPIO6_26 0xba 0x032 | |
| 515 | −#define MX27_PAD_UNUSED18__UNUSED18 0xbb 0x004 | |
| 516 | −#define MX27_PAD_UNUSED18__GPIO6_27 0xbb 0x032 | |
| 517 | −#define MX27_PAD_UNUSED19__UNUSED19 0xbc 0x004 | |
| 518 | −#define MX27_PAD_UNUSED19__GPIO6_28 0xbc 0x032 | |
| 519 | −#define MX27_PAD_UNUSED20__UNUSED20 0xbd 0x004 | |
| 520 | −#define MX27_PAD_UNUSED20__GPIO6_29 0xbd 0x032 | |
| 521 | −#define MX27_PAD_UNUSED21__UNUSED21 0xbe 0x004 | |
| 522 | −#define MX27_PAD_UNUSED21__GPIO6_30 0xbe 0x032 | |
| 523 | −#define MX27_PAD_UNUSED22__UNUSED22 0xbf 0x004 | |
| 524 | −#define MX27_PAD_UNUSED22__GPIO6_31 0xbf 0x032 | |
| 525 | 479 | |
| 526 | 480 | #endif /* __DTS_IMX27_PINFUNC_H */ |
| @@ -11,9 +11,11 @@ · 10 unmodified lines | ||
| 11 | 11 | |
| 12 | 12 | #include "skeleton.dtsi" |
| 13 | 13 | #include "imx27-pinfunc.h" |
| 14 | + | |
| 15 | +#include <dt-bindings/clock/imx27-clock.h> | |
| 16 | +#include <dt-bindings/gpio/gpio.h> | |
| 14 | 17 | #include <dt-bindings/input/input.h> |
| 15 | 18 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | −#include <dt-bindings/gpio/gpio.h> | |
| 17 | 19 | |
| 18 | 20 | / { |
| 19 | 21 | aliases { |
| @@ -68,7 +70,7 @@ · 48 unmodified lines | ||
| 68 | 70 | 399000 1450000 |
| 69 | 71 | >; |
| 70 | 72 | clock-latency = <62500>; |
| 71 | − clocks = <&clks 18>; | |
| 73 | + clocks = <&clks IMX27_CLK_CPU_DIV>; | |
| 72 | 74 | voltage-tolerance = <5>; |
| 73 | 75 | }; |
| 74 | 76 | }; |
| @@ -91,7 +93,8 @@ · 16 unmodified lines | ||
| 91 | 93 | compatible = "fsl,imx27-dma"; |
| 92 | 94 | reg = <0x10001000 0x1000>; |
| 93 | 95 | interrupts = <32>; |
| 94 | − clocks = <&clks 50>, <&clks 70>; | |
| 96 | + clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, | |
| 97 | + <&clks IMX27_CLK_DMA_AHB_GATE>; | |
| 95 | 98 | clock-names = "ipg", "ahb"; |
| 96 | 99 | #dma-cells = <1>; |
| 97 | 100 | #dma-channels = <16>; |
| @@ -101,14 +104,15 @@ · 3 unmodified lines | ||
| 101 | 104 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; |
| 102 | 105 | reg = <0x10002000 0x1000>; |
| 103 | 106 | interrupts = <27>; |
| 104 | − clocks = <&clks 74>; | |
| 107 | + clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>; | |
| 105 | 108 | }; |
| 106 | 109 | |
| 107 | 110 | gpt1: timer@10003000 { |
| 108 | 111 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; |
| 109 | 112 | reg = <0x10003000 0x1000>; |
| 110 | 113 | interrupts = <26>; |
| 111 | − clocks = <&clks 46>, <&clks 61>; | |
| 114 | + clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, | |
| 115 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 112 | 116 | clock-names = "ipg", "per"; |
| 113 | 117 | }; |
| 114 | 118 | |
| @@ -116,7 +120,8 @@ · 1 unmodified line | ||
| 116 | 120 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; |
| 117 | 121 | reg = <0x10004000 0x1000>; |
| 118 | 122 | interrupts = <25>; |
| 119 | − clocks = <&clks 45>, <&clks 61>; | |
| 123 | + clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>, | |
| 124 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 120 | 125 | clock-names = "ipg", "per"; |
| 121 | 126 | }; |
| 122 | 127 | |
| @@ -124,7 +129,8 @@ · 1 unmodified line | ||
| 124 | 129 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; |
| 125 | 130 | reg = <0x10005000 0x1000>; |
| 126 | 131 | interrupts = <24>; |
| 127 | − clocks = <&clks 44>, <&clks 61>; | |
| 132 | + clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>, | |
| 133 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 128 | 134 | clock-names = "ipg", "per"; |
| 129 | 135 | }; |
| 130 | 136 | |
| @@ -133,7 +139,8 @@ · 2 unmodified lines | ||
| 133 | 139 | compatible = "fsl,imx27-pwm"; |
| 134 | 140 | reg = <0x10006000 0x1000>; |
| 135 | 141 | interrupts = <23>; |
| 136 | − clocks = <&clks 34>, <&clks 61>; | |
| 142 | + clocks = <&clks IMX27_CLK_PWM_IPG_GATE>, | |
| 143 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 137 | 144 | clock-names = "ipg", "per"; |
| 138 | 145 | }; |
| 139 | 146 | |
| @@ -141,14 +148,14 @@ · 1 unmodified line | ||
| 141 | 148 | compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; |
| 142 | 149 | reg = <0x10008000 0x1000>; |
| 143 | 150 | interrupts = <21>; |
| 144 | − clocks = <&clks 37>; | |
| 151 | + clocks = <&clks IMX27_CLK_KPP_IPG_GATE>; | |
| 145 | 152 | status = "disabled"; |
| 146 | 153 | }; |
| 147 | 154 | |
| 148 | 155 | owire: owire@10009000 { |
| 149 | 156 | compatible = "fsl,imx27-owire", "fsl,imx21-owire"; |
| 150 | 157 | reg = <0x10009000 0x1000>; |
| 151 | − clocks = <&clks 35>; | |
| 158 | + clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>; | |
| 152 | 159 | status = "disabled"; |
| 153 | 160 | }; |
| 154 | 161 | |
| @@ -156,7 +163,8 @@ · 1 unmodified line | ||
| 156 | 163 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 157 | 164 | reg = <0x1000a000 0x1000>; |
| 158 | 165 | interrupts = <20>; |
| 159 | − clocks = <&clks 81>, <&clks 61>; | |
| 166 | + clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, | |
| 167 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 160 | 168 | clock-names = "ipg", "per"; |
| 161 | 169 | status = "disabled"; |
| 162 | 170 | }; |
| @@ -165,7 +173,8 @@ · 2 unmodified lines | ||
| 165 | 173 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 166 | 174 | reg = <0x1000b000 0x1000>; |
| 167 | 175 | interrupts = <19>; |
| 168 | − clocks = <&clks 80>, <&clks 61>; | |
| 176 | + clocks = <&clks IMX27_CLK_UART2_IPG_GATE>, | |
| 177 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 169 | 178 | clock-names = "ipg", "per"; |
| 170 | 179 | status = "disabled"; |
| 171 | 180 | }; |
| @@ -174,7 +183,8 @@ · 2 unmodified lines | ||
| 174 | 183 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 175 | 184 | reg = <0x1000c000 0x1000>; |
| 176 | 185 | interrupts = <18>; |
| 177 | − clocks = <&clks 79>, <&clks 61>; | |
| 186 | + clocks = <&clks IMX27_CLK_UART3_IPG_GATE>, | |
| 187 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 178 | 188 | clock-names = "ipg", "per"; |
| 179 | 189 | status = "disabled"; |
| 180 | 190 | }; |
| @@ -183,7 +193,8 @@ · 2 unmodified lines | ||
| 183 | 193 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 184 | 194 | reg = <0x1000d000 0x1000>; |
| 185 | 195 | interrupts = <17>; |
| 186 | − clocks = <&clks 78>, <&clks 61>; | |
| 196 | + clocks = <&clks IMX27_CLK_UART4_IPG_GATE>, | |
| 197 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 187 | 198 | clock-names = "ipg", "per"; |
| 188 | 199 | status = "disabled"; |
| 189 | 200 | }; |
| @@ -194,7 +205,8 @@ · 4 unmodified lines | ||
| 194 | 205 | compatible = "fsl,imx27-cspi"; |
| 195 | 206 | reg = <0x1000e000 0x1000>; |
| 196 | 207 | interrupts = <16>; |
| 197 | − clocks = <&clks 53>, <&clks 60>; | |
| 208 | + clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>, | |
| 209 | + <&clks IMX27_CLK_PER2_GATE>; | |
| 198 | 210 | clock-names = "ipg", "per"; |
| 199 | 211 | status = "disabled"; |
| 200 | 212 | }; |
| @@ -205,7 +217,8 @@ · 4 unmodified lines | ||
| 205 | 217 | compatible = "fsl,imx27-cspi"; |
| 206 | 218 | reg = <0x1000f000 0x1000>; |
| 207 | 219 | interrupts = <15>; |
| 208 | − clocks = <&clks 52>, <&clks 60>; | |
| 220 | + clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>, | |
| 221 | + <&clks IMX27_CLK_PER2_GATE>; | |
| 209 | 222 | clock-names = "ipg", "per"; |
| 210 | 223 | status = "disabled"; |
| 211 | 224 | }; |
| @@ -215,7 +228,7 @@ · 3 unmodified lines | ||
| 215 | 228 | compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; |
| 216 | 229 | reg = <0x10010000 0x1000>; |
| 217 | 230 | interrupts = <14>; |
| 218 | − clocks = <&clks 26>; | |
| 231 | + clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>; | |
| 219 | 232 | dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; |
| 220 | 233 | dma-names = "rx0", "tx0", "rx1", "tx1"; |
| 221 | 234 | fsl,fifo-depth = <8>; |
| @@ -227,7 +240,7 @@ · 5 unmodified lines | ||
| 227 | 240 | compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; |
| 228 | 241 | reg = <0x10011000 0x1000>; |
| 229 | 242 | interrupts = <13>; |
| 230 | − clocks = <&clks 25>; | |
| 243 | + clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>; | |
| 231 | 244 | dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; |
| 232 | 245 | dma-names = "rx0", "tx0", "rx1", "tx1"; |
| 233 | 246 | fsl,fifo-depth = <8>; |
| @@ -240,7 +253,7 @@ · 6 unmodified lines | ||
| 240 | 253 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
| 241 | 254 | reg = <0x10012000 0x1000>; |
| 242 | 255 | interrupts = <12>; |
| 243 | − clocks = <&clks 40>; | |
| 256 | + clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>; | |
| 244 | 257 | status = "disabled"; |
| 245 | 258 | }; |
| 246 | 259 | |
| @@ -248,7 +261,8 @@ · 1 unmodified line | ||
| 248 | 261 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; |
| 249 | 262 | reg = <0x10013000 0x1000>; |
| 250 | 263 | interrupts = <11>; |
| 251 | − clocks = <&clks 30>, <&clks 60>; | |
| 264 | + clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>, | |
| 265 | + <&clks IMX27_CLK_PER2_GATE>; | |
| 252 | 266 | clock-names = "ipg", "per"; |
| 253 | 267 | dmas = <&dma 7>; |
| 254 | 268 | dma-names = "rx-tx"; |
| @@ -259,7 +273,8 @@ · 4 unmodified lines | ||
| 259 | 273 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; |
| 260 | 274 | reg = <0x10014000 0x1000>; |
| 261 | 275 | interrupts = <10>; |
| 262 | − clocks = <&clks 29>, <&clks 60>; | |
| 276 | + clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>, | |
| 277 | + <&clks IMX27_CLK_PER2_GATE>; | |
| 263 | 278 | clock-names = "ipg", "per"; |
| 264 | 279 | dmas = <&dma 6>; |
| 265 | 280 | dma-names = "rx-tx"; |
| @@ -276,6 +291,7 @@ · 10 unmodified lines | ||
| 276 | 291 | gpio1: gpio@10015000 { |
| 277 | 292 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 278 | 293 | reg = <0x10015000 0x100>; |
| 294 | + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; | |
| 279 | 295 | interrupts = <8>; |
| 280 | 296 | gpio-controller; |
| 281 | 297 | #gpio-cells = <2>; |
| @@ -286,6 +302,7 @@ · 4 unmodified lines | ||
| 286 | 302 | gpio2: gpio@10015100 { |
| 287 | 303 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 288 | 304 | reg = <0x10015100 0x100>; |
| 305 | + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; | |
| 289 | 306 | interrupts = <8>; |
| 290 | 307 | gpio-controller; |
| 291 | 308 | #gpio-cells = <2>; |
| @@ -296,6 +313,7 @@ · 4 unmodified lines | ||
| 296 | 313 | gpio3: gpio@10015200 { |
| 297 | 314 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 298 | 315 | reg = <0x10015200 0x100>; |
| 316 | + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; | |
| 299 | 317 | interrupts = <8>; |
| 300 | 318 | gpio-controller; |
| 301 | 319 | #gpio-cells = <2>; |
| @@ -306,6 +324,7 @@ · 4 unmodified lines | ||
| 306 | 324 | gpio4: gpio@10015300 { |
| 307 | 325 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 308 | 326 | reg = <0x10015300 0x100>; |
| 327 | + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; | |
| 309 | 328 | interrupts = <8>; |
| 310 | 329 | gpio-controller; |
| 311 | 330 | #gpio-cells = <2>; |
| @@ -316,6 +335,7 @@ · 4 unmodified lines | ||
| 316 | 335 | gpio5: gpio@10015400 { |
| 317 | 336 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 318 | 337 | reg = <0x10015400 0x100>; |
| 338 | + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; | |
| 319 | 339 | interrupts = <8>; |
| 320 | 340 | gpio-controller; |
| 321 | 341 | #gpio-cells = <2>; |
| @@ -326,6 +346,7 @@ · 4 unmodified lines | ||
| 326 | 346 | gpio6: gpio@10015500 { |
| 327 | 347 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 328 | 348 | reg = <0x10015500 0x100>; |
| 349 | + clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; | |
| 329 | 350 | interrupts = <8>; |
| 330 | 351 | gpio-controller; |
| 331 | 352 | #gpio-cells = <2>; |
| @@ -337,7 +358,7 @@ · 5 unmodified lines | ||
| 337 | 358 | audmux: audmux@10016000 { |
| 338 | 359 | compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; |
| 339 | 360 | reg = <0x10016000 0x1000>; |
| 340 | − clocks = <&clks 0>; | |
| 361 | + clocks = <&clks IMX27_CLK_DUMMY>; | |
| 341 | 362 | clock-names = "audmux"; |
| 342 | 363 | status = "disabled"; |
| 343 | 364 | }; |
| @@ -348,7 +369,8 @@ · 4 unmodified lines | ||
| 348 | 369 | compatible = "fsl,imx27-cspi"; |
| 349 | 370 | reg = <0x10017000 0x1000>; |
| 350 | 371 | interrupts = <6>; |
| 351 | − clocks = <&clks 51>, <&clks 60>; | |
| 372 | + clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>, | |
| 373 | + <&clks IMX27_CLK_PER2_GATE>; | |
| 352 | 374 | clock-names = "ipg", "per"; |
| 353 | 375 | status = "disabled"; |
| 354 | 376 | }; |
| @@ -357,7 +379,8 @@ · 2 unmodified lines | ||
| 357 | 379 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; |
| 358 | 380 | reg = <0x10019000 0x1000>; |
| 359 | 381 | interrupts = <4>; |
| 360 | − clocks = <&clks 43>, <&clks 61>; | |
| 382 | + clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>, | |
| 383 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 361 | 384 | clock-names = "ipg", "per"; |
| 362 | 385 | }; |
| 363 | 386 | |
| @@ -365,7 +388,8 @@ · 1 unmodified line | ||
| 365 | 388 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; |
| 366 | 389 | reg = <0x1001a000 0x1000>; |
| 367 | 390 | interrupts = <3>; |
| 368 | − clocks = <&clks 42>, <&clks 61>; | |
| 391 | + clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>, | |
| 392 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 369 | 393 | clock-names = "ipg", "per"; |
| 370 | 394 | }; |
| 371 | 395 | |
| @@ -373,7 +397,8 @@ · 1 unmodified line | ||
| 373 | 397 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 374 | 398 | reg = <0x1001b000 0x1000>; |
| 375 | 399 | interrupts = <49>; |
| 376 | − clocks = <&clks 77>, <&clks 61>; | |
| 400 | + clocks = <&clks IMX27_CLK_UART5_IPG_GATE>, | |
| 401 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 377 | 402 | clock-names = "ipg", "per"; |
| 378 | 403 | status = "disabled"; |
| 379 | 404 | }; |
| @@ -382,7 +407,8 @@ · 2 unmodified lines | ||
| 382 | 407 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 383 | 408 | reg = <0x1001c000 0x1000>; |
| 384 | 409 | interrupts = <48>; |
| 385 | − clocks = <&clks 78>, <&clks 61>; | |
| 410 | + clocks = <&clks IMX27_CLK_UART6_IPG_GATE>, | |
| 411 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 386 | 412 | clock-names = "ipg", "per"; |
| 387 | 413 | status = "disabled"; |
| 388 | 414 | }; |
| @@ -393,7 +419,7 @@ · 4 unmodified lines | ||
| 393 | 419 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
| 394 | 420 | reg = <0x1001d000 0x1000>; |
| 395 | 421 | interrupts = <1>; |
| 396 | − clocks = <&clks 39>; | |
| 422 | + clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>; | |
| 397 | 423 | status = "disabled"; |
| 398 | 424 | }; |
| 399 | 425 | |
| @@ -401,7 +427,8 @@ · 1 unmodified line | ||
| 401 | 427 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; |
| 402 | 428 | reg = <0x1001e000 0x1000>; |
| 403 | 429 | interrupts = <9>; |
| 404 | − clocks = <&clks 28>, <&clks 60>; | |
| 430 | + clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>, | |
| 431 | + <&clks IMX27_CLK_PER2_GATE>; | |
| 405 | 432 | clock-names = "ipg", "per"; |
| 406 | 433 | dmas = <&dma 36>; |
| 407 | 434 | dma-names = "rx-tx"; |
| @@ -412,7 +439,8 @@ · 4 unmodified lines | ||
| 412 | 439 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; |
| 413 | 440 | reg = <0x1001f000 0x1000>; |
| 414 | 441 | interrupts = <2>; |
| 415 | − clocks = <&clks 41>, <&clks 61>; | |
| 442 | + clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>, | |
| 443 | + <&clks IMX27_CLK_PER1_GATE>; | |
| 416 | 444 | clock-names = "ipg", "per"; |
| 417 | 445 | }; |
| 418 | 446 | }; |
| @@ -428,7 +456,9 @@ · 9 unmodified lines | ||
| 428 | 456 | compatible = "fsl,imx27-fb", "fsl,imx21-fb"; |
| 429 | 457 | interrupts = <61>; |
| 430 | 458 | reg = <0x10021000 0x1000>; |
| 431 | − clocks = <&clks 36>, <&clks 65>, <&clks 59>; | |
| 459 | + clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>, | |
| 460 | + <&clks IMX27_CLK_LCDC_AHB_GATE>, | |
| 461 | + <&clks IMX27_CLK_PER3_GATE>; | |
| 432 | 462 | clock-names = "ipg", "ahb", "per"; |
| 433 | 463 | status = "disabled"; |
| 434 | 464 | }; |
| @@ -437,7 +467,8 @@ · 2 unmodified lines | ||
| 437 | 467 | compatible = "fsl,imx27-vpu"; |
| 438 | 468 | reg = <0x10023000 0x0200>; |
| 439 | 469 | interrupts = <53>; |
| 440 | − clocks = <&clks 57>, <&clks 66>; | |
| 470 | + clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, | |
| 471 | + <&clks IMX27_CLK_VPU_AHB_GATE>; | |
| 441 | 472 | clock-names = "per", "ahb"; |
| 442 | 473 | iram = <&iram>; |
| 443 | 474 | }; |
| @@ -446,7 +477,7 @@ · 2 unmodified lines | ||
| 446 | 477 | compatible = "fsl,imx27-usb"; |
| 447 | 478 | reg = <0x10024000 0x200>; |
| 448 | 479 | interrupts = <56>; |
| 449 | − clocks = <&clks 75>; | |
| 480 | + clocks = <&clks IMX27_CLK_USB_IPG_GATE>; | |
| 450 | 481 | fsl,usbmisc = <&usbmisc 0>; |
| 451 | 482 | status = "disabled"; |
| 452 | 483 | }; |
| @@ -455,7 +486,7 @@ · 2 unmodified lines | ||
| 455 | 486 | compatible = "fsl,imx27-usb"; |
| 456 | 487 | reg = <0x10024200 0x200>; |
| 457 | 488 | interrupts = <54>; |
| 458 | − clocks = <&clks 75>; | |
| 489 | + clocks = <&clks IMX27_CLK_USB_IPG_GATE>; | |
| 459 | 490 | fsl,usbmisc = <&usbmisc 1>; |
| 460 | 491 | status = "disabled"; |
| 461 | 492 | }; |
| @@ -464,7 +495,7 @@ · 2 unmodified lines | ||
| 464 | 495 | compatible = "fsl,imx27-usb"; |
| 465 | 496 | reg = <0x10024400 0x200>; |
| 466 | 497 | interrupts = <55>; |
| 467 | − clocks = <&clks 75>; | |
| 498 | + clocks = <&clks IMX27_CLK_USB_IPG_GATE>; | |
| 468 | 499 | fsl,usbmisc = <&usbmisc 2>; |
| 469 | 500 | status = "disabled"; |
| 470 | 501 | }; |
| @@ -473,14 +504,15 @@ · 2 unmodified lines | ||
| 473 | 504 | #index-cells = <1>; |
| 474 | 505 | compatible = "fsl,imx27-usbmisc"; |
| 475 | 506 | reg = <0x10024600 0x200>; |
| 476 | − clocks = <&clks 62>; | |
| 507 | + clocks = <&clks IMX27_CLK_USB_AHB_GATE>; | |
| 477 | 508 | }; |
| 478 | 509 | |
| 479 | 510 | sahara2: sahara@10025000 { |
| 480 | 511 | compatible = "fsl,imx27-sahara"; |
| 481 | 512 | reg = <0x10025000 0x1000>; |
| 482 | 513 | interrupts = <59>; |
| 483 | − clocks = <&clks 32>, <&clks 64>; | |
| 514 | + clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>, | |
| 515 | + <&clks IMX27_CLK_SAHARA_AHB_GATE>; | |
| 484 | 516 | clock-names = "ipg", "ahb"; |
| 485 | 517 | }; |
| 486 | 518 | |
| @@ -494,14 +526,15 @@ · 7 unmodified lines | ||
| 494 | 526 | compatible = "fsl,imx27-iim"; |
| 495 | 527 | reg = <0x10028000 0x1000>; |
| 496 | 528 | interrupts = <62>; |
| 497 | − clocks = <&clks 38>; | |
| 529 | + clocks = <&clks IMX27_CLK_IIM_IPG_GATE>; | |
| 498 | 530 | }; |
| 499 | 531 | |
| 500 | 532 | fec: ethernet@1002b000 { |
| 501 | 533 | compatible = "fsl,imx27-fec"; |
| 502 | 534 | reg = <0x1002b000 0x4000>; |
| 503 | 535 | interrupts = <50>; |
| 504 | − clocks = <&clks 48>, <&clks 67>; | |
| 536 | + clocks = <&clks IMX27_CLK_FEC_IPG_GATE>, | |
| 537 | + <&clks IMX27_CLK_FEC_AHB_GATE>; | |
| 505 | 538 | clock-names = "ipg", "ahb"; |
| 506 | 539 | status = "disabled"; |
| 507 | 540 | }; |
| @@ -513,7 +546,7 @@ · 5 unmodified lines | ||
| 513 | 546 | compatible = "fsl,imx27-nand"; |
| 514 | 547 | reg = <0xd8000000 0x1000>; |
| 515 | 548 | interrupts = <29>; |
| 516 | − clocks = <&clks 54>; | |
| 549 | + clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>; | |
| 517 | 550 | status = "disabled"; |
| 518 | 551 | }; |
| 519 | 552 | |
| @@ -522,7 +555,7 @@ · 2 unmodified lines | ||
| 522 | 555 | #size-cells = <1>; |
| 523 | 556 | compatible = "fsl,imx27-weim"; |
| 524 | 557 | reg = <0xd8002000 0x1000>; |
| 525 | − clocks = <&clks 0>; | |
| 558 | + clocks = <&clks IMX27_CLK_EMI_AHB_GATE>; | |
| 526 | 559 | ranges = < |
| 527 | 560 | 0 0 0xc0000000 0x08000000 |
| 528 | 561 | 1 0 0xc8000000 0x08000000 |
| @@ -53,6 +53,17 @@ · 52 unmodified lines | ||
| 53 | 53 | fsl,pull-up = <MXS_PULL_DISABLE>; |
| 54 | 54 | }; |
| 55 | 55 | |
| 56 | + mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 { | |
| 57 | + reg = <0>; | |
| 58 | + fsl,pinmux-ids = < | |
| 59 | + 0x31c3 /* | |
| 60 | + MX28_PAD_PWM3__GPIO_3_28 */ | |
| 61 | + >; | |
| 62 | + fsl,drive-strength = <0>; | |
| 63 | + fsl,voltage = <1>; | |
| 64 | + fsl,pull-up = <0>; | |
| 65 | + }; | |
| 66 | + | |
| 56 | 67 | }; |
| 57 | 68 | |
| 58 | 69 | ssp0: ssp@80010000 { |
| @@ -60,6 +71,7 @@ · 1 unmodified line | ||
| 60 | 71 | pinctrl-names = "default"; |
| 61 | 72 | pinctrl-0 = <&mmc0_4bit_pins_a |
| 62 | 73 | &mmc0_cd_cfg &mmc0_sck_cfg>; |
| 74 | + vmmc-supply = <®_vddio_sd0>; | |
| 63 | 75 | bus-width = <4>; |
| 64 | 76 | status = "okay"; |
| 65 | 77 | }; |
| @@ -116,4 +128,14 @@ · 50 unmodified lines | ||
| 116 | 128 | default-state = "on"; |
| 117 | 129 | }; |
| 118 | 130 | }; |
| 131 | + | |
| 132 | + reg_vddio_sd0: vddio-sd0 { | |
| 133 | + compatible = "regulator-fixed"; | |
| 134 | + pinctrl-names = "default"; | |
| 135 | + pinctrl-0 = <&mmc_pwr_cfa10036>; | |
| 136 | + regulator-name = "vddio-sd0"; | |
| 137 | + regulator-min-microvolt = <3300000>; | |
| 138 | + regulator-max-microvolt = <3300000>; | |
| 139 | + gpio = <&gpio3 28 0>; | |
| 140 | + }; | |
| 119 | 141 | }; |
| @@ -0,0 +1,87 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) 2014 Marek Vasut <marex@denx.de> | |
| 3 | + * | |
| 4 | + * The code contained herein is licensed under the GNU General Public | |
| 5 | + * License. You may obtain a copy of the GNU General Public License | |
| 6 | + * Version 2 or later at the following locations: | |
| 7 | + * | |
| 8 | + * http://www.opensource.org/licenses/gpl-license.html | |
| 9 | + * http://www.gnu.org/copyleft/gpl.html | |
| 10 | + */ | |
| 11 | + | |
| 12 | +#include "imx28.dtsi" | |
| 13 | + | |
| 14 | +/ { | |
| 15 | + model = "DENX M28"; | |
| 16 | + compatible = "denx,m28", "fsl,imx28"; | |
| 17 | + | |
| 18 | + memory { | |
| 19 | + reg = <0x40000000 0x08000000>; | |
| 20 | + }; | |
| 21 | + | |
| 22 | + apb@80000000 { | |
| 23 | + apbh@80000000 { | |
| 24 | + gpmi-nand@8000c000 { | |
| 25 | + #address-cells = <1>; | |
| 26 | + #size-cells = <1>; | |
| 27 | + pinctrl-names = "default"; | |
| 28 | + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; | |
| 29 | + status = "okay"; | |
| 30 | + | |
| 31 | + partition@0 { | |
| 32 | + label = "bootloader"; | |
| 33 | + reg = <0x00000000 0x00300000>; | |
| 34 | + read-only; | |
| 35 | + }; | |
| 36 | + | |
| 37 | + partition@1 { | |
| 38 | + label = "environment"; | |
| 39 | + reg = <0x00300000 0x00080000>; | |
| 40 | + }; | |
| 41 | + | |
| 42 | + partition@2 { | |
| 43 | + label = "redundant-environment"; | |
| 44 | + reg = <0x00380000 0x00080000>; | |
| 45 | + }; | |
| 46 | + | |
| 47 | + partition@3 { | |
| 48 | + label = "kernel"; | |
| 49 | + reg = <0x00400000 0x00400000>; | |
| 50 | + }; | |
| 51 | + | |
| 52 | + partition@4 { | |
| 53 | + label = "filesystem"; | |
| 54 | + reg = <0x00800000 0x0f800000>; | |
| 55 | + }; | |
| 56 | + }; | |
| 57 | + }; | |
| 58 | + | |
| 59 | + apbx@80040000 { | |
| 60 | + i2c0: i2c@80058000 { | |
| 61 | + pinctrl-names = "default"; | |
| 62 | + pinctrl-0 = <&i2c0_pins_a>; | |
| 63 | + status = "okay"; | |
| 64 | + | |
| 65 | + rtc: rtc@68 { | |
| 66 | + compatible = "stm,m41t62"; | |
| 67 | + reg = <0x68>; | |
| 68 | + }; | |
| 69 | + }; | |
| 70 | + }; | |
| 71 | + }; | |
| 72 | + | |
| 73 | + regulators { | |
| 74 | + compatible = "simple-bus"; | |
| 75 | + #address-cells = <1>; | |
| 76 | + #size-cells = <0>; | |
| 77 | + | |
| 78 | + reg_3p3v: regulator@0 { | |
| 79 | + compatible = "regulator-fixed"; | |
| 80 | + reg = <0>; | |
| 81 | + regulator-name = "3P3V"; | |
| 82 | + regulator-min-microvolt = <3300000>; | |
| 83 | + regulator-max-microvolt = <3300000>; | |
| 84 | + regulator-always-on; | |
| 85 | + }; | |
| 86 | + }; | |
| 87 | +}; | |
| @@ -10,52 +10,14 @@ · 9 unmodified lines | ||
| 10 | 10 | */ |
| 11 | 11 | |
| 12 | 12 | /dts-v1/; |
| 13 | −#include "imx28.dtsi" | |
| 13 | +#include "imx28-m28.dtsi" | |
| 14 | 14 | |
| 15 | 15 | / { |
| 16 | 16 | model = "DENX M28EVK"; |
| 17 | 17 | compatible = "denx,m28evk", "fsl,imx28"; |
| 18 | 18 | |
| 19 | − memory { | |
| 20 | − reg = <0x40000000 0x08000000>; | |
| 21 | − }; | |
| 22 | − | |
| 23 | 19 | apb@80000000 { |
| 24 | 20 | apbh@80000000 { |
| 25 | − gpmi-nand@8000c000 { | |
| 26 | − #address-cells = <1>; | |
| 27 | − #size-cells = <1>; | |
| 28 | − pinctrl-names = "default"; | |
| 29 | − pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; | |
| 30 | − status = "okay"; | |
| 31 | − | |
| 32 | − partition@0 { | |
| 33 | − label = "bootloader"; | |
| 34 | − reg = <0x00000000 0x00300000>; | |
| 35 | − read-only; | |
| 36 | − }; | |
| 37 | − | |
| 38 | − partition@1 { | |
| 39 | − label = "environment"; | |
| 40 | − reg = <0x00300000 0x00080000>; | |
| 41 | − }; | |
| 42 | − | |
| 43 | − partition@2 { | |
| 44 | − label = "redundant-environment"; | |
| 45 | − reg = <0x00380000 0x00080000>; | |
| 46 | − }; | |
| 47 | − | |
| 48 | − partition@3 { | |
| 49 | − label = "kernel"; | |
| 50 | − reg = <0x00400000 0x00400000>; | |
| 51 | − }; | |
| 52 | − | |
| 53 | − partition@4 { | |
| 54 | − label = "filesystem"; | |
| 55 | − reg = <0x00800000 0x0f800000>; | |
| 56 | − }; | |
| 57 | − }; | |
| 58 | − | |
| 59 | 21 | ssp0: ssp@80010000 { |
| 60 | 22 | compatible = "fsl,imx28-mmc"; |
| 61 | 23 | pinctrl-names = "default"; |
| @@ -175,10 +137,6 @@ · 113 unmodified lines | ||
| 175 | 137 | }; |
| 176 | 138 | |
| 177 | 139 | i2c0: i2c@80058000 { |
| 178 | − pinctrl-names = "default"; | |
| 179 | − pinctrl-0 = <&i2c0_pins_a>; | |
| 180 | − status = "okay"; | |
| 181 | − | |
| 182 | 140 | sgtl5000: codec@0a { |
| 183 | 141 | compatible = "fsl,sgtl5000"; |
| 184 | 142 | reg = <0x0a>; |
| @@ -192,11 +150,6 @@ · 7 unmodified lines | ||
| 192 | 150 | reg = <0x51>; |
| 193 | 151 | pagesize = <32>; |
| 194 | 152 | }; |
| 195 | − | |
| 196 | − rtc: rtc@68 { | |
| 197 | − compatible = "stm,m41t62"; | |
| 198 | − reg = <0x68>; | |
| 199 | − }; | |
| 200 | 153 | }; |
| 201 | 154 | |
| 202 | 155 | lradc@80050000 { |
| @@ -284,19 +237,6 @@ · 81 unmodified lines | ||
| 284 | 237 | }; |
| 285 | 238 | |
| 286 | 239 | regulators { |
| 287 | − compatible = "simple-bus"; | |
| 288 | − #address-cells = <1>; | |
| 289 | − #size-cells = <0>; | |
| 290 | − | |
| 291 | − reg_3p3v: regulator@0 { | |
| 292 | − compatible = "regulator-fixed"; | |
| 293 | − reg = <0>; | |
| 294 | − regulator-name = "3P3V"; | |
| 295 | − regulator-min-microvolt = <3300000>; | |
| 296 | − regulator-max-microvolt = <3300000>; | |
| 297 | − regulator-always-on; | |
| 298 | − }; | |
| 299 | − | |
| 300 | 240 | reg_vddio_sd0: regulator@1 { |
| 301 | 241 | compatible = "regulator-fixed"; |
| 302 | 242 | reg = <1>; |
| @@ -133,7 +133,6 @@ · 132 unmodified lines | ||
| 133 | 133 | |
| 134 | 134 | &ssi1 { |
| 135 | 135 | codec-handle = <&tlv320aic23>; |
| 136 | − fsl,mode = "i2s-slave"; | |
| 137 | 136 | status = "okay"; |
| 138 | 137 | }; |
| 139 | 138 | |
| @@ -193,6 +193,14 @@ · 192 unmodified lines | ||
| 193 | 193 | #clock-cells = <1>; |
| 194 | 194 | }; |
| 195 | 195 | |
| 196 | + gpt: timer@53f90000 { | |
| 197 | + compatible = "fsl,imx35-gpt", "fsl,imx31-gpt"; | |
| 198 | + reg = <0x53f90000 0x4000>; | |
| 199 | + interrupts = <29>; | |
| 200 | + clocks = <&clks 9>, <&clks 50>; | |
| 201 | + clock-names = "ipg", "per"; | |
| 202 | + }; | |
| 203 | + | |
| 196 | 204 | gpio3: gpio@53fa4000 { |
| 197 | 205 | compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; |
| 198 | 206 | reg = <0x53fa4000 0x4000>; |
| @@ -151,8 +151,10 @@ · 150 unmodified lines | ||
| 151 | 151 | reg = <0x50014000 0x4000>; |
| 152 | 152 | interrupts = <30>; |
| 153 | 153 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; |
| 154 | + dmas = <&sdma 24 1 0>, | |
| 155 | + <&sdma 25 1 0>; | |
| 156 | + dma-names = "rx", "tx"; | |
| 154 | 157 | fsl,fifo-depth = <15>; |
| 155 | − fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ | |
| 156 | 158 | status = "disabled"; |
| 157 | 159 | }; |
| 158 | 160 | |
| @@ -457,8 +459,10 @@ · 298 unmodified lines | ||
| 457 | 459 | reg = <0x63fcc000 0x4000>; |
| 458 | 460 | interrupts = <29>; |
| 459 | 461 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; |
| 462 | + dmas = <&sdma 28 0 0>, | |
| 463 | + <&sdma 29 0 0>; | |
| 464 | + dma-names = "rx", "tx"; | |
| 460 | 465 | fsl,fifo-depth = <15>; |
| 461 | − fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ | |
| 462 | 466 | status = "disabled"; |
| 463 | 467 | }; |
| 464 | 468 | |
| @@ -203,6 +203,7 @@ · 202 unmodified lines | ||
| 203 | 203 | reg = <0>; |
| 204 | 204 | interrupt-parent = <&gpio1>; |
| 205 | 205 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; |
| 206 | + fsl,mc13xxx-uses-rtc; | |
| 206 | 207 | |
| 207 | 208 | regulators { |
| 208 | 209 | sw1_reg: sw1 { |
| @@ -392,7 +393,6 @@ · 183 unmodified lines | ||
| 392 | 393 | }; |
| 393 | 394 | |
| 394 | 395 | &ssi2 { |
| 395 | − fsl,mode = "i2s-slave"; | |
| 396 | 396 | status = "okay"; |
| 397 | 397 | }; |
| 398 | 398 | |
| @@ -255,7 +255,6 @@ · 254 unmodified lines | ||
| 255 | 255 | |
| 256 | 256 | &ssi2 { |
| 257 | 257 | codec-handle = <&tlv320aic23>; |
| 258 | − fsl,mode = "i2s-slave"; | |
| 259 | 258 | status = "okay"; |
| 260 | 259 | }; |
| 261 | 260 | |
| @@ -218,7 +218,6 @@ · 217 unmodified lines | ||
| 218 | 218 | <&sdma 25 1 0>; |
| 219 | 219 | dma-names = "rx", "tx"; |
| 220 | 220 | fsl,fifo-depth = <15>; |
| 221 | − fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ | |
| 222 | 221 | status = "disabled"; |
| 223 | 222 | }; |
| 224 | 223 | |
| @@ -508,7 +507,6 @@ · 283 unmodified lines | ||
| 508 | 507 | <&sdma 29 0 0>; |
| 509 | 508 | dma-names = "rx", "tx"; |
| 510 | 509 | fsl,fifo-depth = <15>; |
| 511 | − fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ | |
| 512 | 510 | status = "disabled"; |
| 513 | 511 | }; |
| 514 | 512 | |
| @@ -564,7 +562,6 @@ · 49 unmodified lines | ||
| 564 | 562 | <&sdma 47 0 0>; |
| 565 | 563 | dma-names = "rx", "tx"; |
| 566 | 564 | fsl,fifo-depth = <15>; |
| 567 | − fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ | |
| 568 | 565 | status = "disabled"; |
| 569 | 566 | }; |
| 570 | 567 | |
| @@ -0,0 +1,140 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) 2014 Marek Vasut <marex@denx.de> | |
| 3 | + * | |
| 4 | + * The code contained herein is licensed under the GNU General Public | |
| 5 | + * License. You may obtain a copy of the GNU General Public License | |
| 6 | + * Version 2 or later at the following locations: | |
| 7 | + * | |
| 8 | + * http://www.opensource.org/licenses/gpl-license.html | |
| 9 | + * http://www.gnu.org/copyleft/gpl.html | |
| 10 | + */ | |
| 11 | + | |
| 12 | +#include "imx53.dtsi" | |
| 13 | + | |
| 14 | +/ { | |
| 15 | + model = "DENX M53"; | |
| 16 | + compatible = "denx,imx53-m53", "fsl,imx53"; | |
| 17 | + | |
| 18 | + memory { | |
| 19 | + reg = <0x70000000 0x20000000>, | |
| 20 | + <0xb0000000 0x20000000>; | |
| 21 | + }; | |
| 22 | + | |
| 23 | + regulators { | |
| 24 | + compatible = "simple-bus"; | |
| 25 | + #address-cells = <1>; | |
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