This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
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| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | ||
| 2 | /* | ||
| 3 | * Analog Devices Generic AXI ADC IP core driver/library | ||
| 4 | * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip | ||
| 5 | * | ||
| 6 | * Copyright 2012-2020 Analog Devices Inc. | ||
| 7 | */ | ||
| 8 | #ifndef __ADI_AXI_ADC_H__ | ||
| 9 | #define __ADI_AXI_ADC_H__ | ||
| 10 | |||
| 11 | struct device; | ||
| 12 | struct iio_chan_spec; | ||
| 13 | |||
| 14 | /** | ||
| 15 | * struct adi_axi_adc_chip_info - Chip specific information | ||
| 16 | * @name Chip name | ||
| 17 | * @id Chip ID (usually product ID) | ||
| 18 | * @channels Channel specifications of type @struct axi_adc_chan_spec | ||
| 19 | * @num_channels Number of @channels | ||
| 20 | * @scale_table Supported scales by the chip; tuples of 2 ints | ||
| 21 | * @num_scales Number of scales in the table | ||
| 22 | * @max_rate Maximum sampling rate supported by the device | ||
| 23 | */ | ||
| 24 | struct adi_axi_adc_chip_info { | ||
| 25 | const char *name; | ||
| 26 | unsigned int id; | ||
| 27 | |||
| 28 | const struct iio_chan_spec *channels; | ||
| 29 | unsigned int num_channels; | ||
| 30 | |||
| 31 | const unsigned int (*scale_table)[2]; | ||
| 32 | int num_scales; | ||
| 33 | |||
| 34 | unsigned long max_rate; | ||
| 35 | }; | ||
| 36 | |||
| 37 | /** | ||
| 38 | * struct adi_axi_adc_conv - data of the ADC attached to the AXI ADC | ||
| 39 | * @chip_info chip info details for the client ADC | ||
| 40 | * @preenable_setup op to run in the client before enabling the AXI ADC | ||
| 41 | * @reg_access IIO debugfs_reg_access hook for the client ADC | ||
| 42 | * @read_raw IIO read_raw hook for the client ADC | ||
| 43 | * @write_raw IIO write_raw hook for the client ADC | ||
| 44 | */ | ||
| 45 | struct adi_axi_adc_conv { | ||
| 46 | const struct adi_axi_adc_chip_info *chip_info; | ||
| 47 | |||
| 48 | int (*preenable_setup)(struct adi_axi_adc_conv *conv); | ||
| 49 | int (*reg_access)(struct adi_axi_adc_conv *conv, unsigned int reg, | ||
| 50 | unsigned int writeval, unsigned int *readval); | ||
| 51 | int (*read_raw)(struct adi_axi_adc_conv *conv, | ||
| 52 | struct iio_chan_spec const *chan, | ||
| 53 | int *val, int *val2, long mask); | ||
| 54 | int (*write_raw)(struct adi_axi_adc_conv *conv, | ||
| 55 | struct iio_chan_spec const *chan, | ||
| 56 | int val, int val2, long mask); | ||
| 57 | }; | ||
| 58 | |||
| 59 | struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev, | ||
| 60 | size_t sizeof_priv); | ||
| 61 | |||
| 62 | void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv); | ||
| 63 | |||
| 64 | #endif | ||