These were never used and are duplicated with the interface that is used. Maybe leftovers from a previous revision of the patch that added them.
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| @@ -1555,27 +1555,6 @@ struct drm_amdgpu_info_hw_ip { · 1554 unmodified lines | ||
| 1555 | 1555 | __u32 userq_num_slots; |
| 1556 | 1556 | }; |
| 1557 | 1557 | |
| 1558 | −/* GFX metadata BO sizes and alignment info (in bytes) */ | |
| 1559 | −struct drm_amdgpu_info_uq_fw_areas_gfx { | |
| 1560 | − /* shadow area size */ | |
| 1561 | − __u32 shadow_size; | |
| 1562 | − /* shadow area base virtual mem alignment */ | |
| 1563 | − __u32 shadow_alignment; | |
| 1564 | − /* context save area size */ | |
| 1565 | − __u32 csa_size; | |
| 1566 | − /* context save area base virtual mem alignment */ | |
| 1567 | − __u32 csa_alignment; | |
| 1568 | −}; | |
| 1569 | − | |
| 1570 | −/* IP specific fw related information used in the | |
| 1571 | − * subquery AMDGPU_INFO_UQ_FW_AREAS | |
| 1572 | − */ | |
| 1573 | −struct drm_amdgpu_info_uq_fw_areas { | |
| 1574 | − union { | |
| 1575 | − struct drm_amdgpu_info_uq_fw_areas_gfx gfx; | |
| 1576 | − }; | |
| 1577 | −}; | |
| 1578 | − | |
| 1579 | 1558 | struct drm_amdgpu_info_num_handles { |
| 1580 | 1559 | /** Max handles as supported by firmware for UVD */ |
| 1581 | 1560 | __u32 uvd_max_handles; |