| @@ -73,33 +73,6 @@ · 72 unmodified lines |
| 73 | #include <asm/cachectl.h> | 73 | #include <asm/cachectl.h> |
| 74 | #include <asm/setup.h> | 74 | #include <asm/setup.h> |
| 75 | | 75 | |
| 76 | /* Instruction cache related Auxiliary registers */ | | |
| 77 | #define ARC_REG_IC_BCR 0x77 /* Build Config reg */ | | |
| 78 | #define ARC_REG_IC_IVIC 0x10 | | |
| 79 | #define ARC_REG_IC_CTRL 0x11 | | |
| 80 | #define ARC_REG_IC_IVIL 0x19 | | |
| 81 | #if (CONFIG_ARC_MMU_VER > 2) | | |
| 82 | #define ARC_REG_IC_PTAG 0x1E | | |
| 83 | #endif | | |
| 84 | | | |
| 85 | /* Bit val in IC_CTRL */ | | |
| 86 | #define IC_CTRL_CACHE_DISABLE 0x1 | | |
| 87 | | | |
| 88 | /* Data cache related Auxiliary registers */ | | |
| 89 | #define ARC_REG_DC_BCR 0x72 /* Build Config reg */ | | |
| 90 | #define ARC_REG_DC_IVDC 0x47 | | |
| 91 | #define ARC_REG_DC_CTRL 0x48 | | |
| 92 | #define ARC_REG_DC_IVDL 0x4A | | |
| 93 | #define ARC_REG_DC_FLSH 0x4B | | |
| 94 | #define ARC_REG_DC_FLDL 0x4C | | |
| 95 | #if (CONFIG_ARC_MMU_VER > 2) | | |
| 96 | #define ARC_REG_DC_PTAG 0x5C | | |
| 97 | #endif | | |
| 98 | | | |
| 99 | /* Bit val in DC_CTRL */ | | |
| 100 | #define DC_CTRL_INV_MODE_FLUSH 0x40 | | |
| 101 | #define DC_CTRL_FLUSH_STATUS 0x100 | | |
| 102 | | | |
| 103 | char *arc_cache_mumbojumbo(int c, char *buf, int len) | 76 | char *arc_cache_mumbojumbo(int c, char *buf, int len) |
| 104 | { | 77 | { |
| 105 | int n = 0; | 78 | int n = 0; |
| @@ -168,72 +141,43 @@ void read_decode_cache_bcr(void) · 62 unmodified lines |
| 168 | */ | 141 | */ |
| 169 | void arc_cache_init(void) | 142 | void arc_cache_init(void) |
| 170 | { | 143 | { |
| 171 | unsigned int cpu = smp_processor_id(); | 144 | unsigned int __maybe_unused cpu = smp_processor_id(); |
| 172 | struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; | 145 | struct cpuinfo_arc_cache __maybe_unused *ic, __maybe_unused *dc; |
| 173 | struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; | | |
| 174 | unsigned int dcache_does_alias, temp; | | |
| 175 | char str[256]; | 146 | char str[256]; |
| 176 | | 147 | |
| 177 | printk(arc_cache_mumbojumbo(0, str, sizeof(str))); | 148 | printk(arc_cache_mumbojumbo(0, str, sizeof(str))); |
| 178 | | 149 | |
| 179 | if (!ic->ver) | | |
| 180 | goto chk_dc; | | |
| 181 | | | |
| 182 | #ifdef CONFIG_ARC_HAS_ICACHE | 150 | #ifdef CONFIG_ARC_HAS_ICACHE |
| 183 | /* 1. Confirm some of I-cache params which Linux assumes */ | 151 | ic = &cpuinfo_arc700[cpu].icache; |
| 184 | if (ic->line_len != L1_CACHE_BYTES) | 152 | if (ic->ver) { |
| 185 | panic("Cache H/W doesn't match kernel Config"); | 153 | if (ic->line_len != L1_CACHE_BYTES) |
| 186 | | 154 | panic("ICache line [%d] != kernel Config [%d]", |
| 187 | if (ic->ver != CONFIG_ARC_MMU_VER) | 155 | ic->line_len, L1_CACHE_BYTES); |
| 188 | panic("Cache ver doesn't match MMU ver\n"); | 156 | |
| 189 | #endif | 157 | if (ic->ver != CONFIG_ARC_MMU_VER) |
| 190 | | 158 | panic("Cache ver [%d] doesn't match MMU ver [%d]\n", |
| 191 | /* Enable/disable I-Cache */ | 159 | ic->ver, CONFIG_ARC_MMU_VER); |
| 192 | temp = read_aux_reg(ARC_REG_IC_CTRL); | 160 | } |
| 193 | | | |
| 194 | #ifdef CONFIG_ARC_HAS_ICACHE | | |
| 195 | temp &= ~IC_CTRL_CACHE_DISABLE; | | |
| 196 | #else | | |
| 197 | temp |= IC_CTRL_CACHE_DISABLE; | | |
| 198 | #endif | 161 | #endif |
| 199 | | 162 | |
| 200 | write_aux_reg(ARC_REG_IC_CTRL, temp); | | |
| 201 | | | |
| 202 | chk_dc: | | |
| 203 | if (!dc->ver) | | |
| 204 | return; | | |
| 205 | | | |
| 206 | #ifdef CONFIG_ARC_HAS_DCACHE | 163 | #ifdef CONFIG_ARC_HAS_DCACHE |
| 207 | if (dc->line_len != L1_CACHE_BYTES) | 164 | dc = &cpuinfo_arc700[cpu].dcache; |
| 208 | panic("Cache H/W doesn't match kernel Config"); | 165 | if (dc->ver) { |
| | 166 | unsigned int dcache_does_alias; |
| 209 | | 167 | |
| 210 | /* check for D-Cache aliasing */ | 168 | if (dc->line_len != L1_CACHE_BYTES) |
| 211 | dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE; | 169 | panic("DCache line [%d] != kernel Config [%d]", |
| | 170 | dc->line_len, L1_CACHE_BYTES); |
| 212 | | 171 | |
| 213 | if (dcache_does_alias && !cache_is_vipt_aliasing()) | 172 | /* check for D-Cache aliasing */ |
| 214 | panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); | 173 | dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE; |
| 215 | else if (!dcache_does_alias && cache_is_vipt_aliasing()) | | |
| 216 | panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n"); | | |
| 217 | #endif | | |
| 218 | | 174 | |
| 219 | /* Set the default Invalidate Mode to "simpy discard dirty lines" | 175 | if (dcache_does_alias && !cache_is_vipt_aliasing()) |
| 220 | * as this is more frequent then flush before invalidate | 176 | panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); |
| 221 | * Ofcourse we toggle this default behviour when desired | 177 | else if (!dcache_does_alias && cache_is_vipt_aliasing()) |
| 222 | */ | 178 | panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n"); |
| 223 | temp = read_aux_reg(ARC_REG_DC_CTRL); | 179 | } |
| 224 | temp &= ~DC_CTRL_INV_MODE_FLUSH; | | |
| 225 | | | |
| 226 | #ifdef CONFIG_ARC_HAS_DCACHE | | |
| 227 | /* Enable D-Cache: Clear Bit 0 */ | | |
| 228 | write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE); | | |
| 229 | #else | | |
| 230 | /* Flush D cache */ | | |
| 231 | write_aux_reg(ARC_REG_DC_FLSH, 0x1); | | |
| 232 | /* Disable D cache */ | | |
| 233 | write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE); | | |
| 234 | #endif | 180 | #endif |
| 235 | | | |
| 236 | return; | | |
| 237 | } | 181 | } |
| 238 | | 182 | |
| 239 | #define OP_INV 0x1 | 183 | #define OP_INV 0x1 |