Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd: "A handful of critical fixes for changes introduce this merge window. - The TI sci_clk_get() API was pretty broken and nobody noticed. - There were some CPUfreq crashes on C.H.I.P devices because we failed to propagate rates up the clk tree. - Also, the Intel Atom PMC clk driver needs to mark a clk critical if the firmware has it enabled already so that audio doesn't get killed on Baytrail. - Gemini devices have a dead serial console because the reset control usage in the serial driver assume one method of reset that gemini doesn't support (this will be fixed in the next version in the reset framework so this is the small fix for -rc series). - Finally we have two rate calculation fixes, one for Exynos and one for Meson SoCs, that fix rate inconsistencies" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: keystone: sci-clk: Fix sci_clk_get clk: meson: mpll: fix mpll0 fractional part ignored clk: samsung: exynos5420: The EPLL rate table corrections clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock clk: x86: Do not gate clocks enabled by the firmware clk: gemini: Fix reset regression

Linus Torvalds committed 9 years ago

Commit ef9ca022 parents 6999507 f54d2cd9 files · +90 −33Browse files

Unified · Split

9 files

drivers/clk/clk-gemini.c +14 −0
drivers/clk/keystone/sci-clk.c +42 −24
drivers/clk/meson/clk-mpll.c +7 −0
drivers/clk/meson/clkc.h +1 −0
drivers/clk/meson/gxbb.c +5 −0
drivers/clk/meson/meson8b.c +5 −0
drivers/clk/samsung/clk-exynos5420.c +8 −8
drivers/clk/sunxi-ng/ccu-sun5i.c +1 −1
drivers/clk/x86/clk-pmc-atom.c +7 −0

drivers/clk/clk-gemini.c+14−0

@@ -237,6 +237,18 @@ static int gemini_reset(struct reset_controller_dev *rcdev, · 236 unmodified lines
237	BIT(GEMINI_RESET_CPU1) \| BIT(id));	237	BIT(GEMINI_RESET_CPU1) \| BIT(id));
238	}	238	}
239		239
		240	static int gemini_reset_assert(struct reset_controller_dev *rcdev,
		241	unsigned long id)
		242	{
		243	return 0;
		244	}
		245
		246	static int gemini_reset_deassert(struct reset_controller_dev *rcdev,
		247	unsigned long id)
		248	{
		249	return 0;
		250	}
		251
240	static int gemini_reset_status(struct reset_controller_dev *rcdev,	252	static int gemini_reset_status(struct reset_controller_dev *rcdev,
241	unsigned long id)	253	unsigned long id)
242	{	254	{
@@ -253,6 +265,8 @@ static int gemini_reset_status(struct reset_controller_dev *rcdev, · 10 unmodified lines
253		265
254	static const struct reset_control_ops gemini_reset_ops = {	266	static const struct reset_control_ops gemini_reset_ops = {
255	.reset = gemini_reset,	267	.reset = gemini_reset,
		268	.assert = gemini_reset_assert,
		269	.deassert = gemini_reset_deassert,
256	.status = gemini_reset_status,	270	.status = gemini_reset_status,
257	};	271	};
258		272

drivers/clk/keystone/sci-clk.c+42−24

 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/soc/ti/ti_sci_protocol.h>
+#include <linux/bsearch.h>
 #define SCI_CLK_SSC_ENABLE		BIT(0)
 #define SCI_CLK_ALLOW_FREQ_CHANGE	BIT(1)
  * @dev: Device pointer for the clock provider
  * @clk_data: Clock data
  * @clocks: Clocks array for this device
+ * @num_clocks: Total number of clocks for this provider
  */
 struct sci_clk_provider {
 	const struct ti_sci_handle *sci;
 	struct device *dev;
 	const struct sci_clk_data *clk_data;
 	struct clk_hw **clocks;
+	int num_clocks;
 };
 /**
  * @hw:		 Hardware clock cookie for common clock framework
  * @dev_id:	 Device index
  * @clk_id:	 Clock index
- * @node:	 Clocks list link
  * @provider:	 Master clock provider
  * @flags:	 Flags for the clock
  */
 	struct clk_hw hw;
 	u16 dev_id;
 	u8 clk_id;
-	struct list_head node;
 	struct sci_clk_provider *provider;
 	u8 flags;
 };
 	return &sci_clk->hw;
 }
+static int _cmp_sci_clk(const void *a, const void *b)
+{
+	const struct sci_clk *ca = a;
+	const struct sci_clk *cb = *(struct sci_clk **)b;
+	if (ca->dev_id == cb->dev_id && ca->clk_id == cb->clk_id)
+		return 0;
+	if (ca->dev_id > cb->dev_id ||
+	    (ca->dev_id == cb->dev_id && ca->clk_id > cb->clk_id))
+		return 1;
+	return -1;
+}
 /**
  * sci_clk_get - Xlate function for getting clock handles
  * @clkspec: device tree clock specifier
 static struct clk_hw *sci_clk_get(struct of_phandle_args *clkspec, void *data)
 {
 	struct sci_clk_provider *provider = data;
-	u16 dev_id;
+	struct sci_clk **clk;
-	u8 clk_id;
+	struct sci_clk key;
-	const struct sci_clk_data *clks = provider->clk_data;
-	struct clk_hw **clocks = provider->clocks;
 	if (clkspec->args_count != 2)
 		return ERR_PTR(-EINVAL);
-	dev_id = clkspec->args[0];
+	key.dev_id = clkspec->args[0];
-	clk_id = clkspec->args[1];
+	key.clk_id = clkspec->args[1];
-	while (clks->num_clks) {
+	clk = bsearch(&key, provider->clocks, provider->num_clocks,
-		if (clks->dev == dev_id) {
+		      sizeof(clk), _cmp_sci_clk);
-			if (clk_id >= clks->num_clks)
-				return ERR_PTR(-EINVAL);
-			return clocks[clk_id];
-		}
-		clks++;
+	if (!clk)
-	}
+		return ERR_PTR(-ENODEV);
-	return ERR_PTR(-ENODEV);
+	return &(*clk)->hw;
 }
 static int ti_sci_init_clocks(struct sci_clk_provider *p)
 	const struct sci_clk_data *data = p->clk_data;
 	struct clk_hw *hw;
 	int i;
+	int num_clks = 0;
 	while (data->num_clks) {
-		p->clocks = devm_kcalloc(p->dev, data->num_clks,
+		num_clks += data->num_clks;
-					 sizeof(struct sci_clk),
+		data++;
-					 GFP_KERNEL);
+	}
-		if (!p->clocks)
-			return -ENOMEM;
+	p->num_clocks = num_clks;
+	p->clocks = devm_kcalloc(p->dev, num_clks, sizeof(struct sci_clk),
+				 GFP_KERNEL);
+	if (!p->clocks)
+		return -ENOMEM;
+	num_clks = 0;
+	data = p->clk_data;
+	while (data->num_clks) {
 		for (i = 0; i < data->num_clks; i++) {
 			hw = _sci_clk_build(p, data->dev, i);
 			if (!IS_ERR(hw)) {
-				p->clocks[i] = hw;
+				p->clocks[num_clks++] = hw;
 				continue;
 			}

drivers/clk/meson/clk-mpll.c+7−0

@@ -161,6 +161,13 @@ static int mpll_set_rate(struct clk_hw *hw, · 160 unmodified lines
161	reg = PARM_SET(p->width, p->shift, reg, 1);	161	reg = PARM_SET(p->width, p->shift, reg, 1);
162	writel(reg, mpll->base + p->reg_off);	162	writel(reg, mpll->base + p->reg_off);
163		163
		164	p = &mpll->ssen;
		165	if (p->width != 0) {
		166	reg = readl(mpll->base + p->reg_off);
		167	reg = PARM_SET(p->width, p->shift, reg, 1);
		168	writel(reg, mpll->base + p->reg_off);
		169	}
		170
164	p = &mpll->n2;	171	p = &mpll->n2;
165	reg = readl(mpll->base + p->reg_off);	172	reg = readl(mpll->base + p->reg_off);
166	reg = PARM_SET(p->width, p->shift, reg, n2);	173	reg = PARM_SET(p->width, p->shift, reg, n2);

drivers/clk/meson/clkc.h+1−0

@@ -118,6 +118,7 @@ struct meson_clk_mpll { · 117 unmodified lines
118	struct parm sdm_en;	118	struct parm sdm_en;
119	struct parm n2;	119	struct parm n2;
120	struct parm en;	120	struct parm en;
		121	struct parm ssen;
121	spinlock_t *lock;	122	spinlock_t *lock;
122	};	123	};
123		124

drivers/clk/meson/gxbb.c+5−0

 		.shift   = 14,
 		.width	 = 1,
 	},
+	.ssen = {
+		.reg_off = HHI_MPLL_CNTL,
+		.shift   = 25,
+		.width	 = 1,
+	},
 	.lock = &clk_lock,
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll0",

drivers/clk/meson/meson8b.c+5−0

 		.shift   = 14,
 		.width   = 1,
 	},
+	.ssen = {
+		.reg_off = HHI_MPLL_CNTL,
+		.shift   = 25,
+		.width   = 1,
+	},
 	.lock = &clk_lock,
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll0",

drivers/clk/samsung/clk-exynos5420.c+8−8

@@ -1283,16 +1283,16 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini · 1282 unmodified lines
1283	static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {	1283	static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
1284	PLL_36XX_RATE(600000000U, 100, 2, 1, 0),	1284	PLL_36XX_RATE(600000000U, 100, 2, 1, 0),
1285	PLL_36XX_RATE(400000000U, 200, 3, 2, 0),	1285	PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
1286	PLL_36XX_RATE(393216000U, 197, 3, 2, 25690),	1286	PLL_36XX_RATE(393216003U, 197, 3, 2, -25690),
1287	PLL_36XX_RATE(361267200U, 301, 5, 2, 3671),	1287	PLL_36XX_RATE(361267218U, 301, 5, 2, 3671),
1288	PLL_36XX_RATE(200000000U, 200, 3, 3, 0),	1288	PLL_36XX_RATE(200000000U, 200, 3, 3, 0),
1289	PLL_36XX_RATE(196608000U, 197, 3, 3, -25690),	1289	PLL_36XX_RATE(196608001U, 197, 3, 3, -25690),
1290	PLL_36XX_RATE(180633600U, 301, 5, 3, 3671),	1290	PLL_36XX_RATE(180633609U, 301, 5, 3, 3671),
1291	PLL_36XX_RATE(131072000U, 131, 3, 3, 4719),	1291	PLL_36XX_RATE(131072006U, 131, 3, 3, 4719),
1292	PLL_36XX_RATE(100000000U, 200, 3, 4, 0),	1292	PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
1293	PLL_36XX_RATE(65536000U, 131, 3, 4, 4719),	1293	PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719),
1294	PLL_36XX_RATE(49152000U, 197, 3, 5, 25690),	1294	PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690),
1295	PLL_36XX_RATE(32768000U, 131, 3, 5, 4719),	1295	PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719),
1296	};	1296	};
1297		1297
1298	static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {	1298	static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {

drivers/clk/sunxi-ng/ccu-sun5i.c+1−1

@@ -184,7 +184,7 @@ static struct ccu_mux cpu_clk = { · 183 unmodified lines
184	.hw.init = CLK_HW_INIT_PARENTS("cpu",	184	.hw.init = CLK_HW_INIT_PARENTS("cpu",
185	cpu_parents,	185	cpu_parents,
186	&ccu_mux_ops,	186	&ccu_mux_ops,
187	CLK_IS_CRITICAL),	187	CLK_SET_RATE_PARENT \| CLK_IS_CRITICAL),
188	}	188	}
189	};	189	};
190		190

drivers/clk/x86/clk-pmc-atom.c+7−0

@@ -186,6 +186,13 @@ static struct clk_plt plt_clk_register(struct platform_device pdev, int id, · 185 unmodified lines
186	pclk->reg = base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;	186	pclk->reg = base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;
187	spin_lock_init(&pclk->lock);	187	spin_lock_init(&pclk->lock);
188		188
		189	/*
		190	* If the clock was already enabled by the firmware mark it as critical
		191	* to avoid it being gated by the clock framework if no driver owns it.
		192	*/
		193	if (plt_clk_is_enabled(&pclk->hw))
		194	init.flags \|= CLK_IS_CRITICAL;
		195
189	ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);	196	ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);
190	if (ret) {	197	if (ret) {
191	pclk = ERR_PTR(ret);	198	pclk = ERR_PTR(ret);

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

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