To pick the changes from: f43b9876e857c739 ("x86/retbleed: Add fine grained Kconfig knobs") a149180fbcf336e9 ("x86: Add magic AMD return-thunk") 15e67227c49a5783 ("x86: Undo return-thunk damage") 369ae6ffc41a3c11 ("x86/retpoline: Cleanup some #ifdefery") 4ad3278df6fe2b08 x86/speculation: Disable RRSBA behavior 26aae8ccbc197223 x86/cpu/amd: Enumerate BTC_NO 9756bba28470722d x86/speculation: Fill RSB on vmexit for IBRS 3ebc170068885b6f x86/bugs: Add retbleed=ibpb 2dbb887e875b1de3 x86/entry: Add kernel IBRS implementation 6b80b59b35557065 x86/bugs: Report AMD retbleed vulnerability a149180fbcf336e9 x86: Add magic AMD return-thunk 15e67227c49a5783 x86: Undo return-thunk damage a883d624aed463c8 x86/cpufeatures: Move RETPOLINE flags to word 11 51802186158c74a0 x86/speculation/mmio: Enumerate Processor MMIO Stale Data bug This only causes these perf files to be rebuilt: CC /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o CC /tmp/build/perf/bench/mem-memset-x86-64-asm.o And addresses this perf build warning: Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h' diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h Warning: Kernel ABI header at 'tools/arch/x86/include/asm/disabled-features.h' differs from latest version at 'arch/x86/include/asm/disabled-features.h' diff -u tools/arch/x86/include/asm/disabled-features.h arch/x86/include/asm/disabled-features.h
Unified · Split
| @@ -203,8 +203,8 @@ · 202 unmodified lines | ||
| 203 | 203 | #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ |
| 204 | 204 | #define X86_FEATURE_XCOMPACTED ( 7*32+10) /* "" Use compacted XSTATE (XSAVES or XSAVEC) */ |
| 205 | 205 | #define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */ |
| 206 | −#define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */ | |
| 207 | −#define X86_FEATURE_RETPOLINE_LFENCE ( 7*32+13) /* "" Use LFENCE for Spectre variant 2 */ | |
| 206 | +#define X86_FEATURE_KERNEL_IBRS ( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */ | |
| 207 | +#define X86_FEATURE_RSB_VMEXIT ( 7*32+13) /* "" Fill RSB on VM-Exit */ | |
| 208 | 208 | #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ |
| 209 | 209 | #define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */ |
| 210 | 210 | #define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */ |
| @@ -296,6 +296,12 @@ · 85 unmodified lines | ||
| 296 | 296 | #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */ |
| 297 | 297 | #define X86_FEATURE_SGX1 (11*32+ 8) /* "" Basic SGX */ |
| 298 | 298 | #define X86_FEATURE_SGX2 (11*32+ 9) /* "" SGX Enclave Dynamic Memory Management (EDMM) */ |
| 299 | +#define X86_FEATURE_ENTRY_IBPB (11*32+10) /* "" Issue an IBPB on kernel entry */ | |
| 300 | +#define X86_FEATURE_RRSBA_CTRL (11*32+11) /* "" RET prediction control */ | |
| 301 | +#define X86_FEATURE_RETPOLINE (11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */ | |
| 302 | +#define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* "" Use LFENCE for Spectre variant 2 */ | |
| 303 | +#define X86_FEATURE_RETHUNK (11*32+14) /* "" Use REturn THUNK */ | |
| 304 | +#define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */ | |
| 299 | 305 | |
| 300 | 306 | /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ |
| 301 | 307 | #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ |
| @@ -316,6 +322,7 @@ · 14 unmodified lines | ||
| 316 | 322 | #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ |
| 317 | 323 | #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ |
| 318 | 324 | #define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */ |
| 325 | +#define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */ | |
| 319 | 326 | #define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */ |
| 320 | 327 | |
| 321 | 328 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ |
| @@ -447,5 +454,6 @@ · 125 unmodified lines | ||
| 447 | 454 | #define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */ |
| 448 | 455 | #define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG bits if not mitigated */ |
| 449 | 456 | #define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */ |
| 457 | +#define X86_BUG_RETBLEED X86_BUG(26) /* CPU is affected by RETBleed */ | |
| 450 | 458 | |
| 451 | 459 | #endif /* _ASM_X86_CPUFEATURES_H */ |
| @@ -50,6 +50,25 @@ · 49 unmodified lines | ||
| 50 | 50 | # define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31)) |
| 51 | 51 | #endif |
| 52 | 52 | |
| 53 | +#ifdef CONFIG_RETPOLINE | |
| 54 | +# define DISABLE_RETPOLINE 0 | |
| 55 | +#else | |
| 56 | +# define DISABLE_RETPOLINE ((1 << (X86_FEATURE_RETPOLINE & 31)) | \ | |
| 57 | + (1 << (X86_FEATURE_RETPOLINE_LFENCE & 31))) | |
| 58 | +#endif | |
| 59 | + | |
| 60 | +#ifdef CONFIG_RETHUNK | |
| 61 | +# define DISABLE_RETHUNK 0 | |
| 62 | +#else | |
| 63 | +# define DISABLE_RETHUNK (1 << (X86_FEATURE_RETHUNK & 31)) | |
| 64 | +#endif | |
| 65 | + | |
| 66 | +#ifdef CONFIG_CPU_UNRET_ENTRY | |
| 67 | +# define DISABLE_UNRET 0 | |
| 68 | +#else | |
| 69 | +# define DISABLE_UNRET (1 << (X86_FEATURE_UNRET & 31)) | |
| 70 | +#endif | |
| 71 | + | |
| 53 | 72 | #ifdef CONFIG_INTEL_IOMMU_SVM |
| 54 | 73 | # define DISABLE_ENQCMD 0 |
| 55 | 74 | #else |
| @@ -82,7 +101,7 @@ · 26 unmodified lines | ||
| 82 | 101 | #define DISABLED_MASK8 (DISABLE_TDX_GUEST) |
| 83 | 102 | #define DISABLED_MASK9 (DISABLE_SGX) |
| 84 | 103 | #define DISABLED_MASK10 0 |
| 85 | −#define DISABLED_MASK11 0 | |
| 104 | +#define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET) | |
| 86 | 105 | #define DISABLED_MASK12 0 |
| 87 | 106 | #define DISABLED_MASK13 0 |
| 88 | 107 | #define DISABLED_MASK14 0 |