History

Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung

* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: S3C2440: fix section mismatch on mini2440 ARM: S3C24XX: drop return codes in void function of dma.c ARM: S3C24XX: don't use uninitialized variable in dma.c ARM: EXYNOS4: Set appropriate I2C device variant ARM: S5PC100: Fix for compilation error spi/s3c64xx: Bug fix for SPI with different FIFO level ARM: SAMSUNG: Add tx_st_done variable ARM: EXYNOS4: Address a section mismatch w/ suspend issue. ARM: S5P: Fix bug on init of PWMTimers for HRTimer ARM: SAMSUNG: header file revised to prevent declaring duplicated ARM: EXYNOS4: fix improper gpio configuration ARM: EXYNOS4: Fix card detection for sdhci 0 and 2

Linus Torvalds committed 15 years ago

Commit f1a04db2 parents b56045d d34c1fc14 files · +37 −23Browse files

Unified · Split

14 files
  1. arch/arm/mach-exynos4/cpu.c +6 −0
  2. arch/arm/mach-exynos4/dev-audio.c +1 −1
  3. arch/arm/mach-exynos4/headsmp.S +1 −1
  4. arch/arm/mach-exynos4/mach-smdkv310.c +2 −6
  5. arch/arm/mach-s3c2440/mach-mini2440.c +1 −1
  6. arch/arm/mach-s3c64xx/dev-spi.c +2 −0
  7. arch/arm/mach-s5p64x0/dev-spi.c +4 −0
  8. arch/arm/mach-s5pc100/dev-spi.c +4 −0
  9. arch/arm/mach-s5pv210/dev-spi.c +2 −0
  10. arch/arm/plat-s3c24xx/dma.c +3 −9
  11. arch/arm/plat-s5p/s5p-time.c +2 −2
  12. arch/arm/plat-samsung/include/plat/devs.h +6 −0
  13. arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +2 −0
  14. drivers/spi/spi_s3c64xx.c +1 −3
arch/arm/mach-exynos4/cpu.c+6−0
@@ -23,6 +23,7 @@ · 22 unmodified lines
23#include <plat/sdhci.h>23#include <plat/sdhci.h>
24#include <plat/devs.h>24#include <plat/devs.h>
25#include <plat/fimc-core.h>25#include <plat/fimc-core.h>
26#include <plat/iic-core.h>
26 27
27#include <mach/regs-irq.h>28#include <mach/regs-irq.h>
28 29
@@ -132,6 +133,11 @@ void __init exynos4_map_io(void) · 103 unmodified lines
132 s3c_fimc_setname(1, "exynos4-fimc");133 s3c_fimc_setname(1, "exynos4-fimc");
133 s3c_fimc_setname(2, "exynos4-fimc");134 s3c_fimc_setname(2, "exynos4-fimc");
134 s3c_fimc_setname(3, "exynos4-fimc");135 s3c_fimc_setname(3, "exynos4-fimc");
136
137 /* The I2C bus controllers are directly compatible with s3c2440 */
138 s3c_i2c0_setname("s3c2440-i2c");
139 s3c_i2c1_setname("s3c2440-i2c");
140 s3c_i2c2_setname("s3c2440-i2c");
135}141}
136 142
137void __init exynos4_init_clocks(int xtal)143void __init exynos4_init_clocks(int xtal)
arch/arm/mach-exynos4/dev-audio.c+1−1
@@ -330,7 +330,7 @@ struct platform_device exynos4_device_ac97 = { · 329 unmodified lines
330 330
331static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)331static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
332{332{
333 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));333 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
334 334
335 return 0;335 return 0;
336}336}
arch/arm/mach-exynos4/headsmp.S+1−1
@@ -13,7 +13,7 @@ · 12 unmodified lines
13#include <linux/linkage.h>13#include <linux/linkage.h>
14#include <linux/init.h>14#include <linux/init.h>
15 15
16 __INIT16 __CPUINIT
17 17
18/*18/*
19 * exynos4 specific entry point for secondary CPUs. This provides19 * exynos4 specific entry point for secondary CPUs. This provides
arch/arm/mach-exynos4/mach-smdkv310.c+2−6
@@ -78,9 +78,7 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = { · 77 unmodified lines
78};78};
79 79
80static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {80static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
81 .cd_type = S3C_SDHCI_CD_GPIO,81 .cd_type = S3C_SDHCI_CD_INTERNAL,
82 .ext_cd_gpio = EXYNOS4_GPK0(2),
83 .ext_cd_gpio_invert = 1,
84 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,82 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
85#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT83#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
86 .max_width = 8,84 .max_width = 8,
@@ -96,9 +94,7 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = { · 9 unmodified lines
96};94};
97 95
98static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {96static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
99 .cd_type = S3C_SDHCI_CD_GPIO,97 .cd_type = S3C_SDHCI_CD_INTERNAL,
100 .ext_cd_gpio = EXYNOS4_GPK2(2),
101 .ext_cd_gpio_invert = 1,
102 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,98 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
103#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT99#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
104 .max_width = 8,100 .max_width = 8,
arch/arm/mach-s3c2440/mach-mini2440.c+1−1
@@ -552,7 +552,7 @@ struct mini2440_features_t { · 551 unmodified lines
552 struct platform_device *optional[8];552 struct platform_device *optional[8];
553};553};
554 554
555static void mini2440_parse_features(555static void __init mini2440_parse_features(
556 struct mini2440_features_t * features,556 struct mini2440_features_t * features,
557 const char * features_str )557 const char * features_str )
558{558{
arch/arm/mach-s3c64xx/dev-spi.c+2−0
@@ -88,6 +88,7 @@ static struct s3c64xx_spi_info s3c64xx_spi0_pdata = { · 87 unmodified lines
88 .cfg_gpio = s3c64xx_spi_cfg_gpio,88 .cfg_gpio = s3c64xx_spi_cfg_gpio,
89 .fifo_lvl_mask = 0x7f,89 .fifo_lvl_mask = 0x7f,
90 .rx_lvl_offset = 13,90 .rx_lvl_offset = 13,
91 .tx_st_done = 21,
91};92};
92 93
93static u64 spi_dmamask = DMA_BIT_MASK(32);94static u64 spi_dmamask = DMA_BIT_MASK(32);
@@ -132,6 +133,7 @@ static struct s3c64xx_spi_info s3c64xx_spi1_pdata = { · 38 unmodified lines
132 .cfg_gpio = s3c64xx_spi_cfg_gpio,133 .cfg_gpio = s3c64xx_spi_cfg_gpio,
133 .fifo_lvl_mask = 0x7f,134 .fifo_lvl_mask = 0x7f,
134 .rx_lvl_offset = 13,135 .rx_lvl_offset = 13,
136 .tx_st_done = 21,
135};137};
136 138
137struct platform_device s3c64xx_device_spi1 = {139struct platform_device s3c64xx_device_spi1 = {
arch/arm/mach-s5p64x0/dev-spi.c+4−0
@@ -112,12 +112,14 @@ static struct s3c64xx_spi_info s5p6440_spi0_pdata = { · 111 unmodified lines
112 .cfg_gpio = s5p6440_spi_cfg_gpio,112 .cfg_gpio = s5p6440_spi_cfg_gpio,
113 .fifo_lvl_mask = 0x1ff,113 .fifo_lvl_mask = 0x1ff,
114 .rx_lvl_offset = 15,114 .rx_lvl_offset = 15,
115 .tx_st_done = 25,
115};116};
116 117
117static struct s3c64xx_spi_info s5p6450_spi0_pdata = {118static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
118 .cfg_gpio = s5p6450_spi_cfg_gpio,119 .cfg_gpio = s5p6450_spi_cfg_gpio,
119 .fifo_lvl_mask = 0x1ff,120 .fifo_lvl_mask = 0x1ff,
120 .rx_lvl_offset = 15,121 .rx_lvl_offset = 15,
122 .tx_st_done = 25,
121};123};
122 124
123static u64 spi_dmamask = DMA_BIT_MASK(32);125static u64 spi_dmamask = DMA_BIT_MASK(32);
@@ -160,12 +162,14 @@ static struct s3c64xx_spi_info s5p6440_spi1_pdata = { · 36 unmodified lines
160 .cfg_gpio = s5p6440_spi_cfg_gpio,162 .cfg_gpio = s5p6440_spi_cfg_gpio,
161 .fifo_lvl_mask = 0x7f,163 .fifo_lvl_mask = 0x7f,
162 .rx_lvl_offset = 15,164 .rx_lvl_offset = 15,
165 .tx_st_done = 25,
163};166};
164 167
165static struct s3c64xx_spi_info s5p6450_spi1_pdata = {168static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
166 .cfg_gpio = s5p6450_spi_cfg_gpio,169 .cfg_gpio = s5p6450_spi_cfg_gpio,
167 .fifo_lvl_mask = 0x7f,170 .fifo_lvl_mask = 0x7f,
168 .rx_lvl_offset = 15,171 .rx_lvl_offset = 15,
172 .tx_st_done = 25,
169};173};
170 174
171struct platform_device s5p64x0_device_spi1 = {175struct platform_device s5p64x0_device_spi1 = {
arch/arm/mach-s5pc100/dev-spi.c+4−0
@@ -15,6 +15,7 @@ · 14 unmodified lines
15#include <mach/dma.h>15#include <mach/dma.h>
16#include <mach/map.h>16#include <mach/map.h>
17#include <mach/spi-clocks.h>17#include <mach/spi-clocks.h>
18#include <mach/irqs.h>
18 19
19#include <plat/s3c64xx-spi.h>20#include <plat/s3c64xx-spi.h>
20#include <plat/gpio-cfg.h>21#include <plat/gpio-cfg.h>
@@ -90,6 +91,7 @@ static struct s3c64xx_spi_info s5pc100_spi0_pdata = { · 69 unmodified lines
90 .fifo_lvl_mask = 0x7f,91 .fifo_lvl_mask = 0x7f,
91 .rx_lvl_offset = 13,92 .rx_lvl_offset = 13,
92 .high_speed = 1,93 .high_speed = 1,
94 .tx_st_done = 21,
93};95};
94 96
95static u64 spi_dmamask = DMA_BIT_MASK(32);97static u64 spi_dmamask = DMA_BIT_MASK(32);
@@ -134,6 +136,7 @@ static struct s3c64xx_spi_info s5pc100_spi1_pdata = { · 38 unmodified lines
134 .fifo_lvl_mask = 0x7f,136 .fifo_lvl_mask = 0x7f,
135 .rx_lvl_offset = 13,137 .rx_lvl_offset = 13,
136 .high_speed = 1,138 .high_speed = 1,
139 .tx_st_done = 21,
137};140};
138 141
139struct platform_device s5pc100_device_spi1 = {142struct platform_device s5pc100_device_spi1 = {
@@ -176,6 +179,7 @@ static struct s3c64xx_spi_info s5pc100_spi2_pdata = { · 36 unmodified lines
176 .fifo_lvl_mask = 0x7f,179 .fifo_lvl_mask = 0x7f,
177 .rx_lvl_offset = 13,180 .rx_lvl_offset = 13,
178 .high_speed = 1,181 .high_speed = 1,
182 .tx_st_done = 21,
179};183};
180 184
181struct platform_device s5pc100_device_spi2 = {185struct platform_device s5pc100_device_spi2 = {
arch/arm/mach-s5pv210/dev-spi.c+2−0
@@ -85,6 +85,7 @@ static struct s3c64xx_spi_info s5pv210_spi0_pdata = { · 84 unmodified lines
85 .fifo_lvl_mask = 0x1ff,85 .fifo_lvl_mask = 0x1ff,
86 .rx_lvl_offset = 15,86 .rx_lvl_offset = 15,
87 .high_speed = 1,87 .high_speed = 1,
88 .tx_st_done = 25,
88};89};
89 90
90static u64 spi_dmamask = DMA_BIT_MASK(32);91static u64 spi_dmamask = DMA_BIT_MASK(32);
@@ -129,6 +130,7 @@ static struct s3c64xx_spi_info s5pv210_spi1_pdata = { · 38 unmodified lines
129 .fifo_lvl_mask = 0x7f,130 .fifo_lvl_mask = 0x7f,
130 .rx_lvl_offset = 15,131 .rx_lvl_offset = 15,
131 .high_speed = 1,132 .high_speed = 1,
133 .tx_st_done = 25,
132};134};
133 135
134struct platform_device s5pv210_device_spi1 = {136struct platform_device s5pv210_device_spi1 = {
arch/arm/plat-s3c24xx/dma.c+3−9
@@ -1027,17 +1027,13 @@ int s3c2410_dma_config(unsigned int channel, · 1026 unmodified lines
1027 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);1027 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1028 unsigned int dcon;1028 unsigned int dcon;
1029 1029
1030 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",1030 pr_debug("%s: chan=%d, xfer_unit=%d\n", __func__, channel, xferunit);
1031 __func__, channel, xferunit, dcon);
1032 1031
1033 if (chan == NULL)1032 if (chan == NULL)
1034 return -EINVAL;1033 return -EINVAL;
1035 1034
1036 pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
1037
1038 dcon = chan->dcon & dma_sel.dcon_mask;1035 dcon = chan->dcon & dma_sel.dcon_mask;
1039 1036 pr_debug("%s: dcon is %08x\n", __func__, dcon);
1040 pr_debug("%s: New dcon is %08x\n", __func__, dcon);
1041 1037
1042 switch (chan->req_ch) {1038 switch (chan->req_ch) {
1043 case DMACH_I2S_IN:1039 case DMACH_I2S_IN:
@@ -1235,7 +1231,7 @@ static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp) · 191 unmodified lines
1235 /* restore channel's hardware configuration */1231 /* restore channel's hardware configuration */
1236 1232
1237 if (!cp->in_use)1233 if (!cp->in_use)
1238 return 0;1234 return;
1239 1235
1240 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);1236 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
1241 1237
@@ -1246,8 +1242,6 @@ static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp) · 4 unmodified lines
1246 1242
1247 if (cp->map != NULL)1243 if (cp->map != NULL)
1248 dma_sel.select(cp, cp->map);1244 dma_sel.select(cp, cp->map);
1249
1250 return 0;
1251}1245}
1252 1246
1253static void s3c2410_dma_resume(void)1247static void s3c2410_dma_resume(void)
arch/arm/plat-s5p/s5p-time.c+2−2
@@ -370,11 +370,11 @@ static void __init s5p_clocksource_init(void) · 369 unmodified lines
370 370
371 clock_rate = clk_get_rate(tin_source);371 clock_rate = clk_get_rate(tin_source);
372 372
373 init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
374
375 s5p_time_setup(timer_source.source_id, TCNT_MAX);373 s5p_time_setup(timer_source.source_id, TCNT_MAX);
376 s5p_time_start(timer_source.source_id, PERIODIC);374 s5p_time_start(timer_source.source_id, PERIODIC);
377 375
376 init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
377
378 if (clocksource_register_hz(&time_clocksource, clock_rate))378 if (clocksource_register_hz(&time_clocksource, clock_rate))
379 panic("%s: can't register clocksource\n", time_clocksource.name);379 panic("%s: can't register clocksource\n", time_clocksource.name);
380}380}
arch/arm/plat-samsung/include/plat/devs.h+6−0
@@ -12,6 +12,10 @@ · 11 unmodified lines
12 * it under the terms of the GNU General Public License version 2 as12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.13 * published by the Free Software Foundation.
14*/14*/
15
16#ifndef __PLAT_DEVS_H
17#define __PLAT_DEVS_H __FILE__
18
15#include <linux/platform_device.h>19#include <linux/platform_device.h>
16 20
17struct s3c24xx_uart_resources {21struct s3c24xx_uart_resources {
@@ -159,3 +163,5 @@ extern struct platform_device s3c_device_ac97; · 141 unmodified lines
159 */163 */
160extern void *s3c_set_platdata(void *pd, size_t pdsize,164extern void *s3c_set_platdata(void *pd, size_t pdsize,
161 struct platform_device *pdev);165 struct platform_device *pdev);
166
167#endif /* __PLAT_DEVS_H */
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h+2−0
@@ -39,6 +39,7 @@ struct s3c64xx_spi_csinfo { · 38 unmodified lines
39 * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-639 * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
40 * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number40 * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
41 * @high_speed: If the controller supports HIGH_SPEED_EN bit41 * @high_speed: If the controller supports HIGH_SPEED_EN bit
42 * @tx_st_done: Depends on tx fifo_lvl field
42 */43 */
43struct s3c64xx_spi_info {44struct s3c64xx_spi_info {
44 int src_clk_nr;45 int src_clk_nr;
@@ -53,6 +54,7 @@ struct s3c64xx_spi_info { · 8 unmodified lines
53 int fifo_lvl_mask;54 int fifo_lvl_mask;
54 int rx_lvl_offset;55 int rx_lvl_offset;
55 int high_speed;56 int high_speed;
57 int tx_st_done;
56};58};
57 59
58/**60/**
drivers/spi/spi_s3c64xx.c+1−3
@@ -116,9 +116,7 @@ · 115 unmodified lines
116 (((i)->fifo_lvl_mask + 1))) \116 (((i)->fifo_lvl_mask + 1))) \
117 ? 1 : 0)117 ? 1 : 0)
118 118
119#define S3C64XX_SPI_ST_TX_DONE(v, i) ((((v) >> (i)->rx_lvl_offset) & \119#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
120 (((i)->fifo_lvl_mask + 1) << 1)) \
121 ? 1 : 0)
122#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)120#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
123#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)121#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
124 122

Keyboard shortcuts

General

Show keyboard shortcuts
?
Focus the current search
/

Issues and pull requests

Open filters
f

Issues, pull requests and Inbox

Select next item
j↓
Select previous item
k↑
Open selected item
Enter
Dismiss filters or clear selection
Esc

Repository code

Go to file
t